From 2afae082547a091eb566f3d1a6ce74b02d2569ec Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Wed, 18 Nov 2020 15:42:14 +0500 Subject: [PATCH] lsu updated --- el2_dec_decode_ctl.anno.json | 1492 ++ el2_dec_decode_ctl.fir | 5032 ++++ el2_dec_decode_ctl.v | 3386 +++ el2_exu.anno.json | 135 + el2_exu.fir | 3671 +++ el2_exu.v | 2603 ++ el2_exu_alu_ctl.anno.json | 35 +- el2_exu_alu_ctl.fir | 1004 +- el2_exu_alu_ctl.v | 410 +- el2_lsu.anno.json | 277 +- el2_lsu.fir | 22331 +++++++++++----- el2_lsu.v | 13483 +++++++--- el2_lsu_bus_buffer.anno.json | 70 +- el2_lsu_bus_buffer.fir | 12565 ++++----- el2_lsu_bus_buffer.v | 6752 ++--- el2_lsu_bus_intf.anno.json | 59 +- el2_lsu_bus_intf.fir | 13674 +++++----- el2_lsu_bus_intf.v | 7516 +++--- el2_pic_ctrl.anno.json | 962 +- el2_pic_ctrl.fir | 4795 +++- el2_pic_ctrl.v | 3621 ++- firrtl_black_box_resource_files.f | 2 +- .../vsrc/TEC_RV_ICG.v => gated_latch.v | 3 +- ...5e$.class => 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646 bytes ...f1$.class => $e55d6b0d03c5f442179e$.class} | Bin 2762 -> 2762 bytes ...100d.cache => $e55d6b0d03c5f442179e.cache} | 0 .../$e55d6b0d03c5f442179e.class | Bin 0 -> 646 bytes .../$f5cf583e32caad00100d.class | Bin 646 -> 0 bytes .../sbt-1.0/update/update_cache_2.12/output | 2 +- .../streams/update_cache_2.12/output_dsp | 2 +- .../_global/compileBinaryFileInputs/previous | 2 +- .../main/resources/vsrc/gated_latch.v | 3 +- src/main/scala/dbg/el2_dbg.scala | 480 + src/main/scala/dec/el2_dec.scala | 721 + src/main/scala/dec/el2_dec_dec_ctl.scala | 173 + src/main/scala/dec/el2_dec_decode_ctl.scala | 829 + src/main/scala/dec/el2_dec_gpr_ctl.scala | 58 + src/main/scala/dec/el2_dec_ib_ctl.scala | 99 + src/main/scala/dec/el2_dec_tlu_ctl.scala | 2872 ++ src/main/scala/dec/el2_dec_trigger.scala | 20 + .../scala/dmi/dmi_jtag_to_core_sync.scala | 14 +- src/main/scala/dmi/dmi_wrapper.scala | 27 +- src/main/scala/dmi/rvjtag_tap.scala | 145 +- src/main/scala/el2_dma_ctrl.scala | 556 + src/main/scala/el2_pic_ctl.scala | 426 + src/main/scala/el2_pic_ctrl.scala | 271 - src/main/scala/el2_swerv.scala | 869 + src/main/scala/exu/el2_exu.scala | 73 +- src/main/scala/exu/el2_exu_alu_ctl.scala | 22 +- src/main/scala/exu/el2_exu_div_ctl.scala | 13 +- src/main/scala/exu/el2_exu_mul_ctl.scala | 12 +- src/main/scala/ifu/el2_ifu.scala | 344 + src/main/scala/ifu/el2_ifu_aln_ctl.scala | 421 + src/main/scala/ifu/el2_ifu_bp_ctl.scala | 474 + src/main/scala/ifu/el2_ifu_compress_ctl.scala | 178 + src/main/scala/ifu/el2_ifu_ic_mem.scala | 277 + src/main/scala/ifu/el2_ifu_iccm_mem.scala | 118 + src/main/scala/ifu/el2_ifu_ifc_ctl.scala | 149 + src/main/scala/ifu/el2_ifu_mem_ctl.scala | 858 + src/main/scala/include/el2_bundle.scala | 131 +- src/main/scala/lib/RVC.scala | 232 + src/main/scala/lib/ahb_to_axi4.scala | 85 + src/main/scala/lib/axi4_to_ahb.scala | 442 + src/main/scala/lib/beh_ib_func.scala | 217 - src/main/scala/lib/beh_lib.scala | 241 +- src/main/scala/lib/el2_lib.scala | 375 +- src/main/scala/lsu/el2_lsu.scala | 14 +- src/main/scala/lsu/el2_lsu_addrcheck.scala | 48 +- src/main/scala/lsu/el2_lsu_bus_buffer.scala | 1395 +- src/main/scala/lsu/el2_lsu_bus_intf.scala | 604 +- src/main/scala/lsu/el2_lsu_clkdomain.scala | 142 +- src/main/scala/lsu/el2_lsu_dccm_ctl.scala | 16 +- src/main/scala/lsu/el2_lsu_dccm_mem.scala | 99 - src/main/scala/lsu/el2_lsu_ecc.scala | 62 +- src/main/scala/lsu/el2_lsu_lsc_ctl.scala | 20 +- src/main/scala/lsu/el2_lsu_stbuf.scala | 400 +- src/main/scala/lsu/el2_lsu_trigger.scala | 5 +- src/main/scala/snapshot/el2_param.scala | 163 +- target/scala-2.12/classes/SWERV$.class | Bin 0 -> 3819 bytes .../classes/SWERV$delayedInit$body.class | Bin 0 -> 694 bytes .../classes/{lsu/DCCM.class => SWERV.class} | Bin 765 -> 756 bytes target/scala-2.12/classes/dbg/debug$.class | Bin 0 -> 3487 bytes .../classes/dbg/debug$delayedInit$body.class | Bin 0 -> 716 bytes target/scala-2.12/classes/dbg/debug.class | Bin 0 -> 762 bytes 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target/scala-2.12/classes/dec/dec_trig$.class | Bin 0 -> 3880 bytes .../dec/dec_trig$delayedInit$body.class | Bin 0 -> 742 bytes target/scala-2.12/classes/dec/dec_trig.class | Bin 0 -> 785 bytes .../scala-2.12/classes/dec/el2_CSR_IO.class | Bin 0 -> 83474 bytes target/scala-2.12/classes/dec/el2_dec.class | Bin 0 -> 215871 bytes .../scala-2.12/classes/dec/el2_dec_IO.class | Bin 0 -> 83594 bytes .../classes/dec/el2_dec_dec_ctl$$anon$1.class | Bin 0 -> 1790 bytes .../classes/dec/el2_dec_dec_ctl.class | Bin 0 -> 88167 bytes .../classes/dec/el2_dec_decode_csr_read.class | Bin 0 -> 59741 bytes .../dec/el2_dec_decode_csr_read_IO.class | Bin 0 -> 44538 bytes .../dec/el2_dec_decode_ctl$$anon$1.class | Bin 0 -> 17799 bytes .../classes/dec/el2_dec_decode_ctl.class | Bin 0 -> 559141 bytes .../classes/dec/el2_dec_gpr_ctl.class | Bin 0 -> 53689 bytes .../classes/dec/el2_dec_gpr_ctl_IO.class | Bin 0 -> 4008 bytes .../classes/dec/el2_dec_ib_ctl.class | Bin 0 -> 44088 bytes .../classes/dec/el2_dec_ib_ctl_IO.class | Bin 0 -> 42957 bytes .../classes/dec/el2_dec_pkt_t.class | Bin 0 -> 8208 bytes .../classes/dec/el2_dec_timer_ctl.class | Bin 0 -> 61225 bytes .../classes/dec/el2_dec_timer_ctl_IO.class | Bin 0 -> 5579 bytes .../classes/dec/el2_dec_tlu_ctl.class | Bin 0 -> 184343 bytes .../classes/dec/el2_dec_tlu_ctl_IO.class | Bin 0 -> 76883 bytes .../classes/dec/el2_dec_trigger$$anon$1.class | Bin 0 -> 2383 bytes .../classes/dec/el2_dec_trigger.class | Bin 0 -> 53132 bytes target/scala-2.12/classes/dec/gpr_gen$.class | Bin 0 -> 3875 bytes .../dec/gpr_gen$delayedInit$body.class | Bin 0 -> 736 bytes target/scala-2.12/classes/dec/gpr_gen.class | Bin 0 -> 780 bytes target/scala-2.12/classes/dec/ib_gen$.class | Bin 0 -> 3867 bytes .../classes/dec/ib_gen$delayedInit$body.class | Bin 0 -> 729 bytes target/scala-2.12/classes/dec/ib_gen.class | Bin 0 -> 774 bytes target/scala-2.12/classes/dec/tlu_gen$.class | Bin 0 -> 3876 bytes .../dec/tlu_gen$delayedInit$body.class | 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1847 -> 1832 bytes .../classes/lib/rvrangecheck$.class | Bin 0 -> 589 bytes .../scala-2.12/classes/lib/rvrangecheck.class | Bin 0 -> 9379 bytes .../classes/lib/rvrangecheck_ch$.class | Bin 502 -> 0 bytes .../classes/lib/rvrangecheck_ch.class | Bin 8557 -> 0 bytes .../classes/lib/rvsyncss$$anon$2.class | Bin 1948 -> 0 bytes .../classes/lib/rvsyncss$$anon$4.class | Bin 0 -> 1713 bytes target/scala-2.12/classes/lib/rvsyncss$.class | Bin 581 -> 581 bytes target/scala-2.12/classes/lib/rvsyncss.class | Bin 7725 -> 6278 bytes ...$anon$5.class => rvtwoscomp$$anon$7.class} | Bin 1725 -> 1725 bytes .../scala-2.12/classes/lib/rvtwoscomp$.class | Bin 491 -> 491 bytes .../scala-2.12/classes/lib/rvtwoscomp.class | Bin 9040 -> 9200 bytes .../scala-2.12/classes/lsu/BusBufmain$.class | Bin 3934 -> 3935 bytes .../lsu/BusBufmain$delayedInit$body.class | Bin 757 -> 757 bytes .../scala-2.12/classes/lsu/BusIntfMain$.class | Bin 3933 -> 3933 bytes .../lsu/BusIntfMain$delayedInit$body.class | Bin 761 -> 761 bytes target/scala-2.12/classes/lsu/DCCM$.class | Bin 3675 -> 0 bytes .../classes/lsu/DCCM$delayedInit$body.class | Bin 719 -> 0 bytes .../classes/lsu/el2_lsu$$anon$1.class | Bin 17878 -> 18161 bytes target/scala-2.12/classes/lsu/el2_lsu.class | Bin 1251354 -> 1291732 bytes .../classes/lsu/el2_lsu_addrcheck.class | Bin 101963 -> 104832 bytes .../lsu/el2_lsu_bus_buffer$$anon$1.class | Bin 14947 -> 14886 bytes .../classes/lsu/el2_lsu_bus_buffer.class | Bin 435799 -> 547480 bytes .../lsu/el2_lsu_bus_intf$$anon$1.class | Bin 14235 -> 14174 bytes .../classes/lsu/el2_lsu_bus_intf.class | Bin 287977 -> 327035 bytes .../classes/lsu/el2_lsu_clkdomain.class | Bin 90148 -> 91588 bytes .../classes/lsu/el2_lsu_dccm_ctl.class | Bin 387192 -> 389056 bytes .../lsu/el2_lsu_dccm_mem$$anon$1.class | Bin 3276 -> 0 bytes .../classes/lsu/el2_lsu_dccm_mem.class | Bin 26528 -> 0 bytes .../scala-2.12/classes/lsu/el2_lsu_ecc.class | Bin 98995 -> 100647 bytes .../classes/lsu/el2_lsu_lsc_ctl.class | Bin 285804 -> 287650 bytes .../classes/lsu/el2_lsu_stbuf.class | Bin 186025 -> 193430 bytes .../classes/lsu/el2_lsu_trigger.class | Bin 57749 -> 59591 bytes .../classes/lsu/main_lsu_top$.class | Bin 3910 -> 3910 bytes .../lsu/main_lsu_top$delayedInit$body.class | Bin 758 -> 758 bytes target/scala-2.12/classes/lsu/stbmain$.class | Bin 3904 -> 3904 bytes target/scala-2.12/classes/pic_main$.class | Bin 0 -> 3883 bytes .../classes/pic_main$delayedInit$body.class | Bin 0 -> 714 bytes target/scala-2.12/classes/pic_main.class | Bin 0 -> 774 bytes target/scala-2.12/classes/snapshot/pt$.class | Bin 21587 -> 21595 bytes target/scala-2.12/classes/snapshot/pt1$.class | Bin 17460 -> 0 bytes target/scala-2.12/classes/snapshot/pt1.class | Bin 19384 -> 0 bytes target/scala-2.12/classes/vsrc/gated_latch.v | 14 + 370 files changed, 85015 insertions(+), 34076 deletions(-) create mode 100644 el2_dec_decode_ctl.anno.json create mode 100644 el2_dec_decode_ctl.fir create mode 100644 el2_dec_decode_ctl.v create mode 100644 el2_exu.anno.json create mode 100644 el2_exu.fir create mode 100644 el2_exu.v rename src/main/resources/vsrc/TEC_RV_ICG.v => gated_latch.v (91%) rename project/target/config-classes/{$d88dffe9bb5470e5935e$.class => $11be0cb76372ba3ee9f6$.class} (94%) rename project/target/config-classes/{$1a77b77dbd21409628b4.cache => $11be0cb76372ba3ee9f6.cache} (100%) rename project/target/config-classes/{$1a77b77dbd21409628b4.class => $11be0cb76372ba3ee9f6.class} (54%) rename project/target/config-classes/{$78dad6b7a8f577faa340$.class => $1754e38fcce51e8851c0$.class} (94%) rename project/target/config-classes/{$317bf6314662b9759850.cache => $1754e38fcce51e8851c0.cache} (100%) rename project/target/config-classes/{$317bf6314662b9759850.class => $1754e38fcce51e8851c0.class} (54%) rename project/target/config-classes/{$54e4942309167438d043$.class => $2c3e28949b1f44e2665a$.class} (94%) rename project/target/config-classes/{$54e4942309167438d043.cache => $2c3e28949b1f44e2665a.cache} (100%) rename project/target/config-classes/{$54e4942309167438d043.class => $2c3e28949b1f44e2665a.class} (73%) rename project/target/config-classes/{$6dc9b12b35de121f4467$.class => $6f0cf04b54db8e7eadb4$.class} (91%) rename project/target/config-classes/{$49065a475131703adc04.cache => $6f0cf04b54db8e7eadb4.cache} (100%) rename project/target/config-classes/{$49065a475131703adc04.class => $6f0cf04b54db8e7eadb4.class} (55%) rename project/target/config-classes/{$a0413357cd97a7ba40cf$.class => $76b6d0a2b70906284949$.class} (91%) rename project/target/config-classes/{$6dc9b12b35de121f4467.cache => $76b6d0a2b70906284949.cache} (100%) create mode 100644 project/target/config-classes/$76b6d0a2b70906284949.class delete mode 100644 project/target/config-classes/$78dad6b7a8f577faa340.class rename project/target/config-classes/{$1a77b77dbd21409628b4$.class => $923aeedd8b409497dc41$.class} (93%) rename project/target/config-classes/{$6e49811bdc2e518a66f1.cache => $923aeedd8b409497dc41.cache} (100%) create mode 100644 project/target/config-classes/$923aeedd8b409497dc41.class delete mode 100644 project/target/config-classes/$a0413357cd97a7ba40cf.class rename project/target/config-classes/{$49065a475131703adc04$.class => $b043f5653e02863732d6$.class} (90%) rename project/target/config-classes/{$78dad6b7a8f577faa340.cache => $b043f5653e02863732d6.cache} (100%) rename project/target/config-classes/{$6e49811bdc2e518a66f1.class => $b043f5653e02863732d6.class} (55%) rename project/target/config-classes/{$f5cf583e32caad00100d$.class => $b27b0cc0f0df81dd2647$.class} (93%) rename project/target/config-classes/{$a0413357cd97a7ba40cf.cache => $b27b0cc0f0df81dd2647.cache} (100%) rename project/target/config-classes/{$6dc9b12b35de121f4467.class => $b27b0cc0f0df81dd2647.class} (55%) delete mode 100644 project/target/config-classes/$c9da18f64b0977640914.class rename project/target/config-classes/{$c9da18f64b0977640914$.class => $ce84aff798afa255b8e3$.class} (92%) rename project/target/config-classes/{$c9da18f64b0977640914.cache => $ce84aff798afa255b8e3.cache} (100%) create mode 100644 project/target/config-classes/$ce84aff798afa255b8e3.class rename project/target/config-classes/{$317bf6314662b9759850$.class => $dfbf4f39923532da9023$.class} (93%) rename project/target/config-classes/{$d88dffe9bb5470e5935e.cache => $dfbf4f39923532da9023.cache} (100%) rename project/target/config-classes/{$d88dffe9bb5470e5935e.class => $dfbf4f39923532da9023.class} (55%) rename project/target/config-classes/{$6e49811bdc2e518a66f1$.class => $e55d6b0d03c5f442179e$.class} (94%) rename project/target/config-classes/{$f5cf583e32caad00100d.cache => $e55d6b0d03c5f442179e.cache} (100%) create mode 100644 project/target/config-classes/$e55d6b0d03c5f442179e.class delete mode 100644 project/target/config-classes/$f5cf583e32caad00100d.class rename target/scala-2.12/classes/vsrc/TEC_RV_ICG.v => src/main/resources/vsrc/gated_latch.v (91%) create mode 100644 src/main/scala/dbg/el2_dbg.scala create mode 100644 src/main/scala/dec/el2_dec.scala create mode 100644 src/main/scala/dec/el2_dec_dec_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_decode_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_gpr_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_ib_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_tlu_ctl.scala create mode 100644 src/main/scala/dec/el2_dec_trigger.scala create mode 100644 src/main/scala/el2_dma_ctrl.scala create mode 100644 src/main/scala/el2_pic_ctl.scala delete mode 100644 src/main/scala/el2_pic_ctrl.scala create mode 100644 src/main/scala/el2_swerv.scala create mode 100644 src/main/scala/ifu/el2_ifu.scala create mode 100644 src/main/scala/ifu/el2_ifu_aln_ctl.scala create mode 100644 src/main/scala/ifu/el2_ifu_bp_ctl.scala create mode 100644 src/main/scala/ifu/el2_ifu_compress_ctl.scala create mode 100644 src/main/scala/ifu/el2_ifu_ic_mem.scala create mode 100644 src/main/scala/ifu/el2_ifu_iccm_mem.scala create mode 100644 src/main/scala/ifu/el2_ifu_ifc_ctl.scala create mode 100644 src/main/scala/ifu/el2_ifu_mem_ctl.scala create mode 100644 src/main/scala/lib/RVC.scala create mode 100644 src/main/scala/lib/ahb_to_axi4.scala create mode 100644 src/main/scala/lib/axi4_to_ahb.scala delete mode 100644 src/main/scala/lib/beh_ib_func.scala delete mode 100644 src/main/scala/lsu/el2_lsu_dccm_mem.scala create mode 100644 target/scala-2.12/classes/SWERV$.class create mode 100644 target/scala-2.12/classes/SWERV$delayedInit$body.class rename target/scala-2.12/classes/{lsu/DCCM.class => SWERV.class} (51%) create mode 100644 target/scala-2.12/classes/dbg/debug$.class create mode 100644 target/scala-2.12/classes/dbg/debug$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dbg/debug.class create mode 100644 target/scala-2.12/classes/dbg/el2_dbg$$anon$1.class create mode 100644 target/scala-2.12/classes/dbg/el2_dbg.class create mode 100644 target/scala-2.12/classes/dbg/sb_state_t$.class create mode 100644 target/scala-2.12/classes/dbg/sb_state_t.class create mode 100644 target/scala-2.12/classes/dbg/state_t$.class create mode 100644 target/scala-2.12/classes/dbg/state_t.class create mode 100644 target/scala-2.12/classes/dec/CSR_VAL.class create mode 100644 target/scala-2.12/classes/dec/CSRs.class create mode 100644 target/scala-2.12/classes/dec/csr_tlu.class create mode 100644 target/scala-2.12/classes/dec/dec_decode$.class create mode 100644 target/scala-2.12/classes/dec/dec_decode$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_decode.class create mode 100644 target/scala-2.12/classes/dec/dec_main$.class create mode 100644 target/scala-2.12/classes/dec/dec_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_main.class create mode 100644 target/scala-2.12/classes/dec/dec_trig$.class create mode 100644 target/scala-2.12/classes/dec/dec_trig$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/dec_trig.class create mode 100644 target/scala-2.12/classes/dec/el2_CSR_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_dec_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_csr_read.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_csr_read_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_decode_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_gpr_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_gpr_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_ib_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_ib_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_pkt_t.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_timer_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_timer_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_tlu_ctl.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_tlu_ctl_IO.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_trigger$$anon$1.class create mode 100644 target/scala-2.12/classes/dec/el2_dec_trigger.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen$.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/gpr_gen.class create mode 100644 target/scala-2.12/classes/dec/ib_gen$.class create mode 100644 target/scala-2.12/classes/dec/ib_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/ib_gen.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen$.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dec/tlu_gen.class create mode 100644 target/scala-2.12/classes/dma$.class create mode 100644 target/scala-2.12/classes/dma$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dma.class create mode 100644 target/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class create mode 100644 target/scala-2.12/classes/dmi/dmi_wrapper.class create mode 100644 target/scala-2.12/classes/dmi/dmiwrapper_main$.class create mode 100644 target/scala-2.12/classes/dmi/dmiwrapper_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dmi/dmiwrapper_main.class create mode 100644 target/scala-2.12/classes/dmi/rvjtag_tap$$anon$1.class create mode 100644 target/scala-2.12/classes/dmi/rvjtag_tap.class create mode 100644 target/scala-2.12/classes/dmi/tapmain$.class create mode 100644 target/scala-2.12/classes/dmi/tapmain$delayedInit$body.class create mode 100644 target/scala-2.12/classes/dmi/tapmain.class create mode 100644 target/scala-2.12/classes/el2_dma_ctrl$$anon$1.class create mode 100644 target/scala-2.12/classes/el2_dma_ctrl.class create mode 100644 target/scala-2.12/classes/el2_pic_ctrl$$anon$1.class create mode 100644 target/scala-2.12/classes/el2_pic_ctrl.class create mode 100644 target/scala-2.12/classes/el2_swerv$$anon$1.class create mode 100644 target/scala-2.12/classes/el2_swerv.class create mode 100644 target/scala-2.12/classes/ifu/EL2_IC_DATA$$anon$3.class create mode 100644 target/scala-2.12/classes/ifu/EL2_IC_DATA.class create mode 100644 target/scala-2.12/classes/ifu/EL2_IC_TAG$$anon$2.class create mode 100644 target/scala-2.12/classes/ifu/EL2_IC_TAG.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_aln_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_aln_ctl.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_bp_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_bp_ctl.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_compress_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_compress_ctl.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ic_mem$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ic_mem.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl$$anon$1.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_ifc_ctl.class create mode 100644 target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class create mode 100644 target/scala-2.12/classes/ifu/ifu_aln$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_aln$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_aln.class create mode 100644 target/scala-2.12/classes/ifu/ifu_bp$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_bp$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_bp.class create mode 100644 target/scala-2.12/classes/ifu/ifu_comp$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_comp$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_comp.class create mode 100644 target/scala-2.12/classes/ifu/ifu_compress$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_compress$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_compress.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ic$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ic$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ic.class create mode 100644 target/scala-2.12/classes/ifu/ifu_iccm$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_iccm.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ifc$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ifc$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_ifc.class create mode 100644 target/scala-2.12/classes/ifu/ifu_mem$.class create mode 100644 target/scala-2.12/classes/ifu/ifu_mem$delayedInit$body.class create mode 100644 target/scala-2.12/classes/ifu/ifu_mem.class create mode 100644 target/scala-2.12/classes/ifu/mem_ctl_bundle.class create mode 100644 target/scala-2.12/classes/include/el2_dec_tlu_csr_pkt.class create mode 100644 target/scala-2.12/classes/lib/AHB_main$.class create mode 100644 target/scala-2.12/classes/lib/AHB_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lib/AHB_main.class create mode 100644 target/scala-2.12/classes/lib/AXImain$.class create mode 100644 target/scala-2.12/classes/lib/AXImain$delayedInit$body.class create mode 100644 target/scala-2.12/classes/lib/AXImain.class create mode 100644 target/scala-2.12/classes/lib/Config.class create mode 100644 target/scala-2.12/classes/lib/ExpandedInstruction.class create mode 100644 target/scala-2.12/classes/lib/RVCDecoder.class create mode 100644 target/scala-2.12/classes/lib/RVCExpander$$anon$1.class create mode 100644 target/scala-2.12/classes/lib/RVCExpander.class delete mode 100644 target/scala-2.12/classes/lib/TEC_RV_ICG$$anon$14.class delete mode 100644 target/scala-2.12/classes/lib/TEC_RV_ICG.class create mode 100644 target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class create mode 100644 target/scala-2.12/classes/lib/ahb_to_axi4.class create mode 100644 target/scala-2.12/classes/lib/axi4_to_ahb.class create mode 100644 target/scala-2.12/classes/lib/axi4_to_ahb_IO.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$gated_latch$$anon$3.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$gated_latch.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvclkhdr$$anon$4.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvclkhdr$.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvclkhdr.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvdffe$.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvecc_encode$$anon$1.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvecc_encode.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvecc_encode_64$$anon$2.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvecc_encode_64.class create mode 100644 target/scala-2.12/classes/lib/el2_lib$rvsyncss$.class delete mode 100644 target/scala-2.12/classes/lib/rvbradder.class rename target/scala-2.12/classes/lib/{rvbradder$$anon$4.class => rvbsadder$$anon$6.class} (58%) create mode 100644 target/scala-2.12/classes/lib/rvbsadder.class delete mode 100644 target/scala-2.12/classes/lib/rvclkhdr$$anon$15.class delete mode 100644 target/scala-2.12/classes/lib/rvclkhdr$.class delete mode 100644 target/scala-2.12/classes/lib/rvclkhdr.class delete mode 100644 target/scala-2.12/classes/lib/rvdffe$.class delete mode 100644 target/scala-2.12/classes/lib/rvdffe.class create mode 100644 target/scala-2.12/classes/lib/rvdffs$$anon$3.class create mode 100644 target/scala-2.12/classes/lib/rvdffs.class create mode 100644 target/scala-2.12/classes/lib/rvdffsc$$anon$2.class create mode 100644 target/scala-2.12/classes/lib/rvdffsc.class rename target/scala-2.12/classes/lib/{rvecc_decode$$anon$11.class => rvecc_decode$$anon$13.class} (71%) rename target/scala-2.12/classes/lib/{rvecc_decode_64$$anon$13.class => rvecc_decode_64$$anon$15.class} (75%) create mode 100644 target/scala-2.12/classes/lib/rvecc_decode_64$rvsyncss$.class rename target/scala-2.12/classes/lib/{rvecc_encode$$anon$10.class => rvecc_encode$$anon$12.class} (77%) rename target/scala-2.12/classes/lib/{rvecc_encode_64$$anon$12.class => rvecc_encode_64$$anon$14.class} (77%) rename target/scala-2.12/classes/lib/{rveven_paritycheck$$anon$9.class => rveven_paritycheck$$anon$11.class} (56%) rename target/scala-2.12/classes/lib/{rveven_paritygen$$anon$8.class => rveven_paritygen$$anon$10.class} (57%) rename target/scala-2.12/classes/lib/{rvlsadder$$anon$3.class => rvlsadder$$anon$5.class} (75%) rename target/scala-2.12/classes/lib/{rvmaskandmatch$$anon$6.class => rvmaskandmatch$$anon$8.class} (75%) rename target/scala-2.12/classes/lib/{rvrangecheck_ch$$anon$7.class => rvrangecheck$$anon$9.class} (50%) create mode 100644 target/scala-2.12/classes/lib/rvrangecheck$.class create mode 100644 target/scala-2.12/classes/lib/rvrangecheck.class delete mode 100644 target/scala-2.12/classes/lib/rvrangecheck_ch$.class delete mode 100644 target/scala-2.12/classes/lib/rvrangecheck_ch.class delete mode 100644 target/scala-2.12/classes/lib/rvsyncss$$anon$2.class create mode 100644 target/scala-2.12/classes/lib/rvsyncss$$anon$4.class rename target/scala-2.12/classes/lib/{rvtwoscomp$$anon$5.class => rvtwoscomp$$anon$7.class} (77%) delete mode 100644 target/scala-2.12/classes/lsu/DCCM$.class delete mode 100644 target/scala-2.12/classes/lsu/DCCM$delayedInit$body.class delete mode 100644 target/scala-2.12/classes/lsu/el2_lsu_dccm_mem$$anon$1.class delete mode 100644 target/scala-2.12/classes/lsu/el2_lsu_dccm_mem.class create mode 100644 target/scala-2.12/classes/pic_main$.class create mode 100644 target/scala-2.12/classes/pic_main$delayedInit$body.class create mode 100644 target/scala-2.12/classes/pic_main.class delete mode 100644 target/scala-2.12/classes/snapshot/pt1$.class delete mode 100644 target/scala-2.12/classes/snapshot/pt1.class create mode 100644 target/scala-2.12/classes/vsrc/gated_latch.v diff --git a/el2_dec_decode_ctl.anno.json b/el2_dec_decode_ctl.anno.json new file mode 100644 index 00000000..166bf2ae --- /dev/null +++ b/el2_dec_decode_ctl.anno.json @@ -0,0 +1,1492 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_pmu_decode_stall", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_decode_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_load_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dma_dccm_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_store_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_csr_any_unq_d", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + 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"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_add", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_predict_p_d_pja", + "sources":[ + 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"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_i0_ap_predict_t", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ctl_en", + "sources":[ + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_clk_override", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_decode_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_ib0_valid_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_flush_lower_r", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_load_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dma_dccm_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_div_active", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_store_stall_any", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_icaf_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_dbecc_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_instr_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs1_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_div_waddr_wb", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_rs2_en_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_start_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_debug_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_pipelining_disable", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_valid_m", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_br_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_ret", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_debug_fence_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_extint_stall", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dbg_cmd_wrdata", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_toffset", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_tlu_presync_d", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_dec_i0_brp_hist", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_valid", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_error", + "~el2_dec_decode_ctl|el2_dec_decode_ctl>io_lsu_nonblock_load_data_tag" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_dec_decode_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_dec_decode_ctl" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_dec_decode_ctl.fir b/el2_dec_decode_ctl.fir new file mode 100644 index 00000000..00b17a96 --- /dev/null +++ b/el2_dec_decode_ctl.fir @@ -0,0 +1,5032 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_dec_decode_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dec_dec_ctl : + input clock : Clock + input reset : Reset + output io : {flip ins : UInt<32>, out : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>}} + + node _T = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 72:23] + node _T_1 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 72:35] + node _T_2 = or(_T, _T_1) @[el2_dec_dec_ctl.scala 72:27] + node _T_3 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 72:49] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:42] + node _T_5 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:60] + node _T_6 = and(_T_4, _T_5) @[el2_dec_dec_ctl.scala 72:53] + node _T_7 = or(_T_2, _T_6) @[el2_dec_dec_ctl.scala 72:39] + node _T_8 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 72:75] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 72:68] + node _T_10 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 72:85] + node _T_11 = and(_T_9, _T_10) @[el2_dec_dec_ctl.scala 72:78] + node _T_12 = or(_T_7, _T_11) @[el2_dec_dec_ctl.scala 72:65] + io.out.alu <= _T_12 @[el2_dec_dec_ctl.scala 72:14] + node _T_13 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_15 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_17 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_19 = and(_T_14, _T_16) @[el2_dec_dec_ctl.scala 73:51] + node _T_20 = and(_T_19, _T_18) @[el2_dec_dec_ctl.scala 73:51] + node _T_21 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_23 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_24 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_26 = and(_T_22, _T_23) @[el2_dec_dec_ctl.scala 73:90] + node _T_27 = and(_T_26, _T_25) @[el2_dec_dec_ctl.scala 73:90] + node _T_28 = or(_T_20, _T_27) @[el2_dec_dec_ctl.scala 73:55] + node _T_29 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_30 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_31 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_32 = eq(_T_31, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_33 = and(_T_29, _T_30) @[el2_dec_dec_ctl.scala 74:37] + node _T_34 = and(_T_33, _T_32) @[el2_dec_dec_ctl.scala 74:37] + node _T_35 = or(_T_28, _T_34) @[el2_dec_dec_ctl.scala 73:94] + node _T_36 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_38 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_39 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_40 = eq(_T_39, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_41 = and(_T_37, _T_38) @[el2_dec_dec_ctl.scala 74:76] + node _T_42 = and(_T_41, _T_40) @[el2_dec_dec_ctl.scala 74:76] + node _T_43 = or(_T_35, _T_42) @[el2_dec_dec_ctl.scala 74:41] + node _T_44 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_46 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_47 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_49 = and(_T_45, _T_46) @[el2_dec_dec_ctl.scala 75:38] + node _T_50 = and(_T_49, _T_48) @[el2_dec_dec_ctl.scala 75:38] + node _T_51 = or(_T_43, _T_50) @[el2_dec_dec_ctl.scala 74:80] + node _T_52 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_54 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_55 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_57 = and(_T_53, _T_54) @[el2_dec_dec_ctl.scala 75:76] + node _T_58 = and(_T_57, _T_56) @[el2_dec_dec_ctl.scala 75:76] + node _T_59 = or(_T_51, _T_58) @[el2_dec_dec_ctl.scala 75:42] + node _T_60 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_61 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_62 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_63 = eq(_T_62, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_64 = and(_T_60, _T_61) @[el2_dec_dec_ctl.scala 76:37] + node _T_65 = and(_T_64, _T_63) @[el2_dec_dec_ctl.scala 76:37] + node _T_66 = or(_T_59, _T_65) @[el2_dec_dec_ctl.scala 75:80] + node _T_67 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_68 = eq(_T_67, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_69 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_70 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_71 = eq(_T_70, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_72 = and(_T_68, _T_69) @[el2_dec_dec_ctl.scala 76:75] + node _T_73 = and(_T_72, _T_71) @[el2_dec_dec_ctl.scala 76:75] + node _T_74 = or(_T_66, _T_73) @[el2_dec_dec_ctl.scala 76:41] + node _T_75 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_76 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_77 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_79 = and(_T_75, _T_76) @[el2_dec_dec_ctl.scala 77:37] + node _T_80 = and(_T_79, _T_78) @[el2_dec_dec_ctl.scala 77:37] + node _T_81 = or(_T_74, _T_80) @[el2_dec_dec_ctl.scala 76:79] + node _T_82 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_83 = eq(_T_82, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_84 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_85 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_87 = and(_T_83, _T_84) @[el2_dec_dec_ctl.scala 77:75] + node _T_88 = and(_T_87, _T_86) @[el2_dec_dec_ctl.scala 77:75] + node _T_89 = or(_T_81, _T_88) @[el2_dec_dec_ctl.scala 77:41] + node _T_90 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_91 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_92 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_94 = and(_T_90, _T_91) @[el2_dec_dec_ctl.scala 78:37] + node _T_95 = and(_T_94, _T_93) @[el2_dec_dec_ctl.scala 78:37] + node _T_96 = or(_T_89, _T_95) @[el2_dec_dec_ctl.scala 77:79] + node _T_97 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_99 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_100 = eq(_T_99, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_101 = and(_T_98, _T_100) @[el2_dec_dec_ctl.scala 78:71] + node _T_102 = or(_T_96, _T_101) @[el2_dec_dec_ctl.scala 78:41] + node _T_103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_105 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_107 = and(_T_104, _T_106) @[el2_dec_dec_ctl.scala 78:106] + node _T_108 = or(_T_102, _T_107) @[el2_dec_dec_ctl.scala 78:75] + io.out.rs1 <= _T_108 @[el2_dec_dec_ctl.scala 73:14] + node _T_109 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_110 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_111 = eq(_T_110, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_112 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_114 = and(_T_109, _T_111) @[el2_dec_dec_ctl.scala 79:48] + node _T_115 = and(_T_114, _T_113) @[el2_dec_dec_ctl.scala 79:48] + node _T_116 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_118 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_119 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_121 = and(_T_117, _T_118) @[el2_dec_dec_ctl.scala 79:85] + node _T_122 = and(_T_121, _T_120) @[el2_dec_dec_ctl.scala 79:85] + node _T_123 = or(_T_115, _T_122) @[el2_dec_dec_ctl.scala 79:52] + io.out.rs2 <= _T_123 @[el2_dec_dec_ctl.scala 79:14] + node _T_124 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_126 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_127 = eq(_T_126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_128 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_129 = and(_T_125, _T_127) @[el2_dec_dec_ctl.scala 80:50] + node _T_130 = and(_T_129, _T_128) @[el2_dec_dec_ctl.scala 80:50] + node _T_131 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_132 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_133 = eq(_T_132, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_134 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_135 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_137 = and(_T_131, _T_133) @[el2_dec_dec_ctl.scala 80:90] + node _T_138 = and(_T_137, _T_134) @[el2_dec_dec_ctl.scala 80:90] + node _T_139 = and(_T_138, _T_136) @[el2_dec_dec_ctl.scala 80:90] + node _T_140 = or(_T_130, _T_139) @[el2_dec_dec_ctl.scala 80:54] + node _T_141 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_142 = eq(_T_141, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_143 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_144 = eq(_T_143, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_145 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_146 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_147 = and(_T_142, _T_144) @[el2_dec_dec_ctl.scala 81:40] + node _T_148 = and(_T_147, _T_145) @[el2_dec_dec_ctl.scala 81:40] + node _T_149 = and(_T_148, _T_146) @[el2_dec_dec_ctl.scala 81:40] + node _T_150 = or(_T_140, _T_149) @[el2_dec_dec_ctl.scala 80:94] + node _T_151 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_153 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_155 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_156 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_157 = eq(_T_156, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_158 = and(_T_152, _T_154) @[el2_dec_dec_ctl.scala 81:81] + node _T_159 = and(_T_158, _T_155) @[el2_dec_dec_ctl.scala 81:81] + node _T_160 = and(_T_159, _T_157) @[el2_dec_dec_ctl.scala 81:81] + node _T_161 = or(_T_150, _T_160) @[el2_dec_dec_ctl.scala 81:44] + io.out.imm12 <= _T_161 @[el2_dec_dec_ctl.scala 80:16] + node _T_162 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:24] + node _T_163 = eq(_T_162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:17] + node _T_164 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:37] + node _T_165 = eq(_T_164, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 82:30] + node _T_166 = and(_T_163, _T_165) @[el2_dec_dec_ctl.scala 82:28] + node _T_167 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 82:51] + node _T_168 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 82:63] + node _T_169 = and(_T_167, _T_168) @[el2_dec_dec_ctl.scala 82:55] + node _T_170 = or(_T_166, _T_169) @[el2_dec_dec_ctl.scala 82:42] + node _T_171 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 82:76] + node _T_172 = or(_T_170, _T_171) @[el2_dec_dec_ctl.scala 82:68] + io.out.rd <= _T_172 @[el2_dec_dec_ctl.scala 82:13] + node _T_173 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_174 = eq(_T_173, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_175 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_176 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_177 = eq(_T_176, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_178 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_179 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_181 = and(_T_174, _T_175) @[el2_dec_dec_ctl.scala 83:58] + node _T_182 = and(_T_181, _T_177) @[el2_dec_dec_ctl.scala 83:58] + node _T_183 = and(_T_182, _T_178) @[el2_dec_dec_ctl.scala 83:58] + node _T_184 = and(_T_183, _T_180) @[el2_dec_dec_ctl.scala 83:58] + io.out.shimm5 <= _T_184 @[el2_dec_dec_ctl.scala 83:17] + node _T_185 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 84:26] + node _T_186 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 84:36] + node _T_187 = and(_T_185, _T_186) @[el2_dec_dec_ctl.scala 84:29] + node _T_188 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 84:50] + node _T_189 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 84:60] + node _T_190 = and(_T_188, _T_189) @[el2_dec_dec_ctl.scala 84:53] + node _T_191 = or(_T_187, _T_190) @[el2_dec_dec_ctl.scala 84:41] + io.out.imm20 <= _T_191 @[el2_dec_dec_ctl.scala 84:16] + node _T_192 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:24] + node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:17] + node _T_194 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:37] + node _T_195 = eq(_T_194, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 85:30] + node _T_196 = and(_T_193, _T_195) @[el2_dec_dec_ctl.scala 85:28] + node _T_197 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 85:49] + node _T_198 = and(_T_196, _T_197) @[el2_dec_dec_ctl.scala 85:41] + node _T_199 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 85:63] + node _T_200 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 85:75] + node _T_201 = and(_T_199, _T_200) @[el2_dec_dec_ctl.scala 85:67] + node _T_202 = or(_T_198, _T_201) @[el2_dec_dec_ctl.scala 85:54] + io.out.pc <= _T_202 @[el2_dec_dec_ctl.scala 85:13] + node _T_203 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_204 = eq(_T_203, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_205 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_206 = eq(_T_205, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_207 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_209 = and(_T_204, _T_206) @[el2_dec_dec_ctl.scala 86:50] + node _T_210 = and(_T_209, _T_208) @[el2_dec_dec_ctl.scala 86:50] + io.out.load <= _T_210 @[el2_dec_dec_ctl.scala 86:15] + node _T_211 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_212 = eq(_T_211, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_213 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_214 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_215 = eq(_T_214, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_216 = and(_T_212, _T_213) @[el2_dec_dec_ctl.scala 87:50] + node _T_217 = and(_T_216, _T_215) @[el2_dec_dec_ctl.scala 87:50] + io.out.store <= _T_217 @[el2_dec_dec_ctl.scala 87:16] + node _T_218 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_219 = eq(_T_218, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_220 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_221 = eq(_T_220, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_222 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_223 = eq(_T_222, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_224 = and(_T_219, _T_221) @[el2_dec_dec_ctl.scala 88:49] + node _T_225 = and(_T_224, _T_223) @[el2_dec_dec_ctl.scala 88:49] + io.out.lsu <= _T_225 @[el2_dec_dec_ctl.scala 88:14] + node _T_226 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_228 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_229 = eq(_T_228, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_230 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_232 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_234 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_235 = and(_T_227, _T_229) @[el2_dec_dec_ctl.scala 89:57] + node _T_236 = and(_T_235, _T_231) @[el2_dec_dec_ctl.scala 89:57] + node _T_237 = and(_T_236, _T_233) @[el2_dec_dec_ctl.scala 89:57] + node _T_238 = and(_T_237, _T_234) @[el2_dec_dec_ctl.scala 89:57] + node _T_239 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_240 = eq(_T_239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_241 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_243 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_244 = and(_T_240, _T_242) @[el2_dec_dec_ctl.scala 89:94] + node _T_245 = and(_T_244, _T_243) @[el2_dec_dec_ctl.scala 89:94] + node _T_246 = or(_T_238, _T_245) @[el2_dec_dec_ctl.scala 89:61] + node _T_247 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_249 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_250 = eq(_T_249, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_251 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_253 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_254 = eq(_T_253, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_255 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_257 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_259 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_260 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_261 = eq(_T_260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_262 = and(_T_248, _T_250) @[el2_dec_dec_ctl.scala 90:56] + node _T_263 = and(_T_262, _T_252) @[el2_dec_dec_ctl.scala 90:56] + node _T_264 = and(_T_263, _T_254) @[el2_dec_dec_ctl.scala 90:56] + node _T_265 = and(_T_264, _T_256) @[el2_dec_dec_ctl.scala 90:56] + node _T_266 = and(_T_265, _T_258) @[el2_dec_dec_ctl.scala 90:56] + node _T_267 = and(_T_266, _T_259) @[el2_dec_dec_ctl.scala 90:56] + node _T_268 = and(_T_267, _T_261) @[el2_dec_dec_ctl.scala 90:56] + node _T_269 = or(_T_246, _T_268) @[el2_dec_dec_ctl.scala 89:98] + io.out.add <= _T_269 @[el2_dec_dec_ctl.scala 89:14] + node _T_270 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_271 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_272 = eq(_T_271, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_273 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_274 = eq(_T_273, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_275 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_276 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_279 = and(_T_270, _T_272) @[el2_dec_dec_ctl.scala 91:57] + node _T_280 = and(_T_279, _T_274) @[el2_dec_dec_ctl.scala 91:57] + node _T_281 = and(_T_280, _T_275) @[el2_dec_dec_ctl.scala 91:57] + node _T_282 = and(_T_281, _T_276) @[el2_dec_dec_ctl.scala 91:57] + node _T_283 = and(_T_282, _T_278) @[el2_dec_dec_ctl.scala 91:57] + node _T_284 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_286 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_288 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_289 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_290 = eq(_T_289, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_291 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_292 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_294 = and(_T_285, _T_287) @[el2_dec_dec_ctl.scala 91:105] + node _T_295 = and(_T_294, _T_288) @[el2_dec_dec_ctl.scala 91:105] + node _T_296 = and(_T_295, _T_290) @[el2_dec_dec_ctl.scala 91:105] + node _T_297 = and(_T_296, _T_291) @[el2_dec_dec_ctl.scala 91:105] + node _T_298 = and(_T_297, _T_293) @[el2_dec_dec_ctl.scala 91:105] + node _T_299 = or(_T_283, _T_298) @[el2_dec_dec_ctl.scala 91:61] + node _T_300 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_302 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_303 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_304 = eq(_T_303, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_305 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_306 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_308 = and(_T_301, _T_302) @[el2_dec_dec_ctl.scala 92:43] + node _T_309 = and(_T_308, _T_304) @[el2_dec_dec_ctl.scala 92:43] + node _T_310 = and(_T_309, _T_305) @[el2_dec_dec_ctl.scala 92:43] + node _T_311 = and(_T_310, _T_307) @[el2_dec_dec_ctl.scala 92:43] + node _T_312 = or(_T_299, _T_311) @[el2_dec_dec_ctl.scala 91:109] + node _T_313 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_314 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_315 = eq(_T_314, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_316 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_318 = and(_T_313, _T_315) @[el2_dec_dec_ctl.scala 92:80] + node _T_319 = and(_T_318, _T_317) @[el2_dec_dec_ctl.scala 92:80] + node _T_320 = or(_T_312, _T_319) @[el2_dec_dec_ctl.scala 92:47] + io.out.sub <= _T_320 @[el2_dec_dec_ctl.scala 91:14] + node _T_321 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_322 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_323 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_324 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_325 = eq(_T_324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_326 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_328 = and(_T_321, _T_322) @[el2_dec_dec_ctl.scala 93:56] + node _T_329 = and(_T_328, _T_323) @[el2_dec_dec_ctl.scala 93:56] + node _T_330 = and(_T_329, _T_325) @[el2_dec_dec_ctl.scala 93:56] + node _T_331 = and(_T_330, _T_327) @[el2_dec_dec_ctl.scala 93:56] + node _T_332 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_334 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_335 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_336 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_337 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_339 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_341 = and(_T_333, _T_334) @[el2_dec_dec_ctl.scala 93:104] + node _T_342 = and(_T_341, _T_335) @[el2_dec_dec_ctl.scala 93:104] + node _T_343 = and(_T_342, _T_336) @[el2_dec_dec_ctl.scala 93:104] + node _T_344 = and(_T_343, _T_338) @[el2_dec_dec_ctl.scala 93:104] + node _T_345 = and(_T_344, _T_340) @[el2_dec_dec_ctl.scala 93:104] + node _T_346 = or(_T_331, _T_345) @[el2_dec_dec_ctl.scala 93:60] + io.out.land <= _T_346 @[el2_dec_dec_ctl.scala 93:15] + node _T_347 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_348 = eq(_T_347, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_349 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_350 = and(_T_348, _T_349) @[el2_dec_dec_ctl.scala 94:45] + node _T_351 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_353 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_354 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_355 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_357 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_358 = eq(_T_357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_360 = eq(_T_359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_361 = and(_T_352, _T_353) @[el2_dec_dec_ctl.scala 94:94] + node _T_362 = and(_T_361, _T_354) @[el2_dec_dec_ctl.scala 94:94] + node _T_363 = and(_T_362, _T_356) @[el2_dec_dec_ctl.scala 94:94] + node _T_364 = and(_T_363, _T_358) @[el2_dec_dec_ctl.scala 94:94] + node _T_365 = and(_T_364, _T_360) @[el2_dec_dec_ctl.scala 94:94] + node _T_366 = or(_T_350, _T_365) @[el2_dec_dec_ctl.scala 94:49] + node _T_367 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_368 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_369 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_370 = and(_T_367, _T_368) @[el2_dec_dec_ctl.scala 95:34] + node _T_371 = and(_T_370, _T_369) @[el2_dec_dec_ctl.scala 95:34] + node _T_372 = or(_T_366, _T_371) @[el2_dec_dec_ctl.scala 94:98] + node _T_373 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_374 = eq(_T_373, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_375 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_377 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_378 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_379 = and(_T_374, _T_376) @[el2_dec_dec_ctl.scala 95:75] + node _T_380 = and(_T_379, _T_377) @[el2_dec_dec_ctl.scala 95:75] + node _T_381 = and(_T_380, _T_378) @[el2_dec_dec_ctl.scala 95:75] + node _T_382 = or(_T_372, _T_381) @[el2_dec_dec_ctl.scala 95:38] + node _T_383 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_384 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_385 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_386 = eq(_T_385, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_387 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_389 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_391 = and(_T_383, _T_384) @[el2_dec_dec_ctl.scala 96:44] + node _T_392 = and(_T_391, _T_386) @[el2_dec_dec_ctl.scala 96:44] + node _T_393 = and(_T_392, _T_388) @[el2_dec_dec_ctl.scala 96:44] + node _T_394 = and(_T_393, _T_390) @[el2_dec_dec_ctl.scala 96:44] + node _T_395 = or(_T_382, _T_394) @[el2_dec_dec_ctl.scala 95:79] + io.out.lor <= _T_395 @[el2_dec_dec_ctl.scala 94:14] + node _T_396 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_398 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_399 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_401 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_402 = eq(_T_401, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_403 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_404 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_405 = eq(_T_404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_406 = and(_T_397, _T_398) @[el2_dec_dec_ctl.scala 97:61] + node _T_407 = and(_T_406, _T_400) @[el2_dec_dec_ctl.scala 97:61] + node _T_408 = and(_T_407, _T_402) @[el2_dec_dec_ctl.scala 97:61] + node _T_409 = and(_T_408, _T_403) @[el2_dec_dec_ctl.scala 97:61] + node _T_410 = and(_T_409, _T_405) @[el2_dec_dec_ctl.scala 97:61] + node _T_411 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_412 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_414 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_415 = eq(_T_414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_416 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_417 = eq(_T_416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_418 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_419 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_421 = and(_T_411, _T_413) @[el2_dec_dec_ctl.scala 97:109] + node _T_422 = and(_T_421, _T_415) @[el2_dec_dec_ctl.scala 97:109] + node _T_423 = and(_T_422, _T_417) @[el2_dec_dec_ctl.scala 97:109] + node _T_424 = and(_T_423, _T_418) @[el2_dec_dec_ctl.scala 97:109] + node _T_425 = and(_T_424, _T_420) @[el2_dec_dec_ctl.scala 97:109] + node _T_426 = or(_T_410, _T_425) @[el2_dec_dec_ctl.scala 97:65] + io.out.lxor <= _T_426 @[el2_dec_dec_ctl.scala 97:15] + node _T_427 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_428 = eq(_T_427, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_429 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_430 = eq(_T_429, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_431 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_433 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_434 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_436 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_437 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_438 = eq(_T_437, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_439 = and(_T_428, _T_430) @[el2_dec_dec_ctl.scala 98:63] + node _T_440 = and(_T_439, _T_432) @[el2_dec_dec_ctl.scala 98:63] + node _T_441 = and(_T_440, _T_433) @[el2_dec_dec_ctl.scala 98:63] + node _T_442 = and(_T_441, _T_435) @[el2_dec_dec_ctl.scala 98:63] + node _T_443 = and(_T_442, _T_436) @[el2_dec_dec_ctl.scala 98:63] + node _T_444 = and(_T_443, _T_438) @[el2_dec_dec_ctl.scala 98:63] + io.out.sll <= _T_444 @[el2_dec_dec_ctl.scala 98:14] + node _T_445 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:33] + node _T_446 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_447 = eq(_T_446, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_448 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_449 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_450 = eq(_T_449, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_451 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_452 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_454 = and(_T_445, _T_447) @[el2_dec_dec_ctl.scala 99:58] + node _T_455 = and(_T_454, _T_448) @[el2_dec_dec_ctl.scala 99:58] + node _T_456 = and(_T_455, _T_450) @[el2_dec_dec_ctl.scala 99:58] + node _T_457 = and(_T_456, _T_451) @[el2_dec_dec_ctl.scala 99:58] + node _T_458 = and(_T_457, _T_453) @[el2_dec_dec_ctl.scala 99:58] + io.out.sra <= _T_458 @[el2_dec_dec_ctl.scala 99:14] + node _T_459 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_460 = eq(_T_459, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_461 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_463 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_464 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_465 = eq(_T_464, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_466 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_467 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_469 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_470 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_471 = eq(_T_470, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_472 = and(_T_460, _T_462) @[el2_dec_dec_ctl.scala 100:66] + node _T_473 = and(_T_472, _T_463) @[el2_dec_dec_ctl.scala 100:66] + node _T_474 = and(_T_473, _T_465) @[el2_dec_dec_ctl.scala 100:66] + node _T_475 = and(_T_474, _T_466) @[el2_dec_dec_ctl.scala 100:66] + node _T_476 = and(_T_475, _T_468) @[el2_dec_dec_ctl.scala 100:66] + node _T_477 = and(_T_476, _T_469) @[el2_dec_dec_ctl.scala 100:66] + node _T_478 = and(_T_477, _T_471) @[el2_dec_dec_ctl.scala 100:66] + io.out.srl <= _T_478 @[el2_dec_dec_ctl.scala 100:14] + node _T_479 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_480 = eq(_T_479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_481 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_482 = eq(_T_481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_483 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_484 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_485 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_487 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_488 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_490 = and(_T_480, _T_482) @[el2_dec_dec_ctl.scala 101:62] + node _T_491 = and(_T_490, _T_483) @[el2_dec_dec_ctl.scala 101:62] + node _T_492 = and(_T_491, _T_484) @[el2_dec_dec_ctl.scala 101:62] + node _T_493 = and(_T_492, _T_486) @[el2_dec_dec_ctl.scala 101:62] + node _T_494 = and(_T_493, _T_487) @[el2_dec_dec_ctl.scala 101:62] + node _T_495 = and(_T_494, _T_489) @[el2_dec_dec_ctl.scala 101:62] + node _T_496 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_498 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_499 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_501 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_502 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_503 = eq(_T_502, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_504 = and(_T_497, _T_498) @[el2_dec_dec_ctl.scala 101:106] + node _T_505 = and(_T_504, _T_500) @[el2_dec_dec_ctl.scala 101:106] + node _T_506 = and(_T_505, _T_501) @[el2_dec_dec_ctl.scala 101:106] + node _T_507 = and(_T_506, _T_503) @[el2_dec_dec_ctl.scala 101:106] + node _T_508 = or(_T_495, _T_507) @[el2_dec_dec_ctl.scala 101:66] + io.out.slt <= _T_508 @[el2_dec_dec_ctl.scala 101:14] + node _T_509 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_510 = eq(_T_509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_511 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_512 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_513 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_515 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_517 = and(_T_510, _T_511) @[el2_dec_dec_ctl.scala 102:59] + node _T_518 = and(_T_517, _T_512) @[el2_dec_dec_ctl.scala 102:59] + node _T_519 = and(_T_518, _T_514) @[el2_dec_dec_ctl.scala 102:59] + node _T_520 = and(_T_519, _T_516) @[el2_dec_dec_ctl.scala 102:59] + node _T_521 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_522 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_523 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_524 = eq(_T_523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_525 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_526 = eq(_T_525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_527 = and(_T_521, _T_522) @[el2_dec_dec_ctl.scala 102:99] + node _T_528 = and(_T_527, _T_524) @[el2_dec_dec_ctl.scala 102:99] + node _T_529 = and(_T_528, _T_526) @[el2_dec_dec_ctl.scala 102:99] + node _T_530 = or(_T_520, _T_529) @[el2_dec_dec_ctl.scala 102:63] + node _T_531 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_532 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_534 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_536 = and(_T_531, _T_533) @[el2_dec_dec_ctl.scala 103:37] + node _T_537 = and(_T_536, _T_535) @[el2_dec_dec_ctl.scala 103:37] + node _T_538 = or(_T_530, _T_537) @[el2_dec_dec_ctl.scala 102:103] + node _T_539 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_540 = eq(_T_539, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_541 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_542 = eq(_T_541, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_543 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_544 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_545 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_547 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_548 = eq(_T_547, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_549 = and(_T_540, _T_542) @[el2_dec_dec_ctl.scala 103:86] + node _T_550 = and(_T_549, _T_543) @[el2_dec_dec_ctl.scala 103:86] + node _T_551 = and(_T_550, _T_544) @[el2_dec_dec_ctl.scala 103:86] + node _T_552 = and(_T_551, _T_546) @[el2_dec_dec_ctl.scala 103:86] + node _T_553 = and(_T_552, _T_548) @[el2_dec_dec_ctl.scala 103:86] + node _T_554 = or(_T_538, _T_553) @[el2_dec_dec_ctl.scala 103:41] + node _T_555 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_556 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_557 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_558 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_559 = eq(_T_558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_560 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_561 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_563 = and(_T_555, _T_556) @[el2_dec_dec_ctl.scala 104:45] + node _T_564 = and(_T_563, _T_557) @[el2_dec_dec_ctl.scala 104:45] + node _T_565 = and(_T_564, _T_559) @[el2_dec_dec_ctl.scala 104:45] + node _T_566 = and(_T_565, _T_560) @[el2_dec_dec_ctl.scala 104:45] + node _T_567 = and(_T_566, _T_562) @[el2_dec_dec_ctl.scala 104:45] + node _T_568 = or(_T_554, _T_567) @[el2_dec_dec_ctl.scala 103:90] + io.out.unsign <= _T_568 @[el2_dec_dec_ctl.scala 102:17] + node _T_569 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_570 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_571 = eq(_T_570, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_572 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_573 = eq(_T_572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_574 = and(_T_569, _T_571) @[el2_dec_dec_ctl.scala 105:51] + node _T_575 = and(_T_574, _T_573) @[el2_dec_dec_ctl.scala 105:51] + io.out.condbr <= _T_575 @[el2_dec_dec_ctl.scala 105:17] + node _T_576 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_577 = eq(_T_576, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_578 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_580 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_581 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_582 = eq(_T_581, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_583 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_584 = eq(_T_583, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_585 = and(_T_577, _T_579) @[el2_dec_dec_ctl.scala 106:56] + node _T_586 = and(_T_585, _T_580) @[el2_dec_dec_ctl.scala 106:56] + node _T_587 = and(_T_586, _T_582) @[el2_dec_dec_ctl.scala 106:56] + node _T_588 = and(_T_587, _T_584) @[el2_dec_dec_ctl.scala 106:56] + io.out.beq <= _T_588 @[el2_dec_dec_ctl.scala 106:14] + node _T_589 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_590 = eq(_T_589, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_591 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_592 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_593 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_594 = eq(_T_593, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_595 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_597 = and(_T_590, _T_591) @[el2_dec_dec_ctl.scala 107:55] + node _T_598 = and(_T_597, _T_592) @[el2_dec_dec_ctl.scala 107:55] + node _T_599 = and(_T_598, _T_594) @[el2_dec_dec_ctl.scala 107:55] + node _T_600 = and(_T_599, _T_596) @[el2_dec_dec_ctl.scala 107:55] + io.out.bne <= _T_600 @[el2_dec_dec_ctl.scala 107:14] + node _T_601 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_602 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_603 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_604 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_606 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_607 = eq(_T_606, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_608 = and(_T_601, _T_602) @[el2_dec_dec_ctl.scala 108:54] + node _T_609 = and(_T_608, _T_603) @[el2_dec_dec_ctl.scala 108:54] + node _T_610 = and(_T_609, _T_605) @[el2_dec_dec_ctl.scala 108:54] + node _T_611 = and(_T_610, _T_607) @[el2_dec_dec_ctl.scala 108:54] + io.out.bge <= _T_611 @[el2_dec_dec_ctl.scala 108:14] + node _T_612 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_613 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_614 = eq(_T_613, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_615 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_616 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_617 = eq(_T_616, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_618 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_619 = eq(_T_618, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_620 = and(_T_612, _T_614) @[el2_dec_dec_ctl.scala 109:55] + node _T_621 = and(_T_620, _T_615) @[el2_dec_dec_ctl.scala 109:55] + node _T_622 = and(_T_621, _T_617) @[el2_dec_dec_ctl.scala 109:55] + node _T_623 = and(_T_622, _T_619) @[el2_dec_dec_ctl.scala 109:55] + io.out.blt <= _T_623 @[el2_dec_dec_ctl.scala 109:14] + node _T_624 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_625 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_626 = and(_T_624, _T_625) @[el2_dec_dec_ctl.scala 110:44] + io.out.jal <= _T_626 @[el2_dec_dec_ctl.scala 110:14] + node _T_627 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_628 = eq(_T_627, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_629 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_631 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_632 = eq(_T_631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_633 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_634 = eq(_T_633, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_635 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_636 = eq(_T_635, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_637 = and(_T_628, _T_630) @[el2_dec_dec_ctl.scala 111:56] + node _T_638 = and(_T_637, _T_632) @[el2_dec_dec_ctl.scala 111:56] + node _T_639 = and(_T_638, _T_634) @[el2_dec_dec_ctl.scala 111:56] + node _T_640 = and(_T_639, _T_636) @[el2_dec_dec_ctl.scala 111:56] + io.out.by <= _T_640 @[el2_dec_dec_ctl.scala 111:13] + node _T_641 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_642 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_643 = eq(_T_642, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_644 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_646 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_647 = eq(_T_646, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_648 = and(_T_641, _T_643) @[el2_dec_dec_ctl.scala 112:53] + node _T_649 = and(_T_648, _T_645) @[el2_dec_dec_ctl.scala 112:53] + node _T_650 = and(_T_649, _T_647) @[el2_dec_dec_ctl.scala 112:53] + io.out.half <= _T_650 @[el2_dec_dec_ctl.scala 112:15] + node _T_651 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_652 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_653 = eq(_T_652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_654 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_655 = eq(_T_654, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_656 = and(_T_651, _T_653) @[el2_dec_dec_ctl.scala 113:50] + node _T_657 = and(_T_656, _T_655) @[el2_dec_dec_ctl.scala 113:50] + io.out.word <= _T_657 @[el2_dec_dec_ctl.scala 113:15] + node _T_658 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_659 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_660 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_661 = and(_T_658, _T_659) @[el2_dec_dec_ctl.scala 114:52] + node _T_662 = and(_T_661, _T_660) @[el2_dec_dec_ctl.scala 114:52] + node _T_663 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_664 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_665 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_666 = and(_T_663, _T_664) @[el2_dec_dec_ctl.scala 114:87] + node _T_667 = and(_T_666, _T_665) @[el2_dec_dec_ctl.scala 114:87] + node _T_668 = or(_T_662, _T_667) @[el2_dec_dec_ctl.scala 114:56] + node _T_669 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_670 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_672 = and(_T_669, _T_670) @[el2_dec_dec_ctl.scala 115:34] + node _T_673 = and(_T_672, _T_671) @[el2_dec_dec_ctl.scala 115:34] + node _T_674 = or(_T_668, _T_673) @[el2_dec_dec_ctl.scala 114:91] + node _T_675 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_676 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_677 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_678 = and(_T_675, _T_676) @[el2_dec_dec_ctl.scala 115:69] + node _T_679 = and(_T_678, _T_677) @[el2_dec_dec_ctl.scala 115:69] + node _T_680 = or(_T_674, _T_679) @[el2_dec_dec_ctl.scala 115:38] + node _T_681 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_682 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_683 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_684 = and(_T_681, _T_682) @[el2_dec_dec_ctl.scala 115:105] + node _T_685 = and(_T_684, _T_683) @[el2_dec_dec_ctl.scala 115:105] + node _T_686 = or(_T_680, _T_685) @[el2_dec_dec_ctl.scala 115:73] + node _T_687 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_688 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_690 = and(_T_687, _T_688) @[el2_dec_dec_ctl.scala 116:35] + node _T_691 = and(_T_690, _T_689) @[el2_dec_dec_ctl.scala 116:35] + node _T_692 = or(_T_686, _T_691) @[el2_dec_dec_ctl.scala 115:109] + io.out.csr_read <= _T_692 @[el2_dec_dec_ctl.scala 114:19] + node _T_693 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_694 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_695 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_696 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_697 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_698 = and(_T_693, _T_694) @[el2_dec_dec_ctl.scala 117:57] + node _T_699 = and(_T_698, _T_695) @[el2_dec_dec_ctl.scala 117:57] + node _T_700 = and(_T_699, _T_696) @[el2_dec_dec_ctl.scala 117:57] + node _T_701 = and(_T_700, _T_697) @[el2_dec_dec_ctl.scala 117:57] + node _T_702 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_703 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_704 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_705 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_706 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_707 = and(_T_702, _T_703) @[el2_dec_dec_ctl.scala 117:99] + node _T_708 = and(_T_707, _T_704) @[el2_dec_dec_ctl.scala 117:99] + node _T_709 = and(_T_708, _T_705) @[el2_dec_dec_ctl.scala 117:99] + node _T_710 = and(_T_709, _T_706) @[el2_dec_dec_ctl.scala 117:99] + node _T_711 = or(_T_701, _T_710) @[el2_dec_dec_ctl.scala 117:61] + node _T_712 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_713 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_714 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_715 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_716 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_717 = and(_T_712, _T_713) @[el2_dec_dec_ctl.scala 118:41] + node _T_718 = and(_T_717, _T_714) @[el2_dec_dec_ctl.scala 118:41] + node _T_719 = and(_T_718, _T_715) @[el2_dec_dec_ctl.scala 118:41] + node _T_720 = and(_T_719, _T_716) @[el2_dec_dec_ctl.scala 118:41] + node _T_721 = or(_T_711, _T_720) @[el2_dec_dec_ctl.scala 117:103] + node _T_722 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_723 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_724 = eq(_T_723, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_725 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_726 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_727 = and(_T_722, _T_724) @[el2_dec_dec_ctl.scala 118:81] + node _T_728 = and(_T_727, _T_725) @[el2_dec_dec_ctl.scala 118:81] + node _T_729 = and(_T_728, _T_726) @[el2_dec_dec_ctl.scala 118:81] + node _T_730 = or(_T_721, _T_729) @[el2_dec_dec_ctl.scala 118:45] + node _T_731 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_732 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_733 = eq(_T_732, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_734 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_735 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_736 = and(_T_731, _T_733) @[el2_dec_dec_ctl.scala 119:39] + node _T_737 = and(_T_736, _T_734) @[el2_dec_dec_ctl.scala 119:39] + node _T_738 = and(_T_737, _T_735) @[el2_dec_dec_ctl.scala 119:39] + node _T_739 = or(_T_730, _T_738) @[el2_dec_dec_ctl.scala 118:85] + io.out.csr_clr <= _T_739 @[el2_dec_dec_ctl.scala 117:18] + node _T_740 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_741 = eq(_T_740, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_742 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_743 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_744 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_745 = and(_T_741, _T_742) @[el2_dec_dec_ctl.scala 120:57] + node _T_746 = and(_T_745, _T_743) @[el2_dec_dec_ctl.scala 120:57] + node _T_747 = and(_T_746, _T_744) @[el2_dec_dec_ctl.scala 120:57] + io.out.csr_write <= _T_747 @[el2_dec_dec_ctl.scala 120:20] + node _T_748 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_749 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_750 = eq(_T_749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_751 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_752 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_753 = and(_T_748, _T_750) @[el2_dec_dec_ctl.scala 121:55] + node _T_754 = and(_T_753, _T_751) @[el2_dec_dec_ctl.scala 121:55] + node _T_755 = and(_T_754, _T_752) @[el2_dec_dec_ctl.scala 121:55] + node _T_756 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_757 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_758 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_759 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_760 = and(_T_756, _T_757) @[el2_dec_dec_ctl.scala 121:94] + node _T_761 = and(_T_760, _T_758) @[el2_dec_dec_ctl.scala 121:94] + node _T_762 = and(_T_761, _T_759) @[el2_dec_dec_ctl.scala 121:94] + node _T_763 = or(_T_755, _T_762) @[el2_dec_dec_ctl.scala 121:59] + node _T_764 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_765 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_766 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_767 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_768 = and(_T_764, _T_765) @[el2_dec_dec_ctl.scala 122:38] + node _T_769 = and(_T_768, _T_766) @[el2_dec_dec_ctl.scala 122:38] + node _T_770 = and(_T_769, _T_767) @[el2_dec_dec_ctl.scala 122:38] + node _T_771 = or(_T_763, _T_770) @[el2_dec_dec_ctl.scala 121:98] + node _T_772 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_773 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_774 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_775 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_776 = and(_T_772, _T_773) @[el2_dec_dec_ctl.scala 122:77] + node _T_777 = and(_T_776, _T_774) @[el2_dec_dec_ctl.scala 122:77] + node _T_778 = and(_T_777, _T_775) @[el2_dec_dec_ctl.scala 122:77] + node _T_779 = or(_T_771, _T_778) @[el2_dec_dec_ctl.scala 122:42] + node _T_780 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_781 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_782 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_783 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_784 = and(_T_780, _T_781) @[el2_dec_dec_ctl.scala 123:38] + node _T_785 = and(_T_784, _T_782) @[el2_dec_dec_ctl.scala 123:38] + node _T_786 = and(_T_785, _T_783) @[el2_dec_dec_ctl.scala 123:38] + node _T_787 = or(_T_779, _T_786) @[el2_dec_dec_ctl.scala 122:81] + node _T_788 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_789 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_790 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_791 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_792 = and(_T_788, _T_789) @[el2_dec_dec_ctl.scala 123:77] + node _T_793 = and(_T_792, _T_790) @[el2_dec_dec_ctl.scala 123:77] + node _T_794 = and(_T_793, _T_791) @[el2_dec_dec_ctl.scala 123:77] + node _T_795 = or(_T_787, _T_794) @[el2_dec_dec_ctl.scala 123:42] + io.out.csr_imm <= _T_795 @[el2_dec_dec_ctl.scala 121:18] + node _T_796 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_797 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_799 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_800 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_801 = and(_T_796, _T_798) @[el2_dec_dec_ctl.scala 124:55] + node _T_802 = and(_T_801, _T_799) @[el2_dec_dec_ctl.scala 124:55] + node _T_803 = and(_T_802, _T_800) @[el2_dec_dec_ctl.scala 124:55] + node _T_804 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_805 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_806 = eq(_T_805, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_807 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_808 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_809 = and(_T_804, _T_806) @[el2_dec_dec_ctl.scala 124:95] + node _T_810 = and(_T_809, _T_807) @[el2_dec_dec_ctl.scala 124:95] + node _T_811 = and(_T_810, _T_808) @[el2_dec_dec_ctl.scala 124:95] + node _T_812 = or(_T_803, _T_811) @[el2_dec_dec_ctl.scala 124:59] + node _T_813 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_814 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_815 = eq(_T_814, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_816 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_817 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_818 = and(_T_813, _T_815) @[el2_dec_dec_ctl.scala 125:39] + node _T_819 = and(_T_818, _T_816) @[el2_dec_dec_ctl.scala 125:39] + node _T_820 = and(_T_819, _T_817) @[el2_dec_dec_ctl.scala 125:39] + node _T_821 = or(_T_812, _T_820) @[el2_dec_dec_ctl.scala 124:99] + node _T_822 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_823 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_824 = eq(_T_823, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_825 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_826 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_827 = and(_T_822, _T_824) @[el2_dec_dec_ctl.scala 125:79] + node _T_828 = and(_T_827, _T_825) @[el2_dec_dec_ctl.scala 125:79] + node _T_829 = and(_T_828, _T_826) @[el2_dec_dec_ctl.scala 125:79] + node _T_830 = or(_T_821, _T_829) @[el2_dec_dec_ctl.scala 125:43] + node _T_831 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_832 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_833 = eq(_T_832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_834 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_835 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_836 = and(_T_831, _T_833) @[el2_dec_dec_ctl.scala 126:39] + node _T_837 = and(_T_836, _T_834) @[el2_dec_dec_ctl.scala 126:39] + node _T_838 = and(_T_837, _T_835) @[el2_dec_dec_ctl.scala 126:39] + node _T_839 = or(_T_830, _T_838) @[el2_dec_dec_ctl.scala 125:83] + io.out.csr_set <= _T_839 @[el2_dec_dec_ctl.scala 124:18] + node _T_840 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_841 = eq(_T_840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_842 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_843 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_845 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_846 = eq(_T_845, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_847 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_848 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_849 = and(_T_841, _T_842) @[el2_dec_dec_ctl.scala 127:62] + node _T_850 = and(_T_849, _T_844) @[el2_dec_dec_ctl.scala 127:62] + node _T_851 = and(_T_850, _T_846) @[el2_dec_dec_ctl.scala 127:62] + node _T_852 = and(_T_851, _T_847) @[el2_dec_dec_ctl.scala 127:62] + node _T_853 = and(_T_852, _T_848) @[el2_dec_dec_ctl.scala 127:62] + io.out.ebreak <= _T_853 @[el2_dec_dec_ctl.scala 127:17] + node _T_854 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_856 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_857 = eq(_T_856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_858 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_859 = eq(_T_858, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_860 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_861 = eq(_T_860, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_862 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_863 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_864 = and(_T_855, _T_857) @[el2_dec_dec_ctl.scala 128:62] + node _T_865 = and(_T_864, _T_859) @[el2_dec_dec_ctl.scala 128:62] + node _T_866 = and(_T_865, _T_861) @[el2_dec_dec_ctl.scala 128:62] + node _T_867 = and(_T_866, _T_862) @[el2_dec_dec_ctl.scala 128:62] + node _T_868 = and(_T_867, _T_863) @[el2_dec_dec_ctl.scala 128:62] + io.out.ecall <= _T_868 @[el2_dec_dec_ctl.scala 128:16] + node _T_869 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_870 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_871 = eq(_T_870, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_872 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_873 = eq(_T_872, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_874 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_875 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_876 = and(_T_869, _T_871) @[el2_dec_dec_ctl.scala 129:56] + node _T_877 = and(_T_876, _T_873) @[el2_dec_dec_ctl.scala 129:56] + node _T_878 = and(_T_877, _T_874) @[el2_dec_dec_ctl.scala 129:56] + node _T_879 = and(_T_878, _T_875) @[el2_dec_dec_ctl.scala 129:56] + io.out.mret <= _T_879 @[el2_dec_dec_ctl.scala 129:15] + node _T_880 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_881 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_882 = eq(_T_881, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_883 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_884 = eq(_T_883, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_885 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_886 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_887 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_888 = eq(_T_887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_889 = and(_T_880, _T_882) @[el2_dec_dec_ctl.scala 130:57] + node _T_890 = and(_T_889, _T_884) @[el2_dec_dec_ctl.scala 130:57] + node _T_891 = and(_T_890, _T_885) @[el2_dec_dec_ctl.scala 130:57] + node _T_892 = and(_T_891, _T_886) @[el2_dec_dec_ctl.scala 130:57] + node _T_893 = and(_T_892, _T_888) @[el2_dec_dec_ctl.scala 130:57] + io.out.mul <= _T_893 @[el2_dec_dec_ctl.scala 130:14] + node _T_894 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_895 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_896 = eq(_T_895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_897 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_898 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_899 = eq(_T_898, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_900 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_901 = eq(_T_900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_902 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_903 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_904 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_905 = eq(_T_904, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_906 = and(_T_894, _T_896) @[el2_dec_dec_ctl.scala 131:69] + node _T_907 = and(_T_906, _T_897) @[el2_dec_dec_ctl.scala 131:69] + node _T_908 = and(_T_907, _T_899) @[el2_dec_dec_ctl.scala 131:69] + node _T_909 = and(_T_908, _T_901) @[el2_dec_dec_ctl.scala 131:69] + node _T_910 = and(_T_909, _T_902) @[el2_dec_dec_ctl.scala 131:69] + node _T_911 = and(_T_910, _T_903) @[el2_dec_dec_ctl.scala 131:69] + node _T_912 = and(_T_911, _T_905) @[el2_dec_dec_ctl.scala 131:69] + node _T_913 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_914 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_915 = eq(_T_914, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_916 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_917 = eq(_T_916, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_918 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_919 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_920 = eq(_T_919, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_921 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_922 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_923 = eq(_T_922, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_924 = and(_T_913, _T_915) @[el2_dec_dec_ctl.scala 132:50] + node _T_925 = and(_T_924, _T_917) @[el2_dec_dec_ctl.scala 132:50] + node _T_926 = and(_T_925, _T_918) @[el2_dec_dec_ctl.scala 132:50] + node _T_927 = and(_T_926, _T_920) @[el2_dec_dec_ctl.scala 132:50] + node _T_928 = and(_T_927, _T_921) @[el2_dec_dec_ctl.scala 132:50] + node _T_929 = and(_T_928, _T_923) @[el2_dec_dec_ctl.scala 132:50] + node _T_930 = or(_T_912, _T_929) @[el2_dec_dec_ctl.scala 131:73] + io.out.rs1_sign <= _T_930 @[el2_dec_dec_ctl.scala 131:19] + node _T_931 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_932 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_933 = eq(_T_932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_934 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_935 = eq(_T_934, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_936 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_937 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_938 = eq(_T_937, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_939 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_940 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_941 = eq(_T_940, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_942 = and(_T_931, _T_933) @[el2_dec_dec_ctl.scala 133:67] + node _T_943 = and(_T_942, _T_935) @[el2_dec_dec_ctl.scala 133:67] + node _T_944 = and(_T_943, _T_936) @[el2_dec_dec_ctl.scala 133:67] + node _T_945 = and(_T_944, _T_938) @[el2_dec_dec_ctl.scala 133:67] + node _T_946 = and(_T_945, _T_939) @[el2_dec_dec_ctl.scala 133:67] + node _T_947 = and(_T_946, _T_941) @[el2_dec_dec_ctl.scala 133:67] + io.out.rs2_sign <= _T_947 @[el2_dec_dec_ctl.scala 133:19] + node _T_948 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_949 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_950 = eq(_T_949, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_951 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_952 = eq(_T_951, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_953 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_954 = eq(_T_953, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_955 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_956 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_957 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_959 = and(_T_948, _T_950) @[el2_dec_dec_ctl.scala 134:62] + node _T_960 = and(_T_959, _T_952) @[el2_dec_dec_ctl.scala 134:62] + node _T_961 = and(_T_960, _T_954) @[el2_dec_dec_ctl.scala 134:62] + node _T_962 = and(_T_961, _T_955) @[el2_dec_dec_ctl.scala 134:62] + node _T_963 = and(_T_962, _T_956) @[el2_dec_dec_ctl.scala 134:62] + node _T_964 = and(_T_963, _T_958) @[el2_dec_dec_ctl.scala 134:62] + io.out.low <= _T_964 @[el2_dec_dec_ctl.scala 134:14] + node _T_965 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_966 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_968 = eq(_T_967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_969 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_970 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_971 = eq(_T_970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_972 = and(_T_965, _T_966) @[el2_dec_dec_ctl.scala 135:54] + node _T_973 = and(_T_972, _T_968) @[el2_dec_dec_ctl.scala 135:54] + node _T_974 = and(_T_973, _T_969) @[el2_dec_dec_ctl.scala 135:54] + node _T_975 = and(_T_974, _T_971) @[el2_dec_dec_ctl.scala 135:54] + io.out.div <= _T_975 @[el2_dec_dec_ctl.scala 135:14] + node _T_976 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:33] + node _T_977 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_978 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_979 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_980 = eq(_T_979, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_981 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_982 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_983 = eq(_T_982, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_984 = and(_T_976, _T_977) @[el2_dec_dec_ctl.scala 136:57] + node _T_985 = and(_T_984, _T_978) @[el2_dec_dec_ctl.scala 136:57] + node _T_986 = and(_T_985, _T_980) @[el2_dec_dec_ctl.scala 136:57] + node _T_987 = and(_T_986, _T_981) @[el2_dec_dec_ctl.scala 136:57] + node _T_988 = and(_T_987, _T_983) @[el2_dec_dec_ctl.scala 136:57] + io.out.rem <= _T_988 @[el2_dec_dec_ctl.scala 136:14] + node _T_989 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_990 = eq(_T_989, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_991 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_992 = and(_T_990, _T_991) @[el2_dec_dec_ctl.scala 137:47] + io.out.fence <= _T_992 @[el2_dec_dec_ctl.scala 137:16] + node _T_993 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_994 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_995 = eq(_T_994, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_996 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_997 = and(_T_993, _T_995) @[el2_dec_dec_ctl.scala 138:52] + node _T_998 = and(_T_997, _T_996) @[el2_dec_dec_ctl.scala 138:52] + io.out.fence_i <= _T_998 @[el2_dec_dec_ctl.scala 138:18] + node _T_999 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1000 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1001 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1003 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1005 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1006 = and(_T_999, _T_1000) @[el2_dec_dec_ctl.scala 139:59] + node _T_1007 = and(_T_1006, _T_1002) @[el2_dec_dec_ctl.scala 139:59] + node _T_1008 = and(_T_1007, _T_1004) @[el2_dec_dec_ctl.scala 139:59] + node _T_1009 = and(_T_1008, _T_1005) @[el2_dec_dec_ctl.scala 139:59] + node _T_1010 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1011 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1012 = and(_T_1010, _T_1011) @[el2_dec_dec_ctl.scala 139:92] + node _T_1013 = or(_T_1009, _T_1012) @[el2_dec_dec_ctl.scala 139:63] + node _T_1014 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1015 = eq(_T_1014, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1016 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1017 = eq(_T_1016, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1018 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1019 = and(_T_1015, _T_1017) @[el2_dec_dec_ctl.scala 140:37] + node _T_1020 = and(_T_1019, _T_1018) @[el2_dec_dec_ctl.scala 140:37] + node _T_1021 = or(_T_1013, _T_1020) @[el2_dec_dec_ctl.scala 139:96] + node _T_1022 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1023 = eq(_T_1022, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1024 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1025 = and(_T_1023, _T_1024) @[el2_dec_dec_ctl.scala 140:71] + node _T_1026 = or(_T_1021, _T_1025) @[el2_dec_dec_ctl.scala 140:41] + io.out.pm_alu <= _T_1026 @[el2_dec_dec_ctl.scala 139:17] + node _T_1027 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1028 = eq(_T_1027, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1029 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1030 = and(_T_1028, _T_1029) @[el2_dec_dec_ctl.scala 141:49] + node _T_1031 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1032 = eq(_T_1031, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1033 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1034 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1035 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1036 = and(_T_1032, _T_1033) @[el2_dec_dec_ctl.scala 141:88] + node _T_1037 = and(_T_1036, _T_1034) @[el2_dec_dec_ctl.scala 141:88] + node _T_1038 = and(_T_1037, _T_1035) @[el2_dec_dec_ctl.scala 141:88] + node _T_1039 = or(_T_1030, _T_1038) @[el2_dec_dec_ctl.scala 141:53] + node _T_1040 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1041 = eq(_T_1040, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1042 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1043 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1044 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1045 = and(_T_1041, _T_1042) @[el2_dec_dec_ctl.scala 142:38] + node _T_1046 = and(_T_1045, _T_1043) @[el2_dec_dec_ctl.scala 142:38] + node _T_1047 = and(_T_1046, _T_1044) @[el2_dec_dec_ctl.scala 142:38] + node _T_1048 = or(_T_1039, _T_1047) @[el2_dec_dec_ctl.scala 141:92] + node _T_1049 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1050 = eq(_T_1049, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1051 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1052 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1053 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1054 = and(_T_1050, _T_1051) @[el2_dec_dec_ctl.scala 142:77] + node _T_1055 = and(_T_1054, _T_1052) @[el2_dec_dec_ctl.scala 142:77] + node _T_1056 = and(_T_1055, _T_1053) @[el2_dec_dec_ctl.scala 142:77] + node _T_1057 = or(_T_1048, _T_1056) @[el2_dec_dec_ctl.scala 142:42] + node _T_1058 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1059 = eq(_T_1058, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1060 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1061 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1062 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1063 = and(_T_1059, _T_1060) @[el2_dec_dec_ctl.scala 143:38] + node _T_1064 = and(_T_1063, _T_1061) @[el2_dec_dec_ctl.scala 143:38] + node _T_1065 = and(_T_1064, _T_1062) @[el2_dec_dec_ctl.scala 143:38] + node _T_1066 = or(_T_1057, _T_1065) @[el2_dec_dec_ctl.scala 142:81] + node _T_1067 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1068 = eq(_T_1067, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1069 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1070 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1071 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1072 = and(_T_1068, _T_1069) @[el2_dec_dec_ctl.scala 143:78] + node _T_1073 = and(_T_1072, _T_1070) @[el2_dec_dec_ctl.scala 143:78] + node _T_1074 = and(_T_1073, _T_1071) @[el2_dec_dec_ctl.scala 143:78] + node _T_1075 = or(_T_1066, _T_1074) @[el2_dec_dec_ctl.scala 143:42] + node _T_1076 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1077 = eq(_T_1076, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1078 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1079 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1080 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1081 = and(_T_1077, _T_1078) @[el2_dec_dec_ctl.scala 144:39] + node _T_1082 = and(_T_1081, _T_1079) @[el2_dec_dec_ctl.scala 144:39] + node _T_1083 = and(_T_1082, _T_1080) @[el2_dec_dec_ctl.scala 144:39] + node _T_1084 = or(_T_1075, _T_1083) @[el2_dec_dec_ctl.scala 143:82] + node _T_1085 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1086 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1087 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1088 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1089 = and(_T_1085, _T_1086) @[el2_dec_dec_ctl.scala 144:78] + node _T_1090 = and(_T_1089, _T_1087) @[el2_dec_dec_ctl.scala 144:78] + node _T_1091 = and(_T_1090, _T_1088) @[el2_dec_dec_ctl.scala 144:78] + node _T_1092 = or(_T_1084, _T_1091) @[el2_dec_dec_ctl.scala 144:43] + node _T_1093 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1094 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1095 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1096 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1097 = and(_T_1093, _T_1094) @[el2_dec_dec_ctl.scala 145:38] + node _T_1098 = and(_T_1097, _T_1095) @[el2_dec_dec_ctl.scala 145:38] + node _T_1099 = and(_T_1098, _T_1096) @[el2_dec_dec_ctl.scala 145:38] + node _T_1100 = or(_T_1092, _T_1099) @[el2_dec_dec_ctl.scala 144:82] + node _T_1101 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1102 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1103 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1104 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1105 = and(_T_1101, _T_1102) @[el2_dec_dec_ctl.scala 145:77] + node _T_1106 = and(_T_1105, _T_1103) @[el2_dec_dec_ctl.scala 145:77] + node _T_1107 = and(_T_1106, _T_1104) @[el2_dec_dec_ctl.scala 145:77] + node _T_1108 = or(_T_1100, _T_1107) @[el2_dec_dec_ctl.scala 145:42] + node _T_1109 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1110 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1111 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1112 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1113 = and(_T_1109, _T_1110) @[el2_dec_dec_ctl.scala 146:38] + node _T_1114 = and(_T_1113, _T_1111) @[el2_dec_dec_ctl.scala 146:38] + node _T_1115 = and(_T_1114, _T_1112) @[el2_dec_dec_ctl.scala 146:38] + node _T_1116 = or(_T_1108, _T_1115) @[el2_dec_dec_ctl.scala 145:81] + node _T_1117 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1118 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1119 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1120 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1121 = and(_T_1117, _T_1118) @[el2_dec_dec_ctl.scala 146:77] + node _T_1122 = and(_T_1121, _T_1119) @[el2_dec_dec_ctl.scala 146:77] + node _T_1123 = and(_T_1122, _T_1120) @[el2_dec_dec_ctl.scala 146:77] + node _T_1124 = or(_T_1116, _T_1123) @[el2_dec_dec_ctl.scala 146:42] + io.out.presync <= _T_1124 @[el2_dec_dec_ctl.scala 141:18] + node _T_1125 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1126 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1127 = eq(_T_1126, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1128 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1129 = and(_T_1125, _T_1127) @[el2_dec_dec_ctl.scala 147:53] + node _T_1130 = and(_T_1129, _T_1128) @[el2_dec_dec_ctl.scala 147:53] + node _T_1131 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1132 = eq(_T_1131, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1133 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1134 = eq(_T_1133, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1135 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1136 = eq(_T_1135, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1137 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1138 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1139 = and(_T_1132, _T_1134) @[el2_dec_dec_ctl.scala 147:98] + node _T_1140 = and(_T_1139, _T_1136) @[el2_dec_dec_ctl.scala 147:98] + node _T_1141 = and(_T_1140, _T_1137) @[el2_dec_dec_ctl.scala 147:98] + node _T_1142 = and(_T_1141, _T_1138) @[el2_dec_dec_ctl.scala 147:98] + node _T_1143 = or(_T_1130, _T_1142) @[el2_dec_dec_ctl.scala 147:57] + node _T_1144 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1145 = eq(_T_1144, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1146 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:33] + node _T_1147 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1148 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1149 = and(_T_1145, _T_1146) @[el2_dec_dec_ctl.scala 148:38] + node _T_1150 = and(_T_1149, _T_1147) @[el2_dec_dec_ctl.scala 148:38] + node _T_1151 = and(_T_1150, _T_1148) @[el2_dec_dec_ctl.scala 148:38] + node _T_1152 = or(_T_1143, _T_1151) @[el2_dec_dec_ctl.scala 147:102] + node _T_1153 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1154 = eq(_T_1153, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1155 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:33] + node _T_1156 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1157 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1158 = and(_T_1154, _T_1155) @[el2_dec_dec_ctl.scala 148:77] + node _T_1159 = and(_T_1158, _T_1156) @[el2_dec_dec_ctl.scala 148:77] + node _T_1160 = and(_T_1159, _T_1157) @[el2_dec_dec_ctl.scala 148:77] + node _T_1161 = or(_T_1152, _T_1160) @[el2_dec_dec_ctl.scala 148:42] + node _T_1162 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1163 = eq(_T_1162, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1164 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:33] + node _T_1165 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1166 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1167 = and(_T_1163, _T_1164) @[el2_dec_dec_ctl.scala 149:38] + node _T_1168 = and(_T_1167, _T_1165) @[el2_dec_dec_ctl.scala 149:38] + node _T_1169 = and(_T_1168, _T_1166) @[el2_dec_dec_ctl.scala 149:38] + node _T_1170 = or(_T_1161, _T_1169) @[el2_dec_dec_ctl.scala 148:81] + node _T_1171 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1172 = eq(_T_1171, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1173 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:33] + node _T_1174 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1175 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1176 = and(_T_1172, _T_1173) @[el2_dec_dec_ctl.scala 149:78] + node _T_1177 = and(_T_1176, _T_1174) @[el2_dec_dec_ctl.scala 149:78] + node _T_1178 = and(_T_1177, _T_1175) @[el2_dec_dec_ctl.scala 149:78] + node _T_1179 = or(_T_1170, _T_1178) @[el2_dec_dec_ctl.scala 149:42] + node _T_1180 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1181 = eq(_T_1180, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1182 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:33] + node _T_1183 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1184 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1185 = and(_T_1181, _T_1182) @[el2_dec_dec_ctl.scala 150:39] + node _T_1186 = and(_T_1185, _T_1183) @[el2_dec_dec_ctl.scala 150:39] + node _T_1187 = and(_T_1186, _T_1184) @[el2_dec_dec_ctl.scala 150:39] + node _T_1188 = or(_T_1179, _T_1187) @[el2_dec_dec_ctl.scala 149:82] + node _T_1189 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:33] + node _T_1190 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1191 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1192 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1193 = and(_T_1189, _T_1190) @[el2_dec_dec_ctl.scala 150:78] + node _T_1194 = and(_T_1193, _T_1191) @[el2_dec_dec_ctl.scala 150:78] + node _T_1195 = and(_T_1194, _T_1192) @[el2_dec_dec_ctl.scala 150:78] + node _T_1196 = or(_T_1188, _T_1195) @[el2_dec_dec_ctl.scala 150:43] + node _T_1197 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:33] + node _T_1198 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1199 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1200 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1201 = and(_T_1197, _T_1198) @[el2_dec_dec_ctl.scala 151:38] + node _T_1202 = and(_T_1201, _T_1199) @[el2_dec_dec_ctl.scala 151:38] + node _T_1203 = and(_T_1202, _T_1200) @[el2_dec_dec_ctl.scala 151:38] + node _T_1204 = or(_T_1196, _T_1203) @[el2_dec_dec_ctl.scala 150:82] + node _T_1205 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:33] + node _T_1206 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1207 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1208 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1209 = and(_T_1205, _T_1206) @[el2_dec_dec_ctl.scala 151:77] + node _T_1210 = and(_T_1209, _T_1207) @[el2_dec_dec_ctl.scala 151:77] + node _T_1211 = and(_T_1210, _T_1208) @[el2_dec_dec_ctl.scala 151:77] + node _T_1212 = or(_T_1204, _T_1211) @[el2_dec_dec_ctl.scala 151:42] + node _T_1213 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:33] + node _T_1214 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1215 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1216 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1217 = and(_T_1213, _T_1214) @[el2_dec_dec_ctl.scala 152:38] + node _T_1218 = and(_T_1217, _T_1215) @[el2_dec_dec_ctl.scala 152:38] + node _T_1219 = and(_T_1218, _T_1216) @[el2_dec_dec_ctl.scala 152:38] + node _T_1220 = or(_T_1212, _T_1219) @[el2_dec_dec_ctl.scala 151:81] + node _T_1221 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:33] + node _T_1222 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1223 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1224 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1225 = and(_T_1221, _T_1222) @[el2_dec_dec_ctl.scala 152:77] + node _T_1226 = and(_T_1225, _T_1223) @[el2_dec_dec_ctl.scala 152:77] + node _T_1227 = and(_T_1226, _T_1224) @[el2_dec_dec_ctl.scala 152:77] + node _T_1228 = or(_T_1220, _T_1227) @[el2_dec_dec_ctl.scala 152:42] + io.out.postsync <= _T_1228 @[el2_dec_dec_ctl.scala 147:19] + node _T_1229 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1230 = eq(_T_1229, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1231 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1232 = eq(_T_1231, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1233 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:33] + node _T_1234 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1235 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1236 = eq(_T_1235, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1237 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1238 = eq(_T_1237, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1239 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1240 = eq(_T_1239, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1241 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1242 = eq(_T_1241, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1243 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1244 = eq(_T_1243, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1245 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1246 = eq(_T_1245, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1247 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:33] + node _T_1248 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1249 = eq(_T_1248, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1250 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1251 = eq(_T_1250, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1252 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1253 = eq(_T_1252, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1254 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1255 = eq(_T_1254, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1256 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1257 = eq(_T_1256, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1258 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1259 = eq(_T_1258, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1260 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1261 = eq(_T_1260, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1262 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1263 = eq(_T_1262, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1264 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1265 = eq(_T_1264, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1266 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1267 = eq(_T_1266, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1268 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1269 = eq(_T_1268, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1270 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1271 = eq(_T_1270, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1272 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1273 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1274 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1275 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1276 = eq(_T_1275, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1277 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1278 = eq(_T_1277, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1279 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1280 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1281 = eq(_T_1280, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1282 = and(_T_1230, _T_1232) @[el2_dec_dec_ctl.scala 153:144] + node _T_1283 = and(_T_1282, _T_1233) @[el2_dec_dec_ctl.scala 153:144] + node _T_1284 = and(_T_1283, _T_1234) @[el2_dec_dec_ctl.scala 153:144] + node _T_1285 = and(_T_1284, _T_1236) @[el2_dec_dec_ctl.scala 153:144] + node _T_1286 = and(_T_1285, _T_1238) @[el2_dec_dec_ctl.scala 153:144] + node _T_1287 = and(_T_1286, _T_1240) @[el2_dec_dec_ctl.scala 153:144] + node _T_1288 = and(_T_1287, _T_1242) @[el2_dec_dec_ctl.scala 153:144] + node _T_1289 = and(_T_1288, _T_1244) @[el2_dec_dec_ctl.scala 153:144] + node _T_1290 = and(_T_1289, _T_1246) @[el2_dec_dec_ctl.scala 153:144] + node _T_1291 = and(_T_1290, _T_1247) @[el2_dec_dec_ctl.scala 153:144] + node _T_1292 = and(_T_1291, _T_1249) @[el2_dec_dec_ctl.scala 153:144] + node _T_1293 = and(_T_1292, _T_1251) @[el2_dec_dec_ctl.scala 153:144] + node _T_1294 = and(_T_1293, _T_1253) @[el2_dec_dec_ctl.scala 153:144] + node _T_1295 = and(_T_1294, _T_1255) @[el2_dec_dec_ctl.scala 153:144] + node _T_1296 = and(_T_1295, _T_1257) @[el2_dec_dec_ctl.scala 153:144] + node _T_1297 = and(_T_1296, _T_1259) @[el2_dec_dec_ctl.scala 153:144] + node _T_1298 = and(_T_1297, _T_1261) @[el2_dec_dec_ctl.scala 153:144] + node _T_1299 = and(_T_1298, _T_1263) @[el2_dec_dec_ctl.scala 153:144] + node _T_1300 = and(_T_1299, _T_1265) @[el2_dec_dec_ctl.scala 153:144] + node _T_1301 = and(_T_1300, _T_1267) @[el2_dec_dec_ctl.scala 153:144] + node _T_1302 = and(_T_1301, _T_1269) @[el2_dec_dec_ctl.scala 153:144] + node _T_1303 = and(_T_1302, _T_1271) @[el2_dec_dec_ctl.scala 153:144] + node _T_1304 = and(_T_1303, _T_1272) @[el2_dec_dec_ctl.scala 153:144] + node _T_1305 = and(_T_1304, _T_1273) @[el2_dec_dec_ctl.scala 153:144] + node _T_1306 = and(_T_1305, _T_1274) @[el2_dec_dec_ctl.scala 153:144] + node _T_1307 = and(_T_1306, _T_1276) @[el2_dec_dec_ctl.scala 153:144] + node _T_1308 = and(_T_1307, _T_1278) @[el2_dec_dec_ctl.scala 153:144] + node _T_1309 = and(_T_1308, _T_1279) @[el2_dec_dec_ctl.scala 153:144] + node _T_1310 = and(_T_1309, _T_1281) @[el2_dec_dec_ctl.scala 153:144] + node _T_1311 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1312 = eq(_T_1311, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1313 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1315 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1316 = eq(_T_1315, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1317 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:33] + node _T_1318 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1319 = eq(_T_1318, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1320 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1321 = eq(_T_1320, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1322 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1323 = eq(_T_1322, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1324 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1326 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1327 = eq(_T_1326, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1328 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:33] + node _T_1329 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1330 = eq(_T_1329, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1331 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:33] + node _T_1332 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1333 = eq(_T_1332, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1334 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1335 = eq(_T_1334, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1336 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1337 = eq(_T_1336, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1338 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1339 = eq(_T_1338, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1340 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1341 = eq(_T_1340, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1342 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1343 = eq(_T_1342, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1344 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1345 = eq(_T_1344, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1346 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1347 = eq(_T_1346, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1348 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1349 = eq(_T_1348, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1350 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1351 = eq(_T_1350, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1352 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1354 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1355 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1356 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1357 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1358 = eq(_T_1357, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1359 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1360 = eq(_T_1359, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1361 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1362 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1363 = eq(_T_1362, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1364 = and(_T_1312, _T_1314) @[el2_dec_dec_ctl.scala 154:130] + node _T_1365 = and(_T_1364, _T_1316) @[el2_dec_dec_ctl.scala 154:130] + node _T_1366 = and(_T_1365, _T_1317) @[el2_dec_dec_ctl.scala 154:130] + node _T_1367 = and(_T_1366, _T_1319) @[el2_dec_dec_ctl.scala 154:130] + node _T_1368 = and(_T_1367, _T_1321) @[el2_dec_dec_ctl.scala 154:130] + node _T_1369 = and(_T_1368, _T_1323) @[el2_dec_dec_ctl.scala 154:130] + node _T_1370 = and(_T_1369, _T_1325) @[el2_dec_dec_ctl.scala 154:130] + node _T_1371 = and(_T_1370, _T_1327) @[el2_dec_dec_ctl.scala 154:130] + node _T_1372 = and(_T_1371, _T_1328) @[el2_dec_dec_ctl.scala 154:130] + node _T_1373 = and(_T_1372, _T_1330) @[el2_dec_dec_ctl.scala 154:130] + node _T_1374 = and(_T_1373, _T_1331) @[el2_dec_dec_ctl.scala 154:130] + node _T_1375 = and(_T_1374, _T_1333) @[el2_dec_dec_ctl.scala 154:130] + node _T_1376 = and(_T_1375, _T_1335) @[el2_dec_dec_ctl.scala 154:130] + node _T_1377 = and(_T_1376, _T_1337) @[el2_dec_dec_ctl.scala 154:130] + node _T_1378 = and(_T_1377, _T_1339) @[el2_dec_dec_ctl.scala 154:130] + node _T_1379 = and(_T_1378, _T_1341) @[el2_dec_dec_ctl.scala 154:130] + node _T_1380 = and(_T_1379, _T_1343) @[el2_dec_dec_ctl.scala 154:130] + node _T_1381 = and(_T_1380, _T_1345) @[el2_dec_dec_ctl.scala 154:130] + node _T_1382 = and(_T_1381, _T_1347) @[el2_dec_dec_ctl.scala 154:130] + node _T_1383 = and(_T_1382, _T_1349) @[el2_dec_dec_ctl.scala 154:130] + node _T_1384 = and(_T_1383, _T_1351) @[el2_dec_dec_ctl.scala 154:130] + node _T_1385 = and(_T_1384, _T_1353) @[el2_dec_dec_ctl.scala 154:130] + node _T_1386 = and(_T_1385, _T_1354) @[el2_dec_dec_ctl.scala 154:130] + node _T_1387 = and(_T_1386, _T_1355) @[el2_dec_dec_ctl.scala 154:130] + node _T_1388 = and(_T_1387, _T_1356) @[el2_dec_dec_ctl.scala 154:130] + node _T_1389 = and(_T_1388, _T_1358) @[el2_dec_dec_ctl.scala 154:130] + node _T_1390 = and(_T_1389, _T_1360) @[el2_dec_dec_ctl.scala 154:130] + node _T_1391 = and(_T_1390, _T_1361) @[el2_dec_dec_ctl.scala 154:130] + node _T_1392 = and(_T_1391, _T_1363) @[el2_dec_dec_ctl.scala 154:130] + node _T_1393 = or(_T_1310, _T_1392) @[el2_dec_dec_ctl.scala 153:148] + node _T_1394 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1395 = eq(_T_1394, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1396 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1397 = eq(_T_1396, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1398 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1399 = eq(_T_1398, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1400 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1401 = eq(_T_1400, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1402 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1403 = eq(_T_1402, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1404 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1405 = eq(_T_1404, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1406 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1407 = eq(_T_1406, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1408 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1409 = eq(_T_1408, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1410 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1411 = eq(_T_1410, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1412 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1413 = eq(_T_1412, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1414 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1415 = eq(_T_1414, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1416 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1417 = eq(_T_1416, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1418 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1420 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1421 = eq(_T_1420, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1422 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1423 = eq(_T_1422, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1424 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1425 = eq(_T_1424, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1426 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1428 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1429 = eq(_T_1428, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1430 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1431 = eq(_T_1430, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1432 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1433 = eq(_T_1432, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1434 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1435 = eq(_T_1434, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1436 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1437 = eq(_T_1436, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1438 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1439 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1440 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1442 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1443 = eq(_T_1442, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1444 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1445 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1447 = and(_T_1395, _T_1397) @[el2_dec_dec_ctl.scala 155:127] + node _T_1448 = and(_T_1447, _T_1399) @[el2_dec_dec_ctl.scala 155:127] + node _T_1449 = and(_T_1448, _T_1401) @[el2_dec_dec_ctl.scala 155:127] + node _T_1450 = and(_T_1449, _T_1403) @[el2_dec_dec_ctl.scala 155:127] + node _T_1451 = and(_T_1450, _T_1405) @[el2_dec_dec_ctl.scala 155:127] + node _T_1452 = and(_T_1451, _T_1407) @[el2_dec_dec_ctl.scala 155:127] + node _T_1453 = and(_T_1452, _T_1409) @[el2_dec_dec_ctl.scala 155:127] + node _T_1454 = and(_T_1453, _T_1411) @[el2_dec_dec_ctl.scala 155:127] + node _T_1455 = and(_T_1454, _T_1413) @[el2_dec_dec_ctl.scala 155:127] + node _T_1456 = and(_T_1455, _T_1415) @[el2_dec_dec_ctl.scala 155:127] + node _T_1457 = and(_T_1456, _T_1417) @[el2_dec_dec_ctl.scala 155:127] + node _T_1458 = and(_T_1457, _T_1419) @[el2_dec_dec_ctl.scala 155:127] + node _T_1459 = and(_T_1458, _T_1421) @[el2_dec_dec_ctl.scala 155:127] + node _T_1460 = and(_T_1459, _T_1423) @[el2_dec_dec_ctl.scala 155:127] + node _T_1461 = and(_T_1460, _T_1425) @[el2_dec_dec_ctl.scala 155:127] + node _T_1462 = and(_T_1461, _T_1427) @[el2_dec_dec_ctl.scala 155:127] + node _T_1463 = and(_T_1462, _T_1429) @[el2_dec_dec_ctl.scala 155:127] + node _T_1464 = and(_T_1463, _T_1431) @[el2_dec_dec_ctl.scala 155:127] + node _T_1465 = and(_T_1464, _T_1433) @[el2_dec_dec_ctl.scala 155:127] + node _T_1466 = and(_T_1465, _T_1435) @[el2_dec_dec_ctl.scala 155:127] + node _T_1467 = and(_T_1466, _T_1437) @[el2_dec_dec_ctl.scala 155:127] + node _T_1468 = and(_T_1467, _T_1438) @[el2_dec_dec_ctl.scala 155:127] + node _T_1469 = and(_T_1468, _T_1439) @[el2_dec_dec_ctl.scala 155:127] + node _T_1470 = and(_T_1469, _T_1441) @[el2_dec_dec_ctl.scala 155:127] + node _T_1471 = and(_T_1470, _T_1443) @[el2_dec_dec_ctl.scala 155:127] + node _T_1472 = and(_T_1471, _T_1444) @[el2_dec_dec_ctl.scala 155:127] + node _T_1473 = and(_T_1472, _T_1446) @[el2_dec_dec_ctl.scala 155:127] + node _T_1474 = or(_T_1393, _T_1473) @[el2_dec_dec_ctl.scala 154:134] + node _T_1475 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1476 = eq(_T_1475, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1477 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1478 = eq(_T_1477, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1479 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1480 = eq(_T_1479, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1481 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1483 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1484 = eq(_T_1483, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1485 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1486 = eq(_T_1485, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1487 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1488 = eq(_T_1487, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1489 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1491 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1492 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1494 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1495 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1497 = and(_T_1476, _T_1478) @[el2_dec_dec_ctl.scala 156:68] + node _T_1498 = and(_T_1497, _T_1480) @[el2_dec_dec_ctl.scala 156:68] + node _T_1499 = and(_T_1498, _T_1482) @[el2_dec_dec_ctl.scala 156:68] + node _T_1500 = and(_T_1499, _T_1484) @[el2_dec_dec_ctl.scala 156:68] + node _T_1501 = and(_T_1500, _T_1486) @[el2_dec_dec_ctl.scala 156:68] + node _T_1502 = and(_T_1501, _T_1488) @[el2_dec_dec_ctl.scala 156:68] + node _T_1503 = and(_T_1502, _T_1490) @[el2_dec_dec_ctl.scala 156:68] + node _T_1504 = and(_T_1503, _T_1491) @[el2_dec_dec_ctl.scala 156:68] + node _T_1505 = and(_T_1504, _T_1493) @[el2_dec_dec_ctl.scala 156:68] + node _T_1506 = and(_T_1505, _T_1494) @[el2_dec_dec_ctl.scala 156:68] + node _T_1507 = and(_T_1506, _T_1496) @[el2_dec_dec_ctl.scala 156:68] + node _T_1508 = or(_T_1474, _T_1507) @[el2_dec_dec_ctl.scala 155:131] + node _T_1509 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1510 = eq(_T_1509, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1511 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1513 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1514 = eq(_T_1513, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1515 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1516 = eq(_T_1515, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1517 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1518 = eq(_T_1517, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1519 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1520 = eq(_T_1519, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1521 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1522 = eq(_T_1521, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1523 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1525 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1526 = eq(_T_1525, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1527 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1529 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1530 = eq(_T_1529, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1531 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1532 = eq(_T_1531, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1533 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1534 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1535 = eq(_T_1534, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1536 = and(_T_1510, _T_1512) @[el2_dec_dec_ctl.scala 157:77] + node _T_1537 = and(_T_1536, _T_1514) @[el2_dec_dec_ctl.scala 157:77] + node _T_1538 = and(_T_1537, _T_1516) @[el2_dec_dec_ctl.scala 157:77] + node _T_1539 = and(_T_1538, _T_1518) @[el2_dec_dec_ctl.scala 157:77] + node _T_1540 = and(_T_1539, _T_1520) @[el2_dec_dec_ctl.scala 157:77] + node _T_1541 = and(_T_1540, _T_1522) @[el2_dec_dec_ctl.scala 157:77] + node _T_1542 = and(_T_1541, _T_1524) @[el2_dec_dec_ctl.scala 157:77] + node _T_1543 = and(_T_1542, _T_1526) @[el2_dec_dec_ctl.scala 157:77] + node _T_1544 = and(_T_1543, _T_1528) @[el2_dec_dec_ctl.scala 157:77] + node _T_1545 = and(_T_1544, _T_1530) @[el2_dec_dec_ctl.scala 157:77] + node _T_1546 = and(_T_1545, _T_1532) @[el2_dec_dec_ctl.scala 157:77] + node _T_1547 = and(_T_1546, _T_1533) @[el2_dec_dec_ctl.scala 157:77] + node _T_1548 = and(_T_1547, _T_1535) @[el2_dec_dec_ctl.scala 157:77] + node _T_1549 = or(_T_1508, _T_1548) @[el2_dec_dec_ctl.scala 156:72] + node _T_1550 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1552 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1553 = eq(_T_1552, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1554 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1555 = eq(_T_1554, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1556 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1557 = eq(_T_1556, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1558 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1559 = eq(_T_1558, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1560 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1561 = eq(_T_1560, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1562 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1563 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1564 = eq(_T_1563, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1565 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1566 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1567 = eq(_T_1566, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1568 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1569 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1570 = eq(_T_1569, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1571 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1572 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1573 = eq(_T_1572, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1574 = and(_T_1551, _T_1553) @[el2_dec_dec_ctl.scala 158:74] + node _T_1575 = and(_T_1574, _T_1555) @[el2_dec_dec_ctl.scala 158:74] + node _T_1576 = and(_T_1575, _T_1557) @[el2_dec_dec_ctl.scala 158:74] + node _T_1577 = and(_T_1576, _T_1559) @[el2_dec_dec_ctl.scala 158:74] + node _T_1578 = and(_T_1577, _T_1561) @[el2_dec_dec_ctl.scala 158:74] + node _T_1579 = and(_T_1578, _T_1562) @[el2_dec_dec_ctl.scala 158:74] + node _T_1580 = and(_T_1579, _T_1564) @[el2_dec_dec_ctl.scala 158:74] + node _T_1581 = and(_T_1580, _T_1565) @[el2_dec_dec_ctl.scala 158:74] + node _T_1582 = and(_T_1581, _T_1567) @[el2_dec_dec_ctl.scala 158:74] + node _T_1583 = and(_T_1582, _T_1568) @[el2_dec_dec_ctl.scala 158:74] + node _T_1584 = and(_T_1583, _T_1570) @[el2_dec_dec_ctl.scala 158:74] + node _T_1585 = and(_T_1584, _T_1571) @[el2_dec_dec_ctl.scala 158:74] + node _T_1586 = and(_T_1585, _T_1573) @[el2_dec_dec_ctl.scala 158:74] + node _T_1587 = or(_T_1549, _T_1586) @[el2_dec_dec_ctl.scala 157:81] + node _T_1588 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1589 = eq(_T_1588, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1590 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1591 = eq(_T_1590, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1592 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1593 = eq(_T_1592, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1594 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1595 = eq(_T_1594, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1596 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1597 = eq(_T_1596, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1598 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1599 = eq(_T_1598, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1600 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1601 = eq(_T_1600, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1602 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1603 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1604 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1605 = eq(_T_1604, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1606 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1607 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1609 = and(_T_1589, _T_1591) @[el2_dec_dec_ctl.scala 159:66] + node _T_1610 = and(_T_1609, _T_1593) @[el2_dec_dec_ctl.scala 159:66] + node _T_1611 = and(_T_1610, _T_1595) @[el2_dec_dec_ctl.scala 159:66] + node _T_1612 = and(_T_1611, _T_1597) @[el2_dec_dec_ctl.scala 159:66] + node _T_1613 = and(_T_1612, _T_1599) @[el2_dec_dec_ctl.scala 159:66] + node _T_1614 = and(_T_1613, _T_1601) @[el2_dec_dec_ctl.scala 159:66] + node _T_1615 = and(_T_1614, _T_1602) @[el2_dec_dec_ctl.scala 159:66] + node _T_1616 = and(_T_1615, _T_1603) @[el2_dec_dec_ctl.scala 159:66] + node _T_1617 = and(_T_1616, _T_1605) @[el2_dec_dec_ctl.scala 159:66] + node _T_1618 = and(_T_1617, _T_1606) @[el2_dec_dec_ctl.scala 159:66] + node _T_1619 = and(_T_1618, _T_1608) @[el2_dec_dec_ctl.scala 159:66] + node _T_1620 = or(_T_1587, _T_1619) @[el2_dec_dec_ctl.scala 158:78] + node _T_1621 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1622 = eq(_T_1621, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1623 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1624 = eq(_T_1623, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1625 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1626 = eq(_T_1625, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1627 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1628 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1629 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1630 = eq(_T_1629, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1631 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1632 = eq(_T_1631, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1633 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1634 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1635 = eq(_T_1634, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1636 = and(_T_1622, _T_1624) @[el2_dec_dec_ctl.scala 160:54] + node _T_1637 = and(_T_1636, _T_1626) @[el2_dec_dec_ctl.scala 160:54] + node _T_1638 = and(_T_1637, _T_1627) @[el2_dec_dec_ctl.scala 160:54] + node _T_1639 = and(_T_1638, _T_1628) @[el2_dec_dec_ctl.scala 160:54] + node _T_1640 = and(_T_1639, _T_1630) @[el2_dec_dec_ctl.scala 160:54] + node _T_1641 = and(_T_1640, _T_1632) @[el2_dec_dec_ctl.scala 160:54] + node _T_1642 = and(_T_1641, _T_1633) @[el2_dec_dec_ctl.scala 160:54] + node _T_1643 = and(_T_1642, _T_1635) @[el2_dec_dec_ctl.scala 160:54] + node _T_1644 = or(_T_1620, _T_1643) @[el2_dec_dec_ctl.scala 159:70] + node _T_1645 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:33] + node _T_1646 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1647 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1648 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1649 = eq(_T_1648, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1650 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1651 = eq(_T_1650, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1652 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1653 = eq(_T_1652, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1654 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1655 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1656 = eq(_T_1655, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1657 = and(_T_1645, _T_1646) @[el2_dec_dec_ctl.scala 161:48] + node _T_1658 = and(_T_1657, _T_1647) @[el2_dec_dec_ctl.scala 161:48] + node _T_1659 = and(_T_1658, _T_1649) @[el2_dec_dec_ctl.scala 161:48] + node _T_1660 = and(_T_1659, _T_1651) @[el2_dec_dec_ctl.scala 161:48] + node _T_1661 = and(_T_1660, _T_1653) @[el2_dec_dec_ctl.scala 161:48] + node _T_1662 = and(_T_1661, _T_1654) @[el2_dec_dec_ctl.scala 161:48] + node _T_1663 = and(_T_1662, _T_1656) @[el2_dec_dec_ctl.scala 161:48] + node _T_1664 = or(_T_1644, _T_1663) @[el2_dec_dec_ctl.scala 160:58] + node _T_1665 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1666 = eq(_T_1665, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1667 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1668 = eq(_T_1667, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1669 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1670 = eq(_T_1669, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1671 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1672 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1673 = eq(_T_1672, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1674 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1675 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1677 = and(_T_1666, _T_1668) @[el2_dec_dec_ctl.scala 162:47] + node _T_1678 = and(_T_1677, _T_1670) @[el2_dec_dec_ctl.scala 162:47] + node _T_1679 = and(_T_1678, _T_1671) @[el2_dec_dec_ctl.scala 162:47] + node _T_1680 = and(_T_1679, _T_1673) @[el2_dec_dec_ctl.scala 162:47] + node _T_1681 = and(_T_1680, _T_1674) @[el2_dec_dec_ctl.scala 162:47] + node _T_1682 = and(_T_1681, _T_1676) @[el2_dec_dec_ctl.scala 162:47] + node _T_1683 = or(_T_1664, _T_1682) @[el2_dec_dec_ctl.scala 161:52] + node _T_1684 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1685 = eq(_T_1684, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1686 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1688 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1689 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1690 = eq(_T_1689, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1691 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1693 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1695 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1696 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1697 = eq(_T_1696, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1698 = and(_T_1685, _T_1687) @[el2_dec_dec_ctl.scala 162:99] + node _T_1699 = and(_T_1698, _T_1688) @[el2_dec_dec_ctl.scala 162:99] + node _T_1700 = and(_T_1699, _T_1690) @[el2_dec_dec_ctl.scala 162:99] + node _T_1701 = and(_T_1700, _T_1692) @[el2_dec_dec_ctl.scala 162:99] + node _T_1702 = and(_T_1701, _T_1694) @[el2_dec_dec_ctl.scala 162:99] + node _T_1703 = and(_T_1702, _T_1695) @[el2_dec_dec_ctl.scala 162:99] + node _T_1704 = and(_T_1703, _T_1697) @[el2_dec_dec_ctl.scala 162:99] + node _T_1705 = or(_T_1683, _T_1704) @[el2_dec_dec_ctl.scala 162:51] + node _T_1706 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:33] + node _T_1707 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1708 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1709 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1710 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1711 = eq(_T_1710, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1712 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1713 = eq(_T_1712, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1714 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1715 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1716 = eq(_T_1715, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1717 = and(_T_1706, _T_1707) @[el2_dec_dec_ctl.scala 163:47] + node _T_1718 = and(_T_1717, _T_1708) @[el2_dec_dec_ctl.scala 163:47] + node _T_1719 = and(_T_1718, _T_1709) @[el2_dec_dec_ctl.scala 163:47] + node _T_1720 = and(_T_1719, _T_1711) @[el2_dec_dec_ctl.scala 163:47] + node _T_1721 = and(_T_1720, _T_1713) @[el2_dec_dec_ctl.scala 163:47] + node _T_1722 = and(_T_1721, _T_1714) @[el2_dec_dec_ctl.scala 163:47] + node _T_1723 = and(_T_1722, _T_1716) @[el2_dec_dec_ctl.scala 163:47] + node _T_1724 = or(_T_1705, _T_1723) @[el2_dec_dec_ctl.scala 162:103] + node _T_1725 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1727 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1729 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1730 = eq(_T_1729, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1731 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1732 = eq(_T_1731, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1733 = bits(io.ins, 27, 27) @[el2_dec_dec_ctl.scala 67:52] + node _T_1734 = eq(_T_1733, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1735 = bits(io.ins, 26, 26) @[el2_dec_dec_ctl.scala 67:52] + node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1737 = bits(io.ins, 25, 25) @[el2_dec_dec_ctl.scala 67:52] + node _T_1738 = eq(_T_1737, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1739 = bits(io.ins, 24, 24) @[el2_dec_dec_ctl.scala 67:52] + node _T_1740 = eq(_T_1739, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1741 = bits(io.ins, 23, 23) @[el2_dec_dec_ctl.scala 67:52] + node _T_1742 = eq(_T_1741, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1743 = bits(io.ins, 22, 22) @[el2_dec_dec_ctl.scala 67:52] + node _T_1744 = eq(_T_1743, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1745 = bits(io.ins, 21, 21) @[el2_dec_dec_ctl.scala 67:52] + node _T_1746 = eq(_T_1745, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1747 = bits(io.ins, 20, 20) @[el2_dec_dec_ctl.scala 67:52] + node _T_1748 = eq(_T_1747, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1749 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1750 = eq(_T_1749, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1751 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1752 = eq(_T_1751, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1753 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1754 = eq(_T_1753, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1755 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1756 = eq(_T_1755, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1757 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1758 = eq(_T_1757, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1759 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1761 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1762 = eq(_T_1761, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1763 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1764 = eq(_T_1763, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1765 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1767 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1768 = eq(_T_1767, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1769 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1770 = eq(_T_1769, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1771 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1773 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1774 = eq(_T_1773, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1775 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1777 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1778 = eq(_T_1777, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1779 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1780 = eq(_T_1779, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1781 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1782 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1783 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1784 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1785 = eq(_T_1784, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1786 = and(_T_1726, _T_1728) @[el2_dec_dec_ctl.scala 164:142] + node _T_1787 = and(_T_1786, _T_1730) @[el2_dec_dec_ctl.scala 164:142] + node _T_1788 = and(_T_1787, _T_1732) @[el2_dec_dec_ctl.scala 164:142] + node _T_1789 = and(_T_1788, _T_1734) @[el2_dec_dec_ctl.scala 164:142] + node _T_1790 = and(_T_1789, _T_1736) @[el2_dec_dec_ctl.scala 164:142] + node _T_1791 = and(_T_1790, _T_1738) @[el2_dec_dec_ctl.scala 164:142] + node _T_1792 = and(_T_1791, _T_1740) @[el2_dec_dec_ctl.scala 164:142] + node _T_1793 = and(_T_1792, _T_1742) @[el2_dec_dec_ctl.scala 164:142] + node _T_1794 = and(_T_1793, _T_1744) @[el2_dec_dec_ctl.scala 164:142] + node _T_1795 = and(_T_1794, _T_1746) @[el2_dec_dec_ctl.scala 164:142] + node _T_1796 = and(_T_1795, _T_1748) @[el2_dec_dec_ctl.scala 164:142] + node _T_1797 = and(_T_1796, _T_1750) @[el2_dec_dec_ctl.scala 164:142] + node _T_1798 = and(_T_1797, _T_1752) @[el2_dec_dec_ctl.scala 164:142] + node _T_1799 = and(_T_1798, _T_1754) @[el2_dec_dec_ctl.scala 164:142] + node _T_1800 = and(_T_1799, _T_1756) @[el2_dec_dec_ctl.scala 164:142] + node _T_1801 = and(_T_1800, _T_1758) @[el2_dec_dec_ctl.scala 164:142] + node _T_1802 = and(_T_1801, _T_1760) @[el2_dec_dec_ctl.scala 164:142] + node _T_1803 = and(_T_1802, _T_1762) @[el2_dec_dec_ctl.scala 164:142] + node _T_1804 = and(_T_1803, _T_1764) @[el2_dec_dec_ctl.scala 164:142] + node _T_1805 = and(_T_1804, _T_1766) @[el2_dec_dec_ctl.scala 164:142] + node _T_1806 = and(_T_1805, _T_1768) @[el2_dec_dec_ctl.scala 164:142] + node _T_1807 = and(_T_1806, _T_1770) @[el2_dec_dec_ctl.scala 164:142] + node _T_1808 = and(_T_1807, _T_1772) @[el2_dec_dec_ctl.scala 164:142] + node _T_1809 = and(_T_1808, _T_1774) @[el2_dec_dec_ctl.scala 164:142] + node _T_1810 = and(_T_1809, _T_1776) @[el2_dec_dec_ctl.scala 164:142] + node _T_1811 = and(_T_1810, _T_1778) @[el2_dec_dec_ctl.scala 164:142] + node _T_1812 = and(_T_1811, _T_1780) @[el2_dec_dec_ctl.scala 164:142] + node _T_1813 = and(_T_1812, _T_1781) @[el2_dec_dec_ctl.scala 164:142] + node _T_1814 = and(_T_1813, _T_1782) @[el2_dec_dec_ctl.scala 164:142] + node _T_1815 = and(_T_1814, _T_1783) @[el2_dec_dec_ctl.scala 164:142] + node _T_1816 = and(_T_1815, _T_1785) @[el2_dec_dec_ctl.scala 164:142] + node _T_1817 = or(_T_1724, _T_1816) @[el2_dec_dec_ctl.scala 163:51] + node _T_1818 = bits(io.ins, 31, 31) @[el2_dec_dec_ctl.scala 67:52] + node _T_1819 = eq(_T_1818, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1820 = bits(io.ins, 30, 30) @[el2_dec_dec_ctl.scala 67:52] + node _T_1821 = eq(_T_1820, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1822 = bits(io.ins, 29, 29) @[el2_dec_dec_ctl.scala 67:52] + node _T_1823 = eq(_T_1822, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1824 = bits(io.ins, 28, 28) @[el2_dec_dec_ctl.scala 67:52] + node _T_1825 = eq(_T_1824, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1826 = bits(io.ins, 19, 19) @[el2_dec_dec_ctl.scala 67:52] + node _T_1827 = eq(_T_1826, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1828 = bits(io.ins, 18, 18) @[el2_dec_dec_ctl.scala 67:52] + node _T_1829 = eq(_T_1828, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1830 = bits(io.ins, 17, 17) @[el2_dec_dec_ctl.scala 67:52] + node _T_1831 = eq(_T_1830, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1832 = bits(io.ins, 16, 16) @[el2_dec_dec_ctl.scala 67:52] + node _T_1833 = eq(_T_1832, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1834 = bits(io.ins, 15, 15) @[el2_dec_dec_ctl.scala 67:52] + node _T_1835 = eq(_T_1834, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1836 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1837 = eq(_T_1836, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1838 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1839 = eq(_T_1838, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1840 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1841 = eq(_T_1840, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1842 = bits(io.ins, 11, 11) @[el2_dec_dec_ctl.scala 67:52] + node _T_1843 = eq(_T_1842, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1844 = bits(io.ins, 10, 10) @[el2_dec_dec_ctl.scala 67:52] + node _T_1845 = eq(_T_1844, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1846 = bits(io.ins, 9, 9) @[el2_dec_dec_ctl.scala 67:52] + node _T_1847 = eq(_T_1846, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1848 = bits(io.ins, 8, 8) @[el2_dec_dec_ctl.scala 67:52] + node _T_1849 = eq(_T_1848, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1850 = bits(io.ins, 7, 7) @[el2_dec_dec_ctl.scala 67:52] + node _T_1851 = eq(_T_1850, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1852 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1853 = eq(_T_1852, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1854 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1855 = eq(_T_1854, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1856 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1857 = eq(_T_1856, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1858 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1859 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1860 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1861 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1863 = and(_T_1819, _T_1821) @[el2_dec_dec_ctl.scala 165:110] + node _T_1864 = and(_T_1863, _T_1823) @[el2_dec_dec_ctl.scala 165:110] + node _T_1865 = and(_T_1864, _T_1825) @[el2_dec_dec_ctl.scala 165:110] + node _T_1866 = and(_T_1865, _T_1827) @[el2_dec_dec_ctl.scala 165:110] + node _T_1867 = and(_T_1866, _T_1829) @[el2_dec_dec_ctl.scala 165:110] + node _T_1868 = and(_T_1867, _T_1831) @[el2_dec_dec_ctl.scala 165:110] + node _T_1869 = and(_T_1868, _T_1833) @[el2_dec_dec_ctl.scala 165:110] + node _T_1870 = and(_T_1869, _T_1835) @[el2_dec_dec_ctl.scala 165:110] + node _T_1871 = and(_T_1870, _T_1837) @[el2_dec_dec_ctl.scala 165:110] + node _T_1872 = and(_T_1871, _T_1839) @[el2_dec_dec_ctl.scala 165:110] + node _T_1873 = and(_T_1872, _T_1841) @[el2_dec_dec_ctl.scala 165:110] + node _T_1874 = and(_T_1873, _T_1843) @[el2_dec_dec_ctl.scala 165:110] + node _T_1875 = and(_T_1874, _T_1845) @[el2_dec_dec_ctl.scala 165:110] + node _T_1876 = and(_T_1875, _T_1847) @[el2_dec_dec_ctl.scala 165:110] + node _T_1877 = and(_T_1876, _T_1849) @[el2_dec_dec_ctl.scala 165:110] + node _T_1878 = and(_T_1877, _T_1851) @[el2_dec_dec_ctl.scala 165:110] + node _T_1879 = and(_T_1878, _T_1853) @[el2_dec_dec_ctl.scala 165:110] + node _T_1880 = and(_T_1879, _T_1855) @[el2_dec_dec_ctl.scala 165:110] + node _T_1881 = and(_T_1880, _T_1857) @[el2_dec_dec_ctl.scala 165:110] + node _T_1882 = and(_T_1881, _T_1858) @[el2_dec_dec_ctl.scala 165:110] + node _T_1883 = and(_T_1882, _T_1859) @[el2_dec_dec_ctl.scala 165:110] + node _T_1884 = and(_T_1883, _T_1860) @[el2_dec_dec_ctl.scala 165:110] + node _T_1885 = and(_T_1884, _T_1862) @[el2_dec_dec_ctl.scala 165:110] + node _T_1886 = or(_T_1817, _T_1885) @[el2_dec_dec_ctl.scala 164:146] + node _T_1887 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:52] + node _T_1888 = eq(_T_1887, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1889 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1890 = eq(_T_1889, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1891 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1892 = eq(_T_1891, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1893 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1894 = eq(_T_1893, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1895 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1896 = eq(_T_1895, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1897 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1898 = eq(_T_1897, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1899 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1900 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1901 = eq(_T_1900, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1902 = and(_T_1888, _T_1890) @[el2_dec_dec_ctl.scala 166:51] + node _T_1903 = and(_T_1902, _T_1892) @[el2_dec_dec_ctl.scala 166:51] + node _T_1904 = and(_T_1903, _T_1894) @[el2_dec_dec_ctl.scala 166:51] + node _T_1905 = and(_T_1904, _T_1896) @[el2_dec_dec_ctl.scala 166:51] + node _T_1906 = and(_T_1905, _T_1898) @[el2_dec_dec_ctl.scala 166:51] + node _T_1907 = and(_T_1906, _T_1899) @[el2_dec_dec_ctl.scala 166:51] + node _T_1908 = and(_T_1907, _T_1901) @[el2_dec_dec_ctl.scala 166:51] + node _T_1909 = or(_T_1886, _T_1908) @[el2_dec_dec_ctl.scala 165:114] + node _T_1910 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:33] + node _T_1911 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:33] + node _T_1912 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1914 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:33] + node _T_1915 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] + node _T_1916 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1917 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1918 = eq(_T_1917, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1919 = and(_T_1910, _T_1911) @[el2_dec_dec_ctl.scala 166:95] + node _T_1920 = and(_T_1919, _T_1913) @[el2_dec_dec_ctl.scala 166:95] + node _T_1921 = and(_T_1920, _T_1914) @[el2_dec_dec_ctl.scala 166:95] + node _T_1922 = and(_T_1921, _T_1915) @[el2_dec_dec_ctl.scala 166:95] + node _T_1923 = and(_T_1922, _T_1916) @[el2_dec_dec_ctl.scala 166:95] + node _T_1924 = and(_T_1923, _T_1918) @[el2_dec_dec_ctl.scala 166:95] + node _T_1925 = or(_T_1909, _T_1924) @[el2_dec_dec_ctl.scala 166:55] + node _T_1926 = bits(io.ins, 13, 13) @[el2_dec_dec_ctl.scala 67:33] + node _T_1927 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1928 = eq(_T_1927, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1929 = bits(io.ins, 5, 5) @[el2_dec_dec_ctl.scala 67:52] + node _T_1930 = eq(_T_1929, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1931 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1932 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1933 = eq(_T_1932, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1934 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1935 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1936 = eq(_T_1935, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1937 = and(_T_1926, _T_1928) @[el2_dec_dec_ctl.scala 167:46] + node _T_1938 = and(_T_1937, _T_1930) @[el2_dec_dec_ctl.scala 167:46] + node _T_1939 = and(_T_1938, _T_1931) @[el2_dec_dec_ctl.scala 167:46] + node _T_1940 = and(_T_1939, _T_1933) @[el2_dec_dec_ctl.scala 167:46] + node _T_1941 = and(_T_1940, _T_1934) @[el2_dec_dec_ctl.scala 167:46] + node _T_1942 = and(_T_1941, _T_1936) @[el2_dec_dec_ctl.scala 167:46] + node _T_1943 = or(_T_1925, _T_1942) @[el2_dec_dec_ctl.scala 166:99] + node _T_1944 = bits(io.ins, 14, 14) @[el2_dec_dec_ctl.scala 67:52] + node _T_1945 = eq(_T_1944, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1946 = bits(io.ins, 12, 12) @[el2_dec_dec_ctl.scala 67:52] + node _T_1947 = eq(_T_1946, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1948 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1949 = eq(_T_1948, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1950 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:52] + node _T_1951 = eq(_T_1950, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1952 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1953 = eq(_T_1952, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1954 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1956 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1957 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1958 = eq(_T_1957, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1959 = and(_T_1945, _T_1947) @[el2_dec_dec_ctl.scala 167:99] + node _T_1960 = and(_T_1959, _T_1949) @[el2_dec_dec_ctl.scala 167:99] + node _T_1961 = and(_T_1960, _T_1951) @[el2_dec_dec_ctl.scala 167:99] + node _T_1962 = and(_T_1961, _T_1953) @[el2_dec_dec_ctl.scala 167:99] + node _T_1963 = and(_T_1962, _T_1955) @[el2_dec_dec_ctl.scala 167:99] + node _T_1964 = and(_T_1963, _T_1956) @[el2_dec_dec_ctl.scala 167:99] + node _T_1965 = and(_T_1964, _T_1958) @[el2_dec_dec_ctl.scala 167:99] + node _T_1966 = or(_T_1943, _T_1965) @[el2_dec_dec_ctl.scala 167:50] + node _T_1967 = bits(io.ins, 6, 6) @[el2_dec_dec_ctl.scala 67:52] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] + node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] + node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] + node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] + node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] + node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] + node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] + node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] + io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_dec_decode_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip dec_tlu_flush_extint : UInt<1>, flip dec_tlu_force_halt : UInt<1>, dec_extint_stall : UInt<1>, flip ifu_i0_cinst : UInt<16>, dec_i0_inst_wb1 : UInt<32>, dec_i0_pc_wb1 : UInt<31>, flip lsu_nonblock_load_valid_m : UInt<1>, flip lsu_nonblock_load_tag_m : UInt<2>, flip lsu_nonblock_load_inv_r : UInt<1>, flip lsu_nonblock_load_inv_tag_r : UInt<2>, flip lsu_nonblock_load_data_valid : UInt<1>, flip lsu_nonblock_load_data_error : UInt<1>, flip lsu_nonblock_load_data_tag : UInt<2>, flip lsu_nonblock_load_data : UInt<32>, flip dec_i0_trigger_match_d : UInt<4>, flip dec_tlu_wr_pause_r : UInt<1>, flip dec_tlu_pipelining_disable : UInt<1>, flip lsu_trigger_match_m : UInt<4>, flip lsu_pmu_misaligned_m : UInt<1>, flip dec_tlu_debug_stall : UInt<1>, flip dec_tlu_flush_leak_one_r : UInt<1>, flip dec_debug_fence_d : UInt<1>, flip dbg_cmd_wrdata : UInt<2>, flip dec_i0_icaf_d : UInt<1>, flip dec_i0_icaf_f1_d : UInt<1>, flip dec_i0_icaf_type_d : UInt<2>, flip dec_i0_dbecc_d : UInt<1>, flip dec_i0_brp : {valid : UInt<1>, toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}, flip dec_i0_bp_index : UInt<8>, flip dec_i0_bp_fghr : UInt<8>, flip dec_i0_bp_btag : UInt<5>, flip dec_i0_pc_d : UInt<31>, flip lsu_idle_any : UInt<1>, flip lsu_load_stall_any : UInt<1>, flip lsu_store_stall_any : UInt<1>, flip dma_dccm_stall_any : UInt<1>, flip exu_div_wren : UInt<1>, flip dec_tlu_i0_kill_writeb_wb : UInt<1>, flip dec_tlu_flush_lower_wb : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_pause_r : UInt<1>, flip dec_tlu_presync_d : UInt<1>, flip dec_tlu_postsync_d : UInt<1>, flip dec_i0_pc4_d : UInt<1>, flip dec_csr_rddata_d : UInt<32>, flip dec_csr_legal_d : UInt<1>, flip exu_csr_rs1_x : UInt<32>, flip lsu_result_m : UInt<32>, flip lsu_result_corr_r : UInt<32>, flip exu_flush_final : UInt<1>, flip exu_i0_pc_x : UInt<31>, flip dec_i0_instr_d : UInt<32>, flip dec_ib0_valid_d : UInt<1>, flip exu_i0_result_x : UInt<32>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, dec_i0_rs1_en_d : UInt<1>, dec_i0_rs2_en_d : UInt<1>, dec_i0_rs1_d : UInt<5>, dec_i0_rs2_d : UInt<5>, dec_i0_immed_d : UInt<32>, dec_i0_br_immed_d : UInt<12>, i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, dec_i0_decode_d : UInt<1>, dec_i0_alu_decode_d : UInt<1>, dec_i0_rs1_bypass_data_d : UInt<32>, dec_i0_rs2_bypass_data_d : UInt<32>, dec_i0_waddr_r : UInt<5>, dec_i0_wen_r : UInt<1>, dec_i0_wdata_r : UInt<32>, dec_i0_select_pc_d : UInt<1>, dec_i0_rs1_bypass_en_d : UInt<2>, dec_i0_rs2_bypass_en_d : UInt<2>, lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, div_waddr_wb : UInt<5>, dec_div_cancel : UInt<1>, dec_lsu_valid_raw_d : UInt<1>, dec_lsu_offset_d : UInt<12>, dec_csr_ren_d : UInt<1>, dec_csr_wen_unq_d : UInt<1>, dec_csr_any_unq_d : UInt<1>, dec_csr_rdaddr_d : UInt<12>, dec_csr_wen_r : UInt<1>, dec_csr_wraddr_r : UInt<12>, dec_csr_wrdata_r : UInt<32>, dec_csr_stall_int_ff : UInt<1>, dec_tlu_i0_valid_r : UInt<1>, dec_tlu_packet_r : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, dec_tlu_i0_pc_r : UInt<31>, dec_illegal_inst : UInt<32>, pred_correct_npc_x : UInt<31>, dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, i0_predict_fghr_d : UInt<8>, i0_predict_index_d : UInt<8>, i0_predict_btag_d : UInt<5>, dec_data_en : UInt<2>, dec_ctl_en : UInt<2>, dec_pmu_instr_decoded : UInt<1>, dec_pmu_decode_stall : UInt<1>, dec_pmu_presync_stall : UInt<1>, dec_pmu_postsync_stall : UInt<1>, dec_nonblock_load_wen : UInt<1>, dec_nonblock_load_waddr : UInt<5>, dec_pause_state : UInt<1>, dec_pause_state_cg : UInt<1>, dec_div_active : UInt<1>, flip scan_mode : UInt<1>} + + wire _T : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>} @[el2_dec_decode_ctl.scala 126:27] + _T.bfp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32c_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_w <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_h <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.crc32_b <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.unshfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.shfl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.grev <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmulh <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.clmul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bdep <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.bext <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + _T.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 126:27] + io.mul_p.bfp <= _T.bfp @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_w <= _T.crc32c_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_h <= _T.crc32c_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32c_b <= _T.crc32c_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_w <= _T.crc32_w @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_h <= _T.crc32_h @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.crc32_b <= _T.crc32_b @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.unshfl <= _T.unshfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.shfl <= _T.shfl @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.grev <= _T.grev @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulr <= _T.clmulr @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmulh <= _T.clmulh @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.clmul <= _T.clmul @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bdep <= _T.bdep @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.bext <= _T.bext @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.low <= _T.low @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs2_sign <= _T.rs2_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.rs1_sign <= _T.rs1_sign @[el2_dec_decode_ctl.scala 126:12] + io.mul_p.valid <= _T.valid @[el2_dec_decode_ctl.scala 126:12] + wire leak1_i1_stall_in : UInt<1> + leak1_i1_stall_in <= UInt<1>("h00") + wire leak1_i0_stall_in : UInt<1> + leak1_i0_stall_in <= UInt<1>("h00") + wire i0r : {rs1 : UInt<5>, rs2 : UInt<5>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 130:17] + wire d_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 131:17] + wire x_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 132:17] + wire x_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 133:20] + wire r_t : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 134:17] + wire r_t_in : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 135:23] + wire d_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 136:17] + wire x_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 137:17] + wire r_d : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 138:17] + wire r_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 139:20] + wire wbd : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 140:17] + wire i0_d_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 141:20] + wire i0_rs1_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 142:28] + wire i0_rs2_class_d : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 143:28] + wire i0_rs1_depth_d : UInt<2> + i0_rs1_depth_d <= UInt<1>("h00") + wire i0_rs2_depth_d : UInt<2> + i0_rs2_depth_d <= UInt<1>("h00") + wire cam_wen : UInt<4> + cam_wen <= UInt<1>("h00") + wire cam : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 147:17] + wire cam_write : UInt<1> + cam_write <= UInt<1>("h00") + wire cam_inv_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 149:29] + wire cam_data_reset_val : UInt<1>[4] @[el2_dec_decode_ctl.scala 150:30] + wire nonblock_load_write : UInt<1>[4] @[el2_dec_decode_ctl.scala 151:31] + wire cam_raw : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 152:20] + wire cam_in : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}[4] @[el2_dec_decode_ctl.scala 153:20] + wire i0_dp : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 155:18] + wire i0_dp_raw : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 156:22] + wire i0_rs1bypass : UInt<3> + i0_rs1bypass <= UInt<1>("h00") + wire i0_rs2bypass : UInt<3> + i0_rs2bypass <= UInt<1>("h00") + wire illegal_lockout : UInt<1> + illegal_lockout <= UInt<1>("h00") + wire postsync_stall : UInt<1> + postsync_stall <= UInt<1>("h00") + wire ps_stall_in : UInt<1> + ps_stall_in <= UInt<1>("h00") + wire i0_pipe_en : UInt<4> + i0_pipe_en <= UInt<1>("h00") + wire i0_load_block_d : UInt<1> + i0_load_block_d <= UInt<1>("h00") + wire load_ldst_bypass_d : UInt<1> + load_ldst_bypass_d <= UInt<1>("h00") + wire store_data_bypass_d : UInt<1> + store_data_bypass_d <= UInt<1>("h00") + wire store_data_bypass_m : UInt<1> + store_data_bypass_m <= UInt<1>("h00") + wire tlu_wr_pause_r1 : UInt<1> + tlu_wr_pause_r1 <= UInt<1>("h00") + wire tlu_wr_pause_r2 : UInt<1> + tlu_wr_pause_r2 <= UInt<1>("h00") + wire leak1_i1_stall : UInt<1> + leak1_i1_stall <= UInt<1>("h00") + wire leak1_i0_stall : UInt<1> + leak1_i0_stall <= UInt<1>("h00") + wire pause_stall : UInt<1> + pause_stall <= UInt<1>("h00") + wire flush_final_r : UInt<1> + flush_final_r <= UInt<1>("h00") + wire illegal_lockout_in : UInt<1> + illegal_lockout_in <= UInt<1>("h00") + wire lsu_idle : UInt<1> + lsu_idle <= UInt<1>("h00") + wire pause_state_in : UInt<1> + pause_state_in <= UInt<1>("h00") + wire leak1_mode : UInt<1> + leak1_mode <= UInt<1>("h00") + wire i0_pcall : UInt<1> + i0_pcall <= UInt<1>("h00") + wire i0_pja : UInt<1> + i0_pja <= UInt<1>("h00") + wire i0_pret : UInt<1> + i0_pret <= UInt<1>("h00") + wire i0_legal_decode_d : UInt<1> + i0_legal_decode_d <= UInt<1>("h00") + wire i0_pcall_raw : UInt<1> + i0_pcall_raw <= UInt<1>("h00") + wire i0_pja_raw : UInt<1> + i0_pja_raw <= UInt<1>("h00") + wire i0_pret_raw : UInt<1> + i0_pret_raw <= UInt<1>("h00") + wire i0_br_offset : UInt<12> + i0_br_offset <= UInt<1>("h00") + wire i0_csr_write_only_d : UInt<1> + i0_csr_write_only_d <= UInt<1>("h00") + wire i0_jal : UInt<1> + i0_jal <= UInt<1>("h00") + wire i0_wen_r : UInt<1> + i0_wen_r <= UInt<1>("h00") + wire i0_x_ctl_en : UInt<1> + i0_x_ctl_en <= UInt<1>("h00") + wire i0_r_ctl_en : UInt<1> + i0_r_ctl_en <= UInt<1>("h00") + wire i0_wb_ctl_en : UInt<1> + i0_wb_ctl_en <= UInt<1>("h00") + wire i0_x_data_en : UInt<1> + i0_x_data_en <= UInt<1>("h00") + wire i0_r_data_en : UInt<1> + i0_r_data_en <= UInt<1>("h00") + wire i0_wb_data_en : UInt<1> + i0_wb_data_en <= UInt<1>("h00") + wire i0_wb1_data_en : UInt<1> + i0_wb1_data_en <= UInt<1>("h00") + wire i0_nonblock_load_stall : UInt<1> + i0_nonblock_load_stall <= UInt<1>("h00") + wire csr_read : UInt<1> + csr_read <= UInt<1>("h00") + wire lsu_decode_d : UInt<1> + lsu_decode_d <= UInt<1>("h00") + wire mul_decode_d : UInt<1> + mul_decode_d <= UInt<1>("h00") + wire div_decode_d : UInt<1> + div_decode_d <= UInt<1>("h00") + wire write_csr_data : UInt<32> + write_csr_data <= UInt<1>("h00") + wire i0_result_corr_r : UInt<32> + i0_result_corr_r <= UInt<1>("h00") + wire presync_stall : UInt<1> + presync_stall <= UInt<1>("h00") + wire i0_nonblock_div_stall : UInt<1> + i0_nonblock_div_stall <= UInt<1>("h00") + wire debug_fence : UInt<1> + debug_fence <= UInt<1>("h00") + wire i0_immed_d : UInt<32> + i0_immed_d <= UInt<1>("h00") + wire i0_result_x : UInt<32> + i0_result_x <= UInt<1>("h00") + wire i0_result_r : UInt<32> + i0_result_r <= UInt<1>("h00") + node _T_1 = xor(io.dec_tlu_wr_pause_r, tlu_wr_pause_r1) @[el2_dec_decode_ctl.scala 211:51] + node _T_2 = xor(tlu_wr_pause_r1, tlu_wr_pause_r2) @[el2_dec_decode_ctl.scala 212:32] + node _T_3 = or(_T_1, _T_2) @[el2_dec_decode_ctl.scala 211:73] + node _T_4 = xor(io.dec_tlu_flush_extint, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 213:32] + node _T_5 = or(_T_3, _T_4) @[el2_dec_decode_ctl.scala 212:56] + node _T_6 = xor(leak1_i1_stall_in, leak1_i1_stall) @[el2_dec_decode_ctl.scala 214:32] + node _T_7 = or(_T_5, _T_6) @[el2_dec_decode_ctl.scala 213:56] + node _T_8 = xor(leak1_i0_stall_in, leak1_i0_stall) @[el2_dec_decode_ctl.scala 215:32] + node _T_9 = or(_T_7, _T_8) @[el2_dec_decode_ctl.scala 214:56] + node _T_10 = xor(pause_state_in, pause_stall) @[el2_dec_decode_ctl.scala 216:32] + node _T_11 = or(_T_9, _T_10) @[el2_dec_decode_ctl.scala 215:56] + node _T_12 = xor(ps_stall_in, postsync_stall) @[el2_dec_decode_ctl.scala 217:32] + node _T_13 = or(_T_11, _T_12) @[el2_dec_decode_ctl.scala 216:56] + node _T_14 = xor(io.exu_flush_final, flush_final_r) @[el2_dec_decode_ctl.scala 218:32] + node _T_15 = or(_T_13, _T_14) @[el2_dec_decode_ctl.scala 217:56] + node _T_16 = xor(illegal_lockout_in, illegal_lockout) @[el2_dec_decode_ctl.scala 219:32] + node data_gate_en = or(_T_15, _T_16) @[el2_dec_decode_ctl.scala 218:56] + inst data_gated_cgc of rvclkhdr @[el2_dec_decode_ctl.scala 222:29] + data_gated_cgc.clock <= clock + data_gated_cgc.reset <= reset + data_gated_cgc.io.en <= data_gate_en @[el2_dec_decode_ctl.scala 223:31] + data_gated_cgc.io.scan_mode <= io.scan_mode @[el2_dec_decode_ctl.scala 224:31] + data_gated_cgc.io.clk <= clock @[el2_dec_decode_ctl.scala 225:31] + node _T_17 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 230:62] + node i0_brp_valid = and(io.dec_i0_brp.valid, _T_17) @[el2_dec_decode_ctl.scala 230:60] + io.dec_i0_predict_p_d.misp <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 231:38] + io.dec_i0_predict_p_d.ataken <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 232:38] + io.dec_i0_predict_p_d.boffset <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 233:38] + io.dec_i0_predict_p_d.pcall <= i0_pcall @[el2_dec_decode_ctl.scala 234:38] + io.dec_i0_predict_p_d.pja <= i0_pja @[el2_dec_decode_ctl.scala 235:38] + io.dec_i0_predict_p_d.pret <= i0_pret @[el2_dec_decode_ctl.scala 236:38] + io.dec_i0_predict_p_d.prett <= io.dec_i0_brp.prett @[el2_dec_decode_ctl.scala 237:38] + io.dec_i0_predict_p_d.pc4 <= io.dec_i0_pc4_d @[el2_dec_decode_ctl.scala 238:38] + io.dec_i0_predict_p_d.hist <= io.dec_i0_brp.hist @[el2_dec_decode_ctl.scala 239:38] + node _T_18 = and(i0_brp_valid, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 240:55] + io.dec_i0_predict_p_d.valid <= _T_18 @[el2_dec_decode_ctl.scala 240:38] + node _T_19 = or(i0_dp_raw.condbr, i0_pcall_raw) @[el2_dec_decode_ctl.scala 241:75] + node _T_20 = or(_T_19, i0_pja_raw) @[el2_dec_decode_ctl.scala 241:90] + node _T_21 = or(_T_20, i0_pret_raw) @[el2_dec_decode_ctl.scala 241:103] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 241:56] + node i0_notbr_error = and(i0_brp_valid, _T_22) @[el2_dec_decode_ctl.scala 241:54] + node _T_23 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 244:67] + node _T_24 = and(i0_brp_valid, _T_23) @[el2_dec_decode_ctl.scala 244:47] + node _T_25 = neq(io.dec_i0_brp.toffset, i0_br_offset) @[el2_dec_decode_ctl.scala 244:96] + node _T_26 = and(_T_24, _T_25) @[el2_dec_decode_ctl.scala 244:71] + node _T_27 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 244:116] + node i0_br_toffset_error = and(_T_26, _T_27) @[el2_dec_decode_ctl.scala 244:114] + node _T_28 = and(i0_brp_valid, io.dec_i0_brp.ret) @[el2_dec_decode_ctl.scala 245:47] + node _T_29 = eq(i0_pret_raw, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 245:69] + node i0_ret_error = and(_T_28, _T_29) @[el2_dec_decode_ctl.scala 245:67] + node _T_30 = or(io.dec_i0_brp.br_error, i0_notbr_error) @[el2_dec_decode_ctl.scala 246:57] + node _T_31 = or(_T_30, i0_br_toffset_error) @[el2_dec_decode_ctl.scala 246:74] + node i0_br_error = or(_T_31, i0_ret_error) @[el2_dec_decode_ctl.scala 246:96] + node _T_32 = and(i0_br_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 247:67] + node _T_33 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 247:89] + node _T_34 = and(_T_32, _T_33) @[el2_dec_decode_ctl.scala 247:87] + io.dec_i0_predict_p_d.br_error <= _T_34 @[el2_dec_decode_ctl.scala 247:51] + node _T_35 = and(io.dec_i0_brp.br_start_error, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 248:84] + node _T_36 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 248:106] + node _T_37 = and(_T_35, _T_36) @[el2_dec_decode_ctl.scala 248:104] + io.dec_i0_predict_p_d.br_start_error <= _T_37 @[el2_dec_decode_ctl.scala 248:51] + io.i0_predict_index_d <= io.dec_i0_bp_index @[el2_dec_decode_ctl.scala 249:32] + io.i0_predict_btag_d <= io.dec_i0_bp_btag @[el2_dec_decode_ctl.scala 250:32] + node _T_38 = or(i0_br_error, io.dec_i0_brp.br_start_error) @[el2_dec_decode_ctl.scala 251:47] + node _T_39 = eq(leak1_mode, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 251:81] + node i0_br_error_all = and(_T_38, _T_39) @[el2_dec_decode_ctl.scala 251:79] + io.dec_i0_predict_p_d.toffset <= i0_br_offset @[el2_dec_decode_ctl.scala 252:44] + io.i0_predict_fghr_d <= io.dec_i0_bp_fghr @[el2_dec_decode_ctl.scala 253:32] + io.dec_i0_predict_p_d.way <= io.dec_i0_brp.way @[el2_dec_decode_ctl.scala 254:51] + node i0_icaf_d = or(io.dec_i0_icaf_d, io.dec_i0_dbecc_d) @[el2_dec_decode_ctl.scala 260:36] + i0_dp.legal <= i0_dp_raw.legal @[el2_dec_decode_ctl.scala 263:9] + i0_dp.pm_alu <= i0_dp_raw.pm_alu @[el2_dec_decode_ctl.scala 263:9] + i0_dp.fence_i <= i0_dp_raw.fence_i @[el2_dec_decode_ctl.scala 263:9] + i0_dp.fence <= i0_dp_raw.fence @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rem <= i0_dp_raw.rem @[el2_dec_decode_ctl.scala 263:9] + i0_dp.div <= i0_dp_raw.div @[el2_dec_decode_ctl.scala 263:9] + i0_dp.low <= i0_dp_raw.low @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rs2_sign <= i0_dp_raw.rs2_sign @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rs1_sign <= i0_dp_raw.rs1_sign @[el2_dec_decode_ctl.scala 263:9] + i0_dp.mul <= i0_dp_raw.mul @[el2_dec_decode_ctl.scala 263:9] + i0_dp.mret <= i0_dp_raw.mret @[el2_dec_decode_ctl.scala 263:9] + i0_dp.ecall <= i0_dp_raw.ecall @[el2_dec_decode_ctl.scala 263:9] + i0_dp.ebreak <= i0_dp_raw.ebreak @[el2_dec_decode_ctl.scala 263:9] + i0_dp.postsync <= i0_dp_raw.postsync @[el2_dec_decode_ctl.scala 263:9] + i0_dp.presync <= i0_dp_raw.presync @[el2_dec_decode_ctl.scala 263:9] + i0_dp.csr_imm <= i0_dp_raw.csr_imm @[el2_dec_decode_ctl.scala 263:9] + i0_dp.csr_write <= i0_dp_raw.csr_write @[el2_dec_decode_ctl.scala 263:9] + i0_dp.csr_set <= i0_dp_raw.csr_set @[el2_dec_decode_ctl.scala 263:9] + i0_dp.csr_clr <= i0_dp_raw.csr_clr @[el2_dec_decode_ctl.scala 263:9] + i0_dp.csr_read <= i0_dp_raw.csr_read @[el2_dec_decode_ctl.scala 263:9] + i0_dp.word <= i0_dp_raw.word @[el2_dec_decode_ctl.scala 263:9] + i0_dp.half <= i0_dp_raw.half @[el2_dec_decode_ctl.scala 263:9] + i0_dp.by <= i0_dp_raw.by @[el2_dec_decode_ctl.scala 263:9] + i0_dp.jal <= i0_dp_raw.jal @[el2_dec_decode_ctl.scala 263:9] + i0_dp.blt <= i0_dp_raw.blt @[el2_dec_decode_ctl.scala 263:9] + i0_dp.bge <= i0_dp_raw.bge @[el2_dec_decode_ctl.scala 263:9] + i0_dp.bne <= i0_dp_raw.bne @[el2_dec_decode_ctl.scala 263:9] + i0_dp.beq <= i0_dp_raw.beq @[el2_dec_decode_ctl.scala 263:9] + i0_dp.condbr <= i0_dp_raw.condbr @[el2_dec_decode_ctl.scala 263:9] + i0_dp.unsign <= i0_dp_raw.unsign @[el2_dec_decode_ctl.scala 263:9] + i0_dp.slt <= i0_dp_raw.slt @[el2_dec_decode_ctl.scala 263:9] + i0_dp.srl <= i0_dp_raw.srl @[el2_dec_decode_ctl.scala 263:9] + i0_dp.sra <= i0_dp_raw.sra @[el2_dec_decode_ctl.scala 263:9] + i0_dp.sll <= i0_dp_raw.sll @[el2_dec_decode_ctl.scala 263:9] + i0_dp.lxor <= i0_dp_raw.lxor @[el2_dec_decode_ctl.scala 263:9] + i0_dp.lor <= i0_dp_raw.lor @[el2_dec_decode_ctl.scala 263:9] + i0_dp.land <= i0_dp_raw.land @[el2_dec_decode_ctl.scala 263:9] + i0_dp.sub <= i0_dp_raw.sub @[el2_dec_decode_ctl.scala 263:9] + i0_dp.add <= i0_dp_raw.add @[el2_dec_decode_ctl.scala 263:9] + i0_dp.lsu <= i0_dp_raw.lsu @[el2_dec_decode_ctl.scala 263:9] + i0_dp.store <= i0_dp_raw.store @[el2_dec_decode_ctl.scala 263:9] + i0_dp.load <= i0_dp_raw.load @[el2_dec_decode_ctl.scala 263:9] + i0_dp.pc <= i0_dp_raw.pc @[el2_dec_decode_ctl.scala 263:9] + i0_dp.imm20 <= i0_dp_raw.imm20 @[el2_dec_decode_ctl.scala 263:9] + i0_dp.shimm5 <= i0_dp_raw.shimm5 @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rd <= i0_dp_raw.rd @[el2_dec_decode_ctl.scala 263:9] + i0_dp.imm12 <= i0_dp_raw.imm12 @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rs2 <= i0_dp_raw.rs2 @[el2_dec_decode_ctl.scala 263:9] + i0_dp.rs1 <= i0_dp_raw.rs1 @[el2_dec_decode_ctl.scala 263:9] + i0_dp.alu <= i0_dp_raw.alu @[el2_dec_decode_ctl.scala 263:9] + node _T_40 = or(i0_br_error_all, i0_icaf_d) @[el2_dec_decode_ctl.scala 264:25] + node _T_41 = bits(_T_40, 0, 0) @[el2_dec_decode_ctl.scala 264:43] + when _T_41 : @[el2_dec_decode_ctl.scala 264:50] + wire _T_42 : {alu : UInt<1>, rs1 : UInt<1>, rs2 : UInt<1>, imm12 : UInt<1>, rd : UInt<1>, shimm5 : UInt<1>, imm20 : UInt<1>, pc : UInt<1>, load : UInt<1>, store : UInt<1>, lsu : UInt<1>, add : UInt<1>, sub : UInt<1>, land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, sra : UInt<1>, srl : UInt<1>, slt : UInt<1>, unsign : UInt<1>, condbr : UInt<1>, beq : UInt<1>, bne : UInt<1>, bge : UInt<1>, blt : UInt<1>, jal : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, csr_read : UInt<1>, csr_clr : UInt<1>, csr_set : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>, presync : UInt<1>, postsync : UInt<1>, ebreak : UInt<1>, ecall : UInt<1>, mret : UInt<1>, mul : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, div : UInt<1>, rem : UInt<1>, fence : UInt<1>, fence_i : UInt<1>, pm_alu : UInt<1>, legal : UInt<1>} @[el2_dec_decode_ctl.scala 265:35] + _T_42.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.pm_alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.fence <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rem <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.div <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.low <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rs2_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rs1_sign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.mret <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.ecall <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.ebreak <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.postsync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.presync <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.csr_imm <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.csr_write <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.csr_set <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.csr_clr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.csr_read <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.jal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.blt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.bge <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.bne <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.beq <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.condbr <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.slt <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.srl <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.sra <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.sll <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.lxor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.lor <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.land <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.sub <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.add <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.lsu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.pc <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.imm20 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.shimm5 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rd <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.imm12 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rs2 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.rs1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + _T_42.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 265:35] + i0_dp.legal <= _T_42.legal @[el2_dec_decode_ctl.scala 265:20] + i0_dp.pm_alu <= _T_42.pm_alu @[el2_dec_decode_ctl.scala 265:20] + i0_dp.fence_i <= _T_42.fence_i @[el2_dec_decode_ctl.scala 265:20] + i0_dp.fence <= _T_42.fence @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rem <= _T_42.rem @[el2_dec_decode_ctl.scala 265:20] + i0_dp.div <= _T_42.div @[el2_dec_decode_ctl.scala 265:20] + i0_dp.low <= _T_42.low @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs2_sign <= _T_42.rs2_sign @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs1_sign <= _T_42.rs1_sign @[el2_dec_decode_ctl.scala 265:20] + i0_dp.mul <= _T_42.mul @[el2_dec_decode_ctl.scala 265:20] + i0_dp.mret <= _T_42.mret @[el2_dec_decode_ctl.scala 265:20] + i0_dp.ecall <= _T_42.ecall @[el2_dec_decode_ctl.scala 265:20] + i0_dp.ebreak <= _T_42.ebreak @[el2_dec_decode_ctl.scala 265:20] + i0_dp.postsync <= _T_42.postsync @[el2_dec_decode_ctl.scala 265:20] + i0_dp.presync <= _T_42.presync @[el2_dec_decode_ctl.scala 265:20] + i0_dp.csr_imm <= _T_42.csr_imm @[el2_dec_decode_ctl.scala 265:20] + i0_dp.csr_write <= _T_42.csr_write @[el2_dec_decode_ctl.scala 265:20] + i0_dp.csr_set <= _T_42.csr_set @[el2_dec_decode_ctl.scala 265:20] + i0_dp.csr_clr <= _T_42.csr_clr @[el2_dec_decode_ctl.scala 265:20] + i0_dp.csr_read <= _T_42.csr_read @[el2_dec_decode_ctl.scala 265:20] + i0_dp.word <= _T_42.word @[el2_dec_decode_ctl.scala 265:20] + i0_dp.half <= _T_42.half @[el2_dec_decode_ctl.scala 265:20] + i0_dp.by <= _T_42.by @[el2_dec_decode_ctl.scala 265:20] + i0_dp.jal <= _T_42.jal @[el2_dec_decode_ctl.scala 265:20] + i0_dp.blt <= _T_42.blt @[el2_dec_decode_ctl.scala 265:20] + i0_dp.bge <= _T_42.bge @[el2_dec_decode_ctl.scala 265:20] + i0_dp.bne <= _T_42.bne @[el2_dec_decode_ctl.scala 265:20] + i0_dp.beq <= _T_42.beq @[el2_dec_decode_ctl.scala 265:20] + i0_dp.condbr <= _T_42.condbr @[el2_dec_decode_ctl.scala 265:20] + i0_dp.unsign <= _T_42.unsign @[el2_dec_decode_ctl.scala 265:20] + i0_dp.slt <= _T_42.slt @[el2_dec_decode_ctl.scala 265:20] + i0_dp.srl <= _T_42.srl @[el2_dec_decode_ctl.scala 265:20] + i0_dp.sra <= _T_42.sra @[el2_dec_decode_ctl.scala 265:20] + i0_dp.sll <= _T_42.sll @[el2_dec_decode_ctl.scala 265:20] + i0_dp.lxor <= _T_42.lxor @[el2_dec_decode_ctl.scala 265:20] + i0_dp.lor <= _T_42.lor @[el2_dec_decode_ctl.scala 265:20] + i0_dp.land <= _T_42.land @[el2_dec_decode_ctl.scala 265:20] + i0_dp.sub <= _T_42.sub @[el2_dec_decode_ctl.scala 265:20] + i0_dp.add <= _T_42.add @[el2_dec_decode_ctl.scala 265:20] + i0_dp.lsu <= _T_42.lsu @[el2_dec_decode_ctl.scala 265:20] + i0_dp.store <= _T_42.store @[el2_dec_decode_ctl.scala 265:20] + i0_dp.load <= _T_42.load @[el2_dec_decode_ctl.scala 265:20] + i0_dp.pc <= _T_42.pc @[el2_dec_decode_ctl.scala 265:20] + i0_dp.imm20 <= _T_42.imm20 @[el2_dec_decode_ctl.scala 265:20] + i0_dp.shimm5 <= _T_42.shimm5 @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rd <= _T_42.rd @[el2_dec_decode_ctl.scala 265:20] + i0_dp.imm12 <= _T_42.imm12 @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs2 <= _T_42.rs2 @[el2_dec_decode_ctl.scala 265:20] + i0_dp.rs1 <= _T_42.rs1 @[el2_dec_decode_ctl.scala 265:20] + i0_dp.alu <= _T_42.alu @[el2_dec_decode_ctl.scala 265:20] + i0_dp.alu <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 266:20] + i0_dp.rs1 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 267:20] + i0_dp.rs2 <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 268:20] + i0_dp.lor <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 269:20] + i0_dp.legal <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 270:20] + i0_dp.postsync <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 271:20] + skip @[el2_dec_decode_ctl.scala 264:50] + io.dec_i0_select_pc_d <= i0_dp.pc @[el2_dec_decode_ctl.scala 275:25] + node _T_43 = or(i0_dp.condbr, i0_pcall) @[el2_dec_decode_ctl.scala 278:38] + node _T_44 = or(_T_43, i0_pja) @[el2_dec_decode_ctl.scala 278:49] + node i0_predict_br = or(_T_44, i0_pret) @[el2_dec_decode_ctl.scala 278:58] + node _T_45 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 280:46] + node _T_46 = and(_T_45, i0_brp_valid) @[el2_dec_decode_ctl.scala 280:50] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 280:26] + node i0_predict_nt = and(_T_47, i0_predict_br) @[el2_dec_decode_ctl.scala 280:66] + node _T_48 = bits(io.dec_i0_brp.hist, 1, 1) @[el2_dec_decode_ctl.scala 281:46] + node _T_49 = and(_T_48, i0_brp_valid) @[el2_dec_decode_ctl.scala 281:50] + node i0_predict_t = and(_T_49, i0_predict_br) @[el2_dec_decode_ctl.scala 281:66] + node i0_ap_pc2 = eq(io.dec_i0_pc4_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 282:20] + io.i0_ap.predict_nt <= i0_predict_nt @[el2_dec_decode_ctl.scala 284:26] + io.i0_ap.predict_t <= i0_predict_t @[el2_dec_decode_ctl.scala 285:26] + io.i0_ap.add <= i0_dp.add @[el2_dec_decode_ctl.scala 287:20] + io.i0_ap.sub <= i0_dp.sub @[el2_dec_decode_ctl.scala 288:20] + io.i0_ap.land <= i0_dp.land @[el2_dec_decode_ctl.scala 289:20] + io.i0_ap.lor <= i0_dp.lor @[el2_dec_decode_ctl.scala 290:20] + io.i0_ap.lxor <= i0_dp.lxor @[el2_dec_decode_ctl.scala 291:20] + io.i0_ap.sll <= i0_dp.sll @[el2_dec_decode_ctl.scala 292:20] + io.i0_ap.srl <= i0_dp.srl @[el2_dec_decode_ctl.scala 293:20] + io.i0_ap.sra <= i0_dp.sra @[el2_dec_decode_ctl.scala 294:20] + io.i0_ap.slt <= i0_dp.slt @[el2_dec_decode_ctl.scala 295:20] + io.i0_ap.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 296:20] + io.i0_ap.beq <= i0_dp.beq @[el2_dec_decode_ctl.scala 297:20] + io.i0_ap.bne <= i0_dp.bne @[el2_dec_decode_ctl.scala 298:20] + io.i0_ap.blt <= i0_dp.blt @[el2_dec_decode_ctl.scala 299:20] + io.i0_ap.bge <= i0_dp.bge @[el2_dec_decode_ctl.scala 300:20] + io.i0_ap.csr_write <= i0_csr_write_only_d @[el2_dec_decode_ctl.scala 301:22] + io.i0_ap.csr_imm <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 302:22] + io.i0_ap.jal <= i0_jal @[el2_dec_decode_ctl.scala 303:22] + node _T_50 = eq(cam[0].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] + node _T_51 = bits(_T_50, 0, 0) @[el2_dec_decode_ctl.scala 307:137] + node _T_52 = shl(cam_write, 0) @[el2_dec_decode_ctl.scala 307:158] + node _T_53 = eq(cam[1].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] + node _T_54 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_55 = bits(_T_53, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_56 = and(_T_54, _T_55) @[el2_dec_decode_ctl.scala 307:126] + node _T_57 = bits(_T_56, 0, 0) @[el2_dec_decode_ctl.scala 307:137] + node _T_58 = shl(cam_write, 1) @[el2_dec_decode_ctl.scala 307:158] + node _T_59 = eq(cam[2].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] + node _T_60 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_61 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_62 = and(_T_60, _T_61) @[el2_dec_decode_ctl.scala 307:126] + node _T_63 = bits(_T_62, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_64 = bits(_T_59, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_65 = and(_T_63, _T_64) @[el2_dec_decode_ctl.scala 307:126] + node _T_66 = bits(_T_65, 0, 0) @[el2_dec_decode_ctl.scala 307:137] + node _T_67 = shl(cam_write, 2) @[el2_dec_decode_ctl.scala 307:158] + node _T_68 = eq(cam[3].valid, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 307:78] + node _T_69 = bits(cam[0].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_70 = bits(cam[1].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_71 = and(_T_69, _T_70) @[el2_dec_decode_ctl.scala 307:126] + node _T_72 = bits(_T_71, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_73 = bits(cam[2].valid, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_74 = and(_T_72, _T_73) @[el2_dec_decode_ctl.scala 307:126] + node _T_75 = bits(_T_74, 0, 0) @[el2_dec_decode_ctl.scala 307:120] + node _T_76 = bits(_T_68, 0, 0) @[el2_dec_decode_ctl.scala 307:129] + node _T_77 = and(_T_75, _T_76) @[el2_dec_decode_ctl.scala 307:126] + node _T_78 = bits(_T_77, 0, 0) @[el2_dec_decode_ctl.scala 307:137] + node _T_79 = shl(cam_write, 3) @[el2_dec_decode_ctl.scala 307:158] + node _T_80 = mux(_T_51, _T_52, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_81 = mux(_T_57, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_82 = mux(_T_66, _T_67, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_83 = mux(_T_78, _T_79, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_84 = or(_T_80, _T_81) @[Mux.scala 27:72] + node _T_85 = or(_T_84, _T_82) @[Mux.scala 27:72] + node _T_86 = or(_T_85, _T_83) @[Mux.scala 27:72] + wire _T_87 : UInt<4> @[Mux.scala 27:72] + _T_87 <= _T_86 @[Mux.scala 27:72] + cam_wen <= _T_87 @[el2_dec_decode_ctl.scala 307:11] + cam_write <= io.lsu_nonblock_load_valid_m @[el2_dec_decode_ctl.scala 309:25] + node cam_write_tag = bits(io.lsu_nonblock_load_tag_m, 1, 0) @[el2_dec_decode_ctl.scala 310:54] + node cam_inv_reset_tag = bits(io.lsu_nonblock_load_inv_tag_r, 1, 0) @[el2_dec_decode_ctl.scala 313:59] + node cam_data_reset = or(io.lsu_nonblock_load_data_valid, io.lsu_nonblock_load_data_error) @[el2_dec_decode_ctl.scala 315:63] + node cam_data_reset_tag = bits(io.lsu_nonblock_load_data_tag, 1, 0) @[el2_dec_decode_ctl.scala 316:60] + node _T_88 = bits(x_d.i0load, 0, 0) @[el2_dec_decode_ctl.scala 318:43] + node nonblock_load_rd = mux(_T_88, x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 318:31] + node _T_89 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 322:116] + reg nonblock_load_valid_m_delay : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_89 : @[Reg.scala 28:19] + nonblock_load_valid_m_delay <= io.lsu_nonblock_load_valid_m @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node i0_load_kill_wen_r = and(nonblock_load_valid_m_delay, r_d.i0load) @[el2_dec_decode_ctl.scala 323:56] + node _T_90 = eq(cam_inv_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 325:66] + node _T_91 = and(io.lsu_nonblock_load_inv_r, _T_90) @[el2_dec_decode_ctl.scala 325:45] + node _T_92 = and(_T_91, cam[0].valid) @[el2_dec_decode_ctl.scala 325:82] + cam_inv_reset_val[0] <= _T_92 @[el2_dec_decode_ctl.scala 325:26] + node _T_93 = eq(cam_data_reset_tag, cam[0].tag) @[el2_dec_decode_ctl.scala 326:67] + node _T_94 = and(cam_data_reset, _T_93) @[el2_dec_decode_ctl.scala 326:45] + node _T_95 = and(_T_94, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 326:83] + cam_data_reset_val[0] <= _T_95 @[el2_dec_decode_ctl.scala 326:27] + wire _T_96 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28] + _T_96.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_96.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_96.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_96.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + cam_in[0].rd <= _T_96.rd @[el2_dec_decode_ctl.scala 327:14] + cam_in[0].tag <= _T_96.tag @[el2_dec_decode_ctl.scala 327:14] + cam_in[0].wb <= _T_96.wb @[el2_dec_decode_ctl.scala 327:14] + cam_in[0].valid <= _T_96.valid @[el2_dec_decode_ctl.scala 327:14] + cam[0].rd <= cam_raw[0].rd @[el2_dec_decode_ctl.scala 328:11] + cam[0].tag <= cam_raw[0].tag @[el2_dec_decode_ctl.scala 328:11] + cam[0].wb <= cam_raw[0].wb @[el2_dec_decode_ctl.scala 328:11] + cam[0].valid <= cam_raw[0].valid @[el2_dec_decode_ctl.scala 328:11] + node _T_97 = bits(cam_data_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 330:32] + when _T_97 : @[el2_dec_decode_ctl.scala 330:39] + cam[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] + skip @[el2_dec_decode_ctl.scala 330:39] + node _T_98 = bits(cam_wen, 0, 0) @[el2_dec_decode_ctl.scala 333:17] + node _T_99 = bits(_T_98, 0, 0) @[el2_dec_decode_ctl.scala 333:21] + when _T_99 : @[el2_dec_decode_ctl.scala 333:28] + cam_in[0].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] + cam_in[0].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27] + cam_in[0].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27] + cam_in[0].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27] + skip @[el2_dec_decode_ctl.scala 333:28] + else : @[el2_dec_decode_ctl.scala 338:116] + node _T_100 = bits(cam_inv_reset_val[0], 0, 0) @[el2_dec_decode_ctl.scala 338:37] + node _T_101 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] + node _T_102 = eq(r_d_in.i0rd, cam[0].rd) @[el2_dec_decode_ctl.scala 338:80] + node _T_103 = and(_T_101, _T_102) @[el2_dec_decode_ctl.scala 338:64] + node _T_104 = bits(cam[0].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108] + node _T_105 = and(_T_103, _T_104) @[el2_dec_decode_ctl.scala 338:95] + node _T_106 = or(_T_100, _T_105) @[el2_dec_decode_ctl.scala 338:44] + when _T_106 : @[el2_dec_decode_ctl.scala 338:116] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] + skip @[el2_dec_decode_ctl.scala 338:116] + else : @[el2_dec_decode_ctl.scala 340:16] + cam_in[0].rd <= cam[0].rd @[el2_dec_decode_ctl.scala 341:22] + cam_in[0].tag <= cam[0].tag @[el2_dec_decode_ctl.scala 341:22] + cam_in[0].wb <= cam[0].wb @[el2_dec_decode_ctl.scala 341:22] + cam_in[0].valid <= cam[0].valid @[el2_dec_decode_ctl.scala 341:22] + skip @[el2_dec_decode_ctl.scala 340:16] + node _T_107 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] + node _T_108 = eq(io.lsu_nonblock_load_inv_tag_r, cam[0].tag) @[el2_dec_decode_ctl.scala 343:79] + node _T_109 = and(_T_107, _T_108) @[el2_dec_decode_ctl.scala 343:44] + node _T_110 = eq(cam[0].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110] + node _T_111 = and(_T_109, _T_110) @[el2_dec_decode_ctl.scala 343:95] + when _T_111 : @[el2_dec_decode_ctl.scala 343:117] + cam_in[0].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20] + skip @[el2_dec_decode_ctl.scala 343:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] + cam_in[0].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] + skip @[el2_dec_decode_ctl.scala 347:32] + wire _T_112 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70] + _T_112.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_112.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_112.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_112.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + reg _T_113 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_112)) @[el2_dec_decode_ctl.scala 351:47] + _T_113.rd <= cam_in[0].rd @[el2_dec_decode_ctl.scala 351:47] + _T_113.tag <= cam_in[0].tag @[el2_dec_decode_ctl.scala 351:47] + _T_113.wb <= cam_in[0].wb @[el2_dec_decode_ctl.scala 351:47] + _T_113.valid <= cam_in[0].valid @[el2_dec_decode_ctl.scala 351:47] + cam_raw[0].rd <= _T_113.rd @[el2_dec_decode_ctl.scala 351:15] + cam_raw[0].tag <= _T_113.tag @[el2_dec_decode_ctl.scala 351:15] + cam_raw[0].wb <= _T_113.wb @[el2_dec_decode_ctl.scala 351:15] + cam_raw[0].valid <= _T_113.valid @[el2_dec_decode_ctl.scala 351:15] + node _T_114 = eq(io.lsu_nonblock_load_data_tag, cam_raw[0].tag) @[el2_dec_decode_ctl.scala 352:46] + node _T_115 = and(_T_114, cam_raw[0].valid) @[el2_dec_decode_ctl.scala 352:66] + nonblock_load_write[0] <= _T_115 @[el2_dec_decode_ctl.scala 352:28] + node _T_116 = eq(cam_inv_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 325:66] + node _T_117 = and(io.lsu_nonblock_load_inv_r, _T_116) @[el2_dec_decode_ctl.scala 325:45] + node _T_118 = and(_T_117, cam[1].valid) @[el2_dec_decode_ctl.scala 325:82] + cam_inv_reset_val[1] <= _T_118 @[el2_dec_decode_ctl.scala 325:26] + node _T_119 = eq(cam_data_reset_tag, cam[1].tag) @[el2_dec_decode_ctl.scala 326:67] + node _T_120 = and(cam_data_reset, _T_119) @[el2_dec_decode_ctl.scala 326:45] + node _T_121 = and(_T_120, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 326:83] + cam_data_reset_val[1] <= _T_121 @[el2_dec_decode_ctl.scala 326:27] + wire _T_122 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28] + _T_122.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_122.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_122.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_122.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + cam_in[1].rd <= _T_122.rd @[el2_dec_decode_ctl.scala 327:14] + cam_in[1].tag <= _T_122.tag @[el2_dec_decode_ctl.scala 327:14] + cam_in[1].wb <= _T_122.wb @[el2_dec_decode_ctl.scala 327:14] + cam_in[1].valid <= _T_122.valid @[el2_dec_decode_ctl.scala 327:14] + cam[1].rd <= cam_raw[1].rd @[el2_dec_decode_ctl.scala 328:11] + cam[1].tag <= cam_raw[1].tag @[el2_dec_decode_ctl.scala 328:11] + cam[1].wb <= cam_raw[1].wb @[el2_dec_decode_ctl.scala 328:11] + cam[1].valid <= cam_raw[1].valid @[el2_dec_decode_ctl.scala 328:11] + node _T_123 = bits(cam_data_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 330:32] + when _T_123 : @[el2_dec_decode_ctl.scala 330:39] + cam[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] + skip @[el2_dec_decode_ctl.scala 330:39] + node _T_124 = bits(cam_wen, 1, 1) @[el2_dec_decode_ctl.scala 333:17] + node _T_125 = bits(_T_124, 0, 0) @[el2_dec_decode_ctl.scala 333:21] + when _T_125 : @[el2_dec_decode_ctl.scala 333:28] + cam_in[1].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] + cam_in[1].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27] + cam_in[1].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27] + cam_in[1].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27] + skip @[el2_dec_decode_ctl.scala 333:28] + else : @[el2_dec_decode_ctl.scala 338:116] + node _T_126 = bits(cam_inv_reset_val[1], 0, 0) @[el2_dec_decode_ctl.scala 338:37] + node _T_127 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] + node _T_128 = eq(r_d_in.i0rd, cam[1].rd) @[el2_dec_decode_ctl.scala 338:80] + node _T_129 = and(_T_127, _T_128) @[el2_dec_decode_ctl.scala 338:64] + node _T_130 = bits(cam[1].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108] + node _T_131 = and(_T_129, _T_130) @[el2_dec_decode_ctl.scala 338:95] + node _T_132 = or(_T_126, _T_131) @[el2_dec_decode_ctl.scala 338:44] + when _T_132 : @[el2_dec_decode_ctl.scala 338:116] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] + skip @[el2_dec_decode_ctl.scala 338:116] + else : @[el2_dec_decode_ctl.scala 340:16] + cam_in[1].rd <= cam[1].rd @[el2_dec_decode_ctl.scala 341:22] + cam_in[1].tag <= cam[1].tag @[el2_dec_decode_ctl.scala 341:22] + cam_in[1].wb <= cam[1].wb @[el2_dec_decode_ctl.scala 341:22] + cam_in[1].valid <= cam[1].valid @[el2_dec_decode_ctl.scala 341:22] + skip @[el2_dec_decode_ctl.scala 340:16] + node _T_133 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] + node _T_134 = eq(io.lsu_nonblock_load_inv_tag_r, cam[1].tag) @[el2_dec_decode_ctl.scala 343:79] + node _T_135 = and(_T_133, _T_134) @[el2_dec_decode_ctl.scala 343:44] + node _T_136 = eq(cam[1].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110] + node _T_137 = and(_T_135, _T_136) @[el2_dec_decode_ctl.scala 343:95] + when _T_137 : @[el2_dec_decode_ctl.scala 343:117] + cam_in[1].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20] + skip @[el2_dec_decode_ctl.scala 343:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] + cam_in[1].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] + skip @[el2_dec_decode_ctl.scala 347:32] + wire _T_138 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70] + _T_138.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_138.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_138.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_138.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + reg _T_139 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_138)) @[el2_dec_decode_ctl.scala 351:47] + _T_139.rd <= cam_in[1].rd @[el2_dec_decode_ctl.scala 351:47] + _T_139.tag <= cam_in[1].tag @[el2_dec_decode_ctl.scala 351:47] + _T_139.wb <= cam_in[1].wb @[el2_dec_decode_ctl.scala 351:47] + _T_139.valid <= cam_in[1].valid @[el2_dec_decode_ctl.scala 351:47] + cam_raw[1].rd <= _T_139.rd @[el2_dec_decode_ctl.scala 351:15] + cam_raw[1].tag <= _T_139.tag @[el2_dec_decode_ctl.scala 351:15] + cam_raw[1].wb <= _T_139.wb @[el2_dec_decode_ctl.scala 351:15] + cam_raw[1].valid <= _T_139.valid @[el2_dec_decode_ctl.scala 351:15] + node _T_140 = eq(io.lsu_nonblock_load_data_tag, cam_raw[1].tag) @[el2_dec_decode_ctl.scala 352:46] + node _T_141 = and(_T_140, cam_raw[1].valid) @[el2_dec_decode_ctl.scala 352:66] + nonblock_load_write[1] <= _T_141 @[el2_dec_decode_ctl.scala 352:28] + node _T_142 = eq(cam_inv_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 325:66] + node _T_143 = and(io.lsu_nonblock_load_inv_r, _T_142) @[el2_dec_decode_ctl.scala 325:45] + node _T_144 = and(_T_143, cam[2].valid) @[el2_dec_decode_ctl.scala 325:82] + cam_inv_reset_val[2] <= _T_144 @[el2_dec_decode_ctl.scala 325:26] + node _T_145 = eq(cam_data_reset_tag, cam[2].tag) @[el2_dec_decode_ctl.scala 326:67] + node _T_146 = and(cam_data_reset, _T_145) @[el2_dec_decode_ctl.scala 326:45] + node _T_147 = and(_T_146, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 326:83] + cam_data_reset_val[2] <= _T_147 @[el2_dec_decode_ctl.scala 326:27] + wire _T_148 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28] + _T_148.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_148.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_148.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_148.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + cam_in[2].rd <= _T_148.rd @[el2_dec_decode_ctl.scala 327:14] + cam_in[2].tag <= _T_148.tag @[el2_dec_decode_ctl.scala 327:14] + cam_in[2].wb <= _T_148.wb @[el2_dec_decode_ctl.scala 327:14] + cam_in[2].valid <= _T_148.valid @[el2_dec_decode_ctl.scala 327:14] + cam[2].rd <= cam_raw[2].rd @[el2_dec_decode_ctl.scala 328:11] + cam[2].tag <= cam_raw[2].tag @[el2_dec_decode_ctl.scala 328:11] + cam[2].wb <= cam_raw[2].wb @[el2_dec_decode_ctl.scala 328:11] + cam[2].valid <= cam_raw[2].valid @[el2_dec_decode_ctl.scala 328:11] + node _T_149 = bits(cam_data_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 330:32] + when _T_149 : @[el2_dec_decode_ctl.scala 330:39] + cam[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] + skip @[el2_dec_decode_ctl.scala 330:39] + node _T_150 = bits(cam_wen, 2, 2) @[el2_dec_decode_ctl.scala 333:17] + node _T_151 = bits(_T_150, 0, 0) @[el2_dec_decode_ctl.scala 333:21] + when _T_151 : @[el2_dec_decode_ctl.scala 333:28] + cam_in[2].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] + cam_in[2].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27] + cam_in[2].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27] + cam_in[2].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27] + skip @[el2_dec_decode_ctl.scala 333:28] + else : @[el2_dec_decode_ctl.scala 338:116] + node _T_152 = bits(cam_inv_reset_val[2], 0, 0) @[el2_dec_decode_ctl.scala 338:37] + node _T_153 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] + node _T_154 = eq(r_d_in.i0rd, cam[2].rd) @[el2_dec_decode_ctl.scala 338:80] + node _T_155 = and(_T_153, _T_154) @[el2_dec_decode_ctl.scala 338:64] + node _T_156 = bits(cam[2].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108] + node _T_157 = and(_T_155, _T_156) @[el2_dec_decode_ctl.scala 338:95] + node _T_158 = or(_T_152, _T_157) @[el2_dec_decode_ctl.scala 338:44] + when _T_158 : @[el2_dec_decode_ctl.scala 338:116] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] + skip @[el2_dec_decode_ctl.scala 338:116] + else : @[el2_dec_decode_ctl.scala 340:16] + cam_in[2].rd <= cam[2].rd @[el2_dec_decode_ctl.scala 341:22] + cam_in[2].tag <= cam[2].tag @[el2_dec_decode_ctl.scala 341:22] + cam_in[2].wb <= cam[2].wb @[el2_dec_decode_ctl.scala 341:22] + cam_in[2].valid <= cam[2].valid @[el2_dec_decode_ctl.scala 341:22] + skip @[el2_dec_decode_ctl.scala 340:16] + node _T_159 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] + node _T_160 = eq(io.lsu_nonblock_load_inv_tag_r, cam[2].tag) @[el2_dec_decode_ctl.scala 343:79] + node _T_161 = and(_T_159, _T_160) @[el2_dec_decode_ctl.scala 343:44] + node _T_162 = eq(cam[2].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110] + node _T_163 = and(_T_161, _T_162) @[el2_dec_decode_ctl.scala 343:95] + when _T_163 : @[el2_dec_decode_ctl.scala 343:117] + cam_in[2].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20] + skip @[el2_dec_decode_ctl.scala 343:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] + cam_in[2].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] + skip @[el2_dec_decode_ctl.scala 347:32] + wire _T_164 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70] + _T_164.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_164.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_164.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_164.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + reg _T_165 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_164)) @[el2_dec_decode_ctl.scala 351:47] + _T_165.rd <= cam_in[2].rd @[el2_dec_decode_ctl.scala 351:47] + _T_165.tag <= cam_in[2].tag @[el2_dec_decode_ctl.scala 351:47] + _T_165.wb <= cam_in[2].wb @[el2_dec_decode_ctl.scala 351:47] + _T_165.valid <= cam_in[2].valid @[el2_dec_decode_ctl.scala 351:47] + cam_raw[2].rd <= _T_165.rd @[el2_dec_decode_ctl.scala 351:15] + cam_raw[2].tag <= _T_165.tag @[el2_dec_decode_ctl.scala 351:15] + cam_raw[2].wb <= _T_165.wb @[el2_dec_decode_ctl.scala 351:15] + cam_raw[2].valid <= _T_165.valid @[el2_dec_decode_ctl.scala 351:15] + node _T_166 = eq(io.lsu_nonblock_load_data_tag, cam_raw[2].tag) @[el2_dec_decode_ctl.scala 352:46] + node _T_167 = and(_T_166, cam_raw[2].valid) @[el2_dec_decode_ctl.scala 352:66] + nonblock_load_write[2] <= _T_167 @[el2_dec_decode_ctl.scala 352:28] + node _T_168 = eq(cam_inv_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 325:66] + node _T_169 = and(io.lsu_nonblock_load_inv_r, _T_168) @[el2_dec_decode_ctl.scala 325:45] + node _T_170 = and(_T_169, cam[3].valid) @[el2_dec_decode_ctl.scala 325:82] + cam_inv_reset_val[3] <= _T_170 @[el2_dec_decode_ctl.scala 325:26] + node _T_171 = eq(cam_data_reset_tag, cam[3].tag) @[el2_dec_decode_ctl.scala 326:67] + node _T_172 = and(cam_data_reset, _T_171) @[el2_dec_decode_ctl.scala 326:45] + node _T_173 = and(_T_172, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 326:83] + cam_data_reset_val[3] <= _T_173 @[el2_dec_decode_ctl.scala 326:27] + wire _T_174 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 327:28] + _T_174.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_174.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_174.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + _T_174.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 327:28] + cam_in[3].rd <= _T_174.rd @[el2_dec_decode_ctl.scala 327:14] + cam_in[3].tag <= _T_174.tag @[el2_dec_decode_ctl.scala 327:14] + cam_in[3].wb <= _T_174.wb @[el2_dec_decode_ctl.scala 327:14] + cam_in[3].valid <= _T_174.valid @[el2_dec_decode_ctl.scala 327:14] + cam[3].rd <= cam_raw[3].rd @[el2_dec_decode_ctl.scala 328:11] + cam[3].tag <= cam_raw[3].tag @[el2_dec_decode_ctl.scala 328:11] + cam[3].wb <= cam_raw[3].wb @[el2_dec_decode_ctl.scala 328:11] + cam[3].valid <= cam_raw[3].valid @[el2_dec_decode_ctl.scala 328:11] + node _T_175 = bits(cam_data_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 330:32] + when _T_175 : @[el2_dec_decode_ctl.scala 330:39] + cam[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 331:20] + skip @[el2_dec_decode_ctl.scala 330:39] + node _T_176 = bits(cam_wen, 3, 3) @[el2_dec_decode_ctl.scala 333:17] + node _T_177 = bits(_T_176, 0, 0) @[el2_dec_decode_ctl.scala 333:21] + when _T_177 : @[el2_dec_decode_ctl.scala 333:28] + cam_in[3].valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 334:27] + cam_in[3].wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 335:27] + cam_in[3].tag <= cam_write_tag @[el2_dec_decode_ctl.scala 336:27] + cam_in[3].rd <= nonblock_load_rd @[el2_dec_decode_ctl.scala 337:27] + skip @[el2_dec_decode_ctl.scala 333:28] + else : @[el2_dec_decode_ctl.scala 338:116] + node _T_178 = bits(cam_inv_reset_val[3], 0, 0) @[el2_dec_decode_ctl.scala 338:37] + node _T_179 = bits(i0_wen_r, 0, 0) @[el2_dec_decode_ctl.scala 338:57] + node _T_180 = eq(r_d_in.i0rd, cam[3].rd) @[el2_dec_decode_ctl.scala 338:80] + node _T_181 = and(_T_179, _T_180) @[el2_dec_decode_ctl.scala 338:64] + node _T_182 = bits(cam[3].wb, 0, 0) @[el2_dec_decode_ctl.scala 338:108] + node _T_183 = and(_T_181, _T_182) @[el2_dec_decode_ctl.scala 338:95] + node _T_184 = or(_T_178, _T_183) @[el2_dec_decode_ctl.scala 338:44] + when _T_184 : @[el2_dec_decode_ctl.scala 338:116] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 339:23] + skip @[el2_dec_decode_ctl.scala 338:116] + else : @[el2_dec_decode_ctl.scala 340:16] + cam_in[3].rd <= cam[3].rd @[el2_dec_decode_ctl.scala 341:22] + cam_in[3].tag <= cam[3].tag @[el2_dec_decode_ctl.scala 341:22] + cam_in[3].wb <= cam[3].wb @[el2_dec_decode_ctl.scala 341:22] + cam_in[3].valid <= cam[3].valid @[el2_dec_decode_ctl.scala 341:22] + skip @[el2_dec_decode_ctl.scala 340:16] + node _T_185 = eq(nonblock_load_valid_m_delay, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:37] + node _T_186 = eq(io.lsu_nonblock_load_inv_tag_r, cam[3].tag) @[el2_dec_decode_ctl.scala 343:79] + node _T_187 = and(_T_185, _T_186) @[el2_dec_decode_ctl.scala 343:44] + node _T_188 = eq(cam[3].valid, UInt<1>("h01")) @[el2_dec_decode_ctl.scala 343:110] + node _T_189 = and(_T_187, _T_188) @[el2_dec_decode_ctl.scala 343:95] + when _T_189 : @[el2_dec_decode_ctl.scala 343:117] + cam_in[3].wb <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 344:20] + skip @[el2_dec_decode_ctl.scala 343:117] + when io.dec_tlu_force_halt : @[el2_dec_decode_ctl.scala 347:32] + cam_in[3].valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 348:23] + skip @[el2_dec_decode_ctl.scala 347:32] + wire _T_190 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>} @[el2_dec_decode_ctl.scala 351:70] + _T_190.rd <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_190.tag <= UInt<3>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_190.wb <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + _T_190.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 351:70] + reg _T_191 : {valid : UInt<1>, wb : UInt<1>, tag : UInt<3>, rd : UInt<5>}, io.free_clk with : (reset => (reset, _T_190)) @[el2_dec_decode_ctl.scala 351:47] + _T_191.rd <= cam_in[3].rd @[el2_dec_decode_ctl.scala 351:47] + _T_191.tag <= cam_in[3].tag @[el2_dec_decode_ctl.scala 351:47] + _T_191.wb <= cam_in[3].wb @[el2_dec_decode_ctl.scala 351:47] + _T_191.valid <= cam_in[3].valid @[el2_dec_decode_ctl.scala 351:47] + cam_raw[3].rd <= _T_191.rd @[el2_dec_decode_ctl.scala 351:15] + cam_raw[3].tag <= _T_191.tag @[el2_dec_decode_ctl.scala 351:15] + cam_raw[3].wb <= _T_191.wb @[el2_dec_decode_ctl.scala 351:15] + cam_raw[3].valid <= _T_191.valid @[el2_dec_decode_ctl.scala 351:15] + node _T_192 = eq(io.lsu_nonblock_load_data_tag, cam_raw[3].tag) @[el2_dec_decode_ctl.scala 352:46] + node _T_193 = and(_T_192, cam_raw[3].valid) @[el2_dec_decode_ctl.scala 352:66] + nonblock_load_write[3] <= _T_193 @[el2_dec_decode_ctl.scala 352:28] + io.dec_nonblock_load_waddr <= UInt<5>("h00") @[el2_dec_decode_ctl.scala 355:29] + node _T_194 = eq(r_d_in.i0rd, io.dec_nonblock_load_waddr) @[el2_dec_decode_ctl.scala 357:44] + node nonblock_load_cancel = and(_T_194, i0_wen_r) @[el2_dec_decode_ctl.scala 357:76] + node _T_195 = or(nonblock_load_write[0], nonblock_load_write[1]) @[el2_dec_decode_ctl.scala 358:95] + node _T_196 = or(_T_195, nonblock_load_write[2]) @[el2_dec_decode_ctl.scala 358:95] + node _T_197 = or(_T_196, nonblock_load_write[3]) @[el2_dec_decode_ctl.scala 358:95] + node _T_198 = bits(_T_197, 0, 0) @[el2_dec_decode_ctl.scala 358:99] + node _T_199 = and(io.lsu_nonblock_load_data_valid, _T_198) @[el2_dec_decode_ctl.scala 358:64] + node _T_200 = eq(nonblock_load_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 358:109] + node _T_201 = and(_T_199, _T_200) @[el2_dec_decode_ctl.scala 358:106] + io.dec_nonblock_load_wen <= _T_201 @[el2_dec_decode_ctl.scala 358:28] + node _T_202 = eq(nonblock_load_rd, i0r.rs1) @[el2_dec_decode_ctl.scala 359:54] + node _T_203 = and(_T_202, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:66] + node _T_204 = and(_T_203, io.dec_i0_rs1_en_d) @[el2_dec_decode_ctl.scala 359:97] + node _T_205 = eq(nonblock_load_rd, i0r.rs2) @[el2_dec_decode_ctl.scala 359:137] + node _T_206 = and(_T_205, io.lsu_nonblock_load_valid_m) @[el2_dec_decode_ctl.scala 359:149] + node _T_207 = and(_T_206, io.dec_i0_rs2_en_d) @[el2_dec_decode_ctl.scala 359:180] + node i0_nonblock_boundary_stall = or(_T_204, _T_207) @[el2_dec_decode_ctl.scala 359:118] + i0_nonblock_load_stall <= i0_nonblock_boundary_stall @[el2_dec_decode_ctl.scala 361:26] + node _T_208 = bits(nonblock_load_write[0], 0, 0) @[Bitwise.scala 72:15] + node _T_209 = mux(_T_208, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_210 = and(_T_209, cam[0].rd) @[el2_dec_decode_ctl.scala 363:88] + node _T_211 = and(io.dec_i0_rs1_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:121] + node _T_212 = eq(cam[0].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149] + node _T_213 = and(_T_211, _T_212) @[el2_dec_decode_ctl.scala 363:136] + node _T_214 = and(io.dec_i0_rs2_en_d, cam[0].valid) @[el2_dec_decode_ctl.scala 363:182] + node _T_215 = eq(cam[0].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210] + node _T_216 = and(_T_214, _T_215) @[el2_dec_decode_ctl.scala 363:197] + node _T_217 = bits(nonblock_load_write[1], 0, 0) @[Bitwise.scala 72:15] + node _T_218 = mux(_T_217, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_219 = and(_T_218, cam[1].rd) @[el2_dec_decode_ctl.scala 363:88] + node _T_220 = and(io.dec_i0_rs1_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:121] + node _T_221 = eq(cam[1].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149] + node _T_222 = and(_T_220, _T_221) @[el2_dec_decode_ctl.scala 363:136] + node _T_223 = and(io.dec_i0_rs2_en_d, cam[1].valid) @[el2_dec_decode_ctl.scala 363:182] + node _T_224 = eq(cam[1].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210] + node _T_225 = and(_T_223, _T_224) @[el2_dec_decode_ctl.scala 363:197] + node _T_226 = bits(nonblock_load_write[2], 0, 0) @[Bitwise.scala 72:15] + node _T_227 = mux(_T_226, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_228 = and(_T_227, cam[2].rd) @[el2_dec_decode_ctl.scala 363:88] + node _T_229 = and(io.dec_i0_rs1_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:121] + node _T_230 = eq(cam[2].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149] + node _T_231 = and(_T_229, _T_230) @[el2_dec_decode_ctl.scala 363:136] + node _T_232 = and(io.dec_i0_rs2_en_d, cam[2].valid) @[el2_dec_decode_ctl.scala 363:182] + node _T_233 = eq(cam[2].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210] + node _T_234 = and(_T_232, _T_233) @[el2_dec_decode_ctl.scala 363:197] + node _T_235 = bits(nonblock_load_write[3], 0, 0) @[Bitwise.scala 72:15] + node _T_236 = mux(_T_235, UInt<5>("h01f"), UInt<5>("h00")) @[Bitwise.scala 72:12] + node _T_237 = and(_T_236, cam[3].rd) @[el2_dec_decode_ctl.scala 363:88] + node _T_238 = and(io.dec_i0_rs1_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:121] + node _T_239 = eq(cam[3].rd, i0r.rs1) @[el2_dec_decode_ctl.scala 363:149] + node _T_240 = and(_T_238, _T_239) @[el2_dec_decode_ctl.scala 363:136] + node _T_241 = and(io.dec_i0_rs2_en_d, cam[3].valid) @[el2_dec_decode_ctl.scala 363:182] + node _T_242 = eq(cam[3].rd, i0r.rs2) @[el2_dec_decode_ctl.scala 363:210] + node _T_243 = and(_T_241, _T_242) @[el2_dec_decode_ctl.scala 363:197] + node _T_244 = or(_T_210, _T_219) @[el2_dec_decode_ctl.scala 364:69] + node _T_245 = or(_T_244, _T_228) @[el2_dec_decode_ctl.scala 364:69] + node waddr = or(_T_245, _T_237) @[el2_dec_decode_ctl.scala 364:69] + node _T_246 = or(_T_213, _T_222) @[el2_dec_decode_ctl.scala 364:102] + node _T_247 = or(_T_246, _T_231) @[el2_dec_decode_ctl.scala 364:102] + node ld_stall_1 = or(_T_247, _T_240) @[el2_dec_decode_ctl.scala 364:102] + node _T_248 = or(_T_216, _T_225) @[el2_dec_decode_ctl.scala 364:134] + node _T_249 = or(_T_248, _T_234) @[el2_dec_decode_ctl.scala 364:134] + node ld_stall_2 = or(_T_249, _T_243) @[el2_dec_decode_ctl.scala 364:134] + io.dec_nonblock_load_waddr <= waddr @[el2_dec_decode_ctl.scala 365:29] + node _T_250 = or(ld_stall_1, ld_stall_2) @[el2_dec_decode_ctl.scala 366:38] + node _T_251 = or(_T_250, i0_nonblock_boundary_stall) @[el2_dec_decode_ctl.scala 366:51] + i0_nonblock_load_stall <= _T_251 @[el2_dec_decode_ctl.scala 366:25] + node _T_252 = eq(i0_predict_br, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 375:34] + node i0_br_unpred = and(i0_dp.jal, _T_252) @[el2_dec_decode_ctl.scala 375:32] + node _T_253 = bits(i0_legal_decode_d, 0, 0) @[Bitwise.scala 72:15] + node _T_254 = mux(_T_253, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_255 = and(csr_read, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 387:16] + node _T_256 = bits(_T_255, 0, 0) @[el2_dec_decode_ctl.scala 387:30] + node _T_257 = eq(csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 388:6] + node _T_258 = and(_T_257, io.dec_csr_wen_unq_d) @[el2_dec_decode_ctl.scala 388:16] + node _T_259 = bits(_T_258, 0, 0) @[el2_dec_decode_ctl.scala 388:30] + node _T_260 = eq(io.dec_csr_wen_unq_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 389:18] + node _T_261 = and(csr_read, _T_260) @[el2_dec_decode_ctl.scala 389:16] + node _T_262 = bits(_T_261, 0, 0) @[el2_dec_decode_ctl.scala 389:30] + node _T_263 = mux(i0_dp.mul, UInt<4>("h01"), UInt<4>("h00")) @[Mux.scala 98:16] + node _T_264 = mux(i0_dp.load, UInt<4>("h02"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(i0_dp.store, UInt<4>("h03"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(i0_dp.pm_alu, UInt<4>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_262, UInt<4>("h05"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_259, UInt<4>("h06"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_256, UInt<4>("h07"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(i0_dp.ebreak, UInt<4>("h08"), _T_269) @[Mux.scala 98:16] + node _T_271 = mux(i0_dp.ecall, UInt<4>("h09"), _T_270) @[Mux.scala 98:16] + node _T_272 = mux(i0_dp.fence, UInt<4>("h0a"), _T_271) @[Mux.scala 98:16] + node _T_273 = mux(i0_dp.fence_i, UInt<4>("h0b"), _T_272) @[Mux.scala 98:16] + node _T_274 = mux(i0_dp.mret, UInt<4>("h0c"), _T_273) @[Mux.scala 98:16] + node _T_275 = mux(i0_dp.condbr, UInt<4>("h0d"), _T_274) @[Mux.scala 98:16] + node _T_276 = mux(i0_dp.jal, UInt<4>("h0e"), _T_275) @[Mux.scala 98:16] + node _T_277 = and(_T_254, _T_276) @[el2_dec_decode_ctl.scala 379:49] + d_t.pmu_i0_itype <= _T_277 @[el2_dec_decode_ctl.scala 379:21] + inst i0_dec of el2_dec_dec_ctl @[el2_dec_decode_ctl.scala 396:22] + i0_dec.clock <= clock + i0_dec.reset <= reset + i0_dec.io.ins <= io.dec_i0_instr_d @[el2_dec_decode_ctl.scala 397:16] + i0_dp_raw.legal <= i0_dec.io.out.legal @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.pm_alu <= i0_dec.io.out.pm_alu @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.fence_i <= i0_dec.io.out.fence_i @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.fence <= i0_dec.io.out.fence @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rem <= i0_dec.io.out.rem @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.div <= i0_dec.io.out.div @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.low <= i0_dec.io.out.low @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rs2_sign <= i0_dec.io.out.rs2_sign @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rs1_sign <= i0_dec.io.out.rs1_sign @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.mul <= i0_dec.io.out.mul @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.mret <= i0_dec.io.out.mret @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.ecall <= i0_dec.io.out.ecall @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.ebreak <= i0_dec.io.out.ebreak @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.postsync <= i0_dec.io.out.postsync @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.presync <= i0_dec.io.out.presync @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.csr_imm <= i0_dec.io.out.csr_imm @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.csr_write <= i0_dec.io.out.csr_write @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.csr_set <= i0_dec.io.out.csr_set @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.csr_clr <= i0_dec.io.out.csr_clr @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.csr_read <= i0_dec.io.out.csr_read @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.word <= i0_dec.io.out.word @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.half <= i0_dec.io.out.half @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.by <= i0_dec.io.out.by @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.jal <= i0_dec.io.out.jal @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.blt <= i0_dec.io.out.blt @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.bge <= i0_dec.io.out.bge @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.bne <= i0_dec.io.out.bne @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.beq <= i0_dec.io.out.beq @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.condbr <= i0_dec.io.out.condbr @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.unsign <= i0_dec.io.out.unsign @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.slt <= i0_dec.io.out.slt @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.srl <= i0_dec.io.out.srl @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.sra <= i0_dec.io.out.sra @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.sll <= i0_dec.io.out.sll @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.lxor <= i0_dec.io.out.lxor @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.lor <= i0_dec.io.out.lor @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.land <= i0_dec.io.out.land @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.sub <= i0_dec.io.out.sub @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.add <= i0_dec.io.out.add @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.lsu <= i0_dec.io.out.lsu @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.store <= i0_dec.io.out.store @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.load <= i0_dec.io.out.load @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.pc <= i0_dec.io.out.pc @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.imm20 <= i0_dec.io.out.imm20 @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.shimm5 <= i0_dec.io.out.shimm5 @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rd <= i0_dec.io.out.rd @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.imm12 <= i0_dec.io.out.imm12 @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rs2 <= i0_dec.io.out.rs2 @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.rs1 <= i0_dec.io.out.rs1 @[el2_dec_decode_ctl.scala 398:12] + i0_dp_raw.alu <= i0_dec.io.out.alu @[el2_dec_decode_ctl.scala 398:12] + reg _T_278 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 400:45] + _T_278 <= io.lsu_idle_any @[el2_dec_decode_ctl.scala 400:45] + lsu_idle <= _T_278 @[el2_dec_decode_ctl.scala 400:11] + node _T_279 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 403:73] + node _T_280 = and(leak1_i1_stall, _T_279) @[el2_dec_decode_ctl.scala 403:71] + node _T_281 = or(io.dec_tlu_flush_leak_one_r, _T_280) @[el2_dec_decode_ctl.scala 403:53] + leak1_i1_stall_in <= _T_281 @[el2_dec_decode_ctl.scala 403:21] + reg _T_282 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 404:56] + _T_282 <= leak1_i1_stall_in @[el2_dec_decode_ctl.scala 404:56] + leak1_i1_stall <= _T_282 @[el2_dec_decode_ctl.scala 404:21] + leak1_mode <= leak1_i1_stall @[el2_dec_decode_ctl.scala 405:14] + node _T_283 = and(io.dec_i0_decode_d, leak1_i1_stall) @[el2_dec_decode_ctl.scala 406:45] + node _T_284 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 406:83] + node _T_285 = and(leak1_i0_stall, _T_284) @[el2_dec_decode_ctl.scala 406:81] + node _T_286 = or(_T_283, _T_285) @[el2_dec_decode_ctl.scala 406:63] + leak1_i0_stall_in <= _T_286 @[el2_dec_decode_ctl.scala 406:21] + reg _T_287 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 407:56] + _T_287 <= leak1_i0_stall_in @[el2_dec_decode_ctl.scala 407:56] + leak1_i0_stall <= _T_287 @[el2_dec_decode_ctl.scala 407:21] + node _T_288 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 411:29] + node _T_289 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 411:36] + node _T_290 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 411:46] + node _T_291 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 411:53] + node _T_292 = cat(_T_291, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_293 = cat(_T_288, _T_289) @[Cat.scala 29:58] + node _T_294 = cat(_T_293, _T_290) @[Cat.scala 29:58] + node i0_pcall_imm = cat(_T_294, _T_292) @[Cat.scala 29:58] + node _T_295 = bits(i0_pcall_imm, 12, 12) @[el2_dec_decode_ctl.scala 412:46] + node _T_296 = bits(_T_295, 0, 0) @[el2_dec_decode_ctl.scala 412:51] + node _T_297 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:71] + node _T_298 = eq(_T_297, UInt<8>("h0ff")) @[el2_dec_decode_ctl.scala 412:79] + node _T_299 = bits(i0_pcall_imm, 20, 13) @[el2_dec_decode_ctl.scala 412:104] + node _T_300 = eq(_T_299, UInt<8>("h00")) @[el2_dec_decode_ctl.scala 412:112] + node i0_pcall_12b_offset = mux(_T_296, _T_298, _T_300) @[el2_dec_decode_ctl.scala 412:33] + node _T_301 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 413:47] + node _T_302 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 413:76] + node _T_303 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 413:98] + node _T_304 = or(_T_302, _T_303) @[el2_dec_decode_ctl.scala 413:89] + node i0_pcall_case = and(_T_301, _T_304) @[el2_dec_decode_ctl.scala 413:65] + node _T_305 = and(i0_pcall_12b_offset, i0_dp_raw.imm20) @[el2_dec_decode_ctl.scala 414:47] + node _T_306 = eq(i0r.rd, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 414:76] + node _T_307 = eq(i0r.rd, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 414:98] + node _T_308 = or(_T_306, _T_307) @[el2_dec_decode_ctl.scala 414:89] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 414:67] + node i0_pja_case = and(_T_305, _T_309) @[el2_dec_decode_ctl.scala 414:65] + node _T_310 = and(i0_dp_raw.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 415:38] + i0_pcall_raw <= _T_310 @[el2_dec_decode_ctl.scala 415:20] + node _T_311 = and(i0_dp.jal, i0_pcall_case) @[el2_dec_decode_ctl.scala 416:38] + i0_pcall <= _T_311 @[el2_dec_decode_ctl.scala 416:20] + node _T_312 = and(i0_dp_raw.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 417:38] + i0_pja_raw <= _T_312 @[el2_dec_decode_ctl.scala 417:20] + node _T_313 = and(i0_dp.jal, i0_pja_case) @[el2_dec_decode_ctl.scala 418:38] + i0_pja <= _T_313 @[el2_dec_decode_ctl.scala 418:20] + node _T_314 = or(i0_pcall_raw, i0_pja_raw) @[el2_dec_decode_ctl.scala 419:41] + node _T_315 = bits(_T_314, 0, 0) @[el2_dec_decode_ctl.scala 419:55] + node _T_316 = bits(i0_pcall_imm, 12, 1) @[el2_dec_decode_ctl.scala 419:75] + node _T_317 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 419:90] + node _T_318 = bits(io.dec_i0_instr_d, 7, 7) @[el2_dec_decode_ctl.scala 419:97] + node _T_319 = bits(io.dec_i0_instr_d, 30, 25) @[el2_dec_decode_ctl.scala 419:103] + node _T_320 = bits(io.dec_i0_instr_d, 11, 8) @[el2_dec_decode_ctl.scala 419:113] + node _T_321 = cat(_T_319, _T_320) @[Cat.scala 29:58] + node _T_322 = cat(_T_317, _T_318) @[Cat.scala 29:58] + node _T_323 = cat(_T_322, _T_321) @[Cat.scala 29:58] + node _T_324 = mux(_T_315, _T_316, _T_323) @[el2_dec_decode_ctl.scala 419:26] + i0_br_offset <= _T_324 @[el2_dec_decode_ctl.scala 419:20] + node _T_325 = and(i0_dp_raw.jal, i0_dp_raw.imm12) @[el2_dec_decode_ctl.scala 421:37] + node _T_326 = eq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 421:65] + node _T_327 = and(_T_325, _T_326) @[el2_dec_decode_ctl.scala 421:55] + node _T_328 = eq(i0r.rs1, UInt<5>("h01")) @[el2_dec_decode_ctl.scala 421:89] + node _T_329 = eq(i0r.rs1, UInt<5>("h05")) @[el2_dec_decode_ctl.scala 421:111] + node _T_330 = or(_T_328, _T_329) @[el2_dec_decode_ctl.scala 421:101] + node i0_pret_case = and(_T_327, _T_330) @[el2_dec_decode_ctl.scala 421:79] + node _T_331 = and(i0_dp_raw.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 422:32] + i0_pret_raw <= _T_331 @[el2_dec_decode_ctl.scala 422:15] + node _T_332 = and(i0_dp.jal, i0_pret_case) @[el2_dec_decode_ctl.scala 423:32] + i0_pret <= _T_332 @[el2_dec_decode_ctl.scala 423:15] + node _T_333 = eq(i0_pcall_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:35] + node _T_334 = and(i0_dp.jal, _T_333) @[el2_dec_decode_ctl.scala 424:32] + node _T_335 = eq(i0_pja_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:52] + node _T_336 = and(_T_334, _T_335) @[el2_dec_decode_ctl.scala 424:50] + node _T_337 = eq(i0_pret_case, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 424:67] + node _T_338 = and(_T_336, _T_337) @[el2_dec_decode_ctl.scala 424:65] + i0_jal <= _T_338 @[el2_dec_decode_ctl.scala 424:15] + io.div_p.valid <= div_decode_d @[el2_dec_decode_ctl.scala 427:21] + io.div_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 428:21] + io.div_p.rem <= i0_dp.rem @[el2_dec_decode_ctl.scala 429:21] + io.mul_p.valid <= mul_decode_d @[el2_dec_decode_ctl.scala 431:21] + io.mul_p.rs1_sign <= i0_dp.rs1_sign @[el2_dec_decode_ctl.scala 432:21] + io.mul_p.rs2_sign <= i0_dp.rs2_sign @[el2_dec_decode_ctl.scala 433:21] + io.mul_p.low <= i0_dp.low @[el2_dec_decode_ctl.scala 434:21] + reg _T_339 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 436:58] + _T_339 <= io.dec_tlu_flush_extint @[el2_dec_decode_ctl.scala 436:58] + io.dec_extint_stall <= _T_339 @[el2_dec_decode_ctl.scala 436:23] + wire _T_340 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_dec_decode_ctl.scala 438:27] + _T_340.valid <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.load_ldst_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.store_data_bypass_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.dma <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.unsign <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.store <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.dword <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.word <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.half <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.by <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + _T_340.fast_int <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 438:27] + io.lsu_p.valid <= _T_340.valid @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.store_data_bypass_m <= _T_340.store_data_bypass_m @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.load_ldst_bypass_d <= _T_340.load_ldst_bypass_d @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.store_data_bypass_d <= _T_340.store_data_bypass_d @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.dma <= _T_340.dma @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.unsign <= _T_340.unsign @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.store <= _T_340.store @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.load <= _T_340.load @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.dword <= _T_340.dword @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.word <= _T_340.word @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.half <= _T_340.half @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.by <= _T_340.by @[el2_dec_decode_ctl.scala 438:12] + io.lsu_p.fast_int <= _T_340.fast_int @[el2_dec_decode_ctl.scala 438:12] + when io.dec_extint_stall : @[el2_dec_decode_ctl.scala 439:29] + io.lsu_p.load <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 440:24] + io.lsu_p.word <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 441:24] + io.lsu_p.fast_int <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 442:24] + io.lsu_p.valid <= UInt<1>("h01") @[el2_dec_decode_ctl.scala 443:24] + skip @[el2_dec_decode_ctl.scala 439:29] + else : @[el2_dec_decode_ctl.scala 444:15] + io.lsu_p.valid <= lsu_decode_d @[el2_dec_decode_ctl.scala 445:35] + io.lsu_p.load <= i0_dp.load @[el2_dec_decode_ctl.scala 446:35] + io.lsu_p.store <= i0_dp.store @[el2_dec_decode_ctl.scala 447:35] + io.lsu_p.by <= i0_dp.by @[el2_dec_decode_ctl.scala 448:35] + io.lsu_p.half <= i0_dp.half @[el2_dec_decode_ctl.scala 449:35] + io.lsu_p.word <= i0_dp.word @[el2_dec_decode_ctl.scala 450:35] + io.lsu_p.load_ldst_bypass_d <= load_ldst_bypass_d @[el2_dec_decode_ctl.scala 451:35] + io.lsu_p.store_data_bypass_d <= store_data_bypass_d @[el2_dec_decode_ctl.scala 452:35] + io.lsu_p.store_data_bypass_m <= store_data_bypass_m @[el2_dec_decode_ctl.scala 453:35] + io.lsu_p.unsign <= i0_dp.unsign @[el2_dec_decode_ctl.scala 454:35] + skip @[el2_dec_decode_ctl.scala 444:15] + io.dec_csr_ren_d <= i0_dp.csr_read @[el2_dec_decode_ctl.scala 458:21] + node _T_341 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 459:56] + node _T_342 = and(i0_dp.csr_read, _T_341) @[el2_dec_decode_ctl.scala 459:36] + csr_read <= _T_342 @[el2_dec_decode_ctl.scala 459:18] + node _T_343 = eq(io.dec_debug_fence_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 461:42] + node i0_csr_write = and(i0_dp.csr_write, _T_343) @[el2_dec_decode_ctl.scala 461:40] + node _T_344 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 462:61] + node csr_clr_d = and(i0_dp.csr_clr, _T_344) @[el2_dec_decode_ctl.scala 462:41] + node _T_345 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 463:59] + node csr_set_d = and(i0_dp.csr_set, _T_345) @[el2_dec_decode_ctl.scala 463:39] + node _T_346 = bits(i0_legal_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 464:59] + node csr_write_d = and(i0_csr_write, _T_346) @[el2_dec_decode_ctl.scala 464:39] + node _T_347 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 466:41] + node _T_348 = and(i0_csr_write, _T_347) @[el2_dec_decode_ctl.scala 466:39] + i0_csr_write_only_d <= _T_348 @[el2_dec_decode_ctl.scala 466:23] + node _T_349 = or(i0_dp.csr_clr, i0_dp.csr_set) @[el2_dec_decode_ctl.scala 467:42] + node _T_350 = or(_T_349, i0_csr_write) @[el2_dec_decode_ctl.scala 467:58] + io.dec_csr_wen_unq_d <= _T_350 @[el2_dec_decode_ctl.scala 467:24] + node _T_351 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 470:30] + io.dec_csr_rdaddr_d <= _T_351 @[el2_dec_decode_ctl.scala 470:24] + io.dec_csr_wraddr_r <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 471:23] + node _T_352 = and(r_d.csrwen, r_d.i0valid) @[el2_dec_decode_ctl.scala 475:34] + node _T_353 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 475:50] + node _T_354 = and(_T_352, _T_353) @[el2_dec_decode_ctl.scala 475:48] + io.dec_csr_wen_r <= _T_354 @[el2_dec_decode_ctl.scala 475:20] + node _T_355 = eq(r_d.csrwaddr, UInt<10>("h0300")) @[el2_dec_decode_ctl.scala 478:45] + node _T_356 = eq(r_d.csrwaddr, UInt<10>("h0304")) @[el2_dec_decode_ctl.scala 478:75] + node _T_357 = or(_T_355, _T_356) @[el2_dec_decode_ctl.scala 478:59] + node _T_358 = and(_T_357, r_d.csrwen) @[el2_dec_decode_ctl.scala 478:90] + node _T_359 = and(_T_358, r_d.i0valid) @[el2_dec_decode_ctl.scala 478:103] + node _T_360 = eq(io.dec_tlu_i0_kill_writeb_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 478:119] + node _T_361 = and(_T_359, _T_360) @[el2_dec_decode_ctl.scala 478:117] + io.dec_csr_stall_int_ff <= _T_361 @[el2_dec_decode_ctl.scala 478:27] + reg csr_read_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 480:52] + csr_read_x <= csr_read @[el2_dec_decode_ctl.scala 480:52] + reg csr_clr_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 481:51] + csr_clr_x <= csr_clr_d @[el2_dec_decode_ctl.scala 481:51] + reg csr_set_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 482:51] + csr_set_x <= csr_set_d @[el2_dec_decode_ctl.scala 482:51] + reg csr_write_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 483:53] + csr_write_x <= csr_write_d @[el2_dec_decode_ctl.scala 483:53] + reg csr_imm_x : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 484:51] + csr_imm_x <= i0_dp.csr_imm @[el2_dec_decode_ctl.scala 484:51] + node _T_362 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 487:27] + node _T_363 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 487:48] + inst rvclkhdr of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_363 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg csrimm_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + csrimm_x <= _T_362 @[el2_lib.scala 514:16] + node _T_364 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 488:62] + inst rvclkhdr_1 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_364 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg csr_rddata_x : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + csr_rddata_x <= io.dec_csr_rddata_d @[el2_lib.scala 514:16] + node _T_365 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 491:15] + wire _T_366 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_366[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_366[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_367 = cat(_T_366[0], _T_366[1]) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_366[2]) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_366[3]) @[Cat.scala 29:58] + node _T_370 = cat(_T_369, _T_366[4]) @[Cat.scala 29:58] + node _T_371 = cat(_T_370, _T_366[5]) @[Cat.scala 29:58] + node _T_372 = cat(_T_371, _T_366[6]) @[Cat.scala 29:58] + node _T_373 = cat(_T_372, _T_366[7]) @[Cat.scala 29:58] + node _T_374 = cat(_T_373, _T_366[8]) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_366[9]) @[Cat.scala 29:58] + node _T_376 = cat(_T_375, _T_366[10]) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_366[11]) @[Cat.scala 29:58] + node _T_378 = cat(_T_377, _T_366[12]) @[Cat.scala 29:58] + node _T_379 = cat(_T_378, _T_366[13]) @[Cat.scala 29:58] + node _T_380 = cat(_T_379, _T_366[14]) @[Cat.scala 29:58] + node _T_381 = cat(_T_380, _T_366[15]) @[Cat.scala 29:58] + node _T_382 = cat(_T_381, _T_366[16]) @[Cat.scala 29:58] + node _T_383 = cat(_T_382, _T_366[17]) @[Cat.scala 29:58] + node _T_384 = cat(_T_383, _T_366[18]) @[Cat.scala 29:58] + node _T_385 = cat(_T_384, _T_366[19]) @[Cat.scala 29:58] + node _T_386 = cat(_T_385, _T_366[20]) @[Cat.scala 29:58] + node _T_387 = cat(_T_386, _T_366[21]) @[Cat.scala 29:58] + node _T_388 = cat(_T_387, _T_366[22]) @[Cat.scala 29:58] + node _T_389 = cat(_T_388, _T_366[23]) @[Cat.scala 29:58] + node _T_390 = cat(_T_389, _T_366[24]) @[Cat.scala 29:58] + node _T_391 = cat(_T_390, _T_366[25]) @[Cat.scala 29:58] + node _T_392 = cat(_T_391, _T_366[26]) @[Cat.scala 29:58] + node _T_393 = bits(csrimm_x, 4, 0) @[el2_dec_decode_ctl.scala 491:53] + node _T_394 = cat(_T_392, _T_393) @[Cat.scala 29:58] + node _T_395 = bits(csr_imm_x, 0, 0) @[el2_dec_decode_ctl.scala 492:16] + node _T_396 = eq(_T_395, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 492:5] + node _T_397 = mux(_T_365, _T_394, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_398 = mux(_T_396, io.exu_csr_rs1_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_399 = or(_T_397, _T_398) @[Mux.scala 27:72] + wire csr_mask_x : UInt<32> @[Mux.scala 27:72] + csr_mask_x <= _T_399 @[Mux.scala 27:72] + node _T_400 = not(csr_mask_x) @[el2_dec_decode_ctl.scala 495:38] + node _T_401 = and(csr_rddata_x, _T_400) @[el2_dec_decode_ctl.scala 495:35] + node _T_402 = or(csr_rddata_x, csr_mask_x) @[el2_dec_decode_ctl.scala 496:35] + node _T_403 = mux(csr_clr_x, _T_401, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_404 = mux(csr_set_x, _T_402, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_405 = mux(csr_write_x, csr_mask_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_406 = or(_T_403, _T_404) @[Mux.scala 27:72] + node _T_407 = or(_T_406, _T_405) @[Mux.scala 27:72] + wire write_csr_data_x : UInt @[Mux.scala 27:72] + write_csr_data_x <= _T_407 @[Mux.scala 27:72] + node _T_408 = eq(io.dec_tlu_flush_pause_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 499:49] + node _T_409 = and(io.dec_tlu_flush_lower_r, _T_408) @[el2_dec_decode_ctl.scala 499:47] + node _T_410 = eq(write_csr_data, UInt<31>("h00")) @[el2_dec_decode_ctl.scala 499:109] + node _T_411 = and(pause_stall, _T_410) @[el2_dec_decode_ctl.scala 499:91] + node clear_pause = or(_T_409, _T_411) @[el2_dec_decode_ctl.scala 499:76] + node _T_412 = or(io.dec_tlu_wr_pause_r, pause_stall) @[el2_dec_decode_ctl.scala 500:44] + node _T_413 = eq(clear_pause, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 500:61] + node _T_414 = and(_T_412, _T_413) @[el2_dec_decode_ctl.scala 500:59] + pause_state_in <= _T_414 @[el2_dec_decode_ctl.scala 500:18] + reg _T_415 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 501:50] + _T_415 <= pause_state_in @[el2_dec_decode_ctl.scala 501:50] + pause_stall <= _T_415 @[el2_dec_decode_ctl.scala 501:15] + io.dec_pause_state <= pause_stall @[el2_dec_decode_ctl.scala 502:22] + reg _T_416 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 503:29] + _T_416 <= io.dec_tlu_wr_pause_r @[el2_dec_decode_ctl.scala 503:29] + tlu_wr_pause_r1 <= _T_416 @[el2_dec_decode_ctl.scala 503:19] + reg _T_417 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 504:29] + _T_417 <= tlu_wr_pause_r1 @[el2_dec_decode_ctl.scala 504:29] + tlu_wr_pause_r2 <= _T_417 @[el2_dec_decode_ctl.scala 504:19] + node _T_418 = eq(tlu_wr_pause_r1, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:44] + node _T_419 = eq(tlu_wr_pause_r2, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 506:64] + node _T_420 = and(_T_418, _T_419) @[el2_dec_decode_ctl.scala 506:61] + node _T_421 = and(pause_stall, _T_420) @[el2_dec_decode_ctl.scala 506:41] + io.dec_pause_state_cg <= _T_421 @[el2_dec_decode_ctl.scala 506:25] + node _T_422 = sub(write_csr_data, UInt<32>("h01")) @[el2_dec_decode_ctl.scala 509:59] + node _T_423 = tail(_T_422, 1) @[el2_dec_decode_ctl.scala 509:59] + node _T_424 = mux(io.dec_tlu_wr_pause_r, io.dec_csr_wrdata_r, write_csr_data_x) @[el2_dec_decode_ctl.scala 510:8] + node write_csr_data_in = mux(pause_stall, _T_423, _T_424) @[el2_dec_decode_ctl.scala 509:30] + node _T_425 = or(csr_clr_x, csr_set_x) @[el2_dec_decode_ctl.scala 511:34] + node _T_426 = or(_T_425, csr_write_x) @[el2_dec_decode_ctl.scala 511:46] + node _T_427 = and(_T_426, csr_read_x) @[el2_dec_decode_ctl.scala 511:61] + node _T_428 = or(_T_427, io.dec_tlu_wr_pause_r) @[el2_dec_decode_ctl.scala 511:75] + node csr_data_wen = or(_T_428, pause_stall) @[el2_dec_decode_ctl.scala 511:99] + inst rvclkhdr_2 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= csr_data_wen @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_429 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_429 <= write_csr_data_in @[el2_lib.scala 514:16] + write_csr_data <= _T_429 @[el2_dec_decode_ctl.scala 512:18] + node _T_430 = bits(r_d.csrwonly, 0, 0) @[el2_dec_decode_ctl.scala 518:44] + node _T_431 = mux(_T_430, i0_result_corr_r, write_csr_data) @[el2_dec_decode_ctl.scala 518:30] + io.dec_csr_wrdata_r <= _T_431 @[el2_dec_decode_ctl.scala 518:24] + node _T_432 = or(x_d.csrwonly, r_d.csrwonly) @[el2_dec_decode_ctl.scala 520:38] + node prior_csr_write = or(_T_432, wbd.csrwonly) @[el2_dec_decode_ctl.scala 520:53] + node _T_433 = bits(io.dbg_cmd_wrdata, 0, 0) @[el2_dec_decode_ctl.scala 522:67] + node debug_fence_i = and(io.dec_debug_fence_d, _T_433) @[el2_dec_decode_ctl.scala 522:48] + node _T_434 = bits(io.dbg_cmd_wrdata, 1, 1) @[el2_dec_decode_ctl.scala 523:67] + node debug_fence_raw = and(io.dec_debug_fence_d, _T_434) @[el2_dec_decode_ctl.scala 523:48] + node _T_435 = or(debug_fence_raw, debug_fence_i) @[el2_dec_decode_ctl.scala 524:40] + debug_fence <= _T_435 @[el2_dec_decode_ctl.scala 524:21] + node _T_436 = or(i0_dp.presync, io.dec_tlu_presync_d) @[el2_dec_decode_ctl.scala 527:34] + node _T_437 = or(_T_436, debug_fence_i) @[el2_dec_decode_ctl.scala 527:57] + node _T_438 = or(_T_437, debug_fence_raw) @[el2_dec_decode_ctl.scala 527:73] + node i0_presync = or(_T_438, io.dec_tlu_pipelining_disable) @[el2_dec_decode_ctl.scala 527:91] + node _T_439 = or(i0_dp.postsync, io.dec_tlu_postsync_d) @[el2_dec_decode_ctl.scala 530:36] + node _T_440 = or(_T_439, debug_fence_i) @[el2_dec_decode_ctl.scala 530:60] + node _T_441 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 530:104] + node _T_442 = eq(_T_441, UInt<11>("h07c2")) @[el2_dec_decode_ctl.scala 530:112] + node _T_443 = and(i0_csr_write_only_d, _T_442) @[el2_dec_decode_ctl.scala 530:99] + node i0_postsync = or(_T_440, _T_443) @[el2_dec_decode_ctl.scala 530:76] + node any_csr_d = or(i0_dp.csr_read, i0_csr_write) @[el2_dec_decode_ctl.scala 532:34] + io.dec_csr_any_unq_d <= any_csr_d @[el2_dec_decode_ctl.scala 533:24] + node _T_444 = eq(any_csr_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 534:40] + node _T_445 = or(_T_444, io.dec_csr_legal_d) @[el2_dec_decode_ctl.scala 534:51] + node i0_legal = and(i0_dp.legal, _T_445) @[el2_dec_decode_ctl.scala 534:37] + wire _T_446 : UInt<1>[16] @[el2_lib.scala 161:48] + _T_446[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_446[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_447 = cat(_T_446[0], _T_446[1]) @[Cat.scala 29:58] + node _T_448 = cat(_T_447, _T_446[2]) @[Cat.scala 29:58] + node _T_449 = cat(_T_448, _T_446[3]) @[Cat.scala 29:58] + node _T_450 = cat(_T_449, _T_446[4]) @[Cat.scala 29:58] + node _T_451 = cat(_T_450, _T_446[5]) @[Cat.scala 29:58] + node _T_452 = cat(_T_451, _T_446[6]) @[Cat.scala 29:58] + node _T_453 = cat(_T_452, _T_446[7]) @[Cat.scala 29:58] + node _T_454 = cat(_T_453, _T_446[8]) @[Cat.scala 29:58] + node _T_455 = cat(_T_454, _T_446[9]) @[Cat.scala 29:58] + node _T_456 = cat(_T_455, _T_446[10]) @[Cat.scala 29:58] + node _T_457 = cat(_T_456, _T_446[11]) @[Cat.scala 29:58] + node _T_458 = cat(_T_457, _T_446[12]) @[Cat.scala 29:58] + node _T_459 = cat(_T_458, _T_446[13]) @[Cat.scala 29:58] + node _T_460 = cat(_T_459, _T_446[14]) @[Cat.scala 29:58] + node _T_461 = cat(_T_460, _T_446[15]) @[Cat.scala 29:58] + node _T_462 = cat(_T_461, io.ifu_i0_cinst) @[Cat.scala 29:58] + node i0_inst_d = mux(io.dec_i0_pc4_d, io.dec_i0_instr_d, _T_462) @[el2_dec_decode_ctl.scala 535:27] + node _T_463 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 538:49] + node shift_illegal = and(io.dec_i0_decode_d, _T_463) @[el2_dec_decode_ctl.scala 538:47] + node _T_464 = eq(illegal_lockout, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 539:44] + node illegal_inst_en = and(shift_illegal, _T_464) @[el2_dec_decode_ctl.scala 539:42] + inst rvclkhdr_3 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= illegal_inst_en @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_465 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_465 <= i0_inst_d @[el2_lib.scala 514:16] + io.dec_illegal_inst <= _T_465 @[el2_dec_decode_ctl.scala 540:23] + node _T_466 = or(shift_illegal, illegal_lockout) @[el2_dec_decode_ctl.scala 541:40] + node _T_467 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 541:61] + node _T_468 = and(_T_466, _T_467) @[el2_dec_decode_ctl.scala 541:59] + illegal_lockout_in <= _T_468 @[el2_dec_decode_ctl.scala 541:22] + reg _T_469 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 542:54] + _T_469 <= illegal_lockout_in @[el2_dec_decode_ctl.scala 542:54] + illegal_lockout <= _T_469 @[el2_dec_decode_ctl.scala 542:19] + node i0_div_prior_div_stall = and(i0_dp.div, io.dec_div_active) @[el2_dec_decode_ctl.scala 543:42] + node _T_470 = and(i0_dp.csr_read, prior_csr_write) @[el2_dec_decode_ctl.scala 545:40] + node _T_471 = or(_T_470, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 545:59] + node _T_472 = or(_T_471, pause_stall) @[el2_dec_decode_ctl.scala 545:81] + node _T_473 = or(_T_472, leak1_i0_stall) @[el2_dec_decode_ctl.scala 545:95] + node _T_474 = or(_T_473, io.dec_tlu_debug_stall) @[el2_dec_decode_ctl.scala 546:20] + node _T_475 = or(_T_474, postsync_stall) @[el2_dec_decode_ctl.scala 546:45] + node _T_476 = or(_T_475, presync_stall) @[el2_dec_decode_ctl.scala 546:62] + node _T_477 = or(i0_dp.fence, debug_fence) @[el2_dec_decode_ctl.scala 547:19] + node _T_478 = eq(lsu_idle, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 547:36] + node _T_479 = and(_T_477, _T_478) @[el2_dec_decode_ctl.scala 547:34] + node _T_480 = or(_T_476, _T_479) @[el2_dec_decode_ctl.scala 546:79] + node _T_481 = or(_T_480, i0_nonblock_load_stall) @[el2_dec_decode_ctl.scala 547:47] + node _T_482 = or(_T_481, i0_load_block_d) @[el2_dec_decode_ctl.scala 547:72] + node _T_483 = or(_T_482, i0_nonblock_div_stall) @[el2_dec_decode_ctl.scala 548:21] + node i0_block_raw_d = or(_T_483, i0_div_prior_div_stall) @[el2_dec_decode_ctl.scala 548:45] + node _T_484 = or(io.lsu_store_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 550:65] + node i0_store_stall_d = and(i0_dp.store, _T_484) @[el2_dec_decode_ctl.scala 550:39] + node _T_485 = or(io.lsu_load_stall_any, io.dma_dccm_stall_any) @[el2_dec_decode_ctl.scala 551:63] + node i0_load_stall_d = and(i0_dp.load, _T_485) @[el2_dec_decode_ctl.scala 551:38] + node _T_486 = or(i0_block_raw_d, i0_store_stall_d) @[el2_dec_decode_ctl.scala 552:38] + node i0_block_d = or(_T_486, i0_load_stall_d) @[el2_dec_decode_ctl.scala 552:57] + node _T_487 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:46] + node _T_488 = and(io.dec_ib0_valid_d, _T_487) @[el2_dec_decode_ctl.scala 556:44] + node _T_489 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:63] + node _T_490 = and(_T_488, _T_489) @[el2_dec_decode_ctl.scala 556:61] + node _T_491 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 556:91] + node _T_492 = and(_T_490, _T_491) @[el2_dec_decode_ctl.scala 556:89] + io.dec_i0_decode_d <= _T_492 @[el2_dec_decode_ctl.scala 556:22] + node _T_493 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:46] + node _T_494 = and(io.dec_ib0_valid_d, _T_493) @[el2_dec_decode_ctl.scala 557:44] + node _T_495 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:63] + node _T_496 = and(_T_494, _T_495) @[el2_dec_decode_ctl.scala 557:61] + node _T_497 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 557:91] + node i0_exudecode_d = and(_T_496, _T_497) @[el2_dec_decode_ctl.scala 557:89] + node i0_exulegal_decode_d = and(i0_exudecode_d, i0_legal) @[el2_dec_decode_ctl.scala 558:46] + io.dec_pmu_instr_decoded <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 561:28] + node _T_498 = eq(io.dec_i0_decode_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 562:51] + node _T_499 = and(io.dec_ib0_valid_d, _T_498) @[el2_dec_decode_ctl.scala 562:49] + io.dec_pmu_decode_stall <= _T_499 @[el2_dec_decode_ctl.scala 562:27] + node _T_500 = bits(postsync_stall, 0, 0) @[el2_dec_decode_ctl.scala 563:47] + io.dec_pmu_postsync_stall <= _T_500 @[el2_dec_decode_ctl.scala 563:29] + node _T_501 = bits(presync_stall, 0, 0) @[el2_dec_decode_ctl.scala 564:46] + io.dec_pmu_presync_stall <= _T_501 @[el2_dec_decode_ctl.scala 564:29] + node prior_inflight = or(x_d.i0valid, r_d.i0valid) @[el2_dec_decode_ctl.scala 568:41] + node prior_inflight_eff = mux(i0_dp.div, x_d.i0valid, prior_inflight) @[el2_dec_decode_ctl.scala 569:31] + node _T_502 = and(i0_presync, prior_inflight_eff) @[el2_dec_decode_ctl.scala 571:37] + presync_stall <= _T_502 @[el2_dec_decode_ctl.scala 571:22] + reg _T_503 : UInt, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 572:53] + _T_503 <= ps_stall_in @[el2_dec_decode_ctl.scala 572:53] + postsync_stall <= _T_503 @[el2_dec_decode_ctl.scala 572:18] + node _T_504 = eq(i0_legal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 574:56] + node _T_505 = or(i0_postsync, _T_504) @[el2_dec_decode_ctl.scala 574:54] + node _T_506 = and(io.dec_i0_decode_d, _T_505) @[el2_dec_decode_ctl.scala 574:39] + node _T_507 = and(postsync_stall, x_d.i0valid) @[el2_dec_decode_ctl.scala 574:88] + node _T_508 = or(_T_506, _T_507) @[el2_dec_decode_ctl.scala 574:69] + ps_stall_in <= _T_508 @[el2_dec_decode_ctl.scala 574:15] + node _T_509 = and(i0_exulegal_decode_d, i0_dp.alu) @[el2_dec_decode_ctl.scala 576:50] + io.dec_i0_alu_decode_d <= _T_509 @[el2_dec_decode_ctl.scala 576:26] + node _T_510 = and(i0_legal_decode_d, i0_dp.lsu) @[el2_dec_decode_ctl.scala 578:40] + lsu_decode_d <= _T_510 @[el2_dec_decode_ctl.scala 578:16] + node _T_511 = and(i0_exulegal_decode_d, i0_dp.mul) @[el2_dec_decode_ctl.scala 579:40] + mul_decode_d <= _T_511 @[el2_dec_decode_ctl.scala 579:16] + node _T_512 = and(i0_exulegal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 580:40] + div_decode_d <= _T_512 @[el2_dec_decode_ctl.scala 580:16] + node _T_513 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 582:47] + node _T_514 = and(r_d.i0valid, _T_513) @[el2_dec_decode_ctl.scala 582:45] + io.dec_tlu_i0_valid_r <= _T_514 @[el2_dec_decode_ctl.scala 582:29] + d_t.legal <= i0_legal_decode_d @[el2_dec_decode_ctl.scala 585:26] + node _T_515 = and(i0_icaf_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 586:40] + d_t.icaf <= _T_515 @[el2_dec_decode_ctl.scala 586:26] + node _T_516 = and(io.dec_i0_icaf_f1_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 587:50] + d_t.icaf_f1 <= _T_516 @[el2_dec_decode_ctl.scala 587:26] + d_t.icaf_type <= io.dec_i0_icaf_type_d @[el2_dec_decode_ctl.scala 588:26] + node _T_517 = or(i0_dp.fence_i, debug_fence_i) @[el2_dec_decode_ctl.scala 590:44] + node _T_518 = and(_T_517, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 590:61] + d_t.fence_i <= _T_518 @[el2_dec_decode_ctl.scala 590:26] + d_t.pmu_i0_br_unpred <= i0_br_unpred @[el2_dec_decode_ctl.scala 593:26] + d_t.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 594:26] + d_t.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 595:26] + wire _T_519 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_519[0] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[1] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[2] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + _T_519[3] <= io.dec_i0_decode_d @[el2_lib.scala 161:48] + node _T_520 = cat(_T_519[0], _T_519[1]) @[Cat.scala 29:58] + node _T_521 = cat(_T_520, _T_519[2]) @[Cat.scala 29:58] + node _T_522 = cat(_T_521, _T_519[3]) @[Cat.scala 29:58] + node _T_523 = and(io.dec_i0_trigger_match_d, _T_522) @[el2_dec_decode_ctl.scala 597:56] + d_t.i0trigger <= _T_523 @[el2_dec_decode_ctl.scala 597:26] + node _T_524 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 600:33] + inst rvclkhdr_4 of rvclkhdr_5 @[el2_lib.scala 518:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_4.io.en <= _T_524 @[el2_lib.scala 521:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_525 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] + _T_525.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33] + _T_525.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33] + _T_525.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_525.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_525.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_526 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_4.io.l1clk with : (reset => (reset, _T_525)) @[el2_lib.scala 524:16] + _T_526.pmu_lsu_misaligned <= d_t.pmu_lsu_misaligned @[el2_lib.scala 524:16] + _T_526.pmu_divide <= d_t.pmu_divide @[el2_lib.scala 524:16] + _T_526.pmu_i0_br_unpred <= d_t.pmu_i0_br_unpred @[el2_lib.scala 524:16] + _T_526.pmu_i0_itype <= d_t.pmu_i0_itype @[el2_lib.scala 524:16] + _T_526.i0trigger <= d_t.i0trigger @[el2_lib.scala 524:16] + _T_526.fence_i <= d_t.fence_i @[el2_lib.scala 524:16] + _T_526.icaf_type <= d_t.icaf_type @[el2_lib.scala 524:16] + _T_526.icaf_f1 <= d_t.icaf_f1 @[el2_lib.scala 524:16] + _T_526.icaf <= d_t.icaf @[el2_lib.scala 524:16] + _T_526.legal <= d_t.legal @[el2_lib.scala 524:16] + x_t.pmu_lsu_misaligned <= _T_526.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 600:7] + x_t.pmu_divide <= _T_526.pmu_divide @[el2_dec_decode_ctl.scala 600:7] + x_t.pmu_i0_br_unpred <= _T_526.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 600:7] + x_t.pmu_i0_itype <= _T_526.pmu_i0_itype @[el2_dec_decode_ctl.scala 600:7] + x_t.i0trigger <= _T_526.i0trigger @[el2_dec_decode_ctl.scala 600:7] + x_t.fence_i <= _T_526.fence_i @[el2_dec_decode_ctl.scala 600:7] + x_t.icaf_type <= _T_526.icaf_type @[el2_dec_decode_ctl.scala 600:7] + x_t.icaf_f1 <= _T_526.icaf_f1 @[el2_dec_decode_ctl.scala 600:7] + x_t.icaf <= _T_526.icaf @[el2_dec_decode_ctl.scala 600:7] + x_t.legal <= _T_526.legal @[el2_dec_decode_ctl.scala 600:7] + x_t_in.pmu_lsu_misaligned <= x_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 602:10] + x_t_in.pmu_divide <= x_t.pmu_divide @[el2_dec_decode_ctl.scala 602:10] + x_t_in.pmu_i0_br_unpred <= x_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 602:10] + x_t_in.pmu_i0_itype <= x_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 602:10] + x_t_in.i0trigger <= x_t.i0trigger @[el2_dec_decode_ctl.scala 602:10] + x_t_in.fence_i <= x_t.fence_i @[el2_dec_decode_ctl.scala 602:10] + x_t_in.icaf_type <= x_t.icaf_type @[el2_dec_decode_ctl.scala 602:10] + x_t_in.icaf_f1 <= x_t.icaf_f1 @[el2_dec_decode_ctl.scala 602:10] + x_t_in.icaf <= x_t.icaf @[el2_dec_decode_ctl.scala 602:10] + x_t_in.legal <= x_t.legal @[el2_dec_decode_ctl.scala 602:10] + wire _T_527 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_527[0] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[1] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[2] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + _T_527[3] <= io.dec_tlu_flush_lower_wb @[el2_lib.scala 161:48] + node _T_528 = cat(_T_527[0], _T_527[1]) @[Cat.scala 29:58] + node _T_529 = cat(_T_528, _T_527[2]) @[Cat.scala 29:58] + node _T_530 = cat(_T_529, _T_527[3]) @[Cat.scala 29:58] + node _T_531 = not(_T_530) @[el2_dec_decode_ctl.scala 603:39] + node _T_532 = and(x_t.i0trigger, _T_531) @[el2_dec_decode_ctl.scala 603:37] + x_t_in.i0trigger <= _T_532 @[el2_dec_decode_ctl.scala 603:20] + node _T_533 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 605:36] + inst rvclkhdr_5 of rvclkhdr_6 @[el2_lib.scala 518:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_5.io.en <= _T_533 @[el2_lib.scala 521:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_534 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_lib.scala 524:33] + _T_534.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.pmu_divide <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.pmu_i0_itype <= UInt<4>("h00") @[el2_lib.scala 524:33] + _T_534.i0trigger <= UInt<4>("h00") @[el2_lib.scala 524:33] + _T_534.fence_i <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.icaf_type <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_534.icaf_f1 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.icaf <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_534.legal <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_535 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>}, rvclkhdr_5.io.l1clk with : (reset => (reset, _T_534)) @[el2_lib.scala 524:16] + _T_535.pmu_lsu_misaligned <= x_t_in.pmu_lsu_misaligned @[el2_lib.scala 524:16] + _T_535.pmu_divide <= x_t_in.pmu_divide @[el2_lib.scala 524:16] + _T_535.pmu_i0_br_unpred <= x_t_in.pmu_i0_br_unpred @[el2_lib.scala 524:16] + _T_535.pmu_i0_itype <= x_t_in.pmu_i0_itype @[el2_lib.scala 524:16] + _T_535.i0trigger <= x_t_in.i0trigger @[el2_lib.scala 524:16] + _T_535.fence_i <= x_t_in.fence_i @[el2_lib.scala 524:16] + _T_535.icaf_type <= x_t_in.icaf_type @[el2_lib.scala 524:16] + _T_535.icaf_f1 <= x_t_in.icaf_f1 @[el2_lib.scala 524:16] + _T_535.icaf <= x_t_in.icaf @[el2_lib.scala 524:16] + _T_535.legal <= x_t_in.legal @[el2_lib.scala 524:16] + r_t.pmu_lsu_misaligned <= _T_535.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 605:7] + r_t.pmu_divide <= _T_535.pmu_divide @[el2_dec_decode_ctl.scala 605:7] + r_t.pmu_i0_br_unpred <= _T_535.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 605:7] + r_t.pmu_i0_itype <= _T_535.pmu_i0_itype @[el2_dec_decode_ctl.scala 605:7] + r_t.i0trigger <= _T_535.i0trigger @[el2_dec_decode_ctl.scala 605:7] + r_t.fence_i <= _T_535.fence_i @[el2_dec_decode_ctl.scala 605:7] + r_t.icaf_type <= _T_535.icaf_type @[el2_dec_decode_ctl.scala 605:7] + r_t.icaf_f1 <= _T_535.icaf_f1 @[el2_dec_decode_ctl.scala 605:7] + r_t.icaf <= _T_535.icaf @[el2_dec_decode_ctl.scala 605:7] + r_t.legal <= _T_535.legal @[el2_dec_decode_ctl.scala 605:7] + reg lsu_trigger_match_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 606:36] + lsu_trigger_match_r <= io.lsu_trigger_match_m @[el2_dec_decode_ctl.scala 606:36] + reg lsu_pmu_misaligned_r : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 607:37] + lsu_pmu_misaligned_r <= io.lsu_pmu_misaligned_m @[el2_dec_decode_ctl.scala 607:37] + r_t_in.pmu_lsu_misaligned <= r_t.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 609:10] + r_t_in.pmu_divide <= r_t.pmu_divide @[el2_dec_decode_ctl.scala 609:10] + r_t_in.pmu_i0_br_unpred <= r_t.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 609:10] + r_t_in.pmu_i0_itype <= r_t.pmu_i0_itype @[el2_dec_decode_ctl.scala 609:10] + r_t_in.i0trigger <= r_t.i0trigger @[el2_dec_decode_ctl.scala 609:10] + r_t_in.fence_i <= r_t.fence_i @[el2_dec_decode_ctl.scala 609:10] + r_t_in.icaf_type <= r_t.icaf_type @[el2_dec_decode_ctl.scala 609:10] + r_t_in.icaf_f1 <= r_t.icaf_f1 @[el2_dec_decode_ctl.scala 609:10] + r_t_in.icaf <= r_t.icaf @[el2_dec_decode_ctl.scala 609:10] + r_t_in.legal <= r_t.legal @[el2_dec_decode_ctl.scala 609:10] + node _T_536 = or(r_d.i0load, r_d.i0store) @[el2_dec_decode_ctl.scala 611:56] + wire _T_537 : UInt<1>[4] @[el2_lib.scala 161:48] + _T_537[0] <= _T_536 @[el2_lib.scala 161:48] + _T_537[1] <= _T_536 @[el2_lib.scala 161:48] + _T_537[2] <= _T_536 @[el2_lib.scala 161:48] + _T_537[3] <= _T_536 @[el2_lib.scala 161:48] + node _T_538 = cat(_T_537[0], _T_537[1]) @[Cat.scala 29:58] + node _T_539 = cat(_T_538, _T_537[2]) @[Cat.scala 29:58] + node _T_540 = cat(_T_539, _T_537[3]) @[Cat.scala 29:58] + node _T_541 = and(_T_540, lsu_trigger_match_r) @[el2_dec_decode_ctl.scala 611:72] + node _T_542 = or(_T_541, r_t.i0trigger) @[el2_dec_decode_ctl.scala 611:95] + r_t_in.i0trigger <= _T_542 @[el2_dec_decode_ctl.scala 611:33] + r_t_in.pmu_lsu_misaligned <= lsu_pmu_misaligned_r @[el2_dec_decode_ctl.scala 612:33] + node _T_543 = bits(io.dec_tlu_flush_lower_wb, 0, 0) @[el2_dec_decode_ctl.scala 614:35] + when _T_543 : @[el2_dec_decode_ctl.scala 614:43] + wire _T_544 : {legal : UInt<1>, icaf : UInt<1>, icaf_f1 : UInt<1>, icaf_type : UInt<2>, fence_i : UInt<1>, i0trigger : UInt<4>, pmu_i0_itype : UInt<4>, pmu_i0_br_unpred : UInt<1>, pmu_divide : UInt<1>, pmu_lsu_misaligned : UInt<1>} @[el2_dec_decode_ctl.scala 614:66] + _T_544.pmu_lsu_misaligned <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.pmu_divide <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.pmu_i0_br_unpred <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.pmu_i0_itype <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.i0trigger <= UInt<4>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.fence_i <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.icaf_type <= UInt<2>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.icaf_f1 <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.icaf <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + _T_544.legal <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 614:66] + r_t_in.pmu_lsu_misaligned <= _T_544.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 614:51] + r_t_in.pmu_divide <= _T_544.pmu_divide @[el2_dec_decode_ctl.scala 614:51] + r_t_in.pmu_i0_br_unpred <= _T_544.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 614:51] + r_t_in.pmu_i0_itype <= _T_544.pmu_i0_itype @[el2_dec_decode_ctl.scala 614:51] + r_t_in.i0trigger <= _T_544.i0trigger @[el2_dec_decode_ctl.scala 614:51] + r_t_in.fence_i <= _T_544.fence_i @[el2_dec_decode_ctl.scala 614:51] + r_t_in.icaf_type <= _T_544.icaf_type @[el2_dec_decode_ctl.scala 614:51] + r_t_in.icaf_f1 <= _T_544.icaf_f1 @[el2_dec_decode_ctl.scala 614:51] + r_t_in.icaf <= _T_544.icaf @[el2_dec_decode_ctl.scala 614:51] + r_t_in.legal <= _T_544.legal @[el2_dec_decode_ctl.scala 614:51] + skip @[el2_dec_decode_ctl.scala 614:43] + io.dec_tlu_packet_r.pmu_lsu_misaligned <= r_t_in.pmu_lsu_misaligned @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.pmu_divide <= r_t_in.pmu_divide @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.pmu_i0_br_unpred <= r_t_in.pmu_i0_br_unpred @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.pmu_i0_itype <= r_t_in.pmu_i0_itype @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.i0trigger <= r_t_in.i0trigger @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.fence_i <= r_t_in.fence_i @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.icaf_type <= r_t_in.icaf_type @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.icaf_f1 <= r_t_in.icaf_f1 @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.icaf <= r_t_in.icaf @[el2_dec_decode_ctl.scala 616:39] + io.dec_tlu_packet_r.legal <= r_t_in.legal @[el2_dec_decode_ctl.scala 616:39] + node _T_545 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 617:53] + io.dec_tlu_packet_r.pmu_divide <= _T_545 @[el2_dec_decode_ctl.scala 617:39] + reg _T_546 : UInt<1>, data_gated_cgc.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 620:52] + _T_546 <= io.exu_flush_final @[el2_dec_decode_ctl.scala 620:52] + flush_final_r <= _T_546 @[el2_dec_decode_ctl.scala 620:17] + node _T_547 = eq(i0_block_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:46] + node _T_548 = and(io.dec_ib0_valid_d, _T_547) @[el2_dec_decode_ctl.scala 622:44] + node _T_549 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:60] + node _T_550 = and(_T_548, _T_549) @[el2_dec_decode_ctl.scala 622:58] + node _T_551 = eq(flush_final_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 622:88] + node _T_552 = and(_T_550, _T_551) @[el2_dec_decode_ctl.scala 622:86] + io.dec_i0_decode_d <= _T_552 @[el2_dec_decode_ctl.scala 622:22] + node _T_553 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 624:16] + i0r.rs1 <= _T_553 @[el2_dec_decode_ctl.scala 624:11] + node _T_554 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 625:16] + i0r.rs2 <= _T_554 @[el2_dec_decode_ctl.scala 625:11] + node _T_555 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 626:16] + i0r.rd <= _T_555 @[el2_dec_decode_ctl.scala 626:11] + node _T_556 = neq(i0r.rs1, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 628:49] + node _T_557 = and(i0_dp.rs1, _T_556) @[el2_dec_decode_ctl.scala 628:38] + io.dec_i0_rs1_en_d <= _T_557 @[el2_dec_decode_ctl.scala 628:24] + node _T_558 = neq(i0r.rs2, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 629:49] + node _T_559 = and(i0_dp.rs2, _T_558) @[el2_dec_decode_ctl.scala 629:38] + io.dec_i0_rs2_en_d <= _T_559 @[el2_dec_decode_ctl.scala 629:24] + node _T_560 = neq(i0r.rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 630:48] + node i0_rd_en_d = and(i0_dp.rd, _T_560) @[el2_dec_decode_ctl.scala 630:37] + io.dec_i0_rs1_d <= i0r.rs1 @[el2_dec_decode_ctl.scala 631:19] + io.dec_i0_rs2_d <= i0r.rs2 @[el2_dec_decode_ctl.scala 632:19] + node i0_jalimm20 = and(i0_dp.jal, i0_dp.imm20) @[el2_dec_decode_ctl.scala 634:38] + node _T_561 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 635:27] + node i0_uiimm20 = and(_T_561, i0_dp.imm20) @[el2_dec_decode_ctl.scala 635:38] + node _T_562 = eq(i0_dp.csr_read, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 639:5] + node _T_563 = mux(i0_dp.csr_read, io.dec_csr_rddata_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_564 = mux(_T_562, i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_565 = or(_T_563, _T_564) @[Mux.scala 27:72] + wire _T_566 : UInt<32> @[Mux.scala 27:72] + _T_566 <= _T_565 @[Mux.scala 27:72] + io.dec_i0_immed_d <= _T_566 @[el2_dec_decode_ctl.scala 637:21] + node _T_567 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 642:38] + wire _T_568 : UInt<1>[20] @[el2_lib.scala 161:48] + _T_568[0] <= _T_567 @[el2_lib.scala 161:48] + _T_568[1] <= _T_567 @[el2_lib.scala 161:48] + _T_568[2] <= _T_567 @[el2_lib.scala 161:48] + _T_568[3] <= _T_567 @[el2_lib.scala 161:48] + _T_568[4] <= _T_567 @[el2_lib.scala 161:48] + _T_568[5] <= _T_567 @[el2_lib.scala 161:48] + _T_568[6] <= _T_567 @[el2_lib.scala 161:48] + _T_568[7] <= _T_567 @[el2_lib.scala 161:48] + _T_568[8] <= _T_567 @[el2_lib.scala 161:48] + _T_568[9] <= _T_567 @[el2_lib.scala 161:48] + _T_568[10] <= _T_567 @[el2_lib.scala 161:48] + _T_568[11] <= _T_567 @[el2_lib.scala 161:48] + _T_568[12] <= _T_567 @[el2_lib.scala 161:48] + _T_568[13] <= _T_567 @[el2_lib.scala 161:48] + _T_568[14] <= _T_567 @[el2_lib.scala 161:48] + _T_568[15] <= _T_567 @[el2_lib.scala 161:48] + _T_568[16] <= _T_567 @[el2_lib.scala 161:48] + _T_568[17] <= _T_567 @[el2_lib.scala 161:48] + _T_568[18] <= _T_567 @[el2_lib.scala 161:48] + _T_568[19] <= _T_567 @[el2_lib.scala 161:48] + node _T_569 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58] + node _T_570 = cat(_T_569, _T_568[2]) @[Cat.scala 29:58] + node _T_571 = cat(_T_570, _T_568[3]) @[Cat.scala 29:58] + node _T_572 = cat(_T_571, _T_568[4]) @[Cat.scala 29:58] + node _T_573 = cat(_T_572, _T_568[5]) @[Cat.scala 29:58] + node _T_574 = cat(_T_573, _T_568[6]) @[Cat.scala 29:58] + node _T_575 = cat(_T_574, _T_568[7]) @[Cat.scala 29:58] + node _T_576 = cat(_T_575, _T_568[8]) @[Cat.scala 29:58] + node _T_577 = cat(_T_576, _T_568[9]) @[Cat.scala 29:58] + node _T_578 = cat(_T_577, _T_568[10]) @[Cat.scala 29:58] + node _T_579 = cat(_T_578, _T_568[11]) @[Cat.scala 29:58] + node _T_580 = cat(_T_579, _T_568[12]) @[Cat.scala 29:58] + node _T_581 = cat(_T_580, _T_568[13]) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_568[14]) @[Cat.scala 29:58] + node _T_583 = cat(_T_582, _T_568[15]) @[Cat.scala 29:58] + node _T_584 = cat(_T_583, _T_568[16]) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_568[17]) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_568[18]) @[Cat.scala 29:58] + node _T_587 = cat(_T_586, _T_568[19]) @[Cat.scala 29:58] + node _T_588 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 642:46] + node _T_589 = cat(_T_587, _T_588) @[Cat.scala 29:58] + wire _T_590 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_590[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_590[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_591 = cat(_T_590[0], _T_590[1]) @[Cat.scala 29:58] + node _T_592 = cat(_T_591, _T_590[2]) @[Cat.scala 29:58] + node _T_593 = cat(_T_592, _T_590[3]) @[Cat.scala 29:58] + node _T_594 = cat(_T_593, _T_590[4]) @[Cat.scala 29:58] + node _T_595 = cat(_T_594, _T_590[5]) @[Cat.scala 29:58] + node _T_596 = cat(_T_595, _T_590[6]) @[Cat.scala 29:58] + node _T_597 = cat(_T_596, _T_590[7]) @[Cat.scala 29:58] + node _T_598 = cat(_T_597, _T_590[8]) @[Cat.scala 29:58] + node _T_599 = cat(_T_598, _T_590[9]) @[Cat.scala 29:58] + node _T_600 = cat(_T_599, _T_590[10]) @[Cat.scala 29:58] + node _T_601 = cat(_T_600, _T_590[11]) @[Cat.scala 29:58] + node _T_602 = cat(_T_601, _T_590[12]) @[Cat.scala 29:58] + node _T_603 = cat(_T_602, _T_590[13]) @[Cat.scala 29:58] + node _T_604 = cat(_T_603, _T_590[14]) @[Cat.scala 29:58] + node _T_605 = cat(_T_604, _T_590[15]) @[Cat.scala 29:58] + node _T_606 = cat(_T_605, _T_590[16]) @[Cat.scala 29:58] + node _T_607 = cat(_T_606, _T_590[17]) @[Cat.scala 29:58] + node _T_608 = cat(_T_607, _T_590[18]) @[Cat.scala 29:58] + node _T_609 = cat(_T_608, _T_590[19]) @[Cat.scala 29:58] + node _T_610 = cat(_T_609, _T_590[20]) @[Cat.scala 29:58] + node _T_611 = cat(_T_610, _T_590[21]) @[Cat.scala 29:58] + node _T_612 = cat(_T_611, _T_590[22]) @[Cat.scala 29:58] + node _T_613 = cat(_T_612, _T_590[23]) @[Cat.scala 29:58] + node _T_614 = cat(_T_613, _T_590[24]) @[Cat.scala 29:58] + node _T_615 = cat(_T_614, _T_590[25]) @[Cat.scala 29:58] + node _T_616 = cat(_T_615, _T_590[26]) @[Cat.scala 29:58] + node _T_617 = bits(io.dec_i0_instr_d, 24, 20) @[el2_dec_decode_ctl.scala 643:43] + node _T_618 = cat(_T_616, _T_617) @[Cat.scala 29:58] + node _T_619 = bits(io.dec_i0_instr_d, 31, 31) @[el2_dec_decode_ctl.scala 644:38] + wire _T_620 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_620[0] <= _T_619 @[el2_lib.scala 161:48] + _T_620[1] <= _T_619 @[el2_lib.scala 161:48] + _T_620[2] <= _T_619 @[el2_lib.scala 161:48] + _T_620[3] <= _T_619 @[el2_lib.scala 161:48] + _T_620[4] <= _T_619 @[el2_lib.scala 161:48] + _T_620[5] <= _T_619 @[el2_lib.scala 161:48] + _T_620[6] <= _T_619 @[el2_lib.scala 161:48] + _T_620[7] <= _T_619 @[el2_lib.scala 161:48] + _T_620[8] <= _T_619 @[el2_lib.scala 161:48] + _T_620[9] <= _T_619 @[el2_lib.scala 161:48] + _T_620[10] <= _T_619 @[el2_lib.scala 161:48] + _T_620[11] <= _T_619 @[el2_lib.scala 161:48] + node _T_621 = cat(_T_620[0], _T_620[1]) @[Cat.scala 29:58] + node _T_622 = cat(_T_621, _T_620[2]) @[Cat.scala 29:58] + node _T_623 = cat(_T_622, _T_620[3]) @[Cat.scala 29:58] + node _T_624 = cat(_T_623, _T_620[4]) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_620[5]) @[Cat.scala 29:58] + node _T_626 = cat(_T_625, _T_620[6]) @[Cat.scala 29:58] + node _T_627 = cat(_T_626, _T_620[7]) @[Cat.scala 29:58] + node _T_628 = cat(_T_627, _T_620[8]) @[Cat.scala 29:58] + node _T_629 = cat(_T_628, _T_620[9]) @[Cat.scala 29:58] + node _T_630 = cat(_T_629, _T_620[10]) @[Cat.scala 29:58] + node _T_631 = cat(_T_630, _T_620[11]) @[Cat.scala 29:58] + node _T_632 = bits(io.dec_i0_instr_d, 19, 12) @[el2_dec_decode_ctl.scala 644:46] + node _T_633 = bits(io.dec_i0_instr_d, 20, 20) @[el2_dec_decode_ctl.scala 644:56] + node _T_634 = bits(io.dec_i0_instr_d, 30, 21) @[el2_dec_decode_ctl.scala 644:63] + node _T_635 = cat(_T_634, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_636 = cat(_T_631, _T_632) @[Cat.scala 29:58] + node _T_637 = cat(_T_636, _T_633) @[Cat.scala 29:58] + node _T_638 = cat(_T_637, _T_635) @[Cat.scala 29:58] + node _T_639 = bits(io.dec_i0_instr_d, 31, 12) @[el2_dec_decode_ctl.scala 645:30] + wire _T_640 : UInt<1>[12] @[el2_lib.scala 161:48] + _T_640[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_640[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_641 = cat(_T_640[0], _T_640[1]) @[Cat.scala 29:58] + node _T_642 = cat(_T_641, _T_640[2]) @[Cat.scala 29:58] + node _T_643 = cat(_T_642, _T_640[3]) @[Cat.scala 29:58] + node _T_644 = cat(_T_643, _T_640[4]) @[Cat.scala 29:58] + node _T_645 = cat(_T_644, _T_640[5]) @[Cat.scala 29:58] + node _T_646 = cat(_T_645, _T_640[6]) @[Cat.scala 29:58] + node _T_647 = cat(_T_646, _T_640[7]) @[Cat.scala 29:58] + node _T_648 = cat(_T_647, _T_640[8]) @[Cat.scala 29:58] + node _T_649 = cat(_T_648, _T_640[9]) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_640[10]) @[Cat.scala 29:58] + node _T_651 = cat(_T_650, _T_640[11]) @[Cat.scala 29:58] + node _T_652 = cat(_T_639, _T_651) @[Cat.scala 29:58] + node _T_653 = and(i0_csr_write_only_d, i0_dp.csr_imm) @[el2_dec_decode_ctl.scala 646:26] + node _T_654 = bits(_T_653, 0, 0) @[el2_dec_decode_ctl.scala 646:43] + wire _T_655 : UInt<1>[27] @[el2_lib.scala 161:48] + _T_655[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[10] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[11] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[12] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[13] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[14] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[15] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[16] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[17] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[18] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[19] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[20] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[21] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[22] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[23] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[24] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[25] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_655[26] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_656 = cat(_T_655[0], _T_655[1]) @[Cat.scala 29:58] + node _T_657 = cat(_T_656, _T_655[2]) @[Cat.scala 29:58] + node _T_658 = cat(_T_657, _T_655[3]) @[Cat.scala 29:58] + node _T_659 = cat(_T_658, _T_655[4]) @[Cat.scala 29:58] + node _T_660 = cat(_T_659, _T_655[5]) @[Cat.scala 29:58] + node _T_661 = cat(_T_660, _T_655[6]) @[Cat.scala 29:58] + node _T_662 = cat(_T_661, _T_655[7]) @[Cat.scala 29:58] + node _T_663 = cat(_T_662, _T_655[8]) @[Cat.scala 29:58] + node _T_664 = cat(_T_663, _T_655[9]) @[Cat.scala 29:58] + node _T_665 = cat(_T_664, _T_655[10]) @[Cat.scala 29:58] + node _T_666 = cat(_T_665, _T_655[11]) @[Cat.scala 29:58] + node _T_667 = cat(_T_666, _T_655[12]) @[Cat.scala 29:58] + node _T_668 = cat(_T_667, _T_655[13]) @[Cat.scala 29:58] + node _T_669 = cat(_T_668, _T_655[14]) @[Cat.scala 29:58] + node _T_670 = cat(_T_669, _T_655[15]) @[Cat.scala 29:58] + node _T_671 = cat(_T_670, _T_655[16]) @[Cat.scala 29:58] + node _T_672 = cat(_T_671, _T_655[17]) @[Cat.scala 29:58] + node _T_673 = cat(_T_672, _T_655[18]) @[Cat.scala 29:58] + node _T_674 = cat(_T_673, _T_655[19]) @[Cat.scala 29:58] + node _T_675 = cat(_T_674, _T_655[20]) @[Cat.scala 29:58] + node _T_676 = cat(_T_675, _T_655[21]) @[Cat.scala 29:58] + node _T_677 = cat(_T_676, _T_655[22]) @[Cat.scala 29:58] + node _T_678 = cat(_T_677, _T_655[23]) @[Cat.scala 29:58] + node _T_679 = cat(_T_678, _T_655[24]) @[Cat.scala 29:58] + node _T_680 = cat(_T_679, _T_655[25]) @[Cat.scala 29:58] + node _T_681 = cat(_T_680, _T_655[26]) @[Cat.scala 29:58] + node _T_682 = bits(io.dec_i0_instr_d, 19, 15) @[el2_dec_decode_ctl.scala 646:72] + node _T_683 = cat(_T_681, _T_682) @[Cat.scala 29:58] + node _T_684 = mux(i0_dp.imm12, _T_589, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_685 = mux(i0_dp.shimm5, _T_618, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_686 = mux(i0_jalimm20, _T_638, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_687 = mux(i0_uiimm20, _T_652, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_688 = mux(_T_654, _T_683, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_689 = or(_T_684, _T_685) @[Mux.scala 27:72] + node _T_690 = or(_T_689, _T_686) @[Mux.scala 27:72] + node _T_691 = or(_T_690, _T_687) @[Mux.scala 27:72] + node _T_692 = or(_T_691, _T_688) @[Mux.scala 27:72] + wire _T_693 : UInt<32> @[Mux.scala 27:72] + _T_693 <= _T_692 @[Mux.scala 27:72] + i0_immed_d <= _T_693 @[el2_dec_decode_ctl.scala 641:14] + node _T_694 = and(io.dec_i0_decode_d, i0_legal) @[el2_dec_decode_ctl.scala 648:46] + i0_legal_decode_d <= _T_694 @[el2_dec_decode_ctl.scala 648:24] + node _T_695 = and(i0_dp.mul, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 650:44] + i0_d_c.mul <= _T_695 @[el2_dec_decode_ctl.scala 650:29] + node _T_696 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 651:44] + i0_d_c.load <= _T_696 @[el2_dec_decode_ctl.scala 651:29] + node _T_697 = and(i0_dp.alu, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 652:44] + i0_d_c.alu <= _T_697 @[el2_dec_decode_ctl.scala 652:29] + node _T_698 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 654:71] + reg i0_x_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_698 : @[Reg.scala 16:19] + i0_x_c.alu <= i0_d_c.alu @[Reg.scala 16:23] + i0_x_c.load <= i0_d_c.load @[Reg.scala 16:23] + i0_x_c.mul <= i0_d_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_699 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 655:71] + reg i0_r_c : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>}, io.active_clk @[Reg.scala 15:16] + when _T_699 : @[Reg.scala 16:19] + i0_r_c.alu <= i0_x_c.alu @[Reg.scala 16:23] + i0_r_c.load <= i0_x_c.load @[Reg.scala 16:23] + i0_r_c.mul <= i0_x_c.mul @[Reg.scala 16:23] + skip @[Reg.scala 16:19] + node _T_700 = bits(i0_pipe_en, 3, 1) @[el2_dec_decode_ctl.scala 656:83] + reg _T_701 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 656:72] + _T_701 <= _T_700 @[el2_dec_decode_ctl.scala 656:72] + node _T_702 = cat(io.dec_i0_decode_d, _T_701) @[Cat.scala 29:58] + i0_pipe_en <= _T_702 @[el2_dec_decode_ctl.scala 656:14] + node _T_703 = bits(i0_pipe_en, 3, 2) @[el2_dec_decode_ctl.scala 658:43] + node _T_704 = orr(_T_703) @[el2_dec_decode_ctl.scala 658:49] + node _T_705 = or(_T_704, io.clk_override) @[el2_dec_decode_ctl.scala 658:53] + i0_x_ctl_en <= _T_705 @[el2_dec_decode_ctl.scala 658:29] + node _T_706 = bits(i0_pipe_en, 2, 1) @[el2_dec_decode_ctl.scala 659:43] + node _T_707 = orr(_T_706) @[el2_dec_decode_ctl.scala 659:49] + node _T_708 = or(_T_707, io.clk_override) @[el2_dec_decode_ctl.scala 659:53] + i0_r_ctl_en <= _T_708 @[el2_dec_decode_ctl.scala 659:29] + node _T_709 = bits(i0_pipe_en, 1, 0) @[el2_dec_decode_ctl.scala 660:43] + node _T_710 = orr(_T_709) @[el2_dec_decode_ctl.scala 660:49] + node _T_711 = or(_T_710, io.clk_override) @[el2_dec_decode_ctl.scala 660:53] + i0_wb_ctl_en <= _T_711 @[el2_dec_decode_ctl.scala 660:29] + node _T_712 = bits(i0_pipe_en, 3, 3) @[el2_dec_decode_ctl.scala 661:44] + node _T_713 = or(_T_712, io.clk_override) @[el2_dec_decode_ctl.scala 661:50] + i0_x_data_en <= _T_713 @[el2_dec_decode_ctl.scala 661:29] + node _T_714 = bits(i0_pipe_en, 2, 2) @[el2_dec_decode_ctl.scala 662:44] + node _T_715 = or(_T_714, io.clk_override) @[el2_dec_decode_ctl.scala 662:50] + i0_r_data_en <= _T_715 @[el2_dec_decode_ctl.scala 662:29] + node _T_716 = bits(i0_pipe_en, 1, 1) @[el2_dec_decode_ctl.scala 663:44] + node _T_717 = or(_T_716, io.clk_override) @[el2_dec_decode_ctl.scala 663:50] + i0_wb_data_en <= _T_717 @[el2_dec_decode_ctl.scala 663:29] + node _T_718 = bits(i0_pipe_en, 0, 0) @[el2_dec_decode_ctl.scala 664:44] + node _T_719 = or(_T_718, io.clk_override) @[el2_dec_decode_ctl.scala 664:50] + i0_wb1_data_en <= _T_719 @[el2_dec_decode_ctl.scala 664:29] + node _T_720 = cat(i0_x_data_en, i0_r_data_en) @[Cat.scala 29:58] + io.dec_data_en <= _T_720 @[el2_dec_decode_ctl.scala 666:27] + node _T_721 = cat(i0_x_ctl_en, i0_r_ctl_en) @[Cat.scala 29:58] + io.dec_ctl_en <= _T_721 @[el2_dec_decode_ctl.scala 667:27] + d_d.i0rd <= i0r.rd @[el2_dec_decode_ctl.scala 669:29] + node _T_722 = and(i0_rd_en_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 670:45] + d_d.i0v <= _T_722 @[el2_dec_decode_ctl.scala 670:29] + d_d.i0valid <= io.dec_i0_decode_d @[el2_dec_decode_ctl.scala 671:29] + node _T_723 = and(i0_dp.load, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 673:45] + d_d.i0load <= _T_723 @[el2_dec_decode_ctl.scala 673:29] + node _T_724 = and(i0_dp.store, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 674:45] + d_d.i0store <= _T_724 @[el2_dec_decode_ctl.scala 674:29] + node _T_725 = and(i0_dp.div, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 675:45] + d_d.i0div <= _T_725 @[el2_dec_decode_ctl.scala 675:29] + node _T_726 = and(io.dec_csr_wen_unq_d, i0_legal_decode_d) @[el2_dec_decode_ctl.scala 677:56] + d_d.csrwen <= _T_726 @[el2_dec_decode_ctl.scala 677:29] + node _T_727 = and(i0_csr_write_only_d, io.dec_i0_decode_d) @[el2_dec_decode_ctl.scala 678:53] + d_d.csrwonly <= _T_727 @[el2_dec_decode_ctl.scala 678:29] + node _T_728 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 679:35] + d_d.csrwaddr <= _T_728 @[el2_dec_decode_ctl.scala 679:29] + node _T_729 = bits(i0_x_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 681:34] + inst rvclkhdr_6 of rvclkhdr_7 @[el2_lib.scala 518:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_6.io.en <= _T_729 @[el2_lib.scala 521:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_730 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_730.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_730.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_730.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_731 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_6.io.l1clk with : (reset => (reset, _T_730)) @[el2_lib.scala 524:16] + _T_731.csrwaddr <= d_d.csrwaddr @[el2_lib.scala 524:16] + _T_731.csrwonly <= d_d.csrwonly @[el2_lib.scala 524:16] + _T_731.csrwen <= d_d.csrwen @[el2_lib.scala 524:16] + _T_731.i0valid <= d_d.i0valid @[el2_lib.scala 524:16] + _T_731.i0v <= d_d.i0v @[el2_lib.scala 524:16] + _T_731.i0div <= d_d.i0div @[el2_lib.scala 524:16] + _T_731.i0store <= d_d.i0store @[el2_lib.scala 524:16] + _T_731.i0load <= d_d.i0load @[el2_lib.scala 524:16] + _T_731.i0rd <= d_d.i0rd @[el2_lib.scala 524:16] + x_d.csrwaddr <= _T_731.csrwaddr @[el2_dec_decode_ctl.scala 681:7] + x_d.csrwonly <= _T_731.csrwonly @[el2_dec_decode_ctl.scala 681:7] + x_d.csrwen <= _T_731.csrwen @[el2_dec_decode_ctl.scala 681:7] + x_d.i0valid <= _T_731.i0valid @[el2_dec_decode_ctl.scala 681:7] + x_d.i0v <= _T_731.i0v @[el2_dec_decode_ctl.scala 681:7] + x_d.i0div <= _T_731.i0div @[el2_dec_decode_ctl.scala 681:7] + x_d.i0store <= _T_731.i0store @[el2_dec_decode_ctl.scala 681:7] + x_d.i0load <= _T_731.i0load @[el2_dec_decode_ctl.scala 681:7] + x_d.i0rd <= _T_731.i0rd @[el2_dec_decode_ctl.scala 681:7] + wire x_d_in : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_dec_decode_ctl.scala 682:20] + x_d_in.csrwaddr <= x_d.csrwaddr @[el2_dec_decode_ctl.scala 683:10] + x_d_in.csrwonly <= x_d.csrwonly @[el2_dec_decode_ctl.scala 683:10] + x_d_in.csrwen <= x_d.csrwen @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0valid <= x_d.i0valid @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0v <= x_d.i0v @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0div <= x_d.i0div @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0store <= x_d.i0store @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0load <= x_d.i0load @[el2_dec_decode_ctl.scala 683:10] + x_d_in.i0rd <= x_d.i0rd @[el2_dec_decode_ctl.scala 683:10] + node _T_732 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:39] + node _T_733 = and(x_d.i0v, _T_732) @[el2_dec_decode_ctl.scala 684:37] + node _T_734 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 684:68] + node _T_735 = and(_T_733, _T_734) @[el2_dec_decode_ctl.scala 684:66] + x_d_in.i0v <= _T_735 @[el2_dec_decode_ctl.scala 684:22] + node _T_736 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:39] + node _T_737 = and(x_d.i0valid, _T_736) @[el2_dec_decode_ctl.scala 685:37] + node _T_738 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 685:68] + node _T_739 = and(_T_737, _T_738) @[el2_dec_decode_ctl.scala 685:66] + x_d_in.i0valid <= _T_739 @[el2_dec_decode_ctl.scala 685:22] + node _T_740 = bits(i0_r_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 687:36] + inst rvclkhdr_7 of rvclkhdr_8 @[el2_lib.scala 518:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_7.io.en <= _T_740 @[el2_lib.scala 521:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_741 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_741.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_741.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_741.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_742 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_7.io.l1clk with : (reset => (reset, _T_741)) @[el2_lib.scala 524:16] + _T_742.csrwaddr <= x_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_742.csrwonly <= x_d_in.csrwonly @[el2_lib.scala 524:16] + _T_742.csrwen <= x_d_in.csrwen @[el2_lib.scala 524:16] + _T_742.i0valid <= x_d_in.i0valid @[el2_lib.scala 524:16] + _T_742.i0v <= x_d_in.i0v @[el2_lib.scala 524:16] + _T_742.i0div <= x_d_in.i0div @[el2_lib.scala 524:16] + _T_742.i0store <= x_d_in.i0store @[el2_lib.scala 524:16] + _T_742.i0load <= x_d_in.i0load @[el2_lib.scala 524:16] + _T_742.i0rd <= x_d_in.i0rd @[el2_lib.scala 524:16] + r_d.csrwaddr <= _T_742.csrwaddr @[el2_dec_decode_ctl.scala 687:7] + r_d.csrwonly <= _T_742.csrwonly @[el2_dec_decode_ctl.scala 687:7] + r_d.csrwen <= _T_742.csrwen @[el2_dec_decode_ctl.scala 687:7] + r_d.i0valid <= _T_742.i0valid @[el2_dec_decode_ctl.scala 687:7] + r_d.i0v <= _T_742.i0v @[el2_dec_decode_ctl.scala 687:7] + r_d.i0div <= _T_742.i0div @[el2_dec_decode_ctl.scala 687:7] + r_d.i0store <= _T_742.i0store @[el2_dec_decode_ctl.scala 687:7] + r_d.i0load <= _T_742.i0load @[el2_dec_decode_ctl.scala 687:7] + r_d.i0rd <= _T_742.i0rd @[el2_dec_decode_ctl.scala 687:7] + r_d_in.csrwaddr <= r_d.csrwaddr @[el2_dec_decode_ctl.scala 688:10] + r_d_in.csrwonly <= r_d.csrwonly @[el2_dec_decode_ctl.scala 688:10] + r_d_in.csrwen <= r_d.csrwen @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0valid <= r_d.i0valid @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0v <= r_d.i0v @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0div <= r_d.i0div @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0store <= r_d.i0store @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0load <= r_d.i0load @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 688:10] + r_d_in.i0rd <= r_d.i0rd @[el2_dec_decode_ctl.scala 689:17] + node _T_743 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 691:41] + node _T_744 = and(r_d.i0v, _T_743) @[el2_dec_decode_ctl.scala 691:39] + r_d_in.i0v <= _T_744 @[el2_dec_decode_ctl.scala 691:22] + node _T_745 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 692:41] + node _T_746 = and(r_d.i0valid, _T_745) @[el2_dec_decode_ctl.scala 692:39] + r_d_in.i0valid <= _T_746 @[el2_dec_decode_ctl.scala 692:22] + node _T_747 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 693:41] + node _T_748 = and(r_d.i0load, _T_747) @[el2_dec_decode_ctl.scala 693:39] + r_d_in.i0load <= _T_748 @[el2_dec_decode_ctl.scala 693:22] + node _T_749 = eq(io.dec_tlu_flush_lower_wb, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 694:41] + node _T_750 = and(r_d.i0store, _T_749) @[el2_dec_decode_ctl.scala 694:39] + r_d_in.i0store <= _T_750 @[el2_dec_decode_ctl.scala 694:22] + node _T_751 = bits(i0_wb_ctl_en, 0, 0) @[el2_dec_decode_ctl.scala 696:37] + inst rvclkhdr_8 of rvclkhdr_9 @[el2_lib.scala 518:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_8.io.en <= _T_751 @[el2_lib.scala 521:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_752 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>} @[el2_lib.scala 524:33] + _T_752.csrwaddr <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_752.csrwonly <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.csrwen <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0v <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0div <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0store <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0load <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_752.i0rd <= UInt<5>("h00") @[el2_lib.scala 524:33] + reg _T_753 : {i0rd : UInt<5>, i0load : UInt<1>, i0store : UInt<1>, i0div : UInt<1>, i0v : UInt<1>, i0valid : UInt<1>, csrwen : UInt<1>, csrwonly : UInt<1>, csrwaddr : UInt<12>}, rvclkhdr_8.io.l1clk with : (reset => (reset, _T_752)) @[el2_lib.scala 524:16] + _T_753.csrwaddr <= r_d_in.csrwaddr @[el2_lib.scala 524:16] + _T_753.csrwonly <= r_d_in.csrwonly @[el2_lib.scala 524:16] + _T_753.csrwen <= r_d_in.csrwen @[el2_lib.scala 524:16] + _T_753.i0valid <= r_d_in.i0valid @[el2_lib.scala 524:16] + _T_753.i0v <= r_d_in.i0v @[el2_lib.scala 524:16] + _T_753.i0div <= r_d_in.i0div @[el2_lib.scala 524:16] + _T_753.i0store <= r_d_in.i0store @[el2_lib.scala 524:16] + _T_753.i0load <= r_d_in.i0load @[el2_lib.scala 524:16] + _T_753.i0rd <= r_d_in.i0rd @[el2_lib.scala 524:16] + wbd.csrwaddr <= _T_753.csrwaddr @[el2_dec_decode_ctl.scala 696:7] + wbd.csrwonly <= _T_753.csrwonly @[el2_dec_decode_ctl.scala 696:7] + wbd.csrwen <= _T_753.csrwen @[el2_dec_decode_ctl.scala 696:7] + wbd.i0valid <= _T_753.i0valid @[el2_dec_decode_ctl.scala 696:7] + wbd.i0v <= _T_753.i0v @[el2_dec_decode_ctl.scala 696:7] + wbd.i0div <= _T_753.i0div @[el2_dec_decode_ctl.scala 696:7] + wbd.i0store <= _T_753.i0store @[el2_dec_decode_ctl.scala 696:7] + wbd.i0load <= _T_753.i0load @[el2_dec_decode_ctl.scala 696:7] + wbd.i0rd <= _T_753.i0rd @[el2_dec_decode_ctl.scala 696:7] + io.dec_i0_waddr_r <= r_d_in.i0rd @[el2_dec_decode_ctl.scala 698:27] + node _T_754 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 699:42] + node _T_755 = and(r_d_in.i0v, _T_754) @[el2_dec_decode_ctl.scala 699:40] + i0_wen_r <= _T_755 @[el2_dec_decode_ctl.scala 699:25] + node _T_756 = eq(r_d_in.i0div, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:49] + node _T_757 = and(i0_wen_r, _T_756) @[el2_dec_decode_ctl.scala 700:47] + node _T_758 = eq(i0_load_kill_wen_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 700:65] + node _T_759 = and(_T_757, _T_758) @[el2_dec_decode_ctl.scala 700:63] + io.dec_i0_wen_r <= _T_759 @[el2_dec_decode_ctl.scala 700:32] + io.dec_i0_wdata_r <= i0_result_corr_r @[el2_dec_decode_ctl.scala 701:26] + node _T_760 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 703:57] + inst rvclkhdr_9 of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_760 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_result_r_raw : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_result_r_raw <= i0_result_x @[el2_lib.scala 514:16] + node _T_761 = and(x_d.i0v, x_d.i0load) @[el2_dec_decode_ctl.scala 709:42] + node _T_762 = bits(_T_761, 0, 0) @[el2_dec_decode_ctl.scala 709:56] + node _T_763 = mux(_T_762, io.lsu_result_m, io.exu_i0_result_x) @[el2_dec_decode_ctl.scala 709:32] + i0_result_x <= _T_763 @[el2_dec_decode_ctl.scala 709:26] + i0_result_r <= i0_result_r_raw @[el2_dec_decode_ctl.scala 710:26] + node _T_764 = and(r_d.i0v, r_d.i0load) @[el2_dec_decode_ctl.scala 714:37] + node _T_765 = bits(_T_764, 0, 0) @[el2_dec_decode_ctl.scala 714:51] + node _T_766 = mux(_T_765, io.lsu_result_corr_r, i0_result_r_raw) @[el2_dec_decode_ctl.scala 714:27] + i0_result_corr_r <= _T_766 @[el2_dec_decode_ctl.scala 714:21] + node _T_767 = eq(i0_dp.jal, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 715:54] + node _T_768 = and(io.i0_ap.predict_nt, _T_767) @[el2_dec_decode_ctl.scala 715:52] + node _T_769 = bits(_T_768, 0, 0) @[el2_dec_decode_ctl.scala 715:66] + wire _T_770 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_770[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_770[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_771 = cat(_T_770[0], _T_770[1]) @[Cat.scala 29:58] + node _T_772 = cat(_T_771, _T_770[2]) @[Cat.scala 29:58] + node _T_773 = cat(_T_772, _T_770[3]) @[Cat.scala 29:58] + node _T_774 = cat(_T_773, _T_770[4]) @[Cat.scala 29:58] + node _T_775 = cat(_T_774, _T_770[5]) @[Cat.scala 29:58] + node _T_776 = cat(_T_775, _T_770[6]) @[Cat.scala 29:58] + node _T_777 = cat(_T_776, _T_770[7]) @[Cat.scala 29:58] + node _T_778 = cat(_T_777, _T_770[8]) @[Cat.scala 29:58] + node _T_779 = cat(_T_778, _T_770[9]) @[Cat.scala 29:58] + node _T_780 = cat(_T_779, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_781 = cat(_T_780, i0_ap_pc2) @[Cat.scala 29:58] + node _T_782 = mux(_T_769, i0_br_offset, _T_781) @[el2_dec_decode_ctl.scala 715:30] + io.dec_i0_br_immed_d <= _T_782 @[el2_dec_decode_ctl.scala 715:24] + wire last_br_immed_d : UInt<12> + last_br_immed_d <= UInt<1>("h00") + node _T_783 = bits(io.i0_ap.predict_nt, 0, 0) @[el2_dec_decode_ctl.scala 717:48] + wire _T_784 : UInt<1>[10] @[el2_lib.scala 161:48] + _T_784[0] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[1] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[2] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[3] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[4] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[5] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[6] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[7] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[8] <= UInt<1>("h00") @[el2_lib.scala 161:48] + _T_784[9] <= UInt<1>("h00") @[el2_lib.scala 161:48] + node _T_785 = cat(_T_784[0], _T_784[1]) @[Cat.scala 29:58] + node _T_786 = cat(_T_785, _T_784[2]) @[Cat.scala 29:58] + node _T_787 = cat(_T_786, _T_784[3]) @[Cat.scala 29:58] + node _T_788 = cat(_T_787, _T_784[4]) @[Cat.scala 29:58] + node _T_789 = cat(_T_788, _T_784[5]) @[Cat.scala 29:58] + node _T_790 = cat(_T_789, _T_784[6]) @[Cat.scala 29:58] + node _T_791 = cat(_T_790, _T_784[7]) @[Cat.scala 29:58] + node _T_792 = cat(_T_791, _T_784[8]) @[Cat.scala 29:58] + node _T_793 = cat(_T_792, _T_784[9]) @[Cat.scala 29:58] + node _T_794 = cat(_T_793, io.dec_i0_pc4_d) @[Cat.scala 29:58] + node _T_795 = cat(_T_794, i0_ap_pc2) @[Cat.scala 29:58] + node _T_796 = mux(_T_783, _T_795, i0_br_offset) @[el2_dec_decode_ctl.scala 717:25] + last_br_immed_d <= _T_796 @[el2_dec_decode_ctl.scala 717:19] + wire last_br_immed_x : UInt<12> + last_br_immed_x <= UInt<1>("h00") + node _T_797 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 719:58] + inst rvclkhdr_10 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= _T_797 @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_798 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_798 <= last_br_immed_d @[el2_lib.scala 514:16] + last_br_immed_x <= _T_798 @[el2_dec_decode_ctl.scala 719:19] + node _T_799 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 723:40] + node _T_800 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 723:68] + node div_e1_to_r = or(_T_799, _T_800) @[el2_dec_decode_ctl.scala 723:55] + node _T_801 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 725:43] + node _T_802 = eq(x_d.i0rd, UInt<5>("h00")) @[el2_dec_decode_ctl.scala 725:69] + node _T_803 = and(_T_801, _T_802) @[el2_dec_decode_ctl.scala 725:57] + node _T_804 = and(x_d.i0div, x_d.i0valid) @[el2_dec_decode_ctl.scala 726:16] + node _T_805 = and(_T_804, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 726:30] + node _T_806 = or(_T_803, _T_805) @[el2_dec_decode_ctl.scala 725:86] + node _T_807 = and(r_d.i0div, r_d.i0valid) @[el2_dec_decode_ctl.scala 727:16] + node _T_808 = and(_T_807, io.dec_tlu_flush_lower_r) @[el2_dec_decode_ctl.scala 727:30] + node _T_809 = and(_T_808, io.dec_tlu_i0_kill_writeb_r) @[el2_dec_decode_ctl.scala 727:57] + node div_flush = or(_T_806, _T_809) @[el2_dec_decode_ctl.scala 726:59] + node _T_810 = and(io.dec_div_active, div_flush) @[el2_dec_decode_ctl.scala 731:51] + node _T_811 = eq(div_e1_to_r, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 732:26] + node _T_812 = and(io.dec_div_active, _T_811) @[el2_dec_decode_ctl.scala 732:24] + node _T_813 = eq(r_d.i0rd, io.div_waddr_wb) @[el2_dec_decode_ctl.scala 732:51] + node _T_814 = and(_T_812, _T_813) @[el2_dec_decode_ctl.scala 732:39] + node _T_815 = and(_T_814, i0_wen_r) @[el2_dec_decode_ctl.scala 732:72] + node nonblock_div_cancel = or(_T_810, _T_815) @[el2_dec_decode_ctl.scala 731:65] + node _T_816 = bits(nonblock_div_cancel, 0, 0) @[el2_dec_decode_ctl.scala 734:53] + io.dec_div_cancel <= _T_816 @[el2_dec_decode_ctl.scala 734:29] + node i0_div_decode_d = and(i0_legal_decode_d, i0_dp.div) @[el2_dec_decode_ctl.scala 735:55] + node _T_817 = eq(io.exu_div_wren, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:62] + node _T_818 = and(io.dec_div_active, _T_817) @[el2_dec_decode_ctl.scala 737:60] + node _T_819 = eq(nonblock_div_cancel, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 737:81] + node _T_820 = and(_T_818, _T_819) @[el2_dec_decode_ctl.scala 737:79] + node div_active_in = or(i0_div_decode_d, _T_820) @[el2_dec_decode_ctl.scala 737:39] + reg _T_821 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_dec_decode_ctl.scala 739:54] + _T_821 <= div_active_in @[el2_dec_decode_ctl.scala 739:54] + io.dec_div_active <= _T_821 @[el2_dec_decode_ctl.scala 739:21] + node _T_822 = and(io.dec_i0_rs1_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 742:49] + node _T_823 = eq(io.div_waddr_wb, i0r.rs1) @[el2_dec_decode_ctl.scala 742:88] + node _T_824 = and(_T_822, _T_823) @[el2_dec_decode_ctl.scala 742:69] + node _T_825 = and(io.dec_i0_rs2_en_d, io.dec_div_active) @[el2_dec_decode_ctl.scala 743:25] + node _T_826 = eq(io.div_waddr_wb, i0r.rs2) @[el2_dec_decode_ctl.scala 743:64] + node _T_827 = and(_T_825, _T_826) @[el2_dec_decode_ctl.scala 743:45] + node _T_828 = or(_T_824, _T_827) @[el2_dec_decode_ctl.scala 742:102] + i0_nonblock_div_stall <= _T_828 @[el2_dec_decode_ctl.scala 742:26] + node _T_829 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 745:59] + reg _T_830 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_829 : @[Reg.scala 28:19] + _T_830 <= i0r.rd @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + io.div_waddr_wb <= _T_830 @[el2_dec_decode_ctl.scala 745:19] + node _T_831 = bits(i0_inst_d, 24, 7) @[el2_dec_decode_ctl.scala 752:34] + node _T_832 = bits(i0_div_decode_d, 0, 0) @[el2_dec_decode_ctl.scala 752:57] + inst rvclkhdr_11 of rvclkhdr_12 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_832 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg div_inst : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + div_inst <= _T_831 @[el2_lib.scala 514:16] + node _T_833 = bits(i0_x_data_en, 0, 0) @[el2_dec_decode_ctl.scala 753:49] + inst rvclkhdr_12 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_833 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_inst_x : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_x <= i0_inst_d @[el2_lib.scala 514:16] + node _T_834 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 754:49] + inst rvclkhdr_13 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_13.io.en <= _T_834 @[el2_lib.scala 511:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_inst_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_r <= i0_inst_x @[el2_lib.scala 514:16] + node _T_835 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 756:50] + inst rvclkhdr_14 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_14.io.en <= _T_835 @[el2_lib.scala 511:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_inst_wb : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_inst_wb <= i0_inst_r @[el2_lib.scala 514:16] + node _T_836 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 757:53] + inst rvclkhdr_15 of rvclkhdr_16 @[el2_lib.scala 508:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_15.io.en <= _T_836 @[el2_lib.scala 511:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_837 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_837 <= i0_inst_wb @[el2_lib.scala 514:16] + io.dec_i0_inst_wb1 <= _T_837 @[el2_dec_decode_ctl.scala 757:22] + node _T_838 = bits(i0_wb_data_en, 0, 0) @[el2_dec_decode_ctl.scala 758:53] + inst rvclkhdr_16 of rvclkhdr_17 @[el2_lib.scala 508:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_16.io.en <= _T_838 @[el2_lib.scala 511:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_pc_wb : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pc_wb <= io.dec_tlu_i0_pc_r @[el2_lib.scala 514:16] + node _T_839 = bits(i0_wb1_data_en, 0, 0) @[el2_dec_decode_ctl.scala 760:49] + inst rvclkhdr_17 of rvclkhdr_18 @[el2_lib.scala 508:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_17.io.en <= _T_839 @[el2_lib.scala 511:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_840 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_840 <= i0_pc_wb @[el2_lib.scala 514:16] + io.dec_i0_pc_wb1 <= _T_840 @[el2_dec_decode_ctl.scala 760:20] + node _T_841 = bits(i0_r_data_en, 0, 0) @[el2_dec_decode_ctl.scala 761:56] + inst rvclkhdr_18 of rvclkhdr_19 @[el2_lib.scala 508:23] + rvclkhdr_18.clock <= clock + rvclkhdr_18.reset <= reset + rvclkhdr_18.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_18.io.en <= _T_841 @[el2_lib.scala 511:17] + rvclkhdr_18.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg dec_i0_pc_r : UInt, rvclkhdr_18.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + dec_i0_pc_r <= io.exu_i0_pc_x @[el2_lib.scala 514:16] + io.dec_tlu_i0_pc_r <= dec_i0_pc_r @[el2_dec_decode_ctl.scala 763:27] + node _T_842 = cat(io.exu_i0_pc_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_843 = cat(last_br_immed_x, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_844 = bits(_T_842, 12, 1) @[el2_lib.scala 208:24] + node _T_845 = bits(_T_843, 12, 1) @[el2_lib.scala 208:40] + node _T_846 = add(_T_844, _T_845) @[el2_lib.scala 208:31] + node _T_847 = bits(_T_842, 31, 13) @[el2_lib.scala 209:20] + node _T_848 = add(_T_847, UInt<1>("h01")) @[el2_lib.scala 209:27] + node _T_849 = tail(_T_848, 1) @[el2_lib.scala 209:27] + node _T_850 = bits(_T_842, 31, 13) @[el2_lib.scala 210:20] + node _T_851 = sub(_T_850, UInt<1>("h01")) @[el2_lib.scala 210:27] + node _T_852 = tail(_T_851, 1) @[el2_lib.scala 210:27] + node _T_853 = bits(_T_843, 12, 12) @[el2_lib.scala 211:22] + node _T_854 = bits(_T_846, 12, 12) @[el2_lib.scala 212:39] + node _T_855 = eq(_T_854, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_856 = xor(_T_853, _T_855) @[el2_lib.scala 212:26] + node _T_857 = bits(_T_856, 0, 0) @[el2_lib.scala 212:64] + node _T_858 = bits(_T_842, 31, 13) @[el2_lib.scala 212:76] + node _T_859 = eq(_T_853, UInt<1>("h00")) @[el2_lib.scala 213:8] + node _T_860 = bits(_T_846, 12, 12) @[el2_lib.scala 213:27] + node _T_861 = and(_T_859, _T_860) @[el2_lib.scala 213:14] + node _T_862 = bits(_T_861, 0, 0) @[el2_lib.scala 213:52] + node _T_863 = bits(_T_846, 12, 12) @[el2_lib.scala 214:27] + node _T_864 = eq(_T_863, UInt<1>("h00")) @[el2_lib.scala 214:16] + node _T_865 = and(_T_853, _T_864) @[el2_lib.scala 214:14] + node _T_866 = bits(_T_865, 0, 0) @[el2_lib.scala 214:52] + node _T_867 = mux(_T_857, _T_858, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_868 = mux(_T_862, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_869 = mux(_T_866, _T_852, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_870 = or(_T_867, _T_868) @[Mux.scala 27:72] + node _T_871 = or(_T_870, _T_869) @[Mux.scala 27:72] + wire _T_872 : UInt<19> @[Mux.scala 27:72] + _T_872 <= _T_871 @[Mux.scala 27:72] + node _T_873 = bits(_T_846, 11, 0) @[el2_lib.scala 214:82] + node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] + node temp_pred_correct_npc_x = cat(_T_874, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_875 = bits(temp_pred_correct_npc_x, 31, 1) @[el2_dec_decode_ctl.scala 768:51] + io.pred_correct_npc_x <= _T_875 @[el2_dec_decode_ctl.scala 768:25] + node _T_876 = and(io.dec_i0_rs1_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 772:48] + node _T_877 = eq(x_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 772:70] + node i0_rs1_depend_i0_x = and(_T_876, _T_877) @[el2_dec_decode_ctl.scala 772:58] + node _T_878 = and(io.dec_i0_rs1_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 773:48] + node _T_879 = eq(r_d.i0rd, i0r.rs1) @[el2_dec_decode_ctl.scala 773:70] + node i0_rs1_depend_i0_r = and(_T_878, _T_879) @[el2_dec_decode_ctl.scala 773:58] + node _T_880 = and(io.dec_i0_rs2_en_d, x_d.i0v) @[el2_dec_decode_ctl.scala 775:48] + node _T_881 = eq(x_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 775:70] + node i0_rs2_depend_i0_x = and(_T_880, _T_881) @[el2_dec_decode_ctl.scala 775:58] + node _T_882 = and(io.dec_i0_rs2_en_d, r_d.i0v) @[el2_dec_decode_ctl.scala 776:48] + node _T_883 = eq(r_d.i0rd, i0r.rs2) @[el2_dec_decode_ctl.scala 776:70] + node i0_rs2_depend_i0_r = and(_T_882, _T_883) @[el2_dec_decode_ctl.scala 776:58] + node _T_884 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 778:44] + node _T_885 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 778:81] + wire _T_886 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 778:109] + _T_886.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] + _T_886.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] + _T_886.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 778:109] + node _T_887 = mux(_T_885, i0_r_c, _T_886) @[el2_dec_decode_ctl.scala 778:61] + node _T_888 = mux(_T_884, i0_x_c, _T_887) @[el2_dec_decode_ctl.scala 778:24] + i0_rs1_class_d.alu <= _T_888.alu @[el2_dec_decode_ctl.scala 778:18] + i0_rs1_class_d.load <= _T_888.load @[el2_dec_decode_ctl.scala 778:18] + i0_rs1_class_d.mul <= _T_888.mul @[el2_dec_decode_ctl.scala 778:18] + node _T_889 = bits(i0_rs1_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 779:44] + node _T_890 = bits(i0_rs1_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 779:83] + node _T_891 = mux(_T_890, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 779:63] + node _T_892 = mux(_T_889, UInt<2>("h01"), _T_891) @[el2_dec_decode_ctl.scala 779:24] + i0_rs1_depth_d <= _T_892 @[el2_dec_decode_ctl.scala 779:18] + node _T_893 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 780:44] + node _T_894 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 780:81] + wire _T_895 : {mul : UInt<1>, load : UInt<1>, alu : UInt<1>} @[el2_dec_decode_ctl.scala 780:109] + _T_895.alu <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] + _T_895.load <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] + _T_895.mul <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 780:109] + node _T_896 = mux(_T_894, i0_r_c, _T_895) @[el2_dec_decode_ctl.scala 780:61] + node _T_897 = mux(_T_893, i0_x_c, _T_896) @[el2_dec_decode_ctl.scala 780:24] + i0_rs2_class_d.alu <= _T_897.alu @[el2_dec_decode_ctl.scala 780:18] + i0_rs2_class_d.load <= _T_897.load @[el2_dec_decode_ctl.scala 780:18] + i0_rs2_class_d.mul <= _T_897.mul @[el2_dec_decode_ctl.scala 780:18] + node _T_898 = bits(i0_rs2_depend_i0_x, 0, 0) @[el2_dec_decode_ctl.scala 781:44] + node _T_899 = bits(i0_rs2_depend_i0_r, 0, 0) @[el2_dec_decode_ctl.scala 781:83] + node _T_900 = mux(_T_899, UInt<2>("h02"), UInt<1>("h00")) @[el2_dec_decode_ctl.scala 781:63] + node _T_901 = mux(_T_898, UInt<2>("h01"), _T_900) @[el2_dec_decode_ctl.scala 781:24] + i0_rs2_depth_d <= _T_901 @[el2_dec_decode_ctl.scala 781:18] + i0_load_block_d <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 791:21] + node _T_902 = or(i0_dp.load, i0_dp.store) @[el2_dec_decode_ctl.scala 792:43] + node _T_903 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 792:74] + node _T_904 = and(_T_902, _T_903) @[el2_dec_decode_ctl.scala 792:58] + node _T_905 = and(_T_904, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 792:78] + load_ldst_bypass_d <= _T_905 @[el2_dec_decode_ctl.scala 792:27] + node _T_906 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 793:59] + node _T_907 = and(i0_dp.store, _T_906) @[el2_dec_decode_ctl.scala 793:43] + node _T_908 = and(_T_907, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 793:63] + store_data_bypass_d <= _T_908 @[el2_dec_decode_ctl.scala 793:25] + store_data_bypass_m <= UInt<1>("h00") @[el2_dec_decode_ctl.scala 794:25] + node _T_909 = and(io.dec_i0_rs1_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 798:62] + node _T_910 = eq(io.dec_nonblock_load_waddr, i0r.rs1) @[el2_dec_decode_ctl.scala 798:119] + node i0_rs1_nonblock_load_bypass_en_d = and(_T_909, _T_910) @[el2_dec_decode_ctl.scala 798:89] + node _T_911 = and(io.dec_i0_rs2_en_d, io.dec_nonblock_load_wen) @[el2_dec_decode_ctl.scala 800:62] + node _T_912 = eq(io.dec_nonblock_load_waddr, i0r.rs2) @[el2_dec_decode_ctl.scala 800:119] + node i0_rs2_nonblock_load_bypass_en_d = and(_T_911, _T_912) @[el2_dec_decode_ctl.scala 800:89] + node _T_913 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:41] + node _T_914 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:66] + node _T_915 = and(_T_913, _T_914) @[el2_dec_decode_ctl.scala 803:45] + node _T_916 = bits(i0_rs1_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 803:104] + node _T_917 = and(_T_916, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:108] + node _T_918 = bits(i0_rs1_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 803:149] + node _T_919 = or(i0_rs1_class_d.alu, i0_rs1_class_d.mul) @[el2_dec_decode_ctl.scala 803:175] + node _T_920 = or(_T_919, i0_rs1_class_d.load) @[el2_dec_decode_ctl.scala 803:196] + node _T_921 = and(_T_918, _T_920) @[el2_dec_decode_ctl.scala 803:153] + node _T_922 = cat(_T_915, _T_917) @[Cat.scala 29:58] + node _T_923 = cat(_T_922, _T_921) @[Cat.scala 29:58] + i0_rs1bypass <= _T_923 @[el2_dec_decode_ctl.scala 803:18] + node _T_924 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:41] + node _T_925 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:67] + node _T_926 = and(_T_924, _T_925) @[el2_dec_decode_ctl.scala 805:45] + node _T_927 = bits(i0_rs2_depth_d, 0, 0) @[el2_dec_decode_ctl.scala 805:105] + node _T_928 = and(_T_927, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:109] + node _T_929 = bits(i0_rs2_depth_d, 1, 1) @[el2_dec_decode_ctl.scala 805:149] + node _T_930 = or(i0_rs2_class_d.alu, i0_rs2_class_d.mul) @[el2_dec_decode_ctl.scala 805:175] + node _T_931 = or(_T_930, i0_rs2_class_d.load) @[el2_dec_decode_ctl.scala 805:196] + node _T_932 = and(_T_929, _T_931) @[el2_dec_decode_ctl.scala 805:153] + node _T_933 = cat(_T_926, _T_928) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_932) @[Cat.scala 29:58] + i0_rs2bypass <= _T_934 @[el2_dec_decode_ctl.scala 805:18] + node _T_935 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:54] + node _T_936 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 807:71] + node _T_937 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 807:89] + node _T_938 = or(_T_936, _T_937) @[el2_dec_decode_ctl.scala 807:75] + node _T_939 = bits(i0_rs1bypass, 2, 2) @[el2_dec_decode_ctl.scala 807:109] + node _T_940 = eq(_T_939, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 807:96] + node _T_941 = and(_T_940, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 807:113] + node _T_942 = or(_T_938, _T_941) @[el2_dec_decode_ctl.scala 807:93] + node _T_943 = cat(_T_935, _T_942) @[Cat.scala 29:58] + io.dec_i0_rs1_bypass_en_d <= _T_943 @[el2_dec_decode_ctl.scala 807:34] + node _T_944 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:54] + node _T_945 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 808:71] + node _T_946 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 808:89] + node _T_947 = or(_T_945, _T_946) @[el2_dec_decode_ctl.scala 808:75] + node _T_948 = bits(i0_rs2bypass, 2, 2) @[el2_dec_decode_ctl.scala 808:109] + node _T_949 = eq(_T_948, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 808:96] + node _T_950 = and(_T_949, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 808:113] + node _T_951 = or(_T_947, _T_950) @[el2_dec_decode_ctl.scala 808:93] + node _T_952 = cat(_T_944, _T_951) @[Cat.scala 29:58] + io.dec_i0_rs2_bypass_en_d <= _T_952 @[el2_dec_decode_ctl.scala 808:34] + node _T_953 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 811:17] + node _T_954 = bits(_T_953, 0, 0) @[el2_dec_decode_ctl.scala 811:21] + node _T_955 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 812:17] + node _T_956 = bits(_T_955, 0, 0) @[el2_dec_decode_ctl.scala 812:21] + node _T_957 = bits(i0_rs1bypass, 1, 1) @[el2_dec_decode_ctl.scala 813:19] + node _T_958 = eq(_T_957, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:6] + node _T_959 = bits(i0_rs1bypass, 0, 0) @[el2_dec_decode_ctl.scala 813:38] + node _T_960 = eq(_T_959, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 813:25] + node _T_961 = and(_T_958, _T_960) @[el2_dec_decode_ctl.scala 813:23] + node _T_962 = and(_T_961, i0_rs1_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 813:42] + node _T_963 = bits(_T_962, 0, 0) @[el2_dec_decode_ctl.scala 813:78] + node _T_964 = mux(_T_954, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_965 = mux(_T_956, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_966 = mux(_T_963, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_967 = or(_T_964, _T_965) @[Mux.scala 27:72] + node _T_968 = or(_T_967, _T_966) @[Mux.scala 27:72] + wire _T_969 : UInt<32> @[Mux.scala 27:72] + _T_969 <= _T_968 @[Mux.scala 27:72] + io.dec_i0_rs1_bypass_data_d <= _T_969 @[el2_dec_decode_ctl.scala 810:31] + node _T_970 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 816:17] + node _T_971 = bits(_T_970, 0, 0) @[el2_dec_decode_ctl.scala 816:21] + node _T_972 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 817:17] + node _T_973 = bits(_T_972, 0, 0) @[el2_dec_decode_ctl.scala 817:21] + node _T_974 = bits(i0_rs2bypass, 1, 1) @[el2_dec_decode_ctl.scala 818:19] + node _T_975 = eq(_T_974, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:6] + node _T_976 = bits(i0_rs2bypass, 0, 0) @[el2_dec_decode_ctl.scala 818:38] + node _T_977 = eq(_T_976, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 818:25] + node _T_978 = and(_T_975, _T_977) @[el2_dec_decode_ctl.scala 818:23] + node _T_979 = and(_T_978, i0_rs2_nonblock_load_bypass_en_d) @[el2_dec_decode_ctl.scala 818:42] + node _T_980 = bits(_T_979, 0, 0) @[el2_dec_decode_ctl.scala 818:78] + node _T_981 = mux(_T_971, io.lsu_result_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_982 = mux(_T_973, i0_result_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_983 = mux(_T_980, io.lsu_nonblock_load_data, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_984 = or(_T_981, _T_982) @[Mux.scala 27:72] + node _T_985 = or(_T_984, _T_983) @[Mux.scala 27:72] + wire _T_986 : UInt<32> @[Mux.scala 27:72] + _T_986 <= _T_985 @[Mux.scala 27:72] + io.dec_i0_rs2_bypass_data_d <= _T_986 @[el2_dec_decode_ctl.scala 815:31] + node _T_987 = or(i0_dp_raw.load, i0_dp_raw.store) @[el2_dec_decode_ctl.scala 820:68] + node _T_988 = and(io.dec_ib0_valid_d, _T_987) @[el2_dec_decode_ctl.scala 820:50] + node _T_989 = eq(io.dma_dccm_stall_any, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:89] + node _T_990 = and(_T_988, _T_989) @[el2_dec_decode_ctl.scala 820:87] + node _T_991 = eq(i0_block_raw_d, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 820:114] + node _T_992 = and(_T_990, _T_991) @[el2_dec_decode_ctl.scala 820:112] + node _T_993 = or(_T_992, io.dec_extint_stall) @[el2_dec_decode_ctl.scala 820:131] + io.dec_lsu_valid_raw_d <= _T_993 @[el2_dec_decode_ctl.scala 820:26] + node _T_994 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 822:6] + node _T_995 = and(_T_994, i0_dp.lsu) @[el2_dec_decode_ctl.scala 822:27] + node _T_996 = and(_T_995, i0_dp.load) @[el2_dec_decode_ctl.scala 822:39] + node _T_997 = bits(_T_996, 0, 0) @[el2_dec_decode_ctl.scala 822:53] + node _T_998 = bits(io.dec_i0_instr_d, 31, 20) @[el2_dec_decode_ctl.scala 822:70] + node _T_999 = eq(io.dec_extint_stall, UInt<1>("h00")) @[el2_dec_decode_ctl.scala 823:6] + node _T_1000 = and(_T_999, i0_dp.lsu) @[el2_dec_decode_ctl.scala 823:27] + node _T_1001 = and(_T_1000, i0_dp.store) @[el2_dec_decode_ctl.scala 823:39] + node _T_1002 = bits(_T_1001, 0, 0) @[el2_dec_decode_ctl.scala 823:54] + node _T_1003 = bits(io.dec_i0_instr_d, 31, 25) @[el2_dec_decode_ctl.scala 823:74] + node _T_1004 = bits(io.dec_i0_instr_d, 11, 7) @[el2_dec_decode_ctl.scala 823:84] + node _T_1005 = cat(_T_1003, _T_1004) @[Cat.scala 29:58] + node _T_1006 = mux(_T_997, _T_998, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1007 = mux(_T_1002, _T_1005, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1008 = or(_T_1006, _T_1007) @[Mux.scala 27:72] + wire _T_1009 : UInt<12> @[Mux.scala 27:72] + _T_1009 <= _T_1008 @[Mux.scala 27:72] + io.dec_lsu_offset_d <= _T_1009 @[el2_dec_decode_ctl.scala 821:23] + diff --git a/el2_dec_decode_ctl.v b/el2_dec_decode_ctl.v new file mode 100644 index 00000000..bc33c737 --- /dev/null +++ b/el2_dec_decode_ctl.v @@ -0,0 +1,3386 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_dec_dec_ctl( + input [31:0] io_ins, + output io_out_alu, + output io_out_rs1, + output io_out_rs2, + output io_out_imm12, + output io_out_rd, + output io_out_shimm5, + output io_out_imm20, + output io_out_pc, + output io_out_load, + output io_out_store, + output io_out_lsu, + output io_out_add, + output io_out_sub, + output io_out_land, + output io_out_lor, + output io_out_lxor, + output io_out_sll, + output io_out_sra, + output io_out_srl, + output io_out_slt, + output io_out_unsign, + output io_out_condbr, + output io_out_beq, + output io_out_bne, + output io_out_bge, + output io_out_blt, + output io_out_jal, + output io_out_by, + output io_out_half, + output io_out_word, + output io_out_csr_read, + output io_out_csr_clr, + output io_out_csr_set, + output io_out_csr_write, + output io_out_csr_imm, + output io_out_presync, + output io_out_postsync, + output io_out_ebreak, + output io_out_ecall, + output io_out_mret, + output io_out_mul, + output io_out_rs1_sign, + output io_out_rs2_sign, + output io_out_low, + output io_out_div, + output io_out_rem, + output io_out_fence, + output io_out_fence_i, + output io_out_pm_alu, + output io_out_legal +); + wire _T_2 = io_ins[2] | io_ins[6]; // @[el2_dec_dec_ctl.scala 72:27] + wire _T_4 = ~io_ins[25]; // @[el2_dec_dec_ctl.scala 72:42] + wire _T_6 = _T_4 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:53] + wire _T_7 = _T_2 | _T_6; // @[el2_dec_dec_ctl.scala 72:39] + wire _T_9 = ~io_ins[5]; // @[el2_dec_dec_ctl.scala 72:68] + wire _T_11 = _T_9 & io_ins[4]; // @[el2_dec_dec_ctl.scala 72:78] + wire _T_14 = ~io_ins[14]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_16 = ~io_ins[13]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_18 = ~io_ins[2]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_19 = _T_14 & _T_16; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_20 = _T_19 & _T_18; // @[el2_dec_dec_ctl.scala 73:51] + wire _T_26 = _T_16 & io_ins[11]; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_27 = _T_26 & _T_18; // @[el2_dec_dec_ctl.scala 73:90] + wire _T_28 = _T_20 | _T_27; // @[el2_dec_dec_ctl.scala 73:55] + wire _T_33 = io_ins[19] & io_ins[13]; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_34 = _T_33 & _T_18; // @[el2_dec_dec_ctl.scala 74:37] + wire _T_35 = _T_28 | _T_34; // @[el2_dec_dec_ctl.scala 73:94] + wire _T_41 = _T_16 & io_ins[10]; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_42 = _T_41 & _T_18; // @[el2_dec_dec_ctl.scala 74:76] + wire _T_43 = _T_35 | _T_42; // @[el2_dec_dec_ctl.scala 74:41] + wire _T_45 = ~io_ins[18]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_49 = _T_45 & io_ins[13]; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_50 = _T_49 & _T_18; // @[el2_dec_dec_ctl.scala 75:38] + wire _T_51 = _T_43 | _T_50; // @[el2_dec_dec_ctl.scala 74:80] + wire _T_57 = _T_16 & io_ins[9]; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_58 = _T_57 & _T_18; // @[el2_dec_dec_ctl.scala 75:76] + wire _T_59 = _T_51 | _T_58; // @[el2_dec_dec_ctl.scala 75:42] + wire _T_64 = io_ins[17] & io_ins[13]; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_65 = _T_64 & _T_18; // @[el2_dec_dec_ctl.scala 76:37] + wire _T_66 = _T_59 | _T_65; // @[el2_dec_dec_ctl.scala 75:80] + wire _T_72 = _T_16 & io_ins[8]; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_73 = _T_72 & _T_18; // @[el2_dec_dec_ctl.scala 76:75] + wire _T_74 = _T_66 | _T_73; // @[el2_dec_dec_ctl.scala 76:41] + wire _T_79 = io_ins[16] & io_ins[13]; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_80 = _T_79 & _T_18; // @[el2_dec_dec_ctl.scala 77:37] + wire _T_81 = _T_74 | _T_80; // @[el2_dec_dec_ctl.scala 76:79] + wire _T_87 = _T_16 & io_ins[7]; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_88 = _T_87 & _T_18; // @[el2_dec_dec_ctl.scala 77:75] + wire _T_89 = _T_81 | _T_88; // @[el2_dec_dec_ctl.scala 77:41] + wire _T_94 = io_ins[15] & io_ins[13]; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_95 = _T_94 & _T_18; // @[el2_dec_dec_ctl.scala 78:37] + wire _T_96 = _T_89 | _T_95; // @[el2_dec_dec_ctl.scala 77:79] + wire _T_98 = ~io_ins[4]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_100 = ~io_ins[3]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_101 = _T_98 & _T_100; // @[el2_dec_dec_ctl.scala 78:71] + wire _T_102 = _T_96 | _T_101; // @[el2_dec_dec_ctl.scala 78:41] + wire _T_104 = ~io_ins[6]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_107 = _T_104 & _T_18; // @[el2_dec_dec_ctl.scala 78:106] + wire _T_114 = io_ins[5] & _T_98; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_115 = _T_114 & _T_18; // @[el2_dec_dec_ctl.scala 79:48] + wire _T_121 = _T_104 & io_ins[5]; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_122 = _T_121 & _T_18; // @[el2_dec_dec_ctl.scala 79:85] + wire _T_130 = _T_101 & io_ins[2]; // @[el2_dec_dec_ctl.scala 80:50] + wire _T_137 = io_ins[13] & _T_9; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_138 = _T_137 & io_ins[4]; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_139 = _T_138 & _T_18; // @[el2_dec_dec_ctl.scala 80:90] + wire _T_140 = _T_130 | _T_139; // @[el2_dec_dec_ctl.scala 80:54] + wire _T_144 = ~io_ins[12]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_147 = _T_16 & _T_144; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_148 = _T_147 & io_ins[6]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_149 = _T_148 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:40] + wire _T_150 = _T_140 | _T_149; // @[el2_dec_dec_ctl.scala 80:94] + wire _T_158 = _T_144 & _T_9; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_159 = _T_158 & io_ins[4]; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_160 = _T_159 & _T_18; // @[el2_dec_dec_ctl.scala 81:81] + wire _T_166 = _T_9 & _T_18; // @[el2_dec_dec_ctl.scala 82:28] + wire _T_169 = io_ins[5] & io_ins[2]; // @[el2_dec_dec_ctl.scala 82:55] + wire _T_170 = _T_166 | _T_169; // @[el2_dec_dec_ctl.scala 82:42] + wire _T_181 = _T_16 & io_ins[12]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_182 = _T_181 & _T_9; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_183 = _T_182 & io_ins[4]; // @[el2_dec_dec_ctl.scala 83:58] + wire _T_187 = io_ins[5] & io_ins[3]; // @[el2_dec_dec_ctl.scala 84:29] + wire _T_190 = io_ins[4] & io_ins[2]; // @[el2_dec_dec_ctl.scala 84:53] + wire _T_196 = _T_9 & _T_100; // @[el2_dec_dec_ctl.scala 85:28] + wire _T_198 = _T_196 & io_ins[2]; // @[el2_dec_dec_ctl.scala 85:41] + wire _T_209 = _T_9 & _T_98; // @[el2_dec_dec_ctl.scala 86:50] + wire _T_224 = _T_104 & _T_98; // @[el2_dec_dec_ctl.scala 88:49] + wire _T_236 = _T_19 & _T_144; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_237 = _T_236 & _T_9; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_238 = _T_237 & io_ins[4]; // @[el2_dec_dec_ctl.scala 89:57] + wire _T_246 = _T_238 | _T_198; // @[el2_dec_dec_ctl.scala 89:61] + wire _T_248 = ~io_ins[30]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_262 = _T_248 & _T_4; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_263 = _T_262 & _T_14; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_264 = _T_263 & _T_16; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_265 = _T_264 & _T_144; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_266 = _T_265 & _T_104; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_267 = _T_266 & io_ins[4]; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_268 = _T_267 & _T_18; // @[el2_dec_dec_ctl.scala 90:56] + wire _T_279 = io_ins[30] & _T_144; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_280 = _T_279 & _T_104; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_281 = _T_280 & io_ins[5]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_282 = _T_281 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_283 = _T_282 & _T_18; // @[el2_dec_dec_ctl.scala 91:57] + wire _T_294 = _T_4 & _T_14; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_295 = _T_294 & io_ins[13]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_296 = _T_295 & _T_104; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_297 = _T_296 & io_ins[4]; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_298 = _T_297 & _T_18; // @[el2_dec_dec_ctl.scala 91:105] + wire _T_299 = _T_283 | _T_298; // @[el2_dec_dec_ctl.scala 91:61] + wire _T_308 = _T_14 & io_ins[13]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_309 = _T_308 & _T_9; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_310 = _T_309 & io_ins[4]; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_311 = _T_310 & _T_18; // @[el2_dec_dec_ctl.scala 92:43] + wire _T_312 = _T_299 | _T_311; // @[el2_dec_dec_ctl.scala 91:109] + wire _T_318 = io_ins[6] & _T_98; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_319 = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 92:80] + wire _T_328 = io_ins[14] & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_329 = _T_328 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_330 = _T_329 & _T_9; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_331 = _T_330 & _T_18; // @[el2_dec_dec_ctl.scala 93:56] + wire _T_341 = _T_4 & io_ins[14]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_342 = _T_341 & io_ins[13]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_343 = _T_342 & io_ins[12]; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_344 = _T_343 & _T_104; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_345 = _T_344 & _T_18; // @[el2_dec_dec_ctl.scala 93:104] + wire _T_350 = _T_104 & io_ins[3]; // @[el2_dec_dec_ctl.scala 94:45] + wire _T_363 = _T_342 & _T_144; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_364 = _T_363 & _T_104; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_365 = _T_364 & _T_18; // @[el2_dec_dec_ctl.scala 94:94] + wire _T_366 = _T_350 | _T_365; // @[el2_dec_dec_ctl.scala 94:49] + wire _T_370 = io_ins[5] & io_ins[4]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_371 = _T_370 & io_ins[2]; // @[el2_dec_dec_ctl.scala 95:34] + wire _T_372 = _T_366 | _T_371; // @[el2_dec_dec_ctl.scala 94:98] + wire _T_382 = _T_372 | _T_149; // @[el2_dec_dec_ctl.scala 95:38] + wire _T_392 = _T_328 & _T_144; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_393 = _T_392 & _T_9; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_394 = _T_393 & _T_18; // @[el2_dec_dec_ctl.scala 96:44] + wire _T_407 = _T_341 & _T_16; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_408 = _T_407 & _T_144; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_409 = _T_408 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_410 = _T_409 & _T_18; // @[el2_dec_dec_ctl.scala 97:61] + wire _T_421 = io_ins[14] & _T_16; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_422 = _T_421 & _T_144; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_423 = _T_422 & _T_9; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_424 = _T_423 & io_ins[4]; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_425 = _T_424 & _T_18; // @[el2_dec_dec_ctl.scala 97:109] + wire _T_440 = _T_294 & _T_16; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_441 = _T_440 & io_ins[12]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_442 = _T_441 & _T_104; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_443 = _T_442 & io_ins[4]; // @[el2_dec_dec_ctl.scala 98:63] + wire _T_454 = io_ins[30] & _T_16; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_455 = _T_454 & io_ins[12]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_456 = _T_455 & _T_104; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_457 = _T_456 & io_ins[4]; // @[el2_dec_dec_ctl.scala 99:58] + wire _T_473 = _T_262 & io_ins[14]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_474 = _T_473 & _T_16; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_475 = _T_474 & io_ins[12]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_476 = _T_475 & _T_104; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_477 = _T_476 & io_ins[4]; // @[el2_dec_dec_ctl.scala 100:66] + wire _T_492 = _T_295 & io_ins[12]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_493 = _T_492 & _T_104; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_494 = _T_493 & io_ins[4]; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_495 = _T_494 & _T_18; // @[el2_dec_dec_ctl.scala 101:62] + wire _T_518 = _T_308 & io_ins[12]; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_519 = _T_518 & _T_9; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_520 = _T_519 & _T_18; // @[el2_dec_dec_ctl.scala 102:59] + wire _T_527 = io_ins[13] & io_ins[6]; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_528 = _T_527 & _T_98; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_529 = _T_528 & _T_18; // @[el2_dec_dec_ctl.scala 102:99] + wire _T_530 = _T_520 | _T_529; // @[el2_dec_dec_ctl.scala 102:63] + wire _T_536 = io_ins[14] & _T_9; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_537 = _T_536 & _T_98; // @[el2_dec_dec_ctl.scala 103:37] + wire _T_538 = _T_530 | _T_537; // @[el2_dec_dec_ctl.scala 102:103] + wire _T_553 = _T_493 & _T_18; // @[el2_dec_dec_ctl.scala 103:86] + wire _T_554 = _T_538 | _T_553; // @[el2_dec_dec_ctl.scala 103:41] + wire _T_563 = io_ins[25] & io_ins[14]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_564 = _T_563 & io_ins[12]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_565 = _T_564 & _T_104; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_566 = _T_565 & io_ins[5]; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_567 = _T_566 & _T_18; // @[el2_dec_dec_ctl.scala 104:45] + wire _T_585 = _T_14 & _T_144; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_586 = _T_585 & io_ins[6]; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_587 = _T_586 & _T_98; // @[el2_dec_dec_ctl.scala 106:56] + wire _T_597 = _T_14 & io_ins[12]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_598 = _T_597 & io_ins[6]; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_599 = _T_598 & _T_98; // @[el2_dec_dec_ctl.scala 107:55] + wire _T_608 = io_ins[14] & io_ins[12]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_609 = _T_608 & io_ins[5]; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_610 = _T_609 & _T_98; // @[el2_dec_dec_ctl.scala 108:54] + wire _T_620 = io_ins[14] & _T_144; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_621 = _T_620 & io_ins[5]; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_622 = _T_621 & _T_98; // @[el2_dec_dec_ctl.scala 109:55] + wire _T_638 = _T_147 & _T_104; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_639 = _T_638 & _T_98; // @[el2_dec_dec_ctl.scala 111:56] + wire _T_648 = io_ins[12] & _T_104; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_649 = _T_648 & _T_98; // @[el2_dec_dec_ctl.scala 112:53] + wire _T_656 = io_ins[13] & _T_104; // @[el2_dec_dec_ctl.scala 113:50] + wire _T_662 = _T_527 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:52] + wire _T_666 = io_ins[7] & io_ins[6]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_667 = _T_666 & io_ins[4]; // @[el2_dec_dec_ctl.scala 114:87] + wire _T_668 = _T_662 | _T_667; // @[el2_dec_dec_ctl.scala 114:56] + wire _T_672 = io_ins[8] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_673 = _T_672 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:34] + wire _T_674 = _T_668 | _T_673; // @[el2_dec_dec_ctl.scala 114:91] + wire _T_678 = io_ins[9] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_679 = _T_678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:69] + wire _T_680 = _T_674 | _T_679; // @[el2_dec_dec_ctl.scala 115:38] + wire _T_684 = io_ins[10] & io_ins[6]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_685 = _T_684 & io_ins[4]; // @[el2_dec_dec_ctl.scala 115:105] + wire _T_686 = _T_680 | _T_685; // @[el2_dec_dec_ctl.scala 115:73] + wire _T_690 = io_ins[11] & io_ins[6]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_691 = _T_690 & io_ins[4]; // @[el2_dec_dec_ctl.scala 116:35] + wire _T_699 = _T_94 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_700 = _T_699 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_701 = _T_700 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:57] + wire _T_708 = _T_79 & io_ins[12]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_709 = _T_708 & io_ins[6]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_710 = _T_709 & io_ins[4]; // @[el2_dec_dec_ctl.scala 117:99] + wire _T_711 = _T_701 | _T_710; // @[el2_dec_dec_ctl.scala 117:61] + wire _T_718 = _T_64 & io_ins[12]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_719 = _T_718 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_720 = _T_719 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:41] + wire _T_721 = _T_711 | _T_720; // @[el2_dec_dec_ctl.scala 117:103] + wire _T_727 = io_ins[18] & _T_144; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_728 = _T_727 & io_ins[6]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_729 = _T_728 & io_ins[4]; // @[el2_dec_dec_ctl.scala 118:81] + wire _T_730 = _T_721 | _T_729; // @[el2_dec_dec_ctl.scala 118:45] + wire _T_736 = io_ins[19] & _T_144; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_737 = _T_736 & io_ins[6]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_738 = _T_737 & io_ins[4]; // @[el2_dec_dec_ctl.scala 119:39] + wire _T_746 = _T_181 & io_ins[6]; // @[el2_dec_dec_ctl.scala 120:57] + wire _T_754 = _T_421 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_755 = _T_754 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:55] + wire _T_760 = io_ins[15] & io_ins[14]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_761 = _T_760 & io_ins[6]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_762 = _T_761 & io_ins[4]; // @[el2_dec_dec_ctl.scala 121:94] + wire _T_763 = _T_755 | _T_762; // @[el2_dec_dec_ctl.scala 121:59] + wire _T_768 = io_ins[16] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_769 = _T_768 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_770 = _T_769 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:38] + wire _T_771 = _T_763 | _T_770; // @[el2_dec_dec_ctl.scala 121:98] + wire _T_776 = io_ins[17] & io_ins[14]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_777 = _T_776 & io_ins[6]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_778 = _T_777 & io_ins[4]; // @[el2_dec_dec_ctl.scala 122:77] + wire _T_779 = _T_771 | _T_778; // @[el2_dec_dec_ctl.scala 122:42] + wire _T_784 = io_ins[18] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_785 = _T_784 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_786 = _T_785 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:38] + wire _T_787 = _T_779 | _T_786; // @[el2_dec_dec_ctl.scala 122:81] + wire _T_792 = io_ins[19] & io_ins[14]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_793 = _T_792 & io_ins[6]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_794 = _T_793 & io_ins[4]; // @[el2_dec_dec_ctl.scala 123:77] + wire _T_801 = io_ins[15] & _T_144; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_802 = _T_801 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_803 = _T_802 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:55] + wire _T_809 = io_ins[16] & _T_144; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_810 = _T_809 & io_ins[6]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_811 = _T_810 & io_ins[4]; // @[el2_dec_dec_ctl.scala 124:95] + wire _T_812 = _T_803 | _T_811; // @[el2_dec_dec_ctl.scala 124:59] + wire _T_818 = io_ins[17] & _T_144; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_819 = _T_818 & io_ins[6]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_820 = _T_819 & io_ins[4]; // @[el2_dec_dec_ctl.scala 125:39] + wire _T_821 = _T_812 | _T_820; // @[el2_dec_dec_ctl.scala 124:99] + wire _T_830 = _T_821 | _T_729; // @[el2_dec_dec_ctl.scala 125:43] + wire _T_841 = ~io_ins[22]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_849 = _T_841 & io_ins[20]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_850 = _T_849 & _T_16; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_851 = _T_850 & _T_144; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_852 = _T_851 & io_ins[6]; // @[el2_dec_dec_ctl.scala 127:62] + wire _T_855 = ~io_ins[21]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_857 = ~io_ins[20]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_864 = _T_855 & _T_857; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_865 = _T_864 & _T_16; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_866 = _T_865 & _T_144; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_867 = _T_866 & io_ins[6]; // @[el2_dec_dec_ctl.scala 128:62] + wire _T_876 = io_ins[29] & _T_16; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_877 = _T_876 & _T_144; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_878 = _T_877 & io_ins[6]; // @[el2_dec_dec_ctl.scala 129:56] + wire _T_889 = io_ins[25] & _T_14; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_890 = _T_889 & _T_104; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_891 = _T_890 & io_ins[5]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_892 = _T_891 & io_ins[4]; // @[el2_dec_dec_ctl.scala 130:57] + wire _T_907 = _T_889 & io_ins[13]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_908 = _T_907 & _T_144; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_909 = _T_908 & _T_104; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_910 = _T_909 & io_ins[5]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_911 = _T_910 & io_ins[4]; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_912 = _T_911 & _T_18; // @[el2_dec_dec_ctl.scala 131:69] + wire _T_925 = _T_889 & _T_16; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_926 = _T_925 & io_ins[12]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_927 = _T_926 & _T_104; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_928 = _T_927 & io_ins[4]; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_929 = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 132:50] + wire _T_961 = _T_925 & _T_144; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_962 = _T_961 & io_ins[5]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_963 = _T_962 & io_ins[4]; // @[el2_dec_dec_ctl.scala 134:62] + wire _T_973 = _T_563 & _T_104; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_974 = _T_973 & io_ins[5]; // @[el2_dec_dec_ctl.scala 135:54] + wire _T_985 = _T_563 & io_ins[13]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_986 = _T_985 & _T_104; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_987 = _T_986 & io_ins[5]; // @[el2_dec_dec_ctl.scala 136:57] + wire _T_992 = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:47] + wire _T_997 = io_ins[12] & _T_9; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_998 = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:52] + wire _T_1006 = io_ins[28] & io_ins[22]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1007 = _T_1006 & _T_16; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1008 = _T_1007 & _T_144; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1009 = _T_1008 & io_ins[4]; // @[el2_dec_dec_ctl.scala 139:59] + wire _T_1013 = _T_1009 | _T_190; // @[el2_dec_dec_ctl.scala 139:63] + wire _T_1019 = _T_4 & _T_104; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1020 = _T_1019 & io_ins[4]; // @[el2_dec_dec_ctl.scala 140:37] + wire _T_1021 = _T_1013 | _T_1020; // @[el2_dec_dec_ctl.scala 139:96] + wire _T_1037 = _T_87 & io_ins[6]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1038 = _T_1037 & io_ins[4]; // @[el2_dec_dec_ctl.scala 141:88] + wire _T_1039 = _T_992 | _T_1038; // @[el2_dec_dec_ctl.scala 141:53] + wire _T_1046 = _T_72 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1047 = _T_1046 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:38] + wire _T_1048 = _T_1039 | _T_1047; // @[el2_dec_dec_ctl.scala 141:92] + wire _T_1055 = _T_57 & io_ins[6]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1056 = _T_1055 & io_ins[4]; // @[el2_dec_dec_ctl.scala 142:77] + wire _T_1057 = _T_1048 | _T_1056; // @[el2_dec_dec_ctl.scala 142:42] + wire _T_1066 = _T_1057 | _T_1056; // @[el2_dec_dec_ctl.scala 142:81] + wire _T_1073 = _T_41 & io_ins[6]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1074 = _T_1073 & io_ins[4]; // @[el2_dec_dec_ctl.scala 143:78] + wire _T_1075 = _T_1066 | _T_1074; // @[el2_dec_dec_ctl.scala 143:42] + wire _T_1082 = _T_26 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1083 = _T_1082 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:39] + wire _T_1084 = _T_1075 | _T_1083; // @[el2_dec_dec_ctl.scala 143:82] + wire _T_1090 = _T_94 & io_ins[6]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1091 = _T_1090 & io_ins[4]; // @[el2_dec_dec_ctl.scala 144:78] + wire _T_1092 = _T_1084 | _T_1091; // @[el2_dec_dec_ctl.scala 144:43] + wire _T_1098 = _T_79 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1099 = _T_1098 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:38] + wire _T_1100 = _T_1092 | _T_1099; // @[el2_dec_dec_ctl.scala 144:82] + wire _T_1106 = _T_64 & io_ins[6]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1107 = _T_1106 & io_ins[4]; // @[el2_dec_dec_ctl.scala 145:77] + wire _T_1108 = _T_1100 | _T_1107; // @[el2_dec_dec_ctl.scala 145:42] + wire _T_1113 = io_ins[18] & io_ins[13]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1114 = _T_1113 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1115 = _T_1114 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:38] + wire _T_1116 = _T_1108 | _T_1115; // @[el2_dec_dec_ctl.scala 145:81] + wire _T_1122 = _T_33 & io_ins[6]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1123 = _T_1122 & io_ins[4]; // @[el2_dec_dec_ctl.scala 146:77] + wire _T_1139 = _T_841 & _T_16; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1140 = _T_1139 & _T_144; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1141 = _T_1140 & io_ins[6]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1142 = _T_1141 & io_ins[4]; // @[el2_dec_dec_ctl.scala 147:98] + wire _T_1143 = _T_998 | _T_1142; // @[el2_dec_dec_ctl.scala 147:57] + wire _T_1152 = _T_1143 | _T_1038; // @[el2_dec_dec_ctl.scala 147:102] + wire _T_1161 = _T_1152 | _T_1047; // @[el2_dec_dec_ctl.scala 148:42] + wire _T_1170 = _T_1161 | _T_1056; // @[el2_dec_dec_ctl.scala 148:81] + wire _T_1179 = _T_1170 | _T_1074; // @[el2_dec_dec_ctl.scala 149:42] + wire _T_1188 = _T_1179 | _T_1083; // @[el2_dec_dec_ctl.scala 149:82] + wire _T_1196 = _T_1188 | _T_1091; // @[el2_dec_dec_ctl.scala 150:43] + wire _T_1204 = _T_1196 | _T_1099; // @[el2_dec_dec_ctl.scala 150:82] + wire _T_1212 = _T_1204 | _T_1107; // @[el2_dec_dec_ctl.scala 151:42] + wire _T_1220 = _T_1212 | _T_1115; // @[el2_dec_dec_ctl.scala 151:81] + wire _T_1230 = ~io_ins[31]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1236 = ~io_ins[27]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1238 = ~io_ins[26]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1242 = ~io_ins[24]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1244 = ~io_ins[23]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1251 = ~io_ins[19]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1255 = ~io_ins[17]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1257 = ~io_ins[16]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1259 = ~io_ins[15]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1263 = ~io_ins[11]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1265 = ~io_ins[10]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1267 = ~io_ins[9]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1269 = ~io_ins[8]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1271 = ~io_ins[7]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1281 = ~io_ins[0]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1282 = _T_1230 & _T_248; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1283 = _T_1282 & io_ins[29]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1284 = _T_1283 & io_ins[28]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1285 = _T_1284 & _T_1236; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1286 = _T_1285 & _T_1238; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1287 = _T_1286 & _T_4; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1288 = _T_1287 & _T_1242; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1289 = _T_1288 & _T_1244; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1290 = _T_1289 & _T_841; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1291 = _T_1290 & io_ins[21]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1292 = _T_1291 & _T_857; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1293 = _T_1292 & _T_1251; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1294 = _T_1293 & _T_45; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1295 = _T_1294 & _T_1255; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1296 = _T_1295 & _T_1257; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1297 = _T_1296 & _T_1259; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1298 = _T_1297 & _T_14; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1299 = _T_1298 & _T_1263; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1300 = _T_1299 & _T_1265; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1301 = _T_1300 & _T_1267; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1302 = _T_1301 & _T_1269; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1303 = _T_1302 & _T_1271; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1304 = _T_1303 & io_ins[6]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1305 = _T_1304 & io_ins[5]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1306 = _T_1305 & io_ins[4]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1307 = _T_1306 & _T_100; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1308 = _T_1307 & _T_18; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1309 = _T_1308 & io_ins[1]; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1310 = _T_1309 & _T_1281; // @[el2_dec_dec_ctl.scala 153:144] + wire _T_1316 = ~io_ins[29]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1365 = _T_1282 & _T_1316; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1366 = _T_1365 & io_ins[28]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1367 = _T_1366 & _T_1236; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1368 = _T_1367 & _T_1238; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1369 = _T_1368 & _T_4; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1370 = _T_1369 & _T_1242; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1371 = _T_1370 & _T_1244; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1372 = _T_1371 & io_ins[22]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1373 = _T_1372 & _T_855; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1374 = _T_1373 & io_ins[20]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1375 = _T_1374 & _T_1251; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1376 = _T_1375 & _T_45; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1377 = _T_1376 & _T_1255; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1378 = _T_1377 & _T_1257; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1379 = _T_1378 & _T_1259; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1380 = _T_1379 & _T_14; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1381 = _T_1380 & _T_1263; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1382 = _T_1381 & _T_1265; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1383 = _T_1382 & _T_1267; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1384 = _T_1383 & _T_1269; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1385 = _T_1384 & _T_1271; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1386 = _T_1385 & io_ins[6]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1387 = _T_1386 & io_ins[5]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1388 = _T_1387 & io_ins[4]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1389 = _T_1388 & _T_100; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1390 = _T_1389 & _T_18; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1391 = _T_1390 & io_ins[1]; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1392 = _T_1391 & _T_1281; // @[el2_dec_dec_ctl.scala 154:130] + wire _T_1393 = _T_1310 | _T_1392; // @[el2_dec_dec_ctl.scala 153:148] + wire _T_1401 = ~io_ins[28]; // @[el2_dec_dec_ctl.scala 67:45] + wire _T_1449 = _T_1365 & _T_1401; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1450 = _T_1449 & _T_1236; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1451 = _T_1450 & _T_1238; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1452 = _T_1451 & _T_4; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1453 = _T_1452 & _T_1242; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1454 = _T_1453 & _T_1244; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1455 = _T_1454 & _T_841; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1456 = _T_1455 & _T_855; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1457 = _T_1456 & _T_1251; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1458 = _T_1457 & _T_45; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1459 = _T_1458 & _T_1255; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1460 = _T_1459 & _T_1257; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1461 = _T_1460 & _T_1259; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1462 = _T_1461 & _T_14; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1463 = _T_1462 & _T_1263; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1464 = _T_1463 & _T_1265; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1465 = _T_1464 & _T_1267; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1466 = _T_1465 & _T_1269; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1467 = _T_1466 & _T_1271; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1468 = _T_1467 & io_ins[5]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1469 = _T_1468 & io_ins[4]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1470 = _T_1469 & _T_100; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1471 = _T_1470 & _T_18; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1472 = _T_1471 & io_ins[1]; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1473 = _T_1472 & _T_1281; // @[el2_dec_dec_ctl.scala 155:127] + wire _T_1474 = _T_1393 | _T_1473; // @[el2_dec_dec_ctl.scala 154:134] + wire _T_1503 = _T_1452 & _T_104; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1504 = _T_1503 & io_ins[4]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1505 = _T_1504 & _T_100; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1506 = _T_1505 & io_ins[1]; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1507 = _T_1506 & _T_1281; // @[el2_dec_dec_ctl.scala 156:68] + wire _T_1508 = _T_1474 | _T_1507; // @[el2_dec_dec_ctl.scala 155:131] + wire _T_1536 = _T_1230 & _T_1316; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1537 = _T_1536 & _T_1401; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1538 = _T_1537 & _T_1236; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1539 = _T_1538 & _T_1238; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1540 = _T_1539 & _T_4; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1541 = _T_1540 & _T_14; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1542 = _T_1541 & _T_16; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1543 = _T_1542 & _T_144; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1544 = _T_1543 & _T_104; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1545 = _T_1544 & _T_100; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1546 = _T_1545 & _T_18; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1547 = _T_1546 & io_ins[1]; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1548 = _T_1547 & _T_1281; // @[el2_dec_dec_ctl.scala 157:77] + wire _T_1549 = _T_1508 | _T_1548; // @[el2_dec_dec_ctl.scala 156:72] + wire _T_1579 = _T_1540 & io_ins[14]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1580 = _T_1579 & _T_16; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1581 = _T_1580 & io_ins[12]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1582 = _T_1581 & _T_104; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1583 = _T_1582 & io_ins[4]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1584 = _T_1583 & _T_100; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1585 = _T_1584 & io_ins[1]; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1586 = _T_1585 & _T_1281; // @[el2_dec_dec_ctl.scala 158:74] + wire _T_1587 = _T_1549 | _T_1586; // @[el2_dec_dec_ctl.scala 157:81] + wire _T_1614 = _T_1451 & _T_104; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1615 = _T_1614 & io_ins[5]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1616 = _T_1615 & io_ins[4]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1617 = _T_1616 & _T_100; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1618 = _T_1617 & io_ins[1]; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1619 = _T_1618 & _T_1281; // @[el2_dec_dec_ctl.scala 159:66] + wire _T_1620 = _T_1587 | _T_1619; // @[el2_dec_dec_ctl.scala 158:78] + wire _T_1638 = _T_236 & io_ins[6]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1639 = _T_1638 & io_ins[5]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1640 = _T_1639 & _T_98; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1641 = _T_1640 & _T_100; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1642 = _T_1641 & io_ins[1]; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1643 = _T_1642 & _T_1281; // @[el2_dec_dec_ctl.scala 160:54] + wire _T_1644 = _T_1620 | _T_1643; // @[el2_dec_dec_ctl.scala 159:70] + wire _T_1657 = io_ins[14] & io_ins[6]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1658 = _T_1657 & io_ins[5]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1659 = _T_1658 & _T_98; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1660 = _T_1659 & _T_100; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1661 = _T_1660 & _T_18; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1662 = _T_1661 & io_ins[1]; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1663 = _T_1662 & _T_1281; // @[el2_dec_dec_ctl.scala 161:48] + wire _T_1664 = _T_1644 | _T_1663; // @[el2_dec_dec_ctl.scala 160:58] + wire _T_1677 = _T_144 & _T_104; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1678 = _T_1677 & _T_9; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1679 = _T_1678 & io_ins[4]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1680 = _T_1679 & _T_100; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1681 = _T_1680 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1682 = _T_1681 & _T_1281; // @[el2_dec_dec_ctl.scala 162:47] + wire _T_1683 = _T_1664 | _T_1682; // @[el2_dec_dec_ctl.scala 161:52] + wire _T_1699 = _T_19 & io_ins[5]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1700 = _T_1699 & _T_98; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1701 = _T_1700 & _T_100; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1702 = _T_1701 & _T_18; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1703 = _T_1702 & io_ins[1]; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1704 = _T_1703 & _T_1281; // @[el2_dec_dec_ctl.scala 162:99] + wire _T_1705 = _T_1683 | _T_1704; // @[el2_dec_dec_ctl.scala 162:51] + wire _T_1717 = io_ins[12] & io_ins[6]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1718 = _T_1717 & io_ins[5]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1719 = _T_1718 & io_ins[4]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1720 = _T_1719 & _T_100; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1721 = _T_1720 & _T_18; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1722 = _T_1721 & io_ins[1]; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1723 = _T_1722 & _T_1281; // @[el2_dec_dec_ctl.scala 163:47] + wire _T_1724 = _T_1705 | _T_1723; // @[el2_dec_dec_ctl.scala 162:103] + wire _T_1796 = _T_1456 & _T_857; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1797 = _T_1796 & _T_1251; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1798 = _T_1797 & _T_45; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1799 = _T_1798 & _T_1255; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1800 = _T_1799 & _T_1257; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1801 = _T_1800 & _T_1259; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1802 = _T_1801 & _T_14; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1803 = _T_1802 & _T_16; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1804 = _T_1803 & _T_144; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1805 = _T_1804 & _T_1263; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1806 = _T_1805 & _T_1265; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1807 = _T_1806 & _T_1267; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1808 = _T_1807 & _T_1269; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1809 = _T_1808 & _T_1271; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1810 = _T_1809 & _T_104; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1811 = _T_1810 & _T_9; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1812 = _T_1811 & _T_98; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1813 = _T_1812 & io_ins[3]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1814 = _T_1813 & io_ins[2]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1815 = _T_1814 & io_ins[1]; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1816 = _T_1815 & _T_1281; // @[el2_dec_dec_ctl.scala 164:142] + wire _T_1817 = _T_1724 | _T_1816; // @[el2_dec_dec_ctl.scala 163:51] + wire _T_1866 = _T_1449 & _T_1251; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1867 = _T_1866 & _T_45; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1868 = _T_1867 & _T_1255; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1869 = _T_1868 & _T_1257; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1870 = _T_1869 & _T_1259; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1871 = _T_1870 & _T_14; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1872 = _T_1871 & _T_16; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1873 = _T_1872 & _T_144; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1874 = _T_1873 & _T_1263; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1875 = _T_1874 & _T_1265; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1876 = _T_1875 & _T_1267; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1877 = _T_1876 & _T_1269; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1878 = _T_1877 & _T_1271; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1879 = _T_1878 & _T_104; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1880 = _T_1879 & _T_9; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1881 = _T_1880 & _T_98; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1882 = _T_1881 & io_ins[3]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1883 = _T_1882 & io_ins[2]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1884 = _T_1883 & io_ins[1]; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1885 = _T_1884 & _T_1281; // @[el2_dec_dec_ctl.scala 165:110] + wire _T_1886 = _T_1817 | _T_1885; // @[el2_dec_dec_ctl.scala 164:146] + wire _T_1902 = _T_16 & _T_104; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1903 = _T_1902 & _T_9; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1904 = _T_1903 & _T_98; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1905 = _T_1904 & _T_100; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1906 = _T_1905 & _T_18; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1907 = _T_1906 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1908 = _T_1907 & _T_1281; // @[el2_dec_dec_ctl.scala 166:51] + wire _T_1909 = _T_1886 | _T_1908; // @[el2_dec_dec_ctl.scala 165:114] + wire _T_1919 = io_ins[6] & io_ins[5]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1920 = _T_1919 & _T_98; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1921 = _T_1920 & io_ins[3]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1922 = _T_1921 & io_ins[2]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1923 = _T_1922 & io_ins[1]; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1924 = _T_1923 & _T_1281; // @[el2_dec_dec_ctl.scala 166:95] + wire _T_1925 = _T_1909 | _T_1924; // @[el2_dec_dec_ctl.scala 166:55] + wire _T_1938 = _T_656 & _T_9; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1939 = _T_1938 & io_ins[4]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1940 = _T_1939 & _T_100; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1941 = _T_1940 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1942 = _T_1941 & _T_1281; // @[el2_dec_dec_ctl.scala 167:46] + wire _T_1943 = _T_1925 | _T_1942; // @[el2_dec_dec_ctl.scala 166:99] + wire _T_1960 = _T_585 & _T_104; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1961 = _T_1960 & _T_98; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1962 = _T_1961 & _T_100; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1963 = _T_1962 & _T_18; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] + wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] + wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] + assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] + assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] + assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] + assign io_out_imm12 = _T_150 | _T_160; // @[el2_dec_dec_ctl.scala 80:16] + assign io_out_rd = _T_170 | io_ins[4]; // @[el2_dec_dec_ctl.scala 82:13] + assign io_out_shimm5 = _T_183 & _T_18; // @[el2_dec_dec_ctl.scala 83:17] + assign io_out_imm20 = _T_187 | _T_190; // @[el2_dec_dec_ctl.scala 84:16] + assign io_out_pc = _T_198 | _T_187; // @[el2_dec_dec_ctl.scala 85:13] + assign io_out_load = _T_209 & _T_18; // @[el2_dec_dec_ctl.scala 86:15] + assign io_out_store = _T_121 & _T_98; // @[el2_dec_dec_ctl.scala 87:16] + assign io_out_lsu = _T_224 & _T_18; // @[el2_dec_dec_ctl.scala 88:14] + assign io_out_add = _T_246 | _T_268; // @[el2_dec_dec_ctl.scala 89:14] + assign io_out_sub = _T_312 | _T_319; // @[el2_dec_dec_ctl.scala 91:14] + assign io_out_land = _T_331 | _T_345; // @[el2_dec_dec_ctl.scala 93:15] + assign io_out_lor = _T_382 | _T_394; // @[el2_dec_dec_ctl.scala 94:14] + assign io_out_lxor = _T_410 | _T_425; // @[el2_dec_dec_ctl.scala 97:15] + assign io_out_sll = _T_443 & _T_18; // @[el2_dec_dec_ctl.scala 98:14] + assign io_out_sra = _T_457 & _T_18; // @[el2_dec_dec_ctl.scala 99:14] + assign io_out_srl = _T_477 & _T_18; // @[el2_dec_dec_ctl.scala 100:14] + assign io_out_slt = _T_495 | _T_311; // @[el2_dec_dec_ctl.scala 101:14] + assign io_out_unsign = _T_554 | _T_567; // @[el2_dec_dec_ctl.scala 102:17] + assign io_out_condbr = _T_318 & _T_18; // @[el2_dec_dec_ctl.scala 105:17] + assign io_out_beq = _T_587 & _T_18; // @[el2_dec_dec_ctl.scala 106:14] + assign io_out_bne = _T_599 & _T_18; // @[el2_dec_dec_ctl.scala 107:14] + assign io_out_bge = _T_610 & _T_18; // @[el2_dec_dec_ctl.scala 108:14] + assign io_out_blt = _T_622 & _T_18; // @[el2_dec_dec_ctl.scala 109:14] + assign io_out_jal = io_ins[6] & io_ins[2]; // @[el2_dec_dec_ctl.scala 110:14] + assign io_out_by = _T_639 & _T_18; // @[el2_dec_dec_ctl.scala 111:13] + assign io_out_half = _T_649 & _T_18; // @[el2_dec_dec_ctl.scala 112:15] + assign io_out_word = _T_656 & _T_98; // @[el2_dec_dec_ctl.scala 113:15] + assign io_out_csr_read = _T_686 | _T_691; // @[el2_dec_dec_ctl.scala 114:19] + assign io_out_csr_clr = _T_730 | _T_738; // @[el2_dec_dec_ctl.scala 117:18] + assign io_out_csr_set = _T_830 | _T_738; // @[el2_dec_dec_ctl.scala 124:18] + assign io_out_csr_write = _T_746 & io_ins[4]; // @[el2_dec_dec_ctl.scala 120:20] + assign io_out_csr_imm = _T_787 | _T_794; // @[el2_dec_dec_ctl.scala 121:18] + assign io_out_presync = _T_1116 | _T_1123; // @[el2_dec_dec_ctl.scala 141:18] + assign io_out_postsync = _T_1220 | _T_1123; // @[el2_dec_dec_ctl.scala 147:19] + assign io_out_ebreak = _T_852 & io_ins[4]; // @[el2_dec_dec_ctl.scala 127:17] + assign io_out_ecall = _T_867 & io_ins[4]; // @[el2_dec_dec_ctl.scala 128:16] + assign io_out_mret = _T_878 & io_ins[4]; // @[el2_dec_dec_ctl.scala 129:15] + assign io_out_mul = _T_892 & _T_18; // @[el2_dec_dec_ctl.scala 130:14] + assign io_out_rs1_sign = _T_912 | _T_929; // @[el2_dec_dec_ctl.scala 131:19] + assign io_out_rs2_sign = _T_928 & _T_18; // @[el2_dec_dec_ctl.scala 133:19] + assign io_out_low = _T_963 & _T_18; // @[el2_dec_dec_ctl.scala 134:14] + assign io_out_div = _T_974 & _T_18; // @[el2_dec_dec_ctl.scala 135:14] + assign io_out_rem = _T_987 & _T_18; // @[el2_dec_dec_ctl.scala 136:14] + assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] + assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] + assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] + assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] +endmodule +module el2_dec_decode_ctl( + input clock, + input reset, + input io_dec_tlu_flush_extint, + input io_dec_tlu_force_halt, + output io_dec_extint_stall, + input [15:0] io_ifu_i0_cinst, + output [31:0] io_dec_i0_inst_wb1, + output [30:0] io_dec_i0_pc_wb1, + input io_lsu_nonblock_load_valid_m, + input [1:0] io_lsu_nonblock_load_tag_m, + input io_lsu_nonblock_load_inv_r, + input [1:0] io_lsu_nonblock_load_inv_tag_r, + input io_lsu_nonblock_load_data_valid, + input io_lsu_nonblock_load_data_error, + input [1:0] io_lsu_nonblock_load_data_tag, + input [31:0] io_lsu_nonblock_load_data, + input [3:0] io_dec_i0_trigger_match_d, + input io_dec_tlu_wr_pause_r, + input io_dec_tlu_pipelining_disable, + input [3:0] io_lsu_trigger_match_m, + input io_lsu_pmu_misaligned_m, + input io_dec_tlu_debug_stall, + input io_dec_tlu_flush_leak_one_r, + input io_dec_debug_fence_d, + input [1:0] io_dbg_cmd_wrdata, + input io_dec_i0_icaf_d, + input io_dec_i0_icaf_f1_d, + input [1:0] io_dec_i0_icaf_type_d, + input io_dec_i0_dbecc_d, + input io_dec_i0_brp_valid, + input [11:0] io_dec_i0_brp_toffset, + input [1:0] io_dec_i0_brp_hist, + input io_dec_i0_brp_br_error, + input io_dec_i0_brp_br_start_error, + input io_dec_i0_brp_bank, + input [30:0] io_dec_i0_brp_prett, + input io_dec_i0_brp_way, + input io_dec_i0_brp_ret, + input [7:0] io_dec_i0_bp_index, + input [7:0] io_dec_i0_bp_fghr, + input [4:0] io_dec_i0_bp_btag, + input [30:0] io_dec_i0_pc_d, + input io_lsu_idle_any, + input io_lsu_load_stall_any, + input io_lsu_store_stall_any, + input io_dma_dccm_stall_any, + input io_exu_div_wren, + input io_dec_tlu_i0_kill_writeb_wb, + input io_dec_tlu_flush_lower_wb, + input io_dec_tlu_i0_kill_writeb_r, + input io_dec_tlu_flush_lower_r, + input io_dec_tlu_flush_pause_r, + input io_dec_tlu_presync_d, + input io_dec_tlu_postsync_d, + input io_dec_i0_pc4_d, + input [31:0] io_dec_csr_rddata_d, + input io_dec_csr_legal_d, + input [31:0] io_exu_csr_rs1_x, + input [31:0] io_lsu_result_m, + input [31:0] io_lsu_result_corr_r, + input io_exu_flush_final, + input [30:0] io_exu_i0_pc_x, + input [31:0] io_dec_i0_instr_d, + input io_dec_ib0_valid_d, + input [31:0] io_exu_i0_result_x, + input io_free_clk, + input io_active_clk, + input io_clk_override, + output io_dec_i0_rs1_en_d, + output io_dec_i0_rs2_en_d, + output [4:0] io_dec_i0_rs1_d, + output [4:0] io_dec_i0_rs2_d, + output [31:0] io_dec_i0_immed_d, + output [11:0] io_dec_i0_br_immed_d, + output io_i0_ap_land, + output io_i0_ap_lor, + output io_i0_ap_lxor, + output io_i0_ap_sll, + output io_i0_ap_srl, + output io_i0_ap_sra, + output io_i0_ap_beq, + output io_i0_ap_bne, + output io_i0_ap_blt, + output io_i0_ap_bge, + output io_i0_ap_add, + output io_i0_ap_sub, + output io_i0_ap_slt, + output io_i0_ap_unsign, + output io_i0_ap_jal, + output io_i0_ap_predict_t, + output io_i0_ap_predict_nt, + output io_i0_ap_csr_write, + output io_i0_ap_csr_imm, + output io_dec_i0_decode_d, + output io_dec_i0_alu_decode_d, + output [31:0] io_dec_i0_rs1_bypass_data_d, + output [31:0] io_dec_i0_rs2_bypass_data_d, + output [4:0] io_dec_i0_waddr_r, + output io_dec_i0_wen_r, + output [31:0] io_dec_i0_wdata_r, + output io_dec_i0_select_pc_d, + output [1:0] io_dec_i0_rs1_bypass_en_d, + output [1:0] io_dec_i0_rs2_bypass_en_d, + output io_lsu_p_fast_int, + output io_lsu_p_by, + output io_lsu_p_half, + output io_lsu_p_word, + output io_lsu_p_dword, + output io_lsu_p_load, + output io_lsu_p_store, + output io_lsu_p_unsign, + output io_lsu_p_dma, + output io_lsu_p_store_data_bypass_d, + output io_lsu_p_load_ldst_bypass_d, + output io_lsu_p_store_data_bypass_m, + output io_lsu_p_valid, + output io_mul_p_valid, + output io_mul_p_rs1_sign, + output io_mul_p_rs2_sign, + output io_mul_p_low, + output io_mul_p_bext, + output io_mul_p_bdep, + output io_mul_p_clmul, + output io_mul_p_clmulh, + output io_mul_p_clmulr, + output io_mul_p_grev, + output io_mul_p_shfl, + output io_mul_p_unshfl, + output io_mul_p_crc32_b, + output io_mul_p_crc32_h, + output io_mul_p_crc32_w, + output io_mul_p_crc32c_b, + output io_mul_p_crc32c_h, + output io_mul_p_crc32c_w, + output io_mul_p_bfp, + output io_div_p_valid, + output io_div_p_unsign, + output io_div_p_rem, + output [4:0] io_div_waddr_wb, + output io_dec_div_cancel, + output io_dec_lsu_valid_raw_d, + output [11:0] io_dec_lsu_offset_d, + output io_dec_csr_ren_d, + output io_dec_csr_wen_unq_d, + output io_dec_csr_any_unq_d, + output [11:0] io_dec_csr_rdaddr_d, + output io_dec_csr_wen_r, + output [11:0] io_dec_csr_wraddr_r, + output [31:0] io_dec_csr_wrdata_r, + output io_dec_csr_stall_int_ff, + output io_dec_tlu_i0_valid_r, + output io_dec_tlu_packet_r_legal, + output io_dec_tlu_packet_r_icaf, + output io_dec_tlu_packet_r_icaf_f1, + output [1:0] io_dec_tlu_packet_r_icaf_type, + output io_dec_tlu_packet_r_fence_i, + output [3:0] io_dec_tlu_packet_r_i0trigger, + output [3:0] io_dec_tlu_packet_r_pmu_i0_itype, + output io_dec_tlu_packet_r_pmu_i0_br_unpred, + output io_dec_tlu_packet_r_pmu_divide, + output io_dec_tlu_packet_r_pmu_lsu_misaligned, + output [30:0] io_dec_tlu_i0_pc_r, + output [31:0] io_dec_illegal_inst, + output [30:0] io_pred_correct_npc_x, + output io_dec_i0_predict_p_d_misp, + output io_dec_i0_predict_p_d_ataken, + output io_dec_i0_predict_p_d_boffset, + output io_dec_i0_predict_p_d_pc4, + output [1:0] io_dec_i0_predict_p_d_hist, + output [11:0] io_dec_i0_predict_p_d_toffset, + output io_dec_i0_predict_p_d_valid, + output io_dec_i0_predict_p_d_br_error, + output io_dec_i0_predict_p_d_br_start_error, + output [30:0] io_dec_i0_predict_p_d_prett, + output io_dec_i0_predict_p_d_pcall, + output io_dec_i0_predict_p_d_pret, + output io_dec_i0_predict_p_d_pja, + output io_dec_i0_predict_p_d_way, + output [7:0] io_i0_predict_fghr_d, + output [7:0] io_i0_predict_index_d, + output [4:0] io_i0_predict_btag_d, + output [1:0] io_dec_data_en, + output [1:0] io_dec_ctl_en, + output io_dec_pmu_instr_decoded, + output io_dec_pmu_decode_stall, + output io_dec_pmu_presync_stall, + output io_dec_pmu_postsync_stall, + output io_dec_nonblock_load_wen, + output [4:0] io_dec_nonblock_load_waddr, + output io_dec_pause_state, + output io_dec_pause_state_cg, + output io_dec_div_active, + input io_scan_mode +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; +`endif // RANDOMIZE_REG_INIT + wire data_gated_cgc_io_l1clk; // @[el2_dec_decode_ctl.scala 222:29] + wire data_gated_cgc_io_clk; // @[el2_dec_decode_ctl.scala 222:29] + wire data_gated_cgc_io_en; // @[el2_dec_decode_ctl.scala 222:29] + wire data_gated_cgc_io_scan_mode; // @[el2_dec_decode_ctl.scala 222:29] + wire [31:0] i0_dec_io_ins; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 396:22] + wire i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 396:22] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_18_io_scan_mode; // @[el2_lib.scala 508:23] + reg tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 503:29] + wire _T_1 = io_dec_tlu_wr_pause_r ^ tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 211:51] + reg tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 504:29] + wire _T_2 = tlu_wr_pause_r1 ^ tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 212:32] + wire _T_3 = _T_1 | _T_2; // @[el2_dec_decode_ctl.scala 211:73] + wire _T_4 = io_dec_tlu_flush_extint ^ io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 213:32] + wire _T_5 = _T_3 | _T_4; // @[el2_dec_decode_ctl.scala 212:56] + reg leak1_i1_stall; // @[el2_dec_decode_ctl.scala 404:56] + wire _T_279 = ~io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 403:73] + wire _T_280 = leak1_i1_stall & _T_279; // @[el2_dec_decode_ctl.scala 403:71] + wire leak1_i1_stall_in = io_dec_tlu_flush_leak_one_r | _T_280; // @[el2_dec_decode_ctl.scala 403:53] + wire _T_6 = leak1_i1_stall_in ^ leak1_i1_stall; // @[el2_dec_decode_ctl.scala 214:32] + wire _T_7 = _T_5 | _T_6; // @[el2_dec_decode_ctl.scala 213:56] + wire _T_283 = io_dec_i0_decode_d & leak1_i1_stall; // @[el2_dec_decode_ctl.scala 406:45] + reg leak1_i0_stall; // @[el2_dec_decode_ctl.scala 407:56] + wire _T_285 = leak1_i0_stall & _T_279; // @[el2_dec_decode_ctl.scala 406:81] + wire leak1_i0_stall_in = _T_283 | _T_285; // @[el2_dec_decode_ctl.scala 406:63] + wire _T_8 = leak1_i0_stall_in ^ leak1_i0_stall; // @[el2_dec_decode_ctl.scala 215:32] + wire _T_9 = _T_7 | _T_8; // @[el2_dec_decode_ctl.scala 214:56] + reg pause_stall; // @[el2_dec_decode_ctl.scala 501:50] + wire _T_412 = io_dec_tlu_wr_pause_r | pause_stall; // @[el2_dec_decode_ctl.scala 500:44] + wire _T_408 = ~io_dec_tlu_flush_pause_r; // @[el2_dec_decode_ctl.scala 499:49] + wire _T_409 = io_dec_tlu_flush_lower_r & _T_408; // @[el2_dec_decode_ctl.scala 499:47] + reg [31:0] write_csr_data; // @[el2_lib.scala 514:16] + wire _T_410 = write_csr_data == 32'h0; // @[el2_dec_decode_ctl.scala 499:109] + wire _T_411 = pause_stall & _T_410; // @[el2_dec_decode_ctl.scala 499:91] + wire clear_pause = _T_409 | _T_411; // @[el2_dec_decode_ctl.scala 499:76] + wire _T_413 = ~clear_pause; // @[el2_dec_decode_ctl.scala 500:61] + wire pause_state_in = _T_412 & _T_413; // @[el2_dec_decode_ctl.scala 500:59] + wire _T_10 = pause_state_in ^ pause_stall; // @[el2_dec_decode_ctl.scala 216:32] + wire _T_11 = _T_9 | _T_10; // @[el2_dec_decode_ctl.scala 215:56] + wire _T_17 = ~leak1_i1_stall; // @[el2_dec_decode_ctl.scala 230:62] + wire i0_brp_valid = io_dec_i0_brp_valid & _T_17; // @[el2_dec_decode_ctl.scala 230:60] + wire i0_dp_raw_condbr = i0_dec_io_out_condbr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_jal = i0_dec_io_out_jal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire [20:0] i0_pcall_imm = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire _T_298 = i0_pcall_imm[20:13] == 8'hff; // @[el2_dec_decode_ctl.scala 412:79] + wire _T_300 = i0_pcall_imm[20:13] == 8'h0; // @[el2_dec_decode_ctl.scala 412:112] + wire i0_pcall_12b_offset = i0_pcall_imm[12] ? _T_298 : _T_300; // @[el2_dec_decode_ctl.scala 412:33] + wire i0_dp_raw_imm20 = i0_dec_io_out_imm20; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire _T_301 = i0_pcall_12b_offset & i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 413:47] + wire [4:0] i0r_rd = io_dec_i0_instr_d[11:7]; // @[el2_dec_decode_ctl.scala 626:16] + wire _T_302 = i0r_rd == 5'h1; // @[el2_dec_decode_ctl.scala 413:76] + wire _T_303 = i0r_rd == 5'h5; // @[el2_dec_decode_ctl.scala 413:98] + wire _T_304 = _T_302 | _T_303; // @[el2_dec_decode_ctl.scala 413:89] + wire i0_pcall_case = _T_301 & _T_304; // @[el2_dec_decode_ctl.scala 413:65] + wire i0_pcall_raw = i0_dp_raw_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 415:38] + wire _T_19 = i0_dp_raw_condbr | i0_pcall_raw; // @[el2_dec_decode_ctl.scala 241:75] + wire _T_309 = ~_T_304; // @[el2_dec_decode_ctl.scala 414:67] + wire i0_pja_case = _T_301 & _T_309; // @[el2_dec_decode_ctl.scala 414:65] + wire i0_pja_raw = i0_dp_raw_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 417:38] + wire _T_20 = _T_19 | i0_pja_raw; // @[el2_dec_decode_ctl.scala 241:90] + wire i0_dp_raw_imm12 = i0_dec_io_out_imm12; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire _T_325 = i0_dp_raw_jal & i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 421:37] + wire _T_326 = i0r_rd == 5'h0; // @[el2_dec_decode_ctl.scala 421:65] + wire _T_327 = _T_325 & _T_326; // @[el2_dec_decode_ctl.scala 421:55] + wire [4:0] i0r_rs1 = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 624:16] + wire _T_328 = i0r_rs1 == 5'h1; // @[el2_dec_decode_ctl.scala 421:89] + wire _T_329 = i0r_rs1 == 5'h5; // @[el2_dec_decode_ctl.scala 421:111] + wire _T_330 = _T_328 | _T_329; // @[el2_dec_decode_ctl.scala 421:101] + wire i0_pret_case = _T_327 & _T_330; // @[el2_dec_decode_ctl.scala 421:79] + wire i0_pret_raw = i0_dp_raw_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 422:32] + wire _T_21 = _T_20 | i0_pret_raw; // @[el2_dec_decode_ctl.scala 241:103] + wire _T_22 = ~_T_21; // @[el2_dec_decode_ctl.scala 241:56] + wire i0_notbr_error = i0_brp_valid & _T_22; // @[el2_dec_decode_ctl.scala 241:54] + wire _T_30 = io_dec_i0_brp_br_error | i0_notbr_error; // @[el2_dec_decode_ctl.scala 246:57] + wire _T_24 = i0_brp_valid & io_dec_i0_brp_hist[1]; // @[el2_dec_decode_ctl.scala 244:47] + wire _T_314 = i0_pcall_raw | i0_pja_raw; // @[el2_dec_decode_ctl.scala 419:41] + wire [11:0] _T_323 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[7],io_dec_i0_instr_d[30:25],io_dec_i0_instr_d[11:8]}; // @[Cat.scala 29:58] + wire [11:0] i0_br_offset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 419:26] + wire _T_25 = io_dec_i0_brp_toffset != i0_br_offset; // @[el2_dec_decode_ctl.scala 244:96] + wire _T_26 = _T_24 & _T_25; // @[el2_dec_decode_ctl.scala 244:71] + wire _T_27 = ~i0_pret_raw; // @[el2_dec_decode_ctl.scala 244:116] + wire i0_br_toffset_error = _T_26 & _T_27; // @[el2_dec_decode_ctl.scala 244:114] + wire _T_31 = _T_30 | i0_br_toffset_error; // @[el2_dec_decode_ctl.scala 246:74] + wire _T_28 = i0_brp_valid & io_dec_i0_brp_ret; // @[el2_dec_decode_ctl.scala 245:47] + wire i0_ret_error = _T_28 & _T_27; // @[el2_dec_decode_ctl.scala 245:67] + wire i0_br_error = _T_31 | i0_ret_error; // @[el2_dec_decode_ctl.scala 246:96] + wire _T_38 = i0_br_error | io_dec_i0_brp_br_start_error; // @[el2_dec_decode_ctl.scala 251:47] + wire i0_br_error_all = _T_38 & _T_17; // @[el2_dec_decode_ctl.scala 251:79] + wire i0_icaf_d = io_dec_i0_icaf_d | io_dec_i0_dbecc_d; // @[el2_dec_decode_ctl.scala 260:36] + wire _T_40 = i0_br_error_all | i0_icaf_d; // @[el2_dec_decode_ctl.scala 264:25] + wire i0_dp_raw_postsync = i0_dec_io_out_postsync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_postsync = _T_40 | i0_dp_raw_postsync; // @[el2_dec_decode_ctl.scala 264:50] + wire _T_439 = i0_dp_postsync | io_dec_tlu_postsync_d; // @[el2_dec_decode_ctl.scala 530:36] + wire debug_fence_i = io_dec_debug_fence_d & io_dbg_cmd_wrdata[0]; // @[el2_dec_decode_ctl.scala 522:48] + wire _T_440 = _T_439 | debug_fence_i; // @[el2_dec_decode_ctl.scala 530:60] + wire i0_dp_raw_csr_write = i0_dec_io_out_csr_write; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_csr_write = _T_40 ? 1'h0 : i0_dp_raw_csr_write; // @[el2_dec_decode_ctl.scala 264:50] + wire _T_343 = ~io_dec_debug_fence_d; // @[el2_dec_decode_ctl.scala 461:42] + wire i0_csr_write = i0_dp_csr_write & _T_343; // @[el2_dec_decode_ctl.scala 461:40] + wire i0_dp_raw_csr_read = i0_dec_io_out_csr_read; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_csr_read = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 264:50] + wire _T_347 = ~i0_dp_csr_read; // @[el2_dec_decode_ctl.scala 466:41] + wire i0_csr_write_only_d = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 466:39] + wire _T_442 = io_dec_i0_instr_d[31:20] == 12'h7c2; // @[el2_dec_decode_ctl.scala 530:112] + wire _T_443 = i0_csr_write_only_d & _T_442; // @[el2_dec_decode_ctl.scala 530:99] + wire i0_postsync = _T_440 | _T_443; // @[el2_dec_decode_ctl.scala 530:76] + wire i0_dp_raw_legal = i0_dec_io_out_legal; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_legal = _T_40 | i0_dp_raw_legal; // @[el2_dec_decode_ctl.scala 264:50] + wire any_csr_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 532:34] + wire _T_444 = ~any_csr_d; // @[el2_dec_decode_ctl.scala 534:40] + wire _T_445 = _T_444 | io_dec_csr_legal_d; // @[el2_dec_decode_ctl.scala 534:51] + wire i0_legal = i0_dp_legal & _T_445; // @[el2_dec_decode_ctl.scala 534:37] + wire _T_504 = ~i0_legal; // @[el2_dec_decode_ctl.scala 574:56] + wire _T_505 = i0_postsync | _T_504; // @[el2_dec_decode_ctl.scala 574:54] + wire _T_506 = io_dec_i0_decode_d & _T_505; // @[el2_dec_decode_ctl.scala 574:39] + reg postsync_stall; // @[el2_dec_decode_ctl.scala 572:53] + reg x_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_507 = postsync_stall & x_d_i0valid; // @[el2_dec_decode_ctl.scala 574:88] + wire ps_stall_in = _T_506 | _T_507; // @[el2_dec_decode_ctl.scala 574:69] + wire _T_12 = ps_stall_in ^ postsync_stall; // @[el2_dec_decode_ctl.scala 217:32] + wire _T_13 = _T_11 | _T_12; // @[el2_dec_decode_ctl.scala 216:56] + reg flush_final_r; // @[el2_dec_decode_ctl.scala 620:52] + wire _T_14 = io_exu_flush_final ^ flush_final_r; // @[el2_dec_decode_ctl.scala 218:32] + wire _T_15 = _T_13 | _T_14; // @[el2_dec_decode_ctl.scala 217:56] + wire shift_illegal = io_dec_i0_decode_d & _T_504; // @[el2_dec_decode_ctl.scala 538:47] + reg illegal_lockout; // @[el2_dec_decode_ctl.scala 542:54] + wire _T_466 = shift_illegal | illegal_lockout; // @[el2_dec_decode_ctl.scala 541:40] + wire _T_467 = ~flush_final_r; // @[el2_dec_decode_ctl.scala 541:61] + wire illegal_lockout_in = _T_466 & _T_467; // @[el2_dec_decode_ctl.scala 541:59] + wire _T_16 = illegal_lockout_in ^ illegal_lockout; // @[el2_dec_decode_ctl.scala 219:32] + wire i0_legal_decode_d = io_dec_i0_decode_d & i0_legal; // @[el2_dec_decode_ctl.scala 648:46] + wire _T_32 = i0_br_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 247:67] + wire _T_35 = io_dec_i0_brp_br_start_error & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 248:84] + wire i0_dp_raw_pm_alu = i0_dec_io_out_pm_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_pm_alu = _T_40 ? 1'h0 : i0_dp_raw_pm_alu; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_fence_i = i0_dec_io_out_fence_i; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_fence_i = _T_40 ? 1'h0 : i0_dp_raw_fence_i; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_fence = i0_dec_io_out_fence; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_fence = _T_40 ? 1'h0 : i0_dp_raw_fence; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_rem = i0_dec_io_out_rem; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_div = i0_dec_io_out_div; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_div = _T_40 ? 1'h0 : i0_dp_raw_div; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_low = i0_dec_io_out_low; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_rs2_sign = i0_dec_io_out_rs2_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_rs1_sign = i0_dec_io_out_rs1_sign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_mul = i0_dec_io_out_mul; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_mul = _T_40 ? 1'h0 : i0_dp_raw_mul; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_mret = i0_dec_io_out_mret; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_mret = _T_40 ? 1'h0 : i0_dp_raw_mret; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_ecall = i0_dec_io_out_ecall; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_ecall = _T_40 ? 1'h0 : i0_dp_raw_ecall; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_ebreak = i0_dec_io_out_ebreak; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_ebreak = _T_40 ? 1'h0 : i0_dp_raw_ebreak; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_presync = i0_dec_io_out_presync; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_presync = _T_40 ? 1'h0 : i0_dp_raw_presync; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_csr_imm = i0_dec_io_out_csr_imm; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_csr_set = i0_dec_io_out_csr_set; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_csr_set = _T_40 ? 1'h0 : i0_dp_raw_csr_set; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_csr_clr = i0_dec_io_out_csr_clr; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_csr_clr = _T_40 ? 1'h0 : i0_dp_raw_csr_clr; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_word = i0_dec_io_out_word; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_word = _T_40 ? 1'h0 : i0_dp_raw_word; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_half = i0_dec_io_out_half; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_half = _T_40 ? 1'h0 : i0_dp_raw_half; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_by = i0_dec_io_out_by; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_by = _T_40 ? 1'h0 : i0_dp_raw_by; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_jal = _T_40 ? 1'h0 : i0_dp_raw_jal; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_blt = i0_dec_io_out_blt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_bge = i0_dec_io_out_bge; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_bne = i0_dec_io_out_bne; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_beq = i0_dec_io_out_beq; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_condbr = _T_40 ? 1'h0 : i0_dp_raw_condbr; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_unsign = i0_dec_io_out_unsign; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_slt = i0_dec_io_out_slt; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_srl = i0_dec_io_out_srl; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_sra = i0_dec_io_out_sra; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_sll = i0_dec_io_out_sll; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_lxor = i0_dec_io_out_lxor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_lor = i0_dec_io_out_lor; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_land = i0_dec_io_out_land; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_sub = i0_dec_io_out_sub; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_add = i0_dec_io_out_add; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_raw_lsu = i0_dec_io_out_lsu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_lsu = _T_40 ? 1'h0 : i0_dp_raw_lsu; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_store = i0_dec_io_out_store; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_store = _T_40 ? 1'h0 : i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_load = i0_dec_io_out_load; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_load = _T_40 ? 1'h0 : i0_dp_raw_load; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_pc = i0_dec_io_out_pc; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_imm20 = _T_40 ? 1'h0 : i0_dp_raw_imm20; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_shimm5 = i0_dec_io_out_shimm5; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_shimm5 = _T_40 ? 1'h0 : i0_dp_raw_shimm5; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_rd = i0_dec_io_out_rd; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_rd = _T_40 ? 1'h0 : i0_dp_raw_rd; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_imm12 = _T_40 ? 1'h0 : i0_dp_raw_imm12; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_rs2 = i0_dec_io_out_rs2; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_rs2 = _T_40 | i0_dp_raw_rs2; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_rs1 = i0_dec_io_out_rs1; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_rs1 = _T_40 | i0_dp_raw_rs1; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_dp_raw_alu = i0_dec_io_out_alu; // @[el2_dec_decode_ctl.scala 156:22 el2_dec_decode_ctl.scala 398:12] + wire i0_dp_alu = _T_40 | i0_dp_raw_alu; // @[el2_dec_decode_ctl.scala 264:50] + wire i0_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 416:38] + wire _T_43 = i0_dp_condbr | i0_pcall; // @[el2_dec_decode_ctl.scala 278:38] + wire i0_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 418:38] + wire _T_44 = _T_43 | i0_pja; // @[el2_dec_decode_ctl.scala 278:49] + wire i0_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 423:32] + wire i0_predict_br = _T_44 | i0_pret; // @[el2_dec_decode_ctl.scala 278:58] + wire _T_46 = io_dec_i0_brp_hist[1] & i0_brp_valid; // @[el2_dec_decode_ctl.scala 280:50] + wire _T_47 = ~_T_46; // @[el2_dec_decode_ctl.scala 280:26] + wire i0_ap_pc2 = ~io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 282:20] + wire cam_data_reset = io_lsu_nonblock_load_data_valid | io_lsu_nonblock_load_data_error; // @[el2_dec_decode_ctl.scala 315:63] + reg [2:0] cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 351:47] + wire [2:0] _GEN_123 = {{1'd0}, io_lsu_nonblock_load_data_tag}; // @[el2_dec_decode_ctl.scala 326:67] + wire _T_93 = _GEN_123 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 326:67] + wire _T_94 = cam_data_reset & _T_93; // @[el2_dec_decode_ctl.scala 326:45] + reg cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 351:47] + wire cam_data_reset_val_0 = _T_94 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 326:83] + wire cam_0_valid = cam_data_reset_val_0 ? 1'h0 : cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 330:39] + wire _T_50 = ~cam_0_valid; // @[el2_dec_decode_ctl.scala 307:78] + reg [2:0] cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_119 = _GEN_123 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 326:67] + wire _T_120 = cam_data_reset & _T_119; // @[el2_dec_decode_ctl.scala 326:45] + reg cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 351:47] + wire cam_data_reset_val_1 = _T_120 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 326:83] + wire cam_1_valid = cam_data_reset_val_1 ? 1'h0 : cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 330:39] + wire _T_53 = ~cam_1_valid; // @[el2_dec_decode_ctl.scala 307:78] + wire _T_56 = cam_0_valid & _T_53; // @[el2_dec_decode_ctl.scala 307:126] + wire [1:0] _T_58 = {io_lsu_nonblock_load_valid_m, 1'h0}; // @[el2_dec_decode_ctl.scala 307:158] + reg [2:0] cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_145 = _GEN_123 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 326:67] + wire _T_146 = cam_data_reset & _T_145; // @[el2_dec_decode_ctl.scala 326:45] + reg cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 351:47] + wire cam_data_reset_val_2 = _T_146 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 326:83] + wire cam_2_valid = cam_data_reset_val_2 ? 1'h0 : cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 330:39] + wire _T_59 = ~cam_2_valid; // @[el2_dec_decode_ctl.scala 307:78] + wire _T_62 = cam_0_valid & cam_1_valid; // @[el2_dec_decode_ctl.scala 307:126] + wire _T_65 = _T_62 & _T_59; // @[el2_dec_decode_ctl.scala 307:126] + wire [2:0] _T_67 = {io_lsu_nonblock_load_valid_m, 2'h0}; // @[el2_dec_decode_ctl.scala 307:158] + reg [2:0] cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_171 = _GEN_123 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 326:67] + wire _T_172 = cam_data_reset & _T_171; // @[el2_dec_decode_ctl.scala 326:45] + reg cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 351:47] + wire cam_data_reset_val_3 = _T_172 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 326:83] + wire cam_3_valid = cam_data_reset_val_3 ? 1'h0 : cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 330:39] + wire _T_68 = ~cam_3_valid; // @[el2_dec_decode_ctl.scala 307:78] + wire _T_74 = _T_62 & cam_2_valid; // @[el2_dec_decode_ctl.scala 307:126] + wire _T_77 = _T_74 & _T_68; // @[el2_dec_decode_ctl.scala 307:126] + wire [3:0] _T_79 = {io_lsu_nonblock_load_valid_m, 3'h0}; // @[el2_dec_decode_ctl.scala 307:158] + wire _T_80 = _T_50 & io_lsu_nonblock_load_valid_m; // @[Mux.scala 27:72] + wire [1:0] _T_81 = _T_56 ? _T_58 : 2'h0; // @[Mux.scala 27:72] + wire [2:0] _T_82 = _T_65 ? _T_67 : 3'h0; // @[Mux.scala 27:72] + wire [3:0] _T_83 = _T_77 ? _T_79 : 4'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_127 = {{1'd0}, _T_80}; // @[Mux.scala 27:72] + wire [1:0] _T_84 = _GEN_127 | _T_81; // @[Mux.scala 27:72] + wire [2:0] _GEN_128 = {{1'd0}, _T_84}; // @[Mux.scala 27:72] + wire [2:0] _T_85 = _GEN_128 | _T_82; // @[Mux.scala 27:72] + wire [3:0] _GEN_129 = {{1'd0}, _T_85}; // @[Mux.scala 27:72] + wire [3:0] cam_wen = _GEN_129 | _T_83; // @[Mux.scala 27:72] + reg x_d_i0load; // @[el2_lib.scala 524:16] + reg [4:0] x_d_i0rd; // @[el2_lib.scala 524:16] + wire [4:0] nonblock_load_rd = x_d_i0load ? x_d_i0rd : 5'h0; // @[el2_dec_decode_ctl.scala 318:31] + reg [2:0] _T_701; // @[el2_dec_decode_ctl.scala 656:72] + wire [3:0] i0_pipe_en = {io_dec_i0_decode_d,_T_701}; // @[Cat.scala 29:58] + wire _T_707 = |i0_pipe_en[2:1]; // @[el2_dec_decode_ctl.scala 659:49] + wire i0_r_ctl_en = _T_707 | io_clk_override; // @[el2_dec_decode_ctl.scala 659:53] + reg nonblock_load_valid_m_delay; // @[Reg.scala 27:20] + reg r_d_i0load; // @[el2_lib.scala 524:16] + wire i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d_i0load; // @[el2_dec_decode_ctl.scala 323:56] + wire [2:0] _GEN_130 = {{1'd0}, io_lsu_nonblock_load_inv_tag_r}; // @[el2_dec_decode_ctl.scala 325:66] + wire _T_90 = _GEN_130 == cam_raw_0_tag; // @[el2_dec_decode_ctl.scala 325:66] + wire _T_91 = io_lsu_nonblock_load_inv_r & _T_90; // @[el2_dec_decode_ctl.scala 325:45] + wire cam_inv_reset_val_0 = _T_91 & cam_0_valid; // @[el2_dec_decode_ctl.scala 325:82] + reg r_d_i0v; // @[el2_lib.scala 524:16] + wire _T_743 = ~io_dec_tlu_flush_lower_wb; // @[el2_dec_decode_ctl.scala 691:41] + wire r_d_in_i0v = r_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 691:39] + wire _T_754 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 699:42] + wire i0_wen_r = r_d_in_i0v & _T_754; // @[el2_dec_decode_ctl.scala 699:40] + reg [4:0] r_d_i0rd; // @[el2_lib.scala 524:16] + reg [4:0] cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_102 = r_d_i0rd == cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 338:80] + wire _T_103 = i0_wen_r & _T_102; // @[el2_dec_decode_ctl.scala 338:64] + reg cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_105 = _T_103 & cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 338:95] + wire _T_106 = cam_inv_reset_val_0 | _T_105; // @[el2_dec_decode_ctl.scala 338:44] + wire _GEN_52 = _T_106 ? 1'h0 : cam_0_valid; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_55 = _T_106 ? 1'h0 : cam_raw_0_wb; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_56 = cam_wen[0] | _GEN_52; // @[el2_dec_decode_ctl.scala 333:28] + wire _GEN_57 = cam_wen[0] ? 1'h0 : _GEN_55; // @[el2_dec_decode_ctl.scala 333:28] + wire _T_109 = nonblock_load_valid_m_delay & _T_90; // @[el2_dec_decode_ctl.scala 343:44] + wire _T_111 = _T_109 & cam_0_valid; // @[el2_dec_decode_ctl.scala 343:95] + wire nonblock_load_write_0 = _T_93 & cam_raw_0_valid; // @[el2_dec_decode_ctl.scala 352:66] + wire _T_116 = _GEN_130 == cam_raw_1_tag; // @[el2_dec_decode_ctl.scala 325:66] + wire _T_117 = io_lsu_nonblock_load_inv_r & _T_116; // @[el2_dec_decode_ctl.scala 325:45] + wire cam_inv_reset_val_1 = _T_117 & cam_1_valid; // @[el2_dec_decode_ctl.scala 325:82] + reg [4:0] cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_128 = r_d_i0rd == cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 338:80] + wire _T_129 = i0_wen_r & _T_128; // @[el2_dec_decode_ctl.scala 338:64] + reg cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_131 = _T_129 & cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 338:95] + wire _T_132 = cam_inv_reset_val_1 | _T_131; // @[el2_dec_decode_ctl.scala 338:44] + wire _GEN_63 = _T_132 ? 1'h0 : cam_1_valid; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_66 = _T_132 ? 1'h0 : cam_raw_1_wb; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_67 = cam_wen[1] | _GEN_63; // @[el2_dec_decode_ctl.scala 333:28] + wire _GEN_68 = cam_wen[1] ? 1'h0 : _GEN_66; // @[el2_dec_decode_ctl.scala 333:28] + wire _T_135 = nonblock_load_valid_m_delay & _T_116; // @[el2_dec_decode_ctl.scala 343:44] + wire _T_137 = _T_135 & cam_1_valid; // @[el2_dec_decode_ctl.scala 343:95] + wire nonblock_load_write_1 = _T_119 & cam_raw_1_valid; // @[el2_dec_decode_ctl.scala 352:66] + wire _T_142 = _GEN_130 == cam_raw_2_tag; // @[el2_dec_decode_ctl.scala 325:66] + wire _T_143 = io_lsu_nonblock_load_inv_r & _T_142; // @[el2_dec_decode_ctl.scala 325:45] + wire cam_inv_reset_val_2 = _T_143 & cam_2_valid; // @[el2_dec_decode_ctl.scala 325:82] + reg [4:0] cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_154 = r_d_i0rd == cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 338:80] + wire _T_155 = i0_wen_r & _T_154; // @[el2_dec_decode_ctl.scala 338:64] + reg cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_157 = _T_155 & cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 338:95] + wire _T_158 = cam_inv_reset_val_2 | _T_157; // @[el2_dec_decode_ctl.scala 338:44] + wire _GEN_74 = _T_158 ? 1'h0 : cam_2_valid; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_77 = _T_158 ? 1'h0 : cam_raw_2_wb; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_78 = cam_wen[2] | _GEN_74; // @[el2_dec_decode_ctl.scala 333:28] + wire _GEN_79 = cam_wen[2] ? 1'h0 : _GEN_77; // @[el2_dec_decode_ctl.scala 333:28] + wire _T_161 = nonblock_load_valid_m_delay & _T_142; // @[el2_dec_decode_ctl.scala 343:44] + wire _T_163 = _T_161 & cam_2_valid; // @[el2_dec_decode_ctl.scala 343:95] + wire nonblock_load_write_2 = _T_145 & cam_raw_2_valid; // @[el2_dec_decode_ctl.scala 352:66] + wire _T_168 = _GEN_130 == cam_raw_3_tag; // @[el2_dec_decode_ctl.scala 325:66] + wire _T_169 = io_lsu_nonblock_load_inv_r & _T_168; // @[el2_dec_decode_ctl.scala 325:45] + wire cam_inv_reset_val_3 = _T_169 & cam_3_valid; // @[el2_dec_decode_ctl.scala 325:82] + reg [4:0] cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_180 = r_d_i0rd == cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 338:80] + wire _T_181 = i0_wen_r & _T_180; // @[el2_dec_decode_ctl.scala 338:64] + reg cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 351:47] + wire _T_183 = _T_181 & cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 338:95] + wire _T_184 = cam_inv_reset_val_3 | _T_183; // @[el2_dec_decode_ctl.scala 338:44] + wire _GEN_85 = _T_184 ? 1'h0 : cam_3_valid; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_88 = _T_184 ? 1'h0 : cam_raw_3_wb; // @[el2_dec_decode_ctl.scala 338:116] + wire _GEN_89 = cam_wen[3] | _GEN_85; // @[el2_dec_decode_ctl.scala 333:28] + wire _GEN_90 = cam_wen[3] ? 1'h0 : _GEN_88; // @[el2_dec_decode_ctl.scala 333:28] + wire _T_187 = nonblock_load_valid_m_delay & _T_168; // @[el2_dec_decode_ctl.scala 343:44] + wire _T_189 = _T_187 & cam_3_valid; // @[el2_dec_decode_ctl.scala 343:95] + wire nonblock_load_write_3 = _T_171 & cam_raw_3_valid; // @[el2_dec_decode_ctl.scala 352:66] + wire _T_194 = r_d_i0rd == io_dec_nonblock_load_waddr; // @[el2_dec_decode_ctl.scala 357:44] + wire nonblock_load_cancel = _T_194 & i0_wen_r; // @[el2_dec_decode_ctl.scala 357:76] + wire _T_195 = nonblock_load_write_0 | nonblock_load_write_1; // @[el2_dec_decode_ctl.scala 358:95] + wire _T_196 = _T_195 | nonblock_load_write_2; // @[el2_dec_decode_ctl.scala 358:95] + wire _T_197 = _T_196 | nonblock_load_write_3; // @[el2_dec_decode_ctl.scala 358:95] + wire _T_199 = io_lsu_nonblock_load_data_valid & _T_197; // @[el2_dec_decode_ctl.scala 358:64] + wire _T_200 = ~nonblock_load_cancel; // @[el2_dec_decode_ctl.scala 358:109] + wire _T_202 = nonblock_load_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 359:54] + wire _T_203 = _T_202 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:66] + wire _T_204 = _T_203 & io_dec_i0_rs1_en_d; // @[el2_dec_decode_ctl.scala 359:97] + wire [4:0] i0r_rs2 = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 625:16] + wire _T_205 = nonblock_load_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 359:137] + wire _T_206 = _T_205 & io_lsu_nonblock_load_valid_m; // @[el2_dec_decode_ctl.scala 359:149] + wire _T_207 = _T_206 & io_dec_i0_rs2_en_d; // @[el2_dec_decode_ctl.scala 359:180] + wire i0_nonblock_boundary_stall = _T_204 | _T_207; // @[el2_dec_decode_ctl.scala 359:118] + wire [4:0] _T_209 = nonblock_load_write_0 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_210 = _T_209 & cam_raw_0_rd; // @[el2_dec_decode_ctl.scala 363:88] + wire _T_211 = io_dec_i0_rs1_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:121] + wire _T_212 = cam_raw_0_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:149] + wire _T_213 = _T_211 & _T_212; // @[el2_dec_decode_ctl.scala 363:136] + wire _T_214 = io_dec_i0_rs2_en_d & cam_0_valid; // @[el2_dec_decode_ctl.scala 363:182] + wire _T_215 = cam_raw_0_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:210] + wire _T_216 = _T_214 & _T_215; // @[el2_dec_decode_ctl.scala 363:197] + wire [4:0] _T_218 = nonblock_load_write_1 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_219 = _T_218 & cam_raw_1_rd; // @[el2_dec_decode_ctl.scala 363:88] + wire _T_220 = io_dec_i0_rs1_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:121] + wire _T_221 = cam_raw_1_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:149] + wire _T_222 = _T_220 & _T_221; // @[el2_dec_decode_ctl.scala 363:136] + wire _T_223 = io_dec_i0_rs2_en_d & cam_1_valid; // @[el2_dec_decode_ctl.scala 363:182] + wire _T_224 = cam_raw_1_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:210] + wire _T_225 = _T_223 & _T_224; // @[el2_dec_decode_ctl.scala 363:197] + wire [4:0] _T_227 = nonblock_load_write_2 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_228 = _T_227 & cam_raw_2_rd; // @[el2_dec_decode_ctl.scala 363:88] + wire _T_229 = io_dec_i0_rs1_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:121] + wire _T_230 = cam_raw_2_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:149] + wire _T_231 = _T_229 & _T_230; // @[el2_dec_decode_ctl.scala 363:136] + wire _T_232 = io_dec_i0_rs2_en_d & cam_2_valid; // @[el2_dec_decode_ctl.scala 363:182] + wire _T_233 = cam_raw_2_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:210] + wire _T_234 = _T_232 & _T_233; // @[el2_dec_decode_ctl.scala 363:197] + wire [4:0] _T_236 = nonblock_load_write_3 ? 5'h1f : 5'h0; // @[Bitwise.scala 72:12] + wire [4:0] _T_237 = _T_236 & cam_raw_3_rd; // @[el2_dec_decode_ctl.scala 363:88] + wire _T_238 = io_dec_i0_rs1_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:121] + wire _T_239 = cam_raw_3_rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 363:149] + wire _T_240 = _T_238 & _T_239; // @[el2_dec_decode_ctl.scala 363:136] + wire _T_241 = io_dec_i0_rs2_en_d & cam_3_valid; // @[el2_dec_decode_ctl.scala 363:182] + wire _T_242 = cam_raw_3_rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 363:210] + wire _T_243 = _T_241 & _T_242; // @[el2_dec_decode_ctl.scala 363:197] + wire [4:0] _T_244 = _T_210 | _T_219; // @[el2_dec_decode_ctl.scala 364:69] + wire [4:0] _T_245 = _T_244 | _T_228; // @[el2_dec_decode_ctl.scala 364:69] + wire _T_246 = _T_213 | _T_222; // @[el2_dec_decode_ctl.scala 364:102] + wire _T_247 = _T_246 | _T_231; // @[el2_dec_decode_ctl.scala 364:102] + wire ld_stall_1 = _T_247 | _T_240; // @[el2_dec_decode_ctl.scala 364:102] + wire _T_248 = _T_216 | _T_225; // @[el2_dec_decode_ctl.scala 364:134] + wire _T_249 = _T_248 | _T_234; // @[el2_dec_decode_ctl.scala 364:134] + wire ld_stall_2 = _T_249 | _T_243; // @[el2_dec_decode_ctl.scala 364:134] + wire _T_250 = ld_stall_1 | ld_stall_2; // @[el2_dec_decode_ctl.scala 366:38] + wire i0_nonblock_load_stall = _T_250 | i0_nonblock_boundary_stall; // @[el2_dec_decode_ctl.scala 366:51] + wire _T_252 = ~i0_predict_br; // @[el2_dec_decode_ctl.scala 375:34] + wire [3:0] _T_254 = i0_legal_decode_d ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire csr_read = i0_dp_csr_read & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 459:36] + wire _T_255 = csr_read & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 387:16] + wire _T_257 = ~csr_read; // @[el2_dec_decode_ctl.scala 388:6] + wire _T_258 = _T_257 & io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 388:16] + wire _T_260 = ~io_dec_csr_wen_unq_d; // @[el2_dec_decode_ctl.scala 389:18] + wire _T_261 = csr_read & _T_260; // @[el2_dec_decode_ctl.scala 389:16] + wire [3:0] _T_263 = i0_dp_mul ? 4'h1 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_264 = i0_dp_load ? 4'h2 : _T_263; // @[Mux.scala 98:16] + wire [3:0] _T_265 = i0_dp_store ? 4'h3 : _T_264; // @[Mux.scala 98:16] + wire [3:0] _T_266 = i0_dp_pm_alu ? 4'h4 : _T_265; // @[Mux.scala 98:16] + wire [3:0] _T_267 = _T_261 ? 4'h5 : _T_266; // @[Mux.scala 98:16] + wire [3:0] _T_268 = _T_258 ? 4'h6 : _T_267; // @[Mux.scala 98:16] + wire [3:0] _T_269 = _T_255 ? 4'h7 : _T_268; // @[Mux.scala 98:16] + wire [3:0] _T_270 = i0_dp_ebreak ? 4'h8 : _T_269; // @[Mux.scala 98:16] + wire [3:0] _T_271 = i0_dp_ecall ? 4'h9 : _T_270; // @[Mux.scala 98:16] + wire [3:0] _T_272 = i0_dp_fence ? 4'ha : _T_271; // @[Mux.scala 98:16] + wire [3:0] _T_273 = i0_dp_fence_i ? 4'hb : _T_272; // @[Mux.scala 98:16] + wire [3:0] _T_274 = i0_dp_mret ? 4'hc : _T_273; // @[Mux.scala 98:16] + wire [3:0] _T_275 = i0_dp_condbr ? 4'hd : _T_274; // @[Mux.scala 98:16] + wire [3:0] _T_276 = i0_dp_jal ? 4'he : _T_275; // @[Mux.scala 98:16] + reg lsu_idle; // @[el2_dec_decode_ctl.scala 400:45] + wire _T_333 = ~i0_pcall_case; // @[el2_dec_decode_ctl.scala 424:35] + wire _T_334 = i0_dp_jal & _T_333; // @[el2_dec_decode_ctl.scala 424:32] + wire _T_335 = ~i0_pja_case; // @[el2_dec_decode_ctl.scala 424:52] + wire _T_336 = _T_334 & _T_335; // @[el2_dec_decode_ctl.scala 424:50] + wire _T_337 = ~i0_pret_case; // @[el2_dec_decode_ctl.scala 424:67] + reg _T_339; // @[el2_dec_decode_ctl.scala 436:58] + wire lsu_decode_d = i0_legal_decode_d & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 578:40] + wire _T_902 = i0_dp_load | i0_dp_store; // @[el2_dec_decode_ctl.scala 792:43] + reg x_d_i0v; // @[el2_lib.scala 524:16] + wire _T_876 = io_dec_i0_rs1_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 772:48] + wire _T_877 = x_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 772:70] + wire i0_rs1_depend_i0_x = _T_876 & _T_877; // @[el2_dec_decode_ctl.scala 772:58] + wire _T_878 = io_dec_i0_rs1_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 773:48] + wire _T_879 = r_d_i0rd == i0r_rs1; // @[el2_dec_decode_ctl.scala 773:70] + wire i0_rs1_depend_i0_r = _T_878 & _T_879; // @[el2_dec_decode_ctl.scala 773:58] + wire [1:0] _T_891 = i0_rs1_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 779:63] + wire [1:0] i0_rs1_depth_d = i0_rs1_depend_i0_x ? 2'h1 : _T_891; // @[el2_dec_decode_ctl.scala 779:24] + wire _T_904 = _T_902 & i0_rs1_depth_d[0]; // @[el2_dec_decode_ctl.scala 792:58] + reg i0_x_c_load; // @[Reg.scala 15:16] + reg i0_r_c_load; // @[Reg.scala 15:16] + wire _T_887_load = i0_rs1_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 778:61] + wire i0_rs1_class_d_load = i0_rs1_depend_i0_x ? i0_x_c_load : _T_887_load; // @[el2_dec_decode_ctl.scala 778:24] + wire load_ldst_bypass_d = _T_904 & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 792:78] + wire _T_880 = io_dec_i0_rs2_en_d & x_d_i0v; // @[el2_dec_decode_ctl.scala 775:48] + wire _T_881 = x_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 775:70] + wire i0_rs2_depend_i0_x = _T_880 & _T_881; // @[el2_dec_decode_ctl.scala 775:58] + wire _T_882 = io_dec_i0_rs2_en_d & r_d_i0v; // @[el2_dec_decode_ctl.scala 776:48] + wire _T_883 = r_d_i0rd == i0r_rs2; // @[el2_dec_decode_ctl.scala 776:70] + wire i0_rs2_depend_i0_r = _T_882 & _T_883; // @[el2_dec_decode_ctl.scala 776:58] + wire [1:0] _T_900 = i0_rs2_depend_i0_r ? 2'h2 : 2'h0; // @[el2_dec_decode_ctl.scala 781:63] + wire [1:0] i0_rs2_depth_d = i0_rs2_depend_i0_x ? 2'h1 : _T_900; // @[el2_dec_decode_ctl.scala 781:24] + wire _T_907 = i0_dp_store & i0_rs2_depth_d[0]; // @[el2_dec_decode_ctl.scala 793:43] + wire _T_896_load = i0_rs2_depend_i0_r & i0_r_c_load; // @[el2_dec_decode_ctl.scala 780:61] + wire i0_rs2_class_d_load = i0_rs2_depend_i0_x ? i0_x_c_load : _T_896_load; // @[el2_dec_decode_ctl.scala 780:24] + wire store_data_bypass_d = _T_907 & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 793:63] + wire _T_349 = i0_dp_csr_clr | i0_dp_csr_set; // @[el2_dec_decode_ctl.scala 467:42] + reg r_d_csrwen; // @[el2_lib.scala 524:16] + reg r_d_i0valid; // @[el2_lib.scala 524:16] + wire _T_352 = r_d_csrwen & r_d_i0valid; // @[el2_dec_decode_ctl.scala 475:34] + reg [11:0] r_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_355 = r_d_csrwaddr == 12'h300; // @[el2_dec_decode_ctl.scala 478:45] + wire _T_356 = r_d_csrwaddr == 12'h304; // @[el2_dec_decode_ctl.scala 478:75] + wire _T_357 = _T_355 | _T_356; // @[el2_dec_decode_ctl.scala 478:59] + wire _T_358 = _T_357 & r_d_csrwen; // @[el2_dec_decode_ctl.scala 478:90] + wire _T_359 = _T_358 & r_d_i0valid; // @[el2_dec_decode_ctl.scala 478:103] + wire _T_360 = ~io_dec_tlu_i0_kill_writeb_wb; // @[el2_dec_decode_ctl.scala 478:119] + reg csr_read_x; // @[el2_dec_decode_ctl.scala 480:52] + reg csr_clr_x; // @[el2_dec_decode_ctl.scala 481:51] + reg csr_set_x; // @[el2_dec_decode_ctl.scala 482:51] + reg csr_write_x; // @[el2_dec_decode_ctl.scala 483:53] + reg csr_imm_x; // @[el2_dec_decode_ctl.scala 484:51] + wire i0_x_data_en = i0_pipe_en[3] | io_clk_override; // @[el2_dec_decode_ctl.scala 661:50] + reg [4:0] csrimm_x; // @[el2_lib.scala 514:16] + reg [31:0] csr_rddata_x; // @[el2_lib.scala 514:16] + wire [31:0] _T_394 = {27'h0,csrimm_x}; // @[Cat.scala 29:58] + wire _T_396 = ~csr_imm_x; // @[el2_dec_decode_ctl.scala 492:5] + wire [31:0] _T_397 = csr_imm_x ? _T_394 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_398 = _T_396 ? io_exu_csr_rs1_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] csr_mask_x = _T_397 | _T_398; // @[Mux.scala 27:72] + wire [31:0] _T_400 = ~csr_mask_x; // @[el2_dec_decode_ctl.scala 495:38] + wire [31:0] _T_401 = csr_rddata_x & _T_400; // @[el2_dec_decode_ctl.scala 495:35] + wire [31:0] _T_402 = csr_rddata_x | csr_mask_x; // @[el2_dec_decode_ctl.scala 496:35] + wire [31:0] _T_403 = csr_clr_x ? _T_401 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_404 = csr_set_x ? _T_402 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_405 = csr_write_x ? csr_mask_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_406 = _T_403 | _T_404; // @[Mux.scala 27:72] + wire [31:0] write_csr_data_x = _T_406 | _T_405; // @[Mux.scala 27:72] + wire _T_418 = ~tlu_wr_pause_r1; // @[el2_dec_decode_ctl.scala 506:44] + wire _T_419 = ~tlu_wr_pause_r2; // @[el2_dec_decode_ctl.scala 506:64] + wire _T_420 = _T_418 & _T_419; // @[el2_dec_decode_ctl.scala 506:61] + wire [31:0] _T_423 = write_csr_data - 32'h1; // @[el2_dec_decode_ctl.scala 509:59] + wire _T_425 = csr_clr_x | csr_set_x; // @[el2_dec_decode_ctl.scala 511:34] + wire _T_426 = _T_425 | csr_write_x; // @[el2_dec_decode_ctl.scala 511:46] + wire _T_427 = _T_426 & csr_read_x; // @[el2_dec_decode_ctl.scala 511:61] + wire _T_428 = _T_427 | io_dec_tlu_wr_pause_r; // @[el2_dec_decode_ctl.scala 511:75] + reg r_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_764 = r_d_i0v & r_d_i0load; // @[el2_dec_decode_ctl.scala 714:37] + reg [31:0] i0_result_r_raw; // @[el2_lib.scala 514:16] + wire [31:0] i0_result_corr_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 714:27] + reg x_d_csrwonly; // @[el2_lib.scala 524:16] + wire _T_432 = x_d_csrwonly | r_d_csrwonly; // @[el2_dec_decode_ctl.scala 520:38] + reg wbd_csrwonly; // @[el2_lib.scala 524:16] + wire prior_csr_write = _T_432 | wbd_csrwonly; // @[el2_dec_decode_ctl.scala 520:53] + wire debug_fence_raw = io_dec_debug_fence_d & io_dbg_cmd_wrdata[1]; // @[el2_dec_decode_ctl.scala 523:48] + wire debug_fence = debug_fence_raw | debug_fence_i; // @[el2_dec_decode_ctl.scala 524:40] + wire _T_436 = i0_dp_presync | io_dec_tlu_presync_d; // @[el2_dec_decode_ctl.scala 527:34] + wire _T_437 = _T_436 | debug_fence_i; // @[el2_dec_decode_ctl.scala 527:57] + wire _T_438 = _T_437 | debug_fence_raw; // @[el2_dec_decode_ctl.scala 527:73] + wire i0_presync = _T_438 | io_dec_tlu_pipelining_disable; // @[el2_dec_decode_ctl.scala 527:91] + wire [31:0] _T_462 = {16'h0,io_ifu_i0_cinst}; // @[Cat.scala 29:58] + wire _T_464 = ~illegal_lockout; // @[el2_dec_decode_ctl.scala 539:44] + reg [31:0] _T_465; // @[el2_lib.scala 514:16] + wire i0_div_prior_div_stall = i0_dp_div & io_dec_div_active; // @[el2_dec_decode_ctl.scala 543:42] + wire _T_470 = i0_dp_csr_read & prior_csr_write; // @[el2_dec_decode_ctl.scala 545:40] + wire _T_471 = _T_470 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 545:59] + wire _T_472 = _T_471 | pause_stall; // @[el2_dec_decode_ctl.scala 545:81] + wire _T_473 = _T_472 | leak1_i0_stall; // @[el2_dec_decode_ctl.scala 545:95] + wire _T_474 = _T_473 | io_dec_tlu_debug_stall; // @[el2_dec_decode_ctl.scala 546:20] + wire _T_475 = _T_474 | postsync_stall; // @[el2_dec_decode_ctl.scala 546:45] + wire prior_inflight = x_d_i0valid | r_d_i0valid; // @[el2_dec_decode_ctl.scala 568:41] + wire prior_inflight_eff = i0_dp_div ? x_d_i0valid : prior_inflight; // @[el2_dec_decode_ctl.scala 569:31] + wire presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 571:37] + wire _T_476 = _T_475 | presync_stall; // @[el2_dec_decode_ctl.scala 546:62] + wire _T_477 = i0_dp_fence | debug_fence; // @[el2_dec_decode_ctl.scala 547:19] + wire _T_478 = ~lsu_idle; // @[el2_dec_decode_ctl.scala 547:36] + wire _T_479 = _T_477 & _T_478; // @[el2_dec_decode_ctl.scala 547:34] + wire _T_480 = _T_476 | _T_479; // @[el2_dec_decode_ctl.scala 546:79] + wire _T_481 = _T_480 | i0_nonblock_load_stall; // @[el2_dec_decode_ctl.scala 547:47] + wire _T_822 = io_dec_i0_rs1_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 742:49] + wire _T_823 = io_div_waddr_wb == i0r_rs1; // @[el2_dec_decode_ctl.scala 742:88] + wire _T_824 = _T_822 & _T_823; // @[el2_dec_decode_ctl.scala 742:69] + wire _T_825 = io_dec_i0_rs2_en_d & io_dec_div_active; // @[el2_dec_decode_ctl.scala 743:25] + wire _T_826 = io_div_waddr_wb == i0r_rs2; // @[el2_dec_decode_ctl.scala 743:64] + wire _T_827 = _T_825 & _T_826; // @[el2_dec_decode_ctl.scala 743:45] + wire i0_nonblock_div_stall = _T_824 | _T_827; // @[el2_dec_decode_ctl.scala 742:102] + wire _T_483 = _T_481 | i0_nonblock_div_stall; // @[el2_dec_decode_ctl.scala 548:21] + wire i0_block_raw_d = _T_483 | i0_div_prior_div_stall; // @[el2_dec_decode_ctl.scala 548:45] + wire _T_484 = io_lsu_store_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 550:65] + wire i0_store_stall_d = i0_dp_store & _T_484; // @[el2_dec_decode_ctl.scala 550:39] + wire _T_485 = io_lsu_load_stall_any | io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 551:63] + wire i0_load_stall_d = i0_dp_load & _T_485; // @[el2_dec_decode_ctl.scala 551:38] + wire _T_486 = i0_block_raw_d | i0_store_stall_d; // @[el2_dec_decode_ctl.scala 552:38] + wire i0_block_d = _T_486 | i0_load_stall_d; // @[el2_dec_decode_ctl.scala 552:57] + wire _T_487 = ~i0_block_d; // @[el2_dec_decode_ctl.scala 556:46] + wire _T_488 = io_dec_ib0_valid_d & _T_487; // @[el2_dec_decode_ctl.scala 556:44] + wire _T_490 = _T_488 & _T_279; // @[el2_dec_decode_ctl.scala 556:61] + wire _T_493 = ~i0_block_raw_d; // @[el2_dec_decode_ctl.scala 557:46] + wire _T_494 = io_dec_ib0_valid_d & _T_493; // @[el2_dec_decode_ctl.scala 557:44] + wire _T_496 = _T_494 & _T_279; // @[el2_dec_decode_ctl.scala 557:61] + wire i0_exudecode_d = _T_496 & _T_467; // @[el2_dec_decode_ctl.scala 557:89] + wire i0_exulegal_decode_d = i0_exudecode_d & i0_legal; // @[el2_dec_decode_ctl.scala 558:46] + wire _T_498 = ~io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 562:51] + wire _T_517 = i0_dp_fence_i | debug_fence_i; // @[el2_dec_decode_ctl.scala 590:44] + wire [3:0] _T_522 = {io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d,io_dec_i0_decode_d}; // @[Cat.scala 29:58] + wire _T_704 = |i0_pipe_en[3:2]; // @[el2_dec_decode_ctl.scala 658:49] + wire i0_x_ctl_en = _T_704 | io_clk_override; // @[el2_dec_decode_ctl.scala 658:53] + reg x_t_legal; // @[el2_lib.scala 524:16] + reg x_t_icaf; // @[el2_lib.scala 524:16] + reg x_t_icaf_f1; // @[el2_lib.scala 524:16] + reg [1:0] x_t_icaf_type; // @[el2_lib.scala 524:16] + reg x_t_fence_i; // @[el2_lib.scala 524:16] + reg [3:0] x_t_i0trigger; // @[el2_lib.scala 524:16] + reg [3:0] x_t_pmu_i0_itype; // @[el2_lib.scala 524:16] + reg x_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] + wire [3:0] _T_530 = {io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb,io_dec_tlu_flush_lower_wb}; // @[Cat.scala 29:58] + wire [3:0] _T_531 = ~_T_530; // @[el2_dec_decode_ctl.scala 603:39] + reg r_t_legal; // @[el2_lib.scala 524:16] + reg r_t_icaf; // @[el2_lib.scala 524:16] + reg r_t_icaf_f1; // @[el2_lib.scala 524:16] + reg [1:0] r_t_icaf_type; // @[el2_lib.scala 524:16] + reg r_t_fence_i; // @[el2_lib.scala 524:16] + reg [3:0] r_t_i0trigger; // @[el2_lib.scala 524:16] + reg [3:0] r_t_pmu_i0_itype; // @[el2_lib.scala 524:16] + reg r_t_pmu_i0_br_unpred; // @[el2_lib.scala 524:16] + reg [3:0] lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 606:36] + reg lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 607:37] + reg r_d_i0store; // @[el2_lib.scala 524:16] + wire _T_536 = r_d_i0load | r_d_i0store; // @[el2_dec_decode_ctl.scala 611:56] + wire [3:0] _T_540 = {_T_536,_T_536,_T_536,_T_536}; // @[Cat.scala 29:58] + wire [3:0] _T_541 = _T_540 & lsu_trigger_match_r; // @[el2_dec_decode_ctl.scala 611:72] + wire [3:0] _T_542 = _T_541 | r_t_i0trigger; // @[el2_dec_decode_ctl.scala 611:95] + reg r_d_i0div; // @[el2_lib.scala 524:16] + wire _T_545 = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 617:53] + wire _T_556 = i0r_rs1 != 5'h0; // @[el2_dec_decode_ctl.scala 628:49] + wire _T_558 = i0r_rs2 != 5'h0; // @[el2_dec_decode_ctl.scala 629:49] + wire _T_560 = i0r_rd != 5'h0; // @[el2_dec_decode_ctl.scala 630:48] + wire i0_rd_en_d = i0_dp_rd & _T_560; // @[el2_dec_decode_ctl.scala 630:37] + wire i0_jalimm20 = i0_dp_jal & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 634:38] + wire _T_561 = ~i0_dp_jal; // @[el2_dec_decode_ctl.scala 635:27] + wire i0_uiimm20 = _T_561 & i0_dp_imm20; // @[el2_dec_decode_ctl.scala 635:38] + wire [31:0] _T_563 = i0_dp_csr_read ? io_dec_csr_rddata_d : 32'h0; // @[Mux.scala 27:72] + wire [9:0] _T_577 = {io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_586 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[31]}; // @[Cat.scala 29:58] + wire [31:0] _T_589 = {_T_586,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31:20]}; // @[Cat.scala 29:58] + wire [31:0] _T_684 = i0_dp_imm12 ? _T_589 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_618 = {27'h0,i0r_rs2}; // @[Cat.scala 29:58] + wire [31:0] _T_685 = i0_dp_shimm5 ? _T_618 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_689 = _T_684 | _T_685; // @[Mux.scala 27:72] + wire [31:0] _T_638 = {_T_577,io_dec_i0_instr_d[31],io_dec_i0_instr_d[31],io_dec_i0_instr_d[19:12],io_dec_i0_instr_d[20],io_dec_i0_instr_d[30:21],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_686 = i0_jalimm20 ? _T_638 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_690 = _T_689 | _T_686; // @[Mux.scala 27:72] + wire [31:0] _T_652 = {io_dec_i0_instr_d[31:12],12'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_687 = i0_uiimm20 ? _T_652 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_691 = _T_690 | _T_687; // @[Mux.scala 27:72] + wire _T_653 = i0_csr_write_only_d & i0_dp_csr_imm; // @[el2_dec_decode_ctl.scala 646:26] + wire [31:0] _T_683 = {27'h0,i0r_rs1}; // @[Cat.scala 29:58] + wire [31:0] _T_688 = _T_653 ? _T_683 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_immed_d = _T_691 | _T_688; // @[Mux.scala 27:72] + wire [31:0] _T_564 = _T_347 ? i0_immed_d : 32'h0; // @[Mux.scala 27:72] + wire i0_d_c_mul = i0_dp_mul & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 650:44] + wire i0_d_c_load = i0_dp_load & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 651:44] + wire i0_d_c_alu = i0_dp_alu & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 652:44] + reg i0_x_c_mul; // @[Reg.scala 15:16] + reg i0_x_c_alu; // @[Reg.scala 15:16] + reg i0_r_c_mul; // @[Reg.scala 15:16] + reg i0_r_c_alu; // @[Reg.scala 15:16] + wire _T_710 = |i0_pipe_en[1:0]; // @[el2_dec_decode_ctl.scala 660:49] + wire i0_r_data_en = i0_pipe_en[2] | io_clk_override; // @[el2_dec_decode_ctl.scala 662:50] + reg x_d_i0store; // @[el2_lib.scala 524:16] + reg x_d_i0div; // @[el2_lib.scala 524:16] + reg x_d_csrwen; // @[el2_lib.scala 524:16] + reg [11:0] x_d_csrwaddr; // @[el2_lib.scala 524:16] + wire _T_733 = x_d_i0v & _T_743; // @[el2_dec_decode_ctl.scala 684:37] + wire _T_737 = x_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 685:37] + wire _T_756 = ~r_d_i0div; // @[el2_dec_decode_ctl.scala 700:49] + wire _T_757 = i0_wen_r & _T_756; // @[el2_dec_decode_ctl.scala 700:47] + wire _T_758 = ~i0_load_kill_wen_r; // @[el2_dec_decode_ctl.scala 700:65] + wire _T_761 = x_d_i0v & x_d_i0load; // @[el2_dec_decode_ctl.scala 709:42] + wire _T_768 = io_i0_ap_predict_nt & _T_561; // @[el2_dec_decode_ctl.scala 715:52] + wire [11:0] _T_781 = {10'h0,io_dec_i0_pc4_d,i0_ap_pc2}; // @[Cat.scala 29:58] + reg [11:0] last_br_immed_x; // @[el2_lib.scala 514:16] + wire _T_799 = x_d_i0div & x_d_i0valid; // @[el2_dec_decode_ctl.scala 723:40] + wire div_e1_to_r = _T_799 | _T_545; // @[el2_dec_decode_ctl.scala 723:55] + wire _T_802 = x_d_i0rd == 5'h0; // @[el2_dec_decode_ctl.scala 725:69] + wire _T_803 = _T_799 & _T_802; // @[el2_dec_decode_ctl.scala 725:57] + wire _T_805 = _T_799 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 726:30] + wire _T_806 = _T_803 | _T_805; // @[el2_dec_decode_ctl.scala 725:86] + wire _T_808 = _T_545 & io_dec_tlu_flush_lower_r; // @[el2_dec_decode_ctl.scala 727:30] + wire _T_809 = _T_808 & io_dec_tlu_i0_kill_writeb_r; // @[el2_dec_decode_ctl.scala 727:57] + wire div_flush = _T_806 | _T_809; // @[el2_dec_decode_ctl.scala 726:59] + wire _T_810 = io_dec_div_active & div_flush; // @[el2_dec_decode_ctl.scala 731:51] + wire _T_811 = ~div_e1_to_r; // @[el2_dec_decode_ctl.scala 732:26] + wire _T_812 = io_dec_div_active & _T_811; // @[el2_dec_decode_ctl.scala 732:24] + wire _T_813 = r_d_i0rd == io_div_waddr_wb; // @[el2_dec_decode_ctl.scala 732:51] + wire _T_814 = _T_812 & _T_813; // @[el2_dec_decode_ctl.scala 732:39] + wire _T_815 = _T_814 & i0_wen_r; // @[el2_dec_decode_ctl.scala 732:72] + wire nonblock_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 731:65] + wire i0_div_decode_d = i0_legal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 735:55] + wire _T_817 = ~io_exu_div_wren; // @[el2_dec_decode_ctl.scala 737:62] + wire _T_818 = io_dec_div_active & _T_817; // @[el2_dec_decode_ctl.scala 737:60] + wire _T_819 = ~nonblock_div_cancel; // @[el2_dec_decode_ctl.scala 737:81] + wire _T_820 = _T_818 & _T_819; // @[el2_dec_decode_ctl.scala 737:79] + reg _T_821; // @[el2_dec_decode_ctl.scala 739:54] + reg [4:0] _T_830; // @[Reg.scala 27:20] + reg [31:0] i0_inst_x; // @[el2_lib.scala 514:16] + reg [31:0] i0_inst_r; // @[el2_lib.scala 514:16] + reg [31:0] i0_inst_wb; // @[el2_lib.scala 514:16] + reg [31:0] _T_837; // @[el2_lib.scala 514:16] + reg [30:0] i0_pc_wb; // @[el2_lib.scala 514:16] + reg [30:0] _T_840; // @[el2_lib.scala 514:16] + reg [30:0] dec_i0_pc_r; // @[el2_lib.scala 514:16] + wire [31:0] _T_842 = {io_exu_i0_pc_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_843 = {last_br_immed_x,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_846 = _T_842[12:1] + _T_843[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_849 = _T_842[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_852 = _T_842[31:13] - 19'h1; // @[el2_lib.scala 210:27] + wire _T_855 = ~_T_846[12]; // @[el2_lib.scala 212:28] + wire _T_856 = _T_843[12] ^ _T_855; // @[el2_lib.scala 212:26] + wire _T_859 = ~_T_843[12]; // @[el2_lib.scala 213:8] + wire _T_861 = _T_859 & _T_846[12]; // @[el2_lib.scala 213:14] + wire _T_865 = _T_843[12] & _T_855; // @[el2_lib.scala 214:14] + wire [18:0] _T_867 = _T_856 ? _T_842[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_868 = _T_861 ? _T_849 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_869 = _T_865 ? _T_852 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_870 = _T_867 | _T_868; // @[Mux.scala 27:72] + wire [18:0] _T_871 = _T_870 | _T_869; // @[Mux.scala 27:72] + wire [31:0] temp_pred_correct_npc_x = {_T_871,_T_846[11:0],1'h0}; // @[Cat.scala 29:58] + wire _T_887_mul = i0_rs1_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 778:61] + wire _T_887_alu = i0_rs1_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 778:61] + wire i0_rs1_class_d_mul = i0_rs1_depend_i0_x ? i0_x_c_mul : _T_887_mul; // @[el2_dec_decode_ctl.scala 778:24] + wire i0_rs1_class_d_alu = i0_rs1_depend_i0_x ? i0_x_c_alu : _T_887_alu; // @[el2_dec_decode_ctl.scala 778:24] + wire _T_896_mul = i0_rs2_depend_i0_r & i0_r_c_mul; // @[el2_dec_decode_ctl.scala 780:61] + wire _T_896_alu = i0_rs2_depend_i0_r & i0_r_c_alu; // @[el2_dec_decode_ctl.scala 780:61] + wire i0_rs2_class_d_mul = i0_rs2_depend_i0_x ? i0_x_c_mul : _T_896_mul; // @[el2_dec_decode_ctl.scala 780:24] + wire i0_rs2_class_d_alu = i0_rs2_depend_i0_x ? i0_x_c_alu : _T_896_alu; // @[el2_dec_decode_ctl.scala 780:24] + wire _T_909 = io_dec_i0_rs1_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 798:62] + wire _T_910 = io_dec_nonblock_load_waddr == i0r_rs1; // @[el2_dec_decode_ctl.scala 798:119] + wire i0_rs1_nonblock_load_bypass_en_d = _T_909 & _T_910; // @[el2_dec_decode_ctl.scala 798:89] + wire _T_911 = io_dec_i0_rs2_en_d & io_dec_nonblock_load_wen; // @[el2_dec_decode_ctl.scala 800:62] + wire _T_912 = io_dec_nonblock_load_waddr == i0r_rs2; // @[el2_dec_decode_ctl.scala 800:119] + wire i0_rs2_nonblock_load_bypass_en_d = _T_911 & _T_912; // @[el2_dec_decode_ctl.scala 800:89] + wire _T_914 = i0_rs1_class_d_alu | i0_rs1_class_d_mul; // @[el2_dec_decode_ctl.scala 803:66] + wire _T_915 = i0_rs1_depth_d[0] & _T_914; // @[el2_dec_decode_ctl.scala 803:45] + wire _T_917 = i0_rs1_depth_d[0] & i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:108] + wire _T_920 = _T_914 | i0_rs1_class_d_load; // @[el2_dec_decode_ctl.scala 803:196] + wire _T_921 = i0_rs1_depth_d[1] & _T_920; // @[el2_dec_decode_ctl.scala 803:153] + wire [2:0] i0_rs1bypass = {_T_915,_T_917,_T_921}; // @[Cat.scala 29:58] + wire _T_925 = i0_rs2_class_d_alu | i0_rs2_class_d_mul; // @[el2_dec_decode_ctl.scala 805:67] + wire _T_926 = i0_rs2_depth_d[0] & _T_925; // @[el2_dec_decode_ctl.scala 805:45] + wire _T_928 = i0_rs2_depth_d[0] & i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:109] + wire _T_931 = _T_925 | i0_rs2_class_d_load; // @[el2_dec_decode_ctl.scala 805:196] + wire _T_932 = i0_rs2_depth_d[1] & _T_931; // @[el2_dec_decode_ctl.scala 805:153] + wire [2:0] i0_rs2bypass = {_T_926,_T_928,_T_932}; // @[Cat.scala 29:58] + wire _T_938 = i0_rs1bypass[1] | i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 807:75] + wire _T_940 = ~i0_rs1bypass[2]; // @[el2_dec_decode_ctl.scala 807:96] + wire _T_941 = _T_940 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 807:113] + wire _T_942 = _T_938 | _T_941; // @[el2_dec_decode_ctl.scala 807:93] + wire _T_947 = i0_rs2bypass[1] | i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 808:75] + wire _T_949 = ~i0_rs2bypass[2]; // @[el2_dec_decode_ctl.scala 808:96] + wire _T_950 = _T_949 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 808:113] + wire _T_951 = _T_947 | _T_950; // @[el2_dec_decode_ctl.scala 808:93] + wire _T_958 = ~i0_rs1bypass[1]; // @[el2_dec_decode_ctl.scala 813:6] + wire _T_960 = ~i0_rs1bypass[0]; // @[el2_dec_decode_ctl.scala 813:25] + wire _T_961 = _T_958 & _T_960; // @[el2_dec_decode_ctl.scala 813:23] + wire _T_962 = _T_961 & i0_rs1_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 813:42] + wire [31:0] _T_964 = i0_rs1bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_965 = i0_rs1bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_966 = _T_962 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_967 = _T_964 | _T_965; // @[Mux.scala 27:72] + wire _T_975 = ~i0_rs2bypass[1]; // @[el2_dec_decode_ctl.scala 818:6] + wire _T_977 = ~i0_rs2bypass[0]; // @[el2_dec_decode_ctl.scala 818:25] + wire _T_978 = _T_975 & _T_977; // @[el2_dec_decode_ctl.scala 818:23] + wire _T_979 = _T_978 & i0_rs2_nonblock_load_bypass_en_d; // @[el2_dec_decode_ctl.scala 818:42] + wire [31:0] _T_981 = i0_rs2bypass[1] ? io_lsu_result_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_982 = i0_rs2bypass[0] ? i0_result_r_raw : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_983 = _T_979 ? io_lsu_nonblock_load_data : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_984 = _T_981 | _T_982; // @[Mux.scala 27:72] + wire _T_987 = i0_dp_raw_load | i0_dp_raw_store; // @[el2_dec_decode_ctl.scala 820:68] + wire _T_988 = io_dec_ib0_valid_d & _T_987; // @[el2_dec_decode_ctl.scala 820:50] + wire _T_989 = ~io_dma_dccm_stall_any; // @[el2_dec_decode_ctl.scala 820:89] + wire _T_990 = _T_988 & _T_989; // @[el2_dec_decode_ctl.scala 820:87] + wire _T_992 = _T_990 & _T_493; // @[el2_dec_decode_ctl.scala 820:112] + wire _T_994 = ~io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 822:6] + wire _T_995 = _T_994 & i0_dp_lsu; // @[el2_dec_decode_ctl.scala 822:27] + wire _T_996 = _T_995 & i0_dp_load; // @[el2_dec_decode_ctl.scala 822:39] + wire _T_1001 = _T_995 & i0_dp_store; // @[el2_dec_decode_ctl.scala 823:39] + wire [11:0] _T_1005 = {io_dec_i0_instr_d[31:25],i0r_rd}; // @[Cat.scala 29:58] + wire [11:0] _T_1006 = _T_996 ? io_dec_i0_instr_d[31:20] : 12'h0; // @[Mux.scala 27:72] + wire [11:0] _T_1007 = _T_1001 ? _T_1005 : 12'h0; // @[Mux.scala 27:72] + rvclkhdr data_gated_cgc ( // @[el2_dec_decode_ctl.scala 222:29] + .io_l1clk(data_gated_cgc_io_l1clk), + .io_clk(data_gated_cgc_io_clk), + .io_en(data_gated_cgc_io_en), + .io_scan_mode(data_gated_cgc_io_scan_mode) + ); + el2_dec_dec_ctl i0_dec ( // @[el2_dec_decode_ctl.scala 396:22] + .io_ins(i0_dec_io_ins), + .io_out_alu(i0_dec_io_out_alu), + .io_out_rs1(i0_dec_io_out_rs1), + .io_out_rs2(i0_dec_io_out_rs2), + .io_out_imm12(i0_dec_io_out_imm12), + .io_out_rd(i0_dec_io_out_rd), + .io_out_shimm5(i0_dec_io_out_shimm5), + .io_out_imm20(i0_dec_io_out_imm20), + .io_out_pc(i0_dec_io_out_pc), + .io_out_load(i0_dec_io_out_load), + .io_out_store(i0_dec_io_out_store), + .io_out_lsu(i0_dec_io_out_lsu), + .io_out_add(i0_dec_io_out_add), + .io_out_sub(i0_dec_io_out_sub), + .io_out_land(i0_dec_io_out_land), + .io_out_lor(i0_dec_io_out_lor), + .io_out_lxor(i0_dec_io_out_lxor), + .io_out_sll(i0_dec_io_out_sll), + .io_out_sra(i0_dec_io_out_sra), + .io_out_srl(i0_dec_io_out_srl), + .io_out_slt(i0_dec_io_out_slt), + .io_out_unsign(i0_dec_io_out_unsign), + .io_out_condbr(i0_dec_io_out_condbr), + .io_out_beq(i0_dec_io_out_beq), + .io_out_bne(i0_dec_io_out_bne), + .io_out_bge(i0_dec_io_out_bge), + .io_out_blt(i0_dec_io_out_blt), + .io_out_jal(i0_dec_io_out_jal), + .io_out_by(i0_dec_io_out_by), + .io_out_half(i0_dec_io_out_half), + .io_out_word(i0_dec_io_out_word), + .io_out_csr_read(i0_dec_io_out_csr_read), + .io_out_csr_clr(i0_dec_io_out_csr_clr), + .io_out_csr_set(i0_dec_io_out_csr_set), + .io_out_csr_write(i0_dec_io_out_csr_write), + .io_out_csr_imm(i0_dec_io_out_csr_imm), + .io_out_presync(i0_dec_io_out_presync), + .io_out_postsync(i0_dec_io_out_postsync), + .io_out_ebreak(i0_dec_io_out_ebreak), + .io_out_ecall(i0_dec_io_out_ecall), + .io_out_mret(i0_dec_io_out_mret), + .io_out_mul(i0_dec_io_out_mul), + .io_out_rs1_sign(i0_dec_io_out_rs1_sign), + .io_out_rs2_sign(i0_dec_io_out_rs2_sign), + .io_out_low(i0_dec_io_out_low), + .io_out_div(i0_dec_io_out_div), + .io_out_rem(i0_dec_io_out_rem), + .io_out_fence(i0_dec_io_out_fence), + .io_out_fence_i(i0_dec_io_out_fence_i), + .io_out_pm_alu(i0_dec_io_out_pm_alu), + .io_out_legal(i0_dec_io_out_legal) + ); + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + rvclkhdr rvclkhdr_18 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_18_io_l1clk), + .io_clk(rvclkhdr_18_io_clk), + .io_en(rvclkhdr_18_io_en), + .io_scan_mode(rvclkhdr_18_io_scan_mode) + ); + assign io_dec_extint_stall = _T_339; // @[el2_dec_decode_ctl.scala 436:23] + assign io_dec_i0_inst_wb1 = _T_837; // @[el2_dec_decode_ctl.scala 757:22] + assign io_dec_i0_pc_wb1 = _T_840; // @[el2_dec_decode_ctl.scala 760:20] + assign io_dec_i0_rs1_en_d = i0_dp_rs1 & _T_556; // @[el2_dec_decode_ctl.scala 628:24] + assign io_dec_i0_rs2_en_d = i0_dp_rs2 & _T_558; // @[el2_dec_decode_ctl.scala 629:24] + assign io_dec_i0_rs1_d = io_dec_i0_instr_d[19:15]; // @[el2_dec_decode_ctl.scala 631:19] + assign io_dec_i0_rs2_d = io_dec_i0_instr_d[24:20]; // @[el2_dec_decode_ctl.scala 632:19] + assign io_dec_i0_immed_d = _T_563 | _T_564; // @[el2_dec_decode_ctl.scala 637:21] + assign io_dec_i0_br_immed_d = _T_768 ? i0_br_offset : _T_781; // @[el2_dec_decode_ctl.scala 715:24] + assign io_i0_ap_land = _T_40 ? 1'h0 : i0_dp_raw_land; // @[el2_dec_decode_ctl.scala 289:20] + assign io_i0_ap_lor = _T_40 | i0_dp_raw_lor; // @[el2_dec_decode_ctl.scala 290:20] + assign io_i0_ap_lxor = _T_40 ? 1'h0 : i0_dp_raw_lxor; // @[el2_dec_decode_ctl.scala 291:20] + assign io_i0_ap_sll = _T_40 ? 1'h0 : i0_dp_raw_sll; // @[el2_dec_decode_ctl.scala 292:20] + assign io_i0_ap_srl = _T_40 ? 1'h0 : i0_dp_raw_srl; // @[el2_dec_decode_ctl.scala 293:20] + assign io_i0_ap_sra = _T_40 ? 1'h0 : i0_dp_raw_sra; // @[el2_dec_decode_ctl.scala 294:20] + assign io_i0_ap_beq = _T_40 ? 1'h0 : i0_dp_raw_beq; // @[el2_dec_decode_ctl.scala 297:20] + assign io_i0_ap_bne = _T_40 ? 1'h0 : i0_dp_raw_bne; // @[el2_dec_decode_ctl.scala 298:20] + assign io_i0_ap_blt = _T_40 ? 1'h0 : i0_dp_raw_blt; // @[el2_dec_decode_ctl.scala 299:20] + assign io_i0_ap_bge = _T_40 ? 1'h0 : i0_dp_raw_bge; // @[el2_dec_decode_ctl.scala 300:20] + assign io_i0_ap_add = _T_40 ? 1'h0 : i0_dp_raw_add; // @[el2_dec_decode_ctl.scala 287:20] + assign io_i0_ap_sub = _T_40 ? 1'h0 : i0_dp_raw_sub; // @[el2_dec_decode_ctl.scala 288:20] + assign io_i0_ap_slt = _T_40 ? 1'h0 : i0_dp_raw_slt; // @[el2_dec_decode_ctl.scala 295:20] + assign io_i0_ap_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 296:20] + assign io_i0_ap_jal = _T_336 & _T_337; // @[el2_dec_decode_ctl.scala 303:22] + assign io_i0_ap_predict_t = _T_46 & i0_predict_br; // @[el2_dec_decode_ctl.scala 285:26] + assign io_i0_ap_predict_nt = _T_47 & i0_predict_br; // @[el2_dec_decode_ctl.scala 284:26] + assign io_i0_ap_csr_write = i0_csr_write & _T_347; // @[el2_dec_decode_ctl.scala 301:22] + assign io_i0_ap_csr_imm = _T_40 ? 1'h0 : i0_dp_raw_csr_imm; // @[el2_dec_decode_ctl.scala 302:22] + assign io_dec_i0_decode_d = _T_490 & _T_467; // @[el2_dec_decode_ctl.scala 556:22 el2_dec_decode_ctl.scala 622:22] + assign io_dec_i0_alu_decode_d = i0_exulegal_decode_d & i0_dp_alu; // @[el2_dec_decode_ctl.scala 576:26] + assign io_dec_i0_rs1_bypass_data_d = _T_967 | _T_966; // @[el2_dec_decode_ctl.scala 810:31] + assign io_dec_i0_rs2_bypass_data_d = _T_984 | _T_983; // @[el2_dec_decode_ctl.scala 815:31] + assign io_dec_i0_waddr_r = r_d_i0rd; // @[el2_dec_decode_ctl.scala 698:27] + assign io_dec_i0_wen_r = _T_757 & _T_758; // @[el2_dec_decode_ctl.scala 700:32] + assign io_dec_i0_wdata_r = _T_764 ? io_lsu_result_corr_r : i0_result_r_raw; // @[el2_dec_decode_ctl.scala 701:26] + assign io_dec_i0_select_pc_d = _T_40 ? 1'h0 : i0_dp_raw_pc; // @[el2_dec_decode_ctl.scala 275:25] + assign io_dec_i0_rs1_bypass_en_d = {i0_rs1bypass[2],_T_942}; // @[el2_dec_decode_ctl.scala 807:34] + assign io_dec_i0_rs2_bypass_en_d = {i0_rs2bypass[2],_T_951}; // @[el2_dec_decode_ctl.scala 808:34] + assign io_lsu_p_fast_int = io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 442:24] + assign io_lsu_p_by = io_dec_extint_stall ? 1'h0 : i0_dp_by; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 448:35] + assign io_lsu_p_half = io_dec_extint_stall ? 1'h0 : i0_dp_half; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 449:35] + assign io_lsu_p_word = io_dec_extint_stall | i0_dp_word; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 441:24 el2_dec_decode_ctl.scala 450:35] + assign io_lsu_p_dword = 1'h0; // @[el2_dec_decode_ctl.scala 438:12] + assign io_lsu_p_load = io_dec_extint_stall | i0_dp_load; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 440:24 el2_dec_decode_ctl.scala 446:35] + assign io_lsu_p_store = io_dec_extint_stall ? 1'h0 : i0_dp_store; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 447:35] + assign io_lsu_p_unsign = io_dec_extint_stall ? 1'h0 : i0_dp_unsign; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 454:35] + assign io_lsu_p_dma = 1'h0; // @[el2_dec_decode_ctl.scala 438:12] + assign io_lsu_p_store_data_bypass_d = io_dec_extint_stall ? 1'h0 : store_data_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 452:35] + assign io_lsu_p_load_ldst_bypass_d = io_dec_extint_stall ? 1'h0 : load_ldst_bypass_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 451:35] + assign io_lsu_p_store_data_bypass_m = 1'h0; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 453:35] + assign io_lsu_p_valid = io_dec_extint_stall | lsu_decode_d; // @[el2_dec_decode_ctl.scala 438:12 el2_dec_decode_ctl.scala 443:24 el2_dec_decode_ctl.scala 445:35] + assign io_mul_p_valid = i0_exulegal_decode_d & i0_dp_mul; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 431:21] + assign io_mul_p_rs1_sign = _T_40 ? 1'h0 : i0_dp_raw_rs1_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 432:21] + assign io_mul_p_rs2_sign = _T_40 ? 1'h0 : i0_dp_raw_rs2_sign; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 433:21] + assign io_mul_p_low = _T_40 ? 1'h0 : i0_dp_raw_low; // @[el2_dec_decode_ctl.scala 126:12 el2_dec_decode_ctl.scala 434:21] + assign io_mul_p_bext = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_bdep = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_clmul = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_clmulh = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_clmulr = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_grev = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_shfl = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_unshfl = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32_b = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32_h = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32_w = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32c_b = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32c_h = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_crc32c_w = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_mul_p_bfp = 1'h0; // @[el2_dec_decode_ctl.scala 126:12] + assign io_div_p_valid = i0_exulegal_decode_d & i0_dp_div; // @[el2_dec_decode_ctl.scala 427:21] + assign io_div_p_unsign = _T_40 ? 1'h0 : i0_dp_raw_unsign; // @[el2_dec_decode_ctl.scala 428:21] + assign io_div_p_rem = _T_40 ? 1'h0 : i0_dp_raw_rem; // @[el2_dec_decode_ctl.scala 429:21] + assign io_div_waddr_wb = _T_830; // @[el2_dec_decode_ctl.scala 745:19] + assign io_dec_div_cancel = _T_810 | _T_815; // @[el2_dec_decode_ctl.scala 734:29] + assign io_dec_lsu_valid_raw_d = _T_992 | io_dec_extint_stall; // @[el2_dec_decode_ctl.scala 820:26] + assign io_dec_lsu_offset_d = _T_1006 | _T_1007; // @[el2_dec_decode_ctl.scala 821:23] + assign io_dec_csr_ren_d = _T_40 ? 1'h0 : i0_dp_raw_csr_read; // @[el2_dec_decode_ctl.scala 458:21] + assign io_dec_csr_wen_unq_d = _T_349 | i0_csr_write; // @[el2_dec_decode_ctl.scala 467:24] + assign io_dec_csr_any_unq_d = i0_dp_csr_read | i0_csr_write; // @[el2_dec_decode_ctl.scala 533:24] + assign io_dec_csr_rdaddr_d = io_dec_i0_instr_d[31:20]; // @[el2_dec_decode_ctl.scala 470:24] + assign io_dec_csr_wen_r = _T_352 & _T_754; // @[el2_dec_decode_ctl.scala 475:20] + assign io_dec_csr_wraddr_r = r_d_csrwaddr; // @[el2_dec_decode_ctl.scala 471:23] + assign io_dec_csr_wrdata_r = r_d_csrwonly ? i0_result_corr_r : write_csr_data; // @[el2_dec_decode_ctl.scala 518:24] + assign io_dec_csr_stall_int_ff = _T_359 & _T_360; // @[el2_dec_decode_ctl.scala 478:27] + assign io_dec_tlu_i0_valid_r = r_d_i0valid & _T_743; // @[el2_dec_decode_ctl.scala 582:29] + assign io_dec_tlu_packet_r_legal = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_legal; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_icaf = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_icaf_f1 = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_icaf_f1; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_icaf_type = io_dec_tlu_flush_lower_wb ? 2'h0 : r_t_icaf_type; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_fence_i = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_fence_i; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_i0trigger = io_dec_tlu_flush_lower_wb ? 4'h0 : _T_542; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_pmu_i0_itype = io_dec_tlu_flush_lower_wb ? 4'h0 : r_t_pmu_i0_itype; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_pmu_i0_br_unpred = io_dec_tlu_flush_lower_wb ? 1'h0 : r_t_pmu_i0_br_unpred; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_packet_r_pmu_divide = r_d_i0div & r_d_i0valid; // @[el2_dec_decode_ctl.scala 616:39 el2_dec_decode_ctl.scala 617:39] + assign io_dec_tlu_packet_r_pmu_lsu_misaligned = io_dec_tlu_flush_lower_wb ? 1'h0 : lsu_pmu_misaligned_r; // @[el2_dec_decode_ctl.scala 616:39] + assign io_dec_tlu_i0_pc_r = dec_i0_pc_r; // @[el2_dec_decode_ctl.scala 763:27] + assign io_dec_illegal_inst = _T_465; // @[el2_dec_decode_ctl.scala 540:23] + assign io_pred_correct_npc_x = temp_pred_correct_npc_x[31:1]; // @[el2_dec_decode_ctl.scala 768:25] + assign io_dec_i0_predict_p_d_misp = 1'h0; // @[el2_dec_decode_ctl.scala 231:38] + assign io_dec_i0_predict_p_d_ataken = 1'h0; // @[el2_dec_decode_ctl.scala 232:38] + assign io_dec_i0_predict_p_d_boffset = 1'h0; // @[el2_dec_decode_ctl.scala 233:38] + assign io_dec_i0_predict_p_d_pc4 = io_dec_i0_pc4_d; // @[el2_dec_decode_ctl.scala 238:38] + assign io_dec_i0_predict_p_d_hist = io_dec_i0_brp_hist; // @[el2_dec_decode_ctl.scala 239:38] + assign io_dec_i0_predict_p_d_toffset = _T_314 ? i0_pcall_imm[12:1] : _T_323; // @[el2_dec_decode_ctl.scala 252:44] + assign io_dec_i0_predict_p_d_valid = i0_brp_valid & i0_legal_decode_d; // @[el2_dec_decode_ctl.scala 240:38] + assign io_dec_i0_predict_p_d_br_error = _T_32 & _T_17; // @[el2_dec_decode_ctl.scala 247:51] + assign io_dec_i0_predict_p_d_br_start_error = _T_35 & _T_17; // @[el2_dec_decode_ctl.scala 248:51] + assign io_dec_i0_predict_p_d_prett = io_dec_i0_brp_prett; // @[el2_dec_decode_ctl.scala 237:38] + assign io_dec_i0_predict_p_d_pcall = i0_dp_jal & i0_pcall_case; // @[el2_dec_decode_ctl.scala 234:38] + assign io_dec_i0_predict_p_d_pret = i0_dp_jal & i0_pret_case; // @[el2_dec_decode_ctl.scala 236:38] + assign io_dec_i0_predict_p_d_pja = i0_dp_jal & i0_pja_case; // @[el2_dec_decode_ctl.scala 235:38] + assign io_dec_i0_predict_p_d_way = io_dec_i0_brp_way; // @[el2_dec_decode_ctl.scala 254:51] + assign io_i0_predict_fghr_d = io_dec_i0_bp_fghr; // @[el2_dec_decode_ctl.scala 253:32] + assign io_i0_predict_index_d = io_dec_i0_bp_index; // @[el2_dec_decode_ctl.scala 249:32] + assign io_i0_predict_btag_d = io_dec_i0_bp_btag; // @[el2_dec_decode_ctl.scala 250:32] + assign io_dec_data_en = {i0_x_data_en,i0_r_data_en}; // @[el2_dec_decode_ctl.scala 666:27] + assign io_dec_ctl_en = {i0_x_ctl_en,i0_r_ctl_en}; // @[el2_dec_decode_ctl.scala 667:27] + assign io_dec_pmu_instr_decoded = io_dec_i0_decode_d; // @[el2_dec_decode_ctl.scala 561:28] + assign io_dec_pmu_decode_stall = io_dec_ib0_valid_d & _T_498; // @[el2_dec_decode_ctl.scala 562:27] + assign io_dec_pmu_presync_stall = i0_presync & prior_inflight_eff; // @[el2_dec_decode_ctl.scala 564:29] + assign io_dec_pmu_postsync_stall = postsync_stall; // @[el2_dec_decode_ctl.scala 563:29] + assign io_dec_nonblock_load_wen = _T_199 & _T_200; // @[el2_dec_decode_ctl.scala 358:28] + assign io_dec_nonblock_load_waddr = _T_245 | _T_237; // @[el2_dec_decode_ctl.scala 355:29 el2_dec_decode_ctl.scala 365:29] + assign io_dec_pause_state = pause_stall; // @[el2_dec_decode_ctl.scala 502:22] + assign io_dec_pause_state_cg = pause_stall & _T_420; // @[el2_dec_decode_ctl.scala 506:25] + assign io_dec_div_active = _T_821; // @[el2_dec_decode_ctl.scala 739:21] + assign data_gated_cgc_io_clk = clock; // @[el2_dec_decode_ctl.scala 225:31] + assign data_gated_cgc_io_en = _T_15 | _T_16; // @[el2_dec_decode_ctl.scala 223:31] + assign data_gated_cgc_io_scan_mode = io_scan_mode; // @[el2_dec_decode_ctl.scala 224:31] + assign i0_dec_io_ins = io_dec_i0_instr_d; // @[el2_dec_decode_ctl.scala 397:16] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_428 | pause_stall; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = shift_illegal & _T_464; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_4_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_5_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_6_io_en = _T_704 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_7_io_en = _T_707 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_8_io_en = _T_710 | io_clk_override; // @[el2_lib.scala 521:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = i0_legal_decode_d & i0_dp_div; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = i0_pipe_en[3] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_13_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_14_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_15_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_16_io_en = i0_pipe_en[1] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_17_io_en = i0_pipe_en[0] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_18_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_18_io_en = i0_pipe_en[2] | io_clk_override; // @[el2_lib.scala 511:17] + assign rvclkhdr_18_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + tlu_wr_pause_r1 = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + tlu_wr_pause_r2 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + leak1_i1_stall = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + leak1_i0_stall = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + pause_stall = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + write_csr_data = _RAND_5[31:0]; + _RAND_6 = {1{`RANDOM}}; + postsync_stall = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + x_d_i0valid = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + flush_final_r = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + illegal_lockout = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + cam_raw_0_tag = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + cam_raw_0_valid = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + cam_raw_1_tag = _RAND_12[2:0]; + _RAND_13 = {1{`RANDOM}}; + cam_raw_1_valid = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + cam_raw_2_tag = _RAND_14[2:0]; + _RAND_15 = {1{`RANDOM}}; + cam_raw_2_valid = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + cam_raw_3_tag = _RAND_16[2:0]; + _RAND_17 = {1{`RANDOM}}; + cam_raw_3_valid = _RAND_17[0:0]; + _RAND_18 = {1{`RANDOM}}; + x_d_i0load = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + x_d_i0rd = _RAND_19[4:0]; + _RAND_20 = {1{`RANDOM}}; + _T_701 = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + nonblock_load_valid_m_delay = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + r_d_i0load = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + r_d_i0v = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + r_d_i0rd = _RAND_24[4:0]; + _RAND_25 = {1{`RANDOM}}; + cam_raw_0_rd = _RAND_25[4:0]; + _RAND_26 = {1{`RANDOM}}; + cam_raw_0_wb = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + cam_raw_1_rd = _RAND_27[4:0]; + _RAND_28 = {1{`RANDOM}}; + cam_raw_1_wb = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + cam_raw_2_rd = _RAND_29[4:0]; + _RAND_30 = {1{`RANDOM}}; + cam_raw_2_wb = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + cam_raw_3_rd = _RAND_31[4:0]; + _RAND_32 = {1{`RANDOM}}; + cam_raw_3_wb = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + lsu_idle = _RAND_33[0:0]; + _RAND_34 = {1{`RANDOM}}; + _T_339 = _RAND_34[0:0]; + _RAND_35 = {1{`RANDOM}}; + x_d_i0v = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + i0_x_c_load = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + i0_r_c_load = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + r_d_csrwen = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + r_d_i0valid = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + r_d_csrwaddr = _RAND_40[11:0]; + _RAND_41 = {1{`RANDOM}}; + csr_read_x = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + csr_clr_x = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + csr_set_x = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + csr_write_x = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + csr_imm_x = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + csrimm_x = _RAND_46[4:0]; + _RAND_47 = {1{`RANDOM}}; + csr_rddata_x = _RAND_47[31:0]; + _RAND_48 = {1{`RANDOM}}; + r_d_csrwonly = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + i0_result_r_raw = _RAND_49[31:0]; + _RAND_50 = {1{`RANDOM}}; + x_d_csrwonly = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + wbd_csrwonly = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_465 = _RAND_52[31:0]; + _RAND_53 = {1{`RANDOM}}; + x_t_legal = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + x_t_icaf = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + x_t_icaf_f1 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + x_t_icaf_type = _RAND_56[1:0]; + _RAND_57 = {1{`RANDOM}}; + x_t_fence_i = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + x_t_i0trigger = _RAND_58[3:0]; + _RAND_59 = {1{`RANDOM}}; + x_t_pmu_i0_itype = _RAND_59[3:0]; + _RAND_60 = {1{`RANDOM}}; + x_t_pmu_i0_br_unpred = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + r_t_legal = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + r_t_icaf = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + r_t_icaf_f1 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + r_t_icaf_type = _RAND_64[1:0]; + _RAND_65 = {1{`RANDOM}}; + r_t_fence_i = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + r_t_i0trigger = _RAND_66[3:0]; + _RAND_67 = {1{`RANDOM}}; + r_t_pmu_i0_itype = _RAND_67[3:0]; + _RAND_68 = {1{`RANDOM}}; + r_t_pmu_i0_br_unpred = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + lsu_trigger_match_r = _RAND_69[3:0]; + _RAND_70 = {1{`RANDOM}}; + lsu_pmu_misaligned_r = _RAND_70[0:0]; + _RAND_71 = {1{`RANDOM}}; + r_d_i0store = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + r_d_i0div = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + i0_x_c_mul = _RAND_73[0:0]; + _RAND_74 = {1{`RANDOM}}; + i0_x_c_alu = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + i0_r_c_mul = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + i0_r_c_alu = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + x_d_i0store = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + x_d_i0div = _RAND_78[0:0]; + _RAND_79 = {1{`RANDOM}}; + x_d_csrwen = _RAND_79[0:0]; + _RAND_80 = {1{`RANDOM}}; + x_d_csrwaddr = _RAND_80[11:0]; + _RAND_81 = {1{`RANDOM}}; + last_br_immed_x = _RAND_81[11:0]; + _RAND_82 = {1{`RANDOM}}; + _T_821 = _RAND_82[0:0]; + _RAND_83 = {1{`RANDOM}}; + _T_830 = _RAND_83[4:0]; + _RAND_84 = {1{`RANDOM}}; + i0_inst_x = _RAND_84[31:0]; + _RAND_85 = {1{`RANDOM}}; + i0_inst_r = _RAND_85[31:0]; + _RAND_86 = {1{`RANDOM}}; + i0_inst_wb = _RAND_86[31:0]; + _RAND_87 = {1{`RANDOM}}; + _T_837 = _RAND_87[31:0]; + _RAND_88 = {1{`RANDOM}}; + i0_pc_wb = _RAND_88[30:0]; + _RAND_89 = {1{`RANDOM}}; + _T_840 = _RAND_89[30:0]; + _RAND_90 = {1{`RANDOM}}; + dec_i0_pc_r = _RAND_90[30:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + tlu_wr_pause_r1 = 1'h0; + end + if (reset) begin + tlu_wr_pause_r2 = 1'h0; + end + if (reset) begin + leak1_i1_stall = 1'h0; + end + if (reset) begin + leak1_i0_stall = 1'h0; + end + if (reset) begin + pause_stall = 1'h0; + end + if (reset) begin + write_csr_data = 32'h0; + end + if (reset) begin + postsync_stall = 1'h0; + end + if (reset) begin + x_d_i0valid = 1'h0; + end + if (reset) begin + flush_final_r = 1'h0; + end + if (reset) begin + illegal_lockout = 1'h0; + end + if (reset) begin + cam_raw_0_tag = 3'h0; + end + if (reset) begin + cam_raw_0_valid = 1'h0; + end + if (reset) begin + cam_raw_1_tag = 3'h0; + end + if (reset) begin + cam_raw_1_valid = 1'h0; + end + if (reset) begin + cam_raw_2_tag = 3'h0; + end + if (reset) begin + cam_raw_2_valid = 1'h0; + end + if (reset) begin + cam_raw_3_tag = 3'h0; + end + if (reset) begin + cam_raw_3_valid = 1'h0; + end + if (reset) begin + x_d_i0load = 1'h0; + end + if (reset) begin + x_d_i0rd = 5'h0; + end + if (reset) begin + _T_701 = 3'h0; + end + if (reset) begin + nonblock_load_valid_m_delay = 1'h0; + end + if (reset) begin + r_d_i0load = 1'h0; + end + if (reset) begin + r_d_i0v = 1'h0; + end + if (reset) begin + r_d_i0rd = 5'h0; + end + if (reset) begin + cam_raw_0_rd = 5'h0; + end + if (reset) begin + cam_raw_0_wb = 1'h0; + end + if (reset) begin + cam_raw_1_rd = 5'h0; + end + if (reset) begin + cam_raw_1_wb = 1'h0; + end + if (reset) begin + cam_raw_2_rd = 5'h0; + end + if (reset) begin + cam_raw_2_wb = 1'h0; + end + if (reset) begin + cam_raw_3_rd = 5'h0; + end + if (reset) begin + cam_raw_3_wb = 1'h0; + end + if (reset) begin + lsu_idle = 1'h0; + end + if (reset) begin + _T_339 = 1'h0; + end + if (reset) begin + x_d_i0v = 1'h0; + end + if (reset) begin + r_d_csrwen = 1'h0; + end + if (reset) begin + r_d_i0valid = 1'h0; + end + if (reset) begin + r_d_csrwaddr = 12'h0; + end + if (reset) begin + csr_read_x = 1'h0; + end + if (reset) begin + csr_clr_x = 1'h0; + end + if (reset) begin + csr_set_x = 1'h0; + end + if (reset) begin + csr_write_x = 1'h0; + end + if (reset) begin + csr_imm_x = 1'h0; + end + if (reset) begin + csrimm_x = 5'h0; + end + if (reset) begin + csr_rddata_x = 32'h0; + end + if (reset) begin + r_d_csrwonly = 1'h0; + end + if (reset) begin + i0_result_r_raw = 32'h0; + end + if (reset) begin + x_d_csrwonly = 1'h0; + end + if (reset) begin + wbd_csrwonly = 1'h0; + end + if (reset) begin + _T_465 = 32'h0; + end + if (reset) begin + x_t_legal = 1'h0; + end + if (reset) begin + x_t_icaf = 1'h0; + end + if (reset) begin + x_t_icaf_f1 = 1'h0; + end + if (reset) begin + x_t_icaf_type = 2'h0; + end + if (reset) begin + x_t_fence_i = 1'h0; + end + if (reset) begin + x_t_i0trigger = 4'h0; + end + if (reset) begin + x_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + x_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + r_t_legal = 1'h0; + end + if (reset) begin + r_t_icaf = 1'h0; + end + if (reset) begin + r_t_icaf_f1 = 1'h0; + end + if (reset) begin + r_t_icaf_type = 2'h0; + end + if (reset) begin + r_t_fence_i = 1'h0; + end + if (reset) begin + r_t_i0trigger = 4'h0; + end + if (reset) begin + r_t_pmu_i0_itype = 4'h0; + end + if (reset) begin + r_t_pmu_i0_br_unpred = 1'h0; + end + if (reset) begin + lsu_trigger_match_r = 4'h0; + end + if (reset) begin + lsu_pmu_misaligned_r = 1'h0; + end + if (reset) begin + r_d_i0store = 1'h0; + end + if (reset) begin + r_d_i0div = 1'h0; + end + if (reset) begin + x_d_i0store = 1'h0; + end + if (reset) begin + x_d_i0div = 1'h0; + end + if (reset) begin + x_d_csrwen = 1'h0; + end + if (reset) begin + x_d_csrwaddr = 12'h0; + end + if (reset) begin + last_br_immed_x = 12'h0; + end + if (reset) begin + _T_821 = 1'h0; + end + if (reset) begin + _T_830 = 5'h0; + end + if (reset) begin + i0_inst_x = 32'h0; + end + if (reset) begin + i0_inst_r = 32'h0; + end + if (reset) begin + i0_inst_wb = 32'h0; + end + if (reset) begin + _T_837 = 32'h0; + end + if (reset) begin + i0_pc_wb = 31'h0; + end + if (reset) begin + _T_840 = 31'h0; + end + if (reset) begin + dec_i0_pc_r = 31'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_active_clk) begin + if (i0_x_ctl_en) begin + i0_x_c_load <= i0_d_c_load; + end + if (i0_r_ctl_en) begin + i0_r_c_load <= i0_x_c_load; + end + if (i0_x_ctl_en) begin + i0_x_c_mul <= i0_d_c_mul; + end + if (i0_x_ctl_en) begin + i0_x_c_alu <= i0_d_c_alu; + end + if (i0_r_ctl_en) begin + i0_r_c_mul <= i0_x_c_mul; + end + if (i0_r_ctl_en) begin + i0_r_c_alu <= i0_x_c_alu; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + tlu_wr_pause_r1 <= 1'h0; + end else begin + tlu_wr_pause_r1 <= io_dec_tlu_wr_pause_r; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + tlu_wr_pause_r2 <= 1'h0; + end else begin + tlu_wr_pause_r2 <= tlu_wr_pause_r1; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + leak1_i1_stall <= 1'h0; + end else begin + leak1_i1_stall <= io_dec_tlu_flush_leak_one_r | _T_280; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + leak1_i0_stall <= 1'h0; + end else begin + leak1_i0_stall <= _T_283 | _T_285; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + pause_stall <= 1'h0; + end else begin + pause_stall <= _T_412 & _T_413; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + write_csr_data <= 32'h0; + end else if (pause_stall) begin + write_csr_data <= _T_423; + end else if (io_dec_tlu_wr_pause_r) begin + write_csr_data <= io_dec_csr_wrdata_r; + end else begin + write_csr_data <= write_csr_data_x; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + postsync_stall <= 1'h0; + end else begin + postsync_stall <= _T_506 | _T_507; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0valid <= 1'h0; + end else begin + x_d_i0valid <= io_dec_i0_decode_d; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + flush_final_r <= 1'h0; + end else begin + flush_final_r <= io_exu_flush_final; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + illegal_lockout <= 1'h0; + end else begin + illegal_lockout <= _T_466 & _T_467; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_tag <= 3'h0; + end else if (cam_wen[0]) begin + cam_raw_0_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_106) begin + cam_raw_0_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_0_valid <= 1'h0; + end else begin + cam_raw_0_valid <= _GEN_56; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_tag <= 3'h0; + end else if (cam_wen[1]) begin + cam_raw_1_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_132) begin + cam_raw_1_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_1_valid <= 1'h0; + end else begin + cam_raw_1_valid <= _GEN_67; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_tag <= 3'h0; + end else if (cam_wen[2]) begin + cam_raw_2_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_158) begin + cam_raw_2_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_2_valid <= 1'h0; + end else begin + cam_raw_2_valid <= _GEN_78; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_tag <= 3'h0; + end else if (cam_wen[3]) begin + cam_raw_3_tag <= {{1'd0}, io_lsu_nonblock_load_tag_m}; + end else if (_T_184) begin + cam_raw_3_tag <= 3'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_valid <= 1'h0; + end else if (io_dec_tlu_force_halt) begin + cam_raw_3_valid <= 1'h0; + end else begin + cam_raw_3_valid <= _GEN_89; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0load <= 1'h0; + end else begin + x_d_i0load <= i0_dp_load & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0rd <= 5'h0; + end else begin + x_d_i0rd <= io_dec_i0_instr_d[11:7]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + _T_701 <= 3'h0; + end else begin + _T_701 <= i0_pipe_en[3:1]; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + nonblock_load_valid_m_delay <= 1'h0; + end else if (i0_r_ctl_en) begin + nonblock_load_valid_m_delay <= io_lsu_nonblock_load_valid_m; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0load <= 1'h0; + end else begin + r_d_i0load <= x_d_i0load; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0v <= 1'h0; + end else begin + r_d_i0v <= _T_733 & _T_279; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0rd <= 5'h0; + end else begin + r_d_i0rd <= x_d_i0rd; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_rd <= 5'h0; + end else if (cam_wen[0]) begin + if (x_d_i0load) begin + cam_raw_0_rd <= x_d_i0rd; + end else begin + cam_raw_0_rd <= 5'h0; + end + end else if (_T_106) begin + cam_raw_0_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_0_wb <= 1'h0; + end else begin + cam_raw_0_wb <= _T_111 | _GEN_57; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_rd <= 5'h0; + end else if (cam_wen[1]) begin + if (x_d_i0load) begin + cam_raw_1_rd <= x_d_i0rd; + end else begin + cam_raw_1_rd <= 5'h0; + end + end else if (_T_132) begin + cam_raw_1_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_1_wb <= 1'h0; + end else begin + cam_raw_1_wb <= _T_137 | _GEN_68; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_rd <= 5'h0; + end else if (cam_wen[2]) begin + if (x_d_i0load) begin + cam_raw_2_rd <= x_d_i0rd; + end else begin + cam_raw_2_rd <= 5'h0; + end + end else if (_T_158) begin + cam_raw_2_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_2_wb <= 1'h0; + end else begin + cam_raw_2_wb <= _T_163 | _GEN_79; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_rd <= 5'h0; + end else if (cam_wen[3]) begin + if (x_d_i0load) begin + cam_raw_3_rd <= x_d_i0rd; + end else begin + cam_raw_3_rd <= 5'h0; + end + end else if (_T_184) begin + cam_raw_3_rd <= 5'h0; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + cam_raw_3_wb <= 1'h0; + end else begin + cam_raw_3_wb <= _T_189 | _GEN_90; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + lsu_idle <= 1'h0; + end else begin + lsu_idle <= io_lsu_idle_any; + end + end + always @(posedge data_gated_cgc_io_l1clk or posedge reset) begin + if (reset) begin + _T_339 <= 1'h0; + end else begin + _T_339 <= io_dec_tlu_flush_extint; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0v <= 1'h0; + end else begin + x_d_i0v <= i0_rd_en_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwen <= 1'h0; + end else begin + r_d_csrwen <= x_d_csrwen; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0valid <= 1'h0; + end else begin + r_d_i0valid <= _T_737 & _T_279; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwaddr <= 12'h0; + end else begin + r_d_csrwaddr <= x_d_csrwaddr; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_read_x <= 1'h0; + end else begin + csr_read_x <= i0_dp_csr_read & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_clr_x <= 1'h0; + end else begin + csr_clr_x <= i0_dp_csr_clr & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_set_x <= 1'h0; + end else begin + csr_set_x <= i0_dp_csr_set & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_write_x <= 1'h0; + end else begin + csr_write_x <= i0_csr_write & i0_legal_decode_d; + end + end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + csr_imm_x <= 1'h0; + end else if (_T_40) begin + csr_imm_x <= 1'h0; + end else begin + csr_imm_x <= i0_dp_raw_csr_imm; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + csrimm_x <= 5'h0; + end else begin + csrimm_x <= io_dec_i0_instr_d[19:15]; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + csr_rddata_x <= 32'h0; + end else begin + csr_rddata_x <= io_dec_csr_rddata_d; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_csrwonly <= 1'h0; + end else begin + r_d_csrwonly <= x_d_csrwonly; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + i0_result_r_raw <= 32'h0; + end else if (_T_761) begin + i0_result_r_raw <= io_lsu_result_m; + end else begin + i0_result_r_raw <= io_exu_i0_result_x; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwonly <= 1'h0; + end else begin + x_d_csrwonly <= i0_csr_write_only_d & io_dec_i0_decode_d; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + wbd_csrwonly <= 1'h0; + end else begin + wbd_csrwonly <= r_d_csrwonly; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + _T_465 <= 32'h0; + end else if (io_dec_i0_pc4_d) begin + _T_465 <= io_dec_i0_instr_d; + end else begin + _T_465 <= _T_462; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_legal <= 1'h0; + end else begin + x_t_legal <= io_dec_i0_decode_d & i0_legal; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf <= 1'h0; + end else begin + x_t_icaf <= i0_icaf_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf_f1 <= 1'h0; + end else begin + x_t_icaf_f1 <= io_dec_i0_icaf_f1_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_icaf_type <= 2'h0; + end else begin + x_t_icaf_type <= io_dec_i0_icaf_type_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_fence_i <= 1'h0; + end else begin + x_t_fence_i <= _T_517 & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_i0trigger <= 4'h0; + end else begin + x_t_i0trigger <= io_dec_i0_trigger_match_d & _T_522; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_itype <= 4'h0; + end else begin + x_t_pmu_i0_itype <= _T_254 & _T_276; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + x_t_pmu_i0_br_unpred <= 1'h0; + end else begin + x_t_pmu_i0_br_unpred <= i0_dp_jal & _T_252; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_legal <= 1'h0; + end else begin + r_t_legal <= x_t_legal; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf <= 1'h0; + end else begin + r_t_icaf <= x_t_icaf; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf_f1 <= 1'h0; + end else begin + r_t_icaf_f1 <= x_t_icaf_f1; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_icaf_type <= 2'h0; + end else begin + r_t_icaf_type <= x_t_icaf_type; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_fence_i <= 1'h0; + end else begin + r_t_fence_i <= x_t_fence_i; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_i0trigger <= 4'h0; + end else begin + r_t_i0trigger <= x_t_i0trigger & _T_531; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_pmu_i0_itype <= 4'h0; + end else begin + r_t_pmu_i0_itype <= x_t_pmu_i0_itype; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + r_t_pmu_i0_br_unpred <= 1'h0; + end else begin + r_t_pmu_i0_br_unpred <= x_t_pmu_i0_br_unpred; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + lsu_trigger_match_r <= 4'h0; + end else begin + lsu_trigger_match_r <= io_lsu_trigger_match_m; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + lsu_pmu_misaligned_r <= 1'h0; + end else begin + lsu_pmu_misaligned_r <= io_lsu_pmu_misaligned_m; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0store <= 1'h0; + end else begin + r_d_i0store <= x_d_i0store; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + r_d_i0div <= 1'h0; + end else begin + r_d_i0div <= x_d_i0div; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0store <= 1'h0; + end else begin + x_d_i0store <= i0_dp_store & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_i0div <= 1'h0; + end else begin + x_d_i0div <= i0_dp_div & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwen <= 1'h0; + end else begin + x_d_csrwen <= io_dec_csr_wen_unq_d & i0_legal_decode_d; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + x_d_csrwaddr <= 12'h0; + end else begin + x_d_csrwaddr <= io_dec_i0_instr_d[31:20]; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + last_br_immed_x <= 12'h0; + end else if (io_i0_ap_predict_nt) begin + last_br_immed_x <= _T_781; + end else if (_T_314) begin + last_br_immed_x <= i0_pcall_imm[12:1]; + end else begin + last_br_immed_x <= _T_323; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_821 <= 1'h0; + end else begin + _T_821 <= i0_div_decode_d | _T_820; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + _T_830 <= 5'h0; + end else if (i0_div_decode_d) begin + _T_830 <= i0r_rd; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + i0_inst_x <= 32'h0; + end else if (io_dec_i0_pc4_d) begin + i0_inst_x <= io_dec_i0_instr_d; + end else begin + i0_inst_x <= _T_462; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + i0_inst_r <= 32'h0; + end else begin + i0_inst_r <= i0_inst_x; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + i0_inst_wb <= 32'h0; + end else begin + i0_inst_wb <= i0_inst_r; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + _T_837 <= 32'h0; + end else begin + _T_837 <= i0_inst_wb; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + i0_pc_wb <= 31'h0; + end else begin + i0_pc_wb <= io_dec_tlu_i0_pc_r; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + _T_840 <= 31'h0; + end else begin + _T_840 <= i0_pc_wb; + end + end + always @(posedge rvclkhdr_18_io_l1clk or posedge reset) begin + if (reset) begin + dec_i0_pc_r <= 31'h0; + end else begin + dec_i0_pc_r <= io_exu_i0_pc_x; + end + end +endmodule diff --git a/el2_exu.anno.json b/el2_exu.anno.json new file mode 100644 index 00000000..d4582f83 --- /dev/null +++ b/el2_exu.anno.json @@ -0,0 +1,135 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_div_wren", + "sources":[ + "~el2_exu|el2_exu>io_dec_div_cancel" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_mp_fghr", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_lsu_rs1_d", + "sources":[ + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_dec_extint_stall", + "~el2_exu|el2_exu>io_dec_tlu_meihap", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_flush_final", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r", + "~el2_exu|el2_exu>io_dec_i0_alu_decode_d", + "~el2_exu|el2_exu>io_i0_ap_jal", + "~el2_exu|el2_exu>io_i0_ap_predict_t", + "~el2_exu|el2_exu>io_i0_ap_predict_nt", + "~el2_exu|el2_exu>io_i0_ap_bge", + "~el2_exu|el2_exu>io_i0_ap_sub", + "~el2_exu|el2_exu>io_i0_ap_blt", + "~el2_exu|el2_exu>io_i0_ap_beq", + "~el2_exu|el2_exu>io_i0_ap_bne", + "~el2_exu|el2_exu>io_i0_ap_unsign", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_prett", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall", + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_immed_d", + "~el2_exu|el2_exu>io_dbg_cmd_wrdata", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_pc_d", + "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d", + "~el2_exu|el2_exu>io_dec_i0_select_pc_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_flush_path_final", + "sources":[ + "~el2_exu|el2_exu>io_dec_tlu_flush_path_r", + "~el2_exu|el2_exu>io_dec_tlu_flush_lower_r", + "~el2_exu|el2_exu>io_i0_ap_jal", + "~el2_exu|el2_exu>io_i0_ap_sub", + "~el2_exu|el2_exu>io_dec_i0_pc_d", + "~el2_exu|el2_exu>io_dec_i0_br_immed_d", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pret", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pja", + "~el2_exu|el2_exu>io_dec_i0_predict_p_d_pcall", + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_immed_d", + "~el2_exu|el2_exu>io_gpr_i0_rs1_d", + "~el2_exu|el2_exu>io_dbg_cmd_wrdata", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs1_en_d", + "~el2_exu|el2_exu>io_dec_debug_wdata_rs1_d", + "~el2_exu|el2_exu>io_dec_i0_select_pc_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_en_d", + "~el2_exu|el2_exu>io_dec_i0_rs1_bypass_data_d" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_exu|el2_exu>io_exu_lsu_rs2_d", + "sources":[ + "~el2_exu|el2_exu>io_gpr_i0_rs2_d", + "~el2_exu|el2_exu>io_dec_i0_rs2_en_d", + "~el2_exu|el2_exu>io_dec_extint_stall", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_data_d", + "~el2_exu|el2_exu>io_exu_i0_result_x", + "~el2_exu|el2_exu>io_dec_i0_rs2_bypass_en_d" + ] + }, + { + "class":"logger.LogLevelAnnotation", + "globalLogLevel":{ + + } + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_exu.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_exu|el2_exu>i0_rs2_d" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"el2_exu" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/el2_exu.fir b/el2_exu.fir new file mode 100644 index 00000000..dcc75ea0 --- /dev/null +++ b/el2_exu.fir @@ -0,0 +1,3671 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit el2_exu : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_12 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_12 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_13 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_13 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_alu_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} + + node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60] + inst rvclkhdr of rvclkhdr_18 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24] + reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1 <= io.pc_in @[el2_lib.scala 514:16] + io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12] + wire result : UInt<32> + result <= UInt<1>("h00") + node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62] + inst rvclkhdr_1 of rvclkhdr_19 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_3 <= result @[el2_lib.scala 514:16] + io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16] + node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29] + node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37] + node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17] + wire aout : UInt<33> + aout <= UInt<1>("h00") + node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25] + node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] + node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70] + node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58] + node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55] + node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55] + node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80] + node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80] + node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58] + node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58] + node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132] + node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132] + node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157] + node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157] + node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14] + aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8] + node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18] + node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22] + node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14] + node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32] + node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29] + node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27] + node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44] + node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37] + node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61] + node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71] + node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66] + node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83] + node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78] + node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76] + node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50] + node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50] + node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38] + node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29] + node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34] + node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30] + node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51] + node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44] + node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78] + node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76] + node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58] + node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29] + node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19] + node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50] + node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16] + node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50] + node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39] + node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39] + node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15] + node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50] + node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39] + node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39] + node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16] + node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50] + node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39] + node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39] + wire _T_58 : SInt<32> @[Mux.scala 27:72] + node _T_59 = asUInt(_T_45) @[Mux.scala 27:72] + node _T_60 = asSInt(_T_59) @[Mux.scala 27:72] + _T_58 <= _T_60 @[Mux.scala 27:72] + wire _T_61 : SInt<32> @[Mux.scala 27:72] + node _T_62 = asUInt(_T_49) @[Mux.scala 27:72] + node _T_63 = asSInt(_T_62) @[Mux.scala 27:72] + _T_61 <= _T_63 @[Mux.scala 27:72] + wire _T_64 : SInt<32> @[Mux.scala 27:72] + node _T_65 = asUInt(_T_53) @[Mux.scala 27:72] + node _T_66 = asSInt(_T_65) @[Mux.scala 27:72] + _T_64 <= _T_66 @[Mux.scala 27:72] + wire _T_67 : SInt<32> @[Mux.scala 27:72] + node _T_68 = asUInt(_T_57) @[Mux.scala 27:72] + node _T_69 = asSInt(_T_68) @[Mux.scala 27:72] + _T_67 <= _T_69 @[Mux.scala 27:72] + node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72] + node _T_75 = asSInt(_T_74) @[Mux.scala 27:72] + node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72] + node _T_77 = asSInt(_T_76) @[Mux.scala 27:72] + node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72] + node _T_79 = asSInt(_T_78) @[Mux.scala 27:72] + wire lout : SInt<32> @[Mux.scala 27:72] + node _T_80 = asUInt(_T_79) @[Mux.scala 27:72] + node _T_81 = asSInt(_T_80) @[Mux.scala 27:72] + lout <= _T_81 @[Mux.scala 27:72] + node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15] + node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60] + node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58] + node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38] + node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38] + node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15] + node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60] + node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58] + node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15] + node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60] + node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58] + node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72] + node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72] + wire shift_amount : UInt<6> @[Mux.scala 27:72] + shift_amount <= _T_97 @[Mux.scala 27:72] + wire shift_mask : UInt<32> + shift_mask <= UInt<1>("h00") + wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48] + _T_98[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[4] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58] + node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70] + node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61] + node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39] + shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14] + wire shift_extend : UInt<63> + shift_extend <= UInt<1>("h00") + wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_106[0] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[1] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[2] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[3] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[4] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[5] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[6] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[7] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[8] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[9] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[10] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[11] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[12] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[13] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[14] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[15] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[16] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[17] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[18] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[19] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[20] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[21] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[22] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[23] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[24] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[25] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[26] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[27] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[28] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[29] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[30] <= io.ap.sra @[el2_lib.scala 161:48] + node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] + node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58] + node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58] + node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58] + node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58] + node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] + node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61] + wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_138[0] <= _T_137 @[el2_lib.scala 161:48] + _T_138[1] <= _T_137 @[el2_lib.scala 161:48] + _T_138[2] <= _T_137 @[el2_lib.scala 161:48] + _T_138[3] <= _T_137 @[el2_lib.scala 161:48] + _T_138[4] <= _T_137 @[el2_lib.scala 161:48] + _T_138[5] <= _T_137 @[el2_lib.scala 161:48] + _T_138[6] <= _T_137 @[el2_lib.scala 161:48] + _T_138[7] <= _T_137 @[el2_lib.scala 161:48] + _T_138[8] <= _T_137 @[el2_lib.scala 161:48] + _T_138[9] <= _T_137 @[el2_lib.scala 161:48] + _T_138[10] <= _T_137 @[el2_lib.scala 161:48] + _T_138[11] <= _T_137 @[el2_lib.scala 161:48] + _T_138[12] <= _T_137 @[el2_lib.scala 161:48] + _T_138[13] <= _T_137 @[el2_lib.scala 161:48] + _T_138[14] <= _T_137 @[el2_lib.scala 161:48] + _T_138[15] <= _T_137 @[el2_lib.scala 161:48] + _T_138[16] <= _T_137 @[el2_lib.scala 161:48] + _T_138[17] <= _T_137 @[el2_lib.scala 161:48] + _T_138[18] <= _T_137 @[el2_lib.scala 161:48] + _T_138[19] <= _T_137 @[el2_lib.scala 161:48] + _T_138[20] <= _T_137 @[el2_lib.scala 161:48] + _T_138[21] <= _T_137 @[el2_lib.scala 161:48] + _T_138[22] <= _T_137 @[el2_lib.scala 161:48] + _T_138[23] <= _T_137 @[el2_lib.scala 161:48] + _T_138[24] <= _T_137 @[el2_lib.scala 161:48] + _T_138[25] <= _T_137 @[el2_lib.scala 161:48] + _T_138[26] <= _T_137 @[el2_lib.scala 161:48] + _T_138[27] <= _T_137 @[el2_lib.scala 161:48] + _T_138[28] <= _T_137 @[el2_lib.scala 161:48] + _T_138[29] <= _T_137 @[el2_lib.scala 161:48] + _T_138[30] <= _T_137 @[el2_lib.scala 161:48] + node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58] + node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58] + node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58] + node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58] + node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58] + node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58] + node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58] + node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58] + node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58] + node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58] + node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58] + node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58] + node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58] + node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58] + node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] + node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44] + wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_170[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[4] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[5] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[6] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[7] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[8] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[9] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[10] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[11] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[12] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[13] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[14] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[15] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[16] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[17] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[18] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[19] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[20] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[21] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[22] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[23] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[24] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[25] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[26] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[27] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[28] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[29] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[30] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] + node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] + node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] + node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58] + node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58] + node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58] + node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58] + node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58] + node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58] + node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58] + node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58] + node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58] + node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58] + node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58] + node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58] + node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58] + node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58] + node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58] + node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58] + node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58] + node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58] + node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99] + node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90] + node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68] + node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58] + shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16] + wire shift_long : UInt<63> + shift_long <= UInt<1>("h00") + node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47] + node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32] + shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14] + node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27] + node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46] + node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34] + node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41] + node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53] + node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41] + node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56] + node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54] + node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41] + node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58] + node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73] + node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47] + node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63] + node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32] + node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40] + node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24] + node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40] + node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31] + node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20] + node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27] + node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27] + node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20] + node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27] + node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27] + node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22] + node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] + node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] + node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] + node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:8] + node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:27] + node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:14] + node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:52] + node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:27] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:16] + node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:14] + node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:52] + node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72] + node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] + wire _T_247 : UInt<19> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:82] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24] + node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58] + node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31] + node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15] + node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41] + node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15] + node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41] + node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12] + node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21] + node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72] + node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72] + wire _T_267 : UInt<32> @[Mux.scala 27:72] + _T_267 <= _T_266 @[Mux.scala 27:72] + node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56] + result <= _T_268 @[el2_exu_alu_ctl.scala 88:16] + node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45] + node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20] + node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20] + node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40] + node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59] + node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46] + node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85] + node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72] + node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104] + node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91] + node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110] + node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42] + node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63] + node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61] + node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79] + node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77] + node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104] + node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123] + node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141] + node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139] + node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89] + io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26] + node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37] + node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49] + node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62] + node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28] + io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22] + node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47] + node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45] + node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82] + node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62] + node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70] + node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62] + node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44] + node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42] + node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60] + node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81] + node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97] + node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95] + node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119] + node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117] + io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26] + node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42] + node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60] + node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81] + node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97] + node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95] + node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117] + io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26] + wire newhist : UInt<2> + newhist <= UInt<1>("h00") + node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35] + node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55] + node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39] + node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77] + node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63] + node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81] + node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60] + node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20] + node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6] + node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26] + node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24] + node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58] + node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62] + node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42] + node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58] + newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14] + io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30] + node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33] + node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53] + node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51] + node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90] + node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71] + io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30] + io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30] + io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_mul_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip rs1_in : UInt<32>, flip rs2_in : UInt<32>, result_x : UInt<32>} + + wire rs1_ext_in : SInt<33> + rs1_ext_in <= asSInt(UInt<1>("h00")) + wire rs2_ext_in : SInt<33> + rs2_ext_in <= asSInt(UInt<1>("h00")) + wire rs1_x : SInt<33> + rs1_x <= asSInt(UInt<1>("h00")) + wire rs2_x : SInt<33> + rs2_x <= asSInt(UInt<1>("h00")) + wire prod_x : SInt<66> + prod_x <= asSInt(UInt<1>("h00")) + wire low_x : UInt<1> + low_x <= UInt<1>("h00") + node _T = bits(io.rs1_in, 31, 31) @[el2_exu_mul_ctl.scala 26:50] + node _T_1 = and(io.mul_p.rs1_sign, _T) @[el2_exu_mul_ctl.scala 26:39] + node _T_2 = cat(_T_1, io.rs1_in) @[Cat.scala 29:58] + node _T_3 = asSInt(_T_2) @[el2_exu_mul_ctl.scala 26:66] + rs1_ext_in <= _T_3 @[el2_exu_mul_ctl.scala 26:14] + node _T_4 = bits(io.rs2_in, 31, 31) @[el2_exu_mul_ctl.scala 27:50] + node _T_5 = and(io.mul_p.rs2_sign, _T_4) @[el2_exu_mul_ctl.scala 27:39] + node _T_6 = cat(_T_5, io.rs2_in) @[Cat.scala 29:58] + node _T_7 = asSInt(_T_6) @[el2_exu_mul_ctl.scala 27:66] + rs2_ext_in <= _T_7 @[el2_exu_mul_ctl.scala 27:14] + node _T_8 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 36:47] + inst rvclkhdr of rvclkhdr_20 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_8 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_9 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_9 <= io.mul_p.low @[el2_lib.scala 514:16] + low_x <= _T_9 @[el2_exu_mul_ctl.scala 36:9] + node _T_10 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 37:44] + inst rvclkhdr_1 of rvclkhdr_21 @[el2_lib.scala 528:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 530:18] + rvclkhdr_1.io.en <= _T_10 @[el2_lib.scala 531:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] + reg _T_11 : SInt, rvclkhdr_1.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] + _T_11 <= rs1_ext_in @[el2_lib.scala 534:16] + rs1_x <= _T_11 @[el2_exu_mul_ctl.scala 37:9] + node _T_12 = bits(io.mul_p.valid, 0, 0) @[el2_exu_mul_ctl.scala 38:45] + inst rvclkhdr_2 of rvclkhdr_22 @[el2_lib.scala 528:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 530:18] + rvclkhdr_2.io.en <= _T_12 @[el2_lib.scala 531:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 532:24] + reg _T_13 : SInt, rvclkhdr_2.io.l1clk with : (reset => (reset, asSInt(UInt<1>("h00")))) @[el2_lib.scala 534:16] + _T_13 <= rs2_ext_in @[el2_lib.scala 534:16] + rs2_x <= _T_13 @[el2_exu_mul_ctl.scala 38:9] + node _T_14 = mul(rs1_x, rs2_x) @[el2_exu_mul_ctl.scala 40:20] + prod_x <= _T_14 @[el2_exu_mul_ctl.scala 40:10] + node _T_15 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:36] + node _T_16 = eq(_T_15, UInt<1>("h00")) @[el2_exu_mul_ctl.scala 41:29] + node _T_17 = bits(prod_x, 63, 32) @[el2_exu_mul_ctl.scala 41:52] + node _T_18 = bits(low_x, 0, 0) @[el2_exu_mul_ctl.scala 41:67] + node _T_19 = bits(prod_x, 31, 0) @[el2_exu_mul_ctl.scala 41:83] + node _T_20 = mux(_T_16, _T_17, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_21 = mux(_T_18, _T_19, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_22 = or(_T_20, _T_21) @[Mux.scala 27:72] + wire _T_23 : UInt<32> @[Mux.scala 27:72] + _T_23 <= _T_22 @[Mux.scala 27:72] + io.result_x <= _T_23 @[el2_exu_mul_ctl.scala 41:15] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_exu_div_ctl : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dp : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, flip dividend : UInt<32>, flip divisor : UInt<32>, flip cancel : UInt<1>, out : UInt<32>, finish_dly : UInt<1>} + + wire run_state : UInt<1> + run_state <= UInt<1>("h00") + wire count : UInt<6> + count <= UInt<6>("h00") + wire m_ff : UInt<33> + m_ff <= UInt<33>("h00") + wire q_in : UInt<33> + q_in <= UInt<33>("h00") + wire q_ff : UInt<33> + q_ff <= UInt<33>("h00") + wire a_in : UInt<33> + a_in <= UInt<33>("h00") + wire a_ff : UInt<33> + a_ff <= UInt<33>("h00") + wire m_eff : UInt<33> + m_eff <= UInt<33>("h00") + wire dividend_neg_ff : UInt<1> + dividend_neg_ff <= UInt<1>("h00") + wire divisor_neg_ff : UInt<1> + divisor_neg_ff <= UInt<1>("h00") + wire dividend_comp : UInt<32> + dividend_comp <= UInt<32>("h00") + wire q_ff_comp : UInt<32> + q_ff_comp <= UInt<32>("h00") + wire a_ff_comp : UInt<32> + a_ff_comp <= UInt<32>("h00") + wire sign_ff : UInt<1> + sign_ff <= UInt<1>("h00") + wire rem_ff : UInt<1> + rem_ff <= UInt<1>("h00") + wire add : UInt<1> + add <= UInt<1>("h00") + wire a_eff : UInt<33> + a_eff <= UInt<33>("h00") + wire a_eff_shift : UInt<56> + a_eff_shift <= UInt<56>("h00") + wire rem_correct : UInt<1> + rem_correct <= UInt<1>("h00") + wire valid_ff_x : UInt<1> + valid_ff_x <= UInt<1>("h00") + wire finish_ff : UInt<1> + finish_ff <= UInt<1>("h00") + wire smallnum_case_ff : UInt<1> + smallnum_case_ff <= UInt<1>("h00") + wire smallnum_ff : UInt<4> + smallnum_ff <= UInt<4>("h00") + wire smallnum_case : UInt<1> + smallnum_case <= UInt<1>("h00") + wire count_in : UInt<6> + count_in <= UInt<6>("h00") + wire dividend_eff : UInt<32> + dividend_eff <= UInt<32>("h00") + wire a_shift : UInt<33> + a_shift <= UInt<33>("h00") + io.out <= UInt<1>("h00") @[el2_exu_div_ctl.scala 50:10] + io.finish_dly <= UInt<1>("h00") @[el2_exu_div_ctl.scala 51:17] + node _T = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 54:30] + node valid_x = and(valid_ff_x, _T) @[el2_exu_div_ctl.scala 54:28] + node _T_1 = bits(q_ff, 31, 4) @[el2_exu_div_ctl.scala 60:27] + node _T_2 = eq(_T_1, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:34] + node _T_3 = bits(m_ff, 31, 4) @[el2_exu_div_ctl.scala 60:50] + node _T_4 = eq(_T_3, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:57] + node _T_5 = and(_T_2, _T_4) @[el2_exu_div_ctl.scala 60:43] + node _T_6 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 60:73] + node _T_7 = neq(_T_6, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:80] + node _T_8 = and(_T_5, _T_7) @[el2_exu_div_ctl.scala 60:66] + node _T_9 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 60:91] + node _T_10 = and(_T_8, _T_9) @[el2_exu_div_ctl.scala 60:89] + node _T_11 = and(_T_10, valid_x) @[el2_exu_div_ctl.scala 60:99] + node _T_12 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 61:11] + node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:18] + node _T_14 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 61:34] + node _T_15 = neq(_T_14, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:41] + node _T_16 = and(_T_13, _T_15) @[el2_exu_div_ctl.scala 61:27] + node _T_17 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 61:52] + node _T_18 = and(_T_16, _T_17) @[el2_exu_div_ctl.scala 61:50] + node _T_19 = and(_T_18, valid_x) @[el2_exu_div_ctl.scala 61:60] + node _T_20 = or(_T_11, _T_19) @[el2_exu_div_ctl.scala 60:110] + smallnum_case <= _T_20 @[el2_exu_div_ctl.scala 60:17] + node _T_21 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_22 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_23 = eq(_T_22, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_24 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_26 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_27 = eq(_T_26, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_28 = and(_T_23, _T_25) @[el2_exu_div_ctl.scala 65:94] + node _T_29 = and(_T_28, _T_27) @[el2_exu_div_ctl.scala 65:94] + node _T_30 = and(_T_21, _T_29) @[el2_exu_div_ctl.scala 66:10] + node _T_31 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_32 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_34 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_36 = and(_T_33, _T_35) @[el2_exu_div_ctl.scala 65:94] + node _T_37 = and(_T_31, _T_36) @[el2_exu_div_ctl.scala 66:10] + node _T_38 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 72:37] + node _T_39 = eq(_T_38, UInt<1>("h00")) @[el2_exu_div_ctl.scala 72:32] + node _T_40 = and(_T_37, _T_39) @[el2_exu_div_ctl.scala 72:30] + node _T_41 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_42 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_43 = eq(_T_42, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_44 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_46 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_48 = and(_T_43, _T_45) @[el2_exu_div_ctl.scala 65:94] + node _T_49 = and(_T_48, _T_47) @[el2_exu_div_ctl.scala 65:94] + node _T_50 = and(_T_41, _T_49) @[el2_exu_div_ctl.scala 66:10] + node _T_51 = or(_T_40, _T_50) @[el2_exu_div_ctl.scala 72:41] + node _T_52 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_53 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_54 = and(_T_52, _T_53) @[el2_exu_div_ctl.scala 64:94] + node _T_55 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_57 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_58 = eq(_T_57, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_59 = and(_T_56, _T_58) @[el2_exu_div_ctl.scala 65:94] + node _T_60 = and(_T_54, _T_59) @[el2_exu_div_ctl.scala 66:10] + node _T_61 = or(_T_51, _T_60) @[el2_exu_div_ctl.scala 72:73] + node _T_62 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_63 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_65 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_66 = eq(_T_65, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_67 = and(_T_64, _T_66) @[el2_exu_div_ctl.scala 65:94] + node _T_68 = and(_T_62, _T_67) @[el2_exu_div_ctl.scala 66:10] + node _T_69 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:37] + node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:32] + node _T_71 = and(_T_68, _T_70) @[el2_exu_div_ctl.scala 74:30] + node _T_72 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_73 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_75 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_76 = eq(_T_75, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_77 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_78 = eq(_T_77, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_79 = and(_T_74, _T_76) @[el2_exu_div_ctl.scala 65:94] + node _T_80 = and(_T_79, _T_78) @[el2_exu_div_ctl.scala 65:94] + node _T_81 = and(_T_72, _T_80) @[el2_exu_div_ctl.scala 66:10] + node _T_82 = or(_T_71, _T_81) @[el2_exu_div_ctl.scala 74:41] + node _T_83 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_84 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_85 = eq(_T_84, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_86 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_87 = eq(_T_86, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_88 = and(_T_85, _T_87) @[el2_exu_div_ctl.scala 65:94] + node _T_89 = and(_T_83, _T_88) @[el2_exu_div_ctl.scala 66:10] + node _T_90 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 74:110] + node _T_91 = eq(_T_90, UInt<1>("h00")) @[el2_exu_div_ctl.scala 74:105] + node _T_92 = and(_T_89, _T_91) @[el2_exu_div_ctl.scala 74:103] + node _T_93 = or(_T_82, _T_92) @[el2_exu_div_ctl.scala 74:76] + node _T_94 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_95 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_96 = eq(_T_95, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_97 = and(_T_94, _T_96) @[el2_exu_div_ctl.scala 64:94] + node _T_98 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_99 = eq(_T_98, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_100 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_102 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_103 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_104 = and(_T_99, _T_101) @[el2_exu_div_ctl.scala 65:94] + node _T_105 = and(_T_104, _T_102) @[el2_exu_div_ctl.scala 65:94] + node _T_106 = and(_T_105, _T_103) @[el2_exu_div_ctl.scala 65:94] + node _T_107 = and(_T_97, _T_106) @[el2_exu_div_ctl.scala 66:10] + node _T_108 = or(_T_93, _T_107) @[el2_exu_div_ctl.scala 74:114] + node _T_109 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_110 = eq(_T_109, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_111 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_112 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_113 = and(_T_110, _T_111) @[el2_exu_div_ctl.scala 64:94] + node _T_114 = and(_T_113, _T_112) @[el2_exu_div_ctl.scala 64:94] + node _T_115 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_116 = eq(_T_115, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_117 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_119 = and(_T_116, _T_118) @[el2_exu_div_ctl.scala 65:94] + node _T_120 = and(_T_114, _T_119) @[el2_exu_div_ctl.scala 66:10] + node _T_121 = or(_T_108, _T_120) @[el2_exu_div_ctl.scala 75:43] + node _T_122 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_123 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_124 = and(_T_122, _T_123) @[el2_exu_div_ctl.scala 64:94] + node _T_125 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_126 = eq(_T_125, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_127 = and(_T_124, _T_126) @[el2_exu_div_ctl.scala 66:10] + node _T_128 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 75:111] + node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_exu_div_ctl.scala 75:106] + node _T_130 = and(_T_127, _T_129) @[el2_exu_div_ctl.scala 75:104] + node _T_131 = or(_T_121, _T_130) @[el2_exu_div_ctl.scala 75:78] + node _T_132 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_133 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_134 = and(_T_132, _T_133) @[el2_exu_div_ctl.scala 64:94] + node _T_135 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_136 = eq(_T_135, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_137 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_138 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_139 = eq(_T_138, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_140 = and(_T_136, _T_137) @[el2_exu_div_ctl.scala 65:94] + node _T_141 = and(_T_140, _T_139) @[el2_exu_div_ctl.scala 65:94] + node _T_142 = and(_T_134, _T_141) @[el2_exu_div_ctl.scala 66:10] + node _T_143 = or(_T_131, _T_142) @[el2_exu_div_ctl.scala 75:116] + node _T_144 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_145 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_146 = and(_T_144, _T_145) @[el2_exu_div_ctl.scala 64:94] + node _T_147 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_148 = eq(_T_147, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_149 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_150 = eq(_T_149, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_151 = and(_T_148, _T_150) @[el2_exu_div_ctl.scala 65:94] + node _T_152 = and(_T_146, _T_151) @[el2_exu_div_ctl.scala 66:10] + node _T_153 = or(_T_143, _T_152) @[el2_exu_div_ctl.scala 76:43] + node _T_154 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_155 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_156 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_157 = and(_T_154, _T_155) @[el2_exu_div_ctl.scala 64:94] + node _T_158 = and(_T_157, _T_156) @[el2_exu_div_ctl.scala 64:94] + node _T_159 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_160 = eq(_T_159, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_161 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_162 = and(_T_160, _T_161) @[el2_exu_div_ctl.scala 65:94] + node _T_163 = and(_T_158, _T_162) @[el2_exu_div_ctl.scala 66:10] + node _T_164 = or(_T_153, _T_163) @[el2_exu_div_ctl.scala 76:77] + node _T_165 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_166 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_167 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_168 = and(_T_165, _T_166) @[el2_exu_div_ctl.scala 64:94] + node _T_169 = and(_T_168, _T_167) @[el2_exu_div_ctl.scala 64:94] + node _T_170 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_172 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_173 = eq(_T_172, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_174 = and(_T_171, _T_173) @[el2_exu_div_ctl.scala 65:94] + node _T_175 = and(_T_169, _T_174) @[el2_exu_div_ctl.scala 66:10] + node _T_176 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_177 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_178 = eq(_T_177, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_179 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_180 = and(_T_176, _T_178) @[el2_exu_div_ctl.scala 64:94] + node _T_181 = and(_T_180, _T_179) @[el2_exu_div_ctl.scala 64:94] + node _T_182 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_183 = eq(_T_182, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_184 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_185 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_186 = and(_T_183, _T_184) @[el2_exu_div_ctl.scala 65:94] + node _T_187 = and(_T_186, _T_185) @[el2_exu_div_ctl.scala 65:94] + node _T_188 = and(_T_181, _T_187) @[el2_exu_div_ctl.scala 66:10] + node _T_189 = or(_T_175, _T_188) @[el2_exu_div_ctl.scala 78:44] + node _T_190 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_191 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_192 = eq(_T_191, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_193 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_194 = eq(_T_193, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_195 = and(_T_192, _T_194) @[el2_exu_div_ctl.scala 65:94] + node _T_196 = and(_T_190, _T_195) @[el2_exu_div_ctl.scala 66:10] + node _T_197 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 78:118] + node _T_198 = eq(_T_197, UInt<1>("h00")) @[el2_exu_div_ctl.scala 78:113] + node _T_199 = and(_T_196, _T_198) @[el2_exu_div_ctl.scala 78:111] + node _T_200 = or(_T_189, _T_199) @[el2_exu_div_ctl.scala 78:84] + node _T_201 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_202 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_203 = eq(_T_202, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_204 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_205 = eq(_T_204, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_206 = and(_T_203, _T_205) @[el2_exu_div_ctl.scala 65:94] + node _T_207 = and(_T_201, _T_206) @[el2_exu_div_ctl.scala 66:10] + node _T_208 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 79:39] + node _T_209 = eq(_T_208, UInt<1>("h00")) @[el2_exu_div_ctl.scala 79:34] + node _T_210 = and(_T_207, _T_209) @[el2_exu_div_ctl.scala 79:32] + node _T_211 = or(_T_200, _T_210) @[el2_exu_div_ctl.scala 78:126] + node _T_212 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_213 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_214 = eq(_T_213, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_215 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_216 = eq(_T_215, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_217 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_218 = eq(_T_217, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_219 = and(_T_214, _T_216) @[el2_exu_div_ctl.scala 65:94] + node _T_220 = and(_T_219, _T_218) @[el2_exu_div_ctl.scala 65:94] + node _T_221 = and(_T_212, _T_220) @[el2_exu_div_ctl.scala 66:10] + node _T_222 = or(_T_211, _T_221) @[el2_exu_div_ctl.scala 79:46] + node _T_223 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_224 = eq(_T_223, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_225 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_226 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_227 = eq(_T_226, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_228 = and(_T_224, _T_225) @[el2_exu_div_ctl.scala 64:94] + node _T_229 = and(_T_228, _T_227) @[el2_exu_div_ctl.scala 64:94] + node _T_230 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_231 = eq(_T_230, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_232 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_234 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_235 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_236 = and(_T_231, _T_233) @[el2_exu_div_ctl.scala 65:94] + node _T_237 = and(_T_236, _T_234) @[el2_exu_div_ctl.scala 65:94] + node _T_238 = and(_T_237, _T_235) @[el2_exu_div_ctl.scala 65:94] + node _T_239 = and(_T_229, _T_238) @[el2_exu_div_ctl.scala 66:10] + node _T_240 = or(_T_222, _T_239) @[el2_exu_div_ctl.scala 79:86] + node _T_241 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_242 = eq(_T_241, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_243 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_244 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_245 = and(_T_242, _T_243) @[el2_exu_div_ctl.scala 64:94] + node _T_246 = and(_T_245, _T_244) @[el2_exu_div_ctl.scala 64:94] + node _T_247 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_248 = eq(_T_247, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_249 = and(_T_246, _T_248) @[el2_exu_div_ctl.scala 66:10] + node _T_250 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:42] + node _T_251 = eq(_T_250, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:37] + node _T_252 = and(_T_249, _T_251) @[el2_exu_div_ctl.scala 80:35] + node _T_253 = or(_T_240, _T_252) @[el2_exu_div_ctl.scala 79:128] + node _T_254 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_255 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_256 = eq(_T_255, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_257 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_258 = eq(_T_257, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_259 = and(_T_256, _T_258) @[el2_exu_div_ctl.scala 65:94] + node _T_260 = and(_T_254, _T_259) @[el2_exu_div_ctl.scala 66:10] + node _T_261 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 80:81] + node _T_262 = eq(_T_261, UInt<1>("h00")) @[el2_exu_div_ctl.scala 80:76] + node _T_263 = and(_T_260, _T_262) @[el2_exu_div_ctl.scala 80:74] + node _T_264 = or(_T_253, _T_263) @[el2_exu_div_ctl.scala 80:46] + node _T_265 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_266 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_267 = eq(_T_266, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_268 = and(_T_265, _T_267) @[el2_exu_div_ctl.scala 64:94] + node _T_269 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_270 = eq(_T_269, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_271 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_272 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_273 = and(_T_270, _T_271) @[el2_exu_div_ctl.scala 65:94] + node _T_274 = and(_T_273, _T_272) @[el2_exu_div_ctl.scala 65:94] + node _T_275 = and(_T_268, _T_274) @[el2_exu_div_ctl.scala 66:10] + node _T_276 = or(_T_264, _T_275) @[el2_exu_div_ctl.scala 80:86] + node _T_277 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_278 = eq(_T_277, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_279 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_280 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_281 = and(_T_278, _T_279) @[el2_exu_div_ctl.scala 64:94] + node _T_282 = and(_T_281, _T_280) @[el2_exu_div_ctl.scala 64:94] + node _T_283 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_285 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_286 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_288 = and(_T_284, _T_285) @[el2_exu_div_ctl.scala 65:94] + node _T_289 = and(_T_288, _T_287) @[el2_exu_div_ctl.scala 65:94] + node _T_290 = and(_T_282, _T_289) @[el2_exu_div_ctl.scala 66:10] + node _T_291 = or(_T_276, _T_290) @[el2_exu_div_ctl.scala 80:128] + node _T_292 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_293 = eq(_T_292, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_294 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_295 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_296 = and(_T_293, _T_294) @[el2_exu_div_ctl.scala 64:94] + node _T_297 = and(_T_296, _T_295) @[el2_exu_div_ctl.scala 64:94] + node _T_298 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_299 = eq(_T_298, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_300 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_302 = and(_T_299, _T_301) @[el2_exu_div_ctl.scala 65:94] + node _T_303 = and(_T_297, _T_302) @[el2_exu_div_ctl.scala 66:10] + node _T_304 = or(_T_291, _T_303) @[el2_exu_div_ctl.scala 81:46] + node _T_305 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_306 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_308 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_309 = eq(_T_308, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_310 = and(_T_305, _T_307) @[el2_exu_div_ctl.scala 64:94] + node _T_311 = and(_T_310, _T_309) @[el2_exu_div_ctl.scala 64:94] + node _T_312 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_313 = eq(_T_312, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_314 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_315 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_316 = and(_T_313, _T_314) @[el2_exu_div_ctl.scala 65:94] + node _T_317 = and(_T_316, _T_315) @[el2_exu_div_ctl.scala 65:94] + node _T_318 = and(_T_311, _T_317) @[el2_exu_div_ctl.scala 66:10] + node _T_319 = or(_T_304, _T_318) @[el2_exu_div_ctl.scala 81:86] + node _T_320 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_321 = eq(_T_320, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_322 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_323 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_324 = and(_T_321, _T_322) @[el2_exu_div_ctl.scala 64:94] + node _T_325 = and(_T_324, _T_323) @[el2_exu_div_ctl.scala 64:94] + node _T_326 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_328 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_329 = eq(_T_328, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_330 = and(_T_327, _T_329) @[el2_exu_div_ctl.scala 65:94] + node _T_331 = and(_T_325, _T_330) @[el2_exu_div_ctl.scala 66:10] + node _T_332 = or(_T_319, _T_331) @[el2_exu_div_ctl.scala 81:128] + node _T_333 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_334 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_335 = and(_T_333, _T_334) @[el2_exu_div_ctl.scala 64:94] + node _T_336 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_337 = eq(_T_336, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_338 = and(_T_335, _T_337) @[el2_exu_div_ctl.scala 66:10] + node _T_339 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 82:80] + node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_exu_div_ctl.scala 82:75] + node _T_341 = and(_T_338, _T_340) @[el2_exu_div_ctl.scala 82:73] + node _T_342 = or(_T_332, _T_341) @[el2_exu_div_ctl.scala 82:46] + node _T_343 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:74] + node _T_344 = eq(_T_343, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_345 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_346 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_347 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_348 = and(_T_344, _T_345) @[el2_exu_div_ctl.scala 64:94] + node _T_349 = and(_T_348, _T_346) @[el2_exu_div_ctl.scala 64:94] + node _T_350 = and(_T_349, _T_347) @[el2_exu_div_ctl.scala 64:94] + node _T_351 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_352 = eq(_T_351, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_353 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_354 = and(_T_352, _T_353) @[el2_exu_div_ctl.scala 65:94] + node _T_355 = and(_T_350, _T_354) @[el2_exu_div_ctl.scala 66:10] + node _T_356 = or(_T_342, _T_355) @[el2_exu_div_ctl.scala 82:86] + node _T_357 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_358 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_359 = and(_T_357, _T_358) @[el2_exu_div_ctl.scala 64:94] + node _T_360 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_361 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_363 = and(_T_360, _T_362) @[el2_exu_div_ctl.scala 65:94] + node _T_364 = and(_T_359, _T_363) @[el2_exu_div_ctl.scala 66:10] + node _T_365 = or(_T_356, _T_364) @[el2_exu_div_ctl.scala 82:128] + node _T_366 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_367 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_368 = and(_T_366, _T_367) @[el2_exu_div_ctl.scala 64:94] + node _T_369 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_370 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_372 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_374 = and(_T_369, _T_371) @[el2_exu_div_ctl.scala 65:94] + node _T_375 = and(_T_374, _T_373) @[el2_exu_div_ctl.scala 65:94] + node _T_376 = and(_T_368, _T_375) @[el2_exu_div_ctl.scala 66:10] + node _T_377 = or(_T_365, _T_376) @[el2_exu_div_ctl.scala 83:46] + node _T_378 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_379 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_380 = and(_T_378, _T_379) @[el2_exu_div_ctl.scala 64:94] + node _T_381 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_382 = eq(_T_381, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_383 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_385 = and(_T_382, _T_384) @[el2_exu_div_ctl.scala 65:94] + node _T_386 = and(_T_380, _T_385) @[el2_exu_div_ctl.scala 66:10] + node _T_387 = or(_T_377, _T_386) @[el2_exu_div_ctl.scala 83:86] + node _T_388 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_389 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:74] + node _T_390 = eq(_T_389, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_391 = and(_T_388, _T_390) @[el2_exu_div_ctl.scala 64:94] + node _T_392 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_393 = eq(_T_392, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_394 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:57] + node _T_395 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_396 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 65:57] + node _T_397 = and(_T_393, _T_394) @[el2_exu_div_ctl.scala 65:94] + node _T_398 = and(_T_397, _T_395) @[el2_exu_div_ctl.scala 65:94] + node _T_399 = and(_T_398, _T_396) @[el2_exu_div_ctl.scala 65:94] + node _T_400 = and(_T_391, _T_399) @[el2_exu_div_ctl.scala 66:10] + node _T_401 = or(_T_387, _T_400) @[el2_exu_div_ctl.scala 83:128] + node _T_402 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_403 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_404 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_405 = and(_T_402, _T_403) @[el2_exu_div_ctl.scala 64:94] + node _T_406 = and(_T_405, _T_404) @[el2_exu_div_ctl.scala 64:94] + node _T_407 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_408 = and(_T_406, _T_407) @[el2_exu_div_ctl.scala 66:10] + node _T_409 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 84:82] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_exu_div_ctl.scala 84:77] + node _T_411 = and(_T_408, _T_410) @[el2_exu_div_ctl.scala 84:75] + node _T_412 = or(_T_401, _T_411) @[el2_exu_div_ctl.scala 84:46] + node _T_413 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_414 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_415 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_416 = and(_T_413, _T_414) @[el2_exu_div_ctl.scala 64:94] + node _T_417 = and(_T_416, _T_415) @[el2_exu_div_ctl.scala 64:94] + node _T_418 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_419 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_421 = and(_T_418, _T_420) @[el2_exu_div_ctl.scala 65:94] + node _T_422 = and(_T_417, _T_421) @[el2_exu_div_ctl.scala 66:10] + node _T_423 = or(_T_412, _T_422) @[el2_exu_div_ctl.scala 84:86] + node _T_424 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_425 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_426 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_427 = and(_T_424, _T_425) @[el2_exu_div_ctl.scala 64:94] + node _T_428 = and(_T_427, _T_426) @[el2_exu_div_ctl.scala 64:94] + node _T_429 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_430 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:74] + node _T_431 = eq(_T_430, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_432 = and(_T_429, _T_431) @[el2_exu_div_ctl.scala 65:94] + node _T_433 = and(_T_428, _T_432) @[el2_exu_div_ctl.scala 66:10] + node _T_434 = or(_T_423, _T_433) @[el2_exu_div_ctl.scala 84:128] + node _T_435 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_436 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:74] + node _T_437 = eq(_T_436, UInt<1>("h00")) @[el2_exu_div_ctl.scala 64:69] + node _T_438 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_439 = and(_T_435, _T_437) @[el2_exu_div_ctl.scala 64:94] + node _T_440 = and(_T_439, _T_438) @[el2_exu_div_ctl.scala 64:94] + node _T_441 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:74] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_443 = bits(m_ff, 1, 1) @[el2_exu_div_ctl.scala 65:57] + node _T_444 = and(_T_442, _T_443) @[el2_exu_div_ctl.scala 65:94] + node _T_445 = and(_T_440, _T_444) @[el2_exu_div_ctl.scala 66:10] + node _T_446 = or(_T_434, _T_445) @[el2_exu_div_ctl.scala 85:46] + node _T_447 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_448 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_449 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_450 = and(_T_447, _T_448) @[el2_exu_div_ctl.scala 64:94] + node _T_451 = and(_T_450, _T_449) @[el2_exu_div_ctl.scala 64:94] + node _T_452 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_453 = eq(_T_452, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_454 = and(_T_451, _T_453) @[el2_exu_div_ctl.scala 66:10] + node _T_455 = or(_T_446, _T_454) @[el2_exu_div_ctl.scala 85:86] + node _T_456 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_457 = bits(q_ff, 2, 2) @[el2_exu_div_ctl.scala 64:57] + node _T_458 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_459 = bits(q_ff, 0, 0) @[el2_exu_div_ctl.scala 64:57] + node _T_460 = and(_T_456, _T_457) @[el2_exu_div_ctl.scala 64:94] + node _T_461 = and(_T_460, _T_458) @[el2_exu_div_ctl.scala 64:94] + node _T_462 = and(_T_461, _T_459) @[el2_exu_div_ctl.scala 64:94] + node _T_463 = bits(m_ff, 3, 3) @[el2_exu_div_ctl.scala 65:57] + node _T_464 = and(_T_462, _T_463) @[el2_exu_div_ctl.scala 66:10] + node _T_465 = or(_T_455, _T_464) @[el2_exu_div_ctl.scala 85:128] + node _T_466 = bits(q_ff, 3, 3) @[el2_exu_div_ctl.scala 64:57] + node _T_467 = bits(q_ff, 1, 1) @[el2_exu_div_ctl.scala 64:57] + node _T_468 = and(_T_466, _T_467) @[el2_exu_div_ctl.scala 64:94] + node _T_469 = bits(m_ff, 2, 2) @[el2_exu_div_ctl.scala 65:74] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_exu_div_ctl.scala 65:69] + node _T_471 = and(_T_468, _T_470) @[el2_exu_div_ctl.scala 66:10] + node _T_472 = bits(m_ff, 0, 0) @[el2_exu_div_ctl.scala 86:79] + node _T_473 = eq(_T_472, UInt<1>("h00")) @[el2_exu_div_ctl.scala 86:74] + node _T_474 = and(_T_471, _T_473) @[el2_exu_div_ctl.scala 86:72] + node _T_475 = or(_T_465, _T_474) @[el2_exu_div_ctl.scala 86:46] + node _T_476 = cat(_T_164, _T_475) @[Cat.scala 29:58] + node _T_477 = cat(_T_30, _T_61) @[Cat.scala 29:58] + node smallnum = cat(_T_477, _T_476) @[Cat.scala 29:58] + wire shortq_enable_ff : UInt<1> + shortq_enable_ff <= UInt<1>("h00") + wire short_dividend : UInt<33> + short_dividend <= UInt<33>("h00") + wire shortq_shift_xx : UInt<4> + shortq_shift_xx <= UInt<4>("h00") + node _T_478 = bits(q_ff, 31, 31) @[el2_exu_div_ctl.scala 96:40] + node _T_479 = and(sign_ff, _T_478) @[el2_exu_div_ctl.scala 96:34] + node _T_480 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 96:49] + node _T_481 = cat(_T_479, _T_480) @[Cat.scala 29:58] + short_dividend <= _T_481 @[el2_exu_div_ctl.scala 96:18] + node _T_482 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 101:22] + node _T_483 = bits(_T_482, 0, 0) @[el2_exu_div_ctl.scala 101:27] + node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_exu_div_ctl.scala 101:7] + node _T_485 = bits(short_dividend, 31, 24) @[el2_exu_div_ctl.scala 101:52] + node _T_486 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_487 = neq(_T_485, _T_486) @[el2_exu_div_ctl.scala 101:60] + node _T_488 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 102:21] + node _T_489 = bits(_T_488, 0, 0) @[el2_exu_div_ctl.scala 102:26] + node _T_490 = bits(short_dividend, 31, 23) @[el2_exu_div_ctl.scala 102:51] + node _T_491 = mux(UInt<1>("h01"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_492 = neq(_T_490, _T_491) @[el2_exu_div_ctl.scala 102:59] + node _T_493 = mux(_T_484, _T_487, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_494 = mux(_T_489, _T_492, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_495 = or(_T_493, _T_494) @[Mux.scala 27:72] + wire _T_496 : UInt<1> @[Mux.scala 27:72] + _T_496 <= _T_495 @[Mux.scala 27:72] + node _T_497 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 105:22] + node _T_498 = bits(_T_497, 0, 0) @[el2_exu_div_ctl.scala 105:27] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_exu_div_ctl.scala 105:7] + node _T_500 = bits(short_dividend, 23, 16) @[el2_exu_div_ctl.scala 105:52] + node _T_501 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_502 = neq(_T_500, _T_501) @[el2_exu_div_ctl.scala 105:60] + node _T_503 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 106:21] + node _T_504 = bits(_T_503, 0, 0) @[el2_exu_div_ctl.scala 106:26] + node _T_505 = bits(short_dividend, 22, 15) @[el2_exu_div_ctl.scala 106:51] + node _T_506 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_507 = neq(_T_505, _T_506) @[el2_exu_div_ctl.scala 106:59] + node _T_508 = mux(_T_499, _T_502, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_509 = mux(_T_504, _T_507, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_510 = or(_T_508, _T_509) @[Mux.scala 27:72] + wire _T_511 : UInt<1> @[Mux.scala 27:72] + _T_511 <= _T_510 @[Mux.scala 27:72] + node _T_512 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 109:22] + node _T_513 = bits(_T_512, 0, 0) @[el2_exu_div_ctl.scala 109:27] + node _T_514 = eq(_T_513, UInt<1>("h00")) @[el2_exu_div_ctl.scala 109:7] + node _T_515 = bits(short_dividend, 15, 8) @[el2_exu_div_ctl.scala 109:52] + node _T_516 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_517 = neq(_T_515, _T_516) @[el2_exu_div_ctl.scala 109:59] + node _T_518 = bits(short_dividend, 32, 32) @[el2_exu_div_ctl.scala 110:21] + node _T_519 = bits(_T_518, 0, 0) @[el2_exu_div_ctl.scala 110:26] + node _T_520 = bits(short_dividend, 14, 7) @[el2_exu_div_ctl.scala 110:51] + node _T_521 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_522 = neq(_T_520, _T_521) @[el2_exu_div_ctl.scala 110:58] + node _T_523 = mux(_T_514, _T_517, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_524 = mux(_T_519, _T_522, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_525 = or(_T_523, _T_524) @[Mux.scala 27:72] + wire _T_526 : UInt<1> @[Mux.scala 27:72] + _T_526 <= _T_525 @[Mux.scala 27:72] + node _T_527 = cat(_T_496, _T_511) @[Cat.scala 29:58] + node a_cls = cat(_T_527, _T_526) @[Cat.scala 29:58] + node _T_528 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 115:12] + node _T_529 = bits(_T_528, 0, 0) @[el2_exu_div_ctl.scala 115:17] + node _T_530 = eq(_T_529, UInt<1>("h00")) @[el2_exu_div_ctl.scala 115:7] + node _T_531 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 115:32] + node _T_532 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_533 = neq(_T_531, _T_532) @[el2_exu_div_ctl.scala 115:40] + node _T_534 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 116:11] + node _T_535 = bits(_T_534, 0, 0) @[el2_exu_div_ctl.scala 116:16] + node _T_536 = bits(m_ff, 31, 24) @[el2_exu_div_ctl.scala 116:31] + node _T_537 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_538 = neq(_T_536, _T_537) @[el2_exu_div_ctl.scala 116:39] + node _T_539 = mux(_T_530, _T_533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_540 = mux(_T_535, _T_538, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_541 = or(_T_539, _T_540) @[Mux.scala 27:72] + wire _T_542 : UInt<1> @[Mux.scala 27:72] + _T_542 <= _T_541 @[Mux.scala 27:72] + node _T_543 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 119:12] + node _T_544 = bits(_T_543, 0, 0) @[el2_exu_div_ctl.scala 119:17] + node _T_545 = eq(_T_544, UInt<1>("h00")) @[el2_exu_div_ctl.scala 119:7] + node _T_546 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 119:32] + node _T_547 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = neq(_T_546, _T_547) @[el2_exu_div_ctl.scala 119:40] + node _T_549 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 120:11] + node _T_550 = bits(_T_549, 0, 0) @[el2_exu_div_ctl.scala 120:16] + node _T_551 = bits(m_ff, 23, 16) @[el2_exu_div_ctl.scala 120:31] + node _T_552 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_553 = neq(_T_551, _T_552) @[el2_exu_div_ctl.scala 120:39] + node _T_554 = mux(_T_545, _T_548, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_555 = mux(_T_550, _T_553, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_556 = or(_T_554, _T_555) @[Mux.scala 27:72] + wire _T_557 : UInt<1> @[Mux.scala 27:72] + _T_557 <= _T_556 @[Mux.scala 27:72] + node _T_558 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 123:12] + node _T_559 = bits(_T_558, 0, 0) @[el2_exu_div_ctl.scala 123:17] + node _T_560 = eq(_T_559, UInt<1>("h00")) @[el2_exu_div_ctl.scala 123:7] + node _T_561 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 123:32] + node _T_562 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_563 = neq(_T_561, _T_562) @[el2_exu_div_ctl.scala 123:39] + node _T_564 = bits(m_ff, 32, 32) @[el2_exu_div_ctl.scala 124:11] + node _T_565 = bits(_T_564, 0, 0) @[el2_exu_div_ctl.scala 124:16] + node _T_566 = bits(m_ff, 15, 8) @[el2_exu_div_ctl.scala 124:31] + node _T_567 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_568 = neq(_T_566, _T_567) @[el2_exu_div_ctl.scala 124:38] + node _T_569 = mux(_T_560, _T_563, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_570 = mux(_T_565, _T_568, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_571 = or(_T_569, _T_570) @[Mux.scala 27:72] + wire _T_572 : UInt<1> @[Mux.scala 27:72] + _T_572 <= _T_571 @[Mux.scala 27:72] + node _T_573 = cat(_T_542, _T_557) @[Cat.scala 29:58] + node b_cls = cat(_T_573, _T_572) @[Cat.scala 29:58] + node _T_574 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 128:13] + node _T_575 = eq(_T_574, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:19] + node _T_576 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 128:42] + node _T_577 = eq(_T_576, UInt<1>("h01")) @[el2_exu_div_ctl.scala 128:48] + node _T_578 = and(_T_575, _T_577) @[el2_exu_div_ctl.scala 128:34] + node _T_579 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 129:15] + node _T_580 = eq(_T_579, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:21] + node _T_581 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 129:44] + node _T_582 = eq(_T_581, UInt<1>("h01")) @[el2_exu_div_ctl.scala 129:50] + node _T_583 = and(_T_580, _T_582) @[el2_exu_div_ctl.scala 129:36] + node _T_584 = or(_T_578, _T_583) @[el2_exu_div_ctl.scala 128:65] + node _T_585 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 130:15] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[el2_exu_div_ctl.scala 130:21] + node _T_587 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 130:44] + node _T_588 = eq(_T_587, UInt<1>("h01")) @[el2_exu_div_ctl.scala 130:50] + node _T_589 = and(_T_586, _T_588) @[el2_exu_div_ctl.scala 130:36] + node _T_590 = or(_T_584, _T_589) @[el2_exu_div_ctl.scala 129:67] + node _T_591 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 131:15] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:21] + node _T_593 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 131:44] + node _T_594 = eq(_T_593, UInt<1>("h01")) @[el2_exu_div_ctl.scala 131:50] + node _T_595 = and(_T_592, _T_594) @[el2_exu_div_ctl.scala 131:36] + node _T_596 = or(_T_590, _T_595) @[el2_exu_div_ctl.scala 130:67] + node _T_597 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 132:15] + node _T_598 = eq(_T_597, UInt<1>("h00")) @[el2_exu_div_ctl.scala 132:21] + node _T_599 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 132:44] + node _T_600 = eq(_T_599, UInt<1>("h01")) @[el2_exu_div_ctl.scala 132:50] + node _T_601 = and(_T_598, _T_600) @[el2_exu_div_ctl.scala 132:36] + node _T_602 = or(_T_596, _T_601) @[el2_exu_div_ctl.scala 131:67] + node _T_603 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 133:15] + node _T_604 = eq(_T_603, UInt<1>("h00")) @[el2_exu_div_ctl.scala 133:21] + node _T_605 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 133:44] + node _T_606 = eq(_T_605, UInt<1>("h01")) @[el2_exu_div_ctl.scala 133:50] + node _T_607 = and(_T_604, _T_606) @[el2_exu_div_ctl.scala 133:36] + node _T_608 = or(_T_602, _T_607) @[el2_exu_div_ctl.scala 132:67] + node _T_609 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 135:13] + node _T_610 = eq(_T_609, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:19] + node _T_611 = bits(b_cls, 2, 2) @[el2_exu_div_ctl.scala 135:42] + node _T_612 = eq(_T_611, UInt<1>("h01")) @[el2_exu_div_ctl.scala 135:48] + node _T_613 = and(_T_610, _T_612) @[el2_exu_div_ctl.scala 135:34] + node _T_614 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 136:15] + node _T_615 = eq(_T_614, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:21] + node _T_616 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 136:44] + node _T_617 = eq(_T_616, UInt<1>("h01")) @[el2_exu_div_ctl.scala 136:50] + node _T_618 = and(_T_615, _T_617) @[el2_exu_div_ctl.scala 136:36] + node _T_619 = or(_T_613, _T_618) @[el2_exu_div_ctl.scala 135:65] + node _T_620 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 137:15] + node _T_621 = eq(_T_620, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:21] + node _T_622 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 137:44] + node _T_623 = eq(_T_622, UInt<1>("h01")) @[el2_exu_div_ctl.scala 137:50] + node _T_624 = and(_T_621, _T_623) @[el2_exu_div_ctl.scala 137:36] + node _T_625 = or(_T_619, _T_624) @[el2_exu_div_ctl.scala 136:67] + node _T_626 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 138:15] + node _T_627 = eq(_T_626, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:21] + node _T_628 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 138:44] + node _T_629 = eq(_T_628, UInt<1>("h00")) @[el2_exu_div_ctl.scala 138:50] + node _T_630 = and(_T_627, _T_629) @[el2_exu_div_ctl.scala 138:36] + node _T_631 = or(_T_625, _T_630) @[el2_exu_div_ctl.scala 137:67] + node _T_632 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 140:13] + node _T_633 = eq(_T_632, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:19] + node _T_634 = bits(b_cls, 2, 1) @[el2_exu_div_ctl.scala 140:42] + node _T_635 = eq(_T_634, UInt<1>("h01")) @[el2_exu_div_ctl.scala 140:48] + node _T_636 = and(_T_633, _T_635) @[el2_exu_div_ctl.scala 140:34] + node _T_637 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 141:15] + node _T_638 = eq(_T_637, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:21] + node _T_639 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 141:44] + node _T_640 = eq(_T_639, UInt<1>("h01")) @[el2_exu_div_ctl.scala 141:50] + node _T_641 = and(_T_638, _T_640) @[el2_exu_div_ctl.scala 141:36] + node _T_642 = or(_T_636, _T_641) @[el2_exu_div_ctl.scala 140:65] + node _T_643 = bits(a_cls, 2, 0) @[el2_exu_div_ctl.scala 142:15] + node _T_644 = eq(_T_643, UInt<1>("h01")) @[el2_exu_div_ctl.scala 142:21] + node _T_645 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 142:44] + node _T_646 = eq(_T_645, UInt<1>("h00")) @[el2_exu_div_ctl.scala 142:50] + node _T_647 = and(_T_644, _T_646) @[el2_exu_div_ctl.scala 142:36] + node _T_648 = or(_T_642, _T_647) @[el2_exu_div_ctl.scala 141:67] + node _T_649 = bits(a_cls, 2, 2) @[el2_exu_div_ctl.scala 144:13] + node _T_650 = eq(_T_649, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:19] + node _T_651 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 144:42] + node _T_652 = eq(_T_651, UInt<1>("h01")) @[el2_exu_div_ctl.scala 144:48] + node _T_653 = and(_T_650, _T_652) @[el2_exu_div_ctl.scala 144:34] + node _T_654 = bits(a_cls, 2, 1) @[el2_exu_div_ctl.scala 145:15] + node _T_655 = eq(_T_654, UInt<1>("h01")) @[el2_exu_div_ctl.scala 145:21] + node _T_656 = bits(b_cls, 2, 0) @[el2_exu_div_ctl.scala 145:44] + node _T_657 = eq(_T_656, UInt<1>("h00")) @[el2_exu_div_ctl.scala 145:50] + node _T_658 = and(_T_655, _T_657) @[el2_exu_div_ctl.scala 145:36] + node _T_659 = or(_T_653, _T_658) @[el2_exu_div_ctl.scala 144:65] + node _T_660 = cat(_T_648, _T_659) @[Cat.scala 29:58] + node _T_661 = cat(_T_608, _T_631) @[Cat.scala 29:58] + node shortq_raw = cat(_T_661, _T_660) @[Cat.scala 29:58] + node _T_662 = bits(m_ff, 31, 0) @[el2_exu_div_ctl.scala 148:42] + node _T_663 = neq(_T_662, UInt<32>("h00")) @[el2_exu_div_ctl.scala 148:49] + node _T_664 = and(valid_ff_x, _T_663) @[el2_exu_div_ctl.scala 148:35] + node _T_665 = neq(shortq_raw, UInt<4>("h00")) @[el2_exu_div_ctl.scala 148:78] + node shortq_enable = and(_T_664, _T_665) @[el2_exu_div_ctl.scala 148:64] + node _T_666 = bits(shortq_enable, 0, 0) @[Bitwise.scala 72:15] + node _T_667 = mux(_T_666, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node shortq_shift = and(_T_667, shortq_raw) @[el2_exu_div_ctl.scala 149:44] + node _T_668 = bits(shortq_shift_xx, 3, 3) @[el2_exu_div_ctl.scala 152:20] + node _T_669 = bits(_T_668, 0, 0) @[el2_exu_div_ctl.scala 152:24] + node _T_670 = bits(shortq_shift_xx, 2, 2) @[el2_exu_div_ctl.scala 153:20] + node _T_671 = bits(_T_670, 0, 0) @[el2_exu_div_ctl.scala 153:24] + node _T_672 = bits(shortq_shift_xx, 1, 1) @[el2_exu_div_ctl.scala 154:20] + node _T_673 = bits(_T_672, 0, 0) @[el2_exu_div_ctl.scala 154:24] + node _T_674 = bits(shortq_shift_xx, 0, 0) @[el2_exu_div_ctl.scala 155:20] + node _T_675 = bits(_T_674, 0, 0) @[el2_exu_div_ctl.scala 155:24] + node _T_676 = mux(_T_669, UInt<5>("h01f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_677 = mux(_T_671, UInt<5>("h018"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_678 = mux(_T_673, UInt<5>("h010"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_679 = mux(_T_675, UInt<4>("h08"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_680 = or(_T_676, _T_677) @[Mux.scala 27:72] + node _T_681 = or(_T_680, _T_678) @[Mux.scala 27:72] + node _T_682 = or(_T_681, _T_679) @[Mux.scala 27:72] + wire shortq_shift_ff : UInt<5> @[Mux.scala 27:72] + shortq_shift_ff <= _T_682 @[Mux.scala 27:72] + node _T_683 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 159:40] + node _T_684 = eq(count, UInt<6>("h020")) @[el2_exu_div_ctl.scala 159:55] + node _T_685 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 159:76] + node _T_686 = mux(_T_683, _T_684, _T_685) @[el2_exu_div_ctl.scala 159:39] + node finish = or(smallnum_case, _T_686) @[el2_exu_div_ctl.scala 159:34] + node _T_687 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 160:32] + node _T_688 = or(_T_687, finish) @[el2_exu_div_ctl.scala 160:44] + node div_clken = or(_T_688, finish_ff) @[el2_exu_div_ctl.scala 160:53] + node _T_689 = or(io.dp.valid, run_state) @[el2_exu_div_ctl.scala 161:33] + node _T_690 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:48] + node _T_691 = and(_T_689, _T_690) @[el2_exu_div_ctl.scala 161:46] + node _T_692 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 161:58] + node run_in = and(_T_691, _T_692) @[el2_exu_div_ctl.scala 161:56] + node _T_693 = eq(finish, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:37] + node _T_694 = and(run_state, _T_693) @[el2_exu_div_ctl.scala 162:35] + node _T_695 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:47] + node _T_696 = and(_T_694, _T_695) @[el2_exu_div_ctl.scala 162:45] + node _T_697 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 162:60] + node _T_698 = and(_T_696, _T_697) @[el2_exu_div_ctl.scala 162:58] + node _T_699 = bits(_T_698, 0, 0) @[Bitwise.scala 72:15] + node _T_700 = mux(_T_699, UInt<6>("h03f"), UInt<6>("h00")) @[Bitwise.scala 72:12] + node _T_701 = cat(UInt<1>("h00"), shortq_shift_ff) @[Cat.scala 29:58] + node _T_702 = add(count, _T_701) @[el2_exu_div_ctl.scala 162:86] + node _T_703 = tail(_T_702, 1) @[el2_exu_div_ctl.scala 162:86] + node _T_704 = add(_T_703, UInt<6>("h01")) @[el2_exu_div_ctl.scala 162:113] + node _T_705 = tail(_T_704, 1) @[el2_exu_div_ctl.scala 162:113] + node _T_706 = and(_T_700, _T_705) @[el2_exu_div_ctl.scala 162:77] + count_in <= _T_706 @[el2_exu_div_ctl.scala 162:14] + node _T_707 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 165:34] + node _T_708 = and(finish_ff, _T_707) @[el2_exu_div_ctl.scala 165:32] + io.finish_dly <= _T_708 @[el2_exu_div_ctl.scala 165:18] + node _T_709 = eq(io.dp.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 166:20] + node _T_710 = neq(io.divisor, UInt<32>("h00")) @[el2_exu_div_ctl.scala 166:48] + node sign_eff = and(_T_709, _T_710) @[el2_exu_div_ctl.scala 166:34] + node _T_711 = eq(run_state, UInt<1>("h00")) @[el2_exu_div_ctl.scala 170:6] + node _T_712 = bits(_T_711, 0, 0) @[el2_exu_div_ctl.scala 170:18] + node _T_713 = cat(UInt<1>("h00"), io.dividend) @[Cat.scala 29:58] + node _T_714 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 171:30] + node _T_715 = and(run_state, _T_714) @[el2_exu_div_ctl.scala 171:16] + node _T_716 = bits(_T_715, 0, 0) @[el2_exu_div_ctl.scala 171:51] + node _T_717 = bits(dividend_eff, 31, 0) @[el2_exu_div_ctl.scala 171:78] + node _T_718 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 171:90] + node _T_719 = eq(_T_718, UInt<1>("h00")) @[el2_exu_div_ctl.scala 171:85] + node _T_720 = cat(_T_717, _T_719) @[Cat.scala 29:58] + node _T_721 = dshl(_T_720, shortq_shift_ff) @[el2_exu_div_ctl.scala 171:96] + node _T_722 = or(valid_ff_x, shortq_enable_ff) @[el2_exu_div_ctl.scala 172:31] + node _T_723 = eq(_T_722, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:18] + node _T_724 = and(run_state, _T_723) @[el2_exu_div_ctl.scala 172:16] + node _T_725 = bits(_T_724, 0, 0) @[el2_exu_div_ctl.scala 172:52] + node _T_726 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 172:70] + node _T_727 = bits(a_in, 32, 32) @[el2_exu_div_ctl.scala 172:82] + node _T_728 = eq(_T_727, UInt<1>("h00")) @[el2_exu_div_ctl.scala 172:77] + node _T_729 = cat(_T_726, _T_728) @[Cat.scala 29:58] + node _T_730 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_731 = mux(_T_716, _T_721, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_732 = mux(_T_725, _T_729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_733 = or(_T_730, _T_731) @[Mux.scala 27:72] + node _T_734 = or(_T_733, _T_732) @[Mux.scala 27:72] + wire _T_735 : UInt<64> @[Mux.scala 27:72] + _T_735 <= _T_734 @[Mux.scala 27:72] + q_in <= _T_735 @[el2_exu_div_ctl.scala 169:8] + node _T_736 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 174:50] + node _T_737 = and(run_state, _T_736) @[el2_exu_div_ctl.scala 174:48] + node qff_enable = or(io.dp.valid, _T_737) @[el2_exu_div_ctl.scala 174:35] + node _T_738 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 175:32] + node _T_739 = bits(_T_738, 0, 0) @[el2_exu_div_ctl.scala 175:51] + node _T_740 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:74] + wire _T_741 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_742 = bits(_T_740, 0, 0) @[el2_lib.scala 543:27] + node _T_743 = orr(_T_742) @[el2_lib.scala 543:35] + node _T_744 = bits(_T_740, 1, 1) @[el2_lib.scala 543:44] + node _T_745 = not(_T_744) @[el2_lib.scala 543:40] + node _T_746 = bits(_T_740, 1, 1) @[el2_lib.scala 543:51] + node _T_747 = mux(_T_743, _T_745, _T_746) @[el2_lib.scala 543:23] + _T_741[0] <= _T_747 @[el2_lib.scala 543:17] + node _T_748 = bits(_T_740, 1, 0) @[el2_lib.scala 543:27] + node _T_749 = orr(_T_748) @[el2_lib.scala 543:35] + node _T_750 = bits(_T_740, 2, 2) @[el2_lib.scala 543:44] + node _T_751 = not(_T_750) @[el2_lib.scala 543:40] + node _T_752 = bits(_T_740, 2, 2) @[el2_lib.scala 543:51] + node _T_753 = mux(_T_749, _T_751, _T_752) @[el2_lib.scala 543:23] + _T_741[1] <= _T_753 @[el2_lib.scala 543:17] + node _T_754 = bits(_T_740, 2, 0) @[el2_lib.scala 543:27] + node _T_755 = orr(_T_754) @[el2_lib.scala 543:35] + node _T_756 = bits(_T_740, 3, 3) @[el2_lib.scala 543:44] + node _T_757 = not(_T_756) @[el2_lib.scala 543:40] + node _T_758 = bits(_T_740, 3, 3) @[el2_lib.scala 543:51] + node _T_759 = mux(_T_755, _T_757, _T_758) @[el2_lib.scala 543:23] + _T_741[2] <= _T_759 @[el2_lib.scala 543:17] + node _T_760 = bits(_T_740, 3, 0) @[el2_lib.scala 543:27] + node _T_761 = orr(_T_760) @[el2_lib.scala 543:35] + node _T_762 = bits(_T_740, 4, 4) @[el2_lib.scala 543:44] + node _T_763 = not(_T_762) @[el2_lib.scala 543:40] + node _T_764 = bits(_T_740, 4, 4) @[el2_lib.scala 543:51] + node _T_765 = mux(_T_761, _T_763, _T_764) @[el2_lib.scala 543:23] + _T_741[3] <= _T_765 @[el2_lib.scala 543:17] + node _T_766 = bits(_T_740, 4, 0) @[el2_lib.scala 543:27] + node _T_767 = orr(_T_766) @[el2_lib.scala 543:35] + node _T_768 = bits(_T_740, 5, 5) @[el2_lib.scala 543:44] + node _T_769 = not(_T_768) @[el2_lib.scala 543:40] + node _T_770 = bits(_T_740, 5, 5) @[el2_lib.scala 543:51] + node _T_771 = mux(_T_767, _T_769, _T_770) @[el2_lib.scala 543:23] + _T_741[4] <= _T_771 @[el2_lib.scala 543:17] + node _T_772 = bits(_T_740, 5, 0) @[el2_lib.scala 543:27] + node _T_773 = orr(_T_772) @[el2_lib.scala 543:35] + node _T_774 = bits(_T_740, 6, 6) @[el2_lib.scala 543:44] + node _T_775 = not(_T_774) @[el2_lib.scala 543:40] + node _T_776 = bits(_T_740, 6, 6) @[el2_lib.scala 543:51] + node _T_777 = mux(_T_773, _T_775, _T_776) @[el2_lib.scala 543:23] + _T_741[5] <= _T_777 @[el2_lib.scala 543:17] + node _T_778 = bits(_T_740, 6, 0) @[el2_lib.scala 543:27] + node _T_779 = orr(_T_778) @[el2_lib.scala 543:35] + node _T_780 = bits(_T_740, 7, 7) @[el2_lib.scala 543:44] + node _T_781 = not(_T_780) @[el2_lib.scala 543:40] + node _T_782 = bits(_T_740, 7, 7) @[el2_lib.scala 543:51] + node _T_783 = mux(_T_779, _T_781, _T_782) @[el2_lib.scala 543:23] + _T_741[6] <= _T_783 @[el2_lib.scala 543:17] + node _T_784 = bits(_T_740, 7, 0) @[el2_lib.scala 543:27] + node _T_785 = orr(_T_784) @[el2_lib.scala 543:35] + node _T_786 = bits(_T_740, 8, 8) @[el2_lib.scala 543:44] + node _T_787 = not(_T_786) @[el2_lib.scala 543:40] + node _T_788 = bits(_T_740, 8, 8) @[el2_lib.scala 543:51] + node _T_789 = mux(_T_785, _T_787, _T_788) @[el2_lib.scala 543:23] + _T_741[7] <= _T_789 @[el2_lib.scala 543:17] + node _T_790 = bits(_T_740, 8, 0) @[el2_lib.scala 543:27] + node _T_791 = orr(_T_790) @[el2_lib.scala 543:35] + node _T_792 = bits(_T_740, 9, 9) @[el2_lib.scala 543:44] + node _T_793 = not(_T_792) @[el2_lib.scala 543:40] + node _T_794 = bits(_T_740, 9, 9) @[el2_lib.scala 543:51] + node _T_795 = mux(_T_791, _T_793, _T_794) @[el2_lib.scala 543:23] + _T_741[8] <= _T_795 @[el2_lib.scala 543:17] + node _T_796 = bits(_T_740, 9, 0) @[el2_lib.scala 543:27] + node _T_797 = orr(_T_796) @[el2_lib.scala 543:35] + node _T_798 = bits(_T_740, 10, 10) @[el2_lib.scala 543:44] + node _T_799 = not(_T_798) @[el2_lib.scala 543:40] + node _T_800 = bits(_T_740, 10, 10) @[el2_lib.scala 543:51] + node _T_801 = mux(_T_797, _T_799, _T_800) @[el2_lib.scala 543:23] + _T_741[9] <= _T_801 @[el2_lib.scala 543:17] + node _T_802 = bits(_T_740, 10, 0) @[el2_lib.scala 543:27] + node _T_803 = orr(_T_802) @[el2_lib.scala 543:35] + node _T_804 = bits(_T_740, 11, 11) @[el2_lib.scala 543:44] + node _T_805 = not(_T_804) @[el2_lib.scala 543:40] + node _T_806 = bits(_T_740, 11, 11) @[el2_lib.scala 543:51] + node _T_807 = mux(_T_803, _T_805, _T_806) @[el2_lib.scala 543:23] + _T_741[10] <= _T_807 @[el2_lib.scala 543:17] + node _T_808 = bits(_T_740, 11, 0) @[el2_lib.scala 543:27] + node _T_809 = orr(_T_808) @[el2_lib.scala 543:35] + node _T_810 = bits(_T_740, 12, 12) @[el2_lib.scala 543:44] + node _T_811 = not(_T_810) @[el2_lib.scala 543:40] + node _T_812 = bits(_T_740, 12, 12) @[el2_lib.scala 543:51] + node _T_813 = mux(_T_809, _T_811, _T_812) @[el2_lib.scala 543:23] + _T_741[11] <= _T_813 @[el2_lib.scala 543:17] + node _T_814 = bits(_T_740, 12, 0) @[el2_lib.scala 543:27] + node _T_815 = orr(_T_814) @[el2_lib.scala 543:35] + node _T_816 = bits(_T_740, 13, 13) @[el2_lib.scala 543:44] + node _T_817 = not(_T_816) @[el2_lib.scala 543:40] + node _T_818 = bits(_T_740, 13, 13) @[el2_lib.scala 543:51] + node _T_819 = mux(_T_815, _T_817, _T_818) @[el2_lib.scala 543:23] + _T_741[12] <= _T_819 @[el2_lib.scala 543:17] + node _T_820 = bits(_T_740, 13, 0) @[el2_lib.scala 543:27] + node _T_821 = orr(_T_820) @[el2_lib.scala 543:35] + node _T_822 = bits(_T_740, 14, 14) @[el2_lib.scala 543:44] + node _T_823 = not(_T_822) @[el2_lib.scala 543:40] + node _T_824 = bits(_T_740, 14, 14) @[el2_lib.scala 543:51] + node _T_825 = mux(_T_821, _T_823, _T_824) @[el2_lib.scala 543:23] + _T_741[13] <= _T_825 @[el2_lib.scala 543:17] + node _T_826 = bits(_T_740, 14, 0) @[el2_lib.scala 543:27] + node _T_827 = orr(_T_826) @[el2_lib.scala 543:35] + node _T_828 = bits(_T_740, 15, 15) @[el2_lib.scala 543:44] + node _T_829 = not(_T_828) @[el2_lib.scala 543:40] + node _T_830 = bits(_T_740, 15, 15) @[el2_lib.scala 543:51] + node _T_831 = mux(_T_827, _T_829, _T_830) @[el2_lib.scala 543:23] + _T_741[14] <= _T_831 @[el2_lib.scala 543:17] + node _T_832 = bits(_T_740, 15, 0) @[el2_lib.scala 543:27] + node _T_833 = orr(_T_832) @[el2_lib.scala 543:35] + node _T_834 = bits(_T_740, 16, 16) @[el2_lib.scala 543:44] + node _T_835 = not(_T_834) @[el2_lib.scala 543:40] + node _T_836 = bits(_T_740, 16, 16) @[el2_lib.scala 543:51] + node _T_837 = mux(_T_833, _T_835, _T_836) @[el2_lib.scala 543:23] + _T_741[15] <= _T_837 @[el2_lib.scala 543:17] + node _T_838 = bits(_T_740, 16, 0) @[el2_lib.scala 543:27] + node _T_839 = orr(_T_838) @[el2_lib.scala 543:35] + node _T_840 = bits(_T_740, 17, 17) @[el2_lib.scala 543:44] + node _T_841 = not(_T_840) @[el2_lib.scala 543:40] + node _T_842 = bits(_T_740, 17, 17) @[el2_lib.scala 543:51] + node _T_843 = mux(_T_839, _T_841, _T_842) @[el2_lib.scala 543:23] + _T_741[16] <= _T_843 @[el2_lib.scala 543:17] + node _T_844 = bits(_T_740, 17, 0) @[el2_lib.scala 543:27] + node _T_845 = orr(_T_844) @[el2_lib.scala 543:35] + node _T_846 = bits(_T_740, 18, 18) @[el2_lib.scala 543:44] + node _T_847 = not(_T_846) @[el2_lib.scala 543:40] + node _T_848 = bits(_T_740, 18, 18) @[el2_lib.scala 543:51] + node _T_849 = mux(_T_845, _T_847, _T_848) @[el2_lib.scala 543:23] + _T_741[17] <= _T_849 @[el2_lib.scala 543:17] + node _T_850 = bits(_T_740, 18, 0) @[el2_lib.scala 543:27] + node _T_851 = orr(_T_850) @[el2_lib.scala 543:35] + node _T_852 = bits(_T_740, 19, 19) @[el2_lib.scala 543:44] + node _T_853 = not(_T_852) @[el2_lib.scala 543:40] + node _T_854 = bits(_T_740, 19, 19) @[el2_lib.scala 543:51] + node _T_855 = mux(_T_851, _T_853, _T_854) @[el2_lib.scala 543:23] + _T_741[18] <= _T_855 @[el2_lib.scala 543:17] + node _T_856 = bits(_T_740, 19, 0) @[el2_lib.scala 543:27] + node _T_857 = orr(_T_856) @[el2_lib.scala 543:35] + node _T_858 = bits(_T_740, 20, 20) @[el2_lib.scala 543:44] + node _T_859 = not(_T_858) @[el2_lib.scala 543:40] + node _T_860 = bits(_T_740, 20, 20) @[el2_lib.scala 543:51] + node _T_861 = mux(_T_857, _T_859, _T_860) @[el2_lib.scala 543:23] + _T_741[19] <= _T_861 @[el2_lib.scala 543:17] + node _T_862 = bits(_T_740, 20, 0) @[el2_lib.scala 543:27] + node _T_863 = orr(_T_862) @[el2_lib.scala 543:35] + node _T_864 = bits(_T_740, 21, 21) @[el2_lib.scala 543:44] + node _T_865 = not(_T_864) @[el2_lib.scala 543:40] + node _T_866 = bits(_T_740, 21, 21) @[el2_lib.scala 543:51] + node _T_867 = mux(_T_863, _T_865, _T_866) @[el2_lib.scala 543:23] + _T_741[20] <= _T_867 @[el2_lib.scala 543:17] + node _T_868 = bits(_T_740, 21, 0) @[el2_lib.scala 543:27] + node _T_869 = orr(_T_868) @[el2_lib.scala 543:35] + node _T_870 = bits(_T_740, 22, 22) @[el2_lib.scala 543:44] + node _T_871 = not(_T_870) @[el2_lib.scala 543:40] + node _T_872 = bits(_T_740, 22, 22) @[el2_lib.scala 543:51] + node _T_873 = mux(_T_869, _T_871, _T_872) @[el2_lib.scala 543:23] + _T_741[21] <= _T_873 @[el2_lib.scala 543:17] + node _T_874 = bits(_T_740, 22, 0) @[el2_lib.scala 543:27] + node _T_875 = orr(_T_874) @[el2_lib.scala 543:35] + node _T_876 = bits(_T_740, 23, 23) @[el2_lib.scala 543:44] + node _T_877 = not(_T_876) @[el2_lib.scala 543:40] + node _T_878 = bits(_T_740, 23, 23) @[el2_lib.scala 543:51] + node _T_879 = mux(_T_875, _T_877, _T_878) @[el2_lib.scala 543:23] + _T_741[22] <= _T_879 @[el2_lib.scala 543:17] + node _T_880 = bits(_T_740, 23, 0) @[el2_lib.scala 543:27] + node _T_881 = orr(_T_880) @[el2_lib.scala 543:35] + node _T_882 = bits(_T_740, 24, 24) @[el2_lib.scala 543:44] + node _T_883 = not(_T_882) @[el2_lib.scala 543:40] + node _T_884 = bits(_T_740, 24, 24) @[el2_lib.scala 543:51] + node _T_885 = mux(_T_881, _T_883, _T_884) @[el2_lib.scala 543:23] + _T_741[23] <= _T_885 @[el2_lib.scala 543:17] + node _T_886 = bits(_T_740, 24, 0) @[el2_lib.scala 543:27] + node _T_887 = orr(_T_886) @[el2_lib.scala 543:35] + node _T_888 = bits(_T_740, 25, 25) @[el2_lib.scala 543:44] + node _T_889 = not(_T_888) @[el2_lib.scala 543:40] + node _T_890 = bits(_T_740, 25, 25) @[el2_lib.scala 543:51] + node _T_891 = mux(_T_887, _T_889, _T_890) @[el2_lib.scala 543:23] + _T_741[24] <= _T_891 @[el2_lib.scala 543:17] + node _T_892 = bits(_T_740, 25, 0) @[el2_lib.scala 543:27] + node _T_893 = orr(_T_892) @[el2_lib.scala 543:35] + node _T_894 = bits(_T_740, 26, 26) @[el2_lib.scala 543:44] + node _T_895 = not(_T_894) @[el2_lib.scala 543:40] + node _T_896 = bits(_T_740, 26, 26) @[el2_lib.scala 543:51] + node _T_897 = mux(_T_893, _T_895, _T_896) @[el2_lib.scala 543:23] + _T_741[25] <= _T_897 @[el2_lib.scala 543:17] + node _T_898 = bits(_T_740, 26, 0) @[el2_lib.scala 543:27] + node _T_899 = orr(_T_898) @[el2_lib.scala 543:35] + node _T_900 = bits(_T_740, 27, 27) @[el2_lib.scala 543:44] + node _T_901 = not(_T_900) @[el2_lib.scala 543:40] + node _T_902 = bits(_T_740, 27, 27) @[el2_lib.scala 543:51] + node _T_903 = mux(_T_899, _T_901, _T_902) @[el2_lib.scala 543:23] + _T_741[26] <= _T_903 @[el2_lib.scala 543:17] + node _T_904 = bits(_T_740, 27, 0) @[el2_lib.scala 543:27] + node _T_905 = orr(_T_904) @[el2_lib.scala 543:35] + node _T_906 = bits(_T_740, 28, 28) @[el2_lib.scala 543:44] + node _T_907 = not(_T_906) @[el2_lib.scala 543:40] + node _T_908 = bits(_T_740, 28, 28) @[el2_lib.scala 543:51] + node _T_909 = mux(_T_905, _T_907, _T_908) @[el2_lib.scala 543:23] + _T_741[27] <= _T_909 @[el2_lib.scala 543:17] + node _T_910 = bits(_T_740, 28, 0) @[el2_lib.scala 543:27] + node _T_911 = orr(_T_910) @[el2_lib.scala 543:35] + node _T_912 = bits(_T_740, 29, 29) @[el2_lib.scala 543:44] + node _T_913 = not(_T_912) @[el2_lib.scala 543:40] + node _T_914 = bits(_T_740, 29, 29) @[el2_lib.scala 543:51] + node _T_915 = mux(_T_911, _T_913, _T_914) @[el2_lib.scala 543:23] + _T_741[28] <= _T_915 @[el2_lib.scala 543:17] + node _T_916 = bits(_T_740, 29, 0) @[el2_lib.scala 543:27] + node _T_917 = orr(_T_916) @[el2_lib.scala 543:35] + node _T_918 = bits(_T_740, 30, 30) @[el2_lib.scala 543:44] + node _T_919 = not(_T_918) @[el2_lib.scala 543:40] + node _T_920 = bits(_T_740, 30, 30) @[el2_lib.scala 543:51] + node _T_921 = mux(_T_917, _T_919, _T_920) @[el2_lib.scala 543:23] + _T_741[29] <= _T_921 @[el2_lib.scala 543:17] + node _T_922 = bits(_T_740, 30, 0) @[el2_lib.scala 543:27] + node _T_923 = orr(_T_922) @[el2_lib.scala 543:35] + node _T_924 = bits(_T_740, 31, 31) @[el2_lib.scala 543:44] + node _T_925 = not(_T_924) @[el2_lib.scala 543:40] + node _T_926 = bits(_T_740, 31, 31) @[el2_lib.scala 543:51] + node _T_927 = mux(_T_923, _T_925, _T_926) @[el2_lib.scala 543:23] + _T_741[30] <= _T_927 @[el2_lib.scala 543:17] + node _T_928 = cat(_T_741[2], _T_741[1]) @[el2_lib.scala 545:14] + node _T_929 = cat(_T_928, _T_741[0]) @[el2_lib.scala 545:14] + node _T_930 = cat(_T_741[4], _T_741[3]) @[el2_lib.scala 545:14] + node _T_931 = cat(_T_741[6], _T_741[5]) @[el2_lib.scala 545:14] + node _T_932 = cat(_T_931, _T_930) @[el2_lib.scala 545:14] + node _T_933 = cat(_T_932, _T_929) @[el2_lib.scala 545:14] + node _T_934 = cat(_T_741[8], _T_741[7]) @[el2_lib.scala 545:14] + node _T_935 = cat(_T_741[10], _T_741[9]) @[el2_lib.scala 545:14] + node _T_936 = cat(_T_935, _T_934) @[el2_lib.scala 545:14] + node _T_937 = cat(_T_741[12], _T_741[11]) @[el2_lib.scala 545:14] + node _T_938 = cat(_T_741[14], _T_741[13]) @[el2_lib.scala 545:14] + node _T_939 = cat(_T_938, _T_937) @[el2_lib.scala 545:14] + node _T_940 = cat(_T_939, _T_936) @[el2_lib.scala 545:14] + node _T_941 = cat(_T_940, _T_933) @[el2_lib.scala 545:14] + node _T_942 = cat(_T_741[16], _T_741[15]) @[el2_lib.scala 545:14] + node _T_943 = cat(_T_741[18], _T_741[17]) @[el2_lib.scala 545:14] + node _T_944 = cat(_T_943, _T_942) @[el2_lib.scala 545:14] + node _T_945 = cat(_T_741[20], _T_741[19]) @[el2_lib.scala 545:14] + node _T_946 = cat(_T_741[22], _T_741[21]) @[el2_lib.scala 545:14] + node _T_947 = cat(_T_946, _T_945) @[el2_lib.scala 545:14] + node _T_948 = cat(_T_947, _T_944) @[el2_lib.scala 545:14] + node _T_949 = cat(_T_741[24], _T_741[23]) @[el2_lib.scala 545:14] + node _T_950 = cat(_T_741[26], _T_741[25]) @[el2_lib.scala 545:14] + node _T_951 = cat(_T_950, _T_949) @[el2_lib.scala 545:14] + node _T_952 = cat(_T_741[28], _T_741[27]) @[el2_lib.scala 545:14] + node _T_953 = cat(_T_741[30], _T_741[29]) @[el2_lib.scala 545:14] + node _T_954 = cat(_T_953, _T_952) @[el2_lib.scala 545:14] + node _T_955 = cat(_T_954, _T_951) @[el2_lib.scala 545:14] + node _T_956 = cat(_T_955, _T_948) @[el2_lib.scala 545:14] + node _T_957 = cat(_T_956, _T_941) @[el2_lib.scala 545:14] + node _T_958 = bits(_T_740, 0, 0) @[el2_lib.scala 545:24] + node _T_959 = cat(_T_957, _T_958) @[Cat.scala 29:58] + node _T_960 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 175:86] + node _T_961 = mux(_T_739, _T_959, _T_960) @[el2_exu_div_ctl.scala 175:22] + dividend_eff <= _T_961 @[el2_exu_div_ctl.scala 175:16] + node _T_962 = bits(add, 0, 0) @[el2_exu_div_ctl.scala 178:20] + node _T_963 = not(m_ff) @[el2_exu_div_ctl.scala 178:35] + node _T_964 = mux(_T_962, m_ff, _T_963) @[el2_exu_div_ctl.scala 178:15] + m_eff <= _T_964 @[el2_exu_div_ctl.scala 178:9] + node _T_965 = cat(UInt<24>("h00"), dividend_eff) @[Cat.scala 29:58] + node _T_966 = dshl(_T_965, shortq_shift_ff) @[el2_exu_div_ctl.scala 179:47] + a_eff_shift <= _T_966 @[el2_exu_div_ctl.scala 179:15] + node _T_967 = bits(rem_correct, 0, 0) @[el2_exu_div_ctl.scala 181:17] + node _T_968 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:6] + node _T_969 = eq(shortq_enable_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 182:21] + node _T_970 = and(_T_968, _T_969) @[el2_exu_div_ctl.scala 182:19] + node _T_971 = bits(_T_970, 0, 0) @[el2_exu_div_ctl.scala 182:40] + node _T_972 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 182:58] + node _T_973 = bits(q_ff, 32, 32) @[el2_exu_div_ctl.scala 182:70] + node _T_974 = cat(_T_972, _T_973) @[Cat.scala 29:58] + node _T_975 = eq(rem_correct, UInt<1>("h00")) @[el2_exu_div_ctl.scala 183:6] + node _T_976 = and(_T_975, shortq_enable_ff) @[el2_exu_div_ctl.scala 183:19] + node _T_977 = bits(_T_976, 0, 0) @[el2_exu_div_ctl.scala 183:40] + node _T_978 = bits(a_eff_shift, 55, 32) @[el2_exu_div_ctl.scala 183:74] + node _T_979 = cat(UInt<9>("h00"), _T_978) @[Cat.scala 29:58] + node _T_980 = mux(_T_967, a_ff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_981 = mux(_T_971, _T_974, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_982 = mux(_T_977, _T_979, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_983 = or(_T_980, _T_981) @[Mux.scala 27:72] + node _T_984 = or(_T_983, _T_982) @[Mux.scala 27:72] + wire _T_985 : UInt<33> @[Mux.scala 27:72] + _T_985 <= _T_984 @[Mux.scala 27:72] + a_eff <= _T_985 @[el2_exu_div_ctl.scala 180:9] + node _T_986 = eq(shortq_enable, UInt<1>("h00")) @[el2_exu_div_ctl.scala 185:49] + node _T_987 = and(run_state, _T_986) @[el2_exu_div_ctl.scala 185:47] + node _T_988 = neq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 185:73] + node _T_989 = and(_T_987, _T_988) @[el2_exu_div_ctl.scala 185:64] + node _T_990 = or(io.dp.valid, _T_989) @[el2_exu_div_ctl.scala 185:34] + node aff_enable = or(_T_990, rem_correct) @[el2_exu_div_ctl.scala 185:89] + node _T_991 = bits(run_state, 0, 0) @[Bitwise.scala 72:15] + node _T_992 = mux(_T_991, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] + node _T_993 = and(_T_992, a_eff) @[el2_exu_div_ctl.scala 186:33] + a_shift <= _T_993 @[el2_exu_div_ctl.scala 186:11] + node _T_994 = bits(run_state, 0, 0) @[Bitwise.scala 72:15] + node _T_995 = mux(_T_994, UInt<33>("h01ffffffff"), UInt<33>("h00")) @[Bitwise.scala 72:12] + node _T_996 = add(a_shift, m_eff) @[el2_exu_div_ctl.scala 187:41] + node _T_997 = tail(_T_996, 1) @[el2_exu_div_ctl.scala 187:41] + node _T_998 = eq(add, UInt<1>("h00")) @[el2_exu_div_ctl.scala 187:65] + node _T_999 = cat(UInt<32>("h00"), _T_998) @[Cat.scala 29:58] + node _T_1000 = add(_T_997, _T_999) @[el2_exu_div_ctl.scala 187:49] + node _T_1001 = tail(_T_1000, 1) @[el2_exu_div_ctl.scala 187:49] + node _T_1002 = and(_T_995, _T_1001) @[el2_exu_div_ctl.scala 187:30] + a_in <= _T_1002 @[el2_exu_div_ctl.scala 187:8] + node m_already_comp = and(divisor_neg_ff, sign_ff) @[el2_exu_div_ctl.scala 188:48] + node _T_1003 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 190:16] + node _T_1004 = or(_T_1003, rem_correct) @[el2_exu_div_ctl.scala 190:21] + node _T_1005 = xor(_T_1004, m_already_comp) @[el2_exu_div_ctl.scala 190:36] + add <= _T_1005 @[el2_exu_div_ctl.scala 190:8] + node _T_1006 = eq(count, UInt<6>("h021")) @[el2_exu_div_ctl.scala 191:26] + node _T_1007 = and(_T_1006, rem_ff) @[el2_exu_div_ctl.scala 191:41] + node _T_1008 = bits(a_ff, 32, 32) @[el2_exu_div_ctl.scala 191:56] + node _T_1009 = and(_T_1007, _T_1008) @[el2_exu_div_ctl.scala 191:50] + rem_correct <= _T_1009 @[el2_exu_div_ctl.scala 191:16] + node _T_1010 = xor(dividend_neg_ff, divisor_neg_ff) @[el2_exu_div_ctl.scala 192:50] + node _T_1011 = and(sign_ff, _T_1010) @[el2_exu_div_ctl.scala 192:31] + node _T_1012 = bits(_T_1011, 0, 0) @[el2_exu_div_ctl.scala 192:69] + node _T_1013 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:91] + wire _T_1014 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_1015 = bits(_T_1013, 0, 0) @[el2_lib.scala 543:27] + node _T_1016 = orr(_T_1015) @[el2_lib.scala 543:35] + node _T_1017 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:44] + node _T_1018 = not(_T_1017) @[el2_lib.scala 543:40] + node _T_1019 = bits(_T_1013, 1, 1) @[el2_lib.scala 543:51] + node _T_1020 = mux(_T_1016, _T_1018, _T_1019) @[el2_lib.scala 543:23] + _T_1014[0] <= _T_1020 @[el2_lib.scala 543:17] + node _T_1021 = bits(_T_1013, 1, 0) @[el2_lib.scala 543:27] + node _T_1022 = orr(_T_1021) @[el2_lib.scala 543:35] + node _T_1023 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:44] + node _T_1024 = not(_T_1023) @[el2_lib.scala 543:40] + node _T_1025 = bits(_T_1013, 2, 2) @[el2_lib.scala 543:51] + node _T_1026 = mux(_T_1022, _T_1024, _T_1025) @[el2_lib.scala 543:23] + _T_1014[1] <= _T_1026 @[el2_lib.scala 543:17] + node _T_1027 = bits(_T_1013, 2, 0) @[el2_lib.scala 543:27] + node _T_1028 = orr(_T_1027) @[el2_lib.scala 543:35] + node _T_1029 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:44] + node _T_1030 = not(_T_1029) @[el2_lib.scala 543:40] + node _T_1031 = bits(_T_1013, 3, 3) @[el2_lib.scala 543:51] + node _T_1032 = mux(_T_1028, _T_1030, _T_1031) @[el2_lib.scala 543:23] + _T_1014[2] <= _T_1032 @[el2_lib.scala 543:17] + node _T_1033 = bits(_T_1013, 3, 0) @[el2_lib.scala 543:27] + node _T_1034 = orr(_T_1033) @[el2_lib.scala 543:35] + node _T_1035 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:44] + node _T_1036 = not(_T_1035) @[el2_lib.scala 543:40] + node _T_1037 = bits(_T_1013, 4, 4) @[el2_lib.scala 543:51] + node _T_1038 = mux(_T_1034, _T_1036, _T_1037) @[el2_lib.scala 543:23] + _T_1014[3] <= _T_1038 @[el2_lib.scala 543:17] + node _T_1039 = bits(_T_1013, 4, 0) @[el2_lib.scala 543:27] + node _T_1040 = orr(_T_1039) @[el2_lib.scala 543:35] + node _T_1041 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:44] + node _T_1042 = not(_T_1041) @[el2_lib.scala 543:40] + node _T_1043 = bits(_T_1013, 5, 5) @[el2_lib.scala 543:51] + node _T_1044 = mux(_T_1040, _T_1042, _T_1043) @[el2_lib.scala 543:23] + _T_1014[4] <= _T_1044 @[el2_lib.scala 543:17] + node _T_1045 = bits(_T_1013, 5, 0) @[el2_lib.scala 543:27] + node _T_1046 = orr(_T_1045) @[el2_lib.scala 543:35] + node _T_1047 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:44] + node _T_1048 = not(_T_1047) @[el2_lib.scala 543:40] + node _T_1049 = bits(_T_1013, 6, 6) @[el2_lib.scala 543:51] + node _T_1050 = mux(_T_1046, _T_1048, _T_1049) @[el2_lib.scala 543:23] + _T_1014[5] <= _T_1050 @[el2_lib.scala 543:17] + node _T_1051 = bits(_T_1013, 6, 0) @[el2_lib.scala 543:27] + node _T_1052 = orr(_T_1051) @[el2_lib.scala 543:35] + node _T_1053 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:44] + node _T_1054 = not(_T_1053) @[el2_lib.scala 543:40] + node _T_1055 = bits(_T_1013, 7, 7) @[el2_lib.scala 543:51] + node _T_1056 = mux(_T_1052, _T_1054, _T_1055) @[el2_lib.scala 543:23] + _T_1014[6] <= _T_1056 @[el2_lib.scala 543:17] + node _T_1057 = bits(_T_1013, 7, 0) @[el2_lib.scala 543:27] + node _T_1058 = orr(_T_1057) @[el2_lib.scala 543:35] + node _T_1059 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:44] + node _T_1060 = not(_T_1059) @[el2_lib.scala 543:40] + node _T_1061 = bits(_T_1013, 8, 8) @[el2_lib.scala 543:51] + node _T_1062 = mux(_T_1058, _T_1060, _T_1061) @[el2_lib.scala 543:23] + _T_1014[7] <= _T_1062 @[el2_lib.scala 543:17] + node _T_1063 = bits(_T_1013, 8, 0) @[el2_lib.scala 543:27] + node _T_1064 = orr(_T_1063) @[el2_lib.scala 543:35] + node _T_1065 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:44] + node _T_1066 = not(_T_1065) @[el2_lib.scala 543:40] + node _T_1067 = bits(_T_1013, 9, 9) @[el2_lib.scala 543:51] + node _T_1068 = mux(_T_1064, _T_1066, _T_1067) @[el2_lib.scala 543:23] + _T_1014[8] <= _T_1068 @[el2_lib.scala 543:17] + node _T_1069 = bits(_T_1013, 9, 0) @[el2_lib.scala 543:27] + node _T_1070 = orr(_T_1069) @[el2_lib.scala 543:35] + node _T_1071 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:44] + node _T_1072 = not(_T_1071) @[el2_lib.scala 543:40] + node _T_1073 = bits(_T_1013, 10, 10) @[el2_lib.scala 543:51] + node _T_1074 = mux(_T_1070, _T_1072, _T_1073) @[el2_lib.scala 543:23] + _T_1014[9] <= _T_1074 @[el2_lib.scala 543:17] + node _T_1075 = bits(_T_1013, 10, 0) @[el2_lib.scala 543:27] + node _T_1076 = orr(_T_1075) @[el2_lib.scala 543:35] + node _T_1077 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:44] + node _T_1078 = not(_T_1077) @[el2_lib.scala 543:40] + node _T_1079 = bits(_T_1013, 11, 11) @[el2_lib.scala 543:51] + node _T_1080 = mux(_T_1076, _T_1078, _T_1079) @[el2_lib.scala 543:23] + _T_1014[10] <= _T_1080 @[el2_lib.scala 543:17] + node _T_1081 = bits(_T_1013, 11, 0) @[el2_lib.scala 543:27] + node _T_1082 = orr(_T_1081) @[el2_lib.scala 543:35] + node _T_1083 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:44] + node _T_1084 = not(_T_1083) @[el2_lib.scala 543:40] + node _T_1085 = bits(_T_1013, 12, 12) @[el2_lib.scala 543:51] + node _T_1086 = mux(_T_1082, _T_1084, _T_1085) @[el2_lib.scala 543:23] + _T_1014[11] <= _T_1086 @[el2_lib.scala 543:17] + node _T_1087 = bits(_T_1013, 12, 0) @[el2_lib.scala 543:27] + node _T_1088 = orr(_T_1087) @[el2_lib.scala 543:35] + node _T_1089 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:44] + node _T_1090 = not(_T_1089) @[el2_lib.scala 543:40] + node _T_1091 = bits(_T_1013, 13, 13) @[el2_lib.scala 543:51] + node _T_1092 = mux(_T_1088, _T_1090, _T_1091) @[el2_lib.scala 543:23] + _T_1014[12] <= _T_1092 @[el2_lib.scala 543:17] + node _T_1093 = bits(_T_1013, 13, 0) @[el2_lib.scala 543:27] + node _T_1094 = orr(_T_1093) @[el2_lib.scala 543:35] + node _T_1095 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:44] + node _T_1096 = not(_T_1095) @[el2_lib.scala 543:40] + node _T_1097 = bits(_T_1013, 14, 14) @[el2_lib.scala 543:51] + node _T_1098 = mux(_T_1094, _T_1096, _T_1097) @[el2_lib.scala 543:23] + _T_1014[13] <= _T_1098 @[el2_lib.scala 543:17] + node _T_1099 = bits(_T_1013, 14, 0) @[el2_lib.scala 543:27] + node _T_1100 = orr(_T_1099) @[el2_lib.scala 543:35] + node _T_1101 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:44] + node _T_1102 = not(_T_1101) @[el2_lib.scala 543:40] + node _T_1103 = bits(_T_1013, 15, 15) @[el2_lib.scala 543:51] + node _T_1104 = mux(_T_1100, _T_1102, _T_1103) @[el2_lib.scala 543:23] + _T_1014[14] <= _T_1104 @[el2_lib.scala 543:17] + node _T_1105 = bits(_T_1013, 15, 0) @[el2_lib.scala 543:27] + node _T_1106 = orr(_T_1105) @[el2_lib.scala 543:35] + node _T_1107 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:44] + node _T_1108 = not(_T_1107) @[el2_lib.scala 543:40] + node _T_1109 = bits(_T_1013, 16, 16) @[el2_lib.scala 543:51] + node _T_1110 = mux(_T_1106, _T_1108, _T_1109) @[el2_lib.scala 543:23] + _T_1014[15] <= _T_1110 @[el2_lib.scala 543:17] + node _T_1111 = bits(_T_1013, 16, 0) @[el2_lib.scala 543:27] + node _T_1112 = orr(_T_1111) @[el2_lib.scala 543:35] + node _T_1113 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:44] + node _T_1114 = not(_T_1113) @[el2_lib.scala 543:40] + node _T_1115 = bits(_T_1013, 17, 17) @[el2_lib.scala 543:51] + node _T_1116 = mux(_T_1112, _T_1114, _T_1115) @[el2_lib.scala 543:23] + _T_1014[16] <= _T_1116 @[el2_lib.scala 543:17] + node _T_1117 = bits(_T_1013, 17, 0) @[el2_lib.scala 543:27] + node _T_1118 = orr(_T_1117) @[el2_lib.scala 543:35] + node _T_1119 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:44] + node _T_1120 = not(_T_1119) @[el2_lib.scala 543:40] + node _T_1121 = bits(_T_1013, 18, 18) @[el2_lib.scala 543:51] + node _T_1122 = mux(_T_1118, _T_1120, _T_1121) @[el2_lib.scala 543:23] + _T_1014[17] <= _T_1122 @[el2_lib.scala 543:17] + node _T_1123 = bits(_T_1013, 18, 0) @[el2_lib.scala 543:27] + node _T_1124 = orr(_T_1123) @[el2_lib.scala 543:35] + node _T_1125 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:44] + node _T_1126 = not(_T_1125) @[el2_lib.scala 543:40] + node _T_1127 = bits(_T_1013, 19, 19) @[el2_lib.scala 543:51] + node _T_1128 = mux(_T_1124, _T_1126, _T_1127) @[el2_lib.scala 543:23] + _T_1014[18] <= _T_1128 @[el2_lib.scala 543:17] + node _T_1129 = bits(_T_1013, 19, 0) @[el2_lib.scala 543:27] + node _T_1130 = orr(_T_1129) @[el2_lib.scala 543:35] + node _T_1131 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:44] + node _T_1132 = not(_T_1131) @[el2_lib.scala 543:40] + node _T_1133 = bits(_T_1013, 20, 20) @[el2_lib.scala 543:51] + node _T_1134 = mux(_T_1130, _T_1132, _T_1133) @[el2_lib.scala 543:23] + _T_1014[19] <= _T_1134 @[el2_lib.scala 543:17] + node _T_1135 = bits(_T_1013, 20, 0) @[el2_lib.scala 543:27] + node _T_1136 = orr(_T_1135) @[el2_lib.scala 543:35] + node _T_1137 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:44] + node _T_1138 = not(_T_1137) @[el2_lib.scala 543:40] + node _T_1139 = bits(_T_1013, 21, 21) @[el2_lib.scala 543:51] + node _T_1140 = mux(_T_1136, _T_1138, _T_1139) @[el2_lib.scala 543:23] + _T_1014[20] <= _T_1140 @[el2_lib.scala 543:17] + node _T_1141 = bits(_T_1013, 21, 0) @[el2_lib.scala 543:27] + node _T_1142 = orr(_T_1141) @[el2_lib.scala 543:35] + node _T_1143 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:44] + node _T_1144 = not(_T_1143) @[el2_lib.scala 543:40] + node _T_1145 = bits(_T_1013, 22, 22) @[el2_lib.scala 543:51] + node _T_1146 = mux(_T_1142, _T_1144, _T_1145) @[el2_lib.scala 543:23] + _T_1014[21] <= _T_1146 @[el2_lib.scala 543:17] + node _T_1147 = bits(_T_1013, 22, 0) @[el2_lib.scala 543:27] + node _T_1148 = orr(_T_1147) @[el2_lib.scala 543:35] + node _T_1149 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:44] + node _T_1150 = not(_T_1149) @[el2_lib.scala 543:40] + node _T_1151 = bits(_T_1013, 23, 23) @[el2_lib.scala 543:51] + node _T_1152 = mux(_T_1148, _T_1150, _T_1151) @[el2_lib.scala 543:23] + _T_1014[22] <= _T_1152 @[el2_lib.scala 543:17] + node _T_1153 = bits(_T_1013, 23, 0) @[el2_lib.scala 543:27] + node _T_1154 = orr(_T_1153) @[el2_lib.scala 543:35] + node _T_1155 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:44] + node _T_1156 = not(_T_1155) @[el2_lib.scala 543:40] + node _T_1157 = bits(_T_1013, 24, 24) @[el2_lib.scala 543:51] + node _T_1158 = mux(_T_1154, _T_1156, _T_1157) @[el2_lib.scala 543:23] + _T_1014[23] <= _T_1158 @[el2_lib.scala 543:17] + node _T_1159 = bits(_T_1013, 24, 0) @[el2_lib.scala 543:27] + node _T_1160 = orr(_T_1159) @[el2_lib.scala 543:35] + node _T_1161 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:44] + node _T_1162 = not(_T_1161) @[el2_lib.scala 543:40] + node _T_1163 = bits(_T_1013, 25, 25) @[el2_lib.scala 543:51] + node _T_1164 = mux(_T_1160, _T_1162, _T_1163) @[el2_lib.scala 543:23] + _T_1014[24] <= _T_1164 @[el2_lib.scala 543:17] + node _T_1165 = bits(_T_1013, 25, 0) @[el2_lib.scala 543:27] + node _T_1166 = orr(_T_1165) @[el2_lib.scala 543:35] + node _T_1167 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:44] + node _T_1168 = not(_T_1167) @[el2_lib.scala 543:40] + node _T_1169 = bits(_T_1013, 26, 26) @[el2_lib.scala 543:51] + node _T_1170 = mux(_T_1166, _T_1168, _T_1169) @[el2_lib.scala 543:23] + _T_1014[25] <= _T_1170 @[el2_lib.scala 543:17] + node _T_1171 = bits(_T_1013, 26, 0) @[el2_lib.scala 543:27] + node _T_1172 = orr(_T_1171) @[el2_lib.scala 543:35] + node _T_1173 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:44] + node _T_1174 = not(_T_1173) @[el2_lib.scala 543:40] + node _T_1175 = bits(_T_1013, 27, 27) @[el2_lib.scala 543:51] + node _T_1176 = mux(_T_1172, _T_1174, _T_1175) @[el2_lib.scala 543:23] + _T_1014[26] <= _T_1176 @[el2_lib.scala 543:17] + node _T_1177 = bits(_T_1013, 27, 0) @[el2_lib.scala 543:27] + node _T_1178 = orr(_T_1177) @[el2_lib.scala 543:35] + node _T_1179 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:44] + node _T_1180 = not(_T_1179) @[el2_lib.scala 543:40] + node _T_1181 = bits(_T_1013, 28, 28) @[el2_lib.scala 543:51] + node _T_1182 = mux(_T_1178, _T_1180, _T_1181) @[el2_lib.scala 543:23] + _T_1014[27] <= _T_1182 @[el2_lib.scala 543:17] + node _T_1183 = bits(_T_1013, 28, 0) @[el2_lib.scala 543:27] + node _T_1184 = orr(_T_1183) @[el2_lib.scala 543:35] + node _T_1185 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:44] + node _T_1186 = not(_T_1185) @[el2_lib.scala 543:40] + node _T_1187 = bits(_T_1013, 29, 29) @[el2_lib.scala 543:51] + node _T_1188 = mux(_T_1184, _T_1186, _T_1187) @[el2_lib.scala 543:23] + _T_1014[28] <= _T_1188 @[el2_lib.scala 543:17] + node _T_1189 = bits(_T_1013, 29, 0) @[el2_lib.scala 543:27] + node _T_1190 = orr(_T_1189) @[el2_lib.scala 543:35] + node _T_1191 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:44] + node _T_1192 = not(_T_1191) @[el2_lib.scala 543:40] + node _T_1193 = bits(_T_1013, 30, 30) @[el2_lib.scala 543:51] + node _T_1194 = mux(_T_1190, _T_1192, _T_1193) @[el2_lib.scala 543:23] + _T_1014[29] <= _T_1194 @[el2_lib.scala 543:17] + node _T_1195 = bits(_T_1013, 30, 0) @[el2_lib.scala 543:27] + node _T_1196 = orr(_T_1195) @[el2_lib.scala 543:35] + node _T_1197 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:44] + node _T_1198 = not(_T_1197) @[el2_lib.scala 543:40] + node _T_1199 = bits(_T_1013, 31, 31) @[el2_lib.scala 543:51] + node _T_1200 = mux(_T_1196, _T_1198, _T_1199) @[el2_lib.scala 543:23] + _T_1014[30] <= _T_1200 @[el2_lib.scala 543:17] + node _T_1201 = cat(_T_1014[2], _T_1014[1]) @[el2_lib.scala 545:14] + node _T_1202 = cat(_T_1201, _T_1014[0]) @[el2_lib.scala 545:14] + node _T_1203 = cat(_T_1014[4], _T_1014[3]) @[el2_lib.scala 545:14] + node _T_1204 = cat(_T_1014[6], _T_1014[5]) @[el2_lib.scala 545:14] + node _T_1205 = cat(_T_1204, _T_1203) @[el2_lib.scala 545:14] + node _T_1206 = cat(_T_1205, _T_1202) @[el2_lib.scala 545:14] + node _T_1207 = cat(_T_1014[8], _T_1014[7]) @[el2_lib.scala 545:14] + node _T_1208 = cat(_T_1014[10], _T_1014[9]) @[el2_lib.scala 545:14] + node _T_1209 = cat(_T_1208, _T_1207) @[el2_lib.scala 545:14] + node _T_1210 = cat(_T_1014[12], _T_1014[11]) @[el2_lib.scala 545:14] + node _T_1211 = cat(_T_1014[14], _T_1014[13]) @[el2_lib.scala 545:14] + node _T_1212 = cat(_T_1211, _T_1210) @[el2_lib.scala 545:14] + node _T_1213 = cat(_T_1212, _T_1209) @[el2_lib.scala 545:14] + node _T_1214 = cat(_T_1213, _T_1206) @[el2_lib.scala 545:14] + node _T_1215 = cat(_T_1014[16], _T_1014[15]) @[el2_lib.scala 545:14] + node _T_1216 = cat(_T_1014[18], _T_1014[17]) @[el2_lib.scala 545:14] + node _T_1217 = cat(_T_1216, _T_1215) @[el2_lib.scala 545:14] + node _T_1218 = cat(_T_1014[20], _T_1014[19]) @[el2_lib.scala 545:14] + node _T_1219 = cat(_T_1014[22], _T_1014[21]) @[el2_lib.scala 545:14] + node _T_1220 = cat(_T_1219, _T_1218) @[el2_lib.scala 545:14] + node _T_1221 = cat(_T_1220, _T_1217) @[el2_lib.scala 545:14] + node _T_1222 = cat(_T_1014[24], _T_1014[23]) @[el2_lib.scala 545:14] + node _T_1223 = cat(_T_1014[26], _T_1014[25]) @[el2_lib.scala 545:14] + node _T_1224 = cat(_T_1223, _T_1222) @[el2_lib.scala 545:14] + node _T_1225 = cat(_T_1014[28], _T_1014[27]) @[el2_lib.scala 545:14] + node _T_1226 = cat(_T_1014[30], _T_1014[29]) @[el2_lib.scala 545:14] + node _T_1227 = cat(_T_1226, _T_1225) @[el2_lib.scala 545:14] + node _T_1228 = cat(_T_1227, _T_1224) @[el2_lib.scala 545:14] + node _T_1229 = cat(_T_1228, _T_1221) @[el2_lib.scala 545:14] + node _T_1230 = cat(_T_1229, _T_1214) @[el2_lib.scala 545:14] + node _T_1231 = bits(_T_1013, 0, 0) @[el2_lib.scala 545:24] + node _T_1232 = cat(_T_1230, _T_1231) @[Cat.scala 29:58] + node _T_1233 = bits(q_ff, 31, 0) @[el2_exu_div_ctl.scala 192:104] + node q_ff_eff = mux(_T_1012, _T_1232, _T_1233) @[el2_exu_div_ctl.scala 192:21] + node _T_1234 = and(sign_ff, dividend_neg_ff) @[el2_exu_div_ctl.scala 193:31] + node _T_1235 = bits(_T_1234, 0, 0) @[el2_exu_div_ctl.scala 193:51] + node _T_1236 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:74] + wire _T_1237 : UInt<1>[31] @[el2_lib.scala 541:20] + node _T_1238 = bits(_T_1236, 0, 0) @[el2_lib.scala 543:27] + node _T_1239 = orr(_T_1238) @[el2_lib.scala 543:35] + node _T_1240 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:44] + node _T_1241 = not(_T_1240) @[el2_lib.scala 543:40] + node _T_1242 = bits(_T_1236, 1, 1) @[el2_lib.scala 543:51] + node _T_1243 = mux(_T_1239, _T_1241, _T_1242) @[el2_lib.scala 543:23] + _T_1237[0] <= _T_1243 @[el2_lib.scala 543:17] + node _T_1244 = bits(_T_1236, 1, 0) @[el2_lib.scala 543:27] + node _T_1245 = orr(_T_1244) @[el2_lib.scala 543:35] + node _T_1246 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:44] + node _T_1247 = not(_T_1246) @[el2_lib.scala 543:40] + node _T_1248 = bits(_T_1236, 2, 2) @[el2_lib.scala 543:51] + node _T_1249 = mux(_T_1245, _T_1247, _T_1248) @[el2_lib.scala 543:23] + _T_1237[1] <= _T_1249 @[el2_lib.scala 543:17] + node _T_1250 = bits(_T_1236, 2, 0) @[el2_lib.scala 543:27] + node _T_1251 = orr(_T_1250) @[el2_lib.scala 543:35] + node _T_1252 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:44] + node _T_1253 = not(_T_1252) @[el2_lib.scala 543:40] + node _T_1254 = bits(_T_1236, 3, 3) @[el2_lib.scala 543:51] + node _T_1255 = mux(_T_1251, _T_1253, _T_1254) @[el2_lib.scala 543:23] + _T_1237[2] <= _T_1255 @[el2_lib.scala 543:17] + node _T_1256 = bits(_T_1236, 3, 0) @[el2_lib.scala 543:27] + node _T_1257 = orr(_T_1256) @[el2_lib.scala 543:35] + node _T_1258 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:44] + node _T_1259 = not(_T_1258) @[el2_lib.scala 543:40] + node _T_1260 = bits(_T_1236, 4, 4) @[el2_lib.scala 543:51] + node _T_1261 = mux(_T_1257, _T_1259, _T_1260) @[el2_lib.scala 543:23] + _T_1237[3] <= _T_1261 @[el2_lib.scala 543:17] + node _T_1262 = bits(_T_1236, 4, 0) @[el2_lib.scala 543:27] + node _T_1263 = orr(_T_1262) @[el2_lib.scala 543:35] + node _T_1264 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:44] + node _T_1265 = not(_T_1264) @[el2_lib.scala 543:40] + node _T_1266 = bits(_T_1236, 5, 5) @[el2_lib.scala 543:51] + node _T_1267 = mux(_T_1263, _T_1265, _T_1266) @[el2_lib.scala 543:23] + _T_1237[4] <= _T_1267 @[el2_lib.scala 543:17] + node _T_1268 = bits(_T_1236, 5, 0) @[el2_lib.scala 543:27] + node _T_1269 = orr(_T_1268) @[el2_lib.scala 543:35] + node _T_1270 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:44] + node _T_1271 = not(_T_1270) @[el2_lib.scala 543:40] + node _T_1272 = bits(_T_1236, 6, 6) @[el2_lib.scala 543:51] + node _T_1273 = mux(_T_1269, _T_1271, _T_1272) @[el2_lib.scala 543:23] + _T_1237[5] <= _T_1273 @[el2_lib.scala 543:17] + node _T_1274 = bits(_T_1236, 6, 0) @[el2_lib.scala 543:27] + node _T_1275 = orr(_T_1274) @[el2_lib.scala 543:35] + node _T_1276 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:44] + node _T_1277 = not(_T_1276) @[el2_lib.scala 543:40] + node _T_1278 = bits(_T_1236, 7, 7) @[el2_lib.scala 543:51] + node _T_1279 = mux(_T_1275, _T_1277, _T_1278) @[el2_lib.scala 543:23] + _T_1237[6] <= _T_1279 @[el2_lib.scala 543:17] + node _T_1280 = bits(_T_1236, 7, 0) @[el2_lib.scala 543:27] + node _T_1281 = orr(_T_1280) @[el2_lib.scala 543:35] + node _T_1282 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:44] + node _T_1283 = not(_T_1282) @[el2_lib.scala 543:40] + node _T_1284 = bits(_T_1236, 8, 8) @[el2_lib.scala 543:51] + node _T_1285 = mux(_T_1281, _T_1283, _T_1284) @[el2_lib.scala 543:23] + _T_1237[7] <= _T_1285 @[el2_lib.scala 543:17] + node _T_1286 = bits(_T_1236, 8, 0) @[el2_lib.scala 543:27] + node _T_1287 = orr(_T_1286) @[el2_lib.scala 543:35] + node _T_1288 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:44] + node _T_1289 = not(_T_1288) @[el2_lib.scala 543:40] + node _T_1290 = bits(_T_1236, 9, 9) @[el2_lib.scala 543:51] + node _T_1291 = mux(_T_1287, _T_1289, _T_1290) @[el2_lib.scala 543:23] + _T_1237[8] <= _T_1291 @[el2_lib.scala 543:17] + node _T_1292 = bits(_T_1236, 9, 0) @[el2_lib.scala 543:27] + node _T_1293 = orr(_T_1292) @[el2_lib.scala 543:35] + node _T_1294 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:44] + node _T_1295 = not(_T_1294) @[el2_lib.scala 543:40] + node _T_1296 = bits(_T_1236, 10, 10) @[el2_lib.scala 543:51] + node _T_1297 = mux(_T_1293, _T_1295, _T_1296) @[el2_lib.scala 543:23] + _T_1237[9] <= _T_1297 @[el2_lib.scala 543:17] + node _T_1298 = bits(_T_1236, 10, 0) @[el2_lib.scala 543:27] + node _T_1299 = orr(_T_1298) @[el2_lib.scala 543:35] + node _T_1300 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:44] + node _T_1301 = not(_T_1300) @[el2_lib.scala 543:40] + node _T_1302 = bits(_T_1236, 11, 11) @[el2_lib.scala 543:51] + node _T_1303 = mux(_T_1299, _T_1301, _T_1302) @[el2_lib.scala 543:23] + _T_1237[10] <= _T_1303 @[el2_lib.scala 543:17] + node _T_1304 = bits(_T_1236, 11, 0) @[el2_lib.scala 543:27] + node _T_1305 = orr(_T_1304) @[el2_lib.scala 543:35] + node _T_1306 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:44] + node _T_1307 = not(_T_1306) @[el2_lib.scala 543:40] + node _T_1308 = bits(_T_1236, 12, 12) @[el2_lib.scala 543:51] + node _T_1309 = mux(_T_1305, _T_1307, _T_1308) @[el2_lib.scala 543:23] + _T_1237[11] <= _T_1309 @[el2_lib.scala 543:17] + node _T_1310 = bits(_T_1236, 12, 0) @[el2_lib.scala 543:27] + node _T_1311 = orr(_T_1310) @[el2_lib.scala 543:35] + node _T_1312 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:44] + node _T_1313 = not(_T_1312) @[el2_lib.scala 543:40] + node _T_1314 = bits(_T_1236, 13, 13) @[el2_lib.scala 543:51] + node _T_1315 = mux(_T_1311, _T_1313, _T_1314) @[el2_lib.scala 543:23] + _T_1237[12] <= _T_1315 @[el2_lib.scala 543:17] + node _T_1316 = bits(_T_1236, 13, 0) @[el2_lib.scala 543:27] + node _T_1317 = orr(_T_1316) @[el2_lib.scala 543:35] + node _T_1318 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:44] + node _T_1319 = not(_T_1318) @[el2_lib.scala 543:40] + node _T_1320 = bits(_T_1236, 14, 14) @[el2_lib.scala 543:51] + node _T_1321 = mux(_T_1317, _T_1319, _T_1320) @[el2_lib.scala 543:23] + _T_1237[13] <= _T_1321 @[el2_lib.scala 543:17] + node _T_1322 = bits(_T_1236, 14, 0) @[el2_lib.scala 543:27] + node _T_1323 = orr(_T_1322) @[el2_lib.scala 543:35] + node _T_1324 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:44] + node _T_1325 = not(_T_1324) @[el2_lib.scala 543:40] + node _T_1326 = bits(_T_1236, 15, 15) @[el2_lib.scala 543:51] + node _T_1327 = mux(_T_1323, _T_1325, _T_1326) @[el2_lib.scala 543:23] + _T_1237[14] <= _T_1327 @[el2_lib.scala 543:17] + node _T_1328 = bits(_T_1236, 15, 0) @[el2_lib.scala 543:27] + node _T_1329 = orr(_T_1328) @[el2_lib.scala 543:35] + node _T_1330 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:44] + node _T_1331 = not(_T_1330) @[el2_lib.scala 543:40] + node _T_1332 = bits(_T_1236, 16, 16) @[el2_lib.scala 543:51] + node _T_1333 = mux(_T_1329, _T_1331, _T_1332) @[el2_lib.scala 543:23] + _T_1237[15] <= _T_1333 @[el2_lib.scala 543:17] + node _T_1334 = bits(_T_1236, 16, 0) @[el2_lib.scala 543:27] + node _T_1335 = orr(_T_1334) @[el2_lib.scala 543:35] + node _T_1336 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:44] + node _T_1337 = not(_T_1336) @[el2_lib.scala 543:40] + node _T_1338 = bits(_T_1236, 17, 17) @[el2_lib.scala 543:51] + node _T_1339 = mux(_T_1335, _T_1337, _T_1338) @[el2_lib.scala 543:23] + _T_1237[16] <= _T_1339 @[el2_lib.scala 543:17] + node _T_1340 = bits(_T_1236, 17, 0) @[el2_lib.scala 543:27] + node _T_1341 = orr(_T_1340) @[el2_lib.scala 543:35] + node _T_1342 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:44] + node _T_1343 = not(_T_1342) @[el2_lib.scala 543:40] + node _T_1344 = bits(_T_1236, 18, 18) @[el2_lib.scala 543:51] + node _T_1345 = mux(_T_1341, _T_1343, _T_1344) @[el2_lib.scala 543:23] + _T_1237[17] <= _T_1345 @[el2_lib.scala 543:17] + node _T_1346 = bits(_T_1236, 18, 0) @[el2_lib.scala 543:27] + node _T_1347 = orr(_T_1346) @[el2_lib.scala 543:35] + node _T_1348 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:44] + node _T_1349 = not(_T_1348) @[el2_lib.scala 543:40] + node _T_1350 = bits(_T_1236, 19, 19) @[el2_lib.scala 543:51] + node _T_1351 = mux(_T_1347, _T_1349, _T_1350) @[el2_lib.scala 543:23] + _T_1237[18] <= _T_1351 @[el2_lib.scala 543:17] + node _T_1352 = bits(_T_1236, 19, 0) @[el2_lib.scala 543:27] + node _T_1353 = orr(_T_1352) @[el2_lib.scala 543:35] + node _T_1354 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:44] + node _T_1355 = not(_T_1354) @[el2_lib.scala 543:40] + node _T_1356 = bits(_T_1236, 20, 20) @[el2_lib.scala 543:51] + node _T_1357 = mux(_T_1353, _T_1355, _T_1356) @[el2_lib.scala 543:23] + _T_1237[19] <= _T_1357 @[el2_lib.scala 543:17] + node _T_1358 = bits(_T_1236, 20, 0) @[el2_lib.scala 543:27] + node _T_1359 = orr(_T_1358) @[el2_lib.scala 543:35] + node _T_1360 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:44] + node _T_1361 = not(_T_1360) @[el2_lib.scala 543:40] + node _T_1362 = bits(_T_1236, 21, 21) @[el2_lib.scala 543:51] + node _T_1363 = mux(_T_1359, _T_1361, _T_1362) @[el2_lib.scala 543:23] + _T_1237[20] <= _T_1363 @[el2_lib.scala 543:17] + node _T_1364 = bits(_T_1236, 21, 0) @[el2_lib.scala 543:27] + node _T_1365 = orr(_T_1364) @[el2_lib.scala 543:35] + node _T_1366 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:44] + node _T_1367 = not(_T_1366) @[el2_lib.scala 543:40] + node _T_1368 = bits(_T_1236, 22, 22) @[el2_lib.scala 543:51] + node _T_1369 = mux(_T_1365, _T_1367, _T_1368) @[el2_lib.scala 543:23] + _T_1237[21] <= _T_1369 @[el2_lib.scala 543:17] + node _T_1370 = bits(_T_1236, 22, 0) @[el2_lib.scala 543:27] + node _T_1371 = orr(_T_1370) @[el2_lib.scala 543:35] + node _T_1372 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:44] + node _T_1373 = not(_T_1372) @[el2_lib.scala 543:40] + node _T_1374 = bits(_T_1236, 23, 23) @[el2_lib.scala 543:51] + node _T_1375 = mux(_T_1371, _T_1373, _T_1374) @[el2_lib.scala 543:23] + _T_1237[22] <= _T_1375 @[el2_lib.scala 543:17] + node _T_1376 = bits(_T_1236, 23, 0) @[el2_lib.scala 543:27] + node _T_1377 = orr(_T_1376) @[el2_lib.scala 543:35] + node _T_1378 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:44] + node _T_1379 = not(_T_1378) @[el2_lib.scala 543:40] + node _T_1380 = bits(_T_1236, 24, 24) @[el2_lib.scala 543:51] + node _T_1381 = mux(_T_1377, _T_1379, _T_1380) @[el2_lib.scala 543:23] + _T_1237[23] <= _T_1381 @[el2_lib.scala 543:17] + node _T_1382 = bits(_T_1236, 24, 0) @[el2_lib.scala 543:27] + node _T_1383 = orr(_T_1382) @[el2_lib.scala 543:35] + node _T_1384 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:44] + node _T_1385 = not(_T_1384) @[el2_lib.scala 543:40] + node _T_1386 = bits(_T_1236, 25, 25) @[el2_lib.scala 543:51] + node _T_1387 = mux(_T_1383, _T_1385, _T_1386) @[el2_lib.scala 543:23] + _T_1237[24] <= _T_1387 @[el2_lib.scala 543:17] + node _T_1388 = bits(_T_1236, 25, 0) @[el2_lib.scala 543:27] + node _T_1389 = orr(_T_1388) @[el2_lib.scala 543:35] + node _T_1390 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:44] + node _T_1391 = not(_T_1390) @[el2_lib.scala 543:40] + node _T_1392 = bits(_T_1236, 26, 26) @[el2_lib.scala 543:51] + node _T_1393 = mux(_T_1389, _T_1391, _T_1392) @[el2_lib.scala 543:23] + _T_1237[25] <= _T_1393 @[el2_lib.scala 543:17] + node _T_1394 = bits(_T_1236, 26, 0) @[el2_lib.scala 543:27] + node _T_1395 = orr(_T_1394) @[el2_lib.scala 543:35] + node _T_1396 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:44] + node _T_1397 = not(_T_1396) @[el2_lib.scala 543:40] + node _T_1398 = bits(_T_1236, 27, 27) @[el2_lib.scala 543:51] + node _T_1399 = mux(_T_1395, _T_1397, _T_1398) @[el2_lib.scala 543:23] + _T_1237[26] <= _T_1399 @[el2_lib.scala 543:17] + node _T_1400 = bits(_T_1236, 27, 0) @[el2_lib.scala 543:27] + node _T_1401 = orr(_T_1400) @[el2_lib.scala 543:35] + node _T_1402 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:44] + node _T_1403 = not(_T_1402) @[el2_lib.scala 543:40] + node _T_1404 = bits(_T_1236, 28, 28) @[el2_lib.scala 543:51] + node _T_1405 = mux(_T_1401, _T_1403, _T_1404) @[el2_lib.scala 543:23] + _T_1237[27] <= _T_1405 @[el2_lib.scala 543:17] + node _T_1406 = bits(_T_1236, 28, 0) @[el2_lib.scala 543:27] + node _T_1407 = orr(_T_1406) @[el2_lib.scala 543:35] + node _T_1408 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:44] + node _T_1409 = not(_T_1408) @[el2_lib.scala 543:40] + node _T_1410 = bits(_T_1236, 29, 29) @[el2_lib.scala 543:51] + node _T_1411 = mux(_T_1407, _T_1409, _T_1410) @[el2_lib.scala 543:23] + _T_1237[28] <= _T_1411 @[el2_lib.scala 543:17] + node _T_1412 = bits(_T_1236, 29, 0) @[el2_lib.scala 543:27] + node _T_1413 = orr(_T_1412) @[el2_lib.scala 543:35] + node _T_1414 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:44] + node _T_1415 = not(_T_1414) @[el2_lib.scala 543:40] + node _T_1416 = bits(_T_1236, 30, 30) @[el2_lib.scala 543:51] + node _T_1417 = mux(_T_1413, _T_1415, _T_1416) @[el2_lib.scala 543:23] + _T_1237[29] <= _T_1417 @[el2_lib.scala 543:17] + node _T_1418 = bits(_T_1236, 30, 0) @[el2_lib.scala 543:27] + node _T_1419 = orr(_T_1418) @[el2_lib.scala 543:35] + node _T_1420 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:44] + node _T_1421 = not(_T_1420) @[el2_lib.scala 543:40] + node _T_1422 = bits(_T_1236, 31, 31) @[el2_lib.scala 543:51] + node _T_1423 = mux(_T_1419, _T_1421, _T_1422) @[el2_lib.scala 543:23] + _T_1237[30] <= _T_1423 @[el2_lib.scala 543:17] + node _T_1424 = cat(_T_1237[2], _T_1237[1]) @[el2_lib.scala 545:14] + node _T_1425 = cat(_T_1424, _T_1237[0]) @[el2_lib.scala 545:14] + node _T_1426 = cat(_T_1237[4], _T_1237[3]) @[el2_lib.scala 545:14] + node _T_1427 = cat(_T_1237[6], _T_1237[5]) @[el2_lib.scala 545:14] + node _T_1428 = cat(_T_1427, _T_1426) @[el2_lib.scala 545:14] + node _T_1429 = cat(_T_1428, _T_1425) @[el2_lib.scala 545:14] + node _T_1430 = cat(_T_1237[8], _T_1237[7]) @[el2_lib.scala 545:14] + node _T_1431 = cat(_T_1237[10], _T_1237[9]) @[el2_lib.scala 545:14] + node _T_1432 = cat(_T_1431, _T_1430) @[el2_lib.scala 545:14] + node _T_1433 = cat(_T_1237[12], _T_1237[11]) @[el2_lib.scala 545:14] + node _T_1434 = cat(_T_1237[14], _T_1237[13]) @[el2_lib.scala 545:14] + node _T_1435 = cat(_T_1434, _T_1433) @[el2_lib.scala 545:14] + node _T_1436 = cat(_T_1435, _T_1432) @[el2_lib.scala 545:14] + node _T_1437 = cat(_T_1436, _T_1429) @[el2_lib.scala 545:14] + node _T_1438 = cat(_T_1237[16], _T_1237[15]) @[el2_lib.scala 545:14] + node _T_1439 = cat(_T_1237[18], _T_1237[17]) @[el2_lib.scala 545:14] + node _T_1440 = cat(_T_1439, _T_1438) @[el2_lib.scala 545:14] + node _T_1441 = cat(_T_1237[20], _T_1237[19]) @[el2_lib.scala 545:14] + node _T_1442 = cat(_T_1237[22], _T_1237[21]) @[el2_lib.scala 545:14] + node _T_1443 = cat(_T_1442, _T_1441) @[el2_lib.scala 545:14] + node _T_1444 = cat(_T_1443, _T_1440) @[el2_lib.scala 545:14] + node _T_1445 = cat(_T_1237[24], _T_1237[23]) @[el2_lib.scala 545:14] + node _T_1446 = cat(_T_1237[26], _T_1237[25]) @[el2_lib.scala 545:14] + node _T_1447 = cat(_T_1446, _T_1445) @[el2_lib.scala 545:14] + node _T_1448 = cat(_T_1237[28], _T_1237[27]) @[el2_lib.scala 545:14] + node _T_1449 = cat(_T_1237[30], _T_1237[29]) @[el2_lib.scala 545:14] + node _T_1450 = cat(_T_1449, _T_1448) @[el2_lib.scala 545:14] + node _T_1451 = cat(_T_1450, _T_1447) @[el2_lib.scala 545:14] + node _T_1452 = cat(_T_1451, _T_1444) @[el2_lib.scala 545:14] + node _T_1453 = cat(_T_1452, _T_1437) @[el2_lib.scala 545:14] + node _T_1454 = bits(_T_1236, 0, 0) @[el2_lib.scala 545:24] + node _T_1455 = cat(_T_1453, _T_1454) @[Cat.scala 29:58] + node _T_1456 = bits(a_ff, 31, 0) @[el2_exu_div_ctl.scala 193:87] + node a_ff_eff = mux(_T_1235, _T_1455, _T_1456) @[el2_exu_div_ctl.scala 193:21] + node _T_1457 = bits(smallnum_case_ff, 0, 0) @[el2_exu_div_ctl.scala 196:22] + node _T_1458 = cat(UInt<28>("h00"), smallnum_ff) @[Cat.scala 29:58] + node _T_1459 = bits(rem_ff, 0, 0) @[el2_exu_div_ctl.scala 197:12] + node _T_1460 = eq(smallnum_case_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:6] + node _T_1461 = eq(rem_ff, UInt<1>("h00")) @[el2_exu_div_ctl.scala 198:26] + node _T_1462 = and(_T_1460, _T_1461) @[el2_exu_div_ctl.scala 198:24] + node _T_1463 = bits(_T_1462, 0, 0) @[el2_exu_div_ctl.scala 198:35] + node _T_1464 = mux(_T_1457, _T_1458, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1465 = mux(_T_1459, a_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1466 = mux(_T_1463, q_ff_eff, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1467 = or(_T_1464, _T_1465) @[Mux.scala 27:72] + node _T_1468 = or(_T_1467, _T_1466) @[Mux.scala 27:72] + wire _T_1469 : UInt<32> @[Mux.scala 27:72] + _T_1469 <= _T_1468 @[Mux.scala 27:72] + io.out <= _T_1469 @[el2_exu_div_ctl.scala 195:10] + node _T_1470 = bits(div_clken, 0, 0) @[el2_exu_div_ctl.scala 201:46] + inst rvclkhdr of rvclkhdr_23 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_1470 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + node _T_1471 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 204:41] + node _T_1472 = and(io.dp.valid, _T_1471) @[el2_exu_div_ctl.scala 204:39] + reg _T_1473 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 204:26] + _T_1473 <= _T_1472 @[el2_exu_div_ctl.scala 204:26] + valid_ff_x <= _T_1473 @[el2_exu_div_ctl.scala 204:16] + node _T_1474 = eq(io.cancel, UInt<1>("h00")) @[el2_exu_div_ctl.scala 205:35] + node _T_1475 = and(finish, _T_1474) @[el2_exu_div_ctl.scala 205:33] + reg _T_1476 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 205:25] + _T_1476 <= _T_1475 @[el2_exu_div_ctl.scala 205:25] + finish_ff <= _T_1476 @[el2_exu_div_ctl.scala 205:15] + reg _T_1477 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 206:25] + _T_1477 <= run_in @[el2_exu_div_ctl.scala 206:25] + run_state <= _T_1477 @[el2_exu_div_ctl.scala 206:15] + reg _T_1478 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 207:21] + _T_1478 <= count_in @[el2_exu_div_ctl.scala 207:21] + count <= _T_1478 @[el2_exu_div_ctl.scala 207:11] + node _T_1479 = bits(io.dividend, 31, 31) @[el2_exu_div_ctl.scala 208:45] + node _T_1480 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 208:68] + reg _T_1481 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1480 : @[Reg.scala 28:19] + _T_1481 <= _T_1479 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + dividend_neg_ff <= _T_1481 @[el2_exu_div_ctl.scala 208:21] + node _T_1482 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 209:43] + node _T_1483 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 209:66] + reg _T_1484 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1483 : @[Reg.scala 28:19] + _T_1484 <= _T_1482 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + divisor_neg_ff <= _T_1484 @[el2_exu_div_ctl.scala 209:20] + node _T_1485 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 210:53] + reg _T_1486 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1485 : @[Reg.scala 28:19] + _T_1486 <= sign_eff @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + sign_ff <= _T_1486 @[el2_exu_div_ctl.scala 210:13] + node _T_1487 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 211:53] + reg _T_1488 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1487 : @[Reg.scala 28:19] + _T_1488 <= io.dp.rem @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + rem_ff <= _T_1488 @[el2_exu_div_ctl.scala 211:12] + reg _T_1489 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 212:32] + _T_1489 <= smallnum_case @[el2_exu_div_ctl.scala 212:32] + smallnum_case_ff <= _T_1489 @[el2_exu_div_ctl.scala 212:22] + reg _T_1490 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 213:27] + _T_1490 <= smallnum @[el2_exu_div_ctl.scala 213:27] + smallnum_ff <= _T_1490 @[el2_exu_div_ctl.scala 213:17] + reg _T_1491 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 214:32] + _T_1491 <= shortq_enable @[el2_exu_div_ctl.scala 214:32] + shortq_enable_ff <= _T_1491 @[el2_exu_div_ctl.scala 214:22] + reg _T_1492 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_exu_div_ctl.scala 215:31] + _T_1492 <= shortq_shift @[el2_exu_div_ctl.scala 215:31] + shortq_shift_xx <= _T_1492 @[el2_exu_div_ctl.scala 215:21] + node _T_1493 = bits(qff_enable, 0, 0) @[el2_exu_div_ctl.scala 217:35] + inst rvclkhdr_1 of rvclkhdr_24 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_1493 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1494 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1494 <= q_in @[el2_lib.scala 514:16] + q_ff <= _T_1494 @[el2_exu_div_ctl.scala 217:8] + node _T_1495 = bits(aff_enable, 0, 0) @[el2_exu_div_ctl.scala 218:35] + inst rvclkhdr_2 of rvclkhdr_25 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_1495 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1496 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1496 <= a_in @[el2_lib.scala 514:16] + a_ff <= _T_1496 @[el2_exu_div_ctl.scala 218:8] + node _T_1497 = eq(io.dp.unsign, UInt<1>("h00")) @[el2_exu_div_ctl.scala 219:22] + node _T_1498 = bits(io.divisor, 31, 31) @[el2_exu_div_ctl.scala 219:48] + node _T_1499 = and(_T_1497, _T_1498) @[el2_exu_div_ctl.scala 219:36] + node _T_1500 = cat(_T_1499, io.divisor) @[Cat.scala 29:58] + node _T_1501 = bits(io.dp.valid, 0, 0) @[el2_exu_div_ctl.scala 219:79] + inst rvclkhdr_3 of rvclkhdr_26 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_1501 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1502 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1502 <= _T_1500 @[el2_lib.scala 514:16] + m_ff <= _T_1502 @[el2_exu_div_ctl.scala 219:8] + + module el2_exu : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dec_data_en : UInt<2>, flip dec_ctl_en : UInt<2>, flip dbg_cmd_wrdata : UInt<32>, flip i0_ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip dec_debug_wdata_rs1_d : UInt<1>, flip dec_i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip i0_predict_fghr_d : UInt<8>, flip i0_predict_index_d : UInt<8>, flip i0_predict_btag_d : UInt<5>, flip dec_i0_rs1_en_d : UInt<1>, flip dec_i0_rs2_en_d : UInt<1>, flip gpr_i0_rs1_d : UInt<32>, flip gpr_i0_rs2_d : UInt<32>, flip dec_i0_immed_d : UInt<32>, flip dec_i0_rs1_bypass_data_d : UInt<32>, flip dec_i0_rs2_bypass_data_d : UInt<32>, flip dec_i0_br_immed_d : UInt<12>, flip dec_i0_alu_decode_d : UInt<1>, flip dec_i0_select_pc_d : UInt<1>, flip dec_i0_pc_d : UInt<31>, flip dec_i0_rs1_bypass_en_d : UInt<2>, flip dec_i0_rs2_bypass_en_d : UInt<2>, flip dec_csr_ren_d : UInt<1>, flip mul_p : {valid : UInt<1>, rs1_sign : UInt<1>, rs2_sign : UInt<1>, low : UInt<1>, bext : UInt<1>, bdep : UInt<1>, clmul : UInt<1>, clmulh : UInt<1>, clmulr : UInt<1>, grev : UInt<1>, shfl : UInt<1>, unshfl : UInt<1>, crc32_b : UInt<1>, crc32_h : UInt<1>, crc32_w : UInt<1>, crc32c_b : UInt<1>, crc32c_h : UInt<1>, crc32c_w : UInt<1>, bfp : UInt<1>}, flip div_p : {valid : UInt<1>, unsign : UInt<1>, rem : UInt<1>}, flip dec_div_cancel : UInt<1>, flip pred_correct_npc_x : UInt<31>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_flush_path_r : UInt<31>, flip dec_extint_stall : UInt<1>, flip dec_tlu_meihap : UInt<30>, exu_lsu_rs1_d : UInt<32>, exu_lsu_rs2_d : UInt<32>, exu_flush_final : UInt<1>, exu_flush_path_final : UInt<31>, exu_i0_result_x : UInt<32>, exu_i0_pc_x : UInt<31>, exu_csr_rs1_x : UInt<32>, exu_npc_r : UInt<31>, exu_i0_br_hist_r : UInt<2>, exu_i0_br_error_r : UInt<1>, exu_i0_br_start_error_r : UInt<1>, exu_i0_br_index_r : UInt<8>, exu_i0_br_valid_r : UInt<1>, exu_i0_br_mp_r : UInt<1>, exu_i0_br_middle_r : UInt<1>, exu_i0_br_fghr_r : UInt<8>, exu_i0_br_way_r : UInt<1>, exu_mp_pkt : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, exu_mp_eghr : UInt<8>, exu_mp_fghr : UInt<8>, exu_mp_index : UInt<8>, exu_mp_btag : UInt<5>, exu_pmu_i0_br_misp : UInt<1>, exu_pmu_i0_br_ataken : UInt<1>, exu_pmu_i0_pc4 : UInt<1>, exu_div_result : UInt<32>, exu_div_wren : UInt<1>} + + wire ghr_x_ns : UInt<8> @[el2_exu.scala 13:47] + wire ghr_d_ns : UInt<8> @[el2_exu.scala 14:47] + wire ghr_d : UInt<8> @[el2_exu.scala 15:55] + wire i0_taken_d : UInt<1> @[el2_exu.scala 16:54] + wire mul_valid_x : UInt<1> @[el2_exu.scala 17:54] + wire i0_valid_d : UInt<1> @[el2_exu.scala 18:54] + wire flush_lower_ff : UInt<1> @[el2_exu.scala 19:46] + wire data_gate_en : UInt<1> @[el2_exu.scala 20:46] + wire csr_rs1_in_d : UInt<32> @[el2_exu.scala 21:46] + wire i0_predict_newp_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 22:46] + wire i0_flush_path_d : UInt<31> @[el2_exu.scala 23:46] + wire i0_predict_p_d : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 24:46] + wire i0_pp_r : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 25:54] + wire i0_predict_p_x : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 26:46] + wire final_predict_mp : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 27:38] + wire pred_correct_npc_r : UInt<32> @[el2_exu.scala 28:46] + wire i0_pred_correct_upper_d : UInt<1> @[el2_exu.scala 29:38] + wire i0_flush_upper_d : UInt<1> @[el2_exu.scala 30:38] + io.exu_mp_pkt.prett <= UInt<1>("h00") @[el2_exu.scala 31:41] + io.exu_mp_pkt.br_start_error <= UInt<1>("h00") @[el2_exu.scala 32:31] + io.exu_mp_pkt.br_error <= UInt<1>("h00") @[el2_exu.scala 33:41] + io.exu_mp_pkt.valid <= UInt<1>("h00") @[el2_exu.scala 34:41] + i0_pp_r.toffset <= UInt<1>("h00") @[el2_exu.scala 35:19] + node x_data_en = bits(io.dec_data_en, 1, 1) @[el2_exu.scala 37:49] + node r_data_en = bits(io.dec_data_en, 0, 0) @[el2_exu.scala 38:49] + node x_ctl_en = bits(io.dec_ctl_en, 1, 1) @[el2_exu.scala 39:48] + node r_ctl_en = bits(io.dec_ctl_en, 0, 0) @[el2_exu.scala 40:48] + node _T = cat(io.i0_predict_fghr_d, io.i0_predict_index_d) @[Cat.scala 29:58] + node predpipe_d = cat(_T, io.i0_predict_btag_d) @[Cat.scala 29:58] + node _T_1 = bits(x_data_en, 0, 0) @[el2_exu.scala 44:67] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_1 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_path_x : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_path_x <= i0_flush_path_d @[el2_lib.scala 514:16] + node _T_2 = bits(x_data_en, 0, 0) @[el2_exu.scala 45:73] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_2 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_3 <= csr_rs1_in_d @[el2_lib.scala 514:16] + io.exu_csr_rs1_x <= _T_3 @[el2_exu.scala 45:41] + node _T_4 = bits(x_data_en, 0, 0) @[el2_exu.scala 46:83] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 518:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_2.io.en <= _T_4 @[el2_lib.scala 521:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_5 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_lib.scala 524:33] + _T_5.way <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] + _T_5.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_5.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_5.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_5.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_6 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, rvclkhdr_2.io.l1clk with : (reset => (reset, _T_5)) @[el2_lib.scala 524:16] + _T_6.way <= i0_predict_p_d.way @[el2_lib.scala 524:16] + _T_6.pja <= i0_predict_p_d.pja @[el2_lib.scala 524:16] + _T_6.pret <= i0_predict_p_d.pret @[el2_lib.scala 524:16] + _T_6.pcall <= i0_predict_p_d.pcall @[el2_lib.scala 524:16] + _T_6.prett <= i0_predict_p_d.prett @[el2_lib.scala 524:16] + _T_6.br_start_error <= i0_predict_p_d.br_start_error @[el2_lib.scala 524:16] + _T_6.br_error <= i0_predict_p_d.br_error @[el2_lib.scala 524:16] + _T_6.valid <= i0_predict_p_d.valid @[el2_lib.scala 524:16] + _T_6.toffset <= i0_predict_p_d.toffset @[el2_lib.scala 524:16] + _T_6.hist <= i0_predict_p_d.hist @[el2_lib.scala 524:16] + _T_6.pc4 <= i0_predict_p_d.pc4 @[el2_lib.scala 524:16] + _T_6.boffset <= i0_predict_p_d.boffset @[el2_lib.scala 524:16] + _T_6.ataken <= i0_predict_p_d.ataken @[el2_lib.scala 524:16] + _T_6.misp <= i0_predict_p_d.misp @[el2_lib.scala 524:16] + i0_predict_p_x.way <= _T_6.way @[el2_exu.scala 46:49] + i0_predict_p_x.pja <= _T_6.pja @[el2_exu.scala 46:49] + i0_predict_p_x.pret <= _T_6.pret @[el2_exu.scala 46:49] + i0_predict_p_x.pcall <= _T_6.pcall @[el2_exu.scala 46:49] + i0_predict_p_x.prett <= _T_6.prett @[el2_exu.scala 46:49] + i0_predict_p_x.br_start_error <= _T_6.br_start_error @[el2_exu.scala 46:49] + i0_predict_p_x.br_error <= _T_6.br_error @[el2_exu.scala 46:49] + i0_predict_p_x.valid <= _T_6.valid @[el2_exu.scala 46:49] + i0_predict_p_x.toffset <= _T_6.toffset @[el2_exu.scala 46:49] + i0_predict_p_x.hist <= _T_6.hist @[el2_exu.scala 46:49] + i0_predict_p_x.pc4 <= _T_6.pc4 @[el2_exu.scala 46:49] + i0_predict_p_x.boffset <= _T_6.boffset @[el2_exu.scala 46:49] + i0_predict_p_x.ataken <= _T_6.ataken @[el2_exu.scala 46:49] + i0_predict_p_x.misp <= _T_6.misp @[el2_exu.scala 46:49] + node _T_7 = bits(x_data_en, 0, 0) @[el2_exu.scala 47:70] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_7 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg predpipe_x : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + predpipe_x <= predpipe_d @[el2_lib.scala 514:16] + node _T_8 = bits(r_data_en, 0, 0) @[el2_exu.scala 48:79] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_8 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg predpipe_r : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + predpipe_r <= predpipe_x @[el2_lib.scala 514:16] + node _T_9 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 49:76] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_9 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg ghr_x : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + ghr_x <= ghr_x_ns @[el2_lib.scala 514:16] + node _T_10 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 50:75] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_10 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_pred_correct_upper_x : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pred_correct_upper_x <= i0_pred_correct_upper_d @[el2_lib.scala 514:16] + node _T_11 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 51:68] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_11 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_upper_x : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_upper_x <= i0_flush_upper_d @[el2_lib.scala 514:16] + node _T_12 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 52:78] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= _T_12 @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_taken_x : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_taken_x <= i0_taken_d @[el2_lib.scala 514:16] + node _T_13 = bits(x_ctl_en, 0, 0) @[el2_exu.scala 53:78] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= _T_13 @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_valid_x : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_valid_x <= i0_valid_d @[el2_lib.scala 514:16] + node _T_14 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 54:64] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 518:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 520:18] + rvclkhdr_10.io.en <= _T_14 @[el2_lib.scala 521:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 522:24] + wire _T_15 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_lib.scala 524:33] + _T_15.way <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pja <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pret <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.pcall <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.prett <= UInt<31>("h00") @[el2_lib.scala 524:33] + _T_15.br_start_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.br_error <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.valid <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.toffset <= UInt<12>("h00") @[el2_lib.scala 524:33] + _T_15.hist <= UInt<2>("h00") @[el2_lib.scala 524:33] + _T_15.pc4 <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.boffset <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.ataken <= UInt<1>("h00") @[el2_lib.scala 524:33] + _T_15.misp <= UInt<1>("h00") @[el2_lib.scala 524:33] + reg _T_16 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, rvclkhdr_10.io.l1clk with : (reset => (reset, _T_15)) @[el2_lib.scala 524:16] + _T_16.way <= i0_predict_p_x.way @[el2_lib.scala 524:16] + _T_16.pja <= i0_predict_p_x.pja @[el2_lib.scala 524:16] + _T_16.pret <= i0_predict_p_x.pret @[el2_lib.scala 524:16] + _T_16.pcall <= i0_predict_p_x.pcall @[el2_lib.scala 524:16] + _T_16.prett <= i0_predict_p_x.prett @[el2_lib.scala 524:16] + _T_16.br_start_error <= i0_predict_p_x.br_start_error @[el2_lib.scala 524:16] + _T_16.br_error <= i0_predict_p_x.br_error @[el2_lib.scala 524:16] + _T_16.valid <= i0_predict_p_x.valid @[el2_lib.scala 524:16] + _T_16.toffset <= i0_predict_p_x.toffset @[el2_lib.scala 524:16] + _T_16.hist <= i0_predict_p_x.hist @[el2_lib.scala 524:16] + _T_16.pc4 <= i0_predict_p_x.pc4 @[el2_lib.scala 524:16] + _T_16.boffset <= i0_predict_p_x.boffset @[el2_lib.scala 524:16] + _T_16.ataken <= i0_predict_p_x.ataken @[el2_lib.scala 524:16] + _T_16.misp <= i0_predict_p_x.misp @[el2_lib.scala 524:16] + i0_pp_r.way <= _T_16.way @[el2_exu.scala 54:31] + i0_pp_r.pja <= _T_16.pja @[el2_exu.scala 54:31] + i0_pp_r.pret <= _T_16.pret @[el2_exu.scala 54:31] + i0_pp_r.pcall <= _T_16.pcall @[el2_exu.scala 54:31] + i0_pp_r.prett <= _T_16.prett @[el2_exu.scala 54:31] + i0_pp_r.br_start_error <= _T_16.br_start_error @[el2_exu.scala 54:31] + i0_pp_r.br_error <= _T_16.br_error @[el2_exu.scala 54:31] + i0_pp_r.valid <= _T_16.valid @[el2_exu.scala 54:31] + i0_pp_r.toffset <= _T_16.toffset @[el2_exu.scala 54:31] + i0_pp_r.hist <= _T_16.hist @[el2_exu.scala 54:31] + i0_pp_r.pc4 <= _T_16.pc4 @[el2_exu.scala 54:31] + i0_pp_r.boffset <= _T_16.boffset @[el2_exu.scala 54:31] + i0_pp_r.ataken <= _T_16.ataken @[el2_exu.scala 54:31] + i0_pp_r.misp <= _T_16.misp @[el2_exu.scala 54:31] + node _T_17 = bits(io.pred_correct_npc_x, 5, 0) @[el2_exu.scala 55:70] + node _T_18 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 55:86] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= _T_18 @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg pred_temp1 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + pred_temp1 <= _T_17 @[el2_lib.scala 514:16] + node _T_19 = bits(r_ctl_en, 0, 0) @[el2_exu.scala 56:75] + inst rvclkhdr_12 of rvclkhdr_12 @[el2_lib.scala 508:23] + rvclkhdr_12.clock <= clock + rvclkhdr_12.reset <= reset + rvclkhdr_12.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_12.io.en <= _T_19 @[el2_lib.scala 511:17] + rvclkhdr_12.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_pred_correct_upper_r : UInt, rvclkhdr_12.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_pred_correct_upper_r <= i0_pred_correct_upper_x @[el2_lib.scala 514:16] + node _T_20 = bits(r_data_en, 0, 0) @[el2_exu.scala 57:68] + inst rvclkhdr_13 of rvclkhdr_13 @[el2_lib.scala 508:23] + rvclkhdr_13.clock <= clock + rvclkhdr_13.reset <= reset + rvclkhdr_13.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_13.io.en <= _T_20 @[el2_lib.scala 511:17] + rvclkhdr_13.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg i0_flush_path_upper_r : UInt, rvclkhdr_13.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + i0_flush_path_upper_r <= i0_flush_path_x @[el2_lib.scala 514:16] + node _T_21 = bits(io.pred_correct_npc_x, 30, 6) @[el2_exu.scala 58:78] + node _T_22 = bits(r_data_en, 0, 0) @[el2_exu.scala 58:96] + inst rvclkhdr_14 of rvclkhdr_14 @[el2_lib.scala 508:23] + rvclkhdr_14.clock <= clock + rvclkhdr_14.reset <= reset + rvclkhdr_14.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_14.io.en <= _T_22 @[el2_lib.scala 511:17] + rvclkhdr_14.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg pred_temp2 : UInt, rvclkhdr_14.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + pred_temp2 <= _T_21 @[el2_lib.scala 514:16] + node _T_23 = cat(pred_temp2, pred_temp1) @[Cat.scala 29:58] + pred_correct_npc_r <= _T_23 @[el2_exu.scala 59:41] + node _T_24 = eq(UInt<10>("h0200"), UInt<6>("h020")) @[el2_exu.scala 61:24] + node _T_25 = eq(UInt<10>("h0200"), UInt<7>("h040")) @[el2_exu.scala 61:50] + node _T_26 = or(_T_24, _T_25) @[el2_exu.scala 61:32] + when _T_26 : @[el2_exu.scala 61:58] + node _T_27 = bits(data_gate_en, 0, 0) @[el2_exu.scala 62:71] + reg _T_28 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_27 : @[Reg.scala 28:19] + _T_28 <= ghr_d_ns @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ghr_d <= _T_28 @[el2_exu.scala 62:33] + node _T_29 = bits(data_gate_en, 0, 0) @[el2_exu.scala 63:69] + reg _T_30 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_29 : @[Reg.scala 28:19] + _T_30 <= io.mul_p.valid @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + mul_valid_x <= _T_30 @[el2_exu.scala 63:25] + node _T_31 = bits(data_gate_en, 0, 0) @[el2_exu.scala 64:79] + reg _T_32 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_31 : @[Reg.scala 28:19] + _T_32 <= io.dec_tlu_flush_lower_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + flush_lower_ff <= _T_32 @[el2_exu.scala 64:25] + skip @[el2_exu.scala 61:58] + else : @[el2_exu.scala 65:14] + node _T_33 = bits(data_gate_en, 0, 0) @[el2_exu.scala 66:65] + inst rvclkhdr_15 of rvclkhdr_15 @[el2_lib.scala 508:23] + rvclkhdr_15.clock <= clock + rvclkhdr_15.reset <= reset + rvclkhdr_15.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_15.io.en <= _T_33 @[el2_lib.scala 511:17] + rvclkhdr_15.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_34 : UInt, rvclkhdr_15.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_34 <= ghr_d_ns @[el2_lib.scala 514:16] + ghr_d <= _T_34 @[el2_exu.scala 66:33] + node _T_35 = bits(data_gate_en, 0, 0) @[el2_exu.scala 67:63] + inst rvclkhdr_16 of rvclkhdr_16 @[el2_lib.scala 508:23] + rvclkhdr_16.clock <= clock + rvclkhdr_16.reset <= reset + rvclkhdr_16.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_16.io.en <= _T_35 @[el2_lib.scala 511:17] + rvclkhdr_16.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_36 : UInt, rvclkhdr_16.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_36 <= io.mul_p.valid @[el2_lib.scala 514:16] + mul_valid_x <= _T_36 @[el2_exu.scala 67:25] + node _T_37 = bits(data_gate_en, 0, 0) @[el2_exu.scala 68:73] + inst rvclkhdr_17 of rvclkhdr_17 @[el2_lib.scala 508:23] + rvclkhdr_17.clock <= clock + rvclkhdr_17.reset <= reset + rvclkhdr_17.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_17.io.en <= _T_37 @[el2_lib.scala 511:17] + rvclkhdr_17.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_38 : UInt, rvclkhdr_17.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_38 <= io.dec_tlu_flush_lower_r @[el2_lib.scala 514:16] + flush_lower_ff <= _T_38 @[el2_exu.scala 68:25] + skip @[el2_exu.scala 65:14] + node _T_39 = neq(ghr_d_ns, ghr_d) @[el2_exu.scala 72:39] + node _T_40 = neq(io.mul_p.valid, mul_valid_x) @[el2_exu.scala 72:70] + node _T_41 = or(_T_39, _T_40) @[el2_exu.scala 72:50] + node _T_42 = neq(io.dec_tlu_flush_lower_r, flush_lower_ff) @[el2_exu.scala 72:116] + node _T_43 = or(_T_41, _T_42) @[el2_exu.scala 72:87] + data_gate_en <= _T_43 @[el2_exu.scala 72:25] + node _T_44 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 73:61] + node _T_45 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 73:92] + node i0_rs1_bypass_en_d = or(_T_44, _T_45) @[el2_exu.scala 73:65] + node _T_46 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 74:61] + node _T_47 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 74:92] + node i0_rs2_bypass_en_d = or(_T_46, _T_47) @[el2_exu.scala 74:65] + node _T_48 = bits(io.dec_i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 77:30] + node _T_49 = bits(_T_48, 0, 0) @[el2_exu.scala 77:34] + node _T_50 = bits(io.dec_i0_rs1_bypass_en_d, 1, 1) @[el2_exu.scala 78:30] + node _T_51 = bits(_T_50, 0, 0) @[el2_exu.scala 78:34] + node _T_52 = mux(_T_49, io.dec_i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_53 = mux(_T_51, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_54 = or(_T_52, _T_53) @[Mux.scala 27:72] + wire i0_rs1_bypass_data_d : UInt<32> @[Mux.scala 27:72] + i0_rs1_bypass_data_d <= _T_54 @[Mux.scala 27:72] + node _T_55 = bits(io.dec_i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 82:30] + node _T_56 = bits(_T_55, 0, 0) @[el2_exu.scala 82:34] + node _T_57 = bits(io.dec_i0_rs2_bypass_en_d, 1, 1) @[el2_exu.scala 83:30] + node _T_58 = bits(_T_57, 0, 0) @[el2_exu.scala 83:34] + node _T_59 = mux(_T_56, io.dec_i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_60 = mux(_T_58, io.exu_i0_result_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_61 = or(_T_59, _T_60) @[Mux.scala 27:72] + wire i0_rs2_bypass_data_d : UInt<32> @[Mux.scala 27:72] + i0_rs2_bypass_data_d <= _T_61 @[Mux.scala 27:72] + node _T_62 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 87:24] + node _T_63 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 88:6] + node _T_64 = and(_T_63, io.dec_i0_select_pc_d) @[el2_exu.scala 88:26] + node _T_65 = bits(_T_64, 0, 0) @[el2_exu.scala 88:52] + node _T_66 = cat(io.dec_i0_pc_d, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_67 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 89:6] + node _T_68 = and(_T_67, io.dec_debug_wdata_rs1_d) @[el2_exu.scala 89:26] + node _T_69 = bits(_T_68, 0, 0) @[el2_exu.scala 89:55] + node _T_70 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 90:6] + node _T_71 = not(io.dec_debug_wdata_rs1_d) @[el2_exu.scala 90:28] + node _T_72 = and(_T_70, _T_71) @[el2_exu.scala 90:26] + node _T_73 = and(_T_72, io.dec_i0_rs1_en_d) @[el2_exu.scala 90:54] + node _T_74 = bits(_T_73, 0, 0) @[el2_exu.scala 90:76] + node _T_75 = mux(_T_62, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_76 = mux(_T_65, _T_66, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_77 = mux(_T_69, io.dbg_cmd_wrdata, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_78 = mux(_T_74, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_79 = or(_T_75, _T_76) @[Mux.scala 27:72] + node _T_80 = or(_T_79, _T_77) @[Mux.scala 27:72] + node _T_81 = or(_T_80, _T_78) @[Mux.scala 27:72] + wire i0_rs1_d : UInt<32> @[Mux.scala 27:72] + i0_rs1_d <= _T_81 @[Mux.scala 27:72] + node _T_82 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 94:6] + node _T_83 = and(_T_82, io.dec_i0_rs2_en_d) @[el2_exu.scala 94:26] + node _T_84 = bits(_T_83, 0, 0) @[el2_exu.scala 94:48] + node _T_85 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 95:6] + node _T_86 = bits(_T_85, 0, 0) @[el2_exu.scala 95:27] + node _T_87 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 96:26] + node _T_88 = mux(_T_84, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_89 = mux(_T_86, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_90 = mux(_T_87, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_91 = or(_T_88, _T_89) @[Mux.scala 27:72] + node _T_92 = or(_T_91, _T_90) @[Mux.scala 27:72] + wire i0_rs2_d : UInt<32> @[Mux.scala 27:72] + i0_rs2_d <= _T_92 @[Mux.scala 27:72] + node _T_93 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 101:6] + node _T_94 = not(io.dec_extint_stall) @[el2_exu.scala 101:28] + node _T_95 = and(_T_93, _T_94) @[el2_exu.scala 101:26] + node _T_96 = and(_T_95, io.dec_i0_rs1_en_d) @[el2_exu.scala 101:49] + node _T_97 = bits(_T_96, 0, 0) @[el2_exu.scala 101:71] + node _T_98 = not(io.dec_extint_stall) @[el2_exu.scala 102:27] + node _T_99 = and(i0_rs1_bypass_en_d, _T_98) @[el2_exu.scala 102:25] + node _T_100 = bits(_T_99, 0, 0) @[el2_exu.scala 102:49] + node _T_101 = bits(io.dec_extint_stall, 0, 0) @[el2_exu.scala 103:27] + node _T_102 = cat(io.dec_tlu_meihap, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_103 = mux(_T_97, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_104 = mux(_T_100, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_105 = mux(_T_101, _T_102, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_106 = or(_T_103, _T_104) @[Mux.scala 27:72] + node _T_107 = or(_T_106, _T_105) @[Mux.scala 27:72] + wire _T_108 : UInt<32> @[Mux.scala 27:72] + _T_108 <= _T_107 @[Mux.scala 27:72] + io.exu_lsu_rs1_d <= _T_108 @[el2_exu.scala 100:19] + node _T_109 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 107:6] + node _T_110 = not(io.dec_extint_stall) @[el2_exu.scala 107:28] + node _T_111 = and(_T_109, _T_110) @[el2_exu.scala 107:26] + node _T_112 = and(_T_111, io.dec_i0_rs2_en_d) @[el2_exu.scala 107:49] + node _T_113 = bits(_T_112, 0, 0) @[el2_exu.scala 107:71] + node _T_114 = not(io.dec_extint_stall) @[el2_exu.scala 108:27] + node _T_115 = and(i0_rs2_bypass_en_d, _T_114) @[el2_exu.scala 108:25] + node _T_116 = bits(_T_115, 0, 0) @[el2_exu.scala 108:49] + node _T_117 = mux(_T_113, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_118 = mux(_T_116, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_119 = or(_T_117, _T_118) @[Mux.scala 27:72] + wire _T_120 : UInt<32> @[Mux.scala 27:72] + _T_120 <= _T_119 @[Mux.scala 27:72] + io.exu_lsu_rs2_d <= _T_120 @[el2_exu.scala 106:19] + node _T_121 = not(i0_rs1_bypass_en_d) @[el2_exu.scala 112:6] + node _T_122 = and(_T_121, io.dec_i0_rs1_en_d) @[el2_exu.scala 112:26] + node _T_123 = bits(_T_122, 0, 0) @[el2_exu.scala 112:48] + node _T_124 = bits(i0_rs1_bypass_en_d, 0, 0) @[el2_exu.scala 113:26] + node _T_125 = mux(_T_123, io.gpr_i0_rs1_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_126 = mux(_T_124, i0_rs1_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_127 = or(_T_125, _T_126) @[Mux.scala 27:72] + wire muldiv_rs1_d : UInt<32> @[Mux.scala 27:72] + muldiv_rs1_d <= _T_127 @[Mux.scala 27:72] + node _T_128 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 117:6] + node _T_129 = and(_T_128, io.dec_i0_rs2_en_d) @[el2_exu.scala 117:26] + node _T_130 = bits(_T_129, 0, 0) @[el2_exu.scala 117:48] + node _T_131 = not(i0_rs2_bypass_en_d) @[el2_exu.scala 118:6] + node _T_132 = bits(_T_131, 0, 0) @[el2_exu.scala 118:27] + node _T_133 = bits(i0_rs2_bypass_en_d, 0, 0) @[el2_exu.scala 119:26] + node _T_134 = mux(_T_130, io.gpr_i0_rs2_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_135 = mux(_T_132, io.dec_i0_immed_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_136 = mux(_T_133, i0_rs2_bypass_data_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_137 = or(_T_134, _T_135) @[Mux.scala 27:72] + node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72] + wire muldiv_rs2_d : UInt<32> @[Mux.scala 27:72] + muldiv_rs2_d <= _T_138 @[Mux.scala 27:72] + node _T_139 = bits(io.dec_csr_ren_d, 0, 0) @[el2_exu.scala 122:47] + node _T_140 = mux(_T_139, i0_rs1_d, io.exu_csr_rs1_x) @[el2_exu.scala 122:28] + csr_rs1_in_d <= _T_140 @[el2_exu.scala 122:22] + inst i_alu of el2_exu_alu_ctl @[el2_exu.scala 125:19] + i_alu.clock <= clock + i_alu.reset <= reset + i_alu.io.scan_mode <= io.scan_mode @[el2_exu.scala 126:33] + i_alu.io.enable <= x_ctl_en @[el2_exu.scala 127:41] + i_alu.io.pp_in.way <= i0_predict_newp_d.way @[el2_exu.scala 128:41] + i_alu.io.pp_in.pja <= i0_predict_newp_d.pja @[el2_exu.scala 128:41] + i_alu.io.pp_in.pret <= i0_predict_newp_d.pret @[el2_exu.scala 128:41] + i_alu.io.pp_in.pcall <= i0_predict_newp_d.pcall @[el2_exu.scala 128:41] + i_alu.io.pp_in.prett <= i0_predict_newp_d.prett @[el2_exu.scala 128:41] + i_alu.io.pp_in.br_start_error <= i0_predict_newp_d.br_start_error @[el2_exu.scala 128:41] + i_alu.io.pp_in.br_error <= i0_predict_newp_d.br_error @[el2_exu.scala 128:41] + i_alu.io.pp_in.valid <= i0_predict_newp_d.valid @[el2_exu.scala 128:41] + i_alu.io.pp_in.toffset <= i0_predict_newp_d.toffset @[el2_exu.scala 128:41] + i_alu.io.pp_in.hist <= i0_predict_newp_d.hist @[el2_exu.scala 128:41] + i_alu.io.pp_in.pc4 <= i0_predict_newp_d.pc4 @[el2_exu.scala 128:41] + i_alu.io.pp_in.boffset <= i0_predict_newp_d.boffset @[el2_exu.scala 128:41] + i_alu.io.pp_in.ataken <= i0_predict_newp_d.ataken @[el2_exu.scala 128:41] + i_alu.io.pp_in.misp <= i0_predict_newp_d.misp @[el2_exu.scala 128:41] + i_alu.io.valid_in <= io.dec_i0_alu_decode_d @[el2_exu.scala 129:33] + i_alu.io.flush_upper_x <= i0_flush_upper_x @[el2_exu.scala 130:33] + i_alu.io.flush_lower_r <= io.dec_tlu_flush_lower_r @[el2_exu.scala 131:33] + node _T_141 = asSInt(i0_rs1_d) @[el2_exu.scala 132:44] + i_alu.io.a_in <= _T_141 @[el2_exu.scala 132:33] + i_alu.io.b_in <= i0_rs2_d @[el2_exu.scala 133:33] + i_alu.io.pc_in <= io.dec_i0_pc_d @[el2_exu.scala 134:41] + i_alu.io.brimm_in <= io.dec_i0_br_immed_d @[el2_exu.scala 135:33] + i_alu.io.ap.csr_imm <= io.i0_ap.csr_imm @[el2_exu.scala 136:41] + i_alu.io.ap.csr_write <= io.i0_ap.csr_write @[el2_exu.scala 136:41] + i_alu.io.ap.predict_nt <= io.i0_ap.predict_nt @[el2_exu.scala 136:41] + i_alu.io.ap.predict_t <= io.i0_ap.predict_t @[el2_exu.scala 136:41] + i_alu.io.ap.jal <= io.i0_ap.jal @[el2_exu.scala 136:41] + i_alu.io.ap.unsign <= io.i0_ap.unsign @[el2_exu.scala 136:41] + i_alu.io.ap.slt <= io.i0_ap.slt @[el2_exu.scala 136:41] + i_alu.io.ap.sub <= io.i0_ap.sub @[el2_exu.scala 136:41] + i_alu.io.ap.add <= io.i0_ap.add @[el2_exu.scala 136:41] + i_alu.io.ap.bge <= io.i0_ap.bge @[el2_exu.scala 136:41] + i_alu.io.ap.blt <= io.i0_ap.blt @[el2_exu.scala 136:41] + i_alu.io.ap.bne <= io.i0_ap.bne @[el2_exu.scala 136:41] + i_alu.io.ap.beq <= io.i0_ap.beq @[el2_exu.scala 136:41] + i_alu.io.ap.sra <= io.i0_ap.sra @[el2_exu.scala 136:41] + i_alu.io.ap.srl <= io.i0_ap.srl @[el2_exu.scala 136:41] + i_alu.io.ap.sll <= io.i0_ap.sll @[el2_exu.scala 136:41] + i_alu.io.ap.lxor <= io.i0_ap.lxor @[el2_exu.scala 136:41] + i_alu.io.ap.lor <= io.i0_ap.lor @[el2_exu.scala 136:41] + i_alu.io.ap.land <= io.i0_ap.land @[el2_exu.scala 136:41] + i_alu.io.csr_ren_in <= io.dec_csr_ren_d @[el2_exu.scala 137:33] + i0_flush_upper_d <= i_alu.io.flush_upper_out @[el2_exu.scala 139:33] + io.exu_flush_final <= i_alu.io.flush_final_out @[el2_exu.scala 140:33] + i0_flush_path_d <= i_alu.io.flush_path_out @[el2_exu.scala 141:41] + i0_predict_p_d.way <= i_alu.io.predict_p_out.way @[el2_exu.scala 142:41] + i0_predict_p_d.pja <= i_alu.io.predict_p_out.pja @[el2_exu.scala 142:41] + i0_predict_p_d.pret <= i_alu.io.predict_p_out.pret @[el2_exu.scala 142:41] + i0_predict_p_d.pcall <= i_alu.io.predict_p_out.pcall @[el2_exu.scala 142:41] + i0_predict_p_d.prett <= i_alu.io.predict_p_out.prett @[el2_exu.scala 142:41] + i0_predict_p_d.br_start_error <= i_alu.io.predict_p_out.br_start_error @[el2_exu.scala 142:41] + i0_predict_p_d.br_error <= i_alu.io.predict_p_out.br_error @[el2_exu.scala 142:41] + i0_predict_p_d.valid <= i_alu.io.predict_p_out.valid @[el2_exu.scala 142:41] + i0_predict_p_d.toffset <= i_alu.io.predict_p_out.toffset @[el2_exu.scala 142:41] + i0_predict_p_d.hist <= i_alu.io.predict_p_out.hist @[el2_exu.scala 142:41] + i0_predict_p_d.pc4 <= i_alu.io.predict_p_out.pc4 @[el2_exu.scala 142:41] + i0_predict_p_d.boffset <= i_alu.io.predict_p_out.boffset @[el2_exu.scala 142:41] + i0_predict_p_d.ataken <= i_alu.io.predict_p_out.ataken @[el2_exu.scala 142:41] + i0_predict_p_d.misp <= i_alu.io.predict_p_out.misp @[el2_exu.scala 142:41] + i0_pred_correct_upper_d <= i_alu.io.pred_correct_out @[el2_exu.scala 143:27] + io.exu_i0_pc_x <= i_alu.io.pc_ff @[el2_exu.scala 144:41] + inst i_mul of el2_exu_mul_ctl @[el2_exu.scala 146:19] + i_mul.clock <= clock + i_mul.reset <= reset + i_mul.io.scan_mode <= io.scan_mode @[el2_exu.scala 147:33] + i_mul.io.mul_p.bfp <= io.mul_p.bfp @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32c_w <= io.mul_p.crc32c_w @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32c_h <= io.mul_p.crc32c_h @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32c_b <= io.mul_p.crc32c_b @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32_w <= io.mul_p.crc32_w @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32_h <= io.mul_p.crc32_h @[el2_exu.scala 148:41] + i_mul.io.mul_p.crc32_b <= io.mul_p.crc32_b @[el2_exu.scala 148:41] + i_mul.io.mul_p.unshfl <= io.mul_p.unshfl @[el2_exu.scala 148:41] + i_mul.io.mul_p.shfl <= io.mul_p.shfl @[el2_exu.scala 148:41] + i_mul.io.mul_p.grev <= io.mul_p.grev @[el2_exu.scala 148:41] + i_mul.io.mul_p.clmulr <= io.mul_p.clmulr @[el2_exu.scala 148:41] + i_mul.io.mul_p.clmulh <= io.mul_p.clmulh @[el2_exu.scala 148:41] + i_mul.io.mul_p.clmul <= io.mul_p.clmul @[el2_exu.scala 148:41] + i_mul.io.mul_p.bdep <= io.mul_p.bdep @[el2_exu.scala 148:41] + i_mul.io.mul_p.bext <= io.mul_p.bext @[el2_exu.scala 148:41] + i_mul.io.mul_p.low <= io.mul_p.low @[el2_exu.scala 148:41] + i_mul.io.mul_p.rs2_sign <= io.mul_p.rs2_sign @[el2_exu.scala 148:41] + i_mul.io.mul_p.rs1_sign <= io.mul_p.rs1_sign @[el2_exu.scala 148:41] + i_mul.io.mul_p.valid <= io.mul_p.valid @[el2_exu.scala 148:41] + i_mul.io.rs1_in <= muldiv_rs1_d @[el2_exu.scala 149:41] + i_mul.io.rs2_in <= muldiv_rs2_d @[el2_exu.scala 150:41] + inst i_div of el2_exu_div_ctl @[el2_exu.scala 153:19] + i_div.clock <= clock + i_div.reset <= reset + i_div.io.scan_mode <= io.scan_mode @[el2_exu.scala 154:33] + i_div.io.cancel <= io.dec_div_cancel @[el2_exu.scala 155:41] + i_div.io.dp.rem <= io.div_p.rem @[el2_exu.scala 156:41] + i_div.io.dp.unsign <= io.div_p.unsign @[el2_exu.scala 156:41] + i_div.io.dp.valid <= io.div_p.valid @[el2_exu.scala 156:41] + i_div.io.dividend <= muldiv_rs1_d @[el2_exu.scala 157:33] + i_div.io.divisor <= muldiv_rs2_d @[el2_exu.scala 158:33] + io.exu_div_wren <= i_div.io.finish_dly @[el2_exu.scala 159:41] + io.exu_div_result <= i_div.io.out @[el2_exu.scala 160:33] + node _T_142 = bits(mul_valid_x, 0, 0) @[el2_exu.scala 162:61] + node _T_143 = mux(_T_142, i_mul.io.result_x, i_alu.io.result_ff) @[el2_exu.scala 162:48] + io.exu_i0_result_x <= _T_143 @[el2_exu.scala 162:42] + i0_predict_newp_d.way <= io.dec_i0_predict_p_d.way @[el2_exu.scala 163:32] + i0_predict_newp_d.pja <= io.dec_i0_predict_p_d.pja @[el2_exu.scala 163:32] + i0_predict_newp_d.pret <= io.dec_i0_predict_p_d.pret @[el2_exu.scala 163:32] + i0_predict_newp_d.pcall <= io.dec_i0_predict_p_d.pcall @[el2_exu.scala 163:32] + i0_predict_newp_d.prett <= io.dec_i0_predict_p_d.prett @[el2_exu.scala 163:32] + i0_predict_newp_d.br_start_error <= io.dec_i0_predict_p_d.br_start_error @[el2_exu.scala 163:32] + i0_predict_newp_d.br_error <= io.dec_i0_predict_p_d.br_error @[el2_exu.scala 163:32] + i0_predict_newp_d.valid <= io.dec_i0_predict_p_d.valid @[el2_exu.scala 163:32] + i0_predict_newp_d.toffset <= io.dec_i0_predict_p_d.toffset @[el2_exu.scala 163:32] + i0_predict_newp_d.hist <= io.dec_i0_predict_p_d.hist @[el2_exu.scala 163:32] + i0_predict_newp_d.pc4 <= io.dec_i0_predict_p_d.pc4 @[el2_exu.scala 163:32] + i0_predict_newp_d.boffset <= io.dec_i0_predict_p_d.boffset @[el2_exu.scala 163:32] + i0_predict_newp_d.ataken <= io.dec_i0_predict_p_d.ataken @[el2_exu.scala 163:32] + i0_predict_newp_d.misp <= io.dec_i0_predict_p_d.misp @[el2_exu.scala 163:32] + node _T_144 = bits(io.dec_i0_pc_d, 0, 0) @[el2_exu.scala 164:50] + i0_predict_newp_d.boffset <= _T_144 @[el2_exu.scala 164:32] + io.exu_pmu_i0_br_misp <= i0_pp_r.misp @[el2_exu.scala 166:31] + io.exu_pmu_i0_br_ataken <= i0_pp_r.ataken @[el2_exu.scala 167:31] + io.exu_pmu_i0_pc4 <= i0_pp_r.pc4 @[el2_exu.scala 168:31] + node _T_145 = and(i0_predict_p_d.valid, io.dec_i0_alu_decode_d) @[el2_exu.scala 171:54] + node _T_146 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 171:81] + node _T_147 = and(_T_145, _T_146) @[el2_exu.scala 171:79] + i0_valid_d <= _T_147 @[el2_exu.scala 171:28] + node _T_148 = and(i0_predict_p_d.ataken, io.dec_i0_alu_decode_d) @[el2_exu.scala 172:54] + i0_taken_d <= _T_148 @[el2_exu.scala 172:28] + node _T_149 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 178:6] + node _T_150 = and(_T_149, i0_valid_d) @[el2_exu.scala 178:32] + node _T_151 = bits(_T_150, 0, 0) @[el2_exu.scala 178:47] + node _T_152 = bits(ghr_d, 6, 0) @[el2_exu.scala 178:78] + node _T_153 = cat(_T_152, i0_taken_d) @[Cat.scala 29:58] + node _T_154 = not(io.dec_tlu_flush_lower_r) @[el2_exu.scala 179:6] + node _T_155 = not(i0_valid_d) @[el2_exu.scala 179:34] + node _T_156 = and(_T_154, _T_155) @[el2_exu.scala 179:32] + node _T_157 = bits(_T_156, 0, 0) @[el2_exu.scala 179:47] + node _T_158 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 180:32] + node _T_159 = mux(_T_151, _T_153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_160 = mux(_T_157, ghr_d, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_161 = mux(_T_158, ghr_x, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_162 = or(_T_159, _T_160) @[Mux.scala 27:72] + node _T_163 = or(_T_162, _T_161) @[Mux.scala 27:72] + wire _T_164 : UInt @[Mux.scala 27:72] + _T_164 <= _T_163 @[Mux.scala 27:72] + ghr_d_ns <= _T_164 @[el2_exu.scala 177:11] + node _T_165 = eq(i0_valid_x, UInt<1>("h01")) @[el2_exu.scala 184:27] + node _T_166 = bits(ghr_x, 6, 0) @[el2_exu.scala 184:44] + node _T_167 = cat(_T_166, i0_taken_x) @[Cat.scala 29:58] + node _T_168 = mux(_T_165, _T_167, ghr_x) @[el2_exu.scala 184:16] + ghr_x_ns <= _T_168 @[el2_exu.scala 184:11] + io.exu_i0_br_valid_r <= i0_pp_r.valid @[el2_exu.scala 186:36] + io.exu_i0_br_mp_r <= i0_pp_r.misp @[el2_exu.scala 187:36] + io.exu_i0_br_way_r <= i0_pp_r.way @[el2_exu.scala 188:36] + io.exu_i0_br_hist_r <= i0_pp_r.hist @[el2_exu.scala 189:50] + io.exu_i0_br_error_r <= i0_pp_r.br_error @[el2_exu.scala 190:42] + node _T_169 = xor(i0_pp_r.pc4, i0_pp_r.boffset) @[el2_exu.scala 191:52] + io.exu_i0_br_middle_r <= _T_169 @[el2_exu.scala 191:36] + io.exu_i0_br_start_error_r <= i0_pp_r.br_start_error @[el2_exu.scala 192:36] + node _T_170 = bits(predpipe_r, 20, 13) @[el2_exu.scala 193:64] + io.exu_i0_br_fghr_r <= _T_170 @[el2_exu.scala 193:50] + node _T_171 = bits(predpipe_r, 12, 5) @[el2_exu.scala 194:56] + io.exu_i0_br_index_r <= _T_171 @[el2_exu.scala 194:42] + node _T_172 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 195:74] + wire _T_173 : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>} @[el2_exu.scala 195:108] + _T_173.way <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.pja <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.pret <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.pcall <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.prett <= UInt<31>("h00") @[el2_exu.scala 195:108] + _T_173.br_start_error <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.br_error <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.valid <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.toffset <= UInt<12>("h00") @[el2_exu.scala 195:108] + _T_173.hist <= UInt<2>("h00") @[el2_exu.scala 195:108] + _T_173.pc4 <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.boffset <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.ataken <= UInt<1>("h00") @[el2_exu.scala 195:108] + _T_173.misp <= UInt<1>("h00") @[el2_exu.scala 195:108] + node _T_174 = mux(_T_172, i0_predict_p_x, _T_173) @[el2_exu.scala 195:57] + final_predict_mp.way <= _T_174.way @[el2_exu.scala 195:50] + final_predict_mp.pja <= _T_174.pja @[el2_exu.scala 195:50] + final_predict_mp.pret <= _T_174.pret @[el2_exu.scala 195:50] + final_predict_mp.pcall <= _T_174.pcall @[el2_exu.scala 195:50] + final_predict_mp.prett <= _T_174.prett @[el2_exu.scala 195:50] + final_predict_mp.br_start_error <= _T_174.br_start_error @[el2_exu.scala 195:50] + final_predict_mp.br_error <= _T_174.br_error @[el2_exu.scala 195:50] + final_predict_mp.valid <= _T_174.valid @[el2_exu.scala 195:50] + final_predict_mp.toffset <= _T_174.toffset @[el2_exu.scala 195:50] + final_predict_mp.hist <= _T_174.hist @[el2_exu.scala 195:50] + final_predict_mp.pc4 <= _T_174.pc4 @[el2_exu.scala 195:50] + final_predict_mp.boffset <= _T_174.boffset @[el2_exu.scala 195:50] + final_predict_mp.ataken <= _T_174.ataken @[el2_exu.scala 195:50] + final_predict_mp.misp <= _T_174.misp @[el2_exu.scala 195:50] + node _T_175 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 196:66] + node final_predpipe_mp = mux(_T_175, predpipe_x, UInt<1>("h00")) @[el2_exu.scala 196:49] + node _T_176 = eq(i0_flush_upper_x, UInt<1>("h01")) @[el2_exu.scala 198:60] + node _T_177 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h01")) @[el2_exu.scala 198:95] + node _T_178 = not(_T_177) @[el2_exu.scala 198:69] + node _T_179 = and(_T_176, _T_178) @[el2_exu.scala 198:67] + node after_flush_eghr = mux(_T_179, ghr_d, ghr_x) @[el2_exu.scala 198:42] + io.exu_mp_pkt.way <= final_predict_mp.way @[el2_exu.scala 201:36] + io.exu_mp_pkt.misp <= final_predict_mp.misp @[el2_exu.scala 202:36] + io.exu_mp_pkt.pcall <= final_predict_mp.pcall @[el2_exu.scala 203:36] + io.exu_mp_pkt.pja <= final_predict_mp.pja @[el2_exu.scala 204:36] + io.exu_mp_pkt.pret <= final_predict_mp.pret @[el2_exu.scala 205:36] + io.exu_mp_pkt.ataken <= final_predict_mp.ataken @[el2_exu.scala 206:36] + io.exu_mp_pkt.boffset <= final_predict_mp.boffset @[el2_exu.scala 207:36] + io.exu_mp_pkt.pc4 <= final_predict_mp.pc4 @[el2_exu.scala 208:36] + node _T_180 = bits(final_predict_mp.hist, 1, 0) @[el2_exu.scala 209:75] + io.exu_mp_pkt.hist <= _T_180 @[el2_exu.scala 209:50] + node _T_181 = bits(final_predict_mp.toffset, 11, 0) @[el2_exu.scala 210:70] + io.exu_mp_pkt.toffset <= _T_181 @[el2_exu.scala 210:42] + io.exu_mp_fghr <= after_flush_eghr @[el2_exu.scala 211:36] + node _T_182 = bits(final_predpipe_mp, 12, 5) @[el2_exu.scala 212:79] + io.exu_mp_index <= _T_182 @[el2_exu.scala 212:58] + node _T_183 = bits(final_predpipe_mp, 4, 0) @[el2_exu.scala 213:79] + io.exu_mp_btag <= _T_183 @[el2_exu.scala 213:58] + node _T_184 = bits(final_predpipe_mp, 20, 13) @[el2_exu.scala 214:57] + io.exu_mp_eghr <= _T_184 @[el2_exu.scala 214:36] + node _T_185 = bits(io.dec_tlu_flush_lower_r, 0, 0) @[el2_exu.scala 215:82] + node _T_186 = mux(_T_185, io.dec_tlu_flush_path_r, i0_flush_path_d) @[el2_exu.scala 215:56] + io.exu_flush_path_final <= _T_186 @[el2_exu.scala 215:50] + node _T_187 = eq(i0_pred_correct_upper_r, UInt<1>("h01")) @[el2_exu.scala 216:80] + node _T_188 = mux(_T_187, pred_correct_npc_r, i0_flush_path_upper_r) @[el2_exu.scala 216:56] + io.exu_npc_r <= _T_188 @[el2_exu.scala 216:50] + diff --git a/el2_exu.v b/el2_exu.v new file mode 100644 index 00000000..db31adc4 --- /dev/null +++ b/el2_exu.v @@ -0,0 +1,2603 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule +module el2_exu_alu_ctl( + input clock, + input reset, + input io_scan_mode, + input io_flush_upper_x, + input io_flush_lower_r, + input io_enable, + input io_valid_in, + input io_ap_land, + input io_ap_lor, + input io_ap_lxor, + input io_ap_sll, + input io_ap_srl, + input io_ap_sra, + input io_ap_beq, + input io_ap_bne, + input io_ap_blt, + input io_ap_bge, + input io_ap_add, + input io_ap_sub, + input io_ap_slt, + input io_ap_unsign, + input io_ap_jal, + input io_ap_predict_t, + input io_ap_predict_nt, + input io_ap_csr_write, + input io_ap_csr_imm, + input io_csr_ren_in, + input [31:0] io_a_in, + input [31:0] io_b_in, + input [30:0] io_pc_in, + input io_pp_in_boffset, + input io_pp_in_pc4, + input [1:0] io_pp_in_hist, + input [11:0] io_pp_in_toffset, + input io_pp_in_valid, + input io_pp_in_br_error, + input io_pp_in_br_start_error, + input [30:0] io_pp_in_prett, + input io_pp_in_pcall, + input io_pp_in_pret, + input io_pp_in_pja, + input io_pp_in_way, + input [11:0] io_brimm_in, + output [31:0] io_result_ff, + output io_flush_upper_out, + output io_flush_final_out, + output [30:0] io_flush_path_out, + output [30:0] io_pc_ff, + output io_pred_correct_out, + output io_predict_p_out_misp, + output io_predict_p_out_ataken, + output io_predict_p_out_boffset, + output io_predict_p_out_pc4, + output [1:0] io_predict_p_out_hist, + output [11:0] io_predict_p_out_toffset, + output io_predict_p_out_valid, + output io_predict_p_out_br_error, + output io_predict_p_out_br_start_error, + output io_predict_p_out_pcall, + output io_predict_p_out_pret, + output io_predict_p_out_pja, + output io_predict_p_out_way +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + reg [30:0] _T_1; // @[el2_lib.scala 514:16] + reg [31:0] _T_3; // @[el2_lib.scala 514:16] + wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37] + wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] + wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58] + wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58] + wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55] + wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58] + wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80] + wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58] + wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132] + wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157] + wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14] + wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18] + wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14] + wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29] + wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27] + wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37] + wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66] + wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78] + wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76] + wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50] + wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38] + wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29] + wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30] + wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51] + wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44] + wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78] + wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76] + wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58] + wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29] + wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72] + wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72] + wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58] + wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38] + wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72] + wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72] + wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61] + wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39] + wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44] + wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90] + wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68] + wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58] + wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32] + wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14] + wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34] + wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41] + wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53] + wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41] + wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56] + wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54] + wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41] + wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58] + wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73] + wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] + wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] + wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] + wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:8] + wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:14] + wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:14] + wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72] + wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72] + wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24] + wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58] + wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31] + wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51] + wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72] + wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72] + wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40] + wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59] + wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46] + wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85] + wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72] + wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104] + wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91] + wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110] + wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42] + wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63] + wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61] + wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79] + wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77] + wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104] + wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123] + wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139] + wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45] + wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82] + wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62] + wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62] + wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44] + wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42] + wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60] + wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81] + wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97] + wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95] + wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119] + wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39] + wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63] + wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81] + wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60] + wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] + wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24] + wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62] + wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42] + wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51] + wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16] + assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26] + assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26] + assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] + assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] + assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] + assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30] + assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30] + assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30] + assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + _T_1 = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1 = 31'h0; + end + if (reset) begin + _T_3 = 32'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1 <= 31'h0; + end else begin + _T_1 <= io_pc_in; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_3 <= 32'h0; + end else begin + _T_3 <= _T_252 | _T_266; + end + end +endmodule +module el2_exu_mul_ctl( + input clock, + input reset, + input io_scan_mode, + input io_mul_p_valid, + input io_mul_p_rs1_sign, + input io_mul_p_rs2_sign, + input io_mul_p_low, + input [31:0] io_rs1_in, + input [31:0] io_rs2_in, + output [31:0] io_result_x +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [63:0] _RAND_1; + reg [63:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 528:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 528:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 528:23] + wire _T_1 = io_mul_p_rs1_sign & io_rs1_in[31]; // @[el2_exu_mul_ctl.scala 26:39] + wire _T_5 = io_mul_p_rs2_sign & io_rs2_in[31]; // @[el2_exu_mul_ctl.scala 27:39] + reg low_x; // @[el2_lib.scala 514:16] + reg [32:0] rs1_x; // @[el2_lib.scala 534:16] + reg [32:0] rs2_x; // @[el2_lib.scala 534:16] + wire [65:0] prod_x = $signed(rs1_x) * $signed(rs2_x); // @[el2_exu_mul_ctl.scala 40:20] + wire _T_16 = ~low_x; // @[el2_exu_mul_ctl.scala 41:29] + wire [31:0] _T_20 = _T_16 ? prod_x[63:32] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_21 = low_x ? prod_x[31:0] : 32'h0; // @[Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 528:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 528:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + assign io_result_x = _T_20 | _T_21; // @[el2_exu_mul_ctl.scala 41:15] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_mul_p_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 530:18] + assign rvclkhdr_1_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 530:18] + assign rvclkhdr_2_io_en = io_mul_p_valid; // @[el2_lib.scala 531:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 532:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + low_x = _RAND_0[0:0]; + _RAND_1 = {2{`RANDOM}}; + rs1_x = _RAND_1[32:0]; + _RAND_2 = {2{`RANDOM}}; + rs2_x = _RAND_2[32:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + low_x = 1'h0; + end + if (reset) begin + rs1_x = 33'sh0; + end + if (reset) begin + rs2_x = 33'sh0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + low_x <= 1'h0; + end else begin + low_x <= io_mul_p_low; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + rs1_x <= 33'sh0; + end else begin + rs1_x <= {_T_1,io_rs1_in}; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + rs2_x <= 33'sh0; + end else begin + rs2_x <= {_T_5,io_rs2_in}; + end + end +endmodule +module el2_exu_div_ctl( + input clock, + input reset, + input io_scan_mode, + input io_dp_valid, + input io_dp_unsign, + input io_dp_rem, + input [31:0] io_dividend, + input [31:0] io_divisor, + input io_cancel, + output [31:0] io_out, + output io_finish_dly +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [63:0] _RAND_1; + reg [63:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [63:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire _T = ~io_cancel; // @[el2_exu_div_ctl.scala 54:30] + reg valid_ff_x; // @[el2_exu_div_ctl.scala 204:26] + wire valid_x = valid_ff_x & _T; // @[el2_exu_div_ctl.scala 54:28] + reg [32:0] q_ff; // @[el2_lib.scala 514:16] + wire _T_2 = q_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:34] + reg [32:0] m_ff; // @[el2_lib.scala 514:16] + wire _T_4 = m_ff[31:4] == 28'h0; // @[el2_exu_div_ctl.scala 60:57] + wire _T_5 = _T_2 & _T_4; // @[el2_exu_div_ctl.scala 60:43] + wire _T_7 = m_ff[31:0] != 32'h0; // @[el2_exu_div_ctl.scala 60:80] + wire _T_8 = _T_5 & _T_7; // @[el2_exu_div_ctl.scala 60:66] + reg rem_ff; // @[Reg.scala 27:20] + wire _T_9 = ~rem_ff; // @[el2_exu_div_ctl.scala 60:91] + wire _T_10 = _T_8 & _T_9; // @[el2_exu_div_ctl.scala 60:89] + wire _T_11 = _T_10 & valid_x; // @[el2_exu_div_ctl.scala 60:99] + wire _T_13 = q_ff[31:0] == 32'h0; // @[el2_exu_div_ctl.scala 61:18] + wire _T_16 = _T_13 & _T_7; // @[el2_exu_div_ctl.scala 61:27] + wire _T_18 = _T_16 & _T_9; // @[el2_exu_div_ctl.scala 61:50] + wire _T_19 = _T_18 & valid_x; // @[el2_exu_div_ctl.scala 61:60] + wire smallnum_case = _T_11 | _T_19; // @[el2_exu_div_ctl.scala 60:110] + wire _T_23 = ~m_ff[3]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_25 = ~m_ff[2]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_27 = ~m_ff[1]; // @[el2_exu_div_ctl.scala 65:69] + wire _T_28 = _T_23 & _T_25; // @[el2_exu_div_ctl.scala 65:94] + wire _T_29 = _T_28 & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_30 = q_ff[3] & _T_29; // @[el2_exu_div_ctl.scala 66:10] + wire _T_37 = q_ff[3] & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_39 = ~m_ff[0]; // @[el2_exu_div_ctl.scala 72:32] + wire _T_40 = _T_37 & _T_39; // @[el2_exu_div_ctl.scala 72:30] + wire _T_50 = q_ff[2] & _T_29; // @[el2_exu_div_ctl.scala 66:10] + wire _T_51 = _T_40 | _T_50; // @[el2_exu_div_ctl.scala 72:41] + wire _T_54 = q_ff[3] & q_ff[2]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_60 = _T_54 & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_61 = _T_51 | _T_60; // @[el2_exu_div_ctl.scala 72:73] + wire _T_68 = q_ff[2] & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_71 = _T_68 & _T_39; // @[el2_exu_div_ctl.scala 74:30] + wire _T_81 = q_ff[1] & _T_29; // @[el2_exu_div_ctl.scala 66:10] + wire _T_82 = _T_71 | _T_81; // @[el2_exu_div_ctl.scala 74:41] + wire _T_88 = _T_23 & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_89 = q_ff[3] & _T_88; // @[el2_exu_div_ctl.scala 66:10] + wire _T_92 = _T_89 & _T_39; // @[el2_exu_div_ctl.scala 74:103] + wire _T_93 = _T_82 | _T_92; // @[el2_exu_div_ctl.scala 74:76] + wire _T_96 = ~q_ff[2]; // @[el2_exu_div_ctl.scala 64:69] + wire _T_97 = q_ff[3] & _T_96; // @[el2_exu_div_ctl.scala 64:94] + wire _T_105 = _T_28 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_106 = _T_105 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_107 = _T_97 & _T_106; // @[el2_exu_div_ctl.scala 66:10] + wire _T_108 = _T_93 | _T_107; // @[el2_exu_div_ctl.scala 74:114] + wire _T_110 = ~q_ff[3]; // @[el2_exu_div_ctl.scala 64:69] + wire _T_113 = _T_110 & q_ff[2]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_114 = _T_113 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_120 = _T_114 & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_121 = _T_108 | _T_120; // @[el2_exu_div_ctl.scala 75:43] + wire _T_127 = _T_54 & _T_23; // @[el2_exu_div_ctl.scala 66:10] + wire _T_130 = _T_127 & _T_39; // @[el2_exu_div_ctl.scala 75:104] + wire _T_131 = _T_121 | _T_130; // @[el2_exu_div_ctl.scala 75:78] + wire _T_140 = _T_23 & m_ff[2]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_141 = _T_140 & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_142 = _T_54 & _T_141; // @[el2_exu_div_ctl.scala 66:10] + wire _T_143 = _T_131 | _T_142; // @[el2_exu_div_ctl.scala 75:116] + wire _T_146 = q_ff[3] & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_152 = _T_146 & _T_88; // @[el2_exu_div_ctl.scala 66:10] + wire _T_153 = _T_143 | _T_152; // @[el2_exu_div_ctl.scala 76:43] + wire _T_158 = _T_54 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_163 = _T_158 & _T_140; // @[el2_exu_div_ctl.scala 66:10] + wire _T_164 = _T_153 | _T_163; // @[el2_exu_div_ctl.scala 76:77] + wire _T_168 = q_ff[2] & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_169 = _T_168 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_175 = _T_169 & _T_88; // @[el2_exu_div_ctl.scala 66:10] + wire _T_181 = _T_97 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_186 = _T_23 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_187 = _T_186 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_188 = _T_181 & _T_187; // @[el2_exu_div_ctl.scala 66:10] + wire _T_189 = _T_175 | _T_188; // @[el2_exu_div_ctl.scala 78:44] + wire _T_196 = q_ff[2] & _T_88; // @[el2_exu_div_ctl.scala 66:10] + wire _T_199 = _T_196 & _T_39; // @[el2_exu_div_ctl.scala 78:111] + wire _T_200 = _T_189 | _T_199; // @[el2_exu_div_ctl.scala 78:84] + wire _T_207 = q_ff[1] & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_210 = _T_207 & _T_39; // @[el2_exu_div_ctl.scala 79:32] + wire _T_211 = _T_200 | _T_210; // @[el2_exu_div_ctl.scala 78:126] + wire _T_221 = q_ff[0] & _T_29; // @[el2_exu_div_ctl.scala 66:10] + wire _T_222 = _T_211 | _T_221; // @[el2_exu_div_ctl.scala 79:46] + wire _T_227 = ~q_ff[1]; // @[el2_exu_div_ctl.scala 64:69] + wire _T_229 = _T_113 & _T_227; // @[el2_exu_div_ctl.scala 64:94] + wire _T_239 = _T_229 & _T_106; // @[el2_exu_div_ctl.scala 66:10] + wire _T_240 = _T_222 | _T_239; // @[el2_exu_div_ctl.scala 79:86] + wire _T_249 = _T_114 & _T_23; // @[el2_exu_div_ctl.scala 66:10] + wire _T_252 = _T_249 & _T_39; // @[el2_exu_div_ctl.scala 80:35] + wire _T_253 = _T_240 | _T_252; // @[el2_exu_div_ctl.scala 79:128] + wire _T_259 = _T_25 & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_260 = q_ff[3] & _T_259; // @[el2_exu_div_ctl.scala 66:10] + wire _T_263 = _T_260 & _T_39; // @[el2_exu_div_ctl.scala 80:74] + wire _T_264 = _T_253 | _T_263; // @[el2_exu_div_ctl.scala 80:46] + wire _T_274 = _T_140 & m_ff[1]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_275 = _T_97 & _T_274; // @[el2_exu_div_ctl.scala 66:10] + wire _T_276 = _T_264 | _T_275; // @[el2_exu_div_ctl.scala 80:86] + wire _T_290 = _T_114 & _T_141; // @[el2_exu_div_ctl.scala 66:10] + wire _T_291 = _T_276 | _T_290; // @[el2_exu_div_ctl.scala 80:128] + wire _T_297 = _T_113 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_303 = _T_297 & _T_88; // @[el2_exu_div_ctl.scala 66:10] + wire _T_304 = _T_291 | _T_303; // @[el2_exu_div_ctl.scala 81:46] + wire _T_311 = _T_97 & _T_227; // @[el2_exu_div_ctl.scala 64:94] + wire _T_317 = _T_140 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_318 = _T_311 & _T_317; // @[el2_exu_div_ctl.scala 66:10] + wire _T_319 = _T_304 | _T_318; // @[el2_exu_div_ctl.scala 81:86] + wire _T_324 = _T_96 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_325 = _T_324 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_331 = _T_325 & _T_28; // @[el2_exu_div_ctl.scala 66:10] + wire _T_332 = _T_319 | _T_331; // @[el2_exu_div_ctl.scala 81:128] + wire _T_338 = _T_54 & _T_27; // @[el2_exu_div_ctl.scala 66:10] + wire _T_341 = _T_338 & _T_39; // @[el2_exu_div_ctl.scala 82:73] + wire _T_342 = _T_332 | _T_341; // @[el2_exu_div_ctl.scala 82:46] + wire _T_350 = _T_114 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_355 = _T_350 & _T_140; // @[el2_exu_div_ctl.scala 66:10] + wire _T_356 = _T_342 | _T_355; // @[el2_exu_div_ctl.scala 82:86] + wire _T_363 = m_ff[3] & _T_25; // @[el2_exu_div_ctl.scala 65:94] + wire _T_364 = _T_54 & _T_363; // @[el2_exu_div_ctl.scala 66:10] + wire _T_365 = _T_356 | _T_364; // @[el2_exu_div_ctl.scala 82:128] + wire _T_375 = _T_363 & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_376 = _T_146 & _T_375; // @[el2_exu_div_ctl.scala 66:10] + wire _T_377 = _T_365 | _T_376; // @[el2_exu_div_ctl.scala 83:46] + wire _T_380 = q_ff[3] & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_386 = _T_380 & _T_259; // @[el2_exu_div_ctl.scala 66:10] + wire _T_387 = _T_377 | _T_386; // @[el2_exu_div_ctl.scala 83:86] + wire _T_391 = q_ff[3] & _T_227; // @[el2_exu_div_ctl.scala 64:94] + wire _T_399 = _T_274 & m_ff[0]; // @[el2_exu_div_ctl.scala 65:94] + wire _T_400 = _T_391 & _T_399; // @[el2_exu_div_ctl.scala 66:10] + wire _T_401 = _T_387 | _T_400; // @[el2_exu_div_ctl.scala 83:128] + wire _T_408 = _T_158 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10] + wire _T_411 = _T_408 & _T_39; // @[el2_exu_div_ctl.scala 84:75] + wire _T_412 = _T_401 | _T_411; // @[el2_exu_div_ctl.scala 84:46] + wire _T_421 = m_ff[3] & _T_27; // @[el2_exu_div_ctl.scala 65:94] + wire _T_422 = _T_158 & _T_421; // @[el2_exu_div_ctl.scala 66:10] + wire _T_423 = _T_412 | _T_422; // @[el2_exu_div_ctl.scala 84:86] + wire _T_428 = _T_54 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_433 = _T_428 & _T_421; // @[el2_exu_div_ctl.scala 66:10] + wire _T_434 = _T_423 | _T_433; // @[el2_exu_div_ctl.scala 84:128] + wire _T_440 = _T_97 & q_ff[1]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_445 = _T_440 & _T_186; // @[el2_exu_div_ctl.scala 66:10] + wire _T_446 = _T_434 | _T_445; // @[el2_exu_div_ctl.scala 85:46] + wire _T_451 = _T_146 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_454 = _T_451 & _T_25; // @[el2_exu_div_ctl.scala 66:10] + wire _T_455 = _T_446 | _T_454; // @[el2_exu_div_ctl.scala 85:86] + wire _T_462 = _T_158 & q_ff[0]; // @[el2_exu_div_ctl.scala 64:94] + wire _T_464 = _T_462 & m_ff[3]; // @[el2_exu_div_ctl.scala 66:10] + wire _T_465 = _T_455 | _T_464; // @[el2_exu_div_ctl.scala 85:128] + wire _T_471 = _T_146 & _T_25; // @[el2_exu_div_ctl.scala 66:10] + wire _T_474 = _T_471 & _T_39; // @[el2_exu_div_ctl.scala 86:72] + wire _T_475 = _T_465 | _T_474; // @[el2_exu_div_ctl.scala 86:46] + wire [1:0] _T_476 = {_T_164,_T_475}; // @[Cat.scala 29:58] + wire [1:0] _T_477 = {_T_30,_T_61}; // @[Cat.scala 29:58] + reg sign_ff; // @[Reg.scala 27:20] + wire _T_479 = sign_ff & q_ff[31]; // @[el2_exu_div_ctl.scala 96:34] + wire [32:0] short_dividend = {_T_479,q_ff[31:0]}; // @[Cat.scala 29:58] + wire _T_484 = ~short_dividend[32]; // @[el2_exu_div_ctl.scala 101:7] + wire _T_487 = short_dividend[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 101:60] + wire _T_492 = short_dividend[31:23] != 9'h1ff; // @[el2_exu_div_ctl.scala 102:59] + wire _T_493 = _T_484 & _T_487; // @[Mux.scala 27:72] + wire _T_494 = short_dividend[32] & _T_492; // @[Mux.scala 27:72] + wire _T_495 = _T_493 | _T_494; // @[Mux.scala 27:72] + wire _T_502 = short_dividend[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 105:60] + wire _T_507 = short_dividend[22:15] != 8'hff; // @[el2_exu_div_ctl.scala 106:59] + wire _T_508 = _T_484 & _T_502; // @[Mux.scala 27:72] + wire _T_509 = short_dividend[32] & _T_507; // @[Mux.scala 27:72] + wire _T_510 = _T_508 | _T_509; // @[Mux.scala 27:72] + wire _T_517 = short_dividend[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 109:59] + wire _T_522 = short_dividend[14:7] != 8'hff; // @[el2_exu_div_ctl.scala 110:58] + wire _T_523 = _T_484 & _T_517; // @[Mux.scala 27:72] + wire _T_524 = short_dividend[32] & _T_522; // @[Mux.scala 27:72] + wire _T_525 = _T_523 | _T_524; // @[Mux.scala 27:72] + wire [2:0] a_cls = {_T_495,_T_510,_T_525}; // @[Cat.scala 29:58] + wire _T_530 = ~m_ff[32]; // @[el2_exu_div_ctl.scala 115:7] + wire _T_533 = m_ff[31:24] != 8'h0; // @[el2_exu_div_ctl.scala 115:40] + wire _T_538 = m_ff[31:24] != 8'hff; // @[el2_exu_div_ctl.scala 116:39] + wire _T_539 = _T_530 & _T_533; // @[Mux.scala 27:72] + wire _T_540 = m_ff[32] & _T_538; // @[Mux.scala 27:72] + wire _T_541 = _T_539 | _T_540; // @[Mux.scala 27:72] + wire _T_548 = m_ff[23:16] != 8'h0; // @[el2_exu_div_ctl.scala 119:40] + wire _T_553 = m_ff[23:16] != 8'hff; // @[el2_exu_div_ctl.scala 120:39] + wire _T_554 = _T_530 & _T_548; // @[Mux.scala 27:72] + wire _T_555 = m_ff[32] & _T_553; // @[Mux.scala 27:72] + wire _T_556 = _T_554 | _T_555; // @[Mux.scala 27:72] + wire _T_563 = m_ff[15:8] != 8'h0; // @[el2_exu_div_ctl.scala 123:39] + wire _T_568 = m_ff[15:8] != 8'hff; // @[el2_exu_div_ctl.scala 124:38] + wire _T_569 = _T_530 & _T_563; // @[Mux.scala 27:72] + wire _T_570 = m_ff[32] & _T_568; // @[Mux.scala 27:72] + wire _T_571 = _T_569 | _T_570; // @[Mux.scala 27:72] + wire [2:0] b_cls = {_T_541,_T_556,_T_571}; // @[Cat.scala 29:58] + wire _T_575 = a_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 128:19] + wire _T_578 = _T_575 & b_cls[2]; // @[el2_exu_div_ctl.scala 128:34] + wire _T_580 = a_cls == 3'h1; // @[el2_exu_div_ctl.scala 129:21] + wire _T_583 = _T_580 & b_cls[2]; // @[el2_exu_div_ctl.scala 129:36] + wire _T_584 = _T_578 | _T_583; // @[el2_exu_div_ctl.scala 128:65] + wire _T_586 = a_cls == 3'h0; // @[el2_exu_div_ctl.scala 130:21] + wire _T_589 = _T_586 & b_cls[2]; // @[el2_exu_div_ctl.scala 130:36] + wire _T_590 = _T_584 | _T_589; // @[el2_exu_div_ctl.scala 129:67] + wire _T_594 = b_cls[2:1] == 2'h1; // @[el2_exu_div_ctl.scala 131:50] + wire _T_595 = _T_580 & _T_594; // @[el2_exu_div_ctl.scala 131:36] + wire _T_596 = _T_590 | _T_595; // @[el2_exu_div_ctl.scala 130:67] + wire _T_601 = _T_586 & _T_594; // @[el2_exu_div_ctl.scala 132:36] + wire _T_602 = _T_596 | _T_601; // @[el2_exu_div_ctl.scala 131:67] + wire _T_606 = b_cls == 3'h1; // @[el2_exu_div_ctl.scala 133:50] + wire _T_607 = _T_586 & _T_606; // @[el2_exu_div_ctl.scala 133:36] + wire _T_608 = _T_602 | _T_607; // @[el2_exu_div_ctl.scala 132:67] + wire _T_613 = a_cls[2] & b_cls[2]; // @[el2_exu_div_ctl.scala 135:34] + wire _T_618 = _T_575 & _T_594; // @[el2_exu_div_ctl.scala 136:36] + wire _T_619 = _T_613 | _T_618; // @[el2_exu_div_ctl.scala 135:65] + wire _T_624 = _T_580 & _T_606; // @[el2_exu_div_ctl.scala 137:36] + wire _T_625 = _T_619 | _T_624; // @[el2_exu_div_ctl.scala 136:67] + wire _T_629 = b_cls == 3'h0; // @[el2_exu_div_ctl.scala 138:50] + wire _T_630 = _T_586 & _T_629; // @[el2_exu_div_ctl.scala 138:36] + wire _T_631 = _T_625 | _T_630; // @[el2_exu_div_ctl.scala 137:67] + wire _T_636 = a_cls[2] & _T_594; // @[el2_exu_div_ctl.scala 140:34] + wire _T_641 = _T_575 & _T_606; // @[el2_exu_div_ctl.scala 141:36] + wire _T_642 = _T_636 | _T_641; // @[el2_exu_div_ctl.scala 140:65] + wire _T_647 = _T_580 & _T_629; // @[el2_exu_div_ctl.scala 142:36] + wire _T_648 = _T_642 | _T_647; // @[el2_exu_div_ctl.scala 141:67] + wire _T_653 = a_cls[2] & _T_606; // @[el2_exu_div_ctl.scala 144:34] + wire _T_658 = _T_575 & _T_629; // @[el2_exu_div_ctl.scala 145:36] + wire _T_659 = _T_653 | _T_658; // @[el2_exu_div_ctl.scala 144:65] + wire [3:0] shortq_raw = {_T_608,_T_631,_T_648,_T_659}; // @[Cat.scala 29:58] + wire _T_664 = valid_ff_x & _T_7; // @[el2_exu_div_ctl.scala 148:35] + wire _T_665 = shortq_raw != 4'h0; // @[el2_exu_div_ctl.scala 148:78] + wire shortq_enable = _T_664 & _T_665; // @[el2_exu_div_ctl.scala 148:64] + wire [3:0] _T_667 = shortq_enable ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] shortq_shift_xx; // @[el2_exu_div_ctl.scala 215:31] + wire [4:0] _T_676 = shortq_shift_xx[3] ? 5'h1f : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_677 = shortq_shift_xx[2] ? 5'h18 : 5'h0; // @[Mux.scala 27:72] + wire [4:0] _T_678 = shortq_shift_xx[1] ? 5'h10 : 5'h0; // @[Mux.scala 27:72] + wire [3:0] _T_679 = shortq_shift_xx[0] ? 4'h8 : 4'h0; // @[Mux.scala 27:72] + wire [4:0] _T_680 = _T_676 | _T_677; // @[Mux.scala 27:72] + wire [4:0] _T_681 = _T_680 | _T_678; // @[Mux.scala 27:72] + wire [4:0] _GEN_4 = {{1'd0}, _T_679}; // @[Mux.scala 27:72] + wire [4:0] shortq_shift_ff = _T_681 | _GEN_4; // @[Mux.scala 27:72] + reg [5:0] count; // @[el2_exu_div_ctl.scala 207:21] + wire _T_684 = count == 6'h20; // @[el2_exu_div_ctl.scala 159:55] + wire _T_685 = count == 6'h21; // @[el2_exu_div_ctl.scala 159:76] + wire _T_686 = _T_9 ? _T_684 : _T_685; // @[el2_exu_div_ctl.scala 159:39] + wire finish = smallnum_case | _T_686; // @[el2_exu_div_ctl.scala 159:34] + reg run_state; // @[el2_exu_div_ctl.scala 206:25] + wire _T_687 = io_dp_valid | run_state; // @[el2_exu_div_ctl.scala 160:32] + wire _T_688 = _T_687 | finish; // @[el2_exu_div_ctl.scala 160:44] + reg finish_ff; // @[el2_exu_div_ctl.scala 205:25] + wire _T_690 = ~finish; // @[el2_exu_div_ctl.scala 161:48] + wire _T_691 = _T_687 & _T_690; // @[el2_exu_div_ctl.scala 161:46] + wire _T_694 = run_state & _T_690; // @[el2_exu_div_ctl.scala 162:35] + wire _T_696 = _T_694 & _T; // @[el2_exu_div_ctl.scala 162:45] + wire _T_697 = ~shortq_enable; // @[el2_exu_div_ctl.scala 162:60] + wire _T_698 = _T_696 & _T_697; // @[el2_exu_div_ctl.scala 162:58] + wire [5:0] _T_700 = _T_698 ? 6'h3f : 6'h0; // @[Bitwise.scala 72:12] + wire [5:0] _T_701 = {1'h0,shortq_shift_ff}; // @[Cat.scala 29:58] + wire [5:0] _T_703 = count + _T_701; // @[el2_exu_div_ctl.scala 162:86] + wire [5:0] _T_705 = _T_703 + 6'h1; // @[el2_exu_div_ctl.scala 162:113] + wire _T_709 = ~io_dp_unsign; // @[el2_exu_div_ctl.scala 166:20] + wire _T_710 = io_divisor != 32'h0; // @[el2_exu_div_ctl.scala 166:48] + wire sign_eff = _T_709 & _T_710; // @[el2_exu_div_ctl.scala 166:34] + wire _T_711 = ~run_state; // @[el2_exu_div_ctl.scala 170:6] + wire [32:0] _T_713 = {1'h0,io_dividend}; // @[Cat.scala 29:58] + reg shortq_enable_ff; // @[el2_exu_div_ctl.scala 214:32] + wire _T_714 = valid_ff_x | shortq_enable_ff; // @[el2_exu_div_ctl.scala 171:30] + wire _T_715 = run_state & _T_714; // @[el2_exu_div_ctl.scala 171:16] + reg dividend_neg_ff; // @[Reg.scala 27:20] + wire _T_738 = sign_ff & dividend_neg_ff; // @[el2_exu_div_ctl.scala 175:32] + wire _T_923 = |q_ff[30:0]; // @[el2_lib.scala 543:35] + wire _T_925 = ~q_ff[31]; // @[el2_lib.scala 543:40] + wire _T_927 = _T_923 ? _T_925 : q_ff[31]; // @[el2_lib.scala 543:23] + wire _T_917 = |q_ff[29:0]; // @[el2_lib.scala 543:35] + wire _T_919 = ~q_ff[30]; // @[el2_lib.scala 543:40] + wire _T_921 = _T_917 ? _T_919 : q_ff[30]; // @[el2_lib.scala 543:23] + wire _T_911 = |q_ff[28:0]; // @[el2_lib.scala 543:35] + wire _T_913 = ~q_ff[29]; // @[el2_lib.scala 543:40] + wire _T_915 = _T_911 ? _T_913 : q_ff[29]; // @[el2_lib.scala 543:23] + wire _T_905 = |q_ff[27:0]; // @[el2_lib.scala 543:35] + wire _T_907 = ~q_ff[28]; // @[el2_lib.scala 543:40] + wire _T_909 = _T_905 ? _T_907 : q_ff[28]; // @[el2_lib.scala 543:23] + wire _T_899 = |q_ff[26:0]; // @[el2_lib.scala 543:35] + wire _T_901 = ~q_ff[27]; // @[el2_lib.scala 543:40] + wire _T_903 = _T_899 ? _T_901 : q_ff[27]; // @[el2_lib.scala 543:23] + wire _T_893 = |q_ff[25:0]; // @[el2_lib.scala 543:35] + wire _T_895 = ~q_ff[26]; // @[el2_lib.scala 543:40] + wire _T_897 = _T_893 ? _T_895 : q_ff[26]; // @[el2_lib.scala 543:23] + wire _T_887 = |q_ff[24:0]; // @[el2_lib.scala 543:35] + wire _T_889 = ~q_ff[25]; // @[el2_lib.scala 543:40] + wire _T_891 = _T_887 ? _T_889 : q_ff[25]; // @[el2_lib.scala 543:23] + wire _T_881 = |q_ff[23:0]; // @[el2_lib.scala 543:35] + wire _T_883 = ~q_ff[24]; // @[el2_lib.scala 543:40] + wire _T_885 = _T_881 ? _T_883 : q_ff[24]; // @[el2_lib.scala 543:23] + wire _T_875 = |q_ff[22:0]; // @[el2_lib.scala 543:35] + wire _T_877 = ~q_ff[23]; // @[el2_lib.scala 543:40] + wire _T_879 = _T_875 ? _T_877 : q_ff[23]; // @[el2_lib.scala 543:23] + wire _T_869 = |q_ff[21:0]; // @[el2_lib.scala 543:35] + wire _T_871 = ~q_ff[22]; // @[el2_lib.scala 543:40] + wire _T_873 = _T_869 ? _T_871 : q_ff[22]; // @[el2_lib.scala 543:23] + wire _T_863 = |q_ff[20:0]; // @[el2_lib.scala 543:35] + wire _T_865 = ~q_ff[21]; // @[el2_lib.scala 543:40] + wire _T_867 = _T_863 ? _T_865 : q_ff[21]; // @[el2_lib.scala 543:23] + wire _T_857 = |q_ff[19:0]; // @[el2_lib.scala 543:35] + wire _T_859 = ~q_ff[20]; // @[el2_lib.scala 543:40] + wire _T_861 = _T_857 ? _T_859 : q_ff[20]; // @[el2_lib.scala 543:23] + wire _T_851 = |q_ff[18:0]; // @[el2_lib.scala 543:35] + wire _T_853 = ~q_ff[19]; // @[el2_lib.scala 543:40] + wire _T_855 = _T_851 ? _T_853 : q_ff[19]; // @[el2_lib.scala 543:23] + wire _T_845 = |q_ff[17:0]; // @[el2_lib.scala 543:35] + wire _T_847 = ~q_ff[18]; // @[el2_lib.scala 543:40] + wire _T_849 = _T_845 ? _T_847 : q_ff[18]; // @[el2_lib.scala 543:23] + wire _T_839 = |q_ff[16:0]; // @[el2_lib.scala 543:35] + wire _T_841 = ~q_ff[17]; // @[el2_lib.scala 543:40] + wire _T_843 = _T_839 ? _T_841 : q_ff[17]; // @[el2_lib.scala 543:23] + wire _T_833 = |q_ff[15:0]; // @[el2_lib.scala 543:35] + wire _T_835 = ~q_ff[16]; // @[el2_lib.scala 543:40] + wire _T_837 = _T_833 ? _T_835 : q_ff[16]; // @[el2_lib.scala 543:23] + wire [7:0] _T_948 = {_T_879,_T_873,_T_867,_T_861,_T_855,_T_849,_T_843,_T_837}; // @[el2_lib.scala 545:14] + wire _T_827 = |q_ff[14:0]; // @[el2_lib.scala 543:35] + wire _T_829 = ~q_ff[15]; // @[el2_lib.scala 543:40] + wire _T_831 = _T_827 ? _T_829 : q_ff[15]; // @[el2_lib.scala 543:23] + wire _T_821 = |q_ff[13:0]; // @[el2_lib.scala 543:35] + wire _T_823 = ~q_ff[14]; // @[el2_lib.scala 543:40] + wire _T_825 = _T_821 ? _T_823 : q_ff[14]; // @[el2_lib.scala 543:23] + wire _T_815 = |q_ff[12:0]; // @[el2_lib.scala 543:35] + wire _T_817 = ~q_ff[13]; // @[el2_lib.scala 543:40] + wire _T_819 = _T_815 ? _T_817 : q_ff[13]; // @[el2_lib.scala 543:23] + wire _T_809 = |q_ff[11:0]; // @[el2_lib.scala 543:35] + wire _T_811 = ~q_ff[12]; // @[el2_lib.scala 543:40] + wire _T_813 = _T_809 ? _T_811 : q_ff[12]; // @[el2_lib.scala 543:23] + wire _T_803 = |q_ff[10:0]; // @[el2_lib.scala 543:35] + wire _T_805 = ~q_ff[11]; // @[el2_lib.scala 543:40] + wire _T_807 = _T_803 ? _T_805 : q_ff[11]; // @[el2_lib.scala 543:23] + wire _T_797 = |q_ff[9:0]; // @[el2_lib.scala 543:35] + wire _T_799 = ~q_ff[10]; // @[el2_lib.scala 543:40] + wire _T_801 = _T_797 ? _T_799 : q_ff[10]; // @[el2_lib.scala 543:23] + wire _T_791 = |q_ff[8:0]; // @[el2_lib.scala 543:35] + wire _T_793 = ~q_ff[9]; // @[el2_lib.scala 543:40] + wire _T_795 = _T_791 ? _T_793 : q_ff[9]; // @[el2_lib.scala 543:23] + wire _T_785 = |q_ff[7:0]; // @[el2_lib.scala 543:35] + wire _T_787 = ~q_ff[8]; // @[el2_lib.scala 543:40] + wire _T_789 = _T_785 ? _T_787 : q_ff[8]; // @[el2_lib.scala 543:23] + wire _T_779 = |q_ff[6:0]; // @[el2_lib.scala 543:35] + wire _T_781 = ~q_ff[7]; // @[el2_lib.scala 543:40] + wire _T_783 = _T_779 ? _T_781 : q_ff[7]; // @[el2_lib.scala 543:23] + wire _T_773 = |q_ff[5:0]; // @[el2_lib.scala 543:35] + wire _T_775 = ~q_ff[6]; // @[el2_lib.scala 543:40] + wire _T_777 = _T_773 ? _T_775 : q_ff[6]; // @[el2_lib.scala 543:23] + wire _T_767 = |q_ff[4:0]; // @[el2_lib.scala 543:35] + wire _T_769 = ~q_ff[5]; // @[el2_lib.scala 543:40] + wire _T_771 = _T_767 ? _T_769 : q_ff[5]; // @[el2_lib.scala 543:23] + wire _T_761 = |q_ff[3:0]; // @[el2_lib.scala 543:35] + wire _T_763 = ~q_ff[4]; // @[el2_lib.scala 543:40] + wire _T_765 = _T_761 ? _T_763 : q_ff[4]; // @[el2_lib.scala 543:23] + wire _T_755 = |q_ff[2:0]; // @[el2_lib.scala 543:35] + wire _T_757 = ~q_ff[3]; // @[el2_lib.scala 543:40] + wire _T_759 = _T_755 ? _T_757 : q_ff[3]; // @[el2_lib.scala 543:23] + wire _T_749 = |q_ff[1:0]; // @[el2_lib.scala 543:35] + wire _T_751 = ~q_ff[2]; // @[el2_lib.scala 543:40] + wire _T_753 = _T_749 ? _T_751 : q_ff[2]; // @[el2_lib.scala 543:23] + wire _T_743 = |q_ff[0]; // @[el2_lib.scala 543:35] + wire _T_745 = ~q_ff[1]; // @[el2_lib.scala 543:40] + wire _T_747 = _T_743 ? _T_745 : q_ff[1]; // @[el2_lib.scala 543:23] + wire [6:0] _T_933 = {_T_783,_T_777,_T_771,_T_765,_T_759,_T_753,_T_747}; // @[el2_lib.scala 545:14] + wire [14:0] _T_941 = {_T_831,_T_825,_T_819,_T_813,_T_807,_T_801,_T_795,_T_789,_T_933}; // @[el2_lib.scala 545:14] + wire [30:0] _T_957 = {_T_927,_T_921,_T_915,_T_909,_T_903,_T_897,_T_891,_T_885,_T_948,_T_941}; // @[el2_lib.scala 545:14] + wire [31:0] _T_959 = {_T_957,q_ff[0]}; // @[Cat.scala 29:58] + wire [31:0] dividend_eff = _T_738 ? _T_959 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 175:22] + wire [32:0] _T_995 = run_state ? 33'h1ffffffff : 33'h0; // @[Bitwise.scala 72:12] + wire _T_1007 = _T_685 & rem_ff; // @[el2_exu_div_ctl.scala 191:41] + reg [32:0] a_ff; // @[el2_lib.scala 514:16] + wire rem_correct = _T_1007 & a_ff[32]; // @[el2_exu_div_ctl.scala 191:50] + wire [32:0] _T_980 = rem_correct ? a_ff : 33'h0; // @[Mux.scala 27:72] + wire _T_968 = ~rem_correct; // @[el2_exu_div_ctl.scala 182:6] + wire _T_969 = ~shortq_enable_ff; // @[el2_exu_div_ctl.scala 182:21] + wire _T_970 = _T_968 & _T_969; // @[el2_exu_div_ctl.scala 182:19] + wire [32:0] _T_974 = {a_ff[31:0],q_ff[32]}; // @[Cat.scala 29:58] + wire [32:0] _T_981 = _T_970 ? _T_974 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] _T_983 = _T_980 | _T_981; // @[Mux.scala 27:72] + wire _T_976 = _T_968 & shortq_enable_ff; // @[el2_exu_div_ctl.scala 183:19] + wire [55:0] _T_965 = {24'h0,dividend_eff}; // @[Cat.scala 29:58] + wire [86:0] _GEN_5 = {{31'd0}, _T_965}; // @[el2_exu_div_ctl.scala 179:47] + wire [86:0] _T_966 = _GEN_5 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 179:47] + wire [55:0] a_eff_shift = _T_966[55:0]; // @[el2_exu_div_ctl.scala 179:15] + wire [32:0] _T_979 = {9'h0,a_eff_shift[55:32]}; // @[Cat.scala 29:58] + wire [32:0] _T_982 = _T_976 ? _T_979 : 33'h0; // @[Mux.scala 27:72] + wire [32:0] a_eff = _T_983 | _T_982; // @[Mux.scala 27:72] + wire [32:0] a_shift = _T_995 & a_eff; // @[el2_exu_div_ctl.scala 186:33] + wire _T_1004 = a_ff[32] | rem_correct; // @[el2_exu_div_ctl.scala 190:21] + reg divisor_neg_ff; // @[Reg.scala 27:20] + wire m_already_comp = divisor_neg_ff & sign_ff; // @[el2_exu_div_ctl.scala 188:48] + wire add = _T_1004 ^ m_already_comp; // @[el2_exu_div_ctl.scala 190:36] + wire [32:0] _T_963 = ~m_ff; // @[el2_exu_div_ctl.scala 178:35] + wire [32:0] m_eff = add ? m_ff : _T_963; // @[el2_exu_div_ctl.scala 178:15] + wire [32:0] _T_997 = a_shift + m_eff; // @[el2_exu_div_ctl.scala 187:41] + wire _T_998 = ~add; // @[el2_exu_div_ctl.scala 187:65] + wire [32:0] _T_999 = {32'h0,_T_998}; // @[Cat.scala 29:58] + wire [32:0] _T_1001 = _T_997 + _T_999; // @[el2_exu_div_ctl.scala 187:49] + wire [32:0] a_in = _T_995 & _T_1001; // @[el2_exu_div_ctl.scala 187:30] + wire _T_719 = ~a_in[32]; // @[el2_exu_div_ctl.scala 171:85] + wire [32:0] _T_720 = {dividend_eff,_T_719}; // @[Cat.scala 29:58] + wire [63:0] _GEN_6 = {{31'd0}, _T_720}; // @[el2_exu_div_ctl.scala 171:96] + wire [63:0] _T_721 = _GEN_6 << shortq_shift_ff; // @[el2_exu_div_ctl.scala 171:96] + wire _T_723 = ~_T_714; // @[el2_exu_div_ctl.scala 172:18] + wire _T_724 = run_state & _T_723; // @[el2_exu_div_ctl.scala 172:16] + wire [32:0] _T_729 = {q_ff[31:0],_T_719}; // @[Cat.scala 29:58] + wire [32:0] _T_730 = _T_711 ? _T_713 : 33'h0; // @[Mux.scala 27:72] + wire [63:0] _T_731 = _T_715 ? _T_721 : 64'h0; // @[Mux.scala 27:72] + wire [32:0] _T_732 = _T_724 ? _T_729 : 33'h0; // @[Mux.scala 27:72] + wire [63:0] _GEN_7 = {{31'd0}, _T_730}; // @[Mux.scala 27:72] + wire [63:0] _T_733 = _GEN_7 | _T_731; // @[Mux.scala 27:72] + wire [63:0] _GEN_8 = {{31'd0}, _T_732}; // @[Mux.scala 27:72] + wire [63:0] _T_734 = _T_733 | _GEN_8; // @[Mux.scala 27:72] + wire _T_737 = run_state & _T_697; // @[el2_exu_div_ctl.scala 174:48] + wire _T_988 = count != 6'h21; // @[el2_exu_div_ctl.scala 185:73] + wire _T_989 = _T_737 & _T_988; // @[el2_exu_div_ctl.scala 185:64] + wire _T_990 = io_dp_valid | _T_989; // @[el2_exu_div_ctl.scala 185:34] + wire _T_1010 = dividend_neg_ff ^ divisor_neg_ff; // @[el2_exu_div_ctl.scala 192:50] + wire _T_1011 = sign_ff & _T_1010; // @[el2_exu_div_ctl.scala 192:31] + wire [31:0] q_ff_eff = _T_1011 ? _T_959 : q_ff[31:0]; // @[el2_exu_div_ctl.scala 192:21] + wire _T_1239 = |a_ff[0]; // @[el2_lib.scala 543:35] + wire _T_1241 = ~a_ff[1]; // @[el2_lib.scala 543:40] + wire _T_1243 = _T_1239 ? _T_1241 : a_ff[1]; // @[el2_lib.scala 543:23] + wire _T_1245 = |a_ff[1:0]; // @[el2_lib.scala 543:35] + wire _T_1247 = ~a_ff[2]; // @[el2_lib.scala 543:40] + wire _T_1249 = _T_1245 ? _T_1247 : a_ff[2]; // @[el2_lib.scala 543:23] + wire _T_1251 = |a_ff[2:0]; // @[el2_lib.scala 543:35] + wire _T_1253 = ~a_ff[3]; // @[el2_lib.scala 543:40] + wire _T_1255 = _T_1251 ? _T_1253 : a_ff[3]; // @[el2_lib.scala 543:23] + wire _T_1257 = |a_ff[3:0]; // @[el2_lib.scala 543:35] + wire _T_1259 = ~a_ff[4]; // @[el2_lib.scala 543:40] + wire _T_1261 = _T_1257 ? _T_1259 : a_ff[4]; // @[el2_lib.scala 543:23] + wire _T_1263 = |a_ff[4:0]; // @[el2_lib.scala 543:35] + wire _T_1265 = ~a_ff[5]; // @[el2_lib.scala 543:40] + wire _T_1267 = _T_1263 ? _T_1265 : a_ff[5]; // @[el2_lib.scala 543:23] + wire _T_1269 = |a_ff[5:0]; // @[el2_lib.scala 543:35] + wire _T_1271 = ~a_ff[6]; // @[el2_lib.scala 543:40] + wire _T_1273 = _T_1269 ? _T_1271 : a_ff[6]; // @[el2_lib.scala 543:23] + wire _T_1275 = |a_ff[6:0]; // @[el2_lib.scala 543:35] + wire _T_1277 = ~a_ff[7]; // @[el2_lib.scala 543:40] + wire _T_1279 = _T_1275 ? _T_1277 : a_ff[7]; // @[el2_lib.scala 543:23] + wire _T_1281 = |a_ff[7:0]; // @[el2_lib.scala 543:35] + wire _T_1283 = ~a_ff[8]; // @[el2_lib.scala 543:40] + wire _T_1285 = _T_1281 ? _T_1283 : a_ff[8]; // @[el2_lib.scala 543:23] + wire _T_1287 = |a_ff[8:0]; // @[el2_lib.scala 543:35] + wire _T_1289 = ~a_ff[9]; // @[el2_lib.scala 543:40] + wire _T_1291 = _T_1287 ? _T_1289 : a_ff[9]; // @[el2_lib.scala 543:23] + wire _T_1293 = |a_ff[9:0]; // @[el2_lib.scala 543:35] + wire _T_1295 = ~a_ff[10]; // @[el2_lib.scala 543:40] + wire _T_1297 = _T_1293 ? _T_1295 : a_ff[10]; // @[el2_lib.scala 543:23] + wire _T_1299 = |a_ff[10:0]; // @[el2_lib.scala 543:35] + wire _T_1301 = ~a_ff[11]; // @[el2_lib.scala 543:40] + wire _T_1303 = _T_1299 ? _T_1301 : a_ff[11]; // @[el2_lib.scala 543:23] + wire _T_1305 = |a_ff[11:0]; // @[el2_lib.scala 543:35] + wire _T_1307 = ~a_ff[12]; // @[el2_lib.scala 543:40] + wire _T_1309 = _T_1305 ? _T_1307 : a_ff[12]; // @[el2_lib.scala 543:23] + wire _T_1311 = |a_ff[12:0]; // @[el2_lib.scala 543:35] + wire _T_1313 = ~a_ff[13]; // @[el2_lib.scala 543:40] + wire _T_1315 = _T_1311 ? _T_1313 : a_ff[13]; // @[el2_lib.scala 543:23] + wire _T_1317 = |a_ff[13:0]; // @[el2_lib.scala 543:35] + wire _T_1319 = ~a_ff[14]; // @[el2_lib.scala 543:40] + wire _T_1321 = _T_1317 ? _T_1319 : a_ff[14]; // @[el2_lib.scala 543:23] + wire _T_1323 = |a_ff[14:0]; // @[el2_lib.scala 543:35] + wire _T_1325 = ~a_ff[15]; // @[el2_lib.scala 543:40] + wire _T_1327 = _T_1323 ? _T_1325 : a_ff[15]; // @[el2_lib.scala 543:23] + wire _T_1329 = |a_ff[15:0]; // @[el2_lib.scala 543:35] + wire _T_1331 = ~a_ff[16]; // @[el2_lib.scala 543:40] + wire _T_1333 = _T_1329 ? _T_1331 : a_ff[16]; // @[el2_lib.scala 543:23] + wire _T_1335 = |a_ff[16:0]; // @[el2_lib.scala 543:35] + wire _T_1337 = ~a_ff[17]; // @[el2_lib.scala 543:40] + wire _T_1339 = _T_1335 ? _T_1337 : a_ff[17]; // @[el2_lib.scala 543:23] + wire _T_1341 = |a_ff[17:0]; // @[el2_lib.scala 543:35] + wire _T_1343 = ~a_ff[18]; // @[el2_lib.scala 543:40] + wire _T_1345 = _T_1341 ? _T_1343 : a_ff[18]; // @[el2_lib.scala 543:23] + wire _T_1347 = |a_ff[18:0]; // @[el2_lib.scala 543:35] + wire _T_1349 = ~a_ff[19]; // @[el2_lib.scala 543:40] + wire _T_1351 = _T_1347 ? _T_1349 : a_ff[19]; // @[el2_lib.scala 543:23] + wire _T_1353 = |a_ff[19:0]; // @[el2_lib.scala 543:35] + wire _T_1355 = ~a_ff[20]; // @[el2_lib.scala 543:40] + wire _T_1357 = _T_1353 ? _T_1355 : a_ff[20]; // @[el2_lib.scala 543:23] + wire _T_1359 = |a_ff[20:0]; // @[el2_lib.scala 543:35] + wire _T_1361 = ~a_ff[21]; // @[el2_lib.scala 543:40] + wire _T_1363 = _T_1359 ? _T_1361 : a_ff[21]; // @[el2_lib.scala 543:23] + wire _T_1365 = |a_ff[21:0]; // @[el2_lib.scala 543:35] + wire _T_1367 = ~a_ff[22]; // @[el2_lib.scala 543:40] + wire _T_1369 = _T_1365 ? _T_1367 : a_ff[22]; // @[el2_lib.scala 543:23] + wire _T_1371 = |a_ff[22:0]; // @[el2_lib.scala 543:35] + wire _T_1373 = ~a_ff[23]; // @[el2_lib.scala 543:40] + wire _T_1375 = _T_1371 ? _T_1373 : a_ff[23]; // @[el2_lib.scala 543:23] + wire _T_1377 = |a_ff[23:0]; // @[el2_lib.scala 543:35] + wire _T_1379 = ~a_ff[24]; // @[el2_lib.scala 543:40] + wire _T_1381 = _T_1377 ? _T_1379 : a_ff[24]; // @[el2_lib.scala 543:23] + wire _T_1383 = |a_ff[24:0]; // @[el2_lib.scala 543:35] + wire _T_1385 = ~a_ff[25]; // @[el2_lib.scala 543:40] + wire _T_1387 = _T_1383 ? _T_1385 : a_ff[25]; // @[el2_lib.scala 543:23] + wire _T_1389 = |a_ff[25:0]; // @[el2_lib.scala 543:35] + wire _T_1391 = ~a_ff[26]; // @[el2_lib.scala 543:40] + wire _T_1393 = _T_1389 ? _T_1391 : a_ff[26]; // @[el2_lib.scala 543:23] + wire _T_1395 = |a_ff[26:0]; // @[el2_lib.scala 543:35] + wire _T_1397 = ~a_ff[27]; // @[el2_lib.scala 543:40] + wire _T_1399 = _T_1395 ? _T_1397 : a_ff[27]; // @[el2_lib.scala 543:23] + wire _T_1401 = |a_ff[27:0]; // @[el2_lib.scala 543:35] + wire _T_1403 = ~a_ff[28]; // @[el2_lib.scala 543:40] + wire _T_1405 = _T_1401 ? _T_1403 : a_ff[28]; // @[el2_lib.scala 543:23] + wire _T_1407 = |a_ff[28:0]; // @[el2_lib.scala 543:35] + wire _T_1409 = ~a_ff[29]; // @[el2_lib.scala 543:40] + wire _T_1411 = _T_1407 ? _T_1409 : a_ff[29]; // @[el2_lib.scala 543:23] + wire _T_1413 = |a_ff[29:0]; // @[el2_lib.scala 543:35] + wire _T_1415 = ~a_ff[30]; // @[el2_lib.scala 543:40] + wire _T_1417 = _T_1413 ? _T_1415 : a_ff[30]; // @[el2_lib.scala 543:23] + wire _T_1419 = |a_ff[30:0]; // @[el2_lib.scala 543:35] + wire _T_1421 = ~a_ff[31]; // @[el2_lib.scala 543:40] + wire _T_1423 = _T_1419 ? _T_1421 : a_ff[31]; // @[el2_lib.scala 543:23] + wire [6:0] _T_1429 = {_T_1279,_T_1273,_T_1267,_T_1261,_T_1255,_T_1249,_T_1243}; // @[el2_lib.scala 545:14] + wire [14:0] _T_1437 = {_T_1327,_T_1321,_T_1315,_T_1309,_T_1303,_T_1297,_T_1291,_T_1285,_T_1429}; // @[el2_lib.scala 545:14] + wire [7:0] _T_1444 = {_T_1375,_T_1369,_T_1363,_T_1357,_T_1351,_T_1345,_T_1339,_T_1333}; // @[el2_lib.scala 545:14] + wire [30:0] _T_1453 = {_T_1423,_T_1417,_T_1411,_T_1405,_T_1399,_T_1393,_T_1387,_T_1381,_T_1444,_T_1437}; // @[el2_lib.scala 545:14] + wire [31:0] _T_1455 = {_T_1453,a_ff[0]}; // @[Cat.scala 29:58] + wire [31:0] a_ff_eff = _T_738 ? _T_1455 : a_ff[31:0]; // @[el2_exu_div_ctl.scala 193:21] + reg smallnum_case_ff; // @[el2_exu_div_ctl.scala 212:32] + reg [3:0] smallnum_ff; // @[el2_exu_div_ctl.scala 213:27] + wire [31:0] _T_1458 = {28'h0,smallnum_ff}; // @[Cat.scala 29:58] + wire _T_1460 = ~smallnum_case_ff; // @[el2_exu_div_ctl.scala 198:6] + wire _T_1462 = _T_1460 & _T_9; // @[el2_exu_div_ctl.scala 198:24] + wire [31:0] _T_1464 = smallnum_case_ff ? _T_1458 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1465 = rem_ff ? a_ff_eff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1466 = _T_1462 ? q_ff_eff : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1467 = _T_1464 | _T_1465; // @[Mux.scala 27:72] + wire _T_1499 = _T_709 & io_divisor[31]; // @[el2_exu_div_ctl.scala 219:36] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + assign io_out = _T_1467 | _T_1466; // @[el2_exu_div_ctl.scala 50:10 el2_exu_div_ctl.scala 195:10] + assign io_finish_dly = finish_ff & _T; // @[el2_exu_div_ctl.scala 51:17 el2_exu_div_ctl.scala 165:18] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_688 | finish_ff; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_dp_valid | _T_737; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_990 | rem_correct; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = io_dp_valid; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + valid_ff_x = _RAND_0[0:0]; + _RAND_1 = {2{`RANDOM}}; + q_ff = _RAND_1[32:0]; + _RAND_2 = {2{`RANDOM}}; + m_ff = _RAND_2[32:0]; + _RAND_3 = {1{`RANDOM}}; + rem_ff = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + sign_ff = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + shortq_shift_xx = _RAND_5[3:0]; + _RAND_6 = {1{`RANDOM}}; + count = _RAND_6[5:0]; + _RAND_7 = {1{`RANDOM}}; + run_state = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + finish_ff = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + shortq_enable_ff = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + dividend_neg_ff = _RAND_10[0:0]; + _RAND_11 = {2{`RANDOM}}; + a_ff = _RAND_11[32:0]; + _RAND_12 = {1{`RANDOM}}; + divisor_neg_ff = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + smallnum_case_ff = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + smallnum_ff = _RAND_14[3:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + valid_ff_x = 1'h0; + end + if (reset) begin + q_ff = 33'h0; + end + if (reset) begin + m_ff = 33'h0; + end + if (reset) begin + rem_ff = 1'h0; + end + if (reset) begin + sign_ff = 1'h0; + end + if (reset) begin + shortq_shift_xx = 4'h0; + end + if (reset) begin + count = 6'h0; + end + if (reset) begin + run_state = 1'h0; + end + if (reset) begin + finish_ff = 1'h0; + end + if (reset) begin + shortq_enable_ff = 1'h0; + end + if (reset) begin + dividend_neg_ff = 1'h0; + end + if (reset) begin + a_ff = 33'h0; + end + if (reset) begin + divisor_neg_ff = 1'h0; + end + if (reset) begin + smallnum_case_ff = 1'h0; + end + if (reset) begin + smallnum_ff = 4'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + valid_ff_x <= 1'h0; + end else begin + valid_ff_x <= io_dp_valid & _T; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + q_ff <= 33'h0; + end else begin + q_ff <= _T_734[32:0]; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + m_ff <= 33'h0; + end else begin + m_ff <= {_T_1499,io_divisor}; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + rem_ff <= 1'h0; + end else if (io_dp_valid) begin + rem_ff <= io_dp_rem; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + sign_ff <= 1'h0; + end else if (io_dp_valid) begin + sign_ff <= sign_eff; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + shortq_shift_xx <= 4'h0; + end else begin + shortq_shift_xx <= _T_667 & shortq_raw; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + count <= 6'h0; + end else begin + count <= _T_700 & _T_705; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + run_state <= 1'h0; + end else begin + run_state <= _T_691 & _T; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + finish_ff <= 1'h0; + end else begin + finish_ff <= finish & _T; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + shortq_enable_ff <= 1'h0; + end else begin + shortq_enable_ff <= _T_664 & _T_665; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + dividend_neg_ff <= 1'h0; + end else if (io_dp_valid) begin + dividend_neg_ff <= io_dividend[31]; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + a_ff <= 33'h0; + end else begin + a_ff <= _T_995 & _T_1001; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + divisor_neg_ff <= 1'h0; + end else if (io_dp_valid) begin + divisor_neg_ff <= io_divisor[31]; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + smallnum_case_ff <= 1'h0; + end else begin + smallnum_case_ff <= _T_11 | _T_19; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + smallnum_ff <= 4'h0; + end else begin + smallnum_ff <= {_T_477,_T_476}; + end + end +endmodule +module el2_exu( + input clock, + input reset, + input io_scan_mode, + input [1:0] io_dec_data_en, + input [1:0] io_dec_ctl_en, + input [31:0] io_dbg_cmd_wrdata, + input io_i0_ap_land, + input io_i0_ap_lor, + input io_i0_ap_lxor, + input io_i0_ap_sll, + input io_i0_ap_srl, + input io_i0_ap_sra, + input io_i0_ap_beq, + input io_i0_ap_bne, + input io_i0_ap_blt, + input io_i0_ap_bge, + input io_i0_ap_add, + input io_i0_ap_sub, + input io_i0_ap_slt, + input io_i0_ap_unsign, + input io_i0_ap_jal, + input io_i0_ap_predict_t, + input io_i0_ap_predict_nt, + input io_i0_ap_csr_write, + input io_i0_ap_csr_imm, + input io_dec_debug_wdata_rs1_d, + input io_dec_i0_predict_p_d_misp, + input io_dec_i0_predict_p_d_ataken, + input io_dec_i0_predict_p_d_boffset, + input io_dec_i0_predict_p_d_pc4, + input [1:0] io_dec_i0_predict_p_d_hist, + input [11:0] io_dec_i0_predict_p_d_toffset, + input io_dec_i0_predict_p_d_valid, + input io_dec_i0_predict_p_d_br_error, + input io_dec_i0_predict_p_d_br_start_error, + input [30:0] io_dec_i0_predict_p_d_prett, + input io_dec_i0_predict_p_d_pcall, + input io_dec_i0_predict_p_d_pret, + input io_dec_i0_predict_p_d_pja, + input io_dec_i0_predict_p_d_way, + input [7:0] io_i0_predict_fghr_d, + input [7:0] io_i0_predict_index_d, + input [4:0] io_i0_predict_btag_d, + input io_dec_i0_rs1_en_d, + input io_dec_i0_rs2_en_d, + input [31:0] io_gpr_i0_rs1_d, + input [31:0] io_gpr_i0_rs2_d, + input [31:0] io_dec_i0_immed_d, + input [31:0] io_dec_i0_rs1_bypass_data_d, + input [31:0] io_dec_i0_rs2_bypass_data_d, + input [11:0] io_dec_i0_br_immed_d, + input io_dec_i0_alu_decode_d, + input io_dec_i0_select_pc_d, + input [30:0] io_dec_i0_pc_d, + input [1:0] io_dec_i0_rs1_bypass_en_d, + input [1:0] io_dec_i0_rs2_bypass_en_d, + input io_dec_csr_ren_d, + input io_mul_p_valid, + input io_mul_p_rs1_sign, + input io_mul_p_rs2_sign, + input io_mul_p_low, + input io_mul_p_bext, + input io_mul_p_bdep, + input io_mul_p_clmul, + input io_mul_p_clmulh, + input io_mul_p_clmulr, + input io_mul_p_grev, + input io_mul_p_shfl, + input io_mul_p_unshfl, + input io_mul_p_crc32_b, + input io_mul_p_crc32_h, + input io_mul_p_crc32_w, + input io_mul_p_crc32c_b, + input io_mul_p_crc32c_h, + input io_mul_p_crc32c_w, + input io_mul_p_bfp, + input io_div_p_valid, + input io_div_p_unsign, + input io_div_p_rem, + input io_dec_div_cancel, + input [30:0] io_pred_correct_npc_x, + input io_dec_tlu_flush_lower_r, + input [30:0] io_dec_tlu_flush_path_r, + input io_dec_extint_stall, + input [29:0] io_dec_tlu_meihap, + output [31:0] io_exu_lsu_rs1_d, + output [31:0] io_exu_lsu_rs2_d, + output io_exu_flush_final, + output [30:0] io_exu_flush_path_final, + output [31:0] io_exu_i0_result_x, + output [30:0] io_exu_i0_pc_x, + output [31:0] io_exu_csr_rs1_x, + output [30:0] io_exu_npc_r, + output [1:0] io_exu_i0_br_hist_r, + output io_exu_i0_br_error_r, + output io_exu_i0_br_start_error_r, + output [7:0] io_exu_i0_br_index_r, + output io_exu_i0_br_valid_r, + output io_exu_i0_br_mp_r, + output io_exu_i0_br_middle_r, + output [7:0] io_exu_i0_br_fghr_r, + output io_exu_i0_br_way_r, + output io_exu_mp_pkt_misp, + output io_exu_mp_pkt_ataken, + output io_exu_mp_pkt_boffset, + output io_exu_mp_pkt_pc4, + output [1:0] io_exu_mp_pkt_hist, + output [11:0] io_exu_mp_pkt_toffset, + output io_exu_mp_pkt_valid, + output io_exu_mp_pkt_br_error, + output io_exu_mp_pkt_br_start_error, + output [30:0] io_exu_mp_pkt_prett, + output io_exu_mp_pkt_pcall, + output io_exu_mp_pkt_pret, + output io_exu_mp_pkt_pja, + output io_exu_mp_pkt_way, + output [7:0] io_exu_mp_eghr, + output [7:0] io_exu_mp_fghr, + output [7:0] io_exu_mp_index, + output [4:0] io_exu_mp_btag, + output io_exu_pmu_i0_br_misp, + output io_exu_pmu_i0_br_ataken, + output io_exu_pmu_i0_pc4, + output [31:0] io_exu_div_result, + output io_exu_div_wren +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 518:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 518:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_12_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_13_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_14_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_15_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_16_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_17_io_scan_mode; // @[el2_lib.scala 508:23] + wire i_alu_clock; // @[el2_exu.scala 125:19] + wire i_alu_reset; // @[el2_exu.scala 125:19] + wire i_alu_io_scan_mode; // @[el2_exu.scala 125:19] + wire i_alu_io_flush_upper_x; // @[el2_exu.scala 125:19] + wire i_alu_io_flush_lower_r; // @[el2_exu.scala 125:19] + wire i_alu_io_enable; // @[el2_exu.scala 125:19] + wire i_alu_io_valid_in; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_land; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_lor; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_lxor; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_sll; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_srl; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_sra; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_beq; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_bne; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_blt; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_bge; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_add; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_sub; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_slt; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_unsign; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_jal; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_predict_t; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_predict_nt; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_csr_write; // @[el2_exu.scala 125:19] + wire i_alu_io_ap_csr_imm; // @[el2_exu.scala 125:19] + wire i_alu_io_csr_ren_in; // @[el2_exu.scala 125:19] + wire [31:0] i_alu_io_a_in; // @[el2_exu.scala 125:19] + wire [31:0] i_alu_io_b_in; // @[el2_exu.scala 125:19] + wire [30:0] i_alu_io_pc_in; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_boffset; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_pc4; // @[el2_exu.scala 125:19] + wire [1:0] i_alu_io_pp_in_hist; // @[el2_exu.scala 125:19] + wire [11:0] i_alu_io_pp_in_toffset; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_valid; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_br_error; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_br_start_error; // @[el2_exu.scala 125:19] + wire [30:0] i_alu_io_pp_in_prett; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_pcall; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_pret; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_pja; // @[el2_exu.scala 125:19] + wire i_alu_io_pp_in_way; // @[el2_exu.scala 125:19] + wire [11:0] i_alu_io_brimm_in; // @[el2_exu.scala 125:19] + wire [31:0] i_alu_io_result_ff; // @[el2_exu.scala 125:19] + wire i_alu_io_flush_upper_out; // @[el2_exu.scala 125:19] + wire i_alu_io_flush_final_out; // @[el2_exu.scala 125:19] + wire [30:0] i_alu_io_flush_path_out; // @[el2_exu.scala 125:19] + wire [30:0] i_alu_io_pc_ff; // @[el2_exu.scala 125:19] + wire i_alu_io_pred_correct_out; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_misp; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_ataken; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_boffset; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_pc4; // @[el2_exu.scala 125:19] + wire [1:0] i_alu_io_predict_p_out_hist; // @[el2_exu.scala 125:19] + wire [11:0] i_alu_io_predict_p_out_toffset; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_valid; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_br_error; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_br_start_error; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_pcall; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_pret; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_pja; // @[el2_exu.scala 125:19] + wire i_alu_io_predict_p_out_way; // @[el2_exu.scala 125:19] + wire i_mul_clock; // @[el2_exu.scala 146:19] + wire i_mul_reset; // @[el2_exu.scala 146:19] + wire i_mul_io_scan_mode; // @[el2_exu.scala 146:19] + wire i_mul_io_mul_p_valid; // @[el2_exu.scala 146:19] + wire i_mul_io_mul_p_rs1_sign; // @[el2_exu.scala 146:19] + wire i_mul_io_mul_p_rs2_sign; // @[el2_exu.scala 146:19] + wire i_mul_io_mul_p_low; // @[el2_exu.scala 146:19] + wire [31:0] i_mul_io_rs1_in; // @[el2_exu.scala 146:19] + wire [31:0] i_mul_io_rs2_in; // @[el2_exu.scala 146:19] + wire [31:0] i_mul_io_result_x; // @[el2_exu.scala 146:19] + wire i_div_clock; // @[el2_exu.scala 153:19] + wire i_div_reset; // @[el2_exu.scala 153:19] + wire i_div_io_scan_mode; // @[el2_exu.scala 153:19] + wire i_div_io_dp_valid; // @[el2_exu.scala 153:19] + wire i_div_io_dp_unsign; // @[el2_exu.scala 153:19] + wire i_div_io_dp_rem; // @[el2_exu.scala 153:19] + wire [31:0] i_div_io_dividend; // @[el2_exu.scala 153:19] + wire [31:0] i_div_io_divisor; // @[el2_exu.scala 153:19] + wire i_div_io_cancel; // @[el2_exu.scala 153:19] + wire [31:0] i_div_io_out; // @[el2_exu.scala 153:19] + wire i_div_io_finish_dly; // @[el2_exu.scala 153:19] + wire [15:0] _T = {io_i0_predict_fghr_d,io_i0_predict_index_d}; // @[Cat.scala 29:58] + reg [30:0] i0_flush_path_x; // @[el2_lib.scala 514:16] + reg [31:0] _T_3; // @[el2_lib.scala 514:16] + reg i0_predict_p_x_misp; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_ataken; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_boffset; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pc4; // @[el2_lib.scala 524:16] + reg [1:0] i0_predict_p_x_hist; // @[el2_lib.scala 524:16] + reg [11:0] i0_predict_p_x_toffset; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_valid; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_br_error; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_br_start_error; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pcall; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pret; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_pja; // @[el2_lib.scala 524:16] + reg i0_predict_p_x_way; // @[el2_lib.scala 524:16] + reg [20:0] predpipe_x; // @[el2_lib.scala 514:16] + reg [20:0] predpipe_r; // @[el2_lib.scala 514:16] + reg [7:0] ghr_x; // @[el2_lib.scala 514:16] + reg i0_pred_correct_upper_x; // @[el2_lib.scala 514:16] + reg i0_flush_upper_x; // @[el2_lib.scala 514:16] + reg i0_taken_x; // @[el2_lib.scala 514:16] + reg i0_valid_x; // @[el2_lib.scala 514:16] + reg i0_pp_r_misp; // @[el2_lib.scala 524:16] + reg i0_pp_r_ataken; // @[el2_lib.scala 524:16] + reg i0_pp_r_boffset; // @[el2_lib.scala 524:16] + reg i0_pp_r_pc4; // @[el2_lib.scala 524:16] + reg [1:0] i0_pp_r_hist; // @[el2_lib.scala 524:16] + reg i0_pp_r_valid; // @[el2_lib.scala 524:16] + reg i0_pp_r_br_error; // @[el2_lib.scala 524:16] + reg i0_pp_r_br_start_error; // @[el2_lib.scala 524:16] + reg i0_pp_r_way; // @[el2_lib.scala 524:16] + reg [5:0] pred_temp1; // @[el2_lib.scala 514:16] + reg i0_pred_correct_upper_r; // @[el2_lib.scala 514:16] + reg [30:0] i0_flush_path_upper_r; // @[el2_lib.scala 514:16] + reg [24:0] pred_temp2; // @[el2_lib.scala 514:16] + wire [30:0] _T_23 = {pred_temp2,pred_temp1}; // @[Cat.scala 29:58] + wire _T_149 = ~io_dec_tlu_flush_lower_r; // @[el2_exu.scala 178:6] + wire i0_predict_p_d_valid = i_alu_io_predict_p_out_valid; // @[el2_exu.scala 24:46 el2_exu.scala 142:41] + wire _T_145 = i0_predict_p_d_valid & io_dec_i0_alu_decode_d; // @[el2_exu.scala 171:54] + wire i0_valid_d = _T_145 & _T_149; // @[el2_exu.scala 171:79] + wire _T_150 = _T_149 & i0_valid_d; // @[el2_exu.scala 178:32] + reg [7:0] ghr_d; // @[el2_lib.scala 514:16] + wire i0_predict_p_d_ataken = i_alu_io_predict_p_out_ataken; // @[el2_exu.scala 24:46 el2_exu.scala 142:41] + wire i0_taken_d = i0_predict_p_d_ataken & io_dec_i0_alu_decode_d; // @[el2_exu.scala 172:54] + wire [7:0] _T_153 = {ghr_d[6:0],i0_taken_d}; // @[Cat.scala 29:58] + wire [7:0] _T_159 = _T_150 ? _T_153 : 8'h0; // @[Mux.scala 27:72] + wire _T_155 = ~i0_valid_d; // @[el2_exu.scala 179:34] + wire _T_156 = _T_149 & _T_155; // @[el2_exu.scala 179:32] + wire [7:0] _T_160 = _T_156 ? ghr_d : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_162 = _T_159 | _T_160; // @[Mux.scala 27:72] + wire [7:0] _T_161 = io_dec_tlu_flush_lower_r ? ghr_x : 8'h0; // @[Mux.scala 27:72] + wire [7:0] ghr_d_ns = _T_162 | _T_161; // @[Mux.scala 27:72] + wire _T_39 = ghr_d_ns != ghr_d; // @[el2_exu.scala 72:39] + reg mul_valid_x; // @[el2_lib.scala 514:16] + wire _T_40 = io_mul_p_valid != mul_valid_x; // @[el2_exu.scala 72:70] + wire _T_41 = _T_39 | _T_40; // @[el2_exu.scala 72:50] + reg flush_lower_ff; // @[el2_lib.scala 514:16] + wire _T_42 = io_dec_tlu_flush_lower_r != flush_lower_ff; // @[el2_exu.scala 72:116] + wire i0_rs1_bypass_en_d = io_dec_i0_rs1_bypass_en_d[0] | io_dec_i0_rs1_bypass_en_d[1]; // @[el2_exu.scala 73:65] + wire i0_rs2_bypass_en_d = io_dec_i0_rs2_bypass_en_d[0] | io_dec_i0_rs2_bypass_en_d[1]; // @[el2_exu.scala 74:65] + wire [31:0] _T_52 = io_dec_i0_rs1_bypass_en_d[0] ? io_dec_i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_53 = io_dec_i0_rs1_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_rs1_bypass_data_d = _T_52 | _T_53; // @[Mux.scala 27:72] + wire [31:0] _T_59 = io_dec_i0_rs2_bypass_en_d[0] ? io_dec_i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_60 = io_dec_i0_rs2_bypass_en_d[1] ? io_exu_i0_result_x : 32'h0; // @[Mux.scala 27:72] + wire [31:0] i0_rs2_bypass_data_d = _T_59 | _T_60; // @[Mux.scala 27:72] + wire _T_63 = ~i0_rs1_bypass_en_d; // @[el2_exu.scala 88:6] + wire _T_64 = _T_63 & io_dec_i0_select_pc_d; // @[el2_exu.scala 88:26] + wire [31:0] _T_66 = {io_dec_i0_pc_d,1'h0}; // @[Cat.scala 29:58] + wire _T_68 = _T_63 & io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 89:26] + wire _T_71 = ~io_dec_debug_wdata_rs1_d; // @[el2_exu.scala 90:28] + wire _T_72 = _T_63 & _T_71; // @[el2_exu.scala 90:26] + wire _T_73 = _T_72 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 90:54] + wire [31:0] _T_75 = i0_rs1_bypass_en_d ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_76 = _T_64 ? _T_66 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_77 = _T_68 ? io_dbg_cmd_wrdata : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_78 = _T_73 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_79 = _T_75 | _T_76; // @[Mux.scala 27:72] + wire [31:0] _T_80 = _T_79 | _T_77; // @[Mux.scala 27:72] + wire [31:0] i0_rs1_d = _T_80 | _T_78; // @[Mux.scala 27:72] + wire _T_82 = ~i0_rs2_bypass_en_d; // @[el2_exu.scala 94:6] + wire _T_83 = _T_82 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 94:26] + wire [31:0] _T_88 = _T_83 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_89 = _T_82 ? io_dec_i0_immed_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_90 = i0_rs2_bypass_en_d ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_91 = _T_88 | _T_89; // @[Mux.scala 27:72] + wire [31:0] _T_92 = _T_91 | _T_90; // @[Mux.scala 27:72] + wire _T_94 = ~io_dec_extint_stall; // @[el2_exu.scala 101:28] + wire _T_95 = _T_63 & _T_94; // @[el2_exu.scala 101:26] + wire _T_96 = _T_95 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 101:49] + wire _T_99 = i0_rs1_bypass_en_d & _T_94; // @[el2_exu.scala 102:25] + wire [31:0] _T_102 = {io_dec_tlu_meihap,2'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_103 = _T_96 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_104 = _T_99 ? i0_rs1_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_105 = io_dec_extint_stall ? _T_102 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_106 = _T_103 | _T_104; // @[Mux.scala 27:72] + wire _T_111 = _T_82 & _T_94; // @[el2_exu.scala 107:26] + wire _T_112 = _T_111 & io_dec_i0_rs2_en_d; // @[el2_exu.scala 107:49] + wire _T_115 = i0_rs2_bypass_en_d & _T_94; // @[el2_exu.scala 108:25] + wire [31:0] _T_117 = _T_112 ? io_gpr_i0_rs2_d : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_118 = _T_115 ? i0_rs2_bypass_data_d : 32'h0; // @[Mux.scala 27:72] + wire _T_122 = _T_63 & io_dec_i0_rs1_en_d; // @[el2_exu.scala 112:26] + wire [31:0] _T_125 = _T_122 ? io_gpr_i0_rs1_d : 32'h0; // @[Mux.scala 27:72] + wire [7:0] _T_167 = {ghr_x[6:0],i0_taken_x}; // @[Cat.scala 29:58] + wire [20:0] final_predpipe_mp = i0_flush_upper_x ? predpipe_x : 21'h0; // @[el2_exu.scala 196:49] + wire _T_179 = i0_flush_upper_x & _T_149; // @[el2_exu.scala 198:67] + wire [30:0] i0_flush_path_d = i_alu_io_flush_path_out; // @[el2_exu.scala 23:46 el2_exu.scala 141:41] + wire [31:0] pred_correct_npc_r = {{1'd0}, _T_23}; // @[el2_exu.scala 28:46 el2_exu.scala 59:41] + wire [31:0] _T_188 = i0_pred_correct_upper_r ? pred_correct_npc_r : {{1'd0}, i0_flush_path_upper_r}; // @[el2_exu.scala 216:56] + wire [31:0] i0_rs2_d = _T_92; // @[Mux.scala 27:72 Mux.scala 27:72] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 518:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + rvclkhdr rvclkhdr_12 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_12_io_l1clk), + .io_clk(rvclkhdr_12_io_clk), + .io_en(rvclkhdr_12_io_en), + .io_scan_mode(rvclkhdr_12_io_scan_mode) + ); + rvclkhdr rvclkhdr_13 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_13_io_l1clk), + .io_clk(rvclkhdr_13_io_clk), + .io_en(rvclkhdr_13_io_en), + .io_scan_mode(rvclkhdr_13_io_scan_mode) + ); + rvclkhdr rvclkhdr_14 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_14_io_l1clk), + .io_clk(rvclkhdr_14_io_clk), + .io_en(rvclkhdr_14_io_en), + .io_scan_mode(rvclkhdr_14_io_scan_mode) + ); + rvclkhdr rvclkhdr_15 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_15_io_l1clk), + .io_clk(rvclkhdr_15_io_clk), + .io_en(rvclkhdr_15_io_en), + .io_scan_mode(rvclkhdr_15_io_scan_mode) + ); + rvclkhdr rvclkhdr_16 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_16_io_l1clk), + .io_clk(rvclkhdr_16_io_clk), + .io_en(rvclkhdr_16_io_en), + .io_scan_mode(rvclkhdr_16_io_scan_mode) + ); + rvclkhdr rvclkhdr_17 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_17_io_l1clk), + .io_clk(rvclkhdr_17_io_clk), + .io_en(rvclkhdr_17_io_en), + .io_scan_mode(rvclkhdr_17_io_scan_mode) + ); + el2_exu_alu_ctl i_alu ( // @[el2_exu.scala 125:19] + .clock(i_alu_clock), + .reset(i_alu_reset), + .io_scan_mode(i_alu_io_scan_mode), + .io_flush_upper_x(i_alu_io_flush_upper_x), + .io_flush_lower_r(i_alu_io_flush_lower_r), + .io_enable(i_alu_io_enable), + .io_valid_in(i_alu_io_valid_in), + .io_ap_land(i_alu_io_ap_land), + .io_ap_lor(i_alu_io_ap_lor), + .io_ap_lxor(i_alu_io_ap_lxor), + .io_ap_sll(i_alu_io_ap_sll), + .io_ap_srl(i_alu_io_ap_srl), + .io_ap_sra(i_alu_io_ap_sra), + .io_ap_beq(i_alu_io_ap_beq), + .io_ap_bne(i_alu_io_ap_bne), + .io_ap_blt(i_alu_io_ap_blt), + .io_ap_bge(i_alu_io_ap_bge), + .io_ap_add(i_alu_io_ap_add), + .io_ap_sub(i_alu_io_ap_sub), + .io_ap_slt(i_alu_io_ap_slt), + .io_ap_unsign(i_alu_io_ap_unsign), + .io_ap_jal(i_alu_io_ap_jal), + .io_ap_predict_t(i_alu_io_ap_predict_t), + .io_ap_predict_nt(i_alu_io_ap_predict_nt), + .io_ap_csr_write(i_alu_io_ap_csr_write), + .io_ap_csr_imm(i_alu_io_ap_csr_imm), + .io_csr_ren_in(i_alu_io_csr_ren_in), + .io_a_in(i_alu_io_a_in), + .io_b_in(i_alu_io_b_in), + .io_pc_in(i_alu_io_pc_in), + .io_pp_in_boffset(i_alu_io_pp_in_boffset), + .io_pp_in_pc4(i_alu_io_pp_in_pc4), + .io_pp_in_hist(i_alu_io_pp_in_hist), + .io_pp_in_toffset(i_alu_io_pp_in_toffset), + .io_pp_in_valid(i_alu_io_pp_in_valid), + .io_pp_in_br_error(i_alu_io_pp_in_br_error), + .io_pp_in_br_start_error(i_alu_io_pp_in_br_start_error), + .io_pp_in_prett(i_alu_io_pp_in_prett), + .io_pp_in_pcall(i_alu_io_pp_in_pcall), + .io_pp_in_pret(i_alu_io_pp_in_pret), + .io_pp_in_pja(i_alu_io_pp_in_pja), + .io_pp_in_way(i_alu_io_pp_in_way), + .io_brimm_in(i_alu_io_brimm_in), + .io_result_ff(i_alu_io_result_ff), + .io_flush_upper_out(i_alu_io_flush_upper_out), + .io_flush_final_out(i_alu_io_flush_final_out), + .io_flush_path_out(i_alu_io_flush_path_out), + .io_pc_ff(i_alu_io_pc_ff), + .io_pred_correct_out(i_alu_io_pred_correct_out), + .io_predict_p_out_misp(i_alu_io_predict_p_out_misp), + .io_predict_p_out_ataken(i_alu_io_predict_p_out_ataken), + .io_predict_p_out_boffset(i_alu_io_predict_p_out_boffset), + .io_predict_p_out_pc4(i_alu_io_predict_p_out_pc4), + .io_predict_p_out_hist(i_alu_io_predict_p_out_hist), + .io_predict_p_out_toffset(i_alu_io_predict_p_out_toffset), + .io_predict_p_out_valid(i_alu_io_predict_p_out_valid), + .io_predict_p_out_br_error(i_alu_io_predict_p_out_br_error), + .io_predict_p_out_br_start_error(i_alu_io_predict_p_out_br_start_error), + .io_predict_p_out_pcall(i_alu_io_predict_p_out_pcall), + .io_predict_p_out_pret(i_alu_io_predict_p_out_pret), + .io_predict_p_out_pja(i_alu_io_predict_p_out_pja), + .io_predict_p_out_way(i_alu_io_predict_p_out_way) + ); + el2_exu_mul_ctl i_mul ( // @[el2_exu.scala 146:19] + .clock(i_mul_clock), + .reset(i_mul_reset), + .io_scan_mode(i_mul_io_scan_mode), + .io_mul_p_valid(i_mul_io_mul_p_valid), + .io_mul_p_rs1_sign(i_mul_io_mul_p_rs1_sign), + .io_mul_p_rs2_sign(i_mul_io_mul_p_rs2_sign), + .io_mul_p_low(i_mul_io_mul_p_low), + .io_rs1_in(i_mul_io_rs1_in), + .io_rs2_in(i_mul_io_rs2_in), + .io_result_x(i_mul_io_result_x) + ); + el2_exu_div_ctl i_div ( // @[el2_exu.scala 153:19] + .clock(i_div_clock), + .reset(i_div_reset), + .io_scan_mode(i_div_io_scan_mode), + .io_dp_valid(i_div_io_dp_valid), + .io_dp_unsign(i_div_io_dp_unsign), + .io_dp_rem(i_div_io_dp_rem), + .io_dividend(i_div_io_dividend), + .io_divisor(i_div_io_divisor), + .io_cancel(i_div_io_cancel), + .io_out(i_div_io_out), + .io_finish_dly(i_div_io_finish_dly) + ); + assign io_exu_lsu_rs1_d = _T_106 | _T_105; // @[el2_exu.scala 100:19] + assign io_exu_lsu_rs2_d = _T_117 | _T_118; // @[el2_exu.scala 106:19] + assign io_exu_flush_final = i_alu_io_flush_final_out; // @[el2_exu.scala 140:33] + assign io_exu_flush_path_final = io_dec_tlu_flush_lower_r ? io_dec_tlu_flush_path_r : i0_flush_path_d; // @[el2_exu.scala 215:50] + assign io_exu_i0_result_x = mul_valid_x ? i_mul_io_result_x : i_alu_io_result_ff; // @[el2_exu.scala 162:42] + assign io_exu_i0_pc_x = i_alu_io_pc_ff; // @[el2_exu.scala 144:41] + assign io_exu_csr_rs1_x = _T_3; // @[el2_exu.scala 45:41] + assign io_exu_npc_r = _T_188[30:0]; // @[el2_exu.scala 216:50] + assign io_exu_i0_br_hist_r = i0_pp_r_hist; // @[el2_exu.scala 189:50] + assign io_exu_i0_br_error_r = i0_pp_r_br_error; // @[el2_exu.scala 190:42] + assign io_exu_i0_br_start_error_r = i0_pp_r_br_start_error; // @[el2_exu.scala 192:36] + assign io_exu_i0_br_index_r = predpipe_r[12:5]; // @[el2_exu.scala 194:42] + assign io_exu_i0_br_valid_r = i0_pp_r_valid; // @[el2_exu.scala 186:36] + assign io_exu_i0_br_mp_r = i0_pp_r_misp; // @[el2_exu.scala 187:36] + assign io_exu_i0_br_middle_r = i0_pp_r_pc4 ^ i0_pp_r_boffset; // @[el2_exu.scala 191:36] + assign io_exu_i0_br_fghr_r = predpipe_r[20:13]; // @[el2_exu.scala 193:50] + assign io_exu_i0_br_way_r = i0_pp_r_way; // @[el2_exu.scala 188:36] + assign io_exu_mp_pkt_misp = i0_flush_upper_x & i0_predict_p_x_misp; // @[el2_exu.scala 202:36] + assign io_exu_mp_pkt_ataken = i0_flush_upper_x & i0_predict_p_x_ataken; // @[el2_exu.scala 206:36] + assign io_exu_mp_pkt_boffset = i0_flush_upper_x & i0_predict_p_x_boffset; // @[el2_exu.scala 207:36] + assign io_exu_mp_pkt_pc4 = i0_flush_upper_x & i0_predict_p_x_pc4; // @[el2_exu.scala 208:36] + assign io_exu_mp_pkt_hist = i0_flush_upper_x ? i0_predict_p_x_hist : 2'h0; // @[el2_exu.scala 209:50] + assign io_exu_mp_pkt_toffset = i0_flush_upper_x ? i0_predict_p_x_toffset : 12'h0; // @[el2_exu.scala 210:42] + assign io_exu_mp_pkt_valid = 1'h0; // @[el2_exu.scala 34:41] + assign io_exu_mp_pkt_br_error = 1'h0; // @[el2_exu.scala 33:41] + assign io_exu_mp_pkt_br_start_error = 1'h0; // @[el2_exu.scala 32:31] + assign io_exu_mp_pkt_prett = 31'h0; // @[el2_exu.scala 31:41] + assign io_exu_mp_pkt_pcall = i0_flush_upper_x & i0_predict_p_x_pcall; // @[el2_exu.scala 203:36] + assign io_exu_mp_pkt_pret = i0_flush_upper_x & i0_predict_p_x_pret; // @[el2_exu.scala 205:36] + assign io_exu_mp_pkt_pja = i0_flush_upper_x & i0_predict_p_x_pja; // @[el2_exu.scala 204:36] + assign io_exu_mp_pkt_way = i0_flush_upper_x & i0_predict_p_x_way; // @[el2_exu.scala 201:36] + assign io_exu_mp_eghr = final_predpipe_mp[20:13]; // @[el2_exu.scala 214:36] + assign io_exu_mp_fghr = _T_179 ? ghr_d : ghr_x; // @[el2_exu.scala 211:36] + assign io_exu_mp_index = final_predpipe_mp[12:5]; // @[el2_exu.scala 212:58] + assign io_exu_mp_btag = final_predpipe_mp[4:0]; // @[el2_exu.scala 213:58] + assign io_exu_pmu_i0_br_misp = i0_pp_r_misp; // @[el2_exu.scala 166:31] + assign io_exu_pmu_i0_br_ataken = i0_pp_r_ataken; // @[el2_exu.scala 167:31] + assign io_exu_pmu_i0_pc4 = i0_pp_r_pc4; // @[el2_exu.scala 168:31] + assign io_exu_div_result = i_div_io_out; // @[el2_exu.scala 160:33] + assign io_exu_div_wren = i_div_io_finish_dly; // @[el2_exu.scala 159:41] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_2_io_en = io_dec_data_en[1]; // @[el2_lib.scala 521:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = io_dec_data_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = io_dec_ctl_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 520:18] + assign rvclkhdr_10_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 521:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 522:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_12_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_12_io_en = io_dec_ctl_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_12_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_13_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_13_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_13_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_14_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_14_io_en = io_dec_data_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_14_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_15_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_15_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_15_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_16_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_16_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_16_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_17_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_17_io_en = _T_41 | _T_42; // @[el2_lib.scala 511:17] + assign rvclkhdr_17_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign i_alu_clock = clock; + assign i_alu_reset = reset; + assign i_alu_io_scan_mode = io_scan_mode; // @[el2_exu.scala 126:33] + assign i_alu_io_flush_upper_x = i0_flush_upper_x; // @[el2_exu.scala 130:33] + assign i_alu_io_flush_lower_r = io_dec_tlu_flush_lower_r; // @[el2_exu.scala 131:33] + assign i_alu_io_enable = io_dec_ctl_en[1]; // @[el2_exu.scala 127:41] + assign i_alu_io_valid_in = io_dec_i0_alu_decode_d; // @[el2_exu.scala 129:33] + assign i_alu_io_ap_land = io_i0_ap_land; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_lor = io_i0_ap_lor; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_lxor = io_i0_ap_lxor; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_sll = io_i0_ap_sll; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_srl = io_i0_ap_srl; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_sra = io_i0_ap_sra; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_beq = io_i0_ap_beq; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_bne = io_i0_ap_bne; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_blt = io_i0_ap_blt; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_bge = io_i0_ap_bge; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_add = io_i0_ap_add; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_sub = io_i0_ap_sub; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_slt = io_i0_ap_slt; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_unsign = io_i0_ap_unsign; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_jal = io_i0_ap_jal; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_predict_t = io_i0_ap_predict_t; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_predict_nt = io_i0_ap_predict_nt; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_csr_write = io_i0_ap_csr_write; // @[el2_exu.scala 136:41] + assign i_alu_io_ap_csr_imm = io_i0_ap_csr_imm; // @[el2_exu.scala 136:41] + assign i_alu_io_csr_ren_in = io_dec_csr_ren_d; // @[el2_exu.scala 137:33] + assign i_alu_io_a_in = _T_80 | _T_78; // @[el2_exu.scala 132:33] + assign i_alu_io_b_in = i0_rs2_d; // @[el2_exu.scala 133:33] + assign i_alu_io_pc_in = io_dec_i0_pc_d; // @[el2_exu.scala 134:41] + assign i_alu_io_pp_in_boffset = io_dec_i0_pc_d[0]; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_pc4 = io_dec_i0_predict_p_d_pc4; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_hist = io_dec_i0_predict_p_d_hist; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_toffset = io_dec_i0_predict_p_d_toffset; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_valid = io_dec_i0_predict_p_d_valid; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_br_error = io_dec_i0_predict_p_d_br_error; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_br_start_error = io_dec_i0_predict_p_d_br_start_error; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_prett = io_dec_i0_predict_p_d_prett; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_pcall = io_dec_i0_predict_p_d_pcall; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_pret = io_dec_i0_predict_p_d_pret; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_pja = io_dec_i0_predict_p_d_pja; // @[el2_exu.scala 128:41] + assign i_alu_io_pp_in_way = io_dec_i0_predict_p_d_way; // @[el2_exu.scala 128:41] + assign i_alu_io_brimm_in = io_dec_i0_br_immed_d; // @[el2_exu.scala 135:33] + assign i_mul_clock = clock; + assign i_mul_reset = reset; + assign i_mul_io_scan_mode = io_scan_mode; // @[el2_exu.scala 147:33] + assign i_mul_io_mul_p_valid = io_mul_p_valid; // @[el2_exu.scala 148:41] + assign i_mul_io_mul_p_rs1_sign = io_mul_p_rs1_sign; // @[el2_exu.scala 148:41] + assign i_mul_io_mul_p_rs2_sign = io_mul_p_rs2_sign; // @[el2_exu.scala 148:41] + assign i_mul_io_mul_p_low = io_mul_p_low; // @[el2_exu.scala 148:41] + assign i_mul_io_rs1_in = _T_125 | _T_75; // @[el2_exu.scala 149:41] + assign i_mul_io_rs2_in = _T_91 | _T_90; // @[el2_exu.scala 150:41] + assign i_div_clock = clock; + assign i_div_reset = reset; + assign i_div_io_scan_mode = io_scan_mode; // @[el2_exu.scala 154:33] + assign i_div_io_dp_valid = io_div_p_valid; // @[el2_exu.scala 156:41] + assign i_div_io_dp_unsign = io_div_p_unsign; // @[el2_exu.scala 156:41] + assign i_div_io_dp_rem = io_div_p_rem; // @[el2_exu.scala 156:41] + assign i_div_io_dividend = _T_125 | _T_75; // @[el2_exu.scala 157:33] + assign i_div_io_divisor = _T_91 | _T_90; // @[el2_exu.scala 158:33] + assign i_div_io_cancel = io_dec_div_cancel; // @[el2_exu.scala 155:41] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + i0_flush_path_x = _RAND_0[30:0]; + _RAND_1 = {1{`RANDOM}}; + _T_3 = _RAND_1[31:0]; + _RAND_2 = {1{`RANDOM}}; + i0_predict_p_x_misp = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + i0_predict_p_x_ataken = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + i0_predict_p_x_boffset = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + i0_predict_p_x_pc4 = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + i0_predict_p_x_hist = _RAND_6[1:0]; + _RAND_7 = {1{`RANDOM}}; + i0_predict_p_x_toffset = _RAND_7[11:0]; + _RAND_8 = {1{`RANDOM}}; + i0_predict_p_x_valid = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + i0_predict_p_x_br_error = _RAND_9[0:0]; + _RAND_10 = {1{`RANDOM}}; + i0_predict_p_x_br_start_error = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + i0_predict_p_x_pcall = _RAND_11[0:0]; + _RAND_12 = {1{`RANDOM}}; + i0_predict_p_x_pret = _RAND_12[0:0]; + _RAND_13 = {1{`RANDOM}}; + i0_predict_p_x_pja = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + i0_predict_p_x_way = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + predpipe_x = _RAND_15[20:0]; + _RAND_16 = {1{`RANDOM}}; + predpipe_r = _RAND_16[20:0]; + _RAND_17 = {1{`RANDOM}}; + ghr_x = _RAND_17[7:0]; + _RAND_18 = {1{`RANDOM}}; + i0_pred_correct_upper_x = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + i0_flush_upper_x = _RAND_19[0:0]; + _RAND_20 = {1{`RANDOM}}; + i0_taken_x = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + i0_valid_x = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + i0_pp_r_misp = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + i0_pp_r_ataken = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + i0_pp_r_boffset = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + i0_pp_r_pc4 = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + i0_pp_r_hist = _RAND_26[1:0]; + _RAND_27 = {1{`RANDOM}}; + i0_pp_r_valid = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + i0_pp_r_br_error = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + i0_pp_r_br_start_error = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + i0_pp_r_way = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + pred_temp1 = _RAND_31[5:0]; + _RAND_32 = {1{`RANDOM}}; + i0_pred_correct_upper_r = _RAND_32[0:0]; + _RAND_33 = {1{`RANDOM}}; + i0_flush_path_upper_r = _RAND_33[30:0]; + _RAND_34 = {1{`RANDOM}}; + pred_temp2 = _RAND_34[24:0]; + _RAND_35 = {1{`RANDOM}}; + ghr_d = _RAND_35[7:0]; + _RAND_36 = {1{`RANDOM}}; + mul_valid_x = _RAND_36[0:0]; + _RAND_37 = {1{`RANDOM}}; + flush_lower_ff = _RAND_37[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + i0_flush_path_x = 31'h0; + end + if (reset) begin + _T_3 = 32'h0; + end + if (reset) begin + i0_predict_p_x_misp = 1'h0; + end + if (reset) begin + i0_predict_p_x_ataken = 1'h0; + end + if (reset) begin + i0_predict_p_x_boffset = 1'h0; + end + if (reset) begin + i0_predict_p_x_pc4 = 1'h0; + end + if (reset) begin + i0_predict_p_x_hist = 2'h0; + end + if (reset) begin + i0_predict_p_x_toffset = 12'h0; + end + if (reset) begin + i0_predict_p_x_valid = 1'h0; + end + if (reset) begin + i0_predict_p_x_br_error = 1'h0; + end + if (reset) begin + i0_predict_p_x_br_start_error = 1'h0; + end + if (reset) begin + i0_predict_p_x_pcall = 1'h0; + end + if (reset) begin + i0_predict_p_x_pret = 1'h0; + end + if (reset) begin + i0_predict_p_x_pja = 1'h0; + end + if (reset) begin + i0_predict_p_x_way = 1'h0; + end + if (reset) begin + predpipe_x = 21'h0; + end + if (reset) begin + predpipe_r = 21'h0; + end + if (reset) begin + ghr_x = 8'h0; + end + if (reset) begin + i0_pred_correct_upper_x = 1'h0; + end + if (reset) begin + i0_flush_upper_x = 1'h0; + end + if (reset) begin + i0_taken_x = 1'h0; + end + if (reset) begin + i0_valid_x = 1'h0; + end + if (reset) begin + i0_pp_r_misp = 1'h0; + end + if (reset) begin + i0_pp_r_ataken = 1'h0; + end + if (reset) begin + i0_pp_r_boffset = 1'h0; + end + if (reset) begin + i0_pp_r_pc4 = 1'h0; + end + if (reset) begin + i0_pp_r_hist = 2'h0; + end + if (reset) begin + i0_pp_r_valid = 1'h0; + end + if (reset) begin + i0_pp_r_br_error = 1'h0; + end + if (reset) begin + i0_pp_r_br_start_error = 1'h0; + end + if (reset) begin + i0_pp_r_way = 1'h0; + end + if (reset) begin + pred_temp1 = 6'h0; + end + if (reset) begin + i0_pred_correct_upper_r = 1'h0; + end + if (reset) begin + i0_flush_path_upper_r = 31'h0; + end + if (reset) begin + pred_temp2 = 25'h0; + end + if (reset) begin + ghr_d = 8'h0; + end + if (reset) begin + mul_valid_x = 1'h0; + end + if (reset) begin + flush_lower_ff = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_path_x <= 31'h0; + end else begin + i0_flush_path_x <= i_alu_io_flush_path_out; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_3 <= 32'h0; + end else if (io_dec_csr_ren_d) begin + _T_3 <= i0_rs1_d; + end else begin + _T_3 <= io_exu_csr_rs1_x; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_misp <= 1'h0; + end else begin + i0_predict_p_x_misp <= i_alu_io_predict_p_out_misp; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_ataken <= 1'h0; + end else begin + i0_predict_p_x_ataken <= i_alu_io_predict_p_out_ataken; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_boffset <= 1'h0; + end else begin + i0_predict_p_x_boffset <= i_alu_io_predict_p_out_boffset; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pc4 <= 1'h0; + end else begin + i0_predict_p_x_pc4 <= i_alu_io_predict_p_out_pc4; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_hist <= 2'h0; + end else begin + i0_predict_p_x_hist <= i_alu_io_predict_p_out_hist; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_toffset <= 12'h0; + end else begin + i0_predict_p_x_toffset <= i_alu_io_predict_p_out_toffset; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_valid <= 1'h0; + end else begin + i0_predict_p_x_valid <= i_alu_io_predict_p_out_valid; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_br_error <= 1'h0; + end else begin + i0_predict_p_x_br_error <= i_alu_io_predict_p_out_br_error; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_br_start_error <= 1'h0; + end else begin + i0_predict_p_x_br_start_error <= i_alu_io_predict_p_out_br_start_error; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pcall <= 1'h0; + end else begin + i0_predict_p_x_pcall <= i_alu_io_predict_p_out_pcall; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pret <= 1'h0; + end else begin + i0_predict_p_x_pret <= i_alu_io_predict_p_out_pret; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_pja <= 1'h0; + end else begin + i0_predict_p_x_pja <= i_alu_io_predict_p_out_pja; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + i0_predict_p_x_way <= 1'h0; + end else begin + i0_predict_p_x_way <= i_alu_io_predict_p_out_way; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + predpipe_x <= 21'h0; + end else begin + predpipe_x <= {_T,io_i0_predict_btag_d}; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + predpipe_r <= 21'h0; + end else begin + predpipe_r <= predpipe_x; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + ghr_x <= 8'h0; + end else if (i0_valid_x) begin + ghr_x <= _T_167; + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + i0_pred_correct_upper_x <= 1'h0; + end else begin + i0_pred_correct_upper_x <= i_alu_io_pred_correct_out; + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_upper_x <= 1'h0; + end else begin + i0_flush_upper_x <= i_alu_io_flush_upper_out; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + i0_taken_x <= 1'h0; + end else begin + i0_taken_x <= i0_predict_p_d_ataken & io_dec_i0_alu_decode_d; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + i0_valid_x <= 1'h0; + end else begin + i0_valid_x <= _T_145 & _T_149; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_misp <= 1'h0; + end else begin + i0_pp_r_misp <= i0_predict_p_x_misp; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_ataken <= 1'h0; + end else begin + i0_pp_r_ataken <= i0_predict_p_x_ataken; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_boffset <= 1'h0; + end else begin + i0_pp_r_boffset <= i0_predict_p_x_boffset; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_pc4 <= 1'h0; + end else begin + i0_pp_r_pc4 <= i0_predict_p_x_pc4; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_hist <= 2'h0; + end else begin + i0_pp_r_hist <= i0_predict_p_x_hist; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_valid <= 1'h0; + end else begin + i0_pp_r_valid <= i0_predict_p_x_valid; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_br_error <= 1'h0; + end else begin + i0_pp_r_br_error <= i0_predict_p_x_br_error; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_br_start_error <= 1'h0; + end else begin + i0_pp_r_br_start_error <= i0_predict_p_x_br_start_error; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + i0_pp_r_way <= 1'h0; + end else begin + i0_pp_r_way <= i0_predict_p_x_way; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + pred_temp1 <= 6'h0; + end else begin + pred_temp1 <= io_pred_correct_npc_x[5:0]; + end + end + always @(posedge rvclkhdr_12_io_l1clk or posedge reset) begin + if (reset) begin + i0_pred_correct_upper_r <= 1'h0; + end else begin + i0_pred_correct_upper_r <= i0_pred_correct_upper_x; + end + end + always @(posedge rvclkhdr_13_io_l1clk or posedge reset) begin + if (reset) begin + i0_flush_path_upper_r <= 31'h0; + end else begin + i0_flush_path_upper_r <= i0_flush_path_x; + end + end + always @(posedge rvclkhdr_14_io_l1clk or posedge reset) begin + if (reset) begin + pred_temp2 <= 25'h0; + end else begin + pred_temp2 <= io_pred_correct_npc_x[30:6]; + end + end + always @(posedge rvclkhdr_15_io_l1clk or posedge reset) begin + if (reset) begin + ghr_d <= 8'h0; + end else begin + ghr_d <= _T_162 | _T_161; + end + end + always @(posedge rvclkhdr_16_io_l1clk or posedge reset) begin + if (reset) begin + mul_valid_x <= 1'h0; + end else begin + mul_valid_x <= io_mul_p_valid; + end + end + always @(posedge rvclkhdr_17_io_l1clk or posedge reset) begin + if (reset) begin + flush_lower_ff <= 1'h0; + end else begin + flush_lower_ff <= io_dec_tlu_flush_lower_r; + end + end +endmodule diff --git a/el2_exu_alu_ctl.anno.json b/el2_exu_alu_ctl.anno.json index 0256f869..e88ea961 100644 --- a/el2_exu_alu_ctl.anno.json +++ b/el2_exu_alu_ctl.anno.json @@ -40,8 +40,8 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" ] }, @@ -82,19 +82,19 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" ] }, { @@ -118,8 +118,8 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" ] }, @@ -139,19 +139,19 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_flush_upper_x", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pret", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_t", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_predict_nt", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_prett", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bge", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pja", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" ] }, { @@ -165,8 +165,8 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pc_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_brimm_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in" ] }, { @@ -184,12 +184,12 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_blt", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_jal", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_pp_in_pcall", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in" ] }, { @@ -208,8 +208,8 @@ "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_beq", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_bne", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_a_in", - "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_unsign", + "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_b_in", "~el2_exu_alu_ctl|el2_exu_alu_ctl>io_ap_sub" ] }, @@ -224,6 +224,11 @@ "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_exu_alu_ctl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." diff --git a/el2_exu_alu_ctl.fir b/el2_exu_alu_ctl.fir index 894b6988..a8adeb2d 100644 --- a/el2_exu_alu_ctl.fir +++ b/el2_exu_alu_ctl.fir @@ -1,474 +1,568 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_exu_alu_ctl : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + module el2_exu_alu_ctl : input clock : Clock - input reset : UInt<1> - output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : UInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<32>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip flush_upper_x : UInt<1>, flip flush_lower_r : UInt<1>, flip enable : UInt<1>, flip valid_in : UInt<1>, flip ap : {land : UInt<1>, lor : UInt<1>, lxor : UInt<1>, sll : UInt<1>, srl : UInt<1>, sra : UInt<1>, beq : UInt<1>, bne : UInt<1>, blt : UInt<1>, bge : UInt<1>, add : UInt<1>, sub : UInt<1>, slt : UInt<1>, unsign : UInt<1>, jal : UInt<1>, predict_t : UInt<1>, predict_nt : UInt<1>, csr_write : UInt<1>, csr_imm : UInt<1>}, flip csr_ren_in : UInt<1>, flip a_in : SInt<32>, flip b_in : UInt<32>, flip pc_in : UInt<31>, flip pp_in : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}, flip brimm_in : UInt<12>, result_ff : UInt<32>, flush_upper_out : UInt<1>, flush_final_out : UInt<1>, flush_path_out : UInt<31>, pc_ff : UInt<31>, pred_correct_out : UInt<1>, predict_p_out : {misp : UInt<1>, ataken : UInt<1>, boffset : UInt<1>, pc4 : UInt<1>, hist : UInt<2>, toffset : UInt<12>, valid : UInt<1>, br_error : UInt<1>, br_start_error : UInt<1>, prett : UInt<31>, pcall : UInt<1>, pret : UInt<1>, pja : UInt<1>, way : UInt<1>}} - reg _T : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.enable : @[Reg.scala 28:19] - _T <= io.pc_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - io.pc_ff <= _T @[el2_exu_alu_ctl.scala 35:12] + node _T = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 35:60] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= _T @[el2_lib.scala 512:24] + reg _T_1 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1 <= io.pc_in @[el2_lib.scala 514:16] + io.pc_ff <= _T_1 @[el2_exu_alu_ctl.scala 35:12] wire result : UInt<32> result <= UInt<1>("h00") - reg _T_1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.enable : @[Reg.scala 28:19] - _T_1 <= result @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - io.result_ff <= _T_1 @[el2_exu_alu_ctl.scala 37:16] - node _T_2 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29] - node _T_3 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37] - node bm = mux(_T_2, _T_3, io.b_in) @[el2_exu_alu_ctl.scala 39:17] + node _T_2 = bits(io.scan_mode, 0, 0) @[el2_exu_alu_ctl.scala 37:62] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= io.enable @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= _T_2 @[el2_lib.scala 512:24] + reg _T_3 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_3 <= result @[el2_lib.scala 514:16] + io.result_ff <= _T_3 @[el2_exu_alu_ctl.scala 37:16] + node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 39:29] + node _T_5 = not(io.b_in) @[el2_exu_alu_ctl.scala 39:37] + node bm = mux(_T_4, _T_5, io.b_in) @[el2_exu_alu_ctl.scala 39:17] wire aout : UInt<33> aout <= UInt<1>("h00") - node _T_4 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 43:15] - node _T_5 = cat(UInt<1>("h00"), io.a_in) @[Cat.scala 29:58] - node _T_6 = not(io.b_in) @[el2_exu_alu_ctl.scala 43:63] - node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58] - node _T_8 = add(_T_5, _T_7) @[el2_exu_alu_ctl.scala 43:48] - node _T_9 = tail(_T_8, 1) @[el2_exu_alu_ctl.scala 43:48] - node _T_10 = add(_T_9, UInt<1>("h01")) @[el2_exu_alu_ctl.scala 43:73] - node _T_11 = tail(_T_10, 1) @[el2_exu_alu_ctl.scala 43:73] - node _T_12 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 44:16] - node _T_13 = eq(_T_12, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 44:5] - node _T_14 = cat(UInt<1>("h00"), io.a_in) @[Cat.scala 29:58] - node _T_15 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58] - node _T_16 = add(_T_14, _T_15) @[el2_exu_alu_ctl.scala 44:48] - node _T_17 = tail(_T_16, 1) @[el2_exu_alu_ctl.scala 44:48] - node _T_18 = mux(_T_4, _T_11, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_19 = mux(_T_13, _T_17, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_20 = or(_T_18, _T_19) @[Mux.scala 27:72] - wire _T_21 : UInt<33> @[Mux.scala 27:72] - _T_21 <= _T_20 @[Mux.scala 27:72] - aout <= _T_21 @[el2_exu_alu_ctl.scala 42:8] - node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 46:18] - node _T_22 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 48:22] - node _T_23 = not(_T_22) @[el2_exu_alu_ctl.scala 48:14] - node _T_24 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 48:32] - node _T_25 = not(_T_24) @[el2_exu_alu_ctl.scala 48:29] - node _T_26 = and(_T_23, _T_25) @[el2_exu_alu_ctl.scala 48:27] - node _T_27 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 48:44] - node _T_28 = and(_T_26, _T_27) @[el2_exu_alu_ctl.scala 48:37] - node _T_29 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 48:61] - node _T_30 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 48:71] - node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 48:66] - node _T_32 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 48:83] - node _T_33 = not(_T_32) @[el2_exu_alu_ctl.scala 48:78] - node _T_34 = and(_T_31, _T_33) @[el2_exu_alu_ctl.scala 48:76] - node ov = or(_T_28, _T_34) @[el2_exu_alu_ctl.scala 48:50] - node eq = eq(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 50:38] - node ne = not(eq) @[el2_exu_alu_ctl.scala 51:29] - node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 52:34] - node _T_35 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 53:30] - node _T_36 = xor(neg, ov) @[el2_exu_alu_ctl.scala 53:51] - node _T_37 = and(_T_35, _T_36) @[el2_exu_alu_ctl.scala 53:44] - node _T_38 = not(cout) @[el2_exu_alu_ctl.scala 53:78] - node _T_39 = and(io.ap.unsign, _T_38) @[el2_exu_alu_ctl.scala 53:76] - node lt = or(_T_37, _T_39) @[el2_exu_alu_ctl.scala 53:58] - node ge = not(lt) @[el2_exu_alu_ctl.scala 54:29] - node _T_40 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 58:19] - node _T_41 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 59:16] - node _T_42 = and(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 59:39] - node _T_43 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 60:15] - node _T_44 = or(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 60:39] - node _T_45 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 61:16] - node _T_46 = xor(io.a_in, io.b_in) @[el2_exu_alu_ctl.scala 61:39] - node _T_47 = mux(_T_40, io.b_in, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_48 = mux(_T_41, _T_42, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_49 = mux(_T_43, _T_44, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_50 = mux(_T_45, _T_46, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_51 = or(_T_47, _T_48) @[Mux.scala 27:72] - node _T_52 = or(_T_51, _T_49) @[Mux.scala 27:72] - node _T_53 = or(_T_52, _T_50) @[Mux.scala 27:72] - wire lout : UInt<32> @[Mux.scala 27:72] - lout <= _T_53 @[Mux.scala 27:72] - node _T_54 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 64:15] - node _T_55 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 64:60] - node _T_56 = cat(UInt<1>("h00"), _T_55) @[Cat.scala 29:58] - node _T_57 = sub(UInt<6>("h020"), _T_56) @[el2_exu_alu_ctl.scala 64:38] - node _T_58 = tail(_T_57, 1) @[el2_exu_alu_ctl.scala 64:38] - node _T_59 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 65:15] - node _T_60 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 65:60] - node _T_61 = cat(UInt<1>("h00"), _T_60) @[Cat.scala 29:58] - node _T_62 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 66:15] - node _T_63 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:60] - node _T_64 = cat(UInt<1>("h00"), _T_63) @[Cat.scala 29:58] - node _T_65 = mux(_T_54, _T_58, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_66 = mux(_T_59, _T_61, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_67 = mux(_T_62, _T_64, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_68 = or(_T_65, _T_66) @[Mux.scala 27:72] - node _T_69 = or(_T_68, _T_67) @[Mux.scala 27:72] + node _T_6 = bits(io.ap.sub, 0, 0) @[el2_exu_alu_ctl.scala 42:25] + node _T_7 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] + node _T_9 = not(io.b_in) @[el2_exu_alu_ctl.scala 42:70] + node _T_10 = cat(UInt<1>("h00"), _T_9) @[Cat.scala 29:58] + node _T_11 = add(_T_8, _T_10) @[el2_exu_alu_ctl.scala 42:55] + node _T_12 = tail(_T_11, 1) @[el2_exu_alu_ctl.scala 42:55] + node _T_13 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_14 = add(_T_12, _T_13) @[el2_exu_alu_ctl.scala 42:80] + node _T_15 = tail(_T_14, 1) @[el2_exu_alu_ctl.scala 42:80] + node _T_16 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_17 = cat(UInt<1>("h00"), _T_16) @[Cat.scala 29:58] + node _T_18 = cat(UInt<1>("h00"), io.b_in) @[Cat.scala 29:58] + node _T_19 = add(_T_17, _T_18) @[el2_exu_alu_ctl.scala 42:132] + node _T_20 = tail(_T_19, 1) @[el2_exu_alu_ctl.scala 42:132] + node _T_21 = cat(UInt<32>("h00"), io.ap.sub) @[Cat.scala 29:58] + node _T_22 = add(_T_20, _T_21) @[el2_exu_alu_ctl.scala 42:157] + node _T_23 = tail(_T_22, 1) @[el2_exu_alu_ctl.scala 42:157] + node _T_24 = mux(_T_6, _T_15, _T_23) @[el2_exu_alu_ctl.scala 42:14] + aout <= _T_24 @[el2_exu_alu_ctl.scala 42:8] + node cout = bits(aout, 32, 32) @[el2_exu_alu_ctl.scala 43:18] + node _T_25 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:22] + node _T_26 = not(_T_25) @[el2_exu_alu_ctl.scala 45:14] + node _T_27 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:32] + node _T_28 = not(_T_27) @[el2_exu_alu_ctl.scala 45:29] + node _T_29 = and(_T_26, _T_28) @[el2_exu_alu_ctl.scala 45:27] + node _T_30 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:44] + node _T_31 = and(_T_29, _T_30) @[el2_exu_alu_ctl.scala 45:37] + node _T_32 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 45:61] + node _T_33 = bits(bm, 31, 31) @[el2_exu_alu_ctl.scala 45:71] + node _T_34 = and(_T_32, _T_33) @[el2_exu_alu_ctl.scala 45:66] + node _T_35 = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 45:83] + node _T_36 = not(_T_35) @[el2_exu_alu_ctl.scala 45:78] + node _T_37 = and(_T_34, _T_36) @[el2_exu_alu_ctl.scala 45:76] + node ov = or(_T_31, _T_37) @[el2_exu_alu_ctl.scala 45:50] + node _T_38 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 47:50] + node eq = eq(io.a_in, _T_38) @[el2_exu_alu_ctl.scala 47:38] + node ne = not(eq) @[el2_exu_alu_ctl.scala 48:29] + node neg = bits(aout, 31, 31) @[el2_exu_alu_ctl.scala 49:34] + node _T_39 = not(io.ap.unsign) @[el2_exu_alu_ctl.scala 50:30] + node _T_40 = xor(neg, ov) @[el2_exu_alu_ctl.scala 50:51] + node _T_41 = and(_T_39, _T_40) @[el2_exu_alu_ctl.scala 50:44] + node _T_42 = not(cout) @[el2_exu_alu_ctl.scala 50:78] + node _T_43 = and(io.ap.unsign, _T_42) @[el2_exu_alu_ctl.scala 50:76] + node lt = or(_T_41, _T_43) @[el2_exu_alu_ctl.scala 50:58] + node ge = not(lt) @[el2_exu_alu_ctl.scala 51:29] + node _T_44 = bits(io.csr_ren_in, 0, 0) @[el2_exu_alu_ctl.scala 55:19] + node _T_45 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 55:50] + node _T_46 = bits(io.ap.land, 0, 0) @[el2_exu_alu_ctl.scala 56:16] + node _T_47 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 56:50] + node _T_48 = and(io.a_in, _T_47) @[el2_exu_alu_ctl.scala 56:39] + node _T_49 = asSInt(_T_48) @[el2_exu_alu_ctl.scala 56:39] + node _T_50 = bits(io.ap.lor, 0, 0) @[el2_exu_alu_ctl.scala 57:15] + node _T_51 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 57:50] + node _T_52 = or(io.a_in, _T_51) @[el2_exu_alu_ctl.scala 57:39] + node _T_53 = asSInt(_T_52) @[el2_exu_alu_ctl.scala 57:39] + node _T_54 = bits(io.ap.lxor, 0, 0) @[el2_exu_alu_ctl.scala 58:16] + node _T_55 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 58:50] + node _T_56 = xor(io.a_in, _T_55) @[el2_exu_alu_ctl.scala 58:39] + node _T_57 = asSInt(_T_56) @[el2_exu_alu_ctl.scala 58:39] + wire _T_58 : SInt<32> @[Mux.scala 27:72] + node _T_59 = asUInt(_T_45) @[Mux.scala 27:72] + node _T_60 = asSInt(_T_59) @[Mux.scala 27:72] + _T_58 <= _T_60 @[Mux.scala 27:72] + wire _T_61 : SInt<32> @[Mux.scala 27:72] + node _T_62 = asUInt(_T_49) @[Mux.scala 27:72] + node _T_63 = asSInt(_T_62) @[Mux.scala 27:72] + _T_61 <= _T_63 @[Mux.scala 27:72] + wire _T_64 : SInt<32> @[Mux.scala 27:72] + node _T_65 = asUInt(_T_53) @[Mux.scala 27:72] + node _T_66 = asSInt(_T_65) @[Mux.scala 27:72] + _T_64 <= _T_66 @[Mux.scala 27:72] + wire _T_67 : SInt<32> @[Mux.scala 27:72] + node _T_68 = asUInt(_T_57) @[Mux.scala 27:72] + node _T_69 = asSInt(_T_68) @[Mux.scala 27:72] + _T_67 <= _T_69 @[Mux.scala 27:72] + node _T_70 = mux(_T_44, _T_58, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_71 = mux(_T_46, _T_61, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_72 = mux(_T_50, _T_64, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_73 = mux(_T_54, _T_67, asSInt(UInt<1>("h00"))) @[Mux.scala 27:72] + node _T_74 = or(_T_70, _T_71) @[Mux.scala 27:72] + node _T_75 = asSInt(_T_74) @[Mux.scala 27:72] + node _T_76 = or(_T_75, _T_72) @[Mux.scala 27:72] + node _T_77 = asSInt(_T_76) @[Mux.scala 27:72] + node _T_78 = or(_T_77, _T_73) @[Mux.scala 27:72] + node _T_79 = asSInt(_T_78) @[Mux.scala 27:72] + wire lout : SInt<32> @[Mux.scala 27:72] + node _T_80 = asUInt(_T_79) @[Mux.scala 27:72] + node _T_81 = asSInt(_T_80) @[Mux.scala 27:72] + lout <= _T_81 @[Mux.scala 27:72] + node _T_82 = bits(io.ap.sll, 0, 0) @[el2_exu_alu_ctl.scala 61:15] + node _T_83 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 61:60] + node _T_84 = cat(UInt<1>("h00"), _T_83) @[Cat.scala 29:58] + node _T_85 = sub(UInt<6>("h020"), _T_84) @[el2_exu_alu_ctl.scala 61:38] + node _T_86 = tail(_T_85, 1) @[el2_exu_alu_ctl.scala 61:38] + node _T_87 = bits(io.ap.srl, 0, 0) @[el2_exu_alu_ctl.scala 62:15] + node _T_88 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 62:60] + node _T_89 = cat(UInt<1>("h00"), _T_88) @[Cat.scala 29:58] + node _T_90 = bits(io.ap.sra, 0, 0) @[el2_exu_alu_ctl.scala 63:15] + node _T_91 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 63:60] + node _T_92 = cat(UInt<1>("h00"), _T_91) @[Cat.scala 29:58] + node _T_93 = mux(_T_82, _T_86, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_94 = mux(_T_87, _T_89, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_95 = mux(_T_90, _T_92, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_96 = or(_T_93, _T_94) @[Mux.scala 27:72] + node _T_97 = or(_T_96, _T_95) @[Mux.scala 27:72] wire shift_amount : UInt<6> @[Mux.scala 27:72] - shift_amount <= _T_69 @[Mux.scala 27:72] + shift_amount <= _T_97 @[Mux.scala 27:72] wire shift_mask : UInt<32> shift_mask <= UInt<1>("h00") - wire _T_70 : UInt<1>[5] @[el2_lib.scala 178:24] - _T_70[0] <= io.ap.sll @[el2_lib.scala 178:24] - _T_70[1] <= io.ap.sll @[el2_lib.scala 178:24] - _T_70[2] <= io.ap.sll @[el2_lib.scala 178:24] - _T_70[3] <= io.ap.sll @[el2_lib.scala 178:24] - _T_70[4] <= io.ap.sll @[el2_lib.scala 178:24] - node _T_71 = cat(_T_70[0], _T_70[1]) @[Cat.scala 29:58] - node _T_72 = cat(_T_71, _T_70[2]) @[Cat.scala 29:58] - node _T_73 = cat(_T_72, _T_70[3]) @[Cat.scala 29:58] - node _T_74 = cat(_T_73, _T_70[4]) @[Cat.scala 29:58] - node _T_75 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 69:64] - node _T_76 = and(_T_74, _T_75) @[el2_exu_alu_ctl.scala 69:55] - node _T_77 = dshl(UInt<32>("h0ffffffff"), _T_76) @[el2_exu_alu_ctl.scala 69:33] - shift_mask <= _T_77 @[el2_exu_alu_ctl.scala 69:14] + wire _T_98 : UInt<1>[5] @[el2_lib.scala 161:48] + _T_98[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_98[4] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_99 = cat(_T_98[0], _T_98[1]) @[Cat.scala 29:58] + node _T_100 = cat(_T_99, _T_98[2]) @[Cat.scala 29:58] + node _T_101 = cat(_T_100, _T_98[3]) @[Cat.scala 29:58] + node _T_102 = cat(_T_101, _T_98[4]) @[Cat.scala 29:58] + node _T_103 = bits(io.b_in, 4, 0) @[el2_exu_alu_ctl.scala 66:70] + node _T_104 = and(_T_102, _T_103) @[el2_exu_alu_ctl.scala 66:61] + node _T_105 = dshl(UInt<32>("h0ffffffff"), _T_104) @[el2_exu_alu_ctl.scala 66:39] + shift_mask <= _T_105 @[el2_exu_alu_ctl.scala 66:14] wire shift_extend : UInt<63> shift_extend <= UInt<1>("h00") - wire _T_78 : UInt<1>[31] @[el2_lib.scala 178:24] - _T_78[0] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[1] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[2] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[3] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[4] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[5] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[6] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[7] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[8] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[9] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[10] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[11] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[12] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[13] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[14] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[15] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[16] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[17] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[18] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[19] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[20] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[21] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[22] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[23] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[24] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[25] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[26] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[27] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[28] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[29] <= io.ap.sra @[el2_lib.scala 178:24] - _T_78[30] <= io.ap.sra @[el2_lib.scala 178:24] - node _T_79 = cat(_T_78[0], _T_78[1]) @[Cat.scala 29:58] - node _T_80 = cat(_T_79, _T_78[2]) @[Cat.scala 29:58] - node _T_81 = cat(_T_80, _T_78[3]) @[Cat.scala 29:58] - node _T_82 = cat(_T_81, _T_78[4]) @[Cat.scala 29:58] - node _T_83 = cat(_T_82, _T_78[5]) @[Cat.scala 29:58] - node _T_84 = cat(_T_83, _T_78[6]) @[Cat.scala 29:58] - node _T_85 = cat(_T_84, _T_78[7]) @[Cat.scala 29:58] - node _T_86 = cat(_T_85, _T_78[8]) @[Cat.scala 29:58] - node _T_87 = cat(_T_86, _T_78[9]) @[Cat.scala 29:58] - node _T_88 = cat(_T_87, _T_78[10]) @[Cat.scala 29:58] - node _T_89 = cat(_T_88, _T_78[11]) @[Cat.scala 29:58] - node _T_90 = cat(_T_89, _T_78[12]) @[Cat.scala 29:58] - node _T_91 = cat(_T_90, _T_78[13]) @[Cat.scala 29:58] - node _T_92 = cat(_T_91, _T_78[14]) @[Cat.scala 29:58] - node _T_93 = cat(_T_92, _T_78[15]) @[Cat.scala 29:58] - node _T_94 = cat(_T_93, _T_78[16]) @[Cat.scala 29:58] - node _T_95 = cat(_T_94, _T_78[17]) @[Cat.scala 29:58] - node _T_96 = cat(_T_95, _T_78[18]) @[Cat.scala 29:58] - node _T_97 = cat(_T_96, _T_78[19]) @[Cat.scala 29:58] - node _T_98 = cat(_T_97, _T_78[20]) @[Cat.scala 29:58] - node _T_99 = cat(_T_98, _T_78[21]) @[Cat.scala 29:58] - node _T_100 = cat(_T_99, _T_78[22]) @[Cat.scala 29:58] - node _T_101 = cat(_T_100, _T_78[23]) @[Cat.scala 29:58] - node _T_102 = cat(_T_101, _T_78[24]) @[Cat.scala 29:58] - node _T_103 = cat(_T_102, _T_78[25]) @[Cat.scala 29:58] - node _T_104 = cat(_T_103, _T_78[26]) @[Cat.scala 29:58] - node _T_105 = cat(_T_104, _T_78[27]) @[Cat.scala 29:58] - node _T_106 = cat(_T_105, _T_78[28]) @[Cat.scala 29:58] - node _T_107 = cat(_T_106, _T_78[29]) @[Cat.scala 29:58] - node _T_108 = cat(_T_107, _T_78[30]) @[Cat.scala 29:58] - node _T_109 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 72:61] - wire _T_110 : UInt<1>[31] @[el2_lib.scala 178:24] - _T_110[0] <= _T_109 @[el2_lib.scala 178:24] - _T_110[1] <= _T_109 @[el2_lib.scala 178:24] - _T_110[2] <= _T_109 @[el2_lib.scala 178:24] - _T_110[3] <= _T_109 @[el2_lib.scala 178:24] - _T_110[4] <= _T_109 @[el2_lib.scala 178:24] - _T_110[5] <= _T_109 @[el2_lib.scala 178:24] - _T_110[6] <= _T_109 @[el2_lib.scala 178:24] - _T_110[7] <= _T_109 @[el2_lib.scala 178:24] - _T_110[8] <= _T_109 @[el2_lib.scala 178:24] - _T_110[9] <= _T_109 @[el2_lib.scala 178:24] - _T_110[10] <= _T_109 @[el2_lib.scala 178:24] - _T_110[11] <= _T_109 @[el2_lib.scala 178:24] - _T_110[12] <= _T_109 @[el2_lib.scala 178:24] - _T_110[13] <= _T_109 @[el2_lib.scala 178:24] - _T_110[14] <= _T_109 @[el2_lib.scala 178:24] - _T_110[15] <= _T_109 @[el2_lib.scala 178:24] - _T_110[16] <= _T_109 @[el2_lib.scala 178:24] - _T_110[17] <= _T_109 @[el2_lib.scala 178:24] - _T_110[18] <= _T_109 @[el2_lib.scala 178:24] - _T_110[19] <= _T_109 @[el2_lib.scala 178:24] - _T_110[20] <= _T_109 @[el2_lib.scala 178:24] - _T_110[21] <= _T_109 @[el2_lib.scala 178:24] - _T_110[22] <= _T_109 @[el2_lib.scala 178:24] - _T_110[23] <= _T_109 @[el2_lib.scala 178:24] - _T_110[24] <= _T_109 @[el2_lib.scala 178:24] - _T_110[25] <= _T_109 @[el2_lib.scala 178:24] - _T_110[26] <= _T_109 @[el2_lib.scala 178:24] - _T_110[27] <= _T_109 @[el2_lib.scala 178:24] - _T_110[28] <= _T_109 @[el2_lib.scala 178:24] - _T_110[29] <= _T_109 @[el2_lib.scala 178:24] - _T_110[30] <= _T_109 @[el2_lib.scala 178:24] - node _T_111 = cat(_T_110[0], _T_110[1]) @[Cat.scala 29:58] - node _T_112 = cat(_T_111, _T_110[2]) @[Cat.scala 29:58] - node _T_113 = cat(_T_112, _T_110[3]) @[Cat.scala 29:58] - node _T_114 = cat(_T_113, _T_110[4]) @[Cat.scala 29:58] - node _T_115 = cat(_T_114, _T_110[5]) @[Cat.scala 29:58] - node _T_116 = cat(_T_115, _T_110[6]) @[Cat.scala 29:58] - node _T_117 = cat(_T_116, _T_110[7]) @[Cat.scala 29:58] - node _T_118 = cat(_T_117, _T_110[8]) @[Cat.scala 29:58] - node _T_119 = cat(_T_118, _T_110[9]) @[Cat.scala 29:58] - node _T_120 = cat(_T_119, _T_110[10]) @[Cat.scala 29:58] - node _T_121 = cat(_T_120, _T_110[11]) @[Cat.scala 29:58] - node _T_122 = cat(_T_121, _T_110[12]) @[Cat.scala 29:58] - node _T_123 = cat(_T_122, _T_110[13]) @[Cat.scala 29:58] - node _T_124 = cat(_T_123, _T_110[14]) @[Cat.scala 29:58] - node _T_125 = cat(_T_124, _T_110[15]) @[Cat.scala 29:58] - node _T_126 = cat(_T_125, _T_110[16]) @[Cat.scala 29:58] - node _T_127 = cat(_T_126, _T_110[17]) @[Cat.scala 29:58] - node _T_128 = cat(_T_127, _T_110[18]) @[Cat.scala 29:58] - node _T_129 = cat(_T_128, _T_110[19]) @[Cat.scala 29:58] - node _T_130 = cat(_T_129, _T_110[20]) @[Cat.scala 29:58] - node _T_131 = cat(_T_130, _T_110[21]) @[Cat.scala 29:58] - node _T_132 = cat(_T_131, _T_110[22]) @[Cat.scala 29:58] - node _T_133 = cat(_T_132, _T_110[23]) @[Cat.scala 29:58] - node _T_134 = cat(_T_133, _T_110[24]) @[Cat.scala 29:58] - node _T_135 = cat(_T_134, _T_110[25]) @[Cat.scala 29:58] - node _T_136 = cat(_T_135, _T_110[26]) @[Cat.scala 29:58] - node _T_137 = cat(_T_136, _T_110[27]) @[Cat.scala 29:58] - node _T_138 = cat(_T_137, _T_110[28]) @[Cat.scala 29:58] - node _T_139 = cat(_T_138, _T_110[29]) @[Cat.scala 29:58] - node _T_140 = cat(_T_139, _T_110[30]) @[Cat.scala 29:58] - node _T_141 = and(_T_108, _T_140) @[el2_exu_alu_ctl.scala 72:44] - wire _T_142 : UInt<1>[31] @[el2_lib.scala 178:24] - _T_142[0] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[1] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[2] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[3] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[4] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[5] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[6] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[7] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[8] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[9] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[10] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[11] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[12] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[13] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[14] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[15] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[16] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[17] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[18] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[19] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[20] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[21] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[22] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[23] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[24] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[25] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[26] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[27] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[28] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[29] <= io.ap.sll @[el2_lib.scala 178:24] - _T_142[30] <= io.ap.sll @[el2_lib.scala 178:24] - node _T_143 = cat(_T_142[0], _T_142[1]) @[Cat.scala 29:58] - node _T_144 = cat(_T_143, _T_142[2]) @[Cat.scala 29:58] - node _T_145 = cat(_T_144, _T_142[3]) @[Cat.scala 29:58] - node _T_146 = cat(_T_145, _T_142[4]) @[Cat.scala 29:58] - node _T_147 = cat(_T_146, _T_142[5]) @[Cat.scala 29:58] - node _T_148 = cat(_T_147, _T_142[6]) @[Cat.scala 29:58] - node _T_149 = cat(_T_148, _T_142[7]) @[Cat.scala 29:58] - node _T_150 = cat(_T_149, _T_142[8]) @[Cat.scala 29:58] - node _T_151 = cat(_T_150, _T_142[9]) @[Cat.scala 29:58] - node _T_152 = cat(_T_151, _T_142[10]) @[Cat.scala 29:58] - node _T_153 = cat(_T_152, _T_142[11]) @[Cat.scala 29:58] - node _T_154 = cat(_T_153, _T_142[12]) @[Cat.scala 29:58] - node _T_155 = cat(_T_154, _T_142[13]) @[Cat.scala 29:58] - node _T_156 = cat(_T_155, _T_142[14]) @[Cat.scala 29:58] - node _T_157 = cat(_T_156, _T_142[15]) @[Cat.scala 29:58] - node _T_158 = cat(_T_157, _T_142[16]) @[Cat.scala 29:58] - node _T_159 = cat(_T_158, _T_142[17]) @[Cat.scala 29:58] - node _T_160 = cat(_T_159, _T_142[18]) @[Cat.scala 29:58] - node _T_161 = cat(_T_160, _T_142[19]) @[Cat.scala 29:58] - node _T_162 = cat(_T_161, _T_142[20]) @[Cat.scala 29:58] - node _T_163 = cat(_T_162, _T_142[21]) @[Cat.scala 29:58] - node _T_164 = cat(_T_163, _T_142[22]) @[Cat.scala 29:58] - node _T_165 = cat(_T_164, _T_142[23]) @[Cat.scala 29:58] - node _T_166 = cat(_T_165, _T_142[24]) @[Cat.scala 29:58] - node _T_167 = cat(_T_166, _T_142[25]) @[Cat.scala 29:58] - node _T_168 = cat(_T_167, _T_142[26]) @[Cat.scala 29:58] - node _T_169 = cat(_T_168, _T_142[27]) @[Cat.scala 29:58] - node _T_170 = cat(_T_169, _T_142[28]) @[Cat.scala 29:58] - node _T_171 = cat(_T_170, _T_142[29]) @[Cat.scala 29:58] - node _T_172 = cat(_T_171, _T_142[30]) @[Cat.scala 29:58] - node _T_173 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 72:99] - node _T_174 = and(_T_172, _T_173) @[el2_exu_alu_ctl.scala 72:90] - node _T_175 = or(_T_141, _T_174) @[el2_exu_alu_ctl.scala 72:68] - node _T_176 = cat(_T_175, io.a_in) @[Cat.scala 29:58] - shift_extend <= _T_176 @[el2_exu_alu_ctl.scala 72:16] + wire _T_106 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_106[0] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[1] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[2] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[3] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[4] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[5] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[6] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[7] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[8] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[9] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[10] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[11] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[12] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[13] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[14] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[15] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[16] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[17] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[18] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[19] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[20] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[21] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[22] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[23] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[24] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[25] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[26] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[27] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[28] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[29] <= io.ap.sra @[el2_lib.scala 161:48] + _T_106[30] <= io.ap.sra @[el2_lib.scala 161:48] + node _T_107 = cat(_T_106[0], _T_106[1]) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_106[2]) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_106[3]) @[Cat.scala 29:58] + node _T_110 = cat(_T_109, _T_106[4]) @[Cat.scala 29:58] + node _T_111 = cat(_T_110, _T_106[5]) @[Cat.scala 29:58] + node _T_112 = cat(_T_111, _T_106[6]) @[Cat.scala 29:58] + node _T_113 = cat(_T_112, _T_106[7]) @[Cat.scala 29:58] + node _T_114 = cat(_T_113, _T_106[8]) @[Cat.scala 29:58] + node _T_115 = cat(_T_114, _T_106[9]) @[Cat.scala 29:58] + node _T_116 = cat(_T_115, _T_106[10]) @[Cat.scala 29:58] + node _T_117 = cat(_T_116, _T_106[11]) @[Cat.scala 29:58] + node _T_118 = cat(_T_117, _T_106[12]) @[Cat.scala 29:58] + node _T_119 = cat(_T_118, _T_106[13]) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_106[14]) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_106[15]) @[Cat.scala 29:58] + node _T_122 = cat(_T_121, _T_106[16]) @[Cat.scala 29:58] + node _T_123 = cat(_T_122, _T_106[17]) @[Cat.scala 29:58] + node _T_124 = cat(_T_123, _T_106[18]) @[Cat.scala 29:58] + node _T_125 = cat(_T_124, _T_106[19]) @[Cat.scala 29:58] + node _T_126 = cat(_T_125, _T_106[20]) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_106[21]) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_106[22]) @[Cat.scala 29:58] + node _T_129 = cat(_T_128, _T_106[23]) @[Cat.scala 29:58] + node _T_130 = cat(_T_129, _T_106[24]) @[Cat.scala 29:58] + node _T_131 = cat(_T_130, _T_106[25]) @[Cat.scala 29:58] + node _T_132 = cat(_T_131, _T_106[26]) @[Cat.scala 29:58] + node _T_133 = cat(_T_132, _T_106[27]) @[Cat.scala 29:58] + node _T_134 = cat(_T_133, _T_106[28]) @[Cat.scala 29:58] + node _T_135 = cat(_T_134, _T_106[29]) @[Cat.scala 29:58] + node _T_136 = cat(_T_135, _T_106[30]) @[Cat.scala 29:58] + node _T_137 = bits(io.a_in, 31, 31) @[el2_exu_alu_ctl.scala 69:61] + wire _T_138 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_138[0] <= _T_137 @[el2_lib.scala 161:48] + _T_138[1] <= _T_137 @[el2_lib.scala 161:48] + _T_138[2] <= _T_137 @[el2_lib.scala 161:48] + _T_138[3] <= _T_137 @[el2_lib.scala 161:48] + _T_138[4] <= _T_137 @[el2_lib.scala 161:48] + _T_138[5] <= _T_137 @[el2_lib.scala 161:48] + _T_138[6] <= _T_137 @[el2_lib.scala 161:48] + _T_138[7] <= _T_137 @[el2_lib.scala 161:48] + _T_138[8] <= _T_137 @[el2_lib.scala 161:48] + _T_138[9] <= _T_137 @[el2_lib.scala 161:48] + _T_138[10] <= _T_137 @[el2_lib.scala 161:48] + _T_138[11] <= _T_137 @[el2_lib.scala 161:48] + _T_138[12] <= _T_137 @[el2_lib.scala 161:48] + _T_138[13] <= _T_137 @[el2_lib.scala 161:48] + _T_138[14] <= _T_137 @[el2_lib.scala 161:48] + _T_138[15] <= _T_137 @[el2_lib.scala 161:48] + _T_138[16] <= _T_137 @[el2_lib.scala 161:48] + _T_138[17] <= _T_137 @[el2_lib.scala 161:48] + _T_138[18] <= _T_137 @[el2_lib.scala 161:48] + _T_138[19] <= _T_137 @[el2_lib.scala 161:48] + _T_138[20] <= _T_137 @[el2_lib.scala 161:48] + _T_138[21] <= _T_137 @[el2_lib.scala 161:48] + _T_138[22] <= _T_137 @[el2_lib.scala 161:48] + _T_138[23] <= _T_137 @[el2_lib.scala 161:48] + _T_138[24] <= _T_137 @[el2_lib.scala 161:48] + _T_138[25] <= _T_137 @[el2_lib.scala 161:48] + _T_138[26] <= _T_137 @[el2_lib.scala 161:48] + _T_138[27] <= _T_137 @[el2_lib.scala 161:48] + _T_138[28] <= _T_137 @[el2_lib.scala 161:48] + _T_138[29] <= _T_137 @[el2_lib.scala 161:48] + _T_138[30] <= _T_137 @[el2_lib.scala 161:48] + node _T_139 = cat(_T_138[0], _T_138[1]) @[Cat.scala 29:58] + node _T_140 = cat(_T_139, _T_138[2]) @[Cat.scala 29:58] + node _T_141 = cat(_T_140, _T_138[3]) @[Cat.scala 29:58] + node _T_142 = cat(_T_141, _T_138[4]) @[Cat.scala 29:58] + node _T_143 = cat(_T_142, _T_138[5]) @[Cat.scala 29:58] + node _T_144 = cat(_T_143, _T_138[6]) @[Cat.scala 29:58] + node _T_145 = cat(_T_144, _T_138[7]) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_138[8]) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_138[9]) @[Cat.scala 29:58] + node _T_148 = cat(_T_147, _T_138[10]) @[Cat.scala 29:58] + node _T_149 = cat(_T_148, _T_138[11]) @[Cat.scala 29:58] + node _T_150 = cat(_T_149, _T_138[12]) @[Cat.scala 29:58] + node _T_151 = cat(_T_150, _T_138[13]) @[Cat.scala 29:58] + node _T_152 = cat(_T_151, _T_138[14]) @[Cat.scala 29:58] + node _T_153 = cat(_T_152, _T_138[15]) @[Cat.scala 29:58] + node _T_154 = cat(_T_153, _T_138[16]) @[Cat.scala 29:58] + node _T_155 = cat(_T_154, _T_138[17]) @[Cat.scala 29:58] + node _T_156 = cat(_T_155, _T_138[18]) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_138[19]) @[Cat.scala 29:58] + node _T_158 = cat(_T_157, _T_138[20]) @[Cat.scala 29:58] + node _T_159 = cat(_T_158, _T_138[21]) @[Cat.scala 29:58] + node _T_160 = cat(_T_159, _T_138[22]) @[Cat.scala 29:58] + node _T_161 = cat(_T_160, _T_138[23]) @[Cat.scala 29:58] + node _T_162 = cat(_T_161, _T_138[24]) @[Cat.scala 29:58] + node _T_163 = cat(_T_162, _T_138[25]) @[Cat.scala 29:58] + node _T_164 = cat(_T_163, _T_138[26]) @[Cat.scala 29:58] + node _T_165 = cat(_T_164, _T_138[27]) @[Cat.scala 29:58] + node _T_166 = cat(_T_165, _T_138[28]) @[Cat.scala 29:58] + node _T_167 = cat(_T_166, _T_138[29]) @[Cat.scala 29:58] + node _T_168 = cat(_T_167, _T_138[30]) @[Cat.scala 29:58] + node _T_169 = and(_T_136, _T_168) @[el2_exu_alu_ctl.scala 69:44] + wire _T_170 : UInt<1>[31] @[el2_lib.scala 161:48] + _T_170[0] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[1] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[2] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[3] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[4] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[5] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[6] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[7] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[8] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[9] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[10] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[11] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[12] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[13] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[14] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[15] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[16] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[17] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[18] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[19] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[20] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[21] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[22] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[23] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[24] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[25] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[26] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[27] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[28] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[29] <= io.ap.sll @[el2_lib.scala 161:48] + _T_170[30] <= io.ap.sll @[el2_lib.scala 161:48] + node _T_171 = cat(_T_170[0], _T_170[1]) @[Cat.scala 29:58] + node _T_172 = cat(_T_171, _T_170[2]) @[Cat.scala 29:58] + node _T_173 = cat(_T_172, _T_170[3]) @[Cat.scala 29:58] + node _T_174 = cat(_T_173, _T_170[4]) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_170[5]) @[Cat.scala 29:58] + node _T_176 = cat(_T_175, _T_170[6]) @[Cat.scala 29:58] + node _T_177 = cat(_T_176, _T_170[7]) @[Cat.scala 29:58] + node _T_178 = cat(_T_177, _T_170[8]) @[Cat.scala 29:58] + node _T_179 = cat(_T_178, _T_170[9]) @[Cat.scala 29:58] + node _T_180 = cat(_T_179, _T_170[10]) @[Cat.scala 29:58] + node _T_181 = cat(_T_180, _T_170[11]) @[Cat.scala 29:58] + node _T_182 = cat(_T_181, _T_170[12]) @[Cat.scala 29:58] + node _T_183 = cat(_T_182, _T_170[13]) @[Cat.scala 29:58] + node _T_184 = cat(_T_183, _T_170[14]) @[Cat.scala 29:58] + node _T_185 = cat(_T_184, _T_170[15]) @[Cat.scala 29:58] + node _T_186 = cat(_T_185, _T_170[16]) @[Cat.scala 29:58] + node _T_187 = cat(_T_186, _T_170[17]) @[Cat.scala 29:58] + node _T_188 = cat(_T_187, _T_170[18]) @[Cat.scala 29:58] + node _T_189 = cat(_T_188, _T_170[19]) @[Cat.scala 29:58] + node _T_190 = cat(_T_189, _T_170[20]) @[Cat.scala 29:58] + node _T_191 = cat(_T_190, _T_170[21]) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_170[22]) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_170[23]) @[Cat.scala 29:58] + node _T_194 = cat(_T_193, _T_170[24]) @[Cat.scala 29:58] + node _T_195 = cat(_T_194, _T_170[25]) @[Cat.scala 29:58] + node _T_196 = cat(_T_195, _T_170[26]) @[Cat.scala 29:58] + node _T_197 = cat(_T_196, _T_170[27]) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_170[28]) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_170[29]) @[Cat.scala 29:58] + node _T_200 = cat(_T_199, _T_170[30]) @[Cat.scala 29:58] + node _T_201 = bits(io.a_in, 30, 0) @[el2_exu_alu_ctl.scala 69:99] + node _T_202 = and(_T_200, _T_201) @[el2_exu_alu_ctl.scala 69:90] + node _T_203 = or(_T_169, _T_202) @[el2_exu_alu_ctl.scala 69:68] + node _T_204 = asUInt(io.a_in) @[Cat.scala 29:58] + node _T_205 = cat(_T_203, _T_204) @[Cat.scala 29:58] + shift_extend <= _T_205 @[el2_exu_alu_ctl.scala 69:16] wire shift_long : UInt<63> shift_long <= UInt<1>("h00") - node _T_177 = dshr(shift_extend, shift_amount) @[el2_exu_alu_ctl.scala 75:32] - shift_long <= _T_177 @[el2_exu_alu_ctl.scala 75:14] - node _T_178 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 77:27] - node _T_179 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 77:46] - node sout = and(_T_178, _T_179) @[el2_exu_alu_ctl.scala 77:34] - node _T_180 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 80:41] - node sel_shift = or(_T_180, io.ap.sra) @[el2_exu_alu_ctl.scala 80:53] - node _T_181 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 81:41] - node _T_182 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 81:56] - node sel_adder = and(_T_181, _T_182) @[el2_exu_alu_ctl.scala 81:54] - node _T_183 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 82:41] - node _T_184 = or(_T_183, io.pp_in.pja) @[el2_exu_alu_ctl.scala 82:58] - node sel_pc = or(_T_184, io.pp_in.pret) @[el2_exu_alu_ctl.scala 82:73] - node _T_185 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 83:47] - node csr_write_data = mux(_T_185, io.b_in, io.a_in) @[el2_exu_alu_ctl.scala 83:32] - node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 85:40] - node _T_186 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_187 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_188 = bits(_T_186, 12, 1) @[el2_lib.scala 201:24] - node _T_189 = bits(_T_187, 12, 1) @[el2_lib.scala 201:40] - node _T_190 = add(_T_188, _T_189) @[el2_lib.scala 201:31] - node _T_191 = bits(_T_186, 31, 13) @[el2_lib.scala 202:20] - node _T_192 = add(_T_191, UInt<1>("h01")) @[el2_lib.scala 202:27] - node _T_193 = tail(_T_192, 1) @[el2_lib.scala 202:27] - node _T_194 = bits(_T_186, 31, 13) @[el2_lib.scala 203:20] - node _T_195 = sub(_T_194, UInt<1>("h01")) @[el2_lib.scala 203:27] - node _T_196 = tail(_T_195, 1) @[el2_lib.scala 203:27] - node _T_197 = bits(_T_187, 12, 12) @[el2_lib.scala 204:22] - node _T_198 = bits(_T_190, 12, 12) @[el2_lib.scala 205:38] - node _T_199 = eq(_T_198, UInt<1>("h00")) @[el2_lib.scala 205:27] - node _T_200 = xor(_T_197, _T_199) @[el2_lib.scala 205:25] - node _T_201 = bits(_T_200, 0, 0) @[el2_lib.scala 205:63] - node _T_202 = bits(_T_186, 31, 13) @[el2_lib.scala 205:75] - node _T_203 = eq(_T_197, UInt<1>("h00")) @[el2_lib.scala 206:8] - node _T_204 = bits(_T_190, 12, 12) @[el2_lib.scala 206:26] - node _T_205 = and(_T_203, _T_204) @[el2_lib.scala 206:14] - node _T_206 = bits(_T_205, 0, 0) @[el2_lib.scala 206:51] - node _T_207 = bits(_T_190, 12, 12) @[el2_lib.scala 207:26] - node _T_208 = eq(_T_207, UInt<1>("h00")) @[el2_lib.scala 207:15] - node _T_209 = and(_T_197, _T_208) @[el2_lib.scala 207:13] - node _T_210 = bits(_T_209, 0, 0) @[el2_lib.scala 207:51] - node _T_211 = mux(_T_201, _T_202, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_212 = mux(_T_206, _T_193, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_213 = mux(_T_210, _T_196, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_214 = or(_T_211, _T_212) @[Mux.scala 27:72] - node _T_215 = or(_T_214, _T_213) @[Mux.scala 27:72] - wire _T_216 : UInt<19> @[Mux.scala 27:72] - _T_216 <= _T_215 @[Mux.scala 27:72] - node _T_217 = bits(_T_190, 11, 0) @[el2_lib.scala 207:83] - node _T_218 = cat(_T_216, _T_217) @[Cat.scala 29:58] - node pcout = cat(_T_218, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_219 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 91:32] - node _T_220 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 92:15] - node _T_221 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 92:41] - node _T_222 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 93:15] - node _T_223 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 93:41] - node _T_224 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 94:12] - node _T_225 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 95:21] - node _T_226 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 95:51] - node _T_227 = bits(slt_one, 0, 0) @[el2_exu_alu_ctl.scala 96:13] - node _T_228 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58] - node _T_229 = mux(_T_227, _T_228, _T_219) @[Mux.scala 98:16] - node _T_230 = mux(_T_225, _T_226, _T_229) @[Mux.scala 98:16] - node _T_231 = mux(_T_224, pcout, _T_230) @[Mux.scala 98:16] - node _T_232 = mux(_T_222, _T_223, _T_231) @[Mux.scala 98:16] - node _T_233 = mux(_T_220, _T_221, _T_232) @[Mux.scala 98:16] - result <= _T_233 @[el2_exu_alu_ctl.scala 91:16] - node _T_234 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 100:45] - node _T_235 = or(_T_234, io.pp_in.pja) @[el2_exu_alu_ctl.scala 101:20] - node any_jal = or(_T_235, io.pp_in.pret) @[el2_exu_alu_ctl.scala 102:20] - node _T_236 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 105:40] - node _T_237 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 105:59] - node _T_238 = or(_T_236, _T_237) @[el2_exu_alu_ctl.scala 105:46] - node _T_239 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 105:85] - node _T_240 = or(_T_238, _T_239) @[el2_exu_alu_ctl.scala 105:72] - node _T_241 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 105:104] - node _T_242 = or(_T_240, _T_241) @[el2_exu_alu_ctl.scala 105:91] - node actual_taken = or(_T_242, any_jal) @[el2_exu_alu_ctl.scala 105:110] - node _T_243 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 110:42] - node _T_244 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:63] - node _T_245 = and(_T_243, _T_244) @[el2_exu_alu_ctl.scala 110:61] - node _T_246 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:79] - node _T_247 = and(_T_245, _T_246) @[el2_exu_alu_ctl.scala 110:77] - node _T_248 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 110:104] - node _T_249 = and(_T_248, actual_taken) @[el2_exu_alu_ctl.scala 110:123] - node _T_250 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 110:141] - node _T_251 = and(_T_249, _T_250) @[el2_exu_alu_ctl.scala 110:139] - node _T_252 = or(_T_247, _T_251) @[el2_exu_alu_ctl.scala 110:89] - io.pred_correct_out <= _T_252 @[el2_exu_alu_ctl.scala 110:26] - node _T_253 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 112:37] - node _T_254 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 112:49] - node _T_255 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 112:62] - node _T_256 = mux(_T_253, _T_254, _T_255) @[el2_exu_alu_ctl.scala 112:28] - io.flush_path_out <= _T_256 @[el2_exu_alu_ctl.scala 112:22] - node _T_257 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 115:47] - node _T_258 = and(io.ap.predict_t, _T_257) @[el2_exu_alu_ctl.scala 115:45] - node _T_259 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 115:82] - node cond_mispredict = or(_T_258, _T_259) @[el2_exu_alu_ctl.scala 115:62] - node _T_260 = bits(io.pp_in.prett, 31, 1) @[el2_exu_alu_ctl.scala 118:61] - node _T_261 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 118:76] - node _T_262 = neq(_T_260, _T_261) @[el2_exu_alu_ctl.scala 118:68] - node target_mispredict = and(io.pp_in.pret, _T_262) @[el2_exu_alu_ctl.scala 118:44] - node _T_263 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 120:42] - node _T_264 = or(_T_263, target_mispredict) @[el2_exu_alu_ctl.scala 120:60] - node _T_265 = and(_T_264, io.valid_in) @[el2_exu_alu_ctl.scala 120:81] - node _T_266 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 120:97] - node _T_267 = and(_T_265, _T_266) @[el2_exu_alu_ctl.scala 120:95] - node _T_268 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 120:119] - node _T_269 = and(_T_267, _T_268) @[el2_exu_alu_ctl.scala 120:117] - io.flush_upper_out <= _T_269 @[el2_exu_alu_ctl.scala 120:26] - node _T_270 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 122:42] - node _T_271 = or(_T_270, target_mispredict) @[el2_exu_alu_ctl.scala 122:60] - node _T_272 = and(_T_271, io.valid_in) @[el2_exu_alu_ctl.scala 122:81] - node _T_273 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 122:97] - node _T_274 = and(_T_272, _T_273) @[el2_exu_alu_ctl.scala 122:95] - node _T_275 = or(_T_274, io.flush_lower_r) @[el2_exu_alu_ctl.scala 122:117] - io.flush_final_out <= _T_275 @[el2_exu_alu_ctl.scala 122:26] + node _T_206 = bits(shift_amount, 4, 0) @[el2_exu_alu_ctl.scala 72:47] + node _T_207 = dshr(shift_extend, _T_206) @[el2_exu_alu_ctl.scala 72:32] + shift_long <= _T_207 @[el2_exu_alu_ctl.scala 72:14] + node _T_208 = bits(shift_long, 31, 0) @[el2_exu_alu_ctl.scala 74:27] + node _T_209 = bits(shift_mask, 31, 0) @[el2_exu_alu_ctl.scala 74:46] + node sout = and(_T_208, _T_209) @[el2_exu_alu_ctl.scala 74:34] + node _T_210 = or(io.ap.sll, io.ap.srl) @[el2_exu_alu_ctl.scala 77:41] + node sel_shift = or(_T_210, io.ap.sra) @[el2_exu_alu_ctl.scala 77:53] + node _T_211 = or(io.ap.add, io.ap.sub) @[el2_exu_alu_ctl.scala 78:41] + node _T_212 = not(io.ap.slt) @[el2_exu_alu_ctl.scala 78:56] + node sel_adder = and(_T_211, _T_212) @[el2_exu_alu_ctl.scala 78:54] + node _T_213 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 79:41] + node _T_214 = or(_T_213, io.pp_in.pja) @[el2_exu_alu_ctl.scala 79:58] + node sel_pc = or(_T_214, io.pp_in.pret) @[el2_exu_alu_ctl.scala 79:73] + node _T_215 = bits(io.ap.csr_imm, 0, 0) @[el2_exu_alu_ctl.scala 80:47] + node _T_216 = asSInt(io.b_in) @[el2_exu_alu_ctl.scala 80:63] + node csr_write_data = mux(_T_215, _T_216, io.a_in) @[el2_exu_alu_ctl.scala 80:32] + node slt_one = and(io.ap.slt, lt) @[el2_exu_alu_ctl.scala 82:40] + node _T_217 = cat(io.pc_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_218 = cat(io.brimm_in, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_219 = bits(_T_217, 12, 1) @[el2_lib.scala 208:24] + node _T_220 = bits(_T_218, 12, 1) @[el2_lib.scala 208:40] + node _T_221 = add(_T_219, _T_220) @[el2_lib.scala 208:31] + node _T_222 = bits(_T_217, 31, 13) @[el2_lib.scala 209:20] + node _T_223 = add(_T_222, UInt<1>("h01")) @[el2_lib.scala 209:27] + node _T_224 = tail(_T_223, 1) @[el2_lib.scala 209:27] + node _T_225 = bits(_T_217, 31, 13) @[el2_lib.scala 210:20] + node _T_226 = sub(_T_225, UInt<1>("h01")) @[el2_lib.scala 210:27] + node _T_227 = tail(_T_226, 1) @[el2_lib.scala 210:27] + node _T_228 = bits(_T_218, 12, 12) @[el2_lib.scala 211:22] + node _T_229 = bits(_T_221, 12, 12) @[el2_lib.scala 212:39] + node _T_230 = eq(_T_229, UInt<1>("h00")) @[el2_lib.scala 212:28] + node _T_231 = xor(_T_228, _T_230) @[el2_lib.scala 212:26] + node _T_232 = bits(_T_231, 0, 0) @[el2_lib.scala 212:64] + node _T_233 = bits(_T_217, 31, 13) @[el2_lib.scala 212:76] + node _T_234 = eq(_T_228, UInt<1>("h00")) @[el2_lib.scala 213:8] + node _T_235 = bits(_T_221, 12, 12) @[el2_lib.scala 213:27] + node _T_236 = and(_T_234, _T_235) @[el2_lib.scala 213:14] + node _T_237 = bits(_T_236, 0, 0) @[el2_lib.scala 213:52] + node _T_238 = bits(_T_221, 12, 12) @[el2_lib.scala 214:27] + node _T_239 = eq(_T_238, UInt<1>("h00")) @[el2_lib.scala 214:16] + node _T_240 = and(_T_228, _T_239) @[el2_lib.scala 214:14] + node _T_241 = bits(_T_240, 0, 0) @[el2_lib.scala 214:52] + node _T_242 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_243 = mux(_T_237, _T_224, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_244 = mux(_T_241, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = or(_T_242, _T_243) @[Mux.scala 27:72] + node _T_246 = or(_T_245, _T_244) @[Mux.scala 27:72] + wire _T_247 : UInt<19> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(_T_221, 11, 0) @[el2_lib.scala 214:82] + node _T_249 = cat(_T_247, _T_248) @[Cat.scala 29:58] + node pcout = cat(_T_249, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_250 = bits(lout, 31, 0) @[el2_exu_alu_ctl.scala 88:24] + node _T_251 = cat(UInt<31>("h00"), slt_one) @[Cat.scala 29:58] + node _T_252 = or(_T_250, _T_251) @[el2_exu_alu_ctl.scala 88:31] + node _T_253 = bits(sel_shift, 0, 0) @[el2_exu_alu_ctl.scala 89:15] + node _T_254 = bits(sout, 31, 0) @[el2_exu_alu_ctl.scala 89:41] + node _T_255 = bits(sel_adder, 0, 0) @[el2_exu_alu_ctl.scala 90:15] + node _T_256 = bits(aout, 31, 0) @[el2_exu_alu_ctl.scala 90:41] + node _T_257 = bits(sel_pc, 0, 0) @[el2_exu_alu_ctl.scala 91:12] + node _T_258 = bits(io.ap.csr_write, 0, 0) @[el2_exu_alu_ctl.scala 92:21] + node _T_259 = bits(csr_write_data, 31, 0) @[el2_exu_alu_ctl.scala 92:51] + node _T_260 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_261 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_262 = mux(_T_257, pcout, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_263 = mux(_T_258, _T_259, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = or(_T_260, _T_261) @[Mux.scala 27:72] + node _T_265 = or(_T_264, _T_262) @[Mux.scala 27:72] + node _T_266 = or(_T_265, _T_263) @[Mux.scala 27:72] + wire _T_267 : UInt<32> @[Mux.scala 27:72] + _T_267 <= _T_266 @[Mux.scala 27:72] + node _T_268 = or(_T_252, _T_267) @[el2_exu_alu_ctl.scala 88:56] + result <= _T_268 @[el2_exu_alu_ctl.scala 88:16] + node _T_269 = or(io.ap.jal, io.pp_in.pcall) @[el2_exu_alu_ctl.scala 96:45] + node _T_270 = or(_T_269, io.pp_in.pja) @[el2_exu_alu_ctl.scala 97:20] + node any_jal = or(_T_270, io.pp_in.pret) @[el2_exu_alu_ctl.scala 98:20] + node _T_271 = and(io.ap.beq, eq) @[el2_exu_alu_ctl.scala 101:40] + node _T_272 = and(io.ap.bne, ne) @[el2_exu_alu_ctl.scala 101:59] + node _T_273 = or(_T_271, _T_272) @[el2_exu_alu_ctl.scala 101:46] + node _T_274 = and(io.ap.blt, lt) @[el2_exu_alu_ctl.scala 101:85] + node _T_275 = or(_T_273, _T_274) @[el2_exu_alu_ctl.scala 101:72] + node _T_276 = and(io.ap.bge, ge) @[el2_exu_alu_ctl.scala 101:104] + node _T_277 = or(_T_275, _T_276) @[el2_exu_alu_ctl.scala 101:91] + node actual_taken = or(_T_277, any_jal) @[el2_exu_alu_ctl.scala 101:110] + node _T_278 = and(io.valid_in, io.ap.predict_nt) @[el2_exu_alu_ctl.scala 106:42] + node _T_279 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:63] + node _T_280 = and(_T_278, _T_279) @[el2_exu_alu_ctl.scala 106:61] + node _T_281 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:79] + node _T_282 = and(_T_280, _T_281) @[el2_exu_alu_ctl.scala 106:77] + node _T_283 = and(io.valid_in, io.ap.predict_t) @[el2_exu_alu_ctl.scala 106:104] + node _T_284 = and(_T_283, actual_taken) @[el2_exu_alu_ctl.scala 106:123] + node _T_285 = eq(any_jal, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 106:141] + node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 106:139] + node _T_287 = or(_T_282, _T_286) @[el2_exu_alu_ctl.scala 106:89] + io.pred_correct_out <= _T_287 @[el2_exu_alu_ctl.scala 106:26] + node _T_288 = bits(any_jal, 0, 0) @[el2_exu_alu_ctl.scala 108:37] + node _T_289 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 108:49] + node _T_290 = bits(pcout, 31, 1) @[el2_exu_alu_ctl.scala 108:62] + node _T_291 = mux(_T_288, _T_289, _T_290) @[el2_exu_alu_ctl.scala 108:28] + io.flush_path_out <= _T_291 @[el2_exu_alu_ctl.scala 108:22] + node _T_292 = eq(actual_taken, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 111:47] + node _T_293 = and(io.ap.predict_t, _T_292) @[el2_exu_alu_ctl.scala 111:45] + node _T_294 = and(io.ap.predict_nt, actual_taken) @[el2_exu_alu_ctl.scala 111:82] + node cond_mispredict = or(_T_293, _T_294) @[el2_exu_alu_ctl.scala 111:62] + node _T_295 = bits(aout, 31, 1) @[el2_exu_alu_ctl.scala 114:70] + node _T_296 = neq(io.pp_in.prett, _T_295) @[el2_exu_alu_ctl.scala 114:62] + node target_mispredict = and(io.pp_in.pret, _T_296) @[el2_exu_alu_ctl.scala 114:44] + node _T_297 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 116:42] + node _T_298 = or(_T_297, target_mispredict) @[el2_exu_alu_ctl.scala 116:60] + node _T_299 = and(_T_298, io.valid_in) @[el2_exu_alu_ctl.scala 116:81] + node _T_300 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:97] + node _T_301 = and(_T_299, _T_300) @[el2_exu_alu_ctl.scala 116:95] + node _T_302 = eq(io.flush_lower_r, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 116:119] + node _T_303 = and(_T_301, _T_302) @[el2_exu_alu_ctl.scala 116:117] + io.flush_upper_out <= _T_303 @[el2_exu_alu_ctl.scala 116:26] + node _T_304 = or(io.ap.jal, cond_mispredict) @[el2_exu_alu_ctl.scala 118:42] + node _T_305 = or(_T_304, target_mispredict) @[el2_exu_alu_ctl.scala 118:60] + node _T_306 = and(_T_305, io.valid_in) @[el2_exu_alu_ctl.scala 118:81] + node _T_307 = eq(io.flush_upper_x, UInt<1>("h00")) @[el2_exu_alu_ctl.scala 118:97] + node _T_308 = and(_T_306, _T_307) @[el2_exu_alu_ctl.scala 118:95] + node _T_309 = or(_T_308, io.flush_lower_r) @[el2_exu_alu_ctl.scala 118:117] + io.flush_final_out <= _T_309 @[el2_exu_alu_ctl.scala 118:26] wire newhist : UInt<2> newhist <= UInt<1>("h00") - node _T_276 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 126:35] - node _T_277 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 126:55] - node _T_278 = and(_T_276, _T_277) @[el2_exu_alu_ctl.scala 126:39] - node _T_279 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 126:77] - node _T_280 = not(_T_279) @[el2_exu_alu_ctl.scala 126:63] - node _T_281 = and(_T_280, actual_taken) @[el2_exu_alu_ctl.scala 126:81] - node _T_282 = or(_T_278, _T_281) @[el2_exu_alu_ctl.scala 126:60] - node _T_283 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 127:20] - node _T_284 = not(_T_283) @[el2_exu_alu_ctl.scala 127:6] - node _T_285 = not(actual_taken) @[el2_exu_alu_ctl.scala 127:26] - node _T_286 = and(_T_284, _T_285) @[el2_exu_alu_ctl.scala 127:24] - node _T_287 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 127:58] - node _T_288 = and(_T_287, actual_taken) @[el2_exu_alu_ctl.scala 127:62] - node _T_289 = or(_T_286, _T_288) @[el2_exu_alu_ctl.scala 127:42] - node _T_290 = cat(_T_282, _T_289) @[Cat.scala 29:58] - newhist <= _T_290 @[el2_exu_alu_ctl.scala 126:14] - io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 129:30] - io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 129:30] - node _T_291 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 130:33] - node _T_292 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 130:53] - node _T_293 = and(_T_291, _T_292) @[el2_exu_alu_ctl.scala 130:51] - node _T_294 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 130:90] - node _T_295 = and(_T_293, _T_294) @[el2_exu_alu_ctl.scala 130:71] - io.predict_p_out.misp <= _T_295 @[el2_exu_alu_ctl.scala 130:30] - io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 131:30] - io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 132:30] + node _T_310 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 122:35] + node _T_311 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:55] + node _T_312 = and(_T_310, _T_311) @[el2_exu_alu_ctl.scala 122:39] + node _T_313 = bits(io.pp_in.hist, 0, 0) @[el2_exu_alu_ctl.scala 122:77] + node _T_314 = not(_T_313) @[el2_exu_alu_ctl.scala 122:63] + node _T_315 = and(_T_314, actual_taken) @[el2_exu_alu_ctl.scala 122:81] + node _T_316 = or(_T_312, _T_315) @[el2_exu_alu_ctl.scala 122:60] + node _T_317 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:20] + node _T_318 = not(_T_317) @[el2_exu_alu_ctl.scala 123:6] + node _T_319 = not(actual_taken) @[el2_exu_alu_ctl.scala 123:26] + node _T_320 = and(_T_318, _T_319) @[el2_exu_alu_ctl.scala 123:24] + node _T_321 = bits(io.pp_in.hist, 1, 1) @[el2_exu_alu_ctl.scala 123:58] + node _T_322 = and(_T_321, actual_taken) @[el2_exu_alu_ctl.scala 123:62] + node _T_323 = or(_T_320, _T_322) @[el2_exu_alu_ctl.scala 123:42] + node _T_324 = cat(_T_316, _T_323) @[Cat.scala 29:58] + newhist <= _T_324 @[el2_exu_alu_ctl.scala 122:14] + io.predict_p_out.way <= io.pp_in.way @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pja <= io.pp_in.pja @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pret <= io.pp_in.pret @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pcall <= io.pp_in.pcall @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.prett <= io.pp_in.prett @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_start_error <= io.pp_in.br_start_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.br_error <= io.pp_in.br_error @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.valid <= io.pp_in.valid @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.toffset <= io.pp_in.toffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.hist <= io.pp_in.hist @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.pc4 <= io.pp_in.pc4 @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.boffset <= io.pp_in.boffset @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.ataken <= io.pp_in.ataken @[el2_exu_alu_ctl.scala 125:30] + io.predict_p_out.misp <= io.pp_in.misp @[el2_exu_alu_ctl.scala 125:30] + node _T_325 = not(io.flush_upper_x) @[el2_exu_alu_ctl.scala 126:33] + node _T_326 = not(io.flush_lower_r) @[el2_exu_alu_ctl.scala 126:53] + node _T_327 = and(_T_325, _T_326) @[el2_exu_alu_ctl.scala 126:51] + node _T_328 = or(cond_mispredict, target_mispredict) @[el2_exu_alu_ctl.scala 126:90] + node _T_329 = and(_T_327, _T_328) @[el2_exu_alu_ctl.scala 126:71] + io.predict_p_out.misp <= _T_329 @[el2_exu_alu_ctl.scala 126:30] + io.predict_p_out.ataken <= actual_taken @[el2_exu_alu_ctl.scala 127:30] + io.predict_p_out.hist <= newhist @[el2_exu_alu_ctl.scala 128:30] diff --git a/el2_exu_alu_ctl.v b/el2_exu_alu_ctl.v index 42d73fdc..8b3962b7 100644 --- a/el2_exu_alu_ctl.v +++ b/el2_exu_alu_ctl.v @@ -1,3 +1,24 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule module el2_exu_alu_ctl( input clock, input reset, @@ -38,7 +59,7 @@ module el2_exu_alu_ctl( input io_pp_in_valid, input io_pp_in_br_error, input io_pp_in_br_start_error, - input [31:0] io_pp_in_prett, + input [30:0] io_pp_in_prett, input io_pp_in_pcall, input io_pp_in_pret, input io_pp_in_pja, @@ -59,7 +80,7 @@ module el2_exu_alu_ctl( output io_predict_p_out_valid, output io_predict_p_out_br_error, output io_predict_p_out_br_start_error, - output [31:0] io_predict_p_out_prett, + output [30:0] io_predict_p_out_prett, output io_predict_p_out_pcall, output io_predict_p_out_pret, output io_predict_p_out_pja, @@ -69,161 +90,194 @@ module el2_exu_alu_ctl( reg [31:0] _RAND_0; reg [31:0] _RAND_1; `endif // RANDOMIZE_REG_INIT - reg [30:0] _T; // @[Reg.scala 27:20] - reg [31:0] _T_1; // @[Reg.scala 27:20] - wire _T_180 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 80:41] - wire sel_shift = _T_180 | io_ap_sra; // @[el2_exu_alu_ctl.scala 80:53] - wire [9:0] _T_87 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] - wire [18:0] _T_96 = {_T_87,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] - wire [27:0] _T_105 = {_T_96,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] - wire [30:0] _T_108 = {_T_105,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] - wire [9:0] _T_119 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] - wire [18:0] _T_128 = {_T_119,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] - wire [27:0] _T_137 = {_T_128,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] - wire [30:0] _T_140 = {_T_137,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] - wire [30:0] _T_141 = _T_108 & _T_140; // @[el2_exu_alu_ctl.scala 72:44] - wire [4:0] _T_146 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] - wire [9:0] _T_151 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] - wire [18:0] _T_160 = {_T_151,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] - wire [27:0] _T_169 = {_T_160,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] - wire [30:0] _T_172 = {_T_169,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] - wire [30:0] _T_174 = _T_172 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 72:90] - wire [30:0] _T_175 = _T_141 | _T_174; // @[el2_exu_alu_ctl.scala 72:68] - wire [62:0] shift_extend = {_T_175,io_a_in}; // @[Cat.scala 29:58] - wire [5:0] _T_56 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58] - wire [5:0] _T_58 = 6'h20 - _T_56; // @[el2_exu_alu_ctl.scala 64:38] - wire [5:0] _T_65 = io_ap_sll ? _T_58 : 6'h0; // @[Mux.scala 27:72] - wire [5:0] _T_66 = io_ap_srl ? _T_56 : 6'h0; // @[Mux.scala 27:72] - wire [5:0] _T_68 = _T_65 | _T_66; // @[Mux.scala 27:72] - wire [5:0] _T_67 = io_ap_sra ? _T_56 : 6'h0; // @[Mux.scala 27:72] - wire [5:0] shift_amount = _T_68 | _T_67; // @[Mux.scala 27:72] - wire [62:0] shift_long = shift_extend >> shift_amount; // @[el2_exu_alu_ctl.scala 75:32] - wire [4:0] _T_76 = _T_146 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 69:55] - wire [62:0] _T_77 = 63'hffffffff << _T_76; // @[el2_exu_alu_ctl.scala 69:33] - wire [31:0] shift_mask = _T_77[31:0]; // @[el2_exu_alu_ctl.scala 69:14] - wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 77:34] - wire _T_181 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 81:41] - wire _T_182 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 81:56] - wire sel_adder = _T_181 & _T_182; // @[el2_exu_alu_ctl.scala 81:54] - wire [32:0] _T_5 = {1'h0,io_a_in}; // @[Cat.scala 29:58] - wire [31:0] _T_6 = ~io_b_in; // @[el2_exu_alu_ctl.scala 43:63] - wire [32:0] _T_7 = {1'h0,_T_6}; // @[Cat.scala 29:58] - wire [32:0] _T_9 = _T_5 + _T_7; // @[el2_exu_alu_ctl.scala 43:48] - wire [32:0] _T_11 = _T_9 + 33'h1; // @[el2_exu_alu_ctl.scala 43:73] - wire [32:0] _T_18 = io_ap_sub ? _T_11 : 33'h0; // @[Mux.scala 27:72] - wire _T_13 = ~io_ap_sub; // @[el2_exu_alu_ctl.scala 44:5] - wire [32:0] _T_15 = {1'h0,io_b_in}; // @[Cat.scala 29:58] - wire [32:0] _T_17 = _T_5 + _T_15; // @[el2_exu_alu_ctl.scala 44:48] - wire [32:0] _T_19 = _T_13 ? _T_17 : 33'h0; // @[Mux.scala 27:72] - wire [32:0] aout = _T_18 | _T_19; // @[Mux.scala 27:72] - wire _T_183 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 82:41] - wire _T_184 = _T_183 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 82:58] - wire sel_pc = _T_184 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 82:73] - wire [12:0] _T_187 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] - wire [31:0] _T_186 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] - wire [12:0] _T_190 = _T_186[12:1] + _T_187[12:1]; // @[el2_lib.scala 201:31] - wire _T_199 = ~_T_190[12]; // @[el2_lib.scala 205:27] - wire _T_200 = _T_187[12] ^ _T_199; // @[el2_lib.scala 205:25] - wire [18:0] _T_211 = _T_200 ? _T_186[31:13] : 19'h0; // @[Mux.scala 27:72] - wire _T_203 = ~_T_187[12]; // @[el2_lib.scala 206:8] - wire _T_205 = _T_203 & _T_190[12]; // @[el2_lib.scala 206:14] - wire [18:0] _T_193 = _T_186[31:13] + 19'h1; // @[el2_lib.scala 202:27] - wire [18:0] _T_212 = _T_205 ? _T_193 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_214 = _T_211 | _T_212; // @[Mux.scala 27:72] - wire _T_209 = _T_187[12] & _T_199; // @[el2_lib.scala 207:13] - wire [18:0] _T_196 = _T_186[31:13] - 19'h1; // @[el2_lib.scala 203:27] - wire [18:0] _T_213 = _T_209 ? _T_196 : 19'h0; // @[Mux.scala 27:72] - wire [18:0] _T_215 = _T_214 | _T_213; // @[Mux.scala 27:72] - wire [31:0] pcout = {_T_215,_T_190[11:0],1'h0}; // @[Cat.scala 29:58] - wire _T_35 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 53:30] - wire neg = aout[31]; // @[el2_exu_alu_ctl.scala 52:34] - wire _T_23 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 48:14] - wire [31:0] bm = io_ap_sub ? _T_6 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] - wire _T_25 = ~bm[31]; // @[el2_exu_alu_ctl.scala 48:29] - wire _T_26 = _T_23 & _T_25; // @[el2_exu_alu_ctl.scala 48:27] - wire _T_28 = _T_26 & neg; // @[el2_exu_alu_ctl.scala 48:37] - wire _T_31 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 48:66] - wire _T_33 = ~neg; // @[el2_exu_alu_ctl.scala 48:78] - wire _T_34 = _T_31 & _T_33; // @[el2_exu_alu_ctl.scala 48:76] - wire ov = _T_28 | _T_34; // @[el2_exu_alu_ctl.scala 48:50] - wire _T_36 = neg ^ ov; // @[el2_exu_alu_ctl.scala 53:51] - wire _T_37 = _T_35 & _T_36; // @[el2_exu_alu_ctl.scala 53:44] - wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 46:18] - wire _T_38 = ~cout; // @[el2_exu_alu_ctl.scala 53:78] - wire _T_39 = io_ap_unsign & _T_38; // @[el2_exu_alu_ctl.scala 53:76] - wire lt = _T_37 | _T_39; // @[el2_exu_alu_ctl.scala 53:58] - wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 85:40] - wire [31:0] _T_228 = {31'h0,slt_one}; // @[Cat.scala 29:58] - wire [31:0] _T_47 = io_csr_ren_in ? io_b_in : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_42 = io_a_in & io_b_in; // @[el2_exu_alu_ctl.scala 59:39] - wire [31:0] _T_48 = io_ap_land ? _T_42 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_51 = _T_47 | _T_48; // @[Mux.scala 27:72] - wire [31:0] _T_44 = io_a_in | io_b_in; // @[el2_exu_alu_ctl.scala 60:39] - wire [31:0] _T_49 = io_ap_lor ? _T_44 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_52 = _T_51 | _T_49; // @[Mux.scala 27:72] - wire [31:0] _T_46 = io_a_in ^ io_b_in; // @[el2_exu_alu_ctl.scala 61:39] - wire [31:0] _T_50 = io_ap_lxor ? _T_46 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] lout = _T_52 | _T_50; // @[Mux.scala 27:72] - wire eq = io_a_in == io_b_in; // @[el2_exu_alu_ctl.scala 50:38] - wire ne = ~eq; // @[el2_exu_alu_ctl.scala 51:29] - wire ge = ~lt; // @[el2_exu_alu_ctl.scala 54:29] - wire _T_236 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 105:40] - wire _T_237 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 105:59] - wire _T_238 = _T_236 | _T_237; // @[el2_exu_alu_ctl.scala 105:46] - wire _T_239 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 105:85] - wire _T_240 = _T_238 | _T_239; // @[el2_exu_alu_ctl.scala 105:72] - wire _T_241 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 105:104] - wire _T_242 = _T_240 | _T_241; // @[el2_exu_alu_ctl.scala 105:91] - wire actual_taken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 105:110] - wire _T_243 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 110:42] - wire _T_244 = ~actual_taken; // @[el2_exu_alu_ctl.scala 110:63] - wire _T_245 = _T_243 & _T_244; // @[el2_exu_alu_ctl.scala 110:61] - wire _T_246 = ~sel_pc; // @[el2_exu_alu_ctl.scala 110:79] - wire _T_247 = _T_245 & _T_246; // @[el2_exu_alu_ctl.scala 110:77] - wire _T_248 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 110:104] - wire _T_249 = _T_248 & actual_taken; // @[el2_exu_alu_ctl.scala 110:123] - wire _T_251 = _T_249 & _T_246; // @[el2_exu_alu_ctl.scala 110:139] - wire _T_258 = io_ap_predict_t & _T_244; // @[el2_exu_alu_ctl.scala 115:45] - wire _T_259 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 115:82] - wire cond_mispredict = _T_258 | _T_259; // @[el2_exu_alu_ctl.scala 115:62] - wire _T_262 = io_pp_in_prett[31:1] != aout[31:1]; // @[el2_exu_alu_ctl.scala 118:68] - wire target_mispredict = io_pp_in_pret & _T_262; // @[el2_exu_alu_ctl.scala 118:44] - wire _T_263 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 120:42] - wire _T_264 = _T_263 | target_mispredict; // @[el2_exu_alu_ctl.scala 120:60] - wire _T_265 = _T_264 & io_valid_in; // @[el2_exu_alu_ctl.scala 120:81] - wire _T_266 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 120:97] - wire _T_267 = _T_265 & _T_266; // @[el2_exu_alu_ctl.scala 120:95] - wire _T_268 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 120:119] - wire _T_278 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:39] - wire _T_280 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 126:63] - wire _T_281 = _T_280 & actual_taken; // @[el2_exu_alu_ctl.scala 126:81] - wire _T_282 = _T_278 | _T_281; // @[el2_exu_alu_ctl.scala 126:60] - wire _T_284 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 127:6] - wire _T_286 = _T_284 & _T_244; // @[el2_exu_alu_ctl.scala 127:24] - wire _T_288 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 127:62] - wire _T_289 = _T_286 | _T_288; // @[el2_exu_alu_ctl.scala 127:42] - wire _T_293 = _T_266 & _T_268; // @[el2_exu_alu_ctl.scala 130:51] - wire _T_294 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 130:90] - assign io_result_ff = _T_1; // @[el2_exu_alu_ctl.scala 37:16] - assign io_flush_upper_out = _T_267 & _T_268; // @[el2_exu_alu_ctl.scala 120:26] - assign io_flush_final_out = _T_267 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 122:26] - assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 112:22] - assign io_pc_ff = _T; // @[el2_exu_alu_ctl.scala 35:12] - assign io_pred_correct_out = _T_247 | _T_251; // @[el2_exu_alu_ctl.scala 110:26] - assign io_predict_p_out_misp = _T_293 & _T_294; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 130:30] - assign io_predict_p_out_ataken = _T_242 | sel_pc; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 131:30] - assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_hist = {_T_282,_T_289}; // @[el2_exu_alu_ctl.scala 129:30 el2_exu_alu_ctl.scala 132:30] - assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 129:30] - assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 129:30] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + reg [30:0] _T_1; // @[el2_lib.scala 514:16] + reg [31:0] _T_3; // @[el2_lib.scala 514:16] + wire [31:0] _T_5 = ~io_b_in; // @[el2_exu_alu_ctl.scala 39:37] + wire [31:0] bm = io_ap_sub ? _T_5 : io_b_in; // @[el2_exu_alu_ctl.scala 39:17] + wire [32:0] _T_8 = {1'h0,io_a_in}; // @[Cat.scala 29:58] + wire [32:0] _T_10 = {1'h0,_T_5}; // @[Cat.scala 29:58] + wire [32:0] _T_12 = _T_8 + _T_10; // @[el2_exu_alu_ctl.scala 42:55] + wire [32:0] _T_13 = {32'h0,io_ap_sub}; // @[Cat.scala 29:58] + wire [32:0] _T_15 = _T_12 + _T_13; // @[el2_exu_alu_ctl.scala 42:80] + wire [32:0] _T_18 = {1'h0,io_b_in}; // @[Cat.scala 29:58] + wire [32:0] _T_20 = _T_8 + _T_18; // @[el2_exu_alu_ctl.scala 42:132] + wire [32:0] _T_23 = _T_20 + _T_13; // @[el2_exu_alu_ctl.scala 42:157] + wire [32:0] aout = io_ap_sub ? _T_15 : _T_23; // @[el2_exu_alu_ctl.scala 42:14] + wire cout = aout[32]; // @[el2_exu_alu_ctl.scala 43:18] + wire _T_26 = ~io_a_in[31]; // @[el2_exu_alu_ctl.scala 45:14] + wire _T_28 = ~bm[31]; // @[el2_exu_alu_ctl.scala 45:29] + wire _T_29 = _T_26 & _T_28; // @[el2_exu_alu_ctl.scala 45:27] + wire _T_31 = _T_29 & aout[31]; // @[el2_exu_alu_ctl.scala 45:37] + wire _T_34 = io_a_in[31] & bm[31]; // @[el2_exu_alu_ctl.scala 45:66] + wire _T_36 = ~aout[31]; // @[el2_exu_alu_ctl.scala 45:78] + wire _T_37 = _T_34 & _T_36; // @[el2_exu_alu_ctl.scala 45:76] + wire ov = _T_31 | _T_37; // @[el2_exu_alu_ctl.scala 45:50] + wire eq = $signed(io_a_in) == $signed(io_b_in); // @[el2_exu_alu_ctl.scala 47:38] + wire ne = ~eq; // @[el2_exu_alu_ctl.scala 48:29] + wire _T_39 = ~io_ap_unsign; // @[el2_exu_alu_ctl.scala 50:30] + wire _T_40 = aout[31] ^ ov; // @[el2_exu_alu_ctl.scala 50:51] + wire _T_41 = _T_39 & _T_40; // @[el2_exu_alu_ctl.scala 50:44] + wire _T_42 = ~cout; // @[el2_exu_alu_ctl.scala 50:78] + wire _T_43 = io_ap_unsign & _T_42; // @[el2_exu_alu_ctl.scala 50:76] + wire lt = _T_41 | _T_43; // @[el2_exu_alu_ctl.scala 50:58] + wire ge = ~lt; // @[el2_exu_alu_ctl.scala 51:29] + wire [31:0] _T_63 = $signed(io_a_in) & $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_66 = $signed(io_a_in) | $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_69 = $signed(io_a_in) ^ $signed(io_b_in); // @[Mux.scala 27:72] + wire [31:0] _T_70 = io_csr_ren_in ? $signed(io_b_in) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_71 = io_ap_land ? $signed(_T_63) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_72 = io_ap_lor ? $signed(_T_66) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_73 = io_ap_lxor ? $signed(_T_69) : $signed(32'sh0); // @[Mux.scala 27:72] + wire [31:0] _T_75 = $signed(_T_70) | $signed(_T_71); // @[Mux.scala 27:72] + wire [31:0] _T_77 = $signed(_T_75) | $signed(_T_72); // @[Mux.scala 27:72] + wire [5:0] _T_84 = {1'h0,io_b_in[4:0]}; // @[Cat.scala 29:58] + wire [5:0] _T_86 = 6'h20 - _T_84; // @[el2_exu_alu_ctl.scala 61:38] + wire [5:0] _T_93 = io_ap_sll ? _T_86 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_94 = io_ap_srl ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_95 = io_ap_sra ? _T_84 : 6'h0; // @[Mux.scala 27:72] + wire [5:0] _T_96 = _T_93 | _T_94; // @[Mux.scala 27:72] + wire [5:0] shift_amount = _T_96 | _T_95; // @[Mux.scala 27:72] + wire [4:0] _T_102 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [4:0] _T_104 = _T_102 & io_b_in[4:0]; // @[el2_exu_alu_ctl.scala 66:61] + wire [62:0] _T_105 = 63'hffffffff << _T_104; // @[el2_exu_alu_ctl.scala 66:39] + wire [9:0] _T_115 = {io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [18:0] _T_124 = {_T_115,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [27:0] _T_133 = {_T_124,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [30:0] _T_136 = {_T_133,io_ap_sra,io_ap_sra,io_ap_sra}; // @[Cat.scala 29:58] + wire [9:0] _T_147 = {io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [18:0] _T_156 = {_T_147,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [27:0] _T_165 = {_T_156,io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_168 = {_T_165,io_a_in[31],io_a_in[31],io_a_in[31]}; // @[Cat.scala 29:58] + wire [30:0] _T_169 = _T_136 & _T_168; // @[el2_exu_alu_ctl.scala 69:44] + wire [9:0] _T_179 = {io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [18:0] _T_188 = {_T_179,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [27:0] _T_197 = {_T_188,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_200 = {_T_197,io_ap_sll,io_ap_sll,io_ap_sll}; // @[Cat.scala 29:58] + wire [30:0] _T_202 = _T_200 & io_a_in[30:0]; // @[el2_exu_alu_ctl.scala 69:90] + wire [30:0] _T_203 = _T_169 | _T_202; // @[el2_exu_alu_ctl.scala 69:68] + wire [62:0] shift_extend = {_T_203,io_a_in}; // @[Cat.scala 29:58] + wire [62:0] shift_long = shift_extend >> shift_amount[4:0]; // @[el2_exu_alu_ctl.scala 72:32] + wire [31:0] shift_mask = _T_105[31:0]; // @[el2_exu_alu_ctl.scala 66:14] + wire [31:0] sout = shift_long[31:0] & shift_mask; // @[el2_exu_alu_ctl.scala 74:34] + wire _T_210 = io_ap_sll | io_ap_srl; // @[el2_exu_alu_ctl.scala 77:41] + wire sel_shift = _T_210 | io_ap_sra; // @[el2_exu_alu_ctl.scala 77:53] + wire _T_211 = io_ap_add | io_ap_sub; // @[el2_exu_alu_ctl.scala 78:41] + wire _T_212 = ~io_ap_slt; // @[el2_exu_alu_ctl.scala 78:56] + wire sel_adder = _T_211 & _T_212; // @[el2_exu_alu_ctl.scala 78:54] + wire _T_213 = io_ap_jal | io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 79:41] + wire _T_214 = _T_213 | io_pp_in_pja; // @[el2_exu_alu_ctl.scala 79:58] + wire sel_pc = _T_214 | io_pp_in_pret; // @[el2_exu_alu_ctl.scala 79:73] + wire slt_one = io_ap_slt & lt; // @[el2_exu_alu_ctl.scala 82:40] + wire [31:0] _T_217 = {io_pc_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_218 = {io_brimm_in,1'h0}; // @[Cat.scala 29:58] + wire [12:0] _T_221 = _T_217[12:1] + _T_218[12:1]; // @[el2_lib.scala 208:31] + wire [18:0] _T_224 = _T_217[31:13] + 19'h1; // @[el2_lib.scala 209:27] + wire [18:0] _T_227 = _T_217[31:13] - 19'h1; // @[el2_lib.scala 210:27] + wire _T_230 = ~_T_221[12]; // @[el2_lib.scala 212:28] + wire _T_231 = _T_218[12] ^ _T_230; // @[el2_lib.scala 212:26] + wire _T_234 = ~_T_218[12]; // @[el2_lib.scala 213:8] + wire _T_236 = _T_234 & _T_221[12]; // @[el2_lib.scala 213:14] + wire _T_240 = _T_218[12] & _T_230; // @[el2_lib.scala 214:14] + wire [18:0] _T_242 = _T_231 ? _T_217[31:13] : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_243 = _T_236 ? _T_224 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_244 = _T_240 ? _T_227 : 19'h0; // @[Mux.scala 27:72] + wire [18:0] _T_245 = _T_242 | _T_243; // @[Mux.scala 27:72] + wire [18:0] _T_246 = _T_245 | _T_244; // @[Mux.scala 27:72] + wire [31:0] pcout = {_T_246,_T_221[11:0],1'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_250 = $signed(_T_77) | $signed(_T_73); // @[el2_exu_alu_ctl.scala 88:24] + wire [31:0] _T_251 = {31'h0,slt_one}; // @[Cat.scala 29:58] + wire [31:0] _T_252 = _T_250 | _T_251; // @[el2_exu_alu_ctl.scala 88:31] + wire [31:0] _T_259 = io_ap_csr_imm ? $signed(io_b_in) : $signed(io_a_in); // @[el2_exu_alu_ctl.scala 92:51] + wire [31:0] _T_260 = sel_shift ? sout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_261 = sel_adder ? aout[31:0] : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_262 = sel_pc ? pcout : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_263 = io_ap_csr_write ? _T_259 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_264 = _T_260 | _T_261; // @[Mux.scala 27:72] + wire [31:0] _T_265 = _T_264 | _T_262; // @[Mux.scala 27:72] + wire [31:0] _T_266 = _T_265 | _T_263; // @[Mux.scala 27:72] + wire _T_271 = io_ap_beq & eq; // @[el2_exu_alu_ctl.scala 101:40] + wire _T_272 = io_ap_bne & ne; // @[el2_exu_alu_ctl.scala 101:59] + wire _T_273 = _T_271 | _T_272; // @[el2_exu_alu_ctl.scala 101:46] + wire _T_274 = io_ap_blt & lt; // @[el2_exu_alu_ctl.scala 101:85] + wire _T_275 = _T_273 | _T_274; // @[el2_exu_alu_ctl.scala 101:72] + wire _T_276 = io_ap_bge & ge; // @[el2_exu_alu_ctl.scala 101:104] + wire _T_277 = _T_275 | _T_276; // @[el2_exu_alu_ctl.scala 101:91] + wire actual_taken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 101:110] + wire _T_278 = io_valid_in & io_ap_predict_nt; // @[el2_exu_alu_ctl.scala 106:42] + wire _T_279 = ~actual_taken; // @[el2_exu_alu_ctl.scala 106:63] + wire _T_280 = _T_278 & _T_279; // @[el2_exu_alu_ctl.scala 106:61] + wire _T_281 = ~sel_pc; // @[el2_exu_alu_ctl.scala 106:79] + wire _T_282 = _T_280 & _T_281; // @[el2_exu_alu_ctl.scala 106:77] + wire _T_283 = io_valid_in & io_ap_predict_t; // @[el2_exu_alu_ctl.scala 106:104] + wire _T_284 = _T_283 & actual_taken; // @[el2_exu_alu_ctl.scala 106:123] + wire _T_286 = _T_284 & _T_281; // @[el2_exu_alu_ctl.scala 106:139] + wire _T_293 = io_ap_predict_t & _T_279; // @[el2_exu_alu_ctl.scala 111:45] + wire _T_294 = io_ap_predict_nt & actual_taken; // @[el2_exu_alu_ctl.scala 111:82] + wire cond_mispredict = _T_293 | _T_294; // @[el2_exu_alu_ctl.scala 111:62] + wire _T_296 = io_pp_in_prett != aout[31:1]; // @[el2_exu_alu_ctl.scala 114:62] + wire target_mispredict = io_pp_in_pret & _T_296; // @[el2_exu_alu_ctl.scala 114:44] + wire _T_297 = io_ap_jal | cond_mispredict; // @[el2_exu_alu_ctl.scala 116:42] + wire _T_298 = _T_297 | target_mispredict; // @[el2_exu_alu_ctl.scala 116:60] + wire _T_299 = _T_298 & io_valid_in; // @[el2_exu_alu_ctl.scala 116:81] + wire _T_300 = ~io_flush_upper_x; // @[el2_exu_alu_ctl.scala 116:97] + wire _T_301 = _T_299 & _T_300; // @[el2_exu_alu_ctl.scala 116:95] + wire _T_302 = ~io_flush_lower_r; // @[el2_exu_alu_ctl.scala 116:119] + wire _T_312 = io_pp_in_hist[1] & io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:39] + wire _T_314 = ~io_pp_in_hist[0]; // @[el2_exu_alu_ctl.scala 122:63] + wire _T_315 = _T_314 & actual_taken; // @[el2_exu_alu_ctl.scala 122:81] + wire _T_316 = _T_312 | _T_315; // @[el2_exu_alu_ctl.scala 122:60] + wire _T_318 = ~io_pp_in_hist[1]; // @[el2_exu_alu_ctl.scala 123:6] + wire _T_320 = _T_318 & _T_279; // @[el2_exu_alu_ctl.scala 123:24] + wire _T_322 = io_pp_in_hist[1] & actual_taken; // @[el2_exu_alu_ctl.scala 123:62] + wire _T_323 = _T_320 | _T_322; // @[el2_exu_alu_ctl.scala 123:42] + wire _T_327 = _T_300 & _T_302; // @[el2_exu_alu_ctl.scala 126:51] + wire _T_328 = cond_mispredict | target_mispredict; // @[el2_exu_alu_ctl.scala 126:90] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_result_ff = _T_3; // @[el2_exu_alu_ctl.scala 37:16] + assign io_flush_upper_out = _T_301 & _T_302; // @[el2_exu_alu_ctl.scala 116:26] + assign io_flush_final_out = _T_301 | io_flush_lower_r; // @[el2_exu_alu_ctl.scala 118:26] + assign io_flush_path_out = sel_pc ? aout[31:1] : pcout[31:1]; // @[el2_exu_alu_ctl.scala 108:22] + assign io_pc_ff = _T_1; // @[el2_exu_alu_ctl.scala 35:12] + assign io_pred_correct_out = _T_282 | _T_286; // @[el2_exu_alu_ctl.scala 106:26] + assign io_predict_p_out_misp = _T_327 & _T_328; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 126:30] + assign io_predict_p_out_ataken = _T_277 | sel_pc; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 127:30] + assign io_predict_p_out_boffset = io_pp_in_boffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pc4 = io_pp_in_pc4; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_hist = {_T_316,_T_323}; // @[el2_exu_alu_ctl.scala 125:30 el2_exu_alu_ctl.scala 128:30] + assign io_predict_p_out_toffset = io_pp_in_toffset; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_valid = io_pp_in_valid; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_error = io_pp_in_br_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_br_start_error = io_pp_in_br_start_error; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_prett = io_pp_in_prett; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pcall = io_pp_in_pcall; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pret = io_pp_in_pret; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_pja = io_pp_in_pja; // @[el2_exu_alu_ctl.scala 125:30] + assign io_predict_p_out_way = io_pp_in_way; // @[el2_exu_alu_ctl.scala 125:30] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_enable; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -260,42 +314,34 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T = _RAND_0[30:0]; + _T_1 = _RAND_0[30:0]; _RAND_1 = {1{`RANDOM}}; - _T_1 = _RAND_1[31:0]; + _T_3 = _RAND_1[31:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + _T_1 = 31'h0; + end + if (reset) begin + _T_3 = 32'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge clock) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin - _T <= 31'h0; - end else if (io_enable) begin - _T <= io_pc_in; + _T_1 <= 31'h0; + end else begin + _T_1 <= io_pc_in; end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin - _T_1 <= 32'h0; - end else if (io_enable) begin - if (sel_shift) begin - _T_1 <= sout; - end else if (sel_adder) begin - _T_1 <= aout[31:0]; - end else if (sel_pc) begin - _T_1 <= pcout; - end else if (io_ap_csr_write) begin - if (io_ap_csr_imm) begin - _T_1 <= io_b_in; - end else begin - _T_1 <= io_a_in; - end - end else if (slt_one) begin - _T_1 <= _T_228; - end else begin - _T_1 <= lout; - end + _T_3 <= 32'h0; + end else begin + _T_3 <= _T_252 | _T_266; end end endmodule diff --git a/el2_lsu.anno.json b/el2_lsu.anno.json index ac7b25f8..83b08b0c 100644 --- a/el2_lsu.anno.json +++ b/el2_lsu.anno.json @@ -20,6 +20,53 @@ "~el2_lsu|el2_lsu>io_dccm_rd_data_lo" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_picm_rdaddr", + "sources":[ + "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", + "~el2_lsu|el2_lsu>io_dma_mem_addr", + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m", + "sources":[ + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2", + "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_dccm_wren", @@ -28,9 +75,9 @@ "~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -48,7 +95,27 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi", + "sink":"~el2_lsu|el2_lsu>io_lsu_load_stall_any", + "sources":[ + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", + "~el2_lsu|el2_lsu>io_dma_mem_addr", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_lsu_p_dword", + "~el2_lsu|el2_lsu>io_lsu_p_half", + "~el2_lsu|el2_lsu>io_lsu_p_word", + "~el2_lsu|el2_lsu>io_dma_mem_sz", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi", "sources":[ "~el2_lsu|el2_lsu>io_dma_dccm_req", "~el2_lsu|el2_lsu>io_dma_mem_write", @@ -61,9 +128,11 @@ "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", "~el2_lsu|el2_lsu>io_dma_mem_sz", + "~el2_lsu|el2_lsu>io_dma_mem_wdata", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, @@ -73,9 +142,9 @@ "sources":[ "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -99,9 +168,9 @@ "sources":[ "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -118,13 +187,6 @@ "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_dccm_ready", - "sources":[ - "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_picm_wren", @@ -134,48 +196,46 @@ "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", "~el2_lsu|el2_lsu>io_dma_mem_sz", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", - "~el2_lsu|el2_lsu>io_dccm_rd_data_lo" + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_lsu_trigger_match_m", + "sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi", "sources":[ - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_store", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_load", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_select", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_0_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_tdata2", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_1_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_3_match_", - "~el2_lsu|el2_lsu>io_trigger_pkt_any_2_match_", + "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", + "~el2_lsu|el2_lsu>io_dma_mem_addr", + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_dword", + "~el2_lsu|el2_lsu>io_lsu_p_half", + "~el2_lsu|el2_lsu>io_lsu_p_word", + "~el2_lsu|el2_lsu>io_dma_mem_sz", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_dccm_ready", + "sources":[ + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_picm_wraddr", @@ -184,9 +244,29 @@ "~el2_lsu|el2_lsu>io_dma_dccm_req", "~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_dword", + "~el2_lsu|el2_lsu>io_lsu_p_half", + "~el2_lsu|el2_lsu>io_lsu_p_word", + "~el2_lsu|el2_lsu>io_dma_mem_sz", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any", + "sources":[ + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", + "~el2_lsu|el2_lsu>io_dma_mem_addr", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -194,9 +274,19 @@ "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_trxn", + "sources":[ + "~el2_lsu|el2_lsu>io_lsu_axi_arready", + "~el2_lsu|el2_lsu>io_lsu_axi_awready", + "~el2_lsu|el2_lsu>io_lsu_axi_wready" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_dccm_dma_ecc_error", @@ -215,37 +305,39 @@ "~el2_lsu|el2_lsu>io_dccm_rd_data_lo" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_busy", + "sources":[ + "~el2_lsu|el2_lsu>io_lsu_axi_arready", + "~el2_lsu|el2_lsu>io_lsu_axi_awready", + "~el2_lsu|el2_lsu>io_lsu_axi_wready" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_lo", "sources":[ "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_dccm_rd_addr_hi", + "sink":"~el2_lsu|el2_lsu>io_lsu_result_m", "sources":[ - "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", - "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", - "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", - "~el2_lsu|el2_lsu>io_lsu_p_dword", - "~el2_lsu|el2_lsu>io_lsu_p_half", - "~el2_lsu|el2_lsu>io_lsu_p_word", - "~el2_lsu|el2_lsu>io_dma_mem_sz", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, @@ -258,9 +350,9 @@ "~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -276,15 +368,37 @@ "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo", + "sources":[ + "~el2_lsu|el2_lsu>io_dma_dccm_req", + "~el2_lsu|el2_lsu>io_dma_mem_write", + "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", + "~el2_lsu|el2_lsu>io_dma_mem_addr", + "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", + "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_lsu_p_dword", + "~el2_lsu|el2_lsu>io_lsu_p_half", + "~el2_lsu|el2_lsu>io_lsu_p_word", + "~el2_lsu|el2_lsu>io_dma_mem_sz", + "~el2_lsu|el2_lsu>io_picm_rd_data", + "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", + "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu|el2_lsu>io_picm_mken", "sources":[ "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -303,38 +417,9 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_lo", + "sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_valid_m", "sources":[ - "~el2_lsu|el2_lsu>io_dma_dccm_req", - "~el2_lsu|el2_lsu>io_dma_mem_write", - "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", - "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", - "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", - "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu|el2_lsu>io_lsu_p_dword", - "~el2_lsu|el2_lsu>io_lsu_p_half", - "~el2_lsu|el2_lsu>io_lsu_p_word", - "~el2_lsu|el2_lsu>io_dma_mem_sz", - "~el2_lsu|el2_lsu>io_picm_rd_data", - "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", - "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", - "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" - ] - }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_picm_rdaddr", - "sources":[ - "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", - "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", - "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", - "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu|el2_lsu>io_picm_rd_data", - "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", - "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", - "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r" ] }, { @@ -345,9 +430,9 @@ "~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", @@ -356,47 +441,43 @@ "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_lsu_store_stall_any", + "sink":"~el2_lsu|el2_lsu>io_lsu_pmu_bus_misaligned", "sources":[ - "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", - "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", - "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", - "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", - "~el2_lsu|el2_lsu>io_lsu_p_dword", - "~el2_lsu|el2_lsu>io_lsu_p_half", - "~el2_lsu|el2_lsu>io_lsu_p_word", - "~el2_lsu|el2_lsu>io_dma_mem_sz", - "~el2_lsu|el2_lsu>io_picm_rd_data", - "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", - "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu|el2_lsu>io_dccm_wr_data_hi", + "sink":"~el2_lsu|el2_lsu>io_lsu_nonblock_load_inv_r", + "sources":[ + "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu|el2_lsu>io_dccm_wr_addr_hi", "sources":[ "~el2_lsu|el2_lsu>io_dma_dccm_req", "~el2_lsu|el2_lsu>io_dma_mem_write", "~el2_lsu|el2_lsu>io_exu_lsu_rs1_d", "~el2_lsu|el2_lsu>io_dma_mem_addr", - "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_dec_lsu_valid_raw_d", "~el2_lsu|el2_lsu>io_lsu_p_load_ldst_bypass_d", + "~el2_lsu|el2_lsu>io_dec_lsu_offset_d", "~el2_lsu|el2_lsu>io_lsu_p_dword", "~el2_lsu|el2_lsu>io_lsu_p_half", "~el2_lsu|el2_lsu>io_lsu_p_word", "~el2_lsu|el2_lsu>io_dma_mem_sz", - "~el2_lsu|el2_lsu>io_dma_mem_wdata", "~el2_lsu|el2_lsu>io_picm_rd_data", "~el2_lsu|el2_lsu>io_dccm_rd_data_hi", "~el2_lsu|el2_lsu>io_dccm_rd_data_lo", + "~el2_lsu|el2_lsu>io_dec_tlu_flush_lower_r", "~el2_lsu|el2_lsu>io_dec_tlu_i0_kill_writeb_r" ] }, @@ -406,8 +487,8 @@ }, { "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"el2_lsu.TEC_RV_ICG", - "resourceId":"/vsrc/TEC_RV_ICG.v" + "target":"el2_lsu.gated_latch", + "resourceId":"/vsrc/gated_latch.v" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/el2_lsu.fir b/el2_lsu.fir index 6356145c..fefbfa99 100644 --- a/el2_lsu.fir +++ b/el2_lsu.fir @@ -1,1030 +1,793 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu : - module rvlsadder : - input clock : Clock - input reset : Reset - output io : {flip rs1 : UInt<32>, flip offset : UInt<12>, dout : UInt<32>} - - node _T = bits(io.rs1, 11, 0) @[beh_lib.scala 51:32] - node _T_1 = cat(UInt<1>("h00"), _T) @[Cat.scala 29:58] - node _T_2 = bits(io.offset, 11, 0) @[beh_lib.scala 51:64] - node _T_3 = cat(UInt<1>("h00"), _T_2) @[Cat.scala 29:58] - node _T_4 = add(_T_1, _T_3) @[beh_lib.scala 51:40] - node w1 = tail(_T_4, 1) @[beh_lib.scala 51:40] - node _T_5 = bits(io.offset, 11, 11) @[beh_lib.scala 53:42] - node _T_6 = bits(w1, 12, 12) @[beh_lib.scala 53:51] - node _T_7 = xor(_T_5, _T_6) @[beh_lib.scala 53:47] - node _T_8 = not(_T_7) @[beh_lib.scala 53:31] - node _T_9 = bits(_T_8, 0, 0) @[Bitwise.scala 72:15] - node _T_10 = mux(_T_9, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_11 = bits(io.rs1, 31, 12) @[beh_lib.scala 53:67] - node _T_12 = and(_T_10, _T_11) @[beh_lib.scala 53:59] - node _T_13 = bits(io.offset, 11, 11) @[beh_lib.scala 54:26] - node _T_14 = not(_T_13) @[beh_lib.scala 54:16] - node _T_15 = bits(w1, 12, 12) @[beh_lib.scala 54:35] - node _T_16 = and(_T_14, _T_15) @[beh_lib.scala 54:31] - node _T_17 = bits(_T_16, 0, 0) @[Bitwise.scala 72:15] - node _T_18 = mux(_T_17, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_19 = bits(io.rs1, 31, 12) @[beh_lib.scala 54:51] - node _T_20 = add(_T_19, UInt<1>("h01")) @[beh_lib.scala 54:58] - node _T_21 = tail(_T_20, 1) @[beh_lib.scala 54:58] - node _T_22 = and(_T_18, _T_21) @[beh_lib.scala 54:42] - node _T_23 = or(_T_12, _T_22) @[beh_lib.scala 53:76] - node _T_24 = bits(io.offset, 11, 11) @[beh_lib.scala 55:25] - node _T_25 = bits(w1, 12, 12) @[beh_lib.scala 55:35] - node _T_26 = not(_T_25) @[beh_lib.scala 55:32] - node _T_27 = and(_T_24, _T_26) @[beh_lib.scala 55:30] - node _T_28 = bits(_T_27, 0, 0) @[Bitwise.scala 72:15] - node _T_29 = mux(_T_28, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] - node _T_30 = bits(io.rs1, 31, 12) @[beh_lib.scala 55:51] - node _T_31 = sub(_T_30, UInt<1>("h01")) @[beh_lib.scala 55:58] - node _T_32 = tail(_T_31, 1) @[beh_lib.scala 55:58] - node _T_33 = and(_T_29, _T_32) @[beh_lib.scala 55:42] - node dout_upper = or(_T_23, _T_33) @[beh_lib.scala 54:65] - node _T_34 = bits(w1, 11, 0) @[beh_lib.scala 57:31] - node _T_35 = cat(dout_upper, _T_34) @[Cat.scala 29:58] - io.dout <= _T_35 @[beh_lib.scala 57:11] - - module rvrangecheck : - input clock : Clock - input reset : Reset - output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>} - - node _T = bits(io.addr, 31, 28) @[beh_lib.scala 114:28] - node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 114:50] - io.in_region <= _T_1 @[beh_lib.scala 114:17] - node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 118:28] - node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 118:43] - io.in_range <= _T_3 @[beh_lib.scala 118:17] - - module rvrangecheck_1 : - input clock : Clock - input reset : Reset - output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>} - - node _T = bits(io.addr, 31, 28) @[beh_lib.scala 114:28] - node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 114:50] - io.in_region <= _T_1 @[beh_lib.scala 114:17] - node _T_2 = bits(io.addr, 31, 16) @[beh_lib.scala 118:28] - node _T_3 = eq(_T_2, UInt<16>("h0f004")) @[beh_lib.scala 118:43] - io.in_range <= _T_3 @[beh_lib.scala 118:17] - - module rvrangecheck_2 : - input clock : Clock - input reset : Reset - output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>} - - node _T = bits(io.addr, 31, 28) @[beh_lib.scala 114:28] - node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 114:50] - io.in_region <= _T_1 @[beh_lib.scala 114:17] - node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 118:28] - node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 118:43] - io.in_range <= _T_3 @[beh_lib.scala 118:17] - - module rvrangecheck_3 : - input clock : Clock - input reset : Reset - output io : {flip addr : UInt<32>, in_range : UInt<1>, in_region : UInt<1>} - - node _T = bits(io.addr, 31, 28) @[beh_lib.scala 114:28] - node _T_1 = eq(_T, UInt<4>("h0f")) @[beh_lib.scala 114:50] - io.in_region <= _T_1 @[beh_lib.scala 114:17] - node _T_2 = bits(io.addr, 31, 15) @[beh_lib.scala 118:28] - node _T_3 = eq(_T_2, UInt<17>("h01e018")) @[beh_lib.scala 118:43] - io.in_range <= _T_3 @[beh_lib.scala 118:17] - module el2_lsu_addrcheck : input clock : Clock input reset : AsyncReset output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>} - wire start_addr_in_dccm_d : UInt<1> - start_addr_in_dccm_d <= UInt<1>("h00") - wire start_addr_in_dccm_region_d : UInt<1> - start_addr_in_dccm_region_d <= UInt<1>("h00") - wire end_addr_in_dccm_d : UInt<1> - end_addr_in_dccm_d <= UInt<1>("h00") - wire end_addr_in_dccm_region_d : UInt<1> - end_addr_in_dccm_region_d <= UInt<1>("h00") - inst rvrangecheck of rvrangecheck @[el2_lsu_addrcheck.scala 45:44] - rvrangecheck.clock <= clock - rvrangecheck.reset <= reset - rvrangecheck.io.addr <= io.start_addr_d @[el2_lsu_addrcheck.scala 46:41] - start_addr_in_dccm_d <= rvrangecheck.io.in_range @[el2_lsu_addrcheck.scala 47:41] - start_addr_in_dccm_region_d <= rvrangecheck.io.in_region @[el2_lsu_addrcheck.scala 48:41] - inst rvrangecheck_1 of rvrangecheck_1 @[el2_lsu_addrcheck.scala 51:44] - rvrangecheck_1.clock <= clock - rvrangecheck_1.reset <= reset - rvrangecheck_1.io.addr <= io.end_addr_d @[el2_lsu_addrcheck.scala 52:41] - end_addr_in_dccm_d <= rvrangecheck_1.io.in_range @[el2_lsu_addrcheck.scala 53:41] - end_addr_in_dccm_region_d <= rvrangecheck_1.io.in_region @[el2_lsu_addrcheck.scala 54:41] + node _T = bits(io.start_addr_d, 31, 28) @[el2_lib.scala 496:27] + node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire start_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26] + node _T_1 = bits(io.start_addr_d, 31, 16) @[el2_lib.scala 501:24] + node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[el2_lib.scala 501:39] + start_addr_in_dccm_d <= _T_2 @[el2_lib.scala 501:16] + node _T_3 = bits(io.end_addr_d, 31, 28) @[el2_lib.scala 496:27] + node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire end_addr_in_dccm_d : UInt<1> @[el2_lib.scala 497:26] + node _T_4 = bits(io.end_addr_d, 31, 16) @[el2_lib.scala 501:24] + node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[el2_lib.scala 501:39] + end_addr_in_dccm_d <= _T_5 @[el2_lib.scala 501:16] wire addr_in_iccm : UInt<1> addr_in_iccm <= UInt<1>("h00") - node _T = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 65:37] - node _T_1 = eq(_T, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 65:45] - addr_in_iccm <= _T_1 @[el2_lsu_addrcheck.scala 65:18] - inst start_addr_pic_rangecheck of rvrangecheck_2 @[el2_lsu_addrcheck.scala 74:41] - start_addr_pic_rangecheck.clock <= clock - start_addr_pic_rangecheck.reset <= reset - node _T_2 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 75:55] - start_addr_pic_rangecheck.io.addr <= _T_2 @[el2_lsu_addrcheck.scala 75:37] - inst end_addr_pic_rangecheck of rvrangecheck_3 @[el2_lsu_addrcheck.scala 80:39] - end_addr_pic_rangecheck.clock <= clock - end_addr_pic_rangecheck.reset <= reset - node _T_3 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:51] - end_addr_pic_rangecheck.io.addr <= _T_3 @[el2_lsu_addrcheck.scala 81:35] - node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 85:60] - node _T_4 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:48] - node _T_5 = eq(_T_4, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:54] - node _T_6 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 86:92] - node _T_7 = eq(_T_6, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 86:98] - node base_reg_dccm_or_pic = or(_T_5, _T_7) @[el2_lsu_addrcheck.scala 86:74] - node _T_8 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 87:57] - io.addr_in_dccm_d <= _T_8 @[el2_lsu_addrcheck.scala 87:32] - node _T_9 = and(start_addr_pic_rangecheck.io.in_range, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 88:56] - io.addr_in_pic_d <= _T_9 @[el2_lsu_addrcheck.scala 88:32] - node _T_10 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 90:63] - node _T_11 = not(_T_10) @[el2_lsu_addrcheck.scala 90:33] - io.addr_external_d <= _T_11 @[el2_lsu_addrcheck.scala 90:30] - node _T_12 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 91:51] - node csr_idx = cat(_T_12, UInt<1>("h01")) @[Cat.scala 29:58] - node _T_13 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 92:50] - node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_addrcheck.scala 92:50] - node _T_15 = or(start_addr_in_dccm_region_d, start_addr_pic_rangecheck.io.in_region) @[el2_lsu_addrcheck.scala 92:92] - node _T_16 = or(_T_15, addr_in_iccm) @[el2_lsu_addrcheck.scala 92:121] - node _T_17 = not(_T_16) @[el2_lsu_addrcheck.scala 92:62] - node _T_18 = and(_T_14, _T_17) @[el2_lsu_addrcheck.scala 92:60] - node _T_19 = and(_T_18, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 92:137] - node _T_20 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 92:180] - node is_sideeffects_d = and(_T_19, _T_20) @[el2_lsu_addrcheck.scala 92:158] - node _T_21 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 93:69] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:75] - node _T_23 = and(io.lsu_pkt_d.word, _T_22) @[el2_lsu_addrcheck.scala 93:51] - node _T_24 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 93:124] - node _T_25 = eq(_T_24, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:128] - node _T_26 = and(io.lsu_pkt_d.half, _T_25) @[el2_lsu_addrcheck.scala 93:106] - node _T_27 = or(_T_23, _T_26) @[el2_lsu_addrcheck.scala 93:85] - node is_aligned_d = or(_T_27, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 93:138] - node _T_28 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_29 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] - node _T_30 = cat(_T_29, _T_28) @[Cat.scala 29:58] - node _T_31 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] - node _T_32 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] - node _T_33 = cat(_T_32, _T_31) @[Cat.scala 29:58] - node _T_34 = cat(_T_33, _T_30) @[Cat.scala 29:58] - node _T_35 = orr(_T_34) @[el2_lsu_addrcheck.scala 97:99] - node _T_36 = not(_T_35) @[el2_lsu_addrcheck.scala 96:33] - node _T_37 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 98:50] - node _T_38 = or(_T_37, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:57] - node _T_39 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 98:108] - node _T_40 = eq(_T_38, _T_39) @[el2_lsu_addrcheck.scala 98:82] - node _T_41 = and(UInt<1>("h01"), _T_40) @[el2_lsu_addrcheck.scala 98:31] - node _T_42 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 99:50] - node _T_43 = or(_T_42, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:57] - node _T_44 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 99:108] - node _T_45 = eq(_T_43, _T_44) @[el2_lsu_addrcheck.scala 99:82] - node _T_46 = and(UInt<1>("h01"), _T_45) @[el2_lsu_addrcheck.scala 99:31] - node _T_47 = or(_T_41, _T_46) @[el2_lsu_addrcheck.scala 98:133] - node _T_48 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 100:50] - node _T_49 = or(_T_48, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:57] - node _T_50 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 100:108] - node _T_51 = eq(_T_49, _T_50) @[el2_lsu_addrcheck.scala 100:82] - node _T_52 = and(UInt<1>("h01"), _T_51) @[el2_lsu_addrcheck.scala 100:31] - node _T_53 = or(_T_47, _T_52) @[el2_lsu_addrcheck.scala 99:133] - node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 101:50] - node _T_55 = or(_T_54, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:57] - node _T_56 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 101:108] - node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 101:82] - node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 101:31] - node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 100:133] - node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 102:50] - node _T_61 = or(_T_60, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:57] - node _T_62 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 102:108] - node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 102:82] - node _T_64 = and(UInt<1>("h00"), _T_63) @[el2_lsu_addrcheck.scala 102:31] - node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 101:133] - node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 103:50] - node _T_67 = or(_T_66, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:57] - node _T_68 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 103:108] - node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 103:82] - node _T_70 = and(UInt<1>("h00"), _T_69) @[el2_lsu_addrcheck.scala 103:31] - node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 102:133] - node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 104:50] - node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:57] - node _T_74 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 104:108] - node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 104:82] - node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 104:31] - node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 103:133] - node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 105:50] - node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:57] - node _T_80 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 105:108] - node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 105:82] - node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 105:31] - node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 104:133] - node _T_84 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 107:49] - node _T_85 = or(_T_84, UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:58] - node _T_86 = or(UInt<32>("h00"), UInt<32>("h07fffffff")) @[el2_lsu_addrcheck.scala 107:109] - node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 107:83] - node _T_88 = and(UInt<1>("h01"), _T_87) @[el2_lsu_addrcheck.scala 107:32] - node _T_89 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 108:50] - node _T_90 = or(_T_89, UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:59] - node _T_91 = or(UInt<32>("h0c0000000"), UInt<32>("h03fffffff")) @[el2_lsu_addrcheck.scala 108:110] - node _T_92 = eq(_T_90, _T_91) @[el2_lsu_addrcheck.scala 108:84] - node _T_93 = and(UInt<1>("h01"), _T_92) @[el2_lsu_addrcheck.scala 108:33] - node _T_94 = or(_T_88, _T_93) @[el2_lsu_addrcheck.scala 107:134] - node _T_95 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 109:50] - node _T_96 = or(_T_95, UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:59] - node _T_97 = or(UInt<32>("h0a0000000"), UInt<32>("h01fffffff")) @[el2_lsu_addrcheck.scala 109:110] - node _T_98 = eq(_T_96, _T_97) @[el2_lsu_addrcheck.scala 109:84] - node _T_99 = and(UInt<1>("h01"), _T_98) @[el2_lsu_addrcheck.scala 109:33] - node _T_100 = or(_T_94, _T_99) @[el2_lsu_addrcheck.scala 108:135] - node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 110:50] - node _T_102 = or(_T_101, UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:59] - node _T_103 = or(UInt<32>("h080000000"), UInt<32>("h0fffffff")) @[el2_lsu_addrcheck.scala 110:110] - node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 110:84] - node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 110:33] - node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 109:135] - node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 111:50] - node _T_108 = or(_T_107, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:59] - node _T_109 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 111:110] - node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 111:84] - node _T_111 = and(UInt<1>("h00"), _T_110) @[el2_lsu_addrcheck.scala 111:33] - node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 110:135] - node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 112:50] - node _T_114 = or(_T_113, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:59] - node _T_115 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 112:110] - node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 112:84] - node _T_117 = and(UInt<1>("h00"), _T_116) @[el2_lsu_addrcheck.scala 112:33] - node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 111:135] - node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 113:50] - node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:59] - node _T_121 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 113:110] - node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 113:84] - node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 113:33] - node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 112:135] - node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 114:50] - node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:59] - node _T_127 = or(UInt<32>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 114:110] - node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 114:84] - node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 114:33] - node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 113:135] - node _T_131 = and(_T_83, _T_130) @[el2_lsu_addrcheck.scala 106:7] - node non_dccm_access_ok = or(_T_36, _T_131) @[el2_lsu_addrcheck.scala 97:104] - node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 116:57] - node _T_132 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 117:70] - node _T_133 = neq(_T_132, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 117:76] - node _T_134 = not(io.lsu_pkt_d.word) @[el2_lsu_addrcheck.scala 117:92] - node _T_135 = or(_T_133, _T_134) @[el2_lsu_addrcheck.scala 117:90] - node picm_access_fault_d = and(io.addr_in_pic_d, _T_135) @[el2_lsu_addrcheck.scala 117:51] + node _T_6 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 42:37] + node _T_7 = eq(_T_6, UInt<4>("h0e")) @[el2_lsu_addrcheck.scala 42:45] + addr_in_iccm <= _T_7 @[el2_lsu_addrcheck.scala 42:18] + node _T_8 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 50:89] + node _T_9 = bits(_T_8, 31, 28) @[el2_lib.scala 496:27] + node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire start_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26] + node _T_10 = bits(_T_8, 31, 15) @[el2_lib.scala 501:24] + node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[el2_lib.scala 501:39] + start_addr_in_pic_d <= _T_11 @[el2_lib.scala 501:16] + node _T_12 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 52:83] + node _T_13 = bits(_T_12, 31, 28) @[el2_lib.scala 496:27] + node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[el2_lib.scala 496:49] + wire end_addr_in_pic_d : UInt<1> @[el2_lib.scala 497:26] + node _T_14 = bits(_T_12, 31, 15) @[el2_lib.scala 501:24] + node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[el2_lib.scala 501:39] + end_addr_in_pic_d <= _T_15 @[el2_lib.scala 501:16] + node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 54:60] + node _T_16 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:48] + node _T_17 = eq(_T_16, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:54] + node _T_18 = bits(io.rs1_region_d, 3, 0) @[el2_lsu_addrcheck.scala 55:91] + node _T_19 = eq(_T_18, UInt<4>("h0f")) @[el2_lsu_addrcheck.scala 55:97] + node base_reg_dccm_or_pic = or(_T_17, _T_19) @[el2_lsu_addrcheck.scala 55:73] + node _T_20 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 56:57] + io.addr_in_dccm_d <= _T_20 @[el2_lsu_addrcheck.scala 56:32] + node _T_21 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 57:56] + io.addr_in_pic_d <= _T_21 @[el2_lsu_addrcheck.scala 57:32] + node _T_22 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 59:63] + node _T_23 = not(_T_22) @[el2_lsu_addrcheck.scala 59:33] + io.addr_external_d <= _T_23 @[el2_lsu_addrcheck.scala 59:30] + node _T_24 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 60:51] + node csr_idx = cat(_T_24, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_25 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[el2_lsu_addrcheck.scala 61:50] + node _T_26 = bits(_T_25, 0, 0) @[el2_lsu_addrcheck.scala 61:50] + node _T_27 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[el2_lsu_addrcheck.scala 61:92] + node _T_28 = or(_T_27, addr_in_iccm) @[el2_lsu_addrcheck.scala 61:121] + node _T_29 = eq(_T_28, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 61:62] + node _T_30 = and(_T_26, _T_29) @[el2_lsu_addrcheck.scala 61:60] + node _T_31 = and(_T_30, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 61:137] + node _T_32 = or(io.lsu_pkt_d.store, io.lsu_pkt_d.load) @[el2_lsu_addrcheck.scala 61:180] + node is_sideeffects_d = and(_T_31, _T_32) @[el2_lsu_addrcheck.scala 61:158] + node _T_33 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 62:69] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:75] + node _T_35 = and(io.lsu_pkt_d.word, _T_34) @[el2_lsu_addrcheck.scala 62:51] + node _T_36 = bits(io.start_addr_d, 0, 0) @[el2_lsu_addrcheck.scala 62:124] + node _T_37 = eq(_T_36, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 62:128] + node _T_38 = and(io.lsu_pkt_d.half, _T_37) @[el2_lsu_addrcheck.scala 62:106] + node _T_39 = or(_T_35, _T_38) @[el2_lsu_addrcheck.scala 62:85] + node is_aligned_d = or(_T_39, io.lsu_pkt_d.by) @[el2_lsu_addrcheck.scala 62:138] + node _T_40 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] + node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58] + node _T_43 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] + node _T_45 = cat(_T_44, _T_43) @[Cat.scala 29:58] + node _T_46 = cat(_T_45, _T_42) @[Cat.scala 29:58] + node _T_47 = orr(_T_46) @[el2_lsu_addrcheck.scala 66:99] + node _T_48 = eq(_T_47, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 65:33] + node _T_49 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 67:49] + node _T_50 = or(_T_49, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:56] + node _T_51 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 67:121] + node _T_52 = eq(_T_50, _T_51) @[el2_lsu_addrcheck.scala 67:88] + node _T_53 = and(UInt<1>("h01"), _T_52) @[el2_lsu_addrcheck.scala 67:30] + node _T_54 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 68:49] + node _T_55 = or(_T_54, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:56] + node _T_56 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 68:121] + node _T_57 = eq(_T_55, _T_56) @[el2_lsu_addrcheck.scala 68:88] + node _T_58 = and(UInt<1>("h01"), _T_57) @[el2_lsu_addrcheck.scala 68:30] + node _T_59 = or(_T_53, _T_58) @[el2_lsu_addrcheck.scala 67:153] + node _T_60 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 69:49] + node _T_61 = or(_T_60, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:56] + node _T_62 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 69:121] + node _T_63 = eq(_T_61, _T_62) @[el2_lsu_addrcheck.scala 69:88] + node _T_64 = and(UInt<1>("h01"), _T_63) @[el2_lsu_addrcheck.scala 69:30] + node _T_65 = or(_T_59, _T_64) @[el2_lsu_addrcheck.scala 68:153] + node _T_66 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 70:49] + node _T_67 = or(_T_66, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:56] + node _T_68 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 70:121] + node _T_69 = eq(_T_67, _T_68) @[el2_lsu_addrcheck.scala 70:88] + node _T_70 = and(UInt<1>("h01"), _T_69) @[el2_lsu_addrcheck.scala 70:30] + node _T_71 = or(_T_65, _T_70) @[el2_lsu_addrcheck.scala 69:153] + node _T_72 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 71:49] + node _T_73 = or(_T_72, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:56] + node _T_74 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 71:121] + node _T_75 = eq(_T_73, _T_74) @[el2_lsu_addrcheck.scala 71:88] + node _T_76 = and(UInt<1>("h00"), _T_75) @[el2_lsu_addrcheck.scala 71:30] + node _T_77 = or(_T_71, _T_76) @[el2_lsu_addrcheck.scala 70:153] + node _T_78 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 72:49] + node _T_79 = or(_T_78, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:56] + node _T_80 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 72:121] + node _T_81 = eq(_T_79, _T_80) @[el2_lsu_addrcheck.scala 72:88] + node _T_82 = and(UInt<1>("h00"), _T_81) @[el2_lsu_addrcheck.scala 72:30] + node _T_83 = or(_T_77, _T_82) @[el2_lsu_addrcheck.scala 71:153] + node _T_84 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 73:49] + node _T_85 = or(_T_84, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:56] + node _T_86 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 73:121] + node _T_87 = eq(_T_85, _T_86) @[el2_lsu_addrcheck.scala 73:88] + node _T_88 = and(UInt<1>("h00"), _T_87) @[el2_lsu_addrcheck.scala 73:30] + node _T_89 = or(_T_83, _T_88) @[el2_lsu_addrcheck.scala 72:153] + node _T_90 = bits(io.start_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 74:49] + node _T_91 = or(_T_90, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:56] + node _T_92 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 74:121] + node _T_93 = eq(_T_91, _T_92) @[el2_lsu_addrcheck.scala 74:88] + node _T_94 = and(UInt<1>("h00"), _T_93) @[el2_lsu_addrcheck.scala 74:30] + node _T_95 = or(_T_89, _T_94) @[el2_lsu_addrcheck.scala 73:153] + node _T_96 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 76:48] + node _T_97 = or(_T_96, UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:57] + node _T_98 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_lsu_addrcheck.scala 76:122] + node _T_99 = eq(_T_97, _T_98) @[el2_lsu_addrcheck.scala 76:89] + node _T_100 = and(UInt<1>("h01"), _T_99) @[el2_lsu_addrcheck.scala 76:31] + node _T_101 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 77:49] + node _T_102 = or(_T_101, UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:58] + node _T_103 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_lsu_addrcheck.scala 77:123] + node _T_104 = eq(_T_102, _T_103) @[el2_lsu_addrcheck.scala 77:90] + node _T_105 = and(UInt<1>("h01"), _T_104) @[el2_lsu_addrcheck.scala 77:32] + node _T_106 = or(_T_100, _T_105) @[el2_lsu_addrcheck.scala 76:154] + node _T_107 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 78:49] + node _T_108 = or(_T_107, UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:58] + node _T_109 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_lsu_addrcheck.scala 78:123] + node _T_110 = eq(_T_108, _T_109) @[el2_lsu_addrcheck.scala 78:90] + node _T_111 = and(UInt<1>("h01"), _T_110) @[el2_lsu_addrcheck.scala 78:32] + node _T_112 = or(_T_106, _T_111) @[el2_lsu_addrcheck.scala 77:155] + node _T_113 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 79:49] + node _T_114 = or(_T_113, UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:58] + node _T_115 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_lsu_addrcheck.scala 79:123] + node _T_116 = eq(_T_114, _T_115) @[el2_lsu_addrcheck.scala 79:90] + node _T_117 = and(UInt<1>("h01"), _T_116) @[el2_lsu_addrcheck.scala 79:32] + node _T_118 = or(_T_112, _T_117) @[el2_lsu_addrcheck.scala 78:155] + node _T_119 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 80:49] + node _T_120 = or(_T_119, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:58] + node _T_121 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 80:123] + node _T_122 = eq(_T_120, _T_121) @[el2_lsu_addrcheck.scala 80:90] + node _T_123 = and(UInt<1>("h00"), _T_122) @[el2_lsu_addrcheck.scala 80:32] + node _T_124 = or(_T_118, _T_123) @[el2_lsu_addrcheck.scala 79:155] + node _T_125 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 81:49] + node _T_126 = or(_T_125, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:58] + node _T_127 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 81:123] + node _T_128 = eq(_T_126, _T_127) @[el2_lsu_addrcheck.scala 81:90] + node _T_129 = and(UInt<1>("h00"), _T_128) @[el2_lsu_addrcheck.scala 81:32] + node _T_130 = or(_T_124, _T_129) @[el2_lsu_addrcheck.scala 80:155] + node _T_131 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 82:49] + node _T_132 = or(_T_131, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:58] + node _T_133 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 82:123] + node _T_134 = eq(_T_132, _T_133) @[el2_lsu_addrcheck.scala 82:90] + node _T_135 = and(UInt<1>("h00"), _T_134) @[el2_lsu_addrcheck.scala 82:32] + node _T_136 = or(_T_130, _T_135) @[el2_lsu_addrcheck.scala 81:155] + node _T_137 = bits(io.end_addr_d, 31, 0) @[el2_lsu_addrcheck.scala 83:49] + node _T_138 = or(_T_137, UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:58] + node _T_139 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_lsu_addrcheck.scala 83:123] + node _T_140 = eq(_T_138, _T_139) @[el2_lsu_addrcheck.scala 83:90] + node _T_141 = and(UInt<1>("h00"), _T_140) @[el2_lsu_addrcheck.scala 83:32] + node _T_142 = or(_T_136, _T_141) @[el2_lsu_addrcheck.scala 82:155] + node _T_143 = and(_T_95, _T_142) @[el2_lsu_addrcheck.scala 75:7] + node non_dccm_access_ok = or(_T_48, _T_143) @[el2_lsu_addrcheck.scala 66:104] + node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[el2_lsu_addrcheck.scala 85:57] + node _T_144 = bits(io.start_addr_d, 1, 0) @[el2_lsu_addrcheck.scala 86:70] + node _T_145 = neq(_T_144, UInt<2>("h00")) @[el2_lsu_addrcheck.scala 86:76] + node _T_146 = eq(io.lsu_pkt_d.word, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 86:92] + node _T_147 = or(_T_145, _T_146) @[el2_lsu_addrcheck.scala 86:90] + node picm_access_fault_d = and(io.addr_in_pic_d, _T_147) @[el2_lsu_addrcheck.scala 86:51] wire unmapped_access_fault_d : UInt<1> unmapped_access_fault_d <= UInt<1>("h01") wire mpu_access_fault_d : UInt<1> mpu_access_fault_d <= UInt<1>("h01") - node _T_136 = or(start_addr_in_dccm_d, start_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 122:87] - node _T_137 = not(_T_136) @[el2_lsu_addrcheck.scala 122:64] - node _T_138 = and(start_addr_in_dccm_region_d, _T_137) @[el2_lsu_addrcheck.scala 122:62] - node _T_139 = or(end_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 124:57] - node _T_140 = not(_T_139) @[el2_lsu_addrcheck.scala 124:36] - node _T_141 = and(end_addr_in_dccm_region_d, _T_140) @[el2_lsu_addrcheck.scala 124:34] - node _T_142 = or(_T_138, _T_141) @[el2_lsu_addrcheck.scala 122:112] - node _T_143 = and(start_addr_in_dccm_d, end_addr_pic_rangecheck.io.in_range) @[el2_lsu_addrcheck.scala 126:29] - node _T_144 = or(_T_142, _T_143) @[el2_lsu_addrcheck.scala 124:85] - node _T_145 = and(start_addr_pic_rangecheck.io.in_range, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 128:29] - node _T_146 = or(_T_144, _T_145) @[el2_lsu_addrcheck.scala 126:85] - unmapped_access_fault_d <= _T_146 @[el2_lsu_addrcheck.scala 122:29] - node _T_147 = not(start_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 130:33] - node _T_148 = not(non_dccm_access_ok) @[el2_lsu_addrcheck.scala 130:64] - node _T_149 = and(_T_147, _T_148) @[el2_lsu_addrcheck.scala 130:62] - mpu_access_fault_d <= _T_149 @[el2_lsu_addrcheck.scala 130:29] - node _T_150 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 142:49] - node _T_151 = or(_T_150, picm_access_fault_d) @[el2_lsu_addrcheck.scala 142:70] - node _T_152 = or(_T_151, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 142:92] - node _T_153 = and(_T_152, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 142:118] - node _T_154 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 142:141] - node _T_155 = and(_T_153, _T_154) @[el2_lsu_addrcheck.scala 142:139] - io.access_fault_d <= _T_155 @[el2_lsu_addrcheck.scala 142:21] - node _T_156 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:60] - node _T_157 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:100] - node _T_158 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:144] - node _T_159 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 143:185] - node _T_160 = mux(_T_159, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 143:164] - node _T_161 = mux(_T_158, UInt<4>("h05"), _T_160) @[el2_lsu_addrcheck.scala 143:120] - node _T_162 = mux(_T_157, UInt<4>("h03"), _T_161) @[el2_lsu_addrcheck.scala 143:80] - node access_fault_mscause_d = mux(_T_156, UInt<4>("h02"), _T_162) @[el2_lsu_addrcheck.scala 143:35] - node _T_163 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:53] - node _T_164 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 144:78] - node regcross_misaligned_fault_d = neq(_T_163, _T_164) @[el2_lsu_addrcheck.scala 144:61] - node _T_165 = not(is_aligned_d) @[el2_lsu_addrcheck.scala 145:59] - node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_165) @[el2_lsu_addrcheck.scala 145:57] - node _T_166 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 146:90] - node _T_167 = or(regcross_misaligned_fault_d, _T_166) @[el2_lsu_addrcheck.scala 146:57] - node _T_168 = and(_T_167, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 146:113] - node _T_169 = not(io.lsu_pkt_d.dma) @[el2_lsu_addrcheck.scala 146:136] - node _T_170 = and(_T_168, _T_169) @[el2_lsu_addrcheck.scala 146:134] - io.misaligned_fault_d <= _T_170 @[el2_lsu_addrcheck.scala 146:25] - node _T_171 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 147:111] - node _T_172 = mux(_T_171, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 147:80] - node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_172) @[el2_lsu_addrcheck.scala 147:39] - node _T_173 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 148:50] - node _T_174 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:84] - node _T_175 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 148:113] - node _T_176 = mux(_T_173, _T_174, _T_175) @[el2_lsu_addrcheck.scala 148:27] - io.exc_mscause_d <= _T_176 @[el2_lsu_addrcheck.scala 148:21] - node _T_177 = not(start_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:66] - node _T_178 = and(start_addr_in_dccm_region_d, _T_177) @[el2_lsu_addrcheck.scala 149:64] - node _T_179 = not(end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 149:120] - node _T_180 = and(end_addr_in_dccm_region_d, _T_179) @[el2_lsu_addrcheck.scala 149:118] - node _T_181 = or(_T_178, _T_180) @[el2_lsu_addrcheck.scala 149:88] - node _T_182 = and(_T_181, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 149:142] - node _T_183 = and(_T_182, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 149:163] - io.fir_dccm_access_error_d <= _T_183 @[el2_lsu_addrcheck.scala 149:31] - node _T_184 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 150:66] - node _T_185 = not(_T_184) @[el2_lsu_addrcheck.scala 150:36] - node _T_186 = and(_T_185, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 150:95] - node _T_187 = and(_T_186, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 150:116] - io.fir_nondccm_access_error_d <= _T_187 @[el2_lsu_addrcheck.scala 150:33] - reg _T_188 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 152:60] - _T_188 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 152:60] - io.is_sideeffects_m <= _T_188 @[el2_lsu_addrcheck.scala 152:50] - - module rvdff : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_1 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_2 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<4>, dout : UInt<4>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_3 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<2>, dout : UInt<2>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_4 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_5 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_6 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_7 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_8 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_9 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_10 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_11 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_12 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_13 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_14 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_15 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_16 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<1>, dout : UInt<1>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] - - module rvdff_17 : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<32>, dout : UInt<32>} - - reg flop : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 15:21] - flop <= io.din @[beh_lib.scala 15:21] - io.dout <= flop @[beh_lib.scala 20:12] + node _T_148 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[el2_lsu_addrcheck.scala 91:87] + node _T_149 = eq(_T_148, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 91:64] + node _T_150 = and(start_addr_in_dccm_region_d, _T_149) @[el2_lsu_addrcheck.scala 91:62] + node _T_151 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 93:57] + node _T_152 = eq(_T_151, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 93:36] + node _T_153 = and(end_addr_in_dccm_region_d, _T_152) @[el2_lsu_addrcheck.scala 93:34] + node _T_154 = or(_T_150, _T_153) @[el2_lsu_addrcheck.scala 91:112] + node _T_155 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[el2_lsu_addrcheck.scala 95:29] + node _T_156 = or(_T_154, _T_155) @[el2_lsu_addrcheck.scala 93:85] + node _T_157 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[el2_lsu_addrcheck.scala 97:29] + node _T_158 = or(_T_156, _T_157) @[el2_lsu_addrcheck.scala 95:85] + unmapped_access_fault_d <= _T_158 @[el2_lsu_addrcheck.scala 91:29] + node _T_159 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:33] + node _T_160 = eq(non_dccm_access_ok, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 99:64] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_addrcheck.scala 99:62] + mpu_access_fault_d <= _T_161 @[el2_lsu_addrcheck.scala 99:29] + node _T_162 = or(unmapped_access_fault_d, mpu_access_fault_d) @[el2_lsu_addrcheck.scala 111:49] + node _T_163 = or(_T_162, picm_access_fault_d) @[el2_lsu_addrcheck.scala 111:70] + node _T_164 = or(_T_163, regpred_access_fault_d) @[el2_lsu_addrcheck.scala 111:92] + node _T_165 = and(_T_164, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 111:118] + node _T_166 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 111:141] + node _T_167 = and(_T_165, _T_166) @[el2_lsu_addrcheck.scala 111:139] + io.access_fault_d <= _T_167 @[el2_lsu_addrcheck.scala 111:21] + node _T_168 = bits(unmapped_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:60] + node _T_169 = bits(mpu_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:100] + node _T_170 = bits(regpred_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:144] + node _T_171 = bits(picm_access_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 112:185] + node _T_172 = mux(_T_171, UInt<4>("h06"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 112:164] + node _T_173 = mux(_T_170, UInt<4>("h05"), _T_172) @[el2_lsu_addrcheck.scala 112:120] + node _T_174 = mux(_T_169, UInt<4>("h03"), _T_173) @[el2_lsu_addrcheck.scala 112:80] + node access_fault_mscause_d = mux(_T_168, UInt<4>("h02"), _T_174) @[el2_lsu_addrcheck.scala 112:35] + node _T_175 = bits(io.start_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:53] + node _T_176 = bits(io.end_addr_d, 31, 28) @[el2_lsu_addrcheck.scala 113:78] + node regcross_misaligned_fault_d = neq(_T_175, _T_176) @[el2_lsu_addrcheck.scala 113:61] + node _T_177 = eq(is_aligned_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 114:59] + node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_177) @[el2_lsu_addrcheck.scala 114:57] + node _T_178 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[el2_lsu_addrcheck.scala 115:90] + node _T_179 = or(regcross_misaligned_fault_d, _T_178) @[el2_lsu_addrcheck.scala 115:57] + node _T_180 = and(_T_179, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 115:113] + node _T_181 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 115:136] + node _T_182 = and(_T_180, _T_181) @[el2_lsu_addrcheck.scala 115:134] + io.misaligned_fault_d <= _T_182 @[el2_lsu_addrcheck.scala 115:25] + node _T_183 = bits(sideeffect_misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 116:111] + node _T_184 = mux(_T_183, UInt<4>("h01"), UInt<4>("h00")) @[el2_lsu_addrcheck.scala 116:80] + node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_184) @[el2_lsu_addrcheck.scala 116:39] + node _T_185 = bits(io.misaligned_fault_d, 0, 0) @[el2_lsu_addrcheck.scala 117:50] + node _T_186 = bits(misaligned_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:84] + node _T_187 = bits(access_fault_mscause_d, 3, 0) @[el2_lsu_addrcheck.scala 117:113] + node _T_188 = mux(_T_185, _T_186, _T_187) @[el2_lsu_addrcheck.scala 117:27] + io.exc_mscause_d <= _T_188 @[el2_lsu_addrcheck.scala 117:21] + node _T_189 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:66] + node _T_190 = and(start_addr_in_dccm_region_d, _T_189) @[el2_lsu_addrcheck.scala 118:64] + node _T_191 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 118:120] + node _T_192 = and(end_addr_in_dccm_region_d, _T_191) @[el2_lsu_addrcheck.scala 118:118] + node _T_193 = or(_T_190, _T_192) @[el2_lsu_addrcheck.scala 118:88] + node _T_194 = and(_T_193, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 118:142] + node _T_195 = and(_T_194, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 118:163] + io.fir_dccm_access_error_d <= _T_195 @[el2_lsu_addrcheck.scala 118:31] + node _T_196 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[el2_lsu_addrcheck.scala 119:66] + node _T_197 = eq(_T_196, UInt<1>("h00")) @[el2_lsu_addrcheck.scala 119:36] + node _T_198 = and(_T_197, io.lsu_pkt_d.valid) @[el2_lsu_addrcheck.scala 119:95] + node _T_199 = and(_T_198, io.lsu_pkt_d.fast_int) @[el2_lsu_addrcheck.scala 119:116] + io.fir_nondccm_access_error_d <= _T_199 @[el2_lsu_addrcheck.scala 119:33] + reg _T_200 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_addrcheck.scala 121:60] + _T_200 <= is_sideeffects_d @[el2_lsu_addrcheck.scala 121:60] + io.is_sideeffects_m <= _T_200 @[el2_lsu_addrcheck.scala 121:50] module el2_lsu_lsc_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}, lsu_fir_addr : UInt<32>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>} + output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>, lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip scan_mode : UInt<1>} - wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 103:29] - wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 104:29] - wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 105:29] - wire lsu_error_pkt_m : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>} @[el2_lsu_lsc_ctl.scala 106:29] - node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 108:52] - node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 108:28] - node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 109:44] + wire dma_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 96:29] + wire lsu_pkt_m_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 97:29] + wire lsu_pkt_r_in : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 98:29] + wire lsu_error_pkt_m : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>} @[el2_lsu_lsc_ctl.scala 99:29] + node _T = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 101:52] + node lsu_rs1_d = mux(_T, io.exu_lsu_rs1_d, io.dma_mem_addr) @[el2_lsu_lsc_ctl.scala 101:28] + node _T_1 = bits(io.dec_lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 102:44] node _T_2 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15] node _T_3 = mux(_T_2, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12] - node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 109:51] - node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 114:51] - node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 114:18] - inst lsadder of rvlsadder @[el2_lsu_lsc_ctl.scala 118:23] - lsadder.clock <= clock - lsadder.reset <= reset - lsadder.io.rs1 <= rs1_d @[el2_lsu_lsc_ctl.scala 119:26] - lsadder.io.offset <= lsu_offset_d @[el2_lsu_lsc_ctl.scala 120:26] - node _T_5 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15] - node _T_6 = mux(_T_5, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_7 = and(_T_6, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 127:53] - node _T_8 = bits(io.lsu_pkt_d.word, 0, 0) @[Bitwise.scala 72:15] - node _T_9 = mux(_T_8, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_10 = and(_T_9, UInt<2>("h03")) @[el2_lsu_lsc_ctl.scala 128:35] - node _T_11 = or(_T_7, _T_10) @[el2_lsu_lsc_ctl.scala 127:65] - node _T_12 = bits(io.lsu_pkt_d.dword, 0, 0) @[Bitwise.scala 72:15] - node _T_13 = mux(_T_12, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] - node _T_14 = and(_T_13, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 129:35] - node addr_offset_d = or(_T_11, _T_14) @[el2_lsu_lsc_ctl.scala 128:47] - node _T_15 = bits(lsu_offset_d, 11, 11) @[el2_lsu_lsc_ctl.scala 131:39] - node _T_16 = bits(lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 131:52] - node _T_17 = cat(_T_15, _T_16) @[Cat.scala 29:58] - node _T_18 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] - node _T_19 = bits(addr_offset_d, 2, 0) @[el2_lsu_lsc_ctl.scala 131:94] - node _T_20 = cat(_T_18, _T_19) @[Cat.scala 29:58] - node _T_21 = add(_T_17, _T_20) @[el2_lsu_lsc_ctl.scala 131:60] - node end_addr_offset_d = tail(_T_21, 1) @[el2_lsu_lsc_ctl.scala 131:60] - node _T_22 = bits(rs1_d, 31, 0) @[el2_lsu_lsc_ctl.scala 132:32] - node _T_23 = bits(end_addr_offset_d, 12, 12) @[el2_lsu_lsc_ctl.scala 132:70] - node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15] - node _T_25 = mux(_T_24, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] - node _T_26 = bits(end_addr_offset_d, 12, 0) @[el2_lsu_lsc_ctl.scala 132:93] - node _T_27 = cat(_T_25, _T_26) @[Cat.scala 29:58] - node _T_28 = add(_T_22, _T_27) @[el2_lsu_lsc_ctl.scala 132:39] - node full_end_addr_d = tail(_T_28, 1) @[el2_lsu_lsc_ctl.scala 132:39] - io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 133:24] - inst addrcheck of el2_lsu_addrcheck @[el2_lsu_lsc_ctl.scala 141:25] + node lsu_offset_d = and(_T_1, _T_3) @[el2_lsu_lsc_ctl.scala 102:51] + node _T_4 = bits(io.lsu_pkt_d.load_ldst_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 105:61] + node rs1_d = mux(_T_4, io.lsu_result_m, lsu_rs1_d) @[el2_lsu_lsc_ctl.scala 105:28] + node _T_5 = bits(rs1_d, 11, 0) @[el2_lib.scala 232:31] + node _T_6 = cat(UInt<1>("h00"), _T_5) @[Cat.scala 29:58] + node _T_7 = bits(lsu_offset_d, 11, 0) @[el2_lib.scala 232:60] + node _T_8 = cat(UInt<1>("h00"), _T_7) @[Cat.scala 29:58] + node _T_9 = add(_T_6, _T_8) @[el2_lib.scala 232:39] + node _T_10 = tail(_T_9, 1) @[el2_lib.scala 232:39] + node _T_11 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 233:41] + node _T_12 = bits(_T_10, 12, 12) @[el2_lib.scala 233:50] + node _T_13 = xor(_T_11, _T_12) @[el2_lib.scala 233:46] + node _T_14 = not(_T_13) @[el2_lib.scala 233:33] + node _T_15 = bits(_T_14, 0, 0) @[Bitwise.scala 72:15] + node _T_16 = mux(_T_15, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_17 = bits(rs1_d, 31, 12) @[el2_lib.scala 233:63] + node _T_18 = and(_T_16, _T_17) @[el2_lib.scala 233:58] + node _T_19 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 234:25] + node _T_20 = not(_T_19) @[el2_lib.scala 234:18] + node _T_21 = bits(_T_10, 12, 12) @[el2_lib.scala 234:34] + node _T_22 = and(_T_20, _T_21) @[el2_lib.scala 234:30] + node _T_23 = bits(_T_22, 0, 0) @[Bitwise.scala 72:15] + node _T_24 = mux(_T_23, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_25 = bits(rs1_d, 31, 12) @[el2_lib.scala 234:47] + node _T_26 = add(_T_25, UInt<1>("h01")) @[el2_lib.scala 234:54] + node _T_27 = tail(_T_26, 1) @[el2_lib.scala 234:54] + node _T_28 = and(_T_24, _T_27) @[el2_lib.scala 234:41] + node _T_29 = or(_T_18, _T_28) @[el2_lib.scala 233:72] + node _T_30 = bits(lsu_offset_d, 11, 11) @[el2_lib.scala 235:24] + node _T_31 = bits(_T_10, 12, 12) @[el2_lib.scala 235:34] + node _T_32 = not(_T_31) @[el2_lib.scala 235:31] + node _T_33 = and(_T_30, _T_32) @[el2_lib.scala 235:29] + node _T_34 = bits(_T_33, 0, 0) @[Bitwise.scala 72:15] + node _T_35 = mux(_T_34, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12] + node _T_36 = bits(rs1_d, 31, 12) @[el2_lib.scala 235:47] + node _T_37 = sub(_T_36, UInt<1>("h01")) @[el2_lib.scala 235:54] + node _T_38 = tail(_T_37, 1) @[el2_lib.scala 235:54] + node _T_39 = and(_T_35, _T_38) @[el2_lib.scala 235:41] + node _T_40 = or(_T_29, _T_39) @[el2_lib.scala 234:61] + node _T_41 = bits(_T_10, 11, 0) @[el2_lib.scala 236:22] + node full_addr_d = cat(_T_40, _T_41) @[Cat.scala 29:58] + node _T_42 = bits(io.lsu_pkt_d.half, 0, 0) @[Bitwise.scala 72:15] + node _T_43 = mux(_T_42, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_44 = and(_T_43, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 110:53] + node _T_45 = bits(io.lsu_pkt_d.word, 0, 0) @[Bitwise.scala 72:15] + node _T_46 = mux(_T_45, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_47 = and(_T_46, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 111:35] + node _T_48 = or(_T_44, _T_47) @[el2_lsu_lsc_ctl.scala 110:65] + node _T_49 = bits(io.lsu_pkt_d.dword, 0, 0) @[Bitwise.scala 72:15] + node _T_50 = mux(_T_49, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_51 = and(_T_50, UInt<3>("h07")) @[el2_lsu_lsc_ctl.scala 112:35] + node addr_offset_d = or(_T_48, _T_51) @[el2_lsu_lsc_ctl.scala 111:47] + node _T_52 = bits(lsu_offset_d, 11, 11) @[el2_lsu_lsc_ctl.scala 114:39] + node _T_53 = bits(lsu_offset_d, 11, 0) @[el2_lsu_lsc_ctl.scala 114:52] + node _T_54 = cat(_T_52, _T_53) @[Cat.scala 29:58] + node _T_55 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12] + node _T_56 = bits(addr_offset_d, 2, 0) @[el2_lsu_lsc_ctl.scala 114:91] + node _T_57 = cat(_T_55, _T_56) @[Cat.scala 29:58] + node _T_58 = add(_T_54, _T_57) @[el2_lsu_lsc_ctl.scala 114:60] + node end_addr_offset_d = tail(_T_58, 1) @[el2_lsu_lsc_ctl.scala 114:60] + node _T_59 = bits(rs1_d, 31, 0) @[el2_lsu_lsc_ctl.scala 115:32] + node _T_60 = bits(end_addr_offset_d, 12, 12) @[el2_lsu_lsc_ctl.scala 115:70] + node _T_61 = bits(_T_60, 0, 0) @[Bitwise.scala 72:15] + node _T_62 = mux(_T_61, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12] + node _T_63 = bits(end_addr_offset_d, 12, 0) @[el2_lsu_lsc_ctl.scala 115:93] + node _T_64 = cat(_T_62, _T_63) @[Cat.scala 29:58] + node _T_65 = add(_T_59, _T_64) @[el2_lsu_lsc_ctl.scala 115:39] + node full_end_addr_d = tail(_T_65, 1) @[el2_lsu_lsc_ctl.scala 115:39] + io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 116:24] + inst addrcheck of el2_lsu_addrcheck @[el2_lsu_lsc_ctl.scala 119:25] addrcheck.clock <= clock addrcheck.reset <= reset - addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[el2_lsu_lsc_ctl.scala 143:42] - addrcheck.io.start_addr_d <= lsadder.io.dout @[el2_lsu_lsc_ctl.scala 145:42] - addrcheck.io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 146:42] - addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.lsu_pkt_d.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 147:42] - addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu_lsc_ctl.scala 148:42] - node _T_29 = bits(rs1_d, 31, 28) @[el2_lsu_lsc_ctl.scala 149:50] - addrcheck.io.rs1_region_d <= _T_29 @[el2_lsu_lsc_ctl.scala 149:42] - addrcheck.io.rs1_d <= rs1_d @[el2_lsu_lsc_ctl.scala 150:42] - io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[el2_lsu_lsc_ctl.scala 151:42] - io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 152:42] - io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 153:42] - addrcheck.io.scan_mode <= io.scan_mode @[el2_lsu_lsc_ctl.scala 160:42] - wire access_fault_r : UInt<1> - access_fault_r <= UInt<1>("h00") - wire misaligned_fault_r : UInt<1> - misaligned_fault_r <= UInt<1>("h00") + addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[el2_lsu_lsc_ctl.scala 121:42] + addrcheck.io.start_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 123:42] + addrcheck.io.end_addr_d <= full_end_addr_d @[el2_lsu_lsc_ctl.scala 124:42] + addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.lsu_pkt_d.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 125:42] + addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu_lsc_ctl.scala 126:42] + node _T_66 = bits(rs1_d, 31, 28) @[el2_lsu_lsc_ctl.scala 127:50] + addrcheck.io.rs1_region_d <= _T_66 @[el2_lsu_lsc_ctl.scala 127:42] + addrcheck.io.rs1_d <= rs1_d @[el2_lsu_lsc_ctl.scala 128:42] + io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[el2_lsu_lsc_ctl.scala 129:42] + io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 130:42] + io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 131:42] + addrcheck.io.scan_mode <= io.scan_mode @[el2_lsu_lsc_ctl.scala 138:42] wire exc_mscause_r : UInt<4> exc_mscause_r <= UInt<4>("h00") wire fir_dccm_access_error_r : UInt<1> fir_dccm_access_error_r <= UInt<1>("h00") wire fir_nondccm_access_error_r : UInt<1> fir_nondccm_access_error_r <= UInt<1>("h00") - inst access_fault_mff of rvdff @[el2_lsu_lsc_ctl.scala 169:45] - access_fault_mff.clock <= clock - access_fault_mff.reset <= reset - inst misaligned_fault_mff of rvdff_1 @[el2_lsu_lsc_ctl.scala 171:45] - misaligned_fault_mff.clock <= clock - misaligned_fault_mff.reset <= reset - inst exc_mscause_mff of rvdff_2 @[el2_lsu_lsc_ctl.scala 173:45] - exc_mscause_mff.clock <= clock - exc_mscause_mff.reset <= reset - inst lsu_fir_error_rff of rvdff_3 @[el2_lsu_lsc_ctl.scala 177:45] - lsu_fir_error_rff.clock <= clock - lsu_fir_error_rff.reset <= reset + wire access_fault_r : UInt<1> + access_fault_r <= UInt<1>("h00") + wire misaligned_fault_r : UInt<1> + misaligned_fault_r <= UInt<1>("h00") wire lsu_fir_error_m : UInt<2> lsu_fir_error_m <= UInt<2>("h00") - wire access_fault_m : UInt<1> - access_fault_m <= UInt<1>("h00") - wire misaligned_fault_m : UInt<1> - misaligned_fault_m <= UInt<1>("h00") - wire exc_mscause_m : UInt<4> - exc_mscause_m <= UInt<4>("h00") wire fir_dccm_access_error_m : UInt<1> fir_dccm_access_error_m <= UInt<1>("h00") wire fir_nondccm_access_error_m : UInt<1> fir_nondccm_access_error_m <= UInt<1>("h00") - node _T_30 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 188:34] - io.lsu_exc_m <= _T_30 @[el2_lsu_lsc_ctl.scala 188:16] - node _T_31 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 189:64] - node _T_32 = and(io.lsu_single_ecc_error_r, _T_31) @[el2_lsu_lsc_ctl.scala 189:62] - node _T_33 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_lsc_ctl.scala 189:111] - node _T_34 = and(_T_32, _T_33) @[el2_lsu_lsc_ctl.scala 189:92] - node _T_35 = and(_T_34, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 189:131] - io.lsu_single_ecc_error_incr <= _T_35 @[el2_lsu_lsc_ctl.scala 189:32] - io.lsu_fir_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 228:23] - node _T_36 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 230:50] - node _T_37 = or(_T_36, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 230:71] - node _T_38 = and(_T_37, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 230:100] - node _T_39 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 230:123] - node _T_40 = and(_T_38, _T_39) @[el2_lsu_lsc_ctl.scala 230:121] - node _T_41 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 230:143] - node _T_42 = and(_T_40, _T_41) @[el2_lsu_lsc_ctl.scala 230:141] - node _T_43 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 230:168] - node _T_44 = and(_T_42, _T_43) @[el2_lsu_lsc_ctl.scala 230:166] - lsu_error_pkt_m.exc_valid <= _T_44 @[el2_lsu_lsc_ctl.scala 230:31] - node _T_45 = eq(lsu_error_pkt_m.exc_valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 231:70] - node _T_46 = and(io.lsu_single_ecc_error_m, _T_45) @[el2_lsu_lsc_ctl.scala 231:68] - node _T_47 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 231:100] - node _T_48 = and(_T_46, _T_47) @[el2_lsu_lsc_ctl.scala 231:98] - lsu_error_pkt_m.single_ecc_error <= _T_48 @[el2_lsu_lsc_ctl.scala 231:38] - lsu_error_pkt_m.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 232:38] - node _T_49 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 233:41] - lsu_error_pkt_m.exc_type <= _T_49 @[el2_lsu_lsc_ctl.scala 233:38] - node _T_50 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 234:74] - node _T_51 = and(io.lsu_double_ecc_error_m, _T_50) @[el2_lsu_lsc_ctl.scala 234:72] - node _T_52 = eq(access_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 234:96] - node _T_53 = and(_T_51, _T_52) @[el2_lsu_lsc_ctl.scala 234:94] - node _T_54 = bits(_T_53, 0, 0) @[el2_lsu_lsc_ctl.scala 234:113] - node _T_55 = bits(exc_mscause_m, 3, 0) @[el2_lsu_lsc_ctl.scala 234:144] - node _T_56 = mux(_T_54, UInt<1>("h01"), _T_55) @[el2_lsu_lsc_ctl.scala 234:44] - lsu_error_pkt_m.mscause <= _T_56 @[el2_lsu_lsc_ctl.scala 234:38] - node _T_57 = bits(io.lsu_addr_m, 31, 0) @[el2_lsu_lsc_ctl.scala 235:54] - lsu_error_pkt_m.addr <= _T_57 @[el2_lsu_lsc_ctl.scala 235:38] - node _T_58 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 236:72] - node _T_59 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 236:116] - node _T_60 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 236:159] - node _T_61 = bits(_T_60, 0, 0) @[el2_lsu_lsc_ctl.scala 236:188] - node _T_62 = mux(_T_61, UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 236:135] - node _T_63 = mux(_T_59, UInt<2>("h02"), _T_62) @[el2_lsu_lsc_ctl.scala 236:91] - node _T_64 = mux(_T_58, UInt<2>("h03"), _T_63) @[el2_lsu_lsc_ctl.scala 236:44] - lsu_fir_error_m <= _T_64 @[el2_lsu_lsc_ctl.scala 236:38] - reg _T_65 : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}, clock @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.addr <= lsu_error_pkt_m.addr @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.mscause <= lsu_error_pkt_m.mscause @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.exc_type <= lsu_error_pkt_m.exc_type @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.inst_type <= lsu_error_pkt_m.inst_type @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.single_ecc_error <= lsu_error_pkt_m.single_ecc_error @[el2_lsu_lsc_ctl.scala 241:34] - _T_65.exc_valid <= lsu_error_pkt_m.exc_valid @[el2_lsu_lsc_ctl.scala 241:34] - io.lsu_error_pkt_r.addr <= _T_65.addr @[el2_lsu_lsc_ctl.scala 241:24] - io.lsu_error_pkt_r.mscause <= _T_65.mscause @[el2_lsu_lsc_ctl.scala 241:24] - io.lsu_error_pkt_r.exc_type <= _T_65.exc_type @[el2_lsu_lsc_ctl.scala 241:24] - io.lsu_error_pkt_r.inst_type <= _T_65.inst_type @[el2_lsu_lsc_ctl.scala 241:24] - io.lsu_error_pkt_r.single_ecc_error <= _T_65.single_ecc_error @[el2_lsu_lsc_ctl.scala 241:24] - io.lsu_error_pkt_r.exc_valid <= _T_65.exc_valid @[el2_lsu_lsc_ctl.scala 241:24] - lsu_fir_error_rff.io.din <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 243:41] - lsu_fir_error_m <= lsu_fir_error_rff.io.dout @[el2_lsu_lsc_ctl.scala 244:41] - access_fault_mff.io.din <= addrcheck.io.access_fault_d @[el2_lsu_lsc_ctl.scala 246:40] - access_fault_m <= access_fault_mff.io.dout @[el2_lsu_lsc_ctl.scala 247:40] - misaligned_fault_mff.io.din <= addrcheck.io.misaligned_fault_d @[el2_lsu_lsc_ctl.scala 249:40] - misaligned_fault_m <= misaligned_fault_mff.io.dout @[el2_lsu_lsc_ctl.scala 250:40] - exc_mscause_mff.io.din <= addrcheck.io.exc_mscause_d @[el2_lsu_lsc_ctl.scala 252:40] - exc_mscause_m <= exc_mscause_mff.io.dout @[el2_lsu_lsc_ctl.scala 253:40] - reg _T_66 : UInt, clock @[el2_lsu_lsc_ctl.scala 257:52] - _T_66 <= addrcheck.io.fir_dccm_access_error_d @[el2_lsu_lsc_ctl.scala 257:52] - fir_dccm_access_error_m <= _T_66 @[el2_lsu_lsc_ctl.scala 257:42] - reg _T_67 : UInt, clock @[el2_lsu_lsc_ctl.scala 260:54] - _T_67 <= addrcheck.io.fir_nondccm_access_error_d @[el2_lsu_lsc_ctl.scala 260:54] - fir_nondccm_access_error_m <= _T_67 @[el2_lsu_lsc_ctl.scala 260:44] - dma_pkt_d.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 263:22] - dma_pkt_d.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 264:22] - dma_pkt_d.valid <= io.dma_dccm_req @[el2_lsu_lsc_ctl.scala 265:22] - dma_pkt_d.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 266:22] - dma_pkt_d.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 267:22] - node _T_68 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 268:25] - dma_pkt_d.load <= _T_68 @[el2_lsu_lsc_ctl.scala 268:22] - node _T_69 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 269:39] - node _T_70 = eq(_T_69, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 269:45] - dma_pkt_d.by <= _T_70 @[el2_lsu_lsc_ctl.scala 269:22] - node _T_71 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 270:39] - node _T_72 = eq(_T_71, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 270:45] - dma_pkt_d.half <= _T_72 @[el2_lsu_lsc_ctl.scala 270:22] - node _T_73 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 271:39] - node _T_74 = eq(_T_73, UInt<2>("h02")) @[el2_lsu_lsc_ctl.scala 271:45] - dma_pkt_d.word <= _T_74 @[el2_lsu_lsc_ctl.scala 271:22] - node _T_75 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 272:39] - node _T_76 = eq(_T_75, UInt<2>("h03")) @[el2_lsu_lsc_ctl.scala 272:45] - dma_pkt_d.dword <= _T_76 @[el2_lsu_lsc_ctl.scala 272:22] - dma_pkt_d.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 273:34] - dma_pkt_d.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 274:34] - dma_pkt_d.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 275:34] - inst lsu_pkt_vldmff of rvdff_4 @[el2_lsu_lsc_ctl.scala 278:36] - lsu_pkt_vldmff.clock <= clock - lsu_pkt_vldmff.reset <= reset - inst lsu_pkt_vldrff of rvdff_5 @[el2_lsu_lsc_ctl.scala 279:36] - lsu_pkt_vldrff.clock <= clock - lsu_pkt_vldrff.reset <= reset + reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 150:75] + access_fault_m <= addrcheck.io.access_fault_d @[el2_lsu_lsc_ctl.scala 150:75] + reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 151:75] + misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[el2_lsu_lsc_ctl.scala 151:75] + reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 152:75] + exc_mscause_m <= addrcheck.io.exc_mscause_d @[el2_lsu_lsc_ctl.scala 152:75] + reg _T_67 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 153:75] + _T_67 <= addrcheck.io.fir_dccm_access_error_d @[el2_lsu_lsc_ctl.scala 153:75] + fir_dccm_access_error_m <= _T_67 @[el2_lsu_lsc_ctl.scala 153:38] + reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 154:75] + _T_68 <= addrcheck.io.fir_nondccm_access_error_d @[el2_lsu_lsc_ctl.scala 154:75] + fir_nondccm_access_error_m <= _T_68 @[el2_lsu_lsc_ctl.scala 154:38] + node _T_69 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 156:34] + io.lsu_exc_m <= _T_69 @[el2_lsu_lsc_ctl.scala 156:16] + node _T_70 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 157:64] + node _T_71 = and(io.lsu_single_ecc_error_r, _T_70) @[el2_lsu_lsc_ctl.scala 157:62] + node _T_72 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_lsc_ctl.scala 157:111] + node _T_73 = and(_T_71, _T_72) @[el2_lsu_lsc_ctl.scala 157:92] + node _T_74 = and(_T_73, io.lsu_pkt_r.valid) @[el2_lsu_lsc_ctl.scala 157:131] + io.lsu_single_ecc_error_incr <= _T_74 @[el2_lsu_lsc_ctl.scala 157:32] + node _T_75 = or(access_fault_m, misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 179:50] + node _T_76 = or(_T_75, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 179:71] + node _T_77 = and(_T_76, io.lsu_pkt_m.valid) @[el2_lsu_lsc_ctl.scala 179:100] + node _T_78 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:123] + node _T_79 = and(_T_77, _T_78) @[el2_lsu_lsc_ctl.scala 179:121] + node _T_80 = eq(io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:143] + node _T_81 = and(_T_79, _T_80) @[el2_lsu_lsc_ctl.scala 179:141] + node _T_82 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 179:168] + node _T_83 = and(_T_81, _T_82) @[el2_lsu_lsc_ctl.scala 179:166] + lsu_error_pkt_m.exc_valid <= _T_83 @[el2_lsu_lsc_ctl.scala 179:31] + node _T_84 = eq(lsu_error_pkt_m.exc_valid, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:70] + node _T_85 = and(io.lsu_single_ecc_error_m, _T_84) @[el2_lsu_lsc_ctl.scala 180:68] + node _T_86 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 180:100] + node _T_87 = and(_T_85, _T_86) @[el2_lsu_lsc_ctl.scala 180:98] + lsu_error_pkt_m.single_ecc_error <= _T_87 @[el2_lsu_lsc_ctl.scala 180:38] + lsu_error_pkt_m.inst_type <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 181:38] + node _T_88 = not(misaligned_fault_m) @[el2_lsu_lsc_ctl.scala 182:41] + lsu_error_pkt_m.exc_type <= _T_88 @[el2_lsu_lsc_ctl.scala 182:38] + node _T_89 = eq(misaligned_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:75] + node _T_90 = and(io.lsu_double_ecc_error_m, _T_89) @[el2_lsu_lsc_ctl.scala 183:73] + node _T_91 = eq(access_fault_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 183:97] + node _T_92 = and(_T_90, _T_91) @[el2_lsu_lsc_ctl.scala 183:95] + node _T_93 = eq(_T_92, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 183:113] + node _T_94 = bits(exc_mscause_m, 3, 0) @[el2_lsu_lsc_ctl.scala 183:144] + node _T_95 = mux(_T_93, UInt<4>("h01"), _T_94) @[el2_lsu_lsc_ctl.scala 183:44] + lsu_error_pkt_m.mscause <= _T_95 @[el2_lsu_lsc_ctl.scala 183:38] + node _T_96 = bits(io.lsu_addr_m, 31, 0) @[el2_lsu_lsc_ctl.scala 184:54] + lsu_error_pkt_m.addr <= _T_96 @[el2_lsu_lsc_ctl.scala 184:38] + node _T_97 = bits(fir_nondccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:72] + node _T_98 = bits(fir_dccm_access_error_m, 0, 0) @[el2_lsu_lsc_ctl.scala 185:117] + node _T_99 = and(io.lsu_pkt_m.fast_int, io.lsu_double_ecc_error_m) @[el2_lsu_lsc_ctl.scala 185:161] + node _T_100 = bits(_T_99, 0, 0) @[el2_lsu_lsc_ctl.scala 185:190] + node _T_101 = mux(_T_100, UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_lsc_ctl.scala 185:137] + node _T_102 = mux(_T_98, UInt<2>("h02"), _T_101) @[el2_lsu_lsc_ctl.scala 185:92] + node _T_103 = mux(_T_97, UInt<2>("h03"), _T_102) @[el2_lsu_lsc_ctl.scala 185:44] + lsu_fir_error_m <= _T_103 @[el2_lsu_lsc_ctl.scala 185:38] + wire _T_104 : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>} @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.addr <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.mscause <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.exc_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.inst_type <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.single_ecc_error <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + _T_104.exc_valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 186:104] + reg _T_105 : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, io.lsu_c2_r_clk with : (reset => (reset, _T_104)) @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.addr <= lsu_error_pkt_m.addr @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.mscause <= lsu_error_pkt_m.mscause @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.exc_type <= lsu_error_pkt_m.exc_type @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.inst_type <= lsu_error_pkt_m.inst_type @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.single_ecc_error <= lsu_error_pkt_m.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:75] + _T_105.exc_valid <= lsu_error_pkt_m.exc_valid @[el2_lsu_lsc_ctl.scala 186:75] + io.lsu_error_pkt_r.addr <= _T_105.addr @[el2_lsu_lsc_ctl.scala 186:38] + io.lsu_error_pkt_r.mscause <= _T_105.mscause @[el2_lsu_lsc_ctl.scala 186:38] + io.lsu_error_pkt_r.exc_type <= _T_105.exc_type @[el2_lsu_lsc_ctl.scala 186:38] + io.lsu_error_pkt_r.inst_type <= _T_105.inst_type @[el2_lsu_lsc_ctl.scala 186:38] + io.lsu_error_pkt_r.single_ecc_error <= _T_105.single_ecc_error @[el2_lsu_lsc_ctl.scala 186:38] + io.lsu_error_pkt_r.exc_valid <= _T_105.exc_valid @[el2_lsu_lsc_ctl.scala 186:38] + reg _T_106 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 187:75] + _T_106 <= lsu_fir_error_m @[el2_lsu_lsc_ctl.scala 187:75] + io.lsu_fir_error <= _T_106 @[el2_lsu_lsc_ctl.scala 187:38] + dma_pkt_d.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 189:22] + dma_pkt_d.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 190:22] + dma_pkt_d.valid <= io.dma_dccm_req @[el2_lsu_lsc_ctl.scala 191:22] + dma_pkt_d.dma <= UInt<1>("h01") @[el2_lsu_lsc_ctl.scala 192:22] + dma_pkt_d.store <= io.dma_mem_write @[el2_lsu_lsc_ctl.scala 193:22] + node _T_107 = not(io.dma_mem_write) @[el2_lsu_lsc_ctl.scala 194:25] + dma_pkt_d.load <= _T_107 @[el2_lsu_lsc_ctl.scala 194:22] + node _T_108 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 195:39] + node _T_109 = eq(_T_108, UInt<3>("h00")) @[el2_lsu_lsc_ctl.scala 195:45] + dma_pkt_d.by <= _T_109 @[el2_lsu_lsc_ctl.scala 195:22] + node _T_110 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 196:39] + node _T_111 = eq(_T_110, UInt<3>("h01")) @[el2_lsu_lsc_ctl.scala 196:45] + dma_pkt_d.half <= _T_111 @[el2_lsu_lsc_ctl.scala 196:22] + node _T_112 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 197:39] + node _T_113 = eq(_T_112, UInt<3>("h02")) @[el2_lsu_lsc_ctl.scala 197:45] + dma_pkt_d.word <= _T_113 @[el2_lsu_lsc_ctl.scala 197:22] + node _T_114 = bits(io.dma_mem_sz, 2, 0) @[el2_lsu_lsc_ctl.scala 198:39] + node _T_115 = eq(_T_114, UInt<3>("h03")) @[el2_lsu_lsc_ctl.scala 198:45] + dma_pkt_d.dword <= _T_115 @[el2_lsu_lsc_ctl.scala 198:22] + dma_pkt_d.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 199:34] + dma_pkt_d.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 200:34] + dma_pkt_d.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 201:34] wire lsu_ld_datafn_r : UInt<32> lsu_ld_datafn_r <= UInt<32>("h00") wire lsu_ld_datafn_corr_r : UInt<32> lsu_ld_datafn_corr_r <= UInt<32>("h00") wire lsu_ld_datafn_m : UInt<32> lsu_ld_datafn_m <= UInt<32>("h00") - node _T_77 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 285:50] - node _T_78 = mux(_T_77, io.lsu_p, dma_pkt_d) @[el2_lsu_lsc_ctl.scala 285:26] - io.lsu_pkt_d.valid <= _T_78.valid @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.store_data_bypass_m <= _T_78.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.load_ldst_bypass_d <= _T_78.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.store_data_bypass_d <= _T_78.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.dma <= _T_78.dma @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.unsign <= _T_78.unsign @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.store <= _T_78.store @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.load <= _T_78.load @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.dword <= _T_78.dword @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.word <= _T_78.word @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.half <= _T_78.half @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.by <= _T_78.by @[el2_lsu_lsc_ctl.scala 285:20] - io.lsu_pkt_d.fast_int <= _T_78.fast_int @[el2_lsu_lsc_ctl.scala 285:20] - lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_m_in.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 286:20] - lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.dma <= io.lsu_pkt_m.dma @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.store <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.load <= io.lsu_pkt_m.load @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.dword <= io.lsu_pkt_m.dword @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.word <= io.lsu_pkt_m.word @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.half <= io.lsu_pkt_m.half @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.by <= io.lsu_pkt_m.by @[el2_lsu_lsc_ctl.scala 287:20] - lsu_pkt_r_in.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_lsc_ctl.scala 287:20] - node _T_79 = eq(io.lsu_p.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 289:64] - node _T_80 = and(io.flush_m_up, _T_79) @[el2_lsu_lsc_ctl.scala 289:61] - node _T_81 = eq(_T_80, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 289:45] - node _T_82 = and(io.lsu_p.valid, _T_81) @[el2_lsu_lsc_ctl.scala 289:43] - node _T_83 = or(_T_82, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 289:85] - io.lsu_pkt_d.valid <= _T_83 @[el2_lsu_lsc_ctl.scala 289:24] - node _T_84 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 290:68] - node _T_85 = and(io.flush_m_up, _T_84) @[el2_lsu_lsc_ctl.scala 290:65] - node _T_86 = eq(_T_85, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 290:49] - node _T_87 = and(io.lsu_pkt_d.valid, _T_86) @[el2_lsu_lsc_ctl.scala 290:47] - lsu_pkt_m_in.valid <= _T_87 @[el2_lsu_lsc_ctl.scala 290:24] - node _T_88 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 291:68] - node _T_89 = and(io.flush_m_up, _T_88) @[el2_lsu_lsc_ctl.scala 291:65] - node _T_90 = eq(_T_89, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 291:49] - node _T_91 = and(io.lsu_pkt_m.valid, _T_90) @[el2_lsu_lsc_ctl.scala 291:47] - lsu_pkt_r_in.valid <= _T_91 @[el2_lsu_lsc_ctl.scala 291:24] - lsu_pkt_vldmff.io.din <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 295:34] - io.lsu_pkt_m.valid <= lsu_pkt_vldmff.io.dout @[el2_lsu_lsc_ctl.scala 296:34] - lsu_pkt_vldrff.io.din <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 299:33] - io.lsu_pkt_r.valid <= lsu_pkt_vldrff.io.dout @[el2_lsu_lsc_ctl.scala 300:33] - reg _T_92 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, clock @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.valid <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.store_data_bypass_m <= lsu_pkt_m_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.load_ldst_bypass_d <= lsu_pkt_m_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.store_data_bypass_d <= lsu_pkt_m_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.dma <= lsu_pkt_m_in.dma @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.unsign <= lsu_pkt_m_in.unsign @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.store <= lsu_pkt_m_in.store @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.load <= lsu_pkt_m_in.load @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.dword <= lsu_pkt_m_in.dword @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.word <= lsu_pkt_m_in.word @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.half <= lsu_pkt_m_in.half @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.by <= lsu_pkt_m_in.by @[el2_lsu_lsc_ctl.scala 305:26] - _T_92.fast_int <= lsu_pkt_m_in.fast_int @[el2_lsu_lsc_ctl.scala 305:26] - io.lsu_pkt_m.valid <= _T_92.valid @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.store_data_bypass_m <= _T_92.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.load_ldst_bypass_d <= _T_92.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.store_data_bypass_d <= _T_92.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.dma <= _T_92.dma @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.unsign <= _T_92.unsign @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.store <= _T_92.store @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.load <= _T_92.load @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.dword <= _T_92.dword @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.word <= _T_92.word @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.half <= _T_92.half @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.by <= _T_92.by @[el2_lsu_lsc_ctl.scala 305:16] - io.lsu_pkt_m.fast_int <= _T_92.fast_int @[el2_lsu_lsc_ctl.scala 305:16] - reg _T_93 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, clock @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.valid <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.store_data_bypass_m <= lsu_pkt_r_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.load_ldst_bypass_d <= lsu_pkt_r_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.store_data_bypass_d <= lsu_pkt_r_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.dma <= lsu_pkt_r_in.dma @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.unsign <= lsu_pkt_r_in.unsign @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.store <= lsu_pkt_r_in.store @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.load <= lsu_pkt_r_in.load @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.dword <= lsu_pkt_r_in.dword @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.word <= lsu_pkt_r_in.word @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.half <= lsu_pkt_r_in.half @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.by <= lsu_pkt_r_in.by @[el2_lsu_lsc_ctl.scala 310:26] - _T_93.fast_int <= lsu_pkt_r_in.fast_int @[el2_lsu_lsc_ctl.scala 310:26] - io.lsu_pkt_r.valid <= _T_93.valid @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.store_data_bypass_m <= _T_93.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.load_ldst_bypass_d <= _T_93.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.store_data_bypass_d <= _T_93.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.dma <= _T_93.dma @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.unsign <= _T_93.unsign @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.store <= _T_93.store @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.load <= _T_93.load @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.dword <= _T_93.dword @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.word <= _T_93.word @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.half <= _T_93.half @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.by <= _T_93.by @[el2_lsu_lsc_ctl.scala 310:16] - io.lsu_pkt_r.fast_int <= _T_93.fast_int @[el2_lsu_lsc_ctl.scala 310:16] - node _T_94 = bits(io.dma_mem_wdata, 63, 0) @[el2_lsu_lsc_ctl.scala 326:47] - node _T_95 = bits(io.dma_mem_addr, 2, 0) @[el2_lsu_lsc_ctl.scala 326:76] - node _T_96 = cat(_T_95, UInt<1>("h00")) @[Cat.scala 29:58] - node dma_mem_wdata_shifted = dshr(_T_94, _T_96) @[el2_lsu_lsc_ctl.scala 326:54] - node _T_97 = bits(io.dma_dccm_req, 0, 0) @[el2_lsu_lsc_ctl.scala 328:51] - node _T_98 = bits(dma_mem_wdata_shifted, 31, 0) @[el2_lsu_lsc_ctl.scala 328:79] - node _T_99 = bits(io.exu_lsu_rs2_d, 31, 0) @[el2_lsu_lsc_ctl.scala 328:102] - node store_data_d = mux(_T_97, _T_98, _T_99) @[el2_lsu_lsc_ctl.scala 328:34] - node _T_100 = bits(io.lsu_pkt_d.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 330:68] - node _T_101 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 330:90] - node _T_102 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 330:109] - node store_data_m_in = mux(_T_100, _T_101, _T_102) @[el2_lsu_lsc_ctl.scala 330:34] - inst sdmff of rvdff_6 @[el2_lsu_lsc_ctl.scala 333:20] - sdmff.clock <= clock - sdmff.reset <= reset - sdmff.io.din <= store_data_m_in @[el2_lsu_lsc_ctl.scala 334:27] - inst samff of rvdff_7 @[el2_lsu_lsc_ctl.scala 337:20] - samff.clock <= clock - samff.reset <= reset - samff.io.din <= io.lsu_addr_d @[el2_lsu_lsc_ctl.scala 338:23] - io.lsu_addr_m <= samff.io.dout @[el2_lsu_lsc_ctl.scala 339:26] - inst sarff of rvdff_8 @[el2_lsu_lsc_ctl.scala 341:20] - sarff.clock <= clock - sarff.reset <= reset - sarff.io.din <= io.lsu_addr_m @[el2_lsu_lsc_ctl.scala 342:23] - io.lsu_addr_r <= sarff.io.dout @[el2_lsu_lsc_ctl.scala 343:23] - inst end_addr_mff of rvdff_9 @[el2_lsu_lsc_ctl.scala 345:28] - end_addr_mff.clock <= clock - end_addr_mff.reset <= reset - end_addr_mff.io.din <= io.end_addr_d @[el2_lsu_lsc_ctl.scala 346:26] - io.end_addr_m <= end_addr_mff.io.dout @[el2_lsu_lsc_ctl.scala 347:26] - inst end_addr_rff of rvdff_10 @[el2_lsu_lsc_ctl.scala 349:28] - end_addr_rff.clock <= clock - end_addr_rff.reset <= reset - end_addr_rff.io.din <= io.end_addr_m @[el2_lsu_lsc_ctl.scala 350:26] - io.end_addr_r <= end_addr_rff.io.dout @[el2_lsu_lsc_ctl.scala 351:26] - inst addr_in_dccm_mff of rvdff_11 @[el2_lsu_lsc_ctl.scala 353:36] - addr_in_dccm_mff.clock <= clock - addr_in_dccm_mff.reset <= reset - addr_in_dccm_mff.io.din <= io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 354:27] - io.addr_in_dccm_m <= addr_in_dccm_mff.io.dout @[el2_lsu_lsc_ctl.scala 355:27] - inst addr_in_dccm_rff of rvdff_12 @[el2_lsu_lsc_ctl.scala 357:37] - addr_in_dccm_rff.clock <= clock - addr_in_dccm_rff.reset <= reset - addr_in_dccm_rff.io.din <= io.addr_in_dccm_m @[el2_lsu_lsc_ctl.scala 358:28] - io.addr_in_dccm_r <= addr_in_dccm_rff.io.dout @[el2_lsu_lsc_ctl.scala 359:28] - inst addr_in_pic_mff of rvdff_13 @[el2_lsu_lsc_ctl.scala 361:37] - addr_in_pic_mff.clock <= clock - addr_in_pic_mff.reset <= reset - addr_in_pic_mff.io.din <= io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 362:27] - io.addr_in_pic_m <= addr_in_pic_mff.io.dout @[el2_lsu_lsc_ctl.scala 363:27] - inst addr_in_pic_rff of rvdff_14 @[el2_lsu_lsc_ctl.scala 365:37] - addr_in_pic_rff.clock <= clock - addr_in_pic_rff.reset <= reset - addr_in_pic_rff.io.din <= io.addr_in_pic_m @[el2_lsu_lsc_ctl.scala 366:27] - io.addr_in_pic_r <= addr_in_pic_rff.io.dout @[el2_lsu_lsc_ctl.scala 367:27] - inst addr_external_mff of rvdff_15 @[el2_lsu_lsc_ctl.scala 369:37] - addr_external_mff.clock <= clock - addr_external_mff.reset <= reset - addr_external_mff.io.din <= addrcheck.io.addr_external_d @[el2_lsu_lsc_ctl.scala 370:28] - io.addr_external_m <= addr_external_mff.io.dout @[el2_lsu_lsc_ctl.scala 371:28] - inst addr_external_rff of rvdff_16 @[el2_lsu_lsc_ctl.scala 373:37] - addr_external_rff.clock <= clock - addr_external_rff.reset <= reset - addr_external_rff.io.din <= io.addr_external_m @[el2_lsu_lsc_ctl.scala 374:28] - inst bus_read_data_r_ff of rvdff_17 @[el2_lsu_lsc_ctl.scala 377:38] - bus_read_data_r_ff.clock <= clock - bus_read_data_r_ff.reset <= reset - bus_read_data_r_ff.io.din <= io.bus_read_data_m @[el2_lsu_lsc_ctl.scala 378:29] - node _T_103 = bits(io.lsu_ld_data_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 384:52] - io.lsu_fir_addr <= _T_103 @[el2_lsu_lsc_ctl.scala 384:28] - io.lsu_addr_d <= lsadder.io.dout @[el2_lsu_lsc_ctl.scala 387:28] - node _T_104 = or(io.lsu_pkt_r.store, io.lsu_pkt_r.load) @[el2_lsu_lsc_ctl.scala 391:63] - node _T_105 = and(io.lsu_pkt_r.valid, _T_104) @[el2_lsu_lsc_ctl.scala 391:41] - node _T_106 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 391:86] - node _T_107 = and(_T_105, _T_106) @[el2_lsu_lsc_ctl.scala 391:84] - node _T_108 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 391:100] - node _T_109 = and(_T_107, _T_108) @[el2_lsu_lsc_ctl.scala 391:98] - io.lsu_commit_r <= _T_109 @[el2_lsu_lsc_ctl.scala 391:19] - node _T_110 = bits(io.picm_mask_data_m, 31, 0) @[el2_lsu_lsc_ctl.scala 394:52] - node _T_111 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 394:69] - node _T_112 = bits(_T_111, 0, 0) @[Bitwise.scala 72:15] - node _T_113 = mux(_T_112, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_114 = or(_T_110, _T_113) @[el2_lsu_lsc_ctl.scala 394:59] - node _T_115 = bits(io.lsu_pkt_m.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 394:128] - node _T_116 = mux(_T_115, io.lsu_result_m, sdmff.io.dout) @[el2_lsu_lsc_ctl.scala 394:94] - node _T_117 = and(_T_114, _T_116) @[el2_lsu_lsc_ctl.scala 394:89] - io.store_data_m <= _T_117 @[el2_lsu_lsc_ctl.scala 394:29] - node _T_118 = bits(io.addr_external_m, 0, 0) @[el2_lsu_lsc_ctl.scala 425:53] - node _T_119 = mux(_T_118, io.bus_read_data_m, io.lsu_ld_data_m) @[el2_lsu_lsc_ctl.scala 425:33] - lsu_ld_datafn_m <= _T_119 @[el2_lsu_lsc_ctl.scala 425:27] - node _T_120 = bits(addr_external_rff.io.dout, 0, 0) @[el2_lsu_lsc_ctl.scala 426:50] - node _T_121 = mux(_T_120, bus_read_data_r_ff.io.dout, io.lsu_ld_data_corr_r) @[el2_lsu_lsc_ctl.scala 426:33] - lsu_ld_datafn_corr_r <= _T_121 @[el2_lsu_lsc_ctl.scala 426:27] - node _T_122 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 429:61] - node _T_123 = bits(_T_122, 0, 0) @[Bitwise.scala 72:15] - node _T_124 = mux(_T_123, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_125 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 429:117] - node _T_126 = cat(UInt<1>("h00"), _T_125) @[Cat.scala 29:58] - node _T_127 = and(_T_124, _T_126) @[el2_lsu_lsc_ctl.scala 429:84] - node _T_128 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 430:38] - node _T_129 = bits(_T_128, 0, 0) @[Bitwise.scala 72:15] - node _T_130 = mux(_T_129, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_131 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 430:92] - node _T_132 = cat(UInt<1>("h00"), _T_131) @[Cat.scala 29:58] - node _T_133 = and(_T_130, _T_132) @[el2_lsu_lsc_ctl.scala 430:61] - node _T_134 = or(_T_127, _T_133) @[el2_lsu_lsc_ctl.scala 429:125] - node _T_135 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 431:17] - node _T_136 = and(_T_135, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 431:38] - node _T_137 = bits(_T_136, 0, 0) @[Bitwise.scala 72:15] - node _T_138 = mux(_T_137, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_139 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 431:92] - node _T_140 = bits(_T_139, 0, 0) @[Bitwise.scala 72:15] - node _T_141 = mux(_T_140, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_142 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 431:115] - node _T_143 = cat(_T_141, _T_142) @[Cat.scala 29:58] - node _T_144 = and(_T_138, _T_143) @[el2_lsu_lsc_ctl.scala 431:61] - node _T_145 = or(_T_134, _T_144) @[el2_lsu_lsc_ctl.scala 430:104] - node _T_146 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 432:17] - node _T_147 = and(_T_146, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 432:38] - node _T_148 = bits(_T_147, 0, 0) @[Bitwise.scala 72:15] - node _T_149 = mux(_T_148, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_150 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 432:91] - node _T_151 = bits(_T_150, 0, 0) @[Bitwise.scala 72:15] - node _T_152 = mux(_T_151, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_153 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 432:115] - node _T_154 = cat(_T_152, _T_153) @[Cat.scala 29:58] - node _T_155 = and(_T_149, _T_154) @[el2_lsu_lsc_ctl.scala 432:61] - node _T_156 = or(_T_145, _T_155) @[el2_lsu_lsc_ctl.scala 431:124] - node _T_157 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] - node _T_158 = mux(_T_157, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_159 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 433:55] - node _T_160 = and(_T_158, _T_159) @[el2_lsu_lsc_ctl.scala 433:38] - node _T_161 = or(_T_156, _T_160) @[el2_lsu_lsc_ctl.scala 432:124] - io.lsu_result_m <= _T_161 @[el2_lsu_lsc_ctl.scala 429:27] - node _T_162 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 436:61] - node _T_163 = bits(_T_162, 0, 0) @[Bitwise.scala 72:15] - node _T_164 = mux(_T_163, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_165 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 436:122] - node _T_166 = cat(UInt<1>("h00"), _T_165) @[Cat.scala 29:58] - node _T_167 = and(_T_164, _T_166) @[el2_lsu_lsc_ctl.scala 436:84] - node _T_168 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 437:38] - node _T_169 = bits(_T_168, 0, 0) @[Bitwise.scala 72:15] - node _T_170 = mux(_T_169, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_171 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 437:97] - node _T_172 = cat(UInt<1>("h00"), _T_171) @[Cat.scala 29:58] - node _T_173 = and(_T_170, _T_172) @[el2_lsu_lsc_ctl.scala 437:61] - node _T_174 = or(_T_167, _T_173) @[el2_lsu_lsc_ctl.scala 436:130] - node _T_175 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 438:17] - node _T_176 = and(_T_175, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 438:38] - node _T_177 = bits(_T_176, 0, 0) @[Bitwise.scala 72:15] - node _T_178 = mux(_T_177, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_179 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 438:97] - node _T_180 = bits(_T_179, 0, 0) @[Bitwise.scala 72:15] - node _T_181 = mux(_T_180, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_182 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 438:125] - node _T_183 = cat(_T_181, _T_182) @[Cat.scala 29:58] - node _T_184 = and(_T_178, _T_183) @[el2_lsu_lsc_ctl.scala 438:61] - node _T_185 = or(_T_174, _T_184) @[el2_lsu_lsc_ctl.scala 437:109] - node _T_186 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 439:17] - node _T_187 = and(_T_186, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 439:38] - node _T_188 = bits(_T_187, 0, 0) @[Bitwise.scala 72:15] - node _T_189 = mux(_T_188, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_190 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 439:96] - node _T_191 = bits(_T_190, 0, 0) @[Bitwise.scala 72:15] - node _T_192 = mux(_T_191, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_193 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 439:125] - node _T_194 = cat(_T_192, _T_193) @[Cat.scala 29:58] - node _T_195 = and(_T_189, _T_194) @[el2_lsu_lsc_ctl.scala 439:61] - node _T_196 = or(_T_185, _T_195) @[el2_lsu_lsc_ctl.scala 438:134] - node _T_197 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] - node _T_198 = mux(_T_197, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_199 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 440:60] - node _T_200 = and(_T_198, _T_199) @[el2_lsu_lsc_ctl.scala 440:38] - node _T_201 = or(_T_196, _T_200) @[el2_lsu_lsc_ctl.scala 439:134] - io.lsu_result_corr_r <= _T_201 @[el2_lsu_lsc_ctl.scala 436:27] + node _T_116 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[el2_lsu_lsc_ctl.scala 207:50] + node _T_117 = mux(_T_116, io.lsu_p, dma_pkt_d) @[el2_lsu_lsc_ctl.scala 207:26] + io.lsu_pkt_d.valid <= _T_117.valid @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.store_data_bypass_m <= _T_117.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.load_ldst_bypass_d <= _T_117.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.store_data_bypass_d <= _T_117.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.dma <= _T_117.dma @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.unsign <= _T_117.unsign @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.store <= _T_117.store @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.load <= _T_117.load @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.dword <= _T_117.dword @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.word <= _T_117.word @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.half <= _T_117.half @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.by <= _T_117.by @[el2_lsu_lsc_ctl.scala 207:20] + io.lsu_pkt_d.fast_int <= _T_117.fast_int @[el2_lsu_lsc_ctl.scala 207:20] + lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.store_data_bypass_m <= io.lsu_pkt_d.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.load_ldst_bypass_d <= io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.store_data_bypass_d <= io.lsu_pkt_d.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.dma <= io.lsu_pkt_d.dma @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.unsign <= io.lsu_pkt_d.unsign @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.store <= io.lsu_pkt_d.store @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.load <= io.lsu_pkt_d.load @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.dword <= io.lsu_pkt_d.dword @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.word <= io.lsu_pkt_d.word @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.half <= io.lsu_pkt_d.half @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.by <= io.lsu_pkt_d.by @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_m_in.fast_int <= io.lsu_pkt_d.fast_int @[el2_lsu_lsc_ctl.scala 208:20] + lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.dma <= io.lsu_pkt_m.dma @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.store <= io.lsu_pkt_m.store @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.load <= io.lsu_pkt_m.load @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.dword <= io.lsu_pkt_m.dword @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.word <= io.lsu_pkt_m.word @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.half <= io.lsu_pkt_m.half @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.by <= io.lsu_pkt_m.by @[el2_lsu_lsc_ctl.scala 209:20] + lsu_pkt_r_in.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_lsc_ctl.scala 209:20] + node _T_118 = eq(io.lsu_p.fast_int, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:64] + node _T_119 = and(io.flush_m_up, _T_118) @[el2_lsu_lsc_ctl.scala 211:61] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 211:45] + node _T_121 = and(io.lsu_p.valid, _T_120) @[el2_lsu_lsc_ctl.scala 211:43] + node _T_122 = or(_T_121, io.dma_dccm_req) @[el2_lsu_lsc_ctl.scala 211:85] + io.lsu_pkt_d.valid <= _T_122 @[el2_lsu_lsc_ctl.scala 211:24] + node _T_123 = eq(io.lsu_pkt_d.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:68] + node _T_124 = and(io.flush_m_up, _T_123) @[el2_lsu_lsc_ctl.scala 212:65] + node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 212:49] + node _T_126 = and(io.lsu_pkt_d.valid, _T_125) @[el2_lsu_lsc_ctl.scala 212:47] + lsu_pkt_m_in.valid <= _T_126 @[el2_lsu_lsc_ctl.scala 212:24] + node _T_127 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:68] + node _T_128 = and(io.flush_m_up, _T_127) @[el2_lsu_lsc_ctl.scala 213:65] + node _T_129 = eq(_T_128, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 213:49] + node _T_130 = and(io.lsu_pkt_m.valid, _T_129) @[el2_lsu_lsc_ctl.scala 213:47] + lsu_pkt_r_in.valid <= _T_130 @[el2_lsu_lsc_ctl.scala 213:24] + wire _T_131 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + _T_131.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 215:91] + reg _T_132 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_m_clk with : (reset => (reset, _T_131)) @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.valid <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.store_data_bypass_m <= lsu_pkt_m_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.load_ldst_bypass_d <= lsu_pkt_m_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.store_data_bypass_d <= lsu_pkt_m_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.dma <= lsu_pkt_m_in.dma @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.unsign <= lsu_pkt_m_in.unsign @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.store <= lsu_pkt_m_in.store @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.load <= lsu_pkt_m_in.load @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.dword <= lsu_pkt_m_in.dword @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.word <= lsu_pkt_m_in.word @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.half <= lsu_pkt_m_in.half @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.by <= lsu_pkt_m_in.by @[el2_lsu_lsc_ctl.scala 215:65] + _T_132.fast_int <= lsu_pkt_m_in.fast_int @[el2_lsu_lsc_ctl.scala 215:65] + io.lsu_pkt_m.valid <= _T_132.valid @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.store_data_bypass_m <= _T_132.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.load_ldst_bypass_d <= _T_132.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.store_data_bypass_d <= _T_132.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.dma <= _T_132.dma @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.unsign <= _T_132.unsign @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.store <= _T_132.store @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.load <= _T_132.load @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.dword <= _T_132.dword @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.word <= _T_132.word @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.half <= _T_132.half @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.by <= _T_132.by @[el2_lsu_lsc_ctl.scala 215:28] + io.lsu_pkt_m.fast_int <= _T_132.fast_int @[el2_lsu_lsc_ctl.scala 215:28] + wire _T_133 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>} @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.valid <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.store_data_bypass_m <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.load_ldst_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.store_data_bypass_d <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.dma <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.unsign <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.store <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.load <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.dword <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.word <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.half <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.by <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + _T_133.fast_int <= UInt<1>("h00") @[el2_lsu_lsc_ctl.scala 216:91] + reg _T_134 : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, io.lsu_c1_r_clk with : (reset => (reset, _T_133)) @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.valid <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.store_data_bypass_m <= lsu_pkt_r_in.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.load_ldst_bypass_d <= lsu_pkt_r_in.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.store_data_bypass_d <= lsu_pkt_r_in.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.dma <= lsu_pkt_r_in.dma @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.unsign <= lsu_pkt_r_in.unsign @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.store <= lsu_pkt_r_in.store @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.load <= lsu_pkt_r_in.load @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.dword <= lsu_pkt_r_in.dword @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.word <= lsu_pkt_r_in.word @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.half <= lsu_pkt_r_in.half @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.by <= lsu_pkt_r_in.by @[el2_lsu_lsc_ctl.scala 216:65] + _T_134.fast_int <= lsu_pkt_r_in.fast_int @[el2_lsu_lsc_ctl.scala 216:65] + io.lsu_pkt_r.valid <= _T_134.valid @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.store_data_bypass_m <= _T_134.store_data_bypass_m @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.load_ldst_bypass_d <= _T_134.load_ldst_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.store_data_bypass_d <= _T_134.store_data_bypass_d @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.dma <= _T_134.dma @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.unsign <= _T_134.unsign @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.store <= _T_134.store @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.load <= _T_134.load @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.dword <= _T_134.dword @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.word <= _T_134.word @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.half <= _T_134.half @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.by <= _T_134.by @[el2_lsu_lsc_ctl.scala 216:28] + io.lsu_pkt_r.fast_int <= _T_134.fast_int @[el2_lsu_lsc_ctl.scala 216:28] + reg _T_135 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 217:65] + _T_135 <= lsu_pkt_m_in.valid @[el2_lsu_lsc_ctl.scala 217:65] + io.lsu_pkt_m.valid <= _T_135 @[el2_lsu_lsc_ctl.scala 217:28] + reg _T_136 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 218:65] + _T_136 <= lsu_pkt_r_in.valid @[el2_lsu_lsc_ctl.scala 218:65] + io.lsu_pkt_r.valid <= _T_136 @[el2_lsu_lsc_ctl.scala 218:28] + node _T_137 = bits(io.dma_mem_wdata, 63, 0) @[el2_lsu_lsc_ctl.scala 220:47] + node _T_138 = bits(io.dma_mem_addr, 2, 0) @[el2_lsu_lsc_ctl.scala 220:76] + node _T_139 = cat(_T_138, UInt<3>("h00")) @[Cat.scala 29:58] + node dma_mem_wdata_shifted = dshr(_T_137, _T_139) @[el2_lsu_lsc_ctl.scala 220:54] + node _T_140 = bits(io.dma_dccm_req, 0, 0) @[el2_lsu_lsc_ctl.scala 221:51] + node _T_141 = bits(dma_mem_wdata_shifted, 31, 0) @[el2_lsu_lsc_ctl.scala 221:79] + node _T_142 = bits(io.exu_lsu_rs2_d, 31, 0) @[el2_lsu_lsc_ctl.scala 221:102] + node store_data_d = mux(_T_140, _T_141, _T_142) @[el2_lsu_lsc_ctl.scala 221:34] + node _T_143 = bits(io.lsu_pkt_d.store_data_bypass_d, 0, 0) @[el2_lsu_lsc_ctl.scala 222:68] + node _T_144 = bits(io.lsu_result_m, 31, 0) @[el2_lsu_lsc_ctl.scala 222:90] + node _T_145 = bits(store_data_d, 31, 0) @[el2_lsu_lsc_ctl.scala 222:109] + node store_data_m_in = mux(_T_143, _T_144, _T_145) @[el2_lsu_lsc_ctl.scala 222:34] + reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 224:72] + store_data_pre_m <= store_data_m_in @[el2_lsu_lsc_ctl.scala 224:72] + reg _T_146 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 225:62] + _T_146 <= io.lsu_addr_d @[el2_lsu_lsc_ctl.scala 225:62] + io.lsu_addr_m <= _T_146 @[el2_lsu_lsc_ctl.scala 225:24] + reg _T_147 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 226:62] + _T_147 <= io.lsu_addr_m @[el2_lsu_lsc_ctl.scala 226:62] + io.lsu_addr_r <= _T_147 @[el2_lsu_lsc_ctl.scala 226:24] + reg _T_148 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 227:62] + _T_148 <= io.end_addr_d @[el2_lsu_lsc_ctl.scala 227:62] + io.end_addr_m <= _T_148 @[el2_lsu_lsc_ctl.scala 227:24] + reg _T_149 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 228:62] + _T_149 <= io.end_addr_m @[el2_lsu_lsc_ctl.scala 228:62] + io.end_addr_r <= _T_149 @[el2_lsu_lsc_ctl.scala 228:24] + reg _T_150 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 229:62] + _T_150 <= io.addr_in_dccm_d @[el2_lsu_lsc_ctl.scala 229:62] + io.addr_in_dccm_m <= _T_150 @[el2_lsu_lsc_ctl.scala 229:24] + reg _T_151 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 230:62] + _T_151 <= io.addr_in_dccm_m @[el2_lsu_lsc_ctl.scala 230:62] + io.addr_in_dccm_r <= _T_151 @[el2_lsu_lsc_ctl.scala 230:24] + reg _T_152 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 231:62] + _T_152 <= io.addr_in_pic_d @[el2_lsu_lsc_ctl.scala 231:62] + io.addr_in_pic_m <= _T_152 @[el2_lsu_lsc_ctl.scala 231:24] + reg _T_153 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 232:62] + _T_153 <= io.addr_in_pic_m @[el2_lsu_lsc_ctl.scala 232:62] + io.addr_in_pic_r <= _T_153 @[el2_lsu_lsc_ctl.scala 232:24] + reg _T_154 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 233:62] + _T_154 <= addrcheck.io.addr_external_d @[el2_lsu_lsc_ctl.scala 233:62] + io.addr_external_m <= _T_154 @[el2_lsu_lsc_ctl.scala 233:24] + reg addr_external_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 234:66] + addr_external_r <= io.addr_external_m @[el2_lsu_lsc_ctl.scala 234:66] + reg bus_read_data_r : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_lsc_ctl.scala 235:66] + bus_read_data_r <= io.bus_read_data_m @[el2_lsu_lsc_ctl.scala 235:66] + node _T_155 = bits(io.lsu_ld_data_corr_r, 31, 1) @[el2_lsu_lsc_ctl.scala 237:52] + io.lsu_fir_addr <= _T_155 @[el2_lsu_lsc_ctl.scala 237:28] + io.lsu_addr_d <= full_addr_d @[el2_lsu_lsc_ctl.scala 239:28] + node _T_156 = or(io.lsu_pkt_r.store, io.lsu_pkt_r.load) @[el2_lsu_lsc_ctl.scala 241:63] + node _T_157 = and(io.lsu_pkt_r.valid, _T_156) @[el2_lsu_lsc_ctl.scala 241:41] + node _T_158 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:86] + node _T_159 = and(_T_157, _T_158) @[el2_lsu_lsc_ctl.scala 241:84] + node _T_160 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 241:100] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_lsc_ctl.scala 241:98] + io.lsu_commit_r <= _T_161 @[el2_lsu_lsc_ctl.scala 241:19] + node _T_162 = bits(io.picm_mask_data_m, 31, 0) @[el2_lsu_lsc_ctl.scala 242:52] + node _T_163 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 242:69] + node _T_164 = bits(_T_163, 0, 0) @[Bitwise.scala 72:15] + node _T_165 = mux(_T_164, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_166 = or(_T_162, _T_165) @[el2_lsu_lsc_ctl.scala 242:59] + node _T_167 = bits(io.lsu_pkt_m.store_data_bypass_m, 0, 0) @[el2_lsu_lsc_ctl.scala 242:128] + node _T_168 = mux(_T_167, io.lsu_result_m, store_data_pre_m) @[el2_lsu_lsc_ctl.scala 242:94] + node _T_169 = and(_T_166, _T_168) @[el2_lsu_lsc_ctl.scala 242:89] + io.store_data_m <= _T_169 @[el2_lsu_lsc_ctl.scala 242:29] + node _T_170 = bits(io.addr_external_m, 0, 0) @[el2_lsu_lsc_ctl.scala 263:53] + node _T_171 = mux(_T_170, io.bus_read_data_m, io.lsu_ld_data_m) @[el2_lsu_lsc_ctl.scala 263:33] + lsu_ld_datafn_m <= _T_171 @[el2_lsu_lsc_ctl.scala 263:27] + node _T_172 = eq(addr_external_r, UInt<1>("h01")) @[el2_lsu_lsc_ctl.scala 264:49] + node _T_173 = mux(_T_172, bus_read_data_r, io.lsu_ld_data_corr_r) @[el2_lsu_lsc_ctl.scala 264:33] + lsu_ld_datafn_corr_r <= _T_173 @[el2_lsu_lsc_ctl.scala 264:27] + node _T_174 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 265:61] + node _T_175 = bits(_T_174, 0, 0) @[Bitwise.scala 72:15] + node _T_176 = mux(_T_175, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_177 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 265:115] + node _T_178 = cat(UInt<24>("h00"), _T_177) @[Cat.scala 29:58] + node _T_179 = and(_T_176, _T_178) @[el2_lsu_lsc_ctl.scala 265:84] + node _T_180 = and(io.lsu_pkt_m.unsign, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 266:38] + node _T_181 = bits(_T_180, 0, 0) @[Bitwise.scala 72:15] + node _T_182 = mux(_T_181, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_183 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 266:92] + node _T_184 = cat(UInt<16>("h00"), _T_183) @[Cat.scala 29:58] + node _T_185 = and(_T_182, _T_184) @[el2_lsu_lsc_ctl.scala 266:61] + node _T_186 = or(_T_179, _T_185) @[el2_lsu_lsc_ctl.scala 265:123] + node _T_187 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 267:17] + node _T_188 = and(_T_187, io.lsu_pkt_m.by) @[el2_lsu_lsc_ctl.scala 267:38] + node _T_189 = bits(_T_188, 0, 0) @[Bitwise.scala 72:15] + node _T_190 = mux(_T_189, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_191 = bits(lsu_ld_datafn_m, 7, 7) @[el2_lsu_lsc_ctl.scala 267:92] + node _T_192 = bits(_T_191, 0, 0) @[Bitwise.scala 72:15] + node _T_193 = mux(_T_192, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_194 = bits(lsu_ld_datafn_m, 7, 0) @[el2_lsu_lsc_ctl.scala 267:115] + node _T_195 = cat(_T_193, _T_194) @[Cat.scala 29:58] + node _T_196 = and(_T_190, _T_195) @[el2_lsu_lsc_ctl.scala 267:61] + node _T_197 = or(_T_186, _T_196) @[el2_lsu_lsc_ctl.scala 266:104] + node _T_198 = eq(io.lsu_pkt_m.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 268:17] + node _T_199 = and(_T_198, io.lsu_pkt_m.half) @[el2_lsu_lsc_ctl.scala 268:38] + node _T_200 = bits(_T_199, 0, 0) @[Bitwise.scala 72:15] + node _T_201 = mux(_T_200, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_202 = bits(lsu_ld_datafn_m, 15, 15) @[el2_lsu_lsc_ctl.scala 268:91] + node _T_203 = bits(_T_202, 0, 0) @[Bitwise.scala 72:15] + node _T_204 = mux(_T_203, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_205 = bits(lsu_ld_datafn_m, 15, 0) @[el2_lsu_lsc_ctl.scala 268:115] + node _T_206 = cat(_T_204, _T_205) @[Cat.scala 29:58] + node _T_207 = and(_T_201, _T_206) @[el2_lsu_lsc_ctl.scala 268:61] + node _T_208 = or(_T_197, _T_207) @[el2_lsu_lsc_ctl.scala 267:124] + node _T_209 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] + node _T_210 = mux(_T_209, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_211 = bits(lsu_ld_datafn_m, 31, 0) @[el2_lsu_lsc_ctl.scala 269:55] + node _T_212 = and(_T_210, _T_211) @[el2_lsu_lsc_ctl.scala 269:38] + node _T_213 = or(_T_208, _T_212) @[el2_lsu_lsc_ctl.scala 268:124] + io.lsu_result_m <= _T_213 @[el2_lsu_lsc_ctl.scala 265:27] + node _T_214 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 270:61] + node _T_215 = bits(_T_214, 0, 0) @[Bitwise.scala 72:15] + node _T_216 = mux(_T_215, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_217 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 270:120] + node _T_218 = cat(UInt<24>("h00"), _T_217) @[Cat.scala 29:58] + node _T_219 = and(_T_216, _T_218) @[el2_lsu_lsc_ctl.scala 270:84] + node _T_220 = and(io.lsu_pkt_r.unsign, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 271:38] + node _T_221 = bits(_T_220, 0, 0) @[Bitwise.scala 72:15] + node _T_222 = mux(_T_221, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_223 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 271:97] + node _T_224 = cat(UInt<16>("h00"), _T_223) @[Cat.scala 29:58] + node _T_225 = and(_T_222, _T_224) @[el2_lsu_lsc_ctl.scala 271:61] + node _T_226 = or(_T_219, _T_225) @[el2_lsu_lsc_ctl.scala 270:128] + node _T_227 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 272:17] + node _T_228 = and(_T_227, io.lsu_pkt_r.by) @[el2_lsu_lsc_ctl.scala 272:38] + node _T_229 = bits(_T_228, 0, 0) @[Bitwise.scala 72:15] + node _T_230 = mux(_T_229, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_231 = bits(lsu_ld_datafn_corr_r, 7, 7) @[el2_lsu_lsc_ctl.scala 272:97] + node _T_232 = bits(_T_231, 0, 0) @[Bitwise.scala 72:15] + node _T_233 = mux(_T_232, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_234 = bits(lsu_ld_datafn_corr_r, 7, 0) @[el2_lsu_lsc_ctl.scala 272:125] + node _T_235 = cat(_T_233, _T_234) @[Cat.scala 29:58] + node _T_236 = and(_T_230, _T_235) @[el2_lsu_lsc_ctl.scala 272:61] + node _T_237 = or(_T_226, _T_236) @[el2_lsu_lsc_ctl.scala 271:109] + node _T_238 = eq(io.lsu_pkt_r.unsign, UInt<1>("h00")) @[el2_lsu_lsc_ctl.scala 273:17] + node _T_239 = and(_T_238, io.lsu_pkt_r.half) @[el2_lsu_lsc_ctl.scala 273:38] + node _T_240 = bits(_T_239, 0, 0) @[Bitwise.scala 72:15] + node _T_241 = mux(_T_240, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_242 = bits(lsu_ld_datafn_corr_r, 15, 15) @[el2_lsu_lsc_ctl.scala 273:96] + node _T_243 = bits(_T_242, 0, 0) @[Bitwise.scala 72:15] + node _T_244 = mux(_T_243, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_245 = bits(lsu_ld_datafn_corr_r, 15, 0) @[el2_lsu_lsc_ctl.scala 273:125] + node _T_246 = cat(_T_244, _T_245) @[Cat.scala 29:58] + node _T_247 = and(_T_241, _T_246) @[el2_lsu_lsc_ctl.scala 273:61] + node _T_248 = or(_T_237, _T_247) @[el2_lsu_lsc_ctl.scala 272:134] + node _T_249 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] + node _T_250 = mux(_T_249, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_251 = bits(lsu_ld_datafn_corr_r, 31, 0) @[el2_lsu_lsc_ctl.scala 274:60] + node _T_252 = and(_T_250, _T_251) @[el2_lsu_lsc_ctl.scala 274:38] + node _T_253 = or(_T_248, _T_252) @[el2_lsu_lsc_ctl.scala 273:134] + io.lsu_result_corr_r <= _T_253 @[el2_lsu_lsc_ctl.scala 270:27] - extmodule TEC_RV_ICG : + extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr : @@ -1032,23 +795,23 @@ circuit el2_lsu : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG @[beh_lib.scala 331:24] + inst clkhdr of gated_latch @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_1 : + extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_1 : @@ -1056,30 +819,34 @@ circuit el2_lsu : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_dccm_ctl : input clock : Clock input reset : AsyncReset - output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip clk : Clock, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<16>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_rd_addr_lo : UInt<16>, flip dccm_rd_data_lo : UInt<39>, dccm_wr_addr_hi : UInt<16>, dccm_wr_data_hi : UInt<39>, dccm_rd_addr_hi : UInt<16>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, flip scan_mode : UInt<1>} + output io : {flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_store_c1_r_clk : Clock, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip addr_in_dccm_d : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip addr_in_pic_d : UInt<1>, flip addr_in_pic_m : UInt<1>, flip addr_in_pic_r : UInt<1>, flip lsu_raw_fwd_lo_r : UInt<1>, flip lsu_raw_fwd_hi_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<16>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<16>, flip end_addr_r : UInt<16>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_addr_any : UInt<16>, flip stbuf_data_any : UInt<32>, flip stbuf_ecc_any : UInt<7>, flip stbuf_fwddata_hi_m : UInt<32>, flip stbuf_fwddata_lo_m : UInt<32>, flip stbuf_fwdbyteen_lo_m : UInt<4>, flip stbuf_fwdbyteen_hi_m : UInt<4>, dccm_rdata_hi_r : UInt<32>, dccm_rdata_lo_r : UInt<32>, dccm_data_ecc_hi_r : UInt<7>, dccm_data_ecc_lo_r : UInt<7>, lsu_ld_data_r : UInt<32>, lsu_ld_data_corr_r : UInt<32>, flip lsu_double_ecc_error_r : UInt<1>, flip single_ecc_error_hi_r : UInt<1>, flip single_ecc_error_lo_r : UInt<1>, flip sec_data_hi_r : UInt<32>, flip sec_data_lo_r : UInt<32>, flip sec_data_hi_r_ff : UInt<32>, flip sec_data_lo_r_ff : UInt<32>, flip sec_data_ecc_hi_r_ff : UInt<7>, flip sec_data_ecc_lo_r_ff : UInt<7>, dccm_rdata_hi_m : UInt<32>, dccm_rdata_lo_m : UInt<32>, dccm_data_ecc_hi_m : UInt<7>, dccm_data_ecc_lo_m : UInt<7>, lsu_ld_data_m : UInt<32>, flip lsu_double_ecc_error_m : UInt<1>, flip sec_data_hi_m : UInt<32>, flip sec_data_lo_m : UInt<32>, flip store_data_m : UInt<32>, flip dma_dccm_wen : UInt<1>, flip dma_pic_wen : UInt<1>, flip dma_mem_tag_m : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_wdata : UInt<64>, flip dma_dccm_wdata_lo : UInt<32>, flip dma_dccm_wdata_hi : UInt<32>, flip dma_dccm_wdata_ecc_hi : UInt<7>, flip dma_dccm_wdata_ecc_lo : UInt<7>, store_data_hi_r : UInt<32>, store_data_lo_r : UInt<32>, store_datafn_hi_r : UInt<32>, store_datafn_lo_r : UInt<32>, store_data_r : UInt<32>, ld_single_ecc_error_r : UInt<1>, ld_single_ecc_error_r_ff : UInt<1>, picm_mask_data_m : UInt<32>, lsu_stbuf_commit_any : UInt<1>, lsu_dccm_rden_m : UInt<1>, lsu_dccm_rden_r : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_rd_addr_lo : UInt<16>, flip dccm_rd_data_lo : UInt<39>, dccm_wr_addr_hi : UInt<16>, dccm_wr_data_hi : UInt<39>, dccm_rd_addr_hi : UInt<16>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, flip scan_mode : UInt<1>} node picm_rd_data_m = cat(io.picm_rd_data, io.picm_rd_data) @[Cat.scala 29:58] node dccm_rdata_corr_r = cat(io.sec_data_hi_r, io.sec_data_lo_r) @[Cat.scala 29:58] node dccm_rdata_corr_m = cat(io.sec_data_hi_m, io.sec_data_lo_m) @[Cat.scala 29:58] node dccm_rdata_r = cat(io.dccm_rdata_hi_r, io.dccm_rdata_lo_r) @[Cat.scala 29:58] node dccm_rdata_m = cat(io.dccm_rdata_hi_m, io.dccm_rdata_lo_m) @[Cat.scala 29:58] - wire lsu_rdata_r : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 134:32] - wire lsu_rdata_m : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 135:32] - wire lsu_rdata_corr_r : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 136:32] - wire lsu_rdata_corr_m : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 137:32] + wire lsu_rdata_r : UInt<64> + lsu_rdata_r <= UInt<1>("h00") + wire lsu_rdata_m : UInt<64> + lsu_rdata_m <= UInt<1>("h00") + wire lsu_rdata_corr_r : UInt<64> + lsu_rdata_corr_r <= UInt<1>("h00") + wire lsu_rdata_corr_m : UInt<64> + lsu_rdata_corr_m <= UInt<1>("h00") wire stbuf_fwddata_r : UInt<64> stbuf_fwddata_r <= UInt<1>("h00") wire stbuf_fwdbyteen_r : UInt<64> @@ -1090,489 +857,1049 @@ circuit el2_lsu : picm_rd_data_r <= UInt<1>("h00") wire lsu_ld_data_corr_m : UInt<64> lsu_ld_data_corr_m <= UInt<1>("h00") - node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.load) @[el2_lsu_dccm_ctl.scala 168:50] - node _T_1 = and(_T, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 168:70] - io.dccm_dma_rvalid <= _T_1 @[el2_lsu_dccm_ctl.scala 168:28] - io.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[el2_lsu_dccm_ctl.scala 169:28] - node _T_2 = cat(lsu_rdata_corr_m[1], lsu_rdata_corr_m[0]) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_3 = cat(lsu_rdata_corr_m[3], lsu_rdata_corr_m[2]) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_4 = cat(_T_3, _T_2) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_5 = cat(lsu_rdata_corr_m[5], lsu_rdata_corr_m[4]) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_6 = cat(lsu_rdata_corr_m[7], lsu_rdata_corr_m[6]) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_7 = cat(_T_6, _T_5) @[el2_lsu_dccm_ctl.scala 170:48] - node _T_8 = cat(_T_7, _T_4) @[el2_lsu_dccm_ctl.scala 170:48] - io.dccm_dma_rdata <= _T_8 @[el2_lsu_dccm_ctl.scala 170:28] - io.dccm_dma_rtag <= io.dma_mem_tag_m @[el2_lsu_dccm_ctl.scala 171:28] - io.dccm_rdata_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 172:28] - io.dccm_rdata_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 173:28] - io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 174:28] - io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 175:28] - reg _T_9 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 178:65] - _T_9 <= lsu_ld_data_corr_m @[el2_lsu_dccm_ctl.scala 178:65] - io.lsu_ld_data_corr_r <= _T_9 @[el2_lsu_dccm_ctl.scala 178:28] - lsu_rdata_r[0] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[0] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_10 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_11 = bits(_T_10, 0, 0) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_12 = bits(_T_11, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_13 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_14 = bits(_T_13, 7, 0) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_15 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_16 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_17 = bits(dccm_rdata_corr_m, 7, 0) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_18 = mux(_T_15, _T_16, _T_17) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_19 = mux(_T_12, _T_14, _T_18) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[0] <= _T_19 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_20 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_21 = bits(_T_20, 0, 0) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_22 = bits(_T_21, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_23 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_24 = bits(_T_23, 7, 0) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_25 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_26 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_27 = bits(dccm_rdata_m, 7, 0) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_28 = mux(_T_25, _T_26, _T_27) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_29 = mux(_T_22, _T_24, _T_28) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[0] <= _T_29 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[1] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[1] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_30 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_31 = bits(_T_30, 1, 1) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_32 = bits(_T_31, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_33 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_34 = bits(_T_33, 15, 8) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_35 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_36 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_37 = bits(dccm_rdata_corr_m, 15, 8) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_38 = mux(_T_35, _T_36, _T_37) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_39 = mux(_T_32, _T_34, _T_38) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[1] <= _T_39 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_40 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_41 = bits(_T_40, 1, 1) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_42 = bits(_T_41, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_43 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_44 = bits(_T_43, 15, 8) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_45 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_46 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_47 = bits(dccm_rdata_m, 15, 8) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_48 = mux(_T_45, _T_46, _T_47) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_49 = mux(_T_42, _T_44, _T_48) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[1] <= _T_49 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[2] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[2] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_50 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_51 = bits(_T_50, 2, 2) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_52 = bits(_T_51, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_53 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_54 = bits(_T_53, 23, 16) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_55 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_56 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_57 = bits(dccm_rdata_corr_m, 23, 16) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_58 = mux(_T_55, _T_56, _T_57) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_59 = mux(_T_52, _T_54, _T_58) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[2] <= _T_59 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_60 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_61 = bits(_T_60, 2, 2) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_62 = bits(_T_61, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_63 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_64 = bits(_T_63, 23, 16) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_65 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_66 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_67 = bits(dccm_rdata_m, 23, 16) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_68 = mux(_T_65, _T_66, _T_67) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_69 = mux(_T_62, _T_64, _T_68) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[2] <= _T_69 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[3] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[3] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_70 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_71 = bits(_T_70, 3, 3) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_72 = bits(_T_71, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_73 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_74 = bits(_T_73, 31, 24) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_75 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_76 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_77 = bits(dccm_rdata_corr_m, 31, 24) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_78 = mux(_T_75, _T_76, _T_77) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_79 = mux(_T_72, _T_74, _T_78) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[3] <= _T_79 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_80 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_81 = bits(_T_80, 3, 3) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_82 = bits(_T_81, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_83 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_84 = bits(_T_83, 31, 24) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_85 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_86 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_87 = bits(dccm_rdata_m, 31, 24) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_88 = mux(_T_85, _T_86, _T_87) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_89 = mux(_T_82, _T_84, _T_88) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[3] <= _T_89 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[4] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[4] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_90 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_91 = bits(_T_90, 4, 4) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_92 = bits(_T_91, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_93 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_94 = bits(_T_93, 39, 32) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_95 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_96 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_97 = bits(dccm_rdata_corr_m, 39, 32) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_98 = mux(_T_95, _T_96, _T_97) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_99 = mux(_T_92, _T_94, _T_98) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[4] <= _T_99 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_100 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_101 = bits(_T_100, 4, 4) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_102 = bits(_T_101, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_103 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_104 = bits(_T_103, 39, 32) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_105 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_106 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_107 = bits(dccm_rdata_m, 39, 32) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_108 = mux(_T_105, _T_106, _T_107) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_109 = mux(_T_102, _T_104, _T_108) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[4] <= _T_109 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[5] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[5] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_110 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_111 = bits(_T_110, 5, 5) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_112 = bits(_T_111, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_113 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_114 = bits(_T_113, 47, 40) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_115 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_116 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_117 = bits(dccm_rdata_corr_m, 47, 40) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_118 = mux(_T_115, _T_116, _T_117) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_119 = mux(_T_112, _T_114, _T_118) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[5] <= _T_119 @[el2_lsu_dccm_ctl.scala 184:30] + node _T = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.load) @[el2_lsu_dccm_ctl.scala 161:50] + node _T_1 = and(_T, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 161:70] + io.dccm_dma_rvalid <= _T_1 @[el2_lsu_dccm_ctl.scala 161:28] + io.dccm_dma_ecc_error <= io.lsu_double_ecc_error_m @[el2_lsu_dccm_ctl.scala 162:28] + io.dccm_dma_rdata <= lsu_rdata_corr_m @[el2_lsu_dccm_ctl.scala 163:28] + io.dccm_dma_rtag <= io.dma_mem_tag_m @[el2_lsu_dccm_ctl.scala 164:28] + io.dccm_rdata_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 165:28] + io.dccm_rdata_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 166:28] + io.dccm_data_ecc_hi_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 167:28] + io.dccm_data_ecc_lo_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 168:28] + io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 169:28] + reg _T_2 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 171:65] + _T_2 <= lsu_ld_data_corr_m @[el2_lsu_dccm_ctl.scala 171:65] + io.lsu_ld_data_corr_r <= _T_2 @[el2_lsu_dccm_ctl.scala 171:28] + node _T_3 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_4 = bits(_T_3, 0, 0) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_5 = bits(_T_4, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_6 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_7 = bits(_T_6, 7, 0) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_8 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_9 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_10 = bits(dccm_rdata_corr_m, 7, 0) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_11 = mux(_T_8, _T_9, _T_10) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_12 = mux(_T_5, _T_7, _T_11) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_13 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_14 = xor(UInt<8>("h0ff"), _T_13) @[Bitwise.scala 102:21] + node _T_15 = shr(_T_12, 4) @[Bitwise.scala 103:21] + node _T_16 = and(_T_15, _T_14) @[Bitwise.scala 103:31] + node _T_17 = bits(_T_12, 3, 0) @[Bitwise.scala 103:46] + node _T_18 = shl(_T_17, 4) @[Bitwise.scala 103:65] + node _T_19 = not(_T_14) @[Bitwise.scala 103:77] + node _T_20 = and(_T_18, _T_19) @[Bitwise.scala 103:75] + node _T_21 = or(_T_16, _T_20) @[Bitwise.scala 103:39] + node _T_22 = bits(_T_14, 5, 0) @[Bitwise.scala 102:28] + node _T_23 = shl(_T_22, 2) @[Bitwise.scala 102:47] + node _T_24 = xor(_T_14, _T_23) @[Bitwise.scala 102:21] + node _T_25 = shr(_T_21, 2) @[Bitwise.scala 103:21] + node _T_26 = and(_T_25, _T_24) @[Bitwise.scala 103:31] + node _T_27 = bits(_T_21, 5, 0) @[Bitwise.scala 103:46] + node _T_28 = shl(_T_27, 2) @[Bitwise.scala 103:65] + node _T_29 = not(_T_24) @[Bitwise.scala 103:77] + node _T_30 = and(_T_28, _T_29) @[Bitwise.scala 103:75] + node _T_31 = or(_T_26, _T_30) @[Bitwise.scala 103:39] + node _T_32 = bits(_T_24, 6, 0) @[Bitwise.scala 102:28] + node _T_33 = shl(_T_32, 1) @[Bitwise.scala 102:47] + node _T_34 = xor(_T_24, _T_33) @[Bitwise.scala 102:21] + node _T_35 = shr(_T_31, 1) @[Bitwise.scala 103:21] + node _T_36 = and(_T_35, _T_34) @[Bitwise.scala 103:31] + node _T_37 = bits(_T_31, 6, 0) @[Bitwise.scala 103:46] + node _T_38 = shl(_T_37, 1) @[Bitwise.scala 103:65] + node _T_39 = not(_T_34) @[Bitwise.scala 103:77] + node _T_40 = and(_T_38, _T_39) @[Bitwise.scala 103:75] + node _T_41 = or(_T_36, _T_40) @[Bitwise.scala 103:39] + node _T_42 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_43 = bits(_T_42, 1, 1) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_44 = bits(_T_43, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_45 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_46 = bits(_T_45, 15, 8) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_47 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_48 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_49 = bits(dccm_rdata_corr_m, 15, 8) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_50 = mux(_T_47, _T_48, _T_49) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_51 = mux(_T_44, _T_46, _T_50) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_52 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_53 = xor(UInt<8>("h0ff"), _T_52) @[Bitwise.scala 102:21] + node _T_54 = shr(_T_51, 4) @[Bitwise.scala 103:21] + node _T_55 = and(_T_54, _T_53) @[Bitwise.scala 103:31] + node _T_56 = bits(_T_51, 3, 0) @[Bitwise.scala 103:46] + node _T_57 = shl(_T_56, 4) @[Bitwise.scala 103:65] + node _T_58 = not(_T_53) @[Bitwise.scala 103:77] + node _T_59 = and(_T_57, _T_58) @[Bitwise.scala 103:75] + node _T_60 = or(_T_55, _T_59) @[Bitwise.scala 103:39] + node _T_61 = bits(_T_53, 5, 0) @[Bitwise.scala 102:28] + node _T_62 = shl(_T_61, 2) @[Bitwise.scala 102:47] + node _T_63 = xor(_T_53, _T_62) @[Bitwise.scala 102:21] + node _T_64 = shr(_T_60, 2) @[Bitwise.scala 103:21] + node _T_65 = and(_T_64, _T_63) @[Bitwise.scala 103:31] + node _T_66 = bits(_T_60, 5, 0) @[Bitwise.scala 103:46] + node _T_67 = shl(_T_66, 2) @[Bitwise.scala 103:65] + node _T_68 = not(_T_63) @[Bitwise.scala 103:77] + node _T_69 = and(_T_67, _T_68) @[Bitwise.scala 103:75] + node _T_70 = or(_T_65, _T_69) @[Bitwise.scala 103:39] + node _T_71 = bits(_T_63, 6, 0) @[Bitwise.scala 102:28] + node _T_72 = shl(_T_71, 1) @[Bitwise.scala 102:47] + node _T_73 = xor(_T_63, _T_72) @[Bitwise.scala 102:21] + node _T_74 = shr(_T_70, 1) @[Bitwise.scala 103:21] + node _T_75 = and(_T_74, _T_73) @[Bitwise.scala 103:31] + node _T_76 = bits(_T_70, 6, 0) @[Bitwise.scala 103:46] + node _T_77 = shl(_T_76, 1) @[Bitwise.scala 103:65] + node _T_78 = not(_T_73) @[Bitwise.scala 103:77] + node _T_79 = and(_T_77, _T_78) @[Bitwise.scala 103:75] + node _T_80 = or(_T_75, _T_79) @[Bitwise.scala 103:39] + node _T_81 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_82 = bits(_T_81, 2, 2) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_83 = bits(_T_82, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_84 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_85 = bits(_T_84, 23, 16) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_86 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_87 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_88 = bits(dccm_rdata_corr_m, 23, 16) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_89 = mux(_T_86, _T_87, _T_88) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_90 = mux(_T_83, _T_85, _T_89) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_91 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_92 = xor(UInt<8>("h0ff"), _T_91) @[Bitwise.scala 102:21] + node _T_93 = shr(_T_90, 4) @[Bitwise.scala 103:21] + node _T_94 = and(_T_93, _T_92) @[Bitwise.scala 103:31] + node _T_95 = bits(_T_90, 3, 0) @[Bitwise.scala 103:46] + node _T_96 = shl(_T_95, 4) @[Bitwise.scala 103:65] + node _T_97 = not(_T_92) @[Bitwise.scala 103:77] + node _T_98 = and(_T_96, _T_97) @[Bitwise.scala 103:75] + node _T_99 = or(_T_94, _T_98) @[Bitwise.scala 103:39] + node _T_100 = bits(_T_92, 5, 0) @[Bitwise.scala 102:28] + node _T_101 = shl(_T_100, 2) @[Bitwise.scala 102:47] + node _T_102 = xor(_T_92, _T_101) @[Bitwise.scala 102:21] + node _T_103 = shr(_T_99, 2) @[Bitwise.scala 103:21] + node _T_104 = and(_T_103, _T_102) @[Bitwise.scala 103:31] + node _T_105 = bits(_T_99, 5, 0) @[Bitwise.scala 103:46] + node _T_106 = shl(_T_105, 2) @[Bitwise.scala 103:65] + node _T_107 = not(_T_102) @[Bitwise.scala 103:77] + node _T_108 = and(_T_106, _T_107) @[Bitwise.scala 103:75] + node _T_109 = or(_T_104, _T_108) @[Bitwise.scala 103:39] + node _T_110 = bits(_T_102, 6, 0) @[Bitwise.scala 102:28] + node _T_111 = shl(_T_110, 1) @[Bitwise.scala 102:47] + node _T_112 = xor(_T_102, _T_111) @[Bitwise.scala 102:21] + node _T_113 = shr(_T_109, 1) @[Bitwise.scala 103:21] + node _T_114 = and(_T_113, _T_112) @[Bitwise.scala 103:31] + node _T_115 = bits(_T_109, 6, 0) @[Bitwise.scala 103:46] + node _T_116 = shl(_T_115, 1) @[Bitwise.scala 103:65] + node _T_117 = not(_T_112) @[Bitwise.scala 103:77] + node _T_118 = and(_T_116, _T_117) @[Bitwise.scala 103:75] + node _T_119 = or(_T_114, _T_118) @[Bitwise.scala 103:39] node _T_120 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_121 = bits(_T_120, 5, 5) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_122 = bits(_T_121, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] + node _T_121 = bits(_T_120, 3, 3) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_122 = bits(_T_121, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] node _T_123 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_124 = bits(_T_123, 47, 40) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_125 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_126 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_127 = bits(dccm_rdata_m, 47, 40) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_128 = mux(_T_125, _T_126, _T_127) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_129 = mux(_T_122, _T_124, _T_128) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[5] <= _T_129 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[6] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[6] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_130 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_131 = bits(_T_130, 6, 6) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_132 = bits(_T_131, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_133 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_134 = bits(_T_133, 55, 48) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_135 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_136 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_137 = bits(dccm_rdata_corr_m, 55, 48) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_138 = mux(_T_135, _T_136, _T_137) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_139 = mux(_T_132, _T_134, _T_138) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[6] <= _T_139 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_140 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_141 = bits(_T_140, 6, 6) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_142 = bits(_T_141, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_143 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_144 = bits(_T_143, 55, 48) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_145 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_146 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_147 = bits(dccm_rdata_m, 55, 48) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_148 = mux(_T_145, _T_146, _T_147) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_149 = mux(_T_142, _T_144, _T_148) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[6] <= _T_149 @[el2_lsu_dccm_ctl.scala 185:30] - lsu_rdata_r[7] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 180:27] - io.lsu_ld_data_r <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 181:27] - lsu_rdata_corr_r[7] <= UInt<1>("h00") @[el2_lsu_dccm_ctl.scala 182:27] - node _T_150 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_151 = bits(_T_150, 7, 7) @[el2_lsu_dccm_ctl.scala 184:92] - node _T_152 = bits(_T_151, 0, 0) @[el2_lsu_dccm_ctl.scala 184:97] - node _T_153 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_154 = bits(_T_153, 63, 56) @[el2_lsu_dccm_ctl.scala 184:154] - node _T_155 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 184:189] - node _T_156 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 184:210] - node _T_157 = bits(dccm_rdata_corr_m, 63, 56) @[el2_lsu_dccm_ctl.scala 184:241] - node _T_158 = mux(_T_155, _T_156, _T_157) @[el2_lsu_dccm_ctl.scala 184:171] - node _T_159 = mux(_T_152, _T_154, _T_158) @[el2_lsu_dccm_ctl.scala 184:36] - lsu_rdata_corr_m[7] <= _T_159 @[el2_lsu_dccm_ctl.scala 184:30] - node _T_160 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] - node _T_161 = bits(_T_160, 7, 7) @[el2_lsu_dccm_ctl.scala 185:92] - node _T_162 = bits(_T_161, 0, 0) @[el2_lsu_dccm_ctl.scala 185:97] - node _T_163 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] - node _T_164 = bits(_T_163, 63, 56) @[el2_lsu_dccm_ctl.scala 185:154] - node _T_165 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 185:189] - node _T_166 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 185:210] - node _T_167 = bits(dccm_rdata_m, 63, 56) @[el2_lsu_dccm_ctl.scala 185:236] - node _T_168 = mux(_T_165, _T_166, _T_167) @[el2_lsu_dccm_ctl.scala 185:171] - node _T_169 = mux(_T_162, _T_164, _T_168) @[el2_lsu_dccm_ctl.scala 185:36] - lsu_rdata_m[7] <= _T_169 @[el2_lsu_dccm_ctl.scala 185:30] - node _T_170 = cat(lsu_rdata_m[1], lsu_rdata_m[0]) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_171 = cat(lsu_rdata_m[3], lsu_rdata_m[2]) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_172 = cat(_T_171, _T_170) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_173 = cat(lsu_rdata_m[5], lsu_rdata_m[4]) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_174 = cat(lsu_rdata_m[7], lsu_rdata_m[6]) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_175 = cat(_T_174, _T_173) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_176 = cat(_T_175, _T_172) @[el2_lsu_dccm_ctl.scala 186:43] - node _T_177 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 186:70] - node _T_178 = mul(UInt<4>("h08"), _T_177) @[el2_lsu_dccm_ctl.scala 186:56] - node _T_179 = dshr(_T_176, _T_178) @[el2_lsu_dccm_ctl.scala 186:50] - io.lsu_ld_data_m <= _T_179 @[el2_lsu_dccm_ctl.scala 186:28] - node _T_180 = cat(lsu_rdata_corr_m[1], lsu_rdata_corr_m[0]) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_181 = cat(lsu_rdata_corr_m[3], lsu_rdata_corr_m[2]) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_182 = cat(_T_181, _T_180) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_183 = cat(lsu_rdata_corr_m[5], lsu_rdata_corr_m[4]) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_184 = cat(lsu_rdata_corr_m[7], lsu_rdata_corr_m[6]) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_185 = cat(_T_184, _T_183) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_186 = cat(_T_185, _T_182) @[el2_lsu_dccm_ctl.scala 187:48] - node _T_187 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 187:75] - node _T_188 = mul(UInt<4>("h08"), _T_187) @[el2_lsu_dccm_ctl.scala 187:61] - node _T_189 = dshr(_T_186, _T_188) @[el2_lsu_dccm_ctl.scala 187:55] - lsu_ld_data_corr_m <= _T_189 @[el2_lsu_dccm_ctl.scala 187:28] - node _T_190 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 190:44] - node _T_191 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 190:81] - node _T_192 = eq(_T_190, _T_191) @[el2_lsu_dccm_ctl.scala 190:64] - node _T_193 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 190:125] - node _T_194 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 190:162] - node _T_195 = eq(_T_193, _T_194) @[el2_lsu_dccm_ctl.scala 190:145] - node _T_196 = or(_T_192, _T_195) @[el2_lsu_dccm_ctl.scala 190:109] - node _T_197 = and(_T_196, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 190:191] - node _T_198 = and(_T_197, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 190:212] - node _T_199 = and(_T_198, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 190:233] - node _T_200 = and(_T_199, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 190:252] - node _T_201 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 191:21] - node _T_202 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 191:58] - node _T_203 = eq(_T_201, _T_202) @[el2_lsu_dccm_ctl.scala 191:41] - node _T_204 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 191:102] - node _T_205 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 191:139] - node _T_206 = eq(_T_204, _T_205) @[el2_lsu_dccm_ctl.scala 191:122] - node _T_207 = or(_T_203, _T_206) @[el2_lsu_dccm_ctl.scala 191:86] - node _T_208 = and(_T_207, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 191:168] - node _T_209 = and(_T_208, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 191:189] - node _T_210 = and(_T_209, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 191:210] - node _T_211 = and(_T_210, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 191:229] - node kill_ecc_corr_lo_r = or(_T_200, _T_211) @[el2_lsu_dccm_ctl.scala 190:273] - node _T_212 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 192:44] - node _T_213 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 192:81] - node _T_214 = eq(_T_212, _T_213) @[el2_lsu_dccm_ctl.scala 192:64] - node _T_215 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 192:125] - node _T_216 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 192:162] - node _T_217 = eq(_T_215, _T_216) @[el2_lsu_dccm_ctl.scala 192:145] - node _T_218 = or(_T_214, _T_217) @[el2_lsu_dccm_ctl.scala 192:109] - node _T_219 = and(_T_218, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 192:191] - node _T_220 = and(_T_219, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 192:212] - node _T_221 = and(_T_220, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 192:233] - node _T_222 = and(_T_221, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 192:252] - node _T_223 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 193:21] - node _T_224 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 193:58] - node _T_225 = eq(_T_223, _T_224) @[el2_lsu_dccm_ctl.scala 193:41] - node _T_226 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 193:102] - node _T_227 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 193:139] - node _T_228 = eq(_T_226, _T_227) @[el2_lsu_dccm_ctl.scala 193:122] - node _T_229 = or(_T_225, _T_228) @[el2_lsu_dccm_ctl.scala 193:86] - node _T_230 = and(_T_229, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 193:168] - node _T_231 = and(_T_230, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 193:189] - node _T_232 = and(_T_231, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 193:210] - node _T_233 = and(_T_232, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 193:229] - node kill_ecc_corr_hi_r = or(_T_222, _T_233) @[el2_lsu_dccm_ctl.scala 192:273] - node _T_234 = and(io.lsu_pkt_r.load, io.single_ecc_error_lo_r) @[el2_lsu_dccm_ctl.scala 194:55] - node _T_235 = not(io.lsu_raw_fwd_lo_r) @[el2_lsu_dccm_ctl.scala 194:84] - node ld_single_ecc_error_lo_r = and(_T_234, _T_235) @[el2_lsu_dccm_ctl.scala 194:82] - node _T_236 = and(io.lsu_pkt_r.load, io.single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 195:55] - node _T_237 = not(io.lsu_raw_fwd_hi_r) @[el2_lsu_dccm_ctl.scala 195:84] - node ld_single_ecc_error_hi_r = and(_T_236, _T_237) @[el2_lsu_dccm_ctl.scala 195:82] - node _T_238 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 196:62] - node _T_239 = not(io.lsu_double_ecc_error_r) @[el2_lsu_dccm_ctl.scala 196:92] - node _T_240 = and(_T_238, _T_239) @[el2_lsu_dccm_ctl.scala 196:90] - io.ld_single_ecc_error_r <= _T_240 @[el2_lsu_dccm_ctl.scala 196:33] - node _T_241 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 197:81] - node _T_242 = and(ld_single_ecc_error_lo_r, _T_241) @[el2_lsu_dccm_ctl.scala 197:62] - node _T_243 = not(kill_ecc_corr_lo_r) @[el2_lsu_dccm_ctl.scala 197:103] - node ld_single_ecc_error_lo_r_ns = and(_T_242, _T_243) @[el2_lsu_dccm_ctl.scala 197:101] - node _T_244 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 198:81] - node _T_245 = and(ld_single_ecc_error_hi_r, _T_244) @[el2_lsu_dccm_ctl.scala 198:62] - node _T_246 = not(kill_ecc_corr_hi_r) @[el2_lsu_dccm_ctl.scala 198:103] - node ld_single_ecc_error_hi_r_ns = and(_T_245, _T_246) @[el2_lsu_dccm_ctl.scala 198:101] - reg lsu_double_ecc_error_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 200:74] - lsu_double_ecc_error_r_ff <= io.lsu_double_ecc_error_r @[el2_lsu_dccm_ctl.scala 200:74] - reg ld_single_ecc_error_hi_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 201:74] - ld_single_ecc_error_hi_r_ff <= ld_single_ecc_error_hi_r_ns @[el2_lsu_dccm_ctl.scala 201:74] - reg ld_single_ecc_error_lo_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 202:74] - ld_single_ecc_error_lo_r_ff <= ld_single_ecc_error_lo_r_ns @[el2_lsu_dccm_ctl.scala 202:74] - node _T_247 = bits(io.end_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 206:49] - node _T_248 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 206:94] - node _T_249 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 206:121] - inst rvclkhdr of rvclkhdr @[beh_lib.scala 351:21] + node _T_124 = bits(_T_123, 31, 24) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_125 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_126 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_127 = bits(dccm_rdata_corr_m, 31, 24) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_128 = mux(_T_125, _T_126, _T_127) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_129 = mux(_T_122, _T_124, _T_128) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_130 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_131 = xor(UInt<8>("h0ff"), _T_130) @[Bitwise.scala 102:21] + node _T_132 = shr(_T_129, 4) @[Bitwise.scala 103:21] + node _T_133 = and(_T_132, _T_131) @[Bitwise.scala 103:31] + node _T_134 = bits(_T_129, 3, 0) @[Bitwise.scala 103:46] + node _T_135 = shl(_T_134, 4) @[Bitwise.scala 103:65] + node _T_136 = not(_T_131) @[Bitwise.scala 103:77] + node _T_137 = and(_T_135, _T_136) @[Bitwise.scala 103:75] + node _T_138 = or(_T_133, _T_137) @[Bitwise.scala 103:39] + node _T_139 = bits(_T_131, 5, 0) @[Bitwise.scala 102:28] + node _T_140 = shl(_T_139, 2) @[Bitwise.scala 102:47] + node _T_141 = xor(_T_131, _T_140) @[Bitwise.scala 102:21] + node _T_142 = shr(_T_138, 2) @[Bitwise.scala 103:21] + node _T_143 = and(_T_142, _T_141) @[Bitwise.scala 103:31] + node _T_144 = bits(_T_138, 5, 0) @[Bitwise.scala 103:46] + node _T_145 = shl(_T_144, 2) @[Bitwise.scala 103:65] + node _T_146 = not(_T_141) @[Bitwise.scala 103:77] + node _T_147 = and(_T_145, _T_146) @[Bitwise.scala 103:75] + node _T_148 = or(_T_143, _T_147) @[Bitwise.scala 103:39] + node _T_149 = bits(_T_141, 6, 0) @[Bitwise.scala 102:28] + node _T_150 = shl(_T_149, 1) @[Bitwise.scala 102:47] + node _T_151 = xor(_T_141, _T_150) @[Bitwise.scala 102:21] + node _T_152 = shr(_T_148, 1) @[Bitwise.scala 103:21] + node _T_153 = and(_T_152, _T_151) @[Bitwise.scala 103:31] + node _T_154 = bits(_T_148, 6, 0) @[Bitwise.scala 103:46] + node _T_155 = shl(_T_154, 1) @[Bitwise.scala 103:65] + node _T_156 = not(_T_151) @[Bitwise.scala 103:77] + node _T_157 = and(_T_155, _T_156) @[Bitwise.scala 103:75] + node _T_158 = or(_T_153, _T_157) @[Bitwise.scala 103:39] + node _T_159 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_160 = bits(_T_159, 4, 4) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_161 = bits(_T_160, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_162 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_163 = bits(_T_162, 39, 32) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_164 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_165 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_166 = bits(dccm_rdata_corr_m, 39, 32) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_167 = mux(_T_164, _T_165, _T_166) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_168 = mux(_T_161, _T_163, _T_167) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_169 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_170 = xor(UInt<8>("h0ff"), _T_169) @[Bitwise.scala 102:21] + node _T_171 = shr(_T_168, 4) @[Bitwise.scala 103:21] + node _T_172 = and(_T_171, _T_170) @[Bitwise.scala 103:31] + node _T_173 = bits(_T_168, 3, 0) @[Bitwise.scala 103:46] + node _T_174 = shl(_T_173, 4) @[Bitwise.scala 103:65] + node _T_175 = not(_T_170) @[Bitwise.scala 103:77] + node _T_176 = and(_T_174, _T_175) @[Bitwise.scala 103:75] + node _T_177 = or(_T_172, _T_176) @[Bitwise.scala 103:39] + node _T_178 = bits(_T_170, 5, 0) @[Bitwise.scala 102:28] + node _T_179 = shl(_T_178, 2) @[Bitwise.scala 102:47] + node _T_180 = xor(_T_170, _T_179) @[Bitwise.scala 102:21] + node _T_181 = shr(_T_177, 2) @[Bitwise.scala 103:21] + node _T_182 = and(_T_181, _T_180) @[Bitwise.scala 103:31] + node _T_183 = bits(_T_177, 5, 0) @[Bitwise.scala 103:46] + node _T_184 = shl(_T_183, 2) @[Bitwise.scala 103:65] + node _T_185 = not(_T_180) @[Bitwise.scala 103:77] + node _T_186 = and(_T_184, _T_185) @[Bitwise.scala 103:75] + node _T_187 = or(_T_182, _T_186) @[Bitwise.scala 103:39] + node _T_188 = bits(_T_180, 6, 0) @[Bitwise.scala 102:28] + node _T_189 = shl(_T_188, 1) @[Bitwise.scala 102:47] + node _T_190 = xor(_T_180, _T_189) @[Bitwise.scala 102:21] + node _T_191 = shr(_T_187, 1) @[Bitwise.scala 103:21] + node _T_192 = and(_T_191, _T_190) @[Bitwise.scala 103:31] + node _T_193 = bits(_T_187, 6, 0) @[Bitwise.scala 103:46] + node _T_194 = shl(_T_193, 1) @[Bitwise.scala 103:65] + node _T_195 = not(_T_190) @[Bitwise.scala 103:77] + node _T_196 = and(_T_194, _T_195) @[Bitwise.scala 103:75] + node _T_197 = or(_T_192, _T_196) @[Bitwise.scala 103:39] + node _T_198 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_199 = bits(_T_198, 5, 5) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_200 = bits(_T_199, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_201 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_202 = bits(_T_201, 47, 40) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_203 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_204 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_205 = bits(dccm_rdata_corr_m, 47, 40) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_206 = mux(_T_203, _T_204, _T_205) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_207 = mux(_T_200, _T_202, _T_206) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_208 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_209 = xor(UInt<8>("h0ff"), _T_208) @[Bitwise.scala 102:21] + node _T_210 = shr(_T_207, 4) @[Bitwise.scala 103:21] + node _T_211 = and(_T_210, _T_209) @[Bitwise.scala 103:31] + node _T_212 = bits(_T_207, 3, 0) @[Bitwise.scala 103:46] + node _T_213 = shl(_T_212, 4) @[Bitwise.scala 103:65] + node _T_214 = not(_T_209) @[Bitwise.scala 103:77] + node _T_215 = and(_T_213, _T_214) @[Bitwise.scala 103:75] + node _T_216 = or(_T_211, _T_215) @[Bitwise.scala 103:39] + node _T_217 = bits(_T_209, 5, 0) @[Bitwise.scala 102:28] + node _T_218 = shl(_T_217, 2) @[Bitwise.scala 102:47] + node _T_219 = xor(_T_209, _T_218) @[Bitwise.scala 102:21] + node _T_220 = shr(_T_216, 2) @[Bitwise.scala 103:21] + node _T_221 = and(_T_220, _T_219) @[Bitwise.scala 103:31] + node _T_222 = bits(_T_216, 5, 0) @[Bitwise.scala 103:46] + node _T_223 = shl(_T_222, 2) @[Bitwise.scala 103:65] + node _T_224 = not(_T_219) @[Bitwise.scala 103:77] + node _T_225 = and(_T_223, _T_224) @[Bitwise.scala 103:75] + node _T_226 = or(_T_221, _T_225) @[Bitwise.scala 103:39] + node _T_227 = bits(_T_219, 6, 0) @[Bitwise.scala 102:28] + node _T_228 = shl(_T_227, 1) @[Bitwise.scala 102:47] + node _T_229 = xor(_T_219, _T_228) @[Bitwise.scala 102:21] + node _T_230 = shr(_T_226, 1) @[Bitwise.scala 103:21] + node _T_231 = and(_T_230, _T_229) @[Bitwise.scala 103:31] + node _T_232 = bits(_T_226, 6, 0) @[Bitwise.scala 103:46] + node _T_233 = shl(_T_232, 1) @[Bitwise.scala 103:65] + node _T_234 = not(_T_229) @[Bitwise.scala 103:77] + node _T_235 = and(_T_233, _T_234) @[Bitwise.scala 103:75] + node _T_236 = or(_T_231, _T_235) @[Bitwise.scala 103:39] + node _T_237 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_238 = bits(_T_237, 6, 6) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_239 = bits(_T_238, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_240 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_241 = bits(_T_240, 55, 48) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_242 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_243 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_244 = bits(dccm_rdata_corr_m, 55, 48) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_245 = mux(_T_242, _T_243, _T_244) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_246 = mux(_T_239, _T_241, _T_245) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_247 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_248 = xor(UInt<8>("h0ff"), _T_247) @[Bitwise.scala 102:21] + node _T_249 = shr(_T_246, 4) @[Bitwise.scala 103:21] + node _T_250 = and(_T_249, _T_248) @[Bitwise.scala 103:31] + node _T_251 = bits(_T_246, 3, 0) @[Bitwise.scala 103:46] + node _T_252 = shl(_T_251, 4) @[Bitwise.scala 103:65] + node _T_253 = not(_T_248) @[Bitwise.scala 103:77] + node _T_254 = and(_T_252, _T_253) @[Bitwise.scala 103:75] + node _T_255 = or(_T_250, _T_254) @[Bitwise.scala 103:39] + node _T_256 = bits(_T_248, 5, 0) @[Bitwise.scala 102:28] + node _T_257 = shl(_T_256, 2) @[Bitwise.scala 102:47] + node _T_258 = xor(_T_248, _T_257) @[Bitwise.scala 102:21] + node _T_259 = shr(_T_255, 2) @[Bitwise.scala 103:21] + node _T_260 = and(_T_259, _T_258) @[Bitwise.scala 103:31] + node _T_261 = bits(_T_255, 5, 0) @[Bitwise.scala 103:46] + node _T_262 = shl(_T_261, 2) @[Bitwise.scala 103:65] + node _T_263 = not(_T_258) @[Bitwise.scala 103:77] + node _T_264 = and(_T_262, _T_263) @[Bitwise.scala 103:75] + node _T_265 = or(_T_260, _T_264) @[Bitwise.scala 103:39] + node _T_266 = bits(_T_258, 6, 0) @[Bitwise.scala 102:28] + node _T_267 = shl(_T_266, 1) @[Bitwise.scala 102:47] + node _T_268 = xor(_T_258, _T_267) @[Bitwise.scala 102:21] + node _T_269 = shr(_T_265, 1) @[Bitwise.scala 103:21] + node _T_270 = and(_T_269, _T_268) @[Bitwise.scala 103:31] + node _T_271 = bits(_T_265, 6, 0) @[Bitwise.scala 103:46] + node _T_272 = shl(_T_271, 1) @[Bitwise.scala 103:65] + node _T_273 = not(_T_268) @[Bitwise.scala 103:77] + node _T_274 = and(_T_272, _T_273) @[Bitwise.scala 103:75] + node _T_275 = or(_T_270, _T_274) @[Bitwise.scala 103:39] + node _T_276 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_277 = bits(_T_276, 7, 7) @[el2_lsu_dccm_ctl.scala 172:134] + node _T_278 = bits(_T_277, 0, 0) @[el2_lsu_dccm_ctl.scala 172:139] + node _T_279 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_280 = bits(_T_279, 63, 56) @[el2_lsu_dccm_ctl.scala 172:196] + node _T_281 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 172:231] + node _T_282 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 172:252] + node _T_283 = bits(dccm_rdata_corr_m, 63, 56) @[el2_lsu_dccm_ctl.scala 172:283] + node _T_284 = mux(_T_281, _T_282, _T_283) @[el2_lsu_dccm_ctl.scala 172:213] + node _T_285 = mux(_T_278, _T_280, _T_284) @[el2_lsu_dccm_ctl.scala 172:78] + node _T_286 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_287 = xor(UInt<8>("h0ff"), _T_286) @[Bitwise.scala 102:21] + node _T_288 = shr(_T_285, 4) @[Bitwise.scala 103:21] + node _T_289 = and(_T_288, _T_287) @[Bitwise.scala 103:31] + node _T_290 = bits(_T_285, 3, 0) @[Bitwise.scala 103:46] + node _T_291 = shl(_T_290, 4) @[Bitwise.scala 103:65] + node _T_292 = not(_T_287) @[Bitwise.scala 103:77] + node _T_293 = and(_T_291, _T_292) @[Bitwise.scala 103:75] + node _T_294 = or(_T_289, _T_293) @[Bitwise.scala 103:39] + node _T_295 = bits(_T_287, 5, 0) @[Bitwise.scala 102:28] + node _T_296 = shl(_T_295, 2) @[Bitwise.scala 102:47] + node _T_297 = xor(_T_287, _T_296) @[Bitwise.scala 102:21] + node _T_298 = shr(_T_294, 2) @[Bitwise.scala 103:21] + node _T_299 = and(_T_298, _T_297) @[Bitwise.scala 103:31] + node _T_300 = bits(_T_294, 5, 0) @[Bitwise.scala 103:46] + node _T_301 = shl(_T_300, 2) @[Bitwise.scala 103:65] + node _T_302 = not(_T_297) @[Bitwise.scala 103:77] + node _T_303 = and(_T_301, _T_302) @[Bitwise.scala 103:75] + node _T_304 = or(_T_299, _T_303) @[Bitwise.scala 103:39] + node _T_305 = bits(_T_297, 6, 0) @[Bitwise.scala 102:28] + node _T_306 = shl(_T_305, 1) @[Bitwise.scala 102:47] + node _T_307 = xor(_T_297, _T_306) @[Bitwise.scala 102:21] + node _T_308 = shr(_T_304, 1) @[Bitwise.scala 103:21] + node _T_309 = and(_T_308, _T_307) @[Bitwise.scala 103:31] + node _T_310 = bits(_T_304, 6, 0) @[Bitwise.scala 103:46] + node _T_311 = shl(_T_310, 1) @[Bitwise.scala 103:65] + node _T_312 = not(_T_307) @[Bitwise.scala 103:77] + node _T_313 = and(_T_311, _T_312) @[Bitwise.scala 103:75] + node _T_314 = or(_T_309, _T_313) @[Bitwise.scala 103:39] + wire _T_315 : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[0] <= _T_41 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[1] <= _T_80 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[2] <= _T_119 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[3] <= _T_158 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[4] <= _T_197 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[5] <= _T_236 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[6] <= _T_275 @[el2_lsu_dccm_ctl.scala 172:62] + _T_315[7] <= _T_314 @[el2_lsu_dccm_ctl.scala 172:62] + node _T_316 = cat(_T_315[6], _T_315[7]) @[Cat.scala 29:58] + node _T_317 = cat(_T_315[4], _T_315[5]) @[Cat.scala 29:58] + node _T_318 = cat(_T_317, _T_316) @[Cat.scala 29:58] + node _T_319 = cat(_T_315[2], _T_315[3]) @[Cat.scala 29:58] + node _T_320 = cat(_T_315[0], _T_315[1]) @[Cat.scala 29:58] + node _T_321 = cat(_T_320, _T_319) @[Cat.scala 29:58] + node _T_322 = cat(_T_321, _T_318) @[Cat.scala 29:58] + node _T_323 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_324 = xor(UInt<64>("h0ffffffffffffffff"), _T_323) @[Bitwise.scala 102:21] + node _T_325 = shr(_T_322, 32) @[Bitwise.scala 103:21] + node _T_326 = and(_T_325, _T_324) @[Bitwise.scala 103:31] + node _T_327 = bits(_T_322, 31, 0) @[Bitwise.scala 103:46] + node _T_328 = shl(_T_327, 32) @[Bitwise.scala 103:65] + node _T_329 = not(_T_324) @[Bitwise.scala 103:77] + node _T_330 = and(_T_328, _T_329) @[Bitwise.scala 103:75] + node _T_331 = or(_T_326, _T_330) @[Bitwise.scala 103:39] + node _T_332 = bits(_T_324, 47, 0) @[Bitwise.scala 102:28] + node _T_333 = shl(_T_332, 16) @[Bitwise.scala 102:47] + node _T_334 = xor(_T_324, _T_333) @[Bitwise.scala 102:21] + node _T_335 = shr(_T_331, 16) @[Bitwise.scala 103:21] + node _T_336 = and(_T_335, _T_334) @[Bitwise.scala 103:31] + node _T_337 = bits(_T_331, 47, 0) @[Bitwise.scala 103:46] + node _T_338 = shl(_T_337, 16) @[Bitwise.scala 103:65] + node _T_339 = not(_T_334) @[Bitwise.scala 103:77] + node _T_340 = and(_T_338, _T_339) @[Bitwise.scala 103:75] + node _T_341 = or(_T_336, _T_340) @[Bitwise.scala 103:39] + node _T_342 = bits(_T_334, 55, 0) @[Bitwise.scala 102:28] + node _T_343 = shl(_T_342, 8) @[Bitwise.scala 102:47] + node _T_344 = xor(_T_334, _T_343) @[Bitwise.scala 102:21] + node _T_345 = shr(_T_341, 8) @[Bitwise.scala 103:21] + node _T_346 = and(_T_345, _T_344) @[Bitwise.scala 103:31] + node _T_347 = bits(_T_341, 55, 0) @[Bitwise.scala 103:46] + node _T_348 = shl(_T_347, 8) @[Bitwise.scala 103:65] + node _T_349 = not(_T_344) @[Bitwise.scala 103:77] + node _T_350 = and(_T_348, _T_349) @[Bitwise.scala 103:75] + node _T_351 = or(_T_346, _T_350) @[Bitwise.scala 103:39] + node _T_352 = bits(_T_344, 59, 0) @[Bitwise.scala 102:28] + node _T_353 = shl(_T_352, 4) @[Bitwise.scala 102:47] + node _T_354 = xor(_T_344, _T_353) @[Bitwise.scala 102:21] + node _T_355 = shr(_T_351, 4) @[Bitwise.scala 103:21] + node _T_356 = and(_T_355, _T_354) @[Bitwise.scala 103:31] + node _T_357 = bits(_T_351, 59, 0) @[Bitwise.scala 103:46] + node _T_358 = shl(_T_357, 4) @[Bitwise.scala 103:65] + node _T_359 = not(_T_354) @[Bitwise.scala 103:77] + node _T_360 = and(_T_358, _T_359) @[Bitwise.scala 103:75] + node _T_361 = or(_T_356, _T_360) @[Bitwise.scala 103:39] + node _T_362 = bits(_T_354, 61, 0) @[Bitwise.scala 102:28] + node _T_363 = shl(_T_362, 2) @[Bitwise.scala 102:47] + node _T_364 = xor(_T_354, _T_363) @[Bitwise.scala 102:21] + node _T_365 = shr(_T_361, 2) @[Bitwise.scala 103:21] + node _T_366 = and(_T_365, _T_364) @[Bitwise.scala 103:31] + node _T_367 = bits(_T_361, 61, 0) @[Bitwise.scala 103:46] + node _T_368 = shl(_T_367, 2) @[Bitwise.scala 103:65] + node _T_369 = not(_T_364) @[Bitwise.scala 103:77] + node _T_370 = and(_T_368, _T_369) @[Bitwise.scala 103:75] + node _T_371 = or(_T_366, _T_370) @[Bitwise.scala 103:39] + node _T_372 = bits(_T_364, 62, 0) @[Bitwise.scala 102:28] + node _T_373 = shl(_T_372, 1) @[Bitwise.scala 102:47] + node _T_374 = xor(_T_364, _T_373) @[Bitwise.scala 102:21] + node _T_375 = shr(_T_371, 1) @[Bitwise.scala 103:21] + node _T_376 = and(_T_375, _T_374) @[Bitwise.scala 103:31] + node _T_377 = bits(_T_371, 62, 0) @[Bitwise.scala 103:46] + node _T_378 = shl(_T_377, 1) @[Bitwise.scala 103:65] + node _T_379 = not(_T_374) @[Bitwise.scala 103:77] + node _T_380 = and(_T_378, _T_379) @[Bitwise.scala 103:75] + node _T_381 = or(_T_376, _T_380) @[Bitwise.scala 103:39] + lsu_rdata_corr_m <= _T_381 @[el2_lsu_dccm_ctl.scala 172:28] + node _T_382 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_383 = bits(_T_382, 0, 0) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_384 = bits(_T_383, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_385 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_386 = bits(_T_385, 7, 0) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_387 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_388 = bits(picm_rd_data_m, 7, 0) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_389 = bits(dccm_rdata_m, 7, 0) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_390 = mux(_T_387, _T_388, _T_389) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_391 = mux(_T_384, _T_386, _T_390) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_392 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_393 = xor(UInt<8>("h0ff"), _T_392) @[Bitwise.scala 102:21] + node _T_394 = shr(_T_391, 4) @[Bitwise.scala 103:21] + node _T_395 = and(_T_394, _T_393) @[Bitwise.scala 103:31] + node _T_396 = bits(_T_391, 3, 0) @[Bitwise.scala 103:46] + node _T_397 = shl(_T_396, 4) @[Bitwise.scala 103:65] + node _T_398 = not(_T_393) @[Bitwise.scala 103:77] + node _T_399 = and(_T_397, _T_398) @[Bitwise.scala 103:75] + node _T_400 = or(_T_395, _T_399) @[Bitwise.scala 103:39] + node _T_401 = bits(_T_393, 5, 0) @[Bitwise.scala 102:28] + node _T_402 = shl(_T_401, 2) @[Bitwise.scala 102:47] + node _T_403 = xor(_T_393, _T_402) @[Bitwise.scala 102:21] + node _T_404 = shr(_T_400, 2) @[Bitwise.scala 103:21] + node _T_405 = and(_T_404, _T_403) @[Bitwise.scala 103:31] + node _T_406 = bits(_T_400, 5, 0) @[Bitwise.scala 103:46] + node _T_407 = shl(_T_406, 2) @[Bitwise.scala 103:65] + node _T_408 = not(_T_403) @[Bitwise.scala 103:77] + node _T_409 = and(_T_407, _T_408) @[Bitwise.scala 103:75] + node _T_410 = or(_T_405, _T_409) @[Bitwise.scala 103:39] + node _T_411 = bits(_T_403, 6, 0) @[Bitwise.scala 102:28] + node _T_412 = shl(_T_411, 1) @[Bitwise.scala 102:47] + node _T_413 = xor(_T_403, _T_412) @[Bitwise.scala 102:21] + node _T_414 = shr(_T_410, 1) @[Bitwise.scala 103:21] + node _T_415 = and(_T_414, _T_413) @[Bitwise.scala 103:31] + node _T_416 = bits(_T_410, 6, 0) @[Bitwise.scala 103:46] + node _T_417 = shl(_T_416, 1) @[Bitwise.scala 103:65] + node _T_418 = not(_T_413) @[Bitwise.scala 103:77] + node _T_419 = and(_T_417, _T_418) @[Bitwise.scala 103:75] + node _T_420 = or(_T_415, _T_419) @[Bitwise.scala 103:39] + node _T_421 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_422 = bits(_T_421, 1, 1) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_423 = bits(_T_422, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_424 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_425 = bits(_T_424, 15, 8) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_426 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_427 = bits(picm_rd_data_m, 15, 8) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_428 = bits(dccm_rdata_m, 15, 8) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_429 = mux(_T_426, _T_427, _T_428) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_430 = mux(_T_423, _T_425, _T_429) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_431 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_432 = xor(UInt<8>("h0ff"), _T_431) @[Bitwise.scala 102:21] + node _T_433 = shr(_T_430, 4) @[Bitwise.scala 103:21] + node _T_434 = and(_T_433, _T_432) @[Bitwise.scala 103:31] + node _T_435 = bits(_T_430, 3, 0) @[Bitwise.scala 103:46] + node _T_436 = shl(_T_435, 4) @[Bitwise.scala 103:65] + node _T_437 = not(_T_432) @[Bitwise.scala 103:77] + node _T_438 = and(_T_436, _T_437) @[Bitwise.scala 103:75] + node _T_439 = or(_T_434, _T_438) @[Bitwise.scala 103:39] + node _T_440 = bits(_T_432, 5, 0) @[Bitwise.scala 102:28] + node _T_441 = shl(_T_440, 2) @[Bitwise.scala 102:47] + node _T_442 = xor(_T_432, _T_441) @[Bitwise.scala 102:21] + node _T_443 = shr(_T_439, 2) @[Bitwise.scala 103:21] + node _T_444 = and(_T_443, _T_442) @[Bitwise.scala 103:31] + node _T_445 = bits(_T_439, 5, 0) @[Bitwise.scala 103:46] + node _T_446 = shl(_T_445, 2) @[Bitwise.scala 103:65] + node _T_447 = not(_T_442) @[Bitwise.scala 103:77] + node _T_448 = and(_T_446, _T_447) @[Bitwise.scala 103:75] + node _T_449 = or(_T_444, _T_448) @[Bitwise.scala 103:39] + node _T_450 = bits(_T_442, 6, 0) @[Bitwise.scala 102:28] + node _T_451 = shl(_T_450, 1) @[Bitwise.scala 102:47] + node _T_452 = xor(_T_442, _T_451) @[Bitwise.scala 102:21] + node _T_453 = shr(_T_449, 1) @[Bitwise.scala 103:21] + node _T_454 = and(_T_453, _T_452) @[Bitwise.scala 103:31] + node _T_455 = bits(_T_449, 6, 0) @[Bitwise.scala 103:46] + node _T_456 = shl(_T_455, 1) @[Bitwise.scala 103:65] + node _T_457 = not(_T_452) @[Bitwise.scala 103:77] + node _T_458 = and(_T_456, _T_457) @[Bitwise.scala 103:75] + node _T_459 = or(_T_454, _T_458) @[Bitwise.scala 103:39] + node _T_460 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_461 = bits(_T_460, 2, 2) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_462 = bits(_T_461, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_463 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_464 = bits(_T_463, 23, 16) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_465 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_466 = bits(picm_rd_data_m, 23, 16) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_467 = bits(dccm_rdata_m, 23, 16) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_468 = mux(_T_465, _T_466, _T_467) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_469 = mux(_T_462, _T_464, _T_468) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_470 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_471 = xor(UInt<8>("h0ff"), _T_470) @[Bitwise.scala 102:21] + node _T_472 = shr(_T_469, 4) @[Bitwise.scala 103:21] + node _T_473 = and(_T_472, _T_471) @[Bitwise.scala 103:31] + node _T_474 = bits(_T_469, 3, 0) @[Bitwise.scala 103:46] + node _T_475 = shl(_T_474, 4) @[Bitwise.scala 103:65] + node _T_476 = not(_T_471) @[Bitwise.scala 103:77] + node _T_477 = and(_T_475, _T_476) @[Bitwise.scala 103:75] + node _T_478 = or(_T_473, _T_477) @[Bitwise.scala 103:39] + node _T_479 = bits(_T_471, 5, 0) @[Bitwise.scala 102:28] + node _T_480 = shl(_T_479, 2) @[Bitwise.scala 102:47] + node _T_481 = xor(_T_471, _T_480) @[Bitwise.scala 102:21] + node _T_482 = shr(_T_478, 2) @[Bitwise.scala 103:21] + node _T_483 = and(_T_482, _T_481) @[Bitwise.scala 103:31] + node _T_484 = bits(_T_478, 5, 0) @[Bitwise.scala 103:46] + node _T_485 = shl(_T_484, 2) @[Bitwise.scala 103:65] + node _T_486 = not(_T_481) @[Bitwise.scala 103:77] + node _T_487 = and(_T_485, _T_486) @[Bitwise.scala 103:75] + node _T_488 = or(_T_483, _T_487) @[Bitwise.scala 103:39] + node _T_489 = bits(_T_481, 6, 0) @[Bitwise.scala 102:28] + node _T_490 = shl(_T_489, 1) @[Bitwise.scala 102:47] + node _T_491 = xor(_T_481, _T_490) @[Bitwise.scala 102:21] + node _T_492 = shr(_T_488, 1) @[Bitwise.scala 103:21] + node _T_493 = and(_T_492, _T_491) @[Bitwise.scala 103:31] + node _T_494 = bits(_T_488, 6, 0) @[Bitwise.scala 103:46] + node _T_495 = shl(_T_494, 1) @[Bitwise.scala 103:65] + node _T_496 = not(_T_491) @[Bitwise.scala 103:77] + node _T_497 = and(_T_495, _T_496) @[Bitwise.scala 103:75] + node _T_498 = or(_T_493, _T_497) @[Bitwise.scala 103:39] + node _T_499 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_500 = bits(_T_499, 3, 3) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_501 = bits(_T_500, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_502 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_503 = bits(_T_502, 31, 24) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_504 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_505 = bits(picm_rd_data_m, 31, 24) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_506 = bits(dccm_rdata_m, 31, 24) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_507 = mux(_T_504, _T_505, _T_506) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_508 = mux(_T_501, _T_503, _T_507) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_509 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_510 = xor(UInt<8>("h0ff"), _T_509) @[Bitwise.scala 102:21] + node _T_511 = shr(_T_508, 4) @[Bitwise.scala 103:21] + node _T_512 = and(_T_511, _T_510) @[Bitwise.scala 103:31] + node _T_513 = bits(_T_508, 3, 0) @[Bitwise.scala 103:46] + node _T_514 = shl(_T_513, 4) @[Bitwise.scala 103:65] + node _T_515 = not(_T_510) @[Bitwise.scala 103:77] + node _T_516 = and(_T_514, _T_515) @[Bitwise.scala 103:75] + node _T_517 = or(_T_512, _T_516) @[Bitwise.scala 103:39] + node _T_518 = bits(_T_510, 5, 0) @[Bitwise.scala 102:28] + node _T_519 = shl(_T_518, 2) @[Bitwise.scala 102:47] + node _T_520 = xor(_T_510, _T_519) @[Bitwise.scala 102:21] + node _T_521 = shr(_T_517, 2) @[Bitwise.scala 103:21] + node _T_522 = and(_T_521, _T_520) @[Bitwise.scala 103:31] + node _T_523 = bits(_T_517, 5, 0) @[Bitwise.scala 103:46] + node _T_524 = shl(_T_523, 2) @[Bitwise.scala 103:65] + node _T_525 = not(_T_520) @[Bitwise.scala 103:77] + node _T_526 = and(_T_524, _T_525) @[Bitwise.scala 103:75] + node _T_527 = or(_T_522, _T_526) @[Bitwise.scala 103:39] + node _T_528 = bits(_T_520, 6, 0) @[Bitwise.scala 102:28] + node _T_529 = shl(_T_528, 1) @[Bitwise.scala 102:47] + node _T_530 = xor(_T_520, _T_529) @[Bitwise.scala 102:21] + node _T_531 = shr(_T_527, 1) @[Bitwise.scala 103:21] + node _T_532 = and(_T_531, _T_530) @[Bitwise.scala 103:31] + node _T_533 = bits(_T_527, 6, 0) @[Bitwise.scala 103:46] + node _T_534 = shl(_T_533, 1) @[Bitwise.scala 103:65] + node _T_535 = not(_T_530) @[Bitwise.scala 103:77] + node _T_536 = and(_T_534, _T_535) @[Bitwise.scala 103:75] + node _T_537 = or(_T_532, _T_536) @[Bitwise.scala 103:39] + node _T_538 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_539 = bits(_T_538, 4, 4) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_540 = bits(_T_539, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_541 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_542 = bits(_T_541, 39, 32) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_543 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_544 = bits(picm_rd_data_m, 39, 32) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_545 = bits(dccm_rdata_m, 39, 32) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_546 = mux(_T_543, _T_544, _T_545) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_547 = mux(_T_540, _T_542, _T_546) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_548 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_549 = xor(UInt<8>("h0ff"), _T_548) @[Bitwise.scala 102:21] + node _T_550 = shr(_T_547, 4) @[Bitwise.scala 103:21] + node _T_551 = and(_T_550, _T_549) @[Bitwise.scala 103:31] + node _T_552 = bits(_T_547, 3, 0) @[Bitwise.scala 103:46] + node _T_553 = shl(_T_552, 4) @[Bitwise.scala 103:65] + node _T_554 = not(_T_549) @[Bitwise.scala 103:77] + node _T_555 = and(_T_553, _T_554) @[Bitwise.scala 103:75] + node _T_556 = or(_T_551, _T_555) @[Bitwise.scala 103:39] + node _T_557 = bits(_T_549, 5, 0) @[Bitwise.scala 102:28] + node _T_558 = shl(_T_557, 2) @[Bitwise.scala 102:47] + node _T_559 = xor(_T_549, _T_558) @[Bitwise.scala 102:21] + node _T_560 = shr(_T_556, 2) @[Bitwise.scala 103:21] + node _T_561 = and(_T_560, _T_559) @[Bitwise.scala 103:31] + node _T_562 = bits(_T_556, 5, 0) @[Bitwise.scala 103:46] + node _T_563 = shl(_T_562, 2) @[Bitwise.scala 103:65] + node _T_564 = not(_T_559) @[Bitwise.scala 103:77] + node _T_565 = and(_T_563, _T_564) @[Bitwise.scala 103:75] + node _T_566 = or(_T_561, _T_565) @[Bitwise.scala 103:39] + node _T_567 = bits(_T_559, 6, 0) @[Bitwise.scala 102:28] + node _T_568 = shl(_T_567, 1) @[Bitwise.scala 102:47] + node _T_569 = xor(_T_559, _T_568) @[Bitwise.scala 102:21] + node _T_570 = shr(_T_566, 1) @[Bitwise.scala 103:21] + node _T_571 = and(_T_570, _T_569) @[Bitwise.scala 103:31] + node _T_572 = bits(_T_566, 6, 0) @[Bitwise.scala 103:46] + node _T_573 = shl(_T_572, 1) @[Bitwise.scala 103:65] + node _T_574 = not(_T_569) @[Bitwise.scala 103:77] + node _T_575 = and(_T_573, _T_574) @[Bitwise.scala 103:75] + node _T_576 = or(_T_571, _T_575) @[Bitwise.scala 103:39] + node _T_577 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_578 = bits(_T_577, 5, 5) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_579 = bits(_T_578, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_580 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_581 = bits(_T_580, 47, 40) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_582 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_583 = bits(picm_rd_data_m, 47, 40) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_584 = bits(dccm_rdata_m, 47, 40) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_585 = mux(_T_582, _T_583, _T_584) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_586 = mux(_T_579, _T_581, _T_585) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_587 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_588 = xor(UInt<8>("h0ff"), _T_587) @[Bitwise.scala 102:21] + node _T_589 = shr(_T_586, 4) @[Bitwise.scala 103:21] + node _T_590 = and(_T_589, _T_588) @[Bitwise.scala 103:31] + node _T_591 = bits(_T_586, 3, 0) @[Bitwise.scala 103:46] + node _T_592 = shl(_T_591, 4) @[Bitwise.scala 103:65] + node _T_593 = not(_T_588) @[Bitwise.scala 103:77] + node _T_594 = and(_T_592, _T_593) @[Bitwise.scala 103:75] + node _T_595 = or(_T_590, _T_594) @[Bitwise.scala 103:39] + node _T_596 = bits(_T_588, 5, 0) @[Bitwise.scala 102:28] + node _T_597 = shl(_T_596, 2) @[Bitwise.scala 102:47] + node _T_598 = xor(_T_588, _T_597) @[Bitwise.scala 102:21] + node _T_599 = shr(_T_595, 2) @[Bitwise.scala 103:21] + node _T_600 = and(_T_599, _T_598) @[Bitwise.scala 103:31] + node _T_601 = bits(_T_595, 5, 0) @[Bitwise.scala 103:46] + node _T_602 = shl(_T_601, 2) @[Bitwise.scala 103:65] + node _T_603 = not(_T_598) @[Bitwise.scala 103:77] + node _T_604 = and(_T_602, _T_603) @[Bitwise.scala 103:75] + node _T_605 = or(_T_600, _T_604) @[Bitwise.scala 103:39] + node _T_606 = bits(_T_598, 6, 0) @[Bitwise.scala 102:28] + node _T_607 = shl(_T_606, 1) @[Bitwise.scala 102:47] + node _T_608 = xor(_T_598, _T_607) @[Bitwise.scala 102:21] + node _T_609 = shr(_T_605, 1) @[Bitwise.scala 103:21] + node _T_610 = and(_T_609, _T_608) @[Bitwise.scala 103:31] + node _T_611 = bits(_T_605, 6, 0) @[Bitwise.scala 103:46] + node _T_612 = shl(_T_611, 1) @[Bitwise.scala 103:65] + node _T_613 = not(_T_608) @[Bitwise.scala 103:77] + node _T_614 = and(_T_612, _T_613) @[Bitwise.scala 103:75] + node _T_615 = or(_T_610, _T_614) @[Bitwise.scala 103:39] + node _T_616 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_617 = bits(_T_616, 6, 6) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_618 = bits(_T_617, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_619 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_620 = bits(_T_619, 55, 48) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_621 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_622 = bits(picm_rd_data_m, 55, 48) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_623 = bits(dccm_rdata_m, 55, 48) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_624 = mux(_T_621, _T_622, _T_623) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_625 = mux(_T_618, _T_620, _T_624) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_626 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_627 = xor(UInt<8>("h0ff"), _T_626) @[Bitwise.scala 102:21] + node _T_628 = shr(_T_625, 4) @[Bitwise.scala 103:21] + node _T_629 = and(_T_628, _T_627) @[Bitwise.scala 103:31] + node _T_630 = bits(_T_625, 3, 0) @[Bitwise.scala 103:46] + node _T_631 = shl(_T_630, 4) @[Bitwise.scala 103:65] + node _T_632 = not(_T_627) @[Bitwise.scala 103:77] + node _T_633 = and(_T_631, _T_632) @[Bitwise.scala 103:75] + node _T_634 = or(_T_629, _T_633) @[Bitwise.scala 103:39] + node _T_635 = bits(_T_627, 5, 0) @[Bitwise.scala 102:28] + node _T_636 = shl(_T_635, 2) @[Bitwise.scala 102:47] + node _T_637 = xor(_T_627, _T_636) @[Bitwise.scala 102:21] + node _T_638 = shr(_T_634, 2) @[Bitwise.scala 103:21] + node _T_639 = and(_T_638, _T_637) @[Bitwise.scala 103:31] + node _T_640 = bits(_T_634, 5, 0) @[Bitwise.scala 103:46] + node _T_641 = shl(_T_640, 2) @[Bitwise.scala 103:65] + node _T_642 = not(_T_637) @[Bitwise.scala 103:77] + node _T_643 = and(_T_641, _T_642) @[Bitwise.scala 103:75] + node _T_644 = or(_T_639, _T_643) @[Bitwise.scala 103:39] + node _T_645 = bits(_T_637, 6, 0) @[Bitwise.scala 102:28] + node _T_646 = shl(_T_645, 1) @[Bitwise.scala 102:47] + node _T_647 = xor(_T_637, _T_646) @[Bitwise.scala 102:21] + node _T_648 = shr(_T_644, 1) @[Bitwise.scala 103:21] + node _T_649 = and(_T_648, _T_647) @[Bitwise.scala 103:31] + node _T_650 = bits(_T_644, 6, 0) @[Bitwise.scala 103:46] + node _T_651 = shl(_T_650, 1) @[Bitwise.scala 103:65] + node _T_652 = not(_T_647) @[Bitwise.scala 103:77] + node _T_653 = and(_T_651, _T_652) @[Bitwise.scala 103:75] + node _T_654 = or(_T_649, _T_653) @[Bitwise.scala 103:39] + node _T_655 = cat(io.stbuf_fwdbyteen_hi_m, io.stbuf_fwdbyteen_lo_m) @[Cat.scala 29:58] + node _T_656 = bits(_T_655, 7, 7) @[el2_lsu_dccm_ctl.scala 173:134] + node _T_657 = bits(_T_656, 0, 0) @[el2_lsu_dccm_ctl.scala 173:139] + node _T_658 = cat(io.stbuf_fwddata_hi_m, io.stbuf_fwddata_lo_m) @[Cat.scala 29:58] + node _T_659 = bits(_T_658, 63, 56) @[el2_lsu_dccm_ctl.scala 173:196] + node _T_660 = bits(io.addr_in_pic_m, 0, 0) @[el2_lsu_dccm_ctl.scala 173:231] + node _T_661 = bits(picm_rd_data_m, 63, 56) @[el2_lsu_dccm_ctl.scala 173:252] + node _T_662 = bits(dccm_rdata_m, 63, 56) @[el2_lsu_dccm_ctl.scala 173:278] + node _T_663 = mux(_T_660, _T_661, _T_662) @[el2_lsu_dccm_ctl.scala 173:213] + node _T_664 = mux(_T_657, _T_659, _T_663) @[el2_lsu_dccm_ctl.scala 173:78] + node _T_665 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_666 = xor(UInt<8>("h0ff"), _T_665) @[Bitwise.scala 102:21] + node _T_667 = shr(_T_664, 4) @[Bitwise.scala 103:21] + node _T_668 = and(_T_667, _T_666) @[Bitwise.scala 103:31] + node _T_669 = bits(_T_664, 3, 0) @[Bitwise.scala 103:46] + node _T_670 = shl(_T_669, 4) @[Bitwise.scala 103:65] + node _T_671 = not(_T_666) @[Bitwise.scala 103:77] + node _T_672 = and(_T_670, _T_671) @[Bitwise.scala 103:75] + node _T_673 = or(_T_668, _T_672) @[Bitwise.scala 103:39] + node _T_674 = bits(_T_666, 5, 0) @[Bitwise.scala 102:28] + node _T_675 = shl(_T_674, 2) @[Bitwise.scala 102:47] + node _T_676 = xor(_T_666, _T_675) @[Bitwise.scala 102:21] + node _T_677 = shr(_T_673, 2) @[Bitwise.scala 103:21] + node _T_678 = and(_T_677, _T_676) @[Bitwise.scala 103:31] + node _T_679 = bits(_T_673, 5, 0) @[Bitwise.scala 103:46] + node _T_680 = shl(_T_679, 2) @[Bitwise.scala 103:65] + node _T_681 = not(_T_676) @[Bitwise.scala 103:77] + node _T_682 = and(_T_680, _T_681) @[Bitwise.scala 103:75] + node _T_683 = or(_T_678, _T_682) @[Bitwise.scala 103:39] + node _T_684 = bits(_T_676, 6, 0) @[Bitwise.scala 102:28] + node _T_685 = shl(_T_684, 1) @[Bitwise.scala 102:47] + node _T_686 = xor(_T_676, _T_685) @[Bitwise.scala 102:21] + node _T_687 = shr(_T_683, 1) @[Bitwise.scala 103:21] + node _T_688 = and(_T_687, _T_686) @[Bitwise.scala 103:31] + node _T_689 = bits(_T_683, 6, 0) @[Bitwise.scala 103:46] + node _T_690 = shl(_T_689, 1) @[Bitwise.scala 103:65] + node _T_691 = not(_T_686) @[Bitwise.scala 103:77] + node _T_692 = and(_T_690, _T_691) @[Bitwise.scala 103:75] + node _T_693 = or(_T_688, _T_692) @[Bitwise.scala 103:39] + wire _T_694 : UInt<8>[8] @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[0] <= _T_420 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[1] <= _T_459 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[2] <= _T_498 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[3] <= _T_537 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[4] <= _T_576 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[5] <= _T_615 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[6] <= _T_654 @[el2_lsu_dccm_ctl.scala 173:62] + _T_694[7] <= _T_693 @[el2_lsu_dccm_ctl.scala 173:62] + node _T_695 = cat(_T_694[6], _T_694[7]) @[Cat.scala 29:58] + node _T_696 = cat(_T_694[4], _T_694[5]) @[Cat.scala 29:58] + node _T_697 = cat(_T_696, _T_695) @[Cat.scala 29:58] + node _T_698 = cat(_T_694[2], _T_694[3]) @[Cat.scala 29:58] + node _T_699 = cat(_T_694[0], _T_694[1]) @[Cat.scala 29:58] + node _T_700 = cat(_T_699, _T_698) @[Cat.scala 29:58] + node _T_701 = cat(_T_700, _T_697) @[Cat.scala 29:58] + node _T_702 = shl(UInt<32>("h0ffffffff"), 32) @[Bitwise.scala 102:47] + node _T_703 = xor(UInt<64>("h0ffffffffffffffff"), _T_702) @[Bitwise.scala 102:21] + node _T_704 = shr(_T_701, 32) @[Bitwise.scala 103:21] + node _T_705 = and(_T_704, _T_703) @[Bitwise.scala 103:31] + node _T_706 = bits(_T_701, 31, 0) @[Bitwise.scala 103:46] + node _T_707 = shl(_T_706, 32) @[Bitwise.scala 103:65] + node _T_708 = not(_T_703) @[Bitwise.scala 103:77] + node _T_709 = and(_T_707, _T_708) @[Bitwise.scala 103:75] + node _T_710 = or(_T_705, _T_709) @[Bitwise.scala 103:39] + node _T_711 = bits(_T_703, 47, 0) @[Bitwise.scala 102:28] + node _T_712 = shl(_T_711, 16) @[Bitwise.scala 102:47] + node _T_713 = xor(_T_703, _T_712) @[Bitwise.scala 102:21] + node _T_714 = shr(_T_710, 16) @[Bitwise.scala 103:21] + node _T_715 = and(_T_714, _T_713) @[Bitwise.scala 103:31] + node _T_716 = bits(_T_710, 47, 0) @[Bitwise.scala 103:46] + node _T_717 = shl(_T_716, 16) @[Bitwise.scala 103:65] + node _T_718 = not(_T_713) @[Bitwise.scala 103:77] + node _T_719 = and(_T_717, _T_718) @[Bitwise.scala 103:75] + node _T_720 = or(_T_715, _T_719) @[Bitwise.scala 103:39] + node _T_721 = bits(_T_713, 55, 0) @[Bitwise.scala 102:28] + node _T_722 = shl(_T_721, 8) @[Bitwise.scala 102:47] + node _T_723 = xor(_T_713, _T_722) @[Bitwise.scala 102:21] + node _T_724 = shr(_T_720, 8) @[Bitwise.scala 103:21] + node _T_725 = and(_T_724, _T_723) @[Bitwise.scala 103:31] + node _T_726 = bits(_T_720, 55, 0) @[Bitwise.scala 103:46] + node _T_727 = shl(_T_726, 8) @[Bitwise.scala 103:65] + node _T_728 = not(_T_723) @[Bitwise.scala 103:77] + node _T_729 = and(_T_727, _T_728) @[Bitwise.scala 103:75] + node _T_730 = or(_T_725, _T_729) @[Bitwise.scala 103:39] + node _T_731 = bits(_T_723, 59, 0) @[Bitwise.scala 102:28] + node _T_732 = shl(_T_731, 4) @[Bitwise.scala 102:47] + node _T_733 = xor(_T_723, _T_732) @[Bitwise.scala 102:21] + node _T_734 = shr(_T_730, 4) @[Bitwise.scala 103:21] + node _T_735 = and(_T_734, _T_733) @[Bitwise.scala 103:31] + node _T_736 = bits(_T_730, 59, 0) @[Bitwise.scala 103:46] + node _T_737 = shl(_T_736, 4) @[Bitwise.scala 103:65] + node _T_738 = not(_T_733) @[Bitwise.scala 103:77] + node _T_739 = and(_T_737, _T_738) @[Bitwise.scala 103:75] + node _T_740 = or(_T_735, _T_739) @[Bitwise.scala 103:39] + node _T_741 = bits(_T_733, 61, 0) @[Bitwise.scala 102:28] + node _T_742 = shl(_T_741, 2) @[Bitwise.scala 102:47] + node _T_743 = xor(_T_733, _T_742) @[Bitwise.scala 102:21] + node _T_744 = shr(_T_740, 2) @[Bitwise.scala 103:21] + node _T_745 = and(_T_744, _T_743) @[Bitwise.scala 103:31] + node _T_746 = bits(_T_740, 61, 0) @[Bitwise.scala 103:46] + node _T_747 = shl(_T_746, 2) @[Bitwise.scala 103:65] + node _T_748 = not(_T_743) @[Bitwise.scala 103:77] + node _T_749 = and(_T_747, _T_748) @[Bitwise.scala 103:75] + node _T_750 = or(_T_745, _T_749) @[Bitwise.scala 103:39] + node _T_751 = bits(_T_743, 62, 0) @[Bitwise.scala 102:28] + node _T_752 = shl(_T_751, 1) @[Bitwise.scala 102:47] + node _T_753 = xor(_T_743, _T_752) @[Bitwise.scala 102:21] + node _T_754 = shr(_T_750, 1) @[Bitwise.scala 103:21] + node _T_755 = and(_T_754, _T_753) @[Bitwise.scala 103:31] + node _T_756 = bits(_T_750, 62, 0) @[Bitwise.scala 103:46] + node _T_757 = shl(_T_756, 1) @[Bitwise.scala 103:65] + node _T_758 = not(_T_753) @[Bitwise.scala 103:77] + node _T_759 = and(_T_757, _T_758) @[Bitwise.scala 103:75] + node _T_760 = or(_T_755, _T_759) @[Bitwise.scala 103:39] + lsu_rdata_m <= _T_760 @[el2_lsu_dccm_ctl.scala 173:28] + node _T_761 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 174:63] + node _T_762 = mul(UInt<4>("h08"), _T_761) @[el2_lsu_dccm_ctl.scala 174:49] + node _T_763 = dshr(lsu_rdata_m, _T_762) @[el2_lsu_dccm_ctl.scala 174:43] + io.lsu_ld_data_m <= _T_763 @[el2_lsu_dccm_ctl.scala 174:28] + node _T_764 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 175:68] + node _T_765 = mul(UInt<4>("h08"), _T_764) @[el2_lsu_dccm_ctl.scala 175:54] + node _T_766 = dshr(lsu_rdata_corr_m, _T_765) @[el2_lsu_dccm_ctl.scala 175:48] + lsu_ld_data_corr_m <= _T_766 @[el2_lsu_dccm_ctl.scala 175:28] + node _T_767 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 179:44] + node _T_768 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 179:77] + node _T_769 = eq(_T_767, _T_768) @[el2_lsu_dccm_ctl.scala 179:60] + node _T_770 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 179:117] + node _T_771 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 179:150] + node _T_772 = eq(_T_770, _T_771) @[el2_lsu_dccm_ctl.scala 179:133] + node _T_773 = or(_T_769, _T_772) @[el2_lsu_dccm_ctl.scala 179:101] + node _T_774 = and(_T_773, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 179:175] + node _T_775 = and(_T_774, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 179:196] + node _T_776 = and(_T_775, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 179:217] + node _T_777 = and(_T_776, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 179:236] + node _T_778 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 180:21] + node _T_779 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 180:54] + node _T_780 = eq(_T_778, _T_779) @[el2_lsu_dccm_ctl.scala 180:37] + node _T_781 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 180:94] + node _T_782 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 180:127] + node _T_783 = eq(_T_781, _T_782) @[el2_lsu_dccm_ctl.scala 180:110] + node _T_784 = or(_T_780, _T_783) @[el2_lsu_dccm_ctl.scala 180:78] + node _T_785 = and(_T_784, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 180:152] + node _T_786 = and(_T_785, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 180:173] + node _T_787 = and(_T_786, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 180:194] + node _T_788 = and(_T_787, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 180:213] + node kill_ecc_corr_lo_r = or(_T_777, _T_788) @[el2_lsu_dccm_ctl.scala 179:257] + node _T_789 = bits(io.lsu_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 182:44] + node _T_790 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 182:77] + node _T_791 = eq(_T_789, _T_790) @[el2_lsu_dccm_ctl.scala 182:60] + node _T_792 = bits(io.end_addr_d, 15, 2) @[el2_lsu_dccm_ctl.scala 182:117] + node _T_793 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 182:150] + node _T_794 = eq(_T_792, _T_793) @[el2_lsu_dccm_ctl.scala 182:133] + node _T_795 = or(_T_791, _T_794) @[el2_lsu_dccm_ctl.scala 182:101] + node _T_796 = and(_T_795, io.lsu_pkt_d.valid) @[el2_lsu_dccm_ctl.scala 182:175] + node _T_797 = and(_T_796, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 182:196] + node _T_798 = and(_T_797, io.lsu_pkt_d.dma) @[el2_lsu_dccm_ctl.scala 182:217] + node _T_799 = and(_T_798, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 182:236] + node _T_800 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 183:21] + node _T_801 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 183:54] + node _T_802 = eq(_T_800, _T_801) @[el2_lsu_dccm_ctl.scala 183:37] + node _T_803 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 183:94] + node _T_804 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 183:127] + node _T_805 = eq(_T_803, _T_804) @[el2_lsu_dccm_ctl.scala 183:110] + node _T_806 = or(_T_802, _T_805) @[el2_lsu_dccm_ctl.scala 183:78] + node _T_807 = and(_T_806, io.lsu_pkt_m.valid) @[el2_lsu_dccm_ctl.scala 183:152] + node _T_808 = and(_T_807, io.lsu_pkt_m.store) @[el2_lsu_dccm_ctl.scala 183:173] + node _T_809 = and(_T_808, io.lsu_pkt_m.dma) @[el2_lsu_dccm_ctl.scala 183:194] + node _T_810 = and(_T_809, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 183:213] + node kill_ecc_corr_hi_r = or(_T_799, _T_810) @[el2_lsu_dccm_ctl.scala 182:257] + node _T_811 = and(io.lsu_pkt_r.load, io.single_ecc_error_lo_r) @[el2_lsu_dccm_ctl.scala 185:55] + node _T_812 = eq(io.lsu_raw_fwd_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 185:84] + node ld_single_ecc_error_lo_r = and(_T_811, _T_812) @[el2_lsu_dccm_ctl.scala 185:82] + node _T_813 = and(io.lsu_pkt_r.load, io.single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 186:55] + node _T_814 = eq(io.lsu_raw_fwd_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 186:84] + node ld_single_ecc_error_hi_r = and(_T_813, _T_814) @[el2_lsu_dccm_ctl.scala 186:82] + node _T_815 = or(ld_single_ecc_error_lo_r, ld_single_ecc_error_hi_r) @[el2_lsu_dccm_ctl.scala 187:63] + node _T_816 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 187:93] + node _T_817 = and(_T_815, _T_816) @[el2_lsu_dccm_ctl.scala 187:91] + io.ld_single_ecc_error_r <= _T_817 @[el2_lsu_dccm_ctl.scala 187:34] + node _T_818 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 188:81] + node _T_819 = and(ld_single_ecc_error_lo_r, _T_818) @[el2_lsu_dccm_ctl.scala 188:62] + node _T_820 = eq(kill_ecc_corr_lo_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 188:103] + node ld_single_ecc_error_lo_r_ns = and(_T_819, _T_820) @[el2_lsu_dccm_ctl.scala 188:101] + node _T_821 = or(io.lsu_commit_r, io.lsu_pkt_r.dma) @[el2_lsu_dccm_ctl.scala 189:81] + node _T_822 = and(ld_single_ecc_error_hi_r, _T_821) @[el2_lsu_dccm_ctl.scala 189:62] + node _T_823 = eq(kill_ecc_corr_hi_r, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 189:103] + node ld_single_ecc_error_hi_r_ns = and(_T_822, _T_823) @[el2_lsu_dccm_ctl.scala 189:101] + reg lsu_double_ecc_error_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 191:74] + lsu_double_ecc_error_r_ff <= io.lsu_double_ecc_error_r @[el2_lsu_dccm_ctl.scala 191:74] + reg ld_single_ecc_error_hi_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 192:74] + ld_single_ecc_error_hi_r_ff <= ld_single_ecc_error_hi_r_ns @[el2_lsu_dccm_ctl.scala 192:74] + reg ld_single_ecc_error_lo_r_ff : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 193:74] + ld_single_ecc_error_lo_r_ff <= ld_single_ecc_error_lo_r_ns @[el2_lsu_dccm_ctl.scala 193:74] + node _T_824 = bits(io.end_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 195:49] + node _T_825 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 195:90] + node _T_826 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 195:116] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] rvclkhdr.clock <= clock rvclkhdr.reset <= reset - rvclkhdr.io.clk <= io.clk @[beh_lib.scala 353:16] - rvclkhdr.io.en <= _T_248 @[beh_lib.scala 354:15] - rvclkhdr.io.scan_mode <= _T_249 @[beh_lib.scala 355:22] - reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 357:14] - ld_sec_addr_hi_r_ff <= _T_247 @[beh_lib.scala 357:14] - node _T_250 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 207:49] - node _T_251 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 207:94] - node _T_252 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 207:121] - inst rvclkhdr_1 of rvclkhdr_1 @[beh_lib.scala 351:21] + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_825 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= _T_826 @[el2_lib.scala 512:24] + reg ld_sec_addr_hi_r_ff : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + ld_sec_addr_hi_r_ff <= _T_824 @[el2_lib.scala 514:16] + node _T_827 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_dccm_ctl.scala 196:49] + node _T_828 = bits(io.ld_single_ecc_error_r, 0, 0) @[el2_lsu_dccm_ctl.scala 196:90] + node _T_829 = bits(io.scan_mode, 0, 0) @[el2_lsu_dccm_ctl.scala 196:116] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] rvclkhdr_1.clock <= clock rvclkhdr_1.reset <= reset - rvclkhdr_1.io.clk <= io.clk @[beh_lib.scala 353:16] - rvclkhdr_1.io.en <= _T_251 @[beh_lib.scala 354:15] - rvclkhdr_1.io.scan_mode <= _T_252 @[beh_lib.scala 355:22] - reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 357:14] - ld_sec_addr_lo_r_ff <= _T_250 @[beh_lib.scala 357:14] - node _T_253 = or(io.lsu_pkt_d.word, io.lsu_pkt_d.dword) @[el2_lsu_dccm_ctl.scala 208:110] - node _T_254 = not(_T_253) @[el2_lsu_dccm_ctl.scala 208:90] - node _T_255 = bits(io.lsu_addr_d, 1, 0) @[el2_lsu_dccm_ctl.scala 208:148] - node _T_256 = neq(_T_255, UInt<2>("h00")) @[el2_lsu_dccm_ctl.scala 208:154] - node _T_257 = or(_T_254, _T_256) @[el2_lsu_dccm_ctl.scala 208:132] - node _T_258 = and(io.lsu_pkt_d.store, _T_257) @[el2_lsu_dccm_ctl.scala 208:87] - node _T_259 = or(io.lsu_pkt_d.load, _T_258) @[el2_lsu_dccm_ctl.scala 208:65] - node _T_260 = and(io.lsu_pkt_d.valid, _T_259) @[el2_lsu_dccm_ctl.scala 208:44] - node lsu_dccm_rden_d = and(_T_260, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 208:171] - node _T_261 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[el2_lsu_dccm_ctl.scala 211:63] - node _T_262 = not(lsu_double_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 211:96] - node _T_263 = and(_T_261, _T_262) @[el2_lsu_dccm_ctl.scala 211:94] - io.ld_single_ecc_error_r_ff <= _T_263 @[el2_lsu_dccm_ctl.scala 211:31] - node _T_264 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[el2_lsu_dccm_ctl.scala 212:71] - node _T_265 = or(_T_264, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 212:89] - node _T_266 = not(_T_265) @[el2_lsu_dccm_ctl.scala 212:53] - node _T_267 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 213:44] - node _T_268 = bits(io.lsu_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 213:124] - node _T_269 = eq(_T_267, _T_268) @[el2_lsu_dccm_ctl.scala 213:107] - node _T_270 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 214:25] - node _T_271 = bits(io.end_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 214:105] - node _T_272 = eq(_T_270, _T_271) @[el2_lsu_dccm_ctl.scala 214:88] - node _T_273 = or(_T_269, _T_272) @[el2_lsu_dccm_ctl.scala 213:195] - node _T_274 = not(_T_273) @[el2_lsu_dccm_ctl.scala 213:24] - node _T_275 = and(lsu_dccm_rden_d, _T_274) @[el2_lsu_dccm_ctl.scala 213:22] - node _T_276 = or(_T_266, _T_275) @[el2_lsu_dccm_ctl.scala 212:120] - node _T_277 = and(io.stbuf_reqvld_any, _T_276) @[el2_lsu_dccm_ctl.scala 212:50] - io.lsu_stbuf_commit_any <= _T_277 @[el2_lsu_dccm_ctl.scala 212:27] - node _T_278 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[el2_lsu_dccm_ctl.scala 217:41] - node _T_279 = or(_T_278, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 217:67] - io.dccm_wren <= _T_279 @[el2_lsu_dccm_ctl.scala 217:22] - node _T_280 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 218:41] - io.dccm_rden <= _T_280 @[el2_lsu_dccm_ctl.scala 218:22] - node _T_281 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 219:57] - node _T_282 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 220:36] - node _T_283 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 220:62] - node _T_284 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 220:101] - node _T_285 = mux(_T_282, _T_283, _T_284) @[el2_lsu_dccm_ctl.scala 220:8] - node _T_286 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 221:25] - node _T_287 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 221:45] - node _T_288 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 221:82] - node _T_289 = mux(_T_286, _T_287, _T_288) @[el2_lsu_dccm_ctl.scala 221:8] - node _T_290 = mux(_T_281, _T_285, _T_289) @[el2_lsu_dccm_ctl.scala 219:28] - io.dccm_wr_addr_lo <= _T_290 @[el2_lsu_dccm_ctl.scala 219:22] - node _T_291 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 222:57] - node _T_292 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 223:36] - node _T_293 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 223:63] - node _T_294 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 223:103] - node _T_295 = mux(_T_292, _T_293, _T_294) @[el2_lsu_dccm_ctl.scala 223:8] - node _T_296 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 224:25] - node _T_297 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 224:46] - node _T_298 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 224:83] - node _T_299 = mux(_T_296, _T_297, _T_298) @[el2_lsu_dccm_ctl.scala 224:8] - node _T_300 = mux(_T_291, _T_295, _T_299) @[el2_lsu_dccm_ctl.scala 222:28] - io.dccm_wr_addr_hi <= _T_300 @[el2_lsu_dccm_ctl.scala 222:22] - node _T_301 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 225:38] - io.dccm_rd_addr_lo <= _T_301 @[el2_lsu_dccm_ctl.scala 225:22] - node _T_302 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 226:38] - io.dccm_rd_addr_hi <= _T_302 @[el2_lsu_dccm_ctl.scala 226:22] - node _T_303 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 227:57] - node _T_304 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 228:36] - node _T_305 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 228:70] - node _T_306 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 228:114] - node _T_307 = cat(_T_305, _T_306) @[Cat.scala 29:58] - node _T_308 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 229:34] - node _T_309 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 229:78] - node _T_310 = cat(_T_308, _T_309) @[Cat.scala 29:58] - node _T_311 = mux(_T_304, _T_307, _T_310) @[el2_lsu_dccm_ctl.scala 228:8] - node _T_312 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 230:25] - node _T_313 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[el2_lsu_dccm_ctl.scala 230:60] - node _T_314 = bits(io.dma_dccm_wdata_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 230:105] - node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58] - node _T_316 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 231:27] - node _T_317 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 231:69] - node _T_318 = cat(_T_316, _T_317) @[Cat.scala 29:58] - node _T_319 = mux(_T_312, _T_315, _T_318) @[el2_lsu_dccm_ctl.scala 230:8] - node _T_320 = mux(_T_303, _T_311, _T_319) @[el2_lsu_dccm_ctl.scala 227:28] - io.dccm_wr_data_lo <= _T_320 @[el2_lsu_dccm_ctl.scala 227:22] - node _T_321 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 233:57] - node _T_322 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 234:36] - node _T_323 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 234:71] - node _T_324 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 234:115] - node _T_325 = cat(_T_323, _T_324) @[Cat.scala 29:58] - node _T_326 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 235:34] - node _T_327 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 235:78] - node _T_328 = cat(_T_326, _T_327) @[Cat.scala 29:58] - node _T_329 = mux(_T_322, _T_325, _T_328) @[el2_lsu_dccm_ctl.scala 234:8] - node _T_330 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 236:25] - node _T_331 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[el2_lsu_dccm_ctl.scala 236:61] - node _T_332 = bits(io.dma_dccm_wdata_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 236:106] - node _T_333 = cat(_T_331, _T_332) @[Cat.scala 29:58] - node _T_334 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 237:27] - node _T_335 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 237:69] - node _T_336 = cat(_T_334, _T_335) @[Cat.scala 29:58] - node _T_337 = mux(_T_330, _T_333, _T_336) @[el2_lsu_dccm_ctl.scala 236:8] - node _T_338 = mux(_T_321, _T_329, _T_337) @[el2_lsu_dccm_ctl.scala 233:28] - io.dccm_wr_data_hi <= _T_338 @[el2_lsu_dccm_ctl.scala 233:22] - node _T_339 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15] - node _T_340 = mux(_T_339, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_341 = bits(io.lsu_pkt_m.by, 0, 0) @[Bitwise.scala 72:15] - node _T_342 = mux(_T_341, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_343 = and(_T_342, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 240:84] - node _T_344 = bits(io.lsu_pkt_m.half, 0, 0) @[Bitwise.scala 72:15] - node _T_345 = mux(_T_344, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_346 = and(_T_345, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 241:33] - node _T_347 = or(_T_343, _T_346) @[el2_lsu_dccm_ctl.scala 240:97] - node _T_348 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] - node _T_349 = mux(_T_348, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_350 = and(_T_349, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 242:33] - node _T_351 = or(_T_347, _T_350) @[el2_lsu_dccm_ctl.scala 241:46] - node store_byteen_m = and(_T_340, _T_351) @[el2_lsu_dccm_ctl.scala 240:53] - node _T_352 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] - node _T_353 = mux(_T_352, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_354 = bits(io.lsu_pkt_r.by, 0, 0) @[Bitwise.scala 72:15] - node _T_355 = mux(_T_354, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_356 = and(_T_355, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 243:84] - node _T_357 = bits(io.lsu_pkt_r.half, 0, 0) @[Bitwise.scala 72:15] - node _T_358 = mux(_T_357, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_359 = and(_T_358, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 244:33] - node _T_360 = or(_T_356, _T_359) @[el2_lsu_dccm_ctl.scala 243:97] - node _T_361 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] - node _T_362 = mux(_T_361, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_363 = and(_T_362, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 245:33] - node _T_364 = or(_T_360, _T_363) @[el2_lsu_dccm_ctl.scala 244:46] - node store_byteen_r = and(_T_353, _T_364) @[el2_lsu_dccm_ctl.scala 243:53] - node _T_365 = bits(store_byteen_m, 3, 0) @[el2_lsu_dccm_ctl.scala 246:55] - node _T_366 = cat(UInt<4>("h00"), _T_365) @[Cat.scala 29:58] - node _T_367 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 246:78] - node store_byteen_ext_m = dshl(_T_366, _T_367) @[el2_lsu_dccm_ctl.scala 246:62] - node _T_368 = bits(store_byteen_r, 3, 0) @[el2_lsu_dccm_ctl.scala 247:55] - node _T_369 = cat(UInt<4>("h00"), _T_368) @[Cat.scala 29:58] - node _T_370 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 247:78] - node store_byteen_ext_r = dshl(_T_369, _T_370) @[el2_lsu_dccm_ctl.scala 247:62] - node _T_371 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 250:51] - node _T_372 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 250:88] - node _T_373 = eq(_T_371, _T_372) @[el2_lsu_dccm_ctl.scala 250:71] - node dccm_wr_bypass_d_m_lo = and(_T_373, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 250:109] - node _T_374 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 251:51] - node _T_375 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 251:88] - node _T_376 = eq(_T_374, _T_375) @[el2_lsu_dccm_ctl.scala 251:71] - node dccm_wr_bypass_d_m_hi = and(_T_376, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 251:109] - node _T_377 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 253:51] - node _T_378 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 253:88] - node _T_379 = eq(_T_377, _T_378) @[el2_lsu_dccm_ctl.scala 253:71] - node dccm_wr_bypass_d_r_lo = and(_T_379, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 253:109] - node _T_380 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 254:51] - node _T_381 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 254:88] - node _T_382 = eq(_T_380, _T_381) @[el2_lsu_dccm_ctl.scala 254:71] - node dccm_wr_bypass_d_r_hi = and(_T_382, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 254:109] + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_828 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= _T_829 @[el2_lib.scala 512:24] + reg ld_sec_addr_lo_r_ff : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + ld_sec_addr_lo_r_ff <= _T_827 @[el2_lib.scala 514:16] + node _T_830 = or(io.lsu_pkt_d.word, io.lsu_pkt_d.dword) @[el2_lsu_dccm_ctl.scala 197:110] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 197:90] + node _T_832 = bits(io.lsu_addr_d, 1, 0) @[el2_lsu_dccm_ctl.scala 197:148] + node _T_833 = neq(_T_832, UInt<2>("h00")) @[el2_lsu_dccm_ctl.scala 197:154] + node _T_834 = or(_T_831, _T_833) @[el2_lsu_dccm_ctl.scala 197:132] + node _T_835 = and(io.lsu_pkt_d.store, _T_834) @[el2_lsu_dccm_ctl.scala 197:87] + node _T_836 = or(io.lsu_pkt_d.load, _T_835) @[el2_lsu_dccm_ctl.scala 197:65] + node _T_837 = and(io.lsu_pkt_d.valid, _T_836) @[el2_lsu_dccm_ctl.scala 197:44] + node lsu_dccm_rden_d = and(_T_837, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 197:171] + node _T_838 = or(ld_single_ecc_error_lo_r_ff, ld_single_ecc_error_hi_r_ff) @[el2_lsu_dccm_ctl.scala 200:63] + node _T_839 = eq(lsu_double_ecc_error_r_ff, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 200:96] + node _T_840 = and(_T_838, _T_839) @[el2_lsu_dccm_ctl.scala 200:94] + io.ld_single_ecc_error_r_ff <= _T_840 @[el2_lsu_dccm_ctl.scala 200:31] + node _T_841 = or(lsu_dccm_rden_d, io.dma_dccm_wen) @[el2_lsu_dccm_ctl.scala 201:75] + node _T_842 = or(_T_841, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 201:93] + node _T_843 = eq(_T_842, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 201:57] + node _T_844 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 202:44] + node _T_845 = bits(io.lsu_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 202:112] + node _T_846 = eq(_T_844, _T_845) @[el2_lsu_dccm_ctl.scala 202:95] + node _T_847 = bits(io.stbuf_addr_any, 3, 2) @[el2_lsu_dccm_ctl.scala 203:25] + node _T_848 = bits(io.end_addr_d, 3, 2) @[el2_lsu_dccm_ctl.scala 203:93] + node _T_849 = eq(_T_847, _T_848) @[el2_lsu_dccm_ctl.scala 203:76] + node _T_850 = or(_T_846, _T_849) @[el2_lsu_dccm_ctl.scala 202:171] + node _T_851 = eq(_T_850, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 202:24] + node _T_852 = and(lsu_dccm_rden_d, _T_851) @[el2_lsu_dccm_ctl.scala 202:22] + node _T_853 = or(_T_843, _T_852) @[el2_lsu_dccm_ctl.scala 201:124] + node _T_854 = and(io.stbuf_reqvld_any, _T_853) @[el2_lsu_dccm_ctl.scala 201:54] + io.lsu_stbuf_commit_any <= _T_854 @[el2_lsu_dccm_ctl.scala 201:31] + node _T_855 = or(io.dma_dccm_wen, io.lsu_stbuf_commit_any) @[el2_lsu_dccm_ctl.scala 207:41] + node _T_856 = or(_T_855, io.ld_single_ecc_error_r_ff) @[el2_lsu_dccm_ctl.scala 207:67] + io.dccm_wren <= _T_856 @[el2_lsu_dccm_ctl.scala 207:22] + node _T_857 = and(lsu_dccm_rden_d, io.addr_in_dccm_d) @[el2_lsu_dccm_ctl.scala 208:41] + io.dccm_rden <= _T_857 @[el2_lsu_dccm_ctl.scala 208:22] + node _T_858 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 210:57] + node _T_859 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 211:36] + node _T_860 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 211:62] + node _T_861 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 211:97] + node _T_862 = mux(_T_859, _T_860, _T_861) @[el2_lsu_dccm_ctl.scala 211:8] + node _T_863 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 212:25] + node _T_864 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 212:45] + node _T_865 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 212:78] + node _T_866 = mux(_T_863, _T_864, _T_865) @[el2_lsu_dccm_ctl.scala 212:8] + node _T_867 = mux(_T_858, _T_862, _T_866) @[el2_lsu_dccm_ctl.scala 210:28] + io.dccm_wr_addr_lo <= _T_867 @[el2_lsu_dccm_ctl.scala 210:22] + node _T_868 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 214:57] + node _T_869 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 215:36] + node _T_870 = bits(ld_sec_addr_hi_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 215:63] + node _T_871 = bits(ld_sec_addr_lo_r_ff, 15, 0) @[el2_lsu_dccm_ctl.scala 215:99] + node _T_872 = mux(_T_869, _T_870, _T_871) @[el2_lsu_dccm_ctl.scala 215:8] + node _T_873 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 216:25] + node _T_874 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 216:46] + node _T_875 = bits(io.stbuf_addr_any, 15, 0) @[el2_lsu_dccm_ctl.scala 216:79] + node _T_876 = mux(_T_873, _T_874, _T_875) @[el2_lsu_dccm_ctl.scala 216:8] + node _T_877 = mux(_T_868, _T_872, _T_876) @[el2_lsu_dccm_ctl.scala 214:28] + io.dccm_wr_addr_hi <= _T_877 @[el2_lsu_dccm_ctl.scala 214:22] + node _T_878 = bits(io.lsu_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 218:38] + io.dccm_rd_addr_lo <= _T_878 @[el2_lsu_dccm_ctl.scala 218:22] + node _T_879 = bits(io.end_addr_d, 15, 0) @[el2_lsu_dccm_ctl.scala 219:38] + io.dccm_rd_addr_hi <= _T_879 @[el2_lsu_dccm_ctl.scala 219:22] + node _T_880 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 221:57] + node _T_881 = eq(ld_single_ecc_error_lo_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 222:36] + node _T_882 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 222:70] + node _T_883 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 222:110] + node _T_884 = cat(_T_882, _T_883) @[Cat.scala 29:58] + node _T_885 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 223:34] + node _T_886 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 223:74] + node _T_887 = cat(_T_885, _T_886) @[Cat.scala 29:58] + node _T_888 = mux(_T_881, _T_884, _T_887) @[el2_lsu_dccm_ctl.scala 222:8] + node _T_889 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 224:25] + node _T_890 = bits(io.dma_dccm_wdata_ecc_lo, 6, 0) @[el2_lsu_dccm_ctl.scala 224:60] + node _T_891 = bits(io.dma_dccm_wdata_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 224:101] + node _T_892 = cat(_T_890, _T_891) @[Cat.scala 29:58] + node _T_893 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 225:27] + node _T_894 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 225:65] + node _T_895 = cat(_T_893, _T_894) @[Cat.scala 29:58] + node _T_896 = mux(_T_889, _T_892, _T_895) @[el2_lsu_dccm_ctl.scala 224:8] + node _T_897 = mux(_T_880, _T_888, _T_896) @[el2_lsu_dccm_ctl.scala 221:28] + io.dccm_wr_data_lo <= _T_897 @[el2_lsu_dccm_ctl.scala 221:22] + node _T_898 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_dccm_ctl.scala 227:57] + node _T_899 = eq(ld_single_ecc_error_hi_r_ff, UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 228:36] + node _T_900 = bits(io.sec_data_ecc_hi_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 228:71] + node _T_901 = bits(io.sec_data_hi_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 228:111] + node _T_902 = cat(_T_900, _T_901) @[Cat.scala 29:58] + node _T_903 = bits(io.sec_data_ecc_lo_r_ff, 6, 0) @[el2_lsu_dccm_ctl.scala 229:34] + node _T_904 = bits(io.sec_data_lo_r_ff, 31, 0) @[el2_lsu_dccm_ctl.scala 229:74] + node _T_905 = cat(_T_903, _T_904) @[Cat.scala 29:58] + node _T_906 = mux(_T_899, _T_902, _T_905) @[el2_lsu_dccm_ctl.scala 228:8] + node _T_907 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 230:25] + node _T_908 = bits(io.dma_dccm_wdata_ecc_hi, 6, 0) @[el2_lsu_dccm_ctl.scala 230:61] + node _T_909 = bits(io.dma_dccm_wdata_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 230:102] + node _T_910 = cat(_T_908, _T_909) @[Cat.scala 29:58] + node _T_911 = bits(io.stbuf_ecc_any, 6, 0) @[el2_lsu_dccm_ctl.scala 231:27] + node _T_912 = bits(io.stbuf_data_any, 31, 0) @[el2_lsu_dccm_ctl.scala 231:65] + node _T_913 = cat(_T_911, _T_912) @[Cat.scala 29:58] + node _T_914 = mux(_T_907, _T_910, _T_913) @[el2_lsu_dccm_ctl.scala 230:8] + node _T_915 = mux(_T_898, _T_906, _T_914) @[el2_lsu_dccm_ctl.scala 227:28] + io.dccm_wr_data_hi <= _T_915 @[el2_lsu_dccm_ctl.scala 227:22] + node _T_916 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15] + node _T_917 = mux(_T_916, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_918 = bits(io.lsu_pkt_m.by, 0, 0) @[Bitwise.scala 72:15] + node _T_919 = mux(_T_918, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_920 = and(_T_919, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 234:84] + node _T_921 = bits(io.lsu_pkt_m.half, 0, 0) @[Bitwise.scala 72:15] + node _T_922 = mux(_T_921, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_923 = and(_T_922, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 235:33] + node _T_924 = or(_T_920, _T_923) @[el2_lsu_dccm_ctl.scala 234:97] + node _T_925 = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] + node _T_926 = mux(_T_925, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_927 = and(_T_926, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 236:33] + node _T_928 = or(_T_924, _T_927) @[el2_lsu_dccm_ctl.scala 235:46] + node store_byteen_m = and(_T_917, _T_928) @[el2_lsu_dccm_ctl.scala 234:53] + node _T_929 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] + node _T_930 = mux(_T_929, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_931 = bits(io.lsu_pkt_r.by, 0, 0) @[Bitwise.scala 72:15] + node _T_932 = mux(_T_931, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_933 = and(_T_932, UInt<4>("h01")) @[el2_lsu_dccm_ctl.scala 238:84] + node _T_934 = bits(io.lsu_pkt_r.half, 0, 0) @[Bitwise.scala 72:15] + node _T_935 = mux(_T_934, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_936 = and(_T_935, UInt<4>("h03")) @[el2_lsu_dccm_ctl.scala 239:33] + node _T_937 = or(_T_933, _T_936) @[el2_lsu_dccm_ctl.scala 238:97] + node _T_938 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] + node _T_939 = mux(_T_938, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_940 = and(_T_939, UInt<4>("h0f")) @[el2_lsu_dccm_ctl.scala 240:33] + node _T_941 = or(_T_937, _T_940) @[el2_lsu_dccm_ctl.scala 239:46] + node store_byteen_r = and(_T_930, _T_941) @[el2_lsu_dccm_ctl.scala 238:53] + wire store_byteen_ext_m : UInt<8> + store_byteen_ext_m <= UInt<1>("h00") + node _T_942 = bits(store_byteen_m, 3, 0) @[el2_lsu_dccm_ctl.scala 242:39] + node _T_943 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 242:61] + node _T_944 = dshl(_T_942, _T_943) @[el2_lsu_dccm_ctl.scala 242:45] + store_byteen_ext_m <= _T_944 @[el2_lsu_dccm_ctl.scala 242:22] + wire store_byteen_ext_r : UInt<8> + store_byteen_ext_r <= UInt<1>("h00") + node _T_945 = bits(store_byteen_r, 3, 0) @[el2_lsu_dccm_ctl.scala 244:39] + node _T_946 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 244:61] + node _T_947 = dshl(_T_945, _T_946) @[el2_lsu_dccm_ctl.scala 244:45] + store_byteen_ext_r <= _T_947 @[el2_lsu_dccm_ctl.scala 244:22] + node _T_948 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 247:51] + node _T_949 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 247:84] + node _T_950 = eq(_T_948, _T_949) @[el2_lsu_dccm_ctl.scala 247:67] + node dccm_wr_bypass_d_m_lo = and(_T_950, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 247:101] + node _T_951 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 248:51] + node _T_952 = bits(io.end_addr_m, 15, 2) @[el2_lsu_dccm_ctl.scala 248:84] + node _T_953 = eq(_T_951, _T_952) @[el2_lsu_dccm_ctl.scala 248:67] + node dccm_wr_bypass_d_m_hi = and(_T_953, io.addr_in_dccm_m) @[el2_lsu_dccm_ctl.scala 248:101] + node _T_954 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 250:51] + node _T_955 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 250:84] + node _T_956 = eq(_T_954, _T_955) @[el2_lsu_dccm_ctl.scala 250:67] + node dccm_wr_bypass_d_r_lo = and(_T_956, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 250:101] + node _T_957 = bits(io.stbuf_addr_any, 15, 2) @[el2_lsu_dccm_ctl.scala 251:51] + node _T_958 = bits(io.end_addr_r, 15, 2) @[el2_lsu_dccm_ctl.scala 251:84] + node _T_959 = eq(_T_957, _T_958) @[el2_lsu_dccm_ctl.scala 251:67] + node dccm_wr_bypass_d_r_hi = and(_T_959, io.addr_in_dccm_r) @[el2_lsu_dccm_ctl.scala 251:101] wire dccm_wr_bypass_d_m_hi_Q : UInt<1> dccm_wr_bypass_d_m_hi_Q <= UInt<1>("h00") wire dccm_wr_bypass_d_m_lo_Q : UInt<1> @@ -1593,328 +1920,1226 @@ circuit el2_lsu : store_data_hi_m <= UInt<32>("h00") wire store_data_lo_m : UInt<32> store_data_lo_m <= UInt<32>("h00") - node _T_383 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_384 = bits(io.store_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 287:64] - node _T_385 = cat(_T_383, _T_384) @[Cat.scala 29:58] - node _T_386 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 287:92] - node _T_387 = mul(UInt<4>("h08"), _T_386) @[el2_lsu_dccm_ctl.scala 287:78] - node _T_388 = dshl(_T_385, _T_387) @[el2_lsu_dccm_ctl.scala 287:72] - store_data_pre_m <= _T_388 @[el2_lsu_dccm_ctl.scala 287:29] - node _T_389 = bits(store_data_pre_m, 63, 32) @[el2_lsu_dccm_ctl.scala 288:48] - store_data_hi_m <= _T_389 @[el2_lsu_dccm_ctl.scala 288:29] - node _T_390 = bits(store_data_pre_m, 31, 0) @[el2_lsu_dccm_ctl.scala 289:48] - store_data_lo_m <= _T_390 @[el2_lsu_dccm_ctl.scala 289:29] - node _T_391 = bits(store_byteen_ext_m, 0, 0) @[el2_lsu_dccm_ctl.scala 290:123] - node _T_392 = bits(_T_391, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127] - node _T_393 = bits(store_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 290:151] - node _T_394 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195] - node _T_395 = bits(_T_394, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221] - node _T_396 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 290:246] - node _T_397 = bits(io.sec_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 290:276] - node _T_398 = mux(_T_395, _T_396, _T_397) @[el2_lsu_dccm_ctl.scala 290:169] - node _T_399 = mux(_T_392, _T_393, _T_398) @[el2_lsu_dccm_ctl.scala 290:104] - node _T_400 = bits(store_byteen_ext_m, 1, 1) @[el2_lsu_dccm_ctl.scala 290:123] - node _T_401 = bits(_T_400, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127] - node _T_402 = bits(store_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 290:151] - node _T_403 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195] - node _T_404 = bits(_T_403, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221] - node _T_405 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 290:246] - node _T_406 = bits(io.sec_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 290:276] - node _T_407 = mux(_T_404, _T_405, _T_406) @[el2_lsu_dccm_ctl.scala 290:169] - node _T_408 = mux(_T_401, _T_402, _T_407) @[el2_lsu_dccm_ctl.scala 290:104] - node _T_409 = bits(store_byteen_ext_m, 2, 2) @[el2_lsu_dccm_ctl.scala 290:123] - node _T_410 = bits(_T_409, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127] - node _T_411 = bits(store_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 290:151] - node _T_412 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195] - node _T_413 = bits(_T_412, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221] - node _T_414 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 290:246] - node _T_415 = bits(io.sec_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 290:276] - node _T_416 = mux(_T_413, _T_414, _T_415) @[el2_lsu_dccm_ctl.scala 290:169] - node _T_417 = mux(_T_410, _T_411, _T_416) @[el2_lsu_dccm_ctl.scala 290:104] - node _T_418 = bits(store_byteen_ext_m, 3, 3) @[el2_lsu_dccm_ctl.scala 290:123] - node _T_419 = bits(_T_418, 0, 0) @[el2_lsu_dccm_ctl.scala 290:127] - node _T_420 = bits(store_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 290:151] - node _T_421 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 290:195] - node _T_422 = bits(_T_421, 0, 0) @[el2_lsu_dccm_ctl.scala 290:221] - node _T_423 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 290:246] - node _T_424 = bits(io.sec_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 290:276] - node _T_425 = mux(_T_422, _T_423, _T_424) @[el2_lsu_dccm_ctl.scala 290:169] - node _T_426 = mux(_T_419, _T_420, _T_425) @[el2_lsu_dccm_ctl.scala 290:104] - wire _T_427 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 290:96] - _T_427[0] <= _T_399 @[el2_lsu_dccm_ctl.scala 290:96] - _T_427[1] <= _T_408 @[el2_lsu_dccm_ctl.scala 290:96] - _T_427[2] <= _T_417 @[el2_lsu_dccm_ctl.scala 290:96] - _T_427[3] <= _T_426 @[el2_lsu_dccm_ctl.scala 290:96] - node _T_428 = cat(_T_427[2], _T_427[3]) @[Cat.scala 29:58] - node _T_429 = cat(_T_427[0], _T_427[1]) @[Cat.scala 29:58] - node _T_430 = cat(_T_429, _T_428) @[Cat.scala 29:58] - reg _T_431 : UInt, io.lsu_store_c1_r_clk @[el2_lsu_dccm_ctl.scala 290:72] - _T_431 <= _T_430 @[el2_lsu_dccm_ctl.scala 290:72] - io.store_data_lo_r <= _T_431 @[el2_lsu_dccm_ctl.scala 290:29] - node _T_432 = bits(store_byteen_ext_m, 4, 4) @[el2_lsu_dccm_ctl.scala 291:123] - node _T_433 = bits(_T_432, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129] - node _T_434 = bits(store_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 291:151] - node _T_435 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195] - node _T_436 = bits(_T_435, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221] - node _T_437 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 291:246] - node _T_438 = bits(io.sec_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 291:276] - node _T_439 = mux(_T_436, _T_437, _T_438) @[el2_lsu_dccm_ctl.scala 291:169] - node _T_440 = mux(_T_433, _T_434, _T_439) @[el2_lsu_dccm_ctl.scala 291:104] - node _T_441 = bits(store_byteen_ext_m, 5, 5) @[el2_lsu_dccm_ctl.scala 291:123] - node _T_442 = bits(_T_441, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129] - node _T_443 = bits(store_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 291:151] - node _T_444 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195] - node _T_445 = bits(_T_444, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221] - node _T_446 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 291:246] - node _T_447 = bits(io.sec_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 291:276] - node _T_448 = mux(_T_445, _T_446, _T_447) @[el2_lsu_dccm_ctl.scala 291:169] - node _T_449 = mux(_T_442, _T_443, _T_448) @[el2_lsu_dccm_ctl.scala 291:104] - node _T_450 = bits(store_byteen_ext_m, 6, 6) @[el2_lsu_dccm_ctl.scala 291:123] - node _T_451 = bits(_T_450, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129] - node _T_452 = bits(store_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 291:151] - node _T_453 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195] - node _T_454 = bits(_T_453, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221] - node _T_455 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 291:246] - node _T_456 = bits(io.sec_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 291:276] - node _T_457 = mux(_T_454, _T_455, _T_456) @[el2_lsu_dccm_ctl.scala 291:169] - node _T_458 = mux(_T_451, _T_452, _T_457) @[el2_lsu_dccm_ctl.scala 291:104] - node _T_459 = bits(store_byteen_ext_m, 7, 7) @[el2_lsu_dccm_ctl.scala 291:123] - node _T_460 = bits(_T_459, 0, 0) @[el2_lsu_dccm_ctl.scala 291:129] - node _T_461 = bits(store_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 291:151] - node _T_462 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 291:195] - node _T_463 = bits(_T_462, 0, 0) @[el2_lsu_dccm_ctl.scala 291:221] - node _T_464 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 291:246] - node _T_465 = bits(io.sec_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 291:276] - node _T_466 = mux(_T_463, _T_464, _T_465) @[el2_lsu_dccm_ctl.scala 291:169] - node _T_467 = mux(_T_460, _T_461, _T_466) @[el2_lsu_dccm_ctl.scala 291:104] - wire _T_468 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 291:96] - _T_468[0] <= _T_440 @[el2_lsu_dccm_ctl.scala 291:96] - _T_468[1] <= _T_449 @[el2_lsu_dccm_ctl.scala 291:96] - _T_468[2] <= _T_458 @[el2_lsu_dccm_ctl.scala 291:96] - _T_468[3] <= _T_467 @[el2_lsu_dccm_ctl.scala 291:96] - node _T_469 = cat(_T_468[2], _T_468[3]) @[Cat.scala 29:58] - node _T_470 = cat(_T_468[0], _T_468[1]) @[Cat.scala 29:58] - node _T_471 = cat(_T_470, _T_469) @[Cat.scala 29:58] - reg _T_472 : UInt, io.lsu_store_c1_r_clk @[el2_lsu_dccm_ctl.scala 291:72] - _T_472 <= _T_471 @[el2_lsu_dccm_ctl.scala 291:72] - io.store_data_hi_r <= _T_472 @[el2_lsu_dccm_ctl.scala 291:29] - node _T_473 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89] - node _T_474 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 292:134] - node _T_475 = not(_T_474) @[el2_lsu_dccm_ctl.scala 292:115] - node _T_476 = and(_T_473, _T_475) @[el2_lsu_dccm_ctl.scala 292:113] - node _T_477 = bits(_T_476, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139] - node _T_478 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 292:163] - node _T_479 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_dccm_ctl.scala 292:195] - node _T_480 = mux(_T_477, _T_478, _T_479) @[el2_lsu_dccm_ctl.scala 292:63] - node _T_481 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89] - node _T_482 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 292:134] - node _T_483 = not(_T_482) @[el2_lsu_dccm_ctl.scala 292:115] - node _T_484 = and(_T_481, _T_483) @[el2_lsu_dccm_ctl.scala 292:113] - node _T_485 = bits(_T_484, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139] - node _T_486 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 292:163] - node _T_487 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_dccm_ctl.scala 292:195] - node _T_488 = mux(_T_485, _T_486, _T_487) @[el2_lsu_dccm_ctl.scala 292:63] - node _T_489 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89] - node _T_490 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 292:134] - node _T_491 = not(_T_490) @[el2_lsu_dccm_ctl.scala 292:115] - node _T_492 = and(_T_489, _T_491) @[el2_lsu_dccm_ctl.scala 292:113] - node _T_493 = bits(_T_492, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139] - node _T_494 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 292:163] - node _T_495 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_dccm_ctl.scala 292:195] - node _T_496 = mux(_T_493, _T_494, _T_495) @[el2_lsu_dccm_ctl.scala 292:63] - node _T_497 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 292:89] - node _T_498 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 292:134] - node _T_499 = not(_T_498) @[el2_lsu_dccm_ctl.scala 292:115] - node _T_500 = and(_T_497, _T_499) @[el2_lsu_dccm_ctl.scala 292:113] - node _T_501 = bits(_T_500, 0, 0) @[el2_lsu_dccm_ctl.scala 292:139] - node _T_502 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 292:163] - node _T_503 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_dccm_ctl.scala 292:195] - node _T_504 = mux(_T_501, _T_502, _T_503) @[el2_lsu_dccm_ctl.scala 292:63] - wire _T_505 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 292:55] - _T_505[0] <= _T_480 @[el2_lsu_dccm_ctl.scala 292:55] - _T_505[1] <= _T_488 @[el2_lsu_dccm_ctl.scala 292:55] - _T_505[2] <= _T_496 @[el2_lsu_dccm_ctl.scala 292:55] - _T_505[3] <= _T_504 @[el2_lsu_dccm_ctl.scala 292:55] - node _T_506 = cat(_T_505[2], _T_505[3]) @[Cat.scala 29:58] - node _T_507 = cat(_T_505[0], _T_505[1]) @[Cat.scala 29:58] - node _T_508 = cat(_T_507, _T_506) @[Cat.scala 29:58] - io.store_datafn_lo_r <= _T_508 @[el2_lsu_dccm_ctl.scala 292:29] - node _T_509 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89] - node _T_510 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 293:134] - node _T_511 = not(_T_510) @[el2_lsu_dccm_ctl.scala 293:115] - node _T_512 = and(_T_509, _T_511) @[el2_lsu_dccm_ctl.scala 293:113] - node _T_513 = bits(_T_512, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139] - node _T_514 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 293:163] - node _T_515 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_dccm_ctl.scala 293:195] - node _T_516 = mux(_T_513, _T_514, _T_515) @[el2_lsu_dccm_ctl.scala 293:63] - node _T_517 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89] - node _T_518 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 293:134] - node _T_519 = not(_T_518) @[el2_lsu_dccm_ctl.scala 293:115] - node _T_520 = and(_T_517, _T_519) @[el2_lsu_dccm_ctl.scala 293:113] - node _T_521 = bits(_T_520, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139] - node _T_522 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 293:163] - node _T_523 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_dccm_ctl.scala 293:195] - node _T_524 = mux(_T_521, _T_522, _T_523) @[el2_lsu_dccm_ctl.scala 293:63] - node _T_525 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89] - node _T_526 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 293:134] - node _T_527 = not(_T_526) @[el2_lsu_dccm_ctl.scala 293:115] - node _T_528 = and(_T_525, _T_527) @[el2_lsu_dccm_ctl.scala 293:113] - node _T_529 = bits(_T_528, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139] - node _T_530 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 293:163] - node _T_531 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_dccm_ctl.scala 293:195] - node _T_532 = mux(_T_529, _T_530, _T_531) @[el2_lsu_dccm_ctl.scala 293:63] - node _T_533 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 293:89] - node _T_534 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 293:134] - node _T_535 = not(_T_534) @[el2_lsu_dccm_ctl.scala 293:115] - node _T_536 = and(_T_533, _T_535) @[el2_lsu_dccm_ctl.scala 293:113] - node _T_537 = bits(_T_536, 0, 0) @[el2_lsu_dccm_ctl.scala 293:139] - node _T_538 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 293:163] - node _T_539 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_dccm_ctl.scala 293:195] - node _T_540 = mux(_T_537, _T_538, _T_539) @[el2_lsu_dccm_ctl.scala 293:63] - wire _T_541 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 293:55] - _T_541[0] <= _T_516 @[el2_lsu_dccm_ctl.scala 293:55] - _T_541[1] <= _T_524 @[el2_lsu_dccm_ctl.scala 293:55] - _T_541[2] <= _T_532 @[el2_lsu_dccm_ctl.scala 293:55] - _T_541[3] <= _T_540 @[el2_lsu_dccm_ctl.scala 293:55] - node _T_542 = cat(_T_541[2], _T_541[3]) @[Cat.scala 29:58] - node _T_543 = cat(_T_541[0], _T_541[1]) @[Cat.scala 29:58] - node _T_544 = cat(_T_543, _T_542) @[Cat.scala 29:58] - io.store_datafn_hi_r <= _T_544 @[el2_lsu_dccm_ctl.scala 293:29] - node _T_545 = bits(io.store_data_hi_r, 31, 0) @[el2_lsu_dccm_ctl.scala 294:63] - node _T_546 = bits(io.store_data_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 294:88] - node _T_547 = cat(_T_545, _T_546) @[Cat.scala 29:58] - node _T_548 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 294:116] - node _T_549 = mul(UInt<4>("h08"), _T_548) @[el2_lsu_dccm_ctl.scala 294:102] - node _T_550 = dshr(_T_547, _T_549) @[el2_lsu_dccm_ctl.scala 294:96] - node _T_551 = cat(_T_550, _T_550) @[Cat.scala 29:58] - node _T_552 = cat(_T_551, _T_551) @[Cat.scala 29:58] - node _T_553 = cat(_T_552, _T_552) @[Cat.scala 29:58] - node _T_554 = cat(_T_553, _T_553) @[Cat.scala 29:58] - node _T_555 = cat(_T_554, _T_554) @[Cat.scala 29:58] - node _T_556 = bits(store_byteen_r, 0, 0) @[el2_lsu_dccm_ctl.scala 294:174] - node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] - node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_559 = bits(store_byteen_r, 1, 1) @[el2_lsu_dccm_ctl.scala 294:174] - node _T_560 = bits(_T_559, 0, 0) @[Bitwise.scala 72:15] - node _T_561 = mux(_T_560, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_562 = bits(store_byteen_r, 2, 2) @[el2_lsu_dccm_ctl.scala 294:174] - node _T_563 = bits(_T_562, 0, 0) @[Bitwise.scala 72:15] - node _T_564 = mux(_T_563, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_565 = bits(store_byteen_r, 3, 3) @[el2_lsu_dccm_ctl.scala 294:174] - node _T_566 = bits(_T_565, 0, 0) @[Bitwise.scala 72:15] - node _T_567 = mux(_T_566, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - wire _T_568 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 294:148] - _T_568[0] <= _T_558 @[el2_lsu_dccm_ctl.scala 294:148] - _T_568[1] <= _T_561 @[el2_lsu_dccm_ctl.scala 294:148] - _T_568[2] <= _T_564 @[el2_lsu_dccm_ctl.scala 294:148] - _T_568[3] <= _T_567 @[el2_lsu_dccm_ctl.scala 294:148] - node _T_569 = cat(_T_568[2], _T_568[3]) @[Cat.scala 29:58] - node _T_570 = cat(_T_568[0], _T_568[1]) @[Cat.scala 29:58] - node _T_571 = cat(_T_570, _T_569) @[Cat.scala 29:58] - node _T_572 = and(_T_555, _T_571) @[el2_lsu_dccm_ctl.scala 294:123] - io.store_data_r <= _T_572 @[el2_lsu_dccm_ctl.scala 294:29] - node _T_573 = bits(io.dccm_rd_data_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 297:48] - io.dccm_rdata_lo_m <= _T_573 @[el2_lsu_dccm_ctl.scala 297:27] - node _T_574 = bits(io.dccm_rd_data_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 298:48] - io.dccm_rdata_hi_m <= _T_574 @[el2_lsu_dccm_ctl.scala 298:27] - node _T_575 = bits(io.dccm_rd_data_lo, 38, 32) @[el2_lsu_dccm_ctl.scala 299:48] - io.dccm_data_ecc_lo_m <= _T_575 @[el2_lsu_dccm_ctl.scala 299:27] - node _T_576 = bits(io.dccm_rd_data_hi, 38, 32) @[el2_lsu_dccm_ctl.scala 300:48] - io.dccm_data_ecc_hi_m <= _T_576 @[el2_lsu_dccm_ctl.scala 300:27] - node _T_577 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_dccm_ctl.scala 302:50] - node _T_578 = and(_T_577, io.addr_in_pic_r) @[el2_lsu_dccm_ctl.scala 302:71] - node _T_579 = and(_T_578, io.lsu_commit_r) @[el2_lsu_dccm_ctl.scala 302:90] - node _T_580 = or(_T_579, io.dma_pic_wen) @[el2_lsu_dccm_ctl.scala 302:109] - io.picm_wren <= _T_580 @[el2_lsu_dccm_ctl.scala 302:27] - node _T_581 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.load) @[el2_lsu_dccm_ctl.scala 303:50] - node _T_582 = and(_T_581, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 303:71] - io.picm_rden <= _T_582 @[el2_lsu_dccm_ctl.scala 303:27] - node _T_583 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 304:50] - node _T_584 = and(_T_583, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 304:71] - io.picm_mken <= _T_584 @[el2_lsu_dccm_ctl.scala 304:27] - node _T_585 = sub(UInt<6>("h020"), UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 306:58] - node _T_586 = tail(_T_585, 1) @[el2_lsu_dccm_ctl.scala 306:58] - node _T_587 = bits(io.lsu_addr_d, 14, 0) @[el2_lsu_dccm_ctl.scala 306:88] - node _T_588 = cat(_T_586, _T_587) @[Cat.scala 29:58] - node _T_589 = or(UInt<32>("h0f00c0000"), _T_588) @[el2_lsu_dccm_ctl.scala 306:47] - io.picm_rdaddr <= _T_589 @[el2_lsu_dccm_ctl.scala 306:27] - node _T_590 = sub(UInt<6>("h020"), UInt<1>("h01")) @[el2_lsu_dccm_ctl.scala 307:58] - node _T_591 = tail(_T_590, 1) @[el2_lsu_dccm_ctl.scala 307:58] - node _T_592 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 307:94] - node _T_593 = bits(io.dma_mem_addr, 14, 0) @[el2_lsu_dccm_ctl.scala 307:116] - node _T_594 = bits(io.lsu_addr_r, 14, 0) @[el2_lsu_dccm_ctl.scala 307:148] - node _T_595 = mux(_T_592, _T_593, _T_594) @[el2_lsu_dccm_ctl.scala 307:78] - node _T_596 = cat(_T_591, _T_595) @[Cat.scala 29:58] - node _T_597 = or(UInt<32>("h0f00c0000"), _T_596) @[el2_lsu_dccm_ctl.scala 307:47] - io.picm_wraddr <= _T_597 @[el2_lsu_dccm_ctl.scala 307:27] - node _T_598 = bits(picm_rd_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 308:44] - io.picm_mask_data_m <= _T_598 @[el2_lsu_dccm_ctl.scala 308:27] - node _T_599 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 309:49] - node _T_600 = bits(io.dma_mem_wdata, 31, 0) @[el2_lsu_dccm_ctl.scala 309:72] - node _T_601 = bits(io.store_datafn_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 309:99] - node _T_602 = mux(_T_599, _T_600, _T_601) @[el2_lsu_dccm_ctl.scala 309:33] - io.picm_wr_data <= _T_602 @[el2_lsu_dccm_ctl.scala 309:27] - reg _T_603 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 312:61] - _T_603 <= lsu_dccm_rden_d @[el2_lsu_dccm_ctl.scala 312:61] - io.lsu_dccm_rden_m <= _T_603 @[el2_lsu_dccm_ctl.scala 312:24] - reg _T_604 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 313:61] - _T_604 <= io.lsu_dccm_rden_m @[el2_lsu_dccm_ctl.scala 313:61] - io.lsu_dccm_rden_r <= _T_604 @[el2_lsu_dccm_ctl.scala 313:24] + node _T_960 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_961 = bits(io.store_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 280:64] + node _T_962 = cat(_T_960, _T_961) @[Cat.scala 29:58] + node _T_963 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_dccm_ctl.scala 280:92] + node _T_964 = mul(UInt<4>("h08"), _T_963) @[el2_lsu_dccm_ctl.scala 280:78] + node _T_965 = dshl(_T_962, _T_964) @[el2_lsu_dccm_ctl.scala 280:72] + store_data_pre_m <= _T_965 @[el2_lsu_dccm_ctl.scala 280:29] + node _T_966 = bits(store_data_pre_m, 63, 32) @[el2_lsu_dccm_ctl.scala 281:48] + store_data_hi_m <= _T_966 @[el2_lsu_dccm_ctl.scala 281:29] + node _T_967 = bits(store_data_pre_m, 31, 0) @[el2_lsu_dccm_ctl.scala 282:48] + store_data_lo_m <= _T_967 @[el2_lsu_dccm_ctl.scala 282:29] + node _T_968 = bits(store_byteen_ext_m, 0, 0) @[el2_lsu_dccm_ctl.scala 283:139] + node _T_969 = bits(_T_968, 0, 0) @[el2_lsu_dccm_ctl.scala 283:143] + node _T_970 = bits(store_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 283:167] + node _T_971 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 283:211] + node _T_972 = bits(_T_971, 0, 0) @[el2_lsu_dccm_ctl.scala 283:237] + node _T_973 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 283:262] + node _T_974 = bits(io.sec_data_lo_m, 7, 0) @[el2_lsu_dccm_ctl.scala 283:292] + node _T_975 = mux(_T_972, _T_973, _T_974) @[el2_lsu_dccm_ctl.scala 283:185] + node _T_976 = mux(_T_969, _T_970, _T_975) @[el2_lsu_dccm_ctl.scala 283:120] + node _T_977 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_978 = xor(UInt<8>("h0ff"), _T_977) @[Bitwise.scala 102:21] + node _T_979 = shr(_T_976, 4) @[Bitwise.scala 103:21] + node _T_980 = and(_T_979, _T_978) @[Bitwise.scala 103:31] + node _T_981 = bits(_T_976, 3, 0) @[Bitwise.scala 103:46] + node _T_982 = shl(_T_981, 4) @[Bitwise.scala 103:65] + node _T_983 = not(_T_978) @[Bitwise.scala 103:77] + node _T_984 = and(_T_982, _T_983) @[Bitwise.scala 103:75] + node _T_985 = or(_T_980, _T_984) @[Bitwise.scala 103:39] + node _T_986 = bits(_T_978, 5, 0) @[Bitwise.scala 102:28] + node _T_987 = shl(_T_986, 2) @[Bitwise.scala 102:47] + node _T_988 = xor(_T_978, _T_987) @[Bitwise.scala 102:21] + node _T_989 = shr(_T_985, 2) @[Bitwise.scala 103:21] + node _T_990 = and(_T_989, _T_988) @[Bitwise.scala 103:31] + node _T_991 = bits(_T_985, 5, 0) @[Bitwise.scala 103:46] + node _T_992 = shl(_T_991, 2) @[Bitwise.scala 103:65] + node _T_993 = not(_T_988) @[Bitwise.scala 103:77] + node _T_994 = and(_T_992, _T_993) @[Bitwise.scala 103:75] + node _T_995 = or(_T_990, _T_994) @[Bitwise.scala 103:39] + node _T_996 = bits(_T_988, 6, 0) @[Bitwise.scala 102:28] + node _T_997 = shl(_T_996, 1) @[Bitwise.scala 102:47] + node _T_998 = xor(_T_988, _T_997) @[Bitwise.scala 102:21] + node _T_999 = shr(_T_995, 1) @[Bitwise.scala 103:21] + node _T_1000 = and(_T_999, _T_998) @[Bitwise.scala 103:31] + node _T_1001 = bits(_T_995, 6, 0) @[Bitwise.scala 103:46] + node _T_1002 = shl(_T_1001, 1) @[Bitwise.scala 103:65] + node _T_1003 = not(_T_998) @[Bitwise.scala 103:77] + node _T_1004 = and(_T_1002, _T_1003) @[Bitwise.scala 103:75] + node _T_1005 = or(_T_1000, _T_1004) @[Bitwise.scala 103:39] + node _T_1006 = bits(store_byteen_ext_m, 1, 1) @[el2_lsu_dccm_ctl.scala 283:139] + node _T_1007 = bits(_T_1006, 0, 0) @[el2_lsu_dccm_ctl.scala 283:143] + node _T_1008 = bits(store_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 283:167] + node _T_1009 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 283:211] + node _T_1010 = bits(_T_1009, 0, 0) @[el2_lsu_dccm_ctl.scala 283:237] + node _T_1011 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 283:262] + node _T_1012 = bits(io.sec_data_lo_m, 15, 8) @[el2_lsu_dccm_ctl.scala 283:292] + node _T_1013 = mux(_T_1010, _T_1011, _T_1012) @[el2_lsu_dccm_ctl.scala 283:185] + node _T_1014 = mux(_T_1007, _T_1008, _T_1013) @[el2_lsu_dccm_ctl.scala 283:120] + node _T_1015 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1016 = xor(UInt<8>("h0ff"), _T_1015) @[Bitwise.scala 102:21] + node _T_1017 = shr(_T_1014, 4) @[Bitwise.scala 103:21] + node _T_1018 = and(_T_1017, _T_1016) @[Bitwise.scala 103:31] + node _T_1019 = bits(_T_1014, 3, 0) @[Bitwise.scala 103:46] + node _T_1020 = shl(_T_1019, 4) @[Bitwise.scala 103:65] + node _T_1021 = not(_T_1016) @[Bitwise.scala 103:77] + node _T_1022 = and(_T_1020, _T_1021) @[Bitwise.scala 103:75] + node _T_1023 = or(_T_1018, _T_1022) @[Bitwise.scala 103:39] + node _T_1024 = bits(_T_1016, 5, 0) @[Bitwise.scala 102:28] + node _T_1025 = shl(_T_1024, 2) @[Bitwise.scala 102:47] + node _T_1026 = xor(_T_1016, _T_1025) @[Bitwise.scala 102:21] + node _T_1027 = shr(_T_1023, 2) @[Bitwise.scala 103:21] + node _T_1028 = and(_T_1027, _T_1026) @[Bitwise.scala 103:31] + node _T_1029 = bits(_T_1023, 5, 0) @[Bitwise.scala 103:46] + node _T_1030 = shl(_T_1029, 2) @[Bitwise.scala 103:65] + node _T_1031 = not(_T_1026) @[Bitwise.scala 103:77] + node _T_1032 = and(_T_1030, _T_1031) @[Bitwise.scala 103:75] + node _T_1033 = or(_T_1028, _T_1032) @[Bitwise.scala 103:39] + node _T_1034 = bits(_T_1026, 6, 0) @[Bitwise.scala 102:28] + node _T_1035 = shl(_T_1034, 1) @[Bitwise.scala 102:47] + node _T_1036 = xor(_T_1026, _T_1035) @[Bitwise.scala 102:21] + node _T_1037 = shr(_T_1033, 1) @[Bitwise.scala 103:21] + node _T_1038 = and(_T_1037, _T_1036) @[Bitwise.scala 103:31] + node _T_1039 = bits(_T_1033, 6, 0) @[Bitwise.scala 103:46] + node _T_1040 = shl(_T_1039, 1) @[Bitwise.scala 103:65] + node _T_1041 = not(_T_1036) @[Bitwise.scala 103:77] + node _T_1042 = and(_T_1040, _T_1041) @[Bitwise.scala 103:75] + node _T_1043 = or(_T_1038, _T_1042) @[Bitwise.scala 103:39] + node _T_1044 = bits(store_byteen_ext_m, 2, 2) @[el2_lsu_dccm_ctl.scala 283:139] + node _T_1045 = bits(_T_1044, 0, 0) @[el2_lsu_dccm_ctl.scala 283:143] + node _T_1046 = bits(store_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 283:167] + node _T_1047 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 283:211] + node _T_1048 = bits(_T_1047, 0, 0) @[el2_lsu_dccm_ctl.scala 283:237] + node _T_1049 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 283:262] + node _T_1050 = bits(io.sec_data_lo_m, 23, 16) @[el2_lsu_dccm_ctl.scala 283:292] + node _T_1051 = mux(_T_1048, _T_1049, _T_1050) @[el2_lsu_dccm_ctl.scala 283:185] + node _T_1052 = mux(_T_1045, _T_1046, _T_1051) @[el2_lsu_dccm_ctl.scala 283:120] + node _T_1053 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1054 = xor(UInt<8>("h0ff"), _T_1053) @[Bitwise.scala 102:21] + node _T_1055 = shr(_T_1052, 4) @[Bitwise.scala 103:21] + node _T_1056 = and(_T_1055, _T_1054) @[Bitwise.scala 103:31] + node _T_1057 = bits(_T_1052, 3, 0) @[Bitwise.scala 103:46] + node _T_1058 = shl(_T_1057, 4) @[Bitwise.scala 103:65] + node _T_1059 = not(_T_1054) @[Bitwise.scala 103:77] + node _T_1060 = and(_T_1058, _T_1059) @[Bitwise.scala 103:75] + node _T_1061 = or(_T_1056, _T_1060) @[Bitwise.scala 103:39] + node _T_1062 = bits(_T_1054, 5, 0) @[Bitwise.scala 102:28] + node _T_1063 = shl(_T_1062, 2) @[Bitwise.scala 102:47] + node _T_1064 = xor(_T_1054, _T_1063) @[Bitwise.scala 102:21] + node _T_1065 = shr(_T_1061, 2) @[Bitwise.scala 103:21] + node _T_1066 = and(_T_1065, _T_1064) @[Bitwise.scala 103:31] + node _T_1067 = bits(_T_1061, 5, 0) @[Bitwise.scala 103:46] + node _T_1068 = shl(_T_1067, 2) @[Bitwise.scala 103:65] + node _T_1069 = not(_T_1064) @[Bitwise.scala 103:77] + node _T_1070 = and(_T_1068, _T_1069) @[Bitwise.scala 103:75] + node _T_1071 = or(_T_1066, _T_1070) @[Bitwise.scala 103:39] + node _T_1072 = bits(_T_1064, 6, 0) @[Bitwise.scala 102:28] + node _T_1073 = shl(_T_1072, 1) @[Bitwise.scala 102:47] + node _T_1074 = xor(_T_1064, _T_1073) @[Bitwise.scala 102:21] + node _T_1075 = shr(_T_1071, 1) @[Bitwise.scala 103:21] + node _T_1076 = and(_T_1075, _T_1074) @[Bitwise.scala 103:31] + node _T_1077 = bits(_T_1071, 6, 0) @[Bitwise.scala 103:46] + node _T_1078 = shl(_T_1077, 1) @[Bitwise.scala 103:65] + node _T_1079 = not(_T_1074) @[Bitwise.scala 103:77] + node _T_1080 = and(_T_1078, _T_1079) @[Bitwise.scala 103:75] + node _T_1081 = or(_T_1076, _T_1080) @[Bitwise.scala 103:39] + node _T_1082 = bits(store_byteen_ext_m, 3, 3) @[el2_lsu_dccm_ctl.scala 283:139] + node _T_1083 = bits(_T_1082, 0, 0) @[el2_lsu_dccm_ctl.scala 283:143] + node _T_1084 = bits(store_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 283:167] + node _T_1085 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_lo) @[el2_lsu_dccm_ctl.scala 283:211] + node _T_1086 = bits(_T_1085, 0, 0) @[el2_lsu_dccm_ctl.scala 283:237] + node _T_1087 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 283:262] + node _T_1088 = bits(io.sec_data_lo_m, 31, 24) @[el2_lsu_dccm_ctl.scala 283:292] + node _T_1089 = mux(_T_1086, _T_1087, _T_1088) @[el2_lsu_dccm_ctl.scala 283:185] + node _T_1090 = mux(_T_1083, _T_1084, _T_1089) @[el2_lsu_dccm_ctl.scala 283:120] + node _T_1091 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1092 = xor(UInt<8>("h0ff"), _T_1091) @[Bitwise.scala 102:21] + node _T_1093 = shr(_T_1090, 4) @[Bitwise.scala 103:21] + node _T_1094 = and(_T_1093, _T_1092) @[Bitwise.scala 103:31] + node _T_1095 = bits(_T_1090, 3, 0) @[Bitwise.scala 103:46] + node _T_1096 = shl(_T_1095, 4) @[Bitwise.scala 103:65] + node _T_1097 = not(_T_1092) @[Bitwise.scala 103:77] + node _T_1098 = and(_T_1096, _T_1097) @[Bitwise.scala 103:75] + node _T_1099 = or(_T_1094, _T_1098) @[Bitwise.scala 103:39] + node _T_1100 = bits(_T_1092, 5, 0) @[Bitwise.scala 102:28] + node _T_1101 = shl(_T_1100, 2) @[Bitwise.scala 102:47] + node _T_1102 = xor(_T_1092, _T_1101) @[Bitwise.scala 102:21] + node _T_1103 = shr(_T_1099, 2) @[Bitwise.scala 103:21] + node _T_1104 = and(_T_1103, _T_1102) @[Bitwise.scala 103:31] + node _T_1105 = bits(_T_1099, 5, 0) @[Bitwise.scala 103:46] + node _T_1106 = shl(_T_1105, 2) @[Bitwise.scala 103:65] + node _T_1107 = not(_T_1102) @[Bitwise.scala 103:77] + node _T_1108 = and(_T_1106, _T_1107) @[Bitwise.scala 103:75] + node _T_1109 = or(_T_1104, _T_1108) @[Bitwise.scala 103:39] + node _T_1110 = bits(_T_1102, 6, 0) @[Bitwise.scala 102:28] + node _T_1111 = shl(_T_1110, 1) @[Bitwise.scala 102:47] + node _T_1112 = xor(_T_1102, _T_1111) @[Bitwise.scala 102:21] + node _T_1113 = shr(_T_1109, 1) @[Bitwise.scala 103:21] + node _T_1114 = and(_T_1113, _T_1112) @[Bitwise.scala 103:31] + node _T_1115 = bits(_T_1109, 6, 0) @[Bitwise.scala 103:46] + node _T_1116 = shl(_T_1115, 1) @[Bitwise.scala 103:65] + node _T_1117 = not(_T_1112) @[Bitwise.scala 103:77] + node _T_1118 = and(_T_1116, _T_1117) @[Bitwise.scala 103:75] + node _T_1119 = or(_T_1114, _T_1118) @[Bitwise.scala 103:39] + wire _T_1120 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 283:104] + _T_1120[0] <= _T_1005 @[el2_lsu_dccm_ctl.scala 283:104] + _T_1120[1] <= _T_1043 @[el2_lsu_dccm_ctl.scala 283:104] + _T_1120[2] <= _T_1081 @[el2_lsu_dccm_ctl.scala 283:104] + _T_1120[3] <= _T_1119 @[el2_lsu_dccm_ctl.scala 283:104] + node _T_1121 = cat(_T_1120[2], _T_1120[3]) @[Cat.scala 29:58] + node _T_1122 = cat(_T_1120[0], _T_1120[1]) @[Cat.scala 29:58] + node _T_1123 = cat(_T_1122, _T_1121) @[Cat.scala 29:58] + node _T_1124 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1125 = xor(UInt<32>("h0ffffffff"), _T_1124) @[Bitwise.scala 102:21] + node _T_1126 = shr(_T_1123, 16) @[Bitwise.scala 103:21] + node _T_1127 = and(_T_1126, _T_1125) @[Bitwise.scala 103:31] + node _T_1128 = bits(_T_1123, 15, 0) @[Bitwise.scala 103:46] + node _T_1129 = shl(_T_1128, 16) @[Bitwise.scala 103:65] + node _T_1130 = not(_T_1125) @[Bitwise.scala 103:77] + node _T_1131 = and(_T_1129, _T_1130) @[Bitwise.scala 103:75] + node _T_1132 = or(_T_1127, _T_1131) @[Bitwise.scala 103:39] + node _T_1133 = bits(_T_1125, 23, 0) @[Bitwise.scala 102:28] + node _T_1134 = shl(_T_1133, 8) @[Bitwise.scala 102:47] + node _T_1135 = xor(_T_1125, _T_1134) @[Bitwise.scala 102:21] + node _T_1136 = shr(_T_1132, 8) @[Bitwise.scala 103:21] + node _T_1137 = and(_T_1136, _T_1135) @[Bitwise.scala 103:31] + node _T_1138 = bits(_T_1132, 23, 0) @[Bitwise.scala 103:46] + node _T_1139 = shl(_T_1138, 8) @[Bitwise.scala 103:65] + node _T_1140 = not(_T_1135) @[Bitwise.scala 103:77] + node _T_1141 = and(_T_1139, _T_1140) @[Bitwise.scala 103:75] + node _T_1142 = or(_T_1137, _T_1141) @[Bitwise.scala 103:39] + node _T_1143 = bits(_T_1135, 27, 0) @[Bitwise.scala 102:28] + node _T_1144 = shl(_T_1143, 4) @[Bitwise.scala 102:47] + node _T_1145 = xor(_T_1135, _T_1144) @[Bitwise.scala 102:21] + node _T_1146 = shr(_T_1142, 4) @[Bitwise.scala 103:21] + node _T_1147 = and(_T_1146, _T_1145) @[Bitwise.scala 103:31] + node _T_1148 = bits(_T_1142, 27, 0) @[Bitwise.scala 103:46] + node _T_1149 = shl(_T_1148, 4) @[Bitwise.scala 103:65] + node _T_1150 = not(_T_1145) @[Bitwise.scala 103:77] + node _T_1151 = and(_T_1149, _T_1150) @[Bitwise.scala 103:75] + node _T_1152 = or(_T_1147, _T_1151) @[Bitwise.scala 103:39] + node _T_1153 = bits(_T_1145, 29, 0) @[Bitwise.scala 102:28] + node _T_1154 = shl(_T_1153, 2) @[Bitwise.scala 102:47] + node _T_1155 = xor(_T_1145, _T_1154) @[Bitwise.scala 102:21] + node _T_1156 = shr(_T_1152, 2) @[Bitwise.scala 103:21] + node _T_1157 = and(_T_1156, _T_1155) @[Bitwise.scala 103:31] + node _T_1158 = bits(_T_1152, 29, 0) @[Bitwise.scala 103:46] + node _T_1159 = shl(_T_1158, 2) @[Bitwise.scala 103:65] + node _T_1160 = not(_T_1155) @[Bitwise.scala 103:77] + node _T_1161 = and(_T_1159, _T_1160) @[Bitwise.scala 103:75] + node _T_1162 = or(_T_1157, _T_1161) @[Bitwise.scala 103:39] + node _T_1163 = bits(_T_1155, 30, 0) @[Bitwise.scala 102:28] + node _T_1164 = shl(_T_1163, 1) @[Bitwise.scala 102:47] + node _T_1165 = xor(_T_1155, _T_1164) @[Bitwise.scala 102:21] + node _T_1166 = shr(_T_1162, 1) @[Bitwise.scala 103:21] + node _T_1167 = and(_T_1166, _T_1165) @[Bitwise.scala 103:31] + node _T_1168 = bits(_T_1162, 30, 0) @[Bitwise.scala 103:46] + node _T_1169 = shl(_T_1168, 1) @[Bitwise.scala 103:65] + node _T_1170 = not(_T_1165) @[Bitwise.scala 103:77] + node _T_1171 = and(_T_1169, _T_1170) @[Bitwise.scala 103:75] + node _T_1172 = or(_T_1167, _T_1171) @[Bitwise.scala 103:39] + reg _T_1173 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 283:72] + _T_1173 <= _T_1172 @[el2_lsu_dccm_ctl.scala 283:72] + io.store_data_lo_r <= _T_1173 @[el2_lsu_dccm_ctl.scala 283:29] + node _T_1174 = bits(store_byteen_ext_m, 4, 4) @[el2_lsu_dccm_ctl.scala 284:139] + node _T_1175 = bits(_T_1174, 0, 0) @[el2_lsu_dccm_ctl.scala 284:145] + node _T_1176 = bits(store_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 284:167] + node _T_1177 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 284:211] + node _T_1178 = bits(_T_1177, 0, 0) @[el2_lsu_dccm_ctl.scala 284:237] + node _T_1179 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 284:262] + node _T_1180 = bits(io.sec_data_hi_m, 7, 0) @[el2_lsu_dccm_ctl.scala 284:292] + node _T_1181 = mux(_T_1178, _T_1179, _T_1180) @[el2_lsu_dccm_ctl.scala 284:185] + node _T_1182 = mux(_T_1175, _T_1176, _T_1181) @[el2_lsu_dccm_ctl.scala 284:120] + node _T_1183 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1184 = xor(UInt<8>("h0ff"), _T_1183) @[Bitwise.scala 102:21] + node _T_1185 = shr(_T_1182, 4) @[Bitwise.scala 103:21] + node _T_1186 = and(_T_1185, _T_1184) @[Bitwise.scala 103:31] + node _T_1187 = bits(_T_1182, 3, 0) @[Bitwise.scala 103:46] + node _T_1188 = shl(_T_1187, 4) @[Bitwise.scala 103:65] + node _T_1189 = not(_T_1184) @[Bitwise.scala 103:77] + node _T_1190 = and(_T_1188, _T_1189) @[Bitwise.scala 103:75] + node _T_1191 = or(_T_1186, _T_1190) @[Bitwise.scala 103:39] + node _T_1192 = bits(_T_1184, 5, 0) @[Bitwise.scala 102:28] + node _T_1193 = shl(_T_1192, 2) @[Bitwise.scala 102:47] + node _T_1194 = xor(_T_1184, _T_1193) @[Bitwise.scala 102:21] + node _T_1195 = shr(_T_1191, 2) @[Bitwise.scala 103:21] + node _T_1196 = and(_T_1195, _T_1194) @[Bitwise.scala 103:31] + node _T_1197 = bits(_T_1191, 5, 0) @[Bitwise.scala 103:46] + node _T_1198 = shl(_T_1197, 2) @[Bitwise.scala 103:65] + node _T_1199 = not(_T_1194) @[Bitwise.scala 103:77] + node _T_1200 = and(_T_1198, _T_1199) @[Bitwise.scala 103:75] + node _T_1201 = or(_T_1196, _T_1200) @[Bitwise.scala 103:39] + node _T_1202 = bits(_T_1194, 6, 0) @[Bitwise.scala 102:28] + node _T_1203 = shl(_T_1202, 1) @[Bitwise.scala 102:47] + node _T_1204 = xor(_T_1194, _T_1203) @[Bitwise.scala 102:21] + node _T_1205 = shr(_T_1201, 1) @[Bitwise.scala 103:21] + node _T_1206 = and(_T_1205, _T_1204) @[Bitwise.scala 103:31] + node _T_1207 = bits(_T_1201, 6, 0) @[Bitwise.scala 103:46] + node _T_1208 = shl(_T_1207, 1) @[Bitwise.scala 103:65] + node _T_1209 = not(_T_1204) @[Bitwise.scala 103:77] + node _T_1210 = and(_T_1208, _T_1209) @[Bitwise.scala 103:75] + node _T_1211 = or(_T_1206, _T_1210) @[Bitwise.scala 103:39] + node _T_1212 = bits(store_byteen_ext_m, 5, 5) @[el2_lsu_dccm_ctl.scala 284:139] + node _T_1213 = bits(_T_1212, 0, 0) @[el2_lsu_dccm_ctl.scala 284:145] + node _T_1214 = bits(store_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 284:167] + node _T_1215 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 284:211] + node _T_1216 = bits(_T_1215, 0, 0) @[el2_lsu_dccm_ctl.scala 284:237] + node _T_1217 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 284:262] + node _T_1218 = bits(io.sec_data_hi_m, 15, 8) @[el2_lsu_dccm_ctl.scala 284:292] + node _T_1219 = mux(_T_1216, _T_1217, _T_1218) @[el2_lsu_dccm_ctl.scala 284:185] + node _T_1220 = mux(_T_1213, _T_1214, _T_1219) @[el2_lsu_dccm_ctl.scala 284:120] + node _T_1221 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1222 = xor(UInt<8>("h0ff"), _T_1221) @[Bitwise.scala 102:21] + node _T_1223 = shr(_T_1220, 4) @[Bitwise.scala 103:21] + node _T_1224 = and(_T_1223, _T_1222) @[Bitwise.scala 103:31] + node _T_1225 = bits(_T_1220, 3, 0) @[Bitwise.scala 103:46] + node _T_1226 = shl(_T_1225, 4) @[Bitwise.scala 103:65] + node _T_1227 = not(_T_1222) @[Bitwise.scala 103:77] + node _T_1228 = and(_T_1226, _T_1227) @[Bitwise.scala 103:75] + node _T_1229 = or(_T_1224, _T_1228) @[Bitwise.scala 103:39] + node _T_1230 = bits(_T_1222, 5, 0) @[Bitwise.scala 102:28] + node _T_1231 = shl(_T_1230, 2) @[Bitwise.scala 102:47] + node _T_1232 = xor(_T_1222, _T_1231) @[Bitwise.scala 102:21] + node _T_1233 = shr(_T_1229, 2) @[Bitwise.scala 103:21] + node _T_1234 = and(_T_1233, _T_1232) @[Bitwise.scala 103:31] + node _T_1235 = bits(_T_1229, 5, 0) @[Bitwise.scala 103:46] + node _T_1236 = shl(_T_1235, 2) @[Bitwise.scala 103:65] + node _T_1237 = not(_T_1232) @[Bitwise.scala 103:77] + node _T_1238 = and(_T_1236, _T_1237) @[Bitwise.scala 103:75] + node _T_1239 = or(_T_1234, _T_1238) @[Bitwise.scala 103:39] + node _T_1240 = bits(_T_1232, 6, 0) @[Bitwise.scala 102:28] + node _T_1241 = shl(_T_1240, 1) @[Bitwise.scala 102:47] + node _T_1242 = xor(_T_1232, _T_1241) @[Bitwise.scala 102:21] + node _T_1243 = shr(_T_1239, 1) @[Bitwise.scala 103:21] + node _T_1244 = and(_T_1243, _T_1242) @[Bitwise.scala 103:31] + node _T_1245 = bits(_T_1239, 6, 0) @[Bitwise.scala 103:46] + node _T_1246 = shl(_T_1245, 1) @[Bitwise.scala 103:65] + node _T_1247 = not(_T_1242) @[Bitwise.scala 103:77] + node _T_1248 = and(_T_1246, _T_1247) @[Bitwise.scala 103:75] + node _T_1249 = or(_T_1244, _T_1248) @[Bitwise.scala 103:39] + node _T_1250 = bits(store_byteen_ext_m, 6, 6) @[el2_lsu_dccm_ctl.scala 284:139] + node _T_1251 = bits(_T_1250, 0, 0) @[el2_lsu_dccm_ctl.scala 284:145] + node _T_1252 = bits(store_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 284:167] + node _T_1253 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 284:211] + node _T_1254 = bits(_T_1253, 0, 0) @[el2_lsu_dccm_ctl.scala 284:237] + node _T_1255 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 284:262] + node _T_1256 = bits(io.sec_data_hi_m, 23, 16) @[el2_lsu_dccm_ctl.scala 284:292] + node _T_1257 = mux(_T_1254, _T_1255, _T_1256) @[el2_lsu_dccm_ctl.scala 284:185] + node _T_1258 = mux(_T_1251, _T_1252, _T_1257) @[el2_lsu_dccm_ctl.scala 284:120] + node _T_1259 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1260 = xor(UInt<8>("h0ff"), _T_1259) @[Bitwise.scala 102:21] + node _T_1261 = shr(_T_1258, 4) @[Bitwise.scala 103:21] + node _T_1262 = and(_T_1261, _T_1260) @[Bitwise.scala 103:31] + node _T_1263 = bits(_T_1258, 3, 0) @[Bitwise.scala 103:46] + node _T_1264 = shl(_T_1263, 4) @[Bitwise.scala 103:65] + node _T_1265 = not(_T_1260) @[Bitwise.scala 103:77] + node _T_1266 = and(_T_1264, _T_1265) @[Bitwise.scala 103:75] + node _T_1267 = or(_T_1262, _T_1266) @[Bitwise.scala 103:39] + node _T_1268 = bits(_T_1260, 5, 0) @[Bitwise.scala 102:28] + node _T_1269 = shl(_T_1268, 2) @[Bitwise.scala 102:47] + node _T_1270 = xor(_T_1260, _T_1269) @[Bitwise.scala 102:21] + node _T_1271 = shr(_T_1267, 2) @[Bitwise.scala 103:21] + node _T_1272 = and(_T_1271, _T_1270) @[Bitwise.scala 103:31] + node _T_1273 = bits(_T_1267, 5, 0) @[Bitwise.scala 103:46] + node _T_1274 = shl(_T_1273, 2) @[Bitwise.scala 103:65] + node _T_1275 = not(_T_1270) @[Bitwise.scala 103:77] + node _T_1276 = and(_T_1274, _T_1275) @[Bitwise.scala 103:75] + node _T_1277 = or(_T_1272, _T_1276) @[Bitwise.scala 103:39] + node _T_1278 = bits(_T_1270, 6, 0) @[Bitwise.scala 102:28] + node _T_1279 = shl(_T_1278, 1) @[Bitwise.scala 102:47] + node _T_1280 = xor(_T_1270, _T_1279) @[Bitwise.scala 102:21] + node _T_1281 = shr(_T_1277, 1) @[Bitwise.scala 103:21] + node _T_1282 = and(_T_1281, _T_1280) @[Bitwise.scala 103:31] + node _T_1283 = bits(_T_1277, 6, 0) @[Bitwise.scala 103:46] + node _T_1284 = shl(_T_1283, 1) @[Bitwise.scala 103:65] + node _T_1285 = not(_T_1280) @[Bitwise.scala 103:77] + node _T_1286 = and(_T_1284, _T_1285) @[Bitwise.scala 103:75] + node _T_1287 = or(_T_1282, _T_1286) @[Bitwise.scala 103:39] + node _T_1288 = bits(store_byteen_ext_m, 7, 7) @[el2_lsu_dccm_ctl.scala 284:139] + node _T_1289 = bits(_T_1288, 0, 0) @[el2_lsu_dccm_ctl.scala 284:145] + node _T_1290 = bits(store_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 284:167] + node _T_1291 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_m_hi) @[el2_lsu_dccm_ctl.scala 284:211] + node _T_1292 = bits(_T_1291, 0, 0) @[el2_lsu_dccm_ctl.scala 284:237] + node _T_1293 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 284:262] + node _T_1294 = bits(io.sec_data_hi_m, 31, 24) @[el2_lsu_dccm_ctl.scala 284:292] + node _T_1295 = mux(_T_1292, _T_1293, _T_1294) @[el2_lsu_dccm_ctl.scala 284:185] + node _T_1296 = mux(_T_1289, _T_1290, _T_1295) @[el2_lsu_dccm_ctl.scala 284:120] + node _T_1297 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1298 = xor(UInt<8>("h0ff"), _T_1297) @[Bitwise.scala 102:21] + node _T_1299 = shr(_T_1296, 4) @[Bitwise.scala 103:21] + node _T_1300 = and(_T_1299, _T_1298) @[Bitwise.scala 103:31] + node _T_1301 = bits(_T_1296, 3, 0) @[Bitwise.scala 103:46] + node _T_1302 = shl(_T_1301, 4) @[Bitwise.scala 103:65] + node _T_1303 = not(_T_1298) @[Bitwise.scala 103:77] + node _T_1304 = and(_T_1302, _T_1303) @[Bitwise.scala 103:75] + node _T_1305 = or(_T_1300, _T_1304) @[Bitwise.scala 103:39] + node _T_1306 = bits(_T_1298, 5, 0) @[Bitwise.scala 102:28] + node _T_1307 = shl(_T_1306, 2) @[Bitwise.scala 102:47] + node _T_1308 = xor(_T_1298, _T_1307) @[Bitwise.scala 102:21] + node _T_1309 = shr(_T_1305, 2) @[Bitwise.scala 103:21] + node _T_1310 = and(_T_1309, _T_1308) @[Bitwise.scala 103:31] + node _T_1311 = bits(_T_1305, 5, 0) @[Bitwise.scala 103:46] + node _T_1312 = shl(_T_1311, 2) @[Bitwise.scala 103:65] + node _T_1313 = not(_T_1308) @[Bitwise.scala 103:77] + node _T_1314 = and(_T_1312, _T_1313) @[Bitwise.scala 103:75] + node _T_1315 = or(_T_1310, _T_1314) @[Bitwise.scala 103:39] + node _T_1316 = bits(_T_1308, 6, 0) @[Bitwise.scala 102:28] + node _T_1317 = shl(_T_1316, 1) @[Bitwise.scala 102:47] + node _T_1318 = xor(_T_1308, _T_1317) @[Bitwise.scala 102:21] + node _T_1319 = shr(_T_1315, 1) @[Bitwise.scala 103:21] + node _T_1320 = and(_T_1319, _T_1318) @[Bitwise.scala 103:31] + node _T_1321 = bits(_T_1315, 6, 0) @[Bitwise.scala 103:46] + node _T_1322 = shl(_T_1321, 1) @[Bitwise.scala 103:65] + node _T_1323 = not(_T_1318) @[Bitwise.scala 103:77] + node _T_1324 = and(_T_1322, _T_1323) @[Bitwise.scala 103:75] + node _T_1325 = or(_T_1320, _T_1324) @[Bitwise.scala 103:39] + wire _T_1326 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 284:104] + _T_1326[0] <= _T_1211 @[el2_lsu_dccm_ctl.scala 284:104] + _T_1326[1] <= _T_1249 @[el2_lsu_dccm_ctl.scala 284:104] + _T_1326[2] <= _T_1287 @[el2_lsu_dccm_ctl.scala 284:104] + _T_1326[3] <= _T_1325 @[el2_lsu_dccm_ctl.scala 284:104] + node _T_1327 = cat(_T_1326[2], _T_1326[3]) @[Cat.scala 29:58] + node _T_1328 = cat(_T_1326[0], _T_1326[1]) @[Cat.scala 29:58] + node _T_1329 = cat(_T_1328, _T_1327) @[Cat.scala 29:58] + node _T_1330 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1331 = xor(UInt<32>("h0ffffffff"), _T_1330) @[Bitwise.scala 102:21] + node _T_1332 = shr(_T_1329, 16) @[Bitwise.scala 103:21] + node _T_1333 = and(_T_1332, _T_1331) @[Bitwise.scala 103:31] + node _T_1334 = bits(_T_1329, 15, 0) @[Bitwise.scala 103:46] + node _T_1335 = shl(_T_1334, 16) @[Bitwise.scala 103:65] + node _T_1336 = not(_T_1331) @[Bitwise.scala 103:77] + node _T_1337 = and(_T_1335, _T_1336) @[Bitwise.scala 103:75] + node _T_1338 = or(_T_1333, _T_1337) @[Bitwise.scala 103:39] + node _T_1339 = bits(_T_1331, 23, 0) @[Bitwise.scala 102:28] + node _T_1340 = shl(_T_1339, 8) @[Bitwise.scala 102:47] + node _T_1341 = xor(_T_1331, _T_1340) @[Bitwise.scala 102:21] + node _T_1342 = shr(_T_1338, 8) @[Bitwise.scala 103:21] + node _T_1343 = and(_T_1342, _T_1341) @[Bitwise.scala 103:31] + node _T_1344 = bits(_T_1338, 23, 0) @[Bitwise.scala 103:46] + node _T_1345 = shl(_T_1344, 8) @[Bitwise.scala 103:65] + node _T_1346 = not(_T_1341) @[Bitwise.scala 103:77] + node _T_1347 = and(_T_1345, _T_1346) @[Bitwise.scala 103:75] + node _T_1348 = or(_T_1343, _T_1347) @[Bitwise.scala 103:39] + node _T_1349 = bits(_T_1341, 27, 0) @[Bitwise.scala 102:28] + node _T_1350 = shl(_T_1349, 4) @[Bitwise.scala 102:47] + node _T_1351 = xor(_T_1341, _T_1350) @[Bitwise.scala 102:21] + node _T_1352 = shr(_T_1348, 4) @[Bitwise.scala 103:21] + node _T_1353 = and(_T_1352, _T_1351) @[Bitwise.scala 103:31] + node _T_1354 = bits(_T_1348, 27, 0) @[Bitwise.scala 103:46] + node _T_1355 = shl(_T_1354, 4) @[Bitwise.scala 103:65] + node _T_1356 = not(_T_1351) @[Bitwise.scala 103:77] + node _T_1357 = and(_T_1355, _T_1356) @[Bitwise.scala 103:75] + node _T_1358 = or(_T_1353, _T_1357) @[Bitwise.scala 103:39] + node _T_1359 = bits(_T_1351, 29, 0) @[Bitwise.scala 102:28] + node _T_1360 = shl(_T_1359, 2) @[Bitwise.scala 102:47] + node _T_1361 = xor(_T_1351, _T_1360) @[Bitwise.scala 102:21] + node _T_1362 = shr(_T_1358, 2) @[Bitwise.scala 103:21] + node _T_1363 = and(_T_1362, _T_1361) @[Bitwise.scala 103:31] + node _T_1364 = bits(_T_1358, 29, 0) @[Bitwise.scala 103:46] + node _T_1365 = shl(_T_1364, 2) @[Bitwise.scala 103:65] + node _T_1366 = not(_T_1361) @[Bitwise.scala 103:77] + node _T_1367 = and(_T_1365, _T_1366) @[Bitwise.scala 103:75] + node _T_1368 = or(_T_1363, _T_1367) @[Bitwise.scala 103:39] + node _T_1369 = bits(_T_1361, 30, 0) @[Bitwise.scala 102:28] + node _T_1370 = shl(_T_1369, 1) @[Bitwise.scala 102:47] + node _T_1371 = xor(_T_1361, _T_1370) @[Bitwise.scala 102:21] + node _T_1372 = shr(_T_1368, 1) @[Bitwise.scala 103:21] + node _T_1373 = and(_T_1372, _T_1371) @[Bitwise.scala 103:31] + node _T_1374 = bits(_T_1368, 30, 0) @[Bitwise.scala 103:46] + node _T_1375 = shl(_T_1374, 1) @[Bitwise.scala 103:65] + node _T_1376 = not(_T_1371) @[Bitwise.scala 103:77] + node _T_1377 = and(_T_1375, _T_1376) @[Bitwise.scala 103:75] + node _T_1378 = or(_T_1373, _T_1377) @[Bitwise.scala 103:39] + reg _T_1379 : UInt, io.lsu_store_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 284:72] + _T_1379 <= _T_1378 @[el2_lsu_dccm_ctl.scala 284:72] + io.store_data_hi_r <= _T_1379 @[el2_lsu_dccm_ctl.scala 284:29] + node _T_1380 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 285:105] + node _T_1381 = bits(store_byteen_ext_r, 0, 0) @[el2_lsu_dccm_ctl.scala 285:150] + node _T_1382 = eq(_T_1381, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 285:131] + node _T_1383 = and(_T_1380, _T_1382) @[el2_lsu_dccm_ctl.scala 285:129] + node _T_1384 = bits(_T_1383, 0, 0) @[el2_lsu_dccm_ctl.scala 285:155] + node _T_1385 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 285:179] + node _T_1386 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_dccm_ctl.scala 285:211] + node _T_1387 = mux(_T_1384, _T_1385, _T_1386) @[el2_lsu_dccm_ctl.scala 285:79] + node _T_1388 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1389 = xor(UInt<8>("h0ff"), _T_1388) @[Bitwise.scala 102:21] + node _T_1390 = shr(_T_1387, 4) @[Bitwise.scala 103:21] + node _T_1391 = and(_T_1390, _T_1389) @[Bitwise.scala 103:31] + node _T_1392 = bits(_T_1387, 3, 0) @[Bitwise.scala 103:46] + node _T_1393 = shl(_T_1392, 4) @[Bitwise.scala 103:65] + node _T_1394 = not(_T_1389) @[Bitwise.scala 103:77] + node _T_1395 = and(_T_1393, _T_1394) @[Bitwise.scala 103:75] + node _T_1396 = or(_T_1391, _T_1395) @[Bitwise.scala 103:39] + node _T_1397 = bits(_T_1389, 5, 0) @[Bitwise.scala 102:28] + node _T_1398 = shl(_T_1397, 2) @[Bitwise.scala 102:47] + node _T_1399 = xor(_T_1389, _T_1398) @[Bitwise.scala 102:21] + node _T_1400 = shr(_T_1396, 2) @[Bitwise.scala 103:21] + node _T_1401 = and(_T_1400, _T_1399) @[Bitwise.scala 103:31] + node _T_1402 = bits(_T_1396, 5, 0) @[Bitwise.scala 103:46] + node _T_1403 = shl(_T_1402, 2) @[Bitwise.scala 103:65] + node _T_1404 = not(_T_1399) @[Bitwise.scala 103:77] + node _T_1405 = and(_T_1403, _T_1404) @[Bitwise.scala 103:75] + node _T_1406 = or(_T_1401, _T_1405) @[Bitwise.scala 103:39] + node _T_1407 = bits(_T_1399, 6, 0) @[Bitwise.scala 102:28] + node _T_1408 = shl(_T_1407, 1) @[Bitwise.scala 102:47] + node _T_1409 = xor(_T_1399, _T_1408) @[Bitwise.scala 102:21] + node _T_1410 = shr(_T_1406, 1) @[Bitwise.scala 103:21] + node _T_1411 = and(_T_1410, _T_1409) @[Bitwise.scala 103:31] + node _T_1412 = bits(_T_1406, 6, 0) @[Bitwise.scala 103:46] + node _T_1413 = shl(_T_1412, 1) @[Bitwise.scala 103:65] + node _T_1414 = not(_T_1409) @[Bitwise.scala 103:77] + node _T_1415 = and(_T_1413, _T_1414) @[Bitwise.scala 103:75] + node _T_1416 = or(_T_1411, _T_1415) @[Bitwise.scala 103:39] + node _T_1417 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 285:105] + node _T_1418 = bits(store_byteen_ext_r, 1, 1) @[el2_lsu_dccm_ctl.scala 285:150] + node _T_1419 = eq(_T_1418, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 285:131] + node _T_1420 = and(_T_1417, _T_1419) @[el2_lsu_dccm_ctl.scala 285:129] + node _T_1421 = bits(_T_1420, 0, 0) @[el2_lsu_dccm_ctl.scala 285:155] + node _T_1422 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 285:179] + node _T_1423 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_dccm_ctl.scala 285:211] + node _T_1424 = mux(_T_1421, _T_1422, _T_1423) @[el2_lsu_dccm_ctl.scala 285:79] + node _T_1425 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1426 = xor(UInt<8>("h0ff"), _T_1425) @[Bitwise.scala 102:21] + node _T_1427 = shr(_T_1424, 4) @[Bitwise.scala 103:21] + node _T_1428 = and(_T_1427, _T_1426) @[Bitwise.scala 103:31] + node _T_1429 = bits(_T_1424, 3, 0) @[Bitwise.scala 103:46] + node _T_1430 = shl(_T_1429, 4) @[Bitwise.scala 103:65] + node _T_1431 = not(_T_1426) @[Bitwise.scala 103:77] + node _T_1432 = and(_T_1430, _T_1431) @[Bitwise.scala 103:75] + node _T_1433 = or(_T_1428, _T_1432) @[Bitwise.scala 103:39] + node _T_1434 = bits(_T_1426, 5, 0) @[Bitwise.scala 102:28] + node _T_1435 = shl(_T_1434, 2) @[Bitwise.scala 102:47] + node _T_1436 = xor(_T_1426, _T_1435) @[Bitwise.scala 102:21] + node _T_1437 = shr(_T_1433, 2) @[Bitwise.scala 103:21] + node _T_1438 = and(_T_1437, _T_1436) @[Bitwise.scala 103:31] + node _T_1439 = bits(_T_1433, 5, 0) @[Bitwise.scala 103:46] + node _T_1440 = shl(_T_1439, 2) @[Bitwise.scala 103:65] + node _T_1441 = not(_T_1436) @[Bitwise.scala 103:77] + node _T_1442 = and(_T_1440, _T_1441) @[Bitwise.scala 103:75] + node _T_1443 = or(_T_1438, _T_1442) @[Bitwise.scala 103:39] + node _T_1444 = bits(_T_1436, 6, 0) @[Bitwise.scala 102:28] + node _T_1445 = shl(_T_1444, 1) @[Bitwise.scala 102:47] + node _T_1446 = xor(_T_1436, _T_1445) @[Bitwise.scala 102:21] + node _T_1447 = shr(_T_1443, 1) @[Bitwise.scala 103:21] + node _T_1448 = and(_T_1447, _T_1446) @[Bitwise.scala 103:31] + node _T_1449 = bits(_T_1443, 6, 0) @[Bitwise.scala 103:46] + node _T_1450 = shl(_T_1449, 1) @[Bitwise.scala 103:65] + node _T_1451 = not(_T_1446) @[Bitwise.scala 103:77] + node _T_1452 = and(_T_1450, _T_1451) @[Bitwise.scala 103:75] + node _T_1453 = or(_T_1448, _T_1452) @[Bitwise.scala 103:39] + node _T_1454 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 285:105] + node _T_1455 = bits(store_byteen_ext_r, 2, 2) @[el2_lsu_dccm_ctl.scala 285:150] + node _T_1456 = eq(_T_1455, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 285:131] + node _T_1457 = and(_T_1454, _T_1456) @[el2_lsu_dccm_ctl.scala 285:129] + node _T_1458 = bits(_T_1457, 0, 0) @[el2_lsu_dccm_ctl.scala 285:155] + node _T_1459 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 285:179] + node _T_1460 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_dccm_ctl.scala 285:211] + node _T_1461 = mux(_T_1458, _T_1459, _T_1460) @[el2_lsu_dccm_ctl.scala 285:79] + node _T_1462 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1463 = xor(UInt<8>("h0ff"), _T_1462) @[Bitwise.scala 102:21] + node _T_1464 = shr(_T_1461, 4) @[Bitwise.scala 103:21] + node _T_1465 = and(_T_1464, _T_1463) @[Bitwise.scala 103:31] + node _T_1466 = bits(_T_1461, 3, 0) @[Bitwise.scala 103:46] + node _T_1467 = shl(_T_1466, 4) @[Bitwise.scala 103:65] + node _T_1468 = not(_T_1463) @[Bitwise.scala 103:77] + node _T_1469 = and(_T_1467, _T_1468) @[Bitwise.scala 103:75] + node _T_1470 = or(_T_1465, _T_1469) @[Bitwise.scala 103:39] + node _T_1471 = bits(_T_1463, 5, 0) @[Bitwise.scala 102:28] + node _T_1472 = shl(_T_1471, 2) @[Bitwise.scala 102:47] + node _T_1473 = xor(_T_1463, _T_1472) @[Bitwise.scala 102:21] + node _T_1474 = shr(_T_1470, 2) @[Bitwise.scala 103:21] + node _T_1475 = and(_T_1474, _T_1473) @[Bitwise.scala 103:31] + node _T_1476 = bits(_T_1470, 5, 0) @[Bitwise.scala 103:46] + node _T_1477 = shl(_T_1476, 2) @[Bitwise.scala 103:65] + node _T_1478 = not(_T_1473) @[Bitwise.scala 103:77] + node _T_1479 = and(_T_1477, _T_1478) @[Bitwise.scala 103:75] + node _T_1480 = or(_T_1475, _T_1479) @[Bitwise.scala 103:39] + node _T_1481 = bits(_T_1473, 6, 0) @[Bitwise.scala 102:28] + node _T_1482 = shl(_T_1481, 1) @[Bitwise.scala 102:47] + node _T_1483 = xor(_T_1473, _T_1482) @[Bitwise.scala 102:21] + node _T_1484 = shr(_T_1480, 1) @[Bitwise.scala 103:21] + node _T_1485 = and(_T_1484, _T_1483) @[Bitwise.scala 103:31] + node _T_1486 = bits(_T_1480, 6, 0) @[Bitwise.scala 103:46] + node _T_1487 = shl(_T_1486, 1) @[Bitwise.scala 103:65] + node _T_1488 = not(_T_1483) @[Bitwise.scala 103:77] + node _T_1489 = and(_T_1487, _T_1488) @[Bitwise.scala 103:75] + node _T_1490 = or(_T_1485, _T_1489) @[Bitwise.scala 103:39] + node _T_1491 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_lo) @[el2_lsu_dccm_ctl.scala 285:105] + node _T_1492 = bits(store_byteen_ext_r, 3, 3) @[el2_lsu_dccm_ctl.scala 285:150] + node _T_1493 = eq(_T_1492, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 285:131] + node _T_1494 = and(_T_1491, _T_1493) @[el2_lsu_dccm_ctl.scala 285:129] + node _T_1495 = bits(_T_1494, 0, 0) @[el2_lsu_dccm_ctl.scala 285:155] + node _T_1496 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 285:179] + node _T_1497 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_dccm_ctl.scala 285:211] + node _T_1498 = mux(_T_1495, _T_1496, _T_1497) @[el2_lsu_dccm_ctl.scala 285:79] + node _T_1499 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1500 = xor(UInt<8>("h0ff"), _T_1499) @[Bitwise.scala 102:21] + node _T_1501 = shr(_T_1498, 4) @[Bitwise.scala 103:21] + node _T_1502 = and(_T_1501, _T_1500) @[Bitwise.scala 103:31] + node _T_1503 = bits(_T_1498, 3, 0) @[Bitwise.scala 103:46] + node _T_1504 = shl(_T_1503, 4) @[Bitwise.scala 103:65] + node _T_1505 = not(_T_1500) @[Bitwise.scala 103:77] + node _T_1506 = and(_T_1504, _T_1505) @[Bitwise.scala 103:75] + node _T_1507 = or(_T_1502, _T_1506) @[Bitwise.scala 103:39] + node _T_1508 = bits(_T_1500, 5, 0) @[Bitwise.scala 102:28] + node _T_1509 = shl(_T_1508, 2) @[Bitwise.scala 102:47] + node _T_1510 = xor(_T_1500, _T_1509) @[Bitwise.scala 102:21] + node _T_1511 = shr(_T_1507, 2) @[Bitwise.scala 103:21] + node _T_1512 = and(_T_1511, _T_1510) @[Bitwise.scala 103:31] + node _T_1513 = bits(_T_1507, 5, 0) @[Bitwise.scala 103:46] + node _T_1514 = shl(_T_1513, 2) @[Bitwise.scala 103:65] + node _T_1515 = not(_T_1510) @[Bitwise.scala 103:77] + node _T_1516 = and(_T_1514, _T_1515) @[Bitwise.scala 103:75] + node _T_1517 = or(_T_1512, _T_1516) @[Bitwise.scala 103:39] + node _T_1518 = bits(_T_1510, 6, 0) @[Bitwise.scala 102:28] + node _T_1519 = shl(_T_1518, 1) @[Bitwise.scala 102:47] + node _T_1520 = xor(_T_1510, _T_1519) @[Bitwise.scala 102:21] + node _T_1521 = shr(_T_1517, 1) @[Bitwise.scala 103:21] + node _T_1522 = and(_T_1521, _T_1520) @[Bitwise.scala 103:31] + node _T_1523 = bits(_T_1517, 6, 0) @[Bitwise.scala 103:46] + node _T_1524 = shl(_T_1523, 1) @[Bitwise.scala 103:65] + node _T_1525 = not(_T_1520) @[Bitwise.scala 103:77] + node _T_1526 = and(_T_1524, _T_1525) @[Bitwise.scala 103:75] + node _T_1527 = or(_T_1522, _T_1526) @[Bitwise.scala 103:39] + wire _T_1528 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 285:63] + _T_1528[0] <= _T_1416 @[el2_lsu_dccm_ctl.scala 285:63] + _T_1528[1] <= _T_1453 @[el2_lsu_dccm_ctl.scala 285:63] + _T_1528[2] <= _T_1490 @[el2_lsu_dccm_ctl.scala 285:63] + _T_1528[3] <= _T_1527 @[el2_lsu_dccm_ctl.scala 285:63] + node _T_1529 = cat(_T_1528[2], _T_1528[3]) @[Cat.scala 29:58] + node _T_1530 = cat(_T_1528[0], _T_1528[1]) @[Cat.scala 29:58] + node _T_1531 = cat(_T_1530, _T_1529) @[Cat.scala 29:58] + node _T_1532 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1533 = xor(UInt<32>("h0ffffffff"), _T_1532) @[Bitwise.scala 102:21] + node _T_1534 = shr(_T_1531, 16) @[Bitwise.scala 103:21] + node _T_1535 = and(_T_1534, _T_1533) @[Bitwise.scala 103:31] + node _T_1536 = bits(_T_1531, 15, 0) @[Bitwise.scala 103:46] + node _T_1537 = shl(_T_1536, 16) @[Bitwise.scala 103:65] + node _T_1538 = not(_T_1533) @[Bitwise.scala 103:77] + node _T_1539 = and(_T_1537, _T_1538) @[Bitwise.scala 103:75] + node _T_1540 = or(_T_1535, _T_1539) @[Bitwise.scala 103:39] + node _T_1541 = bits(_T_1533, 23, 0) @[Bitwise.scala 102:28] + node _T_1542 = shl(_T_1541, 8) @[Bitwise.scala 102:47] + node _T_1543 = xor(_T_1533, _T_1542) @[Bitwise.scala 102:21] + node _T_1544 = shr(_T_1540, 8) @[Bitwise.scala 103:21] + node _T_1545 = and(_T_1544, _T_1543) @[Bitwise.scala 103:31] + node _T_1546 = bits(_T_1540, 23, 0) @[Bitwise.scala 103:46] + node _T_1547 = shl(_T_1546, 8) @[Bitwise.scala 103:65] + node _T_1548 = not(_T_1543) @[Bitwise.scala 103:77] + node _T_1549 = and(_T_1547, _T_1548) @[Bitwise.scala 103:75] + node _T_1550 = or(_T_1545, _T_1549) @[Bitwise.scala 103:39] + node _T_1551 = bits(_T_1543, 27, 0) @[Bitwise.scala 102:28] + node _T_1552 = shl(_T_1551, 4) @[Bitwise.scala 102:47] + node _T_1553 = xor(_T_1543, _T_1552) @[Bitwise.scala 102:21] + node _T_1554 = shr(_T_1550, 4) @[Bitwise.scala 103:21] + node _T_1555 = and(_T_1554, _T_1553) @[Bitwise.scala 103:31] + node _T_1556 = bits(_T_1550, 27, 0) @[Bitwise.scala 103:46] + node _T_1557 = shl(_T_1556, 4) @[Bitwise.scala 103:65] + node _T_1558 = not(_T_1553) @[Bitwise.scala 103:77] + node _T_1559 = and(_T_1557, _T_1558) @[Bitwise.scala 103:75] + node _T_1560 = or(_T_1555, _T_1559) @[Bitwise.scala 103:39] + node _T_1561 = bits(_T_1553, 29, 0) @[Bitwise.scala 102:28] + node _T_1562 = shl(_T_1561, 2) @[Bitwise.scala 102:47] + node _T_1563 = xor(_T_1553, _T_1562) @[Bitwise.scala 102:21] + node _T_1564 = shr(_T_1560, 2) @[Bitwise.scala 103:21] + node _T_1565 = and(_T_1564, _T_1563) @[Bitwise.scala 103:31] + node _T_1566 = bits(_T_1560, 29, 0) @[Bitwise.scala 103:46] + node _T_1567 = shl(_T_1566, 2) @[Bitwise.scala 103:65] + node _T_1568 = not(_T_1563) @[Bitwise.scala 103:77] + node _T_1569 = and(_T_1567, _T_1568) @[Bitwise.scala 103:75] + node _T_1570 = or(_T_1565, _T_1569) @[Bitwise.scala 103:39] + node _T_1571 = bits(_T_1563, 30, 0) @[Bitwise.scala 102:28] + node _T_1572 = shl(_T_1571, 1) @[Bitwise.scala 102:47] + node _T_1573 = xor(_T_1563, _T_1572) @[Bitwise.scala 102:21] + node _T_1574 = shr(_T_1570, 1) @[Bitwise.scala 103:21] + node _T_1575 = and(_T_1574, _T_1573) @[Bitwise.scala 103:31] + node _T_1576 = bits(_T_1570, 30, 0) @[Bitwise.scala 103:46] + node _T_1577 = shl(_T_1576, 1) @[Bitwise.scala 103:65] + node _T_1578 = not(_T_1573) @[Bitwise.scala 103:77] + node _T_1579 = and(_T_1577, _T_1578) @[Bitwise.scala 103:75] + node _T_1580 = or(_T_1575, _T_1579) @[Bitwise.scala 103:39] + io.store_datafn_lo_r <= _T_1580 @[el2_lsu_dccm_ctl.scala 285:29] + node _T_1581 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105] + node _T_1582 = bits(store_byteen_ext_r, 4, 4) @[el2_lsu_dccm_ctl.scala 286:150] + node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131] + node _T_1584 = and(_T_1581, _T_1583) @[el2_lsu_dccm_ctl.scala 286:129] + node _T_1585 = bits(_T_1584, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157] + node _T_1586 = bits(io.stbuf_data_any, 7, 0) @[el2_lsu_dccm_ctl.scala 286:181] + node _T_1587 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_dccm_ctl.scala 286:213] + node _T_1588 = mux(_T_1585, _T_1586, _T_1587) @[el2_lsu_dccm_ctl.scala 286:79] + node _T_1589 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1590 = xor(UInt<8>("h0ff"), _T_1589) @[Bitwise.scala 102:21] + node _T_1591 = shr(_T_1588, 4) @[Bitwise.scala 103:21] + node _T_1592 = and(_T_1591, _T_1590) @[Bitwise.scala 103:31] + node _T_1593 = bits(_T_1588, 3, 0) @[Bitwise.scala 103:46] + node _T_1594 = shl(_T_1593, 4) @[Bitwise.scala 103:65] + node _T_1595 = not(_T_1590) @[Bitwise.scala 103:77] + node _T_1596 = and(_T_1594, _T_1595) @[Bitwise.scala 103:75] + node _T_1597 = or(_T_1592, _T_1596) @[Bitwise.scala 103:39] + node _T_1598 = bits(_T_1590, 5, 0) @[Bitwise.scala 102:28] + node _T_1599 = shl(_T_1598, 2) @[Bitwise.scala 102:47] + node _T_1600 = xor(_T_1590, _T_1599) @[Bitwise.scala 102:21] + node _T_1601 = shr(_T_1597, 2) @[Bitwise.scala 103:21] + node _T_1602 = and(_T_1601, _T_1600) @[Bitwise.scala 103:31] + node _T_1603 = bits(_T_1597, 5, 0) @[Bitwise.scala 103:46] + node _T_1604 = shl(_T_1603, 2) @[Bitwise.scala 103:65] + node _T_1605 = not(_T_1600) @[Bitwise.scala 103:77] + node _T_1606 = and(_T_1604, _T_1605) @[Bitwise.scala 103:75] + node _T_1607 = or(_T_1602, _T_1606) @[Bitwise.scala 103:39] + node _T_1608 = bits(_T_1600, 6, 0) @[Bitwise.scala 102:28] + node _T_1609 = shl(_T_1608, 1) @[Bitwise.scala 102:47] + node _T_1610 = xor(_T_1600, _T_1609) @[Bitwise.scala 102:21] + node _T_1611 = shr(_T_1607, 1) @[Bitwise.scala 103:21] + node _T_1612 = and(_T_1611, _T_1610) @[Bitwise.scala 103:31] + node _T_1613 = bits(_T_1607, 6, 0) @[Bitwise.scala 103:46] + node _T_1614 = shl(_T_1613, 1) @[Bitwise.scala 103:65] + node _T_1615 = not(_T_1610) @[Bitwise.scala 103:77] + node _T_1616 = and(_T_1614, _T_1615) @[Bitwise.scala 103:75] + node _T_1617 = or(_T_1612, _T_1616) @[Bitwise.scala 103:39] + node _T_1618 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105] + node _T_1619 = bits(store_byteen_ext_r, 5, 5) @[el2_lsu_dccm_ctl.scala 286:150] + node _T_1620 = eq(_T_1619, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131] + node _T_1621 = and(_T_1618, _T_1620) @[el2_lsu_dccm_ctl.scala 286:129] + node _T_1622 = bits(_T_1621, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157] + node _T_1623 = bits(io.stbuf_data_any, 15, 8) @[el2_lsu_dccm_ctl.scala 286:181] + node _T_1624 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_dccm_ctl.scala 286:213] + node _T_1625 = mux(_T_1622, _T_1623, _T_1624) @[el2_lsu_dccm_ctl.scala 286:79] + node _T_1626 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1627 = xor(UInt<8>("h0ff"), _T_1626) @[Bitwise.scala 102:21] + node _T_1628 = shr(_T_1625, 4) @[Bitwise.scala 103:21] + node _T_1629 = and(_T_1628, _T_1627) @[Bitwise.scala 103:31] + node _T_1630 = bits(_T_1625, 3, 0) @[Bitwise.scala 103:46] + node _T_1631 = shl(_T_1630, 4) @[Bitwise.scala 103:65] + node _T_1632 = not(_T_1627) @[Bitwise.scala 103:77] + node _T_1633 = and(_T_1631, _T_1632) @[Bitwise.scala 103:75] + node _T_1634 = or(_T_1629, _T_1633) @[Bitwise.scala 103:39] + node _T_1635 = bits(_T_1627, 5, 0) @[Bitwise.scala 102:28] + node _T_1636 = shl(_T_1635, 2) @[Bitwise.scala 102:47] + node _T_1637 = xor(_T_1627, _T_1636) @[Bitwise.scala 102:21] + node _T_1638 = shr(_T_1634, 2) @[Bitwise.scala 103:21] + node _T_1639 = and(_T_1638, _T_1637) @[Bitwise.scala 103:31] + node _T_1640 = bits(_T_1634, 5, 0) @[Bitwise.scala 103:46] + node _T_1641 = shl(_T_1640, 2) @[Bitwise.scala 103:65] + node _T_1642 = not(_T_1637) @[Bitwise.scala 103:77] + node _T_1643 = and(_T_1641, _T_1642) @[Bitwise.scala 103:75] + node _T_1644 = or(_T_1639, _T_1643) @[Bitwise.scala 103:39] + node _T_1645 = bits(_T_1637, 6, 0) @[Bitwise.scala 102:28] + node _T_1646 = shl(_T_1645, 1) @[Bitwise.scala 102:47] + node _T_1647 = xor(_T_1637, _T_1646) @[Bitwise.scala 102:21] + node _T_1648 = shr(_T_1644, 1) @[Bitwise.scala 103:21] + node _T_1649 = and(_T_1648, _T_1647) @[Bitwise.scala 103:31] + node _T_1650 = bits(_T_1644, 6, 0) @[Bitwise.scala 103:46] + node _T_1651 = shl(_T_1650, 1) @[Bitwise.scala 103:65] + node _T_1652 = not(_T_1647) @[Bitwise.scala 103:77] + node _T_1653 = and(_T_1651, _T_1652) @[Bitwise.scala 103:75] + node _T_1654 = or(_T_1649, _T_1653) @[Bitwise.scala 103:39] + node _T_1655 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105] + node _T_1656 = bits(store_byteen_ext_r, 6, 6) @[el2_lsu_dccm_ctl.scala 286:150] + node _T_1657 = eq(_T_1656, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131] + node _T_1658 = and(_T_1655, _T_1657) @[el2_lsu_dccm_ctl.scala 286:129] + node _T_1659 = bits(_T_1658, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157] + node _T_1660 = bits(io.stbuf_data_any, 23, 16) @[el2_lsu_dccm_ctl.scala 286:181] + node _T_1661 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_dccm_ctl.scala 286:213] + node _T_1662 = mux(_T_1659, _T_1660, _T_1661) @[el2_lsu_dccm_ctl.scala 286:79] + node _T_1663 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1664 = xor(UInt<8>("h0ff"), _T_1663) @[Bitwise.scala 102:21] + node _T_1665 = shr(_T_1662, 4) @[Bitwise.scala 103:21] + node _T_1666 = and(_T_1665, _T_1664) @[Bitwise.scala 103:31] + node _T_1667 = bits(_T_1662, 3, 0) @[Bitwise.scala 103:46] + node _T_1668 = shl(_T_1667, 4) @[Bitwise.scala 103:65] + node _T_1669 = not(_T_1664) @[Bitwise.scala 103:77] + node _T_1670 = and(_T_1668, _T_1669) @[Bitwise.scala 103:75] + node _T_1671 = or(_T_1666, _T_1670) @[Bitwise.scala 103:39] + node _T_1672 = bits(_T_1664, 5, 0) @[Bitwise.scala 102:28] + node _T_1673 = shl(_T_1672, 2) @[Bitwise.scala 102:47] + node _T_1674 = xor(_T_1664, _T_1673) @[Bitwise.scala 102:21] + node _T_1675 = shr(_T_1671, 2) @[Bitwise.scala 103:21] + node _T_1676 = and(_T_1675, _T_1674) @[Bitwise.scala 103:31] + node _T_1677 = bits(_T_1671, 5, 0) @[Bitwise.scala 103:46] + node _T_1678 = shl(_T_1677, 2) @[Bitwise.scala 103:65] + node _T_1679 = not(_T_1674) @[Bitwise.scala 103:77] + node _T_1680 = and(_T_1678, _T_1679) @[Bitwise.scala 103:75] + node _T_1681 = or(_T_1676, _T_1680) @[Bitwise.scala 103:39] + node _T_1682 = bits(_T_1674, 6, 0) @[Bitwise.scala 102:28] + node _T_1683 = shl(_T_1682, 1) @[Bitwise.scala 102:47] + node _T_1684 = xor(_T_1674, _T_1683) @[Bitwise.scala 102:21] + node _T_1685 = shr(_T_1681, 1) @[Bitwise.scala 103:21] + node _T_1686 = and(_T_1685, _T_1684) @[Bitwise.scala 103:31] + node _T_1687 = bits(_T_1681, 6, 0) @[Bitwise.scala 103:46] + node _T_1688 = shl(_T_1687, 1) @[Bitwise.scala 103:65] + node _T_1689 = not(_T_1684) @[Bitwise.scala 103:77] + node _T_1690 = and(_T_1688, _T_1689) @[Bitwise.scala 103:75] + node _T_1691 = or(_T_1686, _T_1690) @[Bitwise.scala 103:39] + node _T_1692 = and(io.lsu_stbuf_commit_any, dccm_wr_bypass_d_r_hi) @[el2_lsu_dccm_ctl.scala 286:105] + node _T_1693 = bits(store_byteen_ext_r, 7, 7) @[el2_lsu_dccm_ctl.scala 286:150] + node _T_1694 = eq(_T_1693, UInt<1>("h00")) @[el2_lsu_dccm_ctl.scala 286:131] + node _T_1695 = and(_T_1692, _T_1694) @[el2_lsu_dccm_ctl.scala 286:129] + node _T_1696 = bits(_T_1695, 0, 0) @[el2_lsu_dccm_ctl.scala 286:157] + node _T_1697 = bits(io.stbuf_data_any, 31, 24) @[el2_lsu_dccm_ctl.scala 286:181] + node _T_1698 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_dccm_ctl.scala 286:213] + node _T_1699 = mux(_T_1696, _T_1697, _T_1698) @[el2_lsu_dccm_ctl.scala 286:79] + node _T_1700 = shl(UInt<4>("h0f"), 4) @[Bitwise.scala 102:47] + node _T_1701 = xor(UInt<8>("h0ff"), _T_1700) @[Bitwise.scala 102:21] + node _T_1702 = shr(_T_1699, 4) @[Bitwise.scala 103:21] + node _T_1703 = and(_T_1702, _T_1701) @[Bitwise.scala 103:31] + node _T_1704 = bits(_T_1699, 3, 0) @[Bitwise.scala 103:46] + node _T_1705 = shl(_T_1704, 4) @[Bitwise.scala 103:65] + node _T_1706 = not(_T_1701) @[Bitwise.scala 103:77] + node _T_1707 = and(_T_1705, _T_1706) @[Bitwise.scala 103:75] + node _T_1708 = or(_T_1703, _T_1707) @[Bitwise.scala 103:39] + node _T_1709 = bits(_T_1701, 5, 0) @[Bitwise.scala 102:28] + node _T_1710 = shl(_T_1709, 2) @[Bitwise.scala 102:47] + node _T_1711 = xor(_T_1701, _T_1710) @[Bitwise.scala 102:21] + node _T_1712 = shr(_T_1708, 2) @[Bitwise.scala 103:21] + node _T_1713 = and(_T_1712, _T_1711) @[Bitwise.scala 103:31] + node _T_1714 = bits(_T_1708, 5, 0) @[Bitwise.scala 103:46] + node _T_1715 = shl(_T_1714, 2) @[Bitwise.scala 103:65] + node _T_1716 = not(_T_1711) @[Bitwise.scala 103:77] + node _T_1717 = and(_T_1715, _T_1716) @[Bitwise.scala 103:75] + node _T_1718 = or(_T_1713, _T_1717) @[Bitwise.scala 103:39] + node _T_1719 = bits(_T_1711, 6, 0) @[Bitwise.scala 102:28] + node _T_1720 = shl(_T_1719, 1) @[Bitwise.scala 102:47] + node _T_1721 = xor(_T_1711, _T_1720) @[Bitwise.scala 102:21] + node _T_1722 = shr(_T_1718, 1) @[Bitwise.scala 103:21] + node _T_1723 = and(_T_1722, _T_1721) @[Bitwise.scala 103:31] + node _T_1724 = bits(_T_1718, 6, 0) @[Bitwise.scala 103:46] + node _T_1725 = shl(_T_1724, 1) @[Bitwise.scala 103:65] + node _T_1726 = not(_T_1721) @[Bitwise.scala 103:77] + node _T_1727 = and(_T_1725, _T_1726) @[Bitwise.scala 103:75] + node _T_1728 = or(_T_1723, _T_1727) @[Bitwise.scala 103:39] + wire _T_1729 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 286:63] + _T_1729[0] <= _T_1617 @[el2_lsu_dccm_ctl.scala 286:63] + _T_1729[1] <= _T_1654 @[el2_lsu_dccm_ctl.scala 286:63] + _T_1729[2] <= _T_1691 @[el2_lsu_dccm_ctl.scala 286:63] + _T_1729[3] <= _T_1728 @[el2_lsu_dccm_ctl.scala 286:63] + node _T_1730 = cat(_T_1729[2], _T_1729[3]) @[Cat.scala 29:58] + node _T_1731 = cat(_T_1729[0], _T_1729[1]) @[Cat.scala 29:58] + node _T_1732 = cat(_T_1731, _T_1730) @[Cat.scala 29:58] + node _T_1733 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1734 = xor(UInt<32>("h0ffffffff"), _T_1733) @[Bitwise.scala 102:21] + node _T_1735 = shr(_T_1732, 16) @[Bitwise.scala 103:21] + node _T_1736 = and(_T_1735, _T_1734) @[Bitwise.scala 103:31] + node _T_1737 = bits(_T_1732, 15, 0) @[Bitwise.scala 103:46] + node _T_1738 = shl(_T_1737, 16) @[Bitwise.scala 103:65] + node _T_1739 = not(_T_1734) @[Bitwise.scala 103:77] + node _T_1740 = and(_T_1738, _T_1739) @[Bitwise.scala 103:75] + node _T_1741 = or(_T_1736, _T_1740) @[Bitwise.scala 103:39] + node _T_1742 = bits(_T_1734, 23, 0) @[Bitwise.scala 102:28] + node _T_1743 = shl(_T_1742, 8) @[Bitwise.scala 102:47] + node _T_1744 = xor(_T_1734, _T_1743) @[Bitwise.scala 102:21] + node _T_1745 = shr(_T_1741, 8) @[Bitwise.scala 103:21] + node _T_1746 = and(_T_1745, _T_1744) @[Bitwise.scala 103:31] + node _T_1747 = bits(_T_1741, 23, 0) @[Bitwise.scala 103:46] + node _T_1748 = shl(_T_1747, 8) @[Bitwise.scala 103:65] + node _T_1749 = not(_T_1744) @[Bitwise.scala 103:77] + node _T_1750 = and(_T_1748, _T_1749) @[Bitwise.scala 103:75] + node _T_1751 = or(_T_1746, _T_1750) @[Bitwise.scala 103:39] + node _T_1752 = bits(_T_1744, 27, 0) @[Bitwise.scala 102:28] + node _T_1753 = shl(_T_1752, 4) @[Bitwise.scala 102:47] + node _T_1754 = xor(_T_1744, _T_1753) @[Bitwise.scala 102:21] + node _T_1755 = shr(_T_1751, 4) @[Bitwise.scala 103:21] + node _T_1756 = and(_T_1755, _T_1754) @[Bitwise.scala 103:31] + node _T_1757 = bits(_T_1751, 27, 0) @[Bitwise.scala 103:46] + node _T_1758 = shl(_T_1757, 4) @[Bitwise.scala 103:65] + node _T_1759 = not(_T_1754) @[Bitwise.scala 103:77] + node _T_1760 = and(_T_1758, _T_1759) @[Bitwise.scala 103:75] + node _T_1761 = or(_T_1756, _T_1760) @[Bitwise.scala 103:39] + node _T_1762 = bits(_T_1754, 29, 0) @[Bitwise.scala 102:28] + node _T_1763 = shl(_T_1762, 2) @[Bitwise.scala 102:47] + node _T_1764 = xor(_T_1754, _T_1763) @[Bitwise.scala 102:21] + node _T_1765 = shr(_T_1761, 2) @[Bitwise.scala 103:21] + node _T_1766 = and(_T_1765, _T_1764) @[Bitwise.scala 103:31] + node _T_1767 = bits(_T_1761, 29, 0) @[Bitwise.scala 103:46] + node _T_1768 = shl(_T_1767, 2) @[Bitwise.scala 103:65] + node _T_1769 = not(_T_1764) @[Bitwise.scala 103:77] + node _T_1770 = and(_T_1768, _T_1769) @[Bitwise.scala 103:75] + node _T_1771 = or(_T_1766, _T_1770) @[Bitwise.scala 103:39] + node _T_1772 = bits(_T_1764, 30, 0) @[Bitwise.scala 102:28] + node _T_1773 = shl(_T_1772, 1) @[Bitwise.scala 102:47] + node _T_1774 = xor(_T_1764, _T_1773) @[Bitwise.scala 102:21] + node _T_1775 = shr(_T_1771, 1) @[Bitwise.scala 103:21] + node _T_1776 = and(_T_1775, _T_1774) @[Bitwise.scala 103:31] + node _T_1777 = bits(_T_1771, 30, 0) @[Bitwise.scala 103:46] + node _T_1778 = shl(_T_1777, 1) @[Bitwise.scala 103:65] + node _T_1779 = not(_T_1774) @[Bitwise.scala 103:77] + node _T_1780 = and(_T_1778, _T_1779) @[Bitwise.scala 103:75] + node _T_1781 = or(_T_1776, _T_1780) @[Bitwise.scala 103:39] + io.store_datafn_hi_r <= _T_1781 @[el2_lsu_dccm_ctl.scala 286:29] + node _T_1782 = bits(io.store_data_hi_r, 31, 0) @[el2_lsu_dccm_ctl.scala 287:55] + node _T_1783 = bits(io.store_data_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 287:80] + node _T_1784 = cat(_T_1782, _T_1783) @[Cat.scala 29:58] + node _T_1785 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_dccm_ctl.scala 287:108] + node _T_1786 = mul(UInt<4>("h08"), _T_1785) @[el2_lsu_dccm_ctl.scala 287:94] + node _T_1787 = dshr(_T_1784, _T_1786) @[el2_lsu_dccm_ctl.scala 287:88] + node _T_1788 = bits(store_byteen_r, 0, 0) @[el2_lsu_dccm_ctl.scala 287:174] + node _T_1789 = bits(_T_1788, 0, 0) @[Bitwise.scala 72:15] + node _T_1790 = mux(_T_1789, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1791 = bits(store_byteen_r, 1, 1) @[el2_lsu_dccm_ctl.scala 287:174] + node _T_1792 = bits(_T_1791, 0, 0) @[Bitwise.scala 72:15] + node _T_1793 = mux(_T_1792, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1794 = bits(store_byteen_r, 2, 2) @[el2_lsu_dccm_ctl.scala 287:174] + node _T_1795 = bits(_T_1794, 0, 0) @[Bitwise.scala 72:15] + node _T_1796 = mux(_T_1795, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1797 = bits(store_byteen_r, 3, 3) @[el2_lsu_dccm_ctl.scala 287:174] + node _T_1798 = bits(_T_1797, 0, 0) @[Bitwise.scala 72:15] + node _T_1799 = mux(_T_1798, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + wire _T_1800 : UInt<8>[4] @[el2_lsu_dccm_ctl.scala 287:148] + _T_1800[0] <= _T_1790 @[el2_lsu_dccm_ctl.scala 287:148] + _T_1800[1] <= _T_1793 @[el2_lsu_dccm_ctl.scala 287:148] + _T_1800[2] <= _T_1796 @[el2_lsu_dccm_ctl.scala 287:148] + _T_1800[3] <= _T_1799 @[el2_lsu_dccm_ctl.scala 287:148] + node _T_1801 = cat(_T_1800[2], _T_1800[3]) @[Cat.scala 29:58] + node _T_1802 = cat(_T_1800[0], _T_1800[1]) @[Cat.scala 29:58] + node _T_1803 = cat(_T_1802, _T_1801) @[Cat.scala 29:58] + node _T_1804 = shl(UInt<16>("h0ffff"), 16) @[Bitwise.scala 102:47] + node _T_1805 = xor(UInt<32>("h0ffffffff"), _T_1804) @[Bitwise.scala 102:21] + node _T_1806 = shr(_T_1803, 16) @[Bitwise.scala 103:21] + node _T_1807 = and(_T_1806, _T_1805) @[Bitwise.scala 103:31] + node _T_1808 = bits(_T_1803, 15, 0) @[Bitwise.scala 103:46] + node _T_1809 = shl(_T_1808, 16) @[Bitwise.scala 103:65] + node _T_1810 = not(_T_1805) @[Bitwise.scala 103:77] + node _T_1811 = and(_T_1809, _T_1810) @[Bitwise.scala 103:75] + node _T_1812 = or(_T_1807, _T_1811) @[Bitwise.scala 103:39] + node _T_1813 = bits(_T_1805, 23, 0) @[Bitwise.scala 102:28] + node _T_1814 = shl(_T_1813, 8) @[Bitwise.scala 102:47] + node _T_1815 = xor(_T_1805, _T_1814) @[Bitwise.scala 102:21] + node _T_1816 = shr(_T_1812, 8) @[Bitwise.scala 103:21] + node _T_1817 = and(_T_1816, _T_1815) @[Bitwise.scala 103:31] + node _T_1818 = bits(_T_1812, 23, 0) @[Bitwise.scala 103:46] + node _T_1819 = shl(_T_1818, 8) @[Bitwise.scala 103:65] + node _T_1820 = not(_T_1815) @[Bitwise.scala 103:77] + node _T_1821 = and(_T_1819, _T_1820) @[Bitwise.scala 103:75] + node _T_1822 = or(_T_1817, _T_1821) @[Bitwise.scala 103:39] + node _T_1823 = bits(_T_1815, 27, 0) @[Bitwise.scala 102:28] + node _T_1824 = shl(_T_1823, 4) @[Bitwise.scala 102:47] + node _T_1825 = xor(_T_1815, _T_1824) @[Bitwise.scala 102:21] + node _T_1826 = shr(_T_1822, 4) @[Bitwise.scala 103:21] + node _T_1827 = and(_T_1826, _T_1825) @[Bitwise.scala 103:31] + node _T_1828 = bits(_T_1822, 27, 0) @[Bitwise.scala 103:46] + node _T_1829 = shl(_T_1828, 4) @[Bitwise.scala 103:65] + node _T_1830 = not(_T_1825) @[Bitwise.scala 103:77] + node _T_1831 = and(_T_1829, _T_1830) @[Bitwise.scala 103:75] + node _T_1832 = or(_T_1827, _T_1831) @[Bitwise.scala 103:39] + node _T_1833 = bits(_T_1825, 29, 0) @[Bitwise.scala 102:28] + node _T_1834 = shl(_T_1833, 2) @[Bitwise.scala 102:47] + node _T_1835 = xor(_T_1825, _T_1834) @[Bitwise.scala 102:21] + node _T_1836 = shr(_T_1832, 2) @[Bitwise.scala 103:21] + node _T_1837 = and(_T_1836, _T_1835) @[Bitwise.scala 103:31] + node _T_1838 = bits(_T_1832, 29, 0) @[Bitwise.scala 103:46] + node _T_1839 = shl(_T_1838, 2) @[Bitwise.scala 103:65] + node _T_1840 = not(_T_1835) @[Bitwise.scala 103:77] + node _T_1841 = and(_T_1839, _T_1840) @[Bitwise.scala 103:75] + node _T_1842 = or(_T_1837, _T_1841) @[Bitwise.scala 103:39] + node _T_1843 = bits(_T_1835, 30, 0) @[Bitwise.scala 102:28] + node _T_1844 = shl(_T_1843, 1) @[Bitwise.scala 102:47] + node _T_1845 = xor(_T_1835, _T_1844) @[Bitwise.scala 102:21] + node _T_1846 = shr(_T_1842, 1) @[Bitwise.scala 103:21] + node _T_1847 = and(_T_1846, _T_1845) @[Bitwise.scala 103:31] + node _T_1848 = bits(_T_1842, 30, 0) @[Bitwise.scala 103:46] + node _T_1849 = shl(_T_1848, 1) @[Bitwise.scala 103:65] + node _T_1850 = not(_T_1845) @[Bitwise.scala 103:77] + node _T_1851 = and(_T_1849, _T_1850) @[Bitwise.scala 103:75] + node _T_1852 = or(_T_1847, _T_1851) @[Bitwise.scala 103:39] + node _T_1853 = and(_T_1787, _T_1852) @[el2_lsu_dccm_ctl.scala 287:115] + io.store_data_r <= _T_1853 @[el2_lsu_dccm_ctl.scala 287:29] + node _T_1854 = bits(io.dccm_rd_data_lo, 31, 0) @[el2_lsu_dccm_ctl.scala 289:48] + io.dccm_rdata_lo_m <= _T_1854 @[el2_lsu_dccm_ctl.scala 289:27] + node _T_1855 = bits(io.dccm_rd_data_hi, 31, 0) @[el2_lsu_dccm_ctl.scala 290:48] + io.dccm_rdata_hi_m <= _T_1855 @[el2_lsu_dccm_ctl.scala 290:27] + node _T_1856 = bits(io.dccm_rd_data_lo, 38, 32) @[el2_lsu_dccm_ctl.scala 291:48] + io.dccm_data_ecc_lo_m <= _T_1856 @[el2_lsu_dccm_ctl.scala 291:27] + node _T_1857 = bits(io.dccm_rd_data_hi, 38, 32) @[el2_lsu_dccm_ctl.scala 292:48] + io.dccm_data_ecc_hi_m <= _T_1857 @[el2_lsu_dccm_ctl.scala 292:27] + node _T_1858 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_dccm_ctl.scala 294:50] + node _T_1859 = and(_T_1858, io.addr_in_pic_r) @[el2_lsu_dccm_ctl.scala 294:71] + node _T_1860 = and(_T_1859, io.lsu_commit_r) @[el2_lsu_dccm_ctl.scala 294:90] + node _T_1861 = or(_T_1860, io.dma_pic_wen) @[el2_lsu_dccm_ctl.scala 294:109] + io.picm_wren <= _T_1861 @[el2_lsu_dccm_ctl.scala 294:27] + node _T_1862 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.load) @[el2_lsu_dccm_ctl.scala 295:50] + node _T_1863 = and(_T_1862, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 295:71] + io.picm_rden <= _T_1863 @[el2_lsu_dccm_ctl.scala 295:27] + node _T_1864 = and(io.lsu_pkt_d.valid, io.lsu_pkt_d.store) @[el2_lsu_dccm_ctl.scala 296:50] + node _T_1865 = and(_T_1864, io.addr_in_pic_d) @[el2_lsu_dccm_ctl.scala 296:71] + io.picm_mken <= _T_1865 @[el2_lsu_dccm_ctl.scala 296:27] + node _T_1866 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1867 = bits(io.lsu_addr_d, 14, 0) @[el2_lsu_dccm_ctl.scala 297:95] + node _T_1868 = cat(_T_1866, _T_1867) @[Cat.scala 29:58] + node _T_1869 = or(UInt<32>("h0f00c0000"), _T_1868) @[el2_lsu_dccm_ctl.scala 297:54] + io.picm_rdaddr <= _T_1869 @[el2_lsu_dccm_ctl.scala 297:27] + node _T_1870 = mux(UInt<1>("h00"), UInt<17>("h01ffff"), UInt<17>("h00")) @[Bitwise.scala 72:12] + node _T_1871 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 298:101] + node _T_1872 = bits(io.dma_mem_addr, 14, 0) @[el2_lsu_dccm_ctl.scala 298:123] + node _T_1873 = bits(io.lsu_addr_r, 14, 0) @[el2_lsu_dccm_ctl.scala 298:151] + node _T_1874 = mux(_T_1871, _T_1872, _T_1873) @[el2_lsu_dccm_ctl.scala 298:85] + node _T_1875 = cat(_T_1870, _T_1874) @[Cat.scala 29:58] + node _T_1876 = or(UInt<32>("h0f00c0000"), _T_1875) @[el2_lsu_dccm_ctl.scala 298:54] + io.picm_wraddr <= _T_1876 @[el2_lsu_dccm_ctl.scala 298:27] + node _T_1877 = bits(picm_rd_data_m, 31, 0) @[el2_lsu_dccm_ctl.scala 299:44] + io.picm_mask_data_m <= _T_1877 @[el2_lsu_dccm_ctl.scala 299:27] + node _T_1878 = bits(io.dma_pic_wen, 0, 0) @[el2_lsu_dccm_ctl.scala 300:49] + node _T_1879 = bits(io.dma_mem_wdata, 31, 0) @[el2_lsu_dccm_ctl.scala 300:72] + node _T_1880 = bits(io.store_datafn_lo_r, 31, 0) @[el2_lsu_dccm_ctl.scala 300:99] + node _T_1881 = mux(_T_1878, _T_1879, _T_1880) @[el2_lsu_dccm_ctl.scala 300:33] + io.picm_wr_data <= _T_1881 @[el2_lsu_dccm_ctl.scala 300:27] + reg _T_1882 : UInt, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 303:61] + _T_1882 <= lsu_dccm_rden_d @[el2_lsu_dccm_ctl.scala 303:61] + io.lsu_dccm_rden_m <= _T_1882 @[el2_lsu_dccm_ctl.scala 303:24] + reg _T_1883 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_dccm_ctl.scala 304:61] + _T_1883 <= io.lsu_dccm_rden_m @[el2_lsu_dccm_ctl.scala 304:61] + io.lsu_dccm_rden_r <= _T_1883 @[el2_lsu_dccm_ctl.scala 304:24] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_stbuf : input clock : Clock input reset : AsyncReset output io : {flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_stbuf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip store_stbuf_reqvld_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip dec_lsu_valid_raw_d : UInt<1>, flip store_data_hi_r : UInt<32>, flip store_data_lo_r : UInt<32>, flip store_datafn_hi_r : UInt<32>, flip store_datafn_lo_r : UInt<32>, flip lsu_stbuf_commit_any : UInt<1>, flip lsu_addr_d : UInt<16>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<16>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip addr_in_dccm_m : UInt<1>, flip addr_in_dccm_r : UInt<1>, flip lsu_cmpen_m : UInt<1>, flip scan_mode : UInt<1>, stbuf_reqvld_any : UInt<1>, stbuf_reqvld_flushed_any : UInt<1>, stbuf_addr_any : UInt<16>, stbuf_data_any : UInt<32>, lsu_stbuf_full_any : UInt<1>, lsu_stbuf_empty_any : UInt<1>, ldst_stbuf_reqvld_r : UInt<1>, stbuf_fwddata_hi_m : UInt<32>, stbuf_fwddata_lo_m : UInt<32>, stbuf_fwdbyteen_hi_m : UInt<4>, stbuf_fwdbyteen_lo_m : UInt<4>} - io.stbuf_reqvld_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 50:47] - io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 51:36] - io.stbuf_addr_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 52:35] - io.stbuf_data_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 53:35] - io.lsu_stbuf_full_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 54:43] - io.lsu_stbuf_empty_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 55:43] - io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[el2_lsu_stbuf.scala 56:43] - io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 57:43] - io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 58:43] - io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 59:37] - io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 60:37] - wire stbuf_vld : UInt<1>[4] @[el2_lsu_stbuf.scala 63:39] + io.stbuf_reqvld_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 52:47] + io.stbuf_reqvld_flushed_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 53:35] + io.stbuf_addr_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 54:35] + io.stbuf_data_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 55:35] + io.lsu_stbuf_full_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 56:43] + io.lsu_stbuf_empty_any <= UInt<1>("h00") @[el2_lsu_stbuf.scala 57:43] + io.ldst_stbuf_reqvld_r <= UInt<1>("h00") @[el2_lsu_stbuf.scala 58:43] + io.stbuf_fwddata_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 59:43] + io.stbuf_fwddata_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 60:43] + io.stbuf_fwdbyteen_hi_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 61:37] + io.stbuf_fwdbyteen_lo_m <= UInt<1>("h00") @[el2_lsu_stbuf.scala 62:37] + wire stbuf_vld : UInt<4> + stbuf_vld <= UInt<1>("h00") + wire stbuf_wr_en : UInt<4> + stbuf_wr_en <= UInt<1>("h00") wire stbuf_dma_kill_en : UInt<4> stbuf_dma_kill_en <= UInt<1>("h00") - wire stbuf_dma_kill : UInt<1>[4] @[el2_lsu_stbuf.scala 65:39] + wire stbuf_dma_kill : UInt<4> + stbuf_dma_kill <= UInt<1>("h00") wire stbuf_reset : UInt<4> stbuf_reset <= UInt<1>("h00") wire store_byteen_ext_r : UInt<8> store_byteen_ext_r <= UInt<1>("h00") - wire stbuf_addr : UInt<16>[4] @[el2_lsu_stbuf.scala 68:39] - stbuf_addr[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 69:15] - stbuf_addr[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 69:15] - stbuf_addr[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 69:15] - stbuf_addr[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 69:15] - wire stbuf_byteen : UInt<4>[4] @[el2_lsu_stbuf.scala 70:39] - stbuf_byteen[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:17] - stbuf_byteen[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:17] - stbuf_byteen[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:17] - stbuf_byteen[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 71:17] - wire stbuf_data : UInt<32>[4] @[el2_lsu_stbuf.scala 72:39] - stbuf_data[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:15] - stbuf_data[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:15] - stbuf_data[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:15] - stbuf_data[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 73:15] - wire stbuf_addrin : UInt<16>[4] @[el2_lsu_stbuf.scala 74:39] - stbuf_addrin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:17] - stbuf_addrin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:17] - stbuf_addrin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:17] - stbuf_addrin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 75:17] - wire stbuf_datain : UInt<32>[4] @[el2_lsu_stbuf.scala 76:39] - stbuf_datain[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:17] - stbuf_datain[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:17] - stbuf_datain[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:17] - stbuf_datain[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 77:17] - wire stbuf_byteenin : UInt<4>[4] @[el2_lsu_stbuf.scala 78:39] - stbuf_byteenin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:19] - stbuf_byteenin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:19] - stbuf_byteenin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:19] - stbuf_byteenin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 79:19] + wire stbuf_addr : UInt<16>[4] @[el2_lsu_stbuf.scala 71:38] + stbuf_addr[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] + stbuf_addr[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] + stbuf_addr[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] + stbuf_addr[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 72:14] + wire stbuf_byteen : UInt<4>[4] @[el2_lsu_stbuf.scala 73:38] + stbuf_byteen[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:16] + stbuf_byteen[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:16] + stbuf_byteen[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:16] + stbuf_byteen[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 74:16] + wire stbuf_data : UInt<32>[4] @[el2_lsu_stbuf.scala 75:38] + stbuf_data[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:14] + stbuf_data[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:14] + stbuf_data[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:14] + stbuf_data[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 76:14] + wire stbuf_addrin : UInt<16>[4] @[el2_lsu_stbuf.scala 77:38] + stbuf_addrin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] + stbuf_addrin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] + stbuf_addrin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] + stbuf_addrin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 78:16] + wire stbuf_datain : UInt<32>[4] @[el2_lsu_stbuf.scala 79:38] + stbuf_datain[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:16] + stbuf_datain[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:16] + stbuf_datain[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:16] + stbuf_datain[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 80:16] + wire stbuf_byteenin : UInt<4>[4] @[el2_lsu_stbuf.scala 81:38] + stbuf_byteenin[0] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:18] + stbuf_byteenin[1] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:18] + stbuf_byteenin[2] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:18] + stbuf_byteenin[3] <= UInt<1>("h00") @[el2_lsu_stbuf.scala 82:18] wire WrPtr : UInt<2> WrPtr <= UInt<1>("h00") wire RdPtr : UInt<2> @@ -1935,13 +3160,13 @@ circuit el2_lsu : stbuf_fwdata_hi_pre_m <= UInt<1>("h00") wire stbuf_fwdata_lo_pre_m : UInt<32> stbuf_fwdata_lo_pre_m <= UInt<1>("h00") - wire ld_byte_rhit_lo_lo : UInt<32> + wire ld_byte_rhit_lo_lo : UInt<4> ld_byte_rhit_lo_lo <= UInt<1>("h00") - wire ld_byte_rhit_hi_lo : UInt<32> + wire ld_byte_rhit_hi_lo : UInt<4> ld_byte_rhit_hi_lo <= UInt<1>("h00") - wire ld_byte_rhit_lo_hi : UInt<32> + wire ld_byte_rhit_lo_hi : UInt<4> ld_byte_rhit_lo_hi <= UInt<1>("h00") - wire ld_byte_rhit_hi_hi : UInt<32> + wire ld_byte_rhit_hi_hi : UInt<4> ld_byte_rhit_hi_hi <= UInt<1>("h00") wire ld_byte_hit_lo : UInt<4> ld_byte_hit_lo <= UInt<1>("h00") @@ -1957,1482 +3182,1625 @@ circuit el2_lsu : ld_fwddata_rpipe_lo <= UInt<1>("h00") wire ld_fwddata_rpipe_hi : UInt<32> ld_fwddata_rpipe_hi <= UInt<1>("h00") - wire datain1 : UInt<8>[4] @[el2_lsu_stbuf.scala 102:34] - wire datain2 : UInt<8>[4] @[el2_lsu_stbuf.scala 103:34] - wire datain3 : UInt<8>[4] @[el2_lsu_stbuf.scala 104:34] - wire datain4 : UInt<8>[4] @[el2_lsu_stbuf.scala 105:34] - node _T = bits(io.lsu_pkt_r.by, 0, 0) @[Bitwise.scala 72:15] - node _T_1 = mux(_T, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_2 = and(_T_1, UInt<1>("h01")) @[el2_lsu_stbuf.scala 108:49] - node _T_3 = bits(io.lsu_pkt_r.half, 0, 0) @[Bitwise.scala 72:15] - node _T_4 = mux(_T_3, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_5 = and(_T_4, UInt<2>("h03")) @[el2_lsu_stbuf.scala 109:32] - node _T_6 = or(_T_2, _T_5) @[el2_lsu_stbuf.scala 108:65] - node _T_7 = bits(io.lsu_pkt_r.word, 0, 0) @[Bitwise.scala 72:15] - node _T_8 = mux(_T_7, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_9 = and(_T_8, UInt<4>("h0f")) @[el2_lsu_stbuf.scala 110:32] - node _T_10 = or(_T_6, _T_9) @[el2_lsu_stbuf.scala 109:48] - node _T_11 = bits(io.lsu_pkt_r.dword, 0, 0) @[Bitwise.scala 72:15] - node _T_12 = mux(_T_11, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_13 = and(_T_12, UInt<8>("h0ff")) @[el2_lsu_stbuf.scala 111:33] - node ldst_byteen_r = or(_T_10, _T_13) @[el2_lsu_stbuf.scala 110:48] - node _T_14 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_stbuf.scala 112:36] - node _T_15 = bits(io.end_addr_d, 2, 2) @[el2_lsu_stbuf.scala 112:57] - node ldst_dual_d = neq(_T_14, _T_15) @[el2_lsu_stbuf.scala 112:40] - node dual_stbuf_write_r = and(ldst_dual_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 113:41] - node _T_16 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 115:56] - node _T_17 = dshl(ldst_byteen_r, _T_16) @[el2_lsu_stbuf.scala 115:40] - store_byteen_ext_r <= _T_17 @[el2_lsu_stbuf.scala 115:23] - node _T_18 = bits(store_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 116:47] - node _T_19 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15] + wire datain1 : UInt<8>[4] @[el2_lsu_stbuf.scala 106:33] + wire datain2 : UInt<8>[4] @[el2_lsu_stbuf.scala 107:33] + wire datain3 : UInt<8>[4] @[el2_lsu_stbuf.scala 108:33] + wire datain4 : UInt<8>[4] @[el2_lsu_stbuf.scala 109:33] + node _T = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_stbuf.scala 113:21] + node _T_1 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_stbuf.scala 114:23] + node _T_2 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_stbuf.scala 115:23] + node _T_3 = bits(io.lsu_pkt_r.dword, 0, 0) @[el2_lsu_stbuf.scala 116:24] + node _T_4 = mux(_T, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_1, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = mux(_T_2, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_7 = mux(_T_3, UInt<8>("h0ff"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_8 = or(_T_4, _T_5) @[Mux.scala 27:72] + node _T_9 = or(_T_8, _T_6) @[Mux.scala 27:72] + node _T_10 = or(_T_9, _T_7) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<8> @[Mux.scala 27:72] + ldst_byteen_r <= _T_10 @[Mux.scala 27:72] + node _T_11 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_stbuf.scala 118:35] + node _T_12 = bits(io.end_addr_d, 2, 2) @[el2_lsu_stbuf.scala 118:56] + node ldst_dual_d = neq(_T_11, _T_12) @[el2_lsu_stbuf.scala 118:39] + node dual_stbuf_write_r = and(ldst_dual_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 119:40] + node _T_13 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 121:55] + node _T_14 = dshl(ldst_byteen_r, _T_13) @[el2_lsu_stbuf.scala 121:39] + store_byteen_ext_r <= _T_14 @[el2_lsu_stbuf.scala 121:22] + node _T_15 = bits(store_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 122:46] + node _T_16 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] + node _T_17 = mux(_T_16, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node store_byteen_hi_r = and(_T_15, _T_17) @[el2_lsu_stbuf.scala 122:52] + node _T_18 = bits(store_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 123:46] + node _T_19 = bits(io.lsu_pkt_r.store, 0, 0) @[Bitwise.scala 72:15] node _T_20 = mux(_T_19, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node store_byteen_hi_r = and(_T_18, _T_20) @[el2_lsu_stbuf.scala 116:53] - node _T_21 = bits(store_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 117:47] - node _T_22 = bits(io.lsu_pkt_m.store, 0, 0) @[Bitwise.scala 72:15] - node _T_23 = mux(_T_22, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node store_byteen_lo_r = and(_T_21, _T_23) @[el2_lsu_stbuf.scala 117:53] - node _T_24 = add(RdPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 118:27] - node NxtRdPtr = tail(_T_24, 1) @[el2_lsu_stbuf.scala 118:27] - node _T_25 = add(WrPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 119:27] - node WrPtrPlus1 = tail(_T_25, 1) @[el2_lsu_stbuf.scala 119:27] - node _T_26 = add(WrPtr, UInt<2>("h02")) @[el2_lsu_stbuf.scala 120:27] - node WrPtrPlus2 = tail(_T_26, 1) @[el2_lsu_stbuf.scala 120:27] - node _T_27 = and(io.lsu_commit_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 122:46] - io.ldst_stbuf_reqvld_r <= _T_27 @[el2_lsu_stbuf.scala 122:27] - node _T_28 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 124:79] - node _T_29 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 124:138] - node _T_30 = eq(_T_28, _T_29) @[el2_lsu_stbuf.scala 124:121] - node _T_31 = and(_T_30, stbuf_vld[0]) @[el2_lsu_stbuf.scala 124:181] - node _T_32 = eq(stbuf_dma_kill[0], UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:198] - node _T_33 = and(_T_31, _T_32) @[el2_lsu_stbuf.scala 124:196] - node _T_34 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 124:231] - node _T_35 = eq(_T_34, UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:219] - node _T_36 = and(_T_33, _T_35) @[el2_lsu_stbuf.scala 124:217] - node _T_37 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 124:79] - node _T_38 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 124:138] - node _T_39 = eq(_T_37, _T_38) @[el2_lsu_stbuf.scala 124:121] - node _T_40 = and(_T_39, stbuf_vld[1]) @[el2_lsu_stbuf.scala 124:181] - node _T_41 = eq(stbuf_dma_kill[1], UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:198] - node _T_42 = and(_T_40, _T_41) @[el2_lsu_stbuf.scala 124:196] - node _T_43 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 124:231] - node _T_44 = eq(_T_43, UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:219] - node _T_45 = and(_T_42, _T_44) @[el2_lsu_stbuf.scala 124:217] - node _T_46 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 124:79] - node _T_47 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 124:138] - node _T_48 = eq(_T_46, _T_47) @[el2_lsu_stbuf.scala 124:121] - node _T_49 = and(_T_48, stbuf_vld[2]) @[el2_lsu_stbuf.scala 124:181] - node _T_50 = eq(stbuf_dma_kill[2], UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:198] - node _T_51 = and(_T_49, _T_50) @[el2_lsu_stbuf.scala 124:196] - node _T_52 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 124:231] - node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:219] - node _T_54 = and(_T_51, _T_53) @[el2_lsu_stbuf.scala 124:217] - node _T_55 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 124:79] - node _T_56 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 124:138] - node _T_57 = eq(_T_55, _T_56) @[el2_lsu_stbuf.scala 124:121] - node _T_58 = and(_T_57, stbuf_vld[3]) @[el2_lsu_stbuf.scala 124:181] - node _T_59 = eq(stbuf_dma_kill[3], UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:198] - node _T_60 = and(_T_58, _T_59) @[el2_lsu_stbuf.scala 124:196] - node _T_61 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 124:231] - node _T_62 = eq(_T_61, UInt<1>("h00")) @[el2_lsu_stbuf.scala 124:219] - node _T_63 = and(_T_60, _T_62) @[el2_lsu_stbuf.scala 124:217] - node _T_64 = cat(_T_63, _T_54) @[Cat.scala 29:58] - node _T_65 = cat(_T_64, _T_45) @[Cat.scala 29:58] - node store_matchvec_lo_r = cat(_T_65, _T_36) @[Cat.scala 29:58] - node _T_66 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 125:79] - node _T_67 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 125:138] - node _T_68 = eq(_T_66, _T_67) @[el2_lsu_stbuf.scala 125:121] - node _T_69 = and(_T_68, stbuf_vld[0]) @[el2_lsu_stbuf.scala 125:181] - node _T_70 = eq(stbuf_dma_kill[0], UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:198] - node _T_71 = and(_T_69, _T_70) @[el2_lsu_stbuf.scala 125:196] - node _T_72 = and(_T_71, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 125:217] - node _T_73 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 125:252] - node _T_74 = eq(_T_73, UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:240] - node _T_75 = and(_T_72, _T_74) @[el2_lsu_stbuf.scala 125:238] - node _T_76 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 125:79] - node _T_77 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 125:138] - node _T_78 = eq(_T_76, _T_77) @[el2_lsu_stbuf.scala 125:121] - node _T_79 = and(_T_78, stbuf_vld[1]) @[el2_lsu_stbuf.scala 125:181] - node _T_80 = eq(stbuf_dma_kill[1], UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:198] - node _T_81 = and(_T_79, _T_80) @[el2_lsu_stbuf.scala 125:196] - node _T_82 = and(_T_81, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 125:217] - node _T_83 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 125:252] - node _T_84 = eq(_T_83, UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:240] - node _T_85 = and(_T_82, _T_84) @[el2_lsu_stbuf.scala 125:238] - node _T_86 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 125:79] - node _T_87 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 125:138] - node _T_88 = eq(_T_86, _T_87) @[el2_lsu_stbuf.scala 125:121] - node _T_89 = and(_T_88, stbuf_vld[2]) @[el2_lsu_stbuf.scala 125:181] - node _T_90 = eq(stbuf_dma_kill[2], UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:198] - node _T_91 = and(_T_89, _T_90) @[el2_lsu_stbuf.scala 125:196] - node _T_92 = and(_T_91, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 125:217] - node _T_93 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 125:252] - node _T_94 = eq(_T_93, UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:240] - node _T_95 = and(_T_92, _T_94) @[el2_lsu_stbuf.scala 125:238] - node _T_96 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 125:79] - node _T_97 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 125:138] - node _T_98 = eq(_T_96, _T_97) @[el2_lsu_stbuf.scala 125:121] - node _T_99 = and(_T_98, stbuf_vld[3]) @[el2_lsu_stbuf.scala 125:181] - node _T_100 = eq(stbuf_dma_kill[3], UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:198] - node _T_101 = and(_T_99, _T_100) @[el2_lsu_stbuf.scala 125:196] - node _T_102 = and(_T_101, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 125:217] - node _T_103 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 125:252] - node _T_104 = eq(_T_103, UInt<1>("h00")) @[el2_lsu_stbuf.scala 125:240] - node _T_105 = and(_T_102, _T_104) @[el2_lsu_stbuf.scala 125:238] - node _T_106 = cat(_T_105, _T_95) @[Cat.scala 29:58] - node _T_107 = cat(_T_106, _T_85) @[Cat.scala 29:58] - node store_matchvec_hi_r = cat(_T_107, _T_75) @[Cat.scala 29:58] - node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[el2_lsu_stbuf.scala 127:50] - node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[el2_lsu_stbuf.scala 128:50] - node _T_108 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 130:92] - node _T_109 = bits(_T_108, 0, 0) @[el2_lsu_stbuf.scala 130:103] - node _T_110 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:112] - node _T_111 = and(_T_109, _T_110) @[el2_lsu_stbuf.scala 130:110] - node _T_112 = and(io.ldst_stbuf_reqvld_r, _T_111) @[el2_lsu_stbuf.scala 130:79] - node _T_113 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 130:147] - node _T_114 = bits(_T_113, 0, 0) @[el2_lsu_stbuf.scala 130:158] - node _T_115 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:167] - node _T_116 = and(_T_114, _T_115) @[el2_lsu_stbuf.scala 130:165] - node _T_117 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:189] - node _T_118 = and(_T_116, _T_117) @[el2_lsu_stbuf.scala 130:187] - node _T_119 = or(_T_112, _T_118) @[el2_lsu_stbuf.scala 130:134] - node _T_120 = eq(UInt<1>("h00"), WrPtrPlus1) @[el2_lsu_stbuf.scala 131:17] - node _T_121 = bits(_T_120, 0, 0) @[el2_lsu_stbuf.scala 131:33] - node _T_122 = and(_T_121, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:40] - node _T_123 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 131:85] - node _T_124 = eq(_T_123, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:63] - node _T_125 = and(_T_122, _T_124) @[el2_lsu_stbuf.scala 131:61] - node _T_126 = or(_T_119, _T_125) @[el2_lsu_stbuf.scala 130:211] - node _T_127 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 131:130] - node _T_128 = or(_T_126, _T_127) @[el2_lsu_stbuf.scala 131:109] - node _T_129 = bits(store_matchvec_hi_r, 0, 0) @[el2_lsu_stbuf.scala 131:155] - node _T_130 = or(_T_128, _T_129) @[el2_lsu_stbuf.scala 131:134] - node _T_131 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 130:92] - node _T_132 = bits(_T_131, 0, 0) @[el2_lsu_stbuf.scala 130:103] - node _T_133 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:112] - node _T_134 = and(_T_132, _T_133) @[el2_lsu_stbuf.scala 130:110] - node _T_135 = and(io.ldst_stbuf_reqvld_r, _T_134) @[el2_lsu_stbuf.scala 130:79] - node _T_136 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 130:147] - node _T_137 = bits(_T_136, 0, 0) @[el2_lsu_stbuf.scala 130:158] - node _T_138 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:167] - node _T_139 = and(_T_137, _T_138) @[el2_lsu_stbuf.scala 130:165] - node _T_140 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:189] - node _T_141 = and(_T_139, _T_140) @[el2_lsu_stbuf.scala 130:187] - node _T_142 = or(_T_135, _T_141) @[el2_lsu_stbuf.scala 130:134] - node _T_143 = eq(UInt<1>("h01"), WrPtrPlus1) @[el2_lsu_stbuf.scala 131:17] - node _T_144 = bits(_T_143, 0, 0) @[el2_lsu_stbuf.scala 131:33] - node _T_145 = and(_T_144, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:40] - node _T_146 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 131:85] - node _T_147 = eq(_T_146, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:63] - node _T_148 = and(_T_145, _T_147) @[el2_lsu_stbuf.scala 131:61] - node _T_149 = or(_T_142, _T_148) @[el2_lsu_stbuf.scala 130:211] - node _T_150 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 131:130] - node _T_151 = or(_T_149, _T_150) @[el2_lsu_stbuf.scala 131:109] - node _T_152 = bits(store_matchvec_hi_r, 1, 1) @[el2_lsu_stbuf.scala 131:155] - node _T_153 = or(_T_151, _T_152) @[el2_lsu_stbuf.scala 131:134] - node _T_154 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 130:92] - node _T_155 = bits(_T_154, 0, 0) @[el2_lsu_stbuf.scala 130:103] - node _T_156 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:112] - node _T_157 = and(_T_155, _T_156) @[el2_lsu_stbuf.scala 130:110] - node _T_158 = and(io.ldst_stbuf_reqvld_r, _T_157) @[el2_lsu_stbuf.scala 130:79] - node _T_159 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 130:147] - node _T_160 = bits(_T_159, 0, 0) @[el2_lsu_stbuf.scala 130:158] - node _T_161 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:167] - node _T_162 = and(_T_160, _T_161) @[el2_lsu_stbuf.scala 130:165] - node _T_163 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:189] - node _T_164 = and(_T_162, _T_163) @[el2_lsu_stbuf.scala 130:187] - node _T_165 = or(_T_158, _T_164) @[el2_lsu_stbuf.scala 130:134] - node _T_166 = eq(UInt<2>("h02"), WrPtrPlus1) @[el2_lsu_stbuf.scala 131:17] - node _T_167 = bits(_T_166, 0, 0) @[el2_lsu_stbuf.scala 131:33] - node _T_168 = and(_T_167, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:40] - node _T_169 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 131:85] - node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:63] - node _T_171 = and(_T_168, _T_170) @[el2_lsu_stbuf.scala 131:61] - node _T_172 = or(_T_165, _T_171) @[el2_lsu_stbuf.scala 130:211] - node _T_173 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 131:130] - node _T_174 = or(_T_172, _T_173) @[el2_lsu_stbuf.scala 131:109] - node _T_175 = bits(store_matchvec_hi_r, 2, 2) @[el2_lsu_stbuf.scala 131:155] - node _T_176 = or(_T_174, _T_175) @[el2_lsu_stbuf.scala 131:134] - node _T_177 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 130:92] - node _T_178 = bits(_T_177, 0, 0) @[el2_lsu_stbuf.scala 130:103] - node _T_179 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:112] - node _T_180 = and(_T_178, _T_179) @[el2_lsu_stbuf.scala 130:110] - node _T_181 = and(io.ldst_stbuf_reqvld_r, _T_180) @[el2_lsu_stbuf.scala 130:79] - node _T_182 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 130:147] - node _T_183 = bits(_T_182, 0, 0) @[el2_lsu_stbuf.scala 130:158] - node _T_184 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:167] - node _T_185 = and(_T_183, _T_184) @[el2_lsu_stbuf.scala 130:165] - node _T_186 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 130:189] - node _T_187 = and(_T_185, _T_186) @[el2_lsu_stbuf.scala 130:187] - node _T_188 = or(_T_181, _T_187) @[el2_lsu_stbuf.scala 130:134] - node _T_189 = eq(UInt<2>("h03"), WrPtrPlus1) @[el2_lsu_stbuf.scala 131:17] - node _T_190 = bits(_T_189, 0, 0) @[el2_lsu_stbuf.scala 131:33] - node _T_191 = and(_T_190, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 131:40] - node _T_192 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 131:85] - node _T_193 = eq(_T_192, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:63] - node _T_194 = and(_T_191, _T_193) @[el2_lsu_stbuf.scala 131:61] - node _T_195 = or(_T_188, _T_194) @[el2_lsu_stbuf.scala 130:211] - node _T_196 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 131:130] - node _T_197 = or(_T_195, _T_196) @[el2_lsu_stbuf.scala 131:109] - node _T_198 = bits(store_matchvec_hi_r, 3, 3) @[el2_lsu_stbuf.scala 131:155] - node _T_199 = or(_T_197, _T_198) @[el2_lsu_stbuf.scala 131:134] - node _T_200 = cat(_T_199, _T_176) @[Cat.scala 29:58] - node _T_201 = cat(_T_200, _T_153) @[Cat.scala 29:58] - node stbuf_wr_en = cat(_T_201, _T_130) @[Cat.scala 29:58] - node _T_202 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 132:78] - node _T_203 = eq(UInt<1>("h00"), RdPtr) @[el2_lsu_stbuf.scala 132:121] - node _T_204 = bits(_T_203, 0, 0) @[el2_lsu_stbuf.scala 132:132] - node _T_205 = and(_T_202, _T_204) @[el2_lsu_stbuf.scala 132:109] - node _T_206 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 132:78] - node _T_207 = eq(UInt<1>("h01"), RdPtr) @[el2_lsu_stbuf.scala 132:121] - node _T_208 = bits(_T_207, 0, 0) @[el2_lsu_stbuf.scala 132:132] - node _T_209 = and(_T_206, _T_208) @[el2_lsu_stbuf.scala 132:109] - node _T_210 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 132:78] - node _T_211 = eq(UInt<2>("h02"), RdPtr) @[el2_lsu_stbuf.scala 132:121] - node _T_212 = bits(_T_211, 0, 0) @[el2_lsu_stbuf.scala 132:132] - node _T_213 = and(_T_210, _T_212) @[el2_lsu_stbuf.scala 132:109] - node _T_214 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 132:78] - node _T_215 = eq(UInt<2>("h03"), RdPtr) @[el2_lsu_stbuf.scala 132:121] - node _T_216 = bits(_T_215, 0, 0) @[el2_lsu_stbuf.scala 132:132] - node _T_217 = and(_T_214, _T_216) @[el2_lsu_stbuf.scala 132:109] - node _T_218 = cat(_T_217, _T_213) @[Cat.scala 29:58] - node _T_219 = cat(_T_218, _T_209) @[Cat.scala 29:58] - node _T_220 = cat(_T_219, _T_205) @[Cat.scala 29:58] - stbuf_reset <= _T_220 @[el2_lsu_stbuf.scala 132:16] - node _T_221 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:52] - node _T_222 = or(_T_221, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 133:65] - node _T_223 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 133:104] - node _T_224 = bits(_T_223, 0, 0) @[el2_lsu_stbuf.scala 133:115] - node _T_225 = and(_T_222, _T_224) @[el2_lsu_stbuf.scala 133:92] - node _T_226 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:124] - node _T_227 = and(_T_225, _T_226) @[el2_lsu_stbuf.scala 133:122] - node _T_228 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 133:166] - node _T_229 = or(_T_227, _T_228) @[el2_lsu_stbuf.scala 133:145] - node _T_230 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:52] - node _T_231 = or(_T_230, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 133:65] - node _T_232 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 133:104] - node _T_233 = bits(_T_232, 0, 0) @[el2_lsu_stbuf.scala 133:115] - node _T_234 = and(_T_231, _T_233) @[el2_lsu_stbuf.scala 133:92] - node _T_235 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:124] - node _T_236 = and(_T_234, _T_235) @[el2_lsu_stbuf.scala 133:122] - node _T_237 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 133:166] - node _T_238 = or(_T_236, _T_237) @[el2_lsu_stbuf.scala 133:145] - node _T_239 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:52] - node _T_240 = or(_T_239, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 133:65] - node _T_241 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 133:104] - node _T_242 = bits(_T_241, 0, 0) @[el2_lsu_stbuf.scala 133:115] - node _T_243 = and(_T_240, _T_242) @[el2_lsu_stbuf.scala 133:92] - node _T_244 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:124] - node _T_245 = and(_T_243, _T_244) @[el2_lsu_stbuf.scala 133:122] - node _T_246 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 133:166] - node _T_247 = or(_T_245, _T_246) @[el2_lsu_stbuf.scala 133:145] - node _T_248 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:52] - node _T_249 = or(_T_248, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 133:65] - node _T_250 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 133:104] - node _T_251 = bits(_T_250, 0, 0) @[el2_lsu_stbuf.scala 133:115] - node _T_252 = and(_T_249, _T_251) @[el2_lsu_stbuf.scala 133:92] - node _T_253 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 133:124] - node _T_254 = and(_T_252, _T_253) @[el2_lsu_stbuf.scala 133:122] - node _T_255 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 133:166] - node _T_256 = or(_T_254, _T_255) @[el2_lsu_stbuf.scala 133:145] - node _T_257 = cat(_T_256, _T_247) @[Cat.scala 29:58] - node _T_258 = cat(_T_257, _T_238) @[Cat.scala 29:58] - node sel_lo = cat(_T_258, _T_229) @[Cat.scala 29:58] - node _T_259 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 135:64] - node _T_260 = mux(_T_259, io.lsu_addr_r, io.end_addr_r) @[el2_lsu_stbuf.scala 135:57] - node _T_261 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 135:64] - node _T_262 = mux(_T_261, io.lsu_addr_r, io.end_addr_r) @[el2_lsu_stbuf.scala 135:57] - node _T_263 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 135:64] - node _T_264 = mux(_T_263, io.lsu_addr_r, io.end_addr_r) @[el2_lsu_stbuf.scala 135:57] - node _T_265 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 135:64] - node _T_266 = mux(_T_265, io.lsu_addr_r, io.end_addr_r) @[el2_lsu_stbuf.scala 135:57] - stbuf_addrin[0] <= _T_266 @[el2_lsu_stbuf.scala 135:17] - stbuf_addrin[1] <= _T_264 @[el2_lsu_stbuf.scala 135:17] - stbuf_addrin[2] <= _T_262 @[el2_lsu_stbuf.scala 135:17] - stbuf_addrin[3] <= _T_260 @[el2_lsu_stbuf.scala 135:17] - node _T_267 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 136:66] - node _T_268 = or(stbuf_byteen[0], store_byteen_lo_r) @[el2_lsu_stbuf.scala 136:87] - node _T_269 = or(stbuf_byteen[0], store_byteen_hi_r) @[el2_lsu_stbuf.scala 136:124] - node _T_270 = mux(_T_267, _T_268, _T_269) @[el2_lsu_stbuf.scala 136:59] - node _T_271 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 136:66] - node _T_272 = or(stbuf_byteen[1], store_byteen_lo_r) @[el2_lsu_stbuf.scala 136:87] - node _T_273 = or(stbuf_byteen[1], store_byteen_hi_r) @[el2_lsu_stbuf.scala 136:124] - node _T_274 = mux(_T_271, _T_272, _T_273) @[el2_lsu_stbuf.scala 136:59] - node _T_275 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 136:66] - node _T_276 = or(stbuf_byteen[2], store_byteen_lo_r) @[el2_lsu_stbuf.scala 136:87] - node _T_277 = or(stbuf_byteen[2], store_byteen_hi_r) @[el2_lsu_stbuf.scala 136:124] - node _T_278 = mux(_T_275, _T_276, _T_277) @[el2_lsu_stbuf.scala 136:59] - node _T_279 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 136:66] - node _T_280 = or(stbuf_byteen[3], store_byteen_lo_r) @[el2_lsu_stbuf.scala 136:87] - node _T_281 = or(stbuf_byteen[3], store_byteen_hi_r) @[el2_lsu_stbuf.scala 136:124] - node _T_282 = mux(_T_279, _T_280, _T_281) @[el2_lsu_stbuf.scala 136:59] - stbuf_byteenin[0] <= _T_282 @[el2_lsu_stbuf.scala 136:19] - stbuf_byteenin[1] <= _T_278 @[el2_lsu_stbuf.scala 136:19] - stbuf_byteenin[2] <= _T_274 @[el2_lsu_stbuf.scala 136:19] - stbuf_byteenin[3] <= _T_270 @[el2_lsu_stbuf.scala 136:19] - node _T_283 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 138:59] - node _T_284 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 138:84] - node _T_285 = eq(_T_284, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:68] - node _T_286 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 138:107] - node _T_287 = or(_T_285, _T_286) @[el2_lsu_stbuf.scala 138:88] - node _T_288 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 138:132] - node _T_289 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 138:153] - node _T_290 = mux(_T_287, _T_288, _T_289) @[el2_lsu_stbuf.scala 138:67] - node _T_291 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 139:27] - node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:11] - node _T_293 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 139:50] - node _T_294 = or(_T_292, _T_293) @[el2_lsu_stbuf.scala 139:31] - node _T_295 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 139:75] - node _T_296 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 139:96] - node _T_297 = mux(_T_294, _T_295, _T_296) @[el2_lsu_stbuf.scala 139:10] - node _T_298 = mux(_T_283, _T_290, _T_297) @[el2_lsu_stbuf.scala 138:52] - node _T_299 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 138:59] - node _T_300 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 138:84] - node _T_301 = eq(_T_300, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:68] - node _T_302 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 138:107] - node _T_303 = or(_T_301, _T_302) @[el2_lsu_stbuf.scala 138:88] - node _T_304 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 138:132] - node _T_305 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 138:153] - node _T_306 = mux(_T_303, _T_304, _T_305) @[el2_lsu_stbuf.scala 138:67] - node _T_307 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 139:27] - node _T_308 = eq(_T_307, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:11] - node _T_309 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 139:50] - node _T_310 = or(_T_308, _T_309) @[el2_lsu_stbuf.scala 139:31] - node _T_311 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 139:75] - node _T_312 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 139:96] - node _T_313 = mux(_T_310, _T_311, _T_312) @[el2_lsu_stbuf.scala 139:10] - node _T_314 = mux(_T_299, _T_306, _T_313) @[el2_lsu_stbuf.scala 138:52] - node _T_315 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 138:59] - node _T_316 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 138:84] - node _T_317 = eq(_T_316, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:68] - node _T_318 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 138:107] - node _T_319 = or(_T_317, _T_318) @[el2_lsu_stbuf.scala 138:88] - node _T_320 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 138:132] - node _T_321 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 138:153] - node _T_322 = mux(_T_319, _T_320, _T_321) @[el2_lsu_stbuf.scala 138:67] - node _T_323 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 139:27] - node _T_324 = eq(_T_323, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:11] - node _T_325 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 139:50] - node _T_326 = or(_T_324, _T_325) @[el2_lsu_stbuf.scala 139:31] - node _T_327 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 139:75] - node _T_328 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 139:96] - node _T_329 = mux(_T_326, _T_327, _T_328) @[el2_lsu_stbuf.scala 139:10] - node _T_330 = mux(_T_315, _T_322, _T_329) @[el2_lsu_stbuf.scala 138:52] - node _T_331 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 138:59] - node _T_332 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 138:84] - node _T_333 = eq(_T_332, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:68] - node _T_334 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 138:107] - node _T_335 = or(_T_333, _T_334) @[el2_lsu_stbuf.scala 138:88] - node _T_336 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 138:132] - node _T_337 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 138:153] - node _T_338 = mux(_T_335, _T_336, _T_337) @[el2_lsu_stbuf.scala 138:67] - node _T_339 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 139:27] - node _T_340 = eq(_T_339, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:11] - node _T_341 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 139:50] - node _T_342 = or(_T_340, _T_341) @[el2_lsu_stbuf.scala 139:31] - node _T_343 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 139:75] - node _T_344 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 139:96] - node _T_345 = mux(_T_342, _T_343, _T_344) @[el2_lsu_stbuf.scala 139:10] - node _T_346 = mux(_T_331, _T_338, _T_345) @[el2_lsu_stbuf.scala 138:52] - datain1[0] <= _T_346 @[el2_lsu_stbuf.scala 138:12] - datain1[1] <= _T_330 @[el2_lsu_stbuf.scala 138:12] - datain1[2] <= _T_314 @[el2_lsu_stbuf.scala 138:12] - datain1[3] <= _T_298 @[el2_lsu_stbuf.scala 138:12] - node _T_347 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 141:60] - node _T_348 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 141:85] - node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_stbuf.scala 141:69] - node _T_350 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:108] - node _T_351 = or(_T_349, _T_350) @[el2_lsu_stbuf.scala 141:89] - node _T_352 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 141:133] - node _T_353 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 141:155] - node _T_354 = mux(_T_351, _T_352, _T_353) @[el2_lsu_stbuf.scala 141:68] - node _T_355 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 142:27] - node _T_356 = eq(_T_355, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:11] - node _T_357 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 142:50] - node _T_358 = or(_T_356, _T_357) @[el2_lsu_stbuf.scala 142:31] - node _T_359 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 142:75] - node _T_360 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 142:97] - node _T_361 = mux(_T_358, _T_359, _T_360) @[el2_lsu_stbuf.scala 142:10] - node _T_362 = mux(_T_347, _T_354, _T_361) @[el2_lsu_stbuf.scala 141:53] - node _T_363 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 141:60] - node _T_364 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 141:85] - node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_stbuf.scala 141:69] - node _T_366 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:108] - node _T_367 = or(_T_365, _T_366) @[el2_lsu_stbuf.scala 141:89] - node _T_368 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 141:133] - node _T_369 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 141:155] - node _T_370 = mux(_T_367, _T_368, _T_369) @[el2_lsu_stbuf.scala 141:68] - node _T_371 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 142:27] - node _T_372 = eq(_T_371, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:11] - node _T_373 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 142:50] - node _T_374 = or(_T_372, _T_373) @[el2_lsu_stbuf.scala 142:31] - node _T_375 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 142:75] - node _T_376 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 142:97] - node _T_377 = mux(_T_374, _T_375, _T_376) @[el2_lsu_stbuf.scala 142:10] - node _T_378 = mux(_T_363, _T_370, _T_377) @[el2_lsu_stbuf.scala 141:53] - node _T_379 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 141:60] - node _T_380 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 141:85] - node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_stbuf.scala 141:69] - node _T_382 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:108] - node _T_383 = or(_T_381, _T_382) @[el2_lsu_stbuf.scala 141:89] - node _T_384 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 141:133] - node _T_385 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 141:155] - node _T_386 = mux(_T_383, _T_384, _T_385) @[el2_lsu_stbuf.scala 141:68] - node _T_387 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 142:27] - node _T_388 = eq(_T_387, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:11] - node _T_389 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 142:50] - node _T_390 = or(_T_388, _T_389) @[el2_lsu_stbuf.scala 142:31] - node _T_391 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 142:75] - node _T_392 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 142:97] - node _T_393 = mux(_T_390, _T_391, _T_392) @[el2_lsu_stbuf.scala 142:10] - node _T_394 = mux(_T_379, _T_386, _T_393) @[el2_lsu_stbuf.scala 141:53] - node _T_395 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 141:60] - node _T_396 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 141:85] - node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_stbuf.scala 141:69] - node _T_398 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:108] - node _T_399 = or(_T_397, _T_398) @[el2_lsu_stbuf.scala 141:89] - node _T_400 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 141:133] - node _T_401 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 141:155] - node _T_402 = mux(_T_399, _T_400, _T_401) @[el2_lsu_stbuf.scala 141:68] - node _T_403 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 142:27] - node _T_404 = eq(_T_403, UInt<1>("h00")) @[el2_lsu_stbuf.scala 142:11] - node _T_405 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 142:50] - node _T_406 = or(_T_404, _T_405) @[el2_lsu_stbuf.scala 142:31] - node _T_407 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 142:75] - node _T_408 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 142:97] - node _T_409 = mux(_T_406, _T_407, _T_408) @[el2_lsu_stbuf.scala 142:10] - node _T_410 = mux(_T_395, _T_402, _T_409) @[el2_lsu_stbuf.scala 141:53] - datain2[0] <= _T_410 @[el2_lsu_stbuf.scala 141:13] - datain2[1] <= _T_394 @[el2_lsu_stbuf.scala 141:13] - datain2[2] <= _T_378 @[el2_lsu_stbuf.scala 141:13] - datain2[3] <= _T_362 @[el2_lsu_stbuf.scala 141:13] - node _T_411 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 144:60] - node _T_412 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 144:85] - node _T_413 = eq(_T_412, UInt<1>("h00")) @[el2_lsu_stbuf.scala 144:69] - node _T_414 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 144:108] - node _T_415 = or(_T_413, _T_414) @[el2_lsu_stbuf.scala 144:89] - node _T_416 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 144:133] - node _T_417 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 144:156] - node _T_418 = mux(_T_415, _T_416, _T_417) @[el2_lsu_stbuf.scala 144:68] - node _T_419 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 145:27] - node _T_420 = eq(_T_419, UInt<1>("h00")) @[el2_lsu_stbuf.scala 145:11] - node _T_421 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 145:50] - node _T_422 = or(_T_420, _T_421) @[el2_lsu_stbuf.scala 145:31] - node _T_423 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 145:75] - node _T_424 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 145:98] - node _T_425 = mux(_T_422, _T_423, _T_424) @[el2_lsu_stbuf.scala 145:10] - node _T_426 = mux(_T_411, _T_418, _T_425) @[el2_lsu_stbuf.scala 144:53] - node _T_427 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 144:60] - node _T_428 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 144:85] - node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_lsu_stbuf.scala 144:69] - node _T_430 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 144:108] - node _T_431 = or(_T_429, _T_430) @[el2_lsu_stbuf.scala 144:89] - node _T_432 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 144:133] - node _T_433 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 144:156] - node _T_434 = mux(_T_431, _T_432, _T_433) @[el2_lsu_stbuf.scala 144:68] - node _T_435 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 145:27] - node _T_436 = eq(_T_435, UInt<1>("h00")) @[el2_lsu_stbuf.scala 145:11] - node _T_437 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 145:50] - node _T_438 = or(_T_436, _T_437) @[el2_lsu_stbuf.scala 145:31] - node _T_439 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 145:75] - node _T_440 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 145:98] - node _T_441 = mux(_T_438, _T_439, _T_440) @[el2_lsu_stbuf.scala 145:10] - node _T_442 = mux(_T_427, _T_434, _T_441) @[el2_lsu_stbuf.scala 144:53] - node _T_443 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 144:60] - node _T_444 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 144:85] - node _T_445 = eq(_T_444, UInt<1>("h00")) @[el2_lsu_stbuf.scala 144:69] - node _T_446 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 144:108] - node _T_447 = or(_T_445, _T_446) @[el2_lsu_stbuf.scala 144:89] - node _T_448 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 144:133] - node _T_449 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 144:156] - node _T_450 = mux(_T_447, _T_448, _T_449) @[el2_lsu_stbuf.scala 144:68] - node _T_451 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 145:27] - node _T_452 = eq(_T_451, UInt<1>("h00")) @[el2_lsu_stbuf.scala 145:11] - node _T_453 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 145:50] - node _T_454 = or(_T_452, _T_453) @[el2_lsu_stbuf.scala 145:31] - node _T_455 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 145:75] - node _T_456 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 145:98] - node _T_457 = mux(_T_454, _T_455, _T_456) @[el2_lsu_stbuf.scala 145:10] - node _T_458 = mux(_T_443, _T_450, _T_457) @[el2_lsu_stbuf.scala 144:53] - node _T_459 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 144:60] - node _T_460 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 144:85] - node _T_461 = eq(_T_460, UInt<1>("h00")) @[el2_lsu_stbuf.scala 144:69] - node _T_462 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 144:108] - node _T_463 = or(_T_461, _T_462) @[el2_lsu_stbuf.scala 144:89] - node _T_464 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 144:133] - node _T_465 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 144:156] - node _T_466 = mux(_T_463, _T_464, _T_465) @[el2_lsu_stbuf.scala 144:68] - node _T_467 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 145:27] - node _T_468 = eq(_T_467, UInt<1>("h00")) @[el2_lsu_stbuf.scala 145:11] - node _T_469 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 145:50] - node _T_470 = or(_T_468, _T_469) @[el2_lsu_stbuf.scala 145:31] - node _T_471 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 145:75] - node _T_472 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 145:98] - node _T_473 = mux(_T_470, _T_471, _T_472) @[el2_lsu_stbuf.scala 145:10] - node _T_474 = mux(_T_459, _T_466, _T_473) @[el2_lsu_stbuf.scala 144:53] - datain3[0] <= _T_474 @[el2_lsu_stbuf.scala 144:13] - datain3[1] <= _T_458 @[el2_lsu_stbuf.scala 144:13] - datain3[2] <= _T_442 @[el2_lsu_stbuf.scala 144:13] - datain3[3] <= _T_426 @[el2_lsu_stbuf.scala 144:13] - node _T_475 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 147:60] - node _T_476 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 147:85] - node _T_477 = eq(_T_476, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:69] - node _T_478 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 147:108] - node _T_479 = or(_T_477, _T_478) @[el2_lsu_stbuf.scala 147:89] - node _T_480 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 147:133] - node _T_481 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 147:156] - node _T_482 = mux(_T_479, _T_480, _T_481) @[el2_lsu_stbuf.scala 147:68] - node _T_483 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 148:27] - node _T_484 = eq(_T_483, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:11] - node _T_485 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 148:50] - node _T_486 = or(_T_484, _T_485) @[el2_lsu_stbuf.scala 148:31] - node _T_487 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 148:75] - node _T_488 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 148:98] - node _T_489 = mux(_T_486, _T_487, _T_488) @[el2_lsu_stbuf.scala 148:10] - node _T_490 = mux(_T_475, _T_482, _T_489) @[el2_lsu_stbuf.scala 147:53] - node _T_491 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 147:60] - node _T_492 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 147:85] - node _T_493 = eq(_T_492, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:69] - node _T_494 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 147:108] - node _T_495 = or(_T_493, _T_494) @[el2_lsu_stbuf.scala 147:89] - node _T_496 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 147:133] - node _T_497 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 147:156] - node _T_498 = mux(_T_495, _T_496, _T_497) @[el2_lsu_stbuf.scala 147:68] - node _T_499 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 148:27] - node _T_500 = eq(_T_499, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:11] - node _T_501 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 148:50] - node _T_502 = or(_T_500, _T_501) @[el2_lsu_stbuf.scala 148:31] - node _T_503 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 148:75] - node _T_504 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 148:98] - node _T_505 = mux(_T_502, _T_503, _T_504) @[el2_lsu_stbuf.scala 148:10] - node _T_506 = mux(_T_491, _T_498, _T_505) @[el2_lsu_stbuf.scala 147:53] - node _T_507 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 147:60] - node _T_508 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 147:85] - node _T_509 = eq(_T_508, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:69] - node _T_510 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 147:108] - node _T_511 = or(_T_509, _T_510) @[el2_lsu_stbuf.scala 147:89] - node _T_512 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 147:133] - node _T_513 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 147:156] - node _T_514 = mux(_T_511, _T_512, _T_513) @[el2_lsu_stbuf.scala 147:68] - node _T_515 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 148:27] - node _T_516 = eq(_T_515, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:11] - node _T_517 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 148:50] - node _T_518 = or(_T_516, _T_517) @[el2_lsu_stbuf.scala 148:31] - node _T_519 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 148:75] - node _T_520 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 148:98] - node _T_521 = mux(_T_518, _T_519, _T_520) @[el2_lsu_stbuf.scala 148:10] - node _T_522 = mux(_T_507, _T_514, _T_521) @[el2_lsu_stbuf.scala 147:53] - node _T_523 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 147:60] - node _T_524 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 147:85] - node _T_525 = eq(_T_524, UInt<1>("h00")) @[el2_lsu_stbuf.scala 147:69] - node _T_526 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 147:108] - node _T_527 = or(_T_525, _T_526) @[el2_lsu_stbuf.scala 147:89] - node _T_528 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 147:133] - node _T_529 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 147:156] - node _T_530 = mux(_T_527, _T_528, _T_529) @[el2_lsu_stbuf.scala 147:68] - node _T_531 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 148:27] - node _T_532 = eq(_T_531, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:11] - node _T_533 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 148:50] - node _T_534 = or(_T_532, _T_533) @[el2_lsu_stbuf.scala 148:31] - node _T_535 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 148:75] - node _T_536 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 148:98] - node _T_537 = mux(_T_534, _T_535, _T_536) @[el2_lsu_stbuf.scala 148:10] - node _T_538 = mux(_T_523, _T_530, _T_537) @[el2_lsu_stbuf.scala 147:53] - datain4[0] <= _T_538 @[el2_lsu_stbuf.scala 147:13] - datain4[1] <= _T_522 @[el2_lsu_stbuf.scala 147:13] - datain4[2] <= _T_506 @[el2_lsu_stbuf.scala 147:13] - datain4[3] <= _T_490 @[el2_lsu_stbuf.scala 147:13] - node _T_539 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] - node _T_540 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] - node _T_541 = cat(_T_540, _T_539) @[Cat.scala 29:58] - node _T_542 = cat(datain2[1], datain1[1]) @[Cat.scala 29:58] - node _T_543 = cat(datain4[1], datain3[1]) @[Cat.scala 29:58] - node _T_544 = cat(_T_543, _T_542) @[Cat.scala 29:58] - node _T_545 = cat(datain2[2], datain1[2]) @[Cat.scala 29:58] - node _T_546 = cat(datain4[2], datain3[2]) @[Cat.scala 29:58] + node store_byteen_lo_r = and(_T_18, _T_20) @[el2_lsu_stbuf.scala 123:52] + node _T_21 = add(RdPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 125:26] + node RdPtrPlus1 = tail(_T_21, 1) @[el2_lsu_stbuf.scala 125:26] + node _T_22 = add(WrPtr, UInt<1>("h01")) @[el2_lsu_stbuf.scala 126:26] + node WrPtrPlus1 = tail(_T_22, 1) @[el2_lsu_stbuf.scala 126:26] + node _T_23 = add(WrPtr, UInt<2>("h02")) @[el2_lsu_stbuf.scala 127:26] + node WrPtrPlus2 = tail(_T_23, 1) @[el2_lsu_stbuf.scala 127:26] + node _T_24 = and(io.lsu_commit_r, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 129:45] + io.ldst_stbuf_reqvld_r <= _T_24 @[el2_lsu_stbuf.scala 129:26] + node _T_25 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_26 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_27 = eq(_T_25, _T_26) @[el2_lsu_stbuf.scala 131:120] + node _T_28 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 131:191] + node _T_29 = and(_T_27, _T_28) @[el2_lsu_stbuf.scala 131:179] + node _T_30 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 131:212] + node _T_31 = eq(_T_30, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] + node _T_32 = and(_T_29, _T_31) @[el2_lsu_stbuf.scala 131:195] + node _T_33 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 131:230] + node _T_34 = eq(_T_33, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] + node _T_35 = and(_T_32, _T_34) @[el2_lsu_stbuf.scala 131:216] + node _T_36 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_37 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_38 = eq(_T_36, _T_37) @[el2_lsu_stbuf.scala 131:120] + node _T_39 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 131:191] + node _T_40 = and(_T_38, _T_39) @[el2_lsu_stbuf.scala 131:179] + node _T_41 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 131:212] + node _T_42 = eq(_T_41, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] + node _T_43 = and(_T_40, _T_42) @[el2_lsu_stbuf.scala 131:195] + node _T_44 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 131:230] + node _T_45 = eq(_T_44, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] + node _T_46 = and(_T_43, _T_45) @[el2_lsu_stbuf.scala 131:216] + node _T_47 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_48 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_49 = eq(_T_47, _T_48) @[el2_lsu_stbuf.scala 131:120] + node _T_50 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 131:191] + node _T_51 = and(_T_49, _T_50) @[el2_lsu_stbuf.scala 131:179] + node _T_52 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 131:212] + node _T_53 = eq(_T_52, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] + node _T_54 = and(_T_51, _T_53) @[el2_lsu_stbuf.scala 131:195] + node _T_55 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 131:230] + node _T_56 = eq(_T_55, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] + node _T_57 = and(_T_54, _T_56) @[el2_lsu_stbuf.scala 131:216] + node _T_58 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 131:78] + node _T_59 = bits(io.lsu_addr_r, 15, 2) @[el2_lsu_stbuf.scala 131:137] + node _T_60 = eq(_T_58, _T_59) @[el2_lsu_stbuf.scala 131:120] + node _T_61 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 131:191] + node _T_62 = and(_T_60, _T_61) @[el2_lsu_stbuf.scala 131:179] + node _T_63 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 131:212] + node _T_64 = eq(_T_63, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:197] + node _T_65 = and(_T_62, _T_64) @[el2_lsu_stbuf.scala 131:195] + node _T_66 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 131:230] + node _T_67 = eq(_T_66, UInt<1>("h00")) @[el2_lsu_stbuf.scala 131:218] + node _T_68 = and(_T_65, _T_67) @[el2_lsu_stbuf.scala 131:216] + node _T_69 = cat(_T_68, _T_57) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_46) @[Cat.scala 29:58] + node store_matchvec_lo_r = cat(_T_70, _T_35) @[Cat.scala 29:58] + node _T_71 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 132:78] + node _T_72 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] + node _T_73 = eq(_T_71, _T_72) @[el2_lsu_stbuf.scala 132:120] + node _T_74 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 132:190] + node _T_75 = and(_T_73, _T_74) @[el2_lsu_stbuf.scala 132:179] + node _T_76 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 132:211] + node _T_77 = eq(_T_76, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] + node _T_78 = and(_T_75, _T_77) @[el2_lsu_stbuf.scala 132:194] + node _T_79 = and(_T_78, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] + node _T_80 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 132:250] + node _T_81 = eq(_T_80, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] + node _T_82 = and(_T_79, _T_81) @[el2_lsu_stbuf.scala 132:236] + node _T_83 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 132:78] + node _T_84 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] + node _T_85 = eq(_T_83, _T_84) @[el2_lsu_stbuf.scala 132:120] + node _T_86 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 132:190] + node _T_87 = and(_T_85, _T_86) @[el2_lsu_stbuf.scala 132:179] + node _T_88 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 132:211] + node _T_89 = eq(_T_88, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] + node _T_90 = and(_T_87, _T_89) @[el2_lsu_stbuf.scala 132:194] + node _T_91 = and(_T_90, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] + node _T_92 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 132:250] + node _T_93 = eq(_T_92, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] + node _T_94 = and(_T_91, _T_93) @[el2_lsu_stbuf.scala 132:236] + node _T_95 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 132:78] + node _T_96 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] + node _T_97 = eq(_T_95, _T_96) @[el2_lsu_stbuf.scala 132:120] + node _T_98 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 132:190] + node _T_99 = and(_T_97, _T_98) @[el2_lsu_stbuf.scala 132:179] + node _T_100 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 132:211] + node _T_101 = eq(_T_100, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] + node _T_102 = and(_T_99, _T_101) @[el2_lsu_stbuf.scala 132:194] + node _T_103 = and(_T_102, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] + node _T_104 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 132:250] + node _T_105 = eq(_T_104, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] + node _T_106 = and(_T_103, _T_105) @[el2_lsu_stbuf.scala 132:236] + node _T_107 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 132:78] + node _T_108 = bits(io.end_addr_r, 15, 2) @[el2_lsu_stbuf.scala 132:137] + node _T_109 = eq(_T_107, _T_108) @[el2_lsu_stbuf.scala 132:120] + node _T_110 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 132:190] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_stbuf.scala 132:179] + node _T_112 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 132:211] + node _T_113 = eq(_T_112, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:196] + node _T_114 = and(_T_111, _T_113) @[el2_lsu_stbuf.scala 132:194] + node _T_115 = and(_T_114, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 132:215] + node _T_116 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 132:250] + node _T_117 = eq(_T_116, UInt<1>("h00")) @[el2_lsu_stbuf.scala 132:238] + node _T_118 = and(_T_115, _T_117) @[el2_lsu_stbuf.scala 132:236] + node _T_119 = cat(_T_118, _T_106) @[Cat.scala 29:58] + node _T_120 = cat(_T_119, _T_94) @[Cat.scala 29:58] + node store_matchvec_hi_r = cat(_T_120, _T_82) @[Cat.scala 29:58] + node store_coalesce_lo_r = orr(store_matchvec_lo_r) @[el2_lsu_stbuf.scala 134:49] + node store_coalesce_hi_r = orr(store_matchvec_hi_r) @[el2_lsu_stbuf.scala 135:49] + node _T_121 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 138:16] + node _T_122 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:29] + node _T_123 = and(_T_121, _T_122) @[el2_lsu_stbuf.scala 138:27] + node _T_124 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 139:18] + node _T_125 = and(_T_124, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:29] + node _T_126 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:52] + node _T_127 = and(_T_125, _T_126) @[el2_lsu_stbuf.scala 139:50] + node _T_128 = or(_T_123, _T_127) @[el2_lsu_stbuf.scala 138:51] + node _T_129 = eq(UInt<1>("h00"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:18] + node _T_130 = and(_T_129, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:34] + node _T_131 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:79] + node _T_132 = eq(_T_131, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:57] + node _T_133 = and(_T_130, _T_132) @[el2_lsu_stbuf.scala 140:55] + node _T_134 = or(_T_128, _T_133) @[el2_lsu_stbuf.scala 139:74] + node _T_135 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 141:26] + node _T_136 = or(_T_134, _T_135) @[el2_lsu_stbuf.scala 140:103] + node _T_137 = bits(store_matchvec_hi_r, 0, 0) @[el2_lsu_stbuf.scala 141:51] + node _T_138 = or(_T_136, _T_137) @[el2_lsu_stbuf.scala 141:30] + node _T_139 = and(io.ldst_stbuf_reqvld_r, _T_138) @[el2_lsu_stbuf.scala 137:76] + node _T_140 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 138:16] + node _T_141 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:29] + node _T_142 = and(_T_140, _T_141) @[el2_lsu_stbuf.scala 138:27] + node _T_143 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 139:18] + node _T_144 = and(_T_143, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:29] + node _T_145 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:52] + node _T_146 = and(_T_144, _T_145) @[el2_lsu_stbuf.scala 139:50] + node _T_147 = or(_T_142, _T_146) @[el2_lsu_stbuf.scala 138:51] + node _T_148 = eq(UInt<1>("h01"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:18] + node _T_149 = and(_T_148, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:34] + node _T_150 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:79] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:57] + node _T_152 = and(_T_149, _T_151) @[el2_lsu_stbuf.scala 140:55] + node _T_153 = or(_T_147, _T_152) @[el2_lsu_stbuf.scala 139:74] + node _T_154 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 141:26] + node _T_155 = or(_T_153, _T_154) @[el2_lsu_stbuf.scala 140:103] + node _T_156 = bits(store_matchvec_hi_r, 1, 1) @[el2_lsu_stbuf.scala 141:51] + node _T_157 = or(_T_155, _T_156) @[el2_lsu_stbuf.scala 141:30] + node _T_158 = and(io.ldst_stbuf_reqvld_r, _T_157) @[el2_lsu_stbuf.scala 137:76] + node _T_159 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 138:16] + node _T_160 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:29] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_stbuf.scala 138:27] + node _T_162 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 139:18] + node _T_163 = and(_T_162, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:29] + node _T_164 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:52] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_stbuf.scala 139:50] + node _T_166 = or(_T_161, _T_165) @[el2_lsu_stbuf.scala 138:51] + node _T_167 = eq(UInt<2>("h02"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:18] + node _T_168 = and(_T_167, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:34] + node _T_169 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:79] + node _T_170 = eq(_T_169, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:57] + node _T_171 = and(_T_168, _T_170) @[el2_lsu_stbuf.scala 140:55] + node _T_172 = or(_T_166, _T_171) @[el2_lsu_stbuf.scala 139:74] + node _T_173 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 141:26] + node _T_174 = or(_T_172, _T_173) @[el2_lsu_stbuf.scala 140:103] + node _T_175 = bits(store_matchvec_hi_r, 2, 2) @[el2_lsu_stbuf.scala 141:51] + node _T_176 = or(_T_174, _T_175) @[el2_lsu_stbuf.scala 141:30] + node _T_177 = and(io.ldst_stbuf_reqvld_r, _T_176) @[el2_lsu_stbuf.scala 137:76] + node _T_178 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 138:16] + node _T_179 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 138:29] + node _T_180 = and(_T_178, _T_179) @[el2_lsu_stbuf.scala 138:27] + node _T_181 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 139:18] + node _T_182 = and(_T_181, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 139:29] + node _T_183 = eq(store_coalesce_hi_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 139:52] + node _T_184 = and(_T_182, _T_183) @[el2_lsu_stbuf.scala 139:50] + node _T_185 = or(_T_180, _T_184) @[el2_lsu_stbuf.scala 138:51] + node _T_186 = eq(UInt<2>("h03"), WrPtrPlus1) @[el2_lsu_stbuf.scala 140:18] + node _T_187 = and(_T_186, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 140:34] + node _T_188 = or(store_coalesce_lo_r, store_coalesce_hi_r) @[el2_lsu_stbuf.scala 140:79] + node _T_189 = eq(_T_188, UInt<1>("h00")) @[el2_lsu_stbuf.scala 140:57] + node _T_190 = and(_T_187, _T_189) @[el2_lsu_stbuf.scala 140:55] + node _T_191 = or(_T_185, _T_190) @[el2_lsu_stbuf.scala 139:74] + node _T_192 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 141:26] + node _T_193 = or(_T_191, _T_192) @[el2_lsu_stbuf.scala 140:103] + node _T_194 = bits(store_matchvec_hi_r, 3, 3) @[el2_lsu_stbuf.scala 141:51] + node _T_195 = or(_T_193, _T_194) @[el2_lsu_stbuf.scala 141:30] + node _T_196 = and(io.ldst_stbuf_reqvld_r, _T_195) @[el2_lsu_stbuf.scala 137:76] + node _T_197 = cat(_T_196, _T_177) @[Cat.scala 29:58] + node _T_198 = cat(_T_197, _T_158) @[Cat.scala 29:58] + node _T_199 = cat(_T_198, _T_139) @[Cat.scala 29:58] + stbuf_wr_en <= _T_199 @[el2_lsu_stbuf.scala 137:15] + node _T_200 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] + node _T_201 = eq(UInt<1>("h00"), RdPtr) @[el2_lsu_stbuf.scala 142:121] + node _T_202 = bits(_T_201, 0, 0) @[el2_lsu_stbuf.scala 142:132] + node _T_203 = and(_T_200, _T_202) @[el2_lsu_stbuf.scala 142:109] + node _T_204 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] + node _T_205 = eq(UInt<1>("h01"), RdPtr) @[el2_lsu_stbuf.scala 142:121] + node _T_206 = bits(_T_205, 0, 0) @[el2_lsu_stbuf.scala 142:132] + node _T_207 = and(_T_204, _T_206) @[el2_lsu_stbuf.scala 142:109] + node _T_208 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] + node _T_209 = eq(UInt<2>("h02"), RdPtr) @[el2_lsu_stbuf.scala 142:121] + node _T_210 = bits(_T_209, 0, 0) @[el2_lsu_stbuf.scala 142:132] + node _T_211 = and(_T_208, _T_210) @[el2_lsu_stbuf.scala 142:109] + node _T_212 = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 142:78] + node _T_213 = eq(UInt<2>("h03"), RdPtr) @[el2_lsu_stbuf.scala 142:121] + node _T_214 = bits(_T_213, 0, 0) @[el2_lsu_stbuf.scala 142:132] + node _T_215 = and(_T_212, _T_214) @[el2_lsu_stbuf.scala 142:109] + node _T_216 = cat(_T_215, _T_211) @[Cat.scala 29:58] + node _T_217 = cat(_T_216, _T_207) @[Cat.scala 29:58] + node _T_218 = cat(_T_217, _T_203) @[Cat.scala 29:58] + stbuf_reset <= _T_218 @[el2_lsu_stbuf.scala 142:15] + node _T_219 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] + node _T_220 = or(_T_219, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] + node _T_221 = eq(UInt<1>("h00"), WrPtr) @[el2_lsu_stbuf.scala 143:105] + node _T_222 = bits(_T_221, 0, 0) @[el2_lsu_stbuf.scala 143:116] + node _T_223 = and(_T_220, _T_222) @[el2_lsu_stbuf.scala 143:93] + node _T_224 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] + node _T_225 = and(_T_223, _T_224) @[el2_lsu_stbuf.scala 143:123] + node _T_226 = bits(store_matchvec_lo_r, 0, 0) @[el2_lsu_stbuf.scala 143:168] + node _T_227 = or(_T_225, _T_226) @[el2_lsu_stbuf.scala 143:147] + node _T_228 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] + node _T_229 = or(_T_228, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] + node _T_230 = eq(UInt<1>("h01"), WrPtr) @[el2_lsu_stbuf.scala 143:105] + node _T_231 = bits(_T_230, 0, 0) @[el2_lsu_stbuf.scala 143:116] + node _T_232 = and(_T_229, _T_231) @[el2_lsu_stbuf.scala 143:93] + node _T_233 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] + node _T_234 = and(_T_232, _T_233) @[el2_lsu_stbuf.scala 143:123] + node _T_235 = bits(store_matchvec_lo_r, 1, 1) @[el2_lsu_stbuf.scala 143:168] + node _T_236 = or(_T_234, _T_235) @[el2_lsu_stbuf.scala 143:147] + node _T_237 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] + node _T_238 = or(_T_237, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] + node _T_239 = eq(UInt<2>("h02"), WrPtr) @[el2_lsu_stbuf.scala 143:105] + node _T_240 = bits(_T_239, 0, 0) @[el2_lsu_stbuf.scala 143:116] + node _T_241 = and(_T_238, _T_240) @[el2_lsu_stbuf.scala 143:93] + node _T_242 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] + node _T_243 = and(_T_241, _T_242) @[el2_lsu_stbuf.scala 143:123] + node _T_244 = bits(store_matchvec_lo_r, 2, 2) @[el2_lsu_stbuf.scala 143:168] + node _T_245 = or(_T_243, _T_244) @[el2_lsu_stbuf.scala 143:147] + node _T_246 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:53] + node _T_247 = or(_T_246, io.store_stbuf_reqvld_r) @[el2_lsu_stbuf.scala 143:66] + node _T_248 = eq(UInt<2>("h03"), WrPtr) @[el2_lsu_stbuf.scala 143:105] + node _T_249 = bits(_T_248, 0, 0) @[el2_lsu_stbuf.scala 143:116] + node _T_250 = and(_T_247, _T_249) @[el2_lsu_stbuf.scala 143:93] + node _T_251 = eq(store_coalesce_lo_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 143:125] + node _T_252 = and(_T_250, _T_251) @[el2_lsu_stbuf.scala 143:123] + node _T_253 = bits(store_matchvec_lo_r, 3, 3) @[el2_lsu_stbuf.scala 143:168] + node _T_254 = or(_T_252, _T_253) @[el2_lsu_stbuf.scala 143:147] + node _T_255 = cat(_T_254, _T_245) @[Cat.scala 29:58] + node _T_256 = cat(_T_255, _T_236) @[Cat.scala 29:58] + node sel_lo = cat(_T_256, _T_227) @[Cat.scala 29:58] + node _T_257 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 145:63] + node _T_258 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:81] + node _T_259 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:113] + node _T_260 = mux(_T_257, _T_258, _T_259) @[el2_lsu_stbuf.scala 145:56] + node _T_261 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 145:63] + node _T_262 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:81] + node _T_263 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:113] + node _T_264 = mux(_T_261, _T_262, _T_263) @[el2_lsu_stbuf.scala 145:56] + node _T_265 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 145:63] + node _T_266 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:81] + node _T_267 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:113] + node _T_268 = mux(_T_265, _T_266, _T_267) @[el2_lsu_stbuf.scala 145:56] + node _T_269 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 145:63] + node _T_270 = bits(io.lsu_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:81] + node _T_271 = bits(io.end_addr_r, 15, 0) @[el2_lsu_stbuf.scala 145:113] + node _T_272 = mux(_T_269, _T_270, _T_271) @[el2_lsu_stbuf.scala 145:56] + stbuf_addrin[0] <= _T_260 @[el2_lsu_stbuf.scala 145:16] + stbuf_addrin[1] <= _T_264 @[el2_lsu_stbuf.scala 145:16] + stbuf_addrin[2] <= _T_268 @[el2_lsu_stbuf.scala 145:16] + stbuf_addrin[3] <= _T_272 @[el2_lsu_stbuf.scala 145:16] + node _T_273 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 146:65] + node _T_274 = or(stbuf_byteen[0], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:86] + node _T_275 = or(stbuf_byteen[0], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:123] + node _T_276 = mux(_T_273, _T_274, _T_275) @[el2_lsu_stbuf.scala 146:58] + node _T_277 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 146:65] + node _T_278 = or(stbuf_byteen[1], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:86] + node _T_279 = or(stbuf_byteen[1], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:123] + node _T_280 = mux(_T_277, _T_278, _T_279) @[el2_lsu_stbuf.scala 146:58] + node _T_281 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 146:65] + node _T_282 = or(stbuf_byteen[2], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:86] + node _T_283 = or(stbuf_byteen[2], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:123] + node _T_284 = mux(_T_281, _T_282, _T_283) @[el2_lsu_stbuf.scala 146:58] + node _T_285 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 146:65] + node _T_286 = or(stbuf_byteen[3], store_byteen_lo_r) @[el2_lsu_stbuf.scala 146:86] + node _T_287 = or(stbuf_byteen[3], store_byteen_hi_r) @[el2_lsu_stbuf.scala 146:123] + node _T_288 = mux(_T_285, _T_286, _T_287) @[el2_lsu_stbuf.scala 146:58] + stbuf_byteenin[0] <= _T_276 @[el2_lsu_stbuf.scala 146:18] + stbuf_byteenin[1] <= _T_280 @[el2_lsu_stbuf.scala 146:18] + stbuf_byteenin[2] <= _T_284 @[el2_lsu_stbuf.scala 146:18] + stbuf_byteenin[3] <= _T_288 @[el2_lsu_stbuf.scala 146:18] + node _T_289 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 148:58] + node _T_290 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 148:83] + node _T_291 = eq(_T_290, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:67] + node _T_292 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:106] + node _T_293 = or(_T_291, _T_292) @[el2_lsu_stbuf.scala 148:87] + node _T_294 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:131] + node _T_295 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 148:152] + node _T_296 = mux(_T_293, _T_294, _T_295) @[el2_lsu_stbuf.scala 148:66] + node _T_297 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 149:25] + node _T_298 = eq(_T_297, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:9] + node _T_299 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:48] + node _T_300 = or(_T_298, _T_299) @[el2_lsu_stbuf.scala 149:29] + node _T_301 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:73] + node _T_302 = bits(stbuf_data[0], 7, 0) @[el2_lsu_stbuf.scala 149:94] + node _T_303 = mux(_T_300, _T_301, _T_302) @[el2_lsu_stbuf.scala 149:8] + node _T_304 = mux(_T_289, _T_296, _T_303) @[el2_lsu_stbuf.scala 148:51] + node _T_305 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 148:58] + node _T_306 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 148:83] + node _T_307 = eq(_T_306, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:67] + node _T_308 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:106] + node _T_309 = or(_T_307, _T_308) @[el2_lsu_stbuf.scala 148:87] + node _T_310 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:131] + node _T_311 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 148:152] + node _T_312 = mux(_T_309, _T_310, _T_311) @[el2_lsu_stbuf.scala 148:66] + node _T_313 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 149:25] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:9] + node _T_315 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:48] + node _T_316 = or(_T_314, _T_315) @[el2_lsu_stbuf.scala 149:29] + node _T_317 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:73] + node _T_318 = bits(stbuf_data[1], 7, 0) @[el2_lsu_stbuf.scala 149:94] + node _T_319 = mux(_T_316, _T_317, _T_318) @[el2_lsu_stbuf.scala 149:8] + node _T_320 = mux(_T_305, _T_312, _T_319) @[el2_lsu_stbuf.scala 148:51] + node _T_321 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 148:58] + node _T_322 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 148:83] + node _T_323 = eq(_T_322, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:67] + node _T_324 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:106] + node _T_325 = or(_T_323, _T_324) @[el2_lsu_stbuf.scala 148:87] + node _T_326 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:131] + node _T_327 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 148:152] + node _T_328 = mux(_T_325, _T_326, _T_327) @[el2_lsu_stbuf.scala 148:66] + node _T_329 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 149:25] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:9] + node _T_331 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:48] + node _T_332 = or(_T_330, _T_331) @[el2_lsu_stbuf.scala 149:29] + node _T_333 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:73] + node _T_334 = bits(stbuf_data[2], 7, 0) @[el2_lsu_stbuf.scala 149:94] + node _T_335 = mux(_T_332, _T_333, _T_334) @[el2_lsu_stbuf.scala 149:8] + node _T_336 = mux(_T_321, _T_328, _T_335) @[el2_lsu_stbuf.scala 148:51] + node _T_337 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 148:58] + node _T_338 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 148:83] + node _T_339 = eq(_T_338, UInt<1>("h00")) @[el2_lsu_stbuf.scala 148:67] + node _T_340 = bits(store_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 148:106] + node _T_341 = or(_T_339, _T_340) @[el2_lsu_stbuf.scala 148:87] + node _T_342 = bits(io.store_datafn_lo_r, 7, 0) @[el2_lsu_stbuf.scala 148:131] + node _T_343 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 148:152] + node _T_344 = mux(_T_341, _T_342, _T_343) @[el2_lsu_stbuf.scala 148:66] + node _T_345 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 149:25] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_stbuf.scala 149:9] + node _T_347 = bits(store_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 149:48] + node _T_348 = or(_T_346, _T_347) @[el2_lsu_stbuf.scala 149:29] + node _T_349 = bits(io.store_datafn_hi_r, 7, 0) @[el2_lsu_stbuf.scala 149:73] + node _T_350 = bits(stbuf_data[3], 7, 0) @[el2_lsu_stbuf.scala 149:94] + node _T_351 = mux(_T_348, _T_349, _T_350) @[el2_lsu_stbuf.scala 149:8] + node _T_352 = mux(_T_337, _T_344, _T_351) @[el2_lsu_stbuf.scala 148:51] + datain1[0] <= _T_304 @[el2_lsu_stbuf.scala 148:11] + datain1[1] <= _T_320 @[el2_lsu_stbuf.scala 148:11] + datain1[2] <= _T_336 @[el2_lsu_stbuf.scala 148:11] + datain1[3] <= _T_352 @[el2_lsu_stbuf.scala 148:11] + node _T_353 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 151:59] + node _T_354 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 151:84] + node _T_355 = eq(_T_354, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:68] + node _T_356 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:107] + node _T_357 = or(_T_355, _T_356) @[el2_lsu_stbuf.scala 151:88] + node _T_358 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:132] + node _T_359 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 151:154] + node _T_360 = mux(_T_357, _T_358, _T_359) @[el2_lsu_stbuf.scala 151:67] + node _T_361 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 152:25] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:9] + node _T_363 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:48] + node _T_364 = or(_T_362, _T_363) @[el2_lsu_stbuf.scala 152:29] + node _T_365 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:73] + node _T_366 = bits(stbuf_data[0], 15, 8) @[el2_lsu_stbuf.scala 152:95] + node _T_367 = mux(_T_364, _T_365, _T_366) @[el2_lsu_stbuf.scala 152:8] + node _T_368 = mux(_T_353, _T_360, _T_367) @[el2_lsu_stbuf.scala 151:52] + node _T_369 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 151:59] + node _T_370 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 151:84] + node _T_371 = eq(_T_370, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:68] + node _T_372 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:107] + node _T_373 = or(_T_371, _T_372) @[el2_lsu_stbuf.scala 151:88] + node _T_374 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:132] + node _T_375 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 151:154] + node _T_376 = mux(_T_373, _T_374, _T_375) @[el2_lsu_stbuf.scala 151:67] + node _T_377 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 152:25] + node _T_378 = eq(_T_377, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:9] + node _T_379 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:48] + node _T_380 = or(_T_378, _T_379) @[el2_lsu_stbuf.scala 152:29] + node _T_381 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:73] + node _T_382 = bits(stbuf_data[1], 15, 8) @[el2_lsu_stbuf.scala 152:95] + node _T_383 = mux(_T_380, _T_381, _T_382) @[el2_lsu_stbuf.scala 152:8] + node _T_384 = mux(_T_369, _T_376, _T_383) @[el2_lsu_stbuf.scala 151:52] + node _T_385 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 151:59] + node _T_386 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 151:84] + node _T_387 = eq(_T_386, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:68] + node _T_388 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:107] + node _T_389 = or(_T_387, _T_388) @[el2_lsu_stbuf.scala 151:88] + node _T_390 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:132] + node _T_391 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 151:154] + node _T_392 = mux(_T_389, _T_390, _T_391) @[el2_lsu_stbuf.scala 151:67] + node _T_393 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 152:25] + node _T_394 = eq(_T_393, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:9] + node _T_395 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:48] + node _T_396 = or(_T_394, _T_395) @[el2_lsu_stbuf.scala 152:29] + node _T_397 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:73] + node _T_398 = bits(stbuf_data[2], 15, 8) @[el2_lsu_stbuf.scala 152:95] + node _T_399 = mux(_T_396, _T_397, _T_398) @[el2_lsu_stbuf.scala 152:8] + node _T_400 = mux(_T_385, _T_392, _T_399) @[el2_lsu_stbuf.scala 151:52] + node _T_401 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 151:59] + node _T_402 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 151:84] + node _T_403 = eq(_T_402, UInt<1>("h00")) @[el2_lsu_stbuf.scala 151:68] + node _T_404 = bits(store_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 151:107] + node _T_405 = or(_T_403, _T_404) @[el2_lsu_stbuf.scala 151:88] + node _T_406 = bits(io.store_datafn_lo_r, 15, 8) @[el2_lsu_stbuf.scala 151:132] + node _T_407 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 151:154] + node _T_408 = mux(_T_405, _T_406, _T_407) @[el2_lsu_stbuf.scala 151:67] + node _T_409 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 152:25] + node _T_410 = eq(_T_409, UInt<1>("h00")) @[el2_lsu_stbuf.scala 152:9] + node _T_411 = bits(store_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 152:48] + node _T_412 = or(_T_410, _T_411) @[el2_lsu_stbuf.scala 152:29] + node _T_413 = bits(io.store_datafn_hi_r, 15, 8) @[el2_lsu_stbuf.scala 152:73] + node _T_414 = bits(stbuf_data[3], 15, 8) @[el2_lsu_stbuf.scala 152:95] + node _T_415 = mux(_T_412, _T_413, _T_414) @[el2_lsu_stbuf.scala 152:8] + node _T_416 = mux(_T_401, _T_408, _T_415) @[el2_lsu_stbuf.scala 151:52] + datain2[0] <= _T_368 @[el2_lsu_stbuf.scala 151:12] + datain2[1] <= _T_384 @[el2_lsu_stbuf.scala 151:12] + datain2[2] <= _T_400 @[el2_lsu_stbuf.scala 151:12] + datain2[3] <= _T_416 @[el2_lsu_stbuf.scala 151:12] + node _T_417 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 154:59] + node _T_418 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 154:84] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:68] + node _T_420 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:107] + node _T_421 = or(_T_419, _T_420) @[el2_lsu_stbuf.scala 154:88] + node _T_422 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:132] + node _T_423 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 154:155] + node _T_424 = mux(_T_421, _T_422, _T_423) @[el2_lsu_stbuf.scala 154:67] + node _T_425 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 155:25] + node _T_426 = eq(_T_425, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:9] + node _T_427 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:48] + node _T_428 = or(_T_426, _T_427) @[el2_lsu_stbuf.scala 155:29] + node _T_429 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:73] + node _T_430 = bits(stbuf_data[0], 23, 16) @[el2_lsu_stbuf.scala 155:96] + node _T_431 = mux(_T_428, _T_429, _T_430) @[el2_lsu_stbuf.scala 155:8] + node _T_432 = mux(_T_417, _T_424, _T_431) @[el2_lsu_stbuf.scala 154:52] + node _T_433 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 154:59] + node _T_434 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 154:84] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:68] + node _T_436 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:107] + node _T_437 = or(_T_435, _T_436) @[el2_lsu_stbuf.scala 154:88] + node _T_438 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:132] + node _T_439 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 154:155] + node _T_440 = mux(_T_437, _T_438, _T_439) @[el2_lsu_stbuf.scala 154:67] + node _T_441 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 155:25] + node _T_442 = eq(_T_441, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:9] + node _T_443 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:48] + node _T_444 = or(_T_442, _T_443) @[el2_lsu_stbuf.scala 155:29] + node _T_445 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:73] + node _T_446 = bits(stbuf_data[1], 23, 16) @[el2_lsu_stbuf.scala 155:96] + node _T_447 = mux(_T_444, _T_445, _T_446) @[el2_lsu_stbuf.scala 155:8] + node _T_448 = mux(_T_433, _T_440, _T_447) @[el2_lsu_stbuf.scala 154:52] + node _T_449 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 154:59] + node _T_450 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 154:84] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:68] + node _T_452 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:107] + node _T_453 = or(_T_451, _T_452) @[el2_lsu_stbuf.scala 154:88] + node _T_454 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:132] + node _T_455 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 154:155] + node _T_456 = mux(_T_453, _T_454, _T_455) @[el2_lsu_stbuf.scala 154:67] + node _T_457 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 155:25] + node _T_458 = eq(_T_457, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:9] + node _T_459 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:48] + node _T_460 = or(_T_458, _T_459) @[el2_lsu_stbuf.scala 155:29] + node _T_461 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:73] + node _T_462 = bits(stbuf_data[2], 23, 16) @[el2_lsu_stbuf.scala 155:96] + node _T_463 = mux(_T_460, _T_461, _T_462) @[el2_lsu_stbuf.scala 155:8] + node _T_464 = mux(_T_449, _T_456, _T_463) @[el2_lsu_stbuf.scala 154:52] + node _T_465 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 154:59] + node _T_466 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 154:84] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:68] + node _T_468 = bits(store_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 154:107] + node _T_469 = or(_T_467, _T_468) @[el2_lsu_stbuf.scala 154:88] + node _T_470 = bits(io.store_datafn_lo_r, 23, 16) @[el2_lsu_stbuf.scala 154:132] + node _T_471 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 154:155] + node _T_472 = mux(_T_469, _T_470, _T_471) @[el2_lsu_stbuf.scala 154:67] + node _T_473 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 155:25] + node _T_474 = eq(_T_473, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:9] + node _T_475 = bits(store_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 155:48] + node _T_476 = or(_T_474, _T_475) @[el2_lsu_stbuf.scala 155:29] + node _T_477 = bits(io.store_datafn_hi_r, 23, 16) @[el2_lsu_stbuf.scala 155:73] + node _T_478 = bits(stbuf_data[3], 23, 16) @[el2_lsu_stbuf.scala 155:96] + node _T_479 = mux(_T_476, _T_477, _T_478) @[el2_lsu_stbuf.scala 155:8] + node _T_480 = mux(_T_465, _T_472, _T_479) @[el2_lsu_stbuf.scala 154:52] + datain3[0] <= _T_432 @[el2_lsu_stbuf.scala 154:12] + datain3[1] <= _T_448 @[el2_lsu_stbuf.scala 154:12] + datain3[2] <= _T_464 @[el2_lsu_stbuf.scala 154:12] + datain3[3] <= _T_480 @[el2_lsu_stbuf.scala 154:12] + node _T_481 = bits(sel_lo, 0, 0) @[el2_lsu_stbuf.scala 157:59] + node _T_482 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 157:84] + node _T_483 = eq(_T_482, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:68] + node _T_484 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:107] + node _T_485 = or(_T_483, _T_484) @[el2_lsu_stbuf.scala 157:88] + node _T_486 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:132] + node _T_487 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 157:155] + node _T_488 = mux(_T_485, _T_486, _T_487) @[el2_lsu_stbuf.scala 157:67] + node _T_489 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 158:25] + node _T_490 = eq(_T_489, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:9] + node _T_491 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:48] + node _T_492 = or(_T_490, _T_491) @[el2_lsu_stbuf.scala 158:29] + node _T_493 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:73] + node _T_494 = bits(stbuf_data[0], 31, 24) @[el2_lsu_stbuf.scala 158:96] + node _T_495 = mux(_T_492, _T_493, _T_494) @[el2_lsu_stbuf.scala 158:8] + node _T_496 = mux(_T_481, _T_488, _T_495) @[el2_lsu_stbuf.scala 157:52] + node _T_497 = bits(sel_lo, 1, 1) @[el2_lsu_stbuf.scala 157:59] + node _T_498 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 157:84] + node _T_499 = eq(_T_498, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:68] + node _T_500 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:107] + node _T_501 = or(_T_499, _T_500) @[el2_lsu_stbuf.scala 157:88] + node _T_502 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:132] + node _T_503 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 157:155] + node _T_504 = mux(_T_501, _T_502, _T_503) @[el2_lsu_stbuf.scala 157:67] + node _T_505 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 158:25] + node _T_506 = eq(_T_505, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:9] + node _T_507 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:48] + node _T_508 = or(_T_506, _T_507) @[el2_lsu_stbuf.scala 158:29] + node _T_509 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:73] + node _T_510 = bits(stbuf_data[1], 31, 24) @[el2_lsu_stbuf.scala 158:96] + node _T_511 = mux(_T_508, _T_509, _T_510) @[el2_lsu_stbuf.scala 158:8] + node _T_512 = mux(_T_497, _T_504, _T_511) @[el2_lsu_stbuf.scala 157:52] + node _T_513 = bits(sel_lo, 2, 2) @[el2_lsu_stbuf.scala 157:59] + node _T_514 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 157:84] + node _T_515 = eq(_T_514, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:68] + node _T_516 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:107] + node _T_517 = or(_T_515, _T_516) @[el2_lsu_stbuf.scala 157:88] + node _T_518 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:132] + node _T_519 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 157:155] + node _T_520 = mux(_T_517, _T_518, _T_519) @[el2_lsu_stbuf.scala 157:67] + node _T_521 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 158:25] + node _T_522 = eq(_T_521, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:9] + node _T_523 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:48] + node _T_524 = or(_T_522, _T_523) @[el2_lsu_stbuf.scala 158:29] + node _T_525 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:73] + node _T_526 = bits(stbuf_data[2], 31, 24) @[el2_lsu_stbuf.scala 158:96] + node _T_527 = mux(_T_524, _T_525, _T_526) @[el2_lsu_stbuf.scala 158:8] + node _T_528 = mux(_T_513, _T_520, _T_527) @[el2_lsu_stbuf.scala 157:52] + node _T_529 = bits(sel_lo, 3, 3) @[el2_lsu_stbuf.scala 157:59] + node _T_530 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 157:84] + node _T_531 = eq(_T_530, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:68] + node _T_532 = bits(store_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 157:107] + node _T_533 = or(_T_531, _T_532) @[el2_lsu_stbuf.scala 157:88] + node _T_534 = bits(io.store_datafn_lo_r, 31, 24) @[el2_lsu_stbuf.scala 157:132] + node _T_535 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 157:155] + node _T_536 = mux(_T_533, _T_534, _T_535) @[el2_lsu_stbuf.scala 157:67] + node _T_537 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 158:25] + node _T_538 = eq(_T_537, UInt<1>("h00")) @[el2_lsu_stbuf.scala 158:9] + node _T_539 = bits(store_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 158:48] + node _T_540 = or(_T_538, _T_539) @[el2_lsu_stbuf.scala 158:29] + node _T_541 = bits(io.store_datafn_hi_r, 31, 24) @[el2_lsu_stbuf.scala 158:73] + node _T_542 = bits(stbuf_data[3], 31, 24) @[el2_lsu_stbuf.scala 158:96] + node _T_543 = mux(_T_540, _T_541, _T_542) @[el2_lsu_stbuf.scala 158:8] + node _T_544 = mux(_T_529, _T_536, _T_543) @[el2_lsu_stbuf.scala 157:52] + datain4[0] <= _T_496 @[el2_lsu_stbuf.scala 157:12] + datain4[1] <= _T_512 @[el2_lsu_stbuf.scala 157:12] + datain4[2] <= _T_528 @[el2_lsu_stbuf.scala 157:12] + datain4[3] <= _T_544 @[el2_lsu_stbuf.scala 157:12] + node _T_545 = cat(datain2[0], datain1[0]) @[Cat.scala 29:58] + node _T_546 = cat(datain4[0], datain3[0]) @[Cat.scala 29:58] node _T_547 = cat(_T_546, _T_545) @[Cat.scala 29:58] - node _T_548 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] - node _T_549 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] + node _T_548 = cat(datain2[1], datain1[1]) @[Cat.scala 29:58] + node _T_549 = cat(datain4[1], datain3[1]) @[Cat.scala 29:58] node _T_550 = cat(_T_549, _T_548) @[Cat.scala 29:58] - stbuf_datain[0] <= _T_541 @[el2_lsu_stbuf.scala 150:17] - stbuf_datain[1] <= _T_544 @[el2_lsu_stbuf.scala 150:17] - stbuf_datain[2] <= _T_547 @[el2_lsu_stbuf.scala 150:17] - stbuf_datain[3] <= _T_550 @[el2_lsu_stbuf.scala 150:17] - node _T_551 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 154:82] - node _T_552 = eq(_T_551, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:70] - node _T_553 = and(UInt<1>("h01"), _T_552) @[el2_lsu_stbuf.scala 154:68] - node _T_554 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 154:103] - reg _T_555 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_554 : @[Reg.scala 28:19] - _T_555 <= _T_553 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_vld[0] <= _T_555 @[el2_lsu_stbuf.scala 154:51] - node _T_556 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 155:87] - node _T_557 = eq(_T_556, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:75] - node _T_558 = and(UInt<1>("h01"), _T_557) @[el2_lsu_stbuf.scala 155:73] - node _T_559 = bits(stbuf_dma_kill_en, 0, 0) @[el2_lsu_stbuf.scala 155:114] - node _T_560 = bits(_T_559, 0, 0) @[el2_lsu_stbuf.scala 155:118] - reg _T_561 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_560 : @[Reg.scala 28:19] - _T_561 <= _T_558 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_dma_kill[0] <= _T_561 @[el2_lsu_stbuf.scala 155:56] - node _T_562 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 156:67] - reg _T_563 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_562 : @[Reg.scala 28:19] - _T_563 <= stbuf_addrin[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_addr[0] <= _T_563 @[el2_lsu_stbuf.scala 156:21] - node _T_564 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 157:134] - node _T_565 = eq(_T_564, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:122] - node _T_566 = bits(_T_565, 0, 0) @[Bitwise.scala 72:15] - node _T_567 = mux(_T_566, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_568 = and(stbuf_byteenin[0], _T_567) @[el2_lsu_stbuf.scala 157:87] - node _T_569 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 157:156] - reg _T_570 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_569 : @[Reg.scala 28:19] - _T_570 <= _T_568 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_byteen[0] <= _T_570 @[el2_lsu_stbuf.scala 157:55] - node _T_571 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 158:67] - reg _T_572 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_571 : @[Reg.scala 28:19] - _T_572 <= stbuf_datain[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_data[0] <= _T_572 @[el2_lsu_stbuf.scala 158:21] - node _T_573 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 154:82] - node _T_574 = eq(_T_573, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:70] - node _T_575 = and(UInt<1>("h01"), _T_574) @[el2_lsu_stbuf.scala 154:68] - node _T_576 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 154:103] - reg _T_577 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_576 : @[Reg.scala 28:19] - _T_577 <= _T_575 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_vld[1] <= _T_577 @[el2_lsu_stbuf.scala 154:51] - node _T_578 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 155:87] - node _T_579 = eq(_T_578, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:75] - node _T_580 = and(UInt<1>("h01"), _T_579) @[el2_lsu_stbuf.scala 155:73] - node _T_581 = bits(stbuf_dma_kill_en, 1, 1) @[el2_lsu_stbuf.scala 155:114] - node _T_582 = bits(_T_581, 0, 0) @[el2_lsu_stbuf.scala 155:118] - reg _T_583 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_582 : @[Reg.scala 28:19] - _T_583 <= _T_580 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_dma_kill[1] <= _T_583 @[el2_lsu_stbuf.scala 155:56] - node _T_584 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 156:67] - reg _T_585 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_584 : @[Reg.scala 28:19] - _T_585 <= stbuf_addrin[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_addr[1] <= _T_585 @[el2_lsu_stbuf.scala 156:21] - node _T_586 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 157:134] - node _T_587 = eq(_T_586, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:122] - node _T_588 = bits(_T_587, 0, 0) @[Bitwise.scala 72:15] - node _T_589 = mux(_T_588, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_590 = and(stbuf_byteenin[1], _T_589) @[el2_lsu_stbuf.scala 157:87] - node _T_591 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 157:156] - reg _T_592 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_591 : @[Reg.scala 28:19] - _T_592 <= _T_590 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_byteen[1] <= _T_592 @[el2_lsu_stbuf.scala 157:55] - node _T_593 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 158:67] - reg _T_594 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_593 : @[Reg.scala 28:19] - _T_594 <= stbuf_datain[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_data[1] <= _T_594 @[el2_lsu_stbuf.scala 158:21] - node _T_595 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 154:82] - node _T_596 = eq(_T_595, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:70] - node _T_597 = and(UInt<1>("h01"), _T_596) @[el2_lsu_stbuf.scala 154:68] - node _T_598 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 154:103] - reg _T_599 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_598 : @[Reg.scala 28:19] - _T_599 <= _T_597 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_vld[2] <= _T_599 @[el2_lsu_stbuf.scala 154:51] - node _T_600 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 155:87] - node _T_601 = eq(_T_600, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:75] - node _T_602 = and(UInt<1>("h01"), _T_601) @[el2_lsu_stbuf.scala 155:73] - node _T_603 = bits(stbuf_dma_kill_en, 2, 2) @[el2_lsu_stbuf.scala 155:114] - node _T_604 = bits(_T_603, 0, 0) @[el2_lsu_stbuf.scala 155:118] - reg _T_605 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_604 : @[Reg.scala 28:19] - _T_605 <= _T_602 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_dma_kill[2] <= _T_605 @[el2_lsu_stbuf.scala 155:56] - node _T_606 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 156:67] - reg _T_607 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_606 : @[Reg.scala 28:19] - _T_607 <= stbuf_addrin[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_addr[2] <= _T_607 @[el2_lsu_stbuf.scala 156:21] - node _T_608 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 157:134] - node _T_609 = eq(_T_608, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:122] - node _T_610 = bits(_T_609, 0, 0) @[Bitwise.scala 72:15] - node _T_611 = mux(_T_610, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_612 = and(stbuf_byteenin[2], _T_611) @[el2_lsu_stbuf.scala 157:87] - node _T_613 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 157:156] - reg _T_614 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_613 : @[Reg.scala 28:19] - _T_614 <= _T_612 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_byteen[2] <= _T_614 @[el2_lsu_stbuf.scala 157:55] - node _T_615 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 158:67] - reg _T_616 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_615 : @[Reg.scala 28:19] - _T_616 <= stbuf_datain[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_data[2] <= _T_616 @[el2_lsu_stbuf.scala 158:21] - node _T_617 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 154:82] - node _T_618 = eq(_T_617, UInt<1>("h00")) @[el2_lsu_stbuf.scala 154:70] - node _T_619 = and(UInt<1>("h01"), _T_618) @[el2_lsu_stbuf.scala 154:68] - node _T_620 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 154:103] - reg _T_621 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_620 : @[Reg.scala 28:19] - _T_621 <= _T_619 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_vld[3] <= _T_621 @[el2_lsu_stbuf.scala 154:51] - node _T_622 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 155:87] - node _T_623 = eq(_T_622, UInt<1>("h00")) @[el2_lsu_stbuf.scala 155:75] - node _T_624 = and(UInt<1>("h01"), _T_623) @[el2_lsu_stbuf.scala 155:73] - node _T_625 = bits(stbuf_dma_kill_en, 3, 3) @[el2_lsu_stbuf.scala 155:114] - node _T_626 = bits(_T_625, 0, 0) @[el2_lsu_stbuf.scala 155:118] - reg _T_627 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_626 : @[Reg.scala 28:19] - _T_627 <= _T_624 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_dma_kill[3] <= _T_627 @[el2_lsu_stbuf.scala 155:56] - node _T_628 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 156:67] - reg _T_629 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_628 : @[Reg.scala 28:19] - _T_629 <= stbuf_addrin[3] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - stbuf_addr[3] <= _T_629 @[el2_lsu_stbuf.scala 156:21] - node _T_630 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 157:134] - node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_lsu_stbuf.scala 157:122] + node _T_551 = cat(datain2[2], datain1[2]) @[Cat.scala 29:58] + node _T_552 = cat(datain4[2], datain3[2]) @[Cat.scala 29:58] + node _T_553 = cat(_T_552, _T_551) @[Cat.scala 29:58] + node _T_554 = cat(datain2[3], datain1[3]) @[Cat.scala 29:58] + node _T_555 = cat(datain4[3], datain3[3]) @[Cat.scala 29:58] + node _T_556 = cat(_T_555, _T_554) @[Cat.scala 29:58] + stbuf_datain[0] <= _T_547 @[el2_lsu_stbuf.scala 160:16] + stbuf_datain[1] <= _T_550 @[el2_lsu_stbuf.scala 160:16] + stbuf_datain[2] <= _T_553 @[el2_lsu_stbuf.scala 160:16] + stbuf_datain[3] <= _T_556 @[el2_lsu_stbuf.scala 160:16] + node _T_557 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 164:104] + node _T_558 = bits(_T_557, 0, 0) @[el2_lsu_stbuf.scala 164:114] + node _T_559 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 164:131] + node _T_560 = mux(_T_558, UInt<1>("h01"), _T_559) @[el2_lsu_stbuf.scala 164:92] + node _T_561 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 164:150] + node _T_562 = eq(_T_561, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] + node _T_563 = and(_T_560, _T_562) @[el2_lsu_stbuf.scala 164:136] + reg _T_564 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] + _T_564 <= _T_563 @[el2_lsu_stbuf.scala 164:88] + node _T_565 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 164:104] + node _T_566 = bits(_T_565, 0, 0) @[el2_lsu_stbuf.scala 164:114] + node _T_567 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 164:131] + node _T_568 = mux(_T_566, UInt<1>("h01"), _T_567) @[el2_lsu_stbuf.scala 164:92] + node _T_569 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 164:150] + node _T_570 = eq(_T_569, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] + node _T_571 = and(_T_568, _T_570) @[el2_lsu_stbuf.scala 164:136] + reg _T_572 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] + _T_572 <= _T_571 @[el2_lsu_stbuf.scala 164:88] + node _T_573 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 164:104] + node _T_574 = bits(_T_573, 0, 0) @[el2_lsu_stbuf.scala 164:114] + node _T_575 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 164:131] + node _T_576 = mux(_T_574, UInt<1>("h01"), _T_575) @[el2_lsu_stbuf.scala 164:92] + node _T_577 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 164:150] + node _T_578 = eq(_T_577, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] + node _T_579 = and(_T_576, _T_578) @[el2_lsu_stbuf.scala 164:136] + reg _T_580 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] + _T_580 <= _T_579 @[el2_lsu_stbuf.scala 164:88] + node _T_581 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 164:104] + node _T_582 = bits(_T_581, 0, 0) @[el2_lsu_stbuf.scala 164:114] + node _T_583 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 164:131] + node _T_584 = mux(_T_582, UInt<1>("h01"), _T_583) @[el2_lsu_stbuf.scala 164:92] + node _T_585 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 164:150] + node _T_586 = eq(_T_585, UInt<1>("h00")) @[el2_lsu_stbuf.scala 164:138] + node _T_587 = and(_T_584, _T_586) @[el2_lsu_stbuf.scala 164:136] + reg _T_588 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 164:88] + _T_588 <= _T_587 @[el2_lsu_stbuf.scala 164:88] + node _T_589 = cat(_T_588, _T_580) @[Cat.scala 29:58] + node _T_590 = cat(_T_589, _T_572) @[Cat.scala 29:58] + node _T_591 = cat(_T_590, _T_564) @[Cat.scala 29:58] + stbuf_vld <= _T_591 @[el2_lsu_stbuf.scala 164:13] + node _T_592 = bits(stbuf_dma_kill_en, 0, 0) @[el2_lsu_stbuf.scala 166:114] + node _T_593 = bits(_T_592, 0, 0) @[el2_lsu_stbuf.scala 166:118] + node _T_594 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 166:144] + node _T_595 = mux(_T_593, UInt<1>("h01"), _T_594) @[el2_lsu_stbuf.scala 166:96] + node _T_596 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 166:163] + node _T_597 = eq(_T_596, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:151] + node _T_598 = and(_T_595, _T_597) @[el2_lsu_stbuf.scala 166:149] + reg _T_599 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:92] + _T_599 <= _T_598 @[el2_lsu_stbuf.scala 166:92] + node _T_600 = bits(stbuf_dma_kill_en, 1, 1) @[el2_lsu_stbuf.scala 166:114] + node _T_601 = bits(_T_600, 0, 0) @[el2_lsu_stbuf.scala 166:118] + node _T_602 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 166:144] + node _T_603 = mux(_T_601, UInt<1>("h01"), _T_602) @[el2_lsu_stbuf.scala 166:96] + node _T_604 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 166:163] + node _T_605 = eq(_T_604, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:151] + node _T_606 = and(_T_603, _T_605) @[el2_lsu_stbuf.scala 166:149] + reg _T_607 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:92] + _T_607 <= _T_606 @[el2_lsu_stbuf.scala 166:92] + node _T_608 = bits(stbuf_dma_kill_en, 2, 2) @[el2_lsu_stbuf.scala 166:114] + node _T_609 = bits(_T_608, 0, 0) @[el2_lsu_stbuf.scala 166:118] + node _T_610 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 166:144] + node _T_611 = mux(_T_609, UInt<1>("h01"), _T_610) @[el2_lsu_stbuf.scala 166:96] + node _T_612 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 166:163] + node _T_613 = eq(_T_612, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:151] + node _T_614 = and(_T_611, _T_613) @[el2_lsu_stbuf.scala 166:149] + reg _T_615 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:92] + _T_615 <= _T_614 @[el2_lsu_stbuf.scala 166:92] + node _T_616 = bits(stbuf_dma_kill_en, 3, 3) @[el2_lsu_stbuf.scala 166:114] + node _T_617 = bits(_T_616, 0, 0) @[el2_lsu_stbuf.scala 166:118] + node _T_618 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 166:144] + node _T_619 = mux(_T_617, UInt<1>("h01"), _T_618) @[el2_lsu_stbuf.scala 166:96] + node _T_620 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 166:163] + node _T_621 = eq(_T_620, UInt<1>("h00")) @[el2_lsu_stbuf.scala 166:151] + node _T_622 = and(_T_619, _T_621) @[el2_lsu_stbuf.scala 166:149] + reg _T_623 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 166:92] + _T_623 <= _T_622 @[el2_lsu_stbuf.scala 166:92] + node _T_624 = cat(_T_623, _T_615) @[Cat.scala 29:58] + node _T_625 = cat(_T_624, _T_607) @[Cat.scala 29:58] + node _T_626 = cat(_T_625, _T_599) @[Cat.scala 29:58] + stbuf_dma_kill <= _T_626 @[el2_lsu_stbuf.scala 166:18] + node _T_627 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 167:108] + node _T_628 = bits(_T_627, 0, 0) @[el2_lsu_stbuf.scala 167:118] + node _T_629 = mux(_T_628, stbuf_byteenin[0], stbuf_byteen[0]) @[el2_lsu_stbuf.scala 167:96] + node _T_630 = bits(stbuf_reset, 0, 0) @[el2_lsu_stbuf.scala 167:206] + node _T_631 = eq(_T_630, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] node _T_632 = bits(_T_631, 0, 0) @[Bitwise.scala 72:15] node _T_633 = mux(_T_632, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_634 = and(stbuf_byteenin[3], _T_633) @[el2_lsu_stbuf.scala 157:87] - node _T_635 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 157:156] - reg _T_636 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_635 : @[Reg.scala 28:19] - _T_636 <= _T_634 @[Reg.scala 28:23] + node _T_634 = and(_T_629, _T_633) @[el2_lsu_stbuf.scala 167:158] + reg _T_635 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] + _T_635 <= _T_634 @[el2_lsu_stbuf.scala 167:92] + node _T_636 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 167:108] + node _T_637 = bits(_T_636, 0, 0) @[el2_lsu_stbuf.scala 167:118] + node _T_638 = mux(_T_637, stbuf_byteenin[1], stbuf_byteen[1]) @[el2_lsu_stbuf.scala 167:96] + node _T_639 = bits(stbuf_reset, 1, 1) @[el2_lsu_stbuf.scala 167:206] + node _T_640 = eq(_T_639, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_643 = and(_T_638, _T_642) @[el2_lsu_stbuf.scala 167:158] + reg _T_644 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] + _T_644 <= _T_643 @[el2_lsu_stbuf.scala 167:92] + node _T_645 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 167:108] + node _T_646 = bits(_T_645, 0, 0) @[el2_lsu_stbuf.scala 167:118] + node _T_647 = mux(_T_646, stbuf_byteenin[2], stbuf_byteen[2]) @[el2_lsu_stbuf.scala 167:96] + node _T_648 = bits(stbuf_reset, 2, 2) @[el2_lsu_stbuf.scala 167:206] + node _T_649 = eq(_T_648, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_650 = bits(_T_649, 0, 0) @[Bitwise.scala 72:15] + node _T_651 = mux(_T_650, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_652 = and(_T_647, _T_651) @[el2_lsu_stbuf.scala 167:158] + reg _T_653 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] + _T_653 <= _T_652 @[el2_lsu_stbuf.scala 167:92] + node _T_654 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 167:108] + node _T_655 = bits(_T_654, 0, 0) @[el2_lsu_stbuf.scala 167:118] + node _T_656 = mux(_T_655, stbuf_byteenin[3], stbuf_byteen[3]) @[el2_lsu_stbuf.scala 167:96] + node _T_657 = bits(stbuf_reset, 3, 3) @[el2_lsu_stbuf.scala 167:206] + node _T_658 = eq(_T_657, UInt<1>("h00")) @[el2_lsu_stbuf.scala 167:194] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_661 = and(_T_656, _T_660) @[el2_lsu_stbuf.scala 167:158] + reg _T_662 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 167:92] + _T_662 <= _T_661 @[el2_lsu_stbuf.scala 167:92] + stbuf_byteen[0] <= _T_635 @[el2_lsu_stbuf.scala 167:16] + stbuf_byteen[1] <= _T_644 @[el2_lsu_stbuf.scala 167:16] + stbuf_byteen[2] <= _T_653 @[el2_lsu_stbuf.scala 167:16] + stbuf_byteen[3] <= _T_662 @[el2_lsu_stbuf.scala 167:16] + node _T_663 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 172:56] + node _T_664 = bits(_T_663, 0, 0) @[el2_lsu_stbuf.scala 172:66] + inst rvclkhdr of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= _T_664 @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_665 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_665 <= stbuf_addrin[0] @[el2_lib.scala 514:16] + stbuf_addr[0] <= _T_665 @[el2_lsu_stbuf.scala 172:19] + node _T_666 = bits(stbuf_wr_en, 0, 0) @[el2_lsu_stbuf.scala 174:56] + node _T_667 = bits(_T_666, 0, 0) @[el2_lsu_stbuf.scala 174:66] + inst rvclkhdr_1 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= _T_667 @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_668 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_668 <= stbuf_datain[0] @[el2_lib.scala 514:16] + stbuf_data[0] <= _T_668 @[el2_lsu_stbuf.scala 174:19] + node _T_669 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 172:56] + node _T_670 = bits(_T_669, 0, 0) @[el2_lsu_stbuf.scala 172:66] + inst rvclkhdr_2 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= _T_670 @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_671 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_671 <= stbuf_addrin[1] @[el2_lib.scala 514:16] + stbuf_addr[1] <= _T_671 @[el2_lsu_stbuf.scala 172:19] + node _T_672 = bits(stbuf_wr_en, 1, 1) @[el2_lsu_stbuf.scala 174:56] + node _T_673 = bits(_T_672, 0, 0) @[el2_lsu_stbuf.scala 174:66] + inst rvclkhdr_3 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= _T_673 @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_674 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_674 <= stbuf_datain[1] @[el2_lib.scala 514:16] + stbuf_data[1] <= _T_674 @[el2_lsu_stbuf.scala 174:19] + node _T_675 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 172:56] + node _T_676 = bits(_T_675, 0, 0) @[el2_lsu_stbuf.scala 172:66] + inst rvclkhdr_4 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_676 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_677 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_677 <= stbuf_addrin[2] @[el2_lib.scala 514:16] + stbuf_addr[2] <= _T_677 @[el2_lsu_stbuf.scala 172:19] + node _T_678 = bits(stbuf_wr_en, 2, 2) @[el2_lsu_stbuf.scala 174:56] + node _T_679 = bits(_T_678, 0, 0) @[el2_lsu_stbuf.scala 174:66] + inst rvclkhdr_5 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_679 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_680 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_680 <= stbuf_datain[2] @[el2_lib.scala 514:16] + stbuf_data[2] <= _T_680 @[el2_lsu_stbuf.scala 174:19] + node _T_681 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 172:56] + node _T_682 = bits(_T_681, 0, 0) @[el2_lsu_stbuf.scala 172:66] + inst rvclkhdr_6 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_682 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_683 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_683 <= stbuf_addrin[3] @[el2_lib.scala 514:16] + stbuf_addr[3] <= _T_683 @[el2_lsu_stbuf.scala 172:19] + node _T_684 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 174:56] + node _T_685 = bits(_T_684, 0, 0) @[el2_lsu_stbuf.scala 174:66] + inst rvclkhdr_7 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_685 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_686 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_686 <= stbuf_datain[3] @[el2_lib.scala 514:16] + stbuf_data[3] <= _T_686 @[el2_lsu_stbuf.scala 174:19] + reg _T_687 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 176:52] + _T_687 <= ldst_dual_d @[el2_lsu_stbuf.scala 176:52] + ldst_dual_m <= _T_687 @[el2_lsu_stbuf.scala 176:42] + reg _T_688 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 177:52] + _T_688 <= ldst_dual_m @[el2_lsu_stbuf.scala 177:52] + ldst_dual_r <= _T_688 @[el2_lsu_stbuf.scala 177:42] + node _T_689 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 180:43] + node _T_690 = bits(_T_689, 0, 0) @[el2_lsu_stbuf.scala 180:43] + node _T_691 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 180:67] + node _T_692 = bits(_T_691, 0, 0) @[el2_lsu_stbuf.scala 180:67] + node _T_693 = and(_T_690, _T_692) @[el2_lsu_stbuf.scala 180:51] + io.stbuf_reqvld_flushed_any <= _T_693 @[el2_lsu_stbuf.scala 180:31] + node _T_694 = dshr(stbuf_vld, RdPtr) @[el2_lsu_stbuf.scala 181:36] + node _T_695 = bits(_T_694, 0, 0) @[el2_lsu_stbuf.scala 181:36] + node _T_696 = dshr(stbuf_dma_kill, RdPtr) @[el2_lsu_stbuf.scala 181:61] + node _T_697 = bits(_T_696, 0, 0) @[el2_lsu_stbuf.scala 181:61] + node _T_698 = eq(_T_697, UInt<1>("h00")) @[el2_lsu_stbuf.scala 181:46] + node _T_699 = and(_T_695, _T_698) @[el2_lsu_stbuf.scala 181:44] + node _T_700 = orr(stbuf_dma_kill_en) @[el2_lsu_stbuf.scala 181:91] + node _T_701 = eq(_T_700, UInt<1>("h00")) @[el2_lsu_stbuf.scala 181:71] + node _T_702 = and(_T_699, _T_701) @[el2_lsu_stbuf.scala 181:69] + io.stbuf_reqvld_any <= _T_702 @[el2_lsu_stbuf.scala 181:24] + io.stbuf_addr_any <= stbuf_addr[RdPtr] @[el2_lsu_stbuf.scala 182:22] + io.stbuf_data_any <= stbuf_data[RdPtr] @[el2_lsu_stbuf.scala 183:22] + node _T_703 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 185:44] + node _T_704 = and(io.ldst_stbuf_reqvld_r, _T_703) @[el2_lsu_stbuf.scala 185:42] + node _T_705 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 185:88] + node _T_706 = eq(_T_705, UInt<1>("h00")) @[el2_lsu_stbuf.scala 185:66] + node _T_707 = and(_T_704, _T_706) @[el2_lsu_stbuf.scala 185:64] + node _T_708 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 186:30] + node _T_709 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 186:76] + node _T_710 = eq(_T_709, UInt<1>("h00")) @[el2_lsu_stbuf.scala 186:54] + node _T_711 = and(_T_708, _T_710) @[el2_lsu_stbuf.scala 186:52] + node _T_712 = or(_T_707, _T_711) @[el2_lsu_stbuf.scala 185:113] + node WrPtrEn = bits(_T_712, 0, 0) @[el2_lsu_stbuf.scala 186:101] + node _T_713 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 187:46] + node _T_714 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 187:91] + node _T_715 = eq(_T_714, UInt<1>("h00")) @[el2_lsu_stbuf.scala 187:69] + node _T_716 = and(_T_713, _T_715) @[el2_lsu_stbuf.scala 187:67] + node _T_717 = bits(_T_716, 0, 0) @[el2_lsu_stbuf.scala 187:115] + node NxtWrPtr = mux(_T_717, WrPtrPlus2, WrPtrPlus1) @[el2_lsu_stbuf.scala 187:21] + node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 188:42] + reg _T_718 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when WrPtrEn : @[Reg.scala 28:19] + _T_718 <= NxtWrPtr @[Reg.scala 28:23] skip @[Reg.scala 28:19] - stbuf_byteen[3] <= _T_636 @[el2_lsu_stbuf.scala 157:55] - node _T_637 = bits(stbuf_wr_en, 3, 3) @[el2_lsu_stbuf.scala 158:67] - reg _T_638 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_637 : @[Reg.scala 28:19] - _T_638 <= stbuf_datain[3] @[Reg.scala 28:23] + WrPtr <= _T_718 @[el2_lsu_stbuf.scala 191:41] + reg _T_719 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when RdPtrEn : @[Reg.scala 28:19] + _T_719 <= RdPtrPlus1 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - stbuf_data[3] <= _T_638 @[el2_lsu_stbuf.scala 158:21] - reg _T_639 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 160:53] - _T_639 <= ldst_dual_d @[el2_lsu_stbuf.scala 160:53] - ldst_dual_m <= _T_639 @[el2_lsu_stbuf.scala 160:43] - reg _T_640 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_stbuf.scala 161:53] - _T_640 <= ldst_dual_m @[el2_lsu_stbuf.scala 161:53] - ldst_dual_r <= _T_640 @[el2_lsu_stbuf.scala 161:43] - node _T_641 = and(stbuf_vld[RdPtr], stbuf_dma_kill[RdPtr]) @[el2_lsu_stbuf.scala 164:52] - io.stbuf_reqvld_flushed_any <= _T_641 @[el2_lsu_stbuf.scala 164:32] - node _T_642 = eq(stbuf_dma_kill[RdPtr], UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:47] - node _T_643 = and(stbuf_vld[RdPtr], _T_642) @[el2_lsu_stbuf.scala 165:45] - node _T_644 = orr(stbuf_dma_kill_en) @[el2_lsu_stbuf.scala 165:91] - node _T_645 = eq(_T_644, UInt<1>("h00")) @[el2_lsu_stbuf.scala 165:72] - node _T_646 = and(_T_643, _T_645) @[el2_lsu_stbuf.scala 165:70] - io.stbuf_reqvld_any <= _T_646 @[el2_lsu_stbuf.scala 165:25] - io.stbuf_addr_any <= stbuf_addr[RdPtr] @[el2_lsu_stbuf.scala 166:23] - io.stbuf_data_any <= stbuf_data[RdPtr] @[el2_lsu_stbuf.scala 167:23] - node _T_647 = eq(dual_stbuf_write_r, UInt<1>("h00")) @[el2_lsu_stbuf.scala 169:45] - node _T_648 = and(io.ldst_stbuf_reqvld_r, _T_647) @[el2_lsu_stbuf.scala 169:43] - node _T_649 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 169:89] - node _T_650 = eq(_T_649, UInt<1>("h00")) @[el2_lsu_stbuf.scala 169:67] - node _T_651 = and(_T_648, _T_650) @[el2_lsu_stbuf.scala 169:65] - node _T_652 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 170:31] - node _T_653 = and(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 170:77] - node _T_654 = eq(_T_653, UInt<1>("h00")) @[el2_lsu_stbuf.scala 170:55] - node _T_655 = and(_T_652, _T_654) @[el2_lsu_stbuf.scala 170:53] - node _T_656 = or(_T_651, _T_655) @[el2_lsu_stbuf.scala 169:114] - node WrPtrEn = bits(_T_656, 0, 0) @[el2_lsu_stbuf.scala 170:102] - node _T_657 = and(io.ldst_stbuf_reqvld_r, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 171:47] - node _T_658 = or(store_coalesce_hi_r, store_coalesce_lo_r) @[el2_lsu_stbuf.scala 171:92] - node _T_659 = eq(_T_658, UInt<1>("h00")) @[el2_lsu_stbuf.scala 171:70] - node _T_660 = and(_T_657, _T_659) @[el2_lsu_stbuf.scala 171:68] - node _T_661 = bits(_T_660, 0, 0) @[el2_lsu_stbuf.scala 171:116] - node NxtWrPtr = mux(_T_661, WrPtrPlus2, WrPtrPlus1) @[el2_lsu_stbuf.scala 171:22] - node RdPtrEn = or(io.lsu_stbuf_commit_any, io.stbuf_reqvld_flushed_any) @[el2_lsu_stbuf.scala 172:43] - node _T_662 = cat(UInt<3>("h00"), stbuf_vld[0]) @[Cat.scala 29:58] - node _T_663 = cat(UInt<3>("h00"), stbuf_vld[1]) @[Cat.scala 29:58] - node _T_664 = cat(UInt<3>("h00"), stbuf_vld[2]) @[Cat.scala 29:58] - node _T_665 = cat(UInt<3>("h00"), stbuf_vld[3]) @[Cat.scala 29:58] - wire _T_666 : UInt<4>[4] @[el2_lsu_stbuf.scala 175:60] - _T_666[0] <= _T_662 @[el2_lsu_stbuf.scala 175:60] - _T_666[1] <= _T_663 @[el2_lsu_stbuf.scala 175:60] - _T_666[2] <= _T_664 @[el2_lsu_stbuf.scala 175:60] - _T_666[3] <= _T_665 @[el2_lsu_stbuf.scala 175:60] - node _T_667 = add(_T_666[0], _T_666[1]) @[el2_lsu_stbuf.scala 175:102] - node _T_668 = tail(_T_667, 1) @[el2_lsu_stbuf.scala 175:102] - node _T_669 = add(_T_668, _T_666[2]) @[el2_lsu_stbuf.scala 175:102] - node _T_670 = tail(_T_669, 1) @[el2_lsu_stbuf.scala 175:102] - node _T_671 = add(_T_670, _T_666[3]) @[el2_lsu_stbuf.scala 175:102] - node stbuf_numvld_any = tail(_T_671, 1) @[el2_lsu_stbuf.scala 175:102] - node _T_672 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 176:40] - node _T_673 = and(_T_672, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 176:61] - node _T_674 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 176:83] - node isdccmst_m = and(_T_673, _T_674) @[el2_lsu_stbuf.scala 176:81] - node _T_675 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 177:40] - node _T_676 = and(_T_675, io.addr_in_dccm_r) @[el2_lsu_stbuf.scala 177:61] - node _T_677 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 177:83] - node isdccmst_r = and(_T_676, _T_677) @[el2_lsu_stbuf.scala 177:81] - node _T_678 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] - node _T_679 = and(isdccmst_m, ldst_dual_m) @[el2_lsu_stbuf.scala 179:63] - node _T_680 = dshl(_T_678, _T_679) @[el2_lsu_stbuf.scala 179:48] - stbuf_specvld_m <= _T_680 @[el2_lsu_stbuf.scala 179:20] - node _T_681 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] - node _T_682 = and(isdccmst_r, ldst_dual_r) @[el2_lsu_stbuf.scala 180:63] - node _T_683 = dshl(_T_681, _T_682) @[el2_lsu_stbuf.scala 180:48] - stbuf_specvld_r <= _T_683 @[el2_lsu_stbuf.scala 180:20] - node _T_684 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] - node _T_685 = add(stbuf_numvld_any, _T_684) @[el2_lsu_stbuf.scala 181:45] - node _T_686 = tail(_T_685, 1) @[el2_lsu_stbuf.scala 181:45] - node _T_687 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] - node _T_688 = add(_T_686, _T_687) @[el2_lsu_stbuf.scala 181:79] - node stbuf_specvld_any = tail(_T_688, 1) @[el2_lsu_stbuf.scala 181:79] - node _T_689 = eq(ldst_dual_d, UInt<1>("h00")) @[el2_lsu_stbuf.scala 183:35] - node _T_690 = and(_T_689, io.dec_lsu_valid_raw_d) @[el2_lsu_stbuf.scala 183:48] - node _T_691 = bits(_T_690, 0, 0) @[el2_lsu_stbuf.scala 183:74] - node _T_692 = geq(stbuf_specvld_any, UInt<3>("h04")) @[el2_lsu_stbuf.scala 183:99] - node _T_693 = geq(stbuf_specvld_any, UInt<2>("h03")) @[el2_lsu_stbuf.scala 183:138] - node _T_694 = mux(_T_691, _T_692, _T_693) @[el2_lsu_stbuf.scala 183:33] - io.lsu_stbuf_full_any <= _T_694 @[el2_lsu_stbuf.scala 183:27] - node _T_695 = eq(stbuf_numvld_any, UInt<1>("h00")) @[el2_lsu_stbuf.scala 184:47] - io.lsu_stbuf_empty_any <= _T_695 @[el2_lsu_stbuf.scala 184:27] - node cmpen_hi_m = and(io.lsu_cmpen_m, ldst_dual_m) @[el2_lsu_stbuf.scala 186:37] - node _T_696 = bits(io.end_addr_m, 15, 2) @[el2_lsu_stbuf.scala 187:33] - cmpaddr_hi_m <= _T_696 @[el2_lsu_stbuf.scala 187:17] - node _T_697 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_stbuf.scala 190:34] - cmpaddr_lo_m <= _T_697 @[el2_lsu_stbuf.scala 190:18] - node _T_698 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 193:74] - node _T_699 = bits(cmpaddr_hi_m, 15, 2) @[el2_lsu_stbuf.scala 193:132] - node _T_700 = eq(_T_698, _T_699) @[el2_lsu_stbuf.scala 193:116] - node _T_701 = and(_T_700, stbuf_vld[0]) @[el2_lsu_stbuf.scala 193:175] - node _T_702 = eq(stbuf_dma_kill[0], UInt<1>("h00")) @[el2_lsu_stbuf.scala 193:192] - node _T_703 = and(_T_701, _T_702) @[el2_lsu_stbuf.scala 193:190] - node _T_704 = and(_T_703, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 193:211] - node _T_705 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 193:74] - node _T_706 = bits(cmpaddr_hi_m, 15, 2) @[el2_lsu_stbuf.scala 193:132] - node _T_707 = eq(_T_705, _T_706) @[el2_lsu_stbuf.scala 193:116] - node _T_708 = and(_T_707, stbuf_vld[1]) @[el2_lsu_stbuf.scala 193:175] - node _T_709 = eq(stbuf_dma_kill[1], UInt<1>("h00")) @[el2_lsu_stbuf.scala 193:192] - node _T_710 = and(_T_708, _T_709) @[el2_lsu_stbuf.scala 193:190] - node _T_711 = and(_T_710, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 193:211] - node _T_712 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 193:74] - node _T_713 = bits(cmpaddr_hi_m, 15, 2) @[el2_lsu_stbuf.scala 193:132] - node _T_714 = eq(_T_712, _T_713) @[el2_lsu_stbuf.scala 193:116] - node _T_715 = and(_T_714, stbuf_vld[2]) @[el2_lsu_stbuf.scala 193:175] - node _T_716 = eq(stbuf_dma_kill[2], UInt<1>("h00")) @[el2_lsu_stbuf.scala 193:192] - node _T_717 = and(_T_715, _T_716) @[el2_lsu_stbuf.scala 193:190] - node _T_718 = and(_T_717, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 193:211] - node _T_719 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 193:74] - node _T_720 = bits(cmpaddr_hi_m, 15, 2) @[el2_lsu_stbuf.scala 193:132] - node _T_721 = eq(_T_719, _T_720) @[el2_lsu_stbuf.scala 193:116] - node _T_722 = and(_T_721, stbuf_vld[3]) @[el2_lsu_stbuf.scala 193:175] - node _T_723 = eq(stbuf_dma_kill[3], UInt<1>("h00")) @[el2_lsu_stbuf.scala 193:192] - node _T_724 = and(_T_722, _T_723) @[el2_lsu_stbuf.scala 193:190] - node _T_725 = and(_T_724, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 193:211] - node _T_726 = cat(_T_725, _T_718) @[Cat.scala 29:58] - node _T_727 = cat(_T_726, _T_711) @[Cat.scala 29:58] - node stbuf_match_hi = cat(_T_727, _T_704) @[Cat.scala 29:58] - node _T_728 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 194:74] - node _T_729 = bits(cmpaddr_lo_m, 15, 2) @[el2_lsu_stbuf.scala 194:132] - node _T_730 = eq(_T_728, _T_729) @[el2_lsu_stbuf.scala 194:116] - node _T_731 = and(_T_730, stbuf_vld[0]) @[el2_lsu_stbuf.scala 194:175] - node _T_732 = eq(stbuf_dma_kill[0], UInt<1>("h00")) @[el2_lsu_stbuf.scala 194:192] - node _T_733 = and(_T_731, _T_732) @[el2_lsu_stbuf.scala 194:190] - node _T_734 = and(_T_733, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 194:211] - node _T_735 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 194:74] - node _T_736 = bits(cmpaddr_lo_m, 15, 2) @[el2_lsu_stbuf.scala 194:132] - node _T_737 = eq(_T_735, _T_736) @[el2_lsu_stbuf.scala 194:116] - node _T_738 = and(_T_737, stbuf_vld[1]) @[el2_lsu_stbuf.scala 194:175] - node _T_739 = eq(stbuf_dma_kill[1], UInt<1>("h00")) @[el2_lsu_stbuf.scala 194:192] - node _T_740 = and(_T_738, _T_739) @[el2_lsu_stbuf.scala 194:190] - node _T_741 = and(_T_740, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 194:211] - node _T_742 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 194:74] - node _T_743 = bits(cmpaddr_lo_m, 15, 2) @[el2_lsu_stbuf.scala 194:132] - node _T_744 = eq(_T_742, _T_743) @[el2_lsu_stbuf.scala 194:116] - node _T_745 = and(_T_744, stbuf_vld[2]) @[el2_lsu_stbuf.scala 194:175] - node _T_746 = eq(stbuf_dma_kill[2], UInt<1>("h00")) @[el2_lsu_stbuf.scala 194:192] - node _T_747 = and(_T_745, _T_746) @[el2_lsu_stbuf.scala 194:190] - node _T_748 = and(_T_747, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 194:211] - node _T_749 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 194:74] - node _T_750 = bits(cmpaddr_lo_m, 15, 2) @[el2_lsu_stbuf.scala 194:132] - node _T_751 = eq(_T_749, _T_750) @[el2_lsu_stbuf.scala 194:116] - node _T_752 = and(_T_751, stbuf_vld[3]) @[el2_lsu_stbuf.scala 194:175] - node _T_753 = eq(stbuf_dma_kill[3], UInt<1>("h00")) @[el2_lsu_stbuf.scala 194:192] - node _T_754 = and(_T_752, _T_753) @[el2_lsu_stbuf.scala 194:190] - node _T_755 = and(_T_754, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 194:211] - node _T_756 = cat(_T_755, _T_748) @[Cat.scala 29:58] - node _T_757 = cat(_T_756, _T_741) @[Cat.scala 29:58] - node stbuf_match_lo = cat(_T_757, _T_734) @[Cat.scala 29:58] - node _T_758 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 195:75] - node _T_759 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 195:95] - node _T_760 = or(_T_758, _T_759) @[el2_lsu_stbuf.scala 195:79] - node _T_761 = and(_T_760, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 195:100] - node _T_762 = and(_T_761, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 195:121] - node _T_763 = and(_T_762, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:140] - node _T_764 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 195:75] - node _T_765 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 195:95] - node _T_766 = or(_T_764, _T_765) @[el2_lsu_stbuf.scala 195:79] - node _T_767 = and(_T_766, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 195:100] - node _T_768 = and(_T_767, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 195:121] - node _T_769 = and(_T_768, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:140] - node _T_770 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 195:75] - node _T_771 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 195:95] - node _T_772 = or(_T_770, _T_771) @[el2_lsu_stbuf.scala 195:79] - node _T_773 = and(_T_772, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 195:100] - node _T_774 = and(_T_773, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 195:121] - node _T_775 = and(_T_774, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:140] - node _T_776 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 195:75] - node _T_777 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 195:95] - node _T_778 = or(_T_776, _T_777) @[el2_lsu_stbuf.scala 195:79] - node _T_779 = and(_T_778, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 195:100] - node _T_780 = and(_T_779, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 195:121] - node _T_781 = and(_T_780, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:140] - node _T_782 = cat(_T_781, _T_775) @[Cat.scala 29:58] - node _T_783 = cat(_T_782, _T_769) @[Cat.scala 29:58] - node _T_784 = cat(_T_783, _T_763) @[Cat.scala 29:58] - stbuf_dma_kill_en <= _T_784 @[el2_lsu_stbuf.scala 195:22] - node _T_785 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 198:113] - node _T_786 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 198:134] - node _T_787 = and(_T_785, _T_786) @[el2_lsu_stbuf.scala 198:117] - node _T_788 = and(_T_787, stbuf_vld[0]) @[el2_lsu_stbuf.scala 198:138] - node _T_789 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 198:113] - node _T_790 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 198:134] - node _T_791 = and(_T_789, _T_790) @[el2_lsu_stbuf.scala 198:117] - node _T_792 = and(_T_791, stbuf_vld[0]) @[el2_lsu_stbuf.scala 198:138] - node _T_793 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 198:113] - node _T_794 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 198:134] - node _T_795 = and(_T_793, _T_794) @[el2_lsu_stbuf.scala 198:117] - node _T_796 = and(_T_795, stbuf_vld[0]) @[el2_lsu_stbuf.scala 198:138] - node _T_797 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 198:113] - node _T_798 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 198:134] - node _T_799 = and(_T_797, _T_798) @[el2_lsu_stbuf.scala 198:117] - node _T_800 = and(_T_799, stbuf_vld[0]) @[el2_lsu_stbuf.scala 198:138] - node _T_801 = cat(_T_800, _T_796) @[Cat.scala 29:58] - node _T_802 = cat(_T_801, _T_792) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_hi_0 = cat(_T_802, _T_788) @[Cat.scala 29:58] - node _T_803 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 198:113] - node _T_804 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 198:134] - node _T_805 = and(_T_803, _T_804) @[el2_lsu_stbuf.scala 198:117] - node _T_806 = and(_T_805, stbuf_vld[1]) @[el2_lsu_stbuf.scala 198:138] - node _T_807 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 198:113] - node _T_808 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 198:134] - node _T_809 = and(_T_807, _T_808) @[el2_lsu_stbuf.scala 198:117] - node _T_810 = and(_T_809, stbuf_vld[1]) @[el2_lsu_stbuf.scala 198:138] - node _T_811 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 198:113] - node _T_812 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 198:134] - node _T_813 = and(_T_811, _T_812) @[el2_lsu_stbuf.scala 198:117] - node _T_814 = and(_T_813, stbuf_vld[1]) @[el2_lsu_stbuf.scala 198:138] - node _T_815 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 198:113] - node _T_816 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 198:134] - node _T_817 = and(_T_815, _T_816) @[el2_lsu_stbuf.scala 198:117] - node _T_818 = and(_T_817, stbuf_vld[1]) @[el2_lsu_stbuf.scala 198:138] - node _T_819 = cat(_T_818, _T_814) @[Cat.scala 29:58] - node _T_820 = cat(_T_819, _T_810) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_hi_1 = cat(_T_820, _T_806) @[Cat.scala 29:58] - node _T_821 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 198:113] - node _T_822 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 198:134] - node _T_823 = and(_T_821, _T_822) @[el2_lsu_stbuf.scala 198:117] - node _T_824 = and(_T_823, stbuf_vld[2]) @[el2_lsu_stbuf.scala 198:138] - node _T_825 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 198:113] - node _T_826 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 198:134] - node _T_827 = and(_T_825, _T_826) @[el2_lsu_stbuf.scala 198:117] - node _T_828 = and(_T_827, stbuf_vld[2]) @[el2_lsu_stbuf.scala 198:138] - node _T_829 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 198:113] - node _T_830 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 198:134] - node _T_831 = and(_T_829, _T_830) @[el2_lsu_stbuf.scala 198:117] - node _T_832 = and(_T_831, stbuf_vld[2]) @[el2_lsu_stbuf.scala 198:138] - node _T_833 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 198:113] - node _T_834 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 198:134] - node _T_835 = and(_T_833, _T_834) @[el2_lsu_stbuf.scala 198:117] - node _T_836 = and(_T_835, stbuf_vld[2]) @[el2_lsu_stbuf.scala 198:138] - node _T_837 = cat(_T_836, _T_832) @[Cat.scala 29:58] - node _T_838 = cat(_T_837, _T_828) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_hi_2 = cat(_T_838, _T_824) @[Cat.scala 29:58] - node _T_839 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 198:113] - node _T_840 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 198:134] - node _T_841 = and(_T_839, _T_840) @[el2_lsu_stbuf.scala 198:117] - node _T_842 = and(_T_841, stbuf_vld[3]) @[el2_lsu_stbuf.scala 198:138] - node _T_843 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 198:113] - node _T_844 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 198:134] - node _T_845 = and(_T_843, _T_844) @[el2_lsu_stbuf.scala 198:117] - node _T_846 = and(_T_845, stbuf_vld[3]) @[el2_lsu_stbuf.scala 198:138] - node _T_847 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 198:113] - node _T_848 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 198:134] - node _T_849 = and(_T_847, _T_848) @[el2_lsu_stbuf.scala 198:117] - node _T_850 = and(_T_849, stbuf_vld[3]) @[el2_lsu_stbuf.scala 198:138] - node _T_851 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 198:113] - node _T_852 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 198:134] - node _T_853 = and(_T_851, _T_852) @[el2_lsu_stbuf.scala 198:117] - node _T_854 = and(_T_853, stbuf_vld[3]) @[el2_lsu_stbuf.scala 198:138] - node _T_855 = cat(_T_854, _T_850) @[Cat.scala 29:58] - node _T_856 = cat(_T_855, _T_846) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_hi_3 = cat(_T_856, _T_842) @[Cat.scala 29:58] - node _T_857 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 199:113] - node _T_858 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 199:134] - node _T_859 = and(_T_857, _T_858) @[el2_lsu_stbuf.scala 199:117] - node _T_860 = and(_T_859, stbuf_vld[0]) @[el2_lsu_stbuf.scala 199:138] - node _T_861 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 199:113] - node _T_862 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 199:134] - node _T_863 = and(_T_861, _T_862) @[el2_lsu_stbuf.scala 199:117] - node _T_864 = and(_T_863, stbuf_vld[0]) @[el2_lsu_stbuf.scala 199:138] - node _T_865 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 199:113] - node _T_866 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 199:134] - node _T_867 = and(_T_865, _T_866) @[el2_lsu_stbuf.scala 199:117] - node _T_868 = and(_T_867, stbuf_vld[0]) @[el2_lsu_stbuf.scala 199:138] - node _T_869 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 199:113] - node _T_870 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 199:134] - node _T_871 = and(_T_869, _T_870) @[el2_lsu_stbuf.scala 199:117] - node _T_872 = and(_T_871, stbuf_vld[0]) @[el2_lsu_stbuf.scala 199:138] - node _T_873 = cat(_T_872, _T_868) @[Cat.scala 29:58] - node _T_874 = cat(_T_873, _T_864) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_lo_0 = cat(_T_874, _T_860) @[Cat.scala 29:58] - node _T_875 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 199:113] - node _T_876 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 199:134] - node _T_877 = and(_T_875, _T_876) @[el2_lsu_stbuf.scala 199:117] - node _T_878 = and(_T_877, stbuf_vld[1]) @[el2_lsu_stbuf.scala 199:138] - node _T_879 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 199:113] - node _T_880 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 199:134] - node _T_881 = and(_T_879, _T_880) @[el2_lsu_stbuf.scala 199:117] - node _T_882 = and(_T_881, stbuf_vld[1]) @[el2_lsu_stbuf.scala 199:138] - node _T_883 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 199:113] - node _T_884 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 199:134] - node _T_885 = and(_T_883, _T_884) @[el2_lsu_stbuf.scala 199:117] - node _T_886 = and(_T_885, stbuf_vld[1]) @[el2_lsu_stbuf.scala 199:138] - node _T_887 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 199:113] - node _T_888 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 199:134] - node _T_889 = and(_T_887, _T_888) @[el2_lsu_stbuf.scala 199:117] - node _T_890 = and(_T_889, stbuf_vld[1]) @[el2_lsu_stbuf.scala 199:138] - node _T_891 = cat(_T_890, _T_886) @[Cat.scala 29:58] - node _T_892 = cat(_T_891, _T_882) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_lo_1 = cat(_T_892, _T_878) @[Cat.scala 29:58] - node _T_893 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 199:113] - node _T_894 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 199:134] - node _T_895 = and(_T_893, _T_894) @[el2_lsu_stbuf.scala 199:117] - node _T_896 = and(_T_895, stbuf_vld[2]) @[el2_lsu_stbuf.scala 199:138] - node _T_897 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 199:113] - node _T_898 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 199:134] - node _T_899 = and(_T_897, _T_898) @[el2_lsu_stbuf.scala 199:117] - node _T_900 = and(_T_899, stbuf_vld[2]) @[el2_lsu_stbuf.scala 199:138] - node _T_901 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 199:113] - node _T_902 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 199:134] - node _T_903 = and(_T_901, _T_902) @[el2_lsu_stbuf.scala 199:117] - node _T_904 = and(_T_903, stbuf_vld[2]) @[el2_lsu_stbuf.scala 199:138] - node _T_905 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 199:113] - node _T_906 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 199:134] - node _T_907 = and(_T_905, _T_906) @[el2_lsu_stbuf.scala 199:117] - node _T_908 = and(_T_907, stbuf_vld[2]) @[el2_lsu_stbuf.scala 199:138] - node _T_909 = cat(_T_908, _T_904) @[Cat.scala 29:58] - node _T_910 = cat(_T_909, _T_900) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_lo_2 = cat(_T_910, _T_896) @[Cat.scala 29:58] - node _T_911 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 199:113] - node _T_912 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 199:134] - node _T_913 = and(_T_911, _T_912) @[el2_lsu_stbuf.scala 199:117] - node _T_914 = and(_T_913, stbuf_vld[3]) @[el2_lsu_stbuf.scala 199:138] - node _T_915 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 199:113] - node _T_916 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 199:134] - node _T_917 = and(_T_915, _T_916) @[el2_lsu_stbuf.scala 199:117] - node _T_918 = and(_T_917, stbuf_vld[3]) @[el2_lsu_stbuf.scala 199:138] - node _T_919 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 199:113] - node _T_920 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 199:134] - node _T_921 = and(_T_919, _T_920) @[el2_lsu_stbuf.scala 199:117] - node _T_922 = and(_T_921, stbuf_vld[3]) @[el2_lsu_stbuf.scala 199:138] - node _T_923 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 199:113] - node _T_924 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 199:134] - node _T_925 = and(_T_923, _T_924) @[el2_lsu_stbuf.scala 199:117] - node _T_926 = and(_T_925, stbuf_vld[3]) @[el2_lsu_stbuf.scala 199:138] - node _T_927 = cat(_T_926, _T_922) @[Cat.scala 29:58] - node _T_928 = cat(_T_927, _T_918) @[Cat.scala 29:58] - node stbuf_fwdbyteenvec_lo_3 = cat(_T_928, _T_914) @[Cat.scala 29:58] - node _T_929 = bits(stbuf_fwdbyteenvec_hi_0, 0, 0) @[el2_lsu_stbuf.scala 200:126] - node _T_930 = bits(stbuf_fwdbyteenvec_hi_0, 1, 1) @[el2_lsu_stbuf.scala 200:126] - node _T_931 = bits(stbuf_fwdbyteenvec_hi_0, 2, 2) @[el2_lsu_stbuf.scala 200:126] - node _T_932 = bits(stbuf_fwdbyteenvec_hi_0, 3, 3) @[el2_lsu_stbuf.scala 200:126] - node _T_933 = or(_T_932, _T_931) @[el2_lsu_stbuf.scala 200:156] - node _T_934 = or(_T_933, _T_930) @[el2_lsu_stbuf.scala 200:156] - node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_934, _T_929) @[el2_lsu_stbuf.scala 200:156] - node _T_935 = bits(stbuf_fwdbyteenvec_hi_1, 0, 0) @[el2_lsu_stbuf.scala 200:126] - node _T_936 = bits(stbuf_fwdbyteenvec_hi_1, 1, 1) @[el2_lsu_stbuf.scala 200:126] - node _T_937 = bits(stbuf_fwdbyteenvec_hi_1, 2, 2) @[el2_lsu_stbuf.scala 200:126] - node _T_938 = bits(stbuf_fwdbyteenvec_hi_1, 3, 3) @[el2_lsu_stbuf.scala 200:126] - node _T_939 = or(_T_938, _T_937) @[el2_lsu_stbuf.scala 200:156] - node _T_940 = or(_T_939, _T_936) @[el2_lsu_stbuf.scala 200:156] - node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_940, _T_935) @[el2_lsu_stbuf.scala 200:156] - node _T_941 = bits(stbuf_fwdbyteenvec_hi_2, 0, 0) @[el2_lsu_stbuf.scala 200:126] - node _T_942 = bits(stbuf_fwdbyteenvec_hi_2, 1, 1) @[el2_lsu_stbuf.scala 200:126] - node _T_943 = bits(stbuf_fwdbyteenvec_hi_2, 2, 2) @[el2_lsu_stbuf.scala 200:126] - node _T_944 = bits(stbuf_fwdbyteenvec_hi_2, 3, 3) @[el2_lsu_stbuf.scala 200:126] - node _T_945 = or(_T_944, _T_943) @[el2_lsu_stbuf.scala 200:156] - node _T_946 = or(_T_945, _T_942) @[el2_lsu_stbuf.scala 200:156] - node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_946, _T_941) @[el2_lsu_stbuf.scala 200:156] - node _T_947 = bits(stbuf_fwdbyteenvec_hi_3, 0, 0) @[el2_lsu_stbuf.scala 200:126] - node _T_948 = bits(stbuf_fwdbyteenvec_hi_3, 1, 1) @[el2_lsu_stbuf.scala 200:126] - node _T_949 = bits(stbuf_fwdbyteenvec_hi_3, 2, 2) @[el2_lsu_stbuf.scala 200:126] - node _T_950 = bits(stbuf_fwdbyteenvec_hi_3, 3, 3) @[el2_lsu_stbuf.scala 200:126] - node _T_951 = or(_T_950, _T_949) @[el2_lsu_stbuf.scala 200:156] - node _T_952 = or(_T_951, _T_948) @[el2_lsu_stbuf.scala 200:156] - node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_952, _T_947) @[el2_lsu_stbuf.scala 200:156] - node _T_953 = bits(stbuf_fwdbyteenvec_lo_0, 0, 0) @[el2_lsu_stbuf.scala 201:126] - node _T_954 = bits(stbuf_fwdbyteenvec_lo_0, 1, 1) @[el2_lsu_stbuf.scala 201:126] - node _T_955 = bits(stbuf_fwdbyteenvec_lo_0, 2, 2) @[el2_lsu_stbuf.scala 201:126] - node _T_956 = bits(stbuf_fwdbyteenvec_lo_0, 3, 3) @[el2_lsu_stbuf.scala 201:126] - node _T_957 = or(_T_956, _T_955) @[el2_lsu_stbuf.scala 201:156] - node _T_958 = or(_T_957, _T_954) @[el2_lsu_stbuf.scala 201:156] - node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_958, _T_953) @[el2_lsu_stbuf.scala 201:156] - node _T_959 = bits(stbuf_fwdbyteenvec_lo_1, 0, 0) @[el2_lsu_stbuf.scala 201:126] - node _T_960 = bits(stbuf_fwdbyteenvec_lo_1, 1, 1) @[el2_lsu_stbuf.scala 201:126] - node _T_961 = bits(stbuf_fwdbyteenvec_lo_1, 2, 2) @[el2_lsu_stbuf.scala 201:126] - node _T_962 = bits(stbuf_fwdbyteenvec_lo_1, 3, 3) @[el2_lsu_stbuf.scala 201:126] - node _T_963 = or(_T_962, _T_961) @[el2_lsu_stbuf.scala 201:156] - node _T_964 = or(_T_963, _T_960) @[el2_lsu_stbuf.scala 201:156] - node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_964, _T_959) @[el2_lsu_stbuf.scala 201:156] - node _T_965 = bits(stbuf_fwdbyteenvec_lo_2, 0, 0) @[el2_lsu_stbuf.scala 201:126] - node _T_966 = bits(stbuf_fwdbyteenvec_lo_2, 1, 1) @[el2_lsu_stbuf.scala 201:126] - node _T_967 = bits(stbuf_fwdbyteenvec_lo_2, 2, 2) @[el2_lsu_stbuf.scala 201:126] - node _T_968 = bits(stbuf_fwdbyteenvec_lo_2, 3, 3) @[el2_lsu_stbuf.scala 201:126] - node _T_969 = or(_T_968, _T_967) @[el2_lsu_stbuf.scala 201:156] - node _T_970 = or(_T_969, _T_966) @[el2_lsu_stbuf.scala 201:156] - node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_970, _T_965) @[el2_lsu_stbuf.scala 201:156] - node _T_971 = bits(stbuf_fwdbyteenvec_lo_3, 0, 0) @[el2_lsu_stbuf.scala 201:126] - node _T_972 = bits(stbuf_fwdbyteenvec_lo_3, 1, 1) @[el2_lsu_stbuf.scala 201:126] - node _T_973 = bits(stbuf_fwdbyteenvec_lo_3, 2, 2) @[el2_lsu_stbuf.scala 201:126] - node _T_974 = bits(stbuf_fwdbyteenvec_lo_3, 3, 3) @[el2_lsu_stbuf.scala 201:126] - node _T_975 = or(_T_974, _T_973) @[el2_lsu_stbuf.scala 201:156] - node _T_976 = or(_T_975, _T_972) @[el2_lsu_stbuf.scala 201:156] - node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_976, _T_971) @[el2_lsu_stbuf.scala 201:156] - node _T_977 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 203:93] - node _T_978 = bits(_T_977, 0, 0) @[Bitwise.scala 72:15] - node _T_979 = mux(_T_978, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_980 = and(_T_979, stbuf_data[0]) @[el2_lsu_stbuf.scala 203:98] - node _T_981 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 203:93] - node _T_982 = bits(_T_981, 0, 0) @[Bitwise.scala 72:15] - node _T_983 = mux(_T_982, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_984 = and(_T_983, stbuf_data[1]) @[el2_lsu_stbuf.scala 203:98] - node _T_985 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 203:93] - node _T_986 = bits(_T_985, 0, 0) @[Bitwise.scala 72:15] - node _T_987 = mux(_T_986, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_988 = and(_T_987, stbuf_data[2]) @[el2_lsu_stbuf.scala 203:98] - node _T_989 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 203:93] - node _T_990 = bits(_T_989, 0, 0) @[Bitwise.scala 72:15] - node _T_991 = mux(_T_990, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_992 = and(_T_991, stbuf_data[3]) @[el2_lsu_stbuf.scala 203:98] - wire _T_993 : UInt<32>[4] @[el2_lsu_stbuf.scala 203:66] - _T_993[0] <= _T_980 @[el2_lsu_stbuf.scala 203:66] - _T_993[1] <= _T_984 @[el2_lsu_stbuf.scala 203:66] - _T_993[2] <= _T_988 @[el2_lsu_stbuf.scala 203:66] - _T_993[3] <= _T_992 @[el2_lsu_stbuf.scala 203:66] - node _T_994 = or(_T_993[0], _T_993[1]) @[el2_lsu_stbuf.scala 203:123] - node _T_995 = or(_T_994, _T_993[2]) @[el2_lsu_stbuf.scala 203:123] - node stbuf_fwddata_hi_pre_m = or(_T_995, _T_993[3]) @[el2_lsu_stbuf.scala 203:123] - node _T_996 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 204:93] - node _T_997 = bits(_T_996, 0, 0) @[Bitwise.scala 72:15] - node _T_998 = mux(_T_997, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_999 = and(_T_998, stbuf_data[0]) @[el2_lsu_stbuf.scala 204:98] - node _T_1000 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 204:93] - node _T_1001 = bits(_T_1000, 0, 0) @[Bitwise.scala 72:15] - node _T_1002 = mux(_T_1001, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1003 = and(_T_1002, stbuf_data[1]) @[el2_lsu_stbuf.scala 204:98] - node _T_1004 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 204:93] - node _T_1005 = bits(_T_1004, 0, 0) @[Bitwise.scala 72:15] - node _T_1006 = mux(_T_1005, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1007 = and(_T_1006, stbuf_data[2]) @[el2_lsu_stbuf.scala 204:98] - node _T_1008 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 204:93] - node _T_1009 = bits(_T_1008, 0, 0) @[Bitwise.scala 72:15] - node _T_1010 = mux(_T_1009, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_1011 = and(_T_1010, stbuf_data[3]) @[el2_lsu_stbuf.scala 204:98] - wire _T_1012 : UInt<32>[4] @[el2_lsu_stbuf.scala 204:66] - _T_1012[0] <= _T_999 @[el2_lsu_stbuf.scala 204:66] - _T_1012[1] <= _T_1003 @[el2_lsu_stbuf.scala 204:66] - _T_1012[2] <= _T_1007 @[el2_lsu_stbuf.scala 204:66] - _T_1012[3] <= _T_1011 @[el2_lsu_stbuf.scala 204:66] - node _T_1013 = or(_T_1012[0], _T_1012[1]) @[el2_lsu_stbuf.scala 204:123] - node _T_1014 = or(_T_1013, _T_1012[2]) @[el2_lsu_stbuf.scala 204:123] - node stbuf_fwddata_lo_pre_m = or(_T_1014, _T_1012[3]) @[el2_lsu_stbuf.scala 204:123] - node _T_1015 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 206:55] - node _T_1016 = dshl(ldst_byteen_r, _T_1015) @[el2_lsu_stbuf.scala 206:39] - ldst_byteen_ext_r <= _T_1016 @[el2_lsu_stbuf.scala 206:22] - node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 207:44] - node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 208:44] - node _T_1017 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 210:43] - node _T_1018 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 210:67] - node _T_1019 = eq(_T_1017, _T_1018) @[el2_lsu_stbuf.scala 210:50] - node _T_1020 = and(_T_1019, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 210:75] - node _T_1021 = and(_T_1020, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 210:96] - node _T_1022 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 210:119] - node ld_addr_rhit_lo_lo = and(_T_1021, _T_1022) @[el2_lsu_stbuf.scala 210:117] - node _T_1023 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 211:43] - node _T_1024 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 211:67] - node _T_1025 = eq(_T_1023, _T_1024) @[el2_lsu_stbuf.scala 211:50] - node _T_1026 = and(_T_1025, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 211:75] - node _T_1027 = and(_T_1026, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 211:96] - node _T_1028 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 211:119] - node ld_addr_rhit_lo_hi = and(_T_1027, _T_1028) @[el2_lsu_stbuf.scala 211:117] - node _T_1029 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 212:43] - node _T_1030 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 212:67] - node _T_1031 = eq(_T_1029, _T_1030) @[el2_lsu_stbuf.scala 212:50] - node _T_1032 = and(_T_1031, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 212:75] - node _T_1033 = and(_T_1032, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 212:96] - node _T_1034 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:119] - node _T_1035 = and(_T_1033, _T_1034) @[el2_lsu_stbuf.scala 212:117] - node ld_addr_rhit_hi_lo = and(_T_1035, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 212:137] - node _T_1036 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 213:43] - node _T_1037 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 213:67] - node _T_1038 = eq(_T_1036, _T_1037) @[el2_lsu_stbuf.scala 213:50] - node _T_1039 = and(_T_1038, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 213:75] - node _T_1040 = and(_T_1039, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 213:96] - node _T_1041 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:119] - node _T_1042 = and(_T_1040, _T_1041) @[el2_lsu_stbuf.scala 213:117] - node ld_addr_rhit_hi_hi = and(_T_1042, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 213:137] - node _T_1043 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 215:98] - node _T_1044 = and(ld_addr_rhit_lo_lo, _T_1043) @[el2_lsu_stbuf.scala 215:80] - node _T_1045 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 215:98] - node _T_1046 = and(ld_addr_rhit_lo_lo, _T_1045) @[el2_lsu_stbuf.scala 215:80] - node _T_1047 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 215:98] - node _T_1048 = and(ld_addr_rhit_lo_lo, _T_1047) @[el2_lsu_stbuf.scala 215:80] - node _T_1049 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 215:98] - node _T_1050 = and(ld_addr_rhit_lo_lo, _T_1049) @[el2_lsu_stbuf.scala 215:80] - node _T_1051 = cat(_T_1050, _T_1048) @[Cat.scala 29:58] - node _T_1052 = cat(_T_1051, _T_1046) @[Cat.scala 29:58] - node _T_1053 = cat(_T_1052, _T_1044) @[Cat.scala 29:58] - ld_byte_rhit_lo_lo <= _T_1053 @[el2_lsu_stbuf.scala 215:23] - node _T_1054 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 216:98] - node _T_1055 = and(ld_addr_rhit_lo_hi, _T_1054) @[el2_lsu_stbuf.scala 216:80] - node _T_1056 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 216:98] - node _T_1057 = and(ld_addr_rhit_lo_hi, _T_1056) @[el2_lsu_stbuf.scala 216:80] - node _T_1058 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 216:98] - node _T_1059 = and(ld_addr_rhit_lo_hi, _T_1058) @[el2_lsu_stbuf.scala 216:80] - node _T_1060 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 216:98] - node _T_1061 = and(ld_addr_rhit_lo_hi, _T_1060) @[el2_lsu_stbuf.scala 216:80] - node _T_1062 = cat(_T_1061, _T_1059) @[Cat.scala 29:58] - node _T_1063 = cat(_T_1062, _T_1057) @[Cat.scala 29:58] - node _T_1064 = cat(_T_1063, _T_1055) @[Cat.scala 29:58] - ld_byte_rhit_lo_hi <= _T_1064 @[el2_lsu_stbuf.scala 216:23] - node _T_1065 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 217:98] - node _T_1066 = and(ld_addr_rhit_hi_lo, _T_1065) @[el2_lsu_stbuf.scala 217:80] - node _T_1067 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 217:98] - node _T_1068 = and(ld_addr_rhit_hi_lo, _T_1067) @[el2_lsu_stbuf.scala 217:80] - node _T_1069 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 217:98] - node _T_1070 = and(ld_addr_rhit_hi_lo, _T_1069) @[el2_lsu_stbuf.scala 217:80] - node _T_1071 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 217:98] - node _T_1072 = and(ld_addr_rhit_hi_lo, _T_1071) @[el2_lsu_stbuf.scala 217:80] - node _T_1073 = cat(_T_1072, _T_1070) @[Cat.scala 29:58] - node _T_1074 = cat(_T_1073, _T_1068) @[Cat.scala 29:58] - node _T_1075 = cat(_T_1074, _T_1066) @[Cat.scala 29:58] - ld_byte_rhit_hi_lo <= _T_1075 @[el2_lsu_stbuf.scala 217:23] - node _T_1076 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 218:98] - node _T_1077 = and(ld_addr_rhit_hi_hi, _T_1076) @[el2_lsu_stbuf.scala 218:80] - node _T_1078 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 218:98] - node _T_1079 = and(ld_addr_rhit_hi_hi, _T_1078) @[el2_lsu_stbuf.scala 218:80] - node _T_1080 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 218:98] - node _T_1081 = and(ld_addr_rhit_hi_hi, _T_1080) @[el2_lsu_stbuf.scala 218:80] - node _T_1082 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 218:98] - node _T_1083 = and(ld_addr_rhit_hi_hi, _T_1082) @[el2_lsu_stbuf.scala 218:80] - node _T_1084 = cat(_T_1083, _T_1081) @[Cat.scala 29:58] - node _T_1085 = cat(_T_1084, _T_1079) @[Cat.scala 29:58] - node _T_1086 = cat(_T_1085, _T_1077) @[Cat.scala 29:58] - ld_byte_rhit_hi_hi <= _T_1086 @[el2_lsu_stbuf.scala 218:23] - node _T_1087 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 220:97] - node _T_1088 = or(ld_byte_rhit_lo_lo, _T_1087) @[el2_lsu_stbuf.scala 220:77] - node _T_1089 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 220:97] - node _T_1090 = or(ld_byte_rhit_lo_lo, _T_1089) @[el2_lsu_stbuf.scala 220:77] - node _T_1091 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 220:97] - node _T_1092 = or(ld_byte_rhit_lo_lo, _T_1091) @[el2_lsu_stbuf.scala 220:77] - node _T_1093 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 220:97] - node _T_1094 = or(ld_byte_rhit_lo_lo, _T_1093) @[el2_lsu_stbuf.scala 220:77] - node _T_1095 = cat(_T_1094, _T_1092) @[Cat.scala 29:58] - node _T_1096 = cat(_T_1095, _T_1090) @[Cat.scala 29:58] - node _T_1097 = cat(_T_1096, _T_1088) @[Cat.scala 29:58] - ld_byte_rhit_lo <= _T_1097 @[el2_lsu_stbuf.scala 220:20] - node _T_1098 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 221:97] - node _T_1099 = or(ld_byte_rhit_lo_hi, _T_1098) @[el2_lsu_stbuf.scala 221:77] - node _T_1100 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 221:97] - node _T_1101 = or(ld_byte_rhit_lo_hi, _T_1100) @[el2_lsu_stbuf.scala 221:77] - node _T_1102 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 221:97] - node _T_1103 = or(ld_byte_rhit_lo_hi, _T_1102) @[el2_lsu_stbuf.scala 221:77] - node _T_1104 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 221:97] - node _T_1105 = or(ld_byte_rhit_lo_hi, _T_1104) @[el2_lsu_stbuf.scala 221:77] - node _T_1106 = cat(_T_1105, _T_1103) @[Cat.scala 29:58] - node _T_1107 = cat(_T_1106, _T_1101) @[Cat.scala 29:58] - node _T_1108 = cat(_T_1107, _T_1099) @[Cat.scala 29:58] - ld_byte_rhit_hi <= _T_1108 @[el2_lsu_stbuf.scala 221:20] - node _T_1109 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 223:49] - node _T_1110 = bits(_T_1109, 0, 0) @[Bitwise.scala 72:15] - node _T_1111 = mux(_T_1110, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1112 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 223:74] - node _T_1113 = and(_T_1111, _T_1112) @[el2_lsu_stbuf.scala 223:54] - node _T_1114 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 223:110] - node _T_1115 = bits(_T_1114, 0, 0) @[Bitwise.scala 72:15] - node _T_1116 = mux(_T_1115, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1117 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 223:135] - node _T_1118 = and(_T_1116, _T_1117) @[el2_lsu_stbuf.scala 223:115] - node fwdpipe1_lo = or(_T_1113, _T_1118) @[el2_lsu_stbuf.scala 223:81] - node _T_1119 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 224:49] - node _T_1120 = bits(_T_1119, 0, 0) @[Bitwise.scala 72:15] - node _T_1121 = mux(_T_1120, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1122 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 224:74] - node _T_1123 = and(_T_1121, _T_1122) @[el2_lsu_stbuf.scala 224:54] - node _T_1124 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 224:111] - node _T_1125 = bits(_T_1124, 0, 0) @[Bitwise.scala 72:15] - node _T_1126 = mux(_T_1125, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1127 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 224:136] - node _T_1128 = and(_T_1126, _T_1127) @[el2_lsu_stbuf.scala 224:116] - node fwdpipe2_lo = or(_T_1123, _T_1128) @[el2_lsu_stbuf.scala 224:82] - node _T_1129 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 225:49] - node _T_1130 = bits(_T_1129, 0, 0) @[Bitwise.scala 72:15] - node _T_1131 = mux(_T_1130, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1132 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 225:74] - node _T_1133 = and(_T_1131, _T_1132) @[el2_lsu_stbuf.scala 225:54] - node _T_1134 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 225:112] - node _T_1135 = bits(_T_1134, 0, 0) @[Bitwise.scala 72:15] - node _T_1136 = mux(_T_1135, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1137 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 225:137] - node _T_1138 = and(_T_1136, _T_1137) @[el2_lsu_stbuf.scala 225:117] - node fwdpipe3_lo = or(_T_1133, _T_1138) @[el2_lsu_stbuf.scala 225:83] - node _T_1139 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 226:49] - node _T_1140 = bits(_T_1139, 0, 0) @[Bitwise.scala 72:15] - node _T_1141 = mux(_T_1140, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1142 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 226:74] - node _T_1143 = and(_T_1141, _T_1142) @[el2_lsu_stbuf.scala 226:54] - node _T_1144 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 226:112] - node _T_1145 = bits(_T_1144, 0, 0) @[Bitwise.scala 72:15] - node _T_1146 = mux(_T_1145, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1147 = bits(io.store_data_hi_r, 31, 8) @[el2_lsu_stbuf.scala 226:137] - node _T_1148 = and(_T_1146, _T_1147) @[el2_lsu_stbuf.scala 226:117] - node fwdpipe4_lo = or(_T_1143, _T_1148) @[el2_lsu_stbuf.scala 226:83] - node _T_1149 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] - node _T_1150 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] - node _T_1151 = cat(_T_1150, _T_1149) @[Cat.scala 29:58] - ld_fwddata_rpipe_lo <= _T_1151 @[el2_lsu_stbuf.scala 227:24] - node _T_1152 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 229:49] + RdPtr <= _T_719 @[el2_lsu_stbuf.scala 192:41] + node _T_720 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 194:86] + node _T_721 = cat(UInt<3>("h00"), _T_720) @[Cat.scala 29:58] + node _T_722 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 194:86] + node _T_723 = cat(UInt<3>("h00"), _T_722) @[Cat.scala 29:58] + node _T_724 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 194:86] + node _T_725 = cat(UInt<3>("h00"), _T_724) @[Cat.scala 29:58] + node _T_726 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 194:86] + node _T_727 = cat(UInt<3>("h00"), _T_726) @[Cat.scala 29:58] + wire _T_728 : UInt<4>[4] @[el2_lsu_stbuf.scala 194:59] + _T_728[0] <= _T_721 @[el2_lsu_stbuf.scala 194:59] + _T_728[1] <= _T_723 @[el2_lsu_stbuf.scala 194:59] + _T_728[2] <= _T_725 @[el2_lsu_stbuf.scala 194:59] + _T_728[3] <= _T_727 @[el2_lsu_stbuf.scala 194:59] + node _T_729 = add(_T_728[0], _T_728[1]) @[el2_lsu_stbuf.scala 194:101] + node _T_730 = tail(_T_729, 1) @[el2_lsu_stbuf.scala 194:101] + node _T_731 = add(_T_730, _T_728[2]) @[el2_lsu_stbuf.scala 194:101] + node _T_732 = tail(_T_731, 1) @[el2_lsu_stbuf.scala 194:101] + node _T_733 = add(_T_732, _T_728[3]) @[el2_lsu_stbuf.scala 194:101] + node stbuf_numvld_any = tail(_T_733, 1) @[el2_lsu_stbuf.scala 194:101] + node _T_734 = and(io.lsu_pkt_m.valid, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 195:39] + node _T_735 = and(_T_734, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 195:60] + node _T_736 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 195:82] + node isdccmst_m = and(_T_735, _T_736) @[el2_lsu_stbuf.scala 195:80] + node _T_737 = and(io.lsu_pkt_r.valid, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 196:39] + node _T_738 = and(_T_737, io.addr_in_dccm_r) @[el2_lsu_stbuf.scala 196:60] + node _T_739 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 196:82] + node isdccmst_r = and(_T_738, _T_739) @[el2_lsu_stbuf.scala 196:80] + node _T_740 = cat(UInt<1>("h00"), isdccmst_m) @[Cat.scala 29:58] + node _T_741 = and(isdccmst_m, ldst_dual_m) @[el2_lsu_stbuf.scala 198:62] + node _T_742 = dshl(_T_740, _T_741) @[el2_lsu_stbuf.scala 198:47] + stbuf_specvld_m <= _T_742 @[el2_lsu_stbuf.scala 198:19] + node _T_743 = cat(UInt<1>("h00"), isdccmst_r) @[Cat.scala 29:58] + node _T_744 = and(isdccmst_r, ldst_dual_r) @[el2_lsu_stbuf.scala 199:62] + node _T_745 = dshl(_T_743, _T_744) @[el2_lsu_stbuf.scala 199:47] + stbuf_specvld_r <= _T_745 @[el2_lsu_stbuf.scala 199:19] + node _T_746 = cat(UInt<2>("h00"), stbuf_specvld_m) @[Cat.scala 29:58] + node _T_747 = add(stbuf_numvld_any, _T_746) @[el2_lsu_stbuf.scala 200:44] + node _T_748 = tail(_T_747, 1) @[el2_lsu_stbuf.scala 200:44] + node _T_749 = cat(UInt<2>("h00"), stbuf_specvld_r) @[Cat.scala 29:58] + node _T_750 = add(_T_748, _T_749) @[el2_lsu_stbuf.scala 200:78] + node stbuf_specvld_any = tail(_T_750, 1) @[el2_lsu_stbuf.scala 200:78] + node _T_751 = eq(ldst_dual_d, UInt<1>("h00")) @[el2_lsu_stbuf.scala 202:34] + node _T_752 = and(_T_751, io.dec_lsu_valid_raw_d) @[el2_lsu_stbuf.scala 202:47] + node _T_753 = bits(_T_752, 0, 0) @[el2_lsu_stbuf.scala 202:73] + node _T_754 = geq(stbuf_specvld_any, UInt<3>("h04")) @[el2_lsu_stbuf.scala 202:99] + node _T_755 = geq(stbuf_specvld_any, UInt<2>("h03")) @[el2_lsu_stbuf.scala 202:140] + node _T_756 = mux(_T_753, _T_754, _T_755) @[el2_lsu_stbuf.scala 202:32] + io.lsu_stbuf_full_any <= _T_756 @[el2_lsu_stbuf.scala 202:26] + node _T_757 = eq(stbuf_numvld_any, UInt<1>("h00")) @[el2_lsu_stbuf.scala 203:46] + io.lsu_stbuf_empty_any <= _T_757 @[el2_lsu_stbuf.scala 203:26] + node cmpen_hi_m = and(io.lsu_cmpen_m, ldst_dual_m) @[el2_lsu_stbuf.scala 205:36] + node _T_758 = bits(io.end_addr_m, 15, 2) @[el2_lsu_stbuf.scala 206:32] + cmpaddr_hi_m <= _T_758 @[el2_lsu_stbuf.scala 206:16] + node _T_759 = bits(io.lsu_addr_m, 15, 2) @[el2_lsu_stbuf.scala 209:33] + cmpaddr_lo_m <= _T_759 @[el2_lsu_stbuf.scala 209:17] + node _T_760 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 212:73] + node _T_761 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:131] + node _T_762 = eq(_T_760, _T_761) @[el2_lsu_stbuf.scala 212:115] + node _T_763 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 212:150] + node _T_764 = and(_T_762, _T_763) @[el2_lsu_stbuf.scala 212:139] + node _T_765 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 212:171] + node _T_766 = eq(_T_765, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:156] + node _T_767 = and(_T_764, _T_766) @[el2_lsu_stbuf.scala 212:154] + node _T_768 = and(_T_767, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:175] + node _T_769 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 212:73] + node _T_770 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:131] + node _T_771 = eq(_T_769, _T_770) @[el2_lsu_stbuf.scala 212:115] + node _T_772 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 212:150] + node _T_773 = and(_T_771, _T_772) @[el2_lsu_stbuf.scala 212:139] + node _T_774 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 212:171] + node _T_775 = eq(_T_774, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:156] + node _T_776 = and(_T_773, _T_775) @[el2_lsu_stbuf.scala 212:154] + node _T_777 = and(_T_776, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:175] + node _T_778 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 212:73] + node _T_779 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:131] + node _T_780 = eq(_T_778, _T_779) @[el2_lsu_stbuf.scala 212:115] + node _T_781 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 212:150] + node _T_782 = and(_T_780, _T_781) @[el2_lsu_stbuf.scala 212:139] + node _T_783 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 212:171] + node _T_784 = eq(_T_783, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:156] + node _T_785 = and(_T_782, _T_784) @[el2_lsu_stbuf.scala 212:154] + node _T_786 = and(_T_785, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:175] + node _T_787 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 212:73] + node _T_788 = bits(cmpaddr_hi_m, 13, 0) @[el2_lsu_stbuf.scala 212:131] + node _T_789 = eq(_T_787, _T_788) @[el2_lsu_stbuf.scala 212:115] + node _T_790 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 212:150] + node _T_791 = and(_T_789, _T_790) @[el2_lsu_stbuf.scala 212:139] + node _T_792 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 212:171] + node _T_793 = eq(_T_792, UInt<1>("h00")) @[el2_lsu_stbuf.scala 212:156] + node _T_794 = and(_T_791, _T_793) @[el2_lsu_stbuf.scala 212:154] + node _T_795 = and(_T_794, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 212:175] + node _T_796 = cat(_T_795, _T_786) @[Cat.scala 29:58] + node _T_797 = cat(_T_796, _T_777) @[Cat.scala 29:58] + node stbuf_match_hi = cat(_T_797, _T_768) @[Cat.scala 29:58] + node _T_798 = bits(stbuf_addr[0], 15, 2) @[el2_lsu_stbuf.scala 213:73] + node _T_799 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:131] + node _T_800 = eq(_T_798, _T_799) @[el2_lsu_stbuf.scala 213:115] + node _T_801 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 213:150] + node _T_802 = and(_T_800, _T_801) @[el2_lsu_stbuf.scala 213:139] + node _T_803 = bits(stbuf_dma_kill, 0, 0) @[el2_lsu_stbuf.scala 213:171] + node _T_804 = eq(_T_803, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:156] + node _T_805 = and(_T_802, _T_804) @[el2_lsu_stbuf.scala 213:154] + node _T_806 = and(_T_805, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:175] + node _T_807 = bits(stbuf_addr[1], 15, 2) @[el2_lsu_stbuf.scala 213:73] + node _T_808 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:131] + node _T_809 = eq(_T_807, _T_808) @[el2_lsu_stbuf.scala 213:115] + node _T_810 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 213:150] + node _T_811 = and(_T_809, _T_810) @[el2_lsu_stbuf.scala 213:139] + node _T_812 = bits(stbuf_dma_kill, 1, 1) @[el2_lsu_stbuf.scala 213:171] + node _T_813 = eq(_T_812, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:156] + node _T_814 = and(_T_811, _T_813) @[el2_lsu_stbuf.scala 213:154] + node _T_815 = and(_T_814, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:175] + node _T_816 = bits(stbuf_addr[2], 15, 2) @[el2_lsu_stbuf.scala 213:73] + node _T_817 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:131] + node _T_818 = eq(_T_816, _T_817) @[el2_lsu_stbuf.scala 213:115] + node _T_819 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 213:150] + node _T_820 = and(_T_818, _T_819) @[el2_lsu_stbuf.scala 213:139] + node _T_821 = bits(stbuf_dma_kill, 2, 2) @[el2_lsu_stbuf.scala 213:171] + node _T_822 = eq(_T_821, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:156] + node _T_823 = and(_T_820, _T_822) @[el2_lsu_stbuf.scala 213:154] + node _T_824 = and(_T_823, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:175] + node _T_825 = bits(stbuf_addr[3], 15, 2) @[el2_lsu_stbuf.scala 213:73] + node _T_826 = bits(cmpaddr_lo_m, 13, 0) @[el2_lsu_stbuf.scala 213:131] + node _T_827 = eq(_T_825, _T_826) @[el2_lsu_stbuf.scala 213:115] + node _T_828 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 213:150] + node _T_829 = and(_T_827, _T_828) @[el2_lsu_stbuf.scala 213:139] + node _T_830 = bits(stbuf_dma_kill, 3, 3) @[el2_lsu_stbuf.scala 213:171] + node _T_831 = eq(_T_830, UInt<1>("h00")) @[el2_lsu_stbuf.scala 213:156] + node _T_832 = and(_T_829, _T_831) @[el2_lsu_stbuf.scala 213:154] + node _T_833 = and(_T_832, io.addr_in_dccm_m) @[el2_lsu_stbuf.scala 213:175] + node _T_834 = cat(_T_833, _T_824) @[Cat.scala 29:58] + node _T_835 = cat(_T_834, _T_815) @[Cat.scala 29:58] + node stbuf_match_lo = cat(_T_835, _T_806) @[Cat.scala 29:58] + node _T_836 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 214:74] + node _T_837 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 214:94] + node _T_838 = or(_T_836, _T_837) @[el2_lsu_stbuf.scala 214:78] + node _T_839 = and(_T_838, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:99] + node _T_840 = and(_T_839, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:120] + node _T_841 = and(_T_840, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:139] + node _T_842 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 214:74] + node _T_843 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 214:94] + node _T_844 = or(_T_842, _T_843) @[el2_lsu_stbuf.scala 214:78] + node _T_845 = and(_T_844, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:99] + node _T_846 = and(_T_845, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:120] + node _T_847 = and(_T_846, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:139] + node _T_848 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 214:74] + node _T_849 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 214:94] + node _T_850 = or(_T_848, _T_849) @[el2_lsu_stbuf.scala 214:78] + node _T_851 = and(_T_850, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:99] + node _T_852 = and(_T_851, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:120] + node _T_853 = and(_T_852, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:139] + node _T_854 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 214:74] + node _T_855 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 214:94] + node _T_856 = or(_T_854, _T_855) @[el2_lsu_stbuf.scala 214:78] + node _T_857 = and(_T_856, io.lsu_pkt_m.valid) @[el2_lsu_stbuf.scala 214:99] + node _T_858 = and(_T_857, io.lsu_pkt_m.dma) @[el2_lsu_stbuf.scala 214:120] + node _T_859 = and(_T_858, io.lsu_pkt_m.store) @[el2_lsu_stbuf.scala 214:139] + node _T_860 = cat(_T_859, _T_853) @[Cat.scala 29:58] + node _T_861 = cat(_T_860, _T_847) @[Cat.scala 29:58] + node _T_862 = cat(_T_861, _T_841) @[Cat.scala 29:58] + stbuf_dma_kill_en <= _T_862 @[el2_lsu_stbuf.scala 214:21] + node _T_863 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:112] + node _T_864 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 217:133] + node _T_865 = and(_T_863, _T_864) @[el2_lsu_stbuf.scala 217:116] + node _T_866 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_0 = and(_T_865, _T_866) @[el2_lsu_stbuf.scala 217:137] + node _T_867 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:112] + node _T_868 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 217:133] + node _T_869 = and(_T_867, _T_868) @[el2_lsu_stbuf.scala 217:116] + node _T_870 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_1 = and(_T_869, _T_870) @[el2_lsu_stbuf.scala 217:137] + node _T_871 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:112] + node _T_872 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 217:133] + node _T_873 = and(_T_871, _T_872) @[el2_lsu_stbuf.scala 217:116] + node _T_874 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_2 = and(_T_873, _T_874) @[el2_lsu_stbuf.scala 217:137] + node _T_875 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 217:112] + node _T_876 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 217:133] + node _T_877 = and(_T_875, _T_876) @[el2_lsu_stbuf.scala 217:116] + node _T_878 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_0_3 = and(_T_877, _T_878) @[el2_lsu_stbuf.scala 217:137] + node _T_879 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:112] + node _T_880 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 217:133] + node _T_881 = and(_T_879, _T_880) @[el2_lsu_stbuf.scala 217:116] + node _T_882 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_0 = and(_T_881, _T_882) @[el2_lsu_stbuf.scala 217:137] + node _T_883 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:112] + node _T_884 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 217:133] + node _T_885 = and(_T_883, _T_884) @[el2_lsu_stbuf.scala 217:116] + node _T_886 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_1 = and(_T_885, _T_886) @[el2_lsu_stbuf.scala 217:137] + node _T_887 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:112] + node _T_888 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 217:133] + node _T_889 = and(_T_887, _T_888) @[el2_lsu_stbuf.scala 217:116] + node _T_890 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_2 = and(_T_889, _T_890) @[el2_lsu_stbuf.scala 217:137] + node _T_891 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 217:112] + node _T_892 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 217:133] + node _T_893 = and(_T_891, _T_892) @[el2_lsu_stbuf.scala 217:116] + node _T_894 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_1_3 = and(_T_893, _T_894) @[el2_lsu_stbuf.scala 217:137] + node _T_895 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:112] + node _T_896 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 217:133] + node _T_897 = and(_T_895, _T_896) @[el2_lsu_stbuf.scala 217:116] + node _T_898 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_0 = and(_T_897, _T_898) @[el2_lsu_stbuf.scala 217:137] + node _T_899 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:112] + node _T_900 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 217:133] + node _T_901 = and(_T_899, _T_900) @[el2_lsu_stbuf.scala 217:116] + node _T_902 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_1 = and(_T_901, _T_902) @[el2_lsu_stbuf.scala 217:137] + node _T_903 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:112] + node _T_904 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 217:133] + node _T_905 = and(_T_903, _T_904) @[el2_lsu_stbuf.scala 217:116] + node _T_906 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_2 = and(_T_905, _T_906) @[el2_lsu_stbuf.scala 217:137] + node _T_907 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 217:112] + node _T_908 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 217:133] + node _T_909 = and(_T_907, _T_908) @[el2_lsu_stbuf.scala 217:116] + node _T_910 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_2_3 = and(_T_909, _T_910) @[el2_lsu_stbuf.scala 217:137] + node _T_911 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:112] + node _T_912 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 217:133] + node _T_913 = and(_T_911, _T_912) @[el2_lsu_stbuf.scala 217:116] + node _T_914 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_0 = and(_T_913, _T_914) @[el2_lsu_stbuf.scala 217:137] + node _T_915 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:112] + node _T_916 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 217:133] + node _T_917 = and(_T_915, _T_916) @[el2_lsu_stbuf.scala 217:116] + node _T_918 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_1 = and(_T_917, _T_918) @[el2_lsu_stbuf.scala 217:137] + node _T_919 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:112] + node _T_920 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 217:133] + node _T_921 = and(_T_919, _T_920) @[el2_lsu_stbuf.scala 217:116] + node _T_922 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_2 = and(_T_921, _T_922) @[el2_lsu_stbuf.scala 217:137] + node _T_923 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 217:112] + node _T_924 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 217:133] + node _T_925 = and(_T_923, _T_924) @[el2_lsu_stbuf.scala 217:116] + node _T_926 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 217:148] + node stbuf_fwdbyteenvec_hi_3_3 = and(_T_925, _T_926) @[el2_lsu_stbuf.scala 217:137] + node _T_927 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:112] + node _T_928 = bits(stbuf_byteen[0], 0, 0) @[el2_lsu_stbuf.scala 218:133] + node _T_929 = and(_T_927, _T_928) @[el2_lsu_stbuf.scala 218:116] + node _T_930 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_0 = and(_T_929, _T_930) @[el2_lsu_stbuf.scala 218:137] + node _T_931 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:112] + node _T_932 = bits(stbuf_byteen[0], 1, 1) @[el2_lsu_stbuf.scala 218:133] + node _T_933 = and(_T_931, _T_932) @[el2_lsu_stbuf.scala 218:116] + node _T_934 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_1 = and(_T_933, _T_934) @[el2_lsu_stbuf.scala 218:137] + node _T_935 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:112] + node _T_936 = bits(stbuf_byteen[0], 2, 2) @[el2_lsu_stbuf.scala 218:133] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_stbuf.scala 218:116] + node _T_938 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_2 = and(_T_937, _T_938) @[el2_lsu_stbuf.scala 218:137] + node _T_939 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 218:112] + node _T_940 = bits(stbuf_byteen[0], 3, 3) @[el2_lsu_stbuf.scala 218:133] + node _T_941 = and(_T_939, _T_940) @[el2_lsu_stbuf.scala 218:116] + node _T_942 = bits(stbuf_vld, 0, 0) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_0_3 = and(_T_941, _T_942) @[el2_lsu_stbuf.scala 218:137] + node _T_943 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:112] + node _T_944 = bits(stbuf_byteen[1], 0, 0) @[el2_lsu_stbuf.scala 218:133] + node _T_945 = and(_T_943, _T_944) @[el2_lsu_stbuf.scala 218:116] + node _T_946 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_0 = and(_T_945, _T_946) @[el2_lsu_stbuf.scala 218:137] + node _T_947 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:112] + node _T_948 = bits(stbuf_byteen[1], 1, 1) @[el2_lsu_stbuf.scala 218:133] + node _T_949 = and(_T_947, _T_948) @[el2_lsu_stbuf.scala 218:116] + node _T_950 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_1 = and(_T_949, _T_950) @[el2_lsu_stbuf.scala 218:137] + node _T_951 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:112] + node _T_952 = bits(stbuf_byteen[1], 2, 2) @[el2_lsu_stbuf.scala 218:133] + node _T_953 = and(_T_951, _T_952) @[el2_lsu_stbuf.scala 218:116] + node _T_954 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_2 = and(_T_953, _T_954) @[el2_lsu_stbuf.scala 218:137] + node _T_955 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 218:112] + node _T_956 = bits(stbuf_byteen[1], 3, 3) @[el2_lsu_stbuf.scala 218:133] + node _T_957 = and(_T_955, _T_956) @[el2_lsu_stbuf.scala 218:116] + node _T_958 = bits(stbuf_vld, 1, 1) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_1_3 = and(_T_957, _T_958) @[el2_lsu_stbuf.scala 218:137] + node _T_959 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:112] + node _T_960 = bits(stbuf_byteen[2], 0, 0) @[el2_lsu_stbuf.scala 218:133] + node _T_961 = and(_T_959, _T_960) @[el2_lsu_stbuf.scala 218:116] + node _T_962 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_0 = and(_T_961, _T_962) @[el2_lsu_stbuf.scala 218:137] + node _T_963 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:112] + node _T_964 = bits(stbuf_byteen[2], 1, 1) @[el2_lsu_stbuf.scala 218:133] + node _T_965 = and(_T_963, _T_964) @[el2_lsu_stbuf.scala 218:116] + node _T_966 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_1 = and(_T_965, _T_966) @[el2_lsu_stbuf.scala 218:137] + node _T_967 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:112] + node _T_968 = bits(stbuf_byteen[2], 2, 2) @[el2_lsu_stbuf.scala 218:133] + node _T_969 = and(_T_967, _T_968) @[el2_lsu_stbuf.scala 218:116] + node _T_970 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_2 = and(_T_969, _T_970) @[el2_lsu_stbuf.scala 218:137] + node _T_971 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 218:112] + node _T_972 = bits(stbuf_byteen[2], 3, 3) @[el2_lsu_stbuf.scala 218:133] + node _T_973 = and(_T_971, _T_972) @[el2_lsu_stbuf.scala 218:116] + node _T_974 = bits(stbuf_vld, 2, 2) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_2_3 = and(_T_973, _T_974) @[el2_lsu_stbuf.scala 218:137] + node _T_975 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:112] + node _T_976 = bits(stbuf_byteen[3], 0, 0) @[el2_lsu_stbuf.scala 218:133] + node _T_977 = and(_T_975, _T_976) @[el2_lsu_stbuf.scala 218:116] + node _T_978 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_0 = and(_T_977, _T_978) @[el2_lsu_stbuf.scala 218:137] + node _T_979 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:112] + node _T_980 = bits(stbuf_byteen[3], 1, 1) @[el2_lsu_stbuf.scala 218:133] + node _T_981 = and(_T_979, _T_980) @[el2_lsu_stbuf.scala 218:116] + node _T_982 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_1 = and(_T_981, _T_982) @[el2_lsu_stbuf.scala 218:137] + node _T_983 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:112] + node _T_984 = bits(stbuf_byteen[3], 2, 2) @[el2_lsu_stbuf.scala 218:133] + node _T_985 = and(_T_983, _T_984) @[el2_lsu_stbuf.scala 218:116] + node _T_986 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_2 = and(_T_985, _T_986) @[el2_lsu_stbuf.scala 218:137] + node _T_987 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 218:112] + node _T_988 = bits(stbuf_byteen[3], 3, 3) @[el2_lsu_stbuf.scala 218:133] + node _T_989 = and(_T_987, _T_988) @[el2_lsu_stbuf.scala 218:116] + node _T_990 = bits(stbuf_vld, 3, 3) @[el2_lsu_stbuf.scala 218:148] + node stbuf_fwdbyteenvec_lo_3_3 = and(_T_989, _T_990) @[el2_lsu_stbuf.scala 218:137] + node _T_991 = or(stbuf_fwdbyteenvec_hi_0_0, stbuf_fwdbyteenvec_hi_1_0) @[el2_lsu_stbuf.scala 219:147] + node _T_992 = or(_T_991, stbuf_fwdbyteenvec_hi_2_0) @[el2_lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_0 = or(_T_992, stbuf_fwdbyteenvec_hi_3_0) @[el2_lsu_stbuf.scala 219:147] + node _T_993 = or(stbuf_fwdbyteenvec_hi_0_1, stbuf_fwdbyteenvec_hi_1_1) @[el2_lsu_stbuf.scala 219:147] + node _T_994 = or(_T_993, stbuf_fwdbyteenvec_hi_2_1) @[el2_lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_1 = or(_T_994, stbuf_fwdbyteenvec_hi_3_1) @[el2_lsu_stbuf.scala 219:147] + node _T_995 = or(stbuf_fwdbyteenvec_hi_0_2, stbuf_fwdbyteenvec_hi_1_2) @[el2_lsu_stbuf.scala 219:147] + node _T_996 = or(_T_995, stbuf_fwdbyteenvec_hi_2_2) @[el2_lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_2 = or(_T_996, stbuf_fwdbyteenvec_hi_3_2) @[el2_lsu_stbuf.scala 219:147] + node _T_997 = or(stbuf_fwdbyteenvec_hi_0_3, stbuf_fwdbyteenvec_hi_1_3) @[el2_lsu_stbuf.scala 219:147] + node _T_998 = or(_T_997, stbuf_fwdbyteenvec_hi_2_3) @[el2_lsu_stbuf.scala 219:147] + node stbuf_fwdbyteen_hi_pre_m_3 = or(_T_998, stbuf_fwdbyteenvec_hi_3_3) @[el2_lsu_stbuf.scala 219:147] + node _T_999 = or(stbuf_fwdbyteenvec_lo_0_0, stbuf_fwdbyteenvec_lo_1_0) @[el2_lsu_stbuf.scala 220:147] + node _T_1000 = or(_T_999, stbuf_fwdbyteenvec_lo_2_0) @[el2_lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_0 = or(_T_1000, stbuf_fwdbyteenvec_lo_3_0) @[el2_lsu_stbuf.scala 220:147] + node _T_1001 = or(stbuf_fwdbyteenvec_lo_0_1, stbuf_fwdbyteenvec_lo_1_1) @[el2_lsu_stbuf.scala 220:147] + node _T_1002 = or(_T_1001, stbuf_fwdbyteenvec_lo_2_1) @[el2_lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_1 = or(_T_1002, stbuf_fwdbyteenvec_lo_3_1) @[el2_lsu_stbuf.scala 220:147] + node _T_1003 = or(stbuf_fwdbyteenvec_lo_0_2, stbuf_fwdbyteenvec_lo_1_2) @[el2_lsu_stbuf.scala 220:147] + node _T_1004 = or(_T_1003, stbuf_fwdbyteenvec_lo_2_2) @[el2_lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_2 = or(_T_1004, stbuf_fwdbyteenvec_lo_3_2) @[el2_lsu_stbuf.scala 220:147] + node _T_1005 = or(stbuf_fwdbyteenvec_lo_0_3, stbuf_fwdbyteenvec_lo_1_3) @[el2_lsu_stbuf.scala 220:147] + node _T_1006 = or(_T_1005, stbuf_fwdbyteenvec_lo_2_3) @[el2_lsu_stbuf.scala 220:147] + node stbuf_fwdbyteen_lo_pre_m_3 = or(_T_1006, stbuf_fwdbyteenvec_lo_3_3) @[el2_lsu_stbuf.scala 220:147] + node _T_1007 = bits(stbuf_match_hi, 0, 0) @[el2_lsu_stbuf.scala 222:92] + node _T_1008 = bits(_T_1007, 0, 0) @[Bitwise.scala 72:15] + node _T_1009 = mux(_T_1008, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1010 = and(_T_1009, stbuf_data[0]) @[el2_lsu_stbuf.scala 222:97] + node _T_1011 = bits(stbuf_match_hi, 1, 1) @[el2_lsu_stbuf.scala 222:92] + node _T_1012 = bits(_T_1011, 0, 0) @[Bitwise.scala 72:15] + node _T_1013 = mux(_T_1012, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1014 = and(_T_1013, stbuf_data[1]) @[el2_lsu_stbuf.scala 222:97] + node _T_1015 = bits(stbuf_match_hi, 2, 2) @[el2_lsu_stbuf.scala 222:92] + node _T_1016 = bits(_T_1015, 0, 0) @[Bitwise.scala 72:15] + node _T_1017 = mux(_T_1016, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1018 = and(_T_1017, stbuf_data[2]) @[el2_lsu_stbuf.scala 222:97] + node _T_1019 = bits(stbuf_match_hi, 3, 3) @[el2_lsu_stbuf.scala 222:92] + node _T_1020 = bits(_T_1019, 0, 0) @[Bitwise.scala 72:15] + node _T_1021 = mux(_T_1020, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1022 = and(_T_1021, stbuf_data[3]) @[el2_lsu_stbuf.scala 222:97] + wire _T_1023 : UInt<32>[4] @[el2_lsu_stbuf.scala 222:65] + _T_1023[0] <= _T_1010 @[el2_lsu_stbuf.scala 222:65] + _T_1023[1] <= _T_1014 @[el2_lsu_stbuf.scala 222:65] + _T_1023[2] <= _T_1018 @[el2_lsu_stbuf.scala 222:65] + _T_1023[3] <= _T_1022 @[el2_lsu_stbuf.scala 222:65] + node _T_1024 = or(_T_1023[3], _T_1023[2]) @[el2_lsu_stbuf.scala 222:130] + node _T_1025 = or(_T_1024, _T_1023[1]) @[el2_lsu_stbuf.scala 222:130] + node stbuf_fwddata_hi_pre_m = or(_T_1025, _T_1023[0]) @[el2_lsu_stbuf.scala 222:130] + node _T_1026 = bits(stbuf_match_lo, 0, 0) @[el2_lsu_stbuf.scala 223:92] + node _T_1027 = bits(_T_1026, 0, 0) @[Bitwise.scala 72:15] + node _T_1028 = mux(_T_1027, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1029 = and(_T_1028, stbuf_data[0]) @[el2_lsu_stbuf.scala 223:97] + node _T_1030 = bits(stbuf_match_lo, 1, 1) @[el2_lsu_stbuf.scala 223:92] + node _T_1031 = bits(_T_1030, 0, 0) @[Bitwise.scala 72:15] + node _T_1032 = mux(_T_1031, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1033 = and(_T_1032, stbuf_data[1]) @[el2_lsu_stbuf.scala 223:97] + node _T_1034 = bits(stbuf_match_lo, 2, 2) @[el2_lsu_stbuf.scala 223:92] + node _T_1035 = bits(_T_1034, 0, 0) @[Bitwise.scala 72:15] + node _T_1036 = mux(_T_1035, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1037 = and(_T_1036, stbuf_data[2]) @[el2_lsu_stbuf.scala 223:97] + node _T_1038 = bits(stbuf_match_lo, 3, 3) @[el2_lsu_stbuf.scala 223:92] + node _T_1039 = bits(_T_1038, 0, 0) @[Bitwise.scala 72:15] + node _T_1040 = mux(_T_1039, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1041 = and(_T_1040, stbuf_data[3]) @[el2_lsu_stbuf.scala 223:97] + wire _T_1042 : UInt<32>[4] @[el2_lsu_stbuf.scala 223:65] + _T_1042[0] <= _T_1029 @[el2_lsu_stbuf.scala 223:65] + _T_1042[1] <= _T_1033 @[el2_lsu_stbuf.scala 223:65] + _T_1042[2] <= _T_1037 @[el2_lsu_stbuf.scala 223:65] + _T_1042[3] <= _T_1041 @[el2_lsu_stbuf.scala 223:65] + node _T_1043 = or(_T_1042[3], _T_1042[2]) @[el2_lsu_stbuf.scala 223:130] + node _T_1044 = or(_T_1043, _T_1042[1]) @[el2_lsu_stbuf.scala 223:130] + node stbuf_fwddata_lo_pre_m = or(_T_1044, _T_1042[0]) @[el2_lsu_stbuf.scala 223:130] + node _T_1045 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_stbuf.scala 226:54] + node _T_1046 = dshl(ldst_byteen_r, _T_1045) @[el2_lsu_stbuf.scala 226:38] + ldst_byteen_ext_r <= _T_1046 @[el2_lsu_stbuf.scala 226:21] + node ldst_byteen_hi_r = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_stbuf.scala 227:43] + node ldst_byteen_lo_r = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_stbuf.scala 228:43] + node _T_1047 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 230:42] + node _T_1048 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 230:66] + node _T_1049 = eq(_T_1047, _T_1048) @[el2_lsu_stbuf.scala 230:49] + node _T_1050 = and(_T_1049, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 230:74] + node _T_1051 = and(_T_1050, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 230:95] + node _T_1052 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 230:118] + node ld_addr_rhit_lo_lo = and(_T_1051, _T_1052) @[el2_lsu_stbuf.scala 230:116] + node _T_1053 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 231:42] + node _T_1054 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_stbuf.scala 231:66] + node _T_1055 = eq(_T_1053, _T_1054) @[el2_lsu_stbuf.scala 231:49] + node _T_1056 = and(_T_1055, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 231:74] + node _T_1057 = and(_T_1056, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 231:95] + node _T_1058 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 231:118] + node ld_addr_rhit_lo_hi = and(_T_1057, _T_1058) @[el2_lsu_stbuf.scala 231:116] + node _T_1059 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_stbuf.scala 232:42] + node _T_1060 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 232:66] + node _T_1061 = eq(_T_1059, _T_1060) @[el2_lsu_stbuf.scala 232:49] + node _T_1062 = and(_T_1061, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 232:74] + node _T_1063 = and(_T_1062, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 232:95] + node _T_1064 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 232:118] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_stbuf.scala 232:116] + node ld_addr_rhit_hi_lo = and(_T_1065, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 232:136] + node _T_1066 = bits(io.end_addr_m, 31, 2) @[el2_lsu_stbuf.scala 233:42] + node _T_1067 = bits(io.end_addr_r, 31, 2) @[el2_lsu_stbuf.scala 233:66] + node _T_1068 = eq(_T_1066, _T_1067) @[el2_lsu_stbuf.scala 233:49] + node _T_1069 = and(_T_1068, io.lsu_pkt_r.valid) @[el2_lsu_stbuf.scala 233:74] + node _T_1070 = and(_T_1069, io.lsu_pkt_r.store) @[el2_lsu_stbuf.scala 233:95] + node _T_1071 = eq(io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu_stbuf.scala 233:118] + node _T_1072 = and(_T_1070, _T_1071) @[el2_lsu_stbuf.scala 233:116] + node ld_addr_rhit_hi_hi = and(_T_1072, dual_stbuf_write_r) @[el2_lsu_stbuf.scala 233:136] + node _T_1073 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 235:97] + node _T_1074 = and(ld_addr_rhit_lo_lo, _T_1073) @[el2_lsu_stbuf.scala 235:79] + node _T_1075 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 235:97] + node _T_1076 = and(ld_addr_rhit_lo_lo, _T_1075) @[el2_lsu_stbuf.scala 235:79] + node _T_1077 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 235:97] + node _T_1078 = and(ld_addr_rhit_lo_lo, _T_1077) @[el2_lsu_stbuf.scala 235:79] + node _T_1079 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 235:97] + node _T_1080 = and(ld_addr_rhit_lo_lo, _T_1079) @[el2_lsu_stbuf.scala 235:79] + node _T_1081 = cat(_T_1080, _T_1078) @[Cat.scala 29:58] + node _T_1082 = cat(_T_1081, _T_1076) @[Cat.scala 29:58] + node _T_1083 = cat(_T_1082, _T_1074) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_1083 @[el2_lsu_stbuf.scala 235:22] + node _T_1084 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_stbuf.scala 236:97] + node _T_1085 = and(ld_addr_rhit_lo_hi, _T_1084) @[el2_lsu_stbuf.scala 236:79] + node _T_1086 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_stbuf.scala 236:97] + node _T_1087 = and(ld_addr_rhit_lo_hi, _T_1086) @[el2_lsu_stbuf.scala 236:79] + node _T_1088 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_stbuf.scala 236:97] + node _T_1089 = and(ld_addr_rhit_lo_hi, _T_1088) @[el2_lsu_stbuf.scala 236:79] + node _T_1090 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_stbuf.scala 236:97] + node _T_1091 = and(ld_addr_rhit_lo_hi, _T_1090) @[el2_lsu_stbuf.scala 236:79] + node _T_1092 = cat(_T_1091, _T_1089) @[Cat.scala 29:58] + node _T_1093 = cat(_T_1092, _T_1087) @[Cat.scala 29:58] + node _T_1094 = cat(_T_1093, _T_1085) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_1094 @[el2_lsu_stbuf.scala 236:22] + node _T_1095 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 237:97] + node _T_1096 = and(ld_addr_rhit_hi_lo, _T_1095) @[el2_lsu_stbuf.scala 237:79] + node _T_1097 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 237:97] + node _T_1098 = and(ld_addr_rhit_hi_lo, _T_1097) @[el2_lsu_stbuf.scala 237:79] + node _T_1099 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 237:97] + node _T_1100 = and(ld_addr_rhit_hi_lo, _T_1099) @[el2_lsu_stbuf.scala 237:79] + node _T_1101 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 237:97] + node _T_1102 = and(ld_addr_rhit_hi_lo, _T_1101) @[el2_lsu_stbuf.scala 237:79] + node _T_1103 = cat(_T_1102, _T_1100) @[Cat.scala 29:58] + node _T_1104 = cat(_T_1103, _T_1098) @[Cat.scala 29:58] + node _T_1105 = cat(_T_1104, _T_1096) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_1105 @[el2_lsu_stbuf.scala 237:22] + node _T_1106 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_stbuf.scala 238:97] + node _T_1107 = and(ld_addr_rhit_hi_hi, _T_1106) @[el2_lsu_stbuf.scala 238:79] + node _T_1108 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_stbuf.scala 238:97] + node _T_1109 = and(ld_addr_rhit_hi_hi, _T_1108) @[el2_lsu_stbuf.scala 238:79] + node _T_1110 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_stbuf.scala 238:97] + node _T_1111 = and(ld_addr_rhit_hi_hi, _T_1110) @[el2_lsu_stbuf.scala 238:79] + node _T_1112 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_stbuf.scala 238:97] + node _T_1113 = and(ld_addr_rhit_hi_hi, _T_1112) @[el2_lsu_stbuf.scala 238:79] + node _T_1114 = cat(_T_1113, _T_1111) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1109) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1107) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_1116 @[el2_lsu_stbuf.scala 238:22] + node _T_1117 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 240:75] + node _T_1118 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 240:99] + node _T_1119 = or(_T_1117, _T_1118) @[el2_lsu_stbuf.scala 240:79] + node _T_1120 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 240:75] + node _T_1121 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 240:99] + node _T_1122 = or(_T_1120, _T_1121) @[el2_lsu_stbuf.scala 240:79] + node _T_1123 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 240:75] + node _T_1124 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 240:99] + node _T_1125 = or(_T_1123, _T_1124) @[el2_lsu_stbuf.scala 240:79] + node _T_1126 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 240:75] + node _T_1127 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 240:99] + node _T_1128 = or(_T_1126, _T_1127) @[el2_lsu_stbuf.scala 240:79] + node _T_1129 = cat(_T_1128, _T_1125) @[Cat.scala 29:58] + node _T_1130 = cat(_T_1129, _T_1122) @[Cat.scala 29:58] + node _T_1131 = cat(_T_1130, _T_1119) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_1131 @[el2_lsu_stbuf.scala 240:19] + node _T_1132 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 241:75] + node _T_1133 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 241:99] + node _T_1134 = or(_T_1132, _T_1133) @[el2_lsu_stbuf.scala 241:79] + node _T_1135 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 241:75] + node _T_1136 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 241:99] + node _T_1137 = or(_T_1135, _T_1136) @[el2_lsu_stbuf.scala 241:79] + node _T_1138 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 241:75] + node _T_1139 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 241:99] + node _T_1140 = or(_T_1138, _T_1139) @[el2_lsu_stbuf.scala 241:79] + node _T_1141 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 241:75] + node _T_1142 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 241:99] + node _T_1143 = or(_T_1141, _T_1142) @[el2_lsu_stbuf.scala 241:79] + node _T_1144 = cat(_T_1143, _T_1140) @[Cat.scala 29:58] + node _T_1145 = cat(_T_1144, _T_1137) @[Cat.scala 29:58] + node _T_1146 = cat(_T_1145, _T_1134) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_1146 @[el2_lsu_stbuf.scala 241:19] + node _T_1147 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 243:48] + node _T_1148 = bits(_T_1147, 0, 0) @[Bitwise.scala 72:15] + node _T_1149 = mux(_T_1148, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1150 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 243:73] + node _T_1151 = and(_T_1149, _T_1150) @[el2_lsu_stbuf.scala 243:53] + node _T_1152 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 243:109] node _T_1153 = bits(_T_1152, 0, 0) @[Bitwise.scala 72:15] node _T_1154 = mux(_T_1153, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1155 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 229:74] - node _T_1156 = and(_T_1154, _T_1155) @[el2_lsu_stbuf.scala 229:54] - node _T_1157 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 229:110] + node _T_1155 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 243:134] + node _T_1156 = and(_T_1154, _T_1155) @[el2_lsu_stbuf.scala 243:114] + node fwdpipe1_lo = or(_T_1151, _T_1156) @[el2_lsu_stbuf.scala 243:80] + node _T_1157 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 244:48] node _T_1158 = bits(_T_1157, 0, 0) @[Bitwise.scala 72:15] node _T_1159 = mux(_T_1158, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1160 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 229:135] - node _T_1161 = and(_T_1159, _T_1160) @[el2_lsu_stbuf.scala 229:115] - node fwdpipe1_hi = or(_T_1156, _T_1161) @[el2_lsu_stbuf.scala 229:81] - node _T_1162 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 230:49] + node _T_1160 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 244:73] + node _T_1161 = and(_T_1159, _T_1160) @[el2_lsu_stbuf.scala 244:53] + node _T_1162 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 244:110] node _T_1163 = bits(_T_1162, 0, 0) @[Bitwise.scala 72:15] node _T_1164 = mux(_T_1163, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1165 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 230:74] - node _T_1166 = and(_T_1164, _T_1165) @[el2_lsu_stbuf.scala 230:54] - node _T_1167 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 230:111] + node _T_1165 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 244:135] + node _T_1166 = and(_T_1164, _T_1165) @[el2_lsu_stbuf.scala 244:115] + node fwdpipe2_lo = or(_T_1161, _T_1166) @[el2_lsu_stbuf.scala 244:81] + node _T_1167 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 245:48] node _T_1168 = bits(_T_1167, 0, 0) @[Bitwise.scala 72:15] node _T_1169 = mux(_T_1168, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1170 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 230:136] - node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_stbuf.scala 230:116] - node fwdpipe2_hi = or(_T_1166, _T_1171) @[el2_lsu_stbuf.scala 230:82] - node _T_1172 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 231:49] + node _T_1170 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 245:73] + node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_stbuf.scala 245:53] + node _T_1172 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 245:111] node _T_1173 = bits(_T_1172, 0, 0) @[Bitwise.scala 72:15] node _T_1174 = mux(_T_1173, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1175 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 231:74] - node _T_1176 = and(_T_1174, _T_1175) @[el2_lsu_stbuf.scala 231:54] - node _T_1177 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 231:112] + node _T_1175 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 245:136] + node _T_1176 = and(_T_1174, _T_1175) @[el2_lsu_stbuf.scala 245:116] + node fwdpipe3_lo = or(_T_1171, _T_1176) @[el2_lsu_stbuf.scala 245:82] + node _T_1177 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 246:48] node _T_1178 = bits(_T_1177, 0, 0) @[Bitwise.scala 72:15] node _T_1179 = mux(_T_1178, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1180 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 231:137] - node _T_1181 = and(_T_1179, _T_1180) @[el2_lsu_stbuf.scala 231:117] - node fwdpipe3_hi = or(_T_1176, _T_1181) @[el2_lsu_stbuf.scala 231:83] - node _T_1182 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 232:49] + node _T_1180 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 246:73] + node _T_1181 = and(_T_1179, _T_1180) @[el2_lsu_stbuf.scala 246:53] + node _T_1182 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 246:111] node _T_1183 = bits(_T_1182, 0, 0) @[Bitwise.scala 72:15] node _T_1184 = mux(_T_1183, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1185 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 232:74] - node _T_1186 = and(_T_1184, _T_1185) @[el2_lsu_stbuf.scala 232:54] - node _T_1187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 232:112] - node _T_1188 = bits(_T_1187, 0, 0) @[Bitwise.scala 72:15] - node _T_1189 = mux(_T_1188, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_1190 = bits(io.store_data_hi_r, 31, 8) @[el2_lsu_stbuf.scala 232:137] - node _T_1191 = and(_T_1189, _T_1190) @[el2_lsu_stbuf.scala 232:117] - node fwdpipe4_hi = or(_T_1186, _T_1191) @[el2_lsu_stbuf.scala 232:83] - node _T_1192 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] - node _T_1193 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] - node _T_1194 = cat(_T_1193, _T_1192) @[Cat.scala 29:58] - ld_fwddata_rpipe_hi <= _T_1194 @[el2_lsu_stbuf.scala 233:24] - node _T_1195 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_stbuf.scala 235:80] - node _T_1196 = or(_T_1195, stbuf_fwdbyteen_hi_pre_m_0) @[el2_lsu_stbuf.scala 235:84] - node _T_1197 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_stbuf.scala 235:80] - node _T_1198 = or(_T_1197, stbuf_fwdbyteen_hi_pre_m_1) @[el2_lsu_stbuf.scala 235:84] - node _T_1199 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_stbuf.scala 235:80] - node _T_1200 = or(_T_1199, stbuf_fwdbyteen_hi_pre_m_2) @[el2_lsu_stbuf.scala 235:84] - node _T_1201 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_stbuf.scala 235:80] - node _T_1202 = or(_T_1201, stbuf_fwdbyteen_hi_pre_m_3) @[el2_lsu_stbuf.scala 235:84] - node _T_1203 = cat(_T_1202, _T_1200) @[Cat.scala 29:58] - node _T_1204 = cat(_T_1203, _T_1198) @[Cat.scala 29:58] - node _T_1205 = cat(_T_1204, _T_1196) @[Cat.scala 29:58] - io.stbuf_fwdbyteen_hi_m <= _T_1205 @[el2_lsu_stbuf.scala 235:28] - node _T_1206 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_stbuf.scala 236:80] - node _T_1207 = or(_T_1206, stbuf_fwdbyteen_lo_pre_m_0) @[el2_lsu_stbuf.scala 236:84] - node _T_1208 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_stbuf.scala 236:80] - node _T_1209 = or(_T_1208, stbuf_fwdbyteen_lo_pre_m_1) @[el2_lsu_stbuf.scala 236:84] - node _T_1210 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_stbuf.scala 236:80] - node _T_1211 = or(_T_1210, stbuf_fwdbyteen_lo_pre_m_2) @[el2_lsu_stbuf.scala 236:84] - node _T_1212 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_stbuf.scala 236:80] - node _T_1213 = or(_T_1212, stbuf_fwdbyteen_lo_pre_m_3) @[el2_lsu_stbuf.scala 236:84] - node _T_1214 = cat(_T_1213, _T_1211) @[Cat.scala 29:58] - node _T_1215 = cat(_T_1214, _T_1209) @[Cat.scala 29:58] - node _T_1216 = cat(_T_1215, _T_1207) @[Cat.scala 29:58] - io.stbuf_fwdbyteen_lo_m <= _T_1216 @[el2_lsu_stbuf.scala 236:28] - node _T_1217 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_stbuf.scala 239:47] - node _T_1218 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_stbuf.scala 239:70] - node _T_1219 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[el2_lsu_stbuf.scala 239:98] - node stbuf_fwdpipe1_lo = mux(_T_1217, _T_1218, _T_1219) @[el2_lsu_stbuf.scala 239:31] - node _T_1220 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_stbuf.scala 240:47] - node _T_1221 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_stbuf.scala 240:70] - node _T_1222 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[el2_lsu_stbuf.scala 240:99] - node stbuf_fwdpipe2_lo = mux(_T_1220, _T_1221, _T_1222) @[el2_lsu_stbuf.scala 240:31] - node _T_1223 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_stbuf.scala 241:47] - node _T_1224 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_stbuf.scala 241:70] - node _T_1225 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[el2_lsu_stbuf.scala 241:100] - node stbuf_fwdpipe3_lo = mux(_T_1223, _T_1224, _T_1225) @[el2_lsu_stbuf.scala 241:31] - node _T_1226 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_stbuf.scala 242:47] - node _T_1227 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_stbuf.scala 242:70] - node _T_1228 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[el2_lsu_stbuf.scala 242:100] - node stbuf_fwdpipe4_lo = mux(_T_1226, _T_1227, _T_1228) @[el2_lsu_stbuf.scala 242:31] - node _T_1229 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] - node _T_1230 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] - node _T_1231 = cat(_T_1230, _T_1229) @[Cat.scala 29:58] - io.stbuf_fwddata_lo_m <= _T_1231 @[el2_lsu_stbuf.scala 243:26] - node _T_1232 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_stbuf.scala 245:47] - node _T_1233 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_stbuf.scala 245:70] - node _T_1234 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[el2_lsu_stbuf.scala 245:98] - node stbuf_fwdpipe1_hi = mux(_T_1232, _T_1233, _T_1234) @[el2_lsu_stbuf.scala 245:31] - node _T_1235 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_stbuf.scala 246:47] - node _T_1236 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_stbuf.scala 246:70] - node _T_1237 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[el2_lsu_stbuf.scala 246:99] - node stbuf_fwdpipe2_hi = mux(_T_1235, _T_1236, _T_1237) @[el2_lsu_stbuf.scala 246:31] - node _T_1238 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_stbuf.scala 247:47] - node _T_1239 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_stbuf.scala 247:70] - node _T_1240 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[el2_lsu_stbuf.scala 247:100] - node stbuf_fwdpipe3_hi = mux(_T_1238, _T_1239, _T_1240) @[el2_lsu_stbuf.scala 247:31] - node _T_1241 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_stbuf.scala 248:47] - node _T_1242 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_stbuf.scala 248:70] - node _T_1243 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[el2_lsu_stbuf.scala 248:100] - node stbuf_fwdpipe4_hi = mux(_T_1241, _T_1242, _T_1243) @[el2_lsu_stbuf.scala 248:31] - node _T_1244 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] - node _T_1245 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] - node _T_1246 = cat(_T_1245, _T_1244) @[Cat.scala 29:58] - io.stbuf_fwddata_hi_m <= _T_1246 @[el2_lsu_stbuf.scala 249:26] - reg _T_1247 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when WrPtrEn : @[Reg.scala 28:19] - _T_1247 <= NxtWrPtr @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - WrPtr <= _T_1247 @[el2_lsu_stbuf.scala 251:42] - reg _T_1248 : UInt, io.lsu_stbuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when RdPtrEn : @[Reg.scala 28:19] - _T_1248 <= NxtRdPtr @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - RdPtr <= _T_1248 @[el2_lsu_stbuf.scala 252:42] + node _T_1185 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_stbuf.scala 246:136] + node _T_1186 = and(_T_1184, _T_1185) @[el2_lsu_stbuf.scala 246:116] + node fwdpipe4_lo = or(_T_1181, _T_1186) @[el2_lsu_stbuf.scala 246:82] + node _T_1187 = cat(fwdpipe2_lo, fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1188 = cat(fwdpipe4_lo, fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1189 = cat(_T_1188, _T_1187) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_1189 @[el2_lsu_stbuf.scala 247:23] + node _T_1190 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 249:48] + node _T_1191 = bits(_T_1190, 0, 0) @[Bitwise.scala 72:15] + node _T_1192 = mux(_T_1191, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1193 = bits(io.store_data_lo_r, 7, 0) @[el2_lsu_stbuf.scala 249:73] + node _T_1194 = and(_T_1192, _T_1193) @[el2_lsu_stbuf.scala 249:53] + node _T_1195 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 249:109] + node _T_1196 = bits(_T_1195, 0, 0) @[Bitwise.scala 72:15] + node _T_1197 = mux(_T_1196, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1198 = bits(io.store_data_hi_r, 7, 0) @[el2_lsu_stbuf.scala 249:134] + node _T_1199 = and(_T_1197, _T_1198) @[el2_lsu_stbuf.scala 249:114] + node fwdpipe1_hi = or(_T_1194, _T_1199) @[el2_lsu_stbuf.scala 249:80] + node _T_1200 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 250:48] + node _T_1201 = bits(_T_1200, 0, 0) @[Bitwise.scala 72:15] + node _T_1202 = mux(_T_1201, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1203 = bits(io.store_data_lo_r, 15, 8) @[el2_lsu_stbuf.scala 250:73] + node _T_1204 = and(_T_1202, _T_1203) @[el2_lsu_stbuf.scala 250:53] + node _T_1205 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 250:110] + node _T_1206 = bits(_T_1205, 0, 0) @[Bitwise.scala 72:15] + node _T_1207 = mux(_T_1206, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1208 = bits(io.store_data_hi_r, 15, 8) @[el2_lsu_stbuf.scala 250:135] + node _T_1209 = and(_T_1207, _T_1208) @[el2_lsu_stbuf.scala 250:115] + node fwdpipe2_hi = or(_T_1204, _T_1209) @[el2_lsu_stbuf.scala 250:81] + node _T_1210 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 251:48] + node _T_1211 = bits(_T_1210, 0, 0) @[Bitwise.scala 72:15] + node _T_1212 = mux(_T_1211, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1213 = bits(io.store_data_lo_r, 23, 16) @[el2_lsu_stbuf.scala 251:73] + node _T_1214 = and(_T_1212, _T_1213) @[el2_lsu_stbuf.scala 251:53] + node _T_1215 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 251:111] + node _T_1216 = bits(_T_1215, 0, 0) @[Bitwise.scala 72:15] + node _T_1217 = mux(_T_1216, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1218 = bits(io.store_data_hi_r, 23, 16) @[el2_lsu_stbuf.scala 251:136] + node _T_1219 = and(_T_1217, _T_1218) @[el2_lsu_stbuf.scala 251:116] + node fwdpipe3_hi = or(_T_1214, _T_1219) @[el2_lsu_stbuf.scala 251:82] + node _T_1220 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 252:48] + node _T_1221 = bits(_T_1220, 0, 0) @[Bitwise.scala 72:15] + node _T_1222 = mux(_T_1221, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1223 = bits(io.store_data_lo_r, 31, 24) @[el2_lsu_stbuf.scala 252:73] + node _T_1224 = and(_T_1222, _T_1223) @[el2_lsu_stbuf.scala 252:53] + node _T_1225 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 252:111] + node _T_1226 = bits(_T_1225, 0, 0) @[Bitwise.scala 72:15] + node _T_1227 = mux(_T_1226, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1228 = bits(io.store_data_hi_r, 31, 24) @[el2_lsu_stbuf.scala 252:136] + node _T_1229 = and(_T_1227, _T_1228) @[el2_lsu_stbuf.scala 252:116] + node fwdpipe4_hi = or(_T_1224, _T_1229) @[el2_lsu_stbuf.scala 252:82] + node _T_1230 = cat(fwdpipe2_hi, fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1231 = cat(fwdpipe4_hi, fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1232 = cat(_T_1231, _T_1230) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_1232 @[el2_lsu_stbuf.scala 253:23] + node _T_1233 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_stbuf.scala 255:74] + node _T_1234 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_stbuf.scala 255:98] + node _T_1235 = or(_T_1233, _T_1234) @[el2_lsu_stbuf.scala 255:78] + node _T_1236 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_stbuf.scala 255:74] + node _T_1237 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_stbuf.scala 255:98] + node _T_1238 = or(_T_1236, _T_1237) @[el2_lsu_stbuf.scala 255:78] + node _T_1239 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_stbuf.scala 255:74] + node _T_1240 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_stbuf.scala 255:98] + node _T_1241 = or(_T_1239, _T_1240) @[el2_lsu_stbuf.scala 255:78] + node _T_1242 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_stbuf.scala 255:74] + node _T_1243 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_stbuf.scala 255:98] + node _T_1244 = or(_T_1242, _T_1243) @[el2_lsu_stbuf.scala 255:78] + node _T_1245 = cat(_T_1244, _T_1241) @[Cat.scala 29:58] + node _T_1246 = cat(_T_1245, _T_1238) @[Cat.scala 29:58] + node _T_1247 = cat(_T_1246, _T_1235) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_1247 @[el2_lsu_stbuf.scala 255:18] + node _T_1248 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_stbuf.scala 256:74] + node _T_1249 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_stbuf.scala 256:98] + node _T_1250 = or(_T_1248, _T_1249) @[el2_lsu_stbuf.scala 256:78] + node _T_1251 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_stbuf.scala 256:74] + node _T_1252 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_stbuf.scala 256:98] + node _T_1253 = or(_T_1251, _T_1252) @[el2_lsu_stbuf.scala 256:78] + node _T_1254 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_stbuf.scala 256:74] + node _T_1255 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_stbuf.scala 256:98] + node _T_1256 = or(_T_1254, _T_1255) @[el2_lsu_stbuf.scala 256:78] + node _T_1257 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_stbuf.scala 256:74] + node _T_1258 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_stbuf.scala 256:98] + node _T_1259 = or(_T_1257, _T_1258) @[el2_lsu_stbuf.scala 256:78] + node _T_1260 = cat(_T_1259, _T_1256) @[Cat.scala 29:58] + node _T_1261 = cat(_T_1260, _T_1253) @[Cat.scala 29:58] + node _T_1262 = cat(_T_1261, _T_1250) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_1262 @[el2_lsu_stbuf.scala 256:18] + node _T_1263 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_stbuf.scala 258:79] + node _T_1264 = or(_T_1263, stbuf_fwdbyteen_hi_pre_m_0) @[el2_lsu_stbuf.scala 258:83] + node _T_1265 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_stbuf.scala 258:79] + node _T_1266 = or(_T_1265, stbuf_fwdbyteen_hi_pre_m_1) @[el2_lsu_stbuf.scala 258:83] + node _T_1267 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_stbuf.scala 258:79] + node _T_1268 = or(_T_1267, stbuf_fwdbyteen_hi_pre_m_2) @[el2_lsu_stbuf.scala 258:83] + node _T_1269 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_stbuf.scala 258:79] + node _T_1270 = or(_T_1269, stbuf_fwdbyteen_hi_pre_m_3) @[el2_lsu_stbuf.scala 258:83] + node _T_1271 = cat(_T_1270, _T_1268) @[Cat.scala 29:58] + node _T_1272 = cat(_T_1271, _T_1266) @[Cat.scala 29:58] + node _T_1273 = cat(_T_1272, _T_1264) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_hi_m <= _T_1273 @[el2_lsu_stbuf.scala 258:27] + node _T_1274 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_stbuf.scala 259:79] + node _T_1275 = or(_T_1274, stbuf_fwdbyteen_lo_pre_m_0) @[el2_lsu_stbuf.scala 259:83] + node _T_1276 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_stbuf.scala 259:79] + node _T_1277 = or(_T_1276, stbuf_fwdbyteen_lo_pre_m_1) @[el2_lsu_stbuf.scala 259:83] + node _T_1278 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_stbuf.scala 259:79] + node _T_1279 = or(_T_1278, stbuf_fwdbyteen_lo_pre_m_2) @[el2_lsu_stbuf.scala 259:83] + node _T_1280 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_stbuf.scala 259:79] + node _T_1281 = or(_T_1280, stbuf_fwdbyteen_lo_pre_m_3) @[el2_lsu_stbuf.scala 259:83] + node _T_1282 = cat(_T_1281, _T_1279) @[Cat.scala 29:58] + node _T_1283 = cat(_T_1282, _T_1277) @[Cat.scala 29:58] + node _T_1284 = cat(_T_1283, _T_1275) @[Cat.scala 29:58] + io.stbuf_fwdbyteen_lo_m <= _T_1284 @[el2_lsu_stbuf.scala 259:27] + node _T_1285 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_stbuf.scala 262:46] + node _T_1286 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_stbuf.scala 262:69] + node _T_1287 = bits(stbuf_fwddata_lo_pre_m, 7, 0) @[el2_lsu_stbuf.scala 262:97] + node stbuf_fwdpipe1_lo = mux(_T_1285, _T_1286, _T_1287) @[el2_lsu_stbuf.scala 262:30] + node _T_1288 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_stbuf.scala 263:46] + node _T_1289 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_stbuf.scala 263:69] + node _T_1290 = bits(stbuf_fwddata_lo_pre_m, 15, 8) @[el2_lsu_stbuf.scala 263:98] + node stbuf_fwdpipe2_lo = mux(_T_1288, _T_1289, _T_1290) @[el2_lsu_stbuf.scala 263:30] + node _T_1291 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_stbuf.scala 264:46] + node _T_1292 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_stbuf.scala 264:69] + node _T_1293 = bits(stbuf_fwddata_lo_pre_m, 23, 16) @[el2_lsu_stbuf.scala 264:99] + node stbuf_fwdpipe3_lo = mux(_T_1291, _T_1292, _T_1293) @[el2_lsu_stbuf.scala 264:30] + node _T_1294 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_stbuf.scala 265:46] + node _T_1295 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_stbuf.scala 265:69] + node _T_1296 = bits(stbuf_fwddata_lo_pre_m, 31, 24) @[el2_lsu_stbuf.scala 265:99] + node stbuf_fwdpipe4_lo = mux(_T_1294, _T_1295, _T_1296) @[el2_lsu_stbuf.scala 265:30] + node _T_1297 = cat(stbuf_fwdpipe2_lo, stbuf_fwdpipe1_lo) @[Cat.scala 29:58] + node _T_1298 = cat(stbuf_fwdpipe4_lo, stbuf_fwdpipe3_lo) @[Cat.scala 29:58] + node _T_1299 = cat(_T_1298, _T_1297) @[Cat.scala 29:58] + io.stbuf_fwddata_lo_m <= _T_1299 @[el2_lsu_stbuf.scala 266:25] + node _T_1300 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_stbuf.scala 268:46] + node _T_1301 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_stbuf.scala 268:69] + node _T_1302 = bits(stbuf_fwddata_hi_pre_m, 7, 0) @[el2_lsu_stbuf.scala 268:97] + node stbuf_fwdpipe1_hi = mux(_T_1300, _T_1301, _T_1302) @[el2_lsu_stbuf.scala 268:30] + node _T_1303 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_stbuf.scala 269:46] + node _T_1304 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_stbuf.scala 269:69] + node _T_1305 = bits(stbuf_fwddata_hi_pre_m, 15, 8) @[el2_lsu_stbuf.scala 269:98] + node stbuf_fwdpipe2_hi = mux(_T_1303, _T_1304, _T_1305) @[el2_lsu_stbuf.scala 269:30] + node _T_1306 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_stbuf.scala 270:46] + node _T_1307 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_stbuf.scala 270:69] + node _T_1308 = bits(stbuf_fwddata_hi_pre_m, 23, 16) @[el2_lsu_stbuf.scala 270:99] + node stbuf_fwdpipe3_hi = mux(_T_1306, _T_1307, _T_1308) @[el2_lsu_stbuf.scala 270:30] + node _T_1309 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_stbuf.scala 271:46] + node _T_1310 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_stbuf.scala 271:69] + node _T_1311 = bits(stbuf_fwddata_hi_pre_m, 31, 24) @[el2_lsu_stbuf.scala 271:99] + node stbuf_fwdpipe4_hi = mux(_T_1309, _T_1310, _T_1311) @[el2_lsu_stbuf.scala 271:30] + node _T_1312 = cat(stbuf_fwdpipe2_hi, stbuf_fwdpipe1_hi) @[Cat.scala 29:58] + node _T_1313 = cat(stbuf_fwdpipe4_hi, stbuf_fwdpipe3_hi) @[Cat.scala 29:58] + node _T_1314 = cat(_T_1313, _T_1312) @[Cat.scala 29:58] + io.stbuf_fwddata_hi_m <= _T_1314 @[el2_lsu_stbuf.scala 272:25] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_ecc : input clock : Clock @@ -3453,10 +4821,6 @@ circuit el2_lsu : dccm_rdata_hi_any <= UInt<32>("h00") wire dccm_rdata_lo_any : UInt<32> dccm_rdata_lo_any <= UInt<32>("h00") - wire dccm_wdata_ecc_hi_any : UInt<7> - dccm_wdata_ecc_hi_any <= UInt<7>("h00") - wire dccm_wdata_ecc_lo_any : UInt<7> - dccm_wdata_ecc_lo_any <= UInt<7>("h00") wire dccm_data_ecc_hi_any : UInt<7> dccm_data_ecc_hi_any <= UInt<7>("h00") wire dccm_data_ecc_lo_any : UInt<7> @@ -3483,3243 +4847,2775 @@ circuit el2_lsu : is_ldst_hi_r <= UInt<1>("h00") wire is_ldst_lo_r : UInt<1> is_ldst_lo_r <= UInt<1>("h00") - io.sec_data_hi_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 88:32] - io.sec_data_lo_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 89:32] - io.lsu_single_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 90:30] - io.lsu_double_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 91:30] - wire _T : UInt<1>[18] @[el2_lib.scala 259:18] - wire _T_1 : UInt<1>[18] @[el2_lib.scala 260:18] - wire _T_2 : UInt<1>[18] @[el2_lib.scala 261:18] - wire _T_3 : UInt<1>[15] @[el2_lib.scala 262:18] - wire _T_4 : UInt<1>[15] @[el2_lib.scala 263:18] - wire _T_5 : UInt<1>[6] @[el2_lib.scala 264:18] - node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 271:36] - _T[0] <= _T_6 @[el2_lib.scala 271:30] - node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 272:36] - _T_1[0] <= _T_7 @[el2_lib.scala 272:30] - node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 271:36] - _T[1] <= _T_8 @[el2_lib.scala 271:30] - node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 273:36] - _T_2[0] <= _T_9 @[el2_lib.scala 273:30] - node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 272:36] - _T_1[1] <= _T_10 @[el2_lib.scala 272:30] - node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 273:36] - _T_2[1] <= _T_11 @[el2_lib.scala 273:30] - node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 271:36] - _T[2] <= _T_12 @[el2_lib.scala 271:30] - node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 272:36] - _T_1[2] <= _T_13 @[el2_lib.scala 272:30] - node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 273:36] - _T_2[2] <= _T_14 @[el2_lib.scala 273:30] - node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 271:36] - _T[3] <= _T_15 @[el2_lib.scala 271:30] - node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 274:36] - _T_3[0] <= _T_16 @[el2_lib.scala 274:30] - node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 272:36] - _T_1[3] <= _T_17 @[el2_lib.scala 272:30] - node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 274:36] - _T_3[1] <= _T_18 @[el2_lib.scala 274:30] - node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 271:36] - _T[4] <= _T_19 @[el2_lib.scala 271:30] - node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 272:36] - _T_1[4] <= _T_20 @[el2_lib.scala 272:30] - node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 274:36] - _T_3[2] <= _T_21 @[el2_lib.scala 274:30] - node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 273:36] - _T_2[3] <= _T_22 @[el2_lib.scala 273:30] - node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 274:36] - _T_3[3] <= _T_23 @[el2_lib.scala 274:30] - node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 271:36] - _T[5] <= _T_24 @[el2_lib.scala 271:30] - node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 273:36] - _T_2[4] <= _T_25 @[el2_lib.scala 273:30] - node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 274:36] - _T_3[4] <= _T_26 @[el2_lib.scala 274:30] - node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 272:36] - _T_1[5] <= _T_27 @[el2_lib.scala 272:30] - node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 273:36] - _T_2[5] <= _T_28 @[el2_lib.scala 273:30] - node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 274:36] - _T_3[5] <= _T_29 @[el2_lib.scala 274:30] - node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 271:36] - _T[6] <= _T_30 @[el2_lib.scala 271:30] - node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 272:36] - _T_1[6] <= _T_31 @[el2_lib.scala 272:30] - node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 273:36] - _T_2[6] <= _T_32 @[el2_lib.scala 273:30] - node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 274:36] - _T_3[6] <= _T_33 @[el2_lib.scala 274:30] - node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 271:36] - _T[7] <= _T_34 @[el2_lib.scala 271:30] - node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 275:36] - _T_4[0] <= _T_35 @[el2_lib.scala 275:30] - node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 272:36] - _T_1[7] <= _T_36 @[el2_lib.scala 272:30] - node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 275:36] - _T_4[1] <= _T_37 @[el2_lib.scala 275:30] - node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 271:36] - _T[8] <= _T_38 @[el2_lib.scala 271:30] - node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 272:36] - _T_1[8] <= _T_39 @[el2_lib.scala 272:30] - node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 275:36] - _T_4[2] <= _T_40 @[el2_lib.scala 275:30] - node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 273:36] - _T_2[7] <= _T_41 @[el2_lib.scala 273:30] - node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 275:36] - _T_4[3] <= _T_42 @[el2_lib.scala 275:30] - node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 271:36] - _T[9] <= _T_43 @[el2_lib.scala 271:30] - node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 273:36] - _T_2[8] <= _T_44 @[el2_lib.scala 273:30] - node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 275:36] - _T_4[4] <= _T_45 @[el2_lib.scala 275:30] - node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 272:36] - _T_1[9] <= _T_46 @[el2_lib.scala 272:30] - node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 273:36] - _T_2[9] <= _T_47 @[el2_lib.scala 273:30] - node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 275:36] - _T_4[5] <= _T_48 @[el2_lib.scala 275:30] - node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 271:36] - _T[10] <= _T_49 @[el2_lib.scala 271:30] - node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 272:36] - _T_1[10] <= _T_50 @[el2_lib.scala 272:30] - node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 273:36] - _T_2[10] <= _T_51 @[el2_lib.scala 273:30] - node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 275:36] - _T_4[6] <= _T_52 @[el2_lib.scala 275:30] - node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 274:36] - _T_3[7] <= _T_53 @[el2_lib.scala 274:30] - node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 275:36] - _T_4[7] <= _T_54 @[el2_lib.scala 275:30] - node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 271:36] - _T[11] <= _T_55 @[el2_lib.scala 271:30] - node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 274:36] - _T_3[8] <= _T_56 @[el2_lib.scala 274:30] - node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 275:36] - _T_4[8] <= _T_57 @[el2_lib.scala 275:30] - node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 272:36] - _T_1[11] <= _T_58 @[el2_lib.scala 272:30] - node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 274:36] - _T_3[9] <= _T_59 @[el2_lib.scala 274:30] - node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 275:36] - _T_4[9] <= _T_60 @[el2_lib.scala 275:30] - node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 271:36] - _T[12] <= _T_61 @[el2_lib.scala 271:30] - node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 272:36] - _T_1[12] <= _T_62 @[el2_lib.scala 272:30] - node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 274:36] - _T_3[10] <= _T_63 @[el2_lib.scala 274:30] - node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 275:36] - _T_4[10] <= _T_64 @[el2_lib.scala 275:30] - node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 273:36] - _T_2[11] <= _T_65 @[el2_lib.scala 273:30] - node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 274:36] - _T_3[11] <= _T_66 @[el2_lib.scala 274:30] - node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 275:36] - _T_4[11] <= _T_67 @[el2_lib.scala 275:30] - node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 271:36] - _T[13] <= _T_68 @[el2_lib.scala 271:30] - node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 273:36] - _T_2[12] <= _T_69 @[el2_lib.scala 273:30] - node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 274:36] - _T_3[12] <= _T_70 @[el2_lib.scala 274:30] - node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 275:36] - _T_4[12] <= _T_71 @[el2_lib.scala 275:30] - node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 272:36] - _T_1[13] <= _T_72 @[el2_lib.scala 272:30] - node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 273:36] - _T_2[13] <= _T_73 @[el2_lib.scala 273:30] - node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 274:36] - _T_3[13] <= _T_74 @[el2_lib.scala 274:30] - node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 275:36] - _T_4[13] <= _T_75 @[el2_lib.scala 275:30] - node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 271:36] - _T[14] <= _T_76 @[el2_lib.scala 271:30] - node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 272:36] - _T_1[14] <= _T_77 @[el2_lib.scala 272:30] - node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 273:36] - _T_2[14] <= _T_78 @[el2_lib.scala 273:30] - node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 274:36] - _T_3[14] <= _T_79 @[el2_lib.scala 274:30] - node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 275:36] - _T_4[14] <= _T_80 @[el2_lib.scala 275:30] - node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 271:36] - _T[15] <= _T_81 @[el2_lib.scala 271:30] - node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 276:36] - _T_5[0] <= _T_82 @[el2_lib.scala 276:30] - node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 272:36] - _T_1[15] <= _T_83 @[el2_lib.scala 272:30] - node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 276:36] - _T_5[1] <= _T_84 @[el2_lib.scala 276:30] - node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 271:36] - _T[16] <= _T_85 @[el2_lib.scala 271:30] - node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 272:36] - _T_1[16] <= _T_86 @[el2_lib.scala 272:30] - node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 276:36] - _T_5[2] <= _T_87 @[el2_lib.scala 276:30] - node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 273:36] - _T_2[15] <= _T_88 @[el2_lib.scala 273:30] - node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 276:36] - _T_5[3] <= _T_89 @[el2_lib.scala 276:30] - node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 271:36] - _T[17] <= _T_90 @[el2_lib.scala 271:30] - node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 273:36] - _T_2[16] <= _T_91 @[el2_lib.scala 273:30] - node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 276:36] - _T_5[4] <= _T_92 @[el2_lib.scala 276:30] - node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 272:36] - _T_1[17] <= _T_93 @[el2_lib.scala 272:30] - node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 273:36] - _T_2[17] <= _T_94 @[el2_lib.scala 273:30] - node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 276:36] - _T_5[5] <= _T_95 @[el2_lib.scala 276:30] - node _T_96 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 279:30] - node _T_97 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 279:44] - node _T_98 = xor(_T_96, _T_97) @[el2_lib.scala 279:35] - node _T_99 = not(UInt<1>("h00")) @[el2_lib.scala 279:52] - node _T_100 = and(_T_98, _T_99) @[el2_lib.scala 279:50] - node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 279:68] - node _T_102 = cat(_T_5[2], _T_5[1]) @[el2_lib.scala 279:76] - node _T_103 = cat(_T_102, _T_5[0]) @[el2_lib.scala 279:76] - node _T_104 = cat(_T_5[5], _T_5[4]) @[el2_lib.scala 279:76] - node _T_105 = cat(_T_104, _T_5[3]) @[el2_lib.scala 279:76] - node _T_106 = cat(_T_105, _T_103) @[el2_lib.scala 279:76] - node _T_107 = xorr(_T_106) @[el2_lib.scala 279:83] - node _T_108 = xor(_T_101, _T_107) @[el2_lib.scala 279:71] - node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 279:95] - node _T_110 = cat(_T_4[2], _T_4[1]) @[el2_lib.scala 279:103] - node _T_111 = cat(_T_110, _T_4[0]) @[el2_lib.scala 279:103] - node _T_112 = cat(_T_4[4], _T_4[3]) @[el2_lib.scala 279:103] - node _T_113 = cat(_T_4[6], _T_4[5]) @[el2_lib.scala 279:103] - node _T_114 = cat(_T_113, _T_112) @[el2_lib.scala 279:103] - node _T_115 = cat(_T_114, _T_111) @[el2_lib.scala 279:103] - node _T_116 = cat(_T_4[8], _T_4[7]) @[el2_lib.scala 279:103] - node _T_117 = cat(_T_4[10], _T_4[9]) @[el2_lib.scala 279:103] - node _T_118 = cat(_T_117, _T_116) @[el2_lib.scala 279:103] - node _T_119 = cat(_T_4[12], _T_4[11]) @[el2_lib.scala 279:103] - node _T_120 = cat(_T_4[14], _T_4[13]) @[el2_lib.scala 279:103] - node _T_121 = cat(_T_120, _T_119) @[el2_lib.scala 279:103] - node _T_122 = cat(_T_121, _T_118) @[el2_lib.scala 279:103] - node _T_123 = cat(_T_122, _T_115) @[el2_lib.scala 279:103] - node _T_124 = xorr(_T_123) @[el2_lib.scala 279:110] - node _T_125 = xor(_T_109, _T_124) @[el2_lib.scala 279:98] - node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 279:122] - node _T_127 = cat(_T_3[2], _T_3[1]) @[el2_lib.scala 279:130] - node _T_128 = cat(_T_127, _T_3[0]) @[el2_lib.scala 279:130] - node _T_129 = cat(_T_3[4], _T_3[3]) @[el2_lib.scala 279:130] - node _T_130 = cat(_T_3[6], _T_3[5]) @[el2_lib.scala 279:130] - node _T_131 = cat(_T_130, _T_129) @[el2_lib.scala 279:130] - node _T_132 = cat(_T_131, _T_128) @[el2_lib.scala 279:130] - node _T_133 = cat(_T_3[8], _T_3[7]) @[el2_lib.scala 279:130] - node _T_134 = cat(_T_3[10], _T_3[9]) @[el2_lib.scala 279:130] - node _T_135 = cat(_T_134, _T_133) @[el2_lib.scala 279:130] - node _T_136 = cat(_T_3[12], _T_3[11]) @[el2_lib.scala 279:130] - node _T_137 = cat(_T_3[14], _T_3[13]) @[el2_lib.scala 279:130] - node _T_138 = cat(_T_137, _T_136) @[el2_lib.scala 279:130] - node _T_139 = cat(_T_138, _T_135) @[el2_lib.scala 279:130] - node _T_140 = cat(_T_139, _T_132) @[el2_lib.scala 279:130] - node _T_141 = xorr(_T_140) @[el2_lib.scala 279:137] - node _T_142 = xor(_T_126, _T_141) @[el2_lib.scala 279:125] - node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 279:149] - node _T_144 = cat(_T_2[1], _T_2[0]) @[el2_lib.scala 279:157] - node _T_145 = cat(_T_2[3], _T_2[2]) @[el2_lib.scala 279:157] - node _T_146 = cat(_T_145, _T_144) @[el2_lib.scala 279:157] - node _T_147 = cat(_T_2[5], _T_2[4]) @[el2_lib.scala 279:157] - node _T_148 = cat(_T_2[8], _T_2[7]) @[el2_lib.scala 279:157] - node _T_149 = cat(_T_148, _T_2[6]) @[el2_lib.scala 279:157] - node _T_150 = cat(_T_149, _T_147) @[el2_lib.scala 279:157] - node _T_151 = cat(_T_150, _T_146) @[el2_lib.scala 279:157] - node _T_152 = cat(_T_2[10], _T_2[9]) @[el2_lib.scala 279:157] - node _T_153 = cat(_T_2[12], _T_2[11]) @[el2_lib.scala 279:157] - node _T_154 = cat(_T_153, _T_152) @[el2_lib.scala 279:157] - node _T_155 = cat(_T_2[14], _T_2[13]) @[el2_lib.scala 279:157] - node _T_156 = cat(_T_2[17], _T_2[16]) @[el2_lib.scala 279:157] - node _T_157 = cat(_T_156, _T_2[15]) @[el2_lib.scala 279:157] - node _T_158 = cat(_T_157, _T_155) @[el2_lib.scala 279:157] - node _T_159 = cat(_T_158, _T_154) @[el2_lib.scala 279:157] - node _T_160 = cat(_T_159, _T_151) @[el2_lib.scala 279:157] - node _T_161 = xorr(_T_160) @[el2_lib.scala 279:164] - node _T_162 = xor(_T_143, _T_161) @[el2_lib.scala 279:152] - node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[el2_lib.scala 279:176] - node _T_164 = cat(_T_1[1], _T_1[0]) @[el2_lib.scala 279:184] - node _T_165 = cat(_T_1[3], _T_1[2]) @[el2_lib.scala 279:184] - node _T_166 = cat(_T_165, _T_164) @[el2_lib.scala 279:184] - node _T_167 = cat(_T_1[5], _T_1[4]) @[el2_lib.scala 279:184] - node _T_168 = cat(_T_1[8], _T_1[7]) @[el2_lib.scala 279:184] - node _T_169 = cat(_T_168, _T_1[6]) @[el2_lib.scala 279:184] - node _T_170 = cat(_T_169, _T_167) @[el2_lib.scala 279:184] - node _T_171 = cat(_T_170, _T_166) @[el2_lib.scala 279:184] - node _T_172 = cat(_T_1[10], _T_1[9]) @[el2_lib.scala 279:184] - node _T_173 = cat(_T_1[12], _T_1[11]) @[el2_lib.scala 279:184] - node _T_174 = cat(_T_173, _T_172) @[el2_lib.scala 279:184] - node _T_175 = cat(_T_1[14], _T_1[13]) @[el2_lib.scala 279:184] - node _T_176 = cat(_T_1[17], _T_1[16]) @[el2_lib.scala 279:184] - node _T_177 = cat(_T_176, _T_1[15]) @[el2_lib.scala 279:184] - node _T_178 = cat(_T_177, _T_175) @[el2_lib.scala 279:184] - node _T_179 = cat(_T_178, _T_174) @[el2_lib.scala 279:184] - node _T_180 = cat(_T_179, _T_171) @[el2_lib.scala 279:184] - node _T_181 = xorr(_T_180) @[el2_lib.scala 279:191] - node _T_182 = xor(_T_163, _T_181) @[el2_lib.scala 279:179] - node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[el2_lib.scala 279:203] - node _T_184 = cat(_T[1], _T[0]) @[el2_lib.scala 279:211] - node _T_185 = cat(_T[3], _T[2]) @[el2_lib.scala 279:211] - node _T_186 = cat(_T_185, _T_184) @[el2_lib.scala 279:211] - node _T_187 = cat(_T[5], _T[4]) @[el2_lib.scala 279:211] - node _T_188 = cat(_T[8], _T[7]) @[el2_lib.scala 279:211] - node _T_189 = cat(_T_188, _T[6]) @[el2_lib.scala 279:211] - node _T_190 = cat(_T_189, _T_187) @[el2_lib.scala 279:211] - node _T_191 = cat(_T_190, _T_186) @[el2_lib.scala 279:211] - node _T_192 = cat(_T[10], _T[9]) @[el2_lib.scala 279:211] - node _T_193 = cat(_T[12], _T[11]) @[el2_lib.scala 279:211] - node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 279:211] - node _T_195 = cat(_T[14], _T[13]) @[el2_lib.scala 279:211] - node _T_196 = cat(_T[17], _T[16]) @[el2_lib.scala 279:211] - node _T_197 = cat(_T_196, _T[15]) @[el2_lib.scala 279:211] - node _T_198 = cat(_T_197, _T_195) @[el2_lib.scala 279:211] - node _T_199 = cat(_T_198, _T_194) @[el2_lib.scala 279:211] - node _T_200 = cat(_T_199, _T_191) @[el2_lib.scala 279:211] - node _T_201 = xorr(_T_200) @[el2_lib.scala 279:218] - node _T_202 = xor(_T_183, _T_201) @[el2_lib.scala 279:206] + io.sec_data_hi_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 90:32] + io.sec_data_lo_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 91:32] + io.lsu_single_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 92:30] + io.lsu_double_ecc_error_m <= UInt<1>("h00") @[el2_lsu_ecc.scala 93:30] + wire _T : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_1 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_2 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_3 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_4 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_5 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_6 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 325:36] + _T[0] <= _T_6 @[el2_lib.scala 325:30] + node _T_7 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 326:36] + _T_1[0] <= _T_7 @[el2_lib.scala 326:30] + node _T_8 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 325:36] + _T[1] <= _T_8 @[el2_lib.scala 325:30] + node _T_9 = bits(dccm_rdata_hi_any, 1, 1) @[el2_lib.scala 327:36] + _T_2[0] <= _T_9 @[el2_lib.scala 327:30] + node _T_10 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 326:36] + _T_1[1] <= _T_10 @[el2_lib.scala 326:30] + node _T_11 = bits(dccm_rdata_hi_any, 2, 2) @[el2_lib.scala 327:36] + _T_2[1] <= _T_11 @[el2_lib.scala 327:30] + node _T_12 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 325:36] + _T[2] <= _T_12 @[el2_lib.scala 325:30] + node _T_13 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 326:36] + _T_1[2] <= _T_13 @[el2_lib.scala 326:30] + node _T_14 = bits(dccm_rdata_hi_any, 3, 3) @[el2_lib.scala 327:36] + _T_2[2] <= _T_14 @[el2_lib.scala 327:30] + node _T_15 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 325:36] + _T[3] <= _T_15 @[el2_lib.scala 325:30] + node _T_16 = bits(dccm_rdata_hi_any, 4, 4) @[el2_lib.scala 328:36] + _T_3[0] <= _T_16 @[el2_lib.scala 328:30] + node _T_17 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 326:36] + _T_1[3] <= _T_17 @[el2_lib.scala 326:30] + node _T_18 = bits(dccm_rdata_hi_any, 5, 5) @[el2_lib.scala 328:36] + _T_3[1] <= _T_18 @[el2_lib.scala 328:30] + node _T_19 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 325:36] + _T[4] <= _T_19 @[el2_lib.scala 325:30] + node _T_20 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 326:36] + _T_1[4] <= _T_20 @[el2_lib.scala 326:30] + node _T_21 = bits(dccm_rdata_hi_any, 6, 6) @[el2_lib.scala 328:36] + _T_3[2] <= _T_21 @[el2_lib.scala 328:30] + node _T_22 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 327:36] + _T_2[3] <= _T_22 @[el2_lib.scala 327:30] + node _T_23 = bits(dccm_rdata_hi_any, 7, 7) @[el2_lib.scala 328:36] + _T_3[3] <= _T_23 @[el2_lib.scala 328:30] + node _T_24 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 325:36] + _T[5] <= _T_24 @[el2_lib.scala 325:30] + node _T_25 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 327:36] + _T_2[4] <= _T_25 @[el2_lib.scala 327:30] + node _T_26 = bits(dccm_rdata_hi_any, 8, 8) @[el2_lib.scala 328:36] + _T_3[4] <= _T_26 @[el2_lib.scala 328:30] + node _T_27 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 326:36] + _T_1[5] <= _T_27 @[el2_lib.scala 326:30] + node _T_28 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 327:36] + _T_2[5] <= _T_28 @[el2_lib.scala 327:30] + node _T_29 = bits(dccm_rdata_hi_any, 9, 9) @[el2_lib.scala 328:36] + _T_3[5] <= _T_29 @[el2_lib.scala 328:30] + node _T_30 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 325:36] + _T[6] <= _T_30 @[el2_lib.scala 325:30] + node _T_31 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 326:36] + _T_1[6] <= _T_31 @[el2_lib.scala 326:30] + node _T_32 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 327:36] + _T_2[6] <= _T_32 @[el2_lib.scala 327:30] + node _T_33 = bits(dccm_rdata_hi_any, 10, 10) @[el2_lib.scala 328:36] + _T_3[6] <= _T_33 @[el2_lib.scala 328:30] + node _T_34 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 325:36] + _T[7] <= _T_34 @[el2_lib.scala 325:30] + node _T_35 = bits(dccm_rdata_hi_any, 11, 11) @[el2_lib.scala 329:36] + _T_4[0] <= _T_35 @[el2_lib.scala 329:30] + node _T_36 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 326:36] + _T_1[7] <= _T_36 @[el2_lib.scala 326:30] + node _T_37 = bits(dccm_rdata_hi_any, 12, 12) @[el2_lib.scala 329:36] + _T_4[1] <= _T_37 @[el2_lib.scala 329:30] + node _T_38 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 325:36] + _T[8] <= _T_38 @[el2_lib.scala 325:30] + node _T_39 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 326:36] + _T_1[8] <= _T_39 @[el2_lib.scala 326:30] + node _T_40 = bits(dccm_rdata_hi_any, 13, 13) @[el2_lib.scala 329:36] + _T_4[2] <= _T_40 @[el2_lib.scala 329:30] + node _T_41 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 327:36] + _T_2[7] <= _T_41 @[el2_lib.scala 327:30] + node _T_42 = bits(dccm_rdata_hi_any, 14, 14) @[el2_lib.scala 329:36] + _T_4[3] <= _T_42 @[el2_lib.scala 329:30] + node _T_43 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 325:36] + _T[9] <= _T_43 @[el2_lib.scala 325:30] + node _T_44 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 327:36] + _T_2[8] <= _T_44 @[el2_lib.scala 327:30] + node _T_45 = bits(dccm_rdata_hi_any, 15, 15) @[el2_lib.scala 329:36] + _T_4[4] <= _T_45 @[el2_lib.scala 329:30] + node _T_46 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 326:36] + _T_1[9] <= _T_46 @[el2_lib.scala 326:30] + node _T_47 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 327:36] + _T_2[9] <= _T_47 @[el2_lib.scala 327:30] + node _T_48 = bits(dccm_rdata_hi_any, 16, 16) @[el2_lib.scala 329:36] + _T_4[5] <= _T_48 @[el2_lib.scala 329:30] + node _T_49 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 325:36] + _T[10] <= _T_49 @[el2_lib.scala 325:30] + node _T_50 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 326:36] + _T_1[10] <= _T_50 @[el2_lib.scala 326:30] + node _T_51 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 327:36] + _T_2[10] <= _T_51 @[el2_lib.scala 327:30] + node _T_52 = bits(dccm_rdata_hi_any, 17, 17) @[el2_lib.scala 329:36] + _T_4[6] <= _T_52 @[el2_lib.scala 329:30] + node _T_53 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 328:36] + _T_3[7] <= _T_53 @[el2_lib.scala 328:30] + node _T_54 = bits(dccm_rdata_hi_any, 18, 18) @[el2_lib.scala 329:36] + _T_4[7] <= _T_54 @[el2_lib.scala 329:30] + node _T_55 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 325:36] + _T[11] <= _T_55 @[el2_lib.scala 325:30] + node _T_56 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 328:36] + _T_3[8] <= _T_56 @[el2_lib.scala 328:30] + node _T_57 = bits(dccm_rdata_hi_any, 19, 19) @[el2_lib.scala 329:36] + _T_4[8] <= _T_57 @[el2_lib.scala 329:30] + node _T_58 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 326:36] + _T_1[11] <= _T_58 @[el2_lib.scala 326:30] + node _T_59 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 328:36] + _T_3[9] <= _T_59 @[el2_lib.scala 328:30] + node _T_60 = bits(dccm_rdata_hi_any, 20, 20) @[el2_lib.scala 329:36] + _T_4[9] <= _T_60 @[el2_lib.scala 329:30] + node _T_61 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 325:36] + _T[12] <= _T_61 @[el2_lib.scala 325:30] + node _T_62 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 326:36] + _T_1[12] <= _T_62 @[el2_lib.scala 326:30] + node _T_63 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 328:36] + _T_3[10] <= _T_63 @[el2_lib.scala 328:30] + node _T_64 = bits(dccm_rdata_hi_any, 21, 21) @[el2_lib.scala 329:36] + _T_4[10] <= _T_64 @[el2_lib.scala 329:30] + node _T_65 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 327:36] + _T_2[11] <= _T_65 @[el2_lib.scala 327:30] + node _T_66 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 328:36] + _T_3[11] <= _T_66 @[el2_lib.scala 328:30] + node _T_67 = bits(dccm_rdata_hi_any, 22, 22) @[el2_lib.scala 329:36] + _T_4[11] <= _T_67 @[el2_lib.scala 329:30] + node _T_68 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 325:36] + _T[13] <= _T_68 @[el2_lib.scala 325:30] + node _T_69 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 327:36] + _T_2[12] <= _T_69 @[el2_lib.scala 327:30] + node _T_70 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 328:36] + _T_3[12] <= _T_70 @[el2_lib.scala 328:30] + node _T_71 = bits(dccm_rdata_hi_any, 23, 23) @[el2_lib.scala 329:36] + _T_4[12] <= _T_71 @[el2_lib.scala 329:30] + node _T_72 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 326:36] + _T_1[13] <= _T_72 @[el2_lib.scala 326:30] + node _T_73 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 327:36] + _T_2[13] <= _T_73 @[el2_lib.scala 327:30] + node _T_74 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 328:36] + _T_3[13] <= _T_74 @[el2_lib.scala 328:30] + node _T_75 = bits(dccm_rdata_hi_any, 24, 24) @[el2_lib.scala 329:36] + _T_4[13] <= _T_75 @[el2_lib.scala 329:30] + node _T_76 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 325:36] + _T[14] <= _T_76 @[el2_lib.scala 325:30] + node _T_77 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 326:36] + _T_1[14] <= _T_77 @[el2_lib.scala 326:30] + node _T_78 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 327:36] + _T_2[14] <= _T_78 @[el2_lib.scala 327:30] + node _T_79 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 328:36] + _T_3[14] <= _T_79 @[el2_lib.scala 328:30] + node _T_80 = bits(dccm_rdata_hi_any, 25, 25) @[el2_lib.scala 329:36] + _T_4[14] <= _T_80 @[el2_lib.scala 329:30] + node _T_81 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 325:36] + _T[15] <= _T_81 @[el2_lib.scala 325:30] + node _T_82 = bits(dccm_rdata_hi_any, 26, 26) @[el2_lib.scala 330:36] + _T_5[0] <= _T_82 @[el2_lib.scala 330:30] + node _T_83 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 326:36] + _T_1[15] <= _T_83 @[el2_lib.scala 326:30] + node _T_84 = bits(dccm_rdata_hi_any, 27, 27) @[el2_lib.scala 330:36] + _T_5[1] <= _T_84 @[el2_lib.scala 330:30] + node _T_85 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 325:36] + _T[16] <= _T_85 @[el2_lib.scala 325:30] + node _T_86 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 326:36] + _T_1[16] <= _T_86 @[el2_lib.scala 326:30] + node _T_87 = bits(dccm_rdata_hi_any, 28, 28) @[el2_lib.scala 330:36] + _T_5[2] <= _T_87 @[el2_lib.scala 330:30] + node _T_88 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 327:36] + _T_2[15] <= _T_88 @[el2_lib.scala 327:30] + node _T_89 = bits(dccm_rdata_hi_any, 29, 29) @[el2_lib.scala 330:36] + _T_5[3] <= _T_89 @[el2_lib.scala 330:30] + node _T_90 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 325:36] + _T[17] <= _T_90 @[el2_lib.scala 325:30] + node _T_91 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 327:36] + _T_2[16] <= _T_91 @[el2_lib.scala 327:30] + node _T_92 = bits(dccm_rdata_hi_any, 30, 30) @[el2_lib.scala 330:36] + _T_5[4] <= _T_92 @[el2_lib.scala 330:30] + node _T_93 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 326:36] + _T_1[17] <= _T_93 @[el2_lib.scala 326:30] + node _T_94 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 327:36] + _T_2[17] <= _T_94 @[el2_lib.scala 327:30] + node _T_95 = bits(dccm_rdata_hi_any, 31, 31) @[el2_lib.scala 330:36] + _T_5[5] <= _T_95 @[el2_lib.scala 330:30] + node _T_96 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 333:30] + node _T_97 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 333:44] + node _T_98 = xor(_T_96, _T_97) @[el2_lib.scala 333:35] + node _T_99 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_100 = and(_T_98, _T_99) @[el2_lib.scala 333:50] + node _T_101 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 333:68] + node _T_102 = cat(_T_5[2], _T_5[1]) @[el2_lib.scala 333:76] + node _T_103 = cat(_T_102, _T_5[0]) @[el2_lib.scala 333:76] + node _T_104 = cat(_T_5[5], _T_5[4]) @[el2_lib.scala 333:76] + node _T_105 = cat(_T_104, _T_5[3]) @[el2_lib.scala 333:76] + node _T_106 = cat(_T_105, _T_103) @[el2_lib.scala 333:76] + node _T_107 = xorr(_T_106) @[el2_lib.scala 333:83] + node _T_108 = xor(_T_101, _T_107) @[el2_lib.scala 333:71] + node _T_109 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 333:95] + node _T_110 = cat(_T_4[2], _T_4[1]) @[el2_lib.scala 333:103] + node _T_111 = cat(_T_110, _T_4[0]) @[el2_lib.scala 333:103] + node _T_112 = cat(_T_4[4], _T_4[3]) @[el2_lib.scala 333:103] + node _T_113 = cat(_T_4[6], _T_4[5]) @[el2_lib.scala 333:103] + node _T_114 = cat(_T_113, _T_112) @[el2_lib.scala 333:103] + node _T_115 = cat(_T_114, _T_111) @[el2_lib.scala 333:103] + node _T_116 = cat(_T_4[8], _T_4[7]) @[el2_lib.scala 333:103] + node _T_117 = cat(_T_4[10], _T_4[9]) @[el2_lib.scala 333:103] + node _T_118 = cat(_T_117, _T_116) @[el2_lib.scala 333:103] + node _T_119 = cat(_T_4[12], _T_4[11]) @[el2_lib.scala 333:103] + node _T_120 = cat(_T_4[14], _T_4[13]) @[el2_lib.scala 333:103] + node _T_121 = cat(_T_120, _T_119) @[el2_lib.scala 333:103] + node _T_122 = cat(_T_121, _T_118) @[el2_lib.scala 333:103] + node _T_123 = cat(_T_122, _T_115) @[el2_lib.scala 333:103] + node _T_124 = xorr(_T_123) @[el2_lib.scala 333:110] + node _T_125 = xor(_T_109, _T_124) @[el2_lib.scala 333:98] + node _T_126 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 333:122] + node _T_127 = cat(_T_3[2], _T_3[1]) @[el2_lib.scala 333:130] + node _T_128 = cat(_T_127, _T_3[0]) @[el2_lib.scala 333:130] + node _T_129 = cat(_T_3[4], _T_3[3]) @[el2_lib.scala 333:130] + node _T_130 = cat(_T_3[6], _T_3[5]) @[el2_lib.scala 333:130] + node _T_131 = cat(_T_130, _T_129) @[el2_lib.scala 333:130] + node _T_132 = cat(_T_131, _T_128) @[el2_lib.scala 333:130] + node _T_133 = cat(_T_3[8], _T_3[7]) @[el2_lib.scala 333:130] + node _T_134 = cat(_T_3[10], _T_3[9]) @[el2_lib.scala 333:130] + node _T_135 = cat(_T_134, _T_133) @[el2_lib.scala 333:130] + node _T_136 = cat(_T_3[12], _T_3[11]) @[el2_lib.scala 333:130] + node _T_137 = cat(_T_3[14], _T_3[13]) @[el2_lib.scala 333:130] + node _T_138 = cat(_T_137, _T_136) @[el2_lib.scala 333:130] + node _T_139 = cat(_T_138, _T_135) @[el2_lib.scala 333:130] + node _T_140 = cat(_T_139, _T_132) @[el2_lib.scala 333:130] + node _T_141 = xorr(_T_140) @[el2_lib.scala 333:137] + node _T_142 = xor(_T_126, _T_141) @[el2_lib.scala 333:125] + node _T_143 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 333:149] + node _T_144 = cat(_T_2[1], _T_2[0]) @[el2_lib.scala 333:157] + node _T_145 = cat(_T_2[3], _T_2[2]) @[el2_lib.scala 333:157] + node _T_146 = cat(_T_145, _T_144) @[el2_lib.scala 333:157] + node _T_147 = cat(_T_2[5], _T_2[4]) @[el2_lib.scala 333:157] + node _T_148 = cat(_T_2[8], _T_2[7]) @[el2_lib.scala 333:157] + node _T_149 = cat(_T_148, _T_2[6]) @[el2_lib.scala 333:157] + node _T_150 = cat(_T_149, _T_147) @[el2_lib.scala 333:157] + node _T_151 = cat(_T_150, _T_146) @[el2_lib.scala 333:157] + node _T_152 = cat(_T_2[10], _T_2[9]) @[el2_lib.scala 333:157] + node _T_153 = cat(_T_2[12], _T_2[11]) @[el2_lib.scala 333:157] + node _T_154 = cat(_T_153, _T_152) @[el2_lib.scala 333:157] + node _T_155 = cat(_T_2[14], _T_2[13]) @[el2_lib.scala 333:157] + node _T_156 = cat(_T_2[17], _T_2[16]) @[el2_lib.scala 333:157] + node _T_157 = cat(_T_156, _T_2[15]) @[el2_lib.scala 333:157] + node _T_158 = cat(_T_157, _T_155) @[el2_lib.scala 333:157] + node _T_159 = cat(_T_158, _T_154) @[el2_lib.scala 333:157] + node _T_160 = cat(_T_159, _T_151) @[el2_lib.scala 333:157] + node _T_161 = xorr(_T_160) @[el2_lib.scala 333:164] + node _T_162 = xor(_T_143, _T_161) @[el2_lib.scala 333:152] + node _T_163 = bits(dccm_data_ecc_hi_any, 1, 1) @[el2_lib.scala 333:176] + node _T_164 = cat(_T_1[1], _T_1[0]) @[el2_lib.scala 333:184] + node _T_165 = cat(_T_1[3], _T_1[2]) @[el2_lib.scala 333:184] + node _T_166 = cat(_T_165, _T_164) @[el2_lib.scala 333:184] + node _T_167 = cat(_T_1[5], _T_1[4]) @[el2_lib.scala 333:184] + node _T_168 = cat(_T_1[8], _T_1[7]) @[el2_lib.scala 333:184] + node _T_169 = cat(_T_168, _T_1[6]) @[el2_lib.scala 333:184] + node _T_170 = cat(_T_169, _T_167) @[el2_lib.scala 333:184] + node _T_171 = cat(_T_170, _T_166) @[el2_lib.scala 333:184] + node _T_172 = cat(_T_1[10], _T_1[9]) @[el2_lib.scala 333:184] + node _T_173 = cat(_T_1[12], _T_1[11]) @[el2_lib.scala 333:184] + node _T_174 = cat(_T_173, _T_172) @[el2_lib.scala 333:184] + node _T_175 = cat(_T_1[14], _T_1[13]) @[el2_lib.scala 333:184] + node _T_176 = cat(_T_1[17], _T_1[16]) @[el2_lib.scala 333:184] + node _T_177 = cat(_T_176, _T_1[15]) @[el2_lib.scala 333:184] + node _T_178 = cat(_T_177, _T_175) @[el2_lib.scala 333:184] + node _T_179 = cat(_T_178, _T_174) @[el2_lib.scala 333:184] + node _T_180 = cat(_T_179, _T_171) @[el2_lib.scala 333:184] + node _T_181 = xorr(_T_180) @[el2_lib.scala 333:191] + node _T_182 = xor(_T_163, _T_181) @[el2_lib.scala 333:179] + node _T_183 = bits(dccm_data_ecc_hi_any, 0, 0) @[el2_lib.scala 333:203] + node _T_184 = cat(_T[1], _T[0]) @[el2_lib.scala 333:211] + node _T_185 = cat(_T[3], _T[2]) @[el2_lib.scala 333:211] + node _T_186 = cat(_T_185, _T_184) @[el2_lib.scala 333:211] + node _T_187 = cat(_T[5], _T[4]) @[el2_lib.scala 333:211] + node _T_188 = cat(_T[8], _T[7]) @[el2_lib.scala 333:211] + node _T_189 = cat(_T_188, _T[6]) @[el2_lib.scala 333:211] + node _T_190 = cat(_T_189, _T_187) @[el2_lib.scala 333:211] + node _T_191 = cat(_T_190, _T_186) @[el2_lib.scala 333:211] + node _T_192 = cat(_T[10], _T[9]) @[el2_lib.scala 333:211] + node _T_193 = cat(_T[12], _T[11]) @[el2_lib.scala 333:211] + node _T_194 = cat(_T_193, _T_192) @[el2_lib.scala 333:211] + node _T_195 = cat(_T[14], _T[13]) @[el2_lib.scala 333:211] + node _T_196 = cat(_T[17], _T[16]) @[el2_lib.scala 333:211] + node _T_197 = cat(_T_196, _T[15]) @[el2_lib.scala 333:211] + node _T_198 = cat(_T_197, _T_195) @[el2_lib.scala 333:211] + node _T_199 = cat(_T_198, _T_194) @[el2_lib.scala 333:211] + node _T_200 = cat(_T_199, _T_191) @[el2_lib.scala 333:211] + node _T_201 = xorr(_T_200) @[el2_lib.scala 333:218] + node _T_202 = xor(_T_183, _T_201) @[el2_lib.scala 333:206] node _T_203 = cat(_T_162, _T_182) @[Cat.scala 29:58] node _T_204 = cat(_T_203, _T_202) @[Cat.scala 29:58] node _T_205 = cat(_T_125, _T_142) @[Cat.scala 29:58] node _T_206 = cat(_T_100, _T_108) @[Cat.scala 29:58] node _T_207 = cat(_T_206, _T_205) @[Cat.scala 29:58] node _T_208 = cat(_T_207, _T_204) @[Cat.scala 29:58] - node _T_209 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 281:44] - node _T_210 = and(is_ldst_hi_any, _T_209) @[el2_lib.scala 281:32] - node _T_211 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 281:60] - node _T_212 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 281:74] - node _T_213 = xor(_T_211, _T_212) @[el2_lib.scala 281:65] - node _T_214 = not(UInt<1>("h00")) @[el2_lib.scala 281:82] - node _T_215 = and(_T_213, _T_214) @[el2_lib.scala 281:80] - node single_ecc_error_hi_any = and(_T_210, _T_215) @[el2_lib.scala 281:52] - node _T_216 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 282:44] - node _T_217 = and(is_ldst_hi_any, _T_216) @[el2_lib.scala 282:32] - node _T_218 = xorr(dccm_rdata_hi_any) @[el2_lib.scala 282:60] - node _T_219 = xorr(dccm_data_ecc_hi_any) @[el2_lib.scala 282:74] - node _T_220 = xor(_T_218, _T_219) @[el2_lib.scala 282:65] - node _T_221 = not(UInt<1>("h00")) @[el2_lib.scala 282:82] - node _T_222 = and(_T_220, _T_221) @[el2_lib.scala 282:80] - node double_ecc_error_hi_any = and(_T_217, _T_222) @[el2_lib.scala 282:52] - wire _T_223 : UInt<1>[39] @[el2_lib.scala 283:26] - node _T_224 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_225 = eq(_T_224, UInt<1>("h01")) @[el2_lib.scala 286:41] - _T_223[0] <= _T_225 @[el2_lib.scala 286:23] - node _T_226 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_227 = eq(_T_226, UInt<2>("h02")) @[el2_lib.scala 286:41] - _T_223[1] <= _T_227 @[el2_lib.scala 286:23] - node _T_228 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_229 = eq(_T_228, UInt<2>("h03")) @[el2_lib.scala 286:41] - _T_223[2] <= _T_229 @[el2_lib.scala 286:23] - node _T_230 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_231 = eq(_T_230, UInt<3>("h04")) @[el2_lib.scala 286:41] - _T_223[3] <= _T_231 @[el2_lib.scala 286:23] - node _T_232 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_233 = eq(_T_232, UInt<3>("h05")) @[el2_lib.scala 286:41] - _T_223[4] <= _T_233 @[el2_lib.scala 286:23] - node _T_234 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_235 = eq(_T_234, UInt<3>("h06")) @[el2_lib.scala 286:41] - _T_223[5] <= _T_235 @[el2_lib.scala 286:23] - node _T_236 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_237 = eq(_T_236, UInt<3>("h07")) @[el2_lib.scala 286:41] - _T_223[6] <= _T_237 @[el2_lib.scala 286:23] - node _T_238 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_239 = eq(_T_238, UInt<4>("h08")) @[el2_lib.scala 286:41] - _T_223[7] <= _T_239 @[el2_lib.scala 286:23] - node _T_240 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_241 = eq(_T_240, UInt<4>("h09")) @[el2_lib.scala 286:41] - _T_223[8] <= _T_241 @[el2_lib.scala 286:23] - node _T_242 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_243 = eq(_T_242, UInt<4>("h0a")) @[el2_lib.scala 286:41] - _T_223[9] <= _T_243 @[el2_lib.scala 286:23] - node _T_244 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_245 = eq(_T_244, UInt<4>("h0b")) @[el2_lib.scala 286:41] - _T_223[10] <= _T_245 @[el2_lib.scala 286:23] - node _T_246 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_247 = eq(_T_246, UInt<4>("h0c")) @[el2_lib.scala 286:41] - _T_223[11] <= _T_247 @[el2_lib.scala 286:23] - node _T_248 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_249 = eq(_T_248, UInt<4>("h0d")) @[el2_lib.scala 286:41] - _T_223[12] <= _T_249 @[el2_lib.scala 286:23] - node _T_250 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_251 = eq(_T_250, UInt<4>("h0e")) @[el2_lib.scala 286:41] - _T_223[13] <= _T_251 @[el2_lib.scala 286:23] - node _T_252 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_253 = eq(_T_252, UInt<4>("h0f")) @[el2_lib.scala 286:41] - _T_223[14] <= _T_253 @[el2_lib.scala 286:23] - node _T_254 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_255 = eq(_T_254, UInt<5>("h010")) @[el2_lib.scala 286:41] - _T_223[15] <= _T_255 @[el2_lib.scala 286:23] - node _T_256 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_257 = eq(_T_256, UInt<5>("h011")) @[el2_lib.scala 286:41] - _T_223[16] <= _T_257 @[el2_lib.scala 286:23] - node _T_258 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_259 = eq(_T_258, UInt<5>("h012")) @[el2_lib.scala 286:41] - _T_223[17] <= _T_259 @[el2_lib.scala 286:23] - node _T_260 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_261 = eq(_T_260, UInt<5>("h013")) @[el2_lib.scala 286:41] - _T_223[18] <= _T_261 @[el2_lib.scala 286:23] - node _T_262 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_263 = eq(_T_262, UInt<5>("h014")) @[el2_lib.scala 286:41] - _T_223[19] <= _T_263 @[el2_lib.scala 286:23] - node _T_264 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_265 = eq(_T_264, UInt<5>("h015")) @[el2_lib.scala 286:41] - _T_223[20] <= _T_265 @[el2_lib.scala 286:23] - node _T_266 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_267 = eq(_T_266, UInt<5>("h016")) @[el2_lib.scala 286:41] - _T_223[21] <= _T_267 @[el2_lib.scala 286:23] - node _T_268 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_269 = eq(_T_268, UInt<5>("h017")) @[el2_lib.scala 286:41] - _T_223[22] <= _T_269 @[el2_lib.scala 286:23] - node _T_270 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_271 = eq(_T_270, UInt<5>("h018")) @[el2_lib.scala 286:41] - _T_223[23] <= _T_271 @[el2_lib.scala 286:23] - node _T_272 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_273 = eq(_T_272, UInt<5>("h019")) @[el2_lib.scala 286:41] - _T_223[24] <= _T_273 @[el2_lib.scala 286:23] - node _T_274 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_275 = eq(_T_274, UInt<5>("h01a")) @[el2_lib.scala 286:41] - _T_223[25] <= _T_275 @[el2_lib.scala 286:23] - node _T_276 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_277 = eq(_T_276, UInt<5>("h01b")) @[el2_lib.scala 286:41] - _T_223[26] <= _T_277 @[el2_lib.scala 286:23] - node _T_278 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_279 = eq(_T_278, UInt<5>("h01c")) @[el2_lib.scala 286:41] - _T_223[27] <= _T_279 @[el2_lib.scala 286:23] - node _T_280 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_281 = eq(_T_280, UInt<5>("h01d")) @[el2_lib.scala 286:41] - _T_223[28] <= _T_281 @[el2_lib.scala 286:23] - node _T_282 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_283 = eq(_T_282, UInt<5>("h01e")) @[el2_lib.scala 286:41] - _T_223[29] <= _T_283 @[el2_lib.scala 286:23] - node _T_284 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_285 = eq(_T_284, UInt<5>("h01f")) @[el2_lib.scala 286:41] - _T_223[30] <= _T_285 @[el2_lib.scala 286:23] - node _T_286 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_287 = eq(_T_286, UInt<6>("h020")) @[el2_lib.scala 286:41] - _T_223[31] <= _T_287 @[el2_lib.scala 286:23] - node _T_288 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_289 = eq(_T_288, UInt<6>("h021")) @[el2_lib.scala 286:41] - _T_223[32] <= _T_289 @[el2_lib.scala 286:23] - node _T_290 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_291 = eq(_T_290, UInt<6>("h022")) @[el2_lib.scala 286:41] - _T_223[33] <= _T_291 @[el2_lib.scala 286:23] - node _T_292 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_293 = eq(_T_292, UInt<6>("h023")) @[el2_lib.scala 286:41] - _T_223[34] <= _T_293 @[el2_lib.scala 286:23] - node _T_294 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_295 = eq(_T_294, UInt<6>("h024")) @[el2_lib.scala 286:41] - _T_223[35] <= _T_295 @[el2_lib.scala 286:23] - node _T_296 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_297 = eq(_T_296, UInt<6>("h025")) @[el2_lib.scala 286:41] - _T_223[36] <= _T_297 @[el2_lib.scala 286:23] - node _T_298 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_299 = eq(_T_298, UInt<6>("h026")) @[el2_lib.scala 286:41] - _T_223[37] <= _T_299 @[el2_lib.scala 286:23] - node _T_300 = bits(_T_208, 5, 0) @[el2_lib.scala 286:35] - node _T_301 = eq(_T_300, UInt<6>("h027")) @[el2_lib.scala 286:41] - _T_223[38] <= _T_301 @[el2_lib.scala 286:23] - node _T_302 = bits(dccm_data_ecc_hi_any, 6, 6) @[el2_lib.scala 288:37] - node _T_303 = bits(dccm_rdata_hi_any, 31, 26) @[el2_lib.scala 288:45] - node _T_304 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 288:60] - node _T_305 = bits(dccm_rdata_hi_any, 25, 11) @[el2_lib.scala 288:68] - node _T_306 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 288:83] - node _T_307 = bits(dccm_rdata_hi_any, 10, 4) @[el2_lib.scala 288:91] - node _T_308 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 288:105] - node _T_309 = bits(dccm_rdata_hi_any, 3, 1) @[el2_lib.scala 288:113] - node _T_310 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 288:126] - node _T_311 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 288:134] - node _T_312 = bits(dccm_data_ecc_hi_any, 1, 0) @[el2_lib.scala 288:145] - node _T_313 = cat(_T_311, _T_312) @[Cat.scala 29:58] - node _T_314 = cat(_T_308, _T_309) @[Cat.scala 29:58] - node _T_315 = cat(_T_314, _T_310) @[Cat.scala 29:58] - node _T_316 = cat(_T_315, _T_313) @[Cat.scala 29:58] - node _T_317 = cat(_T_305, _T_306) @[Cat.scala 29:58] - node _T_318 = cat(_T_317, _T_307) @[Cat.scala 29:58] - node _T_319 = cat(_T_302, _T_303) @[Cat.scala 29:58] - node _T_320 = cat(_T_319, _T_304) @[Cat.scala 29:58] - node _T_321 = cat(_T_320, _T_318) @[Cat.scala 29:58] - node _T_322 = cat(_T_321, _T_316) @[Cat.scala 29:58] - node _T_323 = bits(single_ecc_error_hi_any, 0, 0) @[el2_lib.scala 289:49] - node _T_324 = cat(_T_223[1], _T_223[0]) @[el2_lib.scala 289:69] - node _T_325 = cat(_T_223[3], _T_223[2]) @[el2_lib.scala 289:69] - node _T_326 = cat(_T_325, _T_324) @[el2_lib.scala 289:69] - node _T_327 = cat(_T_223[5], _T_223[4]) @[el2_lib.scala 289:69] - node _T_328 = cat(_T_223[8], _T_223[7]) @[el2_lib.scala 289:69] - node _T_329 = cat(_T_328, _T_223[6]) @[el2_lib.scala 289:69] - node _T_330 = cat(_T_329, _T_327) @[el2_lib.scala 289:69] - node _T_331 = cat(_T_330, _T_326) @[el2_lib.scala 289:69] - node _T_332 = cat(_T_223[10], _T_223[9]) @[el2_lib.scala 289:69] - node _T_333 = cat(_T_223[13], _T_223[12]) @[el2_lib.scala 289:69] - node _T_334 = cat(_T_333, _T_223[11]) @[el2_lib.scala 289:69] - node _T_335 = cat(_T_334, _T_332) @[el2_lib.scala 289:69] - node _T_336 = cat(_T_223[15], _T_223[14]) @[el2_lib.scala 289:69] - node _T_337 = cat(_T_223[18], _T_223[17]) @[el2_lib.scala 289:69] - node _T_338 = cat(_T_337, _T_223[16]) @[el2_lib.scala 289:69] - node _T_339 = cat(_T_338, _T_336) @[el2_lib.scala 289:69] - node _T_340 = cat(_T_339, _T_335) @[el2_lib.scala 289:69] - node _T_341 = cat(_T_340, _T_331) @[el2_lib.scala 289:69] - node _T_342 = cat(_T_223[20], _T_223[19]) @[el2_lib.scala 289:69] - node _T_343 = cat(_T_223[23], _T_223[22]) @[el2_lib.scala 289:69] - node _T_344 = cat(_T_343, _T_223[21]) @[el2_lib.scala 289:69] - node _T_345 = cat(_T_344, _T_342) @[el2_lib.scala 289:69] - node _T_346 = cat(_T_223[25], _T_223[24]) @[el2_lib.scala 289:69] - node _T_347 = cat(_T_223[28], _T_223[27]) @[el2_lib.scala 289:69] - node _T_348 = cat(_T_347, _T_223[26]) @[el2_lib.scala 289:69] - node _T_349 = cat(_T_348, _T_346) @[el2_lib.scala 289:69] - node _T_350 = cat(_T_349, _T_345) @[el2_lib.scala 289:69] - node _T_351 = cat(_T_223[30], _T_223[29]) @[el2_lib.scala 289:69] - node _T_352 = cat(_T_223[33], _T_223[32]) @[el2_lib.scala 289:69] - node _T_353 = cat(_T_352, _T_223[31]) @[el2_lib.scala 289:69] - node _T_354 = cat(_T_353, _T_351) @[el2_lib.scala 289:69] - node _T_355 = cat(_T_223[35], _T_223[34]) @[el2_lib.scala 289:69] - node _T_356 = cat(_T_223[38], _T_223[37]) @[el2_lib.scala 289:69] - node _T_357 = cat(_T_356, _T_223[36]) @[el2_lib.scala 289:69] - node _T_358 = cat(_T_357, _T_355) @[el2_lib.scala 289:69] - node _T_359 = cat(_T_358, _T_354) @[el2_lib.scala 289:69] - node _T_360 = cat(_T_359, _T_350) @[el2_lib.scala 289:69] - node _T_361 = cat(_T_360, _T_341) @[el2_lib.scala 289:69] - node _T_362 = xor(_T_361, _T_322) @[el2_lib.scala 289:76] - node _T_363 = mux(_T_323, _T_362, _T_322) @[el2_lib.scala 289:31] - node _T_364 = bits(_T_363, 37, 32) @[el2_lib.scala 291:37] - node _T_365 = bits(_T_363, 30, 16) @[el2_lib.scala 291:61] - node _T_366 = bits(_T_363, 14, 8) @[el2_lib.scala 291:86] - node _T_367 = bits(_T_363, 6, 4) @[el2_lib.scala 291:110] - node _T_368 = bits(_T_363, 2, 2) @[el2_lib.scala 291:133] - node _T_369 = cat(_T_367, _T_368) @[Cat.scala 29:58] - node _T_370 = cat(_T_364, _T_365) @[Cat.scala 29:58] - node _T_371 = cat(_T_370, _T_366) @[Cat.scala 29:58] - node sec_data_hi_any = cat(_T_371, _T_369) @[Cat.scala 29:58] - node _T_372 = bits(_T_363, 38, 38) @[el2_lib.scala 292:39] - node _T_373 = bits(_T_208, 6, 0) @[el2_lib.scala 292:56] - node _T_374 = eq(_T_373, UInt<7>("h040")) @[el2_lib.scala 292:62] - node _T_375 = xor(_T_372, _T_374) @[el2_lib.scala 292:44] - node _T_376 = bits(_T_363, 31, 31) @[el2_lib.scala 292:97] - node _T_377 = bits(_T_363, 15, 15) @[el2_lib.scala 292:119] - node _T_378 = bits(_T_363, 7, 7) @[el2_lib.scala 292:141] - node _T_379 = bits(_T_363, 3, 3) @[el2_lib.scala 292:162] - node _T_380 = bits(_T_363, 1, 0) @[el2_lib.scala 292:183] - node _T_381 = cat(_T_378, _T_379) @[Cat.scala 29:58] - node _T_382 = cat(_T_381, _T_380) @[Cat.scala 29:58] - node _T_383 = cat(_T_375, _T_376) @[Cat.scala 29:58] - node _T_384 = cat(_T_383, _T_377) @[Cat.scala 29:58] - node ecc_out_hi_nc = cat(_T_384, _T_382) @[Cat.scala 29:58] - wire _T_385 : UInt<1>[18] @[el2_lib.scala 259:18] - wire _T_386 : UInt<1>[18] @[el2_lib.scala 260:18] - wire _T_387 : UInt<1>[18] @[el2_lib.scala 261:18] - wire _T_388 : UInt<1>[15] @[el2_lib.scala 262:18] - wire _T_389 : UInt<1>[15] @[el2_lib.scala 263:18] - wire _T_390 : UInt<1>[6] @[el2_lib.scala 264:18] - node _T_391 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 271:36] - _T_385[0] <= _T_391 @[el2_lib.scala 271:30] - node _T_392 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 272:36] - _T_386[0] <= _T_392 @[el2_lib.scala 272:30] - node _T_393 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 271:36] - _T_385[1] <= _T_393 @[el2_lib.scala 271:30] - node _T_394 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 273:36] - _T_387[0] <= _T_394 @[el2_lib.scala 273:30] - node _T_395 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 272:36] - _T_386[1] <= _T_395 @[el2_lib.scala 272:30] - node _T_396 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 273:36] - _T_387[1] <= _T_396 @[el2_lib.scala 273:30] - node _T_397 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 271:36] - _T_385[2] <= _T_397 @[el2_lib.scala 271:30] - node _T_398 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 272:36] - _T_386[2] <= _T_398 @[el2_lib.scala 272:30] - node _T_399 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 273:36] - _T_387[2] <= _T_399 @[el2_lib.scala 273:30] - node _T_400 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 271:36] - _T_385[3] <= _T_400 @[el2_lib.scala 271:30] - node _T_401 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 274:36] - _T_388[0] <= _T_401 @[el2_lib.scala 274:30] - node _T_402 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 272:36] - _T_386[3] <= _T_402 @[el2_lib.scala 272:30] - node _T_403 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 274:36] - _T_388[1] <= _T_403 @[el2_lib.scala 274:30] - node _T_404 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 271:36] - _T_385[4] <= _T_404 @[el2_lib.scala 271:30] - node _T_405 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 272:36] - _T_386[4] <= _T_405 @[el2_lib.scala 272:30] - node _T_406 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 274:36] - _T_388[2] <= _T_406 @[el2_lib.scala 274:30] - node _T_407 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 273:36] - _T_387[3] <= _T_407 @[el2_lib.scala 273:30] - node _T_408 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 274:36] - _T_388[3] <= _T_408 @[el2_lib.scala 274:30] - node _T_409 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 271:36] - _T_385[5] <= _T_409 @[el2_lib.scala 271:30] - node _T_410 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 273:36] - _T_387[4] <= _T_410 @[el2_lib.scala 273:30] - node _T_411 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 274:36] - _T_388[4] <= _T_411 @[el2_lib.scala 274:30] - node _T_412 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 272:36] - _T_386[5] <= _T_412 @[el2_lib.scala 272:30] - node _T_413 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 273:36] - _T_387[5] <= _T_413 @[el2_lib.scala 273:30] - node _T_414 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 274:36] - _T_388[5] <= _T_414 @[el2_lib.scala 274:30] - node _T_415 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 271:36] - _T_385[6] <= _T_415 @[el2_lib.scala 271:30] - node _T_416 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 272:36] - _T_386[6] <= _T_416 @[el2_lib.scala 272:30] - node _T_417 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 273:36] - _T_387[6] <= _T_417 @[el2_lib.scala 273:30] - node _T_418 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 274:36] - _T_388[6] <= _T_418 @[el2_lib.scala 274:30] - node _T_419 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 271:36] - _T_385[7] <= _T_419 @[el2_lib.scala 271:30] - node _T_420 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 275:36] - _T_389[0] <= _T_420 @[el2_lib.scala 275:30] - node _T_421 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 272:36] - _T_386[7] <= _T_421 @[el2_lib.scala 272:30] - node _T_422 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 275:36] - _T_389[1] <= _T_422 @[el2_lib.scala 275:30] - node _T_423 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 271:36] - _T_385[8] <= _T_423 @[el2_lib.scala 271:30] - node _T_424 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 272:36] - _T_386[8] <= _T_424 @[el2_lib.scala 272:30] - node _T_425 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 275:36] - _T_389[2] <= _T_425 @[el2_lib.scala 275:30] - node _T_426 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 273:36] - _T_387[7] <= _T_426 @[el2_lib.scala 273:30] - node _T_427 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 275:36] - _T_389[3] <= _T_427 @[el2_lib.scala 275:30] - node _T_428 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 271:36] - _T_385[9] <= _T_428 @[el2_lib.scala 271:30] - node _T_429 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 273:36] - _T_387[8] <= _T_429 @[el2_lib.scala 273:30] - node _T_430 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 275:36] - _T_389[4] <= _T_430 @[el2_lib.scala 275:30] - node _T_431 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 272:36] - _T_386[9] <= _T_431 @[el2_lib.scala 272:30] - node _T_432 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 273:36] - _T_387[9] <= _T_432 @[el2_lib.scala 273:30] - node _T_433 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 275:36] - _T_389[5] <= _T_433 @[el2_lib.scala 275:30] - node _T_434 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 271:36] - _T_385[10] <= _T_434 @[el2_lib.scala 271:30] - node _T_435 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 272:36] - _T_386[10] <= _T_435 @[el2_lib.scala 272:30] - node _T_436 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 273:36] - _T_387[10] <= _T_436 @[el2_lib.scala 273:30] - node _T_437 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 275:36] - _T_389[6] <= _T_437 @[el2_lib.scala 275:30] - node _T_438 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 274:36] - _T_388[7] <= _T_438 @[el2_lib.scala 274:30] - node _T_439 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 275:36] - _T_389[7] <= _T_439 @[el2_lib.scala 275:30] - node _T_440 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 271:36] - _T_385[11] <= _T_440 @[el2_lib.scala 271:30] - node _T_441 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 274:36] - _T_388[8] <= _T_441 @[el2_lib.scala 274:30] - node _T_442 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 275:36] - _T_389[8] <= _T_442 @[el2_lib.scala 275:30] - node _T_443 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 272:36] - _T_386[11] <= _T_443 @[el2_lib.scala 272:30] - node _T_444 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 274:36] - _T_388[9] <= _T_444 @[el2_lib.scala 274:30] - node _T_445 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 275:36] - _T_389[9] <= _T_445 @[el2_lib.scala 275:30] - node _T_446 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 271:36] - _T_385[12] <= _T_446 @[el2_lib.scala 271:30] - node _T_447 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 272:36] - _T_386[12] <= _T_447 @[el2_lib.scala 272:30] - node _T_448 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 274:36] - _T_388[10] <= _T_448 @[el2_lib.scala 274:30] - node _T_449 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 275:36] - _T_389[10] <= _T_449 @[el2_lib.scala 275:30] - node _T_450 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 273:36] - _T_387[11] <= _T_450 @[el2_lib.scala 273:30] - node _T_451 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 274:36] - _T_388[11] <= _T_451 @[el2_lib.scala 274:30] - node _T_452 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 275:36] - _T_389[11] <= _T_452 @[el2_lib.scala 275:30] - node _T_453 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 271:36] - _T_385[13] <= _T_453 @[el2_lib.scala 271:30] - node _T_454 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 273:36] - _T_387[12] <= _T_454 @[el2_lib.scala 273:30] - node _T_455 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 274:36] - _T_388[12] <= _T_455 @[el2_lib.scala 274:30] - node _T_456 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 275:36] - _T_389[12] <= _T_456 @[el2_lib.scala 275:30] - node _T_457 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 272:36] - _T_386[13] <= _T_457 @[el2_lib.scala 272:30] - node _T_458 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 273:36] - _T_387[13] <= _T_458 @[el2_lib.scala 273:30] - node _T_459 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 274:36] - _T_388[13] <= _T_459 @[el2_lib.scala 274:30] - node _T_460 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 275:36] - _T_389[13] <= _T_460 @[el2_lib.scala 275:30] - node _T_461 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 271:36] - _T_385[14] <= _T_461 @[el2_lib.scala 271:30] - node _T_462 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 272:36] - _T_386[14] <= _T_462 @[el2_lib.scala 272:30] - node _T_463 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 273:36] - _T_387[14] <= _T_463 @[el2_lib.scala 273:30] - node _T_464 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 274:36] - _T_388[14] <= _T_464 @[el2_lib.scala 274:30] - node _T_465 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 275:36] - _T_389[14] <= _T_465 @[el2_lib.scala 275:30] - node _T_466 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 271:36] - _T_385[15] <= _T_466 @[el2_lib.scala 271:30] - node _T_467 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 276:36] - _T_390[0] <= _T_467 @[el2_lib.scala 276:30] - node _T_468 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 272:36] - _T_386[15] <= _T_468 @[el2_lib.scala 272:30] - node _T_469 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 276:36] - _T_390[1] <= _T_469 @[el2_lib.scala 276:30] - node _T_470 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 271:36] - _T_385[16] <= _T_470 @[el2_lib.scala 271:30] - node _T_471 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 272:36] - _T_386[16] <= _T_471 @[el2_lib.scala 272:30] - node _T_472 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 276:36] - _T_390[2] <= _T_472 @[el2_lib.scala 276:30] - node _T_473 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 273:36] - _T_387[15] <= _T_473 @[el2_lib.scala 273:30] - node _T_474 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 276:36] - _T_390[3] <= _T_474 @[el2_lib.scala 276:30] - node _T_475 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 271:36] - _T_385[17] <= _T_475 @[el2_lib.scala 271:30] - node _T_476 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 273:36] - _T_387[16] <= _T_476 @[el2_lib.scala 273:30] - node _T_477 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 276:36] - _T_390[4] <= _T_477 @[el2_lib.scala 276:30] - node _T_478 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 272:36] - _T_386[17] <= _T_478 @[el2_lib.scala 272:30] - node _T_479 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 273:36] - _T_387[17] <= _T_479 @[el2_lib.scala 273:30] - node _T_480 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 276:36] - _T_390[5] <= _T_480 @[el2_lib.scala 276:30] - node _T_481 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 279:30] - node _T_482 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 279:44] - node _T_483 = xor(_T_481, _T_482) @[el2_lib.scala 279:35] - node _T_484 = not(UInt<1>("h00")) @[el2_lib.scala 279:52] - node _T_485 = and(_T_483, _T_484) @[el2_lib.scala 279:50] - node _T_486 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 279:68] - node _T_487 = cat(_T_390[2], _T_390[1]) @[el2_lib.scala 279:76] - node _T_488 = cat(_T_487, _T_390[0]) @[el2_lib.scala 279:76] - node _T_489 = cat(_T_390[5], _T_390[4]) @[el2_lib.scala 279:76] - node _T_490 = cat(_T_489, _T_390[3]) @[el2_lib.scala 279:76] - node _T_491 = cat(_T_490, _T_488) @[el2_lib.scala 279:76] - node _T_492 = xorr(_T_491) @[el2_lib.scala 279:83] - node _T_493 = xor(_T_486, _T_492) @[el2_lib.scala 279:71] - node _T_494 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 279:95] - node _T_495 = cat(_T_389[2], _T_389[1]) @[el2_lib.scala 279:103] - node _T_496 = cat(_T_495, _T_389[0]) @[el2_lib.scala 279:103] - node _T_497 = cat(_T_389[4], _T_389[3]) @[el2_lib.scala 279:103] - node _T_498 = cat(_T_389[6], _T_389[5]) @[el2_lib.scala 279:103] - node _T_499 = cat(_T_498, _T_497) @[el2_lib.scala 279:103] - node _T_500 = cat(_T_499, _T_496) @[el2_lib.scala 279:103] - node _T_501 = cat(_T_389[8], _T_389[7]) @[el2_lib.scala 279:103] - node _T_502 = cat(_T_389[10], _T_389[9]) @[el2_lib.scala 279:103] - node _T_503 = cat(_T_502, _T_501) @[el2_lib.scala 279:103] - node _T_504 = cat(_T_389[12], _T_389[11]) @[el2_lib.scala 279:103] - node _T_505 = cat(_T_389[14], _T_389[13]) @[el2_lib.scala 279:103] - node _T_506 = cat(_T_505, _T_504) @[el2_lib.scala 279:103] - node _T_507 = cat(_T_506, _T_503) @[el2_lib.scala 279:103] - node _T_508 = cat(_T_507, _T_500) @[el2_lib.scala 279:103] - node _T_509 = xorr(_T_508) @[el2_lib.scala 279:110] - node _T_510 = xor(_T_494, _T_509) @[el2_lib.scala 279:98] - node _T_511 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 279:122] - node _T_512 = cat(_T_388[2], _T_388[1]) @[el2_lib.scala 279:130] - node _T_513 = cat(_T_512, _T_388[0]) @[el2_lib.scala 279:130] - node _T_514 = cat(_T_388[4], _T_388[3]) @[el2_lib.scala 279:130] - node _T_515 = cat(_T_388[6], _T_388[5]) @[el2_lib.scala 279:130] - node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 279:130] - node _T_517 = cat(_T_516, _T_513) @[el2_lib.scala 279:130] - node _T_518 = cat(_T_388[8], _T_388[7]) @[el2_lib.scala 279:130] - node _T_519 = cat(_T_388[10], _T_388[9]) @[el2_lib.scala 279:130] - node _T_520 = cat(_T_519, _T_518) @[el2_lib.scala 279:130] - node _T_521 = cat(_T_388[12], _T_388[11]) @[el2_lib.scala 279:130] - node _T_522 = cat(_T_388[14], _T_388[13]) @[el2_lib.scala 279:130] - node _T_523 = cat(_T_522, _T_521) @[el2_lib.scala 279:130] - node _T_524 = cat(_T_523, _T_520) @[el2_lib.scala 279:130] - node _T_525 = cat(_T_524, _T_517) @[el2_lib.scala 279:130] - node _T_526 = xorr(_T_525) @[el2_lib.scala 279:137] - node _T_527 = xor(_T_511, _T_526) @[el2_lib.scala 279:125] - node _T_528 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 279:149] - node _T_529 = cat(_T_387[1], _T_387[0]) @[el2_lib.scala 279:157] - node _T_530 = cat(_T_387[3], _T_387[2]) @[el2_lib.scala 279:157] - node _T_531 = cat(_T_530, _T_529) @[el2_lib.scala 279:157] - node _T_532 = cat(_T_387[5], _T_387[4]) @[el2_lib.scala 279:157] - node _T_533 = cat(_T_387[8], _T_387[7]) @[el2_lib.scala 279:157] - node _T_534 = cat(_T_533, _T_387[6]) @[el2_lib.scala 279:157] - node _T_535 = cat(_T_534, _T_532) @[el2_lib.scala 279:157] - node _T_536 = cat(_T_535, _T_531) @[el2_lib.scala 279:157] - node _T_537 = cat(_T_387[10], _T_387[9]) @[el2_lib.scala 279:157] - node _T_538 = cat(_T_387[12], _T_387[11]) @[el2_lib.scala 279:157] - node _T_539 = cat(_T_538, _T_537) @[el2_lib.scala 279:157] - node _T_540 = cat(_T_387[14], _T_387[13]) @[el2_lib.scala 279:157] - node _T_541 = cat(_T_387[17], _T_387[16]) @[el2_lib.scala 279:157] - node _T_542 = cat(_T_541, _T_387[15]) @[el2_lib.scala 279:157] - node _T_543 = cat(_T_542, _T_540) @[el2_lib.scala 279:157] - node _T_544 = cat(_T_543, _T_539) @[el2_lib.scala 279:157] - node _T_545 = cat(_T_544, _T_536) @[el2_lib.scala 279:157] - node _T_546 = xorr(_T_545) @[el2_lib.scala 279:164] - node _T_547 = xor(_T_528, _T_546) @[el2_lib.scala 279:152] - node _T_548 = bits(dccm_data_ecc_lo_any, 1, 1) @[el2_lib.scala 279:176] - node _T_549 = cat(_T_386[1], _T_386[0]) @[el2_lib.scala 279:184] - node _T_550 = cat(_T_386[3], _T_386[2]) @[el2_lib.scala 279:184] - node _T_551 = cat(_T_550, _T_549) @[el2_lib.scala 279:184] - node _T_552 = cat(_T_386[5], _T_386[4]) @[el2_lib.scala 279:184] - node _T_553 = cat(_T_386[8], _T_386[7]) @[el2_lib.scala 279:184] - node _T_554 = cat(_T_553, _T_386[6]) @[el2_lib.scala 279:184] - node _T_555 = cat(_T_554, _T_552) @[el2_lib.scala 279:184] - node _T_556 = cat(_T_555, _T_551) @[el2_lib.scala 279:184] - node _T_557 = cat(_T_386[10], _T_386[9]) @[el2_lib.scala 279:184] - node _T_558 = cat(_T_386[12], _T_386[11]) @[el2_lib.scala 279:184] - node _T_559 = cat(_T_558, _T_557) @[el2_lib.scala 279:184] - node _T_560 = cat(_T_386[14], _T_386[13]) @[el2_lib.scala 279:184] - node _T_561 = cat(_T_386[17], _T_386[16]) @[el2_lib.scala 279:184] - node _T_562 = cat(_T_561, _T_386[15]) @[el2_lib.scala 279:184] - node _T_563 = cat(_T_562, _T_560) @[el2_lib.scala 279:184] - node _T_564 = cat(_T_563, _T_559) @[el2_lib.scala 279:184] - node _T_565 = cat(_T_564, _T_556) @[el2_lib.scala 279:184] - node _T_566 = xorr(_T_565) @[el2_lib.scala 279:191] - node _T_567 = xor(_T_548, _T_566) @[el2_lib.scala 279:179] - node _T_568 = bits(dccm_data_ecc_lo_any, 0, 0) @[el2_lib.scala 279:203] - node _T_569 = cat(_T_385[1], _T_385[0]) @[el2_lib.scala 279:211] - node _T_570 = cat(_T_385[3], _T_385[2]) @[el2_lib.scala 279:211] - node _T_571 = cat(_T_570, _T_569) @[el2_lib.scala 279:211] - node _T_572 = cat(_T_385[5], _T_385[4]) @[el2_lib.scala 279:211] - node _T_573 = cat(_T_385[8], _T_385[7]) @[el2_lib.scala 279:211] - node _T_574 = cat(_T_573, _T_385[6]) @[el2_lib.scala 279:211] - node _T_575 = cat(_T_574, _T_572) @[el2_lib.scala 279:211] - node _T_576 = cat(_T_575, _T_571) @[el2_lib.scala 279:211] - node _T_577 = cat(_T_385[10], _T_385[9]) @[el2_lib.scala 279:211] - node _T_578 = cat(_T_385[12], _T_385[11]) @[el2_lib.scala 279:211] - node _T_579 = cat(_T_578, _T_577) @[el2_lib.scala 279:211] - node _T_580 = cat(_T_385[14], _T_385[13]) @[el2_lib.scala 279:211] - node _T_581 = cat(_T_385[17], _T_385[16]) @[el2_lib.scala 279:211] - node _T_582 = cat(_T_581, _T_385[15]) @[el2_lib.scala 279:211] - node _T_583 = cat(_T_582, _T_580) @[el2_lib.scala 279:211] - node _T_584 = cat(_T_583, _T_579) @[el2_lib.scala 279:211] - node _T_585 = cat(_T_584, _T_576) @[el2_lib.scala 279:211] - node _T_586 = xorr(_T_585) @[el2_lib.scala 279:218] - node _T_587 = xor(_T_568, _T_586) @[el2_lib.scala 279:206] - node _T_588 = cat(_T_547, _T_567) @[Cat.scala 29:58] - node _T_589 = cat(_T_588, _T_587) @[Cat.scala 29:58] - node _T_590 = cat(_T_510, _T_527) @[Cat.scala 29:58] - node _T_591 = cat(_T_485, _T_493) @[Cat.scala 29:58] - node _T_592 = cat(_T_591, _T_590) @[Cat.scala 29:58] - node _T_593 = cat(_T_592, _T_589) @[Cat.scala 29:58] - node _T_594 = neq(_T_593, UInt<1>("h00")) @[el2_lib.scala 281:44] - node _T_595 = and(is_ldst_lo_any, _T_594) @[el2_lib.scala 281:32] - node _T_596 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 281:60] - node _T_597 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 281:74] - node _T_598 = xor(_T_596, _T_597) @[el2_lib.scala 281:65] - node _T_599 = not(UInt<1>("h00")) @[el2_lib.scala 281:82] - node _T_600 = and(_T_598, _T_599) @[el2_lib.scala 281:80] - node single_ecc_error_lo_any = and(_T_595, _T_600) @[el2_lib.scala 281:52] - node _T_601 = neq(_T_593, UInt<1>("h00")) @[el2_lib.scala 282:44] - node _T_602 = and(is_ldst_lo_any, _T_601) @[el2_lib.scala 282:32] - node _T_603 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 282:60] - node _T_604 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 282:74] - node _T_605 = xor(_T_603, _T_604) @[el2_lib.scala 282:65] - node _T_606 = not(UInt<1>("h00")) @[el2_lib.scala 282:82] - node _T_607 = and(_T_605, _T_606) @[el2_lib.scala 282:80] - node double_ecc_error_lo_any = and(_T_602, _T_607) @[el2_lib.scala 282:52] - wire _T_608 : UInt<1>[39] @[el2_lib.scala 283:26] - node _T_609 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_610 = eq(_T_609, UInt<1>("h01")) @[el2_lib.scala 286:41] - _T_608[0] <= _T_610 @[el2_lib.scala 286:23] - node _T_611 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_612 = eq(_T_611, UInt<2>("h02")) @[el2_lib.scala 286:41] - _T_608[1] <= _T_612 @[el2_lib.scala 286:23] - node _T_613 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_614 = eq(_T_613, UInt<2>("h03")) @[el2_lib.scala 286:41] - _T_608[2] <= _T_614 @[el2_lib.scala 286:23] - node _T_615 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_616 = eq(_T_615, UInt<3>("h04")) @[el2_lib.scala 286:41] - _T_608[3] <= _T_616 @[el2_lib.scala 286:23] - node _T_617 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_618 = eq(_T_617, UInt<3>("h05")) @[el2_lib.scala 286:41] - _T_608[4] <= _T_618 @[el2_lib.scala 286:23] - node _T_619 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_620 = eq(_T_619, UInt<3>("h06")) @[el2_lib.scala 286:41] - _T_608[5] <= _T_620 @[el2_lib.scala 286:23] - node _T_621 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_622 = eq(_T_621, UInt<3>("h07")) @[el2_lib.scala 286:41] - _T_608[6] <= _T_622 @[el2_lib.scala 286:23] - node _T_623 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_624 = eq(_T_623, UInt<4>("h08")) @[el2_lib.scala 286:41] - _T_608[7] <= _T_624 @[el2_lib.scala 286:23] - node _T_625 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_626 = eq(_T_625, UInt<4>("h09")) @[el2_lib.scala 286:41] - _T_608[8] <= _T_626 @[el2_lib.scala 286:23] - node _T_627 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_628 = eq(_T_627, UInt<4>("h0a")) @[el2_lib.scala 286:41] - _T_608[9] <= _T_628 @[el2_lib.scala 286:23] - node _T_629 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_630 = eq(_T_629, UInt<4>("h0b")) @[el2_lib.scala 286:41] - _T_608[10] <= _T_630 @[el2_lib.scala 286:23] - node _T_631 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_632 = eq(_T_631, UInt<4>("h0c")) @[el2_lib.scala 286:41] - _T_608[11] <= _T_632 @[el2_lib.scala 286:23] - node _T_633 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_634 = eq(_T_633, UInt<4>("h0d")) @[el2_lib.scala 286:41] - _T_608[12] <= _T_634 @[el2_lib.scala 286:23] - node _T_635 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_636 = eq(_T_635, UInt<4>("h0e")) @[el2_lib.scala 286:41] - _T_608[13] <= _T_636 @[el2_lib.scala 286:23] - node _T_637 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_638 = eq(_T_637, UInt<4>("h0f")) @[el2_lib.scala 286:41] - _T_608[14] <= _T_638 @[el2_lib.scala 286:23] - node _T_639 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_640 = eq(_T_639, UInt<5>("h010")) @[el2_lib.scala 286:41] - _T_608[15] <= _T_640 @[el2_lib.scala 286:23] - node _T_641 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_642 = eq(_T_641, UInt<5>("h011")) @[el2_lib.scala 286:41] - _T_608[16] <= _T_642 @[el2_lib.scala 286:23] - node _T_643 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_644 = eq(_T_643, UInt<5>("h012")) @[el2_lib.scala 286:41] - _T_608[17] <= _T_644 @[el2_lib.scala 286:23] - node _T_645 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_646 = eq(_T_645, UInt<5>("h013")) @[el2_lib.scala 286:41] - _T_608[18] <= _T_646 @[el2_lib.scala 286:23] - node _T_647 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_648 = eq(_T_647, UInt<5>("h014")) @[el2_lib.scala 286:41] - _T_608[19] <= _T_648 @[el2_lib.scala 286:23] - node _T_649 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_650 = eq(_T_649, UInt<5>("h015")) @[el2_lib.scala 286:41] - _T_608[20] <= _T_650 @[el2_lib.scala 286:23] - node _T_651 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_652 = eq(_T_651, UInt<5>("h016")) @[el2_lib.scala 286:41] - _T_608[21] <= _T_652 @[el2_lib.scala 286:23] - node _T_653 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_654 = eq(_T_653, UInt<5>("h017")) @[el2_lib.scala 286:41] - _T_608[22] <= _T_654 @[el2_lib.scala 286:23] - node _T_655 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_656 = eq(_T_655, UInt<5>("h018")) @[el2_lib.scala 286:41] - _T_608[23] <= _T_656 @[el2_lib.scala 286:23] - node _T_657 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_658 = eq(_T_657, UInt<5>("h019")) @[el2_lib.scala 286:41] - _T_608[24] <= _T_658 @[el2_lib.scala 286:23] - node _T_659 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_660 = eq(_T_659, UInt<5>("h01a")) @[el2_lib.scala 286:41] - _T_608[25] <= _T_660 @[el2_lib.scala 286:23] - node _T_661 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_662 = eq(_T_661, UInt<5>("h01b")) @[el2_lib.scala 286:41] - _T_608[26] <= _T_662 @[el2_lib.scala 286:23] - node _T_663 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_664 = eq(_T_663, UInt<5>("h01c")) @[el2_lib.scala 286:41] - _T_608[27] <= _T_664 @[el2_lib.scala 286:23] - node _T_665 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_666 = eq(_T_665, UInt<5>("h01d")) @[el2_lib.scala 286:41] - _T_608[28] <= _T_666 @[el2_lib.scala 286:23] - node _T_667 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_668 = eq(_T_667, UInt<5>("h01e")) @[el2_lib.scala 286:41] - _T_608[29] <= _T_668 @[el2_lib.scala 286:23] - node _T_669 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_670 = eq(_T_669, UInt<5>("h01f")) @[el2_lib.scala 286:41] - _T_608[30] <= _T_670 @[el2_lib.scala 286:23] - node _T_671 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_672 = eq(_T_671, UInt<6>("h020")) @[el2_lib.scala 286:41] - _T_608[31] <= _T_672 @[el2_lib.scala 286:23] - node _T_673 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_674 = eq(_T_673, UInt<6>("h021")) @[el2_lib.scala 286:41] - _T_608[32] <= _T_674 @[el2_lib.scala 286:23] - node _T_675 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_676 = eq(_T_675, UInt<6>("h022")) @[el2_lib.scala 286:41] - _T_608[33] <= _T_676 @[el2_lib.scala 286:23] - node _T_677 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_678 = eq(_T_677, UInt<6>("h023")) @[el2_lib.scala 286:41] - _T_608[34] <= _T_678 @[el2_lib.scala 286:23] - node _T_679 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_680 = eq(_T_679, UInt<6>("h024")) @[el2_lib.scala 286:41] - _T_608[35] <= _T_680 @[el2_lib.scala 286:23] - node _T_681 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_682 = eq(_T_681, UInt<6>("h025")) @[el2_lib.scala 286:41] - _T_608[36] <= _T_682 @[el2_lib.scala 286:23] - node _T_683 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_684 = eq(_T_683, UInt<6>("h026")) @[el2_lib.scala 286:41] - _T_608[37] <= _T_684 @[el2_lib.scala 286:23] - node _T_685 = bits(_T_593, 5, 0) @[el2_lib.scala 286:35] - node _T_686 = eq(_T_685, UInt<6>("h027")) @[el2_lib.scala 286:41] - _T_608[38] <= _T_686 @[el2_lib.scala 286:23] - node _T_687 = bits(dccm_data_ecc_lo_any, 6, 6) @[el2_lib.scala 288:37] - node _T_688 = bits(dccm_rdata_lo_any, 31, 26) @[el2_lib.scala 288:45] - node _T_689 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 288:60] - node _T_690 = bits(dccm_rdata_lo_any, 25, 11) @[el2_lib.scala 288:68] - node _T_691 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 288:83] - node _T_692 = bits(dccm_rdata_lo_any, 10, 4) @[el2_lib.scala 288:91] - node _T_693 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 288:105] - node _T_694 = bits(dccm_rdata_lo_any, 3, 1) @[el2_lib.scala 288:113] - node _T_695 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 288:126] - node _T_696 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 288:134] - node _T_697 = bits(dccm_data_ecc_lo_any, 1, 0) @[el2_lib.scala 288:145] - node _T_698 = cat(_T_696, _T_697) @[Cat.scala 29:58] - node _T_699 = cat(_T_693, _T_694) @[Cat.scala 29:58] - node _T_700 = cat(_T_699, _T_695) @[Cat.scala 29:58] - node _T_701 = cat(_T_700, _T_698) @[Cat.scala 29:58] - node _T_702 = cat(_T_690, _T_691) @[Cat.scala 29:58] - node _T_703 = cat(_T_702, _T_692) @[Cat.scala 29:58] - node _T_704 = cat(_T_687, _T_688) @[Cat.scala 29:58] - node _T_705 = cat(_T_704, _T_689) @[Cat.scala 29:58] - node _T_706 = cat(_T_705, _T_703) @[Cat.scala 29:58] - node _T_707 = cat(_T_706, _T_701) @[Cat.scala 29:58] - node _T_708 = bits(single_ecc_error_lo_any, 0, 0) @[el2_lib.scala 289:49] - node _T_709 = cat(_T_608[1], _T_608[0]) @[el2_lib.scala 289:69] - node _T_710 = cat(_T_608[3], _T_608[2]) @[el2_lib.scala 289:69] - node _T_711 = cat(_T_710, _T_709) @[el2_lib.scala 289:69] - node _T_712 = cat(_T_608[5], _T_608[4]) @[el2_lib.scala 289:69] - node _T_713 = cat(_T_608[8], _T_608[7]) @[el2_lib.scala 289:69] - node _T_714 = cat(_T_713, _T_608[6]) @[el2_lib.scala 289:69] - node _T_715 = cat(_T_714, _T_712) @[el2_lib.scala 289:69] - node _T_716 = cat(_T_715, _T_711) @[el2_lib.scala 289:69] - node _T_717 = cat(_T_608[10], _T_608[9]) @[el2_lib.scala 289:69] - node _T_718 = cat(_T_608[13], _T_608[12]) @[el2_lib.scala 289:69] - node _T_719 = cat(_T_718, _T_608[11]) @[el2_lib.scala 289:69] - node _T_720 = cat(_T_719, _T_717) @[el2_lib.scala 289:69] - node _T_721 = cat(_T_608[15], _T_608[14]) @[el2_lib.scala 289:69] - node _T_722 = cat(_T_608[18], _T_608[17]) @[el2_lib.scala 289:69] - node _T_723 = cat(_T_722, _T_608[16]) @[el2_lib.scala 289:69] - node _T_724 = cat(_T_723, _T_721) @[el2_lib.scala 289:69] - node _T_725 = cat(_T_724, _T_720) @[el2_lib.scala 289:69] - node _T_726 = cat(_T_725, _T_716) @[el2_lib.scala 289:69] - node _T_727 = cat(_T_608[20], _T_608[19]) @[el2_lib.scala 289:69] - node _T_728 = cat(_T_608[23], _T_608[22]) @[el2_lib.scala 289:69] - node _T_729 = cat(_T_728, _T_608[21]) @[el2_lib.scala 289:69] - node _T_730 = cat(_T_729, _T_727) @[el2_lib.scala 289:69] - node _T_731 = cat(_T_608[25], _T_608[24]) @[el2_lib.scala 289:69] - node _T_732 = cat(_T_608[28], _T_608[27]) @[el2_lib.scala 289:69] - node _T_733 = cat(_T_732, _T_608[26]) @[el2_lib.scala 289:69] - node _T_734 = cat(_T_733, _T_731) @[el2_lib.scala 289:69] - node _T_735 = cat(_T_734, _T_730) @[el2_lib.scala 289:69] - node _T_736 = cat(_T_608[30], _T_608[29]) @[el2_lib.scala 289:69] - node _T_737 = cat(_T_608[33], _T_608[32]) @[el2_lib.scala 289:69] - node _T_738 = cat(_T_737, _T_608[31]) @[el2_lib.scala 289:69] - node _T_739 = cat(_T_738, _T_736) @[el2_lib.scala 289:69] - node _T_740 = cat(_T_608[35], _T_608[34]) @[el2_lib.scala 289:69] - node _T_741 = cat(_T_608[38], _T_608[37]) @[el2_lib.scala 289:69] - node _T_742 = cat(_T_741, _T_608[36]) @[el2_lib.scala 289:69] - node _T_743 = cat(_T_742, _T_740) @[el2_lib.scala 289:69] - node _T_744 = cat(_T_743, _T_739) @[el2_lib.scala 289:69] - node _T_745 = cat(_T_744, _T_735) @[el2_lib.scala 289:69] - node _T_746 = cat(_T_745, _T_726) @[el2_lib.scala 289:69] - node _T_747 = xor(_T_746, _T_707) @[el2_lib.scala 289:76] - node _T_748 = mux(_T_708, _T_747, _T_707) @[el2_lib.scala 289:31] - node _T_749 = bits(_T_748, 37, 32) @[el2_lib.scala 291:37] - node _T_750 = bits(_T_748, 30, 16) @[el2_lib.scala 291:61] - node _T_751 = bits(_T_748, 14, 8) @[el2_lib.scala 291:86] - node _T_752 = bits(_T_748, 6, 4) @[el2_lib.scala 291:110] - node _T_753 = bits(_T_748, 2, 2) @[el2_lib.scala 291:133] - node _T_754 = cat(_T_752, _T_753) @[Cat.scala 29:58] - node _T_755 = cat(_T_749, _T_750) @[Cat.scala 29:58] - node _T_756 = cat(_T_755, _T_751) @[Cat.scala 29:58] - node sec_data_lo_any = cat(_T_756, _T_754) @[Cat.scala 29:58] - node _T_757 = bits(_T_748, 38, 38) @[el2_lib.scala 292:39] - node _T_758 = bits(_T_593, 6, 0) @[el2_lib.scala 292:56] - node _T_759 = eq(_T_758, UInt<7>("h040")) @[el2_lib.scala 292:62] - node _T_760 = xor(_T_757, _T_759) @[el2_lib.scala 292:44] - node _T_761 = bits(_T_748, 31, 31) @[el2_lib.scala 292:97] - node _T_762 = bits(_T_748, 15, 15) @[el2_lib.scala 292:119] - node _T_763 = bits(_T_748, 7, 7) @[el2_lib.scala 292:141] - node _T_764 = bits(_T_748, 3, 3) @[el2_lib.scala 292:162] - node _T_765 = bits(_T_748, 1, 0) @[el2_lib.scala 292:183] - node _T_766 = cat(_T_763, _T_764) @[Cat.scala 29:58] - node _T_767 = cat(_T_766, _T_765) @[Cat.scala 29:58] - node _T_768 = cat(_T_760, _T_761) @[Cat.scala 29:58] - node _T_769 = cat(_T_768, _T_762) @[Cat.scala 29:58] - node ecc_out_lo_nc = cat(_T_769, _T_767) @[Cat.scala 29:58] - wire _T_770 : UInt<1>[18] @[el2_lib.scala 228:18] - wire _T_771 : UInt<1>[18] @[el2_lib.scala 229:18] - wire _T_772 : UInt<1>[18] @[el2_lib.scala 230:18] - wire _T_773 : UInt<1>[15] @[el2_lib.scala 231:18] - wire _T_774 : UInt<1>[15] @[el2_lib.scala 232:18] - wire _T_775 : UInt<1>[6] @[el2_lib.scala 233:18] - node _T_776 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 240:36] - _T_771[0] <= _T_776 @[el2_lib.scala 240:30] - node _T_777 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 241:36] - _T_772[0] <= _T_777 @[el2_lib.scala 241:30] - node _T_778 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 244:36] - _T_775[0] <= _T_778 @[el2_lib.scala 244:30] - node _T_779 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 239:36] - _T_770[0] <= _T_779 @[el2_lib.scala 239:30] - node _T_780 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 241:36] - _T_772[1] <= _T_780 @[el2_lib.scala 241:30] - node _T_781 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 244:36] - _T_775[1] <= _T_781 @[el2_lib.scala 244:30] - node _T_782 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 241:36] - _T_772[2] <= _T_782 @[el2_lib.scala 241:30] - node _T_783 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 244:36] - _T_775[2] <= _T_783 @[el2_lib.scala 244:30] - node _T_784 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 239:36] - _T_770[1] <= _T_784 @[el2_lib.scala 239:30] - node _T_785 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 240:36] - _T_771[1] <= _T_785 @[el2_lib.scala 240:30] - node _T_786 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 244:36] - _T_775[3] <= _T_786 @[el2_lib.scala 244:30] - node _T_787 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 240:36] - _T_771[2] <= _T_787 @[el2_lib.scala 240:30] - node _T_788 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 244:36] - _T_775[4] <= _T_788 @[el2_lib.scala 244:30] - node _T_789 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 239:36] - _T_770[2] <= _T_789 @[el2_lib.scala 239:30] - node _T_790 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 244:36] - _T_775[5] <= _T_790 @[el2_lib.scala 244:30] - node _T_791 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 239:36] - _T_770[3] <= _T_791 @[el2_lib.scala 239:30] - node _T_792 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 240:36] - _T_771[3] <= _T_792 @[el2_lib.scala 240:30] - node _T_793 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 241:36] - _T_772[3] <= _T_793 @[el2_lib.scala 241:30] - node _T_794 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 242:36] - _T_773[0] <= _T_794 @[el2_lib.scala 242:30] - node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 243:36] - _T_774[0] <= _T_795 @[el2_lib.scala 243:30] - node _T_796 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 240:36] - _T_771[4] <= _T_796 @[el2_lib.scala 240:30] - node _T_797 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 241:36] - _T_772[4] <= _T_797 @[el2_lib.scala 241:30] - node _T_798 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 242:36] - _T_773[1] <= _T_798 @[el2_lib.scala 242:30] - node _T_799 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 243:36] - _T_774[1] <= _T_799 @[el2_lib.scala 243:30] - node _T_800 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 239:36] - _T_770[4] <= _T_800 @[el2_lib.scala 239:30] - node _T_801 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 241:36] - _T_772[5] <= _T_801 @[el2_lib.scala 241:30] - node _T_802 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 242:36] - _T_773[2] <= _T_802 @[el2_lib.scala 242:30] - node _T_803 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 243:36] - _T_774[2] <= _T_803 @[el2_lib.scala 243:30] - node _T_804 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 241:36] - _T_772[6] <= _T_804 @[el2_lib.scala 241:30] - node _T_805 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 242:36] - _T_773[3] <= _T_805 @[el2_lib.scala 242:30] - node _T_806 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 243:36] - _T_774[3] <= _T_806 @[el2_lib.scala 243:30] - node _T_807 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 239:36] - _T_770[5] <= _T_807 @[el2_lib.scala 239:30] - node _T_808 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 240:36] - _T_771[5] <= _T_808 @[el2_lib.scala 240:30] - node _T_809 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 242:36] - _T_773[4] <= _T_809 @[el2_lib.scala 242:30] - node _T_810 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 243:36] - _T_774[4] <= _T_810 @[el2_lib.scala 243:30] - node _T_811 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 240:36] - _T_771[6] <= _T_811 @[el2_lib.scala 240:30] - node _T_812 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 242:36] - _T_773[5] <= _T_812 @[el2_lib.scala 242:30] - node _T_813 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 243:36] - _T_774[5] <= _T_813 @[el2_lib.scala 243:30] - node _T_814 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 239:36] - _T_770[6] <= _T_814 @[el2_lib.scala 239:30] - node _T_815 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 242:36] - _T_773[6] <= _T_815 @[el2_lib.scala 242:30] - node _T_816 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 243:36] - _T_774[6] <= _T_816 @[el2_lib.scala 243:30] - node _T_817 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 242:36] - _T_773[7] <= _T_817 @[el2_lib.scala 242:30] - node _T_818 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 243:36] - _T_774[7] <= _T_818 @[el2_lib.scala 243:30] - node _T_819 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 239:36] - _T_770[7] <= _T_819 @[el2_lib.scala 239:30] - node _T_820 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 240:36] - _T_771[7] <= _T_820 @[el2_lib.scala 240:30] - node _T_821 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 241:36] - _T_772[7] <= _T_821 @[el2_lib.scala 241:30] - node _T_822 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 243:36] - _T_774[8] <= _T_822 @[el2_lib.scala 243:30] - node _T_823 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 240:36] - _T_771[8] <= _T_823 @[el2_lib.scala 240:30] - node _T_824 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 241:36] - _T_772[8] <= _T_824 @[el2_lib.scala 241:30] - node _T_825 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 243:36] - _T_774[9] <= _T_825 @[el2_lib.scala 243:30] - node _T_826 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 239:36] - _T_770[8] <= _T_826 @[el2_lib.scala 239:30] - node _T_827 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 241:36] - _T_772[9] <= _T_827 @[el2_lib.scala 241:30] - node _T_828 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 243:36] - _T_774[10] <= _T_828 @[el2_lib.scala 243:30] - node _T_829 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 241:36] - _T_772[10] <= _T_829 @[el2_lib.scala 241:30] - node _T_830 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 243:36] - _T_774[11] <= _T_830 @[el2_lib.scala 243:30] - node _T_831 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 239:36] - _T_770[9] <= _T_831 @[el2_lib.scala 239:30] - node _T_832 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 240:36] - _T_771[9] <= _T_832 @[el2_lib.scala 240:30] - node _T_833 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 243:36] - _T_774[12] <= _T_833 @[el2_lib.scala 243:30] - node _T_834 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 240:36] - _T_771[10] <= _T_834 @[el2_lib.scala 240:30] - node _T_835 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 243:36] - _T_774[13] <= _T_835 @[el2_lib.scala 243:30] - node _T_836 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 239:36] - _T_770[10] <= _T_836 @[el2_lib.scala 239:30] - node _T_837 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 243:36] - _T_774[14] <= _T_837 @[el2_lib.scala 243:30] - node _T_838 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 239:36] - _T_770[11] <= _T_838 @[el2_lib.scala 239:30] - node _T_839 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 240:36] - _T_771[11] <= _T_839 @[el2_lib.scala 240:30] - node _T_840 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 241:36] - _T_772[11] <= _T_840 @[el2_lib.scala 241:30] - node _T_841 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 242:36] - _T_773[8] <= _T_841 @[el2_lib.scala 242:30] - node _T_842 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 240:36] - _T_771[12] <= _T_842 @[el2_lib.scala 240:30] - node _T_843 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 241:36] - _T_772[12] <= _T_843 @[el2_lib.scala 241:30] - node _T_844 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 242:36] - _T_773[9] <= _T_844 @[el2_lib.scala 242:30] - node _T_845 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 239:36] - _T_770[12] <= _T_845 @[el2_lib.scala 239:30] - node _T_846 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 241:36] - _T_772[13] <= _T_846 @[el2_lib.scala 241:30] - node _T_847 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 242:36] - _T_773[10] <= _T_847 @[el2_lib.scala 242:30] - node _T_848 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 241:36] - _T_772[14] <= _T_848 @[el2_lib.scala 241:30] - node _T_849 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 242:36] - _T_773[11] <= _T_849 @[el2_lib.scala 242:30] - node _T_850 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 239:36] - _T_770[13] <= _T_850 @[el2_lib.scala 239:30] - node _T_851 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 240:36] - _T_771[13] <= _T_851 @[el2_lib.scala 240:30] - node _T_852 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 242:36] - _T_773[12] <= _T_852 @[el2_lib.scala 242:30] - node _T_853 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 240:36] - _T_771[14] <= _T_853 @[el2_lib.scala 240:30] - node _T_854 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 242:36] - _T_773[13] <= _T_854 @[el2_lib.scala 242:30] - node _T_855 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 239:36] - _T_770[14] <= _T_855 @[el2_lib.scala 239:30] - node _T_856 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 242:36] - _T_773[14] <= _T_856 @[el2_lib.scala 242:30] - node _T_857 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 239:36] - _T_770[15] <= _T_857 @[el2_lib.scala 239:30] - node _T_858 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 240:36] - _T_771[15] <= _T_858 @[el2_lib.scala 240:30] - node _T_859 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 241:36] - _T_772[15] <= _T_859 @[el2_lib.scala 241:30] - node _T_860 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 240:36] - _T_771[16] <= _T_860 @[el2_lib.scala 240:30] - node _T_861 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 241:36] - _T_772[16] <= _T_861 @[el2_lib.scala 241:30] - node _T_862 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 239:36] - _T_770[16] <= _T_862 @[el2_lib.scala 239:30] - node _T_863 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 241:36] - _T_772[17] <= _T_863 @[el2_lib.scala 241:30] - node _T_864 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 239:36] - _T_770[17] <= _T_864 @[el2_lib.scala 239:30] - node _T_865 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 240:36] - _T_771[17] <= _T_865 @[el2_lib.scala 240:30] - node _T_866 = cat(_T_770[1], _T_770[0]) @[el2_lib.scala 246:22] - node _T_867 = cat(_T_770[3], _T_770[2]) @[el2_lib.scala 246:22] - node _T_868 = cat(_T_867, _T_866) @[el2_lib.scala 246:22] - node _T_869 = cat(_T_770[5], _T_770[4]) @[el2_lib.scala 246:22] - node _T_870 = cat(_T_770[8], _T_770[7]) @[el2_lib.scala 246:22] - node _T_871 = cat(_T_870, _T_770[6]) @[el2_lib.scala 246:22] - node _T_872 = cat(_T_871, _T_869) @[el2_lib.scala 246:22] - node _T_873 = cat(_T_872, _T_868) @[el2_lib.scala 246:22] - node _T_874 = cat(_T_770[10], _T_770[9]) @[el2_lib.scala 246:22] - node _T_875 = cat(_T_770[12], _T_770[11]) @[el2_lib.scala 246:22] - node _T_876 = cat(_T_875, _T_874) @[el2_lib.scala 246:22] - node _T_877 = cat(_T_770[14], _T_770[13]) @[el2_lib.scala 246:22] - node _T_878 = cat(_T_770[17], _T_770[16]) @[el2_lib.scala 246:22] - node _T_879 = cat(_T_878, _T_770[15]) @[el2_lib.scala 246:22] - node _T_880 = cat(_T_879, _T_877) @[el2_lib.scala 246:22] - node _T_881 = cat(_T_880, _T_876) @[el2_lib.scala 246:22] - node _T_882 = cat(_T_881, _T_873) @[el2_lib.scala 246:22] - node _T_883 = xorr(_T_882) @[el2_lib.scala 246:29] - node _T_884 = cat(_T_771[1], _T_771[0]) @[el2_lib.scala 246:39] - node _T_885 = cat(_T_771[3], _T_771[2]) @[el2_lib.scala 246:39] - node _T_886 = cat(_T_885, _T_884) @[el2_lib.scala 246:39] - node _T_887 = cat(_T_771[5], _T_771[4]) @[el2_lib.scala 246:39] - node _T_888 = cat(_T_771[8], _T_771[7]) @[el2_lib.scala 246:39] - node _T_889 = cat(_T_888, _T_771[6]) @[el2_lib.scala 246:39] - node _T_890 = cat(_T_889, _T_887) @[el2_lib.scala 246:39] - node _T_891 = cat(_T_890, _T_886) @[el2_lib.scala 246:39] - node _T_892 = cat(_T_771[10], _T_771[9]) @[el2_lib.scala 246:39] - node _T_893 = cat(_T_771[12], _T_771[11]) @[el2_lib.scala 246:39] - node _T_894 = cat(_T_893, _T_892) @[el2_lib.scala 246:39] - node _T_895 = cat(_T_771[14], _T_771[13]) @[el2_lib.scala 246:39] - node _T_896 = cat(_T_771[17], _T_771[16]) @[el2_lib.scala 246:39] - node _T_897 = cat(_T_896, _T_771[15]) @[el2_lib.scala 246:39] - node _T_898 = cat(_T_897, _T_895) @[el2_lib.scala 246:39] - node _T_899 = cat(_T_898, _T_894) @[el2_lib.scala 246:39] - node _T_900 = cat(_T_899, _T_891) @[el2_lib.scala 246:39] - node _T_901 = xorr(_T_900) @[el2_lib.scala 246:46] - node _T_902 = cat(_T_772[1], _T_772[0]) @[el2_lib.scala 246:56] - node _T_903 = cat(_T_772[3], _T_772[2]) @[el2_lib.scala 246:56] - node _T_904 = cat(_T_903, _T_902) @[el2_lib.scala 246:56] - node _T_905 = cat(_T_772[5], _T_772[4]) @[el2_lib.scala 246:56] - node _T_906 = cat(_T_772[8], _T_772[7]) @[el2_lib.scala 246:56] - node _T_907 = cat(_T_906, _T_772[6]) @[el2_lib.scala 246:56] - node _T_908 = cat(_T_907, _T_905) @[el2_lib.scala 246:56] - node _T_909 = cat(_T_908, _T_904) @[el2_lib.scala 246:56] - node _T_910 = cat(_T_772[10], _T_772[9]) @[el2_lib.scala 246:56] - node _T_911 = cat(_T_772[12], _T_772[11]) @[el2_lib.scala 246:56] - node _T_912 = cat(_T_911, _T_910) @[el2_lib.scala 246:56] - node _T_913 = cat(_T_772[14], _T_772[13]) @[el2_lib.scala 246:56] - node _T_914 = cat(_T_772[17], _T_772[16]) @[el2_lib.scala 246:56] - node _T_915 = cat(_T_914, _T_772[15]) @[el2_lib.scala 246:56] - node _T_916 = cat(_T_915, _T_913) @[el2_lib.scala 246:56] - node _T_917 = cat(_T_916, _T_912) @[el2_lib.scala 246:56] - node _T_918 = cat(_T_917, _T_909) @[el2_lib.scala 246:56] - node _T_919 = xorr(_T_918) @[el2_lib.scala 246:63] - node _T_920 = cat(_T_773[2], _T_773[1]) @[el2_lib.scala 246:73] - node _T_921 = cat(_T_920, _T_773[0]) @[el2_lib.scala 246:73] - node _T_922 = cat(_T_773[4], _T_773[3]) @[el2_lib.scala 246:73] - node _T_923 = cat(_T_773[6], _T_773[5]) @[el2_lib.scala 246:73] - node _T_924 = cat(_T_923, _T_922) @[el2_lib.scala 246:73] - node _T_925 = cat(_T_924, _T_921) @[el2_lib.scala 246:73] - node _T_926 = cat(_T_773[8], _T_773[7]) @[el2_lib.scala 246:73] - node _T_927 = cat(_T_773[10], _T_773[9]) @[el2_lib.scala 246:73] - node _T_928 = cat(_T_927, _T_926) @[el2_lib.scala 246:73] - node _T_929 = cat(_T_773[12], _T_773[11]) @[el2_lib.scala 246:73] - node _T_930 = cat(_T_773[14], _T_773[13]) @[el2_lib.scala 246:73] - node _T_931 = cat(_T_930, _T_929) @[el2_lib.scala 246:73] - node _T_932 = cat(_T_931, _T_928) @[el2_lib.scala 246:73] - node _T_933 = cat(_T_932, _T_925) @[el2_lib.scala 246:73] - node _T_934 = xorr(_T_933) @[el2_lib.scala 246:80] - node _T_935 = cat(_T_774[2], _T_774[1]) @[el2_lib.scala 246:90] - node _T_936 = cat(_T_935, _T_774[0]) @[el2_lib.scala 246:90] - node _T_937 = cat(_T_774[4], _T_774[3]) @[el2_lib.scala 246:90] - node _T_938 = cat(_T_774[6], _T_774[5]) @[el2_lib.scala 246:90] - node _T_939 = cat(_T_938, _T_937) @[el2_lib.scala 246:90] - node _T_940 = cat(_T_939, _T_936) @[el2_lib.scala 246:90] - node _T_941 = cat(_T_774[8], _T_774[7]) @[el2_lib.scala 246:90] - node _T_942 = cat(_T_774[10], _T_774[9]) @[el2_lib.scala 246:90] - node _T_943 = cat(_T_942, _T_941) @[el2_lib.scala 246:90] - node _T_944 = cat(_T_774[12], _T_774[11]) @[el2_lib.scala 246:90] - node _T_945 = cat(_T_774[14], _T_774[13]) @[el2_lib.scala 246:90] - node _T_946 = cat(_T_945, _T_944) @[el2_lib.scala 246:90] - node _T_947 = cat(_T_946, _T_943) @[el2_lib.scala 246:90] - node _T_948 = cat(_T_947, _T_940) @[el2_lib.scala 246:90] - node _T_949 = xorr(_T_948) @[el2_lib.scala 246:97] - node _T_950 = cat(_T_775[2], _T_775[1]) @[el2_lib.scala 246:107] - node _T_951 = cat(_T_950, _T_775[0]) @[el2_lib.scala 246:107] - node _T_952 = cat(_T_775[5], _T_775[4]) @[el2_lib.scala 246:107] - node _T_953 = cat(_T_952, _T_775[3]) @[el2_lib.scala 246:107] - node _T_954 = cat(_T_953, _T_951) @[el2_lib.scala 246:107] - node _T_955 = xorr(_T_954) @[el2_lib.scala 246:114] - node _T_956 = cat(_T_934, _T_949) @[Cat.scala 29:58] - node _T_957 = cat(_T_956, _T_955) @[Cat.scala 29:58] - node _T_958 = cat(_T_883, _T_901) @[Cat.scala 29:58] - node _T_959 = cat(_T_958, _T_919) @[Cat.scala 29:58] - node _T_960 = cat(_T_959, _T_957) @[Cat.scala 29:58] - node _T_961 = xorr(dccm_wdata_lo_any) @[el2_lib.scala 247:13] - node _T_962 = xorr(_T_960) @[el2_lib.scala 247:23] - node _T_963 = xor(_T_961, _T_962) @[el2_lib.scala 247:18] - node lsu_ecc_encode_lo = cat(_T_963, _T_960) @[Cat.scala 29:58] - wire _T_964 : UInt<1>[18] @[el2_lib.scala 228:18] - wire _T_965 : UInt<1>[18] @[el2_lib.scala 229:18] - wire _T_966 : UInt<1>[18] @[el2_lib.scala 230:18] - wire _T_967 : UInt<1>[15] @[el2_lib.scala 231:18] - wire _T_968 : UInt<1>[15] @[el2_lib.scala 232:18] - wire _T_969 : UInt<1>[6] @[el2_lib.scala 233:18] - node _T_970 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 240:36] - _T_965[0] <= _T_970 @[el2_lib.scala 240:30] - node _T_971 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 241:36] - _T_966[0] <= _T_971 @[el2_lib.scala 241:30] - node _T_972 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 244:36] - _T_969[0] <= _T_972 @[el2_lib.scala 244:30] - node _T_973 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 239:36] - _T_964[0] <= _T_973 @[el2_lib.scala 239:30] - node _T_974 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 241:36] - _T_966[1] <= _T_974 @[el2_lib.scala 241:30] - node _T_975 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 244:36] - _T_969[1] <= _T_975 @[el2_lib.scala 244:30] - node _T_976 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 241:36] - _T_966[2] <= _T_976 @[el2_lib.scala 241:30] - node _T_977 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 244:36] - _T_969[2] <= _T_977 @[el2_lib.scala 244:30] - node _T_978 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 239:36] - _T_964[1] <= _T_978 @[el2_lib.scala 239:30] - node _T_979 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 240:36] - _T_965[1] <= _T_979 @[el2_lib.scala 240:30] - node _T_980 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 244:36] - _T_969[3] <= _T_980 @[el2_lib.scala 244:30] - node _T_981 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 240:36] - _T_965[2] <= _T_981 @[el2_lib.scala 240:30] - node _T_982 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 244:36] - _T_969[4] <= _T_982 @[el2_lib.scala 244:30] - node _T_983 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 239:36] - _T_964[2] <= _T_983 @[el2_lib.scala 239:30] - node _T_984 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 244:36] - _T_969[5] <= _T_984 @[el2_lib.scala 244:30] - node _T_985 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 239:36] - _T_964[3] <= _T_985 @[el2_lib.scala 239:30] - node _T_986 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 240:36] - _T_965[3] <= _T_986 @[el2_lib.scala 240:30] - node _T_987 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 241:36] - _T_966[3] <= _T_987 @[el2_lib.scala 241:30] - node _T_988 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 242:36] - _T_967[0] <= _T_988 @[el2_lib.scala 242:30] - node _T_989 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 243:36] - _T_968[0] <= _T_989 @[el2_lib.scala 243:30] - node _T_990 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 240:36] - _T_965[4] <= _T_990 @[el2_lib.scala 240:30] - node _T_991 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 241:36] - _T_966[4] <= _T_991 @[el2_lib.scala 241:30] - node _T_992 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 242:36] - _T_967[1] <= _T_992 @[el2_lib.scala 242:30] - node _T_993 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 243:36] - _T_968[1] <= _T_993 @[el2_lib.scala 243:30] - node _T_994 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 239:36] - _T_964[4] <= _T_994 @[el2_lib.scala 239:30] - node _T_995 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 241:36] - _T_966[5] <= _T_995 @[el2_lib.scala 241:30] - node _T_996 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 242:36] - _T_967[2] <= _T_996 @[el2_lib.scala 242:30] - node _T_997 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 243:36] - _T_968[2] <= _T_997 @[el2_lib.scala 243:30] - node _T_998 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 241:36] - _T_966[6] <= _T_998 @[el2_lib.scala 241:30] - node _T_999 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 242:36] - _T_967[3] <= _T_999 @[el2_lib.scala 242:30] - node _T_1000 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 243:36] - _T_968[3] <= _T_1000 @[el2_lib.scala 243:30] - node _T_1001 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 239:36] - _T_964[5] <= _T_1001 @[el2_lib.scala 239:30] - node _T_1002 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 240:36] - _T_965[5] <= _T_1002 @[el2_lib.scala 240:30] - node _T_1003 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 242:36] - _T_967[4] <= _T_1003 @[el2_lib.scala 242:30] - node _T_1004 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 243:36] - _T_968[4] <= _T_1004 @[el2_lib.scala 243:30] - node _T_1005 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 240:36] - _T_965[6] <= _T_1005 @[el2_lib.scala 240:30] - node _T_1006 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 242:36] - _T_967[5] <= _T_1006 @[el2_lib.scala 242:30] - node _T_1007 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 243:36] - _T_968[5] <= _T_1007 @[el2_lib.scala 243:30] - node _T_1008 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 239:36] - _T_964[6] <= _T_1008 @[el2_lib.scala 239:30] - node _T_1009 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 242:36] - _T_967[6] <= _T_1009 @[el2_lib.scala 242:30] - node _T_1010 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 243:36] - _T_968[6] <= _T_1010 @[el2_lib.scala 243:30] - node _T_1011 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 242:36] - _T_967[7] <= _T_1011 @[el2_lib.scala 242:30] - node _T_1012 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 243:36] - _T_968[7] <= _T_1012 @[el2_lib.scala 243:30] - node _T_1013 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 239:36] - _T_964[7] <= _T_1013 @[el2_lib.scala 239:30] - node _T_1014 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 240:36] - _T_965[7] <= _T_1014 @[el2_lib.scala 240:30] - node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 241:36] - _T_966[7] <= _T_1015 @[el2_lib.scala 241:30] - node _T_1016 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 243:36] - _T_968[8] <= _T_1016 @[el2_lib.scala 243:30] - node _T_1017 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 240:36] - _T_965[8] <= _T_1017 @[el2_lib.scala 240:30] - node _T_1018 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 241:36] - _T_966[8] <= _T_1018 @[el2_lib.scala 241:30] - node _T_1019 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 243:36] - _T_968[9] <= _T_1019 @[el2_lib.scala 243:30] - node _T_1020 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 239:36] - _T_964[8] <= _T_1020 @[el2_lib.scala 239:30] - node _T_1021 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 241:36] - _T_966[9] <= _T_1021 @[el2_lib.scala 241:30] - node _T_1022 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 243:36] - _T_968[10] <= _T_1022 @[el2_lib.scala 243:30] - node _T_1023 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 241:36] - _T_966[10] <= _T_1023 @[el2_lib.scala 241:30] - node _T_1024 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 243:36] - _T_968[11] <= _T_1024 @[el2_lib.scala 243:30] - node _T_1025 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 239:36] - _T_964[9] <= _T_1025 @[el2_lib.scala 239:30] - node _T_1026 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 240:36] - _T_965[9] <= _T_1026 @[el2_lib.scala 240:30] - node _T_1027 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 243:36] - _T_968[12] <= _T_1027 @[el2_lib.scala 243:30] - node _T_1028 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 240:36] - _T_965[10] <= _T_1028 @[el2_lib.scala 240:30] - node _T_1029 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 243:36] - _T_968[13] <= _T_1029 @[el2_lib.scala 243:30] - node _T_1030 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 239:36] - _T_964[10] <= _T_1030 @[el2_lib.scala 239:30] - node _T_1031 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 243:36] - _T_968[14] <= _T_1031 @[el2_lib.scala 243:30] - node _T_1032 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 239:36] - _T_964[11] <= _T_1032 @[el2_lib.scala 239:30] - node _T_1033 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 240:36] - _T_965[11] <= _T_1033 @[el2_lib.scala 240:30] - node _T_1034 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 241:36] - _T_966[11] <= _T_1034 @[el2_lib.scala 241:30] - node _T_1035 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 242:36] - _T_967[8] <= _T_1035 @[el2_lib.scala 242:30] - node _T_1036 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 240:36] - _T_965[12] <= _T_1036 @[el2_lib.scala 240:30] - node _T_1037 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 241:36] - _T_966[12] <= _T_1037 @[el2_lib.scala 241:30] - node _T_1038 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 242:36] - _T_967[9] <= _T_1038 @[el2_lib.scala 242:30] - node _T_1039 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 239:36] - _T_964[12] <= _T_1039 @[el2_lib.scala 239:30] - node _T_1040 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 241:36] - _T_966[13] <= _T_1040 @[el2_lib.scala 241:30] - node _T_1041 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 242:36] - _T_967[10] <= _T_1041 @[el2_lib.scala 242:30] - node _T_1042 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 241:36] - _T_966[14] <= _T_1042 @[el2_lib.scala 241:30] - node _T_1043 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 242:36] - _T_967[11] <= _T_1043 @[el2_lib.scala 242:30] - node _T_1044 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 239:36] - _T_964[13] <= _T_1044 @[el2_lib.scala 239:30] - node _T_1045 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 240:36] - _T_965[13] <= _T_1045 @[el2_lib.scala 240:30] - node _T_1046 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 242:36] - _T_967[12] <= _T_1046 @[el2_lib.scala 242:30] - node _T_1047 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 240:36] - _T_965[14] <= _T_1047 @[el2_lib.scala 240:30] - node _T_1048 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 242:36] - _T_967[13] <= _T_1048 @[el2_lib.scala 242:30] - node _T_1049 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 239:36] - _T_964[14] <= _T_1049 @[el2_lib.scala 239:30] - node _T_1050 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 242:36] - _T_967[14] <= _T_1050 @[el2_lib.scala 242:30] - node _T_1051 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 239:36] - _T_964[15] <= _T_1051 @[el2_lib.scala 239:30] - node _T_1052 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 240:36] - _T_965[15] <= _T_1052 @[el2_lib.scala 240:30] - node _T_1053 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 241:36] - _T_966[15] <= _T_1053 @[el2_lib.scala 241:30] - node _T_1054 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 240:36] - _T_965[16] <= _T_1054 @[el2_lib.scala 240:30] - node _T_1055 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 241:36] - _T_966[16] <= _T_1055 @[el2_lib.scala 241:30] - node _T_1056 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 239:36] - _T_964[16] <= _T_1056 @[el2_lib.scala 239:30] - node _T_1057 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 241:36] - _T_966[17] <= _T_1057 @[el2_lib.scala 241:30] - node _T_1058 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 239:36] - _T_964[17] <= _T_1058 @[el2_lib.scala 239:30] - node _T_1059 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 240:36] - _T_965[17] <= _T_1059 @[el2_lib.scala 240:30] - node _T_1060 = cat(_T_964[1], _T_964[0]) @[el2_lib.scala 246:22] - node _T_1061 = cat(_T_964[3], _T_964[2]) @[el2_lib.scala 246:22] - node _T_1062 = cat(_T_1061, _T_1060) @[el2_lib.scala 246:22] - node _T_1063 = cat(_T_964[5], _T_964[4]) @[el2_lib.scala 246:22] - node _T_1064 = cat(_T_964[8], _T_964[7]) @[el2_lib.scala 246:22] - node _T_1065 = cat(_T_1064, _T_964[6]) @[el2_lib.scala 246:22] - node _T_1066 = cat(_T_1065, _T_1063) @[el2_lib.scala 246:22] - node _T_1067 = cat(_T_1066, _T_1062) @[el2_lib.scala 246:22] - node _T_1068 = cat(_T_964[10], _T_964[9]) @[el2_lib.scala 246:22] - node _T_1069 = cat(_T_964[12], _T_964[11]) @[el2_lib.scala 246:22] - node _T_1070 = cat(_T_1069, _T_1068) @[el2_lib.scala 246:22] - node _T_1071 = cat(_T_964[14], _T_964[13]) @[el2_lib.scala 246:22] - node _T_1072 = cat(_T_964[17], _T_964[16]) @[el2_lib.scala 246:22] - node _T_1073 = cat(_T_1072, _T_964[15]) @[el2_lib.scala 246:22] - node _T_1074 = cat(_T_1073, _T_1071) @[el2_lib.scala 246:22] - node _T_1075 = cat(_T_1074, _T_1070) @[el2_lib.scala 246:22] - node _T_1076 = cat(_T_1075, _T_1067) @[el2_lib.scala 246:22] - node _T_1077 = xorr(_T_1076) @[el2_lib.scala 246:29] - node _T_1078 = cat(_T_965[1], _T_965[0]) @[el2_lib.scala 246:39] - node _T_1079 = cat(_T_965[3], _T_965[2]) @[el2_lib.scala 246:39] - node _T_1080 = cat(_T_1079, _T_1078) @[el2_lib.scala 246:39] - node _T_1081 = cat(_T_965[5], _T_965[4]) @[el2_lib.scala 246:39] - node _T_1082 = cat(_T_965[8], _T_965[7]) @[el2_lib.scala 246:39] - node _T_1083 = cat(_T_1082, _T_965[6]) @[el2_lib.scala 246:39] - node _T_1084 = cat(_T_1083, _T_1081) @[el2_lib.scala 246:39] - node _T_1085 = cat(_T_1084, _T_1080) @[el2_lib.scala 246:39] - node _T_1086 = cat(_T_965[10], _T_965[9]) @[el2_lib.scala 246:39] - node _T_1087 = cat(_T_965[12], _T_965[11]) @[el2_lib.scala 246:39] - node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 246:39] - node _T_1089 = cat(_T_965[14], _T_965[13]) @[el2_lib.scala 246:39] - node _T_1090 = cat(_T_965[17], _T_965[16]) @[el2_lib.scala 246:39] - node _T_1091 = cat(_T_1090, _T_965[15]) @[el2_lib.scala 246:39] - node _T_1092 = cat(_T_1091, _T_1089) @[el2_lib.scala 246:39] - node _T_1093 = cat(_T_1092, _T_1088) @[el2_lib.scala 246:39] - node _T_1094 = cat(_T_1093, _T_1085) @[el2_lib.scala 246:39] - node _T_1095 = xorr(_T_1094) @[el2_lib.scala 246:46] - node _T_1096 = cat(_T_966[1], _T_966[0]) @[el2_lib.scala 246:56] - node _T_1097 = cat(_T_966[3], _T_966[2]) @[el2_lib.scala 246:56] - node _T_1098 = cat(_T_1097, _T_1096) @[el2_lib.scala 246:56] - node _T_1099 = cat(_T_966[5], _T_966[4]) @[el2_lib.scala 246:56] - node _T_1100 = cat(_T_966[8], _T_966[7]) @[el2_lib.scala 246:56] - node _T_1101 = cat(_T_1100, _T_966[6]) @[el2_lib.scala 246:56] - node _T_1102 = cat(_T_1101, _T_1099) @[el2_lib.scala 246:56] - node _T_1103 = cat(_T_1102, _T_1098) @[el2_lib.scala 246:56] - node _T_1104 = cat(_T_966[10], _T_966[9]) @[el2_lib.scala 246:56] - node _T_1105 = cat(_T_966[12], _T_966[11]) @[el2_lib.scala 246:56] - node _T_1106 = cat(_T_1105, _T_1104) @[el2_lib.scala 246:56] - node _T_1107 = cat(_T_966[14], _T_966[13]) @[el2_lib.scala 246:56] - node _T_1108 = cat(_T_966[17], _T_966[16]) @[el2_lib.scala 246:56] - node _T_1109 = cat(_T_1108, _T_966[15]) @[el2_lib.scala 246:56] - node _T_1110 = cat(_T_1109, _T_1107) @[el2_lib.scala 246:56] - node _T_1111 = cat(_T_1110, _T_1106) @[el2_lib.scala 246:56] - node _T_1112 = cat(_T_1111, _T_1103) @[el2_lib.scala 246:56] - node _T_1113 = xorr(_T_1112) @[el2_lib.scala 246:63] - node _T_1114 = cat(_T_967[2], _T_967[1]) @[el2_lib.scala 246:73] - node _T_1115 = cat(_T_1114, _T_967[0]) @[el2_lib.scala 246:73] - node _T_1116 = cat(_T_967[4], _T_967[3]) @[el2_lib.scala 246:73] - node _T_1117 = cat(_T_967[6], _T_967[5]) @[el2_lib.scala 246:73] - node _T_1118 = cat(_T_1117, _T_1116) @[el2_lib.scala 246:73] - node _T_1119 = cat(_T_1118, _T_1115) @[el2_lib.scala 246:73] - node _T_1120 = cat(_T_967[8], _T_967[7]) @[el2_lib.scala 246:73] - node _T_1121 = cat(_T_967[10], _T_967[9]) @[el2_lib.scala 246:73] - node _T_1122 = cat(_T_1121, _T_1120) @[el2_lib.scala 246:73] - node _T_1123 = cat(_T_967[12], _T_967[11]) @[el2_lib.scala 246:73] - node _T_1124 = cat(_T_967[14], _T_967[13]) @[el2_lib.scala 246:73] - node _T_1125 = cat(_T_1124, _T_1123) @[el2_lib.scala 246:73] - node _T_1126 = cat(_T_1125, _T_1122) @[el2_lib.scala 246:73] - node _T_1127 = cat(_T_1126, _T_1119) @[el2_lib.scala 246:73] - node _T_1128 = xorr(_T_1127) @[el2_lib.scala 246:80] - node _T_1129 = cat(_T_968[2], _T_968[1]) @[el2_lib.scala 246:90] - node _T_1130 = cat(_T_1129, _T_968[0]) @[el2_lib.scala 246:90] - node _T_1131 = cat(_T_968[4], _T_968[3]) @[el2_lib.scala 246:90] - node _T_1132 = cat(_T_968[6], _T_968[5]) @[el2_lib.scala 246:90] - node _T_1133 = cat(_T_1132, _T_1131) @[el2_lib.scala 246:90] - node _T_1134 = cat(_T_1133, _T_1130) @[el2_lib.scala 246:90] - node _T_1135 = cat(_T_968[8], _T_968[7]) @[el2_lib.scala 246:90] - node _T_1136 = cat(_T_968[10], _T_968[9]) @[el2_lib.scala 246:90] - node _T_1137 = cat(_T_1136, _T_1135) @[el2_lib.scala 246:90] - node _T_1138 = cat(_T_968[12], _T_968[11]) @[el2_lib.scala 246:90] - node _T_1139 = cat(_T_968[14], _T_968[13]) @[el2_lib.scala 246:90] - node _T_1140 = cat(_T_1139, _T_1138) @[el2_lib.scala 246:90] - node _T_1141 = cat(_T_1140, _T_1137) @[el2_lib.scala 246:90] - node _T_1142 = cat(_T_1141, _T_1134) @[el2_lib.scala 246:90] - node _T_1143 = xorr(_T_1142) @[el2_lib.scala 246:97] - node _T_1144 = cat(_T_969[2], _T_969[1]) @[el2_lib.scala 246:107] - node _T_1145 = cat(_T_1144, _T_969[0]) @[el2_lib.scala 246:107] - node _T_1146 = cat(_T_969[5], _T_969[4]) @[el2_lib.scala 246:107] - node _T_1147 = cat(_T_1146, _T_969[3]) @[el2_lib.scala 246:107] - node _T_1148 = cat(_T_1147, _T_1145) @[el2_lib.scala 246:107] - node _T_1149 = xorr(_T_1148) @[el2_lib.scala 246:114] - node _T_1150 = cat(_T_1128, _T_1143) @[Cat.scala 29:58] - node _T_1151 = cat(_T_1150, _T_1149) @[Cat.scala 29:58] - node _T_1152 = cat(_T_1077, _T_1095) @[Cat.scala 29:58] - node _T_1153 = cat(_T_1152, _T_1113) @[Cat.scala 29:58] - node _T_1154 = cat(_T_1153, _T_1151) @[Cat.scala 29:58] - node _T_1155 = xorr(dccm_wdata_hi_any) @[el2_lib.scala 247:13] - node _T_1156 = xorr(_T_1154) @[el2_lib.scala 247:23] - node _T_1157 = xor(_T_1155, _T_1156) @[el2_lib.scala 247:18] - node lsu_ecc_encode_hi = cat(_T_1157, _T_1154) @[Cat.scala 29:58] - when UInt<1>("h00") : @[el2_lsu_ecc.scala 101:32] - node _T_1158 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_ecc.scala 102:35] - node _T_1159 = bits(io.end_addr_r, 2, 2) @[el2_lsu_ecc.scala 102:56] - node _T_1160 = neq(_T_1158, _T_1159) @[el2_lsu_ecc.scala 102:39] - ldst_dual_r <= _T_1160 @[el2_lsu_ecc.scala 102:19] - node _T_1161 = or(io.lsu_pkt_r.load, io.lsu_pkt_r.store) @[el2_lsu_ecc.scala 103:60] - node _T_1162 = and(io.lsu_pkt_r.valid, _T_1161) @[el2_lsu_ecc.scala 103:39] - node _T_1163 = and(_T_1162, io.addr_in_dccm_r) @[el2_lsu_ecc.scala 103:82] - node _T_1164 = and(_T_1163, io.lsu_dccm_rden_r) @[el2_lsu_ecc.scala 103:102] - is_ldst_r <= _T_1164 @[el2_lsu_ecc.scala 103:17] - node _T_1165 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 104:35] - node _T_1166 = and(is_ldst_r, _T_1165) @[el2_lsu_ecc.scala 104:33] - is_ldst_lo_r <= _T_1166 @[el2_lsu_ecc.scala 104:20] - node _T_1167 = or(ldst_dual_r, io.lsu_pkt_r.dma) @[el2_lsu_ecc.scala 105:48] - node _T_1168 = and(is_ldst_r, _T_1167) @[el2_lsu_ecc.scala 105:33] - node _T_1169 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 105:70] - node _T_1170 = and(_T_1168, _T_1169) @[el2_lsu_ecc.scala 105:68] - is_ldst_hi_r <= _T_1170 @[el2_lsu_ecc.scala 105:20] - is_ldst_hi_any <= is_ldst_hi_r @[el2_lsu_ecc.scala 106:23] - dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[el2_lsu_ecc.scala 107:26] - dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[el2_lsu_ecc.scala 108:28] - is_ldst_lo_any <= is_ldst_lo_r @[el2_lsu_ecc.scala 109:22] - dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[el2_lsu_ecc.scala 110:27] - dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[el2_lsu_ecc.scala 111:28] - io.sec_data_hi_r <= sec_data_hi_any @[el2_lsu_ecc.scala 112:24] - io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 113:33] - double_ecc_error_hi_r <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 114:30] - io.sec_data_lo_r <= sec_data_lo_any @[el2_lsu_ecc.scala 115:27] - io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 116:33] - double_ecc_error_lo_r <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 117:30] - node _T_1171 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[el2_lsu_ecc.scala 118:61] - io.lsu_single_ecc_error_r <= _T_1171 @[el2_lsu_ecc.scala 118:33] - node _T_1172 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[el2_lsu_ecc.scala 119:58] - io.lsu_double_ecc_error_r <= _T_1172 @[el2_lsu_ecc.scala 119:33] - skip @[el2_lsu_ecc.scala 101:32] - else : @[el2_lsu_ecc.scala 121:16] - node _T_1173 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_ecc.scala 122:35] - node _T_1174 = bits(io.end_addr_m, 2, 2) @[el2_lsu_ecc.scala 122:56] - node _T_1175 = neq(_T_1173, _T_1174) @[el2_lsu_ecc.scala 122:39] - ldst_dual_m <= _T_1175 @[el2_lsu_ecc.scala 122:19] - node _T_1176 = or(io.lsu_pkt_m.load, io.lsu_pkt_m.store) @[el2_lsu_ecc.scala 123:60] - node _T_1177 = and(io.lsu_pkt_m.valid, _T_1176) @[el2_lsu_ecc.scala 123:39] - node _T_1178 = and(_T_1177, io.addr_in_dccm_m) @[el2_lsu_ecc.scala 123:82] - node _T_1179 = and(_T_1178, io.lsu_dccm_rden_m) @[el2_lsu_ecc.scala 123:102] - is_ldst_m <= _T_1179 @[el2_lsu_ecc.scala 123:17] - node _T_1180 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 124:35] - node _T_1181 = and(is_ldst_m, _T_1180) @[el2_lsu_ecc.scala 124:33] - is_ldst_lo_m <= _T_1181 @[el2_lsu_ecc.scala 124:20] - node _T_1182 = or(ldst_dual_m, io.lsu_pkt_m.dma) @[el2_lsu_ecc.scala 125:48] - node _T_1183 = and(is_ldst_m, _T_1182) @[el2_lsu_ecc.scala 125:33] - node _T_1184 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 125:70] - node _T_1185 = and(_T_1183, _T_1184) @[el2_lsu_ecc.scala 125:68] - is_ldst_hi_m <= _T_1185 @[el2_lsu_ecc.scala 125:20] - is_ldst_hi_any <= is_ldst_hi_m @[el2_lsu_ecc.scala 126:23] - dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[el2_lsu_ecc.scala 127:26] - dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[el2_lsu_ecc.scala 128:28] - is_ldst_lo_any <= is_ldst_lo_m @[el2_lsu_ecc.scala 129:22] - dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[el2_lsu_ecc.scala 130:27] - dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[el2_lsu_ecc.scala 131:28] - io.sec_data_hi_m <= sec_data_hi_any @[el2_lsu_ecc.scala 132:27] - double_ecc_error_hi_m <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 133:30] - io.sec_data_lo_m <= sec_data_lo_any @[el2_lsu_ecc.scala 134:27] - double_ecc_error_lo_m <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 135:30] - node _T_1186 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[el2_lsu_ecc.scala 136:60] - io.lsu_single_ecc_error_m <= _T_1186 @[el2_lsu_ecc.scala 136:33] - node _T_1187 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[el2_lsu_ecc.scala 137:58] - io.lsu_double_ecc_error_m <= _T_1187 @[el2_lsu_ecc.scala 137:33] - reg _T_1188 : UInt<1>, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 139:72] - _T_1188 <= io.lsu_single_ecc_error_m @[el2_lsu_ecc.scala 139:72] - io.lsu_single_ecc_error_r <= _T_1188 @[el2_lsu_ecc.scala 139:62] - reg _T_1189 : UInt<1>, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 140:72] - _T_1189 <= io.lsu_double_ecc_error_m @[el2_lsu_ecc.scala 140:72] - io.lsu_double_ecc_error_r <= _T_1189 @[el2_lsu_ecc.scala 140:62] - reg _T_1190 : UInt, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 141:72] - _T_1190 <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 141:72] - io.single_ecc_error_lo_r <= _T_1190 @[el2_lsu_ecc.scala 141:62] - reg _T_1191 : UInt, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 142:72] - _T_1191 <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 142:72] - io.single_ecc_error_hi_r <= _T_1191 @[el2_lsu_ecc.scala 142:62] - reg _T_1192 : UInt, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 143:72] - _T_1192 <= io.sec_data_hi_m @[el2_lsu_ecc.scala 143:72] - io.sec_data_hi_r <= _T_1192 @[el2_lsu_ecc.scala 143:62] - reg _T_1193 : UInt, io.lsu_c2_r_clk @[el2_lsu_ecc.scala 144:72] - _T_1193 <= io.sec_data_lo_m @[el2_lsu_ecc.scala 144:72] - io.sec_data_lo_r <= _T_1193 @[el2_lsu_ecc.scala 144:62] - skip @[el2_lsu_ecc.scala 121:16] - node _T_1194 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 147:58] - node _T_1195 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 147:106] - node _T_1196 = mux(_T_1195, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[el2_lsu_ecc.scala 147:89] - node _T_1197 = mux(_T_1194, io.sec_data_lo_r_ff, _T_1196) @[el2_lsu_ecc.scala 147:29] - dccm_wdata_lo_any <= _T_1197 @[el2_lsu_ecc.scala 147:23] - node _T_1198 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 148:58] - node _T_1199 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 148:106] - node _T_1200 = mux(_T_1199, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[el2_lsu_ecc.scala 148:89] - node _T_1201 = mux(_T_1198, io.sec_data_hi_r_ff, _T_1200) @[el2_lsu_ecc.scala 148:29] - dccm_wdata_hi_any <= _T_1201 @[el2_lsu_ecc.scala 148:23] - io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 149:30] - io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 150:30] - io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 151:30] - io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 152:30] - io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 153:30] - reg _T_1202 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.ld_single_ecc_error_r : @[Reg.scala 28:19] - _T_1202 <= io.sec_data_hi_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - io.sec_data_hi_r_ff <= _T_1202 @[el2_lsu_ecc.scala 155:23] - reg _T_1203 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when io.ld_single_ecc_error_r : @[Reg.scala 28:19] - _T_1203 <= io.sec_data_lo_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - io.sec_data_lo_r_ff <= _T_1203 @[el2_lsu_ecc.scala 156:23] + node _T_209 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_210 = and(is_ldst_hi_any, _T_209) @[el2_lib.scala 334:32] + node _T_211 = bits(_T_208, 6, 6) @[el2_lib.scala 334:64] + node single_ecc_error_hi_any = and(_T_210, _T_211) @[el2_lib.scala 334:53] + node _T_212 = neq(_T_208, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_213 = and(is_ldst_hi_any, _T_212) @[el2_lib.scala 335:32] + node _T_214 = bits(_T_208, 6, 6) @[el2_lib.scala 335:65] + node _T_215 = not(_T_214) @[el2_lib.scala 335:55] + node double_ecc_error_hi_any = and(_T_213, _T_215) @[el2_lib.scala 335:53] + wire _T_216 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_217 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_218 = eq(_T_217, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_216[0] <= _T_218 @[el2_lib.scala 339:23] + node _T_219 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_220 = eq(_T_219, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_216[1] <= _T_220 @[el2_lib.scala 339:23] + node _T_221 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_222 = eq(_T_221, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_216[2] <= _T_222 @[el2_lib.scala 339:23] + node _T_223 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_224 = eq(_T_223, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_216[3] <= _T_224 @[el2_lib.scala 339:23] + node _T_225 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_226 = eq(_T_225, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_216[4] <= _T_226 @[el2_lib.scala 339:23] + node _T_227 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_228 = eq(_T_227, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_216[5] <= _T_228 @[el2_lib.scala 339:23] + node _T_229 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_230 = eq(_T_229, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_216[6] <= _T_230 @[el2_lib.scala 339:23] + node _T_231 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_232 = eq(_T_231, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_216[7] <= _T_232 @[el2_lib.scala 339:23] + node _T_233 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_234 = eq(_T_233, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_216[8] <= _T_234 @[el2_lib.scala 339:23] + node _T_235 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_236 = eq(_T_235, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_216[9] <= _T_236 @[el2_lib.scala 339:23] + node _T_237 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_238 = eq(_T_237, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_216[10] <= _T_238 @[el2_lib.scala 339:23] + node _T_239 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_240 = eq(_T_239, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_216[11] <= _T_240 @[el2_lib.scala 339:23] + node _T_241 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_242 = eq(_T_241, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_216[12] <= _T_242 @[el2_lib.scala 339:23] + node _T_243 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_244 = eq(_T_243, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_216[13] <= _T_244 @[el2_lib.scala 339:23] + node _T_245 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_246 = eq(_T_245, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_216[14] <= _T_246 @[el2_lib.scala 339:23] + node _T_247 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_248 = eq(_T_247, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_216[15] <= _T_248 @[el2_lib.scala 339:23] + node _T_249 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_250 = eq(_T_249, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_216[16] <= _T_250 @[el2_lib.scala 339:23] + node _T_251 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_252 = eq(_T_251, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_216[17] <= _T_252 @[el2_lib.scala 339:23] + node _T_253 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_254 = eq(_T_253, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_216[18] <= _T_254 @[el2_lib.scala 339:23] + node _T_255 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_256 = eq(_T_255, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_216[19] <= _T_256 @[el2_lib.scala 339:23] + node _T_257 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_258 = eq(_T_257, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_216[20] <= _T_258 @[el2_lib.scala 339:23] + node _T_259 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_260 = eq(_T_259, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_216[21] <= _T_260 @[el2_lib.scala 339:23] + node _T_261 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_262 = eq(_T_261, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_216[22] <= _T_262 @[el2_lib.scala 339:23] + node _T_263 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_264 = eq(_T_263, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_216[23] <= _T_264 @[el2_lib.scala 339:23] + node _T_265 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_266 = eq(_T_265, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_216[24] <= _T_266 @[el2_lib.scala 339:23] + node _T_267 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_268 = eq(_T_267, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_216[25] <= _T_268 @[el2_lib.scala 339:23] + node _T_269 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_270 = eq(_T_269, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_216[26] <= _T_270 @[el2_lib.scala 339:23] + node _T_271 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_272 = eq(_T_271, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_216[27] <= _T_272 @[el2_lib.scala 339:23] + node _T_273 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_274 = eq(_T_273, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_216[28] <= _T_274 @[el2_lib.scala 339:23] + node _T_275 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_276 = eq(_T_275, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_216[29] <= _T_276 @[el2_lib.scala 339:23] + node _T_277 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_278 = eq(_T_277, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_216[30] <= _T_278 @[el2_lib.scala 339:23] + node _T_279 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_280 = eq(_T_279, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_216[31] <= _T_280 @[el2_lib.scala 339:23] + node _T_281 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_282 = eq(_T_281, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_216[32] <= _T_282 @[el2_lib.scala 339:23] + node _T_283 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_284 = eq(_T_283, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_216[33] <= _T_284 @[el2_lib.scala 339:23] + node _T_285 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_286 = eq(_T_285, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_216[34] <= _T_286 @[el2_lib.scala 339:23] + node _T_287 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_288 = eq(_T_287, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_216[35] <= _T_288 @[el2_lib.scala 339:23] + node _T_289 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_290 = eq(_T_289, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_216[36] <= _T_290 @[el2_lib.scala 339:23] + node _T_291 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_292 = eq(_T_291, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_216[37] <= _T_292 @[el2_lib.scala 339:23] + node _T_293 = bits(_T_208, 5, 0) @[el2_lib.scala 339:35] + node _T_294 = eq(_T_293, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_216[38] <= _T_294 @[el2_lib.scala 339:23] + node _T_295 = bits(dccm_data_ecc_hi_any, 6, 6) @[el2_lib.scala 341:37] + node _T_296 = bits(dccm_rdata_hi_any, 31, 26) @[el2_lib.scala 341:45] + node _T_297 = bits(dccm_data_ecc_hi_any, 5, 5) @[el2_lib.scala 341:60] + node _T_298 = bits(dccm_rdata_hi_any, 25, 11) @[el2_lib.scala 341:68] + node _T_299 = bits(dccm_data_ecc_hi_any, 4, 4) @[el2_lib.scala 341:83] + node _T_300 = bits(dccm_rdata_hi_any, 10, 4) @[el2_lib.scala 341:91] + node _T_301 = bits(dccm_data_ecc_hi_any, 3, 3) @[el2_lib.scala 341:105] + node _T_302 = bits(dccm_rdata_hi_any, 3, 1) @[el2_lib.scala 341:113] + node _T_303 = bits(dccm_data_ecc_hi_any, 2, 2) @[el2_lib.scala 341:126] + node _T_304 = bits(dccm_rdata_hi_any, 0, 0) @[el2_lib.scala 341:134] + node _T_305 = bits(dccm_data_ecc_hi_any, 1, 0) @[el2_lib.scala 341:145] + node _T_306 = cat(_T_304, _T_305) @[Cat.scala 29:58] + node _T_307 = cat(_T_301, _T_302) @[Cat.scala 29:58] + node _T_308 = cat(_T_307, _T_303) @[Cat.scala 29:58] + node _T_309 = cat(_T_308, _T_306) @[Cat.scala 29:58] + node _T_310 = cat(_T_298, _T_299) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_300) @[Cat.scala 29:58] + node _T_312 = cat(_T_295, _T_296) @[Cat.scala 29:58] + node _T_313 = cat(_T_312, _T_297) @[Cat.scala 29:58] + node _T_314 = cat(_T_313, _T_311) @[Cat.scala 29:58] + node _T_315 = cat(_T_314, _T_309) @[Cat.scala 29:58] + node _T_316 = bits(single_ecc_error_hi_any, 0, 0) @[el2_lib.scala 342:49] + node _T_317 = cat(_T_216[1], _T_216[0]) @[el2_lib.scala 342:69] + node _T_318 = cat(_T_216[3], _T_216[2]) @[el2_lib.scala 342:69] + node _T_319 = cat(_T_318, _T_317) @[el2_lib.scala 342:69] + node _T_320 = cat(_T_216[5], _T_216[4]) @[el2_lib.scala 342:69] + node _T_321 = cat(_T_216[8], _T_216[7]) @[el2_lib.scala 342:69] + node _T_322 = cat(_T_321, _T_216[6]) @[el2_lib.scala 342:69] + node _T_323 = cat(_T_322, _T_320) @[el2_lib.scala 342:69] + node _T_324 = cat(_T_323, _T_319) @[el2_lib.scala 342:69] + node _T_325 = cat(_T_216[10], _T_216[9]) @[el2_lib.scala 342:69] + node _T_326 = cat(_T_216[13], _T_216[12]) @[el2_lib.scala 342:69] + node _T_327 = cat(_T_326, _T_216[11]) @[el2_lib.scala 342:69] + node _T_328 = cat(_T_327, _T_325) @[el2_lib.scala 342:69] + node _T_329 = cat(_T_216[15], _T_216[14]) @[el2_lib.scala 342:69] + node _T_330 = cat(_T_216[18], _T_216[17]) @[el2_lib.scala 342:69] + node _T_331 = cat(_T_330, _T_216[16]) @[el2_lib.scala 342:69] + node _T_332 = cat(_T_331, _T_329) @[el2_lib.scala 342:69] + node _T_333 = cat(_T_332, _T_328) @[el2_lib.scala 342:69] + node _T_334 = cat(_T_333, _T_324) @[el2_lib.scala 342:69] + node _T_335 = cat(_T_216[20], _T_216[19]) @[el2_lib.scala 342:69] + node _T_336 = cat(_T_216[23], _T_216[22]) @[el2_lib.scala 342:69] + node _T_337 = cat(_T_336, _T_216[21]) @[el2_lib.scala 342:69] + node _T_338 = cat(_T_337, _T_335) @[el2_lib.scala 342:69] + node _T_339 = cat(_T_216[25], _T_216[24]) @[el2_lib.scala 342:69] + node _T_340 = cat(_T_216[28], _T_216[27]) @[el2_lib.scala 342:69] + node _T_341 = cat(_T_340, _T_216[26]) @[el2_lib.scala 342:69] + node _T_342 = cat(_T_341, _T_339) @[el2_lib.scala 342:69] + node _T_343 = cat(_T_342, _T_338) @[el2_lib.scala 342:69] + node _T_344 = cat(_T_216[30], _T_216[29]) @[el2_lib.scala 342:69] + node _T_345 = cat(_T_216[33], _T_216[32]) @[el2_lib.scala 342:69] + node _T_346 = cat(_T_345, _T_216[31]) @[el2_lib.scala 342:69] + node _T_347 = cat(_T_346, _T_344) @[el2_lib.scala 342:69] + node _T_348 = cat(_T_216[35], _T_216[34]) @[el2_lib.scala 342:69] + node _T_349 = cat(_T_216[38], _T_216[37]) @[el2_lib.scala 342:69] + node _T_350 = cat(_T_349, _T_216[36]) @[el2_lib.scala 342:69] + node _T_351 = cat(_T_350, _T_348) @[el2_lib.scala 342:69] + node _T_352 = cat(_T_351, _T_347) @[el2_lib.scala 342:69] + node _T_353 = cat(_T_352, _T_343) @[el2_lib.scala 342:69] + node _T_354 = cat(_T_353, _T_334) @[el2_lib.scala 342:69] + node _T_355 = xor(_T_354, _T_315) @[el2_lib.scala 342:76] + node _T_356 = mux(_T_316, _T_355, _T_315) @[el2_lib.scala 342:31] + node _T_357 = bits(_T_356, 37, 32) @[el2_lib.scala 344:37] + node _T_358 = bits(_T_356, 30, 16) @[el2_lib.scala 344:61] + node _T_359 = bits(_T_356, 14, 8) @[el2_lib.scala 344:86] + node _T_360 = bits(_T_356, 6, 4) @[el2_lib.scala 344:110] + node _T_361 = bits(_T_356, 2, 2) @[el2_lib.scala 344:133] + node _T_362 = cat(_T_360, _T_361) @[Cat.scala 29:58] + node _T_363 = cat(_T_357, _T_358) @[Cat.scala 29:58] + node _T_364 = cat(_T_363, _T_359) @[Cat.scala 29:58] + node sec_data_hi_any = cat(_T_364, _T_362) @[Cat.scala 29:58] + node _T_365 = bits(_T_356, 38, 38) @[el2_lib.scala 345:39] + node _T_366 = bits(_T_208, 6, 0) @[el2_lib.scala 345:56] + node _T_367 = eq(_T_366, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_368 = xor(_T_365, _T_367) @[el2_lib.scala 345:44] + node _T_369 = bits(_T_356, 31, 31) @[el2_lib.scala 345:102] + node _T_370 = bits(_T_356, 15, 15) @[el2_lib.scala 345:124] + node _T_371 = bits(_T_356, 7, 7) @[el2_lib.scala 345:146] + node _T_372 = bits(_T_356, 3, 3) @[el2_lib.scala 345:167] + node _T_373 = bits(_T_356, 1, 0) @[el2_lib.scala 345:188] + node _T_374 = cat(_T_371, _T_372) @[Cat.scala 29:58] + node _T_375 = cat(_T_374, _T_373) @[Cat.scala 29:58] + node _T_376 = cat(_T_368, _T_369) @[Cat.scala 29:58] + node _T_377 = cat(_T_376, _T_370) @[Cat.scala 29:58] + node ecc_out_hi_nc = cat(_T_377, _T_375) @[Cat.scala 29:58] + wire _T_378 : UInt<1>[18] @[el2_lib.scala 313:18] + wire _T_379 : UInt<1>[18] @[el2_lib.scala 314:18] + wire _T_380 : UInt<1>[18] @[el2_lib.scala 315:18] + wire _T_381 : UInt<1>[15] @[el2_lib.scala 316:18] + wire _T_382 : UInt<1>[15] @[el2_lib.scala 317:18] + wire _T_383 : UInt<1>[6] @[el2_lib.scala 318:18] + node _T_384 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 325:36] + _T_378[0] <= _T_384 @[el2_lib.scala 325:30] + node _T_385 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 326:36] + _T_379[0] <= _T_385 @[el2_lib.scala 326:30] + node _T_386 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 325:36] + _T_378[1] <= _T_386 @[el2_lib.scala 325:30] + node _T_387 = bits(dccm_rdata_lo_any, 1, 1) @[el2_lib.scala 327:36] + _T_380[0] <= _T_387 @[el2_lib.scala 327:30] + node _T_388 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 326:36] + _T_379[1] <= _T_388 @[el2_lib.scala 326:30] + node _T_389 = bits(dccm_rdata_lo_any, 2, 2) @[el2_lib.scala 327:36] + _T_380[1] <= _T_389 @[el2_lib.scala 327:30] + node _T_390 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 325:36] + _T_378[2] <= _T_390 @[el2_lib.scala 325:30] + node _T_391 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 326:36] + _T_379[2] <= _T_391 @[el2_lib.scala 326:30] + node _T_392 = bits(dccm_rdata_lo_any, 3, 3) @[el2_lib.scala 327:36] + _T_380[2] <= _T_392 @[el2_lib.scala 327:30] + node _T_393 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 325:36] + _T_378[3] <= _T_393 @[el2_lib.scala 325:30] + node _T_394 = bits(dccm_rdata_lo_any, 4, 4) @[el2_lib.scala 328:36] + _T_381[0] <= _T_394 @[el2_lib.scala 328:30] + node _T_395 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 326:36] + _T_379[3] <= _T_395 @[el2_lib.scala 326:30] + node _T_396 = bits(dccm_rdata_lo_any, 5, 5) @[el2_lib.scala 328:36] + _T_381[1] <= _T_396 @[el2_lib.scala 328:30] + node _T_397 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 325:36] + _T_378[4] <= _T_397 @[el2_lib.scala 325:30] + node _T_398 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 326:36] + _T_379[4] <= _T_398 @[el2_lib.scala 326:30] + node _T_399 = bits(dccm_rdata_lo_any, 6, 6) @[el2_lib.scala 328:36] + _T_381[2] <= _T_399 @[el2_lib.scala 328:30] + node _T_400 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 327:36] + _T_380[3] <= _T_400 @[el2_lib.scala 327:30] + node _T_401 = bits(dccm_rdata_lo_any, 7, 7) @[el2_lib.scala 328:36] + _T_381[3] <= _T_401 @[el2_lib.scala 328:30] + node _T_402 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 325:36] + _T_378[5] <= _T_402 @[el2_lib.scala 325:30] + node _T_403 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 327:36] + _T_380[4] <= _T_403 @[el2_lib.scala 327:30] + node _T_404 = bits(dccm_rdata_lo_any, 8, 8) @[el2_lib.scala 328:36] + _T_381[4] <= _T_404 @[el2_lib.scala 328:30] + node _T_405 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 326:36] + _T_379[5] <= _T_405 @[el2_lib.scala 326:30] + node _T_406 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 327:36] + _T_380[5] <= _T_406 @[el2_lib.scala 327:30] + node _T_407 = bits(dccm_rdata_lo_any, 9, 9) @[el2_lib.scala 328:36] + _T_381[5] <= _T_407 @[el2_lib.scala 328:30] + node _T_408 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 325:36] + _T_378[6] <= _T_408 @[el2_lib.scala 325:30] + node _T_409 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 326:36] + _T_379[6] <= _T_409 @[el2_lib.scala 326:30] + node _T_410 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 327:36] + _T_380[6] <= _T_410 @[el2_lib.scala 327:30] + node _T_411 = bits(dccm_rdata_lo_any, 10, 10) @[el2_lib.scala 328:36] + _T_381[6] <= _T_411 @[el2_lib.scala 328:30] + node _T_412 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 325:36] + _T_378[7] <= _T_412 @[el2_lib.scala 325:30] + node _T_413 = bits(dccm_rdata_lo_any, 11, 11) @[el2_lib.scala 329:36] + _T_382[0] <= _T_413 @[el2_lib.scala 329:30] + node _T_414 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 326:36] + _T_379[7] <= _T_414 @[el2_lib.scala 326:30] + node _T_415 = bits(dccm_rdata_lo_any, 12, 12) @[el2_lib.scala 329:36] + _T_382[1] <= _T_415 @[el2_lib.scala 329:30] + node _T_416 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 325:36] + _T_378[8] <= _T_416 @[el2_lib.scala 325:30] + node _T_417 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 326:36] + _T_379[8] <= _T_417 @[el2_lib.scala 326:30] + node _T_418 = bits(dccm_rdata_lo_any, 13, 13) @[el2_lib.scala 329:36] + _T_382[2] <= _T_418 @[el2_lib.scala 329:30] + node _T_419 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 327:36] + _T_380[7] <= _T_419 @[el2_lib.scala 327:30] + node _T_420 = bits(dccm_rdata_lo_any, 14, 14) @[el2_lib.scala 329:36] + _T_382[3] <= _T_420 @[el2_lib.scala 329:30] + node _T_421 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 325:36] + _T_378[9] <= _T_421 @[el2_lib.scala 325:30] + node _T_422 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 327:36] + _T_380[8] <= _T_422 @[el2_lib.scala 327:30] + node _T_423 = bits(dccm_rdata_lo_any, 15, 15) @[el2_lib.scala 329:36] + _T_382[4] <= _T_423 @[el2_lib.scala 329:30] + node _T_424 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 326:36] + _T_379[9] <= _T_424 @[el2_lib.scala 326:30] + node _T_425 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 327:36] + _T_380[9] <= _T_425 @[el2_lib.scala 327:30] + node _T_426 = bits(dccm_rdata_lo_any, 16, 16) @[el2_lib.scala 329:36] + _T_382[5] <= _T_426 @[el2_lib.scala 329:30] + node _T_427 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 325:36] + _T_378[10] <= _T_427 @[el2_lib.scala 325:30] + node _T_428 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 326:36] + _T_379[10] <= _T_428 @[el2_lib.scala 326:30] + node _T_429 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 327:36] + _T_380[10] <= _T_429 @[el2_lib.scala 327:30] + node _T_430 = bits(dccm_rdata_lo_any, 17, 17) @[el2_lib.scala 329:36] + _T_382[6] <= _T_430 @[el2_lib.scala 329:30] + node _T_431 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 328:36] + _T_381[7] <= _T_431 @[el2_lib.scala 328:30] + node _T_432 = bits(dccm_rdata_lo_any, 18, 18) @[el2_lib.scala 329:36] + _T_382[7] <= _T_432 @[el2_lib.scala 329:30] + node _T_433 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 325:36] + _T_378[11] <= _T_433 @[el2_lib.scala 325:30] + node _T_434 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 328:36] + _T_381[8] <= _T_434 @[el2_lib.scala 328:30] + node _T_435 = bits(dccm_rdata_lo_any, 19, 19) @[el2_lib.scala 329:36] + _T_382[8] <= _T_435 @[el2_lib.scala 329:30] + node _T_436 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 326:36] + _T_379[11] <= _T_436 @[el2_lib.scala 326:30] + node _T_437 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 328:36] + _T_381[9] <= _T_437 @[el2_lib.scala 328:30] + node _T_438 = bits(dccm_rdata_lo_any, 20, 20) @[el2_lib.scala 329:36] + _T_382[9] <= _T_438 @[el2_lib.scala 329:30] + node _T_439 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 325:36] + _T_378[12] <= _T_439 @[el2_lib.scala 325:30] + node _T_440 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 326:36] + _T_379[12] <= _T_440 @[el2_lib.scala 326:30] + node _T_441 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 328:36] + _T_381[10] <= _T_441 @[el2_lib.scala 328:30] + node _T_442 = bits(dccm_rdata_lo_any, 21, 21) @[el2_lib.scala 329:36] + _T_382[10] <= _T_442 @[el2_lib.scala 329:30] + node _T_443 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 327:36] + _T_380[11] <= _T_443 @[el2_lib.scala 327:30] + node _T_444 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 328:36] + _T_381[11] <= _T_444 @[el2_lib.scala 328:30] + node _T_445 = bits(dccm_rdata_lo_any, 22, 22) @[el2_lib.scala 329:36] + _T_382[11] <= _T_445 @[el2_lib.scala 329:30] + node _T_446 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 325:36] + _T_378[13] <= _T_446 @[el2_lib.scala 325:30] + node _T_447 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 327:36] + _T_380[12] <= _T_447 @[el2_lib.scala 327:30] + node _T_448 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 328:36] + _T_381[12] <= _T_448 @[el2_lib.scala 328:30] + node _T_449 = bits(dccm_rdata_lo_any, 23, 23) @[el2_lib.scala 329:36] + _T_382[12] <= _T_449 @[el2_lib.scala 329:30] + node _T_450 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 326:36] + _T_379[13] <= _T_450 @[el2_lib.scala 326:30] + node _T_451 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 327:36] + _T_380[13] <= _T_451 @[el2_lib.scala 327:30] + node _T_452 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 328:36] + _T_381[13] <= _T_452 @[el2_lib.scala 328:30] + node _T_453 = bits(dccm_rdata_lo_any, 24, 24) @[el2_lib.scala 329:36] + _T_382[13] <= _T_453 @[el2_lib.scala 329:30] + node _T_454 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 325:36] + _T_378[14] <= _T_454 @[el2_lib.scala 325:30] + node _T_455 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 326:36] + _T_379[14] <= _T_455 @[el2_lib.scala 326:30] + node _T_456 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 327:36] + _T_380[14] <= _T_456 @[el2_lib.scala 327:30] + node _T_457 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 328:36] + _T_381[14] <= _T_457 @[el2_lib.scala 328:30] + node _T_458 = bits(dccm_rdata_lo_any, 25, 25) @[el2_lib.scala 329:36] + _T_382[14] <= _T_458 @[el2_lib.scala 329:30] + node _T_459 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 325:36] + _T_378[15] <= _T_459 @[el2_lib.scala 325:30] + node _T_460 = bits(dccm_rdata_lo_any, 26, 26) @[el2_lib.scala 330:36] + _T_383[0] <= _T_460 @[el2_lib.scala 330:30] + node _T_461 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 326:36] + _T_379[15] <= _T_461 @[el2_lib.scala 326:30] + node _T_462 = bits(dccm_rdata_lo_any, 27, 27) @[el2_lib.scala 330:36] + _T_383[1] <= _T_462 @[el2_lib.scala 330:30] + node _T_463 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 325:36] + _T_378[16] <= _T_463 @[el2_lib.scala 325:30] + node _T_464 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 326:36] + _T_379[16] <= _T_464 @[el2_lib.scala 326:30] + node _T_465 = bits(dccm_rdata_lo_any, 28, 28) @[el2_lib.scala 330:36] + _T_383[2] <= _T_465 @[el2_lib.scala 330:30] + node _T_466 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 327:36] + _T_380[15] <= _T_466 @[el2_lib.scala 327:30] + node _T_467 = bits(dccm_rdata_lo_any, 29, 29) @[el2_lib.scala 330:36] + _T_383[3] <= _T_467 @[el2_lib.scala 330:30] + node _T_468 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 325:36] + _T_378[17] <= _T_468 @[el2_lib.scala 325:30] + node _T_469 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 327:36] + _T_380[16] <= _T_469 @[el2_lib.scala 327:30] + node _T_470 = bits(dccm_rdata_lo_any, 30, 30) @[el2_lib.scala 330:36] + _T_383[4] <= _T_470 @[el2_lib.scala 330:30] + node _T_471 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 326:36] + _T_379[17] <= _T_471 @[el2_lib.scala 326:30] + node _T_472 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 327:36] + _T_380[17] <= _T_472 @[el2_lib.scala 327:30] + node _T_473 = bits(dccm_rdata_lo_any, 31, 31) @[el2_lib.scala 330:36] + _T_383[5] <= _T_473 @[el2_lib.scala 330:30] + node _T_474 = xorr(dccm_rdata_lo_any) @[el2_lib.scala 333:30] + node _T_475 = xorr(dccm_data_ecc_lo_any) @[el2_lib.scala 333:44] + node _T_476 = xor(_T_474, _T_475) @[el2_lib.scala 333:35] + node _T_477 = not(UInt<1>("h00")) @[el2_lib.scala 333:52] + node _T_478 = and(_T_476, _T_477) @[el2_lib.scala 333:50] + node _T_479 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 333:68] + node _T_480 = cat(_T_383[2], _T_383[1]) @[el2_lib.scala 333:76] + node _T_481 = cat(_T_480, _T_383[0]) @[el2_lib.scala 333:76] + node _T_482 = cat(_T_383[5], _T_383[4]) @[el2_lib.scala 333:76] + node _T_483 = cat(_T_482, _T_383[3]) @[el2_lib.scala 333:76] + node _T_484 = cat(_T_483, _T_481) @[el2_lib.scala 333:76] + node _T_485 = xorr(_T_484) @[el2_lib.scala 333:83] + node _T_486 = xor(_T_479, _T_485) @[el2_lib.scala 333:71] + node _T_487 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 333:95] + node _T_488 = cat(_T_382[2], _T_382[1]) @[el2_lib.scala 333:103] + node _T_489 = cat(_T_488, _T_382[0]) @[el2_lib.scala 333:103] + node _T_490 = cat(_T_382[4], _T_382[3]) @[el2_lib.scala 333:103] + node _T_491 = cat(_T_382[6], _T_382[5]) @[el2_lib.scala 333:103] + node _T_492 = cat(_T_491, _T_490) @[el2_lib.scala 333:103] + node _T_493 = cat(_T_492, _T_489) @[el2_lib.scala 333:103] + node _T_494 = cat(_T_382[8], _T_382[7]) @[el2_lib.scala 333:103] + node _T_495 = cat(_T_382[10], _T_382[9]) @[el2_lib.scala 333:103] + node _T_496 = cat(_T_495, _T_494) @[el2_lib.scala 333:103] + node _T_497 = cat(_T_382[12], _T_382[11]) @[el2_lib.scala 333:103] + node _T_498 = cat(_T_382[14], _T_382[13]) @[el2_lib.scala 333:103] + node _T_499 = cat(_T_498, _T_497) @[el2_lib.scala 333:103] + node _T_500 = cat(_T_499, _T_496) @[el2_lib.scala 333:103] + node _T_501 = cat(_T_500, _T_493) @[el2_lib.scala 333:103] + node _T_502 = xorr(_T_501) @[el2_lib.scala 333:110] + node _T_503 = xor(_T_487, _T_502) @[el2_lib.scala 333:98] + node _T_504 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 333:122] + node _T_505 = cat(_T_381[2], _T_381[1]) @[el2_lib.scala 333:130] + node _T_506 = cat(_T_505, _T_381[0]) @[el2_lib.scala 333:130] + node _T_507 = cat(_T_381[4], _T_381[3]) @[el2_lib.scala 333:130] + node _T_508 = cat(_T_381[6], _T_381[5]) @[el2_lib.scala 333:130] + node _T_509 = cat(_T_508, _T_507) @[el2_lib.scala 333:130] + node _T_510 = cat(_T_509, _T_506) @[el2_lib.scala 333:130] + node _T_511 = cat(_T_381[8], _T_381[7]) @[el2_lib.scala 333:130] + node _T_512 = cat(_T_381[10], _T_381[9]) @[el2_lib.scala 333:130] + node _T_513 = cat(_T_512, _T_511) @[el2_lib.scala 333:130] + node _T_514 = cat(_T_381[12], _T_381[11]) @[el2_lib.scala 333:130] + node _T_515 = cat(_T_381[14], _T_381[13]) @[el2_lib.scala 333:130] + node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 333:130] + node _T_517 = cat(_T_516, _T_513) @[el2_lib.scala 333:130] + node _T_518 = cat(_T_517, _T_510) @[el2_lib.scala 333:130] + node _T_519 = xorr(_T_518) @[el2_lib.scala 333:137] + node _T_520 = xor(_T_504, _T_519) @[el2_lib.scala 333:125] + node _T_521 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 333:149] + node _T_522 = cat(_T_380[1], _T_380[0]) @[el2_lib.scala 333:157] + node _T_523 = cat(_T_380[3], _T_380[2]) @[el2_lib.scala 333:157] + node _T_524 = cat(_T_523, _T_522) @[el2_lib.scala 333:157] + node _T_525 = cat(_T_380[5], _T_380[4]) @[el2_lib.scala 333:157] + node _T_526 = cat(_T_380[8], _T_380[7]) @[el2_lib.scala 333:157] + node _T_527 = cat(_T_526, _T_380[6]) @[el2_lib.scala 333:157] + node _T_528 = cat(_T_527, _T_525) @[el2_lib.scala 333:157] + node _T_529 = cat(_T_528, _T_524) @[el2_lib.scala 333:157] + node _T_530 = cat(_T_380[10], _T_380[9]) @[el2_lib.scala 333:157] + node _T_531 = cat(_T_380[12], _T_380[11]) @[el2_lib.scala 333:157] + node _T_532 = cat(_T_531, _T_530) @[el2_lib.scala 333:157] + node _T_533 = cat(_T_380[14], _T_380[13]) @[el2_lib.scala 333:157] + node _T_534 = cat(_T_380[17], _T_380[16]) @[el2_lib.scala 333:157] + node _T_535 = cat(_T_534, _T_380[15]) @[el2_lib.scala 333:157] + node _T_536 = cat(_T_535, _T_533) @[el2_lib.scala 333:157] + node _T_537 = cat(_T_536, _T_532) @[el2_lib.scala 333:157] + node _T_538 = cat(_T_537, _T_529) @[el2_lib.scala 333:157] + node _T_539 = xorr(_T_538) @[el2_lib.scala 333:164] + node _T_540 = xor(_T_521, _T_539) @[el2_lib.scala 333:152] + node _T_541 = bits(dccm_data_ecc_lo_any, 1, 1) @[el2_lib.scala 333:176] + node _T_542 = cat(_T_379[1], _T_379[0]) @[el2_lib.scala 333:184] + node _T_543 = cat(_T_379[3], _T_379[2]) @[el2_lib.scala 333:184] + node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 333:184] + node _T_545 = cat(_T_379[5], _T_379[4]) @[el2_lib.scala 333:184] + node _T_546 = cat(_T_379[8], _T_379[7]) @[el2_lib.scala 333:184] + node _T_547 = cat(_T_546, _T_379[6]) @[el2_lib.scala 333:184] + node _T_548 = cat(_T_547, _T_545) @[el2_lib.scala 333:184] + node _T_549 = cat(_T_548, _T_544) @[el2_lib.scala 333:184] + node _T_550 = cat(_T_379[10], _T_379[9]) @[el2_lib.scala 333:184] + node _T_551 = cat(_T_379[12], _T_379[11]) @[el2_lib.scala 333:184] + node _T_552 = cat(_T_551, _T_550) @[el2_lib.scala 333:184] + node _T_553 = cat(_T_379[14], _T_379[13]) @[el2_lib.scala 333:184] + node _T_554 = cat(_T_379[17], _T_379[16]) @[el2_lib.scala 333:184] + node _T_555 = cat(_T_554, _T_379[15]) @[el2_lib.scala 333:184] + node _T_556 = cat(_T_555, _T_553) @[el2_lib.scala 333:184] + node _T_557 = cat(_T_556, _T_552) @[el2_lib.scala 333:184] + node _T_558 = cat(_T_557, _T_549) @[el2_lib.scala 333:184] + node _T_559 = xorr(_T_558) @[el2_lib.scala 333:191] + node _T_560 = xor(_T_541, _T_559) @[el2_lib.scala 333:179] + node _T_561 = bits(dccm_data_ecc_lo_any, 0, 0) @[el2_lib.scala 333:203] + node _T_562 = cat(_T_378[1], _T_378[0]) @[el2_lib.scala 333:211] + node _T_563 = cat(_T_378[3], _T_378[2]) @[el2_lib.scala 333:211] + node _T_564 = cat(_T_563, _T_562) @[el2_lib.scala 333:211] + node _T_565 = cat(_T_378[5], _T_378[4]) @[el2_lib.scala 333:211] + node _T_566 = cat(_T_378[8], _T_378[7]) @[el2_lib.scala 333:211] + node _T_567 = cat(_T_566, _T_378[6]) @[el2_lib.scala 333:211] + node _T_568 = cat(_T_567, _T_565) @[el2_lib.scala 333:211] + node _T_569 = cat(_T_568, _T_564) @[el2_lib.scala 333:211] + node _T_570 = cat(_T_378[10], _T_378[9]) @[el2_lib.scala 333:211] + node _T_571 = cat(_T_378[12], _T_378[11]) @[el2_lib.scala 333:211] + node _T_572 = cat(_T_571, _T_570) @[el2_lib.scala 333:211] + node _T_573 = cat(_T_378[14], _T_378[13]) @[el2_lib.scala 333:211] + node _T_574 = cat(_T_378[17], _T_378[16]) @[el2_lib.scala 333:211] + node _T_575 = cat(_T_574, _T_378[15]) @[el2_lib.scala 333:211] + node _T_576 = cat(_T_575, _T_573) @[el2_lib.scala 333:211] + node _T_577 = cat(_T_576, _T_572) @[el2_lib.scala 333:211] + node _T_578 = cat(_T_577, _T_569) @[el2_lib.scala 333:211] + node _T_579 = xorr(_T_578) @[el2_lib.scala 333:218] + node _T_580 = xor(_T_561, _T_579) @[el2_lib.scala 333:206] + node _T_581 = cat(_T_540, _T_560) @[Cat.scala 29:58] + node _T_582 = cat(_T_581, _T_580) @[Cat.scala 29:58] + node _T_583 = cat(_T_503, _T_520) @[Cat.scala 29:58] + node _T_584 = cat(_T_478, _T_486) @[Cat.scala 29:58] + node _T_585 = cat(_T_584, _T_583) @[Cat.scala 29:58] + node _T_586 = cat(_T_585, _T_582) @[Cat.scala 29:58] + node _T_587 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 334:44] + node _T_588 = and(is_ldst_lo_any, _T_587) @[el2_lib.scala 334:32] + node _T_589 = bits(_T_586, 6, 6) @[el2_lib.scala 334:64] + node single_ecc_error_lo_any = and(_T_588, _T_589) @[el2_lib.scala 334:53] + node _T_590 = neq(_T_586, UInt<1>("h00")) @[el2_lib.scala 335:44] + node _T_591 = and(is_ldst_lo_any, _T_590) @[el2_lib.scala 335:32] + node _T_592 = bits(_T_586, 6, 6) @[el2_lib.scala 335:65] + node _T_593 = not(_T_592) @[el2_lib.scala 335:55] + node double_ecc_error_lo_any = and(_T_591, _T_593) @[el2_lib.scala 335:53] + wire _T_594 : UInt<1>[39] @[el2_lib.scala 336:26] + node _T_595 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_596 = eq(_T_595, UInt<1>("h01")) @[el2_lib.scala 339:41] + _T_594[0] <= _T_596 @[el2_lib.scala 339:23] + node _T_597 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_lib.scala 339:41] + _T_594[1] <= _T_598 @[el2_lib.scala 339:23] + node _T_599 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_600 = eq(_T_599, UInt<2>("h03")) @[el2_lib.scala 339:41] + _T_594[2] <= _T_600 @[el2_lib.scala 339:23] + node _T_601 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_602 = eq(_T_601, UInt<3>("h04")) @[el2_lib.scala 339:41] + _T_594[3] <= _T_602 @[el2_lib.scala 339:23] + node _T_603 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_604 = eq(_T_603, UInt<3>("h05")) @[el2_lib.scala 339:41] + _T_594[4] <= _T_604 @[el2_lib.scala 339:23] + node _T_605 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_606 = eq(_T_605, UInt<3>("h06")) @[el2_lib.scala 339:41] + _T_594[5] <= _T_606 @[el2_lib.scala 339:23] + node _T_607 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_608 = eq(_T_607, UInt<3>("h07")) @[el2_lib.scala 339:41] + _T_594[6] <= _T_608 @[el2_lib.scala 339:23] + node _T_609 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_610 = eq(_T_609, UInt<4>("h08")) @[el2_lib.scala 339:41] + _T_594[7] <= _T_610 @[el2_lib.scala 339:23] + node _T_611 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_612 = eq(_T_611, UInt<4>("h09")) @[el2_lib.scala 339:41] + _T_594[8] <= _T_612 @[el2_lib.scala 339:23] + node _T_613 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_614 = eq(_T_613, UInt<4>("h0a")) @[el2_lib.scala 339:41] + _T_594[9] <= _T_614 @[el2_lib.scala 339:23] + node _T_615 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_616 = eq(_T_615, UInt<4>("h0b")) @[el2_lib.scala 339:41] + _T_594[10] <= _T_616 @[el2_lib.scala 339:23] + node _T_617 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_618 = eq(_T_617, UInt<4>("h0c")) @[el2_lib.scala 339:41] + _T_594[11] <= _T_618 @[el2_lib.scala 339:23] + node _T_619 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_620 = eq(_T_619, UInt<4>("h0d")) @[el2_lib.scala 339:41] + _T_594[12] <= _T_620 @[el2_lib.scala 339:23] + node _T_621 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_622 = eq(_T_621, UInt<4>("h0e")) @[el2_lib.scala 339:41] + _T_594[13] <= _T_622 @[el2_lib.scala 339:23] + node _T_623 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_624 = eq(_T_623, UInt<4>("h0f")) @[el2_lib.scala 339:41] + _T_594[14] <= _T_624 @[el2_lib.scala 339:23] + node _T_625 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_626 = eq(_T_625, UInt<5>("h010")) @[el2_lib.scala 339:41] + _T_594[15] <= _T_626 @[el2_lib.scala 339:23] + node _T_627 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_628 = eq(_T_627, UInt<5>("h011")) @[el2_lib.scala 339:41] + _T_594[16] <= _T_628 @[el2_lib.scala 339:23] + node _T_629 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_630 = eq(_T_629, UInt<5>("h012")) @[el2_lib.scala 339:41] + _T_594[17] <= _T_630 @[el2_lib.scala 339:23] + node _T_631 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_632 = eq(_T_631, UInt<5>("h013")) @[el2_lib.scala 339:41] + _T_594[18] <= _T_632 @[el2_lib.scala 339:23] + node _T_633 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_634 = eq(_T_633, UInt<5>("h014")) @[el2_lib.scala 339:41] + _T_594[19] <= _T_634 @[el2_lib.scala 339:23] + node _T_635 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_636 = eq(_T_635, UInt<5>("h015")) @[el2_lib.scala 339:41] + _T_594[20] <= _T_636 @[el2_lib.scala 339:23] + node _T_637 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_638 = eq(_T_637, UInt<5>("h016")) @[el2_lib.scala 339:41] + _T_594[21] <= _T_638 @[el2_lib.scala 339:23] + node _T_639 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_640 = eq(_T_639, UInt<5>("h017")) @[el2_lib.scala 339:41] + _T_594[22] <= _T_640 @[el2_lib.scala 339:23] + node _T_641 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_642 = eq(_T_641, UInt<5>("h018")) @[el2_lib.scala 339:41] + _T_594[23] <= _T_642 @[el2_lib.scala 339:23] + node _T_643 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_644 = eq(_T_643, UInt<5>("h019")) @[el2_lib.scala 339:41] + _T_594[24] <= _T_644 @[el2_lib.scala 339:23] + node _T_645 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_646 = eq(_T_645, UInt<5>("h01a")) @[el2_lib.scala 339:41] + _T_594[25] <= _T_646 @[el2_lib.scala 339:23] + node _T_647 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_648 = eq(_T_647, UInt<5>("h01b")) @[el2_lib.scala 339:41] + _T_594[26] <= _T_648 @[el2_lib.scala 339:23] + node _T_649 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_650 = eq(_T_649, UInt<5>("h01c")) @[el2_lib.scala 339:41] + _T_594[27] <= _T_650 @[el2_lib.scala 339:23] + node _T_651 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_652 = eq(_T_651, UInt<5>("h01d")) @[el2_lib.scala 339:41] + _T_594[28] <= _T_652 @[el2_lib.scala 339:23] + node _T_653 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_654 = eq(_T_653, UInt<5>("h01e")) @[el2_lib.scala 339:41] + _T_594[29] <= _T_654 @[el2_lib.scala 339:23] + node _T_655 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_656 = eq(_T_655, UInt<5>("h01f")) @[el2_lib.scala 339:41] + _T_594[30] <= _T_656 @[el2_lib.scala 339:23] + node _T_657 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_658 = eq(_T_657, UInt<6>("h020")) @[el2_lib.scala 339:41] + _T_594[31] <= _T_658 @[el2_lib.scala 339:23] + node _T_659 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_660 = eq(_T_659, UInt<6>("h021")) @[el2_lib.scala 339:41] + _T_594[32] <= _T_660 @[el2_lib.scala 339:23] + node _T_661 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_662 = eq(_T_661, UInt<6>("h022")) @[el2_lib.scala 339:41] + _T_594[33] <= _T_662 @[el2_lib.scala 339:23] + node _T_663 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_664 = eq(_T_663, UInt<6>("h023")) @[el2_lib.scala 339:41] + _T_594[34] <= _T_664 @[el2_lib.scala 339:23] + node _T_665 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_666 = eq(_T_665, UInt<6>("h024")) @[el2_lib.scala 339:41] + _T_594[35] <= _T_666 @[el2_lib.scala 339:23] + node _T_667 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_668 = eq(_T_667, UInt<6>("h025")) @[el2_lib.scala 339:41] + _T_594[36] <= _T_668 @[el2_lib.scala 339:23] + node _T_669 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_670 = eq(_T_669, UInt<6>("h026")) @[el2_lib.scala 339:41] + _T_594[37] <= _T_670 @[el2_lib.scala 339:23] + node _T_671 = bits(_T_586, 5, 0) @[el2_lib.scala 339:35] + node _T_672 = eq(_T_671, UInt<6>("h027")) @[el2_lib.scala 339:41] + _T_594[38] <= _T_672 @[el2_lib.scala 339:23] + node _T_673 = bits(dccm_data_ecc_lo_any, 6, 6) @[el2_lib.scala 341:37] + node _T_674 = bits(dccm_rdata_lo_any, 31, 26) @[el2_lib.scala 341:45] + node _T_675 = bits(dccm_data_ecc_lo_any, 5, 5) @[el2_lib.scala 341:60] + node _T_676 = bits(dccm_rdata_lo_any, 25, 11) @[el2_lib.scala 341:68] + node _T_677 = bits(dccm_data_ecc_lo_any, 4, 4) @[el2_lib.scala 341:83] + node _T_678 = bits(dccm_rdata_lo_any, 10, 4) @[el2_lib.scala 341:91] + node _T_679 = bits(dccm_data_ecc_lo_any, 3, 3) @[el2_lib.scala 341:105] + node _T_680 = bits(dccm_rdata_lo_any, 3, 1) @[el2_lib.scala 341:113] + node _T_681 = bits(dccm_data_ecc_lo_any, 2, 2) @[el2_lib.scala 341:126] + node _T_682 = bits(dccm_rdata_lo_any, 0, 0) @[el2_lib.scala 341:134] + node _T_683 = bits(dccm_data_ecc_lo_any, 1, 0) @[el2_lib.scala 341:145] + node _T_684 = cat(_T_682, _T_683) @[Cat.scala 29:58] + node _T_685 = cat(_T_679, _T_680) @[Cat.scala 29:58] + node _T_686 = cat(_T_685, _T_681) @[Cat.scala 29:58] + node _T_687 = cat(_T_686, _T_684) @[Cat.scala 29:58] + node _T_688 = cat(_T_676, _T_677) @[Cat.scala 29:58] + node _T_689 = cat(_T_688, _T_678) @[Cat.scala 29:58] + node _T_690 = cat(_T_673, _T_674) @[Cat.scala 29:58] + node _T_691 = cat(_T_690, _T_675) @[Cat.scala 29:58] + node _T_692 = cat(_T_691, _T_689) @[Cat.scala 29:58] + node _T_693 = cat(_T_692, _T_687) @[Cat.scala 29:58] + node _T_694 = bits(single_ecc_error_lo_any, 0, 0) @[el2_lib.scala 342:49] + node _T_695 = cat(_T_594[1], _T_594[0]) @[el2_lib.scala 342:69] + node _T_696 = cat(_T_594[3], _T_594[2]) @[el2_lib.scala 342:69] + node _T_697 = cat(_T_696, _T_695) @[el2_lib.scala 342:69] + node _T_698 = cat(_T_594[5], _T_594[4]) @[el2_lib.scala 342:69] + node _T_699 = cat(_T_594[8], _T_594[7]) @[el2_lib.scala 342:69] + node _T_700 = cat(_T_699, _T_594[6]) @[el2_lib.scala 342:69] + node _T_701 = cat(_T_700, _T_698) @[el2_lib.scala 342:69] + node _T_702 = cat(_T_701, _T_697) @[el2_lib.scala 342:69] + node _T_703 = cat(_T_594[10], _T_594[9]) @[el2_lib.scala 342:69] + node _T_704 = cat(_T_594[13], _T_594[12]) @[el2_lib.scala 342:69] + node _T_705 = cat(_T_704, _T_594[11]) @[el2_lib.scala 342:69] + node _T_706 = cat(_T_705, _T_703) @[el2_lib.scala 342:69] + node _T_707 = cat(_T_594[15], _T_594[14]) @[el2_lib.scala 342:69] + node _T_708 = cat(_T_594[18], _T_594[17]) @[el2_lib.scala 342:69] + node _T_709 = cat(_T_708, _T_594[16]) @[el2_lib.scala 342:69] + node _T_710 = cat(_T_709, _T_707) @[el2_lib.scala 342:69] + node _T_711 = cat(_T_710, _T_706) @[el2_lib.scala 342:69] + node _T_712 = cat(_T_711, _T_702) @[el2_lib.scala 342:69] + node _T_713 = cat(_T_594[20], _T_594[19]) @[el2_lib.scala 342:69] + node _T_714 = cat(_T_594[23], _T_594[22]) @[el2_lib.scala 342:69] + node _T_715 = cat(_T_714, _T_594[21]) @[el2_lib.scala 342:69] + node _T_716 = cat(_T_715, _T_713) @[el2_lib.scala 342:69] + node _T_717 = cat(_T_594[25], _T_594[24]) @[el2_lib.scala 342:69] + node _T_718 = cat(_T_594[28], _T_594[27]) @[el2_lib.scala 342:69] + node _T_719 = cat(_T_718, _T_594[26]) @[el2_lib.scala 342:69] + node _T_720 = cat(_T_719, _T_717) @[el2_lib.scala 342:69] + node _T_721 = cat(_T_720, _T_716) @[el2_lib.scala 342:69] + node _T_722 = cat(_T_594[30], _T_594[29]) @[el2_lib.scala 342:69] + node _T_723 = cat(_T_594[33], _T_594[32]) @[el2_lib.scala 342:69] + node _T_724 = cat(_T_723, _T_594[31]) @[el2_lib.scala 342:69] + node _T_725 = cat(_T_724, _T_722) @[el2_lib.scala 342:69] + node _T_726 = cat(_T_594[35], _T_594[34]) @[el2_lib.scala 342:69] + node _T_727 = cat(_T_594[38], _T_594[37]) @[el2_lib.scala 342:69] + node _T_728 = cat(_T_727, _T_594[36]) @[el2_lib.scala 342:69] + node _T_729 = cat(_T_728, _T_726) @[el2_lib.scala 342:69] + node _T_730 = cat(_T_729, _T_725) @[el2_lib.scala 342:69] + node _T_731 = cat(_T_730, _T_721) @[el2_lib.scala 342:69] + node _T_732 = cat(_T_731, _T_712) @[el2_lib.scala 342:69] + node _T_733 = xor(_T_732, _T_693) @[el2_lib.scala 342:76] + node _T_734 = mux(_T_694, _T_733, _T_693) @[el2_lib.scala 342:31] + node _T_735 = bits(_T_734, 37, 32) @[el2_lib.scala 344:37] + node _T_736 = bits(_T_734, 30, 16) @[el2_lib.scala 344:61] + node _T_737 = bits(_T_734, 14, 8) @[el2_lib.scala 344:86] + node _T_738 = bits(_T_734, 6, 4) @[el2_lib.scala 344:110] + node _T_739 = bits(_T_734, 2, 2) @[el2_lib.scala 344:133] + node _T_740 = cat(_T_738, _T_739) @[Cat.scala 29:58] + node _T_741 = cat(_T_735, _T_736) @[Cat.scala 29:58] + node _T_742 = cat(_T_741, _T_737) @[Cat.scala 29:58] + node sec_data_lo_any = cat(_T_742, _T_740) @[Cat.scala 29:58] + node _T_743 = bits(_T_734, 38, 38) @[el2_lib.scala 345:39] + node _T_744 = bits(_T_586, 6, 0) @[el2_lib.scala 345:56] + node _T_745 = eq(_T_744, UInt<7>("h040")) @[el2_lib.scala 345:62] + node _T_746 = xor(_T_743, _T_745) @[el2_lib.scala 345:44] + node _T_747 = bits(_T_734, 31, 31) @[el2_lib.scala 345:102] + node _T_748 = bits(_T_734, 15, 15) @[el2_lib.scala 345:124] + node _T_749 = bits(_T_734, 7, 7) @[el2_lib.scala 345:146] + node _T_750 = bits(_T_734, 3, 3) @[el2_lib.scala 345:167] + node _T_751 = bits(_T_734, 1, 0) @[el2_lib.scala 345:188] + node _T_752 = cat(_T_749, _T_750) @[Cat.scala 29:58] + node _T_753 = cat(_T_752, _T_751) @[Cat.scala 29:58] + node _T_754 = cat(_T_746, _T_747) @[Cat.scala 29:58] + node _T_755 = cat(_T_754, _T_748) @[Cat.scala 29:58] + node ecc_out_lo_nc = cat(_T_755, _T_753) @[Cat.scala 29:58] + node _T_756 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] + node _T_757 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] + node _T_758 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_759 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] + node _T_760 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_761 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_762 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_763 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] + node _T_764 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_765 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_766 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_767 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_768 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_769 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_770 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_771 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] + node _T_772 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_773 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_774 = xor(_T_756, _T_757) @[el2_lib.scala 259:74] + node _T_775 = xor(_T_774, _T_758) @[el2_lib.scala 259:74] + node _T_776 = xor(_T_775, _T_759) @[el2_lib.scala 259:74] + node _T_777 = xor(_T_776, _T_760) @[el2_lib.scala 259:74] + node _T_778 = xor(_T_777, _T_761) @[el2_lib.scala 259:74] + node _T_779 = xor(_T_778, _T_762) @[el2_lib.scala 259:74] + node _T_780 = xor(_T_779, _T_763) @[el2_lib.scala 259:74] + node _T_781 = xor(_T_780, _T_764) @[el2_lib.scala 259:74] + node _T_782 = xor(_T_781, _T_765) @[el2_lib.scala 259:74] + node _T_783 = xor(_T_782, _T_766) @[el2_lib.scala 259:74] + node _T_784 = xor(_T_783, _T_767) @[el2_lib.scala 259:74] + node _T_785 = xor(_T_784, _T_768) @[el2_lib.scala 259:74] + node _T_786 = xor(_T_785, _T_769) @[el2_lib.scala 259:74] + node _T_787 = xor(_T_786, _T_770) @[el2_lib.scala 259:74] + node _T_788 = xor(_T_787, _T_771) @[el2_lib.scala 259:74] + node _T_789 = xor(_T_788, _T_772) @[el2_lib.scala 259:74] + node _T_790 = xor(_T_789, _T_773) @[el2_lib.scala 259:74] + node _T_791 = bits(dccm_wdata_lo_any, 0, 0) @[el2_lib.scala 259:58] + node _T_792 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] + node _T_793 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_794 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] + node _T_795 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_796 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_797 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_798 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] + node _T_799 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_800 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_801 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_802 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_803 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_804 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_805 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_806 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] + node _T_807 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_808 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_809 = xor(_T_791, _T_792) @[el2_lib.scala 259:74] + node _T_810 = xor(_T_809, _T_793) @[el2_lib.scala 259:74] + node _T_811 = xor(_T_810, _T_794) @[el2_lib.scala 259:74] + node _T_812 = xor(_T_811, _T_795) @[el2_lib.scala 259:74] + node _T_813 = xor(_T_812, _T_796) @[el2_lib.scala 259:74] + node _T_814 = xor(_T_813, _T_797) @[el2_lib.scala 259:74] + node _T_815 = xor(_T_814, _T_798) @[el2_lib.scala 259:74] + node _T_816 = xor(_T_815, _T_799) @[el2_lib.scala 259:74] + node _T_817 = xor(_T_816, _T_800) @[el2_lib.scala 259:74] + node _T_818 = xor(_T_817, _T_801) @[el2_lib.scala 259:74] + node _T_819 = xor(_T_818, _T_802) @[el2_lib.scala 259:74] + node _T_820 = xor(_T_819, _T_803) @[el2_lib.scala 259:74] + node _T_821 = xor(_T_820, _T_804) @[el2_lib.scala 259:74] + node _T_822 = xor(_T_821, _T_805) @[el2_lib.scala 259:74] + node _T_823 = xor(_T_822, _T_806) @[el2_lib.scala 259:74] + node _T_824 = xor(_T_823, _T_807) @[el2_lib.scala 259:74] + node _T_825 = xor(_T_824, _T_808) @[el2_lib.scala 259:74] + node _T_826 = bits(dccm_wdata_lo_any, 1, 1) @[el2_lib.scala 259:58] + node _T_827 = bits(dccm_wdata_lo_any, 2, 2) @[el2_lib.scala 259:58] + node _T_828 = bits(dccm_wdata_lo_any, 3, 3) @[el2_lib.scala 259:58] + node _T_829 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] + node _T_830 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_831 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_832 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_833 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] + node _T_834 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_835 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_836 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_837 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_838 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_839 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_840 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_841 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] + node _T_842 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_843 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_844 = xor(_T_826, _T_827) @[el2_lib.scala 259:74] + node _T_845 = xor(_T_844, _T_828) @[el2_lib.scala 259:74] + node _T_846 = xor(_T_845, _T_829) @[el2_lib.scala 259:74] + node _T_847 = xor(_T_846, _T_830) @[el2_lib.scala 259:74] + node _T_848 = xor(_T_847, _T_831) @[el2_lib.scala 259:74] + node _T_849 = xor(_T_848, _T_832) @[el2_lib.scala 259:74] + node _T_850 = xor(_T_849, _T_833) @[el2_lib.scala 259:74] + node _T_851 = xor(_T_850, _T_834) @[el2_lib.scala 259:74] + node _T_852 = xor(_T_851, _T_835) @[el2_lib.scala 259:74] + node _T_853 = xor(_T_852, _T_836) @[el2_lib.scala 259:74] + node _T_854 = xor(_T_853, _T_837) @[el2_lib.scala 259:74] + node _T_855 = xor(_T_854, _T_838) @[el2_lib.scala 259:74] + node _T_856 = xor(_T_855, _T_839) @[el2_lib.scala 259:74] + node _T_857 = xor(_T_856, _T_840) @[el2_lib.scala 259:74] + node _T_858 = xor(_T_857, _T_841) @[el2_lib.scala 259:74] + node _T_859 = xor(_T_858, _T_842) @[el2_lib.scala 259:74] + node _T_860 = xor(_T_859, _T_843) @[el2_lib.scala 259:74] + node _T_861 = bits(dccm_wdata_lo_any, 4, 4) @[el2_lib.scala 259:58] + node _T_862 = bits(dccm_wdata_lo_any, 5, 5) @[el2_lib.scala 259:58] + node _T_863 = bits(dccm_wdata_lo_any, 6, 6) @[el2_lib.scala 259:58] + node _T_864 = bits(dccm_wdata_lo_any, 7, 7) @[el2_lib.scala 259:58] + node _T_865 = bits(dccm_wdata_lo_any, 8, 8) @[el2_lib.scala 259:58] + node _T_866 = bits(dccm_wdata_lo_any, 9, 9) @[el2_lib.scala 259:58] + node _T_867 = bits(dccm_wdata_lo_any, 10, 10) @[el2_lib.scala 259:58] + node _T_868 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] + node _T_869 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_870 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_871 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_872 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_873 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_874 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_875 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_876 = xor(_T_861, _T_862) @[el2_lib.scala 259:74] + node _T_877 = xor(_T_876, _T_863) @[el2_lib.scala 259:74] + node _T_878 = xor(_T_877, _T_864) @[el2_lib.scala 259:74] + node _T_879 = xor(_T_878, _T_865) @[el2_lib.scala 259:74] + node _T_880 = xor(_T_879, _T_866) @[el2_lib.scala 259:74] + node _T_881 = xor(_T_880, _T_867) @[el2_lib.scala 259:74] + node _T_882 = xor(_T_881, _T_868) @[el2_lib.scala 259:74] + node _T_883 = xor(_T_882, _T_869) @[el2_lib.scala 259:74] + node _T_884 = xor(_T_883, _T_870) @[el2_lib.scala 259:74] + node _T_885 = xor(_T_884, _T_871) @[el2_lib.scala 259:74] + node _T_886 = xor(_T_885, _T_872) @[el2_lib.scala 259:74] + node _T_887 = xor(_T_886, _T_873) @[el2_lib.scala 259:74] + node _T_888 = xor(_T_887, _T_874) @[el2_lib.scala 259:74] + node _T_889 = xor(_T_888, _T_875) @[el2_lib.scala 259:74] + node _T_890 = bits(dccm_wdata_lo_any, 11, 11) @[el2_lib.scala 259:58] + node _T_891 = bits(dccm_wdata_lo_any, 12, 12) @[el2_lib.scala 259:58] + node _T_892 = bits(dccm_wdata_lo_any, 13, 13) @[el2_lib.scala 259:58] + node _T_893 = bits(dccm_wdata_lo_any, 14, 14) @[el2_lib.scala 259:58] + node _T_894 = bits(dccm_wdata_lo_any, 15, 15) @[el2_lib.scala 259:58] + node _T_895 = bits(dccm_wdata_lo_any, 16, 16) @[el2_lib.scala 259:58] + node _T_896 = bits(dccm_wdata_lo_any, 17, 17) @[el2_lib.scala 259:58] + node _T_897 = bits(dccm_wdata_lo_any, 18, 18) @[el2_lib.scala 259:58] + node _T_898 = bits(dccm_wdata_lo_any, 19, 19) @[el2_lib.scala 259:58] + node _T_899 = bits(dccm_wdata_lo_any, 20, 20) @[el2_lib.scala 259:58] + node _T_900 = bits(dccm_wdata_lo_any, 21, 21) @[el2_lib.scala 259:58] + node _T_901 = bits(dccm_wdata_lo_any, 22, 22) @[el2_lib.scala 259:58] + node _T_902 = bits(dccm_wdata_lo_any, 23, 23) @[el2_lib.scala 259:58] + node _T_903 = bits(dccm_wdata_lo_any, 24, 24) @[el2_lib.scala 259:58] + node _T_904 = bits(dccm_wdata_lo_any, 25, 25) @[el2_lib.scala 259:58] + node _T_905 = xor(_T_890, _T_891) @[el2_lib.scala 259:74] + node _T_906 = xor(_T_905, _T_892) @[el2_lib.scala 259:74] + node _T_907 = xor(_T_906, _T_893) @[el2_lib.scala 259:74] + node _T_908 = xor(_T_907, _T_894) @[el2_lib.scala 259:74] + node _T_909 = xor(_T_908, _T_895) @[el2_lib.scala 259:74] + node _T_910 = xor(_T_909, _T_896) @[el2_lib.scala 259:74] + node _T_911 = xor(_T_910, _T_897) @[el2_lib.scala 259:74] + node _T_912 = xor(_T_911, _T_898) @[el2_lib.scala 259:74] + node _T_913 = xor(_T_912, _T_899) @[el2_lib.scala 259:74] + node _T_914 = xor(_T_913, _T_900) @[el2_lib.scala 259:74] + node _T_915 = xor(_T_914, _T_901) @[el2_lib.scala 259:74] + node _T_916 = xor(_T_915, _T_902) @[el2_lib.scala 259:74] + node _T_917 = xor(_T_916, _T_903) @[el2_lib.scala 259:74] + node _T_918 = xor(_T_917, _T_904) @[el2_lib.scala 259:74] + node _T_919 = bits(dccm_wdata_lo_any, 26, 26) @[el2_lib.scala 259:58] + node _T_920 = bits(dccm_wdata_lo_any, 27, 27) @[el2_lib.scala 259:58] + node _T_921 = bits(dccm_wdata_lo_any, 28, 28) @[el2_lib.scala 259:58] + node _T_922 = bits(dccm_wdata_lo_any, 29, 29) @[el2_lib.scala 259:58] + node _T_923 = bits(dccm_wdata_lo_any, 30, 30) @[el2_lib.scala 259:58] + node _T_924 = bits(dccm_wdata_lo_any, 31, 31) @[el2_lib.scala 259:58] + node _T_925 = xor(_T_919, _T_920) @[el2_lib.scala 259:74] + node _T_926 = xor(_T_925, _T_921) @[el2_lib.scala 259:74] + node _T_927 = xor(_T_926, _T_922) @[el2_lib.scala 259:74] + node _T_928 = xor(_T_927, _T_923) @[el2_lib.scala 259:74] + node _T_929 = xor(_T_928, _T_924) @[el2_lib.scala 259:74] + node _T_930 = cat(_T_860, _T_825) @[Cat.scala 29:58] + node _T_931 = cat(_T_930, _T_790) @[Cat.scala 29:58] + node _T_932 = cat(_T_929, _T_918) @[Cat.scala 29:58] + node _T_933 = cat(_T_932, _T_889) @[Cat.scala 29:58] + node _T_934 = cat(_T_933, _T_931) @[Cat.scala 29:58] + node _T_935 = xorr(dccm_wdata_lo_any) @[el2_lib.scala 267:13] + node _T_936 = xorr(_T_934) @[el2_lib.scala 267:23] + node _T_937 = xor(_T_935, _T_936) @[el2_lib.scala 267:18] + node dccm_wdata_ecc_lo_any = cat(_T_937, _T_934) @[Cat.scala 29:58] + node _T_938 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] + node _T_939 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] + node _T_940 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_941 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] + node _T_942 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_943 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_944 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_945 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] + node _T_946 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_947 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_948 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_949 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_950 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_951 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_952 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_953 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] + node _T_954 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_955 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_956 = xor(_T_938, _T_939) @[el2_lib.scala 259:74] + node _T_957 = xor(_T_956, _T_940) @[el2_lib.scala 259:74] + node _T_958 = xor(_T_957, _T_941) @[el2_lib.scala 259:74] + node _T_959 = xor(_T_958, _T_942) @[el2_lib.scala 259:74] + node _T_960 = xor(_T_959, _T_943) @[el2_lib.scala 259:74] + node _T_961 = xor(_T_960, _T_944) @[el2_lib.scala 259:74] + node _T_962 = xor(_T_961, _T_945) @[el2_lib.scala 259:74] + node _T_963 = xor(_T_962, _T_946) @[el2_lib.scala 259:74] + node _T_964 = xor(_T_963, _T_947) @[el2_lib.scala 259:74] + node _T_965 = xor(_T_964, _T_948) @[el2_lib.scala 259:74] + node _T_966 = xor(_T_965, _T_949) @[el2_lib.scala 259:74] + node _T_967 = xor(_T_966, _T_950) @[el2_lib.scala 259:74] + node _T_968 = xor(_T_967, _T_951) @[el2_lib.scala 259:74] + node _T_969 = xor(_T_968, _T_952) @[el2_lib.scala 259:74] + node _T_970 = xor(_T_969, _T_953) @[el2_lib.scala 259:74] + node _T_971 = xor(_T_970, _T_954) @[el2_lib.scala 259:74] + node _T_972 = xor(_T_971, _T_955) @[el2_lib.scala 259:74] + node _T_973 = bits(dccm_wdata_hi_any, 0, 0) @[el2_lib.scala 259:58] + node _T_974 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] + node _T_975 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_976 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] + node _T_977 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_978 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_979 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_980 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] + node _T_981 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_982 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_983 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_984 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_985 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_986 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_987 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_988 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] + node _T_989 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_990 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_991 = xor(_T_973, _T_974) @[el2_lib.scala 259:74] + node _T_992 = xor(_T_991, _T_975) @[el2_lib.scala 259:74] + node _T_993 = xor(_T_992, _T_976) @[el2_lib.scala 259:74] + node _T_994 = xor(_T_993, _T_977) @[el2_lib.scala 259:74] + node _T_995 = xor(_T_994, _T_978) @[el2_lib.scala 259:74] + node _T_996 = xor(_T_995, _T_979) @[el2_lib.scala 259:74] + node _T_997 = xor(_T_996, _T_980) @[el2_lib.scala 259:74] + node _T_998 = xor(_T_997, _T_981) @[el2_lib.scala 259:74] + node _T_999 = xor(_T_998, _T_982) @[el2_lib.scala 259:74] + node _T_1000 = xor(_T_999, _T_983) @[el2_lib.scala 259:74] + node _T_1001 = xor(_T_1000, _T_984) @[el2_lib.scala 259:74] + node _T_1002 = xor(_T_1001, _T_985) @[el2_lib.scala 259:74] + node _T_1003 = xor(_T_1002, _T_986) @[el2_lib.scala 259:74] + node _T_1004 = xor(_T_1003, _T_987) @[el2_lib.scala 259:74] + node _T_1005 = xor(_T_1004, _T_988) @[el2_lib.scala 259:74] + node _T_1006 = xor(_T_1005, _T_989) @[el2_lib.scala 259:74] + node _T_1007 = xor(_T_1006, _T_990) @[el2_lib.scala 259:74] + node _T_1008 = bits(dccm_wdata_hi_any, 1, 1) @[el2_lib.scala 259:58] + node _T_1009 = bits(dccm_wdata_hi_any, 2, 2) @[el2_lib.scala 259:58] + node _T_1010 = bits(dccm_wdata_hi_any, 3, 3) @[el2_lib.scala 259:58] + node _T_1011 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] + node _T_1012 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_1013 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_1014 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_1015 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] + node _T_1016 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_1017 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_1018 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_1019 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1020 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1021 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1022 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1023 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] + node _T_1024 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_1025 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_1026 = xor(_T_1008, _T_1009) @[el2_lib.scala 259:74] + node _T_1027 = xor(_T_1026, _T_1010) @[el2_lib.scala 259:74] + node _T_1028 = xor(_T_1027, _T_1011) @[el2_lib.scala 259:74] + node _T_1029 = xor(_T_1028, _T_1012) @[el2_lib.scala 259:74] + node _T_1030 = xor(_T_1029, _T_1013) @[el2_lib.scala 259:74] + node _T_1031 = xor(_T_1030, _T_1014) @[el2_lib.scala 259:74] + node _T_1032 = xor(_T_1031, _T_1015) @[el2_lib.scala 259:74] + node _T_1033 = xor(_T_1032, _T_1016) @[el2_lib.scala 259:74] + node _T_1034 = xor(_T_1033, _T_1017) @[el2_lib.scala 259:74] + node _T_1035 = xor(_T_1034, _T_1018) @[el2_lib.scala 259:74] + node _T_1036 = xor(_T_1035, _T_1019) @[el2_lib.scala 259:74] + node _T_1037 = xor(_T_1036, _T_1020) @[el2_lib.scala 259:74] + node _T_1038 = xor(_T_1037, _T_1021) @[el2_lib.scala 259:74] + node _T_1039 = xor(_T_1038, _T_1022) @[el2_lib.scala 259:74] + node _T_1040 = xor(_T_1039, _T_1023) @[el2_lib.scala 259:74] + node _T_1041 = xor(_T_1040, _T_1024) @[el2_lib.scala 259:74] + node _T_1042 = xor(_T_1041, _T_1025) @[el2_lib.scala 259:74] + node _T_1043 = bits(dccm_wdata_hi_any, 4, 4) @[el2_lib.scala 259:58] + node _T_1044 = bits(dccm_wdata_hi_any, 5, 5) @[el2_lib.scala 259:58] + node _T_1045 = bits(dccm_wdata_hi_any, 6, 6) @[el2_lib.scala 259:58] + node _T_1046 = bits(dccm_wdata_hi_any, 7, 7) @[el2_lib.scala 259:58] + node _T_1047 = bits(dccm_wdata_hi_any, 8, 8) @[el2_lib.scala 259:58] + node _T_1048 = bits(dccm_wdata_hi_any, 9, 9) @[el2_lib.scala 259:58] + node _T_1049 = bits(dccm_wdata_hi_any, 10, 10) @[el2_lib.scala 259:58] + node _T_1050 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] + node _T_1051 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_1052 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_1053 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_1054 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1055 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1056 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1057 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1058 = xor(_T_1043, _T_1044) @[el2_lib.scala 259:74] + node _T_1059 = xor(_T_1058, _T_1045) @[el2_lib.scala 259:74] + node _T_1060 = xor(_T_1059, _T_1046) @[el2_lib.scala 259:74] + node _T_1061 = xor(_T_1060, _T_1047) @[el2_lib.scala 259:74] + node _T_1062 = xor(_T_1061, _T_1048) @[el2_lib.scala 259:74] + node _T_1063 = xor(_T_1062, _T_1049) @[el2_lib.scala 259:74] + node _T_1064 = xor(_T_1063, _T_1050) @[el2_lib.scala 259:74] + node _T_1065 = xor(_T_1064, _T_1051) @[el2_lib.scala 259:74] + node _T_1066 = xor(_T_1065, _T_1052) @[el2_lib.scala 259:74] + node _T_1067 = xor(_T_1066, _T_1053) @[el2_lib.scala 259:74] + node _T_1068 = xor(_T_1067, _T_1054) @[el2_lib.scala 259:74] + node _T_1069 = xor(_T_1068, _T_1055) @[el2_lib.scala 259:74] + node _T_1070 = xor(_T_1069, _T_1056) @[el2_lib.scala 259:74] + node _T_1071 = xor(_T_1070, _T_1057) @[el2_lib.scala 259:74] + node _T_1072 = bits(dccm_wdata_hi_any, 11, 11) @[el2_lib.scala 259:58] + node _T_1073 = bits(dccm_wdata_hi_any, 12, 12) @[el2_lib.scala 259:58] + node _T_1074 = bits(dccm_wdata_hi_any, 13, 13) @[el2_lib.scala 259:58] + node _T_1075 = bits(dccm_wdata_hi_any, 14, 14) @[el2_lib.scala 259:58] + node _T_1076 = bits(dccm_wdata_hi_any, 15, 15) @[el2_lib.scala 259:58] + node _T_1077 = bits(dccm_wdata_hi_any, 16, 16) @[el2_lib.scala 259:58] + node _T_1078 = bits(dccm_wdata_hi_any, 17, 17) @[el2_lib.scala 259:58] + node _T_1079 = bits(dccm_wdata_hi_any, 18, 18) @[el2_lib.scala 259:58] + node _T_1080 = bits(dccm_wdata_hi_any, 19, 19) @[el2_lib.scala 259:58] + node _T_1081 = bits(dccm_wdata_hi_any, 20, 20) @[el2_lib.scala 259:58] + node _T_1082 = bits(dccm_wdata_hi_any, 21, 21) @[el2_lib.scala 259:58] + node _T_1083 = bits(dccm_wdata_hi_any, 22, 22) @[el2_lib.scala 259:58] + node _T_1084 = bits(dccm_wdata_hi_any, 23, 23) @[el2_lib.scala 259:58] + node _T_1085 = bits(dccm_wdata_hi_any, 24, 24) @[el2_lib.scala 259:58] + node _T_1086 = bits(dccm_wdata_hi_any, 25, 25) @[el2_lib.scala 259:58] + node _T_1087 = xor(_T_1072, _T_1073) @[el2_lib.scala 259:74] + node _T_1088 = xor(_T_1087, _T_1074) @[el2_lib.scala 259:74] + node _T_1089 = xor(_T_1088, _T_1075) @[el2_lib.scala 259:74] + node _T_1090 = xor(_T_1089, _T_1076) @[el2_lib.scala 259:74] + node _T_1091 = xor(_T_1090, _T_1077) @[el2_lib.scala 259:74] + node _T_1092 = xor(_T_1091, _T_1078) @[el2_lib.scala 259:74] + node _T_1093 = xor(_T_1092, _T_1079) @[el2_lib.scala 259:74] + node _T_1094 = xor(_T_1093, _T_1080) @[el2_lib.scala 259:74] + node _T_1095 = xor(_T_1094, _T_1081) @[el2_lib.scala 259:74] + node _T_1096 = xor(_T_1095, _T_1082) @[el2_lib.scala 259:74] + node _T_1097 = xor(_T_1096, _T_1083) @[el2_lib.scala 259:74] + node _T_1098 = xor(_T_1097, _T_1084) @[el2_lib.scala 259:74] + node _T_1099 = xor(_T_1098, _T_1085) @[el2_lib.scala 259:74] + node _T_1100 = xor(_T_1099, _T_1086) @[el2_lib.scala 259:74] + node _T_1101 = bits(dccm_wdata_hi_any, 26, 26) @[el2_lib.scala 259:58] + node _T_1102 = bits(dccm_wdata_hi_any, 27, 27) @[el2_lib.scala 259:58] + node _T_1103 = bits(dccm_wdata_hi_any, 28, 28) @[el2_lib.scala 259:58] + node _T_1104 = bits(dccm_wdata_hi_any, 29, 29) @[el2_lib.scala 259:58] + node _T_1105 = bits(dccm_wdata_hi_any, 30, 30) @[el2_lib.scala 259:58] + node _T_1106 = bits(dccm_wdata_hi_any, 31, 31) @[el2_lib.scala 259:58] + node _T_1107 = xor(_T_1101, _T_1102) @[el2_lib.scala 259:74] + node _T_1108 = xor(_T_1107, _T_1103) @[el2_lib.scala 259:74] + node _T_1109 = xor(_T_1108, _T_1104) @[el2_lib.scala 259:74] + node _T_1110 = xor(_T_1109, _T_1105) @[el2_lib.scala 259:74] + node _T_1111 = xor(_T_1110, _T_1106) @[el2_lib.scala 259:74] + node _T_1112 = cat(_T_1042, _T_1007) @[Cat.scala 29:58] + node _T_1113 = cat(_T_1112, _T_972) @[Cat.scala 29:58] + node _T_1114 = cat(_T_1111, _T_1100) @[Cat.scala 29:58] + node _T_1115 = cat(_T_1114, _T_1071) @[Cat.scala 29:58] + node _T_1116 = cat(_T_1115, _T_1113) @[Cat.scala 29:58] + node _T_1117 = xorr(dccm_wdata_hi_any) @[el2_lib.scala 267:13] + node _T_1118 = xorr(_T_1116) @[el2_lib.scala 267:23] + node _T_1119 = xor(_T_1117, _T_1118) @[el2_lib.scala 267:18] + node dccm_wdata_ecc_hi_any = cat(_T_1119, _T_1116) @[Cat.scala 29:58] + when UInt<1>("h00") : @[el2_lsu_ecc.scala 103:30] + node _T_1120 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:33] + node _T_1121 = bits(io.end_addr_r, 2, 2) @[el2_lsu_ecc.scala 104:54] + node _T_1122 = neq(_T_1120, _T_1121) @[el2_lsu_ecc.scala 104:37] + ldst_dual_r <= _T_1122 @[el2_lsu_ecc.scala 104:17] + node _T_1123 = or(io.lsu_pkt_r.load, io.lsu_pkt_r.store) @[el2_lsu_ecc.scala 105:58] + node _T_1124 = and(io.lsu_pkt_r.valid, _T_1123) @[el2_lsu_ecc.scala 105:37] + node _T_1125 = and(_T_1124, io.addr_in_dccm_r) @[el2_lsu_ecc.scala 105:80] + node _T_1126 = and(_T_1125, io.lsu_dccm_rden_r) @[el2_lsu_ecc.scala 105:100] + is_ldst_r <= _T_1126 @[el2_lsu_ecc.scala 105:15] + node _T_1127 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 106:33] + node _T_1128 = and(is_ldst_r, _T_1127) @[el2_lsu_ecc.scala 106:31] + is_ldst_lo_r <= _T_1128 @[el2_lsu_ecc.scala 106:18] + node _T_1129 = or(ldst_dual_r, io.lsu_pkt_r.dma) @[el2_lsu_ecc.scala 107:46] + node _T_1130 = and(is_ldst_r, _T_1129) @[el2_lsu_ecc.scala 107:31] + node _T_1131 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 107:68] + node _T_1132 = and(_T_1130, _T_1131) @[el2_lsu_ecc.scala 107:66] + is_ldst_hi_r <= _T_1132 @[el2_lsu_ecc.scala 107:18] + is_ldst_hi_any <= is_ldst_hi_r @[el2_lsu_ecc.scala 108:21] + dccm_rdata_hi_any <= io.dccm_rdata_hi_r @[el2_lsu_ecc.scala 109:24] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_r @[el2_lsu_ecc.scala 110:26] + is_ldst_lo_any <= is_ldst_lo_r @[el2_lsu_ecc.scala 111:20] + dccm_rdata_lo_any <= io.dccm_rdata_lo_r @[el2_lsu_ecc.scala 112:25] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_r @[el2_lsu_ecc.scala 113:26] + io.sec_data_hi_r <= sec_data_hi_any @[el2_lsu_ecc.scala 114:22] + io.single_ecc_error_hi_r <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 115:31] + double_ecc_error_hi_r <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 116:28] + io.sec_data_lo_r <= sec_data_lo_any @[el2_lsu_ecc.scala 117:25] + io.single_ecc_error_lo_r <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 118:31] + double_ecc_error_lo_r <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 119:28] + node _T_1133 = or(io.single_ecc_error_hi_r, io.single_ecc_error_lo_r) @[el2_lsu_ecc.scala 120:59] + io.lsu_single_ecc_error_r <= _T_1133 @[el2_lsu_ecc.scala 120:31] + node _T_1134 = or(double_ecc_error_hi_r, double_ecc_error_lo_r) @[el2_lsu_ecc.scala 121:56] + io.lsu_double_ecc_error_r <= _T_1134 @[el2_lsu_ecc.scala 121:31] + skip @[el2_lsu_ecc.scala 103:30] + else : @[el2_lsu_ecc.scala 123:16] + node _T_1135 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:35] + node _T_1136 = bits(io.end_addr_m, 2, 2) @[el2_lsu_ecc.scala 124:56] + node _T_1137 = neq(_T_1135, _T_1136) @[el2_lsu_ecc.scala 124:39] + ldst_dual_m <= _T_1137 @[el2_lsu_ecc.scala 124:19] + node _T_1138 = or(io.lsu_pkt_m.load, io.lsu_pkt_m.store) @[el2_lsu_ecc.scala 125:60] + node _T_1139 = and(io.lsu_pkt_m.valid, _T_1138) @[el2_lsu_ecc.scala 125:39] + node _T_1140 = and(_T_1139, io.addr_in_dccm_m) @[el2_lsu_ecc.scala 125:82] + node _T_1141 = and(_T_1140, io.lsu_dccm_rden_m) @[el2_lsu_ecc.scala 125:102] + is_ldst_m <= _T_1141 @[el2_lsu_ecc.scala 125:17] + node _T_1142 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 126:35] + node _T_1143 = and(is_ldst_m, _T_1142) @[el2_lsu_ecc.scala 126:33] + is_ldst_lo_m <= _T_1143 @[el2_lsu_ecc.scala 126:20] + node _T_1144 = or(ldst_dual_m, io.lsu_pkt_m.dma) @[el2_lsu_ecc.scala 127:48] + node _T_1145 = and(is_ldst_m, _T_1144) @[el2_lsu_ecc.scala 127:33] + node _T_1146 = eq(io.dec_tlu_core_ecc_disable, UInt<1>("h00")) @[el2_lsu_ecc.scala 127:70] + node _T_1147 = and(_T_1145, _T_1146) @[el2_lsu_ecc.scala 127:68] + is_ldst_hi_m <= _T_1147 @[el2_lsu_ecc.scala 127:20] + is_ldst_hi_any <= is_ldst_hi_m @[el2_lsu_ecc.scala 128:23] + dccm_rdata_hi_any <= io.dccm_rdata_hi_m @[el2_lsu_ecc.scala 129:26] + dccm_data_ecc_hi_any <= io.dccm_data_ecc_hi_m @[el2_lsu_ecc.scala 130:28] + is_ldst_lo_any <= is_ldst_lo_m @[el2_lsu_ecc.scala 131:22] + dccm_rdata_lo_any <= io.dccm_rdata_lo_m @[el2_lsu_ecc.scala 132:27] + dccm_data_ecc_lo_any <= io.dccm_data_ecc_lo_m @[el2_lsu_ecc.scala 133:28] + io.sec_data_hi_m <= sec_data_hi_any @[el2_lsu_ecc.scala 134:27] + double_ecc_error_hi_m <= double_ecc_error_hi_any @[el2_lsu_ecc.scala 135:30] + io.sec_data_lo_m <= sec_data_lo_any @[el2_lsu_ecc.scala 136:27] + double_ecc_error_lo_m <= double_ecc_error_lo_any @[el2_lsu_ecc.scala 137:30] + node _T_1148 = or(single_ecc_error_hi_any, single_ecc_error_lo_any) @[el2_lsu_ecc.scala 138:60] + io.lsu_single_ecc_error_m <= _T_1148 @[el2_lsu_ecc.scala 138:33] + node _T_1149 = or(double_ecc_error_hi_m, double_ecc_error_lo_m) @[el2_lsu_ecc.scala 139:58] + io.lsu_double_ecc_error_m <= _T_1149 @[el2_lsu_ecc.scala 139:33] + reg _T_1150 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 141:72] + _T_1150 <= io.lsu_single_ecc_error_m @[el2_lsu_ecc.scala 141:72] + io.lsu_single_ecc_error_r <= _T_1150 @[el2_lsu_ecc.scala 141:62] + reg _T_1151 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 142:72] + _T_1151 <= io.lsu_double_ecc_error_m @[el2_lsu_ecc.scala 142:72] + io.lsu_double_ecc_error_r <= _T_1151 @[el2_lsu_ecc.scala 142:62] + reg _T_1152 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 143:72] + _T_1152 <= single_ecc_error_lo_any @[el2_lsu_ecc.scala 143:72] + io.single_ecc_error_lo_r <= _T_1152 @[el2_lsu_ecc.scala 143:62] + reg _T_1153 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 144:72] + _T_1153 <= single_ecc_error_hi_any @[el2_lsu_ecc.scala 144:72] + io.single_ecc_error_hi_r <= _T_1153 @[el2_lsu_ecc.scala 144:62] + reg _T_1154 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 145:72] + _T_1154 <= io.sec_data_hi_m @[el2_lsu_ecc.scala 145:72] + io.sec_data_hi_r <= _T_1154 @[el2_lsu_ecc.scala 145:62] + reg _T_1155 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_ecc.scala 146:72] + _T_1155 <= io.sec_data_lo_m @[el2_lsu_ecc.scala 146:72] + io.sec_data_lo_r <= _T_1155 @[el2_lsu_ecc.scala 146:62] + skip @[el2_lsu_ecc.scala 123:16] + node _T_1156 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 149:56] + node _T_1157 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 149:104] + node _T_1158 = mux(_T_1157, io.dma_dccm_wdata_lo, io.stbuf_data_any) @[el2_lsu_ecc.scala 149:87] + node _T_1159 = mux(_T_1156, io.sec_data_lo_r_ff, _T_1158) @[el2_lsu_ecc.scala 149:27] + dccm_wdata_lo_any <= _T_1159 @[el2_lsu_ecc.scala 149:21] + node _T_1160 = bits(io.ld_single_ecc_error_r_ff, 0, 0) @[el2_lsu_ecc.scala 150:56] + node _T_1161 = bits(io.dma_dccm_wen, 0, 0) @[el2_lsu_ecc.scala 150:104] + node _T_1162 = mux(_T_1161, io.dma_dccm_wdata_hi, io.stbuf_data_any) @[el2_lsu_ecc.scala 150:87] + node _T_1163 = mux(_T_1160, io.sec_data_hi_r_ff, _T_1162) @[el2_lsu_ecc.scala 150:27] + dccm_wdata_hi_any <= _T_1163 @[el2_lsu_ecc.scala 150:21] + io.sec_data_ecc_hi_r_ff <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 151:28] + io.sec_data_ecc_lo_r_ff <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 152:28] + io.stbuf_ecc_any <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 153:28] + io.dma_dccm_wdata_ecc_hi <= dccm_wdata_ecc_hi_any @[el2_lsu_ecc.scala 154:28] + io.dma_dccm_wdata_ecc_lo <= dccm_wdata_ecc_lo_any @[el2_lsu_ecc.scala 155:28] + inst rvclkhdr of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1164 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1164 <= io.sec_data_hi_r @[el2_lib.scala 514:16] + io.sec_data_hi_r_ff <= _T_1164 @[el2_lsu_ecc.scala 157:23] + inst rvclkhdr_1 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= io.ld_single_ecc_error_r @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1165 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1165 <= io.sec_data_lo_r @[el2_lib.scala 514:16] + io.sec_data_lo_r_ff <= _T_1165 @[el2_lsu_ecc.scala 158:23] module el2_lsu_trigger : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip store_data_m : UInt<32>, lsu_trigger_match_m : UInt<4>} - io.lsu_trigger_match_m <= UInt<1>("h00") @[el2_lsu_trigger.scala 15:25] node _T = bits(io.lsu_pkt_m.word, 0, 0) @[Bitwise.scala 72:15] node _T_1 = mux(_T, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_2 = bits(io.store_data_m, 31, 16) @[el2_lsu_trigger.scala 17:77] - node _T_3 = and(_T_1, _T_2) @[el2_lsu_trigger.scala 17:60] - node _T_4 = or(io.lsu_pkt_m.half, io.lsu_pkt_m.word) @[el2_lsu_trigger.scala 17:110] + node _T_2 = bits(io.store_data_m, 31, 16) @[el2_lsu_trigger.scala 16:78] + node _T_3 = and(_T_1, _T_2) @[el2_lsu_trigger.scala 16:61] + node _T_4 = or(io.lsu_pkt_m.half, io.lsu_pkt_m.word) @[el2_lsu_trigger.scala 16:114] node _T_5 = bits(_T_4, 0, 0) @[Bitwise.scala 72:15] node _T_6 = mux(_T_5, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_7 = bits(io.store_data_m, 15, 8) @[el2_lsu_trigger.scala 17:148] - node _T_8 = and(_T_6, _T_7) @[el2_lsu_trigger.scala 17:131] - node _T_9 = bits(io.store_data_m, 7, 0) @[el2_lsu_trigger.scala 17:171] + node _T_7 = bits(io.store_data_m, 15, 8) @[el2_lsu_trigger.scala 16:153] + node _T_8 = and(_T_6, _T_7) @[el2_lsu_trigger.scala 16:136] + node _T_9 = bits(io.store_data_m, 7, 0) @[el2_lsu_trigger.scala 16:177] node _T_10 = cat(_T_3, _T_8) @[Cat.scala 29:58] node store_data_trigger_m = cat(_T_10, _T_9) @[Cat.scala 29:58] - node _T_11 = bits(io.trigger_pkt_any[0].select, 0, 0) @[el2_lsu_trigger.scala 24:137] - node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_lsu_trigger.scala 24:107] - node _T_13 = and(io.trigger_pkt_any[0].select, io.trigger_pkt_any[0].store) @[el2_lsu_trigger.scala 25:35] - node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_trigger.scala 25:66] + node _T_11 = bits(io.trigger_pkt_any[0].select, 0, 0) @[el2_lsu_trigger.scala 17:83] + node _T_12 = eq(_T_11, UInt<1>("h00")) @[el2_lsu_trigger.scala 17:53] + node _T_13 = and(io.trigger_pkt_any[0].select, io.trigger_pkt_any[0].store) @[el2_lsu_trigger.scala 17:136] + node _T_14 = bits(_T_13, 0, 0) @[el2_lsu_trigger.scala 17:167] node _T_15 = mux(_T_12, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_16 = mux(_T_14, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] node _T_17 = or(_T_15, _T_16) @[Mux.scala 27:72] - wire _T_18 : UInt<32> @[Mux.scala 27:72] - _T_18 <= _T_17 @[Mux.scala 27:72] - node _T_19 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 25:133] - wire _T_20 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_21 = bits(_T_19, 0, 0) @[el2_lib.scala 194:37] - node _T_22 = bits(io.trigger_pkt_any[0].tdata2, 31, 0) @[el2_lib.scala 194:53] - node _T_23 = andr(_T_22) @[el2_lib.scala 194:73] - node _T_24 = not(_T_23) @[el2_lib.scala 194:47] - node _T_25 = and(_T_21, _T_24) @[el2_lib.scala 194:44] - node _T_26 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_27 = bits(_T_18, 0, 0) @[el2_lib.scala 195:60] - node _T_28 = eq(_T_26, _T_27) @[el2_lib.scala 195:52] - node _T_29 = or(_T_25, _T_28) @[el2_lib.scala 195:41] - _T_20[0] <= _T_29 @[el2_lib.scala 195:18] - node _T_30 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 197:29] - node _T_31 = andr(_T_30) @[el2_lib.scala 197:37] - node _T_32 = and(_T_31, _T_25) @[el2_lib.scala 197:42] - node _T_33 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 197:75] - node _T_34 = bits(_T_18, 1, 1) @[el2_lib.scala 197:87] - node _T_35 = eq(_T_33, _T_34) @[el2_lib.scala 197:79] - node _T_36 = mux(_T_32, UInt<1>("h01"), _T_35) @[el2_lib.scala 197:24] - _T_20[1] <= _T_36 @[el2_lib.scala 197:18] - node _T_37 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 197:29] - node _T_38 = andr(_T_37) @[el2_lib.scala 197:37] - node _T_39 = and(_T_38, _T_25) @[el2_lib.scala 197:42] - node _T_40 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 197:75] - node _T_41 = bits(_T_18, 2, 2) @[el2_lib.scala 197:87] - node _T_42 = eq(_T_40, _T_41) @[el2_lib.scala 197:79] - node _T_43 = mux(_T_39, UInt<1>("h01"), _T_42) @[el2_lib.scala 197:24] - _T_20[2] <= _T_43 @[el2_lib.scala 197:18] - node _T_44 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 197:29] - node _T_45 = andr(_T_44) @[el2_lib.scala 197:37] - node _T_46 = and(_T_45, _T_25) @[el2_lib.scala 197:42] - node _T_47 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 197:75] - node _T_48 = bits(_T_18, 3, 3) @[el2_lib.scala 197:87] - node _T_49 = eq(_T_47, _T_48) @[el2_lib.scala 197:79] - node _T_50 = mux(_T_46, UInt<1>("h01"), _T_49) @[el2_lib.scala 197:24] - _T_20[3] <= _T_50 @[el2_lib.scala 197:18] - node _T_51 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 197:29] - node _T_52 = andr(_T_51) @[el2_lib.scala 197:37] - node _T_53 = and(_T_52, _T_25) @[el2_lib.scala 197:42] - node _T_54 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 197:75] - node _T_55 = bits(_T_18, 4, 4) @[el2_lib.scala 197:87] - node _T_56 = eq(_T_54, _T_55) @[el2_lib.scala 197:79] - node _T_57 = mux(_T_53, UInt<1>("h01"), _T_56) @[el2_lib.scala 197:24] - _T_20[4] <= _T_57 @[el2_lib.scala 197:18] - node _T_58 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 197:29] - node _T_59 = andr(_T_58) @[el2_lib.scala 197:37] - node _T_60 = and(_T_59, _T_25) @[el2_lib.scala 197:42] - node _T_61 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 197:75] - node _T_62 = bits(_T_18, 5, 5) @[el2_lib.scala 197:87] - node _T_63 = eq(_T_61, _T_62) @[el2_lib.scala 197:79] - node _T_64 = mux(_T_60, UInt<1>("h01"), _T_63) @[el2_lib.scala 197:24] - _T_20[5] <= _T_64 @[el2_lib.scala 197:18] - node _T_65 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 197:29] - node _T_66 = andr(_T_65) @[el2_lib.scala 197:37] - node _T_67 = and(_T_66, _T_25) @[el2_lib.scala 197:42] - node _T_68 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 197:75] - node _T_69 = bits(_T_18, 6, 6) @[el2_lib.scala 197:87] - node _T_70 = eq(_T_68, _T_69) @[el2_lib.scala 197:79] - node _T_71 = mux(_T_67, UInt<1>("h01"), _T_70) @[el2_lib.scala 197:24] - _T_20[6] <= _T_71 @[el2_lib.scala 197:18] - node _T_72 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 197:29] - node _T_73 = andr(_T_72) @[el2_lib.scala 197:37] - node _T_74 = and(_T_73, _T_25) @[el2_lib.scala 197:42] - node _T_75 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 197:75] - node _T_76 = bits(_T_18, 7, 7) @[el2_lib.scala 197:87] - node _T_77 = eq(_T_75, _T_76) @[el2_lib.scala 197:79] - node _T_78 = mux(_T_74, UInt<1>("h01"), _T_77) @[el2_lib.scala 197:24] - _T_20[7] <= _T_78 @[el2_lib.scala 197:18] - node _T_79 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 197:29] - node _T_80 = andr(_T_79) @[el2_lib.scala 197:37] - node _T_81 = and(_T_80, _T_25) @[el2_lib.scala 197:42] - node _T_82 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 197:75] - node _T_83 = bits(_T_18, 8, 8) @[el2_lib.scala 197:87] - node _T_84 = eq(_T_82, _T_83) @[el2_lib.scala 197:79] - node _T_85 = mux(_T_81, UInt<1>("h01"), _T_84) @[el2_lib.scala 197:24] - _T_20[8] <= _T_85 @[el2_lib.scala 197:18] - node _T_86 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 197:29] - node _T_87 = andr(_T_86) @[el2_lib.scala 197:37] - node _T_88 = and(_T_87, _T_25) @[el2_lib.scala 197:42] - node _T_89 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 197:75] - node _T_90 = bits(_T_18, 9, 9) @[el2_lib.scala 197:87] - node _T_91 = eq(_T_89, _T_90) @[el2_lib.scala 197:79] - node _T_92 = mux(_T_88, UInt<1>("h01"), _T_91) @[el2_lib.scala 197:24] - _T_20[9] <= _T_92 @[el2_lib.scala 197:18] - node _T_93 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 197:29] - node _T_94 = andr(_T_93) @[el2_lib.scala 197:37] - node _T_95 = and(_T_94, _T_25) @[el2_lib.scala 197:42] - node _T_96 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 197:75] - node _T_97 = bits(_T_18, 10, 10) @[el2_lib.scala 197:87] - node _T_98 = eq(_T_96, _T_97) @[el2_lib.scala 197:79] - node _T_99 = mux(_T_95, UInt<1>("h01"), _T_98) @[el2_lib.scala 197:24] - _T_20[10] <= _T_99 @[el2_lib.scala 197:18] - node _T_100 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 197:29] - node _T_101 = andr(_T_100) @[el2_lib.scala 197:37] - node _T_102 = and(_T_101, _T_25) @[el2_lib.scala 197:42] - node _T_103 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 197:75] - node _T_104 = bits(_T_18, 11, 11) @[el2_lib.scala 197:87] - node _T_105 = eq(_T_103, _T_104) @[el2_lib.scala 197:79] - node _T_106 = mux(_T_102, UInt<1>("h01"), _T_105) @[el2_lib.scala 197:24] - _T_20[11] <= _T_106 @[el2_lib.scala 197:18] - node _T_107 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 197:29] - node _T_108 = andr(_T_107) @[el2_lib.scala 197:37] - node _T_109 = and(_T_108, _T_25) @[el2_lib.scala 197:42] - node _T_110 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 197:75] - node _T_111 = bits(_T_18, 12, 12) @[el2_lib.scala 197:87] - node _T_112 = eq(_T_110, _T_111) @[el2_lib.scala 197:79] - node _T_113 = mux(_T_109, UInt<1>("h01"), _T_112) @[el2_lib.scala 197:24] - _T_20[12] <= _T_113 @[el2_lib.scala 197:18] - node _T_114 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 197:29] - node _T_115 = andr(_T_114) @[el2_lib.scala 197:37] - node _T_116 = and(_T_115, _T_25) @[el2_lib.scala 197:42] - node _T_117 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 197:75] - node _T_118 = bits(_T_18, 13, 13) @[el2_lib.scala 197:87] - node _T_119 = eq(_T_117, _T_118) @[el2_lib.scala 197:79] - node _T_120 = mux(_T_116, UInt<1>("h01"), _T_119) @[el2_lib.scala 197:24] - _T_20[13] <= _T_120 @[el2_lib.scala 197:18] - node _T_121 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 197:29] - node _T_122 = andr(_T_121) @[el2_lib.scala 197:37] - node _T_123 = and(_T_122, _T_25) @[el2_lib.scala 197:42] - node _T_124 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 197:75] - node _T_125 = bits(_T_18, 14, 14) @[el2_lib.scala 197:87] - node _T_126 = eq(_T_124, _T_125) @[el2_lib.scala 197:79] - node _T_127 = mux(_T_123, UInt<1>("h01"), _T_126) @[el2_lib.scala 197:24] - _T_20[14] <= _T_127 @[el2_lib.scala 197:18] - node _T_128 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 197:29] - node _T_129 = andr(_T_128) @[el2_lib.scala 197:37] - node _T_130 = and(_T_129, _T_25) @[el2_lib.scala 197:42] - node _T_131 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 197:75] - node _T_132 = bits(_T_18, 15, 15) @[el2_lib.scala 197:87] - node _T_133 = eq(_T_131, _T_132) @[el2_lib.scala 197:79] - node _T_134 = mux(_T_130, UInt<1>("h01"), _T_133) @[el2_lib.scala 197:24] - _T_20[15] <= _T_134 @[el2_lib.scala 197:18] - node _T_135 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 197:29] - node _T_136 = andr(_T_135) @[el2_lib.scala 197:37] - node _T_137 = and(_T_136, _T_25) @[el2_lib.scala 197:42] - node _T_138 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 197:75] - node _T_139 = bits(_T_18, 16, 16) @[el2_lib.scala 197:87] - node _T_140 = eq(_T_138, _T_139) @[el2_lib.scala 197:79] - node _T_141 = mux(_T_137, UInt<1>("h01"), _T_140) @[el2_lib.scala 197:24] - _T_20[16] <= _T_141 @[el2_lib.scala 197:18] - node _T_142 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 197:29] - node _T_143 = andr(_T_142) @[el2_lib.scala 197:37] - node _T_144 = and(_T_143, _T_25) @[el2_lib.scala 197:42] - node _T_145 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 197:75] - node _T_146 = bits(_T_18, 17, 17) @[el2_lib.scala 197:87] - node _T_147 = eq(_T_145, _T_146) @[el2_lib.scala 197:79] - node _T_148 = mux(_T_144, UInt<1>("h01"), _T_147) @[el2_lib.scala 197:24] - _T_20[17] <= _T_148 @[el2_lib.scala 197:18] - node _T_149 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 197:29] - node _T_150 = andr(_T_149) @[el2_lib.scala 197:37] - node _T_151 = and(_T_150, _T_25) @[el2_lib.scala 197:42] - node _T_152 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 197:75] - node _T_153 = bits(_T_18, 18, 18) @[el2_lib.scala 197:87] - node _T_154 = eq(_T_152, _T_153) @[el2_lib.scala 197:79] - node _T_155 = mux(_T_151, UInt<1>("h01"), _T_154) @[el2_lib.scala 197:24] - _T_20[18] <= _T_155 @[el2_lib.scala 197:18] - node _T_156 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 197:29] - node _T_157 = andr(_T_156) @[el2_lib.scala 197:37] - node _T_158 = and(_T_157, _T_25) @[el2_lib.scala 197:42] - node _T_159 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 197:75] - node _T_160 = bits(_T_18, 19, 19) @[el2_lib.scala 197:87] - node _T_161 = eq(_T_159, _T_160) @[el2_lib.scala 197:79] - node _T_162 = mux(_T_158, UInt<1>("h01"), _T_161) @[el2_lib.scala 197:24] - _T_20[19] <= _T_162 @[el2_lib.scala 197:18] - node _T_163 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 197:29] - node _T_164 = andr(_T_163) @[el2_lib.scala 197:37] - node _T_165 = and(_T_164, _T_25) @[el2_lib.scala 197:42] - node _T_166 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 197:75] - node _T_167 = bits(_T_18, 20, 20) @[el2_lib.scala 197:87] - node _T_168 = eq(_T_166, _T_167) @[el2_lib.scala 197:79] - node _T_169 = mux(_T_165, UInt<1>("h01"), _T_168) @[el2_lib.scala 197:24] - _T_20[20] <= _T_169 @[el2_lib.scala 197:18] - node _T_170 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 197:29] - node _T_171 = andr(_T_170) @[el2_lib.scala 197:37] - node _T_172 = and(_T_171, _T_25) @[el2_lib.scala 197:42] - node _T_173 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 197:75] - node _T_174 = bits(_T_18, 21, 21) @[el2_lib.scala 197:87] - node _T_175 = eq(_T_173, _T_174) @[el2_lib.scala 197:79] - node _T_176 = mux(_T_172, UInt<1>("h01"), _T_175) @[el2_lib.scala 197:24] - _T_20[21] <= _T_176 @[el2_lib.scala 197:18] - node _T_177 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 197:29] - node _T_178 = andr(_T_177) @[el2_lib.scala 197:37] - node _T_179 = and(_T_178, _T_25) @[el2_lib.scala 197:42] - node _T_180 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 197:75] - node _T_181 = bits(_T_18, 22, 22) @[el2_lib.scala 197:87] - node _T_182 = eq(_T_180, _T_181) @[el2_lib.scala 197:79] - node _T_183 = mux(_T_179, UInt<1>("h01"), _T_182) @[el2_lib.scala 197:24] - _T_20[22] <= _T_183 @[el2_lib.scala 197:18] - node _T_184 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 197:29] - node _T_185 = andr(_T_184) @[el2_lib.scala 197:37] - node _T_186 = and(_T_185, _T_25) @[el2_lib.scala 197:42] - node _T_187 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 197:75] - node _T_188 = bits(_T_18, 23, 23) @[el2_lib.scala 197:87] - node _T_189 = eq(_T_187, _T_188) @[el2_lib.scala 197:79] - node _T_190 = mux(_T_186, UInt<1>("h01"), _T_189) @[el2_lib.scala 197:24] - _T_20[23] <= _T_190 @[el2_lib.scala 197:18] - node _T_191 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 197:29] - node _T_192 = andr(_T_191) @[el2_lib.scala 197:37] - node _T_193 = and(_T_192, _T_25) @[el2_lib.scala 197:42] - node _T_194 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 197:75] - node _T_195 = bits(_T_18, 24, 24) @[el2_lib.scala 197:87] - node _T_196 = eq(_T_194, _T_195) @[el2_lib.scala 197:79] - node _T_197 = mux(_T_193, UInt<1>("h01"), _T_196) @[el2_lib.scala 197:24] - _T_20[24] <= _T_197 @[el2_lib.scala 197:18] - node _T_198 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 197:29] - node _T_199 = andr(_T_198) @[el2_lib.scala 197:37] - node _T_200 = and(_T_199, _T_25) @[el2_lib.scala 197:42] - node _T_201 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 197:75] - node _T_202 = bits(_T_18, 25, 25) @[el2_lib.scala 197:87] - node _T_203 = eq(_T_201, _T_202) @[el2_lib.scala 197:79] - node _T_204 = mux(_T_200, UInt<1>("h01"), _T_203) @[el2_lib.scala 197:24] - _T_20[25] <= _T_204 @[el2_lib.scala 197:18] - node _T_205 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 197:29] - node _T_206 = andr(_T_205) @[el2_lib.scala 197:37] - node _T_207 = and(_T_206, _T_25) @[el2_lib.scala 197:42] - node _T_208 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 197:75] - node _T_209 = bits(_T_18, 26, 26) @[el2_lib.scala 197:87] - node _T_210 = eq(_T_208, _T_209) @[el2_lib.scala 197:79] - node _T_211 = mux(_T_207, UInt<1>("h01"), _T_210) @[el2_lib.scala 197:24] - _T_20[26] <= _T_211 @[el2_lib.scala 197:18] - node _T_212 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 197:29] - node _T_213 = andr(_T_212) @[el2_lib.scala 197:37] - node _T_214 = and(_T_213, _T_25) @[el2_lib.scala 197:42] - node _T_215 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 197:75] - node _T_216 = bits(_T_18, 27, 27) @[el2_lib.scala 197:87] - node _T_217 = eq(_T_215, _T_216) @[el2_lib.scala 197:79] - node _T_218 = mux(_T_214, UInt<1>("h01"), _T_217) @[el2_lib.scala 197:24] - _T_20[27] <= _T_218 @[el2_lib.scala 197:18] - node _T_219 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 197:29] - node _T_220 = andr(_T_219) @[el2_lib.scala 197:37] - node _T_221 = and(_T_220, _T_25) @[el2_lib.scala 197:42] - node _T_222 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 197:75] - node _T_223 = bits(_T_18, 28, 28) @[el2_lib.scala 197:87] - node _T_224 = eq(_T_222, _T_223) @[el2_lib.scala 197:79] - node _T_225 = mux(_T_221, UInt<1>("h01"), _T_224) @[el2_lib.scala 197:24] - _T_20[28] <= _T_225 @[el2_lib.scala 197:18] - node _T_226 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 197:29] - node _T_227 = andr(_T_226) @[el2_lib.scala 197:37] - node _T_228 = and(_T_227, _T_25) @[el2_lib.scala 197:42] - node _T_229 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 197:75] - node _T_230 = bits(_T_18, 29, 29) @[el2_lib.scala 197:87] - node _T_231 = eq(_T_229, _T_230) @[el2_lib.scala 197:79] - node _T_232 = mux(_T_228, UInt<1>("h01"), _T_231) @[el2_lib.scala 197:24] - _T_20[29] <= _T_232 @[el2_lib.scala 197:18] - node _T_233 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 197:29] - node _T_234 = andr(_T_233) @[el2_lib.scala 197:37] - node _T_235 = and(_T_234, _T_25) @[el2_lib.scala 197:42] - node _T_236 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 197:75] - node _T_237 = bits(_T_18, 30, 30) @[el2_lib.scala 197:87] - node _T_238 = eq(_T_236, _T_237) @[el2_lib.scala 197:79] - node _T_239 = mux(_T_235, UInt<1>("h01"), _T_238) @[el2_lib.scala 197:24] - _T_20[30] <= _T_239 @[el2_lib.scala 197:18] - node _T_240 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 197:29] - node _T_241 = andr(_T_240) @[el2_lib.scala 197:37] - node _T_242 = and(_T_241, _T_25) @[el2_lib.scala 197:42] - node _T_243 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 197:75] - node _T_244 = bits(_T_18, 31, 31) @[el2_lib.scala 197:87] - node _T_245 = eq(_T_243, _T_244) @[el2_lib.scala 197:79] - node _T_246 = mux(_T_242, UInt<1>("h01"), _T_245) @[el2_lib.scala 197:24] - _T_20[31] <= _T_246 @[el2_lib.scala 197:18] - node _T_247 = cat(_T_20[1], _T_20[0]) @[el2_lib.scala 198:14] - node _T_248 = cat(_T_20[3], _T_20[2]) @[el2_lib.scala 198:14] - node _T_249 = cat(_T_248, _T_247) @[el2_lib.scala 198:14] - node _T_250 = cat(_T_20[5], _T_20[4]) @[el2_lib.scala 198:14] - node _T_251 = cat(_T_20[7], _T_20[6]) @[el2_lib.scala 198:14] - node _T_252 = cat(_T_251, _T_250) @[el2_lib.scala 198:14] - node _T_253 = cat(_T_252, _T_249) @[el2_lib.scala 198:14] - node _T_254 = cat(_T_20[9], _T_20[8]) @[el2_lib.scala 198:14] - node _T_255 = cat(_T_20[11], _T_20[10]) @[el2_lib.scala 198:14] - node _T_256 = cat(_T_255, _T_254) @[el2_lib.scala 198:14] - node _T_257 = cat(_T_20[13], _T_20[12]) @[el2_lib.scala 198:14] - node _T_258 = cat(_T_20[15], _T_20[14]) @[el2_lib.scala 198:14] - node _T_259 = cat(_T_258, _T_257) @[el2_lib.scala 198:14] - node _T_260 = cat(_T_259, _T_256) @[el2_lib.scala 198:14] - node _T_261 = cat(_T_260, _T_253) @[el2_lib.scala 198:14] - node _T_262 = cat(_T_20[17], _T_20[16]) @[el2_lib.scala 198:14] - node _T_263 = cat(_T_20[19], _T_20[18]) @[el2_lib.scala 198:14] - node _T_264 = cat(_T_263, _T_262) @[el2_lib.scala 198:14] - node _T_265 = cat(_T_20[21], _T_20[20]) @[el2_lib.scala 198:14] - node _T_266 = cat(_T_20[23], _T_20[22]) @[el2_lib.scala 198:14] - node _T_267 = cat(_T_266, _T_265) @[el2_lib.scala 198:14] - node _T_268 = cat(_T_267, _T_264) @[el2_lib.scala 198:14] - node _T_269 = cat(_T_20[25], _T_20[24]) @[el2_lib.scala 198:14] - node _T_270 = cat(_T_20[27], _T_20[26]) @[el2_lib.scala 198:14] - node _T_271 = cat(_T_270, _T_269) @[el2_lib.scala 198:14] - node _T_272 = cat(_T_20[29], _T_20[28]) @[el2_lib.scala 198:14] - node _T_273 = cat(_T_20[31], _T_20[30]) @[el2_lib.scala 198:14] - node _T_274 = cat(_T_273, _T_272) @[el2_lib.scala 198:14] - node _T_275 = cat(_T_274, _T_271) @[el2_lib.scala 198:14] - node _T_276 = cat(_T_275, _T_268) @[el2_lib.scala 198:14] - node _T_277 = cat(_T_276, _T_261) @[el2_lib.scala 198:14] - node lsu_trigger_data_match_0 = andr(_T_277) @[el2_lib.scala 198:21] - node _T_278 = bits(io.trigger_pkt_any[1].select, 0, 0) @[el2_lsu_trigger.scala 24:137] - node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_trigger.scala 24:107] - node _T_280 = and(io.trigger_pkt_any[1].select, io.trigger_pkt_any[1].store) @[el2_lsu_trigger.scala 25:35] - node _T_281 = bits(_T_280, 0, 0) @[el2_lsu_trigger.scala 25:66] - node _T_282 = mux(_T_279, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_283 = mux(_T_281, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_284 = or(_T_282, _T_283) @[Mux.scala 27:72] - wire _T_285 : UInt<32> @[Mux.scala 27:72] - _T_285 <= _T_284 @[Mux.scala 27:72] - node _T_286 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 25:133] - wire _T_287 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_288 = bits(_T_286, 0, 0) @[el2_lib.scala 194:37] - node _T_289 = bits(io.trigger_pkt_any[1].tdata2, 31, 0) @[el2_lib.scala 194:53] - node _T_290 = andr(_T_289) @[el2_lib.scala 194:73] - node _T_291 = not(_T_290) @[el2_lib.scala 194:47] - node _T_292 = and(_T_288, _T_291) @[el2_lib.scala 194:44] - node _T_293 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_294 = bits(_T_285, 0, 0) @[el2_lib.scala 195:60] - node _T_295 = eq(_T_293, _T_294) @[el2_lib.scala 195:52] - node _T_296 = or(_T_292, _T_295) @[el2_lib.scala 195:41] - _T_287[0] <= _T_296 @[el2_lib.scala 195:18] - node _T_297 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 197:29] - node _T_298 = andr(_T_297) @[el2_lib.scala 197:37] - node _T_299 = and(_T_298, _T_292) @[el2_lib.scala 197:42] - node _T_300 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 197:75] - node _T_301 = bits(_T_285, 1, 1) @[el2_lib.scala 197:87] - node _T_302 = eq(_T_300, _T_301) @[el2_lib.scala 197:79] - node _T_303 = mux(_T_299, UInt<1>("h01"), _T_302) @[el2_lib.scala 197:24] - _T_287[1] <= _T_303 @[el2_lib.scala 197:18] - node _T_304 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 197:29] - node _T_305 = andr(_T_304) @[el2_lib.scala 197:37] - node _T_306 = and(_T_305, _T_292) @[el2_lib.scala 197:42] - node _T_307 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 197:75] - node _T_308 = bits(_T_285, 2, 2) @[el2_lib.scala 197:87] - node _T_309 = eq(_T_307, _T_308) @[el2_lib.scala 197:79] - node _T_310 = mux(_T_306, UInt<1>("h01"), _T_309) @[el2_lib.scala 197:24] - _T_287[2] <= _T_310 @[el2_lib.scala 197:18] - node _T_311 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 197:29] - node _T_312 = andr(_T_311) @[el2_lib.scala 197:37] - node _T_313 = and(_T_312, _T_292) @[el2_lib.scala 197:42] - node _T_314 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 197:75] - node _T_315 = bits(_T_285, 3, 3) @[el2_lib.scala 197:87] - node _T_316 = eq(_T_314, _T_315) @[el2_lib.scala 197:79] - node _T_317 = mux(_T_313, UInt<1>("h01"), _T_316) @[el2_lib.scala 197:24] - _T_287[3] <= _T_317 @[el2_lib.scala 197:18] - node _T_318 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 197:29] - node _T_319 = andr(_T_318) @[el2_lib.scala 197:37] - node _T_320 = and(_T_319, _T_292) @[el2_lib.scala 197:42] - node _T_321 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 197:75] - node _T_322 = bits(_T_285, 4, 4) @[el2_lib.scala 197:87] - node _T_323 = eq(_T_321, _T_322) @[el2_lib.scala 197:79] - node _T_324 = mux(_T_320, UInt<1>("h01"), _T_323) @[el2_lib.scala 197:24] - _T_287[4] <= _T_324 @[el2_lib.scala 197:18] - node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 197:29] - node _T_326 = andr(_T_325) @[el2_lib.scala 197:37] - node _T_327 = and(_T_326, _T_292) @[el2_lib.scala 197:42] - node _T_328 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 197:75] - node _T_329 = bits(_T_285, 5, 5) @[el2_lib.scala 197:87] - node _T_330 = eq(_T_328, _T_329) @[el2_lib.scala 197:79] - node _T_331 = mux(_T_327, UInt<1>("h01"), _T_330) @[el2_lib.scala 197:24] - _T_287[5] <= _T_331 @[el2_lib.scala 197:18] - node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 197:29] - node _T_333 = andr(_T_332) @[el2_lib.scala 197:37] - node _T_334 = and(_T_333, _T_292) @[el2_lib.scala 197:42] - node _T_335 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 197:75] - node _T_336 = bits(_T_285, 6, 6) @[el2_lib.scala 197:87] - node _T_337 = eq(_T_335, _T_336) @[el2_lib.scala 197:79] - node _T_338 = mux(_T_334, UInt<1>("h01"), _T_337) @[el2_lib.scala 197:24] - _T_287[6] <= _T_338 @[el2_lib.scala 197:18] - node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 197:29] - node _T_340 = andr(_T_339) @[el2_lib.scala 197:37] - node _T_341 = and(_T_340, _T_292) @[el2_lib.scala 197:42] - node _T_342 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 197:75] - node _T_343 = bits(_T_285, 7, 7) @[el2_lib.scala 197:87] - node _T_344 = eq(_T_342, _T_343) @[el2_lib.scala 197:79] - node _T_345 = mux(_T_341, UInt<1>("h01"), _T_344) @[el2_lib.scala 197:24] - _T_287[7] <= _T_345 @[el2_lib.scala 197:18] - node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 197:29] - node _T_347 = andr(_T_346) @[el2_lib.scala 197:37] - node _T_348 = and(_T_347, _T_292) @[el2_lib.scala 197:42] - node _T_349 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 197:75] - node _T_350 = bits(_T_285, 8, 8) @[el2_lib.scala 197:87] - node _T_351 = eq(_T_349, _T_350) @[el2_lib.scala 197:79] - node _T_352 = mux(_T_348, UInt<1>("h01"), _T_351) @[el2_lib.scala 197:24] - _T_287[8] <= _T_352 @[el2_lib.scala 197:18] - node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 197:29] - node _T_354 = andr(_T_353) @[el2_lib.scala 197:37] - node _T_355 = and(_T_354, _T_292) @[el2_lib.scala 197:42] - node _T_356 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 197:75] - node _T_357 = bits(_T_285, 9, 9) @[el2_lib.scala 197:87] - node _T_358 = eq(_T_356, _T_357) @[el2_lib.scala 197:79] - node _T_359 = mux(_T_355, UInt<1>("h01"), _T_358) @[el2_lib.scala 197:24] - _T_287[9] <= _T_359 @[el2_lib.scala 197:18] - node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 197:29] - node _T_361 = andr(_T_360) @[el2_lib.scala 197:37] - node _T_362 = and(_T_361, _T_292) @[el2_lib.scala 197:42] - node _T_363 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 197:75] - node _T_364 = bits(_T_285, 10, 10) @[el2_lib.scala 197:87] - node _T_365 = eq(_T_363, _T_364) @[el2_lib.scala 197:79] - node _T_366 = mux(_T_362, UInt<1>("h01"), _T_365) @[el2_lib.scala 197:24] - _T_287[10] <= _T_366 @[el2_lib.scala 197:18] - node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 197:29] - node _T_368 = andr(_T_367) @[el2_lib.scala 197:37] - node _T_369 = and(_T_368, _T_292) @[el2_lib.scala 197:42] - node _T_370 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 197:75] - node _T_371 = bits(_T_285, 11, 11) @[el2_lib.scala 197:87] - node _T_372 = eq(_T_370, _T_371) @[el2_lib.scala 197:79] - node _T_373 = mux(_T_369, UInt<1>("h01"), _T_372) @[el2_lib.scala 197:24] - _T_287[11] <= _T_373 @[el2_lib.scala 197:18] - node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 197:29] - node _T_375 = andr(_T_374) @[el2_lib.scala 197:37] - node _T_376 = and(_T_375, _T_292) @[el2_lib.scala 197:42] - node _T_377 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 197:75] - node _T_378 = bits(_T_285, 12, 12) @[el2_lib.scala 197:87] - node _T_379 = eq(_T_377, _T_378) @[el2_lib.scala 197:79] - node _T_380 = mux(_T_376, UInt<1>("h01"), _T_379) @[el2_lib.scala 197:24] - _T_287[12] <= _T_380 @[el2_lib.scala 197:18] - node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 197:29] - node _T_382 = andr(_T_381) @[el2_lib.scala 197:37] - node _T_383 = and(_T_382, _T_292) @[el2_lib.scala 197:42] - node _T_384 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 197:75] - node _T_385 = bits(_T_285, 13, 13) @[el2_lib.scala 197:87] - node _T_386 = eq(_T_384, _T_385) @[el2_lib.scala 197:79] - node _T_387 = mux(_T_383, UInt<1>("h01"), _T_386) @[el2_lib.scala 197:24] - _T_287[13] <= _T_387 @[el2_lib.scala 197:18] - node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 197:29] - node _T_389 = andr(_T_388) @[el2_lib.scala 197:37] - node _T_390 = and(_T_389, _T_292) @[el2_lib.scala 197:42] - node _T_391 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 197:75] - node _T_392 = bits(_T_285, 14, 14) @[el2_lib.scala 197:87] - node _T_393 = eq(_T_391, _T_392) @[el2_lib.scala 197:79] - node _T_394 = mux(_T_390, UInt<1>("h01"), _T_393) @[el2_lib.scala 197:24] - _T_287[14] <= _T_394 @[el2_lib.scala 197:18] - node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 197:29] - node _T_396 = andr(_T_395) @[el2_lib.scala 197:37] - node _T_397 = and(_T_396, _T_292) @[el2_lib.scala 197:42] - node _T_398 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 197:75] - node _T_399 = bits(_T_285, 15, 15) @[el2_lib.scala 197:87] - node _T_400 = eq(_T_398, _T_399) @[el2_lib.scala 197:79] - node _T_401 = mux(_T_397, UInt<1>("h01"), _T_400) @[el2_lib.scala 197:24] - _T_287[15] <= _T_401 @[el2_lib.scala 197:18] - node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 197:29] - node _T_403 = andr(_T_402) @[el2_lib.scala 197:37] - node _T_404 = and(_T_403, _T_292) @[el2_lib.scala 197:42] - node _T_405 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 197:75] - node _T_406 = bits(_T_285, 16, 16) @[el2_lib.scala 197:87] - node _T_407 = eq(_T_405, _T_406) @[el2_lib.scala 197:79] - node _T_408 = mux(_T_404, UInt<1>("h01"), _T_407) @[el2_lib.scala 197:24] - _T_287[16] <= _T_408 @[el2_lib.scala 197:18] - node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 197:29] - node _T_410 = andr(_T_409) @[el2_lib.scala 197:37] - node _T_411 = and(_T_410, _T_292) @[el2_lib.scala 197:42] - node _T_412 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 197:75] - node _T_413 = bits(_T_285, 17, 17) @[el2_lib.scala 197:87] - node _T_414 = eq(_T_412, _T_413) @[el2_lib.scala 197:79] - node _T_415 = mux(_T_411, UInt<1>("h01"), _T_414) @[el2_lib.scala 197:24] - _T_287[17] <= _T_415 @[el2_lib.scala 197:18] - node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 197:29] - node _T_417 = andr(_T_416) @[el2_lib.scala 197:37] - node _T_418 = and(_T_417, _T_292) @[el2_lib.scala 197:42] - node _T_419 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 197:75] - node _T_420 = bits(_T_285, 18, 18) @[el2_lib.scala 197:87] - node _T_421 = eq(_T_419, _T_420) @[el2_lib.scala 197:79] - node _T_422 = mux(_T_418, UInt<1>("h01"), _T_421) @[el2_lib.scala 197:24] - _T_287[18] <= _T_422 @[el2_lib.scala 197:18] - node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 197:29] - node _T_424 = andr(_T_423) @[el2_lib.scala 197:37] - node _T_425 = and(_T_424, _T_292) @[el2_lib.scala 197:42] - node _T_426 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 197:75] - node _T_427 = bits(_T_285, 19, 19) @[el2_lib.scala 197:87] - node _T_428 = eq(_T_426, _T_427) @[el2_lib.scala 197:79] - node _T_429 = mux(_T_425, UInt<1>("h01"), _T_428) @[el2_lib.scala 197:24] - _T_287[19] <= _T_429 @[el2_lib.scala 197:18] - node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 197:29] - node _T_431 = andr(_T_430) @[el2_lib.scala 197:37] - node _T_432 = and(_T_431, _T_292) @[el2_lib.scala 197:42] - node _T_433 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 197:75] - node _T_434 = bits(_T_285, 20, 20) @[el2_lib.scala 197:87] - node _T_435 = eq(_T_433, _T_434) @[el2_lib.scala 197:79] - node _T_436 = mux(_T_432, UInt<1>("h01"), _T_435) @[el2_lib.scala 197:24] - _T_287[20] <= _T_436 @[el2_lib.scala 197:18] - node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 197:29] - node _T_438 = andr(_T_437) @[el2_lib.scala 197:37] - node _T_439 = and(_T_438, _T_292) @[el2_lib.scala 197:42] - node _T_440 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 197:75] - node _T_441 = bits(_T_285, 21, 21) @[el2_lib.scala 197:87] - node _T_442 = eq(_T_440, _T_441) @[el2_lib.scala 197:79] - node _T_443 = mux(_T_439, UInt<1>("h01"), _T_442) @[el2_lib.scala 197:24] - _T_287[21] <= _T_443 @[el2_lib.scala 197:18] - node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 197:29] - node _T_445 = andr(_T_444) @[el2_lib.scala 197:37] - node _T_446 = and(_T_445, _T_292) @[el2_lib.scala 197:42] - node _T_447 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 197:75] - node _T_448 = bits(_T_285, 22, 22) @[el2_lib.scala 197:87] - node _T_449 = eq(_T_447, _T_448) @[el2_lib.scala 197:79] - node _T_450 = mux(_T_446, UInt<1>("h01"), _T_449) @[el2_lib.scala 197:24] - _T_287[22] <= _T_450 @[el2_lib.scala 197:18] - node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 197:29] - node _T_452 = andr(_T_451) @[el2_lib.scala 197:37] - node _T_453 = and(_T_452, _T_292) @[el2_lib.scala 197:42] - node _T_454 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 197:75] - node _T_455 = bits(_T_285, 23, 23) @[el2_lib.scala 197:87] - node _T_456 = eq(_T_454, _T_455) @[el2_lib.scala 197:79] - node _T_457 = mux(_T_453, UInt<1>("h01"), _T_456) @[el2_lib.scala 197:24] - _T_287[23] <= _T_457 @[el2_lib.scala 197:18] - node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 197:29] - node _T_459 = andr(_T_458) @[el2_lib.scala 197:37] - node _T_460 = and(_T_459, _T_292) @[el2_lib.scala 197:42] - node _T_461 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 197:75] - node _T_462 = bits(_T_285, 24, 24) @[el2_lib.scala 197:87] - node _T_463 = eq(_T_461, _T_462) @[el2_lib.scala 197:79] - node _T_464 = mux(_T_460, UInt<1>("h01"), _T_463) @[el2_lib.scala 197:24] - _T_287[24] <= _T_464 @[el2_lib.scala 197:18] - node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 197:29] - node _T_466 = andr(_T_465) @[el2_lib.scala 197:37] - node _T_467 = and(_T_466, _T_292) @[el2_lib.scala 197:42] - node _T_468 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 197:75] - node _T_469 = bits(_T_285, 25, 25) @[el2_lib.scala 197:87] - node _T_470 = eq(_T_468, _T_469) @[el2_lib.scala 197:79] - node _T_471 = mux(_T_467, UInt<1>("h01"), _T_470) @[el2_lib.scala 197:24] - _T_287[25] <= _T_471 @[el2_lib.scala 197:18] - node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 197:29] - node _T_473 = andr(_T_472) @[el2_lib.scala 197:37] - node _T_474 = and(_T_473, _T_292) @[el2_lib.scala 197:42] - node _T_475 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 197:75] - node _T_476 = bits(_T_285, 26, 26) @[el2_lib.scala 197:87] - node _T_477 = eq(_T_475, _T_476) @[el2_lib.scala 197:79] - node _T_478 = mux(_T_474, UInt<1>("h01"), _T_477) @[el2_lib.scala 197:24] - _T_287[26] <= _T_478 @[el2_lib.scala 197:18] - node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 197:29] - node _T_480 = andr(_T_479) @[el2_lib.scala 197:37] - node _T_481 = and(_T_480, _T_292) @[el2_lib.scala 197:42] - node _T_482 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 197:75] - node _T_483 = bits(_T_285, 27, 27) @[el2_lib.scala 197:87] - node _T_484 = eq(_T_482, _T_483) @[el2_lib.scala 197:79] - node _T_485 = mux(_T_481, UInt<1>("h01"), _T_484) @[el2_lib.scala 197:24] - _T_287[27] <= _T_485 @[el2_lib.scala 197:18] - node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 197:29] - node _T_487 = andr(_T_486) @[el2_lib.scala 197:37] - node _T_488 = and(_T_487, _T_292) @[el2_lib.scala 197:42] - node _T_489 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 197:75] - node _T_490 = bits(_T_285, 28, 28) @[el2_lib.scala 197:87] - node _T_491 = eq(_T_489, _T_490) @[el2_lib.scala 197:79] - node _T_492 = mux(_T_488, UInt<1>("h01"), _T_491) @[el2_lib.scala 197:24] - _T_287[28] <= _T_492 @[el2_lib.scala 197:18] - node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 197:29] - node _T_494 = andr(_T_493) @[el2_lib.scala 197:37] - node _T_495 = and(_T_494, _T_292) @[el2_lib.scala 197:42] - node _T_496 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 197:75] - node _T_497 = bits(_T_285, 29, 29) @[el2_lib.scala 197:87] - node _T_498 = eq(_T_496, _T_497) @[el2_lib.scala 197:79] - node _T_499 = mux(_T_495, UInt<1>("h01"), _T_498) @[el2_lib.scala 197:24] - _T_287[29] <= _T_499 @[el2_lib.scala 197:18] - node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 197:29] - node _T_501 = andr(_T_500) @[el2_lib.scala 197:37] - node _T_502 = and(_T_501, _T_292) @[el2_lib.scala 197:42] - node _T_503 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 197:75] - node _T_504 = bits(_T_285, 30, 30) @[el2_lib.scala 197:87] - node _T_505 = eq(_T_503, _T_504) @[el2_lib.scala 197:79] - node _T_506 = mux(_T_502, UInt<1>("h01"), _T_505) @[el2_lib.scala 197:24] - _T_287[30] <= _T_506 @[el2_lib.scala 197:18] - node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 197:29] - node _T_508 = andr(_T_507) @[el2_lib.scala 197:37] - node _T_509 = and(_T_508, _T_292) @[el2_lib.scala 197:42] - node _T_510 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 197:75] - node _T_511 = bits(_T_285, 31, 31) @[el2_lib.scala 197:87] - node _T_512 = eq(_T_510, _T_511) @[el2_lib.scala 197:79] - node _T_513 = mux(_T_509, UInt<1>("h01"), _T_512) @[el2_lib.scala 197:24] - _T_287[31] <= _T_513 @[el2_lib.scala 197:18] - node _T_514 = cat(_T_287[1], _T_287[0]) @[el2_lib.scala 198:14] - node _T_515 = cat(_T_287[3], _T_287[2]) @[el2_lib.scala 198:14] - node _T_516 = cat(_T_515, _T_514) @[el2_lib.scala 198:14] - node _T_517 = cat(_T_287[5], _T_287[4]) @[el2_lib.scala 198:14] - node _T_518 = cat(_T_287[7], _T_287[6]) @[el2_lib.scala 198:14] - node _T_519 = cat(_T_518, _T_517) @[el2_lib.scala 198:14] - node _T_520 = cat(_T_519, _T_516) @[el2_lib.scala 198:14] - node _T_521 = cat(_T_287[9], _T_287[8]) @[el2_lib.scala 198:14] - node _T_522 = cat(_T_287[11], _T_287[10]) @[el2_lib.scala 198:14] - node _T_523 = cat(_T_522, _T_521) @[el2_lib.scala 198:14] - node _T_524 = cat(_T_287[13], _T_287[12]) @[el2_lib.scala 198:14] - node _T_525 = cat(_T_287[15], _T_287[14]) @[el2_lib.scala 198:14] - node _T_526 = cat(_T_525, _T_524) @[el2_lib.scala 198:14] - node _T_527 = cat(_T_526, _T_523) @[el2_lib.scala 198:14] - node _T_528 = cat(_T_527, _T_520) @[el2_lib.scala 198:14] - node _T_529 = cat(_T_287[17], _T_287[16]) @[el2_lib.scala 198:14] - node _T_530 = cat(_T_287[19], _T_287[18]) @[el2_lib.scala 198:14] - node _T_531 = cat(_T_530, _T_529) @[el2_lib.scala 198:14] - node _T_532 = cat(_T_287[21], _T_287[20]) @[el2_lib.scala 198:14] - node _T_533 = cat(_T_287[23], _T_287[22]) @[el2_lib.scala 198:14] - node _T_534 = cat(_T_533, _T_532) @[el2_lib.scala 198:14] - node _T_535 = cat(_T_534, _T_531) @[el2_lib.scala 198:14] - node _T_536 = cat(_T_287[25], _T_287[24]) @[el2_lib.scala 198:14] - node _T_537 = cat(_T_287[27], _T_287[26]) @[el2_lib.scala 198:14] - node _T_538 = cat(_T_537, _T_536) @[el2_lib.scala 198:14] - node _T_539 = cat(_T_287[29], _T_287[28]) @[el2_lib.scala 198:14] - node _T_540 = cat(_T_287[31], _T_287[30]) @[el2_lib.scala 198:14] - node _T_541 = cat(_T_540, _T_539) @[el2_lib.scala 198:14] - node _T_542 = cat(_T_541, _T_538) @[el2_lib.scala 198:14] - node _T_543 = cat(_T_542, _T_535) @[el2_lib.scala 198:14] - node _T_544 = cat(_T_543, _T_528) @[el2_lib.scala 198:14] - node lsu_trigger_data_match_1 = andr(_T_544) @[el2_lib.scala 198:21] - node _T_545 = bits(io.trigger_pkt_any[2].select, 0, 0) @[el2_lsu_trigger.scala 24:137] - node _T_546 = eq(_T_545, UInt<1>("h00")) @[el2_lsu_trigger.scala 24:107] - node _T_547 = and(io.trigger_pkt_any[2].select, io.trigger_pkt_any[2].store) @[el2_lsu_trigger.scala 25:35] - node _T_548 = bits(_T_547, 0, 0) @[el2_lsu_trigger.scala 25:66] - node _T_549 = mux(_T_546, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_550 = mux(_T_548, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_551 = or(_T_549, _T_550) @[Mux.scala 27:72] - wire _T_552 : UInt<32> @[Mux.scala 27:72] - _T_552 <= _T_551 @[Mux.scala 27:72] - node _T_553 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 25:133] - wire _T_554 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_555 = bits(_T_553, 0, 0) @[el2_lib.scala 194:37] - node _T_556 = bits(io.trigger_pkt_any[2].tdata2, 31, 0) @[el2_lib.scala 194:53] - node _T_557 = andr(_T_556) @[el2_lib.scala 194:73] - node _T_558 = not(_T_557) @[el2_lib.scala 194:47] - node _T_559 = and(_T_555, _T_558) @[el2_lib.scala 194:44] - node _T_560 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_561 = bits(_T_552, 0, 0) @[el2_lib.scala 195:60] - node _T_562 = eq(_T_560, _T_561) @[el2_lib.scala 195:52] - node _T_563 = or(_T_559, _T_562) @[el2_lib.scala 195:41] - _T_554[0] <= _T_563 @[el2_lib.scala 195:18] - node _T_564 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 197:29] - node _T_565 = andr(_T_564) @[el2_lib.scala 197:37] - node _T_566 = and(_T_565, _T_559) @[el2_lib.scala 197:42] - node _T_567 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 197:75] - node _T_568 = bits(_T_552, 1, 1) @[el2_lib.scala 197:87] - node _T_569 = eq(_T_567, _T_568) @[el2_lib.scala 197:79] - node _T_570 = mux(_T_566, UInt<1>("h01"), _T_569) @[el2_lib.scala 197:24] - _T_554[1] <= _T_570 @[el2_lib.scala 197:18] - node _T_571 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 197:29] - node _T_572 = andr(_T_571) @[el2_lib.scala 197:37] - node _T_573 = and(_T_572, _T_559) @[el2_lib.scala 197:42] - node _T_574 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 197:75] - node _T_575 = bits(_T_552, 2, 2) @[el2_lib.scala 197:87] - node _T_576 = eq(_T_574, _T_575) @[el2_lib.scala 197:79] - node _T_577 = mux(_T_573, UInt<1>("h01"), _T_576) @[el2_lib.scala 197:24] - _T_554[2] <= _T_577 @[el2_lib.scala 197:18] - node _T_578 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 197:29] - node _T_579 = andr(_T_578) @[el2_lib.scala 197:37] - node _T_580 = and(_T_579, _T_559) @[el2_lib.scala 197:42] - node _T_581 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 197:75] - node _T_582 = bits(_T_552, 3, 3) @[el2_lib.scala 197:87] - node _T_583 = eq(_T_581, _T_582) @[el2_lib.scala 197:79] - node _T_584 = mux(_T_580, UInt<1>("h01"), _T_583) @[el2_lib.scala 197:24] - _T_554[3] <= _T_584 @[el2_lib.scala 197:18] - node _T_585 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 197:29] - node _T_586 = andr(_T_585) @[el2_lib.scala 197:37] - node _T_587 = and(_T_586, _T_559) @[el2_lib.scala 197:42] - node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 197:75] - node _T_589 = bits(_T_552, 4, 4) @[el2_lib.scala 197:87] - node _T_590 = eq(_T_588, _T_589) @[el2_lib.scala 197:79] - node _T_591 = mux(_T_587, UInt<1>("h01"), _T_590) @[el2_lib.scala 197:24] - _T_554[4] <= _T_591 @[el2_lib.scala 197:18] - node _T_592 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 197:29] - node _T_593 = andr(_T_592) @[el2_lib.scala 197:37] - node _T_594 = and(_T_593, _T_559) @[el2_lib.scala 197:42] - node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 197:75] - node _T_596 = bits(_T_552, 5, 5) @[el2_lib.scala 197:87] - node _T_597 = eq(_T_595, _T_596) @[el2_lib.scala 197:79] - node _T_598 = mux(_T_594, UInt<1>("h01"), _T_597) @[el2_lib.scala 197:24] - _T_554[5] <= _T_598 @[el2_lib.scala 197:18] - node _T_599 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 197:29] - node _T_600 = andr(_T_599) @[el2_lib.scala 197:37] - node _T_601 = and(_T_600, _T_559) @[el2_lib.scala 197:42] - node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 197:75] - node _T_603 = bits(_T_552, 6, 6) @[el2_lib.scala 197:87] - node _T_604 = eq(_T_602, _T_603) @[el2_lib.scala 197:79] - node _T_605 = mux(_T_601, UInt<1>("h01"), _T_604) @[el2_lib.scala 197:24] - _T_554[6] <= _T_605 @[el2_lib.scala 197:18] - node _T_606 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 197:29] - node _T_607 = andr(_T_606) @[el2_lib.scala 197:37] - node _T_608 = and(_T_607, _T_559) @[el2_lib.scala 197:42] - node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 197:75] - node _T_610 = bits(_T_552, 7, 7) @[el2_lib.scala 197:87] - node _T_611 = eq(_T_609, _T_610) @[el2_lib.scala 197:79] - node _T_612 = mux(_T_608, UInt<1>("h01"), _T_611) @[el2_lib.scala 197:24] - _T_554[7] <= _T_612 @[el2_lib.scala 197:18] - node _T_613 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 197:29] - node _T_614 = andr(_T_613) @[el2_lib.scala 197:37] - node _T_615 = and(_T_614, _T_559) @[el2_lib.scala 197:42] - node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 197:75] - node _T_617 = bits(_T_552, 8, 8) @[el2_lib.scala 197:87] - node _T_618 = eq(_T_616, _T_617) @[el2_lib.scala 197:79] - node _T_619 = mux(_T_615, UInt<1>("h01"), _T_618) @[el2_lib.scala 197:24] - _T_554[8] <= _T_619 @[el2_lib.scala 197:18] - node _T_620 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 197:29] - node _T_621 = andr(_T_620) @[el2_lib.scala 197:37] - node _T_622 = and(_T_621, _T_559) @[el2_lib.scala 197:42] - node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 197:75] - node _T_624 = bits(_T_552, 9, 9) @[el2_lib.scala 197:87] - node _T_625 = eq(_T_623, _T_624) @[el2_lib.scala 197:79] - node _T_626 = mux(_T_622, UInt<1>("h01"), _T_625) @[el2_lib.scala 197:24] - _T_554[9] <= _T_626 @[el2_lib.scala 197:18] - node _T_627 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 197:29] - node _T_628 = andr(_T_627) @[el2_lib.scala 197:37] - node _T_629 = and(_T_628, _T_559) @[el2_lib.scala 197:42] - node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 197:75] - node _T_631 = bits(_T_552, 10, 10) @[el2_lib.scala 197:87] - node _T_632 = eq(_T_630, _T_631) @[el2_lib.scala 197:79] - node _T_633 = mux(_T_629, UInt<1>("h01"), _T_632) @[el2_lib.scala 197:24] - _T_554[10] <= _T_633 @[el2_lib.scala 197:18] - node _T_634 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 197:29] - node _T_635 = andr(_T_634) @[el2_lib.scala 197:37] - node _T_636 = and(_T_635, _T_559) @[el2_lib.scala 197:42] - node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 197:75] - node _T_638 = bits(_T_552, 11, 11) @[el2_lib.scala 197:87] - node _T_639 = eq(_T_637, _T_638) @[el2_lib.scala 197:79] - node _T_640 = mux(_T_636, UInt<1>("h01"), _T_639) @[el2_lib.scala 197:24] - _T_554[11] <= _T_640 @[el2_lib.scala 197:18] - node _T_641 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 197:29] - node _T_642 = andr(_T_641) @[el2_lib.scala 197:37] - node _T_643 = and(_T_642, _T_559) @[el2_lib.scala 197:42] - node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 197:75] - node _T_645 = bits(_T_552, 12, 12) @[el2_lib.scala 197:87] - node _T_646 = eq(_T_644, _T_645) @[el2_lib.scala 197:79] - node _T_647 = mux(_T_643, UInt<1>("h01"), _T_646) @[el2_lib.scala 197:24] - _T_554[12] <= _T_647 @[el2_lib.scala 197:18] - node _T_648 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 197:29] - node _T_649 = andr(_T_648) @[el2_lib.scala 197:37] - node _T_650 = and(_T_649, _T_559) @[el2_lib.scala 197:42] - node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 197:75] - node _T_652 = bits(_T_552, 13, 13) @[el2_lib.scala 197:87] - node _T_653 = eq(_T_651, _T_652) @[el2_lib.scala 197:79] - node _T_654 = mux(_T_650, UInt<1>("h01"), _T_653) @[el2_lib.scala 197:24] - _T_554[13] <= _T_654 @[el2_lib.scala 197:18] - node _T_655 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 197:29] - node _T_656 = andr(_T_655) @[el2_lib.scala 197:37] - node _T_657 = and(_T_656, _T_559) @[el2_lib.scala 197:42] - node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 197:75] - node _T_659 = bits(_T_552, 14, 14) @[el2_lib.scala 197:87] - node _T_660 = eq(_T_658, _T_659) @[el2_lib.scala 197:79] - node _T_661 = mux(_T_657, UInt<1>("h01"), _T_660) @[el2_lib.scala 197:24] - _T_554[14] <= _T_661 @[el2_lib.scala 197:18] - node _T_662 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 197:29] - node _T_663 = andr(_T_662) @[el2_lib.scala 197:37] - node _T_664 = and(_T_663, _T_559) @[el2_lib.scala 197:42] - node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 197:75] - node _T_666 = bits(_T_552, 15, 15) @[el2_lib.scala 197:87] - node _T_667 = eq(_T_665, _T_666) @[el2_lib.scala 197:79] - node _T_668 = mux(_T_664, UInt<1>("h01"), _T_667) @[el2_lib.scala 197:24] - _T_554[15] <= _T_668 @[el2_lib.scala 197:18] - node _T_669 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 197:29] - node _T_670 = andr(_T_669) @[el2_lib.scala 197:37] - node _T_671 = and(_T_670, _T_559) @[el2_lib.scala 197:42] - node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 197:75] - node _T_673 = bits(_T_552, 16, 16) @[el2_lib.scala 197:87] - node _T_674 = eq(_T_672, _T_673) @[el2_lib.scala 197:79] - node _T_675 = mux(_T_671, UInt<1>("h01"), _T_674) @[el2_lib.scala 197:24] - _T_554[16] <= _T_675 @[el2_lib.scala 197:18] - node _T_676 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 197:29] - node _T_677 = andr(_T_676) @[el2_lib.scala 197:37] - node _T_678 = and(_T_677, _T_559) @[el2_lib.scala 197:42] - node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 197:75] - node _T_680 = bits(_T_552, 17, 17) @[el2_lib.scala 197:87] - node _T_681 = eq(_T_679, _T_680) @[el2_lib.scala 197:79] - node _T_682 = mux(_T_678, UInt<1>("h01"), _T_681) @[el2_lib.scala 197:24] - _T_554[17] <= _T_682 @[el2_lib.scala 197:18] - node _T_683 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 197:29] - node _T_684 = andr(_T_683) @[el2_lib.scala 197:37] - node _T_685 = and(_T_684, _T_559) @[el2_lib.scala 197:42] - node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 197:75] - node _T_687 = bits(_T_552, 18, 18) @[el2_lib.scala 197:87] - node _T_688 = eq(_T_686, _T_687) @[el2_lib.scala 197:79] - node _T_689 = mux(_T_685, UInt<1>("h01"), _T_688) @[el2_lib.scala 197:24] - _T_554[18] <= _T_689 @[el2_lib.scala 197:18] - node _T_690 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 197:29] - node _T_691 = andr(_T_690) @[el2_lib.scala 197:37] - node _T_692 = and(_T_691, _T_559) @[el2_lib.scala 197:42] - node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 197:75] - node _T_694 = bits(_T_552, 19, 19) @[el2_lib.scala 197:87] - node _T_695 = eq(_T_693, _T_694) @[el2_lib.scala 197:79] - node _T_696 = mux(_T_692, UInt<1>("h01"), _T_695) @[el2_lib.scala 197:24] - _T_554[19] <= _T_696 @[el2_lib.scala 197:18] - node _T_697 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 197:29] - node _T_698 = andr(_T_697) @[el2_lib.scala 197:37] - node _T_699 = and(_T_698, _T_559) @[el2_lib.scala 197:42] - node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 197:75] - node _T_701 = bits(_T_552, 20, 20) @[el2_lib.scala 197:87] - node _T_702 = eq(_T_700, _T_701) @[el2_lib.scala 197:79] - node _T_703 = mux(_T_699, UInt<1>("h01"), _T_702) @[el2_lib.scala 197:24] - _T_554[20] <= _T_703 @[el2_lib.scala 197:18] - node _T_704 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 197:29] - node _T_705 = andr(_T_704) @[el2_lib.scala 197:37] - node _T_706 = and(_T_705, _T_559) @[el2_lib.scala 197:42] - node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 197:75] - node _T_708 = bits(_T_552, 21, 21) @[el2_lib.scala 197:87] - node _T_709 = eq(_T_707, _T_708) @[el2_lib.scala 197:79] - node _T_710 = mux(_T_706, UInt<1>("h01"), _T_709) @[el2_lib.scala 197:24] - _T_554[21] <= _T_710 @[el2_lib.scala 197:18] - node _T_711 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 197:29] - node _T_712 = andr(_T_711) @[el2_lib.scala 197:37] - node _T_713 = and(_T_712, _T_559) @[el2_lib.scala 197:42] - node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 197:75] - node _T_715 = bits(_T_552, 22, 22) @[el2_lib.scala 197:87] - node _T_716 = eq(_T_714, _T_715) @[el2_lib.scala 197:79] - node _T_717 = mux(_T_713, UInt<1>("h01"), _T_716) @[el2_lib.scala 197:24] - _T_554[22] <= _T_717 @[el2_lib.scala 197:18] - node _T_718 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 197:29] - node _T_719 = andr(_T_718) @[el2_lib.scala 197:37] - node _T_720 = and(_T_719, _T_559) @[el2_lib.scala 197:42] - node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 197:75] - node _T_722 = bits(_T_552, 23, 23) @[el2_lib.scala 197:87] - node _T_723 = eq(_T_721, _T_722) @[el2_lib.scala 197:79] - node _T_724 = mux(_T_720, UInt<1>("h01"), _T_723) @[el2_lib.scala 197:24] - _T_554[23] <= _T_724 @[el2_lib.scala 197:18] - node _T_725 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 197:29] - node _T_726 = andr(_T_725) @[el2_lib.scala 197:37] - node _T_727 = and(_T_726, _T_559) @[el2_lib.scala 197:42] - node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 197:75] - node _T_729 = bits(_T_552, 24, 24) @[el2_lib.scala 197:87] - node _T_730 = eq(_T_728, _T_729) @[el2_lib.scala 197:79] - node _T_731 = mux(_T_727, UInt<1>("h01"), _T_730) @[el2_lib.scala 197:24] - _T_554[24] <= _T_731 @[el2_lib.scala 197:18] - node _T_732 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 197:29] - node _T_733 = andr(_T_732) @[el2_lib.scala 197:37] - node _T_734 = and(_T_733, _T_559) @[el2_lib.scala 197:42] - node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 197:75] - node _T_736 = bits(_T_552, 25, 25) @[el2_lib.scala 197:87] - node _T_737 = eq(_T_735, _T_736) @[el2_lib.scala 197:79] - node _T_738 = mux(_T_734, UInt<1>("h01"), _T_737) @[el2_lib.scala 197:24] - _T_554[25] <= _T_738 @[el2_lib.scala 197:18] - node _T_739 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 197:29] - node _T_740 = andr(_T_739) @[el2_lib.scala 197:37] - node _T_741 = and(_T_740, _T_559) @[el2_lib.scala 197:42] - node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 197:75] - node _T_743 = bits(_T_552, 26, 26) @[el2_lib.scala 197:87] - node _T_744 = eq(_T_742, _T_743) @[el2_lib.scala 197:79] - node _T_745 = mux(_T_741, UInt<1>("h01"), _T_744) @[el2_lib.scala 197:24] - _T_554[26] <= _T_745 @[el2_lib.scala 197:18] - node _T_746 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 197:29] - node _T_747 = andr(_T_746) @[el2_lib.scala 197:37] - node _T_748 = and(_T_747, _T_559) @[el2_lib.scala 197:42] - node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 197:75] - node _T_750 = bits(_T_552, 27, 27) @[el2_lib.scala 197:87] - node _T_751 = eq(_T_749, _T_750) @[el2_lib.scala 197:79] - node _T_752 = mux(_T_748, UInt<1>("h01"), _T_751) @[el2_lib.scala 197:24] - _T_554[27] <= _T_752 @[el2_lib.scala 197:18] - node _T_753 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 197:29] - node _T_754 = andr(_T_753) @[el2_lib.scala 197:37] - node _T_755 = and(_T_754, _T_559) @[el2_lib.scala 197:42] - node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 197:75] - node _T_757 = bits(_T_552, 28, 28) @[el2_lib.scala 197:87] - node _T_758 = eq(_T_756, _T_757) @[el2_lib.scala 197:79] - node _T_759 = mux(_T_755, UInt<1>("h01"), _T_758) @[el2_lib.scala 197:24] - _T_554[28] <= _T_759 @[el2_lib.scala 197:18] - node _T_760 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 197:29] - node _T_761 = andr(_T_760) @[el2_lib.scala 197:37] - node _T_762 = and(_T_761, _T_559) @[el2_lib.scala 197:42] - node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 197:75] - node _T_764 = bits(_T_552, 29, 29) @[el2_lib.scala 197:87] - node _T_765 = eq(_T_763, _T_764) @[el2_lib.scala 197:79] - node _T_766 = mux(_T_762, UInt<1>("h01"), _T_765) @[el2_lib.scala 197:24] - _T_554[29] <= _T_766 @[el2_lib.scala 197:18] - node _T_767 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 197:29] - node _T_768 = andr(_T_767) @[el2_lib.scala 197:37] - node _T_769 = and(_T_768, _T_559) @[el2_lib.scala 197:42] - node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 197:75] - node _T_771 = bits(_T_552, 30, 30) @[el2_lib.scala 197:87] - node _T_772 = eq(_T_770, _T_771) @[el2_lib.scala 197:79] - node _T_773 = mux(_T_769, UInt<1>("h01"), _T_772) @[el2_lib.scala 197:24] - _T_554[30] <= _T_773 @[el2_lib.scala 197:18] - node _T_774 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 197:29] - node _T_775 = andr(_T_774) @[el2_lib.scala 197:37] - node _T_776 = and(_T_775, _T_559) @[el2_lib.scala 197:42] - node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 197:75] - node _T_778 = bits(_T_552, 31, 31) @[el2_lib.scala 197:87] - node _T_779 = eq(_T_777, _T_778) @[el2_lib.scala 197:79] - node _T_780 = mux(_T_776, UInt<1>("h01"), _T_779) @[el2_lib.scala 197:24] - _T_554[31] <= _T_780 @[el2_lib.scala 197:18] - node _T_781 = cat(_T_554[1], _T_554[0]) @[el2_lib.scala 198:14] - node _T_782 = cat(_T_554[3], _T_554[2]) @[el2_lib.scala 198:14] - node _T_783 = cat(_T_782, _T_781) @[el2_lib.scala 198:14] - node _T_784 = cat(_T_554[5], _T_554[4]) @[el2_lib.scala 198:14] - node _T_785 = cat(_T_554[7], _T_554[6]) @[el2_lib.scala 198:14] - node _T_786 = cat(_T_785, _T_784) @[el2_lib.scala 198:14] - node _T_787 = cat(_T_786, _T_783) @[el2_lib.scala 198:14] - node _T_788 = cat(_T_554[9], _T_554[8]) @[el2_lib.scala 198:14] - node _T_789 = cat(_T_554[11], _T_554[10]) @[el2_lib.scala 198:14] - node _T_790 = cat(_T_789, _T_788) @[el2_lib.scala 198:14] - node _T_791 = cat(_T_554[13], _T_554[12]) @[el2_lib.scala 198:14] - node _T_792 = cat(_T_554[15], _T_554[14]) @[el2_lib.scala 198:14] - node _T_793 = cat(_T_792, _T_791) @[el2_lib.scala 198:14] - node _T_794 = cat(_T_793, _T_790) @[el2_lib.scala 198:14] - node _T_795 = cat(_T_794, _T_787) @[el2_lib.scala 198:14] - node _T_796 = cat(_T_554[17], _T_554[16]) @[el2_lib.scala 198:14] - node _T_797 = cat(_T_554[19], _T_554[18]) @[el2_lib.scala 198:14] - node _T_798 = cat(_T_797, _T_796) @[el2_lib.scala 198:14] - node _T_799 = cat(_T_554[21], _T_554[20]) @[el2_lib.scala 198:14] - node _T_800 = cat(_T_554[23], _T_554[22]) @[el2_lib.scala 198:14] - node _T_801 = cat(_T_800, _T_799) @[el2_lib.scala 198:14] - node _T_802 = cat(_T_801, _T_798) @[el2_lib.scala 198:14] - node _T_803 = cat(_T_554[25], _T_554[24]) @[el2_lib.scala 198:14] - node _T_804 = cat(_T_554[27], _T_554[26]) @[el2_lib.scala 198:14] - node _T_805 = cat(_T_804, _T_803) @[el2_lib.scala 198:14] - node _T_806 = cat(_T_554[29], _T_554[28]) @[el2_lib.scala 198:14] - node _T_807 = cat(_T_554[31], _T_554[30]) @[el2_lib.scala 198:14] - node _T_808 = cat(_T_807, _T_806) @[el2_lib.scala 198:14] - node _T_809 = cat(_T_808, _T_805) @[el2_lib.scala 198:14] - node _T_810 = cat(_T_809, _T_802) @[el2_lib.scala 198:14] - node _T_811 = cat(_T_810, _T_795) @[el2_lib.scala 198:14] - node lsu_trigger_data_match_2 = andr(_T_811) @[el2_lib.scala 198:21] - node _T_812 = bits(io.trigger_pkt_any[3].select, 0, 0) @[el2_lsu_trigger.scala 24:137] - node _T_813 = eq(_T_812, UInt<1>("h00")) @[el2_lsu_trigger.scala 24:107] - node _T_814 = and(io.trigger_pkt_any[3].select, io.trigger_pkt_any[3].store) @[el2_lsu_trigger.scala 25:35] - node _T_815 = bits(_T_814, 0, 0) @[el2_lsu_trigger.scala 25:66] - node _T_816 = mux(_T_813, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_817 = mux(_T_815, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_818 = or(_T_816, _T_817) @[Mux.scala 27:72] - wire _T_819 : UInt<32> @[Mux.scala 27:72] - _T_819 <= _T_818 @[Mux.scala 27:72] - node _T_820 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 25:133] - wire _T_821 : UInt<1>[32] @[el2_lib.scala 193:24] - node _T_822 = bits(_T_820, 0, 0) @[el2_lib.scala 194:37] - node _T_823 = bits(io.trigger_pkt_any[3].tdata2, 31, 0) @[el2_lib.scala 194:53] - node _T_824 = andr(_T_823) @[el2_lib.scala 194:73] - node _T_825 = not(_T_824) @[el2_lib.scala 194:47] - node _T_826 = and(_T_822, _T_825) @[el2_lib.scala 194:44] - node _T_827 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 195:48] - node _T_828 = bits(_T_819, 0, 0) @[el2_lib.scala 195:60] - node _T_829 = eq(_T_827, _T_828) @[el2_lib.scala 195:52] - node _T_830 = or(_T_826, _T_829) @[el2_lib.scala 195:41] - _T_821[0] <= _T_830 @[el2_lib.scala 195:18] - node _T_831 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 197:29] - node _T_832 = andr(_T_831) @[el2_lib.scala 197:37] - node _T_833 = and(_T_832, _T_826) @[el2_lib.scala 197:42] - node _T_834 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 197:75] - node _T_835 = bits(_T_819, 1, 1) @[el2_lib.scala 197:87] - node _T_836 = eq(_T_834, _T_835) @[el2_lib.scala 197:79] - node _T_837 = mux(_T_833, UInt<1>("h01"), _T_836) @[el2_lib.scala 197:24] - _T_821[1] <= _T_837 @[el2_lib.scala 197:18] - node _T_838 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 197:29] - node _T_839 = andr(_T_838) @[el2_lib.scala 197:37] - node _T_840 = and(_T_839, _T_826) @[el2_lib.scala 197:42] - node _T_841 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 197:75] - node _T_842 = bits(_T_819, 2, 2) @[el2_lib.scala 197:87] - node _T_843 = eq(_T_841, _T_842) @[el2_lib.scala 197:79] - node _T_844 = mux(_T_840, UInt<1>("h01"), _T_843) @[el2_lib.scala 197:24] - _T_821[2] <= _T_844 @[el2_lib.scala 197:18] - node _T_845 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 197:29] - node _T_846 = andr(_T_845) @[el2_lib.scala 197:37] - node _T_847 = and(_T_846, _T_826) @[el2_lib.scala 197:42] - node _T_848 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 197:75] - node _T_849 = bits(_T_819, 3, 3) @[el2_lib.scala 197:87] - node _T_850 = eq(_T_848, _T_849) @[el2_lib.scala 197:79] - node _T_851 = mux(_T_847, UInt<1>("h01"), _T_850) @[el2_lib.scala 197:24] - _T_821[3] <= _T_851 @[el2_lib.scala 197:18] - node _T_852 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 197:29] - node _T_853 = andr(_T_852) @[el2_lib.scala 197:37] - node _T_854 = and(_T_853, _T_826) @[el2_lib.scala 197:42] - node _T_855 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 197:75] - node _T_856 = bits(_T_819, 4, 4) @[el2_lib.scala 197:87] - node _T_857 = eq(_T_855, _T_856) @[el2_lib.scala 197:79] - node _T_858 = mux(_T_854, UInt<1>("h01"), _T_857) @[el2_lib.scala 197:24] - _T_821[4] <= _T_858 @[el2_lib.scala 197:18] - node _T_859 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 197:29] - node _T_860 = andr(_T_859) @[el2_lib.scala 197:37] - node _T_861 = and(_T_860, _T_826) @[el2_lib.scala 197:42] - node _T_862 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 197:75] - node _T_863 = bits(_T_819, 5, 5) @[el2_lib.scala 197:87] - node _T_864 = eq(_T_862, _T_863) @[el2_lib.scala 197:79] - node _T_865 = mux(_T_861, UInt<1>("h01"), _T_864) @[el2_lib.scala 197:24] - _T_821[5] <= _T_865 @[el2_lib.scala 197:18] - node _T_866 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 197:29] - node _T_867 = andr(_T_866) @[el2_lib.scala 197:37] - node _T_868 = and(_T_867, _T_826) @[el2_lib.scala 197:42] - node _T_869 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 197:75] - node _T_870 = bits(_T_819, 6, 6) @[el2_lib.scala 197:87] - node _T_871 = eq(_T_869, _T_870) @[el2_lib.scala 197:79] - node _T_872 = mux(_T_868, UInt<1>("h01"), _T_871) @[el2_lib.scala 197:24] - _T_821[6] <= _T_872 @[el2_lib.scala 197:18] - node _T_873 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 197:29] - node _T_874 = andr(_T_873) @[el2_lib.scala 197:37] - node _T_875 = and(_T_874, _T_826) @[el2_lib.scala 197:42] - node _T_876 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 197:75] - node _T_877 = bits(_T_819, 7, 7) @[el2_lib.scala 197:87] - node _T_878 = eq(_T_876, _T_877) @[el2_lib.scala 197:79] - node _T_879 = mux(_T_875, UInt<1>("h01"), _T_878) @[el2_lib.scala 197:24] - _T_821[7] <= _T_879 @[el2_lib.scala 197:18] - node _T_880 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 197:29] - node _T_881 = andr(_T_880) @[el2_lib.scala 197:37] - node _T_882 = and(_T_881, _T_826) @[el2_lib.scala 197:42] - node _T_883 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 197:75] - node _T_884 = bits(_T_819, 8, 8) @[el2_lib.scala 197:87] - node _T_885 = eq(_T_883, _T_884) @[el2_lib.scala 197:79] - node _T_886 = mux(_T_882, UInt<1>("h01"), _T_885) @[el2_lib.scala 197:24] - _T_821[8] <= _T_886 @[el2_lib.scala 197:18] - node _T_887 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 197:29] - node _T_888 = andr(_T_887) @[el2_lib.scala 197:37] - node _T_889 = and(_T_888, _T_826) @[el2_lib.scala 197:42] - node _T_890 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 197:75] - node _T_891 = bits(_T_819, 9, 9) @[el2_lib.scala 197:87] - node _T_892 = eq(_T_890, _T_891) @[el2_lib.scala 197:79] - node _T_893 = mux(_T_889, UInt<1>("h01"), _T_892) @[el2_lib.scala 197:24] - _T_821[9] <= _T_893 @[el2_lib.scala 197:18] - node _T_894 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 197:29] - node _T_895 = andr(_T_894) @[el2_lib.scala 197:37] - node _T_896 = and(_T_895, _T_826) @[el2_lib.scala 197:42] - node _T_897 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 197:75] - node _T_898 = bits(_T_819, 10, 10) @[el2_lib.scala 197:87] - node _T_899 = eq(_T_897, _T_898) @[el2_lib.scala 197:79] - node _T_900 = mux(_T_896, UInt<1>("h01"), _T_899) @[el2_lib.scala 197:24] - _T_821[10] <= _T_900 @[el2_lib.scala 197:18] - node _T_901 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 197:29] - node _T_902 = andr(_T_901) @[el2_lib.scala 197:37] - node _T_903 = and(_T_902, _T_826) @[el2_lib.scala 197:42] - node _T_904 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 197:75] - node _T_905 = bits(_T_819, 11, 11) @[el2_lib.scala 197:87] - node _T_906 = eq(_T_904, _T_905) @[el2_lib.scala 197:79] - node _T_907 = mux(_T_903, UInt<1>("h01"), _T_906) @[el2_lib.scala 197:24] - _T_821[11] <= _T_907 @[el2_lib.scala 197:18] - node _T_908 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 197:29] - node _T_909 = andr(_T_908) @[el2_lib.scala 197:37] - node _T_910 = and(_T_909, _T_826) @[el2_lib.scala 197:42] - node _T_911 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 197:75] - node _T_912 = bits(_T_819, 12, 12) @[el2_lib.scala 197:87] - node _T_913 = eq(_T_911, _T_912) @[el2_lib.scala 197:79] - node _T_914 = mux(_T_910, UInt<1>("h01"), _T_913) @[el2_lib.scala 197:24] - _T_821[12] <= _T_914 @[el2_lib.scala 197:18] - node _T_915 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 197:29] - node _T_916 = andr(_T_915) @[el2_lib.scala 197:37] - node _T_917 = and(_T_916, _T_826) @[el2_lib.scala 197:42] - node _T_918 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 197:75] - node _T_919 = bits(_T_819, 13, 13) @[el2_lib.scala 197:87] - node _T_920 = eq(_T_918, _T_919) @[el2_lib.scala 197:79] - node _T_921 = mux(_T_917, UInt<1>("h01"), _T_920) @[el2_lib.scala 197:24] - _T_821[13] <= _T_921 @[el2_lib.scala 197:18] - node _T_922 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 197:29] - node _T_923 = andr(_T_922) @[el2_lib.scala 197:37] - node _T_924 = and(_T_923, _T_826) @[el2_lib.scala 197:42] - node _T_925 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 197:75] - node _T_926 = bits(_T_819, 14, 14) @[el2_lib.scala 197:87] - node _T_927 = eq(_T_925, _T_926) @[el2_lib.scala 197:79] - node _T_928 = mux(_T_924, UInt<1>("h01"), _T_927) @[el2_lib.scala 197:24] - _T_821[14] <= _T_928 @[el2_lib.scala 197:18] - node _T_929 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 197:29] - node _T_930 = andr(_T_929) @[el2_lib.scala 197:37] - node _T_931 = and(_T_930, _T_826) @[el2_lib.scala 197:42] - node _T_932 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 197:75] - node _T_933 = bits(_T_819, 15, 15) @[el2_lib.scala 197:87] - node _T_934 = eq(_T_932, _T_933) @[el2_lib.scala 197:79] - node _T_935 = mux(_T_931, UInt<1>("h01"), _T_934) @[el2_lib.scala 197:24] - _T_821[15] <= _T_935 @[el2_lib.scala 197:18] - node _T_936 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 197:29] - node _T_937 = andr(_T_936) @[el2_lib.scala 197:37] - node _T_938 = and(_T_937, _T_826) @[el2_lib.scala 197:42] - node _T_939 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 197:75] - node _T_940 = bits(_T_819, 16, 16) @[el2_lib.scala 197:87] - node _T_941 = eq(_T_939, _T_940) @[el2_lib.scala 197:79] - node _T_942 = mux(_T_938, UInt<1>("h01"), _T_941) @[el2_lib.scala 197:24] - _T_821[16] <= _T_942 @[el2_lib.scala 197:18] - node _T_943 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 197:29] - node _T_944 = andr(_T_943) @[el2_lib.scala 197:37] - node _T_945 = and(_T_944, _T_826) @[el2_lib.scala 197:42] - node _T_946 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 197:75] - node _T_947 = bits(_T_819, 17, 17) @[el2_lib.scala 197:87] - node _T_948 = eq(_T_946, _T_947) @[el2_lib.scala 197:79] - node _T_949 = mux(_T_945, UInt<1>("h01"), _T_948) @[el2_lib.scala 197:24] - _T_821[17] <= _T_949 @[el2_lib.scala 197:18] - node _T_950 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 197:29] - node _T_951 = andr(_T_950) @[el2_lib.scala 197:37] - node _T_952 = and(_T_951, _T_826) @[el2_lib.scala 197:42] - node _T_953 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 197:75] - node _T_954 = bits(_T_819, 18, 18) @[el2_lib.scala 197:87] - node _T_955 = eq(_T_953, _T_954) @[el2_lib.scala 197:79] - node _T_956 = mux(_T_952, UInt<1>("h01"), _T_955) @[el2_lib.scala 197:24] - _T_821[18] <= _T_956 @[el2_lib.scala 197:18] - node _T_957 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 197:29] - node _T_958 = andr(_T_957) @[el2_lib.scala 197:37] - node _T_959 = and(_T_958, _T_826) @[el2_lib.scala 197:42] - node _T_960 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 197:75] - node _T_961 = bits(_T_819, 19, 19) @[el2_lib.scala 197:87] - node _T_962 = eq(_T_960, _T_961) @[el2_lib.scala 197:79] - node _T_963 = mux(_T_959, UInt<1>("h01"), _T_962) @[el2_lib.scala 197:24] - _T_821[19] <= _T_963 @[el2_lib.scala 197:18] - node _T_964 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 197:29] - node _T_965 = andr(_T_964) @[el2_lib.scala 197:37] - node _T_966 = and(_T_965, _T_826) @[el2_lib.scala 197:42] - node _T_967 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 197:75] - node _T_968 = bits(_T_819, 20, 20) @[el2_lib.scala 197:87] - node _T_969 = eq(_T_967, _T_968) @[el2_lib.scala 197:79] - node _T_970 = mux(_T_966, UInt<1>("h01"), _T_969) @[el2_lib.scala 197:24] - _T_821[20] <= _T_970 @[el2_lib.scala 197:18] - node _T_971 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 197:29] - node _T_972 = andr(_T_971) @[el2_lib.scala 197:37] - node _T_973 = and(_T_972, _T_826) @[el2_lib.scala 197:42] - node _T_974 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 197:75] - node _T_975 = bits(_T_819, 21, 21) @[el2_lib.scala 197:87] - node _T_976 = eq(_T_974, _T_975) @[el2_lib.scala 197:79] - node _T_977 = mux(_T_973, UInt<1>("h01"), _T_976) @[el2_lib.scala 197:24] - _T_821[21] <= _T_977 @[el2_lib.scala 197:18] - node _T_978 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 197:29] - node _T_979 = andr(_T_978) @[el2_lib.scala 197:37] - node _T_980 = and(_T_979, _T_826) @[el2_lib.scala 197:42] - node _T_981 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 197:75] - node _T_982 = bits(_T_819, 22, 22) @[el2_lib.scala 197:87] - node _T_983 = eq(_T_981, _T_982) @[el2_lib.scala 197:79] - node _T_984 = mux(_T_980, UInt<1>("h01"), _T_983) @[el2_lib.scala 197:24] - _T_821[22] <= _T_984 @[el2_lib.scala 197:18] - node _T_985 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 197:29] - node _T_986 = andr(_T_985) @[el2_lib.scala 197:37] - node _T_987 = and(_T_986, _T_826) @[el2_lib.scala 197:42] - node _T_988 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 197:75] - node _T_989 = bits(_T_819, 23, 23) @[el2_lib.scala 197:87] - node _T_990 = eq(_T_988, _T_989) @[el2_lib.scala 197:79] - node _T_991 = mux(_T_987, UInt<1>("h01"), _T_990) @[el2_lib.scala 197:24] - _T_821[23] <= _T_991 @[el2_lib.scala 197:18] - node _T_992 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 197:29] - node _T_993 = andr(_T_992) @[el2_lib.scala 197:37] - node _T_994 = and(_T_993, _T_826) @[el2_lib.scala 197:42] - node _T_995 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 197:75] - node _T_996 = bits(_T_819, 24, 24) @[el2_lib.scala 197:87] - node _T_997 = eq(_T_995, _T_996) @[el2_lib.scala 197:79] - node _T_998 = mux(_T_994, UInt<1>("h01"), _T_997) @[el2_lib.scala 197:24] - _T_821[24] <= _T_998 @[el2_lib.scala 197:18] - node _T_999 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 197:29] - node _T_1000 = andr(_T_999) @[el2_lib.scala 197:37] - node _T_1001 = and(_T_1000, _T_826) @[el2_lib.scala 197:42] - node _T_1002 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 197:75] - node _T_1003 = bits(_T_819, 25, 25) @[el2_lib.scala 197:87] - node _T_1004 = eq(_T_1002, _T_1003) @[el2_lib.scala 197:79] - node _T_1005 = mux(_T_1001, UInt<1>("h01"), _T_1004) @[el2_lib.scala 197:24] - _T_821[25] <= _T_1005 @[el2_lib.scala 197:18] - node _T_1006 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 197:29] - node _T_1007 = andr(_T_1006) @[el2_lib.scala 197:37] - node _T_1008 = and(_T_1007, _T_826) @[el2_lib.scala 197:42] - node _T_1009 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 197:75] - node _T_1010 = bits(_T_819, 26, 26) @[el2_lib.scala 197:87] - node _T_1011 = eq(_T_1009, _T_1010) @[el2_lib.scala 197:79] - node _T_1012 = mux(_T_1008, UInt<1>("h01"), _T_1011) @[el2_lib.scala 197:24] - _T_821[26] <= _T_1012 @[el2_lib.scala 197:18] - node _T_1013 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 197:29] - node _T_1014 = andr(_T_1013) @[el2_lib.scala 197:37] - node _T_1015 = and(_T_1014, _T_826) @[el2_lib.scala 197:42] - node _T_1016 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 197:75] - node _T_1017 = bits(_T_819, 27, 27) @[el2_lib.scala 197:87] - node _T_1018 = eq(_T_1016, _T_1017) @[el2_lib.scala 197:79] - node _T_1019 = mux(_T_1015, UInt<1>("h01"), _T_1018) @[el2_lib.scala 197:24] - _T_821[27] <= _T_1019 @[el2_lib.scala 197:18] - node _T_1020 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 197:29] - node _T_1021 = andr(_T_1020) @[el2_lib.scala 197:37] - node _T_1022 = and(_T_1021, _T_826) @[el2_lib.scala 197:42] - node _T_1023 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 197:75] - node _T_1024 = bits(_T_819, 28, 28) @[el2_lib.scala 197:87] - node _T_1025 = eq(_T_1023, _T_1024) @[el2_lib.scala 197:79] - node _T_1026 = mux(_T_1022, UInt<1>("h01"), _T_1025) @[el2_lib.scala 197:24] - _T_821[28] <= _T_1026 @[el2_lib.scala 197:18] - node _T_1027 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 197:29] - node _T_1028 = andr(_T_1027) @[el2_lib.scala 197:37] - node _T_1029 = and(_T_1028, _T_826) @[el2_lib.scala 197:42] - node _T_1030 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 197:75] - node _T_1031 = bits(_T_819, 29, 29) @[el2_lib.scala 197:87] - node _T_1032 = eq(_T_1030, _T_1031) @[el2_lib.scala 197:79] - node _T_1033 = mux(_T_1029, UInt<1>("h01"), _T_1032) @[el2_lib.scala 197:24] - _T_821[29] <= _T_1033 @[el2_lib.scala 197:18] - node _T_1034 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 197:29] - node _T_1035 = andr(_T_1034) @[el2_lib.scala 197:37] - node _T_1036 = and(_T_1035, _T_826) @[el2_lib.scala 197:42] - node _T_1037 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 197:75] - node _T_1038 = bits(_T_819, 30, 30) @[el2_lib.scala 197:87] - node _T_1039 = eq(_T_1037, _T_1038) @[el2_lib.scala 197:79] - node _T_1040 = mux(_T_1036, UInt<1>("h01"), _T_1039) @[el2_lib.scala 197:24] - _T_821[30] <= _T_1040 @[el2_lib.scala 197:18] - node _T_1041 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 197:29] - node _T_1042 = andr(_T_1041) @[el2_lib.scala 197:37] - node _T_1043 = and(_T_1042, _T_826) @[el2_lib.scala 197:42] - node _T_1044 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 197:75] - node _T_1045 = bits(_T_819, 31, 31) @[el2_lib.scala 197:87] - node _T_1046 = eq(_T_1044, _T_1045) @[el2_lib.scala 197:79] - node _T_1047 = mux(_T_1043, UInt<1>("h01"), _T_1046) @[el2_lib.scala 197:24] - _T_821[31] <= _T_1047 @[el2_lib.scala 197:18] - node _T_1048 = cat(_T_821[1], _T_821[0]) @[el2_lib.scala 198:14] - node _T_1049 = cat(_T_821[3], _T_821[2]) @[el2_lib.scala 198:14] - node _T_1050 = cat(_T_1049, _T_1048) @[el2_lib.scala 198:14] - node _T_1051 = cat(_T_821[5], _T_821[4]) @[el2_lib.scala 198:14] - node _T_1052 = cat(_T_821[7], _T_821[6]) @[el2_lib.scala 198:14] - node _T_1053 = cat(_T_1052, _T_1051) @[el2_lib.scala 198:14] - node _T_1054 = cat(_T_1053, _T_1050) @[el2_lib.scala 198:14] - node _T_1055 = cat(_T_821[9], _T_821[8]) @[el2_lib.scala 198:14] - node _T_1056 = cat(_T_821[11], _T_821[10]) @[el2_lib.scala 198:14] - node _T_1057 = cat(_T_1056, _T_1055) @[el2_lib.scala 198:14] - node _T_1058 = cat(_T_821[13], _T_821[12]) @[el2_lib.scala 198:14] - node _T_1059 = cat(_T_821[15], _T_821[14]) @[el2_lib.scala 198:14] - node _T_1060 = cat(_T_1059, _T_1058) @[el2_lib.scala 198:14] - node _T_1061 = cat(_T_1060, _T_1057) @[el2_lib.scala 198:14] - node _T_1062 = cat(_T_1061, _T_1054) @[el2_lib.scala 198:14] - node _T_1063 = cat(_T_821[17], _T_821[16]) @[el2_lib.scala 198:14] - node _T_1064 = cat(_T_821[19], _T_821[18]) @[el2_lib.scala 198:14] - node _T_1065 = cat(_T_1064, _T_1063) @[el2_lib.scala 198:14] - node _T_1066 = cat(_T_821[21], _T_821[20]) @[el2_lib.scala 198:14] - node _T_1067 = cat(_T_821[23], _T_821[22]) @[el2_lib.scala 198:14] - node _T_1068 = cat(_T_1067, _T_1066) @[el2_lib.scala 198:14] - node _T_1069 = cat(_T_1068, _T_1065) @[el2_lib.scala 198:14] - node _T_1070 = cat(_T_821[25], _T_821[24]) @[el2_lib.scala 198:14] - node _T_1071 = cat(_T_821[27], _T_821[26]) @[el2_lib.scala 198:14] - node _T_1072 = cat(_T_1071, _T_1070) @[el2_lib.scala 198:14] - node _T_1073 = cat(_T_821[29], _T_821[28]) @[el2_lib.scala 198:14] - node _T_1074 = cat(_T_821[31], _T_821[30]) @[el2_lib.scala 198:14] - node _T_1075 = cat(_T_1074, _T_1073) @[el2_lib.scala 198:14] - node _T_1076 = cat(_T_1075, _T_1072) @[el2_lib.scala 198:14] - node _T_1077 = cat(_T_1076, _T_1069) @[el2_lib.scala 198:14] - node _T_1078 = cat(_T_1077, _T_1062) @[el2_lib.scala 198:14] - node lsu_trigger_data_match_3 = andr(_T_1078) @[el2_lib.scala 198:21] - node _T_1079 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 26:74] - node _T_1080 = and(io.lsu_pkt_m.valid, _T_1079) @[el2_lsu_trigger.scala 26:72] - node _T_1081 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 26:123] - node _T_1082 = and(_T_1080, _T_1081) @[el2_lsu_trigger.scala 26:92] - node _T_1083 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 27:33] - node _T_1084 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 27:55] - node _T_1085 = and(_T_1083, _T_1084) @[el2_lsu_trigger.scala 27:53] - node _T_1086 = and(_T_1085, lsu_trigger_data_match_0) @[el2_lsu_trigger.scala 27:85] - node _T_1087 = or(_T_1082, _T_1086) @[el2_lsu_trigger.scala 26:144] - node _T_1088 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 26:74] - node _T_1089 = and(io.lsu_pkt_m.valid, _T_1088) @[el2_lsu_trigger.scala 26:72] - node _T_1090 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 26:123] - node _T_1091 = and(_T_1089, _T_1090) @[el2_lsu_trigger.scala 26:92] - node _T_1092 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 27:33] - node _T_1093 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 27:55] - node _T_1094 = and(_T_1092, _T_1093) @[el2_lsu_trigger.scala 27:53] - node _T_1095 = and(_T_1094, lsu_trigger_data_match_1) @[el2_lsu_trigger.scala 27:85] - node _T_1096 = or(_T_1091, _T_1095) @[el2_lsu_trigger.scala 26:144] - node _T_1097 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 26:74] - node _T_1098 = and(io.lsu_pkt_m.valid, _T_1097) @[el2_lsu_trigger.scala 26:72] - node _T_1099 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 26:123] - node _T_1100 = and(_T_1098, _T_1099) @[el2_lsu_trigger.scala 26:92] - node _T_1101 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 27:33] - node _T_1102 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 27:55] - node _T_1103 = and(_T_1101, _T_1102) @[el2_lsu_trigger.scala 27:53] - node _T_1104 = and(_T_1103, lsu_trigger_data_match_2) @[el2_lsu_trigger.scala 27:85] - node _T_1105 = or(_T_1100, _T_1104) @[el2_lsu_trigger.scala 26:144] - node _T_1106 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 26:74] - node _T_1107 = and(io.lsu_pkt_m.valid, _T_1106) @[el2_lsu_trigger.scala 26:72] - node _T_1108 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 26:123] - node _T_1109 = and(_T_1107, _T_1108) @[el2_lsu_trigger.scala 26:92] - node _T_1110 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 27:33] - node _T_1111 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 27:55] - node _T_1112 = and(_T_1110, _T_1111) @[el2_lsu_trigger.scala 27:53] - node _T_1113 = and(_T_1112, lsu_trigger_data_match_3) @[el2_lsu_trigger.scala 27:85] - node _T_1114 = or(_T_1109, _T_1113) @[el2_lsu_trigger.scala 26:144] - wire _T_1115 : UInt<1>[4] @[el2_lsu_trigger.scala 26:48] - _T_1115[0] <= _T_1087 @[el2_lsu_trigger.scala 26:48] - _T_1115[1] <= _T_1096 @[el2_lsu_trigger.scala 26:48] - _T_1115[2] <= _T_1105 @[el2_lsu_trigger.scala 26:48] - _T_1115[3] <= _T_1114 @[el2_lsu_trigger.scala 26:48] - node _T_1116 = cat(_T_1115[3], _T_1115[2]) @[Cat.scala 29:58] - node _T_1117 = cat(_T_1116, _T_1115[1]) @[Cat.scala 29:58] - node _T_1118 = cat(_T_1117, _T_1115[0]) @[Cat.scala 29:58] - io.lsu_trigger_match_m <= _T_1118 @[el2_lsu_trigger.scala 26:26] + wire lsu_match_data_0 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_0 <= _T_17 @[Mux.scala 27:72] + node _T_18 = bits(io.trigger_pkt_any[1].select, 0, 0) @[el2_lsu_trigger.scala 17:83] + node _T_19 = eq(_T_18, UInt<1>("h00")) @[el2_lsu_trigger.scala 17:53] + node _T_20 = and(io.trigger_pkt_any[1].select, io.trigger_pkt_any[1].store) @[el2_lsu_trigger.scala 17:136] + node _T_21 = bits(_T_20, 0, 0) @[el2_lsu_trigger.scala 17:167] + node _T_22 = mux(_T_19, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_23 = mux(_T_21, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_24 = or(_T_22, _T_23) @[Mux.scala 27:72] + wire lsu_match_data_1 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_1 <= _T_24 @[Mux.scala 27:72] + node _T_25 = bits(io.trigger_pkt_any[2].select, 0, 0) @[el2_lsu_trigger.scala 17:83] + node _T_26 = eq(_T_25, UInt<1>("h00")) @[el2_lsu_trigger.scala 17:53] + node _T_27 = and(io.trigger_pkt_any[2].select, io.trigger_pkt_any[2].store) @[el2_lsu_trigger.scala 17:136] + node _T_28 = bits(_T_27, 0, 0) @[el2_lsu_trigger.scala 17:167] + node _T_29 = mux(_T_26, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_30 = mux(_T_28, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_31 = or(_T_29, _T_30) @[Mux.scala 27:72] + wire lsu_match_data_2 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_2 <= _T_31 @[Mux.scala 27:72] + node _T_32 = bits(io.trigger_pkt_any[3].select, 0, 0) @[el2_lsu_trigger.scala 17:83] + node _T_33 = eq(_T_32, UInt<1>("h00")) @[el2_lsu_trigger.scala 17:53] + node _T_34 = and(io.trigger_pkt_any[3].select, io.trigger_pkt_any[3].store) @[el2_lsu_trigger.scala 17:136] + node _T_35 = bits(_T_34, 0, 0) @[el2_lsu_trigger.scala 17:167] + node _T_36 = mux(_T_33, io.lsu_addr_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_37 = mux(_T_35, store_data_trigger_m, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_38 = or(_T_36, _T_37) @[Mux.scala 27:72] + wire lsu_match_data_3 : UInt<32> @[Mux.scala 27:72] + lsu_match_data_3 <= _T_38 @[Mux.scala 27:72] + node _T_39 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_40 = and(io.lsu_pkt_m.valid, _T_39) @[el2_lsu_trigger.scala 18:69] + node _T_41 = and(io.trigger_pkt_any[0].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] + node _T_42 = and(io.trigger_pkt_any[0].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] + node _T_43 = eq(io.trigger_pkt_any[0].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] + node _T_44 = and(_T_42, _T_43) @[el2_lsu_trigger.scala 19:53] + node _T_45 = or(_T_41, _T_44) @[el2_lsu_trigger.scala 18:142] + node _T_46 = and(_T_40, _T_45) @[el2_lsu_trigger.scala 18:89] + node _T_47 = bits(io.trigger_pkt_any[0].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + wire _T_48 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_49 = andr(io.trigger_pkt_any[0].tdata2) @[el2_lib.scala 241:45] + node _T_50 = not(_T_49) @[el2_lib.scala 241:39] + node _T_51 = and(_T_47, _T_50) @[el2_lib.scala 241:37] + node _T_52 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_53 = bits(lsu_match_data_0, 0, 0) @[el2_lib.scala 242:60] + node _T_54 = eq(_T_52, _T_53) @[el2_lib.scala 242:52] + node _T_55 = or(_T_51, _T_54) @[el2_lib.scala 242:41] + _T_48[0] <= _T_55 @[el2_lib.scala 242:18] + node _T_56 = bits(io.trigger_pkt_any[0].tdata2, 0, 0) @[el2_lib.scala 244:30] + node _T_57 = andr(_T_56) @[el2_lib.scala 244:38] + node _T_58 = and(_T_57, _T_51) @[el2_lib.scala 244:43] + node _T_59 = bits(io.trigger_pkt_any[0].tdata2, 1, 1) @[el2_lib.scala 244:76] + node _T_60 = bits(lsu_match_data_0, 1, 1) @[el2_lib.scala 244:88] + node _T_61 = eq(_T_59, _T_60) @[el2_lib.scala 244:80] + node _T_62 = mux(_T_58, UInt<1>("h01"), _T_61) @[el2_lib.scala 244:25] + _T_48[1] <= _T_62 @[el2_lib.scala 244:19] + node _T_63 = bits(io.trigger_pkt_any[0].tdata2, 1, 0) @[el2_lib.scala 244:30] + node _T_64 = andr(_T_63) @[el2_lib.scala 244:38] + node _T_65 = and(_T_64, _T_51) @[el2_lib.scala 244:43] + node _T_66 = bits(io.trigger_pkt_any[0].tdata2, 2, 2) @[el2_lib.scala 244:76] + node _T_67 = bits(lsu_match_data_0, 2, 2) @[el2_lib.scala 244:88] + node _T_68 = eq(_T_66, _T_67) @[el2_lib.scala 244:80] + node _T_69 = mux(_T_65, UInt<1>("h01"), _T_68) @[el2_lib.scala 244:25] + _T_48[2] <= _T_69 @[el2_lib.scala 244:19] + node _T_70 = bits(io.trigger_pkt_any[0].tdata2, 2, 0) @[el2_lib.scala 244:30] + node _T_71 = andr(_T_70) @[el2_lib.scala 244:38] + node _T_72 = and(_T_71, _T_51) @[el2_lib.scala 244:43] + node _T_73 = bits(io.trigger_pkt_any[0].tdata2, 3, 3) @[el2_lib.scala 244:76] + node _T_74 = bits(lsu_match_data_0, 3, 3) @[el2_lib.scala 244:88] + node _T_75 = eq(_T_73, _T_74) @[el2_lib.scala 244:80] + node _T_76 = mux(_T_72, UInt<1>("h01"), _T_75) @[el2_lib.scala 244:25] + _T_48[3] <= _T_76 @[el2_lib.scala 244:19] + node _T_77 = bits(io.trigger_pkt_any[0].tdata2, 3, 0) @[el2_lib.scala 244:30] + node _T_78 = andr(_T_77) @[el2_lib.scala 244:38] + node _T_79 = and(_T_78, _T_51) @[el2_lib.scala 244:43] + node _T_80 = bits(io.trigger_pkt_any[0].tdata2, 4, 4) @[el2_lib.scala 244:76] + node _T_81 = bits(lsu_match_data_0, 4, 4) @[el2_lib.scala 244:88] + node _T_82 = eq(_T_80, _T_81) @[el2_lib.scala 244:80] + node _T_83 = mux(_T_79, UInt<1>("h01"), _T_82) @[el2_lib.scala 244:25] + _T_48[4] <= _T_83 @[el2_lib.scala 244:19] + node _T_84 = bits(io.trigger_pkt_any[0].tdata2, 4, 0) @[el2_lib.scala 244:30] + node _T_85 = andr(_T_84) @[el2_lib.scala 244:38] + node _T_86 = and(_T_85, _T_51) @[el2_lib.scala 244:43] + node _T_87 = bits(io.trigger_pkt_any[0].tdata2, 5, 5) @[el2_lib.scala 244:76] + node _T_88 = bits(lsu_match_data_0, 5, 5) @[el2_lib.scala 244:88] + node _T_89 = eq(_T_87, _T_88) @[el2_lib.scala 244:80] + node _T_90 = mux(_T_86, UInt<1>("h01"), _T_89) @[el2_lib.scala 244:25] + _T_48[5] <= _T_90 @[el2_lib.scala 244:19] + node _T_91 = bits(io.trigger_pkt_any[0].tdata2, 5, 0) @[el2_lib.scala 244:30] + node _T_92 = andr(_T_91) @[el2_lib.scala 244:38] + node _T_93 = and(_T_92, _T_51) @[el2_lib.scala 244:43] + node _T_94 = bits(io.trigger_pkt_any[0].tdata2, 6, 6) @[el2_lib.scala 244:76] + node _T_95 = bits(lsu_match_data_0, 6, 6) @[el2_lib.scala 244:88] + node _T_96 = eq(_T_94, _T_95) @[el2_lib.scala 244:80] + node _T_97 = mux(_T_93, UInt<1>("h01"), _T_96) @[el2_lib.scala 244:25] + _T_48[6] <= _T_97 @[el2_lib.scala 244:19] + node _T_98 = bits(io.trigger_pkt_any[0].tdata2, 6, 0) @[el2_lib.scala 244:30] + node _T_99 = andr(_T_98) @[el2_lib.scala 244:38] + node _T_100 = and(_T_99, _T_51) @[el2_lib.scala 244:43] + node _T_101 = bits(io.trigger_pkt_any[0].tdata2, 7, 7) @[el2_lib.scala 244:76] + node _T_102 = bits(lsu_match_data_0, 7, 7) @[el2_lib.scala 244:88] + node _T_103 = eq(_T_101, _T_102) @[el2_lib.scala 244:80] + node _T_104 = mux(_T_100, UInt<1>("h01"), _T_103) @[el2_lib.scala 244:25] + _T_48[7] <= _T_104 @[el2_lib.scala 244:19] + node _T_105 = bits(io.trigger_pkt_any[0].tdata2, 7, 0) @[el2_lib.scala 244:30] + node _T_106 = andr(_T_105) @[el2_lib.scala 244:38] + node _T_107 = and(_T_106, _T_51) @[el2_lib.scala 244:43] + node _T_108 = bits(io.trigger_pkt_any[0].tdata2, 8, 8) @[el2_lib.scala 244:76] + node _T_109 = bits(lsu_match_data_0, 8, 8) @[el2_lib.scala 244:88] + node _T_110 = eq(_T_108, _T_109) @[el2_lib.scala 244:80] + node _T_111 = mux(_T_107, UInt<1>("h01"), _T_110) @[el2_lib.scala 244:25] + _T_48[8] <= _T_111 @[el2_lib.scala 244:19] + node _T_112 = bits(io.trigger_pkt_any[0].tdata2, 8, 0) @[el2_lib.scala 244:30] + node _T_113 = andr(_T_112) @[el2_lib.scala 244:38] + node _T_114 = and(_T_113, _T_51) @[el2_lib.scala 244:43] + node _T_115 = bits(io.trigger_pkt_any[0].tdata2, 9, 9) @[el2_lib.scala 244:76] + node _T_116 = bits(lsu_match_data_0, 9, 9) @[el2_lib.scala 244:88] + node _T_117 = eq(_T_115, _T_116) @[el2_lib.scala 244:80] + node _T_118 = mux(_T_114, UInt<1>("h01"), _T_117) @[el2_lib.scala 244:25] + _T_48[9] <= _T_118 @[el2_lib.scala 244:19] + node _T_119 = bits(io.trigger_pkt_any[0].tdata2, 9, 0) @[el2_lib.scala 244:30] + node _T_120 = andr(_T_119) @[el2_lib.scala 244:38] + node _T_121 = and(_T_120, _T_51) @[el2_lib.scala 244:43] + node _T_122 = bits(io.trigger_pkt_any[0].tdata2, 10, 10) @[el2_lib.scala 244:76] + node _T_123 = bits(lsu_match_data_0, 10, 10) @[el2_lib.scala 244:88] + node _T_124 = eq(_T_122, _T_123) @[el2_lib.scala 244:80] + node _T_125 = mux(_T_121, UInt<1>("h01"), _T_124) @[el2_lib.scala 244:25] + _T_48[10] <= _T_125 @[el2_lib.scala 244:19] + node _T_126 = bits(io.trigger_pkt_any[0].tdata2, 10, 0) @[el2_lib.scala 244:30] + node _T_127 = andr(_T_126) @[el2_lib.scala 244:38] + node _T_128 = and(_T_127, _T_51) @[el2_lib.scala 244:43] + node _T_129 = bits(io.trigger_pkt_any[0].tdata2, 11, 11) @[el2_lib.scala 244:76] + node _T_130 = bits(lsu_match_data_0, 11, 11) @[el2_lib.scala 244:88] + node _T_131 = eq(_T_129, _T_130) @[el2_lib.scala 244:80] + node _T_132 = mux(_T_128, UInt<1>("h01"), _T_131) @[el2_lib.scala 244:25] + _T_48[11] <= _T_132 @[el2_lib.scala 244:19] + node _T_133 = bits(io.trigger_pkt_any[0].tdata2, 11, 0) @[el2_lib.scala 244:30] + node _T_134 = andr(_T_133) @[el2_lib.scala 244:38] + node _T_135 = and(_T_134, _T_51) @[el2_lib.scala 244:43] + node _T_136 = bits(io.trigger_pkt_any[0].tdata2, 12, 12) @[el2_lib.scala 244:76] + node _T_137 = bits(lsu_match_data_0, 12, 12) @[el2_lib.scala 244:88] + node _T_138 = eq(_T_136, _T_137) @[el2_lib.scala 244:80] + node _T_139 = mux(_T_135, UInt<1>("h01"), _T_138) @[el2_lib.scala 244:25] + _T_48[12] <= _T_139 @[el2_lib.scala 244:19] + node _T_140 = bits(io.trigger_pkt_any[0].tdata2, 12, 0) @[el2_lib.scala 244:30] + node _T_141 = andr(_T_140) @[el2_lib.scala 244:38] + node _T_142 = and(_T_141, _T_51) @[el2_lib.scala 244:43] + node _T_143 = bits(io.trigger_pkt_any[0].tdata2, 13, 13) @[el2_lib.scala 244:76] + node _T_144 = bits(lsu_match_data_0, 13, 13) @[el2_lib.scala 244:88] + node _T_145 = eq(_T_143, _T_144) @[el2_lib.scala 244:80] + node _T_146 = mux(_T_142, UInt<1>("h01"), _T_145) @[el2_lib.scala 244:25] + _T_48[13] <= _T_146 @[el2_lib.scala 244:19] + node _T_147 = bits(io.trigger_pkt_any[0].tdata2, 13, 0) @[el2_lib.scala 244:30] + node _T_148 = andr(_T_147) @[el2_lib.scala 244:38] + node _T_149 = and(_T_148, _T_51) @[el2_lib.scala 244:43] + node _T_150 = bits(io.trigger_pkt_any[0].tdata2, 14, 14) @[el2_lib.scala 244:76] + node _T_151 = bits(lsu_match_data_0, 14, 14) @[el2_lib.scala 244:88] + node _T_152 = eq(_T_150, _T_151) @[el2_lib.scala 244:80] + node _T_153 = mux(_T_149, UInt<1>("h01"), _T_152) @[el2_lib.scala 244:25] + _T_48[14] <= _T_153 @[el2_lib.scala 244:19] + node _T_154 = bits(io.trigger_pkt_any[0].tdata2, 14, 0) @[el2_lib.scala 244:30] + node _T_155 = andr(_T_154) @[el2_lib.scala 244:38] + node _T_156 = and(_T_155, _T_51) @[el2_lib.scala 244:43] + node _T_157 = bits(io.trigger_pkt_any[0].tdata2, 15, 15) @[el2_lib.scala 244:76] + node _T_158 = bits(lsu_match_data_0, 15, 15) @[el2_lib.scala 244:88] + node _T_159 = eq(_T_157, _T_158) @[el2_lib.scala 244:80] + node _T_160 = mux(_T_156, UInt<1>("h01"), _T_159) @[el2_lib.scala 244:25] + _T_48[15] <= _T_160 @[el2_lib.scala 244:19] + node _T_161 = bits(io.trigger_pkt_any[0].tdata2, 15, 0) @[el2_lib.scala 244:30] + node _T_162 = andr(_T_161) @[el2_lib.scala 244:38] + node _T_163 = and(_T_162, _T_51) @[el2_lib.scala 244:43] + node _T_164 = bits(io.trigger_pkt_any[0].tdata2, 16, 16) @[el2_lib.scala 244:76] + node _T_165 = bits(lsu_match_data_0, 16, 16) @[el2_lib.scala 244:88] + node _T_166 = eq(_T_164, _T_165) @[el2_lib.scala 244:80] + node _T_167 = mux(_T_163, UInt<1>("h01"), _T_166) @[el2_lib.scala 244:25] + _T_48[16] <= _T_167 @[el2_lib.scala 244:19] + node _T_168 = bits(io.trigger_pkt_any[0].tdata2, 16, 0) @[el2_lib.scala 244:30] + node _T_169 = andr(_T_168) @[el2_lib.scala 244:38] + node _T_170 = and(_T_169, _T_51) @[el2_lib.scala 244:43] + node _T_171 = bits(io.trigger_pkt_any[0].tdata2, 17, 17) @[el2_lib.scala 244:76] + node _T_172 = bits(lsu_match_data_0, 17, 17) @[el2_lib.scala 244:88] + node _T_173 = eq(_T_171, _T_172) @[el2_lib.scala 244:80] + node _T_174 = mux(_T_170, UInt<1>("h01"), _T_173) @[el2_lib.scala 244:25] + _T_48[17] <= _T_174 @[el2_lib.scala 244:19] + node _T_175 = bits(io.trigger_pkt_any[0].tdata2, 17, 0) @[el2_lib.scala 244:30] + node _T_176 = andr(_T_175) @[el2_lib.scala 244:38] + node _T_177 = and(_T_176, _T_51) @[el2_lib.scala 244:43] + node _T_178 = bits(io.trigger_pkt_any[0].tdata2, 18, 18) @[el2_lib.scala 244:76] + node _T_179 = bits(lsu_match_data_0, 18, 18) @[el2_lib.scala 244:88] + node _T_180 = eq(_T_178, _T_179) @[el2_lib.scala 244:80] + node _T_181 = mux(_T_177, UInt<1>("h01"), _T_180) @[el2_lib.scala 244:25] + _T_48[18] <= _T_181 @[el2_lib.scala 244:19] + node _T_182 = bits(io.trigger_pkt_any[0].tdata2, 18, 0) @[el2_lib.scala 244:30] + node _T_183 = andr(_T_182) @[el2_lib.scala 244:38] + node _T_184 = and(_T_183, _T_51) @[el2_lib.scala 244:43] + node _T_185 = bits(io.trigger_pkt_any[0].tdata2, 19, 19) @[el2_lib.scala 244:76] + node _T_186 = bits(lsu_match_data_0, 19, 19) @[el2_lib.scala 244:88] + node _T_187 = eq(_T_185, _T_186) @[el2_lib.scala 244:80] + node _T_188 = mux(_T_184, UInt<1>("h01"), _T_187) @[el2_lib.scala 244:25] + _T_48[19] <= _T_188 @[el2_lib.scala 244:19] + node _T_189 = bits(io.trigger_pkt_any[0].tdata2, 19, 0) @[el2_lib.scala 244:30] + node _T_190 = andr(_T_189) @[el2_lib.scala 244:38] + node _T_191 = and(_T_190, _T_51) @[el2_lib.scala 244:43] + node _T_192 = bits(io.trigger_pkt_any[0].tdata2, 20, 20) @[el2_lib.scala 244:76] + node _T_193 = bits(lsu_match_data_0, 20, 20) @[el2_lib.scala 244:88] + node _T_194 = eq(_T_192, _T_193) @[el2_lib.scala 244:80] + node _T_195 = mux(_T_191, UInt<1>("h01"), _T_194) @[el2_lib.scala 244:25] + _T_48[20] <= _T_195 @[el2_lib.scala 244:19] + node _T_196 = bits(io.trigger_pkt_any[0].tdata2, 20, 0) @[el2_lib.scala 244:30] + node _T_197 = andr(_T_196) @[el2_lib.scala 244:38] + node _T_198 = and(_T_197, _T_51) @[el2_lib.scala 244:43] + node _T_199 = bits(io.trigger_pkt_any[0].tdata2, 21, 21) @[el2_lib.scala 244:76] + node _T_200 = bits(lsu_match_data_0, 21, 21) @[el2_lib.scala 244:88] + node _T_201 = eq(_T_199, _T_200) @[el2_lib.scala 244:80] + node _T_202 = mux(_T_198, UInt<1>("h01"), _T_201) @[el2_lib.scala 244:25] + _T_48[21] <= _T_202 @[el2_lib.scala 244:19] + node _T_203 = bits(io.trigger_pkt_any[0].tdata2, 21, 0) @[el2_lib.scala 244:30] + node _T_204 = andr(_T_203) @[el2_lib.scala 244:38] + node _T_205 = and(_T_204, _T_51) @[el2_lib.scala 244:43] + node _T_206 = bits(io.trigger_pkt_any[0].tdata2, 22, 22) @[el2_lib.scala 244:76] + node _T_207 = bits(lsu_match_data_0, 22, 22) @[el2_lib.scala 244:88] + node _T_208 = eq(_T_206, _T_207) @[el2_lib.scala 244:80] + node _T_209 = mux(_T_205, UInt<1>("h01"), _T_208) @[el2_lib.scala 244:25] + _T_48[22] <= _T_209 @[el2_lib.scala 244:19] + node _T_210 = bits(io.trigger_pkt_any[0].tdata2, 22, 0) @[el2_lib.scala 244:30] + node _T_211 = andr(_T_210) @[el2_lib.scala 244:38] + node _T_212 = and(_T_211, _T_51) @[el2_lib.scala 244:43] + node _T_213 = bits(io.trigger_pkt_any[0].tdata2, 23, 23) @[el2_lib.scala 244:76] + node _T_214 = bits(lsu_match_data_0, 23, 23) @[el2_lib.scala 244:88] + node _T_215 = eq(_T_213, _T_214) @[el2_lib.scala 244:80] + node _T_216 = mux(_T_212, UInt<1>("h01"), _T_215) @[el2_lib.scala 244:25] + _T_48[23] <= _T_216 @[el2_lib.scala 244:19] + node _T_217 = bits(io.trigger_pkt_any[0].tdata2, 23, 0) @[el2_lib.scala 244:30] + node _T_218 = andr(_T_217) @[el2_lib.scala 244:38] + node _T_219 = and(_T_218, _T_51) @[el2_lib.scala 244:43] + node _T_220 = bits(io.trigger_pkt_any[0].tdata2, 24, 24) @[el2_lib.scala 244:76] + node _T_221 = bits(lsu_match_data_0, 24, 24) @[el2_lib.scala 244:88] + node _T_222 = eq(_T_220, _T_221) @[el2_lib.scala 244:80] + node _T_223 = mux(_T_219, UInt<1>("h01"), _T_222) @[el2_lib.scala 244:25] + _T_48[24] <= _T_223 @[el2_lib.scala 244:19] + node _T_224 = bits(io.trigger_pkt_any[0].tdata2, 24, 0) @[el2_lib.scala 244:30] + node _T_225 = andr(_T_224) @[el2_lib.scala 244:38] + node _T_226 = and(_T_225, _T_51) @[el2_lib.scala 244:43] + node _T_227 = bits(io.trigger_pkt_any[0].tdata2, 25, 25) @[el2_lib.scala 244:76] + node _T_228 = bits(lsu_match_data_0, 25, 25) @[el2_lib.scala 244:88] + node _T_229 = eq(_T_227, _T_228) @[el2_lib.scala 244:80] + node _T_230 = mux(_T_226, UInt<1>("h01"), _T_229) @[el2_lib.scala 244:25] + _T_48[25] <= _T_230 @[el2_lib.scala 244:19] + node _T_231 = bits(io.trigger_pkt_any[0].tdata2, 25, 0) @[el2_lib.scala 244:30] + node _T_232 = andr(_T_231) @[el2_lib.scala 244:38] + node _T_233 = and(_T_232, _T_51) @[el2_lib.scala 244:43] + node _T_234 = bits(io.trigger_pkt_any[0].tdata2, 26, 26) @[el2_lib.scala 244:76] + node _T_235 = bits(lsu_match_data_0, 26, 26) @[el2_lib.scala 244:88] + node _T_236 = eq(_T_234, _T_235) @[el2_lib.scala 244:80] + node _T_237 = mux(_T_233, UInt<1>("h01"), _T_236) @[el2_lib.scala 244:25] + _T_48[26] <= _T_237 @[el2_lib.scala 244:19] + node _T_238 = bits(io.trigger_pkt_any[0].tdata2, 26, 0) @[el2_lib.scala 244:30] + node _T_239 = andr(_T_238) @[el2_lib.scala 244:38] + node _T_240 = and(_T_239, _T_51) @[el2_lib.scala 244:43] + node _T_241 = bits(io.trigger_pkt_any[0].tdata2, 27, 27) @[el2_lib.scala 244:76] + node _T_242 = bits(lsu_match_data_0, 27, 27) @[el2_lib.scala 244:88] + node _T_243 = eq(_T_241, _T_242) @[el2_lib.scala 244:80] + node _T_244 = mux(_T_240, UInt<1>("h01"), _T_243) @[el2_lib.scala 244:25] + _T_48[27] <= _T_244 @[el2_lib.scala 244:19] + node _T_245 = bits(io.trigger_pkt_any[0].tdata2, 27, 0) @[el2_lib.scala 244:30] + node _T_246 = andr(_T_245) @[el2_lib.scala 244:38] + node _T_247 = and(_T_246, _T_51) @[el2_lib.scala 244:43] + node _T_248 = bits(io.trigger_pkt_any[0].tdata2, 28, 28) @[el2_lib.scala 244:76] + node _T_249 = bits(lsu_match_data_0, 28, 28) @[el2_lib.scala 244:88] + node _T_250 = eq(_T_248, _T_249) @[el2_lib.scala 244:80] + node _T_251 = mux(_T_247, UInt<1>("h01"), _T_250) @[el2_lib.scala 244:25] + _T_48[28] <= _T_251 @[el2_lib.scala 244:19] + node _T_252 = bits(io.trigger_pkt_any[0].tdata2, 28, 0) @[el2_lib.scala 244:30] + node _T_253 = andr(_T_252) @[el2_lib.scala 244:38] + node _T_254 = and(_T_253, _T_51) @[el2_lib.scala 244:43] + node _T_255 = bits(io.trigger_pkt_any[0].tdata2, 29, 29) @[el2_lib.scala 244:76] + node _T_256 = bits(lsu_match_data_0, 29, 29) @[el2_lib.scala 244:88] + node _T_257 = eq(_T_255, _T_256) @[el2_lib.scala 244:80] + node _T_258 = mux(_T_254, UInt<1>("h01"), _T_257) @[el2_lib.scala 244:25] + _T_48[29] <= _T_258 @[el2_lib.scala 244:19] + node _T_259 = bits(io.trigger_pkt_any[0].tdata2, 29, 0) @[el2_lib.scala 244:30] + node _T_260 = andr(_T_259) @[el2_lib.scala 244:38] + node _T_261 = and(_T_260, _T_51) @[el2_lib.scala 244:43] + node _T_262 = bits(io.trigger_pkt_any[0].tdata2, 30, 30) @[el2_lib.scala 244:76] + node _T_263 = bits(lsu_match_data_0, 30, 30) @[el2_lib.scala 244:88] + node _T_264 = eq(_T_262, _T_263) @[el2_lib.scala 244:80] + node _T_265 = mux(_T_261, UInt<1>("h01"), _T_264) @[el2_lib.scala 244:25] + _T_48[30] <= _T_265 @[el2_lib.scala 244:19] + node _T_266 = bits(io.trigger_pkt_any[0].tdata2, 30, 0) @[el2_lib.scala 244:30] + node _T_267 = andr(_T_266) @[el2_lib.scala 244:38] + node _T_268 = and(_T_267, _T_51) @[el2_lib.scala 244:43] + node _T_269 = bits(io.trigger_pkt_any[0].tdata2, 31, 31) @[el2_lib.scala 244:76] + node _T_270 = bits(lsu_match_data_0, 31, 31) @[el2_lib.scala 244:88] + node _T_271 = eq(_T_269, _T_270) @[el2_lib.scala 244:80] + node _T_272 = mux(_T_268, UInt<1>("h01"), _T_271) @[el2_lib.scala 244:25] + _T_48[31] <= _T_272 @[el2_lib.scala 244:19] + node _T_273 = cat(_T_48[1], _T_48[0]) @[el2_lib.scala 245:14] + node _T_274 = cat(_T_48[3], _T_48[2]) @[el2_lib.scala 245:14] + node _T_275 = cat(_T_274, _T_273) @[el2_lib.scala 245:14] + node _T_276 = cat(_T_48[5], _T_48[4]) @[el2_lib.scala 245:14] + node _T_277 = cat(_T_48[7], _T_48[6]) @[el2_lib.scala 245:14] + node _T_278 = cat(_T_277, _T_276) @[el2_lib.scala 245:14] + node _T_279 = cat(_T_278, _T_275) @[el2_lib.scala 245:14] + node _T_280 = cat(_T_48[9], _T_48[8]) @[el2_lib.scala 245:14] + node _T_281 = cat(_T_48[11], _T_48[10]) @[el2_lib.scala 245:14] + node _T_282 = cat(_T_281, _T_280) @[el2_lib.scala 245:14] + node _T_283 = cat(_T_48[13], _T_48[12]) @[el2_lib.scala 245:14] + node _T_284 = cat(_T_48[15], _T_48[14]) @[el2_lib.scala 245:14] + node _T_285 = cat(_T_284, _T_283) @[el2_lib.scala 245:14] + node _T_286 = cat(_T_285, _T_282) @[el2_lib.scala 245:14] + node _T_287 = cat(_T_286, _T_279) @[el2_lib.scala 245:14] + node _T_288 = cat(_T_48[17], _T_48[16]) @[el2_lib.scala 245:14] + node _T_289 = cat(_T_48[19], _T_48[18]) @[el2_lib.scala 245:14] + node _T_290 = cat(_T_289, _T_288) @[el2_lib.scala 245:14] + node _T_291 = cat(_T_48[21], _T_48[20]) @[el2_lib.scala 245:14] + node _T_292 = cat(_T_48[23], _T_48[22]) @[el2_lib.scala 245:14] + node _T_293 = cat(_T_292, _T_291) @[el2_lib.scala 245:14] + node _T_294 = cat(_T_293, _T_290) @[el2_lib.scala 245:14] + node _T_295 = cat(_T_48[25], _T_48[24]) @[el2_lib.scala 245:14] + node _T_296 = cat(_T_48[27], _T_48[26]) @[el2_lib.scala 245:14] + node _T_297 = cat(_T_296, _T_295) @[el2_lib.scala 245:14] + node _T_298 = cat(_T_48[29], _T_48[28]) @[el2_lib.scala 245:14] + node _T_299 = cat(_T_48[31], _T_48[30]) @[el2_lib.scala 245:14] + node _T_300 = cat(_T_299, _T_298) @[el2_lib.scala 245:14] + node _T_301 = cat(_T_300, _T_297) @[el2_lib.scala 245:14] + node _T_302 = cat(_T_301, _T_294) @[el2_lib.scala 245:14] + node _T_303 = cat(_T_302, _T_287) @[el2_lib.scala 245:14] + node _T_304 = and(_T_46, _T_303) @[el2_lsu_trigger.scala 19:87] + node _T_305 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_306 = and(io.lsu_pkt_m.valid, _T_305) @[el2_lsu_trigger.scala 18:69] + node _T_307 = and(io.trigger_pkt_any[1].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] + node _T_308 = and(io.trigger_pkt_any[1].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] + node _T_309 = eq(io.trigger_pkt_any[1].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] + node _T_310 = and(_T_308, _T_309) @[el2_lsu_trigger.scala 19:53] + node _T_311 = or(_T_307, _T_310) @[el2_lsu_trigger.scala 18:142] + node _T_312 = and(_T_306, _T_311) @[el2_lsu_trigger.scala 18:89] + node _T_313 = bits(io.trigger_pkt_any[1].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + wire _T_314 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_315 = andr(io.trigger_pkt_any[1].tdata2) @[el2_lib.scala 241:45] + node _T_316 = not(_T_315) @[el2_lib.scala 241:39] + node _T_317 = and(_T_313, _T_316) @[el2_lib.scala 241:37] + node _T_318 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_319 = bits(lsu_match_data_1, 0, 0) @[el2_lib.scala 242:60] + node _T_320 = eq(_T_318, _T_319) @[el2_lib.scala 242:52] + node _T_321 = or(_T_317, _T_320) @[el2_lib.scala 242:41] + _T_314[0] <= _T_321 @[el2_lib.scala 242:18] + node _T_322 = bits(io.trigger_pkt_any[1].tdata2, 0, 0) @[el2_lib.scala 244:30] + node _T_323 = andr(_T_322) @[el2_lib.scala 244:38] + node _T_324 = and(_T_323, _T_317) @[el2_lib.scala 244:43] + node _T_325 = bits(io.trigger_pkt_any[1].tdata2, 1, 1) @[el2_lib.scala 244:76] + node _T_326 = bits(lsu_match_data_1, 1, 1) @[el2_lib.scala 244:88] + node _T_327 = eq(_T_325, _T_326) @[el2_lib.scala 244:80] + node _T_328 = mux(_T_324, UInt<1>("h01"), _T_327) @[el2_lib.scala 244:25] + _T_314[1] <= _T_328 @[el2_lib.scala 244:19] + node _T_329 = bits(io.trigger_pkt_any[1].tdata2, 1, 0) @[el2_lib.scala 244:30] + node _T_330 = andr(_T_329) @[el2_lib.scala 244:38] + node _T_331 = and(_T_330, _T_317) @[el2_lib.scala 244:43] + node _T_332 = bits(io.trigger_pkt_any[1].tdata2, 2, 2) @[el2_lib.scala 244:76] + node _T_333 = bits(lsu_match_data_1, 2, 2) @[el2_lib.scala 244:88] + node _T_334 = eq(_T_332, _T_333) @[el2_lib.scala 244:80] + node _T_335 = mux(_T_331, UInt<1>("h01"), _T_334) @[el2_lib.scala 244:25] + _T_314[2] <= _T_335 @[el2_lib.scala 244:19] + node _T_336 = bits(io.trigger_pkt_any[1].tdata2, 2, 0) @[el2_lib.scala 244:30] + node _T_337 = andr(_T_336) @[el2_lib.scala 244:38] + node _T_338 = and(_T_337, _T_317) @[el2_lib.scala 244:43] + node _T_339 = bits(io.trigger_pkt_any[1].tdata2, 3, 3) @[el2_lib.scala 244:76] + node _T_340 = bits(lsu_match_data_1, 3, 3) @[el2_lib.scala 244:88] + node _T_341 = eq(_T_339, _T_340) @[el2_lib.scala 244:80] + node _T_342 = mux(_T_338, UInt<1>("h01"), _T_341) @[el2_lib.scala 244:25] + _T_314[3] <= _T_342 @[el2_lib.scala 244:19] + node _T_343 = bits(io.trigger_pkt_any[1].tdata2, 3, 0) @[el2_lib.scala 244:30] + node _T_344 = andr(_T_343) @[el2_lib.scala 244:38] + node _T_345 = and(_T_344, _T_317) @[el2_lib.scala 244:43] + node _T_346 = bits(io.trigger_pkt_any[1].tdata2, 4, 4) @[el2_lib.scala 244:76] + node _T_347 = bits(lsu_match_data_1, 4, 4) @[el2_lib.scala 244:88] + node _T_348 = eq(_T_346, _T_347) @[el2_lib.scala 244:80] + node _T_349 = mux(_T_345, UInt<1>("h01"), _T_348) @[el2_lib.scala 244:25] + _T_314[4] <= _T_349 @[el2_lib.scala 244:19] + node _T_350 = bits(io.trigger_pkt_any[1].tdata2, 4, 0) @[el2_lib.scala 244:30] + node _T_351 = andr(_T_350) @[el2_lib.scala 244:38] + node _T_352 = and(_T_351, _T_317) @[el2_lib.scala 244:43] + node _T_353 = bits(io.trigger_pkt_any[1].tdata2, 5, 5) @[el2_lib.scala 244:76] + node _T_354 = bits(lsu_match_data_1, 5, 5) @[el2_lib.scala 244:88] + node _T_355 = eq(_T_353, _T_354) @[el2_lib.scala 244:80] + node _T_356 = mux(_T_352, UInt<1>("h01"), _T_355) @[el2_lib.scala 244:25] + _T_314[5] <= _T_356 @[el2_lib.scala 244:19] + node _T_357 = bits(io.trigger_pkt_any[1].tdata2, 5, 0) @[el2_lib.scala 244:30] + node _T_358 = andr(_T_357) @[el2_lib.scala 244:38] + node _T_359 = and(_T_358, _T_317) @[el2_lib.scala 244:43] + node _T_360 = bits(io.trigger_pkt_any[1].tdata2, 6, 6) @[el2_lib.scala 244:76] + node _T_361 = bits(lsu_match_data_1, 6, 6) @[el2_lib.scala 244:88] + node _T_362 = eq(_T_360, _T_361) @[el2_lib.scala 244:80] + node _T_363 = mux(_T_359, UInt<1>("h01"), _T_362) @[el2_lib.scala 244:25] + _T_314[6] <= _T_363 @[el2_lib.scala 244:19] + node _T_364 = bits(io.trigger_pkt_any[1].tdata2, 6, 0) @[el2_lib.scala 244:30] + node _T_365 = andr(_T_364) @[el2_lib.scala 244:38] + node _T_366 = and(_T_365, _T_317) @[el2_lib.scala 244:43] + node _T_367 = bits(io.trigger_pkt_any[1].tdata2, 7, 7) @[el2_lib.scala 244:76] + node _T_368 = bits(lsu_match_data_1, 7, 7) @[el2_lib.scala 244:88] + node _T_369 = eq(_T_367, _T_368) @[el2_lib.scala 244:80] + node _T_370 = mux(_T_366, UInt<1>("h01"), _T_369) @[el2_lib.scala 244:25] + _T_314[7] <= _T_370 @[el2_lib.scala 244:19] + node _T_371 = bits(io.trigger_pkt_any[1].tdata2, 7, 0) @[el2_lib.scala 244:30] + node _T_372 = andr(_T_371) @[el2_lib.scala 244:38] + node _T_373 = and(_T_372, _T_317) @[el2_lib.scala 244:43] + node _T_374 = bits(io.trigger_pkt_any[1].tdata2, 8, 8) @[el2_lib.scala 244:76] + node _T_375 = bits(lsu_match_data_1, 8, 8) @[el2_lib.scala 244:88] + node _T_376 = eq(_T_374, _T_375) @[el2_lib.scala 244:80] + node _T_377 = mux(_T_373, UInt<1>("h01"), _T_376) @[el2_lib.scala 244:25] + _T_314[8] <= _T_377 @[el2_lib.scala 244:19] + node _T_378 = bits(io.trigger_pkt_any[1].tdata2, 8, 0) @[el2_lib.scala 244:30] + node _T_379 = andr(_T_378) @[el2_lib.scala 244:38] + node _T_380 = and(_T_379, _T_317) @[el2_lib.scala 244:43] + node _T_381 = bits(io.trigger_pkt_any[1].tdata2, 9, 9) @[el2_lib.scala 244:76] + node _T_382 = bits(lsu_match_data_1, 9, 9) @[el2_lib.scala 244:88] + node _T_383 = eq(_T_381, _T_382) @[el2_lib.scala 244:80] + node _T_384 = mux(_T_380, UInt<1>("h01"), _T_383) @[el2_lib.scala 244:25] + _T_314[9] <= _T_384 @[el2_lib.scala 244:19] + node _T_385 = bits(io.trigger_pkt_any[1].tdata2, 9, 0) @[el2_lib.scala 244:30] + node _T_386 = andr(_T_385) @[el2_lib.scala 244:38] + node _T_387 = and(_T_386, _T_317) @[el2_lib.scala 244:43] + node _T_388 = bits(io.trigger_pkt_any[1].tdata2, 10, 10) @[el2_lib.scala 244:76] + node _T_389 = bits(lsu_match_data_1, 10, 10) @[el2_lib.scala 244:88] + node _T_390 = eq(_T_388, _T_389) @[el2_lib.scala 244:80] + node _T_391 = mux(_T_387, UInt<1>("h01"), _T_390) @[el2_lib.scala 244:25] + _T_314[10] <= _T_391 @[el2_lib.scala 244:19] + node _T_392 = bits(io.trigger_pkt_any[1].tdata2, 10, 0) @[el2_lib.scala 244:30] + node _T_393 = andr(_T_392) @[el2_lib.scala 244:38] + node _T_394 = and(_T_393, _T_317) @[el2_lib.scala 244:43] + node _T_395 = bits(io.trigger_pkt_any[1].tdata2, 11, 11) @[el2_lib.scala 244:76] + node _T_396 = bits(lsu_match_data_1, 11, 11) @[el2_lib.scala 244:88] + node _T_397 = eq(_T_395, _T_396) @[el2_lib.scala 244:80] + node _T_398 = mux(_T_394, UInt<1>("h01"), _T_397) @[el2_lib.scala 244:25] + _T_314[11] <= _T_398 @[el2_lib.scala 244:19] + node _T_399 = bits(io.trigger_pkt_any[1].tdata2, 11, 0) @[el2_lib.scala 244:30] + node _T_400 = andr(_T_399) @[el2_lib.scala 244:38] + node _T_401 = and(_T_400, _T_317) @[el2_lib.scala 244:43] + node _T_402 = bits(io.trigger_pkt_any[1].tdata2, 12, 12) @[el2_lib.scala 244:76] + node _T_403 = bits(lsu_match_data_1, 12, 12) @[el2_lib.scala 244:88] + node _T_404 = eq(_T_402, _T_403) @[el2_lib.scala 244:80] + node _T_405 = mux(_T_401, UInt<1>("h01"), _T_404) @[el2_lib.scala 244:25] + _T_314[12] <= _T_405 @[el2_lib.scala 244:19] + node _T_406 = bits(io.trigger_pkt_any[1].tdata2, 12, 0) @[el2_lib.scala 244:30] + node _T_407 = andr(_T_406) @[el2_lib.scala 244:38] + node _T_408 = and(_T_407, _T_317) @[el2_lib.scala 244:43] + node _T_409 = bits(io.trigger_pkt_any[1].tdata2, 13, 13) @[el2_lib.scala 244:76] + node _T_410 = bits(lsu_match_data_1, 13, 13) @[el2_lib.scala 244:88] + node _T_411 = eq(_T_409, _T_410) @[el2_lib.scala 244:80] + node _T_412 = mux(_T_408, UInt<1>("h01"), _T_411) @[el2_lib.scala 244:25] + _T_314[13] <= _T_412 @[el2_lib.scala 244:19] + node _T_413 = bits(io.trigger_pkt_any[1].tdata2, 13, 0) @[el2_lib.scala 244:30] + node _T_414 = andr(_T_413) @[el2_lib.scala 244:38] + node _T_415 = and(_T_414, _T_317) @[el2_lib.scala 244:43] + node _T_416 = bits(io.trigger_pkt_any[1].tdata2, 14, 14) @[el2_lib.scala 244:76] + node _T_417 = bits(lsu_match_data_1, 14, 14) @[el2_lib.scala 244:88] + node _T_418 = eq(_T_416, _T_417) @[el2_lib.scala 244:80] + node _T_419 = mux(_T_415, UInt<1>("h01"), _T_418) @[el2_lib.scala 244:25] + _T_314[14] <= _T_419 @[el2_lib.scala 244:19] + node _T_420 = bits(io.trigger_pkt_any[1].tdata2, 14, 0) @[el2_lib.scala 244:30] + node _T_421 = andr(_T_420) @[el2_lib.scala 244:38] + node _T_422 = and(_T_421, _T_317) @[el2_lib.scala 244:43] + node _T_423 = bits(io.trigger_pkt_any[1].tdata2, 15, 15) @[el2_lib.scala 244:76] + node _T_424 = bits(lsu_match_data_1, 15, 15) @[el2_lib.scala 244:88] + node _T_425 = eq(_T_423, _T_424) @[el2_lib.scala 244:80] + node _T_426 = mux(_T_422, UInt<1>("h01"), _T_425) @[el2_lib.scala 244:25] + _T_314[15] <= _T_426 @[el2_lib.scala 244:19] + node _T_427 = bits(io.trigger_pkt_any[1].tdata2, 15, 0) @[el2_lib.scala 244:30] + node _T_428 = andr(_T_427) @[el2_lib.scala 244:38] + node _T_429 = and(_T_428, _T_317) @[el2_lib.scala 244:43] + node _T_430 = bits(io.trigger_pkt_any[1].tdata2, 16, 16) @[el2_lib.scala 244:76] + node _T_431 = bits(lsu_match_data_1, 16, 16) @[el2_lib.scala 244:88] + node _T_432 = eq(_T_430, _T_431) @[el2_lib.scala 244:80] + node _T_433 = mux(_T_429, UInt<1>("h01"), _T_432) @[el2_lib.scala 244:25] + _T_314[16] <= _T_433 @[el2_lib.scala 244:19] + node _T_434 = bits(io.trigger_pkt_any[1].tdata2, 16, 0) @[el2_lib.scala 244:30] + node _T_435 = andr(_T_434) @[el2_lib.scala 244:38] + node _T_436 = and(_T_435, _T_317) @[el2_lib.scala 244:43] + node _T_437 = bits(io.trigger_pkt_any[1].tdata2, 17, 17) @[el2_lib.scala 244:76] + node _T_438 = bits(lsu_match_data_1, 17, 17) @[el2_lib.scala 244:88] + node _T_439 = eq(_T_437, _T_438) @[el2_lib.scala 244:80] + node _T_440 = mux(_T_436, UInt<1>("h01"), _T_439) @[el2_lib.scala 244:25] + _T_314[17] <= _T_440 @[el2_lib.scala 244:19] + node _T_441 = bits(io.trigger_pkt_any[1].tdata2, 17, 0) @[el2_lib.scala 244:30] + node _T_442 = andr(_T_441) @[el2_lib.scala 244:38] + node _T_443 = and(_T_442, _T_317) @[el2_lib.scala 244:43] + node _T_444 = bits(io.trigger_pkt_any[1].tdata2, 18, 18) @[el2_lib.scala 244:76] + node _T_445 = bits(lsu_match_data_1, 18, 18) @[el2_lib.scala 244:88] + node _T_446 = eq(_T_444, _T_445) @[el2_lib.scala 244:80] + node _T_447 = mux(_T_443, UInt<1>("h01"), _T_446) @[el2_lib.scala 244:25] + _T_314[18] <= _T_447 @[el2_lib.scala 244:19] + node _T_448 = bits(io.trigger_pkt_any[1].tdata2, 18, 0) @[el2_lib.scala 244:30] + node _T_449 = andr(_T_448) @[el2_lib.scala 244:38] + node _T_450 = and(_T_449, _T_317) @[el2_lib.scala 244:43] + node _T_451 = bits(io.trigger_pkt_any[1].tdata2, 19, 19) @[el2_lib.scala 244:76] + node _T_452 = bits(lsu_match_data_1, 19, 19) @[el2_lib.scala 244:88] + node _T_453 = eq(_T_451, _T_452) @[el2_lib.scala 244:80] + node _T_454 = mux(_T_450, UInt<1>("h01"), _T_453) @[el2_lib.scala 244:25] + _T_314[19] <= _T_454 @[el2_lib.scala 244:19] + node _T_455 = bits(io.trigger_pkt_any[1].tdata2, 19, 0) @[el2_lib.scala 244:30] + node _T_456 = andr(_T_455) @[el2_lib.scala 244:38] + node _T_457 = and(_T_456, _T_317) @[el2_lib.scala 244:43] + node _T_458 = bits(io.trigger_pkt_any[1].tdata2, 20, 20) @[el2_lib.scala 244:76] + node _T_459 = bits(lsu_match_data_1, 20, 20) @[el2_lib.scala 244:88] + node _T_460 = eq(_T_458, _T_459) @[el2_lib.scala 244:80] + node _T_461 = mux(_T_457, UInt<1>("h01"), _T_460) @[el2_lib.scala 244:25] + _T_314[20] <= _T_461 @[el2_lib.scala 244:19] + node _T_462 = bits(io.trigger_pkt_any[1].tdata2, 20, 0) @[el2_lib.scala 244:30] + node _T_463 = andr(_T_462) @[el2_lib.scala 244:38] + node _T_464 = and(_T_463, _T_317) @[el2_lib.scala 244:43] + node _T_465 = bits(io.trigger_pkt_any[1].tdata2, 21, 21) @[el2_lib.scala 244:76] + node _T_466 = bits(lsu_match_data_1, 21, 21) @[el2_lib.scala 244:88] + node _T_467 = eq(_T_465, _T_466) @[el2_lib.scala 244:80] + node _T_468 = mux(_T_464, UInt<1>("h01"), _T_467) @[el2_lib.scala 244:25] + _T_314[21] <= _T_468 @[el2_lib.scala 244:19] + node _T_469 = bits(io.trigger_pkt_any[1].tdata2, 21, 0) @[el2_lib.scala 244:30] + node _T_470 = andr(_T_469) @[el2_lib.scala 244:38] + node _T_471 = and(_T_470, _T_317) @[el2_lib.scala 244:43] + node _T_472 = bits(io.trigger_pkt_any[1].tdata2, 22, 22) @[el2_lib.scala 244:76] + node _T_473 = bits(lsu_match_data_1, 22, 22) @[el2_lib.scala 244:88] + node _T_474 = eq(_T_472, _T_473) @[el2_lib.scala 244:80] + node _T_475 = mux(_T_471, UInt<1>("h01"), _T_474) @[el2_lib.scala 244:25] + _T_314[22] <= _T_475 @[el2_lib.scala 244:19] + node _T_476 = bits(io.trigger_pkt_any[1].tdata2, 22, 0) @[el2_lib.scala 244:30] + node _T_477 = andr(_T_476) @[el2_lib.scala 244:38] + node _T_478 = and(_T_477, _T_317) @[el2_lib.scala 244:43] + node _T_479 = bits(io.trigger_pkt_any[1].tdata2, 23, 23) @[el2_lib.scala 244:76] + node _T_480 = bits(lsu_match_data_1, 23, 23) @[el2_lib.scala 244:88] + node _T_481 = eq(_T_479, _T_480) @[el2_lib.scala 244:80] + node _T_482 = mux(_T_478, UInt<1>("h01"), _T_481) @[el2_lib.scala 244:25] + _T_314[23] <= _T_482 @[el2_lib.scala 244:19] + node _T_483 = bits(io.trigger_pkt_any[1].tdata2, 23, 0) @[el2_lib.scala 244:30] + node _T_484 = andr(_T_483) @[el2_lib.scala 244:38] + node _T_485 = and(_T_484, _T_317) @[el2_lib.scala 244:43] + node _T_486 = bits(io.trigger_pkt_any[1].tdata2, 24, 24) @[el2_lib.scala 244:76] + node _T_487 = bits(lsu_match_data_1, 24, 24) @[el2_lib.scala 244:88] + node _T_488 = eq(_T_486, _T_487) @[el2_lib.scala 244:80] + node _T_489 = mux(_T_485, UInt<1>("h01"), _T_488) @[el2_lib.scala 244:25] + _T_314[24] <= _T_489 @[el2_lib.scala 244:19] + node _T_490 = bits(io.trigger_pkt_any[1].tdata2, 24, 0) @[el2_lib.scala 244:30] + node _T_491 = andr(_T_490) @[el2_lib.scala 244:38] + node _T_492 = and(_T_491, _T_317) @[el2_lib.scala 244:43] + node _T_493 = bits(io.trigger_pkt_any[1].tdata2, 25, 25) @[el2_lib.scala 244:76] + node _T_494 = bits(lsu_match_data_1, 25, 25) @[el2_lib.scala 244:88] + node _T_495 = eq(_T_493, _T_494) @[el2_lib.scala 244:80] + node _T_496 = mux(_T_492, UInt<1>("h01"), _T_495) @[el2_lib.scala 244:25] + _T_314[25] <= _T_496 @[el2_lib.scala 244:19] + node _T_497 = bits(io.trigger_pkt_any[1].tdata2, 25, 0) @[el2_lib.scala 244:30] + node _T_498 = andr(_T_497) @[el2_lib.scala 244:38] + node _T_499 = and(_T_498, _T_317) @[el2_lib.scala 244:43] + node _T_500 = bits(io.trigger_pkt_any[1].tdata2, 26, 26) @[el2_lib.scala 244:76] + node _T_501 = bits(lsu_match_data_1, 26, 26) @[el2_lib.scala 244:88] + node _T_502 = eq(_T_500, _T_501) @[el2_lib.scala 244:80] + node _T_503 = mux(_T_499, UInt<1>("h01"), _T_502) @[el2_lib.scala 244:25] + _T_314[26] <= _T_503 @[el2_lib.scala 244:19] + node _T_504 = bits(io.trigger_pkt_any[1].tdata2, 26, 0) @[el2_lib.scala 244:30] + node _T_505 = andr(_T_504) @[el2_lib.scala 244:38] + node _T_506 = and(_T_505, _T_317) @[el2_lib.scala 244:43] + node _T_507 = bits(io.trigger_pkt_any[1].tdata2, 27, 27) @[el2_lib.scala 244:76] + node _T_508 = bits(lsu_match_data_1, 27, 27) @[el2_lib.scala 244:88] + node _T_509 = eq(_T_507, _T_508) @[el2_lib.scala 244:80] + node _T_510 = mux(_T_506, UInt<1>("h01"), _T_509) @[el2_lib.scala 244:25] + _T_314[27] <= _T_510 @[el2_lib.scala 244:19] + node _T_511 = bits(io.trigger_pkt_any[1].tdata2, 27, 0) @[el2_lib.scala 244:30] + node _T_512 = andr(_T_511) @[el2_lib.scala 244:38] + node _T_513 = and(_T_512, _T_317) @[el2_lib.scala 244:43] + node _T_514 = bits(io.trigger_pkt_any[1].tdata2, 28, 28) @[el2_lib.scala 244:76] + node _T_515 = bits(lsu_match_data_1, 28, 28) @[el2_lib.scala 244:88] + node _T_516 = eq(_T_514, _T_515) @[el2_lib.scala 244:80] + node _T_517 = mux(_T_513, UInt<1>("h01"), _T_516) @[el2_lib.scala 244:25] + _T_314[28] <= _T_517 @[el2_lib.scala 244:19] + node _T_518 = bits(io.trigger_pkt_any[1].tdata2, 28, 0) @[el2_lib.scala 244:30] + node _T_519 = andr(_T_518) @[el2_lib.scala 244:38] + node _T_520 = and(_T_519, _T_317) @[el2_lib.scala 244:43] + node _T_521 = bits(io.trigger_pkt_any[1].tdata2, 29, 29) @[el2_lib.scala 244:76] + node _T_522 = bits(lsu_match_data_1, 29, 29) @[el2_lib.scala 244:88] + node _T_523 = eq(_T_521, _T_522) @[el2_lib.scala 244:80] + node _T_524 = mux(_T_520, UInt<1>("h01"), _T_523) @[el2_lib.scala 244:25] + _T_314[29] <= _T_524 @[el2_lib.scala 244:19] + node _T_525 = bits(io.trigger_pkt_any[1].tdata2, 29, 0) @[el2_lib.scala 244:30] + node _T_526 = andr(_T_525) @[el2_lib.scala 244:38] + node _T_527 = and(_T_526, _T_317) @[el2_lib.scala 244:43] + node _T_528 = bits(io.trigger_pkt_any[1].tdata2, 30, 30) @[el2_lib.scala 244:76] + node _T_529 = bits(lsu_match_data_1, 30, 30) @[el2_lib.scala 244:88] + node _T_530 = eq(_T_528, _T_529) @[el2_lib.scala 244:80] + node _T_531 = mux(_T_527, UInt<1>("h01"), _T_530) @[el2_lib.scala 244:25] + _T_314[30] <= _T_531 @[el2_lib.scala 244:19] + node _T_532 = bits(io.trigger_pkt_any[1].tdata2, 30, 0) @[el2_lib.scala 244:30] + node _T_533 = andr(_T_532) @[el2_lib.scala 244:38] + node _T_534 = and(_T_533, _T_317) @[el2_lib.scala 244:43] + node _T_535 = bits(io.trigger_pkt_any[1].tdata2, 31, 31) @[el2_lib.scala 244:76] + node _T_536 = bits(lsu_match_data_1, 31, 31) @[el2_lib.scala 244:88] + node _T_537 = eq(_T_535, _T_536) @[el2_lib.scala 244:80] + node _T_538 = mux(_T_534, UInt<1>("h01"), _T_537) @[el2_lib.scala 244:25] + _T_314[31] <= _T_538 @[el2_lib.scala 244:19] + node _T_539 = cat(_T_314[1], _T_314[0]) @[el2_lib.scala 245:14] + node _T_540 = cat(_T_314[3], _T_314[2]) @[el2_lib.scala 245:14] + node _T_541 = cat(_T_540, _T_539) @[el2_lib.scala 245:14] + node _T_542 = cat(_T_314[5], _T_314[4]) @[el2_lib.scala 245:14] + node _T_543 = cat(_T_314[7], _T_314[6]) @[el2_lib.scala 245:14] + node _T_544 = cat(_T_543, _T_542) @[el2_lib.scala 245:14] + node _T_545 = cat(_T_544, _T_541) @[el2_lib.scala 245:14] + node _T_546 = cat(_T_314[9], _T_314[8]) @[el2_lib.scala 245:14] + node _T_547 = cat(_T_314[11], _T_314[10]) @[el2_lib.scala 245:14] + node _T_548 = cat(_T_547, _T_546) @[el2_lib.scala 245:14] + node _T_549 = cat(_T_314[13], _T_314[12]) @[el2_lib.scala 245:14] + node _T_550 = cat(_T_314[15], _T_314[14]) @[el2_lib.scala 245:14] + node _T_551 = cat(_T_550, _T_549) @[el2_lib.scala 245:14] + node _T_552 = cat(_T_551, _T_548) @[el2_lib.scala 245:14] + node _T_553 = cat(_T_552, _T_545) @[el2_lib.scala 245:14] + node _T_554 = cat(_T_314[17], _T_314[16]) @[el2_lib.scala 245:14] + node _T_555 = cat(_T_314[19], _T_314[18]) @[el2_lib.scala 245:14] + node _T_556 = cat(_T_555, _T_554) @[el2_lib.scala 245:14] + node _T_557 = cat(_T_314[21], _T_314[20]) @[el2_lib.scala 245:14] + node _T_558 = cat(_T_314[23], _T_314[22]) @[el2_lib.scala 245:14] + node _T_559 = cat(_T_558, _T_557) @[el2_lib.scala 245:14] + node _T_560 = cat(_T_559, _T_556) @[el2_lib.scala 245:14] + node _T_561 = cat(_T_314[25], _T_314[24]) @[el2_lib.scala 245:14] + node _T_562 = cat(_T_314[27], _T_314[26]) @[el2_lib.scala 245:14] + node _T_563 = cat(_T_562, _T_561) @[el2_lib.scala 245:14] + node _T_564 = cat(_T_314[29], _T_314[28]) @[el2_lib.scala 245:14] + node _T_565 = cat(_T_314[31], _T_314[30]) @[el2_lib.scala 245:14] + node _T_566 = cat(_T_565, _T_564) @[el2_lib.scala 245:14] + node _T_567 = cat(_T_566, _T_563) @[el2_lib.scala 245:14] + node _T_568 = cat(_T_567, _T_560) @[el2_lib.scala 245:14] + node _T_569 = cat(_T_568, _T_553) @[el2_lib.scala 245:14] + node _T_570 = and(_T_312, _T_569) @[el2_lsu_trigger.scala 19:87] + node _T_571 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_572 = and(io.lsu_pkt_m.valid, _T_571) @[el2_lsu_trigger.scala 18:69] + node _T_573 = and(io.trigger_pkt_any[2].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] + node _T_574 = and(io.trigger_pkt_any[2].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] + node _T_575 = eq(io.trigger_pkt_any[2].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] + node _T_576 = and(_T_574, _T_575) @[el2_lsu_trigger.scala 19:53] + node _T_577 = or(_T_573, _T_576) @[el2_lsu_trigger.scala 18:142] + node _T_578 = and(_T_572, _T_577) @[el2_lsu_trigger.scala 18:89] + node _T_579 = bits(io.trigger_pkt_any[2].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + wire _T_580 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_581 = andr(io.trigger_pkt_any[2].tdata2) @[el2_lib.scala 241:45] + node _T_582 = not(_T_581) @[el2_lib.scala 241:39] + node _T_583 = and(_T_579, _T_582) @[el2_lib.scala 241:37] + node _T_584 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_585 = bits(lsu_match_data_2, 0, 0) @[el2_lib.scala 242:60] + node _T_586 = eq(_T_584, _T_585) @[el2_lib.scala 242:52] + node _T_587 = or(_T_583, _T_586) @[el2_lib.scala 242:41] + _T_580[0] <= _T_587 @[el2_lib.scala 242:18] + node _T_588 = bits(io.trigger_pkt_any[2].tdata2, 0, 0) @[el2_lib.scala 244:30] + node _T_589 = andr(_T_588) @[el2_lib.scala 244:38] + node _T_590 = and(_T_589, _T_583) @[el2_lib.scala 244:43] + node _T_591 = bits(io.trigger_pkt_any[2].tdata2, 1, 1) @[el2_lib.scala 244:76] + node _T_592 = bits(lsu_match_data_2, 1, 1) @[el2_lib.scala 244:88] + node _T_593 = eq(_T_591, _T_592) @[el2_lib.scala 244:80] + node _T_594 = mux(_T_590, UInt<1>("h01"), _T_593) @[el2_lib.scala 244:25] + _T_580[1] <= _T_594 @[el2_lib.scala 244:19] + node _T_595 = bits(io.trigger_pkt_any[2].tdata2, 1, 0) @[el2_lib.scala 244:30] + node _T_596 = andr(_T_595) @[el2_lib.scala 244:38] + node _T_597 = and(_T_596, _T_583) @[el2_lib.scala 244:43] + node _T_598 = bits(io.trigger_pkt_any[2].tdata2, 2, 2) @[el2_lib.scala 244:76] + node _T_599 = bits(lsu_match_data_2, 2, 2) @[el2_lib.scala 244:88] + node _T_600 = eq(_T_598, _T_599) @[el2_lib.scala 244:80] + node _T_601 = mux(_T_597, UInt<1>("h01"), _T_600) @[el2_lib.scala 244:25] + _T_580[2] <= _T_601 @[el2_lib.scala 244:19] + node _T_602 = bits(io.trigger_pkt_any[2].tdata2, 2, 0) @[el2_lib.scala 244:30] + node _T_603 = andr(_T_602) @[el2_lib.scala 244:38] + node _T_604 = and(_T_603, _T_583) @[el2_lib.scala 244:43] + node _T_605 = bits(io.trigger_pkt_any[2].tdata2, 3, 3) @[el2_lib.scala 244:76] + node _T_606 = bits(lsu_match_data_2, 3, 3) @[el2_lib.scala 244:88] + node _T_607 = eq(_T_605, _T_606) @[el2_lib.scala 244:80] + node _T_608 = mux(_T_604, UInt<1>("h01"), _T_607) @[el2_lib.scala 244:25] + _T_580[3] <= _T_608 @[el2_lib.scala 244:19] + node _T_609 = bits(io.trigger_pkt_any[2].tdata2, 3, 0) @[el2_lib.scala 244:30] + node _T_610 = andr(_T_609) @[el2_lib.scala 244:38] + node _T_611 = and(_T_610, _T_583) @[el2_lib.scala 244:43] + node _T_612 = bits(io.trigger_pkt_any[2].tdata2, 4, 4) @[el2_lib.scala 244:76] + node _T_613 = bits(lsu_match_data_2, 4, 4) @[el2_lib.scala 244:88] + node _T_614 = eq(_T_612, _T_613) @[el2_lib.scala 244:80] + node _T_615 = mux(_T_611, UInt<1>("h01"), _T_614) @[el2_lib.scala 244:25] + _T_580[4] <= _T_615 @[el2_lib.scala 244:19] + node _T_616 = bits(io.trigger_pkt_any[2].tdata2, 4, 0) @[el2_lib.scala 244:30] + node _T_617 = andr(_T_616) @[el2_lib.scala 244:38] + node _T_618 = and(_T_617, _T_583) @[el2_lib.scala 244:43] + node _T_619 = bits(io.trigger_pkt_any[2].tdata2, 5, 5) @[el2_lib.scala 244:76] + node _T_620 = bits(lsu_match_data_2, 5, 5) @[el2_lib.scala 244:88] + node _T_621 = eq(_T_619, _T_620) @[el2_lib.scala 244:80] + node _T_622 = mux(_T_618, UInt<1>("h01"), _T_621) @[el2_lib.scala 244:25] + _T_580[5] <= _T_622 @[el2_lib.scala 244:19] + node _T_623 = bits(io.trigger_pkt_any[2].tdata2, 5, 0) @[el2_lib.scala 244:30] + node _T_624 = andr(_T_623) @[el2_lib.scala 244:38] + node _T_625 = and(_T_624, _T_583) @[el2_lib.scala 244:43] + node _T_626 = bits(io.trigger_pkt_any[2].tdata2, 6, 6) @[el2_lib.scala 244:76] + node _T_627 = bits(lsu_match_data_2, 6, 6) @[el2_lib.scala 244:88] + node _T_628 = eq(_T_626, _T_627) @[el2_lib.scala 244:80] + node _T_629 = mux(_T_625, UInt<1>("h01"), _T_628) @[el2_lib.scala 244:25] + _T_580[6] <= _T_629 @[el2_lib.scala 244:19] + node _T_630 = bits(io.trigger_pkt_any[2].tdata2, 6, 0) @[el2_lib.scala 244:30] + node _T_631 = andr(_T_630) @[el2_lib.scala 244:38] + node _T_632 = and(_T_631, _T_583) @[el2_lib.scala 244:43] + node _T_633 = bits(io.trigger_pkt_any[2].tdata2, 7, 7) @[el2_lib.scala 244:76] + node _T_634 = bits(lsu_match_data_2, 7, 7) @[el2_lib.scala 244:88] + node _T_635 = eq(_T_633, _T_634) @[el2_lib.scala 244:80] + node _T_636 = mux(_T_632, UInt<1>("h01"), _T_635) @[el2_lib.scala 244:25] + _T_580[7] <= _T_636 @[el2_lib.scala 244:19] + node _T_637 = bits(io.trigger_pkt_any[2].tdata2, 7, 0) @[el2_lib.scala 244:30] + node _T_638 = andr(_T_637) @[el2_lib.scala 244:38] + node _T_639 = and(_T_638, _T_583) @[el2_lib.scala 244:43] + node _T_640 = bits(io.trigger_pkt_any[2].tdata2, 8, 8) @[el2_lib.scala 244:76] + node _T_641 = bits(lsu_match_data_2, 8, 8) @[el2_lib.scala 244:88] + node _T_642 = eq(_T_640, _T_641) @[el2_lib.scala 244:80] + node _T_643 = mux(_T_639, UInt<1>("h01"), _T_642) @[el2_lib.scala 244:25] + _T_580[8] <= _T_643 @[el2_lib.scala 244:19] + node _T_644 = bits(io.trigger_pkt_any[2].tdata2, 8, 0) @[el2_lib.scala 244:30] + node _T_645 = andr(_T_644) @[el2_lib.scala 244:38] + node _T_646 = and(_T_645, _T_583) @[el2_lib.scala 244:43] + node _T_647 = bits(io.trigger_pkt_any[2].tdata2, 9, 9) @[el2_lib.scala 244:76] + node _T_648 = bits(lsu_match_data_2, 9, 9) @[el2_lib.scala 244:88] + node _T_649 = eq(_T_647, _T_648) @[el2_lib.scala 244:80] + node _T_650 = mux(_T_646, UInt<1>("h01"), _T_649) @[el2_lib.scala 244:25] + _T_580[9] <= _T_650 @[el2_lib.scala 244:19] + node _T_651 = bits(io.trigger_pkt_any[2].tdata2, 9, 0) @[el2_lib.scala 244:30] + node _T_652 = andr(_T_651) @[el2_lib.scala 244:38] + node _T_653 = and(_T_652, _T_583) @[el2_lib.scala 244:43] + node _T_654 = bits(io.trigger_pkt_any[2].tdata2, 10, 10) @[el2_lib.scala 244:76] + node _T_655 = bits(lsu_match_data_2, 10, 10) @[el2_lib.scala 244:88] + node _T_656 = eq(_T_654, _T_655) @[el2_lib.scala 244:80] + node _T_657 = mux(_T_653, UInt<1>("h01"), _T_656) @[el2_lib.scala 244:25] + _T_580[10] <= _T_657 @[el2_lib.scala 244:19] + node _T_658 = bits(io.trigger_pkt_any[2].tdata2, 10, 0) @[el2_lib.scala 244:30] + node _T_659 = andr(_T_658) @[el2_lib.scala 244:38] + node _T_660 = and(_T_659, _T_583) @[el2_lib.scala 244:43] + node _T_661 = bits(io.trigger_pkt_any[2].tdata2, 11, 11) @[el2_lib.scala 244:76] + node _T_662 = bits(lsu_match_data_2, 11, 11) @[el2_lib.scala 244:88] + node _T_663 = eq(_T_661, _T_662) @[el2_lib.scala 244:80] + node _T_664 = mux(_T_660, UInt<1>("h01"), _T_663) @[el2_lib.scala 244:25] + _T_580[11] <= _T_664 @[el2_lib.scala 244:19] + node _T_665 = bits(io.trigger_pkt_any[2].tdata2, 11, 0) @[el2_lib.scala 244:30] + node _T_666 = andr(_T_665) @[el2_lib.scala 244:38] + node _T_667 = and(_T_666, _T_583) @[el2_lib.scala 244:43] + node _T_668 = bits(io.trigger_pkt_any[2].tdata2, 12, 12) @[el2_lib.scala 244:76] + node _T_669 = bits(lsu_match_data_2, 12, 12) @[el2_lib.scala 244:88] + node _T_670 = eq(_T_668, _T_669) @[el2_lib.scala 244:80] + node _T_671 = mux(_T_667, UInt<1>("h01"), _T_670) @[el2_lib.scala 244:25] + _T_580[12] <= _T_671 @[el2_lib.scala 244:19] + node _T_672 = bits(io.trigger_pkt_any[2].tdata2, 12, 0) @[el2_lib.scala 244:30] + node _T_673 = andr(_T_672) @[el2_lib.scala 244:38] + node _T_674 = and(_T_673, _T_583) @[el2_lib.scala 244:43] + node _T_675 = bits(io.trigger_pkt_any[2].tdata2, 13, 13) @[el2_lib.scala 244:76] + node _T_676 = bits(lsu_match_data_2, 13, 13) @[el2_lib.scala 244:88] + node _T_677 = eq(_T_675, _T_676) @[el2_lib.scala 244:80] + node _T_678 = mux(_T_674, UInt<1>("h01"), _T_677) @[el2_lib.scala 244:25] + _T_580[13] <= _T_678 @[el2_lib.scala 244:19] + node _T_679 = bits(io.trigger_pkt_any[2].tdata2, 13, 0) @[el2_lib.scala 244:30] + node _T_680 = andr(_T_679) @[el2_lib.scala 244:38] + node _T_681 = and(_T_680, _T_583) @[el2_lib.scala 244:43] + node _T_682 = bits(io.trigger_pkt_any[2].tdata2, 14, 14) @[el2_lib.scala 244:76] + node _T_683 = bits(lsu_match_data_2, 14, 14) @[el2_lib.scala 244:88] + node _T_684 = eq(_T_682, _T_683) @[el2_lib.scala 244:80] + node _T_685 = mux(_T_681, UInt<1>("h01"), _T_684) @[el2_lib.scala 244:25] + _T_580[14] <= _T_685 @[el2_lib.scala 244:19] + node _T_686 = bits(io.trigger_pkt_any[2].tdata2, 14, 0) @[el2_lib.scala 244:30] + node _T_687 = andr(_T_686) @[el2_lib.scala 244:38] + node _T_688 = and(_T_687, _T_583) @[el2_lib.scala 244:43] + node _T_689 = bits(io.trigger_pkt_any[2].tdata2, 15, 15) @[el2_lib.scala 244:76] + node _T_690 = bits(lsu_match_data_2, 15, 15) @[el2_lib.scala 244:88] + node _T_691 = eq(_T_689, _T_690) @[el2_lib.scala 244:80] + node _T_692 = mux(_T_688, UInt<1>("h01"), _T_691) @[el2_lib.scala 244:25] + _T_580[15] <= _T_692 @[el2_lib.scala 244:19] + node _T_693 = bits(io.trigger_pkt_any[2].tdata2, 15, 0) @[el2_lib.scala 244:30] + node _T_694 = andr(_T_693) @[el2_lib.scala 244:38] + node _T_695 = and(_T_694, _T_583) @[el2_lib.scala 244:43] + node _T_696 = bits(io.trigger_pkt_any[2].tdata2, 16, 16) @[el2_lib.scala 244:76] + node _T_697 = bits(lsu_match_data_2, 16, 16) @[el2_lib.scala 244:88] + node _T_698 = eq(_T_696, _T_697) @[el2_lib.scala 244:80] + node _T_699 = mux(_T_695, UInt<1>("h01"), _T_698) @[el2_lib.scala 244:25] + _T_580[16] <= _T_699 @[el2_lib.scala 244:19] + node _T_700 = bits(io.trigger_pkt_any[2].tdata2, 16, 0) @[el2_lib.scala 244:30] + node _T_701 = andr(_T_700) @[el2_lib.scala 244:38] + node _T_702 = and(_T_701, _T_583) @[el2_lib.scala 244:43] + node _T_703 = bits(io.trigger_pkt_any[2].tdata2, 17, 17) @[el2_lib.scala 244:76] + node _T_704 = bits(lsu_match_data_2, 17, 17) @[el2_lib.scala 244:88] + node _T_705 = eq(_T_703, _T_704) @[el2_lib.scala 244:80] + node _T_706 = mux(_T_702, UInt<1>("h01"), _T_705) @[el2_lib.scala 244:25] + _T_580[17] <= _T_706 @[el2_lib.scala 244:19] + node _T_707 = bits(io.trigger_pkt_any[2].tdata2, 17, 0) @[el2_lib.scala 244:30] + node _T_708 = andr(_T_707) @[el2_lib.scala 244:38] + node _T_709 = and(_T_708, _T_583) @[el2_lib.scala 244:43] + node _T_710 = bits(io.trigger_pkt_any[2].tdata2, 18, 18) @[el2_lib.scala 244:76] + node _T_711 = bits(lsu_match_data_2, 18, 18) @[el2_lib.scala 244:88] + node _T_712 = eq(_T_710, _T_711) @[el2_lib.scala 244:80] + node _T_713 = mux(_T_709, UInt<1>("h01"), _T_712) @[el2_lib.scala 244:25] + _T_580[18] <= _T_713 @[el2_lib.scala 244:19] + node _T_714 = bits(io.trigger_pkt_any[2].tdata2, 18, 0) @[el2_lib.scala 244:30] + node _T_715 = andr(_T_714) @[el2_lib.scala 244:38] + node _T_716 = and(_T_715, _T_583) @[el2_lib.scala 244:43] + node _T_717 = bits(io.trigger_pkt_any[2].tdata2, 19, 19) @[el2_lib.scala 244:76] + node _T_718 = bits(lsu_match_data_2, 19, 19) @[el2_lib.scala 244:88] + node _T_719 = eq(_T_717, _T_718) @[el2_lib.scala 244:80] + node _T_720 = mux(_T_716, UInt<1>("h01"), _T_719) @[el2_lib.scala 244:25] + _T_580[19] <= _T_720 @[el2_lib.scala 244:19] + node _T_721 = bits(io.trigger_pkt_any[2].tdata2, 19, 0) @[el2_lib.scala 244:30] + node _T_722 = andr(_T_721) @[el2_lib.scala 244:38] + node _T_723 = and(_T_722, _T_583) @[el2_lib.scala 244:43] + node _T_724 = bits(io.trigger_pkt_any[2].tdata2, 20, 20) @[el2_lib.scala 244:76] + node _T_725 = bits(lsu_match_data_2, 20, 20) @[el2_lib.scala 244:88] + node _T_726 = eq(_T_724, _T_725) @[el2_lib.scala 244:80] + node _T_727 = mux(_T_723, UInt<1>("h01"), _T_726) @[el2_lib.scala 244:25] + _T_580[20] <= _T_727 @[el2_lib.scala 244:19] + node _T_728 = bits(io.trigger_pkt_any[2].tdata2, 20, 0) @[el2_lib.scala 244:30] + node _T_729 = andr(_T_728) @[el2_lib.scala 244:38] + node _T_730 = and(_T_729, _T_583) @[el2_lib.scala 244:43] + node _T_731 = bits(io.trigger_pkt_any[2].tdata2, 21, 21) @[el2_lib.scala 244:76] + node _T_732 = bits(lsu_match_data_2, 21, 21) @[el2_lib.scala 244:88] + node _T_733 = eq(_T_731, _T_732) @[el2_lib.scala 244:80] + node _T_734 = mux(_T_730, UInt<1>("h01"), _T_733) @[el2_lib.scala 244:25] + _T_580[21] <= _T_734 @[el2_lib.scala 244:19] + node _T_735 = bits(io.trigger_pkt_any[2].tdata2, 21, 0) @[el2_lib.scala 244:30] + node _T_736 = andr(_T_735) @[el2_lib.scala 244:38] + node _T_737 = and(_T_736, _T_583) @[el2_lib.scala 244:43] + node _T_738 = bits(io.trigger_pkt_any[2].tdata2, 22, 22) @[el2_lib.scala 244:76] + node _T_739 = bits(lsu_match_data_2, 22, 22) @[el2_lib.scala 244:88] + node _T_740 = eq(_T_738, _T_739) @[el2_lib.scala 244:80] + node _T_741 = mux(_T_737, UInt<1>("h01"), _T_740) @[el2_lib.scala 244:25] + _T_580[22] <= _T_741 @[el2_lib.scala 244:19] + node _T_742 = bits(io.trigger_pkt_any[2].tdata2, 22, 0) @[el2_lib.scala 244:30] + node _T_743 = andr(_T_742) @[el2_lib.scala 244:38] + node _T_744 = and(_T_743, _T_583) @[el2_lib.scala 244:43] + node _T_745 = bits(io.trigger_pkt_any[2].tdata2, 23, 23) @[el2_lib.scala 244:76] + node _T_746 = bits(lsu_match_data_2, 23, 23) @[el2_lib.scala 244:88] + node _T_747 = eq(_T_745, _T_746) @[el2_lib.scala 244:80] + node _T_748 = mux(_T_744, UInt<1>("h01"), _T_747) @[el2_lib.scala 244:25] + _T_580[23] <= _T_748 @[el2_lib.scala 244:19] + node _T_749 = bits(io.trigger_pkt_any[2].tdata2, 23, 0) @[el2_lib.scala 244:30] + node _T_750 = andr(_T_749) @[el2_lib.scala 244:38] + node _T_751 = and(_T_750, _T_583) @[el2_lib.scala 244:43] + node _T_752 = bits(io.trigger_pkt_any[2].tdata2, 24, 24) @[el2_lib.scala 244:76] + node _T_753 = bits(lsu_match_data_2, 24, 24) @[el2_lib.scala 244:88] + node _T_754 = eq(_T_752, _T_753) @[el2_lib.scala 244:80] + node _T_755 = mux(_T_751, UInt<1>("h01"), _T_754) @[el2_lib.scala 244:25] + _T_580[24] <= _T_755 @[el2_lib.scala 244:19] + node _T_756 = bits(io.trigger_pkt_any[2].tdata2, 24, 0) @[el2_lib.scala 244:30] + node _T_757 = andr(_T_756) @[el2_lib.scala 244:38] + node _T_758 = and(_T_757, _T_583) @[el2_lib.scala 244:43] + node _T_759 = bits(io.trigger_pkt_any[2].tdata2, 25, 25) @[el2_lib.scala 244:76] + node _T_760 = bits(lsu_match_data_2, 25, 25) @[el2_lib.scala 244:88] + node _T_761 = eq(_T_759, _T_760) @[el2_lib.scala 244:80] + node _T_762 = mux(_T_758, UInt<1>("h01"), _T_761) @[el2_lib.scala 244:25] + _T_580[25] <= _T_762 @[el2_lib.scala 244:19] + node _T_763 = bits(io.trigger_pkt_any[2].tdata2, 25, 0) @[el2_lib.scala 244:30] + node _T_764 = andr(_T_763) @[el2_lib.scala 244:38] + node _T_765 = and(_T_764, _T_583) @[el2_lib.scala 244:43] + node _T_766 = bits(io.trigger_pkt_any[2].tdata2, 26, 26) @[el2_lib.scala 244:76] + node _T_767 = bits(lsu_match_data_2, 26, 26) @[el2_lib.scala 244:88] + node _T_768 = eq(_T_766, _T_767) @[el2_lib.scala 244:80] + node _T_769 = mux(_T_765, UInt<1>("h01"), _T_768) @[el2_lib.scala 244:25] + _T_580[26] <= _T_769 @[el2_lib.scala 244:19] + node _T_770 = bits(io.trigger_pkt_any[2].tdata2, 26, 0) @[el2_lib.scala 244:30] + node _T_771 = andr(_T_770) @[el2_lib.scala 244:38] + node _T_772 = and(_T_771, _T_583) @[el2_lib.scala 244:43] + node _T_773 = bits(io.trigger_pkt_any[2].tdata2, 27, 27) @[el2_lib.scala 244:76] + node _T_774 = bits(lsu_match_data_2, 27, 27) @[el2_lib.scala 244:88] + node _T_775 = eq(_T_773, _T_774) @[el2_lib.scala 244:80] + node _T_776 = mux(_T_772, UInt<1>("h01"), _T_775) @[el2_lib.scala 244:25] + _T_580[27] <= _T_776 @[el2_lib.scala 244:19] + node _T_777 = bits(io.trigger_pkt_any[2].tdata2, 27, 0) @[el2_lib.scala 244:30] + node _T_778 = andr(_T_777) @[el2_lib.scala 244:38] + node _T_779 = and(_T_778, _T_583) @[el2_lib.scala 244:43] + node _T_780 = bits(io.trigger_pkt_any[2].tdata2, 28, 28) @[el2_lib.scala 244:76] + node _T_781 = bits(lsu_match_data_2, 28, 28) @[el2_lib.scala 244:88] + node _T_782 = eq(_T_780, _T_781) @[el2_lib.scala 244:80] + node _T_783 = mux(_T_779, UInt<1>("h01"), _T_782) @[el2_lib.scala 244:25] + _T_580[28] <= _T_783 @[el2_lib.scala 244:19] + node _T_784 = bits(io.trigger_pkt_any[2].tdata2, 28, 0) @[el2_lib.scala 244:30] + node _T_785 = andr(_T_784) @[el2_lib.scala 244:38] + node _T_786 = and(_T_785, _T_583) @[el2_lib.scala 244:43] + node _T_787 = bits(io.trigger_pkt_any[2].tdata2, 29, 29) @[el2_lib.scala 244:76] + node _T_788 = bits(lsu_match_data_2, 29, 29) @[el2_lib.scala 244:88] + node _T_789 = eq(_T_787, _T_788) @[el2_lib.scala 244:80] + node _T_790 = mux(_T_786, UInt<1>("h01"), _T_789) @[el2_lib.scala 244:25] + _T_580[29] <= _T_790 @[el2_lib.scala 244:19] + node _T_791 = bits(io.trigger_pkt_any[2].tdata2, 29, 0) @[el2_lib.scala 244:30] + node _T_792 = andr(_T_791) @[el2_lib.scala 244:38] + node _T_793 = and(_T_792, _T_583) @[el2_lib.scala 244:43] + node _T_794 = bits(io.trigger_pkt_any[2].tdata2, 30, 30) @[el2_lib.scala 244:76] + node _T_795 = bits(lsu_match_data_2, 30, 30) @[el2_lib.scala 244:88] + node _T_796 = eq(_T_794, _T_795) @[el2_lib.scala 244:80] + node _T_797 = mux(_T_793, UInt<1>("h01"), _T_796) @[el2_lib.scala 244:25] + _T_580[30] <= _T_797 @[el2_lib.scala 244:19] + node _T_798 = bits(io.trigger_pkt_any[2].tdata2, 30, 0) @[el2_lib.scala 244:30] + node _T_799 = andr(_T_798) @[el2_lib.scala 244:38] + node _T_800 = and(_T_799, _T_583) @[el2_lib.scala 244:43] + node _T_801 = bits(io.trigger_pkt_any[2].tdata2, 31, 31) @[el2_lib.scala 244:76] + node _T_802 = bits(lsu_match_data_2, 31, 31) @[el2_lib.scala 244:88] + node _T_803 = eq(_T_801, _T_802) @[el2_lib.scala 244:80] + node _T_804 = mux(_T_800, UInt<1>("h01"), _T_803) @[el2_lib.scala 244:25] + _T_580[31] <= _T_804 @[el2_lib.scala 244:19] + node _T_805 = cat(_T_580[1], _T_580[0]) @[el2_lib.scala 245:14] + node _T_806 = cat(_T_580[3], _T_580[2]) @[el2_lib.scala 245:14] + node _T_807 = cat(_T_806, _T_805) @[el2_lib.scala 245:14] + node _T_808 = cat(_T_580[5], _T_580[4]) @[el2_lib.scala 245:14] + node _T_809 = cat(_T_580[7], _T_580[6]) @[el2_lib.scala 245:14] + node _T_810 = cat(_T_809, _T_808) @[el2_lib.scala 245:14] + node _T_811 = cat(_T_810, _T_807) @[el2_lib.scala 245:14] + node _T_812 = cat(_T_580[9], _T_580[8]) @[el2_lib.scala 245:14] + node _T_813 = cat(_T_580[11], _T_580[10]) @[el2_lib.scala 245:14] + node _T_814 = cat(_T_813, _T_812) @[el2_lib.scala 245:14] + node _T_815 = cat(_T_580[13], _T_580[12]) @[el2_lib.scala 245:14] + node _T_816 = cat(_T_580[15], _T_580[14]) @[el2_lib.scala 245:14] + node _T_817 = cat(_T_816, _T_815) @[el2_lib.scala 245:14] + node _T_818 = cat(_T_817, _T_814) @[el2_lib.scala 245:14] + node _T_819 = cat(_T_818, _T_811) @[el2_lib.scala 245:14] + node _T_820 = cat(_T_580[17], _T_580[16]) @[el2_lib.scala 245:14] + node _T_821 = cat(_T_580[19], _T_580[18]) @[el2_lib.scala 245:14] + node _T_822 = cat(_T_821, _T_820) @[el2_lib.scala 245:14] + node _T_823 = cat(_T_580[21], _T_580[20]) @[el2_lib.scala 245:14] + node _T_824 = cat(_T_580[23], _T_580[22]) @[el2_lib.scala 245:14] + node _T_825 = cat(_T_824, _T_823) @[el2_lib.scala 245:14] + node _T_826 = cat(_T_825, _T_822) @[el2_lib.scala 245:14] + node _T_827 = cat(_T_580[25], _T_580[24]) @[el2_lib.scala 245:14] + node _T_828 = cat(_T_580[27], _T_580[26]) @[el2_lib.scala 245:14] + node _T_829 = cat(_T_828, _T_827) @[el2_lib.scala 245:14] + node _T_830 = cat(_T_580[29], _T_580[28]) @[el2_lib.scala 245:14] + node _T_831 = cat(_T_580[31], _T_580[30]) @[el2_lib.scala 245:14] + node _T_832 = cat(_T_831, _T_830) @[el2_lib.scala 245:14] + node _T_833 = cat(_T_832, _T_829) @[el2_lib.scala 245:14] + node _T_834 = cat(_T_833, _T_826) @[el2_lib.scala 245:14] + node _T_835 = cat(_T_834, _T_819) @[el2_lib.scala 245:14] + node _T_836 = and(_T_578, _T_835) @[el2_lsu_trigger.scala 19:87] + node _T_837 = eq(io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu_trigger.scala 18:71] + node _T_838 = and(io.lsu_pkt_m.valid, _T_837) @[el2_lsu_trigger.scala 18:69] + node _T_839 = and(io.trigger_pkt_any[3].store, io.lsu_pkt_m.store) @[el2_lsu_trigger.scala 18:121] + node _T_840 = and(io.trigger_pkt_any[3].load, io.lsu_pkt_m.load) @[el2_lsu_trigger.scala 19:33] + node _T_841 = eq(io.trigger_pkt_any[3].select, UInt<1>("h00")) @[el2_lsu_trigger.scala 19:55] + node _T_842 = and(_T_840, _T_841) @[el2_lsu_trigger.scala 19:53] + node _T_843 = or(_T_839, _T_842) @[el2_lsu_trigger.scala 18:142] + node _T_844 = and(_T_838, _T_843) @[el2_lsu_trigger.scala 18:89] + node _T_845 = bits(io.trigger_pkt_any[3].match_, 0, 0) @[el2_lsu_trigger.scala 20:104] + wire _T_846 : UInt<1>[32] @[el2_lib.scala 240:24] + node _T_847 = andr(io.trigger_pkt_any[3].tdata2) @[el2_lib.scala 241:45] + node _T_848 = not(_T_847) @[el2_lib.scala 241:39] + node _T_849 = and(_T_845, _T_848) @[el2_lib.scala 241:37] + node _T_850 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 242:48] + node _T_851 = bits(lsu_match_data_3, 0, 0) @[el2_lib.scala 242:60] + node _T_852 = eq(_T_850, _T_851) @[el2_lib.scala 242:52] + node _T_853 = or(_T_849, _T_852) @[el2_lib.scala 242:41] + _T_846[0] <= _T_853 @[el2_lib.scala 242:18] + node _T_854 = bits(io.trigger_pkt_any[3].tdata2, 0, 0) @[el2_lib.scala 244:30] + node _T_855 = andr(_T_854) @[el2_lib.scala 244:38] + node _T_856 = and(_T_855, _T_849) @[el2_lib.scala 244:43] + node _T_857 = bits(io.trigger_pkt_any[3].tdata2, 1, 1) @[el2_lib.scala 244:76] + node _T_858 = bits(lsu_match_data_3, 1, 1) @[el2_lib.scala 244:88] + node _T_859 = eq(_T_857, _T_858) @[el2_lib.scala 244:80] + node _T_860 = mux(_T_856, UInt<1>("h01"), _T_859) @[el2_lib.scala 244:25] + _T_846[1] <= _T_860 @[el2_lib.scala 244:19] + node _T_861 = bits(io.trigger_pkt_any[3].tdata2, 1, 0) @[el2_lib.scala 244:30] + node _T_862 = andr(_T_861) @[el2_lib.scala 244:38] + node _T_863 = and(_T_862, _T_849) @[el2_lib.scala 244:43] + node _T_864 = bits(io.trigger_pkt_any[3].tdata2, 2, 2) @[el2_lib.scala 244:76] + node _T_865 = bits(lsu_match_data_3, 2, 2) @[el2_lib.scala 244:88] + node _T_866 = eq(_T_864, _T_865) @[el2_lib.scala 244:80] + node _T_867 = mux(_T_863, UInt<1>("h01"), _T_866) @[el2_lib.scala 244:25] + _T_846[2] <= _T_867 @[el2_lib.scala 244:19] + node _T_868 = bits(io.trigger_pkt_any[3].tdata2, 2, 0) @[el2_lib.scala 244:30] + node _T_869 = andr(_T_868) @[el2_lib.scala 244:38] + node _T_870 = and(_T_869, _T_849) @[el2_lib.scala 244:43] + node _T_871 = bits(io.trigger_pkt_any[3].tdata2, 3, 3) @[el2_lib.scala 244:76] + node _T_872 = bits(lsu_match_data_3, 3, 3) @[el2_lib.scala 244:88] + node _T_873 = eq(_T_871, _T_872) @[el2_lib.scala 244:80] + node _T_874 = mux(_T_870, UInt<1>("h01"), _T_873) @[el2_lib.scala 244:25] + _T_846[3] <= _T_874 @[el2_lib.scala 244:19] + node _T_875 = bits(io.trigger_pkt_any[3].tdata2, 3, 0) @[el2_lib.scala 244:30] + node _T_876 = andr(_T_875) @[el2_lib.scala 244:38] + node _T_877 = and(_T_876, _T_849) @[el2_lib.scala 244:43] + node _T_878 = bits(io.trigger_pkt_any[3].tdata2, 4, 4) @[el2_lib.scala 244:76] + node _T_879 = bits(lsu_match_data_3, 4, 4) @[el2_lib.scala 244:88] + node _T_880 = eq(_T_878, _T_879) @[el2_lib.scala 244:80] + node _T_881 = mux(_T_877, UInt<1>("h01"), _T_880) @[el2_lib.scala 244:25] + _T_846[4] <= _T_881 @[el2_lib.scala 244:19] + node _T_882 = bits(io.trigger_pkt_any[3].tdata2, 4, 0) @[el2_lib.scala 244:30] + node _T_883 = andr(_T_882) @[el2_lib.scala 244:38] + node _T_884 = and(_T_883, _T_849) @[el2_lib.scala 244:43] + node _T_885 = bits(io.trigger_pkt_any[3].tdata2, 5, 5) @[el2_lib.scala 244:76] + node _T_886 = bits(lsu_match_data_3, 5, 5) @[el2_lib.scala 244:88] + node _T_887 = eq(_T_885, _T_886) @[el2_lib.scala 244:80] + node _T_888 = mux(_T_884, UInt<1>("h01"), _T_887) @[el2_lib.scala 244:25] + _T_846[5] <= _T_888 @[el2_lib.scala 244:19] + node _T_889 = bits(io.trigger_pkt_any[3].tdata2, 5, 0) @[el2_lib.scala 244:30] + node _T_890 = andr(_T_889) @[el2_lib.scala 244:38] + node _T_891 = and(_T_890, _T_849) @[el2_lib.scala 244:43] + node _T_892 = bits(io.trigger_pkt_any[3].tdata2, 6, 6) @[el2_lib.scala 244:76] + node _T_893 = bits(lsu_match_data_3, 6, 6) @[el2_lib.scala 244:88] + node _T_894 = eq(_T_892, _T_893) @[el2_lib.scala 244:80] + node _T_895 = mux(_T_891, UInt<1>("h01"), _T_894) @[el2_lib.scala 244:25] + _T_846[6] <= _T_895 @[el2_lib.scala 244:19] + node _T_896 = bits(io.trigger_pkt_any[3].tdata2, 6, 0) @[el2_lib.scala 244:30] + node _T_897 = andr(_T_896) @[el2_lib.scala 244:38] + node _T_898 = and(_T_897, _T_849) @[el2_lib.scala 244:43] + node _T_899 = bits(io.trigger_pkt_any[3].tdata2, 7, 7) @[el2_lib.scala 244:76] + node _T_900 = bits(lsu_match_data_3, 7, 7) @[el2_lib.scala 244:88] + node _T_901 = eq(_T_899, _T_900) @[el2_lib.scala 244:80] + node _T_902 = mux(_T_898, UInt<1>("h01"), _T_901) @[el2_lib.scala 244:25] + _T_846[7] <= _T_902 @[el2_lib.scala 244:19] + node _T_903 = bits(io.trigger_pkt_any[3].tdata2, 7, 0) @[el2_lib.scala 244:30] + node _T_904 = andr(_T_903) @[el2_lib.scala 244:38] + node _T_905 = and(_T_904, _T_849) @[el2_lib.scala 244:43] + node _T_906 = bits(io.trigger_pkt_any[3].tdata2, 8, 8) @[el2_lib.scala 244:76] + node _T_907 = bits(lsu_match_data_3, 8, 8) @[el2_lib.scala 244:88] + node _T_908 = eq(_T_906, _T_907) @[el2_lib.scala 244:80] + node _T_909 = mux(_T_905, UInt<1>("h01"), _T_908) @[el2_lib.scala 244:25] + _T_846[8] <= _T_909 @[el2_lib.scala 244:19] + node _T_910 = bits(io.trigger_pkt_any[3].tdata2, 8, 0) @[el2_lib.scala 244:30] + node _T_911 = andr(_T_910) @[el2_lib.scala 244:38] + node _T_912 = and(_T_911, _T_849) @[el2_lib.scala 244:43] + node _T_913 = bits(io.trigger_pkt_any[3].tdata2, 9, 9) @[el2_lib.scala 244:76] + node _T_914 = bits(lsu_match_data_3, 9, 9) @[el2_lib.scala 244:88] + node _T_915 = eq(_T_913, _T_914) @[el2_lib.scala 244:80] + node _T_916 = mux(_T_912, UInt<1>("h01"), _T_915) @[el2_lib.scala 244:25] + _T_846[9] <= _T_916 @[el2_lib.scala 244:19] + node _T_917 = bits(io.trigger_pkt_any[3].tdata2, 9, 0) @[el2_lib.scala 244:30] + node _T_918 = andr(_T_917) @[el2_lib.scala 244:38] + node _T_919 = and(_T_918, _T_849) @[el2_lib.scala 244:43] + node _T_920 = bits(io.trigger_pkt_any[3].tdata2, 10, 10) @[el2_lib.scala 244:76] + node _T_921 = bits(lsu_match_data_3, 10, 10) @[el2_lib.scala 244:88] + node _T_922 = eq(_T_920, _T_921) @[el2_lib.scala 244:80] + node _T_923 = mux(_T_919, UInt<1>("h01"), _T_922) @[el2_lib.scala 244:25] + _T_846[10] <= _T_923 @[el2_lib.scala 244:19] + node _T_924 = bits(io.trigger_pkt_any[3].tdata2, 10, 0) @[el2_lib.scala 244:30] + node _T_925 = andr(_T_924) @[el2_lib.scala 244:38] + node _T_926 = and(_T_925, _T_849) @[el2_lib.scala 244:43] + node _T_927 = bits(io.trigger_pkt_any[3].tdata2, 11, 11) @[el2_lib.scala 244:76] + node _T_928 = bits(lsu_match_data_3, 11, 11) @[el2_lib.scala 244:88] + node _T_929 = eq(_T_927, _T_928) @[el2_lib.scala 244:80] + node _T_930 = mux(_T_926, UInt<1>("h01"), _T_929) @[el2_lib.scala 244:25] + _T_846[11] <= _T_930 @[el2_lib.scala 244:19] + node _T_931 = bits(io.trigger_pkt_any[3].tdata2, 11, 0) @[el2_lib.scala 244:30] + node _T_932 = andr(_T_931) @[el2_lib.scala 244:38] + node _T_933 = and(_T_932, _T_849) @[el2_lib.scala 244:43] + node _T_934 = bits(io.trigger_pkt_any[3].tdata2, 12, 12) @[el2_lib.scala 244:76] + node _T_935 = bits(lsu_match_data_3, 12, 12) @[el2_lib.scala 244:88] + node _T_936 = eq(_T_934, _T_935) @[el2_lib.scala 244:80] + node _T_937 = mux(_T_933, UInt<1>("h01"), _T_936) @[el2_lib.scala 244:25] + _T_846[12] <= _T_937 @[el2_lib.scala 244:19] + node _T_938 = bits(io.trigger_pkt_any[3].tdata2, 12, 0) @[el2_lib.scala 244:30] + node _T_939 = andr(_T_938) @[el2_lib.scala 244:38] + node _T_940 = and(_T_939, _T_849) @[el2_lib.scala 244:43] + node _T_941 = bits(io.trigger_pkt_any[3].tdata2, 13, 13) @[el2_lib.scala 244:76] + node _T_942 = bits(lsu_match_data_3, 13, 13) @[el2_lib.scala 244:88] + node _T_943 = eq(_T_941, _T_942) @[el2_lib.scala 244:80] + node _T_944 = mux(_T_940, UInt<1>("h01"), _T_943) @[el2_lib.scala 244:25] + _T_846[13] <= _T_944 @[el2_lib.scala 244:19] + node _T_945 = bits(io.trigger_pkt_any[3].tdata2, 13, 0) @[el2_lib.scala 244:30] + node _T_946 = andr(_T_945) @[el2_lib.scala 244:38] + node _T_947 = and(_T_946, _T_849) @[el2_lib.scala 244:43] + node _T_948 = bits(io.trigger_pkt_any[3].tdata2, 14, 14) @[el2_lib.scala 244:76] + node _T_949 = bits(lsu_match_data_3, 14, 14) @[el2_lib.scala 244:88] + node _T_950 = eq(_T_948, _T_949) @[el2_lib.scala 244:80] + node _T_951 = mux(_T_947, UInt<1>("h01"), _T_950) @[el2_lib.scala 244:25] + _T_846[14] <= _T_951 @[el2_lib.scala 244:19] + node _T_952 = bits(io.trigger_pkt_any[3].tdata2, 14, 0) @[el2_lib.scala 244:30] + node _T_953 = andr(_T_952) @[el2_lib.scala 244:38] + node _T_954 = and(_T_953, _T_849) @[el2_lib.scala 244:43] + node _T_955 = bits(io.trigger_pkt_any[3].tdata2, 15, 15) @[el2_lib.scala 244:76] + node _T_956 = bits(lsu_match_data_3, 15, 15) @[el2_lib.scala 244:88] + node _T_957 = eq(_T_955, _T_956) @[el2_lib.scala 244:80] + node _T_958 = mux(_T_954, UInt<1>("h01"), _T_957) @[el2_lib.scala 244:25] + _T_846[15] <= _T_958 @[el2_lib.scala 244:19] + node _T_959 = bits(io.trigger_pkt_any[3].tdata2, 15, 0) @[el2_lib.scala 244:30] + node _T_960 = andr(_T_959) @[el2_lib.scala 244:38] + node _T_961 = and(_T_960, _T_849) @[el2_lib.scala 244:43] + node _T_962 = bits(io.trigger_pkt_any[3].tdata2, 16, 16) @[el2_lib.scala 244:76] + node _T_963 = bits(lsu_match_data_3, 16, 16) @[el2_lib.scala 244:88] + node _T_964 = eq(_T_962, _T_963) @[el2_lib.scala 244:80] + node _T_965 = mux(_T_961, UInt<1>("h01"), _T_964) @[el2_lib.scala 244:25] + _T_846[16] <= _T_965 @[el2_lib.scala 244:19] + node _T_966 = bits(io.trigger_pkt_any[3].tdata2, 16, 0) @[el2_lib.scala 244:30] + node _T_967 = andr(_T_966) @[el2_lib.scala 244:38] + node _T_968 = and(_T_967, _T_849) @[el2_lib.scala 244:43] + node _T_969 = bits(io.trigger_pkt_any[3].tdata2, 17, 17) @[el2_lib.scala 244:76] + node _T_970 = bits(lsu_match_data_3, 17, 17) @[el2_lib.scala 244:88] + node _T_971 = eq(_T_969, _T_970) @[el2_lib.scala 244:80] + node _T_972 = mux(_T_968, UInt<1>("h01"), _T_971) @[el2_lib.scala 244:25] + _T_846[17] <= _T_972 @[el2_lib.scala 244:19] + node _T_973 = bits(io.trigger_pkt_any[3].tdata2, 17, 0) @[el2_lib.scala 244:30] + node _T_974 = andr(_T_973) @[el2_lib.scala 244:38] + node _T_975 = and(_T_974, _T_849) @[el2_lib.scala 244:43] + node _T_976 = bits(io.trigger_pkt_any[3].tdata2, 18, 18) @[el2_lib.scala 244:76] + node _T_977 = bits(lsu_match_data_3, 18, 18) @[el2_lib.scala 244:88] + node _T_978 = eq(_T_976, _T_977) @[el2_lib.scala 244:80] + node _T_979 = mux(_T_975, UInt<1>("h01"), _T_978) @[el2_lib.scala 244:25] + _T_846[18] <= _T_979 @[el2_lib.scala 244:19] + node _T_980 = bits(io.trigger_pkt_any[3].tdata2, 18, 0) @[el2_lib.scala 244:30] + node _T_981 = andr(_T_980) @[el2_lib.scala 244:38] + node _T_982 = and(_T_981, _T_849) @[el2_lib.scala 244:43] + node _T_983 = bits(io.trigger_pkt_any[3].tdata2, 19, 19) @[el2_lib.scala 244:76] + node _T_984 = bits(lsu_match_data_3, 19, 19) @[el2_lib.scala 244:88] + node _T_985 = eq(_T_983, _T_984) @[el2_lib.scala 244:80] + node _T_986 = mux(_T_982, UInt<1>("h01"), _T_985) @[el2_lib.scala 244:25] + _T_846[19] <= _T_986 @[el2_lib.scala 244:19] + node _T_987 = bits(io.trigger_pkt_any[3].tdata2, 19, 0) @[el2_lib.scala 244:30] + node _T_988 = andr(_T_987) @[el2_lib.scala 244:38] + node _T_989 = and(_T_988, _T_849) @[el2_lib.scala 244:43] + node _T_990 = bits(io.trigger_pkt_any[3].tdata2, 20, 20) @[el2_lib.scala 244:76] + node _T_991 = bits(lsu_match_data_3, 20, 20) @[el2_lib.scala 244:88] + node _T_992 = eq(_T_990, _T_991) @[el2_lib.scala 244:80] + node _T_993 = mux(_T_989, UInt<1>("h01"), _T_992) @[el2_lib.scala 244:25] + _T_846[20] <= _T_993 @[el2_lib.scala 244:19] + node _T_994 = bits(io.trigger_pkt_any[3].tdata2, 20, 0) @[el2_lib.scala 244:30] + node _T_995 = andr(_T_994) @[el2_lib.scala 244:38] + node _T_996 = and(_T_995, _T_849) @[el2_lib.scala 244:43] + node _T_997 = bits(io.trigger_pkt_any[3].tdata2, 21, 21) @[el2_lib.scala 244:76] + node _T_998 = bits(lsu_match_data_3, 21, 21) @[el2_lib.scala 244:88] + node _T_999 = eq(_T_997, _T_998) @[el2_lib.scala 244:80] + node _T_1000 = mux(_T_996, UInt<1>("h01"), _T_999) @[el2_lib.scala 244:25] + _T_846[21] <= _T_1000 @[el2_lib.scala 244:19] + node _T_1001 = bits(io.trigger_pkt_any[3].tdata2, 21, 0) @[el2_lib.scala 244:30] + node _T_1002 = andr(_T_1001) @[el2_lib.scala 244:38] + node _T_1003 = and(_T_1002, _T_849) @[el2_lib.scala 244:43] + node _T_1004 = bits(io.trigger_pkt_any[3].tdata2, 22, 22) @[el2_lib.scala 244:76] + node _T_1005 = bits(lsu_match_data_3, 22, 22) @[el2_lib.scala 244:88] + node _T_1006 = eq(_T_1004, _T_1005) @[el2_lib.scala 244:80] + node _T_1007 = mux(_T_1003, UInt<1>("h01"), _T_1006) @[el2_lib.scala 244:25] + _T_846[22] <= _T_1007 @[el2_lib.scala 244:19] + node _T_1008 = bits(io.trigger_pkt_any[3].tdata2, 22, 0) @[el2_lib.scala 244:30] + node _T_1009 = andr(_T_1008) @[el2_lib.scala 244:38] + node _T_1010 = and(_T_1009, _T_849) @[el2_lib.scala 244:43] + node _T_1011 = bits(io.trigger_pkt_any[3].tdata2, 23, 23) @[el2_lib.scala 244:76] + node _T_1012 = bits(lsu_match_data_3, 23, 23) @[el2_lib.scala 244:88] + node _T_1013 = eq(_T_1011, _T_1012) @[el2_lib.scala 244:80] + node _T_1014 = mux(_T_1010, UInt<1>("h01"), _T_1013) @[el2_lib.scala 244:25] + _T_846[23] <= _T_1014 @[el2_lib.scala 244:19] + node _T_1015 = bits(io.trigger_pkt_any[3].tdata2, 23, 0) @[el2_lib.scala 244:30] + node _T_1016 = andr(_T_1015) @[el2_lib.scala 244:38] + node _T_1017 = and(_T_1016, _T_849) @[el2_lib.scala 244:43] + node _T_1018 = bits(io.trigger_pkt_any[3].tdata2, 24, 24) @[el2_lib.scala 244:76] + node _T_1019 = bits(lsu_match_data_3, 24, 24) @[el2_lib.scala 244:88] + node _T_1020 = eq(_T_1018, _T_1019) @[el2_lib.scala 244:80] + node _T_1021 = mux(_T_1017, UInt<1>("h01"), _T_1020) @[el2_lib.scala 244:25] + _T_846[24] <= _T_1021 @[el2_lib.scala 244:19] + node _T_1022 = bits(io.trigger_pkt_any[3].tdata2, 24, 0) @[el2_lib.scala 244:30] + node _T_1023 = andr(_T_1022) @[el2_lib.scala 244:38] + node _T_1024 = and(_T_1023, _T_849) @[el2_lib.scala 244:43] + node _T_1025 = bits(io.trigger_pkt_any[3].tdata2, 25, 25) @[el2_lib.scala 244:76] + node _T_1026 = bits(lsu_match_data_3, 25, 25) @[el2_lib.scala 244:88] + node _T_1027 = eq(_T_1025, _T_1026) @[el2_lib.scala 244:80] + node _T_1028 = mux(_T_1024, UInt<1>("h01"), _T_1027) @[el2_lib.scala 244:25] + _T_846[25] <= _T_1028 @[el2_lib.scala 244:19] + node _T_1029 = bits(io.trigger_pkt_any[3].tdata2, 25, 0) @[el2_lib.scala 244:30] + node _T_1030 = andr(_T_1029) @[el2_lib.scala 244:38] + node _T_1031 = and(_T_1030, _T_849) @[el2_lib.scala 244:43] + node _T_1032 = bits(io.trigger_pkt_any[3].tdata2, 26, 26) @[el2_lib.scala 244:76] + node _T_1033 = bits(lsu_match_data_3, 26, 26) @[el2_lib.scala 244:88] + node _T_1034 = eq(_T_1032, _T_1033) @[el2_lib.scala 244:80] + node _T_1035 = mux(_T_1031, UInt<1>("h01"), _T_1034) @[el2_lib.scala 244:25] + _T_846[26] <= _T_1035 @[el2_lib.scala 244:19] + node _T_1036 = bits(io.trigger_pkt_any[3].tdata2, 26, 0) @[el2_lib.scala 244:30] + node _T_1037 = andr(_T_1036) @[el2_lib.scala 244:38] + node _T_1038 = and(_T_1037, _T_849) @[el2_lib.scala 244:43] + node _T_1039 = bits(io.trigger_pkt_any[3].tdata2, 27, 27) @[el2_lib.scala 244:76] + node _T_1040 = bits(lsu_match_data_3, 27, 27) @[el2_lib.scala 244:88] + node _T_1041 = eq(_T_1039, _T_1040) @[el2_lib.scala 244:80] + node _T_1042 = mux(_T_1038, UInt<1>("h01"), _T_1041) @[el2_lib.scala 244:25] + _T_846[27] <= _T_1042 @[el2_lib.scala 244:19] + node _T_1043 = bits(io.trigger_pkt_any[3].tdata2, 27, 0) @[el2_lib.scala 244:30] + node _T_1044 = andr(_T_1043) @[el2_lib.scala 244:38] + node _T_1045 = and(_T_1044, _T_849) @[el2_lib.scala 244:43] + node _T_1046 = bits(io.trigger_pkt_any[3].tdata2, 28, 28) @[el2_lib.scala 244:76] + node _T_1047 = bits(lsu_match_data_3, 28, 28) @[el2_lib.scala 244:88] + node _T_1048 = eq(_T_1046, _T_1047) @[el2_lib.scala 244:80] + node _T_1049 = mux(_T_1045, UInt<1>("h01"), _T_1048) @[el2_lib.scala 244:25] + _T_846[28] <= _T_1049 @[el2_lib.scala 244:19] + node _T_1050 = bits(io.trigger_pkt_any[3].tdata2, 28, 0) @[el2_lib.scala 244:30] + node _T_1051 = andr(_T_1050) @[el2_lib.scala 244:38] + node _T_1052 = and(_T_1051, _T_849) @[el2_lib.scala 244:43] + node _T_1053 = bits(io.trigger_pkt_any[3].tdata2, 29, 29) @[el2_lib.scala 244:76] + node _T_1054 = bits(lsu_match_data_3, 29, 29) @[el2_lib.scala 244:88] + node _T_1055 = eq(_T_1053, _T_1054) @[el2_lib.scala 244:80] + node _T_1056 = mux(_T_1052, UInt<1>("h01"), _T_1055) @[el2_lib.scala 244:25] + _T_846[29] <= _T_1056 @[el2_lib.scala 244:19] + node _T_1057 = bits(io.trigger_pkt_any[3].tdata2, 29, 0) @[el2_lib.scala 244:30] + node _T_1058 = andr(_T_1057) @[el2_lib.scala 244:38] + node _T_1059 = and(_T_1058, _T_849) @[el2_lib.scala 244:43] + node _T_1060 = bits(io.trigger_pkt_any[3].tdata2, 30, 30) @[el2_lib.scala 244:76] + node _T_1061 = bits(lsu_match_data_3, 30, 30) @[el2_lib.scala 244:88] + node _T_1062 = eq(_T_1060, _T_1061) @[el2_lib.scala 244:80] + node _T_1063 = mux(_T_1059, UInt<1>("h01"), _T_1062) @[el2_lib.scala 244:25] + _T_846[30] <= _T_1063 @[el2_lib.scala 244:19] + node _T_1064 = bits(io.trigger_pkt_any[3].tdata2, 30, 0) @[el2_lib.scala 244:30] + node _T_1065 = andr(_T_1064) @[el2_lib.scala 244:38] + node _T_1066 = and(_T_1065, _T_849) @[el2_lib.scala 244:43] + node _T_1067 = bits(io.trigger_pkt_any[3].tdata2, 31, 31) @[el2_lib.scala 244:76] + node _T_1068 = bits(lsu_match_data_3, 31, 31) @[el2_lib.scala 244:88] + node _T_1069 = eq(_T_1067, _T_1068) @[el2_lib.scala 244:80] + node _T_1070 = mux(_T_1066, UInt<1>("h01"), _T_1069) @[el2_lib.scala 244:25] + _T_846[31] <= _T_1070 @[el2_lib.scala 244:19] + node _T_1071 = cat(_T_846[1], _T_846[0]) @[el2_lib.scala 245:14] + node _T_1072 = cat(_T_846[3], _T_846[2]) @[el2_lib.scala 245:14] + node _T_1073 = cat(_T_1072, _T_1071) @[el2_lib.scala 245:14] + node _T_1074 = cat(_T_846[5], _T_846[4]) @[el2_lib.scala 245:14] + node _T_1075 = cat(_T_846[7], _T_846[6]) @[el2_lib.scala 245:14] + node _T_1076 = cat(_T_1075, _T_1074) @[el2_lib.scala 245:14] + node _T_1077 = cat(_T_1076, _T_1073) @[el2_lib.scala 245:14] + node _T_1078 = cat(_T_846[9], _T_846[8]) @[el2_lib.scala 245:14] + node _T_1079 = cat(_T_846[11], _T_846[10]) @[el2_lib.scala 245:14] + node _T_1080 = cat(_T_1079, _T_1078) @[el2_lib.scala 245:14] + node _T_1081 = cat(_T_846[13], _T_846[12]) @[el2_lib.scala 245:14] + node _T_1082 = cat(_T_846[15], _T_846[14]) @[el2_lib.scala 245:14] + node _T_1083 = cat(_T_1082, _T_1081) @[el2_lib.scala 245:14] + node _T_1084 = cat(_T_1083, _T_1080) @[el2_lib.scala 245:14] + node _T_1085 = cat(_T_1084, _T_1077) @[el2_lib.scala 245:14] + node _T_1086 = cat(_T_846[17], _T_846[16]) @[el2_lib.scala 245:14] + node _T_1087 = cat(_T_846[19], _T_846[18]) @[el2_lib.scala 245:14] + node _T_1088 = cat(_T_1087, _T_1086) @[el2_lib.scala 245:14] + node _T_1089 = cat(_T_846[21], _T_846[20]) @[el2_lib.scala 245:14] + node _T_1090 = cat(_T_846[23], _T_846[22]) @[el2_lib.scala 245:14] + node _T_1091 = cat(_T_1090, _T_1089) @[el2_lib.scala 245:14] + node _T_1092 = cat(_T_1091, _T_1088) @[el2_lib.scala 245:14] + node _T_1093 = cat(_T_846[25], _T_846[24]) @[el2_lib.scala 245:14] + node _T_1094 = cat(_T_846[27], _T_846[26]) @[el2_lib.scala 245:14] + node _T_1095 = cat(_T_1094, _T_1093) @[el2_lib.scala 245:14] + node _T_1096 = cat(_T_846[29], _T_846[28]) @[el2_lib.scala 245:14] + node _T_1097 = cat(_T_846[31], _T_846[30]) @[el2_lib.scala 245:14] + node _T_1098 = cat(_T_1097, _T_1096) @[el2_lib.scala 245:14] + node _T_1099 = cat(_T_1098, _T_1095) @[el2_lib.scala 245:14] + node _T_1100 = cat(_T_1099, _T_1092) @[el2_lib.scala 245:14] + node _T_1101 = cat(_T_1100, _T_1085) @[el2_lib.scala 245:14] + node _T_1102 = and(_T_844, _T_1101) @[el2_lsu_trigger.scala 19:87] + node _T_1103 = cat(_T_1102, _T_836) @[Cat.scala 29:58] + node _T_1104 = cat(_T_1103, _T_570) @[Cat.scala 29:58] + node _T_1105 = cat(_T_1104, _T_304) @[Cat.scala 29:58] + io.lsu_trigger_match_m <= _T_1105 @[el2_lsu_trigger.scala 18:26] - extmodule TEC_RV_ICG_2 : + extmodule gated_latch_12 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG - - - module rvclkhdr_2 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_3 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_3 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_4 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_4 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_5 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_5 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_5 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_6 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_6 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_6 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_7 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_7 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_7 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_8 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_8 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_8 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_9 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_9 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_9 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_10 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_10 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_10 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_11 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG - - - module rvclkhdr_11 : - input clock : Clock - input reset : Reset - output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - - inst clkhdr of TEC_RV_ICG_11 @[beh_lib.scala 331:24] - clkhdr.SE is invalid - clkhdr.EN is invalid - clkhdr.CK is invalid - clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - extmodule TEC_RV_ICG_12 : - output Q : Clock - input CK : Clock - input EN : UInt<1> - input SE : UInt<1> - - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_12 : @@ -6727,23 +7623,23 @@ circuit el2_lsu : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_12 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_12 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_13 : + extmodule gated_latch_13 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_13 : @@ -6751,215 +7647,7575 @@ circuit el2_lsu : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_13 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_13 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_14 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_14 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_14 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_15 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_15 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_15 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_16 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_16 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_16 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_17 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_17 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_17 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_18 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_18 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_18 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_19 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_19 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_19 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_20 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_20 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_20 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_21 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_21 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_21 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_22 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_22 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_22 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_23 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_23 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_23 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_lsu_clkdomain : input clock : Clock - input reset : Reset + input reset : AsyncReset output io : {flip free_clk : Clock, flip clk_override : UInt<1>, flip addr_in_dccm_m : UInt<1>, flip dma_dccm_req : UInt<1>, flip ldst_stbuf_reqvld_r : UInt<1>, flip stbuf_reqvld_any : UInt<1>, flip stbuf_reqvld_flushed_any : UInt<1>, flip lsu_busreq_r : UInt<1>, flip lsu_bus_buffer_pend_any : UInt<1>, flip lsu_bus_buffer_empty_any : UInt<1>, flip lsu_stbuf_empty_any : UInt<1>, flip lsu_bus_clk_en : UInt<1>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_d : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, lsu_c1_m_clk : Clock, lsu_c1_r_clk : Clock, lsu_c2_m_clk : Clock, lsu_c2_r_clk : Clock, lsu_store_c1_m_clk : Clock, lsu_store_c1_r_clk : Clock, lsu_stbuf_c1_clk : Clock, lsu_bus_obuf_c1_clk : Clock, lsu_bus_ibuf_c1_clk : Clock, lsu_bus_buf_c1_clk : Clock, lsu_busm_clk : Clock, lsu_free_c2_clk : Clock, flip scan_mode : UInt<1>} - wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36] - wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36] - wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 62:36] - wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 63:36] - node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 64:51] - node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 64:70] - node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 65:51] - node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 65:70] - node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 66:51] - node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 66:70] - node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 68:47] - node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 68:66] - node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 69:47] - node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 69:66] - node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 71:49] - node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 71:71] - node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 72:49] - node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 72:71] - node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 73:55] - node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 73:77] - node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 73:107] - node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 74:49] - node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61] - node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 75:79] - node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 75:98] - node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 76:32] - node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 76:61] - node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 76:79] - node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 78:48] - node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 78:69] - node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 78:90] - node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:114] - node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 78:112] - node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 78:145] - node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 78:143] - node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 78:169] - node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 79:50] - node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 79:72] - reg _T_21 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:60] - _T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 82:60] - lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 82:26] - reg _T_22 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67] - _T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 84:67] - lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 84:26] - reg _T_23 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 85:67] - _T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 85:67] - lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 85:26] - reg _T_24 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 86:67] - _T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 86:67] - lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 86:26] - inst lsu_c1m_cgc of rvclkhdr_2 @[el2_lsu_clkdomain.scala 88:35] - lsu_c1m_cgc.clock <= clock - lsu_c1m_cgc.reset <= reset - lsu_c1m_cgc.io.en <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 88:77] - io.lsu_c1_m_clk <= lsu_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 88:127] - inst lsu_c1r_cgc of rvclkhdr_3 @[el2_lsu_clkdomain.scala 89:35] - lsu_c1r_cgc.clock <= clock - lsu_c1r_cgc.reset <= reset - lsu_c1r_cgc.io.en <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 89:77] - io.lsu_c1_r_clk <= lsu_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 89:127] - inst lsu_c2m_cgc of rvclkhdr_4 @[el2_lsu_clkdomain.scala 90:35] - lsu_c2m_cgc.clock <= clock - lsu_c2m_cgc.reset <= reset - lsu_c2m_cgc.io.en <= lsu_c2_m_clken @[el2_lsu_clkdomain.scala 90:77] - io.lsu_c2_m_clk <= lsu_c2m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 90:127] - inst lsu_c2r_cgc of rvclkhdr_5 @[el2_lsu_clkdomain.scala 91:35] - lsu_c2r_cgc.clock <= clock - lsu_c2r_cgc.reset <= reset - lsu_c2r_cgc.io.en <= lsu_c2_r_clken @[el2_lsu_clkdomain.scala 91:77] - io.lsu_c2_r_clk <= lsu_c2r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 91:127] - inst lsu_store_c1m_cgc of rvclkhdr_6 @[el2_lsu_clkdomain.scala 92:35] - lsu_store_c1m_cgc.clock <= clock - lsu_store_c1m_cgc.reset <= reset - lsu_store_c1m_cgc.io.en <= lsu_store_c1_m_clken @[el2_lsu_clkdomain.scala 92:77] - io.lsu_store_c1_m_clk <= lsu_store_c1m_cgc.io.l1clk @[el2_lsu_clkdomain.scala 92:127] - inst lsu_store_c1r_cgc of rvclkhdr_7 @[el2_lsu_clkdomain.scala 93:35] - lsu_store_c1r_cgc.clock <= clock - lsu_store_c1r_cgc.reset <= reset - lsu_store_c1r_cgc.io.en <= lsu_store_c1_r_clken @[el2_lsu_clkdomain.scala 93:77] - io.lsu_store_c1_r_clk <= lsu_store_c1r_cgc.io.l1clk @[el2_lsu_clkdomain.scala 93:127] - inst lsu_stbuf_c1_cgc of rvclkhdr_8 @[el2_lsu_clkdomain.scala 94:35] - lsu_stbuf_c1_cgc.clock <= clock - lsu_stbuf_c1_cgc.reset <= reset - lsu_stbuf_c1_cgc.io.en <= lsu_stbuf_c1_clken @[el2_lsu_clkdomain.scala 94:77] - io.lsu_stbuf_c1_clk <= lsu_stbuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 94:127] - inst lsu_bus_ibuf_c1_cgc of rvclkhdr_9 @[el2_lsu_clkdomain.scala 95:35] - lsu_bus_ibuf_c1_cgc.clock <= clock - lsu_bus_ibuf_c1_cgc.reset <= reset - lsu_bus_ibuf_c1_cgc.io.en <= lsu_bus_ibuf_c1_clken @[el2_lsu_clkdomain.scala 95:77] - io.lsu_bus_ibuf_c1_clk <= lsu_bus_ibuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 95:127] - inst lsu_bus_obuf_c1_cgc of rvclkhdr_10 @[el2_lsu_clkdomain.scala 96:35] - lsu_bus_obuf_c1_cgc.clock <= clock - lsu_bus_obuf_c1_cgc.reset <= reset - lsu_bus_obuf_c1_cgc.io.en <= lsu_bus_obuf_c1_clken @[el2_lsu_clkdomain.scala 96:77] - io.lsu_bus_obuf_c1_clk <= lsu_bus_obuf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 96:127] - inst lsu_bus_buf_c1_cgc of rvclkhdr_11 @[el2_lsu_clkdomain.scala 97:35] - lsu_bus_buf_c1_cgc.clock <= clock - lsu_bus_buf_c1_cgc.reset <= reset - lsu_bus_buf_c1_cgc.io.en <= lsu_bus_buf_c1_clken @[el2_lsu_clkdomain.scala 97:77] - io.lsu_bus_buf_c1_clk <= lsu_bus_buf_c1_cgc.io.l1clk @[el2_lsu_clkdomain.scala 97:127] - inst lsu_busm_cgc of rvclkhdr_12 @[el2_lsu_clkdomain.scala 98:35] - lsu_busm_cgc.clock <= clock - lsu_busm_cgc.reset <= reset - lsu_busm_cgc.io.en <= io.lsu_bus_clk_en @[el2_lsu_clkdomain.scala 98:77] - io.lsu_busm_clk <= lsu_busm_cgc.io.l1clk @[el2_lsu_clkdomain.scala 98:127] - inst lsu_free_cgc of rvclkhdr_13 @[el2_lsu_clkdomain.scala 99:35] - lsu_free_cgc.clock <= clock - lsu_free_cgc.reset <= reset - lsu_free_cgc.io.en <= lsu_free_c2_clken @[el2_lsu_clkdomain.scala 99:77] - io.lsu_free_c2_clk <= lsu_free_cgc.io.l1clk @[el2_lsu_clkdomain.scala 99:127] - lsu_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 101:30] - lsu_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 101:75] - lsu_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 102:30] - lsu_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 102:75] - lsu_c2m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 103:30] - lsu_c2m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 103:75] - lsu_c2r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 104:30] - lsu_c2r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 104:75] - lsu_store_c1m_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 105:30] - lsu_store_c1m_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 105:75] - lsu_store_c1r_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 106:30] - lsu_store_c1r_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 106:75] - lsu_stbuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 107:30] - lsu_stbuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 107:75] - lsu_bus_ibuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 108:30] - lsu_bus_ibuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 108:75] - lsu_bus_obuf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 109:30] - lsu_bus_obuf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 109:75] - lsu_bus_buf_c1_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 110:30] - lsu_bus_buf_c1_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 110:75] - lsu_busm_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 111:30] - lsu_busm_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 111:75] - lsu_free_cgc.io.clk <= clock @[el2_lsu_clkdomain.scala 112:30] - lsu_free_cgc.io.scan_mode <= io.scan_mode @[el2_lsu_clkdomain.scala 112:75] + wire lsu_c1_d_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 58:36] + wire lsu_c1_m_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 59:36] + wire lsu_c1_r_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 60:36] + wire lsu_free_c1_clken_q : UInt<1> @[el2_lsu_clkdomain.scala 61:36] + node _T = or(io.lsu_p.valid, io.dma_dccm_req) @[el2_lsu_clkdomain.scala 63:51] + node lsu_c1_d_clken = or(_T, io.clk_override) @[el2_lsu_clkdomain.scala 63:70] + node _T_1 = or(io.lsu_pkt_d.valid, lsu_c1_d_clken_q) @[el2_lsu_clkdomain.scala 64:51] + node lsu_c1_m_clken = or(_T_1, io.clk_override) @[el2_lsu_clkdomain.scala 64:70] + node _T_2 = or(io.lsu_pkt_m.valid, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 65:51] + node lsu_c1_r_clken = or(_T_2, io.clk_override) @[el2_lsu_clkdomain.scala 65:70] + node _T_3 = or(lsu_c1_m_clken, lsu_c1_m_clken_q) @[el2_lsu_clkdomain.scala 67:47] + node lsu_c2_m_clken = or(_T_3, io.clk_override) @[el2_lsu_clkdomain.scala 67:66] + node _T_4 = or(lsu_c1_r_clken, lsu_c1_r_clken_q) @[el2_lsu_clkdomain.scala 68:47] + node lsu_c2_r_clken = or(_T_4, io.clk_override) @[el2_lsu_clkdomain.scala 68:66] + node _T_5 = and(lsu_c1_m_clken, io.lsu_pkt_d.store) @[el2_lsu_clkdomain.scala 70:49] + node lsu_store_c1_m_clken = or(_T_5, io.clk_override) @[el2_lsu_clkdomain.scala 70:71] + node _T_6 = and(lsu_c1_r_clken, io.lsu_pkt_m.store) @[el2_lsu_clkdomain.scala 71:49] + node lsu_store_c1_r_clken = or(_T_6, io.clk_override) @[el2_lsu_clkdomain.scala 71:71] + node _T_7 = or(io.ldst_stbuf_reqvld_r, io.stbuf_reqvld_any) @[el2_lsu_clkdomain.scala 72:55] + node _T_8 = or(_T_7, io.stbuf_reqvld_flushed_any) @[el2_lsu_clkdomain.scala 72:77] + node lsu_stbuf_c1_clken = or(_T_8, io.clk_override) @[el2_lsu_clkdomain.scala 72:107] + node lsu_bus_ibuf_c1_clken = or(io.lsu_busreq_r, io.clk_override) @[el2_lsu_clkdomain.scala 73:49] + node _T_9 = or(io.lsu_bus_buffer_pend_any, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 74:61] + node _T_10 = or(_T_9, io.clk_override) @[el2_lsu_clkdomain.scala 74:79] + node lsu_bus_obuf_c1_clken = and(_T_10, io.lsu_bus_clk_en) @[el2_lsu_clkdomain.scala 74:98] + node _T_11 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 75:32] + node _T_12 = or(_T_11, io.lsu_busreq_r) @[el2_lsu_clkdomain.scala 75:61] + node lsu_bus_buf_c1_clken = or(_T_12, io.clk_override) @[el2_lsu_clkdomain.scala 75:79] + node _T_13 = or(io.lsu_p.valid, io.lsu_pkt_d.valid) @[el2_lsu_clkdomain.scala 77:48] + node _T_14 = or(_T_13, io.lsu_pkt_m.valid) @[el2_lsu_clkdomain.scala 77:69] + node _T_15 = or(_T_14, io.lsu_pkt_r.valid) @[el2_lsu_clkdomain.scala 77:90] + node _T_16 = eq(io.lsu_bus_buffer_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:114] + node _T_17 = or(_T_15, _T_16) @[el2_lsu_clkdomain.scala 77:112] + node _T_18 = eq(io.lsu_stbuf_empty_any, UInt<1>("h00")) @[el2_lsu_clkdomain.scala 77:145] + node _T_19 = or(_T_17, _T_18) @[el2_lsu_clkdomain.scala 77:143] + node lsu_free_c1_clken = or(_T_19, io.clk_override) @[el2_lsu_clkdomain.scala 77:169] + node _T_20 = or(lsu_free_c1_clken, lsu_free_c1_clken_q) @[el2_lsu_clkdomain.scala 78:50] + node lsu_free_c2_clken = or(_T_20, io.clk_override) @[el2_lsu_clkdomain.scala 78:72] + reg _T_21 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 81:60] + _T_21 <= lsu_free_c1_clken @[el2_lsu_clkdomain.scala 81:60] + lsu_free_c1_clken_q <= _T_21 @[el2_lsu_clkdomain.scala 81:26] + reg _T_22 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 82:67] + _T_22 <= lsu_c1_d_clken @[el2_lsu_clkdomain.scala 82:67] + lsu_c1_d_clken_q <= _T_22 @[el2_lsu_clkdomain.scala 82:26] + reg _T_23 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 83:67] + _T_23 <= lsu_c1_m_clken @[el2_lsu_clkdomain.scala 83:67] + lsu_c1_m_clken_q <= _T_23 @[el2_lsu_clkdomain.scala 83:26] + reg _T_24 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_clkdomain.scala 84:67] + _T_24 <= lsu_c1_r_clken @[el2_lsu_clkdomain.scala 84:67] + lsu_c1_r_clken_q <= _T_24 @[el2_lsu_clkdomain.scala 84:26] + node _T_25 = bits(lsu_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 86:59] + inst rvclkhdr of rvclkhdr_12 @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= _T_25 @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c1_m_clk <= rvclkhdr.io.l1clk @[el2_lsu_clkdomain.scala 86:26] + node _T_26 = bits(lsu_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 87:59] + inst rvclkhdr_1 of rvclkhdr_13 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= _T_26 @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c1_r_clk <= rvclkhdr_1.io.l1clk @[el2_lsu_clkdomain.scala 87:26] + node _T_27 = bits(lsu_c2_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 88:59] + inst rvclkhdr_2 of rvclkhdr_14 @[el2_lib.scala 483:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= _T_27 @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c2_m_clk <= rvclkhdr_2.io.l1clk @[el2_lsu_clkdomain.scala 88:26] + node _T_28 = bits(lsu_c2_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 89:59] + inst rvclkhdr_3 of rvclkhdr_15 @[el2_lib.scala 483:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= _T_28 @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_c2_r_clk <= rvclkhdr_3.io.l1clk @[el2_lsu_clkdomain.scala 89:26] + node _T_29 = bits(lsu_store_c1_m_clken, 0, 0) @[el2_lsu_clkdomain.scala 90:65] + inst rvclkhdr_4 of rvclkhdr_16 @[el2_lib.scala 483:22] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_4.io.en <= _T_29 @[el2_lib.scala 485:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_store_c1_m_clk <= rvclkhdr_4.io.l1clk @[el2_lsu_clkdomain.scala 90:26] + node _T_30 = bits(lsu_store_c1_r_clken, 0, 0) @[el2_lsu_clkdomain.scala 91:65] + inst rvclkhdr_5 of rvclkhdr_17 @[el2_lib.scala 483:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_5.io.en <= _T_30 @[el2_lib.scala 485:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_store_c1_r_clk <= rvclkhdr_5.io.l1clk @[el2_lsu_clkdomain.scala 91:26] + node _T_31 = bits(lsu_stbuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 92:63] + inst rvclkhdr_6 of rvclkhdr_18 @[el2_lib.scala 483:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_6.io.en <= _T_31 @[el2_lib.scala 485:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_stbuf_c1_clk <= rvclkhdr_6.io.l1clk @[el2_lsu_clkdomain.scala 92:26] + node _T_32 = bits(lsu_bus_ibuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 93:66] + inst rvclkhdr_7 of rvclkhdr_19 @[el2_lib.scala 483:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_7.io.en <= _T_32 @[el2_lib.scala 485:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_ibuf_c1_clk <= rvclkhdr_7.io.l1clk @[el2_lsu_clkdomain.scala 93:26] + node _T_33 = bits(lsu_bus_obuf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 94:66] + inst rvclkhdr_8 of rvclkhdr_20 @[el2_lib.scala 483:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_8.io.en <= _T_33 @[el2_lib.scala 485:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_obuf_c1_clk <= rvclkhdr_8.io.l1clk @[el2_lsu_clkdomain.scala 94:26] + node _T_34 = bits(lsu_bus_buf_c1_clken, 0, 0) @[el2_lsu_clkdomain.scala 95:65] + inst rvclkhdr_9 of rvclkhdr_21 @[el2_lib.scala 483:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_9.io.en <= _T_34 @[el2_lib.scala 485:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_bus_buf_c1_clk <= rvclkhdr_9.io.l1clk @[el2_lsu_clkdomain.scala 95:26] + node _T_35 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_clkdomain.scala 96:62] + inst rvclkhdr_10 of rvclkhdr_22 @[el2_lib.scala 483:22] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_10.io.en <= _T_35 @[el2_lib.scala 485:16] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_busm_clk <= rvclkhdr_10.io.l1clk @[el2_lsu_clkdomain.scala 96:26] + node _T_36 = bits(lsu_free_c2_clken, 0, 0) @[el2_lsu_clkdomain.scala 97:62] + inst rvclkhdr_11 of rvclkhdr_23 @[el2_lib.scala 483:22] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_11.io.en <= _T_36 @[el2_lib.scala 485:16] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + io.lsu_free_c2_clk <= rvclkhdr_11.io.l1clk @[el2_lsu_clkdomain.scala 97:26] + + extmodule gated_latch_24 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_24 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_24 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_25 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_25 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_25 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_26 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_26 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_26 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_27 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_27 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_27 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_28 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_28 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_28 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_29 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_29 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_29 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_30 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_30 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_30 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_31 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_31 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_31 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_32 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_32 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_32 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_33 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_33 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_33 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_34 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_34 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_34 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_35 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_35 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_35 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + module el2_lsu_bus_buffer : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + + wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 121:22] + wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 122:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") + wire CmdPtr0 : UInt<2> + CmdPtr0 <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 127:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 128:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_2 = eq(_T, _T_1) @[el2_lsu_bus_buffer.scala 130:74] + node _T_3 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 130:109] + node _T_4 = and(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 130:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_6 = and(_T_4, _T_5) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_9 = eq(_T_7, _T_8) @[el2_lsu_bus_buffer.scala 130:74] + node _T_10 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 130:109] + node _T_11 = and(_T_9, _T_10) @[el2_lsu_bus_buffer.scala 130:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_13 = and(_T_11, _T_12) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_16 = eq(_T_14, _T_15) @[el2_lsu_bus_buffer.scala 130:74] + node _T_17 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 130:109] + node _T_18 = and(_T_16, _T_17) @[el2_lsu_bus_buffer.scala 130:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_20 = and(_T_18, _T_19) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_23 = eq(_T_21, _T_22) @[el2_lsu_bus_buffer.scala 130:74] + node _T_24 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 130:109] + node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 130:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_27 = and(_T_25, _T_26) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_30 = eq(_T_28, _T_29) @[el2_lsu_bus_buffer.scala 131:74] + node _T_31 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 131:109] + node _T_32 = and(_T_30, _T_31) @[el2_lsu_bus_buffer.scala 131:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_34 = and(_T_32, _T_33) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_37 = eq(_T_35, _T_36) @[el2_lsu_bus_buffer.scala 131:74] + node _T_38 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 131:109] + node _T_39 = and(_T_37, _T_38) @[el2_lsu_bus_buffer.scala 131:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_41 = and(_T_39, _T_40) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_44 = eq(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 131:74] + node _T_45 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 131:109] + node _T_46 = and(_T_44, _T_45) @[el2_lsu_bus_buffer.scala 131:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_51 = eq(_T_49, _T_50) @[el2_lsu_bus_buffer.scala 131:74] + node _T_52 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 131:109] + node _T_53 = and(_T_51, _T_52) @[el2_lsu_bus_buffer.scala 131:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_55 = and(_T_53, _T_54) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 132:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 134:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 136:24] + buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 138:26] + buf_nxtstate[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 140:23] + buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 142:25] + buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 144:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 146:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 148:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + wire buf_data_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 150:25] + buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 152:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 154:26] + buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + wire bus_rsp_read_error : UInt<1> + bus_rsp_read_error <= UInt<1>("h00") + wire bus_rsp_rdata : UInt<64> + bus_rsp_rdata <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 159:25] + buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 162:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 167:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 169:21] + buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 172:27] + buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 174:25] + buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 180:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 184:23] + buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") + wire ibuf_data : UInt<32> + ibuf_data <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 191:98] + node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 191:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 191:98] + node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 191:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 191:98] + node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 191:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 191:98] + node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 191:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 191:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 192:98] + node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 192:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 192:98] + node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 192:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 192:98] + node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 192:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 192:98] + node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 192:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 192:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 194:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 194:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 194:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 194:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 194:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 194:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 194:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 194:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 194:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 194:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 194:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 194:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 194:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 194:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 194:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 194:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 194:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 194:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 194:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 194:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 194:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 194:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 194:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 194:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 194:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 194:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 194:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 194:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 194:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 194:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 194:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 194:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 195:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 195:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 195:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 195:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 195:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 195:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 195:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 195:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 195:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 195:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 195:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 195:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 195:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 195:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 195:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 195:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 195:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 195:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 195:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 195:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 195:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 195:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 195:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 195:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 195:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 195:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 195:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 195:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 195:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 195:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 195:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 195:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 197:29] + buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 199:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 199:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 199:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 199:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 199:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 199:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 199:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 199:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 199:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 199:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 199:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 199:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 199:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 199:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 199:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 199:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 199:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 199:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 199:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 199:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 199:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 199:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 199:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 199:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 199:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 199:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 199:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 199:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 199:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 199:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 199:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 199:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 199:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 199:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 199:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 199:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 199:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 199:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 199:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 199:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 199:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 199:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 199:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 199:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 199:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 199:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 199:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 199:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 199:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 200:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 200:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 200:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 200:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 200:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 200:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 200:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 200:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 200:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 200:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 200:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 200:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 200:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 200:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 200:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 200:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 200:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 200:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 200:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 200:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 200:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 200:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 200:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 200:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 200:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 200:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 200:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 200:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 200:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 200:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 200:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 200:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 200:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 200:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 200:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 200:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 200:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 200:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 200:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 200:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 200:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 200:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 200:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 200:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 200:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 200:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 200:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 200:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 200:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 205:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 205:64] + node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 205:51] + node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 205:73] + node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 205:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 205:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 206:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 206:64] + node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 206:51] + node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 206:73] + node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 206:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 206:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[el2_lsu_bus_buffer.scala 210:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[el2_lsu_bus_buffer.scala 210:69] + ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 210:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[el2_lsu_bus_buffer.scala 211:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[el2_lsu_bus_buffer.scala 211:69] + ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 211:23] + wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 213:22] + buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 216:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 216:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 216:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 216:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 217:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 217:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 217:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 217:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 218:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_560 = and(_T_558, _T_559) @[el2_lsu_bus_buffer.scala 218:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 218:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_565 = and(_T_563, _T_564) @[el2_lsu_bus_buffer.scala 218:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 218:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_570 = and(_T_568, _T_569) @[el2_lsu_bus_buffer.scala 218:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 218:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_575 = and(_T_573, _T_574) @[el2_lsu_bus_buffer.scala 218:91] + node _T_576 = or(_T_560, _T_565) @[el2_lsu_bus_buffer.scala 218:123] + node _T_577 = or(_T_576, _T_570) @[el2_lsu_bus_buffer.scala 218:123] + node _T_578 = or(_T_577, _T_575) @[el2_lsu_bus_buffer.scala 218:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 219:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_583 = and(_T_581, _T_582) @[el2_lsu_bus_buffer.scala 219:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 219:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_588 = and(_T_586, _T_587) @[el2_lsu_bus_buffer.scala 219:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 219:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_593 = and(_T_591, _T_592) @[el2_lsu_bus_buffer.scala 219:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 219:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_598 = and(_T_596, _T_597) @[el2_lsu_bus_buffer.scala 219:65] + node _T_599 = or(_T_583, _T_588) @[el2_lsu_bus_buffer.scala 219:97] + node _T_600 = or(_T_599, _T_593) @[el2_lsu_bus_buffer.scala 219:97] + node _T_601 = or(_T_600, _T_598) @[el2_lsu_bus_buffer.scala 219:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_606 = and(_T_604, _T_605) @[el2_lsu_bus_buffer.scala 220:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_611 = and(_T_609, _T_610) @[el2_lsu_bus_buffer.scala 220:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_616 = and(_T_614, _T_615) @[el2_lsu_bus_buffer.scala 220:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_621 = and(_T_619, _T_620) @[el2_lsu_bus_buffer.scala 220:65] + node _T_622 = or(_T_606, _T_611) @[el2_lsu_bus_buffer.scala 220:97] + node _T_623 = or(_T_622, _T_616) @[el2_lsu_bus_buffer.scala 220:97] + node _T_624 = or(_T_623, _T_621) @[el2_lsu_bus_buffer.scala 220:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_629 = and(_T_627, _T_628) @[el2_lsu_bus_buffer.scala 221:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_634 = and(_T_632, _T_633) @[el2_lsu_bus_buffer.scala 221:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_639 = and(_T_637, _T_638) @[el2_lsu_bus_buffer.scala 221:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_644 = and(_T_642, _T_643) @[el2_lsu_bus_buffer.scala 221:65] + node _T_645 = or(_T_629, _T_634) @[el2_lsu_bus_buffer.scala 221:97] + node _T_646 = or(_T_645, _T_639) @[el2_lsu_bus_buffer.scala 221:97] + node _T_647 = or(_T_646, _T_644) @[el2_lsu_bus_buffer.scala 221:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 222:32] + node _T_652 = or(_T_650, _T_651) @[el2_lsu_bus_buffer.scala 221:103] + io.ld_fwddata_buf_lo <= _T_652 @[el2_lsu_bus_buffer.scala 218:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 224:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_657 = and(_T_655, _T_656) @[el2_lsu_bus_buffer.scala 224:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 224:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_662 = and(_T_660, _T_661) @[el2_lsu_bus_buffer.scala 224:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 224:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_667 = and(_T_665, _T_666) @[el2_lsu_bus_buffer.scala 224:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 224:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_672 = and(_T_670, _T_671) @[el2_lsu_bus_buffer.scala 224:91] + node _T_673 = or(_T_657, _T_662) @[el2_lsu_bus_buffer.scala 224:123] + node _T_674 = or(_T_673, _T_667) @[el2_lsu_bus_buffer.scala 224:123] + node _T_675 = or(_T_674, _T_672) @[el2_lsu_bus_buffer.scala 224:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 225:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_680 = and(_T_678, _T_679) @[el2_lsu_bus_buffer.scala 225:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 225:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_685 = and(_T_683, _T_684) @[el2_lsu_bus_buffer.scala 225:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 225:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_690 = and(_T_688, _T_689) @[el2_lsu_bus_buffer.scala 225:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 225:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_695 = and(_T_693, _T_694) @[el2_lsu_bus_buffer.scala 225:65] + node _T_696 = or(_T_680, _T_685) @[el2_lsu_bus_buffer.scala 225:97] + node _T_697 = or(_T_696, _T_690) @[el2_lsu_bus_buffer.scala 225:97] + node _T_698 = or(_T_697, _T_695) @[el2_lsu_bus_buffer.scala 225:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 226:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_703 = and(_T_701, _T_702) @[el2_lsu_bus_buffer.scala 226:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 226:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_708 = and(_T_706, _T_707) @[el2_lsu_bus_buffer.scala 226:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 226:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_713 = and(_T_711, _T_712) @[el2_lsu_bus_buffer.scala 226:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 226:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_718 = and(_T_716, _T_717) @[el2_lsu_bus_buffer.scala 226:65] + node _T_719 = or(_T_703, _T_708) @[el2_lsu_bus_buffer.scala 226:97] + node _T_720 = or(_T_719, _T_713) @[el2_lsu_bus_buffer.scala 226:97] + node _T_721 = or(_T_720, _T_718) @[el2_lsu_bus_buffer.scala 226:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 227:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_726 = and(_T_724, _T_725) @[el2_lsu_bus_buffer.scala 227:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 227:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_731 = and(_T_729, _T_730) @[el2_lsu_bus_buffer.scala 227:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 227:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_736 = and(_T_734, _T_735) @[el2_lsu_bus_buffer.scala 227:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 227:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_741 = and(_T_739, _T_740) @[el2_lsu_bus_buffer.scala 227:65] + node _T_742 = or(_T_726, _T_731) @[el2_lsu_bus_buffer.scala 227:97] + node _T_743 = or(_T_742, _T_736) @[el2_lsu_bus_buffer.scala 227:97] + node _T_744 = or(_T_743, _T_741) @[el2_lsu_bus_buffer.scala 227:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 228:32] + node _T_749 = or(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 227:103] + io.ld_fwddata_buf_hi <= _T_749 @[el2_lsu_bus_buffer.scala 224:24] + node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 230:65] + node _T_750 = mux(io.lsu_pkt_r.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 235:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 235:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 236:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 236:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[el2_lsu_bus_buffer.scala 236:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 237:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 237:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[el2_lsu_bus_buffer.scala 237:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 238:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 238:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[el2_lsu_bus_buffer.scala 238:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 239:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 239:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 240:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 240:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[el2_lsu_bus_buffer.scala 240:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 241:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 242:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[el2_lsu_bus_buffer.scala 242:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 244:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 244:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 245:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 245:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[el2_lsu_bus_buffer.scala 245:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 246:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 246:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[el2_lsu_bus_buffer.scala 246:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 247:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 247:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[el2_lsu_bus_buffer.scala 247:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 249:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 249:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 250:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 250:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[el2_lsu_bus_buffer.scala 250:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 251:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 251:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[el2_lsu_bus_buffer.scala 251:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 252:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 252:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[el2_lsu_bus_buffer.scala 252:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[el2_lsu_bus_buffer.scala 255:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 256:67] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 256:74] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 257:40] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 257:26] + node _T_845 = mux(io.lsu_pkt_r.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 259:55] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[el2_lsu_bus_buffer.scala 259:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 259:79] + node ibuf_byp = and(_T_851, _T_852) @[el2_lsu_bus_buffer.scala 259:77] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 260:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 260:56] + node ibuf_wr_en = and(_T_853, _T_854) @[el2_lsu_bus_buffer.scala 260:54] + wire ibuf_drain_vld : UInt<1> + ibuf_drain_vld <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 262:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[el2_lsu_bus_buffer.scala 262:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 262:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 263:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[el2_lsu_bus_buffer.scala 263:42] + node _T_859 = and(_T_858, ibuf_valid) @[el2_lsu_bus_buffer.scala 263:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 263:107] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 263:132] + node _T_862 = neq(_T_860, _T_861) @[el2_lsu_bus_buffer.scala 263:115] + node _T_863 = or(io.lsu_pkt_m.load, _T_862) @[el2_lsu_bus_buffer.scala 263:95] + node ibuf_force_drain = and(_T_859, _T_863) @[el2_lsu_bus_buffer.scala 263:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") + wire ibuf_merge_en : UInt<1> + ibuf_merge_en <= UInt<1>("h00") + wire ibuf_merge_in : UInt<1> + ibuf_merge_in <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[el2_lsu_bus_buffer.scala 268:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 268:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:82] + node _T_868 = and(_T_865, _T_867) @[el2_lsu_bus_buffer.scala 268:80] + node _T_869 = or(_T_868, ibuf_byp) @[el2_lsu_bus_buffer.scala 269:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 269:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 269:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 269:55] + node _T_873 = or(_T_871, _T_872) @[el2_lsu_bus_buffer.scala 269:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 269:67] + node _T_875 = and(ibuf_valid, _T_874) @[el2_lsu_bus_buffer.scala 268:32] + ibuf_drain_vld <= _T_875 @[el2_lsu_bus_buffer.scala 268:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 274:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 274:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[el2_lsu_bus_buffer.scala 274:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 277:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 278:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 278:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 278:95] + node _T_881 = or(_T_879, _T_880) @[el2_lsu_bus_buffer.scala 278:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[el2_lsu_bus_buffer.scala 279:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[el2_lsu_bus_buffer.scala 278:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 283:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 283:45] + node _T_888 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 283:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 283:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[el2_lsu_bus_buffer.scala 284:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[el2_lsu_bus_buffer.scala 282:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 283:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 283:45] + node _T_897 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 283:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[el2_lsu_bus_buffer.scala 283:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[el2_lsu_bus_buffer.scala 284:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[el2_lsu_bus_buffer.scala 282:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 283:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 283:45] + node _T_906 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 283:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 283:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[el2_lsu_bus_buffer.scala 284:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[el2_lsu_bus_buffer.scala 282:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 283:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 283:45] + node _T_915 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 283:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[el2_lsu_bus_buffer.scala 283:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[el2_lsu_bus_buffer.scala 284:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[el2_lsu_bus_buffer.scala 282:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 285:59] + node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 285:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 285:93] + node _T_926 = tail(_T_925, 1) @[el2_lsu_bus_buffer.scala 285:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[el2_lsu_bus_buffer.scala 285:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[el2_lsu_bus_buffer.scala 285:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 287:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 287:54] + node _T_930 = and(_T_929, ibuf_valid) @[el2_lsu_bus_buffer.scala 287:75] + node _T_931 = and(_T_930, ibuf_write) @[el2_lsu_bus_buffer.scala 287:88] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 287:117] + node _T_933 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 287:137] + node _T_934 = eq(_T_932, _T_933) @[el2_lsu_bus_buffer.scala 287:124] + node _T_935 = and(_T_931, _T_934) @[el2_lsu_bus_buffer.scala 287:101] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:147] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_bus_buffer.scala 287:145] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:170] + node _T_939 = and(_T_937, _T_938) @[el2_lsu_bus_buffer.scala 287:168] + ibuf_merge_en <= _T_939 @[el2_lsu_bus_buffer.scala 287:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:20] + ibuf_merge_in <= _T_940 @[el2_lsu_bus_buffer.scala 288:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[el2_lsu_bus_buffer.scala 289:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 289:114] + node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 289:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[el2_lsu_bus_buffer.scala 289:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[el2_lsu_bus_buffer.scala 289:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 289:114] + node _T_952 = or(_T_950, _T_951) @[el2_lsu_bus_buffer.scala 289:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 289:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[el2_lsu_bus_buffer.scala 289:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 289:114] + node _T_959 = or(_T_957, _T_958) @[el2_lsu_bus_buffer.scala 289:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[el2_lsu_bus_buffer.scala 289:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[el2_lsu_bus_buffer.scala 289:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 289:114] + node _T_966 = or(_T_964, _T_965) @[el2_lsu_bus_buffer.scala 289:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[el2_lsu_bus_buffer.scala 289:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[el2_lsu_bus_buffer.scala 290:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 290:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 290:118] + node _T_975 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[el2_lsu_bus_buffer.scala 290:81] + node _T_977 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[el2_lsu_bus_buffer.scala 290:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[el2_lsu_bus_buffer.scala 290:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 290:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 290:118] + node _T_983 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 290:81] + node _T_985 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[el2_lsu_bus_buffer.scala 290:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[el2_lsu_bus_buffer.scala 290:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 290:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 290:118] + node _T_991 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[el2_lsu_bus_buffer.scala 290:81] + node _T_993 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[el2_lsu_bus_buffer.scala 290:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[el2_lsu_bus_buffer.scala 290:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 290:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 290:118] + node _T_999 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 290:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[el2_lsu_bus_buffer.scala 290:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 292:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 292:93] + node _T_1007 = and(_T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 292:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 292:54] + _T_1008 <= _T_1007 @[el2_lsu_bus_buffer.scala 292:54] + ibuf_valid <= _T_1008 @[el2_lsu_bus_buffer.scala 292:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[el2_lsu_bus_buffer.scala 293:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[el2_lsu_bus_buffer.scala 298:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[el2_lsu_bus_buffer.scala 300:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr_24 @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1012 <= ibuf_addr_in @[el2_lib.scala 514:16] + ibuf_addr <= _T_1012 @[el2_lsu_bus_buffer.scala 302:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[el2_lsu_bus_buffer.scala 303:15] + inst rvclkhdr_1 of rvclkhdr_25 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1014 <= ibuf_data_in @[el2_lib.scala 514:16] + ibuf_data <= _T_1014 @[el2_lsu_bus_buffer.scala 304:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 305:55] + _T_1015 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 305:55] + ibuf_timer <= _T_1015 @[el2_lsu_bus_buffer.scala 305:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") + wire obuf_wr_timer : UInt<3> + obuf_wr_timer <= UInt<1>("h00") + wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 309:25] + buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:72] + node _T_1018 = and(_T_1016, _T_1017) @[el2_lsu_bus_buffer.scala 315:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 315:97] + node _T_1020 = and(_T_1018, _T_1019) @[el2_lsu_bus_buffer.scala 315:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:5] + node _T_1022 = and(_T_1020, _T_1021) @[el2_lsu_bus_buffer.scala 315:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:31] + node _T_1036 = and(_T_1022, _T_1035) @[el2_lsu_bus_buffer.scala 316:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:5] + node _T_1054 = and(_T_1036, _T_1053) @[el2_lsu_bus_buffer.scala 316:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 317:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 318:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 318:95] + node _T_1058 = and(_T_1056, _T_1057) @[el2_lsu_bus_buffer.scala 318:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 318:123] + node _T_1060 = tail(_T_1059, 1) @[el2_lsu_bus_buffer.scala 318:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 318:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[el2_lsu_bus_buffer.scala 318:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[el2_lsu_bus_buffer.scala 319:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:60] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_bus_buffer.scala 319:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:93] + node _T_1067 = and(_T_1065, _T_1066) @[el2_lsu_bus_buffer.scala 319:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 319:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[el2_lsu_bus_buffer.scala 319:123] + node _T_1086 = and(_T_1067, _T_1085) @[el2_lsu_bus_buffer.scala 319:101] + obuf_force_wr_en <= _T_1086 @[el2_lsu_bus_buffer.scala 319:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[el2_lsu_bus_buffer.scala 321:31] + node _T_1089 = eq(io.lsu_pkt_r.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 321:84] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[el2_lsu_bus_buffer.scala 321:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 324:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 326:22] + buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 328:24] + buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 336:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 336:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 336:52] + node _T_1094 = and(_T_1091, _T_1093) @[el2_lsu_bus_buffer.scala 336:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 337:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[el2_lsu_bus_buffer.scala 337:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1113 = bits(_T_1111, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1115 = bits(_T_1111, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1117 = bits(_T_1111, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1119 = bits(_T_1111, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:23] + node _T_1129 = and(_T_1108, _T_1128) @[el2_lsu_bus_buffer.scala 338:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 338:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:105] + node _T_1148 = and(_T_1129, _T_1147) @[el2_lsu_bus_buffer.scala 338:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1153 = bits(_T_1151, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1155 = bits(_T_1151, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1157 = bits(_T_1151, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1159 = bits(_T_1151, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1172 = bits(_T_1170, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1174 = bits(_T_1170, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1176 = bits(_T_1170, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1178 = bits(_T_1170, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[el2_lsu_bus_buffer.scala 339:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1189 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1191 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1193 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1195 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:150] + node _T_1205 = and(_T_1187, _T_1204) @[el2_lsu_bus_buffer.scala 339:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[el2_lsu_bus_buffer.scala 339:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1212 = bits(_T_1210, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1214 = bits(_T_1210, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1216 = bits(_T_1210, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1218 = bits(_T_1210, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[el2_lsu_bus_buffer.scala 339:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 339:269] + node _T_1229 = and(_T_1148, _T_1228) @[el2_lsu_bus_buffer.scala 338:164] + node _T_1230 = or(_T_1094, _T_1229) @[el2_lsu_bus_buffer.scala 336:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[el2_lsu_bus_buffer.scala 340:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[el2_lsu_bus_buffer.scala 340:60] + node _T_1234 = and(_T_1230, _T_1233) @[el2_lsu_bus_buffer.scala 340:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:77] + node _T_1236 = and(_T_1234, _T_1235) @[el2_lsu_bus_buffer.scala 340:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:93] + node _T_1238 = and(_T_1236, _T_1237) @[el2_lsu_bus_buffer.scala 340:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:118] + node _T_1240 = and(_T_1238, _T_1239) @[el2_lsu_bus_buffer.scala 340:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 340:142] + obuf_wr_en <= _T_1241 @[el2_lsu_bus_buffer.scala 336:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1242 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 342:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[el2_lsu_bus_buffer.scala 342:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 342:65] + node _T_1245 = and(_T_1243, _T_1244) @[el2_lsu_bus_buffer.scala 342:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 342:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 342:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1248 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1250 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1252 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1254 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1258 = mux(_T_1253, _T_1254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1259 = or(_T_1255, _T_1256) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1257) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] + wire _T_1262 : UInt<1> @[Mux.scala 27:72] + _T_1262 <= _T_1261 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.store, _T_1262) @[el2_lsu_bus_buffer.scala 343:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1274 = mux(_T_1269, _T_1270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1275 = or(_T_1271, _T_1272) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1273) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] + wire _T_1278 : UInt<1> @[Mux.scala 27:72] + _T_1278 <= _T_1277 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[el2_lsu_bus_buffer.scala 344:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1286 = mux(_T_1282, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1287 = or(_T_1283, _T_1284) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1285) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] + wire _T_1290 : UInt<32> @[Mux.scala 27:72] + _T_1290 <= _T_1289 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[el2_lsu_bus_buffer.scala 345:25] + wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 346:20] + buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + node _T_1291 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1299 = mux(_T_1295, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1300 = or(_T_1296, _T_1297) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1298) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] + wire _T_1303 : UInt<2> @[Mux.scala 27:72] + _T_1303 <= _T_1302 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[el2_lsu_bus_buffer.scala 348:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 351:25] + wire Cmdptr1 : UInt<2> + Cmdptr1 <= UInt<1>("h00") + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) @[el2_lsu_bus_buffer.scala 354:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1304 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 357:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 357:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 357:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[el2_lsu_bus_buffer.scala 357:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1307 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 360:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 360:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 360:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[el2_lsu_bus_buffer.scala 360:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:98] + node _T_1315 = and(_T_1312, _T_1314) @[el2_lsu_bus_buffer.scala 361:96] + node _T_1316 = or(_T_1311, _T_1315) @[el2_lsu_bus_buffer.scala 361:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 361:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:147] + node _T_1319 = orr(_T_1318) @[el2_lsu_bus_buffer.scala 361:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:134] + node _T_1321 = and(_T_1317, _T_1320) @[el2_lsu_bus_buffer.scala 361:132] + node _T_1322 = or(_T_1316, _T_1321) @[el2_lsu_bus_buffer.scala 361:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[el2_lsu_bus_buffer.scala 361:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[el2_lsu_bus_buffer.scala 369:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 369:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 369:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[el2_lsu_bus_buffer.scala 369:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:81] + node _T_1330 = and(_T_1326, _T_1329) @[el2_lsu_bus_buffer.scala 369:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[el2_lsu_bus_buffer.scala 370:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:37] + node _T_1334 = and(_T_1332, _T_1333) @[el2_lsu_bus_buffer.scala 370:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[el2_lsu_bus_buffer.scala 369:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 372:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[el2_lsu_bus_buffer.scala 372:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 372:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1337 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 375:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 375:52] + node _T_1339 = eq(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 375:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 375:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:80] + node _T_1342 = and(_T_1340, _T_1341) @[el2_lsu_bus_buffer.scala 375:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:99] + node _T_1344 = and(_T_1342, _T_1343) @[el2_lsu_bus_buffer.scala 375:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:113] + node _T_1346 = and(_T_1344, _T_1345) @[el2_lsu_bus_buffer.scala 375:111] + node _T_1347 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:130] + node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 375:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:20] + node _T_1350 = and(obuf_valid, _T_1349) @[el2_lsu_bus_buffer.scala 376:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 376:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[el2_lsu_bus_buffer.scala 376:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[el2_lsu_bus_buffer.scala 376:53] + node _T_1355 = or(_T_1350, _T_1354) @[el2_lsu_bus_buffer.scala 376:34] + node _T_1356 = and(_T_1348, _T_1355) @[el2_lsu_bus_buffer.scala 375:165] + obuf_nosend_in <= _T_1356 @[el2_lsu_bus_buffer.scala 375:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 377:60] + node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[el2_lsu_bus_buffer.scala 377:46] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1364, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = or(_T_1365, _T_1366) @[Mux.scala 27:72] + node _T_1370 = or(_T_1369, _T_1367) @[Mux.scala 27:72] + node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] + wire _T_1372 : UInt<32> @[Mux.scala 27:72] + _T_1372 <= _T_1371 @[Mux.scala 27:72] + node _T_1373 = bits(_T_1372, 2, 2) @[el2_lsu_bus_buffer.scala 378:36] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_lsu_bus_buffer.scala 378:46] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = or(_T_1379, _T_1380) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + wire _T_1386 : UInt<4> @[Mux.scala 27:72] + _T_1386 <= _T_1385 @[Mux.scala 27:72] + node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = or(_T_1392, _T_1393) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1394) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1395) @[Mux.scala 27:72] + wire _T_1399 : UInt<4> @[Mux.scala 27:72] + _T_1399 <= _T_1398 @[Mux.scala 27:72] + node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[el2_lsu_bus_buffer.scala 378:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[el2_lsu_bus_buffer.scala 377:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 379:60] + node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[el2_lsu_bus_buffer.scala 379:46] + node _T_1406 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1407 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1408 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1409 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1413 = mux(_T_1409, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1414 = or(_T_1410, _T_1411) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1412) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] + wire _T_1417 : UInt<32> @[Mux.scala 27:72] + _T_1417 <= _T_1416 @[Mux.scala 27:72] + node _T_1418 = bits(_T_1417, 2, 2) @[el2_lsu_bus_buffer.scala 380:36] + node _T_1419 = bits(_T_1418, 0, 0) @[el2_lsu_bus_buffer.scala 380:46] + node _T_1420 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1421 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1422 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1423 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = or(_T_1424, _T_1425) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + wire _T_1431 : UInt<4> @[Mux.scala 27:72] + _T_1431 <= _T_1430 @[Mux.scala 27:72] + node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1433 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1434 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1435 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1436 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = or(_T_1437, _T_1438) @[Mux.scala 27:72] + node _T_1442 = or(_T_1441, _T_1439) @[Mux.scala 27:72] + node _T_1443 = or(_T_1442, _T_1440) @[Mux.scala 27:72] + wire _T_1444 : UInt<4> @[Mux.scala 27:72] + _T_1444 <= _T_1443 @[Mux.scala 27:72] + node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[el2_lsu_bus_buffer.scala 380:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[el2_lsu_bus_buffer.scala 379:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 382:58] + node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[el2_lsu_bus_buffer.scala 382:44] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1454, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = or(_T_1455, _T_1456) @[Mux.scala 27:72] + node _T_1460 = or(_T_1459, _T_1457) @[Mux.scala 27:72] + node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] + wire _T_1462 : UInt<32> @[Mux.scala 27:72] + _T_1462 <= _T_1461 @[Mux.scala 27:72] + node _T_1463 = bits(_T_1462, 2, 2) @[el2_lsu_bus_buffer.scala 383:36] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_lsu_bus_buffer.scala 383:46] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1468, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1474 = or(_T_1473, _T_1471) @[Mux.scala 27:72] + node _T_1475 = or(_T_1474, _T_1472) @[Mux.scala 27:72] + wire _T_1476 : UInt<32> @[Mux.scala 27:72] + _T_1476 <= _T_1475 @[Mux.scala 27:72] + node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1481, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = or(_T_1482, _T_1483) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1484) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1485) @[Mux.scala 27:72] + wire _T_1489 : UInt<32> @[Mux.scala 27:72] + _T_1489 <= _T_1488 @[Mux.scala 27:72] + node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[el2_lsu_bus_buffer.scala 383:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[el2_lsu_bus_buffer.scala 382:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 384:58] + node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[el2_lsu_bus_buffer.scala 384:44] + node _T_1496 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1497 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1498 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1499 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1499, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = or(_T_1500, _T_1501) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1502) @[Mux.scala 27:72] + node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] + wire _T_1507 : UInt<32> @[Mux.scala 27:72] + _T_1507 <= _T_1506 @[Mux.scala 27:72] + node _T_1508 = bits(_T_1507, 2, 2) @[el2_lsu_bus_buffer.scala 385:36] + node _T_1509 = bits(_T_1508, 0, 0) @[el2_lsu_bus_buffer.scala 385:46] + node _T_1510 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1511 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1512 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1513 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1513, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = or(_T_1514, _T_1515) @[Mux.scala 27:72] + node _T_1519 = or(_T_1518, _T_1516) @[Mux.scala 27:72] + node _T_1520 = or(_T_1519, _T_1517) @[Mux.scala 27:72] + wire _T_1521 : UInt<32> @[Mux.scala 27:72] + _T_1521 <= _T_1520 @[Mux.scala 27:72] + node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1523 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1524 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1525 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1526 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1526, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = or(_T_1527, _T_1528) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1529) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1530) @[Mux.scala 27:72] + wire _T_1534 : UInt<32> @[Mux.scala 27:72] + _T_1534 <= _T_1533 @[Mux.scala 27:72] + node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[el2_lsu_bus_buffer.scala 385:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[el2_lsu_bus_buffer.scala 384:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1540 = or(_T_1537, _T_1539) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1544 = or(_T_1541, _T_1543) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1548 = or(_T_1545, _T_1547) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1552 = or(_T_1549, _T_1551) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1556 = or(_T_1553, _T_1555) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1560 = or(_T_1557, _T_1559) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1564 = or(_T_1561, _T_1563) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1568 = or(_T_1565, _T_1567) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1552) @[Cat.scala 29:58] + node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] + node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1594) @[Cat.scala 29:58] + node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] + node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 389:24] + buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + node _T_1621 = neq(CmdPtr0, Cmdptr1) @[el2_lsu_bus_buffer.scala 391:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[el2_lsu_bus_buffer.scala 391:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[el2_lsu_bus_buffer.scala 391:59] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1631 = mux(_T_1627, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1632 = or(_T_1628, _T_1629) @[Mux.scala 27:72] + node _T_1633 = or(_T_1632, _T_1630) @[Mux.scala 27:72] + node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] + wire _T_1635 : UInt<3> @[Mux.scala 27:72] + _T_1635 <= _T_1634 @[Mux.scala 27:72] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:107] + node _T_1637 = and(_T_1623, _T_1636) @[el2_lsu_bus_buffer.scala 391:75] + node _T_1638 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1639 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1640 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1641 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1645 = mux(_T_1641, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1646 = or(_T_1642, _T_1643) @[Mux.scala 27:72] + node _T_1647 = or(_T_1646, _T_1644) @[Mux.scala 27:72] + node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] + wire _T_1649 : UInt<3> @[Mux.scala 27:72] + _T_1649 <= _T_1648 @[Mux.scala 27:72] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:150] + node _T_1651 = and(_T_1637, _T_1650) @[el2_lsu_bus_buffer.scala 391:118] + node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1656 = bits(_T_1654, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1658 = bits(_T_1654, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1660 = bits(_T_1654, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1662 = bits(_T_1654, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = or(_T_1663, _T_1664) @[Mux.scala 27:72] + node _T_1668 = or(_T_1667, _T_1665) @[Mux.scala 27:72] + node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] + wire _T_1670 : UInt<1> @[Mux.scala 27:72] + _T_1670 <= _T_1669 @[Mux.scala 27:72] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:5] + node _T_1672 = and(_T_1651, _T_1671) @[el2_lsu_bus_buffer.scala 391:161] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1684 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1685 = or(_T_1681, _T_1682) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1683) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] + wire _T_1688 : UInt<1> @[Mux.scala 27:72] + _T_1688 <= _T_1687 @[Mux.scala 27:72] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:87] + node _T_1690 = and(_T_1672, _T_1689) @[el2_lsu_bus_buffer.scala 392:85] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1692 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1694 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1696 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1698 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1702 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1703 = or(_T_1699, _T_1700) @[Mux.scala 27:72] + node _T_1704 = or(_T_1703, _T_1701) @[Mux.scala 27:72] + node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] + wire _T_1706 : UInt<1> @[Mux.scala 27:72] + _T_1706 <= _T_1705 @[Mux.scala 27:72] + node _T_1707 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1708 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1709 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1710 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1711 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1712 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1713 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1714 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = or(_T_1715, _T_1716) @[Mux.scala 27:72] + node _T_1720 = or(_T_1719, _T_1717) @[Mux.scala 27:72] + node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] + wire _T_1722 : UInt<1> @[Mux.scala 27:72] + _T_1722 <= _T_1721 @[Mux.scala 27:72] + node _T_1723 = and(_T_1706, _T_1722) @[el2_lsu_bus_buffer.scala 393:36] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1727, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = or(_T_1728, _T_1729) @[Mux.scala 27:72] + node _T_1733 = or(_T_1732, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + wire _T_1735 : UInt<32> @[Mux.scala 27:72] + _T_1735 <= _T_1734 @[Mux.scala 27:72] + node _T_1736 = bits(_T_1735, 31, 3) @[el2_lsu_bus_buffer.scala 394:35] + node _T_1737 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1738 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1739 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1740 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1740, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1746 = or(_T_1745, _T_1743) @[Mux.scala 27:72] + node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] + wire _T_1748 : UInt<32> @[Mux.scala 27:72] + _T_1748 <= _T_1747 @[Mux.scala 27:72] + node _T_1749 = bits(_T_1748, 31, 3) @[el2_lsu_bus_buffer.scala 394:71] + node _T_1750 = eq(_T_1736, _T_1749) @[el2_lsu_bus_buffer.scala 394:41] + node _T_1751 = and(_T_1723, _T_1750) @[el2_lsu_bus_buffer.scala 393:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:81] + node _T_1753 = and(_T_1751, _T_1752) @[el2_lsu_bus_buffer.scala 394:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:107] + node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 394:105] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1757 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1759 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1761 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1763 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1762, _T_1763, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = or(_T_1764, _T_1765) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1766) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] + wire _T_1771 : UInt<1> @[Mux.scala 27:72] + _T_1771 <= _T_1770 @[Mux.scala 27:72] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:8] + node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] + node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1777 = bits(_T_1775, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1779 = bits(_T_1775, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1781 = bits(_T_1775, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1783 = bits(_T_1775, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = or(_T_1784, _T_1785) @[Mux.scala 27:72] + node _T_1789 = or(_T_1788, _T_1786) @[Mux.scala 27:72] + node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] + wire _T_1791 : UInt<1> @[Mux.scala 27:72] + _T_1791 <= _T_1790 @[Mux.scala 27:72] + node _T_1792 = and(_T_1772, _T_1791) @[el2_lsu_bus_buffer.scala 395:38] + node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1797 = bits(_T_1795, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1799 = bits(_T_1795, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1801 = bits(_T_1795, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1803 = bits(_T_1795, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1804, _T_1805) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1806) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] + wire _T_1811 : UInt<1> @[Mux.scala 27:72] + _T_1811 <= _T_1810 @[Mux.scala 27:72] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:109] + node _T_1813 = and(_T_1792, _T_1812) @[el2_lsu_bus_buffer.scala 395:107] + node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1818 = bits(_T_1816, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1820 = bits(_T_1816, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1822 = bits(_T_1816, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1824 = bits(_T_1816, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = or(_T_1825, _T_1826) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1827) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] + wire _T_1832 : UInt<1> @[Mux.scala 27:72] + _T_1832 <= _T_1831 @[Mux.scala 27:72] + node _T_1833 = and(_T_1813, _T_1832) @[el2_lsu_bus_buffer.scala 395:179] + node _T_1834 = or(_T_1755, _T_1833) @[el2_lsu_bus_buffer.scala 394:128] + node _T_1835 = and(_T_1690, _T_1834) @[el2_lsu_bus_buffer.scala 392:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 396:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 396:35] + node _T_1838 = or(_T_1835, _T_1837) @[el2_lsu_bus_buffer.scala 395:253] + obuf_merge_en <= _T_1838 @[el2_lsu_bus_buffer.scala 391:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 398:55] + obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 398:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 399:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 399:93] + node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 399:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 399:54] + _T_1842 <= _T_1841 @[el2_lsu_bus_buffer.scala 399:54] + obuf_valid <= _T_1842 @[el2_lsu_bus_buffer.scala 399:14] + reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_nosend <= _T_1843 @[el2_lsu_bus_buffer.scala 400:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 401:54] + _T_1844 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 401:54] + obuf_cmd_done <= _T_1844 @[el2_lsu_bus_buffer.scala 401:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 402:55] + _T_1845 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 402:55] + obuf_data_done <= _T_1845 @[el2_lsu_bus_buffer.scala 402:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 403:56] + _T_1846 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 403:56] + obuf_rdrsp_pend <= _T_1846 @[el2_lsu_bus_buffer.scala 403:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 404:55] + _T_1847 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 404:55] + obuf_rdrsp_tag <= _T_1847 @[el2_lsu_bus_buffer.scala 404:18] + reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_tag0 <= _T_1848 @[el2_lsu_bus_buffer.scala 405:13] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1849 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1849 <= obuf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_write <= _T_1849 @[el2_lsu_bus_buffer.scala 408:14] + reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + obuf_sideeffect <= _T_1850 @[el2_lsu_bus_buffer.scala 409:19] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_2 of rvclkhdr_26 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1851 <= obuf_addr_in @[el2_lib.scala 514:16] + obuf_addr <= _T_1851 @[el2_lsu_bus_buffer.scala 411:13] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when obuf_wr_en : @[Reg.scala 28:19] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr_3 of rvclkhdr_27 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + obuf_data <= obuf_data_in @[el2_lib.scala 514:16] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 414:54] + _T_1852 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 414:54] + obuf_wr_timer <= _T_1852 @[el2_lsu_bus_buffer.scala 414:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1859 = or(_T_1856, _T_1858) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1861 = or(_T_1855, _T_1860) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1863 = and(_T_1853, _T_1862) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1870 = or(_T_1867, _T_1869) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1872 = or(_T_1866, _T_1871) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1874 = and(_T_1864, _T_1873) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1881 = or(_T_1878, _T_1880) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1883 = or(_T_1877, _T_1882) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1885 = and(_T_1875, _T_1884) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1892 = or(_T_1889, _T_1891) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1894 = or(_T_1888, _T_1893) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1896 = and(_T_1886, _T_1895) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] + WrPtr0_m <= _T_1900 @[el2_lsu_bus_buffer.scala 417:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1906 = or(_T_1903, _T_1905) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1910 = or(_T_1907, _T_1909) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1912 = or(_T_1906, _T_1911) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1914 = and(_T_1901, _T_1913) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1920 = or(_T_1917, _T_1919) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1924 = or(_T_1921, _T_1923) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1926 = or(_T_1920, _T_1925) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1928 = and(_T_1915, _T_1927) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1934 = or(_T_1931, _T_1933) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1938 = or(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1940 = or(_T_1934, _T_1939) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1942 = and(_T_1929, _T_1941) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1948 = or(_T_1945, _T_1947) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1952 = or(_T_1949, _T_1951) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1954 = or(_T_1948, _T_1953) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1956 = and(_T_1943, _T_1955) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] + node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] + node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] + WrPtr1_m <= _T_1960 @[el2_lsu_bus_buffer.scala 423:12] + wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 428:21] + buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + node _T_1961 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1967 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1970 = and(_T_1968, _T_1969) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1972 = and(_T_1970, _T_1971) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1973 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1976 = and(_T_1974, _T_1975) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1978 = and(_T_1976, _T_1977) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1979 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1982 = and(_T_1980, _T_1981) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1984 = and(_T_1982, _T_1983) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] + node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] + node _T_1987 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1988 = and(buf_age[0], _T_1987) @[el2_lsu_bus_buffer.scala 432:59] + node _T_1989 = orr(_T_1988) @[el2_lsu_bus_buffer.scala 432:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 432:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_1993 = and(_T_1990, _T_1992) @[el2_lsu_bus_buffer.scala 432:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_1995 = and(_T_1993, _T_1994) @[el2_lsu_bus_buffer.scala 432:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_1997 = and(_T_1995, _T_1996) @[el2_lsu_bus_buffer.scala 432:123] + node _T_1998 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1999 = and(buf_age[1], _T_1998) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2000 = orr(_T_1999) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2004 = and(_T_2001, _T_2003) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2006 = and(_T_2004, _T_2005) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2008 = and(_T_2006, _T_2007) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2009 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2010 = and(buf_age[2], _T_2009) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2011 = orr(_T_2010) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2015 = and(_T_2012, _T_2014) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2019 = and(_T_2017, _T_2018) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2020 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2021 = and(buf_age[3], _T_2020) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2022 = orr(_T_2021) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2026 = and(_T_2023, _T_2025) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] + node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 433:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2036 = and(_T_2034, _T_2035) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2044 = and(_T_2042, _T_2043) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2048 = and(_T_2046, _T_2047) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] + node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] + node _T_2051 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 436:31] + found_cmdptr0 <= _T_2051 @[el2_lsu_bus_buffer.scala 436:17] + node _T_2052 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 437:31] + found_cmdptr1 <= _T_2052 @[el2_lsu_bus_buffer.scala 437:17] + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_2055 = bits(_T_2054, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2056 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2057 = or(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2058 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2059 = or(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2060 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2061 = or(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2062 = bits(_T_2054, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2063 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2064 = or(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2065 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2066 = or(_T_2064, _T_2065) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2067 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2069 = bits(_T_2054, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2070 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2071 = or(_T_2069, _T_2070) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2072 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2073 = or(_T_2071, _T_2072) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2074 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2075 = or(_T_2073, _T_2074) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] + node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] + CmdPtr0 <= _T_2077 @[el2_lsu_bus_buffer.scala 444:11] + node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2080 = bits(_T_2079, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2081 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2082 = or(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2083 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2084 = or(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2085 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2086 = or(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2087 = bits(_T_2079, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2088 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2089 = or(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2090 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2091 = or(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2092 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2094 = bits(_T_2079, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2095 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2096 = or(_T_2094, _T_2095) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2097 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2098 = or(_T_2096, _T_2097) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2099 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2100 = or(_T_2098, _T_2099) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] + node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] + CmdPtr1 <= _T_2102 @[el2_lsu_bus_buffer.scala 446:11] + node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] + node _T_2105 = bits(_T_2104, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2106 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2107 = or(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2108 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2109 = or(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2110 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2111 = or(_T_2109, _T_2110) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2112 = bits(_T_2104, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2113 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2114 = or(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2115 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2116 = or(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2117 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2118 = or(_T_2116, _T_2117) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2119 = bits(_T_2104, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2120 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2121 = or(_T_2119, _T_2120) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2122 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2123 = or(_T_2121, _T_2122) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2124 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2125 = or(_T_2123, _T_2124) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] + RspPtr <= _T_2127 @[el2_lsu_bus_buffer.scala 447:10] + wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 448:26] + buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 450:25] + buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 452:28] + buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 454:27] + buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 456:24] + buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2133 = and(_T_2131, _T_2132) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2134 = or(_T_2130, _T_2133) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2137 = and(_T_2135, _T_2136) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2142 = or(_T_2134, _T_2141) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2146 = and(_T_2144, _T_2145) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2148 = and(_T_2146, _T_2147) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2149 = or(_T_2142, _T_2148) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2150 = and(_T_2129, _T_2149) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2152 = or(_T_2150, _T_2151) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2158 = and(_T_2156, _T_2157) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2159 = or(_T_2155, _T_2158) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2162 = and(_T_2160, _T_2161) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2167 = or(_T_2159, _T_2166) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2171 = and(_T_2169, _T_2170) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2173 = and(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2174 = or(_T_2167, _T_2173) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2175 = and(_T_2154, _T_2174) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2177 = or(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2183 = and(_T_2181, _T_2182) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2184 = or(_T_2180, _T_2183) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2187 = and(_T_2185, _T_2186) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2192 = or(_T_2184, _T_2191) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2196 = and(_T_2194, _T_2195) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2198 = and(_T_2196, _T_2197) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2199 = or(_T_2192, _T_2198) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2200 = and(_T_2179, _T_2199) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2202 = or(_T_2200, _T_2201) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2208 = and(_T_2206, _T_2207) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2209 = or(_T_2205, _T_2208) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2212 = and(_T_2210, _T_2211) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2214 = and(_T_2212, _T_2213) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2217 = or(_T_2209, _T_2216) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2224 = or(_T_2217, _T_2223) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2225 = and(_T_2204, _T_2224) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2227 = or(_T_2225, _T_2226) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] + node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2235 = and(_T_2233, _T_2234) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2236 = or(_T_2232, _T_2235) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2239 = and(_T_2237, _T_2238) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2244 = or(_T_2236, _T_2243) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2248 = and(_T_2246, _T_2247) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2250 = and(_T_2248, _T_2249) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2251 = or(_T_2244, _T_2250) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2252 = and(_T_2231, _T_2251) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2254 = or(_T_2252, _T_2253) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2260 = and(_T_2258, _T_2259) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2261 = or(_T_2257, _T_2260) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2264 = and(_T_2262, _T_2263) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2269 = or(_T_2261, _T_2268) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2273 = and(_T_2271, _T_2272) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2275 = and(_T_2273, _T_2274) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2276 = or(_T_2269, _T_2275) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2277 = and(_T_2256, _T_2276) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2279 = or(_T_2277, _T_2278) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2285 = and(_T_2283, _T_2284) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2286 = or(_T_2282, _T_2285) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2289 = and(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2294 = or(_T_2286, _T_2293) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2298 = and(_T_2296, _T_2297) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2301 = or(_T_2294, _T_2300) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2302 = and(_T_2281, _T_2301) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2304 = or(_T_2302, _T_2303) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2310 = and(_T_2308, _T_2309) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2311 = or(_T_2307, _T_2310) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2319 = or(_T_2311, _T_2318) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2323 = and(_T_2321, _T_2322) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2326 = or(_T_2319, _T_2325) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2327 = and(_T_2306, _T_2326) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2329 = or(_T_2327, _T_2328) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] + node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2338 = or(_T_2334, _T_2337) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2341 = and(_T_2339, _T_2340) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2346 = or(_T_2338, _T_2345) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2350 = and(_T_2348, _T_2349) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2352 = and(_T_2350, _T_2351) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2353 = or(_T_2346, _T_2352) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2354 = and(_T_2333, _T_2353) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2356 = or(_T_2354, _T_2355) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2362 = and(_T_2360, _T_2361) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2363 = or(_T_2359, _T_2362) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2366 = and(_T_2364, _T_2365) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2371 = or(_T_2363, _T_2370) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2375 = and(_T_2373, _T_2374) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2377 = and(_T_2375, _T_2376) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2378 = or(_T_2371, _T_2377) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2379 = and(_T_2358, _T_2378) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2381 = or(_T_2379, _T_2380) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2387 = and(_T_2385, _T_2386) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2388 = or(_T_2384, _T_2387) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2391 = and(_T_2389, _T_2390) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2396 = or(_T_2388, _T_2395) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2400 = and(_T_2398, _T_2399) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2402 = and(_T_2400, _T_2401) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2403 = or(_T_2396, _T_2402) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2404 = and(_T_2383, _T_2403) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2406 = or(_T_2404, _T_2405) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2412 = and(_T_2410, _T_2411) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2413 = or(_T_2409, _T_2412) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2416 = and(_T_2414, _T_2415) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2418 = and(_T_2416, _T_2417) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2421 = or(_T_2413, _T_2420) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2425 = and(_T_2423, _T_2424) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2427 = and(_T_2425, _T_2426) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2428 = or(_T_2421, _T_2427) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2429 = and(_T_2408, _T_2428) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2431 = or(_T_2429, _T_2430) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] + node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2440 = or(_T_2436, _T_2439) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2443 = and(_T_2441, _T_2442) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2445 = and(_T_2443, _T_2444) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2447 = and(_T_2445, _T_2446) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2448 = or(_T_2440, _T_2447) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2454 = and(_T_2452, _T_2453) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2455 = or(_T_2448, _T_2454) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2456 = and(_T_2435, _T_2455) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2465 = or(_T_2461, _T_2464) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2468 = and(_T_2466, _T_2467) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2470 = and(_T_2468, _T_2469) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2472 = and(_T_2470, _T_2471) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2473 = or(_T_2465, _T_2472) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2477 = and(_T_2475, _T_2476) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2479 = and(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2480 = or(_T_2473, _T_2479) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2481 = and(_T_2460, _T_2480) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2483 = or(_T_2481, _T_2482) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2489 = and(_T_2487, _T_2488) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2490 = or(_T_2486, _T_2489) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2493 = and(_T_2491, _T_2492) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2495 = and(_T_2493, _T_2494) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2497 = and(_T_2495, _T_2496) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2498 = or(_T_2490, _T_2497) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2502 = and(_T_2500, _T_2501) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2505 = or(_T_2498, _T_2504) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2506 = and(_T_2485, _T_2505) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2508 = or(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2514 = and(_T_2512, _T_2513) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2515 = or(_T_2511, _T_2514) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2518 = and(_T_2516, _T_2517) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2520 = and(_T_2518, _T_2519) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2522 = and(_T_2520, _T_2521) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2523 = or(_T_2515, _T_2522) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2530 = or(_T_2523, _T_2529) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2531 = and(_T_2510, _T_2530) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2533 = or(_T_2531, _T_2532) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 463:22] + buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2540 = and(_T_2536, _T_2539) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2545 = and(_T_2541, _T_2544) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2550 = and(_T_2546, _T_2549) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2555 = and(_T_2551, _T_2554) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2563 = and(_T_2559, _T_2562) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2568 = and(_T_2564, _T_2567) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2573 = and(_T_2569, _T_2572) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2578 = and(_T_2574, _T_2577) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] + node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] + node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2586 = and(_T_2582, _T_2585) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2591 = and(_T_2587, _T_2590) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2596 = and(_T_2592, _T_2595) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2601 = and(_T_2597, _T_2600) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] + node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] + node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2609 = and(_T_2605, _T_2608) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2614 = and(_T_2610, _T_2613) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2619 = and(_T_2615, _T_2618) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2624 = and(_T_2620, _T_2623) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] + node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] + node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] + buf_age[0] <= _T_2558 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[1] <= _T_2581 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[2] <= _T_2604 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[3] <= _T_2627 @[el2_lsu_bus_buffer.scala 465:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2632 = and(_T_2630, _T_2631) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2638 = and(_T_2636, _T_2637) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2644 = and(_T_2642, _T_2643) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2650 = and(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] + node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] + node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2659 = and(_T_2657, _T_2658) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2671 = and(_T_2669, _T_2670) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2677 = and(_T_2675, _T_2676) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] + node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] + node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2686 = and(_T_2684, _T_2685) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2692 = and(_T_2690, _T_2691) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2704 = and(_T_2702, _T_2703) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] + node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] + node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2713 = and(_T_2711, _T_2712) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2725 = and(_T_2723, _T_2724) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] + node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2654 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[1] <= _T_2681 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[2] <= _T_2708 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[3] <= _T_2735 @[el2_lsu_bus_buffer.scala 466:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2738 = and(_T_2736, _T_2737) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2741 = and(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2744 = and(_T_2742, _T_2743) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] + node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2753 = and(_T_2751, _T_2752) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2759 = and(_T_2757, _T_2758) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2762 = and(_T_2760, _T_2761) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] + node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2768 = and(_T_2766, _T_2767) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2774 = and(_T_2772, _T_2773) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] + node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] + node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2783 = and(_T_2781, _T_2782) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2786 = and(_T_2784, _T_2785) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2792 = and(_T_2790, _T_2791) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] + node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] + node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2750 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[1] <= _T_2765 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[2] <= _T_2780 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[3] <= _T_2795 @[el2_lsu_bus_buffer.scala 467:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2800 = or(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2804 = and(_T_2802, _T_2803) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2808 = and(_T_2806, _T_2807) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2809 = or(_T_2801, _T_2808) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2816 = or(_T_2809, _T_2815) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2817 = and(_T_2797, _T_2816) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2822 = or(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2826 = and(_T_2824, _T_2825) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2828 = and(_T_2826, _T_2827) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2830 = and(_T_2828, _T_2829) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2831 = or(_T_2823, _T_2830) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2835 = and(_T_2833, _T_2834) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2837 = and(_T_2835, _T_2836) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2838 = or(_T_2831, _T_2837) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2839 = and(_T_2819, _T_2838) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2844 = or(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2848 = and(_T_2846, _T_2847) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2850 = and(_T_2848, _T_2849) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2852 = and(_T_2850, _T_2851) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2853 = or(_T_2845, _T_2852) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2857 = and(_T_2855, _T_2856) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2859 = and(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2860 = or(_T_2853, _T_2859) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2861 = and(_T_2841, _T_2860) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2866 = or(_T_2864, _T_2865) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2874 = and(_T_2872, _T_2873) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2875 = or(_T_2867, _T_2874) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2879 = and(_T_2877, _T_2878) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2881 = and(_T_2879, _T_2880) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2882 = or(_T_2875, _T_2881) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2883 = and(_T_2863, _T_2882) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] + node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] + node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2891 = or(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2897 = and(_T_2895, _T_2896) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2899 = and(_T_2897, _T_2898) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2900 = or(_T_2892, _T_2899) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2907 = or(_T_2900, _T_2906) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2908 = and(_T_2888, _T_2907) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2913 = or(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2917 = and(_T_2915, _T_2916) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2919 = and(_T_2917, _T_2918) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2921 = and(_T_2919, _T_2920) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2922 = or(_T_2914, _T_2921) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2926 = and(_T_2924, _T_2925) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2928 = and(_T_2926, _T_2927) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2929 = or(_T_2922, _T_2928) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2930 = and(_T_2910, _T_2929) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2935 = or(_T_2933, _T_2934) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2943 = and(_T_2941, _T_2942) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2944 = or(_T_2936, _T_2943) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2950 = and(_T_2948, _T_2949) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2951 = or(_T_2944, _T_2950) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2952 = and(_T_2932, _T_2951) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2957 = or(_T_2955, _T_2956) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2961 = and(_T_2959, _T_2960) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2963 = and(_T_2961, _T_2962) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2966 = or(_T_2958, _T_2965) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2970 = and(_T_2968, _T_2969) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2972 = and(_T_2970, _T_2971) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2973 = or(_T_2966, _T_2972) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2974 = and(_T_2954, _T_2973) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] + node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] + node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2982 = or(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2986 = and(_T_2984, _T_2985) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2988 = and(_T_2986, _T_2987) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2991 = or(_T_2983, _T_2990) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2998 = or(_T_2991, _T_2997) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2999 = and(_T_2979, _T_2998) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3004 = or(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3008 = and(_T_3006, _T_3007) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3010 = and(_T_3008, _T_3009) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3012 = and(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3013 = or(_T_3005, _T_3012) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3017 = and(_T_3015, _T_3016) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3019 = and(_T_3017, _T_3018) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3020 = or(_T_3013, _T_3019) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3021 = and(_T_3001, _T_3020) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3026 = or(_T_3024, _T_3025) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3030 = and(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3035 = or(_T_3027, _T_3034) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3039 = and(_T_3037, _T_3038) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3042 = or(_T_3035, _T_3041) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3043 = and(_T_3023, _T_3042) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3052 = and(_T_3050, _T_3051) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3054 = and(_T_3052, _T_3053) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3056 = and(_T_3054, _T_3055) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3057 = or(_T_3049, _T_3056) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3061 = and(_T_3059, _T_3060) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3063 = and(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3064 = or(_T_3057, _T_3063) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3065 = and(_T_3045, _T_3064) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] + node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3077 = and(_T_3075, _T_3076) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3079 = and(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3081 = and(_T_3079, _T_3080) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3082 = or(_T_3074, _T_3081) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3086 = and(_T_3084, _T_3085) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3088 = and(_T_3086, _T_3087) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3089 = or(_T_3082, _T_3088) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3090 = and(_T_3070, _T_3089) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3095 = or(_T_3093, _T_3094) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3099 = and(_T_3097, _T_3098) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3101 = and(_T_3099, _T_3100) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3103 = and(_T_3101, _T_3102) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3104 = or(_T_3096, _T_3103) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3108 = and(_T_3106, _T_3107) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3110 = and(_T_3108, _T_3109) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3111 = or(_T_3104, _T_3110) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3112 = and(_T_3092, _T_3111) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3117 = or(_T_3115, _T_3116) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3121 = and(_T_3119, _T_3120) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3125 = and(_T_3123, _T_3124) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3126 = or(_T_3118, _T_3125) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3130 = and(_T_3128, _T_3129) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3132 = and(_T_3130, _T_3131) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3133 = or(_T_3126, _T_3132) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3134 = and(_T_3114, _T_3133) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3145 = and(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3147 = and(_T_3145, _T_3146) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3148 = or(_T_3140, _T_3147) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3152 = and(_T_3150, _T_3151) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3154 = and(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3155 = or(_T_3148, _T_3154) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3156 = and(_T_3136, _T_3155) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] + node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2886 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[1] <= _T_2977 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[2] <= _T_3068 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[3] <= _T_3159 @[el2_lsu_bus_buffer.scala 469:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3162 = or(_T_3160, _T_3161) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3165 = or(_T_3163, _T_3164) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3168 = or(_T_3166, _T_3167) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3171 = or(_T_3169, _T_3170) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] + node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3177 = or(_T_3175, _T_3176) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3180 = or(_T_3178, _T_3179) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3183 = or(_T_3181, _T_3182) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3186 = or(_T_3184, _T_3185) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3192 = or(_T_3190, _T_3191) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3195 = or(_T_3193, _T_3194) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3198 = or(_T_3196, _T_3197) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3201 = or(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] + node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] + node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3207 = or(_T_3205, _T_3206) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3210 = or(_T_3208, _T_3209) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3213 = or(_T_3211, _T_3212) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3216 = or(_T_3214, _T_3215) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] + node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] + node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3174 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[1] <= _T_3189 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[2] <= _T_3204 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[3] <= _T_3219 @[el2_lsu_bus_buffer.scala 473:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3223 = or(_T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3225 = and(_T_3220, _T_3224) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3229 = or(_T_3227, _T_3228) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3231 = and(_T_3226, _T_3230) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3235 = or(_T_3233, _T_3234) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3237 = and(_T_3232, _T_3236) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3241 = or(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3243 = and(_T_3238, _T_3242) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] + node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] + node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3250 = or(_T_3248, _T_3249) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3252 = and(_T_3247, _T_3251) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3256 = or(_T_3254, _T_3255) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3258 = and(_T_3253, _T_3257) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3262 = or(_T_3260, _T_3261) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3264 = and(_T_3259, _T_3263) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3268 = or(_T_3266, _T_3267) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3270 = and(_T_3265, _T_3269) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] + node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] + node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3277 = or(_T_3275, _T_3276) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3279 = and(_T_3274, _T_3278) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3283 = or(_T_3281, _T_3282) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3285 = and(_T_3280, _T_3284) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3289 = or(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3291 = and(_T_3286, _T_3290) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3295 = or(_T_3293, _T_3294) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3297 = and(_T_3292, _T_3296) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] + node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] + node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3304 = or(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3306 = and(_T_3301, _T_3305) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3310 = or(_T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3312 = and(_T_3307, _T_3311) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3316 = or(_T_3314, _T_3315) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3318 = and(_T_3313, _T_3317) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3322 = or(_T_3320, _T_3321) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3324 = and(_T_3319, _T_3323) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] + node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] + node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3246 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[1] <= _T_3273 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[2] <= _T_3300 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[3] <= _T_3327 @[el2_lsu_bus_buffer.scala 474:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] + node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] + node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3338 @[el2_lsu_bus_buffer.scala 479:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3343 = and(_T_3341, _T_3342) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3352 = and(_T_3350, _T_3351) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3361 = and(_T_3359, _T_3360) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3370 = and(_T_3368, _T_3369) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[el2_lsu_bus_buffer.scala 480:46] + buf_byteen_in[0] <= _T_3347 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[2] <= _T_3365 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[3] <= _T_3374 @[el2_lsu_bus_buffer.scala 480:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3378 = and(_T_3376, _T_3377) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3390 = and(_T_3388, _T_3389) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3396 = and(_T_3394, _T_3395) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[el2_lsu_bus_buffer.scala 482:44] + buf_addr_in[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[2] <= _T_3392 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[3] <= _T_3398 @[el2_lsu_bus_buffer.scala 482:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] + node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] + node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] + buf_dual_in <= _T_3409 @[el2_lsu_bus_buffer.scala 483:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] + node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] + node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] + buf_samedw_in <= _T_3420 @[el2_lsu_bus_buffer.scala 484:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] + node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] + node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3435 @[el2_lsu_bus_buffer.scala 485:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3439 = and(_T_3437, _T_3438) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3444 = and(_T_3442, _T_3443) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3454 = and(_T_3452, _T_3453) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] + node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] + node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3458 @[el2_lsu_bus_buffer.scala 486:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3462 = and(_T_3460, _T_3461) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3468 = and(_T_3466, _T_3467) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3474 = and(_T_3472, _T_3473) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3480 = and(_T_3478, _T_3479) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[el2_lsu_bus_buffer.scala 487:47] + buf_dualtag_in[0] <= _T_3464 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[1] <= _T_3470 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[2] <= _T_3476 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[3] <= _T_3482 @[el2_lsu_bus_buffer.scala 487:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] + node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] + node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3493 @[el2_lsu_bus_buffer.scala 488:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] + node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] + node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] + buf_unsign_in <= _T_3504 @[el2_lsu_bus_buffer.scala 489:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3506 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3509 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3512 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3515 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[el2_lsu_bus_buffer.scala 490:42] + buf_sz_in[0] <= _T_3507 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[1] <= _T_3510 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[2] <= _T_3513 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[3] <= _T_3516 @[el2_lsu_bus_buffer.scala 490:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] + node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] + node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] + buf_write_in <= _T_3527 @[el2_lsu_bus_buffer.scala 491:16] + node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3528 : @[Conditional.scala 40:58] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[0] <= _T_3530 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3534 = and(_T_3532, _T_3533) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3536 = and(_T_3534, _T_3535) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3540 = or(_T_3536, _T_3539) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3541 = and(_T_3531, _T_3540) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3544 = or(_T_3541, _T_3543) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[0] <= _T_3544 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3547 = bits(_T_3546, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[0] <= _T_3550 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3551 : @[Conditional.scala 39:67] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[0] <= _T_3553 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3555 : @[Conditional.scala 39:67] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3564 = and(obuf_merge, _T_3563) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3565 = or(_T_3562, _T_3564) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3566 = and(_T_3565, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[0] <= _T_3569 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3570 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3575 = and(_T_3573, _T_3574) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[0] <= _T_3575 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[0] <= _T_3576 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[0] <= _T_3579 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[0] <= _T_3582 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[0] <= _T_3588 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3589 : @[Conditional.scala 39:67] + node _T_3590 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3593 = and(_T_3590, _T_3592) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3595 = bits(_T_3594, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3598 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3600 = and(_T_3597, _T_3599) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3607 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3609 = and(_T_3606, _T_3608) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = or(_T_3618, _T_3619) @[Mux.scala 27:72] + node _T_3623 = or(_T_3622, _T_3620) @[Mux.scala 27:72] + node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] + wire _T_3625 : UInt<1> @[Mux.scala 27:72] + _T_3625 <= _T_3624 @[Mux.scala 27:72] + node _T_3626 = and(_T_3609, _T_3625) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3628 = and(_T_3626, _T_3627) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3630 = or(_T_3604, _T_3629) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[0] <= _T_3633 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3639 = and(_T_3637, _T_3638) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3640 = or(_T_3636, _T_3639) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3642 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3643 = not(_T_3642) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3644 = and(_T_3641, _T_3643) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3647 = and(_T_3645, _T_3646) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3648 = or(_T_3640, _T_3647) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3650 = or(_T_3635, _T_3649) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[0] <= _T_3650 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[0] <= _T_3652 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[0] <= _T_3654 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3662 = or(_T_3657, _T_3661) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3665 = and(_T_3663, _T_3664) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3666 = or(_T_3662, _T_3665) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3667 = and(_T_3655, _T_3666) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[0] <= _T_3667 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[0] <= _T_3675 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3676 : @[Conditional.scala 39:67] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3680 = bits(_T_3679, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[0] <= _T_3684 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3687 = bits(_T_3686, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3689 = and(_T_3687, _T_3688) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3690 = or(_T_3685, _T_3689) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[0] <= _T_3691 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[0] <= _T_3693 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3694 : @[Conditional.scala 39:67] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[0] <= _T_3696 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3700 = or(_T_3697, _T_3699) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[0] <= _T_3701 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3702 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3703 : @[Reg.scala 28:19] + _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[0] <= _T_3704 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3705 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[0] <= _T_3705 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3706 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[0] <= _T_3706 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3707 : @[Reg.scala 28:19] + _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[0] <= _T_3708 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3710 : @[Reg.scala 28:19] + _T_3711 <= _T_3709 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[0] <= _T_3711 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3713 : @[Reg.scala 28:19] + _T_3714 <= _T_3712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3714 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3716 : @[Reg.scala 28:19] + _T_3717 <= _T_3715 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3717 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3719 : @[Reg.scala 28:19] + _T_3720 <= _T_3718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3720 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3721 : @[Conditional.scala 40:58] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[1] <= _T_3723 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3727 = and(_T_3725, _T_3726) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3729 = and(_T_3727, _T_3728) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3733 = or(_T_3729, _T_3732) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3734 = and(_T_3724, _T_3733) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3737 = or(_T_3734, _T_3736) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[1] <= _T_3737 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3740 = bits(_T_3739, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[1] <= _T_3743 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3744 : @[Conditional.scala 39:67] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[1] <= _T_3746 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3748 : @[Conditional.scala 39:67] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3752 = and(_T_3750, _T_3751) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3757 = and(obuf_merge, _T_3756) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3758 = or(_T_3755, _T_3757) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3759 = and(_T_3758, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[1] <= _T_3762 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3763 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3768 = and(_T_3766, _T_3767) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[1] <= _T_3768 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[1] <= _T_3769 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[1] <= _T_3772 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[1] <= _T_3775 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[1] <= _T_3781 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3782 : @[Conditional.scala 39:67] + node _T_3783 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3786 = and(_T_3783, _T_3785) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3788 = bits(_T_3787, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3791 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3793 = and(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3800 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3802 = and(_T_3799, _T_3801) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3821 = and(_T_3819, _T_3820) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3823 = or(_T_3797, _T_3822) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[1] <= _T_3826 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3833 = or(_T_3829, _T_3832) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3835 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3836 = not(_T_3835) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3837 = and(_T_3834, _T_3836) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3840 = and(_T_3838, _T_3839) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3841 = or(_T_3833, _T_3840) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3843 = or(_T_3828, _T_3842) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[1] <= _T_3843 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[1] <= _T_3845 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[1] <= _T_3847 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3854 = and(_T_3852, _T_3853) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3855 = or(_T_3850, _T_3854) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3858 = and(_T_3856, _T_3857) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3859 = or(_T_3855, _T_3858) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3860 = and(_T_3848, _T_3859) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[1] <= _T_3860 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[1] <= _T_3868 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3869 : @[Conditional.scala 39:67] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3873 = bits(_T_3872, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3874 = or(_T_3871, _T_3873) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[1] <= _T_3877 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3880 = bits(_T_3879, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3882 = and(_T_3880, _T_3881) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3883 = or(_T_3878, _T_3882) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[1] <= _T_3884 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[1] <= _T_3886 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3887 : @[Conditional.scala 39:67] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[1] <= _T_3889 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3893 = or(_T_3890, _T_3892) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[1] <= _T_3894 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3895 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3896 : @[Reg.scala 28:19] + _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[1] <= _T_3897 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3898 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[1] <= _T_3898 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3899 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[1] <= _T_3899 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3900 : @[Reg.scala 28:19] + _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[1] <= _T_3901 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3903 : @[Reg.scala 28:19] + _T_3904 <= _T_3902 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[1] <= _T_3904 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3906 : @[Reg.scala 28:19] + _T_3907 <= _T_3905 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[1] <= _T_3907 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3909 : @[Reg.scala 28:19] + _T_3910 <= _T_3908 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[1] <= _T_3910 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3912 : @[Reg.scala 28:19] + _T_3913 <= _T_3911 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[1] <= _T_3913 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3914 : @[Conditional.scala 40:58] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[2] <= _T_3916 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3920 = and(_T_3918, _T_3919) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3922 = and(_T_3920, _T_3921) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3926 = or(_T_3922, _T_3925) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3927 = and(_T_3917, _T_3926) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3930 = or(_T_3927, _T_3929) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[2] <= _T_3930 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3933 = bits(_T_3932, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[2] <= _T_3936 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3937 : @[Conditional.scala 39:67] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[2] <= _T_3939 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3941 : @[Conditional.scala 39:67] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3950 = and(obuf_merge, _T_3949) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3951 = or(_T_3948, _T_3950) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3952 = and(_T_3951, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[2] <= _T_3955 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3956 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3961 = and(_T_3959, _T_3960) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[2] <= _T_3961 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[2] <= _T_3962 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[2] <= _T_3965 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[2] <= _T_3968 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[2] <= _T_3974 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3975 : @[Conditional.scala 39:67] + node _T_3976 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3979 = and(_T_3976, _T_3978) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3981 = bits(_T_3980, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3984 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3986 = and(_T_3983, _T_3985) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3993 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3995 = and(_T_3992, _T_3994) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4007 = mux(_T_4002, _T_4003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4008 = or(_T_4004, _T_4005) @[Mux.scala 27:72] + node _T_4009 = or(_T_4008, _T_4006) @[Mux.scala 27:72] + node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] + wire _T_4011 : UInt<1> @[Mux.scala 27:72] + _T_4011 <= _T_4010 @[Mux.scala 27:72] + node _T_4012 = and(_T_3995, _T_4011) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4014 = and(_T_4012, _T_4013) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4016 = or(_T_3990, _T_4015) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[2] <= _T_4019 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4025 = and(_T_4023, _T_4024) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4026 = or(_T_4022, _T_4025) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4028 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4029 = not(_T_4028) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4030 = and(_T_4027, _T_4029) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4033 = and(_T_4031, _T_4032) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4034 = or(_T_4026, _T_4033) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4036 = or(_T_4021, _T_4035) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[2] <= _T_4036 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[2] <= _T_4038 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[2] <= _T_4040 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4047 = and(_T_4045, _T_4046) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4048 = or(_T_4043, _T_4047) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4051 = and(_T_4049, _T_4050) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4052 = or(_T_4048, _T_4051) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4053 = and(_T_4041, _T_4052) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[2] <= _T_4053 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[2] <= _T_4061 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4062 : @[Conditional.scala 39:67] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4066 = bits(_T_4065, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4067 = or(_T_4064, _T_4066) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[2] <= _T_4070 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4073 = bits(_T_4072, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4075 = and(_T_4073, _T_4074) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4076 = or(_T_4071, _T_4075) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[2] <= _T_4077 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[2] <= _T_4079 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4080 : @[Conditional.scala 39:67] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[2] <= _T_4082 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4086 = or(_T_4083, _T_4085) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[2] <= _T_4087 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4088 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4089 : @[Reg.scala 28:19] + _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[2] <= _T_4090 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4091 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[2] <= _T_4091 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4092 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[2] <= _T_4092 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[2] <= _T_4094 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[2] <= _T_4097 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[2] <= _T_4100 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[2] <= _T_4103 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4105 : @[Reg.scala 28:19] + _T_4106 <= _T_4104 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[2] <= _T_4106 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4107 : @[Conditional.scala 40:58] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[3] <= _T_4109 @[el2_lsu_bus_buffer.scala 496:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_4113 = and(_T_4111, _T_4112) @[el2_lsu_bus_buffer.scala 497:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_4115 = and(_T_4113, _T_4114) @[el2_lsu_bus_buffer.scala 497:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 497:161] + node _T_4119 = or(_T_4115, _T_4118) @[el2_lsu_bus_buffer.scala 497:132] + node _T_4120 = and(_T_4110, _T_4119) @[el2_lsu_bus_buffer.scala 497:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[el2_lsu_bus_buffer.scala 497:201] + node _T_4123 = or(_T_4120, _T_4122) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[3] <= _T_4123 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 499:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[el2_lsu_bus_buffer.scala 500:47] + node _T_4126 = bits(_T_4125, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[3] <= _T_4129 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4130 : @[Conditional.scala 39:67] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[3] <= _T_4132 @[el2_lsu_bus_buffer.scala 503:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4134 : @[Conditional.scala 39:67] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_4138 = and(_T_4136, _T_4137) @[el2_lsu_bus_buffer.scala 507:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 507:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_4143 = and(obuf_merge, _T_4142) @[el2_lsu_bus_buffer.scala 508:91] + node _T_4144 = or(_T_4141, _T_4143) @[el2_lsu_bus_buffer.scala 508:77] + node _T_4145 = and(_T_4144, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 509:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[3] <= _T_4148 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_4149 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 512:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[el2_lsu_bus_buffer.scala 512:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_4154 = and(_T_4152, _T_4153) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[3] <= _T_4154 @[el2_lsu_bus_buffer.scala 512:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[3] <= _T_4155 @[el2_lsu_bus_buffer.scala 513:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[3] <= _T_4158 @[el2_lsu_bus_buffer.scala 514:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[3] <= _T_4161 @[el2_lsu_bus_buffer.scala 515:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[el2_lsu_bus_buffer.scala 516:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[3] <= _T_4167 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4168 : @[Conditional.scala 39:67] + node _T_4169 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 519:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_4172 = and(_T_4169, _T_4171) @[el2_lsu_bus_buffer.scala 519:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[el2_lsu_bus_buffer.scala 519:55] + node _T_4174 = bits(_T_4173, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[el2_lsu_bus_buffer.scala 520:28] + node _T_4177 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 520:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_4179 = and(_T_4176, _T_4178) @[el2_lsu_bus_buffer.scala 520:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_4181 = and(_T_4179, _T_4180) @[el2_lsu_bus_buffer.scala 520:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 521:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[el2_lsu_bus_buffer.scala 521:68] + node _T_4186 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 521:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_4188 = and(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 521:85] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4200 = mux(_T_4195, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4201 = or(_T_4197, _T_4198) @[Mux.scala 27:72] + node _T_4202 = or(_T_4201, _T_4199) @[Mux.scala 27:72] + node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] + wire _T_4204 : UInt<1> @[Mux.scala 27:72] + _T_4204 <= _T_4203 @[Mux.scala 27:72] + node _T_4205 = and(_T_4188, _T_4204) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4207 = and(_T_4205, _T_4206) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4209 = or(_T_4183, _T_4208) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[3] <= _T_4212 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4218 = and(_T_4216, _T_4217) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4219 = or(_T_4215, _T_4218) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4221 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4222 = not(_T_4221) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4223 = and(_T_4220, _T_4222) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4226 = and(_T_4224, _T_4225) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4227 = or(_T_4219, _T_4226) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4229 = or(_T_4214, _T_4228) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[3] <= _T_4231 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[3] <= _T_4233 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4240 = and(_T_4238, _T_4239) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4241 = or(_T_4236, _T_4240) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4244 = and(_T_4242, _T_4243) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4245 = or(_T_4241, _T_4244) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4246 = and(_T_4234, _T_4245) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[3] <= _T_4246 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[3] <= _T_4254 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4255 : @[Conditional.scala 39:67] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4259 = bits(_T_4258, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4260 = or(_T_4257, _T_4259) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[3] <= _T_4263 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4266 = bits(_T_4265, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4268 = and(_T_4266, _T_4267) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4269 = or(_T_4264, _T_4268) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[3] <= _T_4270 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[3] <= _T_4272 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4273 : @[Conditional.scala 39:67] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[3] <= _T_4275 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4279 = or(_T_4276, _T_4278) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[3] <= _T_4280 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4281 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state[3] <= _T_4283 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4284 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[3] <= _T_4284 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4285 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[3] <= _T_4285 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualtag[3] <= _T_4287 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4289 : @[Reg.scala 28:19] + _T_4290 <= _T_4288 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dual[3] <= _T_4290 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4292 : @[Reg.scala 28:19] + _T_4293 <= _T_4291 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[3] <= _T_4293 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= _T_4294 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[3] <= _T_4296 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= _T_4297 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4299 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4300 : @[Reg.scala 28:19] + _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4304 : @[Reg.scala 28:19] + _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] + node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] + node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] + buf_ldfwd <= _T_4310 @[el2_lsu_bus_buffer.scala 562:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4311 : @[Reg.scala 28:19] + _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4313 : @[Reg.scala 28:19] + _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4317 : @[Reg.scala 28:19] + _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4312 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[1] <= _T_4314 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[2] <= _T_4316 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[3] <= _T_4318 @[el2_lsu_bus_buffer.scala 563:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4320 : @[Reg.scala 28:19] + _T_4321 <= _T_4319 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4323 : @[Reg.scala 28:19] + _T_4324 <= _T_4322 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= _T_4325 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4329 : @[Reg.scala 28:19] + _T_4330 <= _T_4328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] + node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] + node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] + buf_sideeffect <= _T_4333 @[el2_lsu_bus_buffer.scala 564:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4335 : @[Reg.scala 28:19] + _T_4336 <= _T_4334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= _T_4337 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4341 : @[Reg.scala 28:19] + _T_4342 <= _T_4340 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4344 : @[Reg.scala 28:19] + _T_4345 <= _T_4343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] + node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] + node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] + buf_unsign <= _T_4348 @[el2_lsu_bus_buffer.scala 565:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= _T_4349 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4352 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4353 : @[Reg.scala 28:19] + _T_4354 <= _T_4352 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4355 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4356 : @[Reg.scala 28:19] + _T_4357 <= _T_4355 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4358 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= _T_4358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] + node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] + node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] + buf_write <= _T_4363 @[el2_lsu_bus_buffer.scala 566:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4364 : @[Reg.scala 28:19] + _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4368 : @[Reg.scala 28:19] + _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4365 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[1] <= _T_4367 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[2] <= _T_4369 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[3] <= _T_4371 @[el2_lsu_bus_buffer.scala 567:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_4 of rvclkhdr_28 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_4372 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4373 <= buf_addr_in[0] @[el2_lib.scala 514:16] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_5 of rvclkhdr_29 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_4374 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4375 <= buf_addr_in[1] @[el2_lib.scala 514:16] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_6 of rvclkhdr_30 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_4376 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4377 <= buf_addr_in[2] @[el2_lib.scala 514:16] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_7 of rvclkhdr_31 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_4378 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4379 <= buf_addr_in[3] @[el2_lib.scala 514:16] + buf_addr[0] <= _T_4373 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[1] <= _T_4375 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[2] <= _T_4377 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[3] <= _T_4379 @[el2_lsu_bus_buffer.scala 568:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4380 : @[Reg.scala 28:19] + _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4384 : @[Reg.scala 28:19] + _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4381 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[1] <= _T_4383 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[2] <= _T_4385 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[3] <= _T_4387 @[el2_lsu_bus_buffer.scala 569:14] + inst rvclkhdr_8 of rvclkhdr_32 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4388 <= buf_data_in[0] @[el2_lib.scala 514:16] + inst rvclkhdr_9 of rvclkhdr_33 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4389 <= buf_data_in[1] @[el2_lib.scala 514:16] + inst rvclkhdr_10 of rvclkhdr_34 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4390 <= buf_data_in[2] @[el2_lib.scala 514:16] + inst rvclkhdr_11 of rvclkhdr_35 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4391 <= buf_data_in[3] @[el2_lib.scala 514:16] + buf_data[0] <= _T_4388 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[1] <= _T_4389 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[2] <= _T_4390 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[3] <= _T_4391 @[el2_lsu_bus_buffer.scala 570:12] + node _T_4392 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4395 = and(_T_4393, _T_4394) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4396 <= _T_4395 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4397 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4400 = and(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4401 <= _T_4400 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4402 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4405 = and(_T_4403, _T_4404) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4406 <= _T_4405 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4407 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4410 = and(_T_4408, _T_4409) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4411 <= _T_4410 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] + node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] + node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] + buf_error <= _T_4414 @[el2_lsu_bus_buffer.scala 571:13] + node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 574:28] + node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 574:94] + node _T_4419 = add(_T_4416, _T_4418) @[el2_lsu_bus_buffer.scala 574:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[el2_lsu_bus_buffer.scala 574:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4425 = add(_T_4421, _T_4422) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4426 = add(_T_4425, _T_4423) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4427 = add(_T_4426, _T_4424) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4428 = add(_T_4420, _T_4427) @[el2_lsu_bus_buffer.scala 574:169] + node buf_numvld_any = tail(_T_4428, 1) @[el2_lsu_bus_buffer.scala 574:169] + node _T_4429 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4431 = and(_T_4429, _T_4430) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4433 = and(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4434 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4436 = and(_T_4434, _T_4435) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4438 = and(_T_4436, _T_4437) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4439 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4441 = and(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4443 = and(_T_4441, _T_4442) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4444 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4446 = and(_T_4444, _T_4445) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4448 = and(_T_4446, _T_4447) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4449 = add(_T_4448, _T_4443) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4450 = add(_T_4449, _T_4438) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4451 = add(_T_4450, _T_4433) @[el2_lsu_bus_buffer.scala 575:142] + buf_numvld_wrcmd_any <= _T_4451 @[el2_lsu_bus_buffer.scala 575:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4454 = and(_T_4452, _T_4453) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4457 = and(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4460 = and(_T_4458, _T_4459) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4463 = and(_T_4461, _T_4462) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4464 = add(_T_4463, _T_4460) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4465 = add(_T_4464, _T_4457) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4466 = add(_T_4465, _T_4454) @[el2_lsu_bus_buffer.scala 576:126] + buf_numvld_cmd_any <= _T_4466 @[el2_lsu_bus_buffer.scala 576:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4470 = and(_T_4468, _T_4469) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4471 = or(_T_4467, _T_4470) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4475 = and(_T_4473, _T_4474) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4476 = or(_T_4472, _T_4475) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4480 = and(_T_4478, _T_4479) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4481 = or(_T_4477, _T_4480) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4485 = and(_T_4483, _T_4484) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4486 = or(_T_4482, _T_4485) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4487 = add(_T_4486, _T_4481) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4488 = add(_T_4487, _T_4476) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4489 = add(_T_4488, _T_4471) @[el2_lsu_bus_buffer.scala 577:154] + buf_numvld_pend_any <= _T_4489 @[el2_lsu_bus_buffer.scala 577:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4494 = or(_T_4493, _T_4492) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4495 = or(_T_4494, _T_4491) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4496 = or(_T_4495, _T_4490) @[el2_lsu_bus_buffer.scala 578:93] + any_done_wait_state <= _T_4496 @[el2_lsu_bus_buffer.scala 578:23] + node _T_4497 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 579:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[el2_lsu_bus_buffer.scala 579:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 580:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 580:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 580:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[el2_lsu_bus_buffer.scala 580:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[el2_lsu_bus_buffer.scala 580:30] + node _T_4502 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4503 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4504 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4505 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4506 = or(_T_4502, _T_4503) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4507 = or(_T_4506, _T_4504) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4508 = or(_T_4507, _T_4505) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:72] + node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 581:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:86] + node _T_4513 = and(_T_4511, _T_4512) @[el2_lsu_bus_buffer.scala 581:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[el2_lsu_bus_buffer.scala 581:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 583:51] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 583:72] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:94] + node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 583:92] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:111] + node _T_4519 = and(_T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 583:109] + io.lsu_nonblock_load_valid_m <= _T_4519 @[el2_lsu_bus_buffer.scala 583:32] + io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 584:30] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 586:61] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[el2_lsu_bus_buffer.scala 586:59] + io.lsu_nonblock_load_inv_r <= _T_4521 @[el2_lsu_bus_buffer.scala 586:30] + io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 587:34] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4523 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4527 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4531 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4535 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4541 = mux(_T_4534, _T_4537, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = or(_T_4538, _T_4539) @[Mux.scala 27:72] + node _T_4543 = or(_T_4542, _T_4540) @[Mux.scala 27:72] + node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4546 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4547 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4549 = and(_T_4546, _T_4548) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4551 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4552 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4554 = and(_T_4551, _T_4553) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4556 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4557 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4559 = and(_T_4556, _T_4558) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4561 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4562 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4564 = and(_T_4561, _T_4563) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4560, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = or(_T_4565, _T_4566) @[Mux.scala 27:72] + node _T_4570 = or(_T_4569, _T_4567) @[Mux.scala 27:72] + node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] + wire _T_4572 : UInt<1> @[Mux.scala 27:72] + _T_4572 <= _T_4571 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_error <= _T_4572 @[el2_lsu_bus_buffer.scala 589:35] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4574 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4576 = and(_T_4573, _T_4575) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4579 = or(_T_4577, _T_4578) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4580 = and(_T_4576, _T_4579) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4582 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4584 = and(_T_4581, _T_4583) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4587 = or(_T_4585, _T_4586) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4588 = and(_T_4584, _T_4587) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4590 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4592 = and(_T_4589, _T_4591) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4595 = or(_T_4593, _T_4594) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4596 = and(_T_4592, _T_4595) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4598 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4600 = and(_T_4597, _T_4599) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4603 = or(_T_4601, _T_4602) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4604 = and(_T_4600, _T_4603) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4608 = mux(_T_4604, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4609 = or(_T_4605, _T_4606) @[Mux.scala 27:72] + node _T_4610 = or(_T_4609, _T_4607) @[Mux.scala 27:72] + node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] + wire _T_4612 : UInt<2> @[Mux.scala 27:72] + _T_4612 <= _T_4611 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_tag <= _T_4612 @[el2_lsu_bus_buffer.scala 590:33] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4614 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4616 = and(_T_4613, _T_4615) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4619 = or(_T_4617, _T_4618) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4620 = and(_T_4616, _T_4619) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4622 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4624 = and(_T_4621, _T_4623) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4627 = or(_T_4625, _T_4626) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4628 = and(_T_4624, _T_4627) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4630 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4632 = and(_T_4629, _T_4631) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4635 = or(_T_4633, _T_4634) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4636 = and(_T_4632, _T_4635) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4638 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4640 = and(_T_4637, _T_4639) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4643 = or(_T_4641, _T_4642) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4644 = and(_T_4640, _T_4643) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4648 = mux(_T_4644, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4649 = or(_T_4645, _T_4646) @[Mux.scala 27:72] + node _T_4650 = or(_T_4649, _T_4647) @[Mux.scala 27:72] + node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4653 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4655 = and(_T_4652, _T_4654) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4657 = and(_T_4655, _T_4656) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4659 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4661 = and(_T_4658, _T_4660) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4663 = and(_T_4661, _T_4662) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4665 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4667 = and(_T_4664, _T_4666) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4669 = and(_T_4667, _T_4668) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4671 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4673 = and(_T_4670, _T_4672) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4675 = and(_T_4673, _T_4674) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = or(_T_4676, _T_4677) @[Mux.scala 27:72] + node _T_4681 = or(_T_4680, _T_4678) @[Mux.scala 27:72] + node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] + node _T_4683 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4684 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4685 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4686 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4690 = mux(_T_4686, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = or(_T_4687, _T_4688) @[Mux.scala 27:72] + node _T_4692 = or(_T_4691, _T_4689) @[Mux.scala 27:72] + node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] + wire _T_4694 : UInt<32> @[Mux.scala 27:72] + _T_4694 <= _T_4693 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[el2_lsu_bus_buffer.scala 593:83] + node _T_4695 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4696 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4697 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4698 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4698, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] + node _T_4706 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4708 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4710 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4712 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4717 = mux(_T_4712, _T_4713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4718 = or(_T_4714, _T_4715) @[Mux.scala 27:72] + node _T_4719 = or(_T_4718, _T_4716) @[Mux.scala 27:72] + node _T_4720 = or(_T_4719, _T_4717) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4720 @[Mux.scala 27:72] + node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] + node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] + node _T_4724 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4725 = bits(_T_4723, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4726 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4727 = bits(_T_4723, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4728 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4729 = bits(_T_4723, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4730 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4731 = bits(_T_4723, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4735 = mux(_T_4730, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4736 = or(_T_4732, _T_4733) @[Mux.scala 27:72] + node _T_4737 = or(_T_4736, _T_4734) @[Mux.scala 27:72] + node _T_4738 = or(_T_4737, _T_4735) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] + node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 597:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 597:92] + node _T_4741 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:69] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[el2_lsu_bus_buffer.scala 599:67] + io.lsu_nonblock_load_data_valid <= _T_4742 @[el2_lsu_bus_buffer.scala 599:35] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 600:81] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[el2_lsu_bus_buffer.scala 600:63] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 600:131] + node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 601:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[el2_lsu_bus_buffer.scala 601:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 601:95] + node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:45] + node _T_4753 = and(_T_4751, _T_4752) @[el2_lsu_bus_buffer.scala 602:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 602:93] + node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] + node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 602:123] + node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 603:45] + node _T_4761 = and(_T_4759, _T_4760) @[el2_lsu_bus_buffer.scala 603:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 603:93] + node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] + node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 603:124] + node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 604:21] + node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4761, _T_4766, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4767, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = or(_T_4768, _T_4769) @[Mux.scala 27:72] + node _T_4774 = or(_T_4773, _T_4770) @[Mux.scala 27:72] + node _T_4775 = or(_T_4774, _T_4771) @[Mux.scala 27:72] + node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] + wire _T_4777 : UInt<64> @[Mux.scala 27:72] + _T_4777 <= _T_4776 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4777 @[el2_lsu_bus_buffer.scala 600:29] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4780 = and(_T_4778, _T_4779) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4781 = and(_T_4780, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4784 = and(_T_4782, _T_4783) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4785 = and(_T_4784, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4789 = and(_T_4788, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4792 = and(_T_4790, _T_4791) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4793 = and(_T_4792, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4794 = or(_T_4781, _T_4785) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4795 = or(_T_4794, _T_4789) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4796 = or(_T_4795, _T_4793) @[el2_lsu_bus_buffer.scala 605:141] + bus_sideeffect_pend <= _T_4796 @[el2_lsu_bus_buffer.scala 605:23] + node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4799 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4800 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4801 = eq(_T_4799, _T_4800) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4802 = and(_T_4798, _T_4801) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4805 = and(obuf_merge, _T_4804) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4806 = or(_T_4803, _T_4805) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4808 = and(_T_4802, _T_4807) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4811 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4812 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4813 = eq(_T_4811, _T_4812) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4814 = and(_T_4810, _T_4813) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4817 = and(obuf_merge, _T_4816) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4818 = or(_T_4815, _T_4817) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4820 = and(_T_4814, _T_4819) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4823 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4824 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4825 = eq(_T_4823, _T_4824) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4826 = and(_T_4822, _T_4825) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4829 = and(obuf_merge, _T_4828) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4830 = or(_T_4827, _T_4829) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4832 = and(_T_4826, _T_4831) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4835 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4836 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4837 = eq(_T_4835, _T_4836) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4838 = and(_T_4834, _T_4837) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4841 = and(obuf_merge, _T_4840) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4842 = or(_T_4839, _T_4841) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4844 = and(_T_4838, _T_4843) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4845 = mux(_T_4797, _T_4808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4846 = mux(_T_4809, _T_4820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4847 = mux(_T_4821, _T_4832, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4848 = mux(_T_4833, _T_4844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = or(_T_4845, _T_4846) @[Mux.scala 27:72] + node _T_4850 = or(_T_4849, _T_4847) @[Mux.scala 27:72] + node _T_4851 = or(_T_4850, _T_4848) @[Mux.scala 27:72] + wire _T_4852 : UInt<1> @[Mux.scala 27:72] + _T_4852 <= _T_4851 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4852 @[el2_lsu_bus_buffer.scala 606:26] + node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 609:54] + node _T_4854 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:75] + node _T_4855 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:150] + node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[el2_lsu_bus_buffer.scala 609:39] + node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 609:23] + bus_cmd_ready <= _T_4857 @[el2_lsu_bus_buffer.scala 609:17] + node _T_4858 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:39] + bus_wcmd_sent <= _T_4858 @[el2_lsu_bus_buffer.scala 610:17] + node _T_4859 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 611:39] + bus_wdata_sent <= _T_4859 @[el2_lsu_bus_buffer.scala 611:18] + node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 612:35] + node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 612:70] + node _T_4862 = and(_T_4860, _T_4861) @[el2_lsu_bus_buffer.scala 612:52] + node _T_4863 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 612:111] + node _T_4864 = or(_T_4862, _T_4863) @[el2_lsu_bus_buffer.scala 612:89] + bus_cmd_sent <= _T_4864 @[el2_lsu_bus_buffer.scala 612:16] + node _T_4865 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 613:37] + bus_rsp_read <= _T_4865 @[el2_lsu_bus_buffer.scala 613:16] + node _T_4866 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 614:38] + bus_rsp_write <= _T_4866 @[el2_lsu_bus_buffer.scala 614:17] + bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 615:20] + bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 616:21] + node _T_4867 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:60] + node _T_4868 = and(bus_rsp_write, _T_4867) @[el2_lsu_bus_buffer.scala 617:40] + bus_rsp_write_error <= _T_4868 @[el2_lsu_bus_buffer.scala 617:23] + node _T_4869 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 618:58] + node _T_4870 = and(bus_rsp_read, _T_4869) @[el2_lsu_bus_buffer.scala 618:38] + bus_rsp_read_error <= _T_4870 @[el2_lsu_bus_buffer.scala 618:22] + bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 619:17] + node _T_4871 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 622:36] + node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:51] + node _T_4873 = and(_T_4871, _T_4872) @[el2_lsu_bus_buffer.scala 622:49] + node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:68] + node _T_4875 = and(_T_4873, _T_4874) @[el2_lsu_bus_buffer.scala 622:66] + io.lsu_axi_awvalid <= _T_4875 @[el2_lsu_bus_buffer.scala 622:22] + io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 623:19] + node _T_4876 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 624:69] + node _T_4877 = cat(_T_4876, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[el2_lsu_bus_buffer.scala 624:27] + io.lsu_axi_awaddr <= _T_4878 @[el2_lsu_bus_buffer.scala 624:21] + node _T_4879 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 625:27] + io.lsu_axi_awsize <= _T_4880 @[el2_lsu_bus_buffer.scala 625:21] + io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 626:21] + node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 627:28] + io.lsu_axi_awcache <= _T_4881 @[el2_lsu_bus_buffer.scala 627:22] + node _T_4882 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 628:35] + io.lsu_axi_awregion <= _T_4882 @[el2_lsu_bus_buffer.scala 628:23] + io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 629:20] + io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 630:22] + io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 631:20] + io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 632:21] + node _T_4883 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 634:35] + node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:50] + node _T_4885 = and(_T_4883, _T_4884) @[el2_lsu_bus_buffer.scala 634:48] + node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:68] + node _T_4887 = and(_T_4885, _T_4886) @[el2_lsu_bus_buffer.scala 634:66] + io.lsu_axi_wvalid <= _T_4887 @[el2_lsu_bus_buffer.scala 634:21] + node _T_4888 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4889 = mux(_T_4888, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4890 = and(obuf_byteen, _T_4889) @[el2_lsu_bus_buffer.scala 635:35] + io.lsu_axi_wstrb <= _T_4890 @[el2_lsu_bus_buffer.scala 635:20] + io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 636:20] + io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 637:20] + node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:38] + node _T_4892 = and(obuf_valid, _T_4891) @[el2_lsu_bus_buffer.scala 639:36] + node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:52] + node _T_4894 = and(_T_4892, _T_4893) @[el2_lsu_bus_buffer.scala 639:50] + node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:67] + node _T_4896 = and(_T_4894, _T_4895) @[el2_lsu_bus_buffer.scala 639:65] + io.lsu_axi_arvalid <= _T_4896 @[el2_lsu_bus_buffer.scala 639:22] + io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 640:19] + node _T_4897 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 641:69] + node _T_4898 = cat(_T_4897, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[el2_lsu_bus_buffer.scala 641:27] + io.lsu_axi_araddr <= _T_4899 @[el2_lsu_bus_buffer.scala 641:21] + node _T_4900 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:27] + io.lsu_axi_arsize <= _T_4901 @[el2_lsu_bus_buffer.scala 642:21] + io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 643:21] + node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 644:28] + io.lsu_axi_arcache <= _T_4902 @[el2_lsu_bus_buffer.scala 644:22] + node _T_4903 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 645:35] + io.lsu_axi_arregion <= _T_4903 @[el2_lsu_bus_buffer.scala 645:23] + io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 646:20] + io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 647:22] + io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 648:20] + io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 649:21] + io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 650:21] + io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 651:21] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4905 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4907 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4908 = and(_T_4906, _T_4907) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4910 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4912 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4913 = and(_T_4911, _T_4912) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4915 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4917 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4918 = and(_T_4916, _T_4917) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4920 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4922 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4923 = and(_T_4921, _T_4922) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4924 = mux(_T_4904, _T_4908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4909, _T_4913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4914, _T_4918, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4919, _T_4923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire _T_4931 : UInt<1> @[Mux.scala 27:72] + _T_4931 <= _T_4930 @[Mux.scala 27:72] + io.lsu_imprecise_error_store_any <= _T_4931 @[el2_lsu_bus_buffer.scala 652:36] + node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4933 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4934 = and(_T_4932, _T_4933) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4935 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4936 = and(_T_4934, _T_4935) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4938 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4939 = and(_T_4937, _T_4938) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4940 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4941 = and(_T_4939, _T_4940) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4943 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4944 = and(_T_4942, _T_4943) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4945 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4946 = and(_T_4944, _T_4945) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4948 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4949 = and(_T_4947, _T_4948) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4950 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4951 = and(_T_4949, _T_4950) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4952 = mux(_T_4936, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4953 = mux(_T_4941, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4954 = mux(_T_4946, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4955 = mux(_T_4951, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4956 = or(_T_4952, _T_4953) @[Mux.scala 27:72] + node _T_4957 = or(_T_4956, _T_4954) @[Mux.scala 27:72] + node _T_4958 = or(_T_4957, _T_4955) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4958 @[Mux.scala 27:72] + node _T_4959 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 655:72] + node _T_4960 = and(io.lsu_nonblock_load_data_error, _T_4959) @[el2_lsu_bus_buffer.scala 655:70] + io.lsu_imprecise_error_load_any <= _T_4960 @[el2_lsu_bus_buffer.scala 655:35] + node _T_4961 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 656:41] + io.lsu_imprecise_error_addr_any <= _T_4961 @[el2_lsu_bus_buffer.scala 656:35] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 657:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 659:23] + node _T_4962 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 662:46] + node _T_4963 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 662:89] + node _T_4964 = or(_T_4962, _T_4963) @[el2_lsu_bus_buffer.scala 662:68] + node _T_4965 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 662:132] + node _T_4966 = or(_T_4964, _T_4965) @[el2_lsu_bus_buffer.scala 662:110] + io.lsu_pmu_bus_trxn <= _T_4966 @[el2_lsu_bus_buffer.scala 662:23] + node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 663:48] + node _T_4968 = and(_T_4967, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 663:65] + io.lsu_pmu_bus_misaligned <= _T_4968 @[el2_lsu_bus_buffer.scala 663:29] + node _T_4969 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 664:59] + io.lsu_pmu_bus_error <= _T_4969 @[el2_lsu_bus_buffer.scala 664:24] + node _T_4970 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:48] + node _T_4971 = and(io.lsu_axi_awvalid, _T_4970) @[el2_lsu_bus_buffer.scala 666:46] + node _T_4972 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:92] + node _T_4973 = and(io.lsu_axi_wvalid, _T_4972) @[el2_lsu_bus_buffer.scala 666:90] + node _T_4974 = or(_T_4971, _T_4973) @[el2_lsu_bus_buffer.scala 666:69] + node _T_4975 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:136] + node _T_4976 = and(io.lsu_axi_arvalid, _T_4975) @[el2_lsu_bus_buffer.scala 666:134] + node _T_4977 = or(_T_4974, _T_4976) @[el2_lsu_bus_buffer.scala 666:112] + io.lsu_pmu_bus_busy <= _T_4977 @[el2_lsu_bus_buffer.scala 666:23] + reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 668:49] + _T_4978 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 668:49] + WrPtr0_r <= _T_4978 @[el2_lsu_bus_buffer.scala 668:12] + reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 669:49] + _T_4979 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 669:49] + WrPtr1_r <= _T_4979 @[el2_lsu_bus_buffer.scala 669:12] + node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:75] + node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[el2_lsu_bus_buffer.scala 670:73] + node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:89] + node _T_4983 = and(_T_4981, _T_4982) @[el2_lsu_bus_buffer.scala 670:87] + reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 670:56] + _T_4984 <= _T_4983 @[el2_lsu_bus_buffer.scala 670:56] + io.lsu_busreq_r <= _T_4984 @[el2_lsu_bus_buffer.scala 670:19] + reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 671:66] + _T_4985 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 671:66] + lsu_nonblock_load_valid_r <= _T_4985 @[el2_lsu_bus_buffer.scala 671:29] module el2_lsu_bus_intf : input clock : Clock - input reset : Reset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_m : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<32>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>} + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>} - io.lsu_busreq_r <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 124:32] - io.lsu_bus_buffer_pend_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 125:32] - io.lsu_bus_buffer_full_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 126:32] - io.lsu_bus_buffer_empty_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 127:32] - io.lsu_bus_idle_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 128:32] - io.bus_read_data_m <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 129:32] - io.lsu_imprecise_error_load_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 131:36] - io.lsu_imprecise_error_store_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 132:36] - io.lsu_imprecise_error_addr_any <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 133:36] - io.lsu_nonblock_load_valid_m <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 135:36] - io.lsu_nonblock_load_tag_m <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 136:36] - io.lsu_nonblock_load_inv_r <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 137:36] - io.lsu_nonblock_load_inv_tag_r <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 138:36] - io.lsu_nonblock_load_data_valid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 139:36] - io.lsu_nonblock_load_data_error <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 140:36] - io.lsu_nonblock_load_data_tag <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 141:36] - io.lsu_nonblock_load_data <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 142:36] - io.lsu_pmu_bus_trxn <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 144:36] - io.lsu_pmu_bus_misaligned <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 145:36] - io.lsu_pmu_bus_error <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 146:36] - io.lsu_pmu_bus_busy <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 147:36] - io.lsu_axi_awvalid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 149:26] - io.lsu_axi_awid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 150:26] - io.lsu_axi_awaddr <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 151:26] - io.lsu_axi_awregion <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 152:26] - io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 153:26] - io.lsu_axi_awsize <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 154:26] - io.lsu_axi_awburst <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 155:26] - io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 156:26] - io.lsu_axi_awcache <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 157:26] - io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 158:26] - io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 159:26] - io.lsu_axi_wvalid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 161:26] - io.lsu_axi_wdata <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 162:26] - io.lsu_axi_wstrb <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 163:26] - io.lsu_axi_wlast <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 164:26] - io.lsu_axi_bready <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 166:26] - io.lsu_axi_arvalid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 168:26] - io.lsu_axi_arid <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 169:26] - io.lsu_axi_araddr <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 170:26] - io.lsu_axi_arregion <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 171:26] - io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 172:26] - io.lsu_axi_arsize <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 173:26] - io.lsu_axi_arburst <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 174:26] - io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 175:26] - io.lsu_axi_arcache <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 176:26] - io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 177:26] - io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 178:26] - io.lsu_axi_rready <= UInt<1>("h00") @[el2_lsu_bus_intf.scala 180:26] + wire lsu_bus_clk_en_q : UInt<1> + lsu_bus_clk_en_q <= UInt<1>("h00") + wire ldst_dual_d : UInt<1> + ldst_dual_d <= UInt<1>("h00") + wire ldst_dual_m : UInt<1> + ldst_dual_m <= UInt<1>("h00") + wire ldst_dual_r : UInt<1> + ldst_dual_r <= UInt<1>("h00") + wire ldst_byteen_m : UInt<4> + ldst_byteen_m <= UInt<1>("h00") + wire ldst_byteen_r : UInt<4> + ldst_byteen_r <= UInt<1>("h00") + wire ldst_byteen_ext_m : UInt<8> + ldst_byteen_ext_m <= UInt<1>("h00") + wire ldst_byteen_ext_r : UInt<8> + ldst_byteen_ext_r <= UInt<1>("h00") + wire ldst_byteen_hi_m : UInt<4> + ldst_byteen_hi_m <= UInt<1>("h00") + wire ldst_byteen_hi_r : UInt<4> + ldst_byteen_hi_r <= UInt<1>("h00") + wire ldst_byteen_lo_m : UInt<4> + ldst_byteen_lo_m <= UInt<1>("h00") + wire ldst_byteen_lo_r : UInt<4> + ldst_byteen_lo_r <= UInt<1>("h00") + wire is_sideeffects_r : UInt<1> + is_sideeffects_r <= UInt<1>("h00") + wire store_data_ext_r : UInt<64> + store_data_ext_r <= UInt<1>("h00") + wire store_data_hi_r : UInt<32> + store_data_hi_r <= UInt<1>("h00") + wire store_data_lo_r : UInt<32> + store_data_lo_r <= UInt<1>("h00") + wire addr_match_dw_lo_r_m : UInt<1> + addr_match_dw_lo_r_m <= UInt<1>("h00") + wire addr_match_word_lo_r_m : UInt<1> + addr_match_word_lo_r_m <= UInt<1>("h00") + wire no_word_merge_r : UInt<1> + no_word_merge_r <= UInt<1>("h00") + wire no_dword_merge_r : UInt<1> + no_dword_merge_r <= UInt<1>("h00") + wire ld_addr_rhit_lo_lo : UInt<1> + ld_addr_rhit_lo_lo <= UInt<1>("h00") + wire ld_addr_rhit_hi_lo : UInt<1> + ld_addr_rhit_hi_lo <= UInt<1>("h00") + wire ld_addr_rhit_lo_hi : UInt<1> + ld_addr_rhit_lo_hi <= UInt<1>("h00") + wire ld_addr_rhit_hi_hi : UInt<1> + ld_addr_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_rhit_lo_lo : UInt<4> + ld_byte_rhit_lo_lo <= UInt<1>("h00") + wire ld_byte_rhit_hi_lo : UInt<4> + ld_byte_rhit_hi_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo_hi : UInt<4> + ld_byte_rhit_lo_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi_hi : UInt<4> + ld_byte_rhit_hi_hi <= UInt<1>("h00") + wire ld_byte_hit_lo : UInt<4> + ld_byte_hit_lo <= UInt<1>("h00") + wire ld_byte_rhit_lo : UInt<4> + ld_byte_rhit_lo <= UInt<1>("h00") + wire ld_byte_hit_hi : UInt<4> + ld_byte_hit_hi <= UInt<1>("h00") + wire ld_byte_rhit_hi : UInt<4> + ld_byte_rhit_hi <= UInt<1>("h00") + wire ld_fwddata_rpipe_lo : UInt<32> + ld_fwddata_rpipe_lo <= UInt<1>("h00") + wire ld_fwddata_rpipe_hi : UInt<32> + ld_fwddata_rpipe_hi <= UInt<1>("h00") + wire ld_byte_hit_buf_lo : UInt<4> + ld_byte_hit_buf_lo <= UInt<1>("h00") + wire ld_byte_hit_buf_hi : UInt<4> + ld_byte_hit_buf_hi <= UInt<1>("h00") + wire ld_fwddata_buf_lo : UInt<32> + ld_fwddata_buf_lo <= UInt<1>("h00") + wire ld_fwddata_buf_hi : UInt<32> + ld_fwddata_buf_hi <= UInt<1>("h00") + wire ld_fwddata_lo : UInt<64> + ld_fwddata_lo <= UInt<1>("h00") + wire ld_fwddata_hi : UInt<64> + ld_fwddata_hi <= UInt<1>("h00") + wire ld_fwddata_m : UInt<64> + ld_fwddata_m <= UInt<1>("h00") + wire ld_full_hit_hi_m : UInt<1> + ld_full_hit_hi_m <= UInt<1>("h01") + wire ld_full_hit_lo_m : UInt<1> + ld_full_hit_lo_m <= UInt<1>("h01") + wire ld_full_hit_m : UInt<1> + ld_full_hit_m <= UInt<1>("h00") + inst bus_buffer of el2_lsu_bus_buffer @[el2_lsu_bus_intf.scala 167:39] + bus_buffer.clock <= clock + bus_buffer.reset <= reset + bus_buffer.io.scan_mode <= io.scan_mode @[el2_lsu_bus_intf.scala 169:29] + bus_buffer.io.dec_tlu_external_ldfwd_disable <= io.dec_tlu_external_ldfwd_disable @[el2_lsu_bus_intf.scala 171:51] + bus_buffer.io.dec_tlu_wb_coalescing_disable <= io.dec_tlu_wb_coalescing_disable @[el2_lsu_bus_intf.scala 172:51] + bus_buffer.io.dec_tlu_sideeffect_posted_disable <= io.dec_tlu_sideeffect_posted_disable @[el2_lsu_bus_intf.scala 173:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[el2_lsu_bus_intf.scala 174:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[el2_lsu_bus_intf.scala 175:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[el2_lsu_bus_intf.scala 176:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[el2_lsu_bus_intf.scala 177:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[el2_lsu_bus_intf.scala 178:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[el2_lsu_bus_intf.scala 179:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[el2_lsu_bus_intf.scala 180:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu_bus_intf.scala 181:51] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.dma <= io.lsu_pkt_m.dma @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store <= io.lsu_pkt_m.store @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.load <= io.lsu_pkt_m.load @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.dword <= io.lsu_pkt_m.dword @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.word <= io.lsu_pkt_m.word @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.half <= io.lsu_pkt_m.half @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.by <= io.lsu_pkt_m.by @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store_data_bypass_m <= io.lsu_pkt_r.store_data_bypass_m @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.load_ldst_bypass_d <= io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store_data_bypass_d <= io.lsu_pkt_r.store_data_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.dma <= io.lsu_pkt_r.dma @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.unsign <= io.lsu_pkt_r.unsign @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store <= io.lsu_pkt_r.store @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.load <= io.lsu_pkt_r.load @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.dword <= io.lsu_pkt_r.dword @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.word <= io.lsu_pkt_r.word @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.half <= io.lsu_pkt_r.half @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.by <= io.lsu_pkt_r.by @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.fast_int <= io.lsu_pkt_r.fast_int @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[el2_lsu_bus_intf.scala 188:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[el2_lsu_bus_intf.scala 189:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[el2_lsu_bus_intf.scala 190:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[el2_lsu_bus_intf.scala 191:51] + bus_buffer.io.store_data_r <= io.store_data_r @[el2_lsu_bus_intf.scala 192:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[el2_lsu_bus_intf.scala 194:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[el2_lsu_bus_intf.scala 195:51] + bus_buffer.io.flush_r <= io.flush_r @[el2_lsu_bus_intf.scala 196:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[el2_lsu_bus_intf.scala 197:51] + bus_buffer.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_lsu_bus_intf.scala 198:51] + bus_buffer.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_lsu_bus_intf.scala 199:51] + bus_buffer.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_lsu_bus_intf.scala 200:51] + bus_buffer.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_lsu_bus_intf.scala 201:51] + bus_buffer.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_lsu_bus_intf.scala 202:51] + bus_buffer.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_lsu_bus_intf.scala 203:51] + bus_buffer.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_lsu_bus_intf.scala 204:51] + bus_buffer.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_lsu_bus_intf.scala 205:51] + bus_buffer.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_intf.scala 206:51] + bus_buffer.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_lsu_bus_intf.scala 207:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 208:51] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[el2_lsu_bus_intf.scala 210:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[el2_lsu_bus_intf.scala 211:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[el2_lsu_bus_intf.scala 212:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[el2_lsu_bus_intf.scala 213:38] + io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[el2_lsu_bus_intf.scala 214:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[el2_lsu_bus_intf.scala 215:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[el2_lsu_bus_intf.scala 216:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[el2_lsu_bus_intf.scala 217:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[el2_lsu_bus_intf.scala 218:38] + io.lsu_imprecise_error_load_any <= bus_buffer.io.lsu_imprecise_error_load_any @[el2_lsu_bus_intf.scala 219:38] + io.lsu_imprecise_error_store_any <= bus_buffer.io.lsu_imprecise_error_store_any @[el2_lsu_bus_intf.scala 220:38] + io.lsu_imprecise_error_addr_any <= bus_buffer.io.lsu_imprecise_error_addr_any @[el2_lsu_bus_intf.scala 221:38] + io.lsu_nonblock_load_valid_m <= bus_buffer.io.lsu_nonblock_load_valid_m @[el2_lsu_bus_intf.scala 222:38] + io.lsu_nonblock_load_tag_m <= bus_buffer.io.lsu_nonblock_load_tag_m @[el2_lsu_bus_intf.scala 223:38] + io.lsu_nonblock_load_inv_r <= bus_buffer.io.lsu_nonblock_load_inv_r @[el2_lsu_bus_intf.scala 224:38] + io.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.lsu_nonblock_load_inv_tag_r @[el2_lsu_bus_intf.scala 225:38] + io.lsu_nonblock_load_data_valid <= bus_buffer.io.lsu_nonblock_load_data_valid @[el2_lsu_bus_intf.scala 226:38] + io.lsu_nonblock_load_data_error <= bus_buffer.io.lsu_nonblock_load_data_error @[el2_lsu_bus_intf.scala 227:38] + io.lsu_nonblock_load_data_tag <= bus_buffer.io.lsu_nonblock_load_data_tag @[el2_lsu_bus_intf.scala 228:38] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[el2_lsu_bus_intf.scala 229:38] + io.lsu_pmu_bus_trxn <= bus_buffer.io.lsu_pmu_bus_trxn @[el2_lsu_bus_intf.scala 230:38] + io.lsu_pmu_bus_misaligned <= bus_buffer.io.lsu_pmu_bus_misaligned @[el2_lsu_bus_intf.scala 231:38] + io.lsu_pmu_bus_error <= bus_buffer.io.lsu_pmu_bus_error @[el2_lsu_bus_intf.scala 232:38] + io.lsu_pmu_bus_busy <= bus_buffer.io.lsu_pmu_bus_busy @[el2_lsu_bus_intf.scala 233:38] + io.lsu_axi_awvalid <= bus_buffer.io.lsu_axi_awvalid @[el2_lsu_bus_intf.scala 234:38] + io.lsu_axi_awid <= bus_buffer.io.lsu_axi_awid @[el2_lsu_bus_intf.scala 235:38] + io.lsu_axi_awaddr <= bus_buffer.io.lsu_axi_awaddr @[el2_lsu_bus_intf.scala 236:38] + io.lsu_axi_awregion <= bus_buffer.io.lsu_axi_awregion @[el2_lsu_bus_intf.scala 237:38] + io.lsu_axi_awlen <= bus_buffer.io.lsu_axi_awlen @[el2_lsu_bus_intf.scala 238:38] + io.lsu_axi_awsize <= bus_buffer.io.lsu_axi_awsize @[el2_lsu_bus_intf.scala 239:38] + io.lsu_axi_awburst <= bus_buffer.io.lsu_axi_awburst @[el2_lsu_bus_intf.scala 240:38] + io.lsu_axi_awlock <= bus_buffer.io.lsu_axi_awlock @[el2_lsu_bus_intf.scala 241:38] + io.lsu_axi_awcache <= bus_buffer.io.lsu_axi_awcache @[el2_lsu_bus_intf.scala 242:38] + io.lsu_axi_awprot <= bus_buffer.io.lsu_axi_awprot @[el2_lsu_bus_intf.scala 243:38] + io.lsu_axi_awqos <= bus_buffer.io.lsu_axi_awqos @[el2_lsu_bus_intf.scala 244:38] + io.lsu_axi_wvalid <= bus_buffer.io.lsu_axi_wvalid @[el2_lsu_bus_intf.scala 245:38] + io.lsu_axi_wdata <= bus_buffer.io.lsu_axi_wdata @[el2_lsu_bus_intf.scala 246:38] + io.lsu_axi_wstrb <= bus_buffer.io.lsu_axi_wstrb @[el2_lsu_bus_intf.scala 247:38] + io.lsu_axi_wlast <= bus_buffer.io.lsu_axi_wlast @[el2_lsu_bus_intf.scala 248:38] + io.lsu_axi_bready <= bus_buffer.io.lsu_axi_bready @[el2_lsu_bus_intf.scala 249:38] + io.lsu_axi_arvalid <= bus_buffer.io.lsu_axi_arvalid @[el2_lsu_bus_intf.scala 250:38] + io.lsu_axi_arid <= bus_buffer.io.lsu_axi_arid @[el2_lsu_bus_intf.scala 251:38] + io.lsu_axi_araddr <= bus_buffer.io.lsu_axi_araddr @[el2_lsu_bus_intf.scala 252:38] + io.lsu_axi_arregion <= bus_buffer.io.lsu_axi_arregion @[el2_lsu_bus_intf.scala 253:38] + io.lsu_axi_arlen <= bus_buffer.io.lsu_axi_arlen @[el2_lsu_bus_intf.scala 254:38] + io.lsu_axi_arsize <= bus_buffer.io.lsu_axi_arsize @[el2_lsu_bus_intf.scala 255:38] + io.lsu_axi_arburst <= bus_buffer.io.lsu_axi_arburst @[el2_lsu_bus_intf.scala 256:38] + io.lsu_axi_arlock <= bus_buffer.io.lsu_axi_arlock @[el2_lsu_bus_intf.scala 257:38] + io.lsu_axi_arcache <= bus_buffer.io.lsu_axi_arcache @[el2_lsu_bus_intf.scala 258:38] + io.lsu_axi_arprot <= bus_buffer.io.lsu_axi_arprot @[el2_lsu_bus_intf.scala 259:38] + io.lsu_axi_arqos <= bus_buffer.io.lsu_axi_arqos @[el2_lsu_bus_intf.scala 260:38] + io.lsu_axi_rready <= bus_buffer.io.lsu_axi_rready @[el2_lsu_bus_intf.scala 261:38] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[el2_lsu_bus_intf.scala 263:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[el2_lsu_bus_intf.scala 264:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[el2_lsu_bus_intf.scala 265:51] + bus_buffer.io.ldst_dual_d <= ldst_dual_d @[el2_lsu_bus_intf.scala 266:51] + bus_buffer.io.ldst_dual_m <= ldst_dual_m @[el2_lsu_bus_intf.scala 267:51] + bus_buffer.io.ldst_dual_r <= ldst_dual_r @[el2_lsu_bus_intf.scala 268:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[el2_lsu_bus_intf.scala 269:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[el2_lsu_bus_intf.scala 270:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[el2_lsu_bus_intf.scala 271:51] + node _T = bits(io.lsu_pkt_m.word, 0, 0) @[el2_lsu_bus_intf.scala 276:58] + node _T_1 = bits(io.lsu_pkt_m.half, 0, 0) @[el2_lsu_bus_intf.scala 276:97] + node _T_2 = bits(io.lsu_pkt_m.by, 0, 0) @[el2_lsu_bus_intf.scala 276:133] + node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_6 = or(_T_3, _T_4) @[Mux.scala 27:72] + node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] + wire _T_8 : UInt<4> @[Mux.scala 27:72] + _T_8 <= _T_7 @[Mux.scala 27:72] + ldst_byteen_m <= _T_8 @[el2_lsu_bus_intf.scala 276:27] + node _T_9 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 277:43] + node _T_10 = bits(io.end_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 277:64] + node _T_11 = neq(_T_9, _T_10) @[el2_lsu_bus_intf.scala 277:47] + ldst_dual_d <= _T_11 @[el2_lsu_bus_intf.scala 277:27] + node _T_12 = bits(io.lsu_addr_r, 31, 3) @[el2_lsu_bus_intf.scala 278:44] + node _T_13 = bits(io.lsu_addr_m, 31, 3) @[el2_lsu_bus_intf.scala 278:68] + node _T_14 = eq(_T_12, _T_13) @[el2_lsu_bus_intf.scala 278:51] + addr_match_dw_lo_r_m <= _T_14 @[el2_lsu_bus_intf.scala 278:27] + node _T_15 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_intf.scala 279:68] + node _T_16 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_bus_intf.scala 279:85] + node _T_17 = xor(_T_15, _T_16) @[el2_lsu_bus_intf.scala 279:71] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 279:53] + node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[el2_lsu_bus_intf.scala 279:51] + addr_match_word_lo_r_m <= _T_19 @[el2_lsu_bus_intf.scala 279:27] + node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:48] + node _T_21 = and(io.lsu_busreq_r, _T_20) @[el2_lsu_bus_intf.scala 280:46] + node _T_22 = and(_T_21, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 280:61] + node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:102] + node _T_24 = or(io.lsu_pkt_m.load, _T_23) @[el2_lsu_bus_intf.scala 280:100] + node _T_25 = and(_T_22, _T_24) @[el2_lsu_bus_intf.scala 280:79] + no_word_merge_r <= _T_25 @[el2_lsu_bus_intf.scala 280:27] + node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:48] + node _T_27 = and(io.lsu_busreq_r, _T_26) @[el2_lsu_bus_intf.scala 281:46] + node _T_28 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 281:61] + node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:102] + node _T_30 = or(io.lsu_pkt_m.load, _T_29) @[el2_lsu_bus_intf.scala 281:100] + node _T_31 = and(_T_28, _T_30) @[el2_lsu_bus_intf.scala 281:79] + no_dword_merge_r <= _T_31 @[el2_lsu_bus_intf.scala 281:27] + node _T_32 = bits(ldst_byteen_m, 3, 0) @[el2_lsu_bus_intf.scala 283:43] + node _T_33 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 283:65] + node _T_34 = dshl(_T_32, _T_33) @[el2_lsu_bus_intf.scala 283:49] + ldst_byteen_ext_m <= _T_34 @[el2_lsu_bus_intf.scala 283:27] + node _T_35 = bits(ldst_byteen_r, 3, 0) @[el2_lsu_bus_intf.scala 284:43] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 284:65] + node _T_37 = dshl(_T_35, _T_36) @[el2_lsu_bus_intf.scala 284:49] + ldst_byteen_ext_r <= _T_37 @[el2_lsu_bus_intf.scala 284:27] + node _T_38 = bits(io.store_data_r, 31, 0) @[el2_lsu_bus_intf.scala 285:45] + node _T_39 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 285:72] + node _T_40 = cat(_T_39, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_41 = dshl(_T_38, _T_40) @[el2_lsu_bus_intf.scala 285:52] + store_data_ext_r <= _T_41 @[el2_lsu_bus_intf.scala 285:27] + node _T_42 = bits(ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_intf.scala 286:47] + ldst_byteen_hi_m <= _T_42 @[el2_lsu_bus_intf.scala 286:27] + node _T_43 = bits(ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_intf.scala 287:47] + ldst_byteen_lo_m <= _T_43 @[el2_lsu_bus_intf.scala 287:27] + node _T_44 = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_bus_intf.scala 288:47] + ldst_byteen_hi_r <= _T_44 @[el2_lsu_bus_intf.scala 288:27] + node _T_45 = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_bus_intf.scala 289:47] + ldst_byteen_lo_r <= _T_45 @[el2_lsu_bus_intf.scala 289:27] + node _T_46 = bits(store_data_ext_r, 63, 32) @[el2_lsu_bus_intf.scala 291:46] + store_data_hi_r <= _T_46 @[el2_lsu_bus_intf.scala 291:27] + node _T_47 = bits(store_data_ext_r, 31, 0) @[el2_lsu_bus_intf.scala 292:46] + store_data_lo_r <= _T_47 @[el2_lsu_bus_intf.scala 292:27] + node _T_48 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 293:44] + node _T_49 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 293:68] + node _T_50 = eq(_T_48, _T_49) @[el2_lsu_bus_intf.scala 293:51] + node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 293:76] + node _T_52 = and(_T_51, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 293:97] + node _T_53 = and(_T_52, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 293:118] + ld_addr_rhit_lo_lo <= _T_53 @[el2_lsu_bus_intf.scala 293:27] + node _T_54 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 294:44] + node _T_55 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 294:68] + node _T_56 = eq(_T_54, _T_55) @[el2_lsu_bus_intf.scala 294:51] + node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 294:76] + node _T_58 = and(_T_57, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 294:97] + node _T_59 = and(_T_58, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 294:118] + ld_addr_rhit_lo_hi <= _T_59 @[el2_lsu_bus_intf.scala 294:27] + node _T_60 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 295:44] + node _T_61 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 295:68] + node _T_62 = eq(_T_60, _T_61) @[el2_lsu_bus_intf.scala 295:51] + node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 295:76] + node _T_64 = and(_T_63, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 295:97] + node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 295:118] + ld_addr_rhit_hi_lo <= _T_65 @[el2_lsu_bus_intf.scala 295:27] + node _T_66 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 296:44] + node _T_67 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 296:68] + node _T_68 = eq(_T_66, _T_67) @[el2_lsu_bus_intf.scala 296:51] + node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 296:76] + node _T_70 = and(_T_69, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 296:97] + node _T_71 = and(_T_70, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 296:118] + ld_addr_rhit_hi_hi <= _T_71 @[el2_lsu_bus_intf.scala 296:27] + node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 298:88] + node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[el2_lsu_bus_intf.scala 298:70] + node _T_74 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 298:110] + node _T_75 = and(_T_73, _T_74) @[el2_lsu_bus_intf.scala 298:92] + node _T_76 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 298:88] + node _T_77 = and(ld_addr_rhit_lo_lo, _T_76) @[el2_lsu_bus_intf.scala 298:70] + node _T_78 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 298:110] + node _T_79 = and(_T_77, _T_78) @[el2_lsu_bus_intf.scala 298:92] + node _T_80 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 298:88] + node _T_81 = and(ld_addr_rhit_lo_lo, _T_80) @[el2_lsu_bus_intf.scala 298:70] + node _T_82 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 298:110] + node _T_83 = and(_T_81, _T_82) @[el2_lsu_bus_intf.scala 298:92] + node _T_84 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 298:88] + node _T_85 = and(ld_addr_rhit_lo_lo, _T_84) @[el2_lsu_bus_intf.scala 298:70] + node _T_86 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 298:110] + node _T_87 = and(_T_85, _T_86) @[el2_lsu_bus_intf.scala 298:92] + node _T_88 = cat(_T_87, _T_83) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_79) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_75) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_90 @[el2_lsu_bus_intf.scala 298:27] + node _T_91 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 299:88] + node _T_92 = and(ld_addr_rhit_lo_hi, _T_91) @[el2_lsu_bus_intf.scala 299:70] + node _T_93 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 299:110] + node _T_94 = and(_T_92, _T_93) @[el2_lsu_bus_intf.scala 299:92] + node _T_95 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 299:88] + node _T_96 = and(ld_addr_rhit_lo_hi, _T_95) @[el2_lsu_bus_intf.scala 299:70] + node _T_97 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 299:110] + node _T_98 = and(_T_96, _T_97) @[el2_lsu_bus_intf.scala 299:92] + node _T_99 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 299:88] + node _T_100 = and(ld_addr_rhit_lo_hi, _T_99) @[el2_lsu_bus_intf.scala 299:70] + node _T_101 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 299:110] + node _T_102 = and(_T_100, _T_101) @[el2_lsu_bus_intf.scala 299:92] + node _T_103 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 299:88] + node _T_104 = and(ld_addr_rhit_lo_hi, _T_103) @[el2_lsu_bus_intf.scala 299:70] + node _T_105 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 299:110] + node _T_106 = and(_T_104, _T_105) @[el2_lsu_bus_intf.scala 299:92] + node _T_107 = cat(_T_106, _T_102) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_98) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_94) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_109 @[el2_lsu_bus_intf.scala 299:27] + node _T_110 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 300:88] + node _T_111 = and(ld_addr_rhit_hi_lo, _T_110) @[el2_lsu_bus_intf.scala 300:70] + node _T_112 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 300:110] + node _T_113 = and(_T_111, _T_112) @[el2_lsu_bus_intf.scala 300:92] + node _T_114 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 300:88] + node _T_115 = and(ld_addr_rhit_hi_lo, _T_114) @[el2_lsu_bus_intf.scala 300:70] + node _T_116 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 300:110] + node _T_117 = and(_T_115, _T_116) @[el2_lsu_bus_intf.scala 300:92] + node _T_118 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 300:88] + node _T_119 = and(ld_addr_rhit_hi_lo, _T_118) @[el2_lsu_bus_intf.scala 300:70] + node _T_120 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 300:110] + node _T_121 = and(_T_119, _T_120) @[el2_lsu_bus_intf.scala 300:92] + node _T_122 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 300:88] + node _T_123 = and(ld_addr_rhit_hi_lo, _T_122) @[el2_lsu_bus_intf.scala 300:70] + node _T_124 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 300:110] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_intf.scala 300:92] + node _T_126 = cat(_T_125, _T_121) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_117) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_128 @[el2_lsu_bus_intf.scala 300:27] + node _T_129 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 301:88] + node _T_130 = and(ld_addr_rhit_hi_hi, _T_129) @[el2_lsu_bus_intf.scala 301:70] + node _T_131 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 301:110] + node _T_132 = and(_T_130, _T_131) @[el2_lsu_bus_intf.scala 301:92] + node _T_133 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 301:88] + node _T_134 = and(ld_addr_rhit_hi_hi, _T_133) @[el2_lsu_bus_intf.scala 301:70] + node _T_135 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 301:110] + node _T_136 = and(_T_134, _T_135) @[el2_lsu_bus_intf.scala 301:92] + node _T_137 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 301:88] + node _T_138 = and(ld_addr_rhit_hi_hi, _T_137) @[el2_lsu_bus_intf.scala 301:70] + node _T_139 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 301:110] + node _T_140 = and(_T_138, _T_139) @[el2_lsu_bus_intf.scala 301:92] + node _T_141 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 301:88] + node _T_142 = and(ld_addr_rhit_hi_hi, _T_141) @[el2_lsu_bus_intf.scala 301:70] + node _T_143 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 301:110] + node _T_144 = and(_T_142, _T_143) @[el2_lsu_bus_intf.scala 301:92] + node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_136) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_132) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_147 @[el2_lsu_bus_intf.scala 301:27] + node _T_148 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:69] + node _T_149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:93] + node _T_150 = or(_T_148, _T_149) @[el2_lsu_bus_intf.scala 303:73] + node _T_151 = bits(ld_byte_hit_buf_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:117] + node _T_152 = or(_T_150, _T_151) @[el2_lsu_bus_intf.scala 303:97] + node _T_153 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:69] + node _T_154 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:93] + node _T_155 = or(_T_153, _T_154) @[el2_lsu_bus_intf.scala 303:73] + node _T_156 = bits(ld_byte_hit_buf_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:117] + node _T_157 = or(_T_155, _T_156) @[el2_lsu_bus_intf.scala 303:97] + node _T_158 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:69] + node _T_159 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:93] + node _T_160 = or(_T_158, _T_159) @[el2_lsu_bus_intf.scala 303:73] + node _T_161 = bits(ld_byte_hit_buf_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:117] + node _T_162 = or(_T_160, _T_161) @[el2_lsu_bus_intf.scala 303:97] + node _T_163 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:69] + node _T_164 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:93] + node _T_165 = or(_T_163, _T_164) @[el2_lsu_bus_intf.scala 303:73] + node _T_166 = bits(ld_byte_hit_buf_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:117] + node _T_167 = or(_T_165, _T_166) @[el2_lsu_bus_intf.scala 303:97] + node _T_168 = cat(_T_167, _T_162) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_157) @[Cat.scala 29:58] + node _T_170 = cat(_T_169, _T_152) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_170 @[el2_lsu_bus_intf.scala 303:27] + node _T_171 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:69] + node _T_172 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:93] + node _T_173 = or(_T_171, _T_172) @[el2_lsu_bus_intf.scala 304:73] + node _T_174 = bits(ld_byte_hit_buf_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:117] + node _T_175 = or(_T_173, _T_174) @[el2_lsu_bus_intf.scala 304:97] + node _T_176 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:69] + node _T_177 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:93] + node _T_178 = or(_T_176, _T_177) @[el2_lsu_bus_intf.scala 304:73] + node _T_179 = bits(ld_byte_hit_buf_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:117] + node _T_180 = or(_T_178, _T_179) @[el2_lsu_bus_intf.scala 304:97] + node _T_181 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:69] + node _T_182 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:93] + node _T_183 = or(_T_181, _T_182) @[el2_lsu_bus_intf.scala 304:73] + node _T_184 = bits(ld_byte_hit_buf_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:117] + node _T_185 = or(_T_183, _T_184) @[el2_lsu_bus_intf.scala 304:97] + node _T_186 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:69] + node _T_187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:93] + node _T_188 = or(_T_186, _T_187) @[el2_lsu_bus_intf.scala 304:73] + node _T_189 = bits(ld_byte_hit_buf_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:117] + node _T_190 = or(_T_188, _T_189) @[el2_lsu_bus_intf.scala 304:97] + node _T_191 = cat(_T_190, _T_185) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_180) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_175) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_193 @[el2_lsu_bus_intf.scala 304:27] + node _T_194 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 305:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 305:93] + node _T_196 = or(_T_194, _T_195) @[el2_lsu_bus_intf.scala 305:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 305:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 305:93] + node _T_199 = or(_T_197, _T_198) @[el2_lsu_bus_intf.scala 305:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 305:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 305:93] + node _T_202 = or(_T_200, _T_201) @[el2_lsu_bus_intf.scala 305:73] + node _T_203 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 305:69] + node _T_204 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 305:93] + node _T_205 = or(_T_203, _T_204) @[el2_lsu_bus_intf.scala 305:73] + node _T_206 = cat(_T_205, _T_202) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_199) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_196) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_208 @[el2_lsu_bus_intf.scala 305:27] + node _T_209 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 306:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 306:93] + node _T_211 = or(_T_209, _T_210) @[el2_lsu_bus_intf.scala 306:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 306:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 306:93] + node _T_214 = or(_T_212, _T_213) @[el2_lsu_bus_intf.scala 306:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 306:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 306:93] + node _T_217 = or(_T_215, _T_216) @[el2_lsu_bus_intf.scala 306:73] + node _T_218 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 306:69] + node _T_219 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 306:93] + node _T_220 = or(_T_218, _T_219) @[el2_lsu_bus_intf.scala 306:73] + node _T_221 = cat(_T_220, _T_217) @[Cat.scala 29:58] + node _T_222 = cat(_T_221, _T_214) @[Cat.scala 29:58] + node _T_223 = cat(_T_222, _T_211) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_223 @[el2_lsu_bus_intf.scala 306:27] + node _T_224 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 307:79] + node _T_225 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 307:101] + node _T_226 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 307:136] + node _T_227 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 307:158] + node _T_228 = mux(_T_224, _T_225, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = mux(_T_226, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_230 = or(_T_228, _T_229) @[Mux.scala 27:72] + wire _T_231 : UInt<8> @[Mux.scala 27:72] + _T_231 <= _T_230 @[Mux.scala 27:72] + node _T_232 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 307:79] + node _T_233 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 307:101] + node _T_234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 307:136] + node _T_235 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 307:158] + node _T_236 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_234, _T_235, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = or(_T_236, _T_237) @[Mux.scala 27:72] + wire _T_239 : UInt<8> @[Mux.scala 27:72] + _T_239 <= _T_238 @[Mux.scala 27:72] + node _T_240 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 307:79] + node _T_241 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 307:101] + node _T_242 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 307:136] + node _T_243 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 307:158] + node _T_244 = mux(_T_240, _T_241, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_242, _T_243, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = or(_T_244, _T_245) @[Mux.scala 27:72] + wire _T_247 : UInt<8> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 307:79] + node _T_249 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 307:101] + node _T_250 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 307:136] + node _T_251 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 307:158] + node _T_252 = mux(_T_248, _T_249, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_253 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_254 = or(_T_252, _T_253) @[Mux.scala 27:72] + wire _T_255 : UInt<8> @[Mux.scala 27:72] + _T_255 <= _T_254 @[Mux.scala 27:72] + node _T_256 = cat(_T_255, _T_247) @[Cat.scala 29:58] + node _T_257 = cat(_T_256, _T_239) @[Cat.scala 29:58] + node _T_258 = cat(_T_257, _T_231) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_258 @[el2_lsu_bus_intf.scala 307:27] + node _T_259 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 308:79] + node _T_260 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 308:101] + node _T_261 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 308:136] + node _T_262 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 308:158] + node _T_263 = mux(_T_259, _T_260, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_261, _T_262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = or(_T_263, _T_264) @[Mux.scala 27:72] + wire _T_266 : UInt<8> @[Mux.scala 27:72] + _T_266 <= _T_265 @[Mux.scala 27:72] + node _T_267 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 308:79] + node _T_268 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 308:101] + node _T_269 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 308:136] + node _T_270 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 308:158] + node _T_271 = mux(_T_267, _T_268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_272 = mux(_T_269, _T_270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_273 = or(_T_271, _T_272) @[Mux.scala 27:72] + wire _T_274 : UInt<8> @[Mux.scala 27:72] + _T_274 <= _T_273 @[Mux.scala 27:72] + node _T_275 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 308:79] + node _T_276 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 308:101] + node _T_277 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 308:136] + node _T_278 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 308:158] + node _T_279 = mux(_T_275, _T_276, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_280 = mux(_T_277, _T_278, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_281 = or(_T_279, _T_280) @[Mux.scala 27:72] + wire _T_282 : UInt<8> @[Mux.scala 27:72] + _T_282 <= _T_281 @[Mux.scala 27:72] + node _T_283 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 308:79] + node _T_284 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 308:101] + node _T_285 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 308:136] + node _T_286 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 308:158] + node _T_287 = mux(_T_283, _T_284, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_288 = mux(_T_285, _T_286, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_289 = or(_T_287, _T_288) @[Mux.scala 27:72] + wire _T_290 : UInt<8> @[Mux.scala 27:72] + _T_290 <= _T_289 @[Mux.scala 27:72] + node _T_291 = cat(_T_290, _T_282) @[Cat.scala 29:58] + node _T_292 = cat(_T_291, _T_274) @[Cat.scala 29:58] + node _T_293 = cat(_T_292, _T_266) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_293 @[el2_lsu_bus_intf.scala 308:27] + node _T_294 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_bus_intf.scala 309:70] + node _T_295 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_bus_intf.scala 309:94] + node _T_296 = bits(ld_fwddata_buf_lo, 7, 0) @[el2_lsu_bus_intf.scala 309:128] + node _T_297 = mux(_T_294, _T_295, _T_296) @[el2_lsu_bus_intf.scala 309:54] + node _T_298 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_bus_intf.scala 309:70] + node _T_299 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_bus_intf.scala 309:94] + node _T_300 = bits(ld_fwddata_buf_lo, 15, 8) @[el2_lsu_bus_intf.scala 309:128] + node _T_301 = mux(_T_298, _T_299, _T_300) @[el2_lsu_bus_intf.scala 309:54] + node _T_302 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_bus_intf.scala 309:70] + node _T_303 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_bus_intf.scala 309:94] + node _T_304 = bits(ld_fwddata_buf_lo, 23, 16) @[el2_lsu_bus_intf.scala 309:128] + node _T_305 = mux(_T_302, _T_303, _T_304) @[el2_lsu_bus_intf.scala 309:54] + node _T_306 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_bus_intf.scala 309:70] + node _T_307 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_bus_intf.scala 309:94] + node _T_308 = bits(ld_fwddata_buf_lo, 31, 24) @[el2_lsu_bus_intf.scala 309:128] + node _T_309 = mux(_T_306, _T_307, _T_308) @[el2_lsu_bus_intf.scala 309:54] + node _T_310 = cat(_T_309, _T_305) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_301) @[Cat.scala 29:58] + node _T_312 = cat(_T_311, _T_297) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_312 @[el2_lsu_bus_intf.scala 309:27] + node _T_313 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_bus_intf.scala 310:70] + node _T_314 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_bus_intf.scala 310:94] + node _T_315 = bits(ld_fwddata_buf_hi, 7, 0) @[el2_lsu_bus_intf.scala 310:128] + node _T_316 = mux(_T_313, _T_314, _T_315) @[el2_lsu_bus_intf.scala 310:54] + node _T_317 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_bus_intf.scala 310:70] + node _T_318 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_bus_intf.scala 310:94] + node _T_319 = bits(ld_fwddata_buf_hi, 15, 8) @[el2_lsu_bus_intf.scala 310:128] + node _T_320 = mux(_T_317, _T_318, _T_319) @[el2_lsu_bus_intf.scala 310:54] + node _T_321 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_bus_intf.scala 310:70] + node _T_322 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_bus_intf.scala 310:94] + node _T_323 = bits(ld_fwddata_buf_hi, 23, 16) @[el2_lsu_bus_intf.scala 310:128] + node _T_324 = mux(_T_321, _T_322, _T_323) @[el2_lsu_bus_intf.scala 310:54] + node _T_325 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_bus_intf.scala 310:70] + node _T_326 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_bus_intf.scala 310:94] + node _T_327 = bits(ld_fwddata_buf_hi, 31, 24) @[el2_lsu_bus_intf.scala 310:128] + node _T_328 = mux(_T_325, _T_326, _T_327) @[el2_lsu_bus_intf.scala 310:54] + node _T_329 = cat(_T_328, _T_324) @[Cat.scala 29:58] + node _T_330 = cat(_T_329, _T_320) @[Cat.scala 29:58] + node _T_331 = cat(_T_330, _T_316) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_331 @[el2_lsu_bus_intf.scala 310:27] + node _T_332 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_bus_intf.scala 311:66] + node _T_333 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 311:89] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_335 = or(_T_332, _T_334) @[el2_lsu_bus_intf.scala 311:70] + node _T_336 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_bus_intf.scala 311:66] + node _T_337 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 311:89] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_339 = or(_T_336, _T_338) @[el2_lsu_bus_intf.scala 311:70] + node _T_340 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_bus_intf.scala 311:66] + node _T_341 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 311:89] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_343 = or(_T_340, _T_342) @[el2_lsu_bus_intf.scala 311:70] + node _T_344 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_bus_intf.scala 311:66] + node _T_345 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 311:89] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_347 = or(_T_344, _T_346) @[el2_lsu_bus_intf.scala 311:70] + node _T_348 = and(_T_335, _T_339) @[el2_lsu_bus_intf.scala 311:111] + node _T_349 = and(_T_348, _T_343) @[el2_lsu_bus_intf.scala 311:111] + node _T_350 = and(_T_349, _T_347) @[el2_lsu_bus_intf.scala 311:111] + ld_full_hit_lo_m <= _T_350 @[el2_lsu_bus_intf.scala 311:27] + node _T_351 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_bus_intf.scala 312:66] + node _T_352 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 312:89] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_354 = or(_T_351, _T_353) @[el2_lsu_bus_intf.scala 312:70] + node _T_355 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_bus_intf.scala 312:66] + node _T_356 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 312:89] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_358 = or(_T_355, _T_357) @[el2_lsu_bus_intf.scala 312:70] + node _T_359 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_bus_intf.scala 312:66] + node _T_360 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 312:89] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_362 = or(_T_359, _T_361) @[el2_lsu_bus_intf.scala 312:70] + node _T_363 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_bus_intf.scala 312:66] + node _T_364 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 312:89] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_366 = or(_T_363, _T_365) @[el2_lsu_bus_intf.scala 312:70] + node _T_367 = and(_T_354, _T_358) @[el2_lsu_bus_intf.scala 312:111] + node _T_368 = and(_T_367, _T_362) @[el2_lsu_bus_intf.scala 312:111] + node _T_369 = and(_T_368, _T_366) @[el2_lsu_bus_intf.scala 312:111] + ld_full_hit_hi_m <= _T_369 @[el2_lsu_bus_intf.scala 312:27] + node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[el2_lsu_bus_intf.scala 313:47] + node _T_371 = and(_T_370, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 313:66] + node _T_372 = and(_T_371, io.lsu_pkt_m.load) @[el2_lsu_bus_intf.scala 313:84] + node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 313:106] + node _T_374 = and(_T_372, _T_373) @[el2_lsu_bus_intf.scala 313:104] + ld_full_hit_m <= _T_374 @[el2_lsu_bus_intf.scala 313:27] + node _T_375 = bits(ld_fwddata_hi, 31, 0) @[el2_lsu_bus_intf.scala 314:47] + node _T_376 = bits(ld_fwddata_lo, 31, 0) @[el2_lsu_bus_intf.scala 314:68] + node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] + node _T_378 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 314:97] + node _T_379 = mul(UInt<4>("h08"), _T_378) @[el2_lsu_bus_intf.scala 314:83] + node _T_380 = dshr(_T_377, _T_379) @[el2_lsu_bus_intf.scala 314:76] + ld_fwddata_m <= _T_380 @[el2_lsu_bus_intf.scala 314:27] + node _T_381 = bits(ld_fwddata_m, 31, 0) @[el2_lsu_bus_intf.scala 315:42] + io.bus_read_data_m <= _T_381 @[el2_lsu_bus_intf.scala 315:27] + reg _T_382 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 318:32] + _T_382 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 318:32] + lsu_bus_clk_en_q <= _T_382 @[el2_lsu_bus_intf.scala 318:22] + reg _T_383 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 321:27] + _T_383 <= ldst_dual_d @[el2_lsu_bus_intf.scala 321:27] + ldst_dual_m <= _T_383 @[el2_lsu_bus_intf.scala 321:17] + reg _T_384 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 324:33] + _T_384 <= ldst_dual_m @[el2_lsu_bus_intf.scala 324:33] + ldst_dual_r <= _T_384 @[el2_lsu_bus_intf.scala 324:23] + reg _T_385 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 325:33] + _T_385 <= io.is_sideeffects_m @[el2_lsu_bus_intf.scala 325:33] + is_sideeffects_r <= _T_385 @[el2_lsu_bus_intf.scala 325:23] + reg _T_386 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[el2_lsu_bus_intf.scala 326:33] + _T_386 <= ldst_byteen_m @[el2_lsu_bus_intf.scala 326:33] + ldst_byteen_r <= _T_386 @[el2_lsu_bus_intf.scala 326:23] module el2_lsu : input clock : Clock input reset : AsyncReset - output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<32>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} + output io : {flip clk_override : UInt<1>, flip dec_tlu_flush_lower_r : UInt<1>, flip dec_tlu_i0_kill_writeb_r : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_core_ecc_disable : UInt<1>, flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, flip dec_lsu_offset_d : UInt<12>, flip lsu_p : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip trigger_pkt_any : {select : UInt<1>, match_ : UInt<1>, store : UInt<1>, load : UInt<1>, execute : UInt<1>, m : UInt<1>, tdata2 : UInt<32>}[4], flip dec_lsu_valid_raw_d : UInt<1>, flip dec_tlu_mrac_ff : UInt<32>, lsu_result_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_load_stall_any : UInt<1>, lsu_store_stall_any : UInt<1>, lsu_fastint_stall_any : UInt<1>, lsu_idle_any : UInt<1>, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {exc_valid : UInt<1>, single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<1>, addr : UInt<1>}, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_load_external_m : UInt<1>, lsu_pmu_store_external_m : UInt<1>, lsu_pmu_misaligned_m : UInt<1>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_trigger_match_m : UInt<4>, dccm_wren : UInt<1>, dccm_rden : UInt<1>, dccm_wr_addr_lo : UInt<16>, dccm_wr_addr_hi : UInt<16>, dccm_rd_addr_lo : UInt<16>, dccm_rd_addr_hi : UInt<16>, dccm_wr_data_lo : UInt<39>, dccm_wr_data_hi : UInt<39>, flip dccm_rd_data_lo : UInt<39>, flip dccm_rd_data_hi : UInt<39>, picm_wren : UInt<1>, picm_rden : UInt<1>, picm_mken : UInt<1>, picm_rdaddr : UInt<32>, picm_wraddr : UInt<32>, picm_wr_data : UInt<32>, flip picm_rd_data : UInt<32>, lsu_axi_awvalid : UInt<1>, lsu_axi_awlock : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, lsu_axi_arlock : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rlast : UInt<1>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rid : UInt<3>, flip lsu_bus_clk_en : UInt<1>, flip dma_dccm_req : UInt<1>, flip dma_mem_write : UInt<1>, dccm_dma_rvalid : UInt<1>, dccm_dma_ecc_error : UInt<1>, flip dma_mem_tag : UInt<3>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_wdata : UInt<64>, dccm_dma_rtag : UInt<3>, dccm_dma_rdata : UInt<64>, dccm_ready : UInt<1>, flip scan_mode : UInt<1>, flip free_clk : Clock} wire dma_dccm_wdata : UInt<64> dma_dccm_wdata <= UInt<64>("h00") @@ -6967,313 +15223,314 @@ circuit el2_lsu : dma_dccm_wdata_lo <= UInt<32>("h00") wire dma_dccm_wdata_hi : UInt<32> dma_dccm_wdata_hi <= UInt<32>("h00") - wire dma_mem_tag_m : UInt<32> - dma_mem_tag_m <= UInt<32>("h00") + wire dma_mem_tag_m : UInt<3> + dma_mem_tag_m <= UInt<3>("h00") wire lsu_raw_fwd_lo_r : UInt<1> lsu_raw_fwd_lo_r <= UInt<1>("h00") wire lsu_raw_fwd_hi_r : UInt<1> lsu_raw_fwd_hi_r <= UInt<1>("h00") - inst lsu_lsc_ctl of el2_lsu_lsc_ctl @[el2_lsu.scala 153:30] + inst lsu_lsc_ctl of el2_lsu_lsc_ctl @[el2_lsu.scala 154:30] lsu_lsc_ctl.clock <= clock lsu_lsc_ctl.reset <= reset - inst dccm_ctl of el2_lsu_dccm_ctl @[el2_lsu.scala 154:30] + io.lsu_result_m <= lsu_lsc_ctl.io.lsu_result_m @[el2_lsu.scala 155:19] + io.lsu_result_corr_r <= lsu_lsc_ctl.io.lsu_result_corr_r @[el2_lsu.scala 156:24] + inst dccm_ctl of el2_lsu_dccm_ctl @[el2_lsu.scala 157:30] dccm_ctl.clock <= clock dccm_ctl.reset <= reset - inst stbuf of el2_lsu_stbuf @[el2_lsu.scala 155:30] + inst stbuf of el2_lsu_stbuf @[el2_lsu.scala 158:30] stbuf.clock <= clock stbuf.reset <= reset - inst ecc of el2_lsu_ecc @[el2_lsu.scala 156:30] + inst ecc of el2_lsu_ecc @[el2_lsu.scala 159:30] ecc.clock <= clock ecc.reset <= reset - inst trigger of el2_lsu_trigger @[el2_lsu.scala 157:30] + inst trigger of el2_lsu_trigger @[el2_lsu.scala 160:30] trigger.clock <= clock trigger.reset <= reset - inst clkdomain of el2_lsu_clkdomain @[el2_lsu.scala 158:30] + inst clkdomain of el2_lsu_clkdomain @[el2_lsu.scala 161:30] clkdomain.clock <= clock clkdomain.reset <= reset - inst bus_intf of el2_lsu_bus_intf @[el2_lsu.scala 159:30] + inst bus_intf of el2_lsu_bus_intf @[el2_lsu.scala 162:30] bus_intf.clock <= clock bus_intf.reset <= reset - node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[el2_lsu.scala 161:56] - node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[el2_lsu.scala 162:56] - node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[el2_lsu.scala 165:57] - node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 165:95] - io.lsu_store_stall_any <= _T_1 @[el2_lsu.scala 165:26] - node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 166:64] - io.lsu_load_stall_any <= _T_2 @[el2_lsu.scala 166:25] - io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[el2_lsu.scala 167:28] - node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu.scala 172:58] - node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[el2_lsu.scala 172:56] - node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[el2_lsu.scala 172:121] - node _T_6 = and(_T_4, _T_5) @[el2_lsu.scala 172:88] - node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 172:153] - node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[el2_lsu.scala 173:45] - node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 173:63] - node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_lsu.scala 173:20] - io.dccm_ready <= _T_9 @[el2_lsu.scala 173:17] - node _T_10 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_lsu.scala 174:38] - node dma_dccm_wen = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[el2_lsu.scala 174:57] - node _T_11 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_lsu.scala 175:38] - node dma_pic_wen = and(_T_11, lsu_lsc_ctl.io.addr_in_pic_d) @[el2_lsu.scala 175:57] - node _T_12 = bits(io.dma_mem_addr, 2, 0) @[el2_lsu.scala 176:60] + node lsu_raw_fwd_lo_m = orr(stbuf.io.stbuf_fwdbyteen_lo_m) @[el2_lsu.scala 164:56] + node lsu_raw_fwd_hi_m = orr(stbuf.io.stbuf_fwdbyteen_hi_m) @[el2_lsu.scala 165:56] + node _T = or(stbuf.io.lsu_stbuf_full_any, bus_intf.io.lsu_bus_buffer_full_any) @[el2_lsu.scala 168:57] + node _T_1 = or(_T, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 168:95] + io.lsu_store_stall_any <= _T_1 @[el2_lsu.scala 168:26] + node _T_2 = or(bus_intf.io.lsu_bus_buffer_full_any, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 169:64] + io.lsu_load_stall_any <= _T_2 @[el2_lsu.scala 169:25] + io.lsu_fastint_stall_any <= dccm_ctl.io.ld_single_ecc_error_r @[el2_lsu.scala 170:28] + node _T_3 = eq(lsu_lsc_ctl.io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu.scala 175:58] + node _T_4 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_3) @[el2_lsu.scala 175:56] + node _T_5 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[el2_lsu.scala 175:121] + node _T_6 = and(_T_4, _T_5) @[el2_lsu.scala 175:88] + node ldst_nodma_mtor = and(_T_6, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 175:153] + node _T_7 = or(io.dec_lsu_valid_raw_d, ldst_nodma_mtor) @[el2_lsu.scala 176:45] + node _T_8 = or(_T_7, dccm_ctl.io.ld_single_ecc_error_r_ff) @[el2_lsu.scala 176:63] + node _T_9 = eq(_T_8, UInt<1>("h00")) @[el2_lsu.scala 176:20] + io.dccm_ready <= _T_9 @[el2_lsu.scala 176:17] + node _T_10 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_lsu.scala 177:38] + node dma_dccm_wen = and(_T_10, lsu_lsc_ctl.io.addr_in_dccm_d) @[el2_lsu.scala 177:57] + node _T_11 = and(io.dma_dccm_req, io.dma_mem_write) @[el2_lsu.scala 178:38] + node dma_pic_wen = and(_T_11, lsu_lsc_ctl.io.addr_in_pic_d) @[el2_lsu.scala 178:57] + node _T_12 = bits(io.dma_mem_addr, 2, 0) @[el2_lsu.scala 179:60] node _T_13 = cat(_T_12, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_14 = dshr(io.dma_mem_wdata, _T_13) @[el2_lsu.scala 176:38] - dma_dccm_wdata <= _T_14 @[el2_lsu.scala 176:18] - node _T_15 = bits(dma_dccm_wdata, 63, 32) @[el2_lsu.scala 177:38] - dma_dccm_wdata_hi <= _T_15 @[el2_lsu.scala 177:21] - node _T_16 = bits(dma_dccm_wdata, 31, 0) @[el2_lsu.scala 178:38] - dma_dccm_wdata_lo <= _T_16 @[el2_lsu.scala 178:21] - node _T_17 = eq(lsu_lsc_ctl.io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu.scala 187:58] - node _T_18 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_17) @[el2_lsu.scala 187:56] - node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu.scala 187:125] - node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_19) @[el2_lsu.scala 187:123] - node _T_21 = or(_T_18, _T_20) @[el2_lsu.scala 187:89] - node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu.scala 187:22] - node _T_23 = and(_T_22, bus_intf.io.lsu_bus_buffer_empty_any) @[el2_lsu.scala 187:157] - node _T_24 = and(_T_23, bus_intf.io.lsu_bus_idle_any) @[el2_lsu.scala 187:196] - io.lsu_idle_any <= _T_24 @[el2_lsu.scala 187:19] - node _T_25 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.store) @[el2_lsu.scala 189:61] - node _T_26 = and(_T_25, lsu_lsc_ctl.io.addr_in_dccm_r) @[el2_lsu.scala 189:94] - node _T_27 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_lsu.scala 189:128] - node _T_28 = and(_T_26, _T_27) @[el2_lsu.scala 189:126] - node _T_29 = eq(lsu_lsc_ctl.io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu.scala 189:139] - node store_stbuf_reqvld_r = and(_T_28, _T_29) @[el2_lsu.scala 189:137] - node _T_30 = or(lsu_lsc_ctl.io.lsu_pkt_m.load, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 191:85] - node _T_31 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_30) @[el2_lsu.scala 191:52] - node _T_32 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[el2_lsu.scala 191:152] - node lsu_cmpen_m = and(_T_31, _T_32) @[el2_lsu.scala 191:119] - node _T_33 = or(lsu_lsc_ctl.io.lsu_pkt_m.load, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 193:87] - node _T_34 = and(_T_33, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 193:121] - node _T_35 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_34) @[el2_lsu.scala 193:53] - node _T_36 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_lsu.scala 193:157] - node _T_37 = and(_T_35, _T_36) @[el2_lsu.scala 193:155] - node _T_38 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[el2_lsu.scala 193:171] - node _T_39 = and(_T_37, _T_38) @[el2_lsu.scala 193:169] - node _T_40 = eq(lsu_lsc_ctl.io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu.scala 193:199] - node lsu_busreq_m = and(_T_39, _T_40) @[el2_lsu.scala 193:197] - node _T_41 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[el2_lsu.scala 195:121] - node _T_42 = and(lsu_lsc_ctl.io.lsu_pkt_m.half, _T_41) @[el2_lsu.scala 195:94] - node _T_43 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[el2_lsu.scala 195:186] - node _T_44 = orr(_T_43) @[el2_lsu.scala 195:192] - node _T_45 = and(lsu_lsc_ctl.io.lsu_pkt_m.word, _T_44) @[el2_lsu.scala 195:159] - node _T_46 = or(_T_42, _T_45) @[el2_lsu.scala 195:126] - node _T_47 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_46) @[el2_lsu.scala 195:60] - io.lsu_pmu_misaligned_m <= _T_47 @[el2_lsu.scala 195:26] - node _T_48 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.load) @[el2_lsu.scala 196:64] - node _T_49 = and(_T_48, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 196:96] - io.lsu_pmu_load_external_m <= _T_49 @[el2_lsu.scala 196:30] - node _T_50 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 197:64] - node _T_51 = and(_T_50, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 197:97] - io.lsu_pmu_store_external_m <= _T_51 @[el2_lsu.scala 197:30] - lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 201:50] - lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 202:50] - lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 203:50] - lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 204:50] - lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[el2_lsu.scala 205:50] - lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[el2_lsu.scala 206:50] - lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[el2_lsu.scala 207:50] - lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[el2_lsu.scala 208:50] - lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[el2_lsu.scala 209:50] - lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[el2_lsu.scala 210:50] - lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[el2_lsu.scala 211:50] - lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[el2_lsu.scala 212:50] - lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[el2_lsu.scala 213:50] - lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[el2_lsu.scala 214:50] - lsu_lsc_ctl.io.exu_lsu_rs1_d <= io.exu_lsu_rs1_d @[el2_lsu.scala 215:50] - lsu_lsc_ctl.io.exu_lsu_rs2_d <= io.exu_lsu_rs2_d @[el2_lsu.scala 216:50] - lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.store_data_bypass_m <= io.lsu_p.store_data_bypass_m @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.load_ldst_bypass_d <= io.lsu_p.load_ldst_bypass_d @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.store_data_bypass_d <= io.lsu_p.store_data_bypass_d @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.dma <= io.lsu_p.dma @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.unsign <= io.lsu_p.unsign @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.store <= io.lsu_p.store @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.load <= io.lsu_p.load @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.dword <= io.lsu_p.dword @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.word <= io.lsu_p.word @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.half <= io.lsu_p.half @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.by <= io.lsu_p.by @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.lsu_p.fast_int <= io.lsu_p.fast_int @[el2_lsu.scala 217:50] - lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 218:50] - lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[el2_lsu.scala 219:50] - lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[el2_lsu.scala 220:50] - lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[el2_lsu.scala 221:50] - lsu_lsc_ctl.io.dma_dccm_req <= io.dma_dccm_req @[el2_lsu.scala 222:50] - lsu_lsc_ctl.io.dma_mem_addr <= io.dma_mem_addr @[el2_lsu.scala 223:50] - lsu_lsc_ctl.io.dma_mem_sz <= io.dma_mem_sz @[el2_lsu.scala 224:50] - lsu_lsc_ctl.io.dma_mem_write <= io.dma_mem_write @[el2_lsu.scala 225:50] - lsu_lsc_ctl.io.dma_mem_wdata <= io.dma_mem_wdata @[el2_lsu.scala 226:50] - lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu.scala 227:50] - lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[el2_lsu.scala 228:50] - io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[el2_lsu.scala 231:50] - io.lsu_error_pkt_r.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.addr @[el2_lsu.scala 232:50] - io.lsu_error_pkt_r.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.mscause @[el2_lsu.scala 232:50] - io.lsu_error_pkt_r.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.exc_type @[el2_lsu.scala 232:50] - io.lsu_error_pkt_r.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.inst_type @[el2_lsu.scala 232:50] - io.lsu_error_pkt_r.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.single_ecc_error @[el2_lsu.scala 232:50] - io.lsu_error_pkt_r.exc_valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.exc_valid @[el2_lsu.scala 232:50] - io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[el2_lsu.scala 233:50] - io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[el2_lsu.scala 234:50] - dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 239:50] - dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 240:50] - dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 241:50] - dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 242:50] - dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 243:50] - dccm_ctl.io.clk <= clock @[el2_lsu.scala 244:50] - dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.store_data_bypass_m @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.store_data_bypass_d @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.dma <= lsu_lsc_ctl.io.lsu_pkt_d.dma @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.unsign @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.store <= lsu_lsc_ctl.io.lsu_pkt_d.store @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.load <= lsu_lsc_ctl.io.lsu_pkt_d.load @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.dword <= lsu_lsc_ctl.io.lsu_pkt_d.dword @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.word <= lsu_lsc_ctl.io.lsu_pkt_d.word @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.half <= lsu_lsc_ctl.io.lsu_pkt_d.half @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.by <= lsu_lsc_ctl.io.lsu_pkt_d.by @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_d.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.fast_int @[el2_lsu.scala 245:50] - dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_d @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.dma <= lsu_lsc_ctl.io.lsu_pkt_m.dma @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.unsign @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.store <= lsu_lsc_ctl.io.lsu_pkt_m.store @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.load <= lsu_lsc_ctl.io.lsu_pkt_m.load @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.dword <= lsu_lsc_ctl.io.lsu_pkt_m.dword @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.word <= lsu_lsc_ctl.io.lsu_pkt_m.word @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.half <= lsu_lsc_ctl.io.lsu_pkt_m.half @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.by <= lsu_lsc_ctl.io.lsu_pkt_m.by @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_m.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.fast_int @[el2_lsu.scala 246:50] - dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_m @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_d @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.dma <= lsu_lsc_ctl.io.lsu_pkt_r.dma @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.unsign @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.store <= lsu_lsc_ctl.io.lsu_pkt_r.store @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.load <= lsu_lsc_ctl.io.lsu_pkt_r.load @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.dword <= lsu_lsc_ctl.io.lsu_pkt_r.dword @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.word <= lsu_lsc_ctl.io.lsu_pkt_r.word @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.half <= lsu_lsc_ctl.io.lsu_pkt_r.half @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 247:50] - dccm_ctl.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 247:50] - dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[el2_lsu.scala 248:50] - dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[el2_lsu.scala 249:50] - dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[el2_lsu.scala 250:50] - dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[el2_lsu.scala 251:50] - dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[el2_lsu.scala 252:50] - dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[el2_lsu.scala 253:50] - dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[el2_lsu.scala 254:50] - dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[el2_lsu.scala 255:50] - dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 256:50] - dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[el2_lsu.scala 257:50] - dccm_ctl.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[el2_lsu.scala 258:50] - dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[el2_lsu.scala 259:50] - dccm_ctl.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[el2_lsu.scala 260:50] - dccm_ctl.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[el2_lsu.scala 261:50] - dccm_ctl.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[el2_lsu.scala 262:50] - dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[el2_lsu.scala 263:50] - dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[el2_lsu.scala 264:50] - dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[el2_lsu.scala 265:50] - dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[el2_lsu.scala 266:50] - dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[el2_lsu.scala 267:50] - dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[el2_lsu.scala 268:50] - dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[el2_lsu.scala 269:50] - dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[el2_lsu.scala 270:50] - dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[el2_lsu.scala 271:50] - dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[el2_lsu.scala 272:50] - dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[el2_lsu.scala 273:50] - dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[el2_lsu.scala 274:50] - dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[el2_lsu.scala 275:50] - dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[el2_lsu.scala 276:50] - dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[el2_lsu.scala 277:50] - dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[el2_lsu.scala 278:50] - dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[el2_lsu.scala 279:50] - dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[el2_lsu.scala 280:50] - dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[el2_lsu.scala 281:50] - dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[el2_lsu.scala 282:50] - dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[el2_lsu.scala 283:50] - dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[el2_lsu.scala 284:50] - dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[el2_lsu.scala 285:50] - dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[el2_lsu.scala 286:50] - dccm_ctl.io.dma_mem_addr <= io.dma_mem_addr @[el2_lsu.scala 287:50] - dccm_ctl.io.dma_mem_wdata <= io.dma_mem_wdata @[el2_lsu.scala 288:50] - dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[el2_lsu.scala 289:50] - dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[el2_lsu.scala 290:50] - dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[el2_lsu.scala 291:50] - dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[el2_lsu.scala 292:50] - dccm_ctl.io.dccm_rd_data_lo <= io.dccm_rd_data_lo @[el2_lsu.scala 293:50] - dccm_ctl.io.dccm_rd_data_hi <= io.dccm_rd_data_hi @[el2_lsu.scala 294:50] - dccm_ctl.io.picm_rd_data <= io.picm_rd_data @[el2_lsu.scala 295:50] - dccm_ctl.io.scan_mode <= io.scan_mode @[el2_lsu.scala 296:50] - io.dccm_dma_rvalid <= dccm_ctl.io.dccm_dma_rvalid @[el2_lsu.scala 299:50] - io.dccm_dma_ecc_error <= dccm_ctl.io.dccm_dma_ecc_error @[el2_lsu.scala 300:50] - io.dccm_dma_rtag <= dccm_ctl.io.dccm_dma_rtag @[el2_lsu.scala 301:50] - io.dccm_dma_rdata <= dccm_ctl.io.dccm_dma_rdata @[el2_lsu.scala 302:50] - io.dccm_wren <= dccm_ctl.io.dccm_wren @[el2_lsu.scala 303:50] - io.dccm_rden <= dccm_ctl.io.dccm_rden @[el2_lsu.scala 304:50] - io.dccm_wr_addr_lo <= dccm_ctl.io.dccm_wr_addr_lo @[el2_lsu.scala 305:50] - io.dccm_wr_data_lo <= dccm_ctl.io.dccm_wr_data_lo @[el2_lsu.scala 306:50] - io.dccm_rd_addr_lo <= dccm_ctl.io.dccm_rd_addr_lo @[el2_lsu.scala 307:50] - io.dccm_wr_addr_hi <= dccm_ctl.io.dccm_wr_addr_hi @[el2_lsu.scala 308:50] - io.dccm_wr_data_hi <= dccm_ctl.io.dccm_wr_data_hi @[el2_lsu.scala 309:50] - io.dccm_rd_addr_hi <= dccm_ctl.io.dccm_rd_addr_hi @[el2_lsu.scala 310:50] - io.picm_wren <= dccm_ctl.io.picm_wren @[el2_lsu.scala 311:50] - io.picm_rden <= dccm_ctl.io.picm_rden @[el2_lsu.scala 312:50] - io.picm_mken <= dccm_ctl.io.picm_mken @[el2_lsu.scala 313:50] - io.picm_rdaddr <= dccm_ctl.io.picm_rdaddr @[el2_lsu.scala 314:50] - io.picm_wraddr <= dccm_ctl.io.picm_wraddr @[el2_lsu.scala 315:50] - io.picm_wr_data <= dccm_ctl.io.picm_wr_data @[el2_lsu.scala 316:50] - stbuf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 319:50] - stbuf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 320:56] + node _T_14 = dshr(io.dma_mem_wdata, _T_13) @[el2_lsu.scala 179:38] + dma_dccm_wdata <= _T_14 @[el2_lsu.scala 179:18] + node _T_15 = bits(dma_dccm_wdata, 63, 32) @[el2_lsu.scala 180:38] + dma_dccm_wdata_hi <= _T_15 @[el2_lsu.scala 180:21] + node _T_16 = bits(dma_dccm_wdata, 31, 0) @[el2_lsu.scala 181:38] + dma_dccm_wdata_lo <= _T_16 @[el2_lsu.scala 181:21] + node _T_17 = eq(lsu_lsc_ctl.io.lsu_pkt_m.dma, UInt<1>("h00")) @[el2_lsu.scala 190:58] + node _T_18 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_17) @[el2_lsu.scala 190:56] + node _T_19 = eq(lsu_lsc_ctl.io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu.scala 190:125] + node _T_20 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, _T_19) @[el2_lsu.scala 190:123] + node _T_21 = or(_T_18, _T_20) @[el2_lsu.scala 190:89] + node _T_22 = eq(_T_21, UInt<1>("h00")) @[el2_lsu.scala 190:22] + node _T_23 = and(_T_22, bus_intf.io.lsu_bus_buffer_empty_any) @[el2_lsu.scala 190:157] + node _T_24 = and(_T_23, bus_intf.io.lsu_bus_idle_any) @[el2_lsu.scala 190:196] + io.lsu_idle_any <= _T_24 @[el2_lsu.scala 190:19] + node _T_25 = and(lsu_lsc_ctl.io.lsu_pkt_r.valid, lsu_lsc_ctl.io.lsu_pkt_r.store) @[el2_lsu.scala 192:61] + node _T_26 = and(_T_25, lsu_lsc_ctl.io.addr_in_dccm_r) @[el2_lsu.scala 192:94] + node _T_27 = eq(io.dec_tlu_i0_kill_writeb_r, UInt<1>("h00")) @[el2_lsu.scala 192:128] + node _T_28 = and(_T_26, _T_27) @[el2_lsu.scala 192:126] + node _T_29 = eq(lsu_lsc_ctl.io.lsu_pkt_r.dma, UInt<1>("h00")) @[el2_lsu.scala 192:139] + node store_stbuf_reqvld_r = and(_T_28, _T_29) @[el2_lsu.scala 192:137] + node _T_30 = or(lsu_lsc_ctl.io.lsu_pkt_m.load, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 194:85] + node _T_31 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_30) @[el2_lsu.scala 194:52] + node _T_32 = or(lsu_lsc_ctl.io.addr_in_dccm_m, lsu_lsc_ctl.io.addr_in_pic_m) @[el2_lsu.scala 194:152] + node lsu_cmpen_m = and(_T_31, _T_32) @[el2_lsu.scala 194:119] + node _T_33 = or(lsu_lsc_ctl.io.lsu_pkt_m.load, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 196:87] + node _T_34 = and(_T_33, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 196:121] + node _T_35 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_34) @[el2_lsu.scala 196:53] + node _T_36 = eq(io.dec_tlu_flush_lower_r, UInt<1>("h00")) @[el2_lsu.scala 196:157] + node _T_37 = and(_T_35, _T_36) @[el2_lsu.scala 196:155] + node _T_38 = eq(lsu_lsc_ctl.io.lsu_exc_m, UInt<1>("h00")) @[el2_lsu.scala 196:171] + node _T_39 = and(_T_37, _T_38) @[el2_lsu.scala 196:169] + node _T_40 = eq(lsu_lsc_ctl.io.lsu_pkt_m.fast_int, UInt<1>("h00")) @[el2_lsu.scala 196:199] + node lsu_busreq_m = and(_T_39, _T_40) @[el2_lsu.scala 196:197] + node _T_41 = bits(lsu_lsc_ctl.io.lsu_addr_m, 0, 0) @[el2_lsu.scala 198:122] + node _T_42 = and(lsu_lsc_ctl.io.lsu_pkt_m.half, _T_41) @[el2_lsu.scala 198:95] + node _T_43 = bits(lsu_lsc_ctl.io.lsu_addr_m, 1, 0) @[el2_lsu.scala 198:187] + node _T_44 = orr(_T_43) @[el2_lsu.scala 198:193] + node _T_45 = and(lsu_lsc_ctl.io.lsu_pkt_m.word, _T_44) @[el2_lsu.scala 198:160] + node _T_46 = or(_T_42, _T_45) @[el2_lsu.scala 198:127] + node _T_47 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, _T_46) @[el2_lsu.scala 198:61] + io.lsu_pmu_misaligned_m <= _T_47 @[el2_lsu.scala 198:27] + node _T_48 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.load) @[el2_lsu.scala 199:65] + node _T_49 = and(_T_48, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 199:97] + io.lsu_pmu_load_external_m <= _T_49 @[el2_lsu.scala 199:31] + node _T_50 = and(lsu_lsc_ctl.io.lsu_pkt_m.valid, lsu_lsc_ctl.io.lsu_pkt_m.store) @[el2_lsu.scala 200:65] + node _T_51 = and(_T_50, lsu_lsc_ctl.io.addr_external_m) @[el2_lsu.scala 200:98] + io.lsu_pmu_store_external_m <= _T_51 @[el2_lsu.scala 200:31] + lsu_lsc_ctl.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 204:46] + lsu_lsc_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 205:46] + lsu_lsc_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 206:46] + lsu_lsc_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 207:46] + lsu_lsc_ctl.io.lsu_store_c1_m_clk <= clkdomain.io.lsu_store_c1_m_clk @[el2_lsu.scala 208:46] + lsu_lsc_ctl.io.lsu_ld_data_r <= dccm_ctl.io.lsu_ld_data_r @[el2_lsu.scala 209:46] + lsu_lsc_ctl.io.lsu_ld_data_corr_r <= dccm_ctl.io.lsu_ld_data_corr_r @[el2_lsu.scala 210:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_r <= ecc.io.lsu_single_ecc_error_r @[el2_lsu.scala 211:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[el2_lsu.scala 212:46] + lsu_lsc_ctl.io.lsu_ld_data_m <= dccm_ctl.io.lsu_ld_data_m @[el2_lsu.scala 213:46] + lsu_lsc_ctl.io.lsu_single_ecc_error_m <= ecc.io.lsu_single_ecc_error_m @[el2_lsu.scala 214:46] + lsu_lsc_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[el2_lsu.scala 215:46] + lsu_lsc_ctl.io.flush_m_up <= io.dec_tlu_flush_lower_r @[el2_lsu.scala 216:46] + lsu_lsc_ctl.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[el2_lsu.scala 217:46] + lsu_lsc_ctl.io.exu_lsu_rs1_d <= io.exu_lsu_rs1_d @[el2_lsu.scala 218:46] + lsu_lsc_ctl.io.exu_lsu_rs2_d <= io.exu_lsu_rs2_d @[el2_lsu.scala 219:46] + lsu_lsc_ctl.io.lsu_p.valid <= io.lsu_p.valid @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.store_data_bypass_m <= io.lsu_p.store_data_bypass_m @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.load_ldst_bypass_d <= io.lsu_p.load_ldst_bypass_d @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.store_data_bypass_d <= io.lsu_p.store_data_bypass_d @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.dma <= io.lsu_p.dma @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.unsign <= io.lsu_p.unsign @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.store <= io.lsu_p.store @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.load <= io.lsu_p.load @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.dword <= io.lsu_p.dword @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.word <= io.lsu_p.word @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.half <= io.lsu_p.half @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.by <= io.lsu_p.by @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.lsu_p.fast_int <= io.lsu_p.fast_int @[el2_lsu.scala 220:46] + lsu_lsc_ctl.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 221:46] + lsu_lsc_ctl.io.dec_lsu_offset_d <= io.dec_lsu_offset_d @[el2_lsu.scala 222:46] + lsu_lsc_ctl.io.picm_mask_data_m <= dccm_ctl.io.picm_mask_data_m @[el2_lsu.scala 223:46] + lsu_lsc_ctl.io.bus_read_data_m <= bus_intf.io.bus_read_data_m @[el2_lsu.scala 224:46] + lsu_lsc_ctl.io.dma_dccm_req <= io.dma_dccm_req @[el2_lsu.scala 225:46] + lsu_lsc_ctl.io.dma_mem_addr <= io.dma_mem_addr @[el2_lsu.scala 226:46] + lsu_lsc_ctl.io.dma_mem_sz <= io.dma_mem_sz @[el2_lsu.scala 227:46] + lsu_lsc_ctl.io.dma_mem_write <= io.dma_mem_write @[el2_lsu.scala 228:46] + lsu_lsc_ctl.io.dma_mem_wdata <= io.dma_mem_wdata @[el2_lsu.scala 229:46] + lsu_lsc_ctl.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[el2_lsu.scala 230:46] + lsu_lsc_ctl.io.scan_mode <= io.scan_mode @[el2_lsu.scala 231:46] + io.lsu_single_ecc_error_incr <= lsu_lsc_ctl.io.lsu_single_ecc_error_incr @[el2_lsu.scala 234:49] + io.lsu_error_pkt_r.addr <= lsu_lsc_ctl.io.lsu_error_pkt_r.addr @[el2_lsu.scala 235:49] + io.lsu_error_pkt_r.mscause <= lsu_lsc_ctl.io.lsu_error_pkt_r.mscause @[el2_lsu.scala 235:49] + io.lsu_error_pkt_r.exc_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.exc_type @[el2_lsu.scala 235:49] + io.lsu_error_pkt_r.inst_type <= lsu_lsc_ctl.io.lsu_error_pkt_r.inst_type @[el2_lsu.scala 235:49] + io.lsu_error_pkt_r.single_ecc_error <= lsu_lsc_ctl.io.lsu_error_pkt_r.single_ecc_error @[el2_lsu.scala 235:49] + io.lsu_error_pkt_r.exc_valid <= lsu_lsc_ctl.io.lsu_error_pkt_r.exc_valid @[el2_lsu.scala 235:49] + io.lsu_fir_addr <= lsu_lsc_ctl.io.lsu_fir_addr @[el2_lsu.scala 236:49] + io.lsu_fir_error <= lsu_lsc_ctl.io.lsu_fir_error @[el2_lsu.scala 237:49] + dccm_ctl.io.lsu_c2_m_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 240:46] + dccm_ctl.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_m_clk @[el2_lsu.scala 241:46] + dccm_ctl.io.lsu_free_c2_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 242:46] + dccm_ctl.io.lsu_c1_r_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 243:46] + dccm_ctl.io.lsu_store_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 244:46] + dccm_ctl.io.lsu_pkt_d.valid <= lsu_lsc_ctl.io.lsu_pkt_d.valid @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_d.store_data_bypass_m @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.load_ldst_bypass_d @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_d.store_data_bypass_d @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.dma <= lsu_lsc_ctl.io.lsu_pkt_d.dma @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.unsign <= lsu_lsc_ctl.io.lsu_pkt_d.unsign @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.store <= lsu_lsc_ctl.io.lsu_pkt_d.store @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.load <= lsu_lsc_ctl.io.lsu_pkt_d.load @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.dword <= lsu_lsc_ctl.io.lsu_pkt_d.dword @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.word <= lsu_lsc_ctl.io.lsu_pkt_d.word @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.half <= lsu_lsc_ctl.io.lsu_pkt_d.half @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.by <= lsu_lsc_ctl.io.lsu_pkt_d.by @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_d.fast_int <= lsu_lsc_ctl.io.lsu_pkt_d.fast_int @[el2_lsu.scala 246:46] + dccm_ctl.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_d @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.dma <= lsu_lsc_ctl.io.lsu_pkt_m.dma @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.unsign @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.store <= lsu_lsc_ctl.io.lsu_pkt_m.store @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.load <= lsu_lsc_ctl.io.lsu_pkt_m.load @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.dword <= lsu_lsc_ctl.io.lsu_pkt_m.dword @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.word <= lsu_lsc_ctl.io.lsu_pkt_m.word @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.half <= lsu_lsc_ctl.io.lsu_pkt_m.half @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.by <= lsu_lsc_ctl.io.lsu_pkt_m.by @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_m.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.fast_int @[el2_lsu.scala 247:46] + dccm_ctl.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_m @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_d @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.dma <= lsu_lsc_ctl.io.lsu_pkt_r.dma @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.unsign @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.store <= lsu_lsc_ctl.io.lsu_pkt_r.store @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.load <= lsu_lsc_ctl.io.lsu_pkt_r.load @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.dword <= lsu_lsc_ctl.io.lsu_pkt_r.dword @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.word <= lsu_lsc_ctl.io.lsu_pkt_r.word @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.half <= lsu_lsc_ctl.io.lsu_pkt_r.half @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 248:46] + dccm_ctl.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 248:46] + dccm_ctl.io.addr_in_dccm_d <= lsu_lsc_ctl.io.addr_in_dccm_d @[el2_lsu.scala 249:46] + dccm_ctl.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[el2_lsu.scala 250:46] + dccm_ctl.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[el2_lsu.scala 251:46] + dccm_ctl.io.addr_in_pic_d <= lsu_lsc_ctl.io.addr_in_pic_d @[el2_lsu.scala 252:46] + dccm_ctl.io.addr_in_pic_m <= lsu_lsc_ctl.io.addr_in_pic_m @[el2_lsu.scala 253:46] + dccm_ctl.io.addr_in_pic_r <= lsu_lsc_ctl.io.addr_in_pic_r @[el2_lsu.scala 254:46] + dccm_ctl.io.lsu_raw_fwd_lo_r <= lsu_raw_fwd_lo_r @[el2_lsu.scala 255:46] + dccm_ctl.io.lsu_raw_fwd_hi_r <= lsu_raw_fwd_hi_r @[el2_lsu.scala 256:46] + dccm_ctl.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 257:46] + dccm_ctl.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[el2_lsu.scala 258:46] + dccm_ctl.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[el2_lsu.scala 259:46] + dccm_ctl.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[el2_lsu.scala 260:46] + dccm_ctl.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[el2_lsu.scala 261:46] + dccm_ctl.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[el2_lsu.scala 262:46] + dccm_ctl.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[el2_lsu.scala 263:46] + dccm_ctl.io.stbuf_reqvld_any <= stbuf.io.stbuf_reqvld_any @[el2_lsu.scala 264:46] + dccm_ctl.io.stbuf_addr_any <= stbuf.io.stbuf_addr_any @[el2_lsu.scala 265:46] + dccm_ctl.io.stbuf_data_any <= stbuf.io.stbuf_data_any @[el2_lsu.scala 266:46] + dccm_ctl.io.stbuf_ecc_any <= ecc.io.stbuf_ecc_any @[el2_lsu.scala 267:46] + dccm_ctl.io.stbuf_fwddata_hi_m <= stbuf.io.stbuf_fwddata_hi_m @[el2_lsu.scala 268:46] + dccm_ctl.io.stbuf_fwddata_lo_m <= stbuf.io.stbuf_fwddata_lo_m @[el2_lsu.scala 269:46] + dccm_ctl.io.stbuf_fwdbyteen_lo_m <= stbuf.io.stbuf_fwdbyteen_lo_m @[el2_lsu.scala 270:46] + dccm_ctl.io.stbuf_fwdbyteen_hi_m <= stbuf.io.stbuf_fwdbyteen_hi_m @[el2_lsu.scala 271:46] + dccm_ctl.io.lsu_double_ecc_error_r <= ecc.io.lsu_double_ecc_error_r @[el2_lsu.scala 272:46] + dccm_ctl.io.single_ecc_error_hi_r <= ecc.io.single_ecc_error_hi_r @[el2_lsu.scala 273:46] + dccm_ctl.io.single_ecc_error_lo_r <= ecc.io.single_ecc_error_lo_r @[el2_lsu.scala 274:46] + dccm_ctl.io.sec_data_hi_r <= ecc.io.sec_data_hi_r @[el2_lsu.scala 275:46] + dccm_ctl.io.sec_data_lo_r <= ecc.io.sec_data_lo_r @[el2_lsu.scala 276:46] + dccm_ctl.io.sec_data_hi_r_ff <= ecc.io.sec_data_hi_r_ff @[el2_lsu.scala 277:46] + dccm_ctl.io.sec_data_lo_r_ff <= ecc.io.sec_data_lo_r_ff @[el2_lsu.scala 278:46] + dccm_ctl.io.sec_data_ecc_hi_r_ff <= ecc.io.sec_data_ecc_hi_r_ff @[el2_lsu.scala 279:46] + dccm_ctl.io.sec_data_ecc_lo_r_ff <= ecc.io.sec_data_ecc_lo_r_ff @[el2_lsu.scala 280:46] + dccm_ctl.io.lsu_double_ecc_error_m <= ecc.io.lsu_double_ecc_error_m @[el2_lsu.scala 281:46] + dccm_ctl.io.sec_data_hi_m <= ecc.io.sec_data_hi_m @[el2_lsu.scala 282:46] + dccm_ctl.io.sec_data_lo_m <= ecc.io.sec_data_lo_m @[el2_lsu.scala 283:46] + dccm_ctl.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[el2_lsu.scala 284:46] + dccm_ctl.io.dma_dccm_wen <= dma_dccm_wen @[el2_lsu.scala 285:46] + dccm_ctl.io.dma_pic_wen <= dma_pic_wen @[el2_lsu.scala 286:46] + dccm_ctl.io.dma_mem_tag_m <= dma_mem_tag_m @[el2_lsu.scala 287:46] + dccm_ctl.io.dma_mem_addr <= io.dma_mem_addr @[el2_lsu.scala 288:46] + dccm_ctl.io.dma_mem_wdata <= io.dma_mem_wdata @[el2_lsu.scala 289:46] + dccm_ctl.io.dma_dccm_wdata_lo <= dma_dccm_wdata_lo @[el2_lsu.scala 290:46] + dccm_ctl.io.dma_dccm_wdata_hi <= dma_dccm_wdata_hi @[el2_lsu.scala 291:46] + dccm_ctl.io.dma_dccm_wdata_ecc_hi <= ecc.io.dma_dccm_wdata_ecc_hi @[el2_lsu.scala 292:46] + dccm_ctl.io.dma_dccm_wdata_ecc_lo <= ecc.io.dma_dccm_wdata_ecc_lo @[el2_lsu.scala 293:46] + dccm_ctl.io.dccm_rd_data_lo <= io.dccm_rd_data_lo @[el2_lsu.scala 294:46] + dccm_ctl.io.dccm_rd_data_hi <= io.dccm_rd_data_hi @[el2_lsu.scala 295:46] + dccm_ctl.io.picm_rd_data <= io.picm_rd_data @[el2_lsu.scala 296:46] + dccm_ctl.io.scan_mode <= io.scan_mode @[el2_lsu.scala 297:46] + io.dccm_dma_rvalid <= dccm_ctl.io.dccm_dma_rvalid @[el2_lsu.scala 299:49] + io.dccm_dma_ecc_error <= dccm_ctl.io.dccm_dma_ecc_error @[el2_lsu.scala 300:49] + io.dccm_dma_rtag <= dccm_ctl.io.dccm_dma_rtag @[el2_lsu.scala 301:49] + io.dccm_dma_rdata <= dccm_ctl.io.dccm_dma_rdata @[el2_lsu.scala 302:49] + io.dccm_wren <= dccm_ctl.io.dccm_wren @[el2_lsu.scala 303:49] + io.dccm_rden <= dccm_ctl.io.dccm_rden @[el2_lsu.scala 304:49] + io.dccm_wr_addr_lo <= dccm_ctl.io.dccm_wr_addr_lo @[el2_lsu.scala 305:49] + io.dccm_wr_data_lo <= dccm_ctl.io.dccm_wr_data_lo @[el2_lsu.scala 306:49] + io.dccm_rd_addr_lo <= dccm_ctl.io.dccm_rd_addr_lo @[el2_lsu.scala 307:49] + io.dccm_wr_addr_hi <= dccm_ctl.io.dccm_wr_addr_hi @[el2_lsu.scala 308:49] + io.dccm_wr_data_hi <= dccm_ctl.io.dccm_wr_data_hi @[el2_lsu.scala 309:49] + io.dccm_rd_addr_hi <= dccm_ctl.io.dccm_rd_addr_hi @[el2_lsu.scala 310:49] + io.picm_wren <= dccm_ctl.io.picm_wren @[el2_lsu.scala 311:49] + io.picm_rden <= dccm_ctl.io.picm_rden @[el2_lsu.scala 312:49] + io.picm_mken <= dccm_ctl.io.picm_mken @[el2_lsu.scala 313:49] + io.picm_rdaddr <= dccm_ctl.io.picm_rdaddr @[el2_lsu.scala 314:49] + io.picm_wraddr <= dccm_ctl.io.picm_wraddr @[el2_lsu.scala 315:49] + io.picm_wr_data <= dccm_ctl.io.picm_wr_data @[el2_lsu.scala 316:49] + stbuf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 319:49] + stbuf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 320:48] stbuf.io.lsu_stbuf_c1_clk <= clkdomain.io.lsu_stbuf_c1_clk @[el2_lsu.scala 321:54] stbuf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 322:54] - stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_d @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.dma <= lsu_lsc_ctl.io.lsu_pkt_m.dma @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.unsign @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.store <= lsu_lsc_ctl.io.lsu_pkt_m.store @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.load <= lsu_lsc_ctl.io.lsu_pkt_m.load @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.dword <= lsu_lsc_ctl.io.lsu_pkt_m.dword @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.word <= lsu_lsc_ctl.io.lsu_pkt_m.word @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.half <= lsu_lsc_ctl.io.lsu_pkt_m.half @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.by <= lsu_lsc_ctl.io.lsu_pkt_m.by @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_m.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.fast_int @[el2_lsu.scala 323:56] - stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_m @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_d @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.dma <= lsu_lsc_ctl.io.lsu_pkt_r.dma @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.unsign @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.store <= lsu_lsc_ctl.io.lsu_pkt_r.store @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.load <= lsu_lsc_ctl.io.lsu_pkt_r.load @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.dword <= lsu_lsc_ctl.io.lsu_pkt_r.dword @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.word <= lsu_lsc_ctl.io.lsu_pkt_r.word @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.half <= lsu_lsc_ctl.io.lsu_pkt_r.half @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 324:56] - stbuf.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 324:56] - stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[el2_lsu.scala 325:56] - stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 326:50] - stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 327:50] + stbuf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_d @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.dma <= lsu_lsc_ctl.io.lsu_pkt_m.dma @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.unsign @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.store <= lsu_lsc_ctl.io.lsu_pkt_m.store @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.load <= lsu_lsc_ctl.io.lsu_pkt_m.load @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.dword <= lsu_lsc_ctl.io.lsu_pkt_m.dword @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.word <= lsu_lsc_ctl.io.lsu_pkt_m.word @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.half <= lsu_lsc_ctl.io.lsu_pkt_m.half @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.by <= lsu_lsc_ctl.io.lsu_pkt_m.by @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_m.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.fast_int @[el2_lsu.scala 323:48] + stbuf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_m @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_d @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.dma <= lsu_lsc_ctl.io.lsu_pkt_r.dma @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.unsign @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.store <= lsu_lsc_ctl.io.lsu_pkt_r.store @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.load <= lsu_lsc_ctl.io.lsu_pkt_r.load @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.dword <= lsu_lsc_ctl.io.lsu_pkt_r.dword @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.word <= lsu_lsc_ctl.io.lsu_pkt_r.word @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.half <= lsu_lsc_ctl.io.lsu_pkt_r.half @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 324:48] + stbuf.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 324:48] + stbuf.io.store_stbuf_reqvld_r <= store_stbuf_reqvld_r @[el2_lsu.scala 325:48] + stbuf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 326:49] + stbuf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 327:49] stbuf.io.store_data_hi_r <= dccm_ctl.io.store_data_hi_r @[el2_lsu.scala 328:62] stbuf.io.store_data_lo_r <= dccm_ctl.io.store_data_lo_r @[el2_lsu.scala 329:62] - stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[el2_lsu.scala 330:50] + stbuf.io.store_datafn_hi_r <= dccm_ctl.io.store_datafn_hi_r @[el2_lsu.scala 330:49] stbuf.io.store_datafn_lo_r <= dccm_ctl.io.store_datafn_lo_r @[el2_lsu.scala 331:56] - stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[el2_lsu.scala 332:60] + stbuf.io.lsu_stbuf_commit_any <= dccm_ctl.io.lsu_stbuf_commit_any @[el2_lsu.scala 332:52] stbuf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[el2_lsu.scala 333:64] stbuf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[el2_lsu.scala 334:64] stbuf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[el2_lsu.scala 335:64] stbuf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[el2_lsu.scala 336:64] stbuf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[el2_lsu.scala 337:64] stbuf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[el2_lsu.scala 338:64] - stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[el2_lsu.scala 339:50] + stbuf.io.addr_in_dccm_m <= lsu_lsc_ctl.io.addr_in_dccm_m @[el2_lsu.scala 339:49] stbuf.io.addr_in_dccm_r <= lsu_lsc_ctl.io.addr_in_dccm_r @[el2_lsu.scala 340:56] stbuf.io.lsu_cmpen_m <= lsu_cmpen_m @[el2_lsu.scala 341:54] - stbuf.io.scan_mode <= io.scan_mode @[el2_lsu.scala 342:50] + stbuf.io.scan_mode <= io.scan_mode @[el2_lsu.scala 342:49] ecc.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 346:52] ecc.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 347:52] ecc.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 347:52] @@ -7434,95 +15691,121 @@ circuit el2_lsu : clkdomain.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 400:50] clkdomain.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 400:50] clkdomain.io.scan_mode <= io.scan_mode @[el2_lsu.scala 401:50] - bus_intf.io.scan_mode <= io.scan_mode @[el2_lsu.scala 405:50] - bus_intf.io.dec_tlu_external_ldfwd_disable <= io.dec_tlu_external_ldfwd_disable @[el2_lsu.scala 406:50] - bus_intf.io.dec_tlu_wb_coalescing_disable <= io.dec_tlu_wb_coalescing_disable @[el2_lsu.scala 407:50] - bus_intf.io.dec_tlu_sideeffect_posted_disable <= io.dec_tlu_sideeffect_posted_disable @[el2_lsu.scala 408:50] - bus_intf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 409:50] - bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 410:50] - bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 411:50] - bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[el2_lsu.scala 412:50] - bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[el2_lsu.scala 413:50] - bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[el2_lsu.scala 414:50] - bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 415:50] - bus_intf.io.free_clk <= io.free_clk @[el2_lsu.scala 416:50] - bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[el2_lsu.scala 417:50] - bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 418:50] - bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[el2_lsu.scala 419:50] - bus_intf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[el2_lsu.scala 420:50] - bus_intf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[el2_lsu.scala 421:50] - bus_intf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[el2_lsu.scala 422:50] - bus_intf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[el2_lsu.scala 423:50] - bus_intf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[el2_lsu.scala 424:50] - bus_intf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[el2_lsu.scala 425:50] - bus_intf.io.store_data_m <= lsu_lsc_ctl.io.store_data_m @[el2_lsu.scala 426:50] - bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[el2_lsu.scala 427:50] - bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 428:50] - bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[el2_lsu.scala 429:50] - bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[el2_lsu.scala 430:50] - bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[el2_lsu.scala 431:50] - io.lsu_imprecise_error_load_any <= bus_intf.io.lsu_imprecise_error_load_any @[el2_lsu.scala 434:50] - io.lsu_imprecise_error_store_any <= bus_intf.io.lsu_imprecise_error_store_any @[el2_lsu.scala 435:50] - io.lsu_imprecise_error_addr_any <= bus_intf.io.lsu_imprecise_error_addr_any @[el2_lsu.scala 436:50] - io.lsu_nonblock_load_valid_m <= bus_intf.io.lsu_nonblock_load_valid_m @[el2_lsu.scala 437:50] - io.lsu_nonblock_load_tag_m <= bus_intf.io.lsu_nonblock_load_tag_m @[el2_lsu.scala 438:50] - io.lsu_nonblock_load_inv_r <= bus_intf.io.lsu_nonblock_load_inv_r @[el2_lsu.scala 439:50] - io.lsu_nonblock_load_inv_tag_r <= bus_intf.io.lsu_nonblock_load_inv_tag_r @[el2_lsu.scala 440:50] - io.lsu_nonblock_load_data_valid <= bus_intf.io.lsu_nonblock_load_data_valid @[el2_lsu.scala 441:50] - io.lsu_nonblock_load_data_error <= bus_intf.io.lsu_nonblock_load_data_error @[el2_lsu.scala 442:50] - io.lsu_nonblock_load_data_tag <= bus_intf.io.lsu_nonblock_load_data_tag @[el2_lsu.scala 443:50] - io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[el2_lsu.scala 444:50] - io.lsu_pmu_bus_trxn <= bus_intf.io.lsu_pmu_bus_trxn @[el2_lsu.scala 445:50] - io.lsu_pmu_bus_misaligned <= bus_intf.io.lsu_pmu_bus_misaligned @[el2_lsu.scala 446:50] - io.lsu_pmu_bus_error <= bus_intf.io.lsu_pmu_bus_error @[el2_lsu.scala 447:50] - io.lsu_pmu_bus_busy <= bus_intf.io.lsu_pmu_bus_busy @[el2_lsu.scala 448:50] - io.lsu_axi_awvalid <= bus_intf.io.lsu_axi_awvalid @[el2_lsu.scala 449:50] - bus_intf.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_lsu.scala 450:50] - io.lsu_axi_awid <= bus_intf.io.lsu_axi_awid @[el2_lsu.scala 451:50] - io.lsu_axi_awaddr <= bus_intf.io.lsu_axi_awaddr @[el2_lsu.scala 452:50] - io.lsu_axi_awregion <= bus_intf.io.lsu_axi_awregion @[el2_lsu.scala 453:50] - io.lsu_axi_awlen <= bus_intf.io.lsu_axi_awlen @[el2_lsu.scala 454:50] - io.lsu_axi_awsize <= bus_intf.io.lsu_axi_awsize @[el2_lsu.scala 455:50] - io.lsu_axi_awburst <= bus_intf.io.lsu_axi_awburst @[el2_lsu.scala 456:50] - io.lsu_axi_awlock <= bus_intf.io.lsu_axi_awlock @[el2_lsu.scala 457:50] - io.lsu_axi_awcache <= bus_intf.io.lsu_axi_awcache @[el2_lsu.scala 458:50] - io.lsu_axi_awprot <= bus_intf.io.lsu_axi_awprot @[el2_lsu.scala 459:50] - io.lsu_axi_awqos <= bus_intf.io.lsu_axi_awqos @[el2_lsu.scala 460:50] - io.lsu_axi_wvalid <= bus_intf.io.lsu_axi_wvalid @[el2_lsu.scala 461:50] - bus_intf.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_lsu.scala 462:50] - io.lsu_axi_wdata <= bus_intf.io.lsu_axi_wdata @[el2_lsu.scala 463:50] - io.lsu_axi_wstrb <= bus_intf.io.lsu_axi_wstrb @[el2_lsu.scala 464:50] - io.lsu_axi_wlast <= bus_intf.io.lsu_axi_wlast @[el2_lsu.scala 465:50] - bus_intf.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_lsu.scala 466:50] - io.lsu_axi_bready <= bus_intf.io.lsu_axi_bready @[el2_lsu.scala 467:50] - bus_intf.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_lsu.scala 468:50] - bus_intf.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_lsu.scala 469:50] - io.lsu_axi_arvalid <= bus_intf.io.lsu_axi_arvalid @[el2_lsu.scala 470:50] - bus_intf.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_lsu.scala 471:50] - io.lsu_axi_arid <= bus_intf.io.lsu_axi_arid @[el2_lsu.scala 472:50] - io.lsu_axi_araddr <= bus_intf.io.lsu_axi_araddr @[el2_lsu.scala 473:50] - io.lsu_axi_arregion <= bus_intf.io.lsu_axi_arregion @[el2_lsu.scala 474:50] - io.lsu_axi_arlen <= bus_intf.io.lsu_axi_arlen @[el2_lsu.scala 475:50] - io.lsu_axi_arsize <= bus_intf.io.lsu_axi_arsize @[el2_lsu.scala 476:50] - io.lsu_axi_arburst <= bus_intf.io.lsu_axi_arburst @[el2_lsu.scala 477:50] - io.lsu_axi_arlock <= bus_intf.io.lsu_axi_arlock @[el2_lsu.scala 478:50] - io.lsu_axi_arcache <= bus_intf.io.lsu_axi_arcache @[el2_lsu.scala 479:50] - io.lsu_axi_arprot <= bus_intf.io.lsu_axi_arprot @[el2_lsu.scala 480:50] - io.lsu_axi_arqos <= bus_intf.io.lsu_axi_arqos @[el2_lsu.scala 481:50] - bus_intf.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_lsu.scala 482:50] - io.lsu_axi_rready <= bus_intf.io.lsu_axi_rready @[el2_lsu.scala 483:50] - bus_intf.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_lsu.scala 484:50] - bus_intf.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_lsu.scala 485:50] - bus_intf.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_lsu.scala 486:50] - bus_intf.io.lsu_axi_rlast <= io.lsu_axi_rlast @[el2_lsu.scala 487:50] - bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_lsu.scala 488:50] - reg _T_52 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 490:67] - _T_52 <= io.dma_mem_tag @[el2_lsu.scala 490:67] - dma_mem_tag_m <= _T_52 @[el2_lsu.scala 490:57] - reg _T_53 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 491:67] - _T_53 <= lsu_raw_fwd_hi_m @[el2_lsu.scala 491:67] - lsu_raw_fwd_hi_r <= _T_53 @[el2_lsu.scala 491:57] - reg _T_54 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 492:67] - _T_54 <= lsu_raw_fwd_lo_m @[el2_lsu.scala 492:67] - lsu_raw_fwd_lo_r <= _T_54 @[el2_lsu.scala 492:57] + bus_intf.io.scan_mode <= io.scan_mode @[el2_lsu.scala 405:49] + bus_intf.io.dec_tlu_external_ldfwd_disable <= io.dec_tlu_external_ldfwd_disable @[el2_lsu.scala 406:49] + bus_intf.io.dec_tlu_wb_coalescing_disable <= io.dec_tlu_wb_coalescing_disable @[el2_lsu.scala 407:49] + bus_intf.io.dec_tlu_sideeffect_posted_disable <= io.dec_tlu_sideeffect_posted_disable @[el2_lsu.scala 408:49] + bus_intf.io.lsu_c1_m_clk <= clkdomain.io.lsu_c1_m_clk @[el2_lsu.scala 409:49] + bus_intf.io.lsu_c1_r_clk <= clkdomain.io.lsu_c1_r_clk @[el2_lsu.scala 410:49] + bus_intf.io.lsu_c2_r_clk <= clkdomain.io.lsu_c2_r_clk @[el2_lsu.scala 411:49] + bus_intf.io.lsu_bus_ibuf_c1_clk <= clkdomain.io.lsu_bus_ibuf_c1_clk @[el2_lsu.scala 412:49] + bus_intf.io.lsu_bus_obuf_c1_clk <= clkdomain.io.lsu_bus_obuf_c1_clk @[el2_lsu.scala 413:49] + bus_intf.io.lsu_bus_buf_c1_clk <= clkdomain.io.lsu_bus_buf_c1_clk @[el2_lsu.scala 414:49] + bus_intf.io.lsu_free_c2_clk <= clkdomain.io.lsu_free_c2_clk @[el2_lsu.scala 415:49] + bus_intf.io.free_clk <= io.free_clk @[el2_lsu.scala 416:49] + bus_intf.io.lsu_busm_clk <= clkdomain.io.lsu_busm_clk @[el2_lsu.scala 417:49] + bus_intf.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu.scala 418:49] + bus_intf.io.lsu_busreq_m <= lsu_busreq_m @[el2_lsu.scala 419:49] + bus_intf.io.lsu_addr_d <= lsu_lsc_ctl.io.lsu_addr_d @[el2_lsu.scala 420:49] + bus_intf.io.lsu_addr_m <= lsu_lsc_ctl.io.lsu_addr_m @[el2_lsu.scala 421:49] + bus_intf.io.lsu_addr_r <= lsu_lsc_ctl.io.lsu_addr_r @[el2_lsu.scala 422:49] + bus_intf.io.end_addr_d <= lsu_lsc_ctl.io.end_addr_d @[el2_lsu.scala 423:49] + bus_intf.io.end_addr_m <= lsu_lsc_ctl.io.end_addr_m @[el2_lsu.scala 424:49] + bus_intf.io.end_addr_r <= lsu_lsc_ctl.io.end_addr_r @[el2_lsu.scala 425:49] + bus_intf.io.store_data_r <= dccm_ctl.io.store_data_r @[el2_lsu.scala 426:49] + bus_intf.io.lsu_pkt_m.valid <= lsu_lsc_ctl.io.lsu_pkt_m.valid @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_m @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_m.store_data_bypass_d @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.dma <= lsu_lsc_ctl.io.lsu_pkt_m.dma @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.unsign <= lsu_lsc_ctl.io.lsu_pkt_m.unsign @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.store <= lsu_lsc_ctl.io.lsu_pkt_m.store @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.load <= lsu_lsc_ctl.io.lsu_pkt_m.load @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.dword <= lsu_lsc_ctl.io.lsu_pkt_m.dword @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.word <= lsu_lsc_ctl.io.lsu_pkt_m.word @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.half <= lsu_lsc_ctl.io.lsu_pkt_m.half @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.by <= lsu_lsc_ctl.io.lsu_pkt_m.by @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_m.fast_int <= lsu_lsc_ctl.io.lsu_pkt_m.fast_int @[el2_lsu.scala 427:49] + bus_intf.io.lsu_pkt_r.valid <= lsu_lsc_ctl.io.lsu_pkt_r.valid @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.store_data_bypass_m <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_m @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.load_ldst_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.store_data_bypass_d <= lsu_lsc_ctl.io.lsu_pkt_r.store_data_bypass_d @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.dma <= lsu_lsc_ctl.io.lsu_pkt_r.dma @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.unsign <= lsu_lsc_ctl.io.lsu_pkt_r.unsign @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.store <= lsu_lsc_ctl.io.lsu_pkt_r.store @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.load <= lsu_lsc_ctl.io.lsu_pkt_r.load @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.dword <= lsu_lsc_ctl.io.lsu_pkt_r.dword @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.word <= lsu_lsc_ctl.io.lsu_pkt_r.word @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.half <= lsu_lsc_ctl.io.lsu_pkt_r.half @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.by <= lsu_lsc_ctl.io.lsu_pkt_r.by @[el2_lsu.scala 428:49] + bus_intf.io.lsu_pkt_r.fast_int <= lsu_lsc_ctl.io.lsu_pkt_r.fast_int @[el2_lsu.scala 428:49] + bus_intf.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[el2_lsu.scala 429:49] + bus_intf.io.lsu_commit_r <= lsu_lsc_ctl.io.lsu_commit_r @[el2_lsu.scala 430:49] + bus_intf.io.is_sideeffects_m <= lsu_lsc_ctl.io.is_sideeffects_m @[el2_lsu.scala 431:49] + bus_intf.io.flush_m_up <= io.dec_tlu_flush_lower_r @[el2_lsu.scala 432:49] + bus_intf.io.flush_r <= io.dec_tlu_i0_kill_writeb_r @[el2_lsu.scala 433:49] + io.lsu_imprecise_error_load_any <= bus_intf.io.lsu_imprecise_error_load_any @[el2_lsu.scala 436:49] + io.lsu_imprecise_error_store_any <= bus_intf.io.lsu_imprecise_error_store_any @[el2_lsu.scala 437:49] + io.lsu_imprecise_error_addr_any <= bus_intf.io.lsu_imprecise_error_addr_any @[el2_lsu.scala 438:49] + io.lsu_nonblock_load_valid_m <= bus_intf.io.lsu_nonblock_load_valid_m @[el2_lsu.scala 439:49] + io.lsu_nonblock_load_tag_m <= bus_intf.io.lsu_nonblock_load_tag_m @[el2_lsu.scala 440:49] + io.lsu_nonblock_load_inv_r <= bus_intf.io.lsu_nonblock_load_inv_r @[el2_lsu.scala 441:49] + io.lsu_nonblock_load_inv_tag_r <= bus_intf.io.lsu_nonblock_load_inv_tag_r @[el2_lsu.scala 442:49] + io.lsu_nonblock_load_data_valid <= bus_intf.io.lsu_nonblock_load_data_valid @[el2_lsu.scala 443:49] + io.lsu_nonblock_load_data_error <= bus_intf.io.lsu_nonblock_load_data_error @[el2_lsu.scala 444:49] + io.lsu_nonblock_load_data_tag <= bus_intf.io.lsu_nonblock_load_data_tag @[el2_lsu.scala 445:49] + io.lsu_nonblock_load_data <= bus_intf.io.lsu_nonblock_load_data @[el2_lsu.scala 446:49] + io.lsu_pmu_bus_trxn <= bus_intf.io.lsu_pmu_bus_trxn @[el2_lsu.scala 447:49] + io.lsu_pmu_bus_misaligned <= bus_intf.io.lsu_pmu_bus_misaligned @[el2_lsu.scala 448:49] + io.lsu_pmu_bus_error <= bus_intf.io.lsu_pmu_bus_error @[el2_lsu.scala 449:49] + io.lsu_pmu_bus_busy <= bus_intf.io.lsu_pmu_bus_busy @[el2_lsu.scala 450:49] + io.lsu_axi_awvalid <= bus_intf.io.lsu_axi_awvalid @[el2_lsu.scala 451:49] + bus_intf.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_lsu.scala 452:49] + io.lsu_axi_awid <= bus_intf.io.lsu_axi_awid @[el2_lsu.scala 453:49] + io.lsu_axi_awaddr <= bus_intf.io.lsu_axi_awaddr @[el2_lsu.scala 454:49] + io.lsu_axi_awregion <= bus_intf.io.lsu_axi_awregion @[el2_lsu.scala 455:49] + io.lsu_axi_awlen <= bus_intf.io.lsu_axi_awlen @[el2_lsu.scala 456:49] + io.lsu_axi_awsize <= bus_intf.io.lsu_axi_awsize @[el2_lsu.scala 457:49] + io.lsu_axi_awburst <= bus_intf.io.lsu_axi_awburst @[el2_lsu.scala 458:49] + io.lsu_axi_awlock <= bus_intf.io.lsu_axi_awlock @[el2_lsu.scala 459:49] + io.lsu_axi_awcache <= bus_intf.io.lsu_axi_awcache @[el2_lsu.scala 460:49] + io.lsu_axi_awprot <= bus_intf.io.lsu_axi_awprot @[el2_lsu.scala 461:49] + io.lsu_axi_awqos <= bus_intf.io.lsu_axi_awqos @[el2_lsu.scala 462:49] + io.lsu_axi_wvalid <= bus_intf.io.lsu_axi_wvalid @[el2_lsu.scala 463:49] + bus_intf.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_lsu.scala 464:49] + io.lsu_axi_wdata <= bus_intf.io.lsu_axi_wdata @[el2_lsu.scala 465:49] + io.lsu_axi_wstrb <= bus_intf.io.lsu_axi_wstrb @[el2_lsu.scala 466:49] + io.lsu_axi_wlast <= bus_intf.io.lsu_axi_wlast @[el2_lsu.scala 467:49] + bus_intf.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_lsu.scala 468:49] + io.lsu_axi_bready <= bus_intf.io.lsu_axi_bready @[el2_lsu.scala 469:49] + bus_intf.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_lsu.scala 470:49] + bus_intf.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_lsu.scala 471:49] + io.lsu_axi_arvalid <= bus_intf.io.lsu_axi_arvalid @[el2_lsu.scala 472:49] + bus_intf.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_lsu.scala 473:49] + io.lsu_axi_arid <= bus_intf.io.lsu_axi_arid @[el2_lsu.scala 474:49] + io.lsu_axi_araddr <= bus_intf.io.lsu_axi_araddr @[el2_lsu.scala 475:49] + io.lsu_axi_arregion <= bus_intf.io.lsu_axi_arregion @[el2_lsu.scala 476:49] + io.lsu_axi_arlen <= bus_intf.io.lsu_axi_arlen @[el2_lsu.scala 477:49] + io.lsu_axi_arsize <= bus_intf.io.lsu_axi_arsize @[el2_lsu.scala 478:49] + io.lsu_axi_arburst <= bus_intf.io.lsu_axi_arburst @[el2_lsu.scala 479:49] + io.lsu_axi_arlock <= bus_intf.io.lsu_axi_arlock @[el2_lsu.scala 480:49] + io.lsu_axi_arcache <= bus_intf.io.lsu_axi_arcache @[el2_lsu.scala 481:49] + io.lsu_axi_arprot <= bus_intf.io.lsu_axi_arprot @[el2_lsu.scala 482:49] + io.lsu_axi_arqos <= bus_intf.io.lsu_axi_arqos @[el2_lsu.scala 483:49] + bus_intf.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_lsu.scala 484:49] + io.lsu_axi_rready <= bus_intf.io.lsu_axi_rready @[el2_lsu.scala 485:49] + bus_intf.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_lsu.scala 486:49] + bus_intf.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_lsu.scala 487:49] + bus_intf.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_lsu.scala 488:49] + bus_intf.io.lsu_axi_rlast <= io.lsu_axi_rlast @[el2_lsu.scala 489:49] + bus_intf.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_lsu.scala 490:49] + reg _T_52 : UInt, clkdomain.io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 492:67] + _T_52 <= io.dma_mem_tag @[el2_lsu.scala 492:67] + dma_mem_tag_m <= _T_52 @[el2_lsu.scala 492:57] + reg _T_53 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 493:67] + _T_53 <= lsu_raw_fwd_hi_m @[el2_lsu.scala 493:67] + lsu_raw_fwd_hi_r <= _T_53 @[el2_lsu.scala 493:57] + reg _T_54 : UInt<1>, clkdomain.io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu.scala 494:67] + _T_54 <= lsu_raw_fwd_lo_m @[el2_lsu.scala 494:67] + lsu_raw_fwd_lo_r <= _T_54 @[el2_lsu.scala 494:57] diff --git a/el2_lsu.v b/el2_lsu.v index 5c943490..275bac8f 100644 --- a/el2_lsu.v +++ b/el2_lsu.v @@ -1,48 +1,9 @@ -module rvlsadder( - input [31:0] io_rs1, - input [11:0] io_offset, - output [31:0] io_dout -); - wire [12:0] _T_1 = {1'h0,io_rs1[11:0]}; // @[Cat.scala 29:58] - wire [12:0] _T_3 = {1'h0,io_offset}; // @[Cat.scala 29:58] - wire [12:0] w1 = _T_1 + _T_3; // @[beh_lib.scala 51:40] - wire _T_7 = io_offset[11] ^ w1[12]; // @[beh_lib.scala 53:47] - wire _T_8 = ~_T_7; // @[beh_lib.scala 53:31] - wire [19:0] _T_10 = _T_8 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_12 = _T_10 & io_rs1[31:12]; // @[beh_lib.scala 53:59] - wire _T_14 = ~io_offset[11]; // @[beh_lib.scala 54:16] - wire _T_16 = _T_14 & w1[12]; // @[beh_lib.scala 54:31] - wire [19:0] _T_18 = _T_16 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_21 = io_rs1[31:12] + 20'h1; // @[beh_lib.scala 54:58] - wire [19:0] _T_22 = _T_18 & _T_21; // @[beh_lib.scala 54:42] - wire [19:0] _T_23 = _T_12 | _T_22; // @[beh_lib.scala 53:76] - wire _T_26 = ~w1[12]; // @[beh_lib.scala 55:32] - wire _T_27 = io_offset[11] & _T_26; // @[beh_lib.scala 55:30] - wire [19:0] _T_29 = _T_27 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] - wire [19:0] _T_32 = io_rs1[31:12] - 20'h1; // @[beh_lib.scala 55:58] - wire [19:0] _T_33 = _T_29 & _T_32; // @[beh_lib.scala 55:42] - wire [19:0] dout_upper = _T_23 | _T_33; // @[beh_lib.scala 54:65] - assign io_dout = {dout_upper,w1[11:0]}; // @[beh_lib.scala 57:11] -endmodule -module rvrangecheck( - input [31:0] io_addr, - output io_in_range, - output io_in_region -); - assign io_in_range = io_addr[31:16] == 16'hf004; // @[beh_lib.scala 118:17] - assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 114:17] -endmodule -module rvrangecheck_2( - input [31:0] io_addr, - output io_in_range, - output io_in_region -); - assign io_in_range = io_addr[31:15] == 17'h1e018; // @[beh_lib.scala 118:17] - assign io_in_region = io_addr[31:28] == 4'hf; // @[beh_lib.scala 114:17] -endmodule module el2_lsu_addrcheck( + input reset, + input io_lsu_c2_m_clk, input [31:0] io_start_addr_d, input [31:0] io_end_addr_d, + input io_lsu_pkt_d_fast_int, input io_lsu_pkt_d_by, input io_lsu_pkt_d_half, input io_lsu_pkt_d_word, @@ -52,148 +13,121 @@ module el2_lsu_addrcheck( input io_lsu_pkt_d_valid, input [31:0] io_dec_tlu_mrac_ff, input [3:0] io_rs1_region_d, + output io_is_sideeffects_m, output io_addr_in_dccm_d, output io_addr_in_pic_d, output io_addr_external_d, output io_access_fault_d, output io_misaligned_fault_d, - output [3:0] io_exc_mscause_d + output [3:0] io_exc_mscause_d, + output io_fir_dccm_access_error_d, + output io_fir_nondccm_access_error_d ); - wire [31:0] rvrangecheck_io_addr; // @[el2_lsu_addrcheck.scala 45:44] - wire rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 45:44] - wire rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 45:44] - wire [31:0] rvrangecheck_1_io_addr; // @[el2_lsu_addrcheck.scala 51:44] - wire rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 51:44] - wire rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 51:44] - wire [31:0] start_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 74:41] - wire start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 74:41] - wire start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 74:41] - wire [31:0] end_addr_pic_rangecheck_io_addr; // @[el2_lsu_addrcheck.scala 80:39] - wire end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 80:39] - wire end_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 80:39] - wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 65:45] - wire start_addr_in_dccm_region_d = rvrangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 48:41] - wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_pic_rangecheck_io_in_region; // @[el2_lsu_addrcheck.scala 85:60] - wire _T_5 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 86:54] - wire base_reg_dccm_or_pic = _T_5 | _T_5; // @[el2_lsu_addrcheck.scala 86:74] - wire start_addr_in_dccm_d = rvrangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 47:41] - wire end_addr_in_dccm_d = rvrangecheck_1_io_in_range; // @[el2_lsu_addrcheck.scala 53:41] +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; +`endif // RANDOMIZE_REG_INIT + wire start_addr_in_dccm_region_d = io_start_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49] + wire start_addr_in_dccm_d = io_start_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39] + wire end_addr_in_dccm_region_d = io_end_addr_d[31:28] == 4'hf; // @[el2_lib.scala 496:49] + wire end_addr_in_dccm_d = io_end_addr_d[31:16] == 16'hf004; // @[el2_lib.scala 501:39] + wire addr_in_iccm = io_start_addr_d[31:28] == 4'he; // @[el2_lsu_addrcheck.scala 42:45] + wire start_addr_in_pic_d = io_start_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] + wire end_addr_in_pic_d = io_end_addr_d[31:15] == 17'h1e018; // @[el2_lib.scala 501:39] + wire start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 54:60] + wire _T_17 = io_rs1_region_d == 4'hf; // @[el2_lsu_addrcheck.scala 55:54] + wire base_reg_dccm_or_pic = _T_17 | _T_17; // @[el2_lsu_addrcheck.scala 55:73] wire [4:0] csr_idx = {io_start_addr_d[31:28],1'h1}; // @[Cat.scala 29:58] - wire [31:0] _T_13 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 92:50] - wire _T_16 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 92:121] - wire _T_17 = ~_T_16; // @[el2_lsu_addrcheck.scala 92:62] - wire _T_18 = _T_13[0] & _T_17; // @[el2_lsu_addrcheck.scala 92:60] - wire _T_19 = _T_18 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 92:137] - wire _T_20 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 92:180] - wire is_sideeffects_d = _T_19 & _T_20; // @[el2_lsu_addrcheck.scala 92:158] - wire _T_22 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 93:75] - wire _T_23 = io_lsu_pkt_d_word & _T_22; // @[el2_lsu_addrcheck.scala 93:51] - wire _T_25 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 93:128] - wire _T_26 = io_lsu_pkt_d_half & _T_25; // @[el2_lsu_addrcheck.scala 93:106] - wire _T_27 = _T_23 | _T_26; // @[el2_lsu_addrcheck.scala 93:85] - wire is_aligned_d = _T_27 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 93:138] - wire [31:0] _T_38 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:57] - wire _T_40 = _T_38 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 98:82] - wire [31:0] _T_43 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 99:57] - wire _T_45 = _T_43 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 99:82] - wire _T_47 = _T_40 | _T_45; // @[el2_lsu_addrcheck.scala 98:133] - wire [31:0] _T_49 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 100:57] - wire _T_51 = _T_49 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 100:82] - wire _T_53 = _T_47 | _T_51; // @[el2_lsu_addrcheck.scala 99:133] - wire [31:0] _T_55 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 101:57] - wire _T_57 = _T_55 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 101:82] - wire _T_59 = _T_53 | _T_57; // @[el2_lsu_addrcheck.scala 100:133] - wire [31:0] _T_85 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:58] - wire _T_87 = _T_85 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 107:83] - wire [31:0] _T_90 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 108:59] - wire _T_92 = _T_90 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 108:84] - wire _T_94 = _T_87 | _T_92; // @[el2_lsu_addrcheck.scala 107:134] - wire [31:0] _T_96 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 109:59] - wire _T_98 = _T_96 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 109:84] - wire _T_100 = _T_94 | _T_98; // @[el2_lsu_addrcheck.scala 108:135] - wire [31:0] _T_102 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 110:59] - wire _T_104 = _T_102 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 110:84] - wire _T_106 = _T_100 | _T_104; // @[el2_lsu_addrcheck.scala 109:135] - wire non_dccm_access_ok = _T_59 & _T_106; // @[el2_lsu_addrcheck.scala 106:7] - wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 116:57] - wire _T_133 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 117:76] - wire _T_134 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 117:92] - wire _T_135 = _T_133 | _T_134; // @[el2_lsu_addrcheck.scala 117:90] - wire picm_access_fault_d = io_addr_in_pic_d & _T_135; // @[el2_lsu_addrcheck.scala 117:51] - wire _T_136 = start_addr_in_dccm_d | start_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 122:87] - wire _T_137 = ~_T_136; // @[el2_lsu_addrcheck.scala 122:64] - wire _T_138 = start_addr_in_dccm_region_d & _T_137; // @[el2_lsu_addrcheck.scala 122:62] - wire _T_139 = end_addr_in_dccm_d | end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 124:57] - wire _T_140 = ~_T_139; // @[el2_lsu_addrcheck.scala 124:36] - wire end_addr_in_dccm_region_d = rvrangecheck_1_io_in_region; // @[el2_lsu_addrcheck.scala 54:41] - wire _T_141 = end_addr_in_dccm_region_d & _T_140; // @[el2_lsu_addrcheck.scala 124:34] - wire _T_142 = _T_138 | _T_141; // @[el2_lsu_addrcheck.scala 122:112] - wire _T_143 = start_addr_in_dccm_d & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 126:29] - wire _T_144 = _T_142 | _T_143; // @[el2_lsu_addrcheck.scala 124:85] - wire _T_145 = start_addr_pic_rangecheck_io_in_range & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 128:29] - wire unmapped_access_fault_d = _T_144 | _T_145; // @[el2_lsu_addrcheck.scala 126:85] - wire _T_147 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 130:33] - wire _T_148 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 130:64] - wire mpu_access_fault_d = _T_147 & _T_148; // @[el2_lsu_addrcheck.scala 130:62] - wire _T_150 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 142:49] - wire _T_151 = _T_150 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 142:70] - wire _T_152 = _T_151 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 142:92] - wire _T_153 = _T_152 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 142:118] - wire _T_154 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 142:141] - wire [3:0] _T_160 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 143:164] - wire [3:0] _T_161 = regpred_access_fault_d ? 4'h5 : _T_160; // @[el2_lsu_addrcheck.scala 143:120] - wire [3:0] _T_162 = mpu_access_fault_d ? 4'h3 : _T_161; // @[el2_lsu_addrcheck.scala 143:80] - wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_162; // @[el2_lsu_addrcheck.scala 143:35] - wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 144:61] - wire _T_165 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 145:59] - wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_165; // @[el2_lsu_addrcheck.scala 145:57] - wire _T_166 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 146:90] - wire _T_167 = regcross_misaligned_fault_d | _T_166; // @[el2_lsu_addrcheck.scala 146:57] - wire _T_168 = _T_167 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 146:113] - wire [3:0] _T_172 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 147:80] - wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_172; // @[el2_lsu_addrcheck.scala 147:39] - rvrangecheck rvrangecheck ( // @[el2_lsu_addrcheck.scala 45:44] - .io_addr(rvrangecheck_io_addr), - .io_in_range(rvrangecheck_io_in_range), - .io_in_region(rvrangecheck_io_in_region) - ); - rvrangecheck rvrangecheck_1 ( // @[el2_lsu_addrcheck.scala 51:44] - .io_addr(rvrangecheck_1_io_addr), - .io_in_range(rvrangecheck_1_io_in_range), - .io_in_region(rvrangecheck_1_io_in_region) - ); - rvrangecheck_2 start_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 74:41] - .io_addr(start_addr_pic_rangecheck_io_addr), - .io_in_range(start_addr_pic_rangecheck_io_in_range), - .io_in_region(start_addr_pic_rangecheck_io_in_region) - ); - rvrangecheck_2 end_addr_pic_rangecheck ( // @[el2_lsu_addrcheck.scala 80:39] - .io_addr(end_addr_pic_rangecheck_io_addr), - .io_in_range(end_addr_pic_rangecheck_io_in_range), - .io_in_region(end_addr_pic_rangecheck_io_in_region) - ); - assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 87:32] - assign io_addr_in_pic_d = start_addr_pic_rangecheck_io_in_range & end_addr_pic_rangecheck_io_in_range; // @[el2_lsu_addrcheck.scala 88:32] - assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 90:30] - assign io_access_fault_d = _T_153 & _T_154; // @[el2_lsu_addrcheck.scala 142:21] - assign io_misaligned_fault_d = _T_168 & _T_154; // @[el2_lsu_addrcheck.scala 146:25] - assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 148:21] - assign rvrangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 46:41] - assign rvrangecheck_1_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 52:41] - assign start_addr_pic_rangecheck_io_addr = io_start_addr_d; // @[el2_lsu_addrcheck.scala 75:37] - assign end_addr_pic_rangecheck_io_addr = io_end_addr_d; // @[el2_lsu_addrcheck.scala 81:35] -endmodule -module rvdff( - input clock, - input reset, - input io_din, - output io_dout -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; -`endif // RANDOMIZE_REG_INIT - reg flop; // @[beh_lib.scala 15:21] - assign io_dout = flop; // @[beh_lib.scala 20:12] + wire [31:0] _T_25 = io_dec_tlu_mrac_ff >> csr_idx; // @[el2_lsu_addrcheck.scala 61:50] + wire _T_28 = start_addr_dccm_or_pic | addr_in_iccm; // @[el2_lsu_addrcheck.scala 61:121] + wire _T_29 = ~_T_28; // @[el2_lsu_addrcheck.scala 61:62] + wire _T_30 = _T_25[0] & _T_29; // @[el2_lsu_addrcheck.scala 61:60] + wire _T_31 = _T_30 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 61:137] + wire _T_32 = io_lsu_pkt_d_store | io_lsu_pkt_d_load; // @[el2_lsu_addrcheck.scala 61:180] + wire is_sideeffects_d = _T_31 & _T_32; // @[el2_lsu_addrcheck.scala 61:158] + wire _T_34 = io_start_addr_d[1:0] == 2'h0; // @[el2_lsu_addrcheck.scala 62:75] + wire _T_35 = io_lsu_pkt_d_word & _T_34; // @[el2_lsu_addrcheck.scala 62:51] + wire _T_37 = ~io_start_addr_d[0]; // @[el2_lsu_addrcheck.scala 62:128] + wire _T_38 = io_lsu_pkt_d_half & _T_37; // @[el2_lsu_addrcheck.scala 62:106] + wire _T_39 = _T_35 | _T_38; // @[el2_lsu_addrcheck.scala 62:85] + wire is_aligned_d = _T_39 | io_lsu_pkt_d_by; // @[el2_lsu_addrcheck.scala 62:138] + wire [31:0] _T_50 = io_start_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:56] + wire _T_52 = _T_50 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 67:88] + wire [31:0] _T_55 = io_start_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 68:56] + wire _T_57 = _T_55 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 68:88] + wire _T_59 = _T_52 | _T_57; // @[el2_lsu_addrcheck.scala 67:153] + wire [31:0] _T_61 = io_start_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 69:56] + wire _T_63 = _T_61 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 69:88] + wire _T_65 = _T_59 | _T_63; // @[el2_lsu_addrcheck.scala 68:153] + wire [31:0] _T_67 = io_start_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 70:56] + wire _T_69 = _T_67 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 70:88] + wire _T_71 = _T_65 | _T_69; // @[el2_lsu_addrcheck.scala 69:153] + wire [31:0] _T_97 = io_end_addr_d | 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:57] + wire _T_99 = _T_97 == 32'h7fffffff; // @[el2_lsu_addrcheck.scala 76:89] + wire [31:0] _T_102 = io_end_addr_d | 32'h3fffffff; // @[el2_lsu_addrcheck.scala 77:58] + wire _T_104 = _T_102 == 32'hffffffff; // @[el2_lsu_addrcheck.scala 77:90] + wire _T_106 = _T_99 | _T_104; // @[el2_lsu_addrcheck.scala 76:154] + wire [31:0] _T_108 = io_end_addr_d | 32'h1fffffff; // @[el2_lsu_addrcheck.scala 78:58] + wire _T_110 = _T_108 == 32'hbfffffff; // @[el2_lsu_addrcheck.scala 78:90] + wire _T_112 = _T_106 | _T_110; // @[el2_lsu_addrcheck.scala 77:155] + wire [31:0] _T_114 = io_end_addr_d | 32'hfffffff; // @[el2_lsu_addrcheck.scala 79:58] + wire _T_116 = _T_114 == 32'h8fffffff; // @[el2_lsu_addrcheck.scala 79:90] + wire _T_118 = _T_112 | _T_116; // @[el2_lsu_addrcheck.scala 78:155] + wire non_dccm_access_ok = _T_71 & _T_118; // @[el2_lsu_addrcheck.scala 75:7] + wire regpred_access_fault_d = start_addr_dccm_or_pic ^ base_reg_dccm_or_pic; // @[el2_lsu_addrcheck.scala 85:57] + wire _T_145 = io_start_addr_d[1:0] != 2'h0; // @[el2_lsu_addrcheck.scala 86:76] + wire _T_146 = ~io_lsu_pkt_d_word; // @[el2_lsu_addrcheck.scala 86:92] + wire _T_147 = _T_145 | _T_146; // @[el2_lsu_addrcheck.scala 86:90] + wire picm_access_fault_d = io_addr_in_pic_d & _T_147; // @[el2_lsu_addrcheck.scala 86:51] + wire _T_148 = start_addr_in_dccm_d | start_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 91:87] + wire _T_149 = ~_T_148; // @[el2_lsu_addrcheck.scala 91:64] + wire _T_150 = start_addr_in_dccm_region_d & _T_149; // @[el2_lsu_addrcheck.scala 91:62] + wire _T_151 = end_addr_in_dccm_d | end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 93:57] + wire _T_152 = ~_T_151; // @[el2_lsu_addrcheck.scala 93:36] + wire _T_153 = end_addr_in_dccm_region_d & _T_152; // @[el2_lsu_addrcheck.scala 93:34] + wire _T_154 = _T_150 | _T_153; // @[el2_lsu_addrcheck.scala 91:112] + wire _T_155 = start_addr_in_dccm_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 95:29] + wire _T_156 = _T_154 | _T_155; // @[el2_lsu_addrcheck.scala 93:85] + wire _T_157 = start_addr_in_pic_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 97:29] + wire unmapped_access_fault_d = _T_156 | _T_157; // @[el2_lsu_addrcheck.scala 95:85] + wire _T_159 = ~start_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 99:33] + wire _T_160 = ~non_dccm_access_ok; // @[el2_lsu_addrcheck.scala 99:64] + wire mpu_access_fault_d = _T_159 & _T_160; // @[el2_lsu_addrcheck.scala 99:62] + wire _T_162 = unmapped_access_fault_d | mpu_access_fault_d; // @[el2_lsu_addrcheck.scala 111:49] + wire _T_163 = _T_162 | picm_access_fault_d; // @[el2_lsu_addrcheck.scala 111:70] + wire _T_164 = _T_163 | regpred_access_fault_d; // @[el2_lsu_addrcheck.scala 111:92] + wire _T_165 = _T_164 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 111:118] + wire _T_166 = ~io_lsu_pkt_d_dma; // @[el2_lsu_addrcheck.scala 111:141] + wire [3:0] _T_172 = picm_access_fault_d ? 4'h6 : 4'h0; // @[el2_lsu_addrcheck.scala 112:164] + wire [3:0] _T_173 = regpred_access_fault_d ? 4'h5 : _T_172; // @[el2_lsu_addrcheck.scala 112:120] + wire [3:0] _T_174 = mpu_access_fault_d ? 4'h3 : _T_173; // @[el2_lsu_addrcheck.scala 112:80] + wire [3:0] access_fault_mscause_d = unmapped_access_fault_d ? 4'h2 : _T_174; // @[el2_lsu_addrcheck.scala 112:35] + wire regcross_misaligned_fault_d = io_start_addr_d[31:28] != io_end_addr_d[31:28]; // @[el2_lsu_addrcheck.scala 113:61] + wire _T_177 = ~is_aligned_d; // @[el2_lsu_addrcheck.scala 114:59] + wire sideeffect_misaligned_fault_d = is_sideeffects_d & _T_177; // @[el2_lsu_addrcheck.scala 114:57] + wire _T_178 = sideeffect_misaligned_fault_d & io_addr_external_d; // @[el2_lsu_addrcheck.scala 115:90] + wire _T_179 = regcross_misaligned_fault_d | _T_178; // @[el2_lsu_addrcheck.scala 115:57] + wire _T_180 = _T_179 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 115:113] + wire [3:0] _T_184 = sideeffect_misaligned_fault_d ? 4'h1 : 4'h0; // @[el2_lsu_addrcheck.scala 116:80] + wire [3:0] misaligned_fault_mscause_d = regcross_misaligned_fault_d ? 4'h2 : _T_184; // @[el2_lsu_addrcheck.scala 116:39] + wire _T_189 = ~start_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:66] + wire _T_190 = start_addr_in_dccm_region_d & _T_189; // @[el2_lsu_addrcheck.scala 118:64] + wire _T_191 = ~end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 118:120] + wire _T_192 = end_addr_in_dccm_region_d & _T_191; // @[el2_lsu_addrcheck.scala 118:118] + wire _T_193 = _T_190 | _T_192; // @[el2_lsu_addrcheck.scala 118:88] + wire _T_194 = _T_193 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 118:142] + wire _T_196 = start_addr_in_dccm_region_d & end_addr_in_dccm_region_d; // @[el2_lsu_addrcheck.scala 119:66] + wire _T_197 = ~_T_196; // @[el2_lsu_addrcheck.scala 119:36] + wire _T_198 = _T_197 & io_lsu_pkt_d_valid; // @[el2_lsu_addrcheck.scala 119:95] + reg _T_200; // @[el2_lsu_addrcheck.scala 121:60] + assign io_is_sideeffects_m = _T_200; // @[el2_lsu_addrcheck.scala 121:50] + assign io_addr_in_dccm_d = start_addr_in_dccm_d & end_addr_in_dccm_d; // @[el2_lsu_addrcheck.scala 56:32] + assign io_addr_in_pic_d = start_addr_in_pic_d & end_addr_in_pic_d; // @[el2_lsu_addrcheck.scala 57:32] + assign io_addr_external_d = ~start_addr_dccm_or_pic; // @[el2_lsu_addrcheck.scala 59:30] + assign io_access_fault_d = _T_165 & _T_166; // @[el2_lsu_addrcheck.scala 111:21] + assign io_misaligned_fault_d = _T_180 & _T_166; // @[el2_lsu_addrcheck.scala 115:25] + assign io_exc_mscause_d = io_misaligned_fault_d ? misaligned_fault_mscause_d : access_fault_mscause_d; // @[el2_lsu_addrcheck.scala 117:21] + assign io_fir_dccm_access_error_d = _T_194 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 118:31] + assign io_fir_nondccm_access_error_d = _T_198 & io_lsu_pkt_d_fast_int; // @[el2_lsu_addrcheck.scala 119:33] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -230,10 +164,10 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - flop = _RAND_0[0:0]; + _T_200 = _RAND_0[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - flop = 1'h0; + _T_200 = 1'h0; end `endif // RANDOMIZE end // initial @@ -241,149 +175,21 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_c2_m_clk or posedge reset) begin if (reset) begin - flop <= 1'h0; + _T_200 <= 1'h0; end else begin - flop <= io_din; - end - end -endmodule -module rvdff_2( - input clock, - input reset, - input [3:0] io_din, - output [3:0] io_dout -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; -`endif // RANDOMIZE_REG_INIT - reg [3:0] flop; // @[beh_lib.scala 15:21] - assign io_dout = flop; // @[beh_lib.scala 20:12] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - flop = _RAND_0[3:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - flop = 4'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge clock or posedge reset) begin - if (reset) begin - flop <= 4'h0; - end else begin - flop <= io_din; - end - end -endmodule -module rvdff_6( - input clock, - input reset, - input [31:0] io_din, - output [31:0] io_dout -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; -`endif // RANDOMIZE_REG_INIT - reg [31:0] flop; // @[beh_lib.scala 15:21] - assign io_dout = flop; // @[beh_lib.scala 20:12] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - flop = _RAND_0[31:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - flop = 32'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge clock or posedge reset) begin - if (reset) begin - flop <= 32'h0; - end else begin - flop <= io_din; + _T_200 <= _T_31 & _T_32; end end endmodule module el2_lsu_lsc_ctl( - input clock, input reset, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_m_clk, + input io_lsu_c2_r_clk, + input io_lsu_store_c1_m_clk, input [31:0] io_lsu_ld_data_corr_r, input io_lsu_single_ecc_error_r, input io_lsu_double_ecc_error_r, @@ -410,7 +216,9 @@ module el2_lsu_lsc_ctl( input io_dec_lsu_valid_raw_d, input [11:0] io_dec_lsu_offset_d, input [31:0] io_picm_mask_data_m, + input [31:0] io_bus_read_data_m, output [31:0] io_lsu_result_m, + output [31:0] io_lsu_result_corr_r, output [31:0] io_lsu_addr_d, output [31:0] io_lsu_addr_m, output [31:0] io_lsu_addr_r, @@ -419,15 +227,18 @@ module el2_lsu_lsc_ctl( output [31:0] io_end_addr_r, output [31:0] io_store_data_m, input [31:0] io_dec_tlu_mrac_ff, + output io_lsu_exc_m, + output io_is_sideeffects_m, output io_lsu_commit_r, output io_lsu_single_ecc_error_incr, output io_lsu_error_pkt_r_exc_valid, output io_lsu_error_pkt_r_single_ecc_error, output io_lsu_error_pkt_r_inst_type, output io_lsu_error_pkt_r_exc_type, - output [3:0] io_lsu_error_pkt_r_mscause, - output [31:0] io_lsu_error_pkt_r_addr, - output [31:0] io_lsu_fir_addr, + output io_lsu_error_pkt_r_mscause, + output io_lsu_error_pkt_r_addr, + output [30:0] io_lsu_fir_addr, + output [1:0] io_lsu_fir_error, output io_addr_in_dccm_d, output io_addr_in_dccm_m, output io_addr_in_dccm_r, @@ -501,221 +312,230 @@ module el2_lsu_lsc_ctl( reg [31:0] _RAND_23; reg [31:0] _RAND_24; reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; `endif // RANDOMIZE_REG_INIT - wire [31:0] lsadder_io_rs1; // @[el2_lsu_lsc_ctl.scala 118:23] - wire [11:0] lsadder_io_offset; // @[el2_lsu_lsc_ctl.scala 118:23] - wire [31:0] lsadder_io_dout; // @[el2_lsu_lsc_ctl.scala 118:23] - wire [31:0] addrcheck_io_start_addr_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire [31:0] addrcheck_io_end_addr_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 141:25] - wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 141:25] - wire [3:0] addrcheck_io_rs1_region_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_addr_external_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_access_fault_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire addrcheck_io_misaligned_fault_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire [3:0] addrcheck_io_exc_mscause_d; // @[el2_lsu_lsc_ctl.scala 141:25] - wire access_fault_mff_clock; // @[el2_lsu_lsc_ctl.scala 169:45] - wire access_fault_mff_reset; // @[el2_lsu_lsc_ctl.scala 169:45] - wire access_fault_mff_io_din; // @[el2_lsu_lsc_ctl.scala 169:45] - wire access_fault_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 169:45] - wire misaligned_fault_mff_clock; // @[el2_lsu_lsc_ctl.scala 171:45] - wire misaligned_fault_mff_reset; // @[el2_lsu_lsc_ctl.scala 171:45] - wire misaligned_fault_mff_io_din; // @[el2_lsu_lsc_ctl.scala 171:45] - wire misaligned_fault_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 171:45] - wire exc_mscause_mff_clock; // @[el2_lsu_lsc_ctl.scala 173:45] - wire exc_mscause_mff_reset; // @[el2_lsu_lsc_ctl.scala 173:45] - wire [3:0] exc_mscause_mff_io_din; // @[el2_lsu_lsc_ctl.scala 173:45] - wire [3:0] exc_mscause_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 173:45] - wire lsu_pkt_vldmff_clock; // @[el2_lsu_lsc_ctl.scala 278:36] - wire lsu_pkt_vldmff_reset; // @[el2_lsu_lsc_ctl.scala 278:36] - wire lsu_pkt_vldmff_io_din; // @[el2_lsu_lsc_ctl.scala 278:36] - wire lsu_pkt_vldmff_io_dout; // @[el2_lsu_lsc_ctl.scala 278:36] - wire lsu_pkt_vldrff_clock; // @[el2_lsu_lsc_ctl.scala 279:36] - wire lsu_pkt_vldrff_reset; // @[el2_lsu_lsc_ctl.scala 279:36] - wire lsu_pkt_vldrff_io_din; // @[el2_lsu_lsc_ctl.scala 279:36] - wire lsu_pkt_vldrff_io_dout; // @[el2_lsu_lsc_ctl.scala 279:36] - wire sdmff_clock; // @[el2_lsu_lsc_ctl.scala 333:20] - wire sdmff_reset; // @[el2_lsu_lsc_ctl.scala 333:20] - wire [31:0] sdmff_io_din; // @[el2_lsu_lsc_ctl.scala 333:20] - wire [31:0] sdmff_io_dout; // @[el2_lsu_lsc_ctl.scala 333:20] - wire samff_clock; // @[el2_lsu_lsc_ctl.scala 337:20] - wire samff_reset; // @[el2_lsu_lsc_ctl.scala 337:20] - wire [31:0] samff_io_din; // @[el2_lsu_lsc_ctl.scala 337:20] - wire [31:0] samff_io_dout; // @[el2_lsu_lsc_ctl.scala 337:20] - wire sarff_clock; // @[el2_lsu_lsc_ctl.scala 341:20] - wire sarff_reset; // @[el2_lsu_lsc_ctl.scala 341:20] - wire [31:0] sarff_io_din; // @[el2_lsu_lsc_ctl.scala 341:20] - wire [31:0] sarff_io_dout; // @[el2_lsu_lsc_ctl.scala 341:20] - wire end_addr_mff_clock; // @[el2_lsu_lsc_ctl.scala 345:28] - wire end_addr_mff_reset; // @[el2_lsu_lsc_ctl.scala 345:28] - wire [31:0] end_addr_mff_io_din; // @[el2_lsu_lsc_ctl.scala 345:28] - wire [31:0] end_addr_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 345:28] - wire end_addr_rff_clock; // @[el2_lsu_lsc_ctl.scala 349:28] - wire end_addr_rff_reset; // @[el2_lsu_lsc_ctl.scala 349:28] - wire [31:0] end_addr_rff_io_din; // @[el2_lsu_lsc_ctl.scala 349:28] - wire [31:0] end_addr_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 349:28] - wire addr_in_dccm_mff_clock; // @[el2_lsu_lsc_ctl.scala 353:36] - wire addr_in_dccm_mff_reset; // @[el2_lsu_lsc_ctl.scala 353:36] - wire addr_in_dccm_mff_io_din; // @[el2_lsu_lsc_ctl.scala 353:36] - wire addr_in_dccm_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 353:36] - wire addr_in_dccm_rff_clock; // @[el2_lsu_lsc_ctl.scala 357:37] - wire addr_in_dccm_rff_reset; // @[el2_lsu_lsc_ctl.scala 357:37] - wire addr_in_dccm_rff_io_din; // @[el2_lsu_lsc_ctl.scala 357:37] - wire addr_in_dccm_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 357:37] - wire addr_in_pic_mff_clock; // @[el2_lsu_lsc_ctl.scala 361:37] - wire addr_in_pic_mff_reset; // @[el2_lsu_lsc_ctl.scala 361:37] - wire addr_in_pic_mff_io_din; // @[el2_lsu_lsc_ctl.scala 361:37] - wire addr_in_pic_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 361:37] - wire addr_in_pic_rff_clock; // @[el2_lsu_lsc_ctl.scala 365:37] - wire addr_in_pic_rff_reset; // @[el2_lsu_lsc_ctl.scala 365:37] - wire addr_in_pic_rff_io_din; // @[el2_lsu_lsc_ctl.scala 365:37] - wire addr_in_pic_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 365:37] - wire addr_external_mff_clock; // @[el2_lsu_lsc_ctl.scala 369:37] - wire addr_external_mff_reset; // @[el2_lsu_lsc_ctl.scala 369:37] - wire addr_external_mff_io_din; // @[el2_lsu_lsc_ctl.scala 369:37] - wire addr_external_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 369:37] - wire addr_external_rff_clock; // @[el2_lsu_lsc_ctl.scala 373:37] - wire addr_external_rff_reset; // @[el2_lsu_lsc_ctl.scala 373:37] - wire addr_external_rff_io_din; // @[el2_lsu_lsc_ctl.scala 373:37] - wire addr_external_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 373:37] - wire bus_read_data_r_ff_clock; // @[el2_lsu_lsc_ctl.scala 377:38] - wire bus_read_data_r_ff_reset; // @[el2_lsu_lsc_ctl.scala 377:38] - wire [31:0] bus_read_data_r_ff_io_din; // @[el2_lsu_lsc_ctl.scala 377:38] - wire [31:0] bus_read_data_r_ff_io_dout; // @[el2_lsu_lsc_ctl.scala 377:38] - wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_exu_lsu_rs1_d : io_dma_mem_addr; // @[el2_lsu_lsc_ctl.scala 108:28] + wire addrcheck_reset; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [31:0] addrcheck_io_start_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [31:0] addrcheck_io_end_addr_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_fast_int; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [31:0] addrcheck_io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [3:0] addrcheck_io_rs1_region_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_addr_external_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_access_fault_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_misaligned_fault_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [3:0] addrcheck_io_exc_mscause_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_fir_dccm_access_error_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire addrcheck_io_fir_nondccm_access_error_d; // @[el2_lsu_lsc_ctl.scala 119:25] + wire [31:0] lsu_rs1_d = io_dec_lsu_valid_raw_d ? io_exu_lsu_rs1_d : io_dma_mem_addr; // @[el2_lsu_lsc_ctl.scala 101:28] wire [11:0] _T_3 = io_dec_lsu_valid_raw_d ? 12'hfff : 12'h0; // @[Bitwise.scala 72:12] - wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[el2_lsu_lsc_ctl.scala 109:51] - wire [31:0] rs1_d = io_lsu_pkt_d_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 114:18] - wire [2:0] _T_6 = io_lsu_pkt_d_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_7 = _T_6 & 3'h1; // @[el2_lsu_lsc_ctl.scala 127:53] - wire [2:0] _T_9 = io_lsu_pkt_d_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] _T_10 = _T_9 & 3'h3; // @[el2_lsu_lsc_ctl.scala 128:35] - wire [2:0] _T_11 = _T_7 | _T_10; // @[el2_lsu_lsc_ctl.scala 127:65] - wire [2:0] _T_13 = io_lsu_pkt_d_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] - wire [2:0] addr_offset_d = _T_11 | _T_13; // @[el2_lsu_lsc_ctl.scala 128:47] - wire [12:0] _T_17 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] - wire [11:0] _T_20 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] - wire [12:0] _GEN_0 = {{1'd0}, _T_20}; // @[el2_lsu_lsc_ctl.scala 131:60] - wire [12:0] end_addr_offset_d = _T_17 + _GEN_0; // @[el2_lsu_lsc_ctl.scala 131:60] - wire [18:0] _T_25 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_27 = {_T_25,end_addr_offset_d}; // @[Cat.scala 29:58] - wire access_fault_m = access_fault_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 247:40] - wire misaligned_fault_m = misaligned_fault_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 250:40] - wire _T_30 = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 188:34] - wire _T_31 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_lsc_ctl.scala 189:64] - wire _T_32 = io_lsu_single_ecc_error_r & _T_31; // @[el2_lsu_lsc_ctl.scala 189:62] - wire _T_33 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 189:111] - wire _T_34 = _T_32 & _T_33; // @[el2_lsu_lsc_ctl.scala 189:92] - wire _T_37 = _T_30 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 230:71] - wire _T_38 = _T_37 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 230:100] - wire _T_39 = ~io_lsu_pkt_m_dma; // @[el2_lsu_lsc_ctl.scala 230:123] - wire _T_40 = _T_38 & _T_39; // @[el2_lsu_lsc_ctl.scala 230:121] - wire _T_41 = ~io_lsu_pkt_m_fast_int; // @[el2_lsu_lsc_ctl.scala 230:143] - wire _T_42 = _T_40 & _T_41; // @[el2_lsu_lsc_ctl.scala 230:141] - wire _T_43 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 230:168] - wire lsu_error_pkt_m_exc_valid = _T_42 & _T_43; // @[el2_lsu_lsc_ctl.scala 230:166] - wire _T_45 = ~lsu_error_pkt_m_exc_valid; // @[el2_lsu_lsc_ctl.scala 231:70] - wire _T_46 = io_lsu_single_ecc_error_m & _T_45; // @[el2_lsu_lsc_ctl.scala 231:68] - wire lsu_error_pkt_m_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 233:41] - wire _T_51 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_exc_type; // @[el2_lsu_lsc_ctl.scala 234:72] - wire _T_52 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 234:96] - wire _T_53 = _T_51 & _T_52; // @[el2_lsu_lsc_ctl.scala 234:94] - wire [3:0] exc_mscause_m = exc_mscause_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 253:40] - reg _T_65_exc_valid; // @[el2_lsu_lsc_ctl.scala 241:34] - reg _T_65_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 241:34] - reg _T_65_inst_type; // @[el2_lsu_lsc_ctl.scala 241:34] - reg _T_65_exc_type; // @[el2_lsu_lsc_ctl.scala 241:34] - reg [3:0] _T_65_mscause; // @[el2_lsu_lsc_ctl.scala 241:34] - reg [31:0] _T_65_addr; // @[el2_lsu_lsc_ctl.scala 241:34] - wire dma_pkt_d_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 268:25] - wire dma_pkt_d_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 269:45] - wire dma_pkt_d_half = io_dma_mem_sz == 3'h1; // @[el2_lsu_lsc_ctl.scala 270:45] - wire dma_pkt_d_word = io_dma_mem_sz == 3'h2; // @[el2_lsu_lsc_ctl.scala 271:45] - wire dma_pkt_d_dword = io_dma_mem_sz == 3'h3; // @[el2_lsu_lsc_ctl.scala 272:45] - wire _T_79 = ~io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 289:64] - wire _T_80 = io_flush_m_up & _T_79; // @[el2_lsu_lsc_ctl.scala 289:61] - wire _T_81 = ~_T_80; // @[el2_lsu_lsc_ctl.scala 289:45] - wire _T_82 = io_lsu_p_valid & _T_81; // @[el2_lsu_lsc_ctl.scala 289:43] - wire _T_84 = ~io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 290:68] - wire _T_85 = io_flush_m_up & _T_84; // @[el2_lsu_lsc_ctl.scala 290:65] - wire _T_86 = ~_T_85; // @[el2_lsu_lsc_ctl.scala 290:49] - wire _T_89 = io_flush_m_up & _T_39; // @[el2_lsu_lsc_ctl.scala 291:65] - wire _T_90 = ~_T_89; // @[el2_lsu_lsc_ctl.scala 291:49] - reg _T_92_fast_int; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_by; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_half; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_word; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_dword; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_load; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_store; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_unsign; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_dma; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_92_valid; // @[el2_lsu_lsc_ctl.scala 305:26] - reg _T_93_by; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_half; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_word; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_dword; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_load; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_store; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_unsign; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_dma; // @[el2_lsu_lsc_ctl.scala 310:26] - reg _T_93_valid; // @[el2_lsu_lsc_ctl.scala 310:26] - wire [3:0] _T_96 = {io_dma_mem_addr[2:0],1'h0}; // @[Cat.scala 29:58] - wire [63:0] dma_mem_wdata_shifted = io_dma_mem_wdata >> _T_96; // @[el2_lsu_lsc_ctl.scala 326:54] - wire [31:0] store_data_d = io_dma_dccm_req ? dma_mem_wdata_shifted[31:0] : io_exu_lsu_rs2_d; // @[el2_lsu_lsc_ctl.scala 328:34] - wire _T_104 = io_lsu_pkt_r_store | io_lsu_pkt_r_load; // @[el2_lsu_lsc_ctl.scala 391:63] - wire _T_105 = io_lsu_pkt_r_valid & _T_104; // @[el2_lsu_lsc_ctl.scala 391:41] - wire _T_106 = ~io_flush_r; // @[el2_lsu_lsc_ctl.scala 391:86] - wire _T_107 = _T_105 & _T_106; // @[el2_lsu_lsc_ctl.scala 391:84] - wire _T_108 = ~io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 391:100] - wire _T_111 = ~io_addr_in_pic_m; // @[el2_lsu_lsc_ctl.scala 394:69] - wire [31:0] _T_113 = _T_111 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_114 = io_picm_mask_data_m | _T_113; // @[el2_lsu_lsc_ctl.scala 394:59] - wire [31:0] _T_116 = io_lsu_pkt_m_store_data_bypass_m ? io_lsu_result_m : sdmff_io_dout; // @[el2_lsu_lsc_ctl.scala 394:94] - wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? 32'h0 : io_lsu_ld_data_m; // @[el2_lsu_lsc_ctl.scala 425:33] - wire _T_122 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 429:61] - wire [31:0] _T_124 = _T_122 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [8:0] _T_126 = {1'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _GEN_1 = {{23'd0}, _T_126}; // @[el2_lsu_lsc_ctl.scala 429:84] - wire [31:0] _T_127 = _T_124 & _GEN_1; // @[el2_lsu_lsc_ctl.scala 429:84] - wire _T_128 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 430:38] - wire [31:0] _T_130 = _T_128 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [16:0] _T_132 = {1'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _GEN_2 = {{15'd0}, _T_132}; // @[el2_lsu_lsc_ctl.scala 430:61] - wire [31:0] _T_133 = _T_130 & _GEN_2; // @[el2_lsu_lsc_ctl.scala 430:61] - wire [31:0] _T_134 = _T_127 | _T_133; // @[el2_lsu_lsc_ctl.scala 429:125] - wire _T_135 = ~io_lsu_pkt_r_unsign; // @[el2_lsu_lsc_ctl.scala 431:17] - wire _T_136 = _T_135 & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 431:38] - wire [31:0] _T_138 = _T_136 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [23:0] _T_141 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_143 = {_T_141,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_144 = _T_138 & _T_143; // @[el2_lsu_lsc_ctl.scala 431:61] - wire [31:0] _T_145 = _T_134 | _T_144; // @[el2_lsu_lsc_ctl.scala 430:104] - wire _T_147 = _T_135 & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 432:38] - wire [31:0] _T_149 = _T_147 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [15:0] _T_152 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_154 = {_T_152,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] - wire [31:0] _T_155 = _T_149 & _T_154; // @[el2_lsu_lsc_ctl.scala 432:61] - wire [31:0] _T_156 = _T_145 | _T_155; // @[el2_lsu_lsc_ctl.scala 431:124] - wire [31:0] _T_158 = io_lsu_pkt_r_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_160 = _T_158 & lsu_ld_datafn_m; // @[el2_lsu_lsc_ctl.scala 433:38] - rvlsadder lsadder ( // @[el2_lsu_lsc_ctl.scala 118:23] - .io_rs1(lsadder_io_rs1), - .io_offset(lsadder_io_offset), - .io_dout(lsadder_io_dout) - ); - el2_lsu_addrcheck addrcheck ( // @[el2_lsu_lsc_ctl.scala 141:25] + wire [11:0] lsu_offset_d = io_dec_lsu_offset_d & _T_3; // @[el2_lsu_lsc_ctl.scala 102:51] + wire [31:0] rs1_d = io_lsu_pkt_d_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 105:28] + wire [12:0] _T_6 = {1'h0,rs1_d[11:0]}; // @[Cat.scala 29:58] + wire [12:0] _T_8 = {1'h0,lsu_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _T_10 = _T_6 + _T_8; // @[el2_lib.scala 232:39] + wire _T_13 = lsu_offset_d[11] ^ _T_10[12]; // @[el2_lib.scala 233:46] + wire _T_14 = ~_T_13; // @[el2_lib.scala 233:33] + wire [19:0] _T_16 = _T_14 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_18 = _T_16 & rs1_d[31:12]; // @[el2_lib.scala 233:58] + wire _T_20 = ~lsu_offset_d[11]; // @[el2_lib.scala 234:18] + wire _T_22 = _T_20 & _T_10[12]; // @[el2_lib.scala 234:30] + wire [19:0] _T_24 = _T_22 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_27 = rs1_d[31:12] + 20'h1; // @[el2_lib.scala 234:54] + wire [19:0] _T_28 = _T_24 & _T_27; // @[el2_lib.scala 234:41] + wire [19:0] _T_29 = _T_18 | _T_28; // @[el2_lib.scala 233:72] + wire _T_32 = ~_T_10[12]; // @[el2_lib.scala 235:31] + wire _T_33 = lsu_offset_d[11] & _T_32; // @[el2_lib.scala 235:29] + wire [19:0] _T_35 = _T_33 ? 20'hfffff : 20'h0; // @[Bitwise.scala 72:12] + wire [19:0] _T_38 = rs1_d[31:12] - 20'h1; // @[el2_lib.scala 235:54] + wire [19:0] _T_39 = _T_35 & _T_38; // @[el2_lib.scala 235:41] + wire [19:0] _T_40 = _T_29 | _T_39; // @[el2_lib.scala 234:61] + wire [2:0] _T_43 = io_lsu_pkt_d_half ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_44 = _T_43 & 3'h1; // @[el2_lsu_lsc_ctl.scala 110:53] + wire [2:0] _T_46 = io_lsu_pkt_d_word ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_47 = _T_46 & 3'h3; // @[el2_lsu_lsc_ctl.scala 111:35] + wire [2:0] _T_48 = _T_44 | _T_47; // @[el2_lsu_lsc_ctl.scala 110:65] + wire [2:0] _T_50 = io_lsu_pkt_d_dword ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] addr_offset_d = _T_48 | _T_50; // @[el2_lsu_lsc_ctl.scala 111:47] + wire [12:0] _T_54 = {lsu_offset_d[11],lsu_offset_d}; // @[Cat.scala 29:58] + wire [11:0] _T_57 = {9'h0,addr_offset_d}; // @[Cat.scala 29:58] + wire [12:0] _GEN_0 = {{1'd0}, _T_57}; // @[el2_lsu_lsc_ctl.scala 114:60] + wire [12:0] end_addr_offset_d = _T_54 + _GEN_0; // @[el2_lsu_lsc_ctl.scala 114:60] + wire [18:0] _T_62 = end_addr_offset_d[12] ? 19'h7ffff : 19'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_64 = {_T_62,end_addr_offset_d}; // @[Cat.scala 29:58] + reg access_fault_m; // @[el2_lsu_lsc_ctl.scala 150:75] + reg misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 151:75] + reg [3:0] exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 152:75] + reg fir_dccm_access_error_m; // @[el2_lsu_lsc_ctl.scala 153:75] + reg fir_nondccm_access_error_m; // @[el2_lsu_lsc_ctl.scala 154:75] + wire _T_69 = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:34] + wire _T_70 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_lsc_ctl.scala 157:64] + wire _T_71 = io_lsu_single_ecc_error_r & _T_70; // @[el2_lsu_lsc_ctl.scala 157:62] + wire _T_72 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 157:111] + wire _T_73 = _T_71 & _T_72; // @[el2_lsu_lsc_ctl.scala 157:92] + wire _T_76 = _T_69 | io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 179:71] + wire _T_77 = _T_76 & io_lsu_pkt_m_valid; // @[el2_lsu_lsc_ctl.scala 179:100] + wire _T_78 = ~io_lsu_pkt_m_dma; // @[el2_lsu_lsc_ctl.scala 179:123] + wire _T_79 = _T_77 & _T_78; // @[el2_lsu_lsc_ctl.scala 179:121] + wire _T_80 = ~io_lsu_pkt_m_fast_int; // @[el2_lsu_lsc_ctl.scala 179:143] + wire _T_81 = _T_79 & _T_80; // @[el2_lsu_lsc_ctl.scala 179:141] + wire _T_82 = ~io_flush_m_up; // @[el2_lsu_lsc_ctl.scala 179:168] + wire lsu_error_pkt_m_exc_valid = _T_81 & _T_82; // @[el2_lsu_lsc_ctl.scala 179:166] + wire _T_84 = ~lsu_error_pkt_m_exc_valid; // @[el2_lsu_lsc_ctl.scala 180:70] + wire _T_85 = io_lsu_single_ecc_error_m & _T_84; // @[el2_lsu_lsc_ctl.scala 180:68] + wire lsu_error_pkt_m_exc_type = ~misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 182:41] + wire _T_90 = io_lsu_double_ecc_error_m & lsu_error_pkt_m_exc_type; // @[el2_lsu_lsc_ctl.scala 183:73] + wire _T_91 = ~access_fault_m; // @[el2_lsu_lsc_ctl.scala 183:97] + wire _T_92 = _T_90 & _T_91; // @[el2_lsu_lsc_ctl.scala 183:95] + wire [3:0] _T_95 = _T_92 ? 4'h1 : exc_mscause_m; // @[el2_lsu_lsc_ctl.scala 183:44] + wire _T_99 = io_lsu_pkt_m_fast_int & io_lsu_double_ecc_error_m; // @[el2_lsu_lsc_ctl.scala 185:161] + reg _T_105_exc_valid; // @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105_inst_type; // @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105_exc_type; // @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105_mscause; // @[el2_lsu_lsc_ctl.scala 186:75] + reg _T_105_addr; // @[el2_lsu_lsc_ctl.scala 186:75] + reg [1:0] _T_106; // @[el2_lsu_lsc_ctl.scala 187:75] + wire dma_pkt_d_load = ~io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 194:25] + wire dma_pkt_d_by = io_dma_mem_sz == 3'h0; // @[el2_lsu_lsc_ctl.scala 195:45] + wire dma_pkt_d_half = io_dma_mem_sz == 3'h1; // @[el2_lsu_lsc_ctl.scala 196:45] + wire dma_pkt_d_word = io_dma_mem_sz == 3'h2; // @[el2_lsu_lsc_ctl.scala 197:45] + wire dma_pkt_d_dword = io_dma_mem_sz == 3'h3; // @[el2_lsu_lsc_ctl.scala 198:45] + wire _T_118 = ~io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 211:64] + wire _T_119 = io_flush_m_up & _T_118; // @[el2_lsu_lsc_ctl.scala 211:61] + wire _T_120 = ~_T_119; // @[el2_lsu_lsc_ctl.scala 211:45] + wire _T_121 = io_lsu_p_valid & _T_120; // @[el2_lsu_lsc_ctl.scala 211:43] + wire _T_123 = ~io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 212:68] + wire _T_124 = io_flush_m_up & _T_123; // @[el2_lsu_lsc_ctl.scala 212:65] + wire _T_125 = ~_T_124; // @[el2_lsu_lsc_ctl.scala 212:49] + wire _T_128 = io_flush_m_up & _T_78; // @[el2_lsu_lsc_ctl.scala 213:65] + wire _T_129 = ~_T_128; // @[el2_lsu_lsc_ctl.scala 213:49] + reg _T_132_fast_int; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_by; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_half; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_word; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_dword; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_load; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_store; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_unsign; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_dma; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_132_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:65] + reg _T_134_by; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_half; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_word; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_dword; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_load; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_store; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_unsign; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_134_dma; // @[el2_lsu_lsc_ctl.scala 216:65] + reg _T_135; // @[el2_lsu_lsc_ctl.scala 217:65] + reg _T_136; // @[el2_lsu_lsc_ctl.scala 218:65] + wire [5:0] _T_139 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] + wire [63:0] dma_mem_wdata_shifted = io_dma_mem_wdata >> _T_139; // @[el2_lsu_lsc_ctl.scala 220:54] + reg [31:0] store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 224:72] + reg [31:0] _T_146; // @[el2_lsu_lsc_ctl.scala 225:62] + reg [31:0] _T_147; // @[el2_lsu_lsc_ctl.scala 226:62] + reg [31:0] _T_148; // @[el2_lsu_lsc_ctl.scala 227:62] + reg [31:0] _T_149; // @[el2_lsu_lsc_ctl.scala 228:62] + reg _T_150; // @[el2_lsu_lsc_ctl.scala 229:62] + reg _T_151; // @[el2_lsu_lsc_ctl.scala 230:62] + reg _T_152; // @[el2_lsu_lsc_ctl.scala 231:62] + reg _T_153; // @[el2_lsu_lsc_ctl.scala 232:62] + reg _T_154; // @[el2_lsu_lsc_ctl.scala 233:62] + reg addr_external_r; // @[el2_lsu_lsc_ctl.scala 234:66] + reg [31:0] bus_read_data_r; // @[el2_lsu_lsc_ctl.scala 235:66] + wire _T_156 = io_lsu_pkt_r_store | io_lsu_pkt_r_load; // @[el2_lsu_lsc_ctl.scala 241:63] + wire _T_157 = io_lsu_pkt_r_valid & _T_156; // @[el2_lsu_lsc_ctl.scala 241:41] + wire _T_158 = ~io_flush_r; // @[el2_lsu_lsc_ctl.scala 241:86] + wire _T_159 = _T_157 & _T_158; // @[el2_lsu_lsc_ctl.scala 241:84] + wire _T_160 = ~io_lsu_pkt_r_dma; // @[el2_lsu_lsc_ctl.scala 241:100] + wire _T_163 = ~io_addr_in_pic_m; // @[el2_lsu_lsc_ctl.scala 242:69] + wire [31:0] _T_165 = _T_163 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_166 = io_picm_mask_data_m | _T_165; // @[el2_lsu_lsc_ctl.scala 242:59] + wire [31:0] _T_168 = io_lsu_pkt_m_store_data_bypass_m ? io_lsu_result_m : store_data_pre_m; // @[el2_lsu_lsc_ctl.scala 242:94] + wire [31:0] lsu_ld_datafn_m = io_addr_external_m ? io_bus_read_data_m : io_lsu_ld_data_m; // @[el2_lsu_lsc_ctl.scala 263:33] + wire [31:0] lsu_ld_datafn_corr_r = addr_external_r ? bus_read_data_r : io_lsu_ld_data_corr_r; // @[el2_lsu_lsc_ctl.scala 264:33] + wire _T_174 = io_lsu_pkt_m_unsign & io_lsu_pkt_m_by; // @[el2_lsu_lsc_ctl.scala 265:61] + wire [31:0] _T_176 = _T_174 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_178 = {24'h0,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_179 = _T_176 & _T_178; // @[el2_lsu_lsc_ctl.scala 265:84] + wire _T_180 = io_lsu_pkt_m_unsign & io_lsu_pkt_m_half; // @[el2_lsu_lsc_ctl.scala 266:38] + wire [31:0] _T_182 = _T_180 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_184 = {16'h0,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_185 = _T_182 & _T_184; // @[el2_lsu_lsc_ctl.scala 266:61] + wire [31:0] _T_186 = _T_179 | _T_185; // @[el2_lsu_lsc_ctl.scala 265:123] + wire _T_187 = ~io_lsu_pkt_m_unsign; // @[el2_lsu_lsc_ctl.scala 267:17] + wire _T_188 = _T_187 & io_lsu_pkt_m_by; // @[el2_lsu_lsc_ctl.scala 267:38] + wire [31:0] _T_190 = _T_188 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_193 = lsu_ld_datafn_m[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_195 = {_T_193,lsu_ld_datafn_m[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_196 = _T_190 & _T_195; // @[el2_lsu_lsc_ctl.scala 267:61] + wire [31:0] _T_197 = _T_186 | _T_196; // @[el2_lsu_lsc_ctl.scala 266:104] + wire _T_199 = _T_187 & io_lsu_pkt_m_half; // @[el2_lsu_lsc_ctl.scala 268:38] + wire [31:0] _T_201 = _T_199 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_204 = lsu_ld_datafn_m[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_206 = {_T_204,lsu_ld_datafn_m[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_207 = _T_201 & _T_206; // @[el2_lsu_lsc_ctl.scala 268:61] + wire [31:0] _T_208 = _T_197 | _T_207; // @[el2_lsu_lsc_ctl.scala 267:124] + wire [31:0] _T_210 = io_lsu_pkt_m_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_212 = _T_210 & lsu_ld_datafn_m; // @[el2_lsu_lsc_ctl.scala 269:38] + wire _T_214 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 270:61] + wire [31:0] _T_216 = _T_214 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_218 = {24'h0,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_219 = _T_216 & _T_218; // @[el2_lsu_lsc_ctl.scala 270:84] + wire _T_220 = io_lsu_pkt_r_unsign & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 271:38] + wire [31:0] _T_222 = _T_220 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_224 = {16'h0,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_225 = _T_222 & _T_224; // @[el2_lsu_lsc_ctl.scala 271:61] + wire [31:0] _T_226 = _T_219 | _T_225; // @[el2_lsu_lsc_ctl.scala 270:128] + wire _T_227 = ~io_lsu_pkt_r_unsign; // @[el2_lsu_lsc_ctl.scala 272:17] + wire _T_228 = _T_227 & io_lsu_pkt_r_by; // @[el2_lsu_lsc_ctl.scala 272:38] + wire [31:0] _T_230 = _T_228 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [23:0] _T_233 = lsu_ld_datafn_corr_r[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_235 = {_T_233,lsu_ld_datafn_corr_r[7:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_236 = _T_230 & _T_235; // @[el2_lsu_lsc_ctl.scala 272:61] + wire [31:0] _T_237 = _T_226 | _T_236; // @[el2_lsu_lsc_ctl.scala 271:109] + wire _T_239 = _T_227 & io_lsu_pkt_r_half; // @[el2_lsu_lsc_ctl.scala 273:38] + wire [31:0] _T_241 = _T_239 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [15:0] _T_244 = lsu_ld_datafn_corr_r[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_246 = {_T_244,lsu_ld_datafn_corr_r[15:0]}; // @[Cat.scala 29:58] + wire [31:0] _T_247 = _T_241 & _T_246; // @[el2_lsu_lsc_ctl.scala 273:61] + wire [31:0] _T_248 = _T_237 | _T_247; // @[el2_lsu_lsc_ctl.scala 272:134] + wire [31:0] _T_250 = io_lsu_pkt_r_word ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_252 = _T_250 & lsu_ld_datafn_corr_r; // @[el2_lsu_lsc_ctl.scala 274:38] + el2_lsu_addrcheck addrcheck ( // @[el2_lsu_lsc_ctl.scala 119:25] + .reset(addrcheck_reset), + .io_lsu_c2_m_clk(addrcheck_io_lsu_c2_m_clk), .io_start_addr_d(addrcheck_io_start_addr_d), .io_end_addr_d(addrcheck_io_end_addr_d), + .io_lsu_pkt_d_fast_int(addrcheck_io_lsu_pkt_d_fast_int), .io_lsu_pkt_d_by(addrcheck_io_lsu_pkt_d_by), .io_lsu_pkt_d_half(addrcheck_io_lsu_pkt_d_half), .io_lsu_pkt_d_word(addrcheck_io_lsu_pkt_d_word), @@ -725,236 +545,91 @@ module el2_lsu_lsc_ctl( .io_lsu_pkt_d_valid(addrcheck_io_lsu_pkt_d_valid), .io_dec_tlu_mrac_ff(addrcheck_io_dec_tlu_mrac_ff), .io_rs1_region_d(addrcheck_io_rs1_region_d), + .io_is_sideeffects_m(addrcheck_io_is_sideeffects_m), .io_addr_in_dccm_d(addrcheck_io_addr_in_dccm_d), .io_addr_in_pic_d(addrcheck_io_addr_in_pic_d), .io_addr_external_d(addrcheck_io_addr_external_d), .io_access_fault_d(addrcheck_io_access_fault_d), .io_misaligned_fault_d(addrcheck_io_misaligned_fault_d), - .io_exc_mscause_d(addrcheck_io_exc_mscause_d) + .io_exc_mscause_d(addrcheck_io_exc_mscause_d), + .io_fir_dccm_access_error_d(addrcheck_io_fir_dccm_access_error_d), + .io_fir_nondccm_access_error_d(addrcheck_io_fir_nondccm_access_error_d) ); - rvdff access_fault_mff ( // @[el2_lsu_lsc_ctl.scala 169:45] - .clock(access_fault_mff_clock), - .reset(access_fault_mff_reset), - .io_din(access_fault_mff_io_din), - .io_dout(access_fault_mff_io_dout) - ); - rvdff misaligned_fault_mff ( // @[el2_lsu_lsc_ctl.scala 171:45] - .clock(misaligned_fault_mff_clock), - .reset(misaligned_fault_mff_reset), - .io_din(misaligned_fault_mff_io_din), - .io_dout(misaligned_fault_mff_io_dout) - ); - rvdff_2 exc_mscause_mff ( // @[el2_lsu_lsc_ctl.scala 173:45] - .clock(exc_mscause_mff_clock), - .reset(exc_mscause_mff_reset), - .io_din(exc_mscause_mff_io_din), - .io_dout(exc_mscause_mff_io_dout) - ); - rvdff lsu_pkt_vldmff ( // @[el2_lsu_lsc_ctl.scala 278:36] - .clock(lsu_pkt_vldmff_clock), - .reset(lsu_pkt_vldmff_reset), - .io_din(lsu_pkt_vldmff_io_din), - .io_dout(lsu_pkt_vldmff_io_dout) - ); - rvdff lsu_pkt_vldrff ( // @[el2_lsu_lsc_ctl.scala 279:36] - .clock(lsu_pkt_vldrff_clock), - .reset(lsu_pkt_vldrff_reset), - .io_din(lsu_pkt_vldrff_io_din), - .io_dout(lsu_pkt_vldrff_io_dout) - ); - rvdff_6 sdmff ( // @[el2_lsu_lsc_ctl.scala 333:20] - .clock(sdmff_clock), - .reset(sdmff_reset), - .io_din(sdmff_io_din), - .io_dout(sdmff_io_dout) - ); - rvdff_6 samff ( // @[el2_lsu_lsc_ctl.scala 337:20] - .clock(samff_clock), - .reset(samff_reset), - .io_din(samff_io_din), - .io_dout(samff_io_dout) - ); - rvdff_6 sarff ( // @[el2_lsu_lsc_ctl.scala 341:20] - .clock(sarff_clock), - .reset(sarff_reset), - .io_din(sarff_io_din), - .io_dout(sarff_io_dout) - ); - rvdff_6 end_addr_mff ( // @[el2_lsu_lsc_ctl.scala 345:28] - .clock(end_addr_mff_clock), - .reset(end_addr_mff_reset), - .io_din(end_addr_mff_io_din), - .io_dout(end_addr_mff_io_dout) - ); - rvdff_6 end_addr_rff ( // @[el2_lsu_lsc_ctl.scala 349:28] - .clock(end_addr_rff_clock), - .reset(end_addr_rff_reset), - .io_din(end_addr_rff_io_din), - .io_dout(end_addr_rff_io_dout) - ); - rvdff addr_in_dccm_mff ( // @[el2_lsu_lsc_ctl.scala 353:36] - .clock(addr_in_dccm_mff_clock), - .reset(addr_in_dccm_mff_reset), - .io_din(addr_in_dccm_mff_io_din), - .io_dout(addr_in_dccm_mff_io_dout) - ); - rvdff addr_in_dccm_rff ( // @[el2_lsu_lsc_ctl.scala 357:37] - .clock(addr_in_dccm_rff_clock), - .reset(addr_in_dccm_rff_reset), - .io_din(addr_in_dccm_rff_io_din), - .io_dout(addr_in_dccm_rff_io_dout) - ); - rvdff addr_in_pic_mff ( // @[el2_lsu_lsc_ctl.scala 361:37] - .clock(addr_in_pic_mff_clock), - .reset(addr_in_pic_mff_reset), - .io_din(addr_in_pic_mff_io_din), - .io_dout(addr_in_pic_mff_io_dout) - ); - rvdff addr_in_pic_rff ( // @[el2_lsu_lsc_ctl.scala 365:37] - .clock(addr_in_pic_rff_clock), - .reset(addr_in_pic_rff_reset), - .io_din(addr_in_pic_rff_io_din), - .io_dout(addr_in_pic_rff_io_dout) - ); - rvdff addr_external_mff ( // @[el2_lsu_lsc_ctl.scala 369:37] - .clock(addr_external_mff_clock), - .reset(addr_external_mff_reset), - .io_din(addr_external_mff_io_din), - .io_dout(addr_external_mff_io_dout) - ); - rvdff addr_external_rff ( // @[el2_lsu_lsc_ctl.scala 373:37] - .clock(addr_external_rff_clock), - .reset(addr_external_rff_reset), - .io_din(addr_external_rff_io_din), - .io_dout(addr_external_rff_io_dout) - ); - rvdff_6 bus_read_data_r_ff ( // @[el2_lsu_lsc_ctl.scala 377:38] - .clock(bus_read_data_r_ff_clock), - .reset(bus_read_data_r_ff_reset), - .io_din(bus_read_data_r_ff_io_din), - .io_dout(bus_read_data_r_ff_io_dout) - ); - assign io_lsu_result_m = _T_156 | _T_160; // @[el2_lsu_lsc_ctl.scala 429:27] - assign io_lsu_addr_d = lsadder_io_dout; // @[el2_lsu_lsc_ctl.scala 387:28] - assign io_lsu_addr_m = samff_io_dout; // @[el2_lsu_lsc_ctl.scala 339:26] - assign io_lsu_addr_r = sarff_io_dout; // @[el2_lsu_lsc_ctl.scala 343:23] - assign io_end_addr_d = rs1_d + _T_27; // @[el2_lsu_lsc_ctl.scala 133:24] - assign io_end_addr_m = end_addr_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 347:26] - assign io_end_addr_r = end_addr_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 351:26] - assign io_store_data_m = _T_114 & _T_116; // @[el2_lsu_lsc_ctl.scala 394:29] - assign io_lsu_commit_r = _T_107 & _T_108; // @[el2_lsu_lsc_ctl.scala 391:19] - assign io_lsu_single_ecc_error_incr = _T_34 & io_lsu_pkt_r_valid; // @[el2_lsu_lsc_ctl.scala 189:32] - assign io_lsu_error_pkt_r_exc_valid = _T_65_exc_valid; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_error_pkt_r_single_ecc_error = _T_65_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_error_pkt_r_inst_type = _T_65_inst_type; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_error_pkt_r_exc_type = _T_65_exc_type; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_error_pkt_r_mscause = _T_65_mscause; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_error_pkt_r_addr = _T_65_addr; // @[el2_lsu_lsc_ctl.scala 241:24] - assign io_lsu_fir_addr = io_lsu_ld_data_corr_r; // @[el2_lsu_lsc_ctl.scala 384:28] - assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 152:42] - assign io_addr_in_dccm_m = addr_in_dccm_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 355:27] - assign io_addr_in_dccm_r = addr_in_dccm_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 359:28] - assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 153:42] - assign io_addr_in_pic_m = addr_in_pic_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 363:27] - assign io_addr_in_pic_r = addr_in_pic_rff_io_dout; // @[el2_lsu_lsc_ctl.scala 367:27] - assign io_addr_external_m = addr_external_mff_io_dout; // @[el2_lsu_lsc_ctl.scala 371:28] - assign io_lsu_pkt_d_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_by = io_dec_lsu_valid_raw_d ? io_lsu_p_by : dma_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_half = io_dec_lsu_valid_raw_d ? io_lsu_p_half : dma_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_word = io_dec_lsu_valid_raw_d ? io_lsu_p_word : dma_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_dword : dma_pkt_d_dword; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_load = io_dec_lsu_valid_raw_d ? io_lsu_p_load : dma_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_store = io_dec_lsu_valid_raw_d ? io_lsu_p_store : io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_unsign; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_dma : 1'h1; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 285:20] - assign io_lsu_pkt_d_valid = _T_82 | io_dma_dccm_req; // @[el2_lsu_lsc_ctl.scala 285:20 el2_lsu_lsc_ctl.scala 289:24] - assign io_lsu_pkt_m_fast_int = _T_92_fast_int; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_by = _T_92_by; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_half = _T_92_half; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_word = _T_92_word; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_dword = _T_92_dword; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_load = _T_92_load; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_store = _T_92_store; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_unsign = _T_92_unsign; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_dma = _T_92_dma; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_store_data_bypass_m = _T_92_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_m_valid = _T_92_valid; // @[el2_lsu_lsc_ctl.scala 296:34 el2_lsu_lsc_ctl.scala 305:16] - assign io_lsu_pkt_r_by = _T_93_by; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_half = _T_93_half; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_word = _T_93_word; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_dword = _T_93_dword; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_load = _T_93_load; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_store = _T_93_store; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_unsign = _T_93_unsign; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_dma = _T_93_dma; // @[el2_lsu_lsc_ctl.scala 310:16] - assign io_lsu_pkt_r_valid = _T_93_valid; // @[el2_lsu_lsc_ctl.scala 300:33 el2_lsu_lsc_ctl.scala 310:16] - assign lsadder_io_rs1 = io_lsu_pkt_d_load_ldst_bypass_d ? io_lsu_result_m : lsu_rs1_d; // @[el2_lsu_lsc_ctl.scala 119:26] - assign lsadder_io_offset = io_dec_lsu_offset_d & _T_3; // @[el2_lsu_lsc_ctl.scala 120:26] - assign addrcheck_io_start_addr_d = lsadder_io_dout; // @[el2_lsu_lsc_ctl.scala 145:42] - assign addrcheck_io_end_addr_d = rs1_d + _T_27; // @[el2_lsu_lsc_ctl.scala 146:42] - assign addrcheck_io_lsu_pkt_d_by = io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_half = io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_word = io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_load = io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_store = io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_dma = io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 147:42] - assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 148:42] - assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[el2_lsu_lsc_ctl.scala 149:42] - assign access_fault_mff_clock = clock; - assign access_fault_mff_reset = reset; - assign access_fault_mff_io_din = addrcheck_io_access_fault_d; // @[el2_lsu_lsc_ctl.scala 246:40] - assign misaligned_fault_mff_clock = clock; - assign misaligned_fault_mff_reset = reset; - assign misaligned_fault_mff_io_din = addrcheck_io_misaligned_fault_d; // @[el2_lsu_lsc_ctl.scala 249:40] - assign exc_mscause_mff_clock = clock; - assign exc_mscause_mff_reset = reset; - assign exc_mscause_mff_io_din = addrcheck_io_exc_mscause_d; // @[el2_lsu_lsc_ctl.scala 252:40] - assign lsu_pkt_vldmff_clock = clock; - assign lsu_pkt_vldmff_reset = reset; - assign lsu_pkt_vldmff_io_din = io_lsu_pkt_d_valid & _T_86; // @[el2_lsu_lsc_ctl.scala 295:34] - assign lsu_pkt_vldrff_clock = clock; - assign lsu_pkt_vldrff_reset = reset; - assign lsu_pkt_vldrff_io_din = io_lsu_pkt_m_valid & _T_90; // @[el2_lsu_lsc_ctl.scala 299:33] - assign sdmff_clock = clock; - assign sdmff_reset = reset; - assign sdmff_io_din = io_lsu_pkt_d_store_data_bypass_d ? io_lsu_result_m : store_data_d; // @[el2_lsu_lsc_ctl.scala 334:27] - assign samff_clock = clock; - assign samff_reset = reset; - assign samff_io_din = io_lsu_addr_d; // @[el2_lsu_lsc_ctl.scala 338:23] - assign sarff_clock = clock; - assign sarff_reset = reset; - assign sarff_io_din = io_lsu_addr_m; // @[el2_lsu_lsc_ctl.scala 342:23] - assign end_addr_mff_clock = clock; - assign end_addr_mff_reset = reset; - assign end_addr_mff_io_din = io_end_addr_d; // @[el2_lsu_lsc_ctl.scala 346:26] - assign end_addr_rff_clock = clock; - assign end_addr_rff_reset = reset; - assign end_addr_rff_io_din = io_end_addr_m; // @[el2_lsu_lsc_ctl.scala 350:26] - assign addr_in_dccm_mff_clock = clock; - assign addr_in_dccm_mff_reset = reset; - assign addr_in_dccm_mff_io_din = io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 354:27] - assign addr_in_dccm_rff_clock = clock; - assign addr_in_dccm_rff_reset = reset; - assign addr_in_dccm_rff_io_din = io_addr_in_dccm_m; // @[el2_lsu_lsc_ctl.scala 358:28] - assign addr_in_pic_mff_clock = clock; - assign addr_in_pic_mff_reset = reset; - assign addr_in_pic_mff_io_din = io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 362:27] - assign addr_in_pic_rff_clock = clock; - assign addr_in_pic_rff_reset = reset; - assign addr_in_pic_rff_io_din = io_addr_in_pic_m; // @[el2_lsu_lsc_ctl.scala 366:27] - assign addr_external_mff_clock = clock; - assign addr_external_mff_reset = reset; - assign addr_external_mff_io_din = addrcheck_io_addr_external_d; // @[el2_lsu_lsc_ctl.scala 370:28] - assign addr_external_rff_clock = clock; - assign addr_external_rff_reset = reset; - assign addr_external_rff_io_din = io_addr_external_m; // @[el2_lsu_lsc_ctl.scala 374:28] - assign bus_read_data_r_ff_clock = clock; - assign bus_read_data_r_ff_reset = reset; - assign bus_read_data_r_ff_io_din = 32'h0; // @[el2_lsu_lsc_ctl.scala 378:29] + assign io_lsu_result_m = _T_208 | _T_212; // @[el2_lsu_lsc_ctl.scala 265:27] + assign io_lsu_result_corr_r = _T_248 | _T_252; // @[el2_lsu_lsc_ctl.scala 270:27] + assign io_lsu_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 239:28] + assign io_lsu_addr_m = _T_146; // @[el2_lsu_lsc_ctl.scala 225:24] + assign io_lsu_addr_r = _T_147; // @[el2_lsu_lsc_ctl.scala 226:24] + assign io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 116:24] + assign io_end_addr_m = _T_148; // @[el2_lsu_lsc_ctl.scala 227:24] + assign io_end_addr_r = _T_149; // @[el2_lsu_lsc_ctl.scala 228:24] + assign io_store_data_m = _T_166 & _T_168; // @[el2_lsu_lsc_ctl.scala 242:29] + assign io_lsu_exc_m = access_fault_m | misaligned_fault_m; // @[el2_lsu_lsc_ctl.scala 156:16] + assign io_is_sideeffects_m = addrcheck_io_is_sideeffects_m; // @[el2_lsu_lsc_ctl.scala 129:42] + assign io_lsu_commit_r = _T_159 & _T_160; // @[el2_lsu_lsc_ctl.scala 241:19] + assign io_lsu_single_ecc_error_incr = _T_73 & io_lsu_pkt_r_valid; // @[el2_lsu_lsc_ctl.scala 157:32] + assign io_lsu_error_pkt_r_exc_valid = _T_105_exc_valid; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_error_pkt_r_single_ecc_error = _T_105_single_ecc_error; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_error_pkt_r_inst_type = _T_105_inst_type; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_error_pkt_r_exc_type = _T_105_exc_type; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_error_pkt_r_mscause = _T_105_mscause; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_error_pkt_r_addr = _T_105_addr; // @[el2_lsu_lsc_ctl.scala 186:38] + assign io_lsu_fir_addr = io_lsu_ld_data_corr_r[31:1]; // @[el2_lsu_lsc_ctl.scala 237:28] + assign io_lsu_fir_error = _T_106; // @[el2_lsu_lsc_ctl.scala 187:38] + assign io_addr_in_dccm_d = addrcheck_io_addr_in_dccm_d; // @[el2_lsu_lsc_ctl.scala 130:42] + assign io_addr_in_dccm_m = _T_150; // @[el2_lsu_lsc_ctl.scala 229:24] + assign io_addr_in_dccm_r = _T_151; // @[el2_lsu_lsc_ctl.scala 230:24] + assign io_addr_in_pic_d = addrcheck_io_addr_in_pic_d; // @[el2_lsu_lsc_ctl.scala 131:42] + assign io_addr_in_pic_m = _T_152; // @[el2_lsu_lsc_ctl.scala 231:24] + assign io_addr_in_pic_r = _T_153; // @[el2_lsu_lsc_ctl.scala 232:24] + assign io_addr_external_m = _T_154; // @[el2_lsu_lsc_ctl.scala 233:24] + assign io_lsu_pkt_d_fast_int = io_dec_lsu_valid_raw_d & io_lsu_p_fast_int; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_by = io_dec_lsu_valid_raw_d ? io_lsu_p_by : dma_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_half = io_dec_lsu_valid_raw_d ? io_lsu_p_half : dma_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_word = io_dec_lsu_valid_raw_d ? io_lsu_p_word : dma_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_dword = io_dec_lsu_valid_raw_d ? io_lsu_p_dword : dma_pkt_d_dword; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_load = io_dec_lsu_valid_raw_d ? io_lsu_p_load : dma_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_store = io_dec_lsu_valid_raw_d ? io_lsu_p_store : io_dma_mem_write; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_unsign = io_dec_lsu_valid_raw_d & io_lsu_p_unsign; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_dma = io_dec_lsu_valid_raw_d ? io_lsu_p_dma : 1'h1; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_store_data_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_load_ldst_bypass_d = io_dec_lsu_valid_raw_d & io_lsu_p_load_ldst_bypass_d; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_store_data_bypass_m = io_dec_lsu_valid_raw_d & io_lsu_p_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 207:20] + assign io_lsu_pkt_d_valid = _T_121 | io_dma_dccm_req; // @[el2_lsu_lsc_ctl.scala 207:20 el2_lsu_lsc_ctl.scala 211:24] + assign io_lsu_pkt_m_fast_int = _T_132_fast_int; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_by = _T_132_by; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_half = _T_132_half; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_word = _T_132_word; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_dword = _T_132_dword; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_load = _T_132_load; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_store = _T_132_store; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_unsign = _T_132_unsign; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_dma = _T_132_dma; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_store_data_bypass_m = _T_132_store_data_bypass_m; // @[el2_lsu_lsc_ctl.scala 215:28] + assign io_lsu_pkt_m_valid = _T_135; // @[el2_lsu_lsc_ctl.scala 215:28 el2_lsu_lsc_ctl.scala 217:28] + assign io_lsu_pkt_r_by = _T_134_by; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_half = _T_134_half; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_word = _T_134_word; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_dword = _T_134_dword; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_load = _T_134_load; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_store = _T_134_store; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_unsign = _T_134_unsign; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_dma = _T_134_dma; // @[el2_lsu_lsc_ctl.scala 216:28] + assign io_lsu_pkt_r_valid = _T_136; // @[el2_lsu_lsc_ctl.scala 216:28 el2_lsu_lsc_ctl.scala 218:28] + assign addrcheck_reset = reset; + assign addrcheck_io_lsu_c2_m_clk = io_lsu_c2_m_clk; // @[el2_lsu_lsc_ctl.scala 121:42] + assign addrcheck_io_start_addr_d = {_T_40,_T_10[11:0]}; // @[el2_lsu_lsc_ctl.scala 123:42] + assign addrcheck_io_end_addr_d = rs1_d + _T_64; // @[el2_lsu_lsc_ctl.scala 124:42] + assign addrcheck_io_lsu_pkt_d_fast_int = io_lsu_pkt_d_fast_int; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_by = io_lsu_pkt_d_by; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_half = io_lsu_pkt_d_half; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_word = io_lsu_pkt_d_word; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_load = io_lsu_pkt_d_load; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_store = io_lsu_pkt_d_store; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_dma = io_lsu_pkt_d_dma; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_lsu_pkt_d_valid = io_lsu_pkt_d_valid; // @[el2_lsu_lsc_ctl.scala 125:42] + assign addrcheck_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu_lsc_ctl.scala 126:42] + assign addrcheck_io_rs1_region_d = rs1_d[31:28]; // @[el2_lsu_lsc_ctl.scala 127:42] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -991,95 +666,549 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_65_exc_valid = _RAND_0[0:0]; + access_fault_m = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - _T_65_single_ecc_error = _RAND_1[0:0]; + misaligned_fault_m = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - _T_65_inst_type = _RAND_2[0:0]; + exc_mscause_m = _RAND_2[3:0]; _RAND_3 = {1{`RANDOM}}; - _T_65_exc_type = _RAND_3[0:0]; + fir_dccm_access_error_m = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - _T_65_mscause = _RAND_4[3:0]; + fir_nondccm_access_error_m = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - _T_65_addr = _RAND_5[31:0]; + _T_105_exc_valid = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - _T_92_fast_int = _RAND_6[0:0]; + _T_105_single_ecc_error = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - _T_92_by = _RAND_7[0:0]; + _T_105_inst_type = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - _T_92_half = _RAND_8[0:0]; + _T_105_exc_type = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - _T_92_word = _RAND_9[0:0]; + _T_105_mscause = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - _T_92_dword = _RAND_10[0:0]; + _T_105_addr = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - _T_92_load = _RAND_11[0:0]; + _T_106 = _RAND_11[1:0]; _RAND_12 = {1{`RANDOM}}; - _T_92_store = _RAND_12[0:0]; + _T_132_fast_int = _RAND_12[0:0]; _RAND_13 = {1{`RANDOM}}; - _T_92_unsign = _RAND_13[0:0]; + _T_132_by = _RAND_13[0:0]; _RAND_14 = {1{`RANDOM}}; - _T_92_dma = _RAND_14[0:0]; + _T_132_half = _RAND_14[0:0]; _RAND_15 = {1{`RANDOM}}; - _T_92_store_data_bypass_m = _RAND_15[0:0]; + _T_132_word = _RAND_15[0:0]; _RAND_16 = {1{`RANDOM}}; - _T_92_valid = _RAND_16[0:0]; + _T_132_dword = _RAND_16[0:0]; _RAND_17 = {1{`RANDOM}}; - _T_93_by = _RAND_17[0:0]; + _T_132_load = _RAND_17[0:0]; _RAND_18 = {1{`RANDOM}}; - _T_93_half = _RAND_18[0:0]; + _T_132_store = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - _T_93_word = _RAND_19[0:0]; + _T_132_unsign = _RAND_19[0:0]; _RAND_20 = {1{`RANDOM}}; - _T_93_dword = _RAND_20[0:0]; + _T_132_dma = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - _T_93_load = _RAND_21[0:0]; + _T_132_store_data_bypass_m = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - _T_93_store = _RAND_22[0:0]; + _T_134_by = _RAND_22[0:0]; _RAND_23 = {1{`RANDOM}}; - _T_93_unsign = _RAND_23[0:0]; + _T_134_half = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - _T_93_dma = _RAND_24[0:0]; + _T_134_word = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - _T_93_valid = _RAND_25[0:0]; + _T_134_dword = _RAND_25[0:0]; + _RAND_26 = {1{`RANDOM}}; + _T_134_load = _RAND_26[0:0]; + _RAND_27 = {1{`RANDOM}}; + _T_134_store = _RAND_27[0:0]; + _RAND_28 = {1{`RANDOM}}; + _T_134_unsign = _RAND_28[0:0]; + _RAND_29 = {1{`RANDOM}}; + _T_134_dma = _RAND_29[0:0]; + _RAND_30 = {1{`RANDOM}}; + _T_135 = _RAND_30[0:0]; + _RAND_31 = {1{`RANDOM}}; + _T_136 = _RAND_31[0:0]; + _RAND_32 = {1{`RANDOM}}; + store_data_pre_m = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + _T_146 = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + _T_147 = _RAND_34[31:0]; + _RAND_35 = {1{`RANDOM}}; + _T_148 = _RAND_35[31:0]; + _RAND_36 = {1{`RANDOM}}; + _T_149 = _RAND_36[31:0]; + _RAND_37 = {1{`RANDOM}}; + _T_150 = _RAND_37[0:0]; + _RAND_38 = {1{`RANDOM}}; + _T_151 = _RAND_38[0:0]; + _RAND_39 = {1{`RANDOM}}; + _T_152 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + _T_153 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + _T_154 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + addr_external_r = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + bus_read_data_r = _RAND_43[31:0]; `endif // RANDOMIZE_REG_INIT + if (reset) begin + access_fault_m = 1'h0; + end + if (reset) begin + misaligned_fault_m = 1'h0; + end + if (reset) begin + exc_mscause_m = 4'h0; + end + if (reset) begin + fir_dccm_access_error_m = 1'h0; + end + if (reset) begin + fir_nondccm_access_error_m = 1'h0; + end + if (reset) begin + _T_105_exc_valid = 1'h0; + end + if (reset) begin + _T_105_single_ecc_error = 1'h0; + end + if (reset) begin + _T_105_inst_type = 1'h0; + end + if (reset) begin + _T_105_exc_type = 1'h0; + end + if (reset) begin + _T_105_mscause = 1'h0; + end + if (reset) begin + _T_105_addr = 1'h0; + end + if (reset) begin + _T_106 = 2'h0; + end + if (reset) begin + _T_132_fast_int = 1'h0; + end + if (reset) begin + _T_132_by = 1'h0; + end + if (reset) begin + _T_132_half = 1'h0; + end + if (reset) begin + _T_132_word = 1'h0; + end + if (reset) begin + _T_132_dword = 1'h0; + end + if (reset) begin + _T_132_load = 1'h0; + end + if (reset) begin + _T_132_store = 1'h0; + end + if (reset) begin + _T_132_unsign = 1'h0; + end + if (reset) begin + _T_132_dma = 1'h0; + end + if (reset) begin + _T_132_store_data_bypass_m = 1'h0; + end + if (reset) begin + _T_134_by = 1'h0; + end + if (reset) begin + _T_134_half = 1'h0; + end + if (reset) begin + _T_134_word = 1'h0; + end + if (reset) begin + _T_134_dword = 1'h0; + end + if (reset) begin + _T_134_load = 1'h0; + end + if (reset) begin + _T_134_store = 1'h0; + end + if (reset) begin + _T_134_unsign = 1'h0; + end + if (reset) begin + _T_134_dma = 1'h0; + end + if (reset) begin + _T_135 = 1'h0; + end + if (reset) begin + _T_136 = 1'h0; + end + if (reset) begin + store_data_pre_m = 32'h0; + end + if (reset) begin + _T_146 = 32'h0; + end + if (reset) begin + _T_147 = 32'h0; + end + if (reset) begin + _T_148 = 32'h0; + end + if (reset) begin + _T_149 = 32'h0; + end + if (reset) begin + _T_150 = 1'h0; + end + if (reset) begin + _T_151 = 1'h0; + end + if (reset) begin + _T_152 = 1'h0; + end + if (reset) begin + _T_153 = 1'h0; + end + if (reset) begin + _T_154 = 1'h0; + end + if (reset) begin + addr_external_r = 1'h0; + end + if (reset) begin + bus_read_data_r = 32'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge clock) begin - _T_65_exc_valid <= _T_42 & _T_43; - _T_65_single_ecc_error <= _T_46 & _T_39; - _T_65_inst_type <= io_lsu_pkt_m_store; - _T_65_exc_type <= ~misaligned_fault_m; - if (_T_53) begin - _T_65_mscause <= 4'h1; + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + access_fault_m <= 1'h0; end else begin - _T_65_mscause <= exc_mscause_m; + access_fault_m <= addrcheck_io_access_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + misaligned_fault_m <= 1'h0; + end else begin + misaligned_fault_m <= addrcheck_io_misaligned_fault_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + exc_mscause_m <= 4'h0; + end else begin + exc_mscause_m <= addrcheck_io_exc_mscause_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_dccm_access_error_m <= 1'h0; + end else begin + fir_dccm_access_error_m <= addrcheck_io_fir_dccm_access_error_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + fir_nondccm_access_error_m <= 1'h0; + end else begin + fir_nondccm_access_error_m <= addrcheck_io_fir_nondccm_access_error_d; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_exc_valid <= 1'h0; + end else begin + _T_105_exc_valid <= _T_81 & _T_82; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_single_ecc_error <= 1'h0; + end else begin + _T_105_single_ecc_error <= _T_85 & _T_78; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_inst_type <= 1'h0; + end else begin + _T_105_inst_type <= io_lsu_pkt_m_store; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_exc_type <= 1'h0; + end else begin + _T_105_exc_type <= ~misaligned_fault_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_mscause <= 1'h0; + end else begin + _T_105_mscause <= _T_95[0]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_105_addr <= 1'h0; + end else begin + _T_105_addr <= io_lsu_addr_m[0]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_106 <= 2'h0; + end else if (fir_nondccm_access_error_m) begin + _T_106 <= 2'h3; + end else if (fir_dccm_access_error_m) begin + _T_106 <= 2'h2; + end else if (_T_99) begin + _T_106 <= 2'h1; + end else begin + _T_106 <= 2'h0; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_fast_int <= 1'h0; + end else begin + _T_132_fast_int <= io_lsu_pkt_d_fast_int; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_by <= 1'h0; + end else begin + _T_132_by <= io_lsu_pkt_d_by; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_half <= 1'h0; + end else begin + _T_132_half <= io_lsu_pkt_d_half; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_word <= 1'h0; + end else begin + _T_132_word <= io_lsu_pkt_d_word; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_dword <= 1'h0; + end else begin + _T_132_dword <= io_lsu_pkt_d_dword; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_load <= 1'h0; + end else begin + _T_132_load <= io_lsu_pkt_d_load; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_store <= 1'h0; + end else begin + _T_132_store <= io_lsu_pkt_d_store; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_unsign <= 1'h0; + end else begin + _T_132_unsign <= io_lsu_pkt_d_unsign; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_dma <= 1'h0; + end else begin + _T_132_dma <= io_lsu_pkt_d_dma; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_132_store_data_bypass_m <= 1'h0; + end else begin + _T_132_store_data_bypass_m <= io_lsu_pkt_d_store_data_bypass_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_by <= 1'h0; + end else begin + _T_134_by <= io_lsu_pkt_m_by; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_half <= 1'h0; + end else begin + _T_134_half <= io_lsu_pkt_m_half; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_word <= 1'h0; + end else begin + _T_134_word <= io_lsu_pkt_m_word; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_dword <= 1'h0; + end else begin + _T_134_dword <= io_lsu_pkt_m_dword; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_load <= 1'h0; + end else begin + _T_134_load <= io_lsu_pkt_m_load; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_store <= 1'h0; + end else begin + _T_134_store <= io_lsu_pkt_m_store; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_unsign <= 1'h0; + end else begin + _T_134_unsign <= io_lsu_pkt_m_unsign; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_134_dma <= 1'h0; + end else begin + _T_134_dma <= io_lsu_pkt_m_dma; + end + end + always @(posedge io_lsu_c2_m_clk or posedge reset) begin + if (reset) begin + _T_135 <= 1'h0; + end else begin + _T_135 <= io_lsu_pkt_d_valid & _T_125; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_136 <= 1'h0; + end else begin + _T_136 <= io_lsu_pkt_m_valid & _T_129; + end + end + always @(posedge io_lsu_store_c1_m_clk or posedge reset) begin + if (reset) begin + store_data_pre_m <= 32'h0; + end else if (io_lsu_pkt_d_store_data_bypass_d) begin + store_data_pre_m <= io_lsu_result_m; + end else if (io_dma_dccm_req) begin + store_data_pre_m <= dma_mem_wdata_shifted[31:0]; + end else begin + store_data_pre_m <= io_exu_lsu_rs2_d; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_146 <= 32'h0; + end else begin + _T_146 <= io_lsu_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_147 <= 32'h0; + end else begin + _T_147 <= io_lsu_addr_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_148 <= 32'h0; + end else begin + _T_148 <= io_end_addr_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_149 <= 32'h0; + end else begin + _T_149 <= io_end_addr_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_150 <= 1'h0; + end else begin + _T_150 <= io_addr_in_dccm_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_151 <= 1'h0; + end else begin + _T_151 <= io_addr_in_dccm_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_152 <= 1'h0; + end else begin + _T_152 <= io_addr_in_pic_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + _T_153 <= 1'h0; + end else begin + _T_153 <= io_addr_in_pic_m; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + _T_154 <= 1'h0; + end else begin + _T_154 <= addrcheck_io_addr_external_d; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + addr_external_r <= 1'h0; + end else begin + addr_external_r <= io_addr_external_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + bus_read_data_r <= 32'h0; + end else begin + bus_read_data_r <= io_bus_read_data_m; end - _T_65_addr <= io_lsu_addr_m; - _T_92_fast_int <= io_lsu_pkt_d_fast_int; - _T_92_by <= io_lsu_pkt_d_by; - _T_92_half <= io_lsu_pkt_d_half; - _T_92_word <= io_lsu_pkt_d_word; - _T_92_dword <= io_lsu_pkt_d_dword; - _T_92_load <= io_lsu_pkt_d_load; - _T_92_store <= io_lsu_pkt_d_store; - _T_92_unsign <= io_lsu_pkt_d_unsign; - _T_92_dma <= io_lsu_pkt_d_dma; - _T_92_store_data_bypass_m <= io_lsu_pkt_d_store_data_bypass_m; - _T_92_valid <= io_lsu_pkt_d_valid & _T_86; - _T_93_by <= io_lsu_pkt_m_by; - _T_93_half <= io_lsu_pkt_m_half; - _T_93_word <= io_lsu_pkt_m_word; - _T_93_dword <= io_lsu_pkt_m_dword; - _T_93_load <= io_lsu_pkt_m_load; - _T_93_store <= io_lsu_pkt_m_store; - _T_93_unsign <= io_lsu_pkt_m_unsign; - _T_93_dma <= io_lsu_pkt_m_dma; - _T_93_valid <= io_lsu_pkt_m_valid & _T_90; end endmodule module rvclkhdr( @@ -1088,28 +1217,28 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 331:24] - wire clkhdr_CK; // @[beh_lib.scala 331:24] - wire clkhdr_EN; // @[beh_lib.scala 331:24] - wire clkhdr_SE; // @[beh_lib.scala 331:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 331:24] + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 332:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 333:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 334:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 335:16] + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] endmodule module el2_lsu_dccm_ctl( + input clock, input reset, input io_lsu_c2_m_clk, input io_lsu_c2_r_clk, input io_lsu_free_c2_clk, input io_lsu_store_c1_r_clk, - input io_clk, input io_lsu_pkt_d_word, input io_lsu_pkt_d_dword, input io_lsu_pkt_d_load, @@ -1139,15 +1268,16 @@ module el2_lsu_dccm_ctl( input io_lsu_raw_fwd_lo_r, input io_lsu_raw_fwd_hi_r, input io_lsu_commit_r, - input [15:0] io_lsu_addr_d, + input [31:0] io_lsu_addr_d, input [15:0] io_lsu_addr_m, - input [15:0] io_lsu_addr_r, + input [31:0] io_lsu_addr_r, input [15:0] io_end_addr_d, input [15:0] io_end_addr_m, input [15:0] io_end_addr_r, input io_stbuf_reqvld_any, input [15:0] io_stbuf_addr_any, input [31:0] io_stbuf_data_any, + input [6:0] io_stbuf_ecc_any, input [31:0] io_stbuf_fwddata_hi_m, input [31:0] io_stbuf_fwddata_lo_m, input [3:0] io_stbuf_fwdbyteen_lo_m, @@ -1158,6 +1288,8 @@ module el2_lsu_dccm_ctl( input io_single_ecc_error_lo_r, input [31:0] io_sec_data_hi_r_ff, input [31:0] io_sec_data_lo_r_ff, + input [6:0] io_sec_data_ecc_hi_r_ff, + input [6:0] io_sec_data_ecc_lo_r_ff, output [31:0] io_dccm_rdata_hi_m, output [31:0] io_dccm_rdata_lo_m, output [6:0] io_dccm_data_ecc_hi_m, @@ -1174,10 +1306,13 @@ module el2_lsu_dccm_ctl( input [63:0] io_dma_mem_wdata, input [31:0] io_dma_dccm_wdata_lo, input [31:0] io_dma_dccm_wdata_hi, + input [6:0] io_dma_dccm_wdata_ecc_hi, + input [6:0] io_dma_dccm_wdata_ecc_lo, output [31:0] io_store_data_hi_r, output [31:0] io_store_data_lo_r, output [31:0] io_store_datafn_hi_r, output [31:0] io_store_datafn_lo_r, + output [31:0] io_store_data_r, output io_ld_single_ecc_error_r, output io_ld_single_ecc_error_r_ff, output [31:0] io_picm_mask_data_m, @@ -1217,287 +1352,921 @@ module el2_lsu_dccm_ctl( reg [31:0] _RAND_7; reg [31:0] _RAND_8; `endif // RANDOMIZE_REG_INIT - wire rvclkhdr_io_l1clk; // @[beh_lib.scala 351:21] - wire rvclkhdr_io_clk; // @[beh_lib.scala 351:21] - wire rvclkhdr_io_en; // @[beh_lib.scala 351:21] - wire rvclkhdr_io_scan_mode; // @[beh_lib.scala 351:21] - wire rvclkhdr_1_io_l1clk; // @[beh_lib.scala 351:21] - wire rvclkhdr_1_io_clk; // @[beh_lib.scala 351:21] - wire rvclkhdr_1_io_en; // @[beh_lib.scala 351:21] - wire rvclkhdr_1_io_scan_mode; // @[beh_lib.scala 351:21] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] wire [63:0] picm_rd_data_m = {io_picm_rd_data,io_picm_rd_data}; // @[Cat.scala 29:58] wire [63:0] dccm_rdata_corr_m = {io_sec_data_hi_m,io_sec_data_lo_m}; // @[Cat.scala 29:58] wire [63:0] dccm_rdata_m = {io_dccm_rdata_hi_m,io_dccm_rdata_lo_m}; // @[Cat.scala 29:58] - wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_load; // @[el2_lsu_dccm_ctl.scala 168:50] - wire [7:0] _T_30 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58] - wire [63:0] _T_33 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58] - wire [7:0] _T_38 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_corr_m[15:8]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_1 = _T_30[1] ? _T_33[15:8] : _T_38; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_18 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_corr_m[7:0]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_0 = _T_30[0] ? _T_33[7:0] : _T_18; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_78 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_corr_m[31:24]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_3 = _T_30[3] ? _T_33[31:24] : _T_78; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_58 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_corr_m[23:16]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_2 = _T_30[2] ? _T_33[23:16] : _T_58; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [31:0] _T_4 = {lsu_rdata_corr_m_3,lsu_rdata_corr_m_2,lsu_rdata_corr_m_1,lsu_rdata_corr_m_0}; // @[el2_lsu_dccm_ctl.scala 170:48] - wire [7:0] _T_118 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_corr_m[47:40]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_5 = _T_30[5] ? _T_33[47:40] : _T_118; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_98 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_corr_m[39:32]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_4 = _T_30[4] ? _T_33[39:32] : _T_98; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_158 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_corr_m[63:56]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_7 = _T_30[7] ? _T_33[63:56] : _T_158; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [7:0] _T_138 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_corr_m[55:48]; // @[el2_lsu_dccm_ctl.scala 184:171] - wire [7:0] lsu_rdata_corr_m_6 = _T_30[6] ? _T_33[55:48] : _T_138; // @[el2_lsu_dccm_ctl.scala 184:36] - wire [31:0] _T_7 = {lsu_rdata_corr_m_7,lsu_rdata_corr_m_6,lsu_rdata_corr_m_5,lsu_rdata_corr_m_4}; // @[el2_lsu_dccm_ctl.scala 170:48] - wire [63:0] _T_8 = {lsu_rdata_corr_m_7,lsu_rdata_corr_m_6,lsu_rdata_corr_m_5,lsu_rdata_corr_m_4,lsu_rdata_corr_m_3,lsu_rdata_corr_m_2,lsu_rdata_corr_m_1,lsu_rdata_corr_m_0}; // @[el2_lsu_dccm_ctl.scala 170:48] - reg [63:0] _T_9; // @[el2_lsu_dccm_ctl.scala 178:65] - wire [7:0] _T_28 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_m[7:0]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_0 = _T_30[0] ? _T_33[7:0] : _T_28; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_48 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_m[15:8]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_1 = _T_30[1] ? _T_33[15:8] : _T_48; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_68 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_m[23:16]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_2 = _T_30[2] ? _T_33[23:16] : _T_68; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_88 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_m[31:24]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_3 = _T_30[3] ? _T_33[31:24] : _T_88; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_108 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_m[39:32]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_4 = _T_30[4] ? _T_33[39:32] : _T_108; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_128 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_m[47:40]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_5 = _T_30[5] ? _T_33[47:40] : _T_128; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_148 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_m[55:48]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_6 = _T_30[6] ? _T_33[55:48] : _T_148; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [7:0] _T_168 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_m[63:56]; // @[el2_lsu_dccm_ctl.scala 185:171] - wire [7:0] lsu_rdata_m_7 = _T_30[7] ? _T_33[63:56] : _T_168; // @[el2_lsu_dccm_ctl.scala 185:36] - wire [63:0] _T_176 = {lsu_rdata_m_7,lsu_rdata_m_6,lsu_rdata_m_5,lsu_rdata_m_4,lsu_rdata_m_3,lsu_rdata_m_2,lsu_rdata_m_1,lsu_rdata_m_0}; // @[el2_lsu_dccm_ctl.scala 186:43] - wire [3:0] _GEN_0 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_dccm_ctl.scala 186:56] - wire [5:0] _T_178 = 4'h8 * _GEN_0; // @[el2_lsu_dccm_ctl.scala 186:56] - wire [63:0] _T_179 = _T_176 >> _T_178; // @[el2_lsu_dccm_ctl.scala 186:50] - wire _T_192 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 190:64] - wire _T_195 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 190:145] - wire _T_196 = _T_192 | _T_195; // @[el2_lsu_dccm_ctl.scala 190:109] - wire _T_197 = _T_196 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 190:191] - wire _T_198 = _T_197 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 190:212] - wire _T_199 = _T_198 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 190:233] - wire _T_200 = _T_199 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 190:252] - wire _T_203 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 191:41] - wire _T_206 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 191:122] - wire _T_207 = _T_203 | _T_206; // @[el2_lsu_dccm_ctl.scala 191:86] - wire _T_208 = _T_207 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 191:168] - wire _T_209 = _T_208 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 191:189] - wire _T_210 = _T_209 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 191:210] - wire _T_211 = _T_210 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 191:229] - wire kill_ecc_corr_lo_r = _T_200 | _T_211; // @[el2_lsu_dccm_ctl.scala 190:273] - wire _T_214 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 192:64] - wire _T_217 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 192:145] - wire _T_218 = _T_214 | _T_217; // @[el2_lsu_dccm_ctl.scala 192:109] - wire _T_219 = _T_218 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 192:191] - wire _T_220 = _T_219 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 192:212] - wire _T_221 = _T_220 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 192:233] - wire _T_222 = _T_221 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 192:252] - wire _T_225 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 193:41] - wire _T_228 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 193:122] - wire _T_229 = _T_225 | _T_228; // @[el2_lsu_dccm_ctl.scala 193:86] - wire _T_230 = _T_229 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 193:168] - wire _T_231 = _T_230 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 193:189] - wire _T_232 = _T_231 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 193:210] - wire _T_233 = _T_232 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 193:229] - wire kill_ecc_corr_hi_r = _T_222 | _T_233; // @[el2_lsu_dccm_ctl.scala 192:273] - wire _T_234 = io_lsu_pkt_r_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 194:55] - wire _T_235 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 194:84] - wire ld_single_ecc_error_lo_r = _T_234 & _T_235; // @[el2_lsu_dccm_ctl.scala 194:82] - wire _T_236 = io_lsu_pkt_r_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 195:55] - wire _T_237 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 195:84] - wire ld_single_ecc_error_hi_r = _T_236 & _T_237; // @[el2_lsu_dccm_ctl.scala 195:82] - wire _T_238 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 196:62] - wire _T_239 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_dccm_ctl.scala 196:92] - wire _T_241 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_dccm_ctl.scala 197:81] - wire _T_242 = ld_single_ecc_error_lo_r & _T_241; // @[el2_lsu_dccm_ctl.scala 197:62] - wire _T_243 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 197:103] - wire _T_245 = ld_single_ecc_error_hi_r & _T_241; // @[el2_lsu_dccm_ctl.scala 198:62] - wire _T_246 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 198:103] - reg lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 200:74] - reg ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 201:74] - reg ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 202:74] - reg [15:0] ld_sec_addr_hi_r_ff; // @[beh_lib.scala 357:14] - reg [15:0] ld_sec_addr_lo_r_ff; // @[beh_lib.scala 357:14] - wire _T_253 = io_lsu_pkt_d_word | io_lsu_pkt_d_dword; // @[el2_lsu_dccm_ctl.scala 208:110] - wire _T_254 = ~_T_253; // @[el2_lsu_dccm_ctl.scala 208:90] - wire _T_256 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 208:154] - wire _T_257 = _T_254 | _T_256; // @[el2_lsu_dccm_ctl.scala 208:132] - wire _T_258 = io_lsu_pkt_d_store & _T_257; // @[el2_lsu_dccm_ctl.scala 208:87] - wire _T_259 = io_lsu_pkt_d_load | _T_258; // @[el2_lsu_dccm_ctl.scala 208:65] - wire _T_260 = io_lsu_pkt_d_valid & _T_259; // @[el2_lsu_dccm_ctl.scala 208:44] - wire lsu_dccm_rden_d = _T_260 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 208:171] - wire _T_261 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 211:63] - wire _T_262 = ~lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 211:96] - wire _T_264 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[el2_lsu_dccm_ctl.scala 212:71] - wire _T_265 = _T_264 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 212:89] - wire _T_266 = ~_T_265; // @[el2_lsu_dccm_ctl.scala 212:53] - wire _T_269 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 213:107] - wire _T_272 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 214:88] - wire _T_273 = _T_269 | _T_272; // @[el2_lsu_dccm_ctl.scala 213:195] - wire _T_274 = ~_T_273; // @[el2_lsu_dccm_ctl.scala 213:24] - wire _T_275 = lsu_dccm_rden_d & _T_274; // @[el2_lsu_dccm_ctl.scala 213:22] - wire _T_276 = _T_266 | _T_275; // @[el2_lsu_dccm_ctl.scala 212:120] - wire _T_278 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[el2_lsu_dccm_ctl.scala 217:41] - wire [15:0] _T_285 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 220:8] - wire [15:0] _T_289 = io_dma_dccm_wen ? io_lsu_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 221:8] - wire [15:0] _T_295 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 223:8] - wire [15:0] _T_299 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 224:8] - wire _T_304 = ~ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 228:36] - wire [38:0] _T_307 = {7'h0,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58] - wire [38:0] _T_310 = {7'h0,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58] - wire [38:0] _T_311 = _T_304 ? _T_307 : _T_310; // @[el2_lsu_dccm_ctl.scala 228:8] - wire [38:0] _T_315 = {7'h0,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58] - wire [38:0] _T_318 = {7'h0,io_stbuf_data_any}; // @[Cat.scala 29:58] - wire [38:0] _T_319 = io_dma_dccm_wen ? _T_315 : _T_318; // @[el2_lsu_dccm_ctl.scala 230:8] - wire _T_322 = ~ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 234:36] - wire [38:0] _T_329 = _T_322 ? _T_310 : _T_307; // @[el2_lsu_dccm_ctl.scala 234:8] - wire [38:0] _T_333 = {7'h0,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58] - wire [38:0] _T_337 = io_dma_dccm_wen ? _T_333 : _T_318; // @[el2_lsu_dccm_ctl.scala 236:8] - wire [3:0] _T_340 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_342 = io_lsu_pkt_m_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_343 = _T_342 & 4'h1; // @[el2_lsu_dccm_ctl.scala 240:84] - wire [3:0] _T_345 = io_lsu_pkt_m_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_346 = _T_345 & 4'h3; // @[el2_lsu_dccm_ctl.scala 241:33] - wire [3:0] _T_347 = _T_343 | _T_346; // @[el2_lsu_dccm_ctl.scala 240:97] - wire [3:0] _T_349 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_351 = _T_347 | _T_349; // @[el2_lsu_dccm_ctl.scala 241:46] - wire [3:0] store_byteen_m = _T_340 & _T_351; // @[el2_lsu_dccm_ctl.scala 240:53] - wire [3:0] _T_353 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_355 = io_lsu_pkt_r_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_356 = _T_355 & 4'h1; // @[el2_lsu_dccm_ctl.scala 243:84] - wire [3:0] _T_358 = io_lsu_pkt_r_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_359 = _T_358 & 4'h3; // @[el2_lsu_dccm_ctl.scala 244:33] - wire [3:0] _T_360 = _T_356 | _T_359; // @[el2_lsu_dccm_ctl.scala 243:97] - wire [3:0] _T_362 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_364 = _T_360 | _T_362; // @[el2_lsu_dccm_ctl.scala 244:46] - wire [3:0] store_byteen_r = _T_353 & _T_364; // @[el2_lsu_dccm_ctl.scala 243:53] - wire [7:0] _T_366 = {4'h0,store_byteen_m}; // @[Cat.scala 29:58] - wire [10:0] _GEN_2 = {{3'd0}, _T_366}; // @[el2_lsu_dccm_ctl.scala 246:62] - wire [10:0] store_byteen_ext_m = _GEN_2 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 246:62] - wire [7:0] _T_369 = {4'h0,store_byteen_r}; // @[Cat.scala 29:58] - wire [10:0] _GEN_3 = {{3'd0}, _T_369}; // @[el2_lsu_dccm_ctl.scala 247:62] - wire [10:0] store_byteen_ext_r = _GEN_3 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 247:62] - wire _T_373 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 250:71] - wire dccm_wr_bypass_d_m_lo = _T_373 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 250:109] - wire _T_376 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 251:71] - wire dccm_wr_bypass_d_m_hi = _T_376 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 251:109] - wire _T_379 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 253:71] - wire dccm_wr_bypass_d_r_lo = _T_379 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 253:109] - wire [63:0] _T_385 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58] - wire [126:0] _GEN_5 = {{63'd0}, _T_385}; // @[el2_lsu_dccm_ctl.scala 287:72] - wire [126:0] _T_388 = _GEN_5 << _T_178; // @[el2_lsu_dccm_ctl.scala 287:72] - wire [63:0] store_data_pre_m = _T_388[63:0]; // @[el2_lsu_dccm_ctl.scala 287:29] - wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[el2_lsu_dccm_ctl.scala 288:48] - wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[el2_lsu_dccm_ctl.scala 289:48] - wire _T_394 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[el2_lsu_dccm_ctl.scala 290:195] - wire [7:0] _T_398 = _T_394 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[el2_lsu_dccm_ctl.scala 290:169] - wire [7:0] _T_399 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_398; // @[el2_lsu_dccm_ctl.scala 290:104] - wire [7:0] _T_407 = _T_394 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[el2_lsu_dccm_ctl.scala 290:169] - wire [7:0] _T_408 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_407; // @[el2_lsu_dccm_ctl.scala 290:104] - wire [7:0] _T_416 = _T_394 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[el2_lsu_dccm_ctl.scala 290:169] - wire [7:0] _T_417 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_416; // @[el2_lsu_dccm_ctl.scala 290:104] - wire [7:0] _T_425 = _T_394 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[el2_lsu_dccm_ctl.scala 290:169] - wire [7:0] _T_426 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_425; // @[el2_lsu_dccm_ctl.scala 290:104] - wire [15:0] _T_428 = {_T_417,_T_426}; // @[Cat.scala 29:58] - wire [15:0] _T_429 = {_T_399,_T_408}; // @[Cat.scala 29:58] - reg [31:0] _T_431; // @[el2_lsu_dccm_ctl.scala 290:72] - wire _T_435 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[el2_lsu_dccm_ctl.scala 291:195] - wire [7:0] _T_439 = _T_435 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[el2_lsu_dccm_ctl.scala 291:169] - wire [7:0] _T_440 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_439; // @[el2_lsu_dccm_ctl.scala 291:104] - wire [7:0] _T_448 = _T_435 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[el2_lsu_dccm_ctl.scala 291:169] - wire [7:0] _T_449 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_448; // @[el2_lsu_dccm_ctl.scala 291:104] - wire [7:0] _T_457 = _T_435 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[el2_lsu_dccm_ctl.scala 291:169] - wire [7:0] _T_458 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_457; // @[el2_lsu_dccm_ctl.scala 291:104] - wire [7:0] _T_466 = _T_435 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[el2_lsu_dccm_ctl.scala 291:169] - wire [7:0] _T_467 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_466; // @[el2_lsu_dccm_ctl.scala 291:104] - wire [15:0] _T_469 = {_T_458,_T_467}; // @[Cat.scala 29:58] - wire [15:0] _T_470 = {_T_440,_T_449}; // @[Cat.scala 29:58] - reg [31:0] _T_472; // @[el2_lsu_dccm_ctl.scala 291:72] - wire _T_473 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[el2_lsu_dccm_ctl.scala 292:89] - wire _T_475 = ~store_byteen_ext_r[0]; // @[el2_lsu_dccm_ctl.scala 292:115] - wire _T_476 = _T_473 & _T_475; // @[el2_lsu_dccm_ctl.scala 292:113] - wire [7:0] _T_480 = _T_476 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[el2_lsu_dccm_ctl.scala 292:63] - wire _T_483 = ~store_byteen_ext_r[1]; // @[el2_lsu_dccm_ctl.scala 292:115] - wire _T_484 = _T_473 & _T_483; // @[el2_lsu_dccm_ctl.scala 292:113] - wire [7:0] _T_488 = _T_484 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[el2_lsu_dccm_ctl.scala 292:63] - wire _T_491 = ~store_byteen_ext_r[2]; // @[el2_lsu_dccm_ctl.scala 292:115] - wire _T_492 = _T_473 & _T_491; // @[el2_lsu_dccm_ctl.scala 292:113] - wire [7:0] _T_496 = _T_492 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[el2_lsu_dccm_ctl.scala 292:63] - wire _T_499 = ~store_byteen_ext_r[3]; // @[el2_lsu_dccm_ctl.scala 292:115] - wire _T_500 = _T_473 & _T_499; // @[el2_lsu_dccm_ctl.scala 292:113] - wire [7:0] _T_504 = _T_500 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[el2_lsu_dccm_ctl.scala 292:63] - wire [15:0] _T_506 = {_T_496,_T_504}; // @[Cat.scala 29:58] - wire [15:0] _T_507 = {_T_480,_T_488}; // @[Cat.scala 29:58] - wire [7:0] _T_516 = _T_476 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 293:63] - wire [7:0] _T_524 = _T_484 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 293:63] - wire [7:0] _T_532 = _T_492 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 293:63] - wire [7:0] _T_540 = _T_500 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 293:63] - wire [15:0] _T_542 = {_T_532,_T_540}; // @[Cat.scala 29:58] - wire [15:0] _T_543 = {_T_516,_T_524}; // @[Cat.scala 29:58] - wire _T_577 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_dccm_ctl.scala 302:50] - wire _T_578 = _T_577 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 302:71] - wire _T_579 = _T_578 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 302:90] - wire _T_581 = io_lsu_pkt_d_valid & io_lsu_pkt_d_load; // @[el2_lsu_dccm_ctl.scala 303:50] - wire _T_583 = io_lsu_pkt_d_valid & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 304:50] - wire [5:0] _T_586 = 6'h20 - 6'h1; // @[el2_lsu_dccm_ctl.scala 306:58] - wire [20:0] _T_588 = {_T_586,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58] - wire [31:0] _GEN_8 = {{11'd0}, _T_588}; // @[el2_lsu_dccm_ctl.scala 306:47] - wire [14:0] _T_595 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 307:78] - wire [20:0] _T_596 = {_T_586,_T_595}; // @[Cat.scala 29:58] - wire [31:0] _GEN_9 = {{11'd0}, _T_596}; // @[el2_lsu_dccm_ctl.scala 307:47] - reg _T_603; // @[el2_lsu_dccm_ctl.scala 312:61] - rvclkhdr rvclkhdr ( // @[beh_lib.scala 351:21] + wire _T = io_lsu_pkt_m_valid & io_lsu_pkt_m_load; // @[el2_lsu_dccm_ctl.scala 161:50] + reg [63:0] _T_2; // @[el2_lsu_dccm_ctl.scala 171:65] + wire [7:0] _T_3 = {io_stbuf_fwdbyteen_hi_m,io_stbuf_fwdbyteen_lo_m}; // @[Cat.scala 29:58] + wire [63:0] _T_6 = {io_stbuf_fwddata_hi_m,io_stbuf_fwddata_lo_m}; // @[Cat.scala 29:58] + wire [7:0] _T_11 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_corr_m[7:0]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_12 = _T_3[0] ? _T_6[7:0] : _T_11; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_16 = {{4'd0}, _T_12[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_18 = {_T_12[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_20 = _T_18 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_21 = _T_16 | _T_20; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_0 = {{2'd0}, _T_21[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_26 = _GEN_0 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_28 = {_T_21[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_30 = _T_28 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_31 = _T_26 | _T_30; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_1 = {{1'd0}, _T_31[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_36 = _GEN_1 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_38 = {_T_31[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_40 = _T_38 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_41 = _T_36 | _T_40; // @[Bitwise.scala 103:39] + wire [7:0] _T_50 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_corr_m[15:8]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_51 = _T_3[1] ? _T_6[15:8] : _T_50; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_55 = {{4'd0}, _T_51[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_57 = {_T_51[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_59 = _T_57 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_60 = _T_55 | _T_59; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_2 = {{2'd0}, _T_60[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_65 = _GEN_2 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_67 = {_T_60[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_69 = _T_67 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_70 = _T_65 | _T_69; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_3 = {{1'd0}, _T_70[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_75 = _GEN_3 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_77 = {_T_70[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_79 = _T_77 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_80 = _T_75 | _T_79; // @[Bitwise.scala 103:39] + wire [7:0] _T_89 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_corr_m[23:16]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_90 = _T_3[2] ? _T_6[23:16] : _T_89; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_94 = {{4'd0}, _T_90[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_96 = {_T_90[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_98 = _T_96 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_99 = _T_94 | _T_98; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_4 = {{2'd0}, _T_99[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_104 = _GEN_4 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_106 = {_T_99[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_108 = _T_106 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_109 = _T_104 | _T_108; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_5 = {{1'd0}, _T_109[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_114 = _GEN_5 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_116 = {_T_109[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_118 = _T_116 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_119 = _T_114 | _T_118; // @[Bitwise.scala 103:39] + wire [7:0] _T_128 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_corr_m[31:24]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_129 = _T_3[3] ? _T_6[31:24] : _T_128; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_133 = {{4'd0}, _T_129[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_135 = {_T_129[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_137 = _T_135 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_138 = _T_133 | _T_137; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_6 = {{2'd0}, _T_138[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_143 = _GEN_6 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_145 = {_T_138[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_147 = _T_145 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_148 = _T_143 | _T_147; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_7 = {{1'd0}, _T_148[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_153 = _GEN_7 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_155 = {_T_148[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_157 = _T_155 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_158 = _T_153 | _T_157; // @[Bitwise.scala 103:39] + wire [7:0] _T_167 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_corr_m[39:32]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_168 = _T_3[4] ? _T_6[39:32] : _T_167; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_172 = {{4'd0}, _T_168[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_174 = {_T_168[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_176 = _T_174 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_177 = _T_172 | _T_176; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_8 = {{2'd0}, _T_177[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_182 = _GEN_8 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_184 = {_T_177[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_186 = _T_184 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_187 = _T_182 | _T_186; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_9 = {{1'd0}, _T_187[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_192 = _GEN_9 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_194 = {_T_187[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_196 = _T_194 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_197 = _T_192 | _T_196; // @[Bitwise.scala 103:39] + wire [7:0] _T_206 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_corr_m[47:40]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_207 = _T_3[5] ? _T_6[47:40] : _T_206; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_211 = {{4'd0}, _T_207[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_213 = {_T_207[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_215 = _T_213 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_216 = _T_211 | _T_215; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_10 = {{2'd0}, _T_216[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_221 = _GEN_10 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_223 = {_T_216[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_225 = _T_223 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_226 = _T_221 | _T_225; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_11 = {{1'd0}, _T_226[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_231 = _GEN_11 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_233 = {_T_226[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_235 = _T_233 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_236 = _T_231 | _T_235; // @[Bitwise.scala 103:39] + wire [7:0] _T_245 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_corr_m[55:48]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_246 = _T_3[6] ? _T_6[55:48] : _T_245; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_250 = {{4'd0}, _T_246[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_252 = {_T_246[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_254 = _T_252 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_255 = _T_250 | _T_254; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_12 = {{2'd0}, _T_255[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_260 = _GEN_12 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_262 = {_T_255[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_264 = _T_262 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_265 = _T_260 | _T_264; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_13 = {{1'd0}, _T_265[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_270 = _GEN_13 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_272 = {_T_265[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_274 = _T_272 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_275 = _T_270 | _T_274; // @[Bitwise.scala 103:39] + wire [7:0] _T_284 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_corr_m[63:56]; // @[el2_lsu_dccm_ctl.scala 172:213] + wire [7:0] _T_285 = _T_3[7] ? _T_6[63:56] : _T_284; // @[el2_lsu_dccm_ctl.scala 172:78] + wire [7:0] _T_289 = {{4'd0}, _T_285[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_291 = {_T_285[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_293 = _T_291 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_294 = _T_289 | _T_293; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_14 = {{2'd0}, _T_294[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_299 = _GEN_14 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_301 = {_T_294[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_303 = _T_301 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_304 = _T_299 | _T_303; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_15 = {{1'd0}, _T_304[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_309 = _GEN_15 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_311 = {_T_304[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_313 = _T_311 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_314 = _T_309 | _T_313; // @[Bitwise.scala 103:39] + wire [63:0] _T_322 = {_T_41,_T_80,_T_119,_T_158,_T_197,_T_236,_T_275,_T_314}; // @[Cat.scala 29:58] + wire [63:0] _T_326 = {{32'd0}, _T_322[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_328 = {_T_322[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_330 = _T_328 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_331 = _T_326 | _T_330; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_16 = {{16'd0}, _T_331[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_336 = _GEN_16 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_338 = {_T_331[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_340 = _T_338 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_341 = _T_336 | _T_340; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_17 = {{8'd0}, _T_341[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_346 = _GEN_17 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_348 = {_T_341[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_350 = _T_348 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_351 = _T_346 | _T_350; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_18 = {{4'd0}, _T_351[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_356 = _GEN_18 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_358 = {_T_351[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_360 = _T_358 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_361 = _T_356 | _T_360; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_19 = {{2'd0}, _T_361[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_366 = _GEN_19 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_368 = {_T_361[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_370 = _T_368 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_371 = _T_366 | _T_370; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_20 = {{1'd0}, _T_371[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_376 = _GEN_20 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_378 = {_T_371[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_380 = _T_378 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_corr_m = _T_376 | _T_380; // @[Bitwise.scala 103:39] + wire [7:0] _T_390 = io_addr_in_pic_m ? picm_rd_data_m[7:0] : dccm_rdata_m[7:0]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_391 = _T_3[0] ? _T_6[7:0] : _T_390; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_395 = {{4'd0}, _T_391[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_397 = {_T_391[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_399 = _T_397 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_400 = _T_395 | _T_399; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_21 = {{2'd0}, _T_400[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_405 = _GEN_21 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_407 = {_T_400[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_409 = _T_407 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_410 = _T_405 | _T_409; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_22 = {{1'd0}, _T_410[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_415 = _GEN_22 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_417 = {_T_410[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_419 = _T_417 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_420 = _T_415 | _T_419; // @[Bitwise.scala 103:39] + wire [7:0] _T_429 = io_addr_in_pic_m ? picm_rd_data_m[15:8] : dccm_rdata_m[15:8]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_430 = _T_3[1] ? _T_6[15:8] : _T_429; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_434 = {{4'd0}, _T_430[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_436 = {_T_430[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_438 = _T_436 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_439 = _T_434 | _T_438; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_23 = {{2'd0}, _T_439[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_444 = _GEN_23 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_446 = {_T_439[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_448 = _T_446 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_449 = _T_444 | _T_448; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_24 = {{1'd0}, _T_449[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_454 = _GEN_24 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_456 = {_T_449[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_458 = _T_456 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_459 = _T_454 | _T_458; // @[Bitwise.scala 103:39] + wire [7:0] _T_468 = io_addr_in_pic_m ? picm_rd_data_m[23:16] : dccm_rdata_m[23:16]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_469 = _T_3[2] ? _T_6[23:16] : _T_468; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_473 = {{4'd0}, _T_469[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_475 = {_T_469[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_477 = _T_475 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_478 = _T_473 | _T_477; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_25 = {{2'd0}, _T_478[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_483 = _GEN_25 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_485 = {_T_478[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_487 = _T_485 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_488 = _T_483 | _T_487; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_26 = {{1'd0}, _T_488[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_493 = _GEN_26 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_495 = {_T_488[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_497 = _T_495 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_498 = _T_493 | _T_497; // @[Bitwise.scala 103:39] + wire [7:0] _T_507 = io_addr_in_pic_m ? picm_rd_data_m[31:24] : dccm_rdata_m[31:24]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_508 = _T_3[3] ? _T_6[31:24] : _T_507; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_512 = {{4'd0}, _T_508[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_514 = {_T_508[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_516 = _T_514 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_517 = _T_512 | _T_516; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_27 = {{2'd0}, _T_517[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_522 = _GEN_27 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_524 = {_T_517[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_526 = _T_524 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_527 = _T_522 | _T_526; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_28 = {{1'd0}, _T_527[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_532 = _GEN_28 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_534 = {_T_527[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_536 = _T_534 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_537 = _T_532 | _T_536; // @[Bitwise.scala 103:39] + wire [7:0] _T_546 = io_addr_in_pic_m ? picm_rd_data_m[39:32] : dccm_rdata_m[39:32]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_547 = _T_3[4] ? _T_6[39:32] : _T_546; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_551 = {{4'd0}, _T_547[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_553 = {_T_547[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_555 = _T_553 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_556 = _T_551 | _T_555; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_29 = {{2'd0}, _T_556[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_561 = _GEN_29 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_563 = {_T_556[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_565 = _T_563 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_566 = _T_561 | _T_565; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_30 = {{1'd0}, _T_566[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_571 = _GEN_30 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_573 = {_T_566[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_575 = _T_573 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_576 = _T_571 | _T_575; // @[Bitwise.scala 103:39] + wire [7:0] _T_585 = io_addr_in_pic_m ? picm_rd_data_m[47:40] : dccm_rdata_m[47:40]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_586 = _T_3[5] ? _T_6[47:40] : _T_585; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_590 = {{4'd0}, _T_586[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_592 = {_T_586[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_594 = _T_592 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_595 = _T_590 | _T_594; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_31 = {{2'd0}, _T_595[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_600 = _GEN_31 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_602 = {_T_595[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_604 = _T_602 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_605 = _T_600 | _T_604; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_32 = {{1'd0}, _T_605[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_610 = _GEN_32 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_612 = {_T_605[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_614 = _T_612 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_615 = _T_610 | _T_614; // @[Bitwise.scala 103:39] + wire [7:0] _T_624 = io_addr_in_pic_m ? picm_rd_data_m[55:48] : dccm_rdata_m[55:48]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_625 = _T_3[6] ? _T_6[55:48] : _T_624; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_629 = {{4'd0}, _T_625[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_631 = {_T_625[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_633 = _T_631 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_634 = _T_629 | _T_633; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_33 = {{2'd0}, _T_634[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_639 = _GEN_33 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_641 = {_T_634[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_643 = _T_641 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_644 = _T_639 | _T_643; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_34 = {{1'd0}, _T_644[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_649 = _GEN_34 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_651 = {_T_644[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_653 = _T_651 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_654 = _T_649 | _T_653; // @[Bitwise.scala 103:39] + wire [7:0] _T_663 = io_addr_in_pic_m ? picm_rd_data_m[63:56] : dccm_rdata_m[63:56]; // @[el2_lsu_dccm_ctl.scala 173:213] + wire [7:0] _T_664 = _T_3[7] ? _T_6[63:56] : _T_663; // @[el2_lsu_dccm_ctl.scala 173:78] + wire [7:0] _T_668 = {{4'd0}, _T_664[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_670 = {_T_664[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_672 = _T_670 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_673 = _T_668 | _T_672; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_35 = {{2'd0}, _T_673[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_678 = _GEN_35 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_680 = {_T_673[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_682 = _T_680 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_683 = _T_678 | _T_682; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_36 = {{1'd0}, _T_683[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_688 = _GEN_36 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_690 = {_T_683[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_692 = _T_690 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_693 = _T_688 | _T_692; // @[Bitwise.scala 103:39] + wire [63:0] _T_701 = {_T_420,_T_459,_T_498,_T_537,_T_576,_T_615,_T_654,_T_693}; // @[Cat.scala 29:58] + wire [63:0] _T_705 = {{32'd0}, _T_701[63:32]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_707 = {_T_701[31:0], 32'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_709 = _T_707 & 64'hffffffff00000000; // @[Bitwise.scala 103:75] + wire [63:0] _T_710 = _T_705 | _T_709; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_37 = {{16'd0}, _T_710[63:16]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_715 = _GEN_37 & 64'hffff0000ffff; // @[Bitwise.scala 103:31] + wire [63:0] _T_717 = {_T_710[47:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_719 = _T_717 & 64'hffff0000ffff0000; // @[Bitwise.scala 103:75] + wire [63:0] _T_720 = _T_715 | _T_719; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_38 = {{8'd0}, _T_720[63:8]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_725 = _GEN_38 & 64'hff00ff00ff00ff; // @[Bitwise.scala 103:31] + wire [63:0] _T_727 = {_T_720[55:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_729 = _T_727 & 64'hff00ff00ff00ff00; // @[Bitwise.scala 103:75] + wire [63:0] _T_730 = _T_725 | _T_729; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_39 = {{4'd0}, _T_730[63:4]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_735 = _GEN_39 & 64'hf0f0f0f0f0f0f0f; // @[Bitwise.scala 103:31] + wire [63:0] _T_737 = {_T_730[59:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_739 = _T_737 & 64'hf0f0f0f0f0f0f0f0; // @[Bitwise.scala 103:75] + wire [63:0] _T_740 = _T_735 | _T_739; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_40 = {{2'd0}, _T_740[63:2]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_745 = _GEN_40 & 64'h3333333333333333; // @[Bitwise.scala 103:31] + wire [63:0] _T_747 = {_T_740[61:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_749 = _T_747 & 64'hcccccccccccccccc; // @[Bitwise.scala 103:75] + wire [63:0] _T_750 = _T_745 | _T_749; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_41 = {{1'd0}, _T_750[63:1]}; // @[Bitwise.scala 103:31] + wire [63:0] _T_755 = _GEN_41 & 64'h5555555555555555; // @[Bitwise.scala 103:31] + wire [63:0] _T_757 = {_T_750[62:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [63:0] _T_759 = _T_757 & 64'haaaaaaaaaaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] lsu_rdata_m = _T_755 | _T_759; // @[Bitwise.scala 103:39] + wire [3:0] _GEN_42 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_dccm_ctl.scala 174:49] + wire [5:0] _T_762 = 4'h8 * _GEN_42; // @[el2_lsu_dccm_ctl.scala 174:49] + wire [63:0] _T_763 = lsu_rdata_m >> _T_762; // @[el2_lsu_dccm_ctl.scala 174:43] + wire _T_769 = io_lsu_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 179:60] + wire _T_772 = io_end_addr_d[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 179:133] + wire _T_773 = _T_769 | _T_772; // @[el2_lsu_dccm_ctl.scala 179:101] + wire _T_774 = _T_773 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 179:175] + wire _T_775 = _T_774 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 179:196] + wire _T_776 = _T_775 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 179:217] + wire _T_777 = _T_776 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 179:236] + wire _T_780 = io_lsu_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:37] + wire _T_783 = io_end_addr_m[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 180:110] + wire _T_784 = _T_780 | _T_783; // @[el2_lsu_dccm_ctl.scala 180:78] + wire _T_785 = _T_784 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 180:152] + wire _T_786 = _T_785 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 180:173] + wire _T_787 = _T_786 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 180:194] + wire _T_788 = _T_787 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 180:213] + wire kill_ecc_corr_lo_r = _T_777 | _T_788; // @[el2_lsu_dccm_ctl.scala 179:257] + wire _T_791 = io_lsu_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:60] + wire _T_794 = io_end_addr_d[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 182:133] + wire _T_795 = _T_791 | _T_794; // @[el2_lsu_dccm_ctl.scala 182:101] + wire _T_796 = _T_795 & io_lsu_pkt_d_valid; // @[el2_lsu_dccm_ctl.scala 182:175] + wire _T_797 = _T_796 & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 182:196] + wire _T_798 = _T_797 & io_lsu_pkt_d_dma; // @[el2_lsu_dccm_ctl.scala 182:217] + wire _T_799 = _T_798 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 182:236] + wire _T_802 = io_lsu_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:37] + wire _T_805 = io_end_addr_m[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 183:110] + wire _T_806 = _T_802 | _T_805; // @[el2_lsu_dccm_ctl.scala 183:78] + wire _T_807 = _T_806 & io_lsu_pkt_m_valid; // @[el2_lsu_dccm_ctl.scala 183:152] + wire _T_808 = _T_807 & io_lsu_pkt_m_store; // @[el2_lsu_dccm_ctl.scala 183:173] + wire _T_809 = _T_808 & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 183:194] + wire _T_810 = _T_809 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 183:213] + wire kill_ecc_corr_hi_r = _T_799 | _T_810; // @[el2_lsu_dccm_ctl.scala 182:257] + wire _T_811 = io_lsu_pkt_r_load & io_single_ecc_error_lo_r; // @[el2_lsu_dccm_ctl.scala 185:55] + wire _T_812 = ~io_lsu_raw_fwd_lo_r; // @[el2_lsu_dccm_ctl.scala 185:84] + wire ld_single_ecc_error_lo_r = _T_811 & _T_812; // @[el2_lsu_dccm_ctl.scala 185:82] + wire _T_813 = io_lsu_pkt_r_load & io_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 186:55] + wire _T_814 = ~io_lsu_raw_fwd_hi_r; // @[el2_lsu_dccm_ctl.scala 186:84] + wire ld_single_ecc_error_hi_r = _T_813 & _T_814; // @[el2_lsu_dccm_ctl.scala 186:82] + wire _T_815 = ld_single_ecc_error_lo_r | ld_single_ecc_error_hi_r; // @[el2_lsu_dccm_ctl.scala 187:63] + wire _T_816 = ~io_lsu_double_ecc_error_r; // @[el2_lsu_dccm_ctl.scala 187:93] + wire _T_818 = io_lsu_commit_r | io_lsu_pkt_r_dma; // @[el2_lsu_dccm_ctl.scala 188:81] + wire _T_819 = ld_single_ecc_error_lo_r & _T_818; // @[el2_lsu_dccm_ctl.scala 188:62] + wire _T_820 = ~kill_ecc_corr_lo_r; // @[el2_lsu_dccm_ctl.scala 188:103] + wire _T_822 = ld_single_ecc_error_hi_r & _T_818; // @[el2_lsu_dccm_ctl.scala 189:62] + wire _T_823 = ~kill_ecc_corr_hi_r; // @[el2_lsu_dccm_ctl.scala 189:103] + reg lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 191:74] + reg ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 192:74] + reg ld_single_ecc_error_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 193:74] + reg [15:0] ld_sec_addr_hi_r_ff; // @[el2_lib.scala 514:16] + reg [15:0] ld_sec_addr_lo_r_ff; // @[el2_lib.scala 514:16] + wire _T_830 = io_lsu_pkt_d_word | io_lsu_pkt_d_dword; // @[el2_lsu_dccm_ctl.scala 197:110] + wire _T_831 = ~_T_830; // @[el2_lsu_dccm_ctl.scala 197:90] + wire _T_833 = io_lsu_addr_d[1:0] != 2'h0; // @[el2_lsu_dccm_ctl.scala 197:154] + wire _T_834 = _T_831 | _T_833; // @[el2_lsu_dccm_ctl.scala 197:132] + wire _T_835 = io_lsu_pkt_d_store & _T_834; // @[el2_lsu_dccm_ctl.scala 197:87] + wire _T_836 = io_lsu_pkt_d_load | _T_835; // @[el2_lsu_dccm_ctl.scala 197:65] + wire _T_837 = io_lsu_pkt_d_valid & _T_836; // @[el2_lsu_dccm_ctl.scala 197:44] + wire lsu_dccm_rden_d = _T_837 & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 197:171] + wire _T_838 = ld_single_ecc_error_lo_r_ff | ld_single_ecc_error_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 200:63] + wire _T_839 = ~lsu_double_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 200:96] + wire _T_841 = lsu_dccm_rden_d | io_dma_dccm_wen; // @[el2_lsu_dccm_ctl.scala 201:75] + wire _T_842 = _T_841 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 201:93] + wire _T_843 = ~_T_842; // @[el2_lsu_dccm_ctl.scala 201:57] + wire _T_846 = io_stbuf_addr_any[3:2] == io_lsu_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 202:95] + wire _T_849 = io_stbuf_addr_any[3:2] == io_end_addr_d[3:2]; // @[el2_lsu_dccm_ctl.scala 203:76] + wire _T_850 = _T_846 | _T_849; // @[el2_lsu_dccm_ctl.scala 202:171] + wire _T_851 = ~_T_850; // @[el2_lsu_dccm_ctl.scala 202:24] + wire _T_852 = lsu_dccm_rden_d & _T_851; // @[el2_lsu_dccm_ctl.scala 202:22] + wire _T_853 = _T_843 | _T_852; // @[el2_lsu_dccm_ctl.scala 201:124] + wire _T_855 = io_dma_dccm_wen | io_lsu_stbuf_commit_any; // @[el2_lsu_dccm_ctl.scala 207:41] + wire [15:0] _T_862 = ld_single_ecc_error_lo_r_ff ? ld_sec_addr_lo_r_ff : ld_sec_addr_hi_r_ff; // @[el2_lsu_dccm_ctl.scala 211:8] + wire [15:0] _T_866 = io_dma_dccm_wen ? io_lsu_addr_d[15:0] : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 212:8] + wire [15:0] _T_872 = ld_single_ecc_error_hi_r_ff ? ld_sec_addr_hi_r_ff : ld_sec_addr_lo_r_ff; // @[el2_lsu_dccm_ctl.scala 215:8] + wire [15:0] _T_876 = io_dma_dccm_wen ? io_end_addr_d : io_stbuf_addr_any; // @[el2_lsu_dccm_ctl.scala 216:8] + wire [38:0] _T_884 = {io_sec_data_ecc_lo_r_ff,io_sec_data_lo_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_887 = {io_sec_data_ecc_hi_r_ff,io_sec_data_hi_r_ff}; // @[Cat.scala 29:58] + wire [38:0] _T_888 = ld_single_ecc_error_lo_r_ff ? _T_884 : _T_887; // @[el2_lsu_dccm_ctl.scala 222:8] + wire [38:0] _T_892 = {io_dma_dccm_wdata_ecc_lo,io_dma_dccm_wdata_lo}; // @[Cat.scala 29:58] + wire [38:0] _T_895 = {io_stbuf_ecc_any,io_stbuf_data_any}; // @[Cat.scala 29:58] + wire [38:0] _T_896 = io_dma_dccm_wen ? _T_892 : _T_895; // @[el2_lsu_dccm_ctl.scala 224:8] + wire [38:0] _T_906 = ld_single_ecc_error_hi_r_ff ? _T_887 : _T_884; // @[el2_lsu_dccm_ctl.scala 228:8] + wire [38:0] _T_910 = {io_dma_dccm_wdata_ecc_hi,io_dma_dccm_wdata_hi}; // @[Cat.scala 29:58] + wire [38:0] _T_914 = io_dma_dccm_wen ? _T_910 : _T_895; // @[el2_lsu_dccm_ctl.scala 230:8] + wire [3:0] _T_917 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_919 = io_lsu_pkt_m_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_920 = _T_919 & 4'h1; // @[el2_lsu_dccm_ctl.scala 234:84] + wire [3:0] _T_922 = io_lsu_pkt_m_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_923 = _T_922 & 4'h3; // @[el2_lsu_dccm_ctl.scala 235:33] + wire [3:0] _T_924 = _T_920 | _T_923; // @[el2_lsu_dccm_ctl.scala 234:97] + wire [3:0] _T_926 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_928 = _T_924 | _T_926; // @[el2_lsu_dccm_ctl.scala 235:46] + wire [3:0] store_byteen_m = _T_917 & _T_928; // @[el2_lsu_dccm_ctl.scala 234:53] + wire [3:0] _T_930 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_932 = io_lsu_pkt_r_by ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_933 = _T_932 & 4'h1; // @[el2_lsu_dccm_ctl.scala 238:84] + wire [3:0] _T_935 = io_lsu_pkt_r_half ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_936 = _T_935 & 4'h3; // @[el2_lsu_dccm_ctl.scala 239:33] + wire [3:0] _T_937 = _T_933 | _T_936; // @[el2_lsu_dccm_ctl.scala 238:97] + wire [3:0] _T_939 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_941 = _T_937 | _T_939; // @[el2_lsu_dccm_ctl.scala 239:46] + wire [3:0] store_byteen_r = _T_930 & _T_941; // @[el2_lsu_dccm_ctl.scala 238:53] + wire [6:0] _GEN_44 = {{3'd0}, store_byteen_m}; // @[el2_lsu_dccm_ctl.scala 242:45] + wire [6:0] _T_944 = _GEN_44 << io_lsu_addr_m[1:0]; // @[el2_lsu_dccm_ctl.scala 242:45] + wire [6:0] _GEN_45 = {{3'd0}, store_byteen_r}; // @[el2_lsu_dccm_ctl.scala 244:45] + wire [6:0] _T_947 = _GEN_45 << io_lsu_addr_r[1:0]; // @[el2_lsu_dccm_ctl.scala 244:45] + wire _T_950 = io_stbuf_addr_any[15:2] == io_lsu_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 247:67] + wire dccm_wr_bypass_d_m_lo = _T_950 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 247:101] + wire _T_953 = io_stbuf_addr_any[15:2] == io_end_addr_m[15:2]; // @[el2_lsu_dccm_ctl.scala 248:67] + wire dccm_wr_bypass_d_m_hi = _T_953 & io_addr_in_dccm_m; // @[el2_lsu_dccm_ctl.scala 248:101] + wire _T_956 = io_stbuf_addr_any[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 250:67] + wire dccm_wr_bypass_d_r_lo = _T_956 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 250:101] + wire _T_959 = io_stbuf_addr_any[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_dccm_ctl.scala 251:67] + wire dccm_wr_bypass_d_r_hi = _T_959 & io_addr_in_dccm_r; // @[el2_lsu_dccm_ctl.scala 251:101] + wire [63:0] _T_962 = {32'h0,io_store_data_m}; // @[Cat.scala 29:58] + wire [126:0] _GEN_47 = {{63'd0}, _T_962}; // @[el2_lsu_dccm_ctl.scala 280:72] + wire [126:0] _T_965 = _GEN_47 << _T_762; // @[el2_lsu_dccm_ctl.scala 280:72] + wire [63:0] store_data_pre_m = _T_965[63:0]; // @[el2_lsu_dccm_ctl.scala 280:29] + wire [31:0] store_data_hi_m = store_data_pre_m[63:32]; // @[el2_lsu_dccm_ctl.scala 281:48] + wire [31:0] store_data_lo_m = store_data_pre_m[31:0]; // @[el2_lsu_dccm_ctl.scala 282:48] + wire [7:0] store_byteen_ext_m = {{1'd0}, _T_944}; // @[el2_lsu_dccm_ctl.scala 242:22] + wire _T_971 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo; // @[el2_lsu_dccm_ctl.scala 283:211] + wire [7:0] _T_975 = _T_971 ? io_stbuf_data_any[7:0] : io_sec_data_lo_m[7:0]; // @[el2_lsu_dccm_ctl.scala 283:185] + wire [7:0] _T_976 = store_byteen_ext_m[0] ? store_data_lo_m[7:0] : _T_975; // @[el2_lsu_dccm_ctl.scala 283:120] + wire [7:0] _T_980 = {{4'd0}, _T_976[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_982 = {_T_976[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_984 = _T_982 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_985 = _T_980 | _T_984; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_48 = {{2'd0}, _T_985[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_990 = _GEN_48 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_992 = {_T_985[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_994 = _T_992 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_995 = _T_990 | _T_994; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_49 = {{1'd0}, _T_995[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1000 = _GEN_49 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1002 = {_T_995[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1004 = _T_1002 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1005 = _T_1000 | _T_1004; // @[Bitwise.scala 103:39] + wire [7:0] _T_1013 = _T_971 ? io_stbuf_data_any[15:8] : io_sec_data_lo_m[15:8]; // @[el2_lsu_dccm_ctl.scala 283:185] + wire [7:0] _T_1014 = store_byteen_ext_m[1] ? store_data_lo_m[15:8] : _T_1013; // @[el2_lsu_dccm_ctl.scala 283:120] + wire [7:0] _T_1018 = {{4'd0}, _T_1014[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1020 = {_T_1014[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1022 = _T_1020 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1023 = _T_1018 | _T_1022; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_50 = {{2'd0}, _T_1023[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1028 = _GEN_50 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1030 = {_T_1023[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1032 = _T_1030 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1033 = _T_1028 | _T_1032; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_51 = {{1'd0}, _T_1033[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1038 = _GEN_51 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1040 = {_T_1033[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1042 = _T_1040 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1043 = _T_1038 | _T_1042; // @[Bitwise.scala 103:39] + wire [7:0] _T_1051 = _T_971 ? io_stbuf_data_any[23:16] : io_sec_data_lo_m[23:16]; // @[el2_lsu_dccm_ctl.scala 283:185] + wire [7:0] _T_1052 = store_byteen_ext_m[2] ? store_data_lo_m[23:16] : _T_1051; // @[el2_lsu_dccm_ctl.scala 283:120] + wire [7:0] _T_1056 = {{4'd0}, _T_1052[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1058 = {_T_1052[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1060 = _T_1058 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1061 = _T_1056 | _T_1060; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_52 = {{2'd0}, _T_1061[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1066 = _GEN_52 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1068 = {_T_1061[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1070 = _T_1068 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1071 = _T_1066 | _T_1070; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_53 = {{1'd0}, _T_1071[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1076 = _GEN_53 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1078 = {_T_1071[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1080 = _T_1078 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1081 = _T_1076 | _T_1080; // @[Bitwise.scala 103:39] + wire [7:0] _T_1089 = _T_971 ? io_stbuf_data_any[31:24] : io_sec_data_lo_m[31:24]; // @[el2_lsu_dccm_ctl.scala 283:185] + wire [7:0] _T_1090 = store_byteen_ext_m[3] ? store_data_lo_m[31:24] : _T_1089; // @[el2_lsu_dccm_ctl.scala 283:120] + wire [7:0] _T_1094 = {{4'd0}, _T_1090[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1096 = {_T_1090[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1098 = _T_1096 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1099 = _T_1094 | _T_1098; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_54 = {{2'd0}, _T_1099[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1104 = _GEN_54 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1106 = {_T_1099[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1108 = _T_1106 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1109 = _T_1104 | _T_1108; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_55 = {{1'd0}, _T_1109[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1114 = _GEN_55 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1116 = {_T_1109[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1118 = _T_1116 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1119 = _T_1114 | _T_1118; // @[Bitwise.scala 103:39] + wire [31:0] _T_1123 = {_T_1005,_T_1043,_T_1081,_T_1119}; // @[Cat.scala 29:58] + wire [31:0] _T_1127 = {{16'd0}, _T_1123[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1129 = {_T_1123[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1131 = _T_1129 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1132 = _T_1127 | _T_1131; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_56 = {{8'd0}, _T_1132[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1137 = _GEN_56 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1139 = {_T_1132[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1141 = _T_1139 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1142 = _T_1137 | _T_1141; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_57 = {{4'd0}, _T_1142[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1147 = _GEN_57 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1149 = {_T_1142[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1151 = _T_1149 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1152 = _T_1147 | _T_1151; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_58 = {{2'd0}, _T_1152[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1157 = _GEN_58 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1159 = {_T_1152[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1161 = _T_1159 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1162 = _T_1157 | _T_1161; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_59 = {{1'd0}, _T_1162[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1167 = _GEN_59 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1169 = {_T_1162[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1171 = _T_1169 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1173; // @[el2_lsu_dccm_ctl.scala 283:72] + wire _T_1177 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi; // @[el2_lsu_dccm_ctl.scala 284:211] + wire [7:0] _T_1181 = _T_1177 ? io_stbuf_data_any[7:0] : io_sec_data_hi_m[7:0]; // @[el2_lsu_dccm_ctl.scala 284:185] + wire [7:0] _T_1182 = store_byteen_ext_m[4] ? store_data_hi_m[7:0] : _T_1181; // @[el2_lsu_dccm_ctl.scala 284:120] + wire [7:0] _T_1186 = {{4'd0}, _T_1182[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1188 = {_T_1182[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1190 = _T_1188 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1191 = _T_1186 | _T_1190; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_60 = {{2'd0}, _T_1191[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1196 = _GEN_60 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1198 = {_T_1191[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1200 = _T_1198 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1201 = _T_1196 | _T_1200; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_61 = {{1'd0}, _T_1201[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1206 = _GEN_61 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1208 = {_T_1201[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1210 = _T_1208 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1211 = _T_1206 | _T_1210; // @[Bitwise.scala 103:39] + wire [7:0] _T_1219 = _T_1177 ? io_stbuf_data_any[15:8] : io_sec_data_hi_m[15:8]; // @[el2_lsu_dccm_ctl.scala 284:185] + wire [7:0] _T_1220 = store_byteen_ext_m[5] ? store_data_hi_m[15:8] : _T_1219; // @[el2_lsu_dccm_ctl.scala 284:120] + wire [7:0] _T_1224 = {{4'd0}, _T_1220[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1226 = {_T_1220[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1228 = _T_1226 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1229 = _T_1224 | _T_1228; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_62 = {{2'd0}, _T_1229[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1234 = _GEN_62 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1236 = {_T_1229[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1238 = _T_1236 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1239 = _T_1234 | _T_1238; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_63 = {{1'd0}, _T_1239[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1244 = _GEN_63 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1246 = {_T_1239[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1248 = _T_1246 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1249 = _T_1244 | _T_1248; // @[Bitwise.scala 103:39] + wire [7:0] _T_1257 = _T_1177 ? io_stbuf_data_any[23:16] : io_sec_data_hi_m[23:16]; // @[el2_lsu_dccm_ctl.scala 284:185] + wire [7:0] _T_1258 = store_byteen_ext_m[6] ? store_data_hi_m[23:16] : _T_1257; // @[el2_lsu_dccm_ctl.scala 284:120] + wire [7:0] _T_1262 = {{4'd0}, _T_1258[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1264 = {_T_1258[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1266 = _T_1264 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1267 = _T_1262 | _T_1266; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_64 = {{2'd0}, _T_1267[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1272 = _GEN_64 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1274 = {_T_1267[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1276 = _T_1274 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1277 = _T_1272 | _T_1276; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_65 = {{1'd0}, _T_1277[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1282 = _GEN_65 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1284 = {_T_1277[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1286 = _T_1284 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1287 = _T_1282 | _T_1286; // @[Bitwise.scala 103:39] + wire [7:0] _T_1295 = _T_1177 ? io_stbuf_data_any[31:24] : io_sec_data_hi_m[31:24]; // @[el2_lsu_dccm_ctl.scala 284:185] + wire [7:0] _T_1296 = store_byteen_ext_m[7] ? store_data_hi_m[31:24] : _T_1295; // @[el2_lsu_dccm_ctl.scala 284:120] + wire [7:0] _T_1300 = {{4'd0}, _T_1296[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1302 = {_T_1296[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1304 = _T_1302 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1305 = _T_1300 | _T_1304; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_66 = {{2'd0}, _T_1305[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1310 = _GEN_66 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1312 = {_T_1305[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1314 = _T_1312 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1315 = _T_1310 | _T_1314; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_67 = {{1'd0}, _T_1315[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1320 = _GEN_67 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1322 = {_T_1315[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1324 = _T_1322 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1325 = _T_1320 | _T_1324; // @[Bitwise.scala 103:39] + wire [31:0] _T_1329 = {_T_1211,_T_1249,_T_1287,_T_1325}; // @[Cat.scala 29:58] + wire [31:0] _T_1333 = {{16'd0}, _T_1329[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1335 = {_T_1329[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1337 = _T_1335 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1338 = _T_1333 | _T_1337; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_68 = {{8'd0}, _T_1338[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1343 = _GEN_68 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1345 = {_T_1338[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1347 = _T_1345 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1348 = _T_1343 | _T_1347; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_69 = {{4'd0}, _T_1348[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1353 = _GEN_69 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1355 = {_T_1348[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1357 = _T_1355 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1358 = _T_1353 | _T_1357; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_70 = {{2'd0}, _T_1358[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1363 = _GEN_70 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1365 = {_T_1358[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1367 = _T_1365 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1368 = _T_1363 | _T_1367; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_71 = {{1'd0}, _T_1368[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1373 = _GEN_71 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1375 = {_T_1368[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1377 = _T_1375 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + reg [31:0] _T_1379; // @[el2_lsu_dccm_ctl.scala 284:72] + wire _T_1380 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo; // @[el2_lsu_dccm_ctl.scala 285:105] + wire [7:0] store_byteen_ext_r = {{1'd0}, _T_947}; // @[el2_lsu_dccm_ctl.scala 244:22] + wire _T_1382 = ~store_byteen_ext_r[0]; // @[el2_lsu_dccm_ctl.scala 285:131] + wire _T_1383 = _T_1380 & _T_1382; // @[el2_lsu_dccm_ctl.scala 285:129] + wire [7:0] _T_1387 = _T_1383 ? io_stbuf_data_any[7:0] : io_store_data_lo_r[7:0]; // @[el2_lsu_dccm_ctl.scala 285:79] + wire [7:0] _T_1391 = {{4'd0}, _T_1387[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1393 = {_T_1387[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1395 = _T_1393 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1396 = _T_1391 | _T_1395; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_72 = {{2'd0}, _T_1396[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1401 = _GEN_72 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1403 = {_T_1396[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1405 = _T_1403 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1406 = _T_1401 | _T_1405; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_73 = {{1'd0}, _T_1406[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1411 = _GEN_73 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1413 = {_T_1406[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1415 = _T_1413 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1416 = _T_1411 | _T_1415; // @[Bitwise.scala 103:39] + wire _T_1419 = ~store_byteen_ext_r[1]; // @[el2_lsu_dccm_ctl.scala 285:131] + wire _T_1420 = _T_1380 & _T_1419; // @[el2_lsu_dccm_ctl.scala 285:129] + wire [7:0] _T_1424 = _T_1420 ? io_stbuf_data_any[15:8] : io_store_data_lo_r[15:8]; // @[el2_lsu_dccm_ctl.scala 285:79] + wire [7:0] _T_1428 = {{4'd0}, _T_1424[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1430 = {_T_1424[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1432 = _T_1430 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1433 = _T_1428 | _T_1432; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_74 = {{2'd0}, _T_1433[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1438 = _GEN_74 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1440 = {_T_1433[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1442 = _T_1440 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1443 = _T_1438 | _T_1442; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_75 = {{1'd0}, _T_1443[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1448 = _GEN_75 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1450 = {_T_1443[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1452 = _T_1450 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1453 = _T_1448 | _T_1452; // @[Bitwise.scala 103:39] + wire _T_1456 = ~store_byteen_ext_r[2]; // @[el2_lsu_dccm_ctl.scala 285:131] + wire _T_1457 = _T_1380 & _T_1456; // @[el2_lsu_dccm_ctl.scala 285:129] + wire [7:0] _T_1461 = _T_1457 ? io_stbuf_data_any[23:16] : io_store_data_lo_r[23:16]; // @[el2_lsu_dccm_ctl.scala 285:79] + wire [7:0] _T_1465 = {{4'd0}, _T_1461[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1467 = {_T_1461[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1469 = _T_1467 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1470 = _T_1465 | _T_1469; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_76 = {{2'd0}, _T_1470[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1475 = _GEN_76 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1477 = {_T_1470[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1479 = _T_1477 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1480 = _T_1475 | _T_1479; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_77 = {{1'd0}, _T_1480[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1485 = _GEN_77 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1487 = {_T_1480[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1489 = _T_1487 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1490 = _T_1485 | _T_1489; // @[Bitwise.scala 103:39] + wire _T_1493 = ~store_byteen_ext_r[3]; // @[el2_lsu_dccm_ctl.scala 285:131] + wire _T_1494 = _T_1380 & _T_1493; // @[el2_lsu_dccm_ctl.scala 285:129] + wire [7:0] _T_1498 = _T_1494 ? io_stbuf_data_any[31:24] : io_store_data_lo_r[31:24]; // @[el2_lsu_dccm_ctl.scala 285:79] + wire [7:0] _T_1502 = {{4'd0}, _T_1498[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1504 = {_T_1498[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1506 = _T_1504 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1507 = _T_1502 | _T_1506; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_78 = {{2'd0}, _T_1507[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1512 = _GEN_78 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1514 = {_T_1507[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1516 = _T_1514 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1517 = _T_1512 | _T_1516; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_79 = {{1'd0}, _T_1517[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1522 = _GEN_79 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1524 = {_T_1517[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1526 = _T_1524 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1527 = _T_1522 | _T_1526; // @[Bitwise.scala 103:39] + wire [31:0] _T_1531 = {_T_1416,_T_1453,_T_1490,_T_1527}; // @[Cat.scala 29:58] + wire [31:0] _T_1535 = {{16'd0}, _T_1531[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1537 = {_T_1531[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1539 = _T_1537 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1540 = _T_1535 | _T_1539; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_80 = {{8'd0}, _T_1540[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1545 = _GEN_80 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1547 = {_T_1540[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1549 = _T_1547 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1550 = _T_1545 | _T_1549; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_81 = {{4'd0}, _T_1550[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1555 = _GEN_81 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1557 = {_T_1550[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1559 = _T_1557 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1560 = _T_1555 | _T_1559; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_82 = {{2'd0}, _T_1560[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1565 = _GEN_82 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1567 = {_T_1560[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1569 = _T_1567 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1570 = _T_1565 | _T_1569; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_83 = {{1'd0}, _T_1570[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1575 = _GEN_83 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1577 = {_T_1570[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1579 = _T_1577 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire _T_1581 = io_lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi; // @[el2_lsu_dccm_ctl.scala 286:105] + wire _T_1583 = ~store_byteen_ext_r[4]; // @[el2_lsu_dccm_ctl.scala 286:131] + wire _T_1584 = _T_1581 & _T_1583; // @[el2_lsu_dccm_ctl.scala 286:129] + wire [7:0] _T_1588 = _T_1584 ? io_stbuf_data_any[7:0] : io_store_data_hi_r[7:0]; // @[el2_lsu_dccm_ctl.scala 286:79] + wire [7:0] _T_1592 = {{4'd0}, _T_1588[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1594 = {_T_1588[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1596 = _T_1594 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1597 = _T_1592 | _T_1596; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_84 = {{2'd0}, _T_1597[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1602 = _GEN_84 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1604 = {_T_1597[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1606 = _T_1604 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1607 = _T_1602 | _T_1606; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_85 = {{1'd0}, _T_1607[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1612 = _GEN_85 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1614 = {_T_1607[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1616 = _T_1614 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1617 = _T_1612 | _T_1616; // @[Bitwise.scala 103:39] + wire _T_1620 = ~store_byteen_ext_r[5]; // @[el2_lsu_dccm_ctl.scala 286:131] + wire _T_1621 = _T_1581 & _T_1620; // @[el2_lsu_dccm_ctl.scala 286:129] + wire [7:0] _T_1625 = _T_1621 ? io_stbuf_data_any[15:8] : io_store_data_hi_r[15:8]; // @[el2_lsu_dccm_ctl.scala 286:79] + wire [7:0] _T_1629 = {{4'd0}, _T_1625[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1631 = {_T_1625[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1633 = _T_1631 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1634 = _T_1629 | _T_1633; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_86 = {{2'd0}, _T_1634[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1639 = _GEN_86 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1641 = {_T_1634[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1643 = _T_1641 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1644 = _T_1639 | _T_1643; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_87 = {{1'd0}, _T_1644[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1649 = _GEN_87 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1651 = {_T_1644[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1653 = _T_1651 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1654 = _T_1649 | _T_1653; // @[Bitwise.scala 103:39] + wire _T_1657 = ~store_byteen_ext_r[6]; // @[el2_lsu_dccm_ctl.scala 286:131] + wire _T_1658 = _T_1581 & _T_1657; // @[el2_lsu_dccm_ctl.scala 286:129] + wire [7:0] _T_1662 = _T_1658 ? io_stbuf_data_any[23:16] : io_store_data_hi_r[23:16]; // @[el2_lsu_dccm_ctl.scala 286:79] + wire [7:0] _T_1666 = {{4'd0}, _T_1662[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1668 = {_T_1662[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1670 = _T_1668 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1671 = _T_1666 | _T_1670; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_88 = {{2'd0}, _T_1671[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1676 = _GEN_88 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1678 = {_T_1671[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1680 = _T_1678 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1681 = _T_1676 | _T_1680; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_89 = {{1'd0}, _T_1681[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1686 = _GEN_89 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1688 = {_T_1681[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1690 = _T_1688 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1691 = _T_1686 | _T_1690; // @[Bitwise.scala 103:39] + wire _T_1694 = ~store_byteen_ext_r[7]; // @[el2_lsu_dccm_ctl.scala 286:131] + wire _T_1695 = _T_1581 & _T_1694; // @[el2_lsu_dccm_ctl.scala 286:129] + wire [7:0] _T_1699 = _T_1695 ? io_stbuf_data_any[31:24] : io_store_data_hi_r[31:24]; // @[el2_lsu_dccm_ctl.scala 286:79] + wire [7:0] _T_1703 = {{4'd0}, _T_1699[7:4]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1705 = {_T_1699[3:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1707 = _T_1705 & 8'hf0; // @[Bitwise.scala 103:75] + wire [7:0] _T_1708 = _T_1703 | _T_1707; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_90 = {{2'd0}, _T_1708[7:2]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1713 = _GEN_90 & 8'h33; // @[Bitwise.scala 103:31] + wire [7:0] _T_1715 = {_T_1708[5:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1717 = _T_1715 & 8'hcc; // @[Bitwise.scala 103:75] + wire [7:0] _T_1718 = _T_1713 | _T_1717; // @[Bitwise.scala 103:39] + wire [7:0] _GEN_91 = {{1'd0}, _T_1718[7:1]}; // @[Bitwise.scala 103:31] + wire [7:0] _T_1723 = _GEN_91 & 8'h55; // @[Bitwise.scala 103:31] + wire [7:0] _T_1725 = {_T_1718[6:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [7:0] _T_1727 = _T_1725 & 8'haa; // @[Bitwise.scala 103:75] + wire [7:0] _T_1728 = _T_1723 | _T_1727; // @[Bitwise.scala 103:39] + wire [31:0] _T_1732 = {_T_1617,_T_1654,_T_1691,_T_1728}; // @[Cat.scala 29:58] + wire [31:0] _T_1736 = {{16'd0}, _T_1732[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1738 = {_T_1732[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1740 = _T_1738 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1741 = _T_1736 | _T_1740; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_92 = {{8'd0}, _T_1741[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1746 = _GEN_92 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1748 = {_T_1741[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1750 = _T_1748 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1751 = _T_1746 | _T_1750; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_93 = {{4'd0}, _T_1751[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1756 = _GEN_93 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1758 = {_T_1751[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1760 = _T_1758 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1761 = _T_1756 | _T_1760; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_94 = {{2'd0}, _T_1761[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1766 = _GEN_94 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1768 = {_T_1761[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1770 = _T_1768 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1771 = _T_1766 | _T_1770; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_95 = {{1'd0}, _T_1771[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1776 = _GEN_95 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1778 = {_T_1771[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1780 = _T_1778 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [63:0] _T_1784 = {io_store_data_hi_r,io_store_data_lo_r}; // @[Cat.scala 29:58] + wire [3:0] _GEN_96 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_dccm_ctl.scala 287:94] + wire [5:0] _T_1786 = 4'h8 * _GEN_96; // @[el2_lsu_dccm_ctl.scala 287:94] + wire [63:0] _T_1787 = _T_1784 >> _T_1786; // @[el2_lsu_dccm_ctl.scala 287:88] + wire [7:0] _T_1790 = store_byteen_r[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1793 = store_byteen_r[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1796 = store_byteen_r[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1799 = store_byteen_r[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1803 = {_T_1790,_T_1793,_T_1796,_T_1799}; // @[Cat.scala 29:58] + wire [31:0] _T_1807 = {{16'd0}, _T_1803[31:16]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1809 = {_T_1803[15:0], 16'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1811 = _T_1809 & 32'hffff0000; // @[Bitwise.scala 103:75] + wire [31:0] _T_1812 = _T_1807 | _T_1811; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_97 = {{8'd0}, _T_1812[31:8]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1817 = _GEN_97 & 32'hff00ff; // @[Bitwise.scala 103:31] + wire [31:0] _T_1819 = {_T_1812[23:0], 8'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1821 = _T_1819 & 32'hff00ff00; // @[Bitwise.scala 103:75] + wire [31:0] _T_1822 = _T_1817 | _T_1821; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_98 = {{4'd0}, _T_1822[31:4]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1827 = _GEN_98 & 32'hf0f0f0f; // @[Bitwise.scala 103:31] + wire [31:0] _T_1829 = {_T_1822[27:0], 4'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1831 = _T_1829 & 32'hf0f0f0f0; // @[Bitwise.scala 103:75] + wire [31:0] _T_1832 = _T_1827 | _T_1831; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_99 = {{2'd0}, _T_1832[31:2]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1837 = _GEN_99 & 32'h33333333; // @[Bitwise.scala 103:31] + wire [31:0] _T_1839 = {_T_1832[29:0], 2'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1841 = _T_1839 & 32'hcccccccc; // @[Bitwise.scala 103:75] + wire [31:0] _T_1842 = _T_1837 | _T_1841; // @[Bitwise.scala 103:39] + wire [31:0] _GEN_100 = {{1'd0}, _T_1842[31:1]}; // @[Bitwise.scala 103:31] + wire [31:0] _T_1847 = _GEN_100 & 32'h55555555; // @[Bitwise.scala 103:31] + wire [31:0] _T_1849 = {_T_1842[30:0], 1'h0}; // @[Bitwise.scala 103:65] + wire [31:0] _T_1851 = _T_1849 & 32'haaaaaaaa; // @[Bitwise.scala 103:75] + wire [31:0] _T_1852 = _T_1847 | _T_1851; // @[Bitwise.scala 103:39] + wire [63:0] _GEN_101 = {{32'd0}, _T_1852}; // @[el2_lsu_dccm_ctl.scala 287:115] + wire [63:0] _T_1853 = _T_1787 & _GEN_101; // @[el2_lsu_dccm_ctl.scala 287:115] + wire _T_1858 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_dccm_ctl.scala 294:50] + wire _T_1859 = _T_1858 & io_addr_in_pic_r; // @[el2_lsu_dccm_ctl.scala 294:71] + wire _T_1860 = _T_1859 & io_lsu_commit_r; // @[el2_lsu_dccm_ctl.scala 294:90] + wire _T_1862 = io_lsu_pkt_d_valid & io_lsu_pkt_d_load; // @[el2_lsu_dccm_ctl.scala 295:50] + wire _T_1864 = io_lsu_pkt_d_valid & io_lsu_pkt_d_store; // @[el2_lsu_dccm_ctl.scala 296:50] + wire [31:0] _T_1868 = {17'h0,io_lsu_addr_d[14:0]}; // @[Cat.scala 29:58] + wire [14:0] _T_1874 = io_dma_pic_wen ? io_dma_mem_addr[14:0] : io_lsu_addr_r[14:0]; // @[el2_lsu_dccm_ctl.scala 298:85] + wire [31:0] _T_1875 = {17'h0,_T_1874}; // @[Cat.scala 29:58] + reg _T_1882; // @[el2_lsu_dccm_ctl.scala 303:61] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_io_l1clk), .io_clk(rvclkhdr_io_clk), .io_en(rvclkhdr_io_en), .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr rvclkhdr_1 ( // @[beh_lib.scala 351:21] + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] .io_l1clk(rvclkhdr_1_io_l1clk), .io_clk(rvclkhdr_1_io_clk), .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_lsu_ld_data_corr_r = _T_9[31:0]; // @[el2_lsu_dccm_ctl.scala 178:28] - assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[el2_lsu_dccm_ctl.scala 298:27] - assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[el2_lsu_dccm_ctl.scala 297:27] - assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[el2_lsu_dccm_ctl.scala 300:27] - assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[el2_lsu_dccm_ctl.scala 299:27] - assign io_lsu_ld_data_m = _T_179[31:0]; // @[el2_lsu_dccm_ctl.scala 186:28] - assign io_store_data_hi_r = _T_472; // @[el2_lsu_dccm_ctl.scala 291:29] - assign io_store_data_lo_r = _T_431; // @[el2_lsu_dccm_ctl.scala 290:29] - assign io_store_datafn_hi_r = {_T_543,_T_542}; // @[el2_lsu_dccm_ctl.scala 293:29] - assign io_store_datafn_lo_r = {_T_507,_T_506}; // @[el2_lsu_dccm_ctl.scala 292:29] - assign io_ld_single_ecc_error_r = _T_238 & _T_239; // @[el2_lsu_dccm_ctl.scala 196:33] - assign io_ld_single_ecc_error_r_ff = _T_261 & _T_262; // @[el2_lsu_dccm_ctl.scala 211:31] - assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[el2_lsu_dccm_ctl.scala 308:27] - assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_276; // @[el2_lsu_dccm_ctl.scala 212:27] - assign io_lsu_dccm_rden_m = _T_603; // @[el2_lsu_dccm_ctl.scala 312:24] - assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 168:28] - assign io_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[el2_lsu_dccm_ctl.scala 169:28] - assign io_dccm_dma_rtag = io_dma_mem_tag_m; // @[el2_lsu_dccm_ctl.scala 171:28] - assign io_dccm_dma_rdata = {_T_7,_T_4}; // @[el2_lsu_dccm_ctl.scala 170:28] - assign io_dccm_wren = _T_278 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 217:22] - assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 218:22] - assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_285 : _T_289; // @[el2_lsu_dccm_ctl.scala 219:22] - assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_311 : _T_319; // @[el2_lsu_dccm_ctl.scala 227:22] - assign io_dccm_rd_addr_lo = io_lsu_addr_d; // @[el2_lsu_dccm_ctl.scala 225:22] - assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_295 : _T_299; // @[el2_lsu_dccm_ctl.scala 222:22] - assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_329 : _T_337; // @[el2_lsu_dccm_ctl.scala 233:22] - assign io_dccm_rd_addr_hi = io_end_addr_d; // @[el2_lsu_dccm_ctl.scala 226:22] - assign io_picm_wren = _T_579 | io_dma_pic_wen; // @[el2_lsu_dccm_ctl.scala 302:27] - assign io_picm_rden = _T_581 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 303:27] - assign io_picm_mken = _T_583 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 304:27] - assign io_picm_rdaddr = 32'hf00c0000 | _GEN_8; // @[el2_lsu_dccm_ctl.scala 306:27] - assign io_picm_wraddr = 32'hf00c0000 | _GEN_9; // @[el2_lsu_dccm_ctl.scala 307:27] - assign io_picm_wr_data = io_dma_pic_wen ? io_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[el2_lsu_dccm_ctl.scala 309:27] - assign rvclkhdr_io_clk = io_clk; // @[beh_lib.scala 353:16] - assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 354:15] - assign rvclkhdr_io_scan_mode = io_scan_mode; // @[beh_lib.scala 355:22] - assign rvclkhdr_1_io_clk = io_clk; // @[beh_lib.scala 353:16] - assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[beh_lib.scala 354:15] - assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[beh_lib.scala 355:22] + assign io_lsu_ld_data_corr_r = _T_2[31:0]; // @[el2_lsu_dccm_ctl.scala 171:28] + assign io_dccm_rdata_hi_m = io_dccm_rd_data_hi[31:0]; // @[el2_lsu_dccm_ctl.scala 290:27] + assign io_dccm_rdata_lo_m = io_dccm_rd_data_lo[31:0]; // @[el2_lsu_dccm_ctl.scala 289:27] + assign io_dccm_data_ecc_hi_m = io_dccm_rd_data_hi[38:32]; // @[el2_lsu_dccm_ctl.scala 292:27] + assign io_dccm_data_ecc_lo_m = io_dccm_rd_data_lo[38:32]; // @[el2_lsu_dccm_ctl.scala 291:27] + assign io_lsu_ld_data_m = _T_763[31:0]; // @[el2_lsu_dccm_ctl.scala 174:28] + assign io_store_data_hi_r = _T_1379; // @[el2_lsu_dccm_ctl.scala 284:29] + assign io_store_data_lo_r = _T_1173; // @[el2_lsu_dccm_ctl.scala 283:29] + assign io_store_datafn_hi_r = _T_1776 | _T_1780; // @[el2_lsu_dccm_ctl.scala 286:29] + assign io_store_datafn_lo_r = _T_1575 | _T_1579; // @[el2_lsu_dccm_ctl.scala 285:29] + assign io_store_data_r = _T_1853[31:0]; // @[el2_lsu_dccm_ctl.scala 287:29] + assign io_ld_single_ecc_error_r = _T_815 & _T_816; // @[el2_lsu_dccm_ctl.scala 187:34] + assign io_ld_single_ecc_error_r_ff = _T_838 & _T_839; // @[el2_lsu_dccm_ctl.scala 200:31] + assign io_picm_mask_data_m = picm_rd_data_m[31:0]; // @[el2_lsu_dccm_ctl.scala 299:27] + assign io_lsu_stbuf_commit_any = io_stbuf_reqvld_any & _T_853; // @[el2_lsu_dccm_ctl.scala 201:31] + assign io_lsu_dccm_rden_m = _T_1882; // @[el2_lsu_dccm_ctl.scala 303:24] + assign io_dccm_dma_rvalid = _T & io_lsu_pkt_m_dma; // @[el2_lsu_dccm_ctl.scala 161:28] + assign io_dccm_dma_ecc_error = io_lsu_double_ecc_error_m; // @[el2_lsu_dccm_ctl.scala 162:28] + assign io_dccm_dma_rtag = io_dma_mem_tag_m; // @[el2_lsu_dccm_ctl.scala 164:28] + assign io_dccm_dma_rdata = _T_376 | _T_380; // @[el2_lsu_dccm_ctl.scala 163:28] + assign io_dccm_wren = _T_855 | io_ld_single_ecc_error_r_ff; // @[el2_lsu_dccm_ctl.scala 207:22] + assign io_dccm_rden = lsu_dccm_rden_d & io_addr_in_dccm_d; // @[el2_lsu_dccm_ctl.scala 208:22] + assign io_dccm_wr_addr_lo = io_ld_single_ecc_error_r_ff ? _T_862 : _T_866; // @[el2_lsu_dccm_ctl.scala 210:22] + assign io_dccm_wr_data_lo = io_ld_single_ecc_error_r_ff ? _T_888 : _T_896; // @[el2_lsu_dccm_ctl.scala 221:22] + assign io_dccm_rd_addr_lo = io_lsu_addr_d[15:0]; // @[el2_lsu_dccm_ctl.scala 218:22] + assign io_dccm_wr_addr_hi = io_ld_single_ecc_error_r_ff ? _T_872 : _T_876; // @[el2_lsu_dccm_ctl.scala 214:22] + assign io_dccm_wr_data_hi = io_ld_single_ecc_error_r_ff ? _T_906 : _T_914; // @[el2_lsu_dccm_ctl.scala 227:22] + assign io_dccm_rd_addr_hi = io_end_addr_d; // @[el2_lsu_dccm_ctl.scala 219:22] + assign io_picm_wren = _T_1860 | io_dma_pic_wen; // @[el2_lsu_dccm_ctl.scala 294:27] + assign io_picm_rden = _T_1862 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 295:27] + assign io_picm_mken = _T_1864 & io_addr_in_pic_d; // @[el2_lsu_dccm_ctl.scala 296:27] + assign io_picm_rdaddr = 32'hf00c0000 | _T_1868; // @[el2_lsu_dccm_ctl.scala 297:27] + assign io_picm_wraddr = 32'hf00c0000 | _T_1875; // @[el2_lsu_dccm_ctl.scala 298:27] + assign io_picm_wr_data = io_dma_pic_wen ? io_dma_mem_wdata[31:0] : io_store_datafn_lo_r; // @[el2_lsu_dccm_ctl.scala 300:27] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -1534,7 +2303,7 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {2{`RANDOM}}; - _T_9 = _RAND_0[63:0]; + _T_2 = _RAND_0[63:0]; _RAND_1 = {1{`RANDOM}}; lsu_double_ecc_error_r_ff = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; @@ -1546,14 +2315,14 @@ initial begin _RAND_5 = {1{`RANDOM}}; ld_sec_addr_lo_r_ff = _RAND_5[15:0]; _RAND_6 = {1{`RANDOM}}; - _T_431 = _RAND_6[31:0]; + _T_1173 = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_472 = _RAND_7[31:0]; + _T_1379 = _RAND_7[31:0]; _RAND_8 = {1{`RANDOM}}; - _T_603 = _RAND_8[0:0]; + _T_1882 = _RAND_8[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - _T_9 = 64'h0; + _T_2 = 64'h0; end if (reset) begin lsu_double_ecc_error_r_ff = 1'h0; @@ -1571,7 +2340,13 @@ initial begin ld_sec_addr_lo_r_ff = 16'h0; end if (reset) begin - _T_603 = 1'h0; + _T_1173 = 32'h0; + end + if (reset) begin + _T_1379 = 32'h0; + end + if (reset) begin + _T_1882 = 1'h0; end `endif // RANDOMIZE end // initial @@ -1579,15 +2354,11 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge io_lsu_store_c1_r_clk) begin - _T_431 <= {_T_429,_T_428}; - _T_472 <= {_T_470,_T_469}; - end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_9 <= 64'h0; + _T_2 <= 64'h0; end else begin - _T_9 <= _T_8 >> _T_178; + _T_2 <= lsu_rdata_corr_m >> _T_762; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -1601,14 +2372,14 @@ end // initial if (reset) begin ld_single_ecc_error_hi_r_ff <= 1'h0; end else begin - ld_single_ecc_error_hi_r_ff <= _T_245 & _T_246; + ld_single_ecc_error_hi_r_ff <= _T_822 & _T_823; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin ld_single_ecc_error_lo_r_ff <= 1'h0; end else begin - ld_single_ecc_error_lo_r_ff <= _T_242 & _T_243; + ld_single_ecc_error_lo_r_ff <= _T_819 & _T_820; end end always @(posedge rvclkhdr_io_l1clk or posedge reset) begin @@ -1622,14 +2393,28 @@ end // initial if (reset) begin ld_sec_addr_lo_r_ff <= 16'h0; end else begin - ld_sec_addr_lo_r_ff <= io_lsu_addr_r; + ld_sec_addr_lo_r_ff <= io_lsu_addr_r[15:0]; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1173 <= 32'h0; + end else begin + _T_1173 <= _T_1167 | _T_1171; + end + end + always @(posedge io_lsu_store_c1_r_clk or posedge reset) begin + if (reset) begin + _T_1379 <= 32'h0; + end else begin + _T_1379 <= _T_1373 | _T_1377; end end always @(posedge io_lsu_c2_m_clk or posedge reset) begin if (reset) begin - _T_603 <= 1'h0; + _T_1882 <= 1'h0; end else begin - _T_603 <= _T_260 & io_addr_in_dccm_d; + _T_1882 <= _T_837 & io_addr_in_dccm_d; end end endmodule @@ -1666,11 +2451,13 @@ module el2_lsu_stbuf( input [31:0] io_end_addr_r, input io_addr_in_dccm_m, input io_addr_in_dccm_r, + input io_scan_mode, output io_stbuf_reqvld_any, output io_stbuf_reqvld_flushed_any, output [15:0] io_stbuf_addr_any, output [31:0] io_stbuf_data_any, output io_lsu_stbuf_full_any, + output io_lsu_stbuf_empty_any, output io_ldst_stbuf_reqvld_r, output [31:0] io_stbuf_fwddata_hi_m, output [31:0] io_stbuf_fwddata_lo_m, @@ -1703,668 +2490,754 @@ module el2_lsu_stbuf( reg [31:0] _RAND_22; reg [31:0] _RAND_23; `endif // RANDOMIZE_REG_INIT - wire [7:0] _T_1 = io_lsu_pkt_r_by ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_2 = _T_1 & 8'h1; // @[el2_lsu_stbuf.scala 108:49] - wire [7:0] _T_4 = io_lsu_pkt_r_half ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_5 = _T_4 & 8'h3; // @[el2_lsu_stbuf.scala 109:32] - wire [7:0] _T_6 = _T_2 | _T_5; // @[el2_lsu_stbuf.scala 108:65] - wire [7:0] _T_8 = io_lsu_pkt_r_word ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_9 = _T_8 & 8'hf; // @[el2_lsu_stbuf.scala 110:32] - wire [7:0] _T_10 = _T_6 | _T_9; // @[el2_lsu_stbuf.scala 109:48] - wire [7:0] _T_12 = io_lsu_pkt_r_dword ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] ldst_byteen_r = _T_10 | _T_12; // @[el2_lsu_stbuf.scala 110:48] - wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 112:40] - reg ldst_dual_r; // @[el2_lsu_stbuf.scala 161:53] - wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 113:41] - wire [10:0] _GEN_38 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 115:40] - wire [10:0] _T_17 = _GEN_38 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 115:40] - wire [7:0] store_byteen_ext_r = _T_17[7:0]; // @[el2_lsu_stbuf.scala 115:23] - wire [3:0] _T_20 = io_lsu_pkt_m_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_20; // @[el2_lsu_stbuf.scala 116:53] - wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_20; // @[el2_lsu_stbuf.scala 117:53] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire [1:0] _T_5 = io_lsu_pkt_r_half ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [7:0] _T_7 = io_lsu_pkt_r_dword ? 8'hff : 8'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_10 = {{1'd0}, io_lsu_pkt_r_by}; // @[Mux.scala 27:72] + wire [1:0] _T_8 = _GEN_10 | _T_5; // @[Mux.scala 27:72] + wire [3:0] _GEN_11 = {{2'd0}, _T_8}; // @[Mux.scala 27:72] + wire [3:0] _T_9 = _GEN_11 | _T_6; // @[Mux.scala 27:72] + wire [7:0] _GEN_12 = {{4'd0}, _T_9}; // @[Mux.scala 27:72] + wire [7:0] ldst_byteen_r = _GEN_12 | _T_7; // @[Mux.scala 27:72] + wire ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_stbuf.scala 118:39] + reg ldst_dual_r; // @[el2_lsu_stbuf.scala 177:52] + wire dual_stbuf_write_r = ldst_dual_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 119:40] + wire [10:0] _GEN_13 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_stbuf.scala 121:39] + wire [10:0] _T_14 = _GEN_13 << io_lsu_addr_r[1:0]; // @[el2_lsu_stbuf.scala 121:39] + wire [7:0] store_byteen_ext_r = _T_14[7:0]; // @[el2_lsu_stbuf.scala 121:22] + wire [3:0] _T_17 = io_lsu_pkt_r_store ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] store_byteen_hi_r = store_byteen_ext_r[7:4] & _T_17; // @[el2_lsu_stbuf.scala 122:52] + wire [3:0] store_byteen_lo_r = store_byteen_ext_r[3:0] & _T_17; // @[el2_lsu_stbuf.scala 123:52] reg [1:0] RdPtr; // @[Reg.scala 27:20] - wire [1:0] NxtRdPtr = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 118:27] + wire [1:0] RdPtrPlus1 = RdPtr + 2'h1; // @[el2_lsu_stbuf.scala 125:26] reg [1:0] WrPtr; // @[Reg.scala 27:20] - wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 119:27] - wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 120:27] - reg [15:0] stbuf_addr_0; // @[Reg.scala 27:20] - wire _T_30 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121] - reg stbuf_vld_0; // @[Reg.scala 27:20] - wire _T_31 = _T_30 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 124:181] - reg stbuf_dma_kill_0; // @[Reg.scala 27:20] - wire _T_32 = ~stbuf_dma_kill_0; // @[el2_lsu_stbuf.scala 124:198] - wire _T_33 = _T_31 & _T_32; // @[el2_lsu_stbuf.scala 124:196] - wire _T_214 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 132:78] - wire _T_215 = 2'h3 == RdPtr; // @[el2_lsu_stbuf.scala 132:121] - wire _T_217 = _T_214 & _T_215; // @[el2_lsu_stbuf.scala 132:109] - wire _T_211 = 2'h2 == RdPtr; // @[el2_lsu_stbuf.scala 132:121] - wire _T_213 = _T_214 & _T_211; // @[el2_lsu_stbuf.scala 132:109] - wire _T_207 = 2'h1 == RdPtr; // @[el2_lsu_stbuf.scala 132:121] - wire _T_209 = _T_214 & _T_207; // @[el2_lsu_stbuf.scala 132:109] - wire _T_203 = 2'h0 == RdPtr; // @[el2_lsu_stbuf.scala 132:121] - wire _T_205 = _T_214 & _T_203; // @[el2_lsu_stbuf.scala 132:109] - wire [3:0] stbuf_reset = {_T_217,_T_213,_T_209,_T_205}; // @[Cat.scala 29:58] - wire _T_35 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 124:219] - wire _T_36 = _T_33 & _T_35; // @[el2_lsu_stbuf.scala 124:217] - reg [15:0] stbuf_addr_1; // @[Reg.scala 27:20] - wire _T_39 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121] - reg stbuf_vld_1; // @[Reg.scala 27:20] - wire _T_40 = _T_39 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 124:181] - reg stbuf_dma_kill_1; // @[Reg.scala 27:20] - wire _T_41 = ~stbuf_dma_kill_1; // @[el2_lsu_stbuf.scala 124:198] - wire _T_42 = _T_40 & _T_41; // @[el2_lsu_stbuf.scala 124:196] - wire _T_44 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 124:219] - wire _T_45 = _T_42 & _T_44; // @[el2_lsu_stbuf.scala 124:217] - reg [15:0] stbuf_addr_2; // @[Reg.scala 27:20] - wire _T_48 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121] - reg stbuf_vld_2; // @[Reg.scala 27:20] - wire _T_49 = _T_48 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 124:181] - reg stbuf_dma_kill_2; // @[Reg.scala 27:20] - wire _T_50 = ~stbuf_dma_kill_2; // @[el2_lsu_stbuf.scala 124:198] - wire _T_51 = _T_49 & _T_50; // @[el2_lsu_stbuf.scala 124:196] - wire _T_53 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 124:219] - wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 124:217] - reg [15:0] stbuf_addr_3; // @[Reg.scala 27:20] - wire _T_57 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 124:121] - reg stbuf_vld_3; // @[Reg.scala 27:20] - wire _T_58 = _T_57 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 124:181] - reg stbuf_dma_kill_3; // @[Reg.scala 27:20] - wire _T_59 = ~stbuf_dma_kill_3; // @[el2_lsu_stbuf.scala 124:198] - wire _T_60 = _T_58 & _T_59; // @[el2_lsu_stbuf.scala 124:196] - wire _T_62 = ~stbuf_reset[3]; // @[el2_lsu_stbuf.scala 124:219] - wire _T_63 = _T_60 & _T_62; // @[el2_lsu_stbuf.scala 124:217] - wire [3:0] store_matchvec_lo_r = {_T_63,_T_54,_T_45,_T_36}; // @[Cat.scala 29:58] - wire _T_68 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121] - wire _T_69 = _T_68 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 125:181] - wire _T_71 = _T_69 & _T_32; // @[el2_lsu_stbuf.scala 125:196] - wire _T_72 = _T_71 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217] - wire _T_75 = _T_72 & _T_35; // @[el2_lsu_stbuf.scala 125:238] - wire _T_78 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121] - wire _T_79 = _T_78 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 125:181] - wire _T_81 = _T_79 & _T_41; // @[el2_lsu_stbuf.scala 125:196] - wire _T_82 = _T_81 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217] - wire _T_85 = _T_82 & _T_44; // @[el2_lsu_stbuf.scala 125:238] - wire _T_88 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121] - wire _T_89 = _T_88 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 125:181] - wire _T_91 = _T_89 & _T_50; // @[el2_lsu_stbuf.scala 125:196] - wire _T_92 = _T_91 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217] - wire _T_95 = _T_92 & _T_53; // @[el2_lsu_stbuf.scala 125:238] - wire _T_98 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 125:121] - wire _T_99 = _T_98 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 125:181] - wire _T_101 = _T_99 & _T_59; // @[el2_lsu_stbuf.scala 125:196] - wire _T_102 = _T_101 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 125:217] - wire _T_105 = _T_102 & _T_62; // @[el2_lsu_stbuf.scala 125:238] - wire [3:0] store_matchvec_hi_r = {_T_105,_T_95,_T_85,_T_75}; // @[Cat.scala 29:58] - wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[el2_lsu_stbuf.scala 127:50] - wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[el2_lsu_stbuf.scala 128:50] - wire _T_108 = 2'h0 == WrPtr; // @[el2_lsu_stbuf.scala 130:92] - wire _T_110 = ~store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 130:112] - wire _T_111 = _T_108 & _T_110; // @[el2_lsu_stbuf.scala 130:110] - wire _T_112 = io_ldst_stbuf_reqvld_r & _T_111; // @[el2_lsu_stbuf.scala 130:79] - wire _T_115 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 130:167] - wire _T_116 = _T_108 & _T_115; // @[el2_lsu_stbuf.scala 130:165] - wire _T_117 = ~store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 130:189] - wire _T_118 = _T_116 & _T_117; // @[el2_lsu_stbuf.scala 130:187] - wire _T_119 = _T_112 | _T_118; // @[el2_lsu_stbuf.scala 130:134] - wire _T_120 = 2'h0 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 131:17] - wire _T_122 = _T_120 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:40] - wire _T_123 = store_coalesce_lo_r | store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 131:85] - wire _T_124 = ~_T_123; // @[el2_lsu_stbuf.scala 131:63] - wire _T_125 = _T_122 & _T_124; // @[el2_lsu_stbuf.scala 131:61] - wire _T_126 = _T_119 | _T_125; // @[el2_lsu_stbuf.scala 130:211] - wire _T_128 = _T_126 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 131:109] - wire _T_130 = _T_128 | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 131:134] - wire _T_131 = 2'h1 == WrPtr; // @[el2_lsu_stbuf.scala 130:92] - wire _T_134 = _T_131 & _T_110; // @[el2_lsu_stbuf.scala 130:110] - wire _T_135 = io_ldst_stbuf_reqvld_r & _T_134; // @[el2_lsu_stbuf.scala 130:79] - wire _T_139 = _T_131 & _T_115; // @[el2_lsu_stbuf.scala 130:165] - wire _T_141 = _T_139 & _T_117; // @[el2_lsu_stbuf.scala 130:187] - wire _T_142 = _T_135 | _T_141; // @[el2_lsu_stbuf.scala 130:134] - wire _T_143 = 2'h1 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 131:17] - wire _T_145 = _T_143 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:40] - wire _T_148 = _T_145 & _T_124; // @[el2_lsu_stbuf.scala 131:61] - wire _T_149 = _T_142 | _T_148; // @[el2_lsu_stbuf.scala 130:211] - wire _T_151 = _T_149 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 131:109] - wire _T_153 = _T_151 | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 131:134] - wire _T_154 = 2'h2 == WrPtr; // @[el2_lsu_stbuf.scala 130:92] - wire _T_157 = _T_154 & _T_110; // @[el2_lsu_stbuf.scala 130:110] - wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[el2_lsu_stbuf.scala 130:79] - wire _T_162 = _T_154 & _T_115; // @[el2_lsu_stbuf.scala 130:165] - wire _T_164 = _T_162 & _T_117; // @[el2_lsu_stbuf.scala 130:187] - wire _T_165 = _T_158 | _T_164; // @[el2_lsu_stbuf.scala 130:134] - wire _T_166 = 2'h2 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 131:17] - wire _T_168 = _T_166 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:40] - wire _T_171 = _T_168 & _T_124; // @[el2_lsu_stbuf.scala 131:61] - wire _T_172 = _T_165 | _T_171; // @[el2_lsu_stbuf.scala 130:211] - wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 131:109] - wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 131:134] - wire _T_177 = 2'h3 == WrPtr; // @[el2_lsu_stbuf.scala 130:92] - wire _T_180 = _T_177 & _T_110; // @[el2_lsu_stbuf.scala 130:110] - wire _T_181 = io_ldst_stbuf_reqvld_r & _T_180; // @[el2_lsu_stbuf.scala 130:79] - wire _T_185 = _T_177 & _T_115; // @[el2_lsu_stbuf.scala 130:165] - wire _T_187 = _T_185 & _T_117; // @[el2_lsu_stbuf.scala 130:187] - wire _T_188 = _T_181 | _T_187; // @[el2_lsu_stbuf.scala 130:134] - wire _T_189 = 2'h3 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 131:17] - wire _T_191 = _T_189 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 131:40] - wire _T_194 = _T_191 & _T_124; // @[el2_lsu_stbuf.scala 131:61] - wire _T_195 = _T_188 | _T_194; // @[el2_lsu_stbuf.scala 130:211] - wire _T_197 = _T_195 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 131:109] - wire _T_199 = _T_197 | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 131:134] - wire [3:0] stbuf_wr_en = {_T_199,_T_176,_T_153,_T_130}; // @[Cat.scala 29:58] - wire _T_221 = ~ldst_dual_r; // @[el2_lsu_stbuf.scala 133:52] - wire _T_222 = _T_221 | io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 133:65] - wire _T_225 = _T_222 & _T_108; // @[el2_lsu_stbuf.scala 133:92] - wire _T_227 = _T_225 & _T_110; // @[el2_lsu_stbuf.scala 133:122] - wire _T_229 = _T_227 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 133:145] - wire _T_234 = _T_222 & _T_131; // @[el2_lsu_stbuf.scala 133:92] - wire _T_236 = _T_234 & _T_110; // @[el2_lsu_stbuf.scala 133:122] - wire _T_238 = _T_236 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 133:145] - wire _T_243 = _T_222 & _T_154; // @[el2_lsu_stbuf.scala 133:92] - wire _T_245 = _T_243 & _T_110; // @[el2_lsu_stbuf.scala 133:122] - wire _T_247 = _T_245 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 133:145] - wire _T_252 = _T_222 & _T_177; // @[el2_lsu_stbuf.scala 133:92] - wire _T_254 = _T_252 & _T_110; // @[el2_lsu_stbuf.scala 133:122] - wire _T_256 = _T_254 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 133:145] - wire [3:0] sel_lo = {_T_256,_T_247,_T_238,_T_229}; // @[Cat.scala 29:58] - wire [31:0] _T_260 = sel_lo[0] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57] - wire [31:0] _T_262 = sel_lo[1] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57] - wire [31:0] _T_264 = sel_lo[2] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57] - wire [31:0] _T_266 = sel_lo[3] ? io_lsu_addr_r : io_end_addr_r; // @[el2_lsu_stbuf.scala 135:57] - reg [3:0] stbuf_byteen_0; // @[Reg.scala 27:20] - wire [3:0] _T_268 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87] - wire [3:0] _T_269 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124] - wire [3:0] stbuf_byteenin_3 = sel_lo[0] ? _T_268 : _T_269; // @[el2_lsu_stbuf.scala 136:59] - reg [3:0] stbuf_byteen_1; // @[Reg.scala 27:20] - wire [3:0] _T_272 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87] - wire [3:0] _T_273 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124] - wire [3:0] stbuf_byteenin_2 = sel_lo[1] ? _T_272 : _T_273; // @[el2_lsu_stbuf.scala 136:59] - reg [3:0] stbuf_byteen_2; // @[Reg.scala 27:20] - wire [3:0] _T_276 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87] - wire [3:0] _T_277 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124] - wire [3:0] stbuf_byteenin_1 = sel_lo[2] ? _T_276 : _T_277; // @[el2_lsu_stbuf.scala 136:59] - reg [3:0] stbuf_byteen_3; // @[Reg.scala 27:20] - wire [3:0] _T_280 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 136:87] - wire [3:0] _T_281 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 136:124] - wire [3:0] stbuf_byteenin_0 = sel_lo[3] ? _T_280 : _T_281; // @[el2_lsu_stbuf.scala 136:59] - wire _T_285 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 138:68] - wire _T_287 = _T_285 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88] - reg [31:0] stbuf_data_0; // @[Reg.scala 27:20] - wire [7:0] _T_290 = _T_287 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 138:67] - wire _T_294 = _T_285 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31] - wire [7:0] _T_297 = _T_294 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 139:10] - wire [7:0] datain1_3 = sel_lo[0] ? _T_290 : _T_297; // @[el2_lsu_stbuf.scala 138:52] - wire _T_301 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 138:68] - wire _T_303 = _T_301 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88] - reg [31:0] stbuf_data_1; // @[Reg.scala 27:20] - wire [7:0] _T_306 = _T_303 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 138:67] - wire _T_310 = _T_301 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31] - wire [7:0] _T_313 = _T_310 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 139:10] - wire [7:0] datain1_2 = sel_lo[1] ? _T_306 : _T_313; // @[el2_lsu_stbuf.scala 138:52] - wire _T_317 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 138:68] - wire _T_319 = _T_317 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88] - reg [31:0] stbuf_data_2; // @[Reg.scala 27:20] - wire [7:0] _T_322 = _T_319 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 138:67] - wire _T_326 = _T_317 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31] - wire [7:0] _T_329 = _T_326 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 139:10] - wire [7:0] datain1_1 = sel_lo[2] ? _T_322 : _T_329; // @[el2_lsu_stbuf.scala 138:52] - wire _T_333 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 138:68] - wire _T_335 = _T_333 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 138:88] - reg [31:0] stbuf_data_3; // @[Reg.scala 27:20] - wire [7:0] _T_338 = _T_335 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 138:67] - wire _T_342 = _T_333 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 139:31] - wire [7:0] _T_345 = _T_342 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 139:10] - wire [7:0] datain1_0 = sel_lo[3] ? _T_338 : _T_345; // @[el2_lsu_stbuf.scala 138:52] - wire _T_349 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 141:69] - wire _T_351 = _T_349 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89] - wire [7:0] _T_354 = _T_351 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 141:68] - wire _T_358 = _T_349 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31] - wire [7:0] _T_361 = _T_358 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 142:10] - wire [7:0] datain2_3 = sel_lo[0] ? _T_354 : _T_361; // @[el2_lsu_stbuf.scala 141:53] - wire _T_365 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 141:69] - wire _T_367 = _T_365 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89] - wire [7:0] _T_370 = _T_367 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 141:68] - wire _T_374 = _T_365 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31] - wire [7:0] _T_377 = _T_374 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 142:10] - wire [7:0] datain2_2 = sel_lo[1] ? _T_370 : _T_377; // @[el2_lsu_stbuf.scala 141:53] - wire _T_381 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 141:69] - wire _T_383 = _T_381 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89] - wire [7:0] _T_386 = _T_383 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 141:68] - wire _T_390 = _T_381 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31] - wire [7:0] _T_393 = _T_390 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 142:10] - wire [7:0] datain2_1 = sel_lo[2] ? _T_386 : _T_393; // @[el2_lsu_stbuf.scala 141:53] - wire _T_397 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 141:69] - wire _T_399 = _T_397 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 141:89] - wire [7:0] _T_402 = _T_399 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 141:68] - wire _T_406 = _T_397 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 142:31] - wire [7:0] _T_409 = _T_406 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 142:10] - wire [7:0] datain2_0 = sel_lo[3] ? _T_402 : _T_409; // @[el2_lsu_stbuf.scala 141:53] - wire _T_413 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 144:69] - wire _T_415 = _T_413 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89] - wire [7:0] _T_418 = _T_415 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 144:68] - wire _T_422 = _T_413 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31] - wire [7:0] _T_425 = _T_422 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 145:10] - wire [7:0] datain3_3 = sel_lo[0] ? _T_418 : _T_425; // @[el2_lsu_stbuf.scala 144:53] - wire _T_429 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 144:69] - wire _T_431 = _T_429 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89] - wire [7:0] _T_434 = _T_431 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 144:68] - wire _T_438 = _T_429 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31] - wire [7:0] _T_441 = _T_438 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 145:10] - wire [7:0] datain3_2 = sel_lo[1] ? _T_434 : _T_441; // @[el2_lsu_stbuf.scala 144:53] - wire _T_445 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 144:69] - wire _T_447 = _T_445 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89] - wire [7:0] _T_450 = _T_447 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 144:68] - wire _T_454 = _T_445 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31] - wire [7:0] _T_457 = _T_454 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 145:10] - wire [7:0] datain3_1 = sel_lo[2] ? _T_450 : _T_457; // @[el2_lsu_stbuf.scala 144:53] - wire _T_461 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 144:69] - wire _T_463 = _T_461 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 144:89] - wire [7:0] _T_466 = _T_463 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 144:68] - wire _T_470 = _T_461 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 145:31] - wire [7:0] _T_473 = _T_470 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 145:10] - wire [7:0] datain3_0 = sel_lo[3] ? _T_466 : _T_473; // @[el2_lsu_stbuf.scala 144:53] - wire _T_477 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 147:69] - wire _T_479 = _T_477 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89] - wire [7:0] _T_482 = _T_479 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 147:68] - wire _T_486 = _T_477 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31] - wire [7:0] _T_489 = _T_486 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 148:10] - wire [7:0] datain4_3 = sel_lo[0] ? _T_482 : _T_489; // @[el2_lsu_stbuf.scala 147:53] - wire _T_493 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 147:69] - wire _T_495 = _T_493 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89] - wire [7:0] _T_498 = _T_495 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 147:68] - wire _T_502 = _T_493 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31] - wire [7:0] _T_505 = _T_502 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 148:10] - wire [7:0] datain4_2 = sel_lo[1] ? _T_498 : _T_505; // @[el2_lsu_stbuf.scala 147:53] - wire _T_509 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 147:69] - wire _T_511 = _T_509 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89] - wire [7:0] _T_514 = _T_511 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 147:68] - wire _T_518 = _T_509 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31] - wire [7:0] _T_521 = _T_518 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 148:10] - wire [7:0] datain4_1 = sel_lo[2] ? _T_514 : _T_521; // @[el2_lsu_stbuf.scala 147:53] - wire _T_525 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 147:69] - wire _T_527 = _T_525 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 147:89] - wire [7:0] _T_530 = _T_527 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 147:68] - wire _T_534 = _T_525 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 148:31] - wire [7:0] _T_537 = _T_534 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 148:10] - wire [7:0] datain4_0 = sel_lo[3] ? _T_530 : _T_537; // @[el2_lsu_stbuf.scala 147:53] - wire [31:0] stbuf_datain_0 = {datain4_0,datain3_0,datain2_0,datain1_0}; // @[Cat.scala 29:58] - wire [31:0] stbuf_datain_1 = {datain4_1,datain3_1,datain2_1,datain1_1}; // @[Cat.scala 29:58] - wire [31:0] stbuf_datain_2 = {datain4_2,datain3_2,datain2_2,datain1_2}; // @[Cat.scala 29:58] - wire [31:0] stbuf_datain_3 = {datain4_3,datain3_3,datain2_3,datain1_3}; // @[Cat.scala 29:58] - wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 187:17] - wire _T_721 = stbuf_addr_3[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116] - wire _T_722 = _T_721 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 193:175] - wire _T_724 = _T_722 & _T_59; // @[el2_lsu_stbuf.scala 193:190] - wire _T_725 = _T_724 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211] - wire _T_714 = stbuf_addr_2[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116] - wire _T_715 = _T_714 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 193:175] - wire _T_717 = _T_715 & _T_50; // @[el2_lsu_stbuf.scala 193:190] - wire _T_718 = _T_717 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211] - wire _T_707 = stbuf_addr_1[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116] - wire _T_708 = _T_707 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 193:175] - wire _T_710 = _T_708 & _T_41; // @[el2_lsu_stbuf.scala 193:190] - wire _T_711 = _T_710 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211] - wire _T_700 = stbuf_addr_0[15:2] == cmpaddr_hi_m[15:2]; // @[el2_lsu_stbuf.scala 193:116] - wire _T_701 = _T_700 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 193:175] - wire _T_703 = _T_701 & _T_32; // @[el2_lsu_stbuf.scala 193:190] - wire _T_704 = _T_703 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 193:211] - wire [3:0] stbuf_match_hi = {_T_725,_T_718,_T_711,_T_704}; // @[Cat.scala 29:58] - wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 190:18] - wire _T_751 = stbuf_addr_3[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116] - wire _T_752 = _T_751 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 194:175] - wire _T_754 = _T_752 & _T_59; // @[el2_lsu_stbuf.scala 194:190] - wire _T_755 = _T_754 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211] - wire _T_744 = stbuf_addr_2[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116] - wire _T_745 = _T_744 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 194:175] - wire _T_747 = _T_745 & _T_50; // @[el2_lsu_stbuf.scala 194:190] - wire _T_748 = _T_747 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211] - wire _T_737 = stbuf_addr_1[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116] - wire _T_738 = _T_737 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 194:175] - wire _T_740 = _T_738 & _T_41; // @[el2_lsu_stbuf.scala 194:190] - wire _T_741 = _T_740 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211] - wire _T_730 = stbuf_addr_0[15:2] == cmpaddr_lo_m[15:2]; // @[el2_lsu_stbuf.scala 194:116] - wire _T_731 = _T_730 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 194:175] - wire _T_733 = _T_731 & _T_32; // @[el2_lsu_stbuf.scala 194:190] - wire _T_734 = _T_733 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 194:211] - wire [3:0] stbuf_match_lo = {_T_755,_T_748,_T_741,_T_734}; // @[Cat.scala 29:58] - wire _T_778 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 195:79] - wire _T_779 = _T_778 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100] - wire _T_780 = _T_779 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121] - wire _T_781 = _T_780 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140] - wire _T_772 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 195:79] - wire _T_773 = _T_772 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100] - wire _T_774 = _T_773 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121] - wire _T_775 = _T_774 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140] - wire _T_766 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 195:79] - wire _T_767 = _T_766 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100] - wire _T_768 = _T_767 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121] - wire _T_769 = _T_768 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140] - wire _T_760 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 195:79] - wire _T_761 = _T_760 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 195:100] - wire _T_762 = _T_761 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:121] - wire _T_763 = _T_762 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:140] - wire [3:0] stbuf_dma_kill_en = {_T_781,_T_775,_T_769,_T_763}; // @[Cat.scala 29:58] - wire [15:0] stbuf_addrin_0 = _T_266[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17] - wire [3:0] _T_567 = _T_35 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_568 = stbuf_byteenin_0 & _T_567; // @[el2_lsu_stbuf.scala 157:87] - wire [15:0] stbuf_addrin_1 = _T_264[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17] - wire [3:0] _T_589 = _T_44 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_590 = stbuf_byteenin_1 & _T_589; // @[el2_lsu_stbuf.scala 157:87] - wire [15:0] stbuf_addrin_2 = _T_262[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17] - wire [3:0] _T_611 = _T_53 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_612 = stbuf_byteenin_2 & _T_611; // @[el2_lsu_stbuf.scala 157:87] - wire [15:0] stbuf_addrin_3 = _T_260[15:0]; // @[el2_lsu_stbuf.scala 74:39 el2_lsu_stbuf.scala 75:17 el2_lsu_stbuf.scala 135:17] - wire [3:0] _T_633 = _T_62 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] - wire [3:0] _T_634 = stbuf_byteenin_3 & _T_633; // @[el2_lsu_stbuf.scala 157:87] - reg ldst_dual_m; // @[el2_lsu_stbuf.scala 160:53] - wire _GEN_21 = 2'h1 == RdPtr ? stbuf_vld_1 : stbuf_vld_0; // @[el2_lsu_stbuf.scala 164:52] - wire _GEN_22 = 2'h2 == RdPtr ? stbuf_vld_2 : _GEN_21; // @[el2_lsu_stbuf.scala 164:52] - wire _GEN_23 = 2'h3 == RdPtr ? stbuf_vld_3 : _GEN_22; // @[el2_lsu_stbuf.scala 164:52] - wire _GEN_25 = 2'h1 == RdPtr ? stbuf_dma_kill_1 : stbuf_dma_kill_0; // @[el2_lsu_stbuf.scala 164:52] - wire _GEN_26 = 2'h2 == RdPtr ? stbuf_dma_kill_2 : _GEN_25; // @[el2_lsu_stbuf.scala 164:52] - wire _GEN_27 = 2'h3 == RdPtr ? stbuf_dma_kill_3 : _GEN_26; // @[el2_lsu_stbuf.scala 164:52] - wire _T_642 = ~_GEN_27; // @[el2_lsu_stbuf.scala 165:47] - wire _T_643 = _GEN_23 & _T_642; // @[el2_lsu_stbuf.scala 165:45] - wire _T_644 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 165:91] - wire _T_645 = ~_T_644; // @[el2_lsu_stbuf.scala 165:72] - wire [15:0] _GEN_29 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 166:23] - wire [15:0] _GEN_30 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_29; // @[el2_lsu_stbuf.scala 166:23] - wire [31:0] _GEN_33 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 167:23] - wire [31:0] _GEN_34 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_33; // @[el2_lsu_stbuf.scala 167:23] - wire _T_648 = io_ldst_stbuf_reqvld_r & _T_115; // @[el2_lsu_stbuf.scala 169:43] - wire _T_649 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 169:89] - wire _T_650 = ~_T_649; // @[el2_lsu_stbuf.scala 169:67] - wire _T_651 = _T_648 & _T_650; // @[el2_lsu_stbuf.scala 169:65] - wire _T_652 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 170:31] - wire _T_653 = store_coalesce_hi_r & store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 170:77] - wire _T_654 = ~_T_653; // @[el2_lsu_stbuf.scala 170:55] - wire _T_655 = _T_652 & _T_654; // @[el2_lsu_stbuf.scala 170:53] - wire WrPtrEn = _T_651 | _T_655; // @[el2_lsu_stbuf.scala 169:114] - wire _T_660 = _T_652 & _T_650; // @[el2_lsu_stbuf.scala 171:68] - wire [3:0] _T_662 = {3'h0,stbuf_vld_0}; // @[Cat.scala 29:58] - wire [3:0] _T_663 = {3'h0,stbuf_vld_1}; // @[Cat.scala 29:58] - wire [3:0] _T_664 = {3'h0,stbuf_vld_2}; // @[Cat.scala 29:58] - wire [3:0] _T_665 = {3'h0,stbuf_vld_3}; // @[Cat.scala 29:58] - wire [3:0] _T_668 = _T_662 + _T_663; // @[el2_lsu_stbuf.scala 175:102] - wire [3:0] _T_670 = _T_668 + _T_664; // @[el2_lsu_stbuf.scala 175:102] - wire [3:0] stbuf_numvld_any = _T_670 + _T_665; // @[el2_lsu_stbuf.scala 175:102] - wire _T_672 = io_lsu_pkt_m_valid & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 176:40] - wire _T_673 = _T_672 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 176:61] - wire _T_674 = ~io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 176:83] - wire isdccmst_m = _T_673 & _T_674; // @[el2_lsu_stbuf.scala 176:81] - wire _T_675 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 177:40] - wire _T_676 = _T_675 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 177:61] - wire _T_677 = ~io_lsu_pkt_r_dma; // @[el2_lsu_stbuf.scala 177:83] - wire isdccmst_r = _T_676 & _T_677; // @[el2_lsu_stbuf.scala 177:81] - wire [1:0] _T_678 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] - wire _T_679 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 179:63] - wire [2:0] _GEN_39 = {{1'd0}, _T_678}; // @[el2_lsu_stbuf.scala 179:48] - wire [2:0] _T_680 = _GEN_39 << _T_679; // @[el2_lsu_stbuf.scala 179:48] - wire [1:0] _T_681 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] - wire _T_682 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 180:63] - wire [2:0] _GEN_40 = {{1'd0}, _T_681}; // @[el2_lsu_stbuf.scala 180:48] - wire [2:0] _T_683 = _GEN_40 << _T_682; // @[el2_lsu_stbuf.scala 180:48] - wire [1:0] stbuf_specvld_m = _T_680[1:0]; // @[el2_lsu_stbuf.scala 179:20] - wire [3:0] _T_684 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] - wire [3:0] _T_686 = stbuf_numvld_any + _T_684; // @[el2_lsu_stbuf.scala 181:45] - wire [1:0] stbuf_specvld_r = _T_683[1:0]; // @[el2_lsu_stbuf.scala 180:20] - wire [3:0] _T_687 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] - wire [3:0] stbuf_specvld_any = _T_686 + _T_687; // @[el2_lsu_stbuf.scala 181:79] - wire _T_689 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 183:35] - wire _T_690 = _T_689 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 183:48] - wire _T_692 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 183:99] - wire _T_693 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 183:138] - wire _T_787 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_788 = _T_787 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138] - wire _T_791 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_792 = _T_791 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138] - wire _T_795 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_796 = _T_795 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138] - wire _T_799 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_800 = _T_799 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 198:138] - wire [3:0] stbuf_fwdbyteenvec_hi_0 = {_T_800,_T_796,_T_792,_T_788}; // @[Cat.scala 29:58] - wire _T_805 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_806 = _T_805 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138] - wire _T_809 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_810 = _T_809 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138] - wire _T_813 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_814 = _T_813 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138] - wire _T_817 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_818 = _T_817 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 198:138] - wire [3:0] stbuf_fwdbyteenvec_hi_1 = {_T_818,_T_814,_T_810,_T_806}; // @[Cat.scala 29:58] - wire _T_823 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_824 = _T_823 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138] - wire _T_827 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_828 = _T_827 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138] - wire _T_831 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_832 = _T_831 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138] - wire _T_835 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_836 = _T_835 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 198:138] - wire [3:0] stbuf_fwdbyteenvec_hi_2 = {_T_836,_T_832,_T_828,_T_824}; // @[Cat.scala 29:58] - wire _T_841 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_842 = _T_841 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138] - wire _T_845 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_846 = _T_845 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138] - wire _T_849 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_850 = _T_849 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138] - wire _T_853 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 198:117] - wire _T_854 = _T_853 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 198:138] - wire [3:0] stbuf_fwdbyteenvec_hi_3 = {_T_854,_T_850,_T_846,_T_842}; // @[Cat.scala 29:58] - wire _T_859 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_860 = _T_859 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138] - wire _T_863 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_864 = _T_863 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138] - wire _T_867 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_868 = _T_867 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138] - wire _T_871 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_872 = _T_871 & stbuf_vld_0; // @[el2_lsu_stbuf.scala 199:138] - wire [3:0] stbuf_fwdbyteenvec_lo_0 = {_T_872,_T_868,_T_864,_T_860}; // @[Cat.scala 29:58] - wire _T_877 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_878 = _T_877 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138] - wire _T_881 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_882 = _T_881 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138] - wire _T_885 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_886 = _T_885 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138] - wire _T_889 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_890 = _T_889 & stbuf_vld_1; // @[el2_lsu_stbuf.scala 199:138] - wire [3:0] stbuf_fwdbyteenvec_lo_1 = {_T_890,_T_886,_T_882,_T_878}; // @[Cat.scala 29:58] - wire _T_895 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_896 = _T_895 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138] - wire _T_899 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_900 = _T_899 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138] - wire _T_903 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_904 = _T_903 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138] - wire _T_907 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_908 = _T_907 & stbuf_vld_2; // @[el2_lsu_stbuf.scala 199:138] - wire [3:0] stbuf_fwdbyteenvec_lo_2 = {_T_908,_T_904,_T_900,_T_896}; // @[Cat.scala 29:58] - wire _T_913 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_914 = _T_913 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138] - wire _T_917 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_918 = _T_917 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138] - wire _T_921 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_922 = _T_921 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138] - wire _T_925 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 199:117] - wire _T_926 = _T_925 & stbuf_vld_3; // @[el2_lsu_stbuf.scala 199:138] - wire [3:0] stbuf_fwdbyteenvec_lo_3 = {_T_926,_T_922,_T_918,_T_914}; // @[Cat.scala 29:58] - wire _T_933 = stbuf_fwdbyteenvec_hi_0[3] | stbuf_fwdbyteenvec_hi_0[2]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_934 = _T_933 | stbuf_fwdbyteenvec_hi_0[1]; // @[el2_lsu_stbuf.scala 200:156] - wire stbuf_fwdbyteen_hi_pre_m_0 = _T_934 | stbuf_fwdbyteenvec_hi_0[0]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_939 = stbuf_fwdbyteenvec_hi_1[3] | stbuf_fwdbyteenvec_hi_1[2]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_940 = _T_939 | stbuf_fwdbyteenvec_hi_1[1]; // @[el2_lsu_stbuf.scala 200:156] - wire stbuf_fwdbyteen_hi_pre_m_1 = _T_940 | stbuf_fwdbyteenvec_hi_1[0]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_945 = stbuf_fwdbyteenvec_hi_2[3] | stbuf_fwdbyteenvec_hi_2[2]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_946 = _T_945 | stbuf_fwdbyteenvec_hi_2[1]; // @[el2_lsu_stbuf.scala 200:156] - wire stbuf_fwdbyteen_hi_pre_m_2 = _T_946 | stbuf_fwdbyteenvec_hi_2[0]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_951 = stbuf_fwdbyteenvec_hi_3[3] | stbuf_fwdbyteenvec_hi_3[2]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_952 = _T_951 | stbuf_fwdbyteenvec_hi_3[1]; // @[el2_lsu_stbuf.scala 200:156] - wire stbuf_fwdbyteen_hi_pre_m_3 = _T_952 | stbuf_fwdbyteenvec_hi_3[0]; // @[el2_lsu_stbuf.scala 200:156] - wire _T_957 = stbuf_fwdbyteenvec_lo_0[3] | stbuf_fwdbyteenvec_lo_0[2]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_958 = _T_957 | stbuf_fwdbyteenvec_lo_0[1]; // @[el2_lsu_stbuf.scala 201:156] - wire stbuf_fwdbyteen_lo_pre_m_0 = _T_958 | stbuf_fwdbyteenvec_lo_0[0]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_963 = stbuf_fwdbyteenvec_lo_1[3] | stbuf_fwdbyteenvec_lo_1[2]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_964 = _T_963 | stbuf_fwdbyteenvec_lo_1[1]; // @[el2_lsu_stbuf.scala 201:156] - wire stbuf_fwdbyteen_lo_pre_m_1 = _T_964 | stbuf_fwdbyteenvec_lo_1[0]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_969 = stbuf_fwdbyteenvec_lo_2[3] | stbuf_fwdbyteenvec_lo_2[2]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_970 = _T_969 | stbuf_fwdbyteenvec_lo_2[1]; // @[el2_lsu_stbuf.scala 201:156] - wire stbuf_fwdbyteen_lo_pre_m_2 = _T_970 | stbuf_fwdbyteenvec_lo_2[0]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_975 = stbuf_fwdbyteenvec_lo_3[3] | stbuf_fwdbyteenvec_lo_3[2]; // @[el2_lsu_stbuf.scala 201:156] - wire _T_976 = _T_975 | stbuf_fwdbyteenvec_lo_3[1]; // @[el2_lsu_stbuf.scala 201:156] - wire stbuf_fwdbyteen_lo_pre_m_3 = _T_976 | stbuf_fwdbyteenvec_lo_3[0]; // @[el2_lsu_stbuf.scala 201:156] - wire [31:0] _T_979 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_980 = _T_979 & stbuf_data_0; // @[el2_lsu_stbuf.scala 203:98] - wire [31:0] _T_983 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_984 = _T_983 & stbuf_data_1; // @[el2_lsu_stbuf.scala 203:98] - wire [31:0] _T_987 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_988 = _T_987 & stbuf_data_2; // @[el2_lsu_stbuf.scala 203:98] - wire [31:0] _T_991 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_992 = _T_991 & stbuf_data_3; // @[el2_lsu_stbuf.scala 203:98] - wire [31:0] _T_994 = _T_980 | _T_984; // @[el2_lsu_stbuf.scala 203:123] - wire [31:0] _T_995 = _T_994 | _T_988; // @[el2_lsu_stbuf.scala 203:123] - wire [31:0] stbuf_fwddata_hi_pre_m = _T_995 | _T_992; // @[el2_lsu_stbuf.scala 203:123] - wire [31:0] _T_998 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_999 = _T_998 & stbuf_data_0; // @[el2_lsu_stbuf.scala 204:98] - wire [31:0] _T_1002 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1003 = _T_1002 & stbuf_data_1; // @[el2_lsu_stbuf.scala 204:98] - wire [31:0] _T_1006 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1007 = _T_1006 & stbuf_data_2; // @[el2_lsu_stbuf.scala 204:98] - wire [31:0] _T_1010 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_1011 = _T_1010 & stbuf_data_3; // @[el2_lsu_stbuf.scala 204:98] - wire [31:0] _T_1013 = _T_999 | _T_1003; // @[el2_lsu_stbuf.scala 204:123] - wire [31:0] _T_1014 = _T_1013 | _T_1007; // @[el2_lsu_stbuf.scala 204:123] - wire [31:0] stbuf_fwddata_lo_pre_m = _T_1014 | _T_1011; // @[el2_lsu_stbuf.scala 204:123] - wire _T_1019 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 210:50] - wire _T_1020 = _T_1019 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 210:75] - wire _T_1021 = _T_1020 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 210:96] - wire ld_addr_rhit_lo_lo = _T_1021 & _T_677; // @[el2_lsu_stbuf.scala 210:117] - wire _T_1025 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 211:50] - wire _T_1026 = _T_1025 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 211:75] - wire _T_1027 = _T_1026 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 211:96] - wire ld_addr_rhit_lo_hi = _T_1027 & _T_677; // @[el2_lsu_stbuf.scala 211:117] - wire _T_1031 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 212:50] - wire _T_1032 = _T_1031 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 212:75] - wire _T_1033 = _T_1032 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 212:96] - wire _T_1035 = _T_1033 & _T_677; // @[el2_lsu_stbuf.scala 212:117] - wire ld_addr_rhit_hi_lo = _T_1035 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 212:137] - wire _T_1038 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 213:50] - wire _T_1039 = _T_1038 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 213:75] - wire _T_1040 = _T_1039 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 213:96] - wire _T_1042 = _T_1040 & _T_677; // @[el2_lsu_stbuf.scala 213:117] - wire ld_addr_rhit_hi_hi = _T_1042 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 213:137] - wire _T_1044 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 215:80] - wire _T_1046 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 215:80] - wire _T_1048 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 215:80] - wire _T_1050 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 215:80] - wire [3:0] _T_1053 = {_T_1050,_T_1048,_T_1046,_T_1044}; // @[Cat.scala 29:58] - wire _T_1055 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 216:80] - wire _T_1057 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 216:80] - wire _T_1059 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 216:80] - wire _T_1061 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 216:80] - wire [3:0] _T_1064 = {_T_1061,_T_1059,_T_1057,_T_1055}; // @[Cat.scala 29:58] - wire _T_1066 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 217:80] - wire _T_1068 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 217:80] - wire _T_1070 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 217:80] - wire _T_1072 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 217:80] - wire [3:0] _T_1075 = {_T_1072,_T_1070,_T_1068,_T_1066}; // @[Cat.scala 29:58] - wire _T_1077 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 218:80] - wire _T_1079 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 218:80] - wire _T_1081 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 218:80] - wire _T_1083 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 218:80] - wire [3:0] _T_1086 = {_T_1083,_T_1081,_T_1079,_T_1077}; // @[Cat.scala 29:58] - wire [31:0] ld_byte_rhit_hi_lo = {{28'd0}, _T_1075}; // @[el2_lsu_stbuf.scala 217:23] - wire [31:0] ld_byte_rhit_lo_lo = {{28'd0}, _T_1053}; // @[el2_lsu_stbuf.scala 215:23] - wire [31:0] _GEN_42 = {{31'd0}, ld_byte_rhit_hi_lo[0]}; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _T_1088 = ld_byte_rhit_lo_lo | _GEN_42; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _GEN_43 = {{31'd0}, ld_byte_rhit_hi_lo[1]}; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _T_1090 = ld_byte_rhit_lo_lo | _GEN_43; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _GEN_44 = {{31'd0}, ld_byte_rhit_hi_lo[2]}; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _T_1092 = ld_byte_rhit_lo_lo | _GEN_44; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _GEN_45 = {{31'd0}, ld_byte_rhit_hi_lo[3]}; // @[el2_lsu_stbuf.scala 220:77] - wire [31:0] _T_1094 = ld_byte_rhit_lo_lo | _GEN_45; // @[el2_lsu_stbuf.scala 220:77] - wire [127:0] _T_1097 = {_T_1094,_T_1092,_T_1090,_T_1088}; // @[Cat.scala 29:58] - wire [31:0] ld_byte_rhit_hi_hi = {{28'd0}, _T_1086}; // @[el2_lsu_stbuf.scala 218:23] - wire [31:0] ld_byte_rhit_lo_hi = {{28'd0}, _T_1064}; // @[el2_lsu_stbuf.scala 216:23] - wire [31:0] _GEN_46 = {{31'd0}, ld_byte_rhit_hi_hi[0]}; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _T_1099 = ld_byte_rhit_lo_hi | _GEN_46; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _GEN_47 = {{31'd0}, ld_byte_rhit_hi_hi[1]}; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _T_1101 = ld_byte_rhit_lo_hi | _GEN_47; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _GEN_48 = {{31'd0}, ld_byte_rhit_hi_hi[2]}; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _T_1103 = ld_byte_rhit_lo_hi | _GEN_48; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _GEN_49 = {{31'd0}, ld_byte_rhit_hi_hi[3]}; // @[el2_lsu_stbuf.scala 221:77] - wire [31:0] _T_1105 = ld_byte_rhit_lo_hi | _GEN_49; // @[el2_lsu_stbuf.scala 221:77] - wire [127:0] _T_1108 = {_T_1105,_T_1103,_T_1101,_T_1099}; // @[Cat.scala 29:58] - wire [7:0] _T_1111 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1113 = _T_1111 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 223:54] - wire [7:0] _T_1116 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1118 = _T_1116 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 223:115] - wire [7:0] fwdpipe1_lo = _T_1113 | _T_1118; // @[el2_lsu_stbuf.scala 223:81] - wire [7:0] _T_1121 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1123 = _T_1121 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 224:54] - wire [7:0] _T_1126 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1128 = _T_1126 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 224:116] - wire [7:0] fwdpipe2_lo = _T_1123 | _T_1128; // @[el2_lsu_stbuf.scala 224:82] - wire [7:0] _T_1131 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1133 = _T_1131 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 225:54] - wire [7:0] _T_1136 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1138 = _T_1136 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 225:117] - wire [7:0] fwdpipe3_lo = _T_1133 | _T_1138; // @[el2_lsu_stbuf.scala 225:83] - wire [7:0] _T_1141 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1143 = _T_1141 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 226:54] - wire [7:0] _T_1146 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [23:0] _GEN_50 = {{16'd0}, _T_1146}; // @[el2_lsu_stbuf.scala 226:117] - wire [23:0] _T_1148 = _GEN_50 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 226:117] - wire [23:0] _GEN_51 = {{16'd0}, _T_1143}; // @[el2_lsu_stbuf.scala 226:83] - wire [23:0] fwdpipe4_lo = _GEN_51 | _T_1148; // @[el2_lsu_stbuf.scala 226:83] - wire [47:0] _T_1151 = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] - wire [7:0] _T_1154 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1156 = _T_1154 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 229:54] - wire [7:0] _T_1159 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1161 = _T_1159 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 229:115] - wire [7:0] fwdpipe1_hi = _T_1156 | _T_1161; // @[el2_lsu_stbuf.scala 229:81] - wire [7:0] _T_1164 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1166 = _T_1164 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 230:54] - wire [7:0] _T_1169 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1171 = _T_1169 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 230:116] - wire [7:0] fwdpipe2_hi = _T_1166 | _T_1171; // @[el2_lsu_stbuf.scala 230:82] - wire [7:0] _T_1174 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1176 = _T_1174 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 231:54] - wire [7:0] _T_1179 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1181 = _T_1179 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 231:117] - wire [7:0] fwdpipe3_hi = _T_1176 | _T_1181; // @[el2_lsu_stbuf.scala 231:83] - wire [7:0] _T_1184 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_1186 = _T_1184 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 232:54] - wire [7:0] _T_1189 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [23:0] _GEN_52 = {{16'd0}, _T_1189}; // @[el2_lsu_stbuf.scala 232:117] - wire [23:0] _T_1191 = _GEN_52 & io_store_data_hi_r[31:8]; // @[el2_lsu_stbuf.scala 232:117] - wire [23:0] _GEN_53 = {{16'd0}, _T_1186}; // @[el2_lsu_stbuf.scala 232:83] - wire [23:0] fwdpipe4_hi = _GEN_53 | _T_1191; // @[el2_lsu_stbuf.scala 232:83] - wire [47:0] _T_1194 = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] - wire [2:0] _T_1204 = {stbuf_fwdbyteen_hi_pre_m_3,stbuf_fwdbyteen_hi_pre_m_2,stbuf_fwdbyteen_hi_pre_m_1}; // @[Cat.scala 29:58] - wire [2:0] _T_1215 = {stbuf_fwdbyteen_lo_pre_m_3,stbuf_fwdbyteen_lo_pre_m_2,stbuf_fwdbyteen_lo_pre_m_1}; // @[Cat.scala 29:58] - wire [3:0] ld_byte_rhit_lo = _T_1097[3:0]; // @[el2_lsu_stbuf.scala 220:20] - wire [31:0] ld_fwddata_rpipe_lo = _T_1151[31:0]; // @[el2_lsu_stbuf.scala 227:24] - wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 239:31] - wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 240:31] - wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 241:31] - wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 242:31] - wire [15:0] _T_1229 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] - wire [15:0] _T_1230 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] - wire [3:0] ld_byte_rhit_hi = _T_1108[3:0]; // @[el2_lsu_stbuf.scala 221:20] - wire [31:0] ld_fwddata_rpipe_hi = _T_1194[31:0]; // @[el2_lsu_stbuf.scala 233:24] - wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 245:31] - wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 246:31] - wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 247:31] - wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 248:31] - wire [15:0] _T_1244 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] - wire [15:0] _T_1245 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] - assign io_stbuf_reqvld_any = _T_643 & _T_645; // @[el2_lsu_stbuf.scala 50:47 el2_lsu_stbuf.scala 165:25] - assign io_stbuf_reqvld_flushed_any = _GEN_23 & _GEN_27; // @[el2_lsu_stbuf.scala 51:36 el2_lsu_stbuf.scala 164:32] - assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_30; // @[el2_lsu_stbuf.scala 52:35 el2_lsu_stbuf.scala 166:23] - assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_34; // @[el2_lsu_stbuf.scala 53:35 el2_lsu_stbuf.scala 167:23] - assign io_lsu_stbuf_full_any = _T_690 ? _T_692 : _T_693; // @[el2_lsu_stbuf.scala 54:43 el2_lsu_stbuf.scala 183:27] - assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 122:27] - assign io_stbuf_fwddata_hi_m = {_T_1245,_T_1244}; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 249:26] - assign io_stbuf_fwddata_lo_m = {_T_1230,_T_1229}; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 243:26] - assign io_stbuf_fwdbyteen_hi_m = {_T_1204,stbuf_fwdbyteen_hi_pre_m_0}; // @[el2_lsu_stbuf.scala 59:37 el2_lsu_stbuf.scala 235:28] - assign io_stbuf_fwdbyteen_lo_m = {_T_1215,stbuf_fwdbyteen_lo_pre_m_0}; // @[el2_lsu_stbuf.scala 60:37 el2_lsu_stbuf.scala 236:28] + wire [1:0] WrPtrPlus1 = WrPtr + 2'h1; // @[el2_lsu_stbuf.scala 126:26] + wire [1:0] WrPtrPlus2 = WrPtr + 2'h2; // @[el2_lsu_stbuf.scala 127:26] + reg [15:0] stbuf_addr_0; // @[el2_lib.scala 514:16] + wire _T_27 = stbuf_addr_0[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + reg _T_588; // @[el2_lsu_stbuf.scala 164:88] + reg _T_580; // @[el2_lsu_stbuf.scala 164:88] + reg _T_572; // @[el2_lsu_stbuf.scala 164:88] + reg _T_564; // @[el2_lsu_stbuf.scala 164:88] + wire [3:0] stbuf_vld = {_T_588,_T_580,_T_572,_T_564}; // @[Cat.scala 29:58] + wire _T_29 = _T_27 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 131:179] + reg _T_623; // @[el2_lsu_stbuf.scala 166:92] + reg _T_615; // @[el2_lsu_stbuf.scala 166:92] + reg _T_607; // @[el2_lsu_stbuf.scala 166:92] + reg _T_599; // @[el2_lsu_stbuf.scala 166:92] + wire [3:0] stbuf_dma_kill = {_T_623,_T_615,_T_607,_T_599}; // @[Cat.scala 29:58] + wire _T_31 = ~stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 131:197] + wire _T_32 = _T_29 & _T_31; // @[el2_lsu_stbuf.scala 131:195] + wire _T_212 = io_lsu_stbuf_commit_any | io_stbuf_reqvld_flushed_any; // @[el2_lsu_stbuf.scala 142:78] + wire _T_213 = 2'h3 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] + wire _T_215 = _T_212 & _T_213; // @[el2_lsu_stbuf.scala 142:109] + wire _T_209 = 2'h2 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] + wire _T_211 = _T_212 & _T_209; // @[el2_lsu_stbuf.scala 142:109] + wire _T_205 = 2'h1 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] + wire _T_207 = _T_212 & _T_205; // @[el2_lsu_stbuf.scala 142:109] + wire _T_201 = 2'h0 == RdPtr; // @[el2_lsu_stbuf.scala 142:121] + wire _T_203 = _T_212 & _T_201; // @[el2_lsu_stbuf.scala 142:109] + wire [3:0] stbuf_reset = {_T_215,_T_211,_T_207,_T_203}; // @[Cat.scala 29:58] + wire _T_34 = ~stbuf_reset[0]; // @[el2_lsu_stbuf.scala 131:218] + wire _T_35 = _T_32 & _T_34; // @[el2_lsu_stbuf.scala 131:216] + reg [15:0] stbuf_addr_1; // @[el2_lib.scala 514:16] + wire _T_38 = stbuf_addr_1[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_40 = _T_38 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_42 = ~stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 131:197] + wire _T_43 = _T_40 & _T_42; // @[el2_lsu_stbuf.scala 131:195] + wire _T_45 = ~stbuf_reset[1]; // @[el2_lsu_stbuf.scala 131:218] + wire _T_46 = _T_43 & _T_45; // @[el2_lsu_stbuf.scala 131:216] + reg [15:0] stbuf_addr_2; // @[el2_lib.scala 514:16] + wire _T_49 = stbuf_addr_2[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_51 = _T_49 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_53 = ~stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 131:197] + wire _T_54 = _T_51 & _T_53; // @[el2_lsu_stbuf.scala 131:195] + wire _T_56 = ~stbuf_reset[2]; // @[el2_lsu_stbuf.scala 131:218] + wire _T_57 = _T_54 & _T_56; // @[el2_lsu_stbuf.scala 131:216] + reg [15:0] stbuf_addr_3; // @[el2_lib.scala 514:16] + wire _T_60 = stbuf_addr_3[15:2] == io_lsu_addr_r[15:2]; // @[el2_lsu_stbuf.scala 131:120] + wire _T_62 = _T_60 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 131:179] + wire _T_64 = ~stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 131:197] + wire _T_65 = _T_62 & _T_64; // @[el2_lsu_stbuf.scala 131:195] + wire _T_67 = ~stbuf_reset[3]; // @[el2_lsu_stbuf.scala 131:218] + wire _T_68 = _T_65 & _T_67; // @[el2_lsu_stbuf.scala 131:216] + wire [3:0] store_matchvec_lo_r = {_T_68,_T_57,_T_46,_T_35}; // @[Cat.scala 29:58] + wire _T_73 = stbuf_addr_0[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] + wire _T_75 = _T_73 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 132:179] + wire _T_78 = _T_75 & _T_31; // @[el2_lsu_stbuf.scala 132:194] + wire _T_79 = _T_78 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] + wire _T_82 = _T_79 & _T_34; // @[el2_lsu_stbuf.scala 132:236] + wire _T_85 = stbuf_addr_1[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] + wire _T_87 = _T_85 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 132:179] + wire _T_90 = _T_87 & _T_42; // @[el2_lsu_stbuf.scala 132:194] + wire _T_91 = _T_90 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] + wire _T_94 = _T_91 & _T_45; // @[el2_lsu_stbuf.scala 132:236] + wire _T_97 = stbuf_addr_2[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] + wire _T_99 = _T_97 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 132:179] + wire _T_102 = _T_99 & _T_53; // @[el2_lsu_stbuf.scala 132:194] + wire _T_103 = _T_102 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] + wire _T_106 = _T_103 & _T_56; // @[el2_lsu_stbuf.scala 132:236] + wire _T_109 = stbuf_addr_3[15:2] == io_end_addr_r[15:2]; // @[el2_lsu_stbuf.scala 132:120] + wire _T_111 = _T_109 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 132:179] + wire _T_114 = _T_111 & _T_64; // @[el2_lsu_stbuf.scala 132:194] + wire _T_115 = _T_114 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 132:215] + wire _T_118 = _T_115 & _T_67; // @[el2_lsu_stbuf.scala 132:236] + wire [3:0] store_matchvec_hi_r = {_T_118,_T_106,_T_94,_T_82}; // @[Cat.scala 29:58] + wire store_coalesce_lo_r = |store_matchvec_lo_r; // @[el2_lsu_stbuf.scala 134:49] + wire store_coalesce_hi_r = |store_matchvec_hi_r; // @[el2_lsu_stbuf.scala 135:49] + wire _T_121 = 2'h0 == WrPtr; // @[el2_lsu_stbuf.scala 138:16] + wire _T_122 = ~store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 138:29] + wire _T_123 = _T_121 & _T_122; // @[el2_lsu_stbuf.scala 138:27] + wire _T_125 = _T_121 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:29] + wire _T_126 = ~store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 139:52] + wire _T_127 = _T_125 & _T_126; // @[el2_lsu_stbuf.scala 139:50] + wire _T_128 = _T_123 | _T_127; // @[el2_lsu_stbuf.scala 138:51] + wire _T_129 = 2'h0 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:18] + wire _T_130 = _T_129 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:34] + wire _T_131 = store_coalesce_lo_r | store_coalesce_hi_r; // @[el2_lsu_stbuf.scala 140:79] + wire _T_132 = ~_T_131; // @[el2_lsu_stbuf.scala 140:57] + wire _T_133 = _T_130 & _T_132; // @[el2_lsu_stbuf.scala 140:55] + wire _T_134 = _T_128 | _T_133; // @[el2_lsu_stbuf.scala 139:74] + wire _T_136 = _T_134 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 140:103] + wire _T_138 = _T_136 | store_matchvec_hi_r[0]; // @[el2_lsu_stbuf.scala 141:30] + wire _T_139 = io_ldst_stbuf_reqvld_r & _T_138; // @[el2_lsu_stbuf.scala 137:76] + wire _T_140 = 2'h1 == WrPtr; // @[el2_lsu_stbuf.scala 138:16] + wire _T_142 = _T_140 & _T_122; // @[el2_lsu_stbuf.scala 138:27] + wire _T_144 = _T_140 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:29] + wire _T_146 = _T_144 & _T_126; // @[el2_lsu_stbuf.scala 139:50] + wire _T_147 = _T_142 | _T_146; // @[el2_lsu_stbuf.scala 138:51] + wire _T_148 = 2'h1 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:18] + wire _T_149 = _T_148 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:34] + wire _T_152 = _T_149 & _T_132; // @[el2_lsu_stbuf.scala 140:55] + wire _T_153 = _T_147 | _T_152; // @[el2_lsu_stbuf.scala 139:74] + wire _T_155 = _T_153 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 140:103] + wire _T_157 = _T_155 | store_matchvec_hi_r[1]; // @[el2_lsu_stbuf.scala 141:30] + wire _T_158 = io_ldst_stbuf_reqvld_r & _T_157; // @[el2_lsu_stbuf.scala 137:76] + wire _T_159 = 2'h2 == WrPtr; // @[el2_lsu_stbuf.scala 138:16] + wire _T_161 = _T_159 & _T_122; // @[el2_lsu_stbuf.scala 138:27] + wire _T_163 = _T_159 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:29] + wire _T_165 = _T_163 & _T_126; // @[el2_lsu_stbuf.scala 139:50] + wire _T_166 = _T_161 | _T_165; // @[el2_lsu_stbuf.scala 138:51] + wire _T_167 = 2'h2 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:18] + wire _T_168 = _T_167 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:34] + wire _T_171 = _T_168 & _T_132; // @[el2_lsu_stbuf.scala 140:55] + wire _T_172 = _T_166 | _T_171; // @[el2_lsu_stbuf.scala 139:74] + wire _T_174 = _T_172 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 140:103] + wire _T_176 = _T_174 | store_matchvec_hi_r[2]; // @[el2_lsu_stbuf.scala 141:30] + wire _T_177 = io_ldst_stbuf_reqvld_r & _T_176; // @[el2_lsu_stbuf.scala 137:76] + wire _T_178 = 2'h3 == WrPtr; // @[el2_lsu_stbuf.scala 138:16] + wire _T_180 = _T_178 & _T_122; // @[el2_lsu_stbuf.scala 138:27] + wire _T_182 = _T_178 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 139:29] + wire _T_184 = _T_182 & _T_126; // @[el2_lsu_stbuf.scala 139:50] + wire _T_185 = _T_180 | _T_184; // @[el2_lsu_stbuf.scala 138:51] + wire _T_186 = 2'h3 == WrPtrPlus1; // @[el2_lsu_stbuf.scala 140:18] + wire _T_187 = _T_186 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 140:34] + wire _T_190 = _T_187 & _T_132; // @[el2_lsu_stbuf.scala 140:55] + wire _T_191 = _T_185 | _T_190; // @[el2_lsu_stbuf.scala 139:74] + wire _T_193 = _T_191 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 140:103] + wire _T_195 = _T_193 | store_matchvec_hi_r[3]; // @[el2_lsu_stbuf.scala 141:30] + wire _T_196 = io_ldst_stbuf_reqvld_r & _T_195; // @[el2_lsu_stbuf.scala 137:76] + wire [3:0] stbuf_wr_en = {_T_196,_T_177,_T_158,_T_139}; // @[Cat.scala 29:58] + wire _T_219 = ~ldst_dual_r; // @[el2_lsu_stbuf.scala 143:53] + wire _T_220 = _T_219 | io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 143:66] + wire _T_223 = _T_220 & _T_121; // @[el2_lsu_stbuf.scala 143:93] + wire _T_225 = _T_223 & _T_122; // @[el2_lsu_stbuf.scala 143:123] + wire _T_227 = _T_225 | store_matchvec_lo_r[0]; // @[el2_lsu_stbuf.scala 143:147] + wire _T_232 = _T_220 & _T_140; // @[el2_lsu_stbuf.scala 143:93] + wire _T_234 = _T_232 & _T_122; // @[el2_lsu_stbuf.scala 143:123] + wire _T_236 = _T_234 | store_matchvec_lo_r[1]; // @[el2_lsu_stbuf.scala 143:147] + wire _T_241 = _T_220 & _T_159; // @[el2_lsu_stbuf.scala 143:93] + wire _T_243 = _T_241 & _T_122; // @[el2_lsu_stbuf.scala 143:123] + wire _T_245 = _T_243 | store_matchvec_lo_r[2]; // @[el2_lsu_stbuf.scala 143:147] + wire _T_250 = _T_220 & _T_178; // @[el2_lsu_stbuf.scala 143:93] + wire _T_252 = _T_250 & _T_122; // @[el2_lsu_stbuf.scala 143:123] + wire _T_254 = _T_252 | store_matchvec_lo_r[3]; // @[el2_lsu_stbuf.scala 143:147] + wire [3:0] sel_lo = {_T_254,_T_245,_T_236,_T_227}; // @[Cat.scala 29:58] + reg [3:0] stbuf_byteen_0; // @[el2_lsu_stbuf.scala 167:92] + wire [3:0] _T_274 = stbuf_byteen_0 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:86] + wire [3:0] _T_275 = stbuf_byteen_0 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:123] + wire [3:0] stbuf_byteenin_0 = sel_lo[0] ? _T_274 : _T_275; // @[el2_lsu_stbuf.scala 146:58] + reg [3:0] stbuf_byteen_1; // @[el2_lsu_stbuf.scala 167:92] + wire [3:0] _T_278 = stbuf_byteen_1 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:86] + wire [3:0] _T_279 = stbuf_byteen_1 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:123] + wire [3:0] stbuf_byteenin_1 = sel_lo[1] ? _T_278 : _T_279; // @[el2_lsu_stbuf.scala 146:58] + reg [3:0] stbuf_byteen_2; // @[el2_lsu_stbuf.scala 167:92] + wire [3:0] _T_282 = stbuf_byteen_2 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:86] + wire [3:0] _T_283 = stbuf_byteen_2 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:123] + wire [3:0] stbuf_byteenin_2 = sel_lo[2] ? _T_282 : _T_283; // @[el2_lsu_stbuf.scala 146:58] + reg [3:0] stbuf_byteen_3; // @[el2_lsu_stbuf.scala 167:92] + wire [3:0] _T_286 = stbuf_byteen_3 | store_byteen_lo_r; // @[el2_lsu_stbuf.scala 146:86] + wire [3:0] _T_287 = stbuf_byteen_3 | store_byteen_hi_r; // @[el2_lsu_stbuf.scala 146:123] + wire [3:0] stbuf_byteenin_3 = sel_lo[3] ? _T_286 : _T_287; // @[el2_lsu_stbuf.scala 146:58] + wire _T_291 = ~stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 148:67] + wire _T_293 = _T_291 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:87] + reg [31:0] stbuf_data_0; // @[el2_lib.scala 514:16] + wire [7:0] _T_296 = _T_293 ? io_store_datafn_lo_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 148:66] + wire _T_300 = _T_291 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:29] + wire [7:0] _T_303 = _T_300 ? io_store_datafn_hi_r[7:0] : stbuf_data_0[7:0]; // @[el2_lsu_stbuf.scala 149:8] + wire [7:0] datain1_0 = sel_lo[0] ? _T_296 : _T_303; // @[el2_lsu_stbuf.scala 148:51] + wire _T_307 = ~stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 148:67] + wire _T_309 = _T_307 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:87] + reg [31:0] stbuf_data_1; // @[el2_lib.scala 514:16] + wire [7:0] _T_312 = _T_309 ? io_store_datafn_lo_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 148:66] + wire _T_316 = _T_307 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:29] + wire [7:0] _T_319 = _T_316 ? io_store_datafn_hi_r[7:0] : stbuf_data_1[7:0]; // @[el2_lsu_stbuf.scala 149:8] + wire [7:0] datain1_1 = sel_lo[1] ? _T_312 : _T_319; // @[el2_lsu_stbuf.scala 148:51] + wire _T_323 = ~stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 148:67] + wire _T_325 = _T_323 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:87] + reg [31:0] stbuf_data_2; // @[el2_lib.scala 514:16] + wire [7:0] _T_328 = _T_325 ? io_store_datafn_lo_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 148:66] + wire _T_332 = _T_323 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:29] + wire [7:0] _T_335 = _T_332 ? io_store_datafn_hi_r[7:0] : stbuf_data_2[7:0]; // @[el2_lsu_stbuf.scala 149:8] + wire [7:0] datain1_2 = sel_lo[2] ? _T_328 : _T_335; // @[el2_lsu_stbuf.scala 148:51] + wire _T_339 = ~stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 148:67] + wire _T_341 = _T_339 | store_byteen_lo_r[0]; // @[el2_lsu_stbuf.scala 148:87] + reg [31:0] stbuf_data_3; // @[el2_lib.scala 514:16] + wire [7:0] _T_344 = _T_341 ? io_store_datafn_lo_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 148:66] + wire _T_348 = _T_339 | store_byteen_hi_r[0]; // @[el2_lsu_stbuf.scala 149:29] + wire [7:0] _T_351 = _T_348 ? io_store_datafn_hi_r[7:0] : stbuf_data_3[7:0]; // @[el2_lsu_stbuf.scala 149:8] + wire [7:0] datain1_3 = sel_lo[3] ? _T_344 : _T_351; // @[el2_lsu_stbuf.scala 148:51] + wire _T_355 = ~stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 151:68] + wire _T_357 = _T_355 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:88] + wire [7:0] _T_360 = _T_357 ? io_store_datafn_lo_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 151:67] + wire _T_364 = _T_355 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:29] + wire [7:0] _T_367 = _T_364 ? io_store_datafn_hi_r[15:8] : stbuf_data_0[15:8]; // @[el2_lsu_stbuf.scala 152:8] + wire [7:0] datain2_0 = sel_lo[0] ? _T_360 : _T_367; // @[el2_lsu_stbuf.scala 151:52] + wire _T_371 = ~stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 151:68] + wire _T_373 = _T_371 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:88] + wire [7:0] _T_376 = _T_373 ? io_store_datafn_lo_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 151:67] + wire _T_380 = _T_371 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:29] + wire [7:0] _T_383 = _T_380 ? io_store_datafn_hi_r[15:8] : stbuf_data_1[15:8]; // @[el2_lsu_stbuf.scala 152:8] + wire [7:0] datain2_1 = sel_lo[1] ? _T_376 : _T_383; // @[el2_lsu_stbuf.scala 151:52] + wire _T_387 = ~stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 151:68] + wire _T_389 = _T_387 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:88] + wire [7:0] _T_392 = _T_389 ? io_store_datafn_lo_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 151:67] + wire _T_396 = _T_387 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:29] + wire [7:0] _T_399 = _T_396 ? io_store_datafn_hi_r[15:8] : stbuf_data_2[15:8]; // @[el2_lsu_stbuf.scala 152:8] + wire [7:0] datain2_2 = sel_lo[2] ? _T_392 : _T_399; // @[el2_lsu_stbuf.scala 151:52] + wire _T_403 = ~stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 151:68] + wire _T_405 = _T_403 | store_byteen_lo_r[1]; // @[el2_lsu_stbuf.scala 151:88] + wire [7:0] _T_408 = _T_405 ? io_store_datafn_lo_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 151:67] + wire _T_412 = _T_403 | store_byteen_hi_r[1]; // @[el2_lsu_stbuf.scala 152:29] + wire [7:0] _T_415 = _T_412 ? io_store_datafn_hi_r[15:8] : stbuf_data_3[15:8]; // @[el2_lsu_stbuf.scala 152:8] + wire [7:0] datain2_3 = sel_lo[3] ? _T_408 : _T_415; // @[el2_lsu_stbuf.scala 151:52] + wire _T_419 = ~stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 154:68] + wire _T_421 = _T_419 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:88] + wire [7:0] _T_424 = _T_421 ? io_store_datafn_lo_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 154:67] + wire _T_428 = _T_419 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:29] + wire [7:0] _T_431 = _T_428 ? io_store_datafn_hi_r[23:16] : stbuf_data_0[23:16]; // @[el2_lsu_stbuf.scala 155:8] + wire [7:0] datain3_0 = sel_lo[0] ? _T_424 : _T_431; // @[el2_lsu_stbuf.scala 154:52] + wire _T_435 = ~stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 154:68] + wire _T_437 = _T_435 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:88] + wire [7:0] _T_440 = _T_437 ? io_store_datafn_lo_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 154:67] + wire _T_444 = _T_435 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:29] + wire [7:0] _T_447 = _T_444 ? io_store_datafn_hi_r[23:16] : stbuf_data_1[23:16]; // @[el2_lsu_stbuf.scala 155:8] + wire [7:0] datain3_1 = sel_lo[1] ? _T_440 : _T_447; // @[el2_lsu_stbuf.scala 154:52] + wire _T_451 = ~stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 154:68] + wire _T_453 = _T_451 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:88] + wire [7:0] _T_456 = _T_453 ? io_store_datafn_lo_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 154:67] + wire _T_460 = _T_451 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:29] + wire [7:0] _T_463 = _T_460 ? io_store_datafn_hi_r[23:16] : stbuf_data_2[23:16]; // @[el2_lsu_stbuf.scala 155:8] + wire [7:0] datain3_2 = sel_lo[2] ? _T_456 : _T_463; // @[el2_lsu_stbuf.scala 154:52] + wire _T_467 = ~stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 154:68] + wire _T_469 = _T_467 | store_byteen_lo_r[2]; // @[el2_lsu_stbuf.scala 154:88] + wire [7:0] _T_472 = _T_469 ? io_store_datafn_lo_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 154:67] + wire _T_476 = _T_467 | store_byteen_hi_r[2]; // @[el2_lsu_stbuf.scala 155:29] + wire [7:0] _T_479 = _T_476 ? io_store_datafn_hi_r[23:16] : stbuf_data_3[23:16]; // @[el2_lsu_stbuf.scala 155:8] + wire [7:0] datain3_3 = sel_lo[3] ? _T_472 : _T_479; // @[el2_lsu_stbuf.scala 154:52] + wire _T_483 = ~stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 157:68] + wire _T_485 = _T_483 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:88] + wire [7:0] _T_488 = _T_485 ? io_store_datafn_lo_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 157:67] + wire _T_492 = _T_483 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:29] + wire [7:0] _T_495 = _T_492 ? io_store_datafn_hi_r[31:24] : stbuf_data_0[31:24]; // @[el2_lsu_stbuf.scala 158:8] + wire [7:0] datain4_0 = sel_lo[0] ? _T_488 : _T_495; // @[el2_lsu_stbuf.scala 157:52] + wire _T_499 = ~stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 157:68] + wire _T_501 = _T_499 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:88] + wire [7:0] _T_504 = _T_501 ? io_store_datafn_lo_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 157:67] + wire _T_508 = _T_499 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:29] + wire [7:0] _T_511 = _T_508 ? io_store_datafn_hi_r[31:24] : stbuf_data_1[31:24]; // @[el2_lsu_stbuf.scala 158:8] + wire [7:0] datain4_1 = sel_lo[1] ? _T_504 : _T_511; // @[el2_lsu_stbuf.scala 157:52] + wire _T_515 = ~stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 157:68] + wire _T_517 = _T_515 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:88] + wire [7:0] _T_520 = _T_517 ? io_store_datafn_lo_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 157:67] + wire _T_524 = _T_515 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:29] + wire [7:0] _T_527 = _T_524 ? io_store_datafn_hi_r[31:24] : stbuf_data_2[31:24]; // @[el2_lsu_stbuf.scala 158:8] + wire [7:0] datain4_2 = sel_lo[2] ? _T_520 : _T_527; // @[el2_lsu_stbuf.scala 157:52] + wire _T_531 = ~stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 157:68] + wire _T_533 = _T_531 | store_byteen_lo_r[3]; // @[el2_lsu_stbuf.scala 157:88] + wire [7:0] _T_536 = _T_533 ? io_store_datafn_lo_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 157:67] + wire _T_540 = _T_531 | store_byteen_hi_r[3]; // @[el2_lsu_stbuf.scala 158:29] + wire [7:0] _T_543 = _T_540 ? io_store_datafn_hi_r[31:24] : stbuf_data_3[31:24]; // @[el2_lsu_stbuf.scala 158:8] + wire [7:0] datain4_3 = sel_lo[3] ? _T_536 : _T_543; // @[el2_lsu_stbuf.scala 157:52] + wire [15:0] _T_545 = {datain2_0,datain1_0}; // @[Cat.scala 29:58] + wire [15:0] _T_546 = {datain4_0,datain3_0}; // @[Cat.scala 29:58] + wire [15:0] _T_548 = {datain2_1,datain1_1}; // @[Cat.scala 29:58] + wire [15:0] _T_549 = {datain4_1,datain3_1}; // @[Cat.scala 29:58] + wire [15:0] _T_551 = {datain2_2,datain1_2}; // @[Cat.scala 29:58] + wire [15:0] _T_552 = {datain4_2,datain3_2}; // @[Cat.scala 29:58] + wire [15:0] _T_554 = {datain2_3,datain1_3}; // @[Cat.scala 29:58] + wire [15:0] _T_555 = {datain4_3,datain3_3}; // @[Cat.scala 29:58] + wire _T_560 = stbuf_wr_en[0] | stbuf_vld[0]; // @[el2_lsu_stbuf.scala 164:92] + wire _T_568 = stbuf_wr_en[1] | stbuf_vld[1]; // @[el2_lsu_stbuf.scala 164:92] + wire _T_576 = stbuf_wr_en[2] | stbuf_vld[2]; // @[el2_lsu_stbuf.scala 164:92] + wire _T_584 = stbuf_wr_en[3] | stbuf_vld[3]; // @[el2_lsu_stbuf.scala 164:92] + wire [15:0] cmpaddr_hi_m = {{2'd0}, io_end_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 206:16] + wire _T_789 = stbuf_addr_3[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:115] + wire _T_791 = _T_789 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 212:139] + wire _T_794 = _T_791 & _T_64; // @[el2_lsu_stbuf.scala 212:154] + wire _T_795 = _T_794 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:175] + wire _T_780 = stbuf_addr_2[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:115] + wire _T_782 = _T_780 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 212:139] + wire _T_785 = _T_782 & _T_53; // @[el2_lsu_stbuf.scala 212:154] + wire _T_786 = _T_785 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:175] + wire _T_771 = stbuf_addr_1[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:115] + wire _T_773 = _T_771 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 212:139] + wire _T_776 = _T_773 & _T_42; // @[el2_lsu_stbuf.scala 212:154] + wire _T_777 = _T_776 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:175] + wire _T_762 = stbuf_addr_0[15:2] == cmpaddr_hi_m[13:0]; // @[el2_lsu_stbuf.scala 212:115] + wire _T_764 = _T_762 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 212:139] + wire _T_767 = _T_764 & _T_31; // @[el2_lsu_stbuf.scala 212:154] + wire _T_768 = _T_767 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 212:175] + wire [3:0] stbuf_match_hi = {_T_795,_T_786,_T_777,_T_768}; // @[Cat.scala 29:58] + wire [15:0] cmpaddr_lo_m = {{2'd0}, io_lsu_addr_m[15:2]}; // @[el2_lsu_stbuf.scala 209:17] + wire _T_827 = stbuf_addr_3[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:115] + wire _T_829 = _T_827 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 213:139] + wire _T_832 = _T_829 & _T_64; // @[el2_lsu_stbuf.scala 213:154] + wire _T_833 = _T_832 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:175] + wire _T_818 = stbuf_addr_2[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:115] + wire _T_820 = _T_818 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 213:139] + wire _T_823 = _T_820 & _T_53; // @[el2_lsu_stbuf.scala 213:154] + wire _T_824 = _T_823 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:175] + wire _T_809 = stbuf_addr_1[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:115] + wire _T_811 = _T_809 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 213:139] + wire _T_814 = _T_811 & _T_42; // @[el2_lsu_stbuf.scala 213:154] + wire _T_815 = _T_814 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:175] + wire _T_800 = stbuf_addr_0[15:2] == cmpaddr_lo_m[13:0]; // @[el2_lsu_stbuf.scala 213:115] + wire _T_802 = _T_800 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 213:139] + wire _T_805 = _T_802 & _T_31; // @[el2_lsu_stbuf.scala 213:154] + wire _T_806 = _T_805 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 213:175] + wire [3:0] stbuf_match_lo = {_T_833,_T_824,_T_815,_T_806}; // @[Cat.scala 29:58] + wire _T_856 = stbuf_match_hi[3] | stbuf_match_lo[3]; // @[el2_lsu_stbuf.scala 214:78] + wire _T_857 = _T_856 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:99] + wire _T_858 = _T_857 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:120] + wire _T_859 = _T_858 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:139] + wire _T_850 = stbuf_match_hi[2] | stbuf_match_lo[2]; // @[el2_lsu_stbuf.scala 214:78] + wire _T_851 = _T_850 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:99] + wire _T_852 = _T_851 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:120] + wire _T_853 = _T_852 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:139] + wire _T_844 = stbuf_match_hi[1] | stbuf_match_lo[1]; // @[el2_lsu_stbuf.scala 214:78] + wire _T_845 = _T_844 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:99] + wire _T_846 = _T_845 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:120] + wire _T_847 = _T_846 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:139] + wire _T_838 = stbuf_match_hi[0] | stbuf_match_lo[0]; // @[el2_lsu_stbuf.scala 214:78] + wire _T_839 = _T_838 & io_lsu_pkt_m_valid; // @[el2_lsu_stbuf.scala 214:99] + wire _T_840 = _T_839 & io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 214:120] + wire _T_841 = _T_840 & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 214:139] + wire [3:0] stbuf_dma_kill_en = {_T_859,_T_853,_T_847,_T_841}; // @[Cat.scala 29:58] + wire _T_595 = stbuf_dma_kill_en[0] | stbuf_dma_kill[0]; // @[el2_lsu_stbuf.scala 166:96] + wire _T_603 = stbuf_dma_kill_en[1] | stbuf_dma_kill[1]; // @[el2_lsu_stbuf.scala 166:96] + wire _T_611 = stbuf_dma_kill_en[2] | stbuf_dma_kill[2]; // @[el2_lsu_stbuf.scala 166:96] + wire _T_619 = stbuf_dma_kill_en[3] | stbuf_dma_kill[3]; // @[el2_lsu_stbuf.scala 166:96] + wire [3:0] _T_629 = stbuf_wr_en[0] ? stbuf_byteenin_0 : stbuf_byteen_0; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_633 = _T_34 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_638 = stbuf_wr_en[1] ? stbuf_byteenin_1 : stbuf_byteen_1; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_642 = _T_45 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_647 = stbuf_wr_en[2] ? stbuf_byteenin_2 : stbuf_byteen_2; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_651 = _T_56 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_656 = stbuf_wr_en[3] ? stbuf_byteenin_3 : stbuf_byteen_3; // @[el2_lsu_stbuf.scala 167:96] + wire [3:0] _T_660 = _T_67 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg ldst_dual_m; // @[el2_lsu_stbuf.scala 176:52] + wire [3:0] _T_689 = stbuf_vld >> RdPtr; // @[el2_lsu_stbuf.scala 180:43] + wire [3:0] _T_691 = stbuf_dma_kill >> RdPtr; // @[el2_lsu_stbuf.scala 180:67] + wire _T_698 = ~_T_691[0]; // @[el2_lsu_stbuf.scala 181:46] + wire _T_699 = _T_689[0] & _T_698; // @[el2_lsu_stbuf.scala 181:44] + wire _T_700 = |stbuf_dma_kill_en; // @[el2_lsu_stbuf.scala 181:91] + wire _T_701 = ~_T_700; // @[el2_lsu_stbuf.scala 181:71] + wire [15:0] _GEN_1 = 2'h1 == RdPtr ? stbuf_addr_1 : stbuf_addr_0; // @[el2_lsu_stbuf.scala 182:22] + wire [15:0] _GEN_2 = 2'h2 == RdPtr ? stbuf_addr_2 : _GEN_1; // @[el2_lsu_stbuf.scala 182:22] + wire [31:0] _GEN_5 = 2'h1 == RdPtr ? stbuf_data_1 : stbuf_data_0; // @[el2_lsu_stbuf.scala 183:22] + wire [31:0] _GEN_6 = 2'h2 == RdPtr ? stbuf_data_2 : _GEN_5; // @[el2_lsu_stbuf.scala 183:22] + wire _T_703 = ~dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 185:44] + wire _T_704 = io_ldst_stbuf_reqvld_r & _T_703; // @[el2_lsu_stbuf.scala 185:42] + wire _T_705 = store_coalesce_hi_r | store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 185:88] + wire _T_706 = ~_T_705; // @[el2_lsu_stbuf.scala 185:66] + wire _T_707 = _T_704 & _T_706; // @[el2_lsu_stbuf.scala 185:64] + wire _T_708 = io_ldst_stbuf_reqvld_r & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 186:30] + wire _T_709 = store_coalesce_hi_r & store_coalesce_lo_r; // @[el2_lsu_stbuf.scala 186:76] + wire _T_710 = ~_T_709; // @[el2_lsu_stbuf.scala 186:54] + wire _T_711 = _T_708 & _T_710; // @[el2_lsu_stbuf.scala 186:52] + wire WrPtrEn = _T_707 | _T_711; // @[el2_lsu_stbuf.scala 185:113] + wire _T_716 = _T_708 & _T_706; // @[el2_lsu_stbuf.scala 187:67] + wire [3:0] _T_721 = {3'h0,stbuf_vld[0]}; // @[Cat.scala 29:58] + wire [3:0] _T_723 = {3'h0,stbuf_vld[1]}; // @[Cat.scala 29:58] + wire [3:0] _T_725 = {3'h0,stbuf_vld[2]}; // @[Cat.scala 29:58] + wire [3:0] _T_727 = {3'h0,stbuf_vld[3]}; // @[Cat.scala 29:58] + wire [3:0] _T_730 = _T_721 + _T_723; // @[el2_lsu_stbuf.scala 194:101] + wire [3:0] _T_732 = _T_730 + _T_725; // @[el2_lsu_stbuf.scala 194:101] + wire [3:0] stbuf_numvld_any = _T_732 + _T_727; // @[el2_lsu_stbuf.scala 194:101] + wire _T_734 = io_lsu_pkt_m_valid & io_lsu_pkt_m_store; // @[el2_lsu_stbuf.scala 195:39] + wire _T_735 = _T_734 & io_addr_in_dccm_m; // @[el2_lsu_stbuf.scala 195:60] + wire _T_736 = ~io_lsu_pkt_m_dma; // @[el2_lsu_stbuf.scala 195:82] + wire isdccmst_m = _T_735 & _T_736; // @[el2_lsu_stbuf.scala 195:80] + wire _T_737 = io_lsu_pkt_r_valid & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 196:39] + wire _T_738 = _T_737 & io_addr_in_dccm_r; // @[el2_lsu_stbuf.scala 196:60] + wire _T_739 = ~io_lsu_pkt_r_dma; // @[el2_lsu_stbuf.scala 196:82] + wire isdccmst_r = _T_738 & _T_739; // @[el2_lsu_stbuf.scala 196:80] + wire [1:0] _T_740 = {1'h0,isdccmst_m}; // @[Cat.scala 29:58] + wire _T_741 = isdccmst_m & ldst_dual_m; // @[el2_lsu_stbuf.scala 198:62] + wire [2:0] _GEN_14 = {{1'd0}, _T_740}; // @[el2_lsu_stbuf.scala 198:47] + wire [2:0] _T_742 = _GEN_14 << _T_741; // @[el2_lsu_stbuf.scala 198:47] + wire [1:0] _T_743 = {1'h0,isdccmst_r}; // @[Cat.scala 29:58] + wire _T_744 = isdccmst_r & ldst_dual_r; // @[el2_lsu_stbuf.scala 199:62] + wire [2:0] _GEN_15 = {{1'd0}, _T_743}; // @[el2_lsu_stbuf.scala 199:47] + wire [2:0] _T_745 = _GEN_15 << _T_744; // @[el2_lsu_stbuf.scala 199:47] + wire [1:0] stbuf_specvld_m = _T_742[1:0]; // @[el2_lsu_stbuf.scala 198:19] + wire [3:0] _T_746 = {2'h0,stbuf_specvld_m}; // @[Cat.scala 29:58] + wire [3:0] _T_748 = stbuf_numvld_any + _T_746; // @[el2_lsu_stbuf.scala 200:44] + wire [1:0] stbuf_specvld_r = _T_745[1:0]; // @[el2_lsu_stbuf.scala 199:19] + wire [3:0] _T_749 = {2'h0,stbuf_specvld_r}; // @[Cat.scala 29:58] + wire [3:0] stbuf_specvld_any = _T_748 + _T_749; // @[el2_lsu_stbuf.scala 200:78] + wire _T_751 = ~ldst_dual_d; // @[el2_lsu_stbuf.scala 202:34] + wire _T_752 = _T_751 & io_dec_lsu_valid_raw_d; // @[el2_lsu_stbuf.scala 202:47] + wire _T_754 = stbuf_specvld_any >= 4'h4; // @[el2_lsu_stbuf.scala 202:99] + wire _T_755 = stbuf_specvld_any >= 4'h3; // @[el2_lsu_stbuf.scala 202:140] + wire _T_865 = stbuf_match_hi[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_0 = _T_865 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_869 = stbuf_match_hi[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_1 = _T_869 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_873 = stbuf_match_hi[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_2 = _T_873 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_877 = stbuf_match_hi[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_0_3 = _T_877 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_881 = stbuf_match_hi[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_0 = _T_881 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_885 = stbuf_match_hi[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_1 = _T_885 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_889 = stbuf_match_hi[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_2 = _T_889 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_893 = stbuf_match_hi[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_1_3 = _T_893 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_897 = stbuf_match_hi[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_0 = _T_897 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_901 = stbuf_match_hi[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_1 = _T_901 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_905 = stbuf_match_hi[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_2 = _T_905 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_909 = stbuf_match_hi[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_2_3 = _T_909 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_913 = stbuf_match_hi[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_0 = _T_913 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_917 = stbuf_match_hi[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_1 = _T_917 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_921 = stbuf_match_hi[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_2 = _T_921 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_925 = stbuf_match_hi[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 217:116] + wire stbuf_fwdbyteenvec_hi_3_3 = _T_925 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 217:137] + wire _T_929 = stbuf_match_lo[0] & stbuf_byteen_0[0]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_0 = _T_929 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_933 = stbuf_match_lo[0] & stbuf_byteen_0[1]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_1 = _T_933 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_937 = stbuf_match_lo[0] & stbuf_byteen_0[2]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_2 = _T_937 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_941 = stbuf_match_lo[0] & stbuf_byteen_0[3]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_0_3 = _T_941 & stbuf_vld[0]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_945 = stbuf_match_lo[1] & stbuf_byteen_1[0]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_0 = _T_945 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_949 = stbuf_match_lo[1] & stbuf_byteen_1[1]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_1 = _T_949 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_953 = stbuf_match_lo[1] & stbuf_byteen_1[2]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_2 = _T_953 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_957 = stbuf_match_lo[1] & stbuf_byteen_1[3]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_1_3 = _T_957 & stbuf_vld[1]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_961 = stbuf_match_lo[2] & stbuf_byteen_2[0]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_0 = _T_961 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_965 = stbuf_match_lo[2] & stbuf_byteen_2[1]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_1 = _T_965 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_969 = stbuf_match_lo[2] & stbuf_byteen_2[2]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_2 = _T_969 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_973 = stbuf_match_lo[2] & stbuf_byteen_2[3]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_2_3 = _T_973 & stbuf_vld[2]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_977 = stbuf_match_lo[3] & stbuf_byteen_3[0]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_0 = _T_977 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_981 = stbuf_match_lo[3] & stbuf_byteen_3[1]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_1 = _T_981 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_985 = stbuf_match_lo[3] & stbuf_byteen_3[2]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_2 = _T_985 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_989 = stbuf_match_lo[3] & stbuf_byteen_3[3]; // @[el2_lsu_stbuf.scala 218:116] + wire stbuf_fwdbyteenvec_lo_3_3 = _T_989 & stbuf_vld[3]; // @[el2_lsu_stbuf.scala 218:137] + wire _T_991 = stbuf_fwdbyteenvec_hi_0_0 | stbuf_fwdbyteenvec_hi_1_0; // @[el2_lsu_stbuf.scala 219:147] + wire _T_992 = _T_991 | stbuf_fwdbyteenvec_hi_2_0; // @[el2_lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_0 = _T_992 | stbuf_fwdbyteenvec_hi_3_0; // @[el2_lsu_stbuf.scala 219:147] + wire _T_993 = stbuf_fwdbyteenvec_hi_0_1 | stbuf_fwdbyteenvec_hi_1_1; // @[el2_lsu_stbuf.scala 219:147] + wire _T_994 = _T_993 | stbuf_fwdbyteenvec_hi_2_1; // @[el2_lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_1 = _T_994 | stbuf_fwdbyteenvec_hi_3_1; // @[el2_lsu_stbuf.scala 219:147] + wire _T_995 = stbuf_fwdbyteenvec_hi_0_2 | stbuf_fwdbyteenvec_hi_1_2; // @[el2_lsu_stbuf.scala 219:147] + wire _T_996 = _T_995 | stbuf_fwdbyteenvec_hi_2_2; // @[el2_lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_2 = _T_996 | stbuf_fwdbyteenvec_hi_3_2; // @[el2_lsu_stbuf.scala 219:147] + wire _T_997 = stbuf_fwdbyteenvec_hi_0_3 | stbuf_fwdbyteenvec_hi_1_3; // @[el2_lsu_stbuf.scala 219:147] + wire _T_998 = _T_997 | stbuf_fwdbyteenvec_hi_2_3; // @[el2_lsu_stbuf.scala 219:147] + wire stbuf_fwdbyteen_hi_pre_m_3 = _T_998 | stbuf_fwdbyteenvec_hi_3_3; // @[el2_lsu_stbuf.scala 219:147] + wire _T_999 = stbuf_fwdbyteenvec_lo_0_0 | stbuf_fwdbyteenvec_lo_1_0; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1000 = _T_999 | stbuf_fwdbyteenvec_lo_2_0; // @[el2_lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_0 = _T_1000 | stbuf_fwdbyteenvec_lo_3_0; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1001 = stbuf_fwdbyteenvec_lo_0_1 | stbuf_fwdbyteenvec_lo_1_1; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1002 = _T_1001 | stbuf_fwdbyteenvec_lo_2_1; // @[el2_lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_1 = _T_1002 | stbuf_fwdbyteenvec_lo_3_1; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1003 = stbuf_fwdbyteenvec_lo_0_2 | stbuf_fwdbyteenvec_lo_1_2; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1004 = _T_1003 | stbuf_fwdbyteenvec_lo_2_2; // @[el2_lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_2 = _T_1004 | stbuf_fwdbyteenvec_lo_3_2; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1005 = stbuf_fwdbyteenvec_lo_0_3 | stbuf_fwdbyteenvec_lo_1_3; // @[el2_lsu_stbuf.scala 220:147] + wire _T_1006 = _T_1005 | stbuf_fwdbyteenvec_lo_2_3; // @[el2_lsu_stbuf.scala 220:147] + wire stbuf_fwdbyteen_lo_pre_m_3 = _T_1006 | stbuf_fwdbyteenvec_lo_3_3; // @[el2_lsu_stbuf.scala 220:147] + wire [31:0] _T_1009 = stbuf_match_hi[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1010 = _T_1009 & stbuf_data_0; // @[el2_lsu_stbuf.scala 222:97] + wire [31:0] _T_1013 = stbuf_match_hi[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1014 = _T_1013 & stbuf_data_1; // @[el2_lsu_stbuf.scala 222:97] + wire [31:0] _T_1017 = stbuf_match_hi[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1018 = _T_1017 & stbuf_data_2; // @[el2_lsu_stbuf.scala 222:97] + wire [31:0] _T_1021 = stbuf_match_hi[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1022 = _T_1021 & stbuf_data_3; // @[el2_lsu_stbuf.scala 222:97] + wire [31:0] _T_1024 = _T_1022 | _T_1018; // @[el2_lsu_stbuf.scala 222:130] + wire [31:0] _T_1025 = _T_1024 | _T_1014; // @[el2_lsu_stbuf.scala 222:130] + wire [31:0] stbuf_fwddata_hi_pre_m = _T_1025 | _T_1010; // @[el2_lsu_stbuf.scala 222:130] + wire [31:0] _T_1028 = stbuf_match_lo[0] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1029 = _T_1028 & stbuf_data_0; // @[el2_lsu_stbuf.scala 223:97] + wire [31:0] _T_1032 = stbuf_match_lo[1] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1033 = _T_1032 & stbuf_data_1; // @[el2_lsu_stbuf.scala 223:97] + wire [31:0] _T_1036 = stbuf_match_lo[2] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1037 = _T_1036 & stbuf_data_2; // @[el2_lsu_stbuf.scala 223:97] + wire [31:0] _T_1040 = stbuf_match_lo[3] ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_1041 = _T_1040 & stbuf_data_3; // @[el2_lsu_stbuf.scala 223:97] + wire [31:0] _T_1043 = _T_1041 | _T_1037; // @[el2_lsu_stbuf.scala 223:130] + wire [31:0] _T_1044 = _T_1043 | _T_1033; // @[el2_lsu_stbuf.scala 223:130] + wire [31:0] stbuf_fwddata_lo_pre_m = _T_1044 | _T_1029; // @[el2_lsu_stbuf.scala 223:130] + wire _T_1049 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 230:49] + wire _T_1050 = _T_1049 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 230:74] + wire _T_1051 = _T_1050 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 230:95] + wire ld_addr_rhit_lo_lo = _T_1051 & _T_739; // @[el2_lsu_stbuf.scala 230:116] + wire _T_1055 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_stbuf.scala 231:49] + wire _T_1056 = _T_1055 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 231:74] + wire _T_1057 = _T_1056 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 231:95] + wire ld_addr_rhit_lo_hi = _T_1057 & _T_739; // @[el2_lsu_stbuf.scala 231:116] + wire _T_1061 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 232:49] + wire _T_1062 = _T_1061 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 232:74] + wire _T_1063 = _T_1062 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 232:95] + wire _T_1065 = _T_1063 & _T_739; // @[el2_lsu_stbuf.scala 232:116] + wire ld_addr_rhit_hi_lo = _T_1065 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 232:136] + wire _T_1068 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_stbuf.scala 233:49] + wire _T_1069 = _T_1068 & io_lsu_pkt_r_valid; // @[el2_lsu_stbuf.scala 233:74] + wire _T_1070 = _T_1069 & io_lsu_pkt_r_store; // @[el2_lsu_stbuf.scala 233:95] + wire _T_1072 = _T_1070 & _T_739; // @[el2_lsu_stbuf.scala 233:116] + wire ld_addr_rhit_hi_hi = _T_1072 & dual_stbuf_write_r; // @[el2_lsu_stbuf.scala 233:136] + wire _T_1074 = ld_addr_rhit_lo_lo & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1076 = ld_addr_rhit_lo_lo & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1078 = ld_addr_rhit_lo_lo & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 235:79] + wire _T_1080 = ld_addr_rhit_lo_lo & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 235:79] + wire [3:0] ld_byte_rhit_lo_lo = {_T_1080,_T_1078,_T_1076,_T_1074}; // @[Cat.scala 29:58] + wire _T_1085 = ld_addr_rhit_lo_hi & store_byteen_ext_r[0]; // @[el2_lsu_stbuf.scala 236:79] + wire _T_1087 = ld_addr_rhit_lo_hi & store_byteen_ext_r[1]; // @[el2_lsu_stbuf.scala 236:79] + wire _T_1089 = ld_addr_rhit_lo_hi & store_byteen_ext_r[2]; // @[el2_lsu_stbuf.scala 236:79] + wire _T_1091 = ld_addr_rhit_lo_hi & store_byteen_ext_r[3]; // @[el2_lsu_stbuf.scala 236:79] + wire [3:0] ld_byte_rhit_lo_hi = {_T_1091,_T_1089,_T_1087,_T_1085}; // @[Cat.scala 29:58] + wire _T_1096 = ld_addr_rhit_hi_lo & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 237:79] + wire _T_1098 = ld_addr_rhit_hi_lo & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 237:79] + wire _T_1100 = ld_addr_rhit_hi_lo & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 237:79] + wire _T_1102 = ld_addr_rhit_hi_lo & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 237:79] + wire [3:0] ld_byte_rhit_hi_lo = {_T_1102,_T_1100,_T_1098,_T_1096}; // @[Cat.scala 29:58] + wire _T_1107 = ld_addr_rhit_hi_hi & store_byteen_ext_r[4]; // @[el2_lsu_stbuf.scala 238:79] + wire _T_1109 = ld_addr_rhit_hi_hi & store_byteen_ext_r[5]; // @[el2_lsu_stbuf.scala 238:79] + wire _T_1111 = ld_addr_rhit_hi_hi & store_byteen_ext_r[6]; // @[el2_lsu_stbuf.scala 238:79] + wire _T_1113 = ld_addr_rhit_hi_hi & store_byteen_ext_r[7]; // @[el2_lsu_stbuf.scala 238:79] + wire [3:0] ld_byte_rhit_hi_hi = {_T_1113,_T_1111,_T_1109,_T_1107}; // @[Cat.scala 29:58] + wire _T_1119 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_stbuf.scala 240:79] + wire _T_1122 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_stbuf.scala 240:79] + wire _T_1125 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_stbuf.scala 240:79] + wire _T_1128 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_stbuf.scala 240:79] + wire [3:0] ld_byte_rhit_lo = {_T_1128,_T_1125,_T_1122,_T_1119}; // @[Cat.scala 29:58] + wire _T_1134 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_stbuf.scala 241:79] + wire _T_1137 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_stbuf.scala 241:79] + wire _T_1140 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_stbuf.scala 241:79] + wire _T_1143 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_stbuf.scala 241:79] + wire [3:0] ld_byte_rhit_hi = {_T_1143,_T_1140,_T_1137,_T_1134}; // @[Cat.scala 29:58] + wire [7:0] _T_1149 = ld_byte_rhit_lo_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1151 = _T_1149 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 243:53] + wire [7:0] _T_1154 = ld_byte_rhit_hi_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1156 = _T_1154 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 243:114] + wire [7:0] fwdpipe1_lo = _T_1151 | _T_1156; // @[el2_lsu_stbuf.scala 243:80] + wire [7:0] _T_1159 = ld_byte_rhit_lo_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1161 = _T_1159 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 244:53] + wire [7:0] _T_1164 = ld_byte_rhit_hi_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1166 = _T_1164 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 244:115] + wire [7:0] fwdpipe2_lo = _T_1161 | _T_1166; // @[el2_lsu_stbuf.scala 244:81] + wire [7:0] _T_1169 = ld_byte_rhit_lo_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1171 = _T_1169 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 245:53] + wire [7:0] _T_1174 = ld_byte_rhit_hi_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1176 = _T_1174 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 245:116] + wire [7:0] fwdpipe3_lo = _T_1171 | _T_1176; // @[el2_lsu_stbuf.scala 245:82] + wire [7:0] _T_1179 = ld_byte_rhit_lo_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1181 = _T_1179 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 246:53] + wire [7:0] _T_1184 = ld_byte_rhit_hi_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1186 = _T_1184 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 246:116] + wire [7:0] fwdpipe4_lo = _T_1181 | _T_1186; // @[el2_lsu_stbuf.scala 246:82] + wire [31:0] ld_fwddata_rpipe_lo = {fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [7:0] _T_1192 = ld_byte_rhit_lo_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1194 = _T_1192 & io_store_data_lo_r[7:0]; // @[el2_lsu_stbuf.scala 249:53] + wire [7:0] _T_1197 = ld_byte_rhit_hi_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1199 = _T_1197 & io_store_data_hi_r[7:0]; // @[el2_lsu_stbuf.scala 249:114] + wire [7:0] fwdpipe1_hi = _T_1194 | _T_1199; // @[el2_lsu_stbuf.scala 249:80] + wire [7:0] _T_1202 = ld_byte_rhit_lo_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1204 = _T_1202 & io_store_data_lo_r[15:8]; // @[el2_lsu_stbuf.scala 250:53] + wire [7:0] _T_1207 = ld_byte_rhit_hi_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1209 = _T_1207 & io_store_data_hi_r[15:8]; // @[el2_lsu_stbuf.scala 250:115] + wire [7:0] fwdpipe2_hi = _T_1204 | _T_1209; // @[el2_lsu_stbuf.scala 250:81] + wire [7:0] _T_1212 = ld_byte_rhit_lo_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1214 = _T_1212 & io_store_data_lo_r[23:16]; // @[el2_lsu_stbuf.scala 251:53] + wire [7:0] _T_1217 = ld_byte_rhit_hi_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1219 = _T_1217 & io_store_data_hi_r[23:16]; // @[el2_lsu_stbuf.scala 251:116] + wire [7:0] fwdpipe3_hi = _T_1214 | _T_1219; // @[el2_lsu_stbuf.scala 251:82] + wire [7:0] _T_1222 = ld_byte_rhit_lo_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1224 = _T_1222 & io_store_data_lo_r[31:24]; // @[el2_lsu_stbuf.scala 252:53] + wire [7:0] _T_1227 = ld_byte_rhit_hi_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_1229 = _T_1227 & io_store_data_hi_r[31:24]; // @[el2_lsu_stbuf.scala 252:116] + wire [7:0] fwdpipe4_hi = _T_1224 | _T_1229; // @[el2_lsu_stbuf.scala 252:82] + wire [31:0] ld_fwddata_rpipe_hi = {fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi}; // @[Cat.scala 29:58] + wire _T_1264 = ld_byte_rhit_hi[0] | stbuf_fwdbyteen_hi_pre_m_0; // @[el2_lsu_stbuf.scala 258:83] + wire _T_1266 = ld_byte_rhit_hi[1] | stbuf_fwdbyteen_hi_pre_m_1; // @[el2_lsu_stbuf.scala 258:83] + wire _T_1268 = ld_byte_rhit_hi[2] | stbuf_fwdbyteen_hi_pre_m_2; // @[el2_lsu_stbuf.scala 258:83] + wire _T_1270 = ld_byte_rhit_hi[3] | stbuf_fwdbyteen_hi_pre_m_3; // @[el2_lsu_stbuf.scala 258:83] + wire [2:0] _T_1272 = {_T_1270,_T_1268,_T_1266}; // @[Cat.scala 29:58] + wire _T_1275 = ld_byte_rhit_lo[0] | stbuf_fwdbyteen_lo_pre_m_0; // @[el2_lsu_stbuf.scala 259:83] + wire _T_1277 = ld_byte_rhit_lo[1] | stbuf_fwdbyteen_lo_pre_m_1; // @[el2_lsu_stbuf.scala 259:83] + wire _T_1279 = ld_byte_rhit_lo[2] | stbuf_fwdbyteen_lo_pre_m_2; // @[el2_lsu_stbuf.scala 259:83] + wire _T_1281 = ld_byte_rhit_lo[3] | stbuf_fwdbyteen_lo_pre_m_3; // @[el2_lsu_stbuf.scala 259:83] + wire [2:0] _T_1283 = {_T_1281,_T_1279,_T_1277}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_lo = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : stbuf_fwddata_lo_pre_m[7:0]; // @[el2_lsu_stbuf.scala 262:30] + wire [7:0] stbuf_fwdpipe2_lo = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : stbuf_fwddata_lo_pre_m[15:8]; // @[el2_lsu_stbuf.scala 263:30] + wire [7:0] stbuf_fwdpipe3_lo = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : stbuf_fwddata_lo_pre_m[23:16]; // @[el2_lsu_stbuf.scala 264:30] + wire [7:0] stbuf_fwdpipe4_lo = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : stbuf_fwddata_lo_pre_m[31:24]; // @[el2_lsu_stbuf.scala 265:30] + wire [15:0] _T_1297 = {stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo}; // @[Cat.scala 29:58] + wire [15:0] _T_1298 = {stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo}; // @[Cat.scala 29:58] + wire [7:0] stbuf_fwdpipe1_hi = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : stbuf_fwddata_hi_pre_m[7:0]; // @[el2_lsu_stbuf.scala 268:30] + wire [7:0] stbuf_fwdpipe2_hi = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : stbuf_fwddata_hi_pre_m[15:8]; // @[el2_lsu_stbuf.scala 269:30] + wire [7:0] stbuf_fwdpipe3_hi = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : stbuf_fwddata_hi_pre_m[23:16]; // @[el2_lsu_stbuf.scala 270:30] + wire [7:0] stbuf_fwdpipe4_hi = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : stbuf_fwddata_hi_pre_m[31:24]; // @[el2_lsu_stbuf.scala 271:30] + wire [15:0] _T_1312 = {stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi}; // @[Cat.scala 29:58] + wire [15:0] _T_1313 = {stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi}; // @[Cat.scala 29:58] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + assign io_stbuf_reqvld_any = _T_699 & _T_701; // @[el2_lsu_stbuf.scala 52:47 el2_lsu_stbuf.scala 181:24] + assign io_stbuf_reqvld_flushed_any = _T_689[0] & _T_691[0]; // @[el2_lsu_stbuf.scala 53:35 el2_lsu_stbuf.scala 180:31] + assign io_stbuf_addr_any = 2'h3 == RdPtr ? stbuf_addr_3 : _GEN_2; // @[el2_lsu_stbuf.scala 54:35 el2_lsu_stbuf.scala 182:22] + assign io_stbuf_data_any = 2'h3 == RdPtr ? stbuf_data_3 : _GEN_6; // @[el2_lsu_stbuf.scala 55:35 el2_lsu_stbuf.scala 183:22] + assign io_lsu_stbuf_full_any = _T_752 ? _T_754 : _T_755; // @[el2_lsu_stbuf.scala 56:43 el2_lsu_stbuf.scala 202:26] + assign io_lsu_stbuf_empty_any = stbuf_numvld_any == 4'h0; // @[el2_lsu_stbuf.scala 57:43 el2_lsu_stbuf.scala 203:26] + assign io_ldst_stbuf_reqvld_r = io_lsu_commit_r & io_store_stbuf_reqvld_r; // @[el2_lsu_stbuf.scala 58:43 el2_lsu_stbuf.scala 129:26] + assign io_stbuf_fwddata_hi_m = {_T_1313,_T_1312}; // @[el2_lsu_stbuf.scala 59:43 el2_lsu_stbuf.scala 272:25] + assign io_stbuf_fwddata_lo_m = {_T_1298,_T_1297}; // @[el2_lsu_stbuf.scala 60:43 el2_lsu_stbuf.scala 266:25] + assign io_stbuf_fwdbyteen_hi_m = {_T_1272,_T_1264}; // @[el2_lsu_stbuf.scala 61:37 el2_lsu_stbuf.scala 258:27] + assign io_stbuf_fwdbyteen_lo_m = {_T_1283,_T_1275}; // @[el2_lsu_stbuf.scala 62:37 el2_lsu_stbuf.scala 259:27] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = stbuf_wr_en[0]; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = stbuf_wr_en[1]; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = stbuf_wr_en[2]; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = stbuf_wr_en[3]; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2409,27 +3282,27 @@ initial begin _RAND_3 = {1{`RANDOM}}; stbuf_addr_0 = _RAND_3[15:0]; _RAND_4 = {1{`RANDOM}}; - stbuf_vld_0 = _RAND_4[0:0]; + _T_588 = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - stbuf_dma_kill_0 = _RAND_5[0:0]; + _T_580 = _RAND_5[0:0]; _RAND_6 = {1{`RANDOM}}; - stbuf_addr_1 = _RAND_6[15:0]; + _T_572 = _RAND_6[0:0]; _RAND_7 = {1{`RANDOM}}; - stbuf_vld_1 = _RAND_7[0:0]; + _T_564 = _RAND_7[0:0]; _RAND_8 = {1{`RANDOM}}; - stbuf_dma_kill_1 = _RAND_8[0:0]; + _T_623 = _RAND_8[0:0]; _RAND_9 = {1{`RANDOM}}; - stbuf_addr_2 = _RAND_9[15:0]; + _T_615 = _RAND_9[0:0]; _RAND_10 = {1{`RANDOM}}; - stbuf_vld_2 = _RAND_10[0:0]; + _T_607 = _RAND_10[0:0]; _RAND_11 = {1{`RANDOM}}; - stbuf_dma_kill_2 = _RAND_11[0:0]; + _T_599 = _RAND_11[0:0]; _RAND_12 = {1{`RANDOM}}; - stbuf_addr_3 = _RAND_12[15:0]; + stbuf_addr_1 = _RAND_12[15:0]; _RAND_13 = {1{`RANDOM}}; - stbuf_vld_3 = _RAND_13[0:0]; + stbuf_addr_2 = _RAND_13[15:0]; _RAND_14 = {1{`RANDOM}}; - stbuf_dma_kill_3 = _RAND_14[0:0]; + stbuf_addr_3 = _RAND_14[15:0]; _RAND_15 = {1{`RANDOM}}; stbuf_byteen_0 = _RAND_15[3:0]; _RAND_16 = {1{`RANDOM}}; @@ -2462,38 +3335,38 @@ initial begin stbuf_addr_0 = 16'h0; end if (reset) begin - stbuf_vld_0 = 1'h0; + _T_588 = 1'h0; end if (reset) begin - stbuf_dma_kill_0 = 1'h0; + _T_580 = 1'h0; + end + if (reset) begin + _T_572 = 1'h0; + end + if (reset) begin + _T_564 = 1'h0; + end + if (reset) begin + _T_623 = 1'h0; + end + if (reset) begin + _T_615 = 1'h0; + end + if (reset) begin + _T_607 = 1'h0; + end + if (reset) begin + _T_599 = 1'h0; end if (reset) begin stbuf_addr_1 = 16'h0; end - if (reset) begin - stbuf_vld_1 = 1'h0; - end - if (reset) begin - stbuf_dma_kill_1 = 1'h0; - end if (reset) begin stbuf_addr_2 = 16'h0; end - if (reset) begin - stbuf_vld_2 = 1'h0; - end - if (reset) begin - stbuf_dma_kill_2 = 1'h0; - end if (reset) begin stbuf_addr_3 = 16'h0; end - if (reset) begin - stbuf_vld_3 = 1'h0; - end - if (reset) begin - stbuf_dma_kill_3 = 1'h0; - end if (reset) begin stbuf_byteen_0 = 4'h0; end @@ -2537,159 +3410,167 @@ end // initial always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin RdPtr <= 2'h0; - end else if (_T_214) begin - RdPtr <= NxtRdPtr; + end else if (_T_212) begin + RdPtr <= RdPtrPlus1; end end always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin WrPtr <= 2'h0; end else if (WrPtrEn) begin - if (_T_660) begin + if (_T_716) begin WrPtr <= WrPtrPlus2; end else begin WrPtr <= WrPtrPlus1; end end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin stbuf_addr_0 <= 16'h0; - end else if (stbuf_wr_en[0]) begin - stbuf_addr_0 <= stbuf_addrin_0; + end else if (sel_lo[0]) begin + stbuf_addr_0 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_0 <= io_end_addr_r[15:0]; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin - stbuf_vld_0 <= 1'h0; - end else if (stbuf_wr_en[0]) begin - stbuf_vld_0 <= _T_35; + _T_588 <= 1'h0; + end else begin + _T_588 <= _T_584 & _T_67; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin if (reset) begin - stbuf_dma_kill_0 <= 1'h0; - end else if (stbuf_dma_kill_en[0]) begin - stbuf_dma_kill_0 <= _T_35; + _T_580 <= 1'h0; + end else begin + _T_580 <= _T_576 & _T_56; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_572 <= 1'h0; + end else begin + _T_572 <= _T_568 & _T_45; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_564 <= 1'h0; + end else begin + _T_564 <= _T_560 & _T_34; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_623 <= 1'h0; + end else begin + _T_623 <= _T_619 & _T_67; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_615 <= 1'h0; + end else begin + _T_615 <= _T_611 & _T_56; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_607 <= 1'h0; + end else begin + _T_607 <= _T_603 & _T_45; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + _T_599 <= 1'h0; + end else begin + _T_599 <= _T_595 & _T_34; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin stbuf_addr_1 <= 16'h0; - end else if (stbuf_wr_en[1]) begin - stbuf_addr_1 <= stbuf_addrin_1; + end else if (sel_lo[1]) begin + stbuf_addr_1 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_1 <= io_end_addr_r[15:0]; end end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_vld_1 <= 1'h0; - end else if (stbuf_wr_en[1]) begin - stbuf_vld_1 <= _T_44; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_dma_kill_1 <= 1'h0; - end else if (stbuf_dma_kill_en[1]) begin - stbuf_dma_kill_1 <= _T_44; - end - end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin if (reset) begin stbuf_addr_2 <= 16'h0; - end else if (stbuf_wr_en[2]) begin - stbuf_addr_2 <= stbuf_addrin_2; + end else if (sel_lo[2]) begin + stbuf_addr_2 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_2 <= io_end_addr_r[15:0]; end end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_vld_2 <= 1'h0; - end else if (stbuf_wr_en[2]) begin - stbuf_vld_2 <= _T_53; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_dma_kill_2 <= 1'h0; - end else if (stbuf_dma_kill_en[2]) begin - stbuf_dma_kill_2 <= _T_53; - end - end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin if (reset) begin stbuf_addr_3 <= 16'h0; - end else if (stbuf_wr_en[3]) begin - stbuf_addr_3 <= stbuf_addrin_3; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_vld_3 <= 1'h0; - end else if (stbuf_wr_en[3]) begin - stbuf_vld_3 <= _T_62; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - stbuf_dma_kill_3 <= 1'h0; - end else if (stbuf_dma_kill_en[3]) begin - stbuf_dma_kill_3 <= _T_62; + end else if (sel_lo[3]) begin + stbuf_addr_3 <= io_lsu_addr_r[15:0]; + end else begin + stbuf_addr_3 <= io_end_addr_r[15:0]; end end always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin stbuf_byteen_0 <= 4'h0; - end else if (stbuf_wr_en[0]) begin - stbuf_byteen_0 <= _T_568; + end else begin + stbuf_byteen_0 <= _T_629 & _T_633; end end always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin stbuf_byteen_1 <= 4'h0; - end else if (stbuf_wr_en[1]) begin - stbuf_byteen_1 <= _T_590; + end else begin + stbuf_byteen_1 <= _T_638 & _T_642; end end always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin stbuf_byteen_2 <= 4'h0; - end else if (stbuf_wr_en[2]) begin - stbuf_byteen_2 <= _T_612; + end else begin + stbuf_byteen_2 <= _T_647 & _T_651; end end always @(posedge io_lsu_stbuf_c1_clk or posedge reset) begin if (reset) begin stbuf_byteen_3 <= 4'h0; - end else if (stbuf_wr_en[3]) begin - stbuf_byteen_3 <= _T_634; + end else begin + stbuf_byteen_3 <= _T_656 & _T_660; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin if (reset) begin stbuf_data_0 <= 32'h0; - end else if (stbuf_wr_en[0]) begin - stbuf_data_0 <= stbuf_datain_0; + end else begin + stbuf_data_0 <= {_T_546,_T_545}; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin stbuf_data_1 <= 32'h0; - end else if (stbuf_wr_en[1]) begin - stbuf_data_1 <= stbuf_datain_1; + end else begin + stbuf_data_1 <= {_T_549,_T_548}; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin if (reset) begin stbuf_data_2 <= 32'h0; - end else if (stbuf_wr_en[2]) begin - stbuf_data_2 <= stbuf_datain_2; + end else begin + stbuf_data_2 <= {_T_552,_T_551}; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin if (reset) begin stbuf_data_3 <= 32'h0; - end else if (stbuf_wr_en[3]) begin - stbuf_data_3 <= stbuf_datain_3; + end else begin + stbuf_data_3 <= {_T_555,_T_554}; end end always @(posedge io_lsu_c1_m_clk or posedge reset) begin @@ -2708,6 +3589,7 @@ module el2_lsu_ecc( input io_lsu_pkt_m_store, input io_lsu_pkt_m_dma, input io_lsu_pkt_m_valid, + input [31:0] io_stbuf_data_any, input io_dec_tlu_core_ecc_disable, input [15:0] io_lsu_addr_m, input [15:0] io_end_addr_m, @@ -2716,14 +3598,24 @@ module el2_lsu_ecc( input [6:0] io_dccm_data_ecc_hi_m, input [6:0] io_dccm_data_ecc_lo_m, input io_ld_single_ecc_error_r, + input io_ld_single_ecc_error_r_ff, input io_lsu_dccm_rden_m, input io_addr_in_dccm_m, + input io_dma_dccm_wen, + input [31:0] io_dma_dccm_wdata_lo, + input [31:0] io_dma_dccm_wdata_hi, + input io_scan_mode, output [31:0] io_sec_data_hi_r, output [31:0] io_sec_data_lo_r, output [31:0] io_sec_data_hi_m, output [31:0] io_sec_data_lo_m, output [31:0] io_sec_data_hi_r_ff, output [31:0] io_sec_data_lo_r_ff, + output [6:0] io_dma_dccm_wdata_ecc_hi, + output [6:0] io_dma_dccm_wdata_ecc_lo, + output [6:0] io_stbuf_ecc_any, + output [6:0] io_sec_data_ecc_hi_r_ff, + output [6:0] io_sec_data_ecc_lo_r_ff, output io_single_ecc_error_hi_r, output io_single_ecc_error_lo_r, output io_lsu_single_ecc_error_r, @@ -2741,196 +3633,411 @@ module el2_lsu_ecc( reg [31:0] _RAND_6; reg [31:0] _RAND_7; `endif // RANDOMIZE_REG_INIT - wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 279:30] - wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 279:44] - wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 279:35] - wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 279:76] - wire _T_107 = ^_T_106; // @[el2_lib.scala 279:83] - wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 279:71] - wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 279:103] - wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 279:103] - wire _T_124 = ^_T_123; // @[el2_lib.scala 279:110] - wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 279:98] - wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 279:130] - wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 279:130] - wire _T_141 = ^_T_140; // @[el2_lib.scala 279:137] - wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 279:125] - wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 279:157] - wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 279:157] - wire _T_161 = ^_T_160; // @[el2_lib.scala 279:164] - wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 279:152] - wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 279:184] - wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 279:184] - wire _T_181 = ^_T_180; // @[el2_lib.scala 279:191] - wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 279:179] - wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 279:211] - wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 279:211] - wire _T_201 = ^_T_200; // @[el2_lib.scala 279:218] - wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 279:206] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire _T_96 = ^io_dccm_rdata_hi_m; // @[el2_lib.scala 333:30] + wire _T_97 = ^io_dccm_data_ecc_hi_m; // @[el2_lib.scala 333:44] + wire _T_98 = _T_96 ^ _T_97; // @[el2_lib.scala 333:35] + wire [5:0] _T_106 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[26]}; // @[el2_lib.scala 333:76] + wire _T_107 = ^_T_106; // @[el2_lib.scala 333:83] + wire _T_108 = io_dccm_data_ecc_hi_m[5] ^ _T_107; // @[el2_lib.scala 333:71] + wire [6:0] _T_115 = {io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[11]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_123 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_115}; // @[el2_lib.scala 333:103] + wire _T_124 = ^_T_123; // @[el2_lib.scala 333:110] + wire _T_125 = io_dccm_data_ecc_hi_m[4] ^ _T_124; // @[el2_lib.scala 333:98] + wire [6:0] _T_132 = {io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[4]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_140 = {io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[18],_T_132}; // @[el2_lib.scala 333:130] + wire _T_141 = ^_T_140; // @[el2_lib.scala 333:137] + wire _T_142 = io_dccm_data_ecc_hi_m[3] ^ _T_141; // @[el2_lib.scala 333:125] + wire [8:0] _T_151 = {io_dccm_rdata_hi_m[15],io_dccm_rdata_hi_m[14],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[7],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[1]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_160 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[29],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[22],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_151}; // @[el2_lib.scala 333:157] + wire _T_161 = ^_T_160; // @[el2_lib.scala 333:164] + wire _T_162 = io_dccm_data_ecc_hi_m[2] ^ _T_161; // @[el2_lib.scala 333:152] + wire [8:0] _T_171 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[12],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[9],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[5],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[2],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_180 = {io_dccm_rdata_hi_m[31],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[27],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[24],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[20],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[16],_T_171}; // @[el2_lib.scala 333:184] + wire _T_181 = ^_T_180; // @[el2_lib.scala 333:191] + wire _T_182 = io_dccm_data_ecc_hi_m[1] ^ _T_181; // @[el2_lib.scala 333:179] + wire [8:0] _T_191 = {io_dccm_rdata_hi_m[13],io_dccm_rdata_hi_m[11],io_dccm_rdata_hi_m[10],io_dccm_rdata_hi_m[8],io_dccm_rdata_hi_m[6],io_dccm_rdata_hi_m[4],io_dccm_rdata_hi_m[3],io_dccm_rdata_hi_m[1],io_dccm_rdata_hi_m[0]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_200 = {io_dccm_rdata_hi_m[30],io_dccm_rdata_hi_m[28],io_dccm_rdata_hi_m[26],io_dccm_rdata_hi_m[25],io_dccm_rdata_hi_m[23],io_dccm_rdata_hi_m[21],io_dccm_rdata_hi_m[19],io_dccm_rdata_hi_m[17],io_dccm_rdata_hi_m[15],_T_191}; // @[el2_lib.scala 333:211] + wire _T_201 = ^_T_200; // @[el2_lib.scala 333:218] + wire _T_202 = io_dccm_data_ecc_hi_m[0] ^ _T_201; // @[el2_lib.scala 333:206] wire [6:0] _T_208 = {_T_98,_T_108,_T_125,_T_142,_T_162,_T_182,_T_202}; // @[Cat.scala 29:58] - wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 281:44] - wire _T_1169 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 105:70] - wire _T_1176 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 123:60] - wire _T_1177 = io_lsu_pkt_m_valid & _T_1176; // @[el2_lsu_ecc.scala 123:39] - wire _T_1178 = _T_1177 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 123:82] - wire is_ldst_m = _T_1178 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 123:102] - wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 122:39] - wire _T_1182 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 125:48] - wire _T_1183 = is_ldst_m & _T_1182; // @[el2_lsu_ecc.scala 125:33] - wire is_ldst_hi_m = _T_1183 & _T_1169; // @[el2_lsu_ecc.scala 125:68] - wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 281:32] - wire single_ecc_error_hi_any = _T_210 & _T_98; // @[el2_lib.scala 281:52] - wire _T_225 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 286:41] - wire _T_227 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 286:41] - wire _T_229 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 286:41] - wire _T_231 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 286:41] - wire _T_233 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 286:41] - wire _T_235 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 286:41] - wire _T_237 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 286:41] - wire _T_239 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 286:41] - wire _T_241 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 286:41] - wire _T_243 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 286:41] - wire _T_245 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 286:41] - wire _T_247 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 286:41] - wire _T_249 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 286:41] - wire _T_251 = _T_208[5:0] == 6'he; // @[el2_lib.scala 286:41] - wire _T_253 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 286:41] - wire _T_255 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 286:41] - wire _T_257 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 286:41] - wire _T_259 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 286:41] - wire _T_261 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 286:41] - wire _T_263 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 286:41] - wire _T_265 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 286:41] - wire _T_267 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 286:41] - wire _T_269 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 286:41] - wire _T_271 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 286:41] - wire _T_273 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 286:41] - wire _T_275 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 286:41] - wire _T_277 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 286:41] - wire _T_279 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 286:41] - wire _T_281 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 286:41] - wire _T_283 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 286:41] - wire _T_285 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 286:41] - wire _T_287 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 286:41] - wire _T_289 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 286:41] - wire _T_291 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 286:41] - wire _T_293 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 286:41] - wire _T_295 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 286:41] - wire _T_297 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 286:41] - wire _T_299 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 286:41] - wire _T_301 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 286:41] - wire [7:0] _T_316 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_322 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_316}; // @[Cat.scala 29:58] - wire [9:0] _T_340 = {_T_261,_T_259,_T_257,_T_255,_T_253,_T_251,_T_249,_T_247,_T_245,_T_243}; // @[el2_lib.scala 289:69] - wire [18:0] _T_341 = {_T_340,_T_241,_T_239,_T_237,_T_235,_T_233,_T_231,_T_229,_T_227,_T_225}; // @[el2_lib.scala 289:69] - wire [9:0] _T_350 = {_T_281,_T_279,_T_277,_T_275,_T_273,_T_271,_T_269,_T_267,_T_265,_T_263}; // @[el2_lib.scala 289:69] - wire [9:0] _T_359 = {_T_301,_T_299,_T_297,_T_295,_T_293,_T_291,_T_289,_T_287,_T_285,_T_283}; // @[el2_lib.scala 289:69] - wire [38:0] _T_361 = {_T_359,_T_350,_T_341}; // @[el2_lib.scala 289:69] - wire [38:0] _T_362 = _T_361 ^ _T_322; // @[el2_lib.scala 289:76] - wire [38:0] _T_363 = single_ecc_error_hi_any ? _T_362 : _T_322; // @[el2_lib.scala 289:31] - wire [3:0] _T_369 = {_T_363[6:4],_T_363[2]}; // @[Cat.scala 29:58] - wire [27:0] _T_371 = {_T_363[37:32],_T_363[30:16],_T_363[14:8]}; // @[Cat.scala 29:58] - wire _T_481 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 279:30] - wire _T_482 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 279:44] - wire _T_483 = _T_481 ^ _T_482; // @[el2_lib.scala 279:35] - wire [5:0] _T_491 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 279:76] - wire _T_492 = ^_T_491; // @[el2_lib.scala 279:83] - wire _T_493 = io_dccm_data_ecc_lo_m[5] ^ _T_492; // @[el2_lib.scala 279:71] - wire [6:0] _T_500 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 279:103] - wire [14:0] _T_508 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_500}; // @[el2_lib.scala 279:103] - wire _T_509 = ^_T_508; // @[el2_lib.scala 279:110] - wire _T_510 = io_dccm_data_ecc_lo_m[4] ^ _T_509; // @[el2_lib.scala 279:98] - wire [6:0] _T_517 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 279:130] - wire [14:0] _T_525 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_517}; // @[el2_lib.scala 279:130] - wire _T_526 = ^_T_525; // @[el2_lib.scala 279:137] - wire _T_527 = io_dccm_data_ecc_lo_m[3] ^ _T_526; // @[el2_lib.scala 279:125] - wire [8:0] _T_536 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 279:157] - wire [17:0] _T_545 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_536}; // @[el2_lib.scala 279:157] - wire _T_546 = ^_T_545; // @[el2_lib.scala 279:164] - wire _T_547 = io_dccm_data_ecc_lo_m[2] ^ _T_546; // @[el2_lib.scala 279:152] - wire [8:0] _T_556 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 279:184] - wire [17:0] _T_565 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_556}; // @[el2_lib.scala 279:184] - wire _T_566 = ^_T_565; // @[el2_lib.scala 279:191] - wire _T_567 = io_dccm_data_ecc_lo_m[1] ^ _T_566; // @[el2_lib.scala 279:179] - wire [8:0] _T_576 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 279:211] - wire [17:0] _T_585 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_576}; // @[el2_lib.scala 279:211] - wire _T_586 = ^_T_585; // @[el2_lib.scala 279:218] - wire _T_587 = io_dccm_data_ecc_lo_m[0] ^ _T_586; // @[el2_lib.scala 279:206] - wire [6:0] _T_593 = {_T_483,_T_493,_T_510,_T_527,_T_547,_T_567,_T_587}; // @[Cat.scala 29:58] - wire _T_594 = _T_593 != 7'h0; // @[el2_lib.scala 281:44] - wire is_ldst_lo_m = is_ldst_m & _T_1169; // @[el2_lsu_ecc.scala 124:33] - wire _T_595 = is_ldst_lo_m & _T_594; // @[el2_lib.scala 281:32] - wire single_ecc_error_lo_any = _T_595 & _T_483; // @[el2_lib.scala 281:52] - wire _T_610 = _T_593[5:0] == 6'h1; // @[el2_lib.scala 286:41] - wire _T_612 = _T_593[5:0] == 6'h2; // @[el2_lib.scala 286:41] - wire _T_614 = _T_593[5:0] == 6'h3; // @[el2_lib.scala 286:41] - wire _T_616 = _T_593[5:0] == 6'h4; // @[el2_lib.scala 286:41] - wire _T_618 = _T_593[5:0] == 6'h5; // @[el2_lib.scala 286:41] - wire _T_620 = _T_593[5:0] == 6'h6; // @[el2_lib.scala 286:41] - wire _T_622 = _T_593[5:0] == 6'h7; // @[el2_lib.scala 286:41] - wire _T_624 = _T_593[5:0] == 6'h8; // @[el2_lib.scala 286:41] - wire _T_626 = _T_593[5:0] == 6'h9; // @[el2_lib.scala 286:41] - wire _T_628 = _T_593[5:0] == 6'ha; // @[el2_lib.scala 286:41] - wire _T_630 = _T_593[5:0] == 6'hb; // @[el2_lib.scala 286:41] - wire _T_632 = _T_593[5:0] == 6'hc; // @[el2_lib.scala 286:41] - wire _T_634 = _T_593[5:0] == 6'hd; // @[el2_lib.scala 286:41] - wire _T_636 = _T_593[5:0] == 6'he; // @[el2_lib.scala 286:41] - wire _T_638 = _T_593[5:0] == 6'hf; // @[el2_lib.scala 286:41] - wire _T_640 = _T_593[5:0] == 6'h10; // @[el2_lib.scala 286:41] - wire _T_642 = _T_593[5:0] == 6'h11; // @[el2_lib.scala 286:41] - wire _T_644 = _T_593[5:0] == 6'h12; // @[el2_lib.scala 286:41] - wire _T_646 = _T_593[5:0] == 6'h13; // @[el2_lib.scala 286:41] - wire _T_648 = _T_593[5:0] == 6'h14; // @[el2_lib.scala 286:41] - wire _T_650 = _T_593[5:0] == 6'h15; // @[el2_lib.scala 286:41] - wire _T_652 = _T_593[5:0] == 6'h16; // @[el2_lib.scala 286:41] - wire _T_654 = _T_593[5:0] == 6'h17; // @[el2_lib.scala 286:41] - wire _T_656 = _T_593[5:0] == 6'h18; // @[el2_lib.scala 286:41] - wire _T_658 = _T_593[5:0] == 6'h19; // @[el2_lib.scala 286:41] - wire _T_660 = _T_593[5:0] == 6'h1a; // @[el2_lib.scala 286:41] - wire _T_662 = _T_593[5:0] == 6'h1b; // @[el2_lib.scala 286:41] - wire _T_664 = _T_593[5:0] == 6'h1c; // @[el2_lib.scala 286:41] - wire _T_666 = _T_593[5:0] == 6'h1d; // @[el2_lib.scala 286:41] - wire _T_668 = _T_593[5:0] == 6'h1e; // @[el2_lib.scala 286:41] - wire _T_670 = _T_593[5:0] == 6'h1f; // @[el2_lib.scala 286:41] - wire _T_672 = _T_593[5:0] == 6'h20; // @[el2_lib.scala 286:41] - wire _T_674 = _T_593[5:0] == 6'h21; // @[el2_lib.scala 286:41] - wire _T_676 = _T_593[5:0] == 6'h22; // @[el2_lib.scala 286:41] - wire _T_678 = _T_593[5:0] == 6'h23; // @[el2_lib.scala 286:41] - wire _T_680 = _T_593[5:0] == 6'h24; // @[el2_lib.scala 286:41] - wire _T_682 = _T_593[5:0] == 6'h25; // @[el2_lib.scala 286:41] - wire _T_684 = _T_593[5:0] == 6'h26; // @[el2_lib.scala 286:41] - wire _T_686 = _T_593[5:0] == 6'h27; // @[el2_lib.scala 286:41] - wire [7:0] _T_701 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] - wire [38:0] _T_707 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_701}; // @[Cat.scala 29:58] - wire [9:0] _T_725 = {_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634,_T_632,_T_630,_T_628}; // @[el2_lib.scala 289:69] - wire [18:0] _T_726 = {_T_725,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614,_T_612,_T_610}; // @[el2_lib.scala 289:69] - wire [9:0] _T_735 = {_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654,_T_652,_T_650,_T_648}; // @[el2_lib.scala 289:69] - wire [9:0] _T_744 = {_T_686,_T_684,_T_682,_T_680,_T_678,_T_676,_T_674,_T_672,_T_670,_T_668}; // @[el2_lib.scala 289:69] - wire [38:0] _T_746 = {_T_744,_T_735,_T_726}; // @[el2_lib.scala 289:69] - wire [38:0] _T_747 = _T_746 ^ _T_707; // @[el2_lib.scala 289:76] - wire [38:0] _T_748 = single_ecc_error_lo_any ? _T_747 : _T_707; // @[el2_lib.scala 289:31] - wire [3:0] _T_754 = {_T_748[6:4],_T_748[2]}; // @[Cat.scala 29:58] - wire [27:0] _T_756 = {_T_748[37:32],_T_748[30:16],_T_748[14:8]}; // @[Cat.scala 29:58] - reg _T_1188; // @[el2_lsu_ecc.scala 139:72] - reg _T_1189; // @[el2_lsu_ecc.scala 140:72] - reg _T_1190; // @[el2_lsu_ecc.scala 141:72] - reg _T_1191; // @[el2_lsu_ecc.scala 142:72] - reg [31:0] _T_1192; // @[el2_lsu_ecc.scala 143:72] - reg [31:0] _T_1193; // @[el2_lsu_ecc.scala 144:72] - reg [31:0] _T_1202; // @[Reg.scala 27:20] - reg [31:0] _T_1203; // @[Reg.scala 27:20] - assign io_sec_data_hi_r = _T_1192; // @[el2_lsu_ecc.scala 112:24 el2_lsu_ecc.scala 143:62] - assign io_sec_data_lo_r = _T_1193; // @[el2_lsu_ecc.scala 115:27 el2_lsu_ecc.scala 144:62] - assign io_sec_data_hi_m = {_T_371,_T_369}; // @[el2_lsu_ecc.scala 88:32 el2_lsu_ecc.scala 132:27] - assign io_sec_data_lo_m = {_T_756,_T_754}; // @[el2_lsu_ecc.scala 89:32 el2_lsu_ecc.scala 134:27] - assign io_sec_data_hi_r_ff = _T_1202; // @[el2_lsu_ecc.scala 155:23] - assign io_sec_data_lo_r_ff = _T_1203; // @[el2_lsu_ecc.scala 156:23] - assign io_single_ecc_error_hi_r = _T_1191; // @[el2_lsu_ecc.scala 113:33 el2_lsu_ecc.scala 142:62] - assign io_single_ecc_error_lo_r = _T_1190; // @[el2_lsu_ecc.scala 116:33 el2_lsu_ecc.scala 141:62] - assign io_lsu_single_ecc_error_r = _T_1188; // @[el2_lsu_ecc.scala 118:33 el2_lsu_ecc.scala 139:62] - assign io_lsu_double_ecc_error_r = _T_1189; // @[el2_lsu_ecc.scala 119:33 el2_lsu_ecc.scala 140:62] - assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 90:30 el2_lsu_ecc.scala 136:33] - assign io_lsu_double_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 91:30 el2_lsu_ecc.scala 137:33] + wire _T_209 = _T_208 != 7'h0; // @[el2_lib.scala 334:44] + wire _T_1131 = ~io_dec_tlu_core_ecc_disable; // @[el2_lsu_ecc.scala 107:68] + wire _T_1138 = io_lsu_pkt_m_load | io_lsu_pkt_m_store; // @[el2_lsu_ecc.scala 125:60] + wire _T_1139 = io_lsu_pkt_m_valid & _T_1138; // @[el2_lsu_ecc.scala 125:39] + wire _T_1140 = _T_1139 & io_addr_in_dccm_m; // @[el2_lsu_ecc.scala 125:82] + wire is_ldst_m = _T_1140 & io_lsu_dccm_rden_m; // @[el2_lsu_ecc.scala 125:102] + wire ldst_dual_m = io_lsu_addr_m[2] != io_end_addr_m[2]; // @[el2_lsu_ecc.scala 124:39] + wire _T_1144 = ldst_dual_m | io_lsu_pkt_m_dma; // @[el2_lsu_ecc.scala 127:48] + wire _T_1145 = is_ldst_m & _T_1144; // @[el2_lsu_ecc.scala 127:33] + wire is_ldst_hi_m = _T_1145 & _T_1131; // @[el2_lsu_ecc.scala 127:68] + wire _T_210 = is_ldst_hi_m & _T_209; // @[el2_lib.scala 334:32] + wire single_ecc_error_hi_any = _T_210 & _T_208[6]; // @[el2_lib.scala 334:53] + wire _T_215 = ~_T_208[6]; // @[el2_lib.scala 335:55] + wire double_ecc_error_hi_any = _T_210 & _T_215; // @[el2_lib.scala 335:53] + wire _T_218 = _T_208[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire _T_220 = _T_208[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_222 = _T_208[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_224 = _T_208[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_226 = _T_208[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_228 = _T_208[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_230 = _T_208[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_232 = _T_208[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_234 = _T_208[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_236 = _T_208[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire _T_238 = _T_208[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_240 = _T_208[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_242 = _T_208[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_244 = _T_208[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_246 = _T_208[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_248 = _T_208[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_250 = _T_208[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_252 = _T_208[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_254 = _T_208[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_256 = _T_208[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire _T_258 = _T_208[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_260 = _T_208[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_262 = _T_208[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_264 = _T_208[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_266 = _T_208[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_268 = _T_208[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_270 = _T_208[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_272 = _T_208[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_274 = _T_208[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_276 = _T_208[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire _T_278 = _T_208[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_280 = _T_208[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_282 = _T_208[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_284 = _T_208[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_286 = _T_208[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_288 = _T_208[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_290 = _T_208[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_292 = _T_208[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_294 = _T_208[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire [7:0] _T_309 = {io_dccm_data_ecc_hi_m[3],io_dccm_rdata_hi_m[3:1],io_dccm_data_ecc_hi_m[2],io_dccm_rdata_hi_m[0],io_dccm_data_ecc_hi_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_315 = {io_dccm_data_ecc_hi_m[6],io_dccm_rdata_hi_m[31:26],io_dccm_data_ecc_hi_m[5],io_dccm_rdata_hi_m[25:11],io_dccm_data_ecc_hi_m[4],io_dccm_rdata_hi_m[10:4],_T_309}; // @[Cat.scala 29:58] + wire [9:0] _T_333 = {_T_254,_T_252,_T_250,_T_248,_T_246,_T_244,_T_242,_T_240,_T_238,_T_236}; // @[el2_lib.scala 342:69] + wire [18:0] _T_334 = {_T_333,_T_234,_T_232,_T_230,_T_228,_T_226,_T_224,_T_222,_T_220,_T_218}; // @[el2_lib.scala 342:69] + wire [9:0] _T_343 = {_T_274,_T_272,_T_270,_T_268,_T_266,_T_264,_T_262,_T_260,_T_258,_T_256}; // @[el2_lib.scala 342:69] + wire [9:0] _T_352 = {_T_294,_T_292,_T_290,_T_288,_T_286,_T_284,_T_282,_T_280,_T_278,_T_276}; // @[el2_lib.scala 342:69] + wire [38:0] _T_354 = {_T_352,_T_343,_T_334}; // @[el2_lib.scala 342:69] + wire [38:0] _T_355 = _T_354 ^ _T_315; // @[el2_lib.scala 342:76] + wire [38:0] _T_356 = single_ecc_error_hi_any ? _T_355 : _T_315; // @[el2_lib.scala 342:31] + wire [3:0] _T_362 = {_T_356[6:4],_T_356[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_364 = {_T_356[37:32],_T_356[30:16],_T_356[14:8]}; // @[Cat.scala 29:58] + wire _T_474 = ^io_dccm_rdata_lo_m; // @[el2_lib.scala 333:30] + wire _T_475 = ^io_dccm_data_ecc_lo_m; // @[el2_lib.scala 333:44] + wire _T_476 = _T_474 ^ _T_475; // @[el2_lib.scala 333:35] + wire [5:0] _T_484 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[26]}; // @[el2_lib.scala 333:76] + wire _T_485 = ^_T_484; // @[el2_lib.scala 333:83] + wire _T_486 = io_dccm_data_ecc_lo_m[5] ^ _T_485; // @[el2_lib.scala 333:71] + wire [6:0] _T_493 = {io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[11]}; // @[el2_lib.scala 333:103] + wire [14:0] _T_501 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_493}; // @[el2_lib.scala 333:103] + wire _T_502 = ^_T_501; // @[el2_lib.scala 333:110] + wire _T_503 = io_dccm_data_ecc_lo_m[4] ^ _T_502; // @[el2_lib.scala 333:98] + wire [6:0] _T_510 = {io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[4]}; // @[el2_lib.scala 333:130] + wire [14:0] _T_518 = {io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[18],_T_510}; // @[el2_lib.scala 333:130] + wire _T_519 = ^_T_518; // @[el2_lib.scala 333:137] + wire _T_520 = io_dccm_data_ecc_lo_m[3] ^ _T_519; // @[el2_lib.scala 333:125] + wire [8:0] _T_529 = {io_dccm_rdata_lo_m[15],io_dccm_rdata_lo_m[14],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[7],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[1]}; // @[el2_lib.scala 333:157] + wire [17:0] _T_538 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[29],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[22],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_529}; // @[el2_lib.scala 333:157] + wire _T_539 = ^_T_538; // @[el2_lib.scala 333:164] + wire _T_540 = io_dccm_data_ecc_lo_m[2] ^ _T_539; // @[el2_lib.scala 333:152] + wire [8:0] _T_549 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[12],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[9],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[5],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[2],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:184] + wire [17:0] _T_558 = {io_dccm_rdata_lo_m[31],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[27],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[24],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[20],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[16],_T_549}; // @[el2_lib.scala 333:184] + wire _T_559 = ^_T_558; // @[el2_lib.scala 333:191] + wire _T_560 = io_dccm_data_ecc_lo_m[1] ^ _T_559; // @[el2_lib.scala 333:179] + wire [8:0] _T_569 = {io_dccm_rdata_lo_m[13],io_dccm_rdata_lo_m[11],io_dccm_rdata_lo_m[10],io_dccm_rdata_lo_m[8],io_dccm_rdata_lo_m[6],io_dccm_rdata_lo_m[4],io_dccm_rdata_lo_m[3],io_dccm_rdata_lo_m[1],io_dccm_rdata_lo_m[0]}; // @[el2_lib.scala 333:211] + wire [17:0] _T_578 = {io_dccm_rdata_lo_m[30],io_dccm_rdata_lo_m[28],io_dccm_rdata_lo_m[26],io_dccm_rdata_lo_m[25],io_dccm_rdata_lo_m[23],io_dccm_rdata_lo_m[21],io_dccm_rdata_lo_m[19],io_dccm_rdata_lo_m[17],io_dccm_rdata_lo_m[15],_T_569}; // @[el2_lib.scala 333:211] + wire _T_579 = ^_T_578; // @[el2_lib.scala 333:218] + wire _T_580 = io_dccm_data_ecc_lo_m[0] ^ _T_579; // @[el2_lib.scala 333:206] + wire [6:0] _T_586 = {_T_476,_T_486,_T_503,_T_520,_T_540,_T_560,_T_580}; // @[Cat.scala 29:58] + wire _T_587 = _T_586 != 7'h0; // @[el2_lib.scala 334:44] + wire is_ldst_lo_m = is_ldst_m & _T_1131; // @[el2_lsu_ecc.scala 126:33] + wire _T_588 = is_ldst_lo_m & _T_587; // @[el2_lib.scala 334:32] + wire single_ecc_error_lo_any = _T_588 & _T_586[6]; // @[el2_lib.scala 334:53] + wire _T_593 = ~_T_586[6]; // @[el2_lib.scala 335:55] + wire double_ecc_error_lo_any = _T_588 & _T_593; // @[el2_lib.scala 335:53] + wire _T_596 = _T_586[5:0] == 6'h1; // @[el2_lib.scala 339:41] + wire _T_598 = _T_586[5:0] == 6'h2; // @[el2_lib.scala 339:41] + wire _T_600 = _T_586[5:0] == 6'h3; // @[el2_lib.scala 339:41] + wire _T_602 = _T_586[5:0] == 6'h4; // @[el2_lib.scala 339:41] + wire _T_604 = _T_586[5:0] == 6'h5; // @[el2_lib.scala 339:41] + wire _T_606 = _T_586[5:0] == 6'h6; // @[el2_lib.scala 339:41] + wire _T_608 = _T_586[5:0] == 6'h7; // @[el2_lib.scala 339:41] + wire _T_610 = _T_586[5:0] == 6'h8; // @[el2_lib.scala 339:41] + wire _T_612 = _T_586[5:0] == 6'h9; // @[el2_lib.scala 339:41] + wire _T_614 = _T_586[5:0] == 6'ha; // @[el2_lib.scala 339:41] + wire _T_616 = _T_586[5:0] == 6'hb; // @[el2_lib.scala 339:41] + wire _T_618 = _T_586[5:0] == 6'hc; // @[el2_lib.scala 339:41] + wire _T_620 = _T_586[5:0] == 6'hd; // @[el2_lib.scala 339:41] + wire _T_622 = _T_586[5:0] == 6'he; // @[el2_lib.scala 339:41] + wire _T_624 = _T_586[5:0] == 6'hf; // @[el2_lib.scala 339:41] + wire _T_626 = _T_586[5:0] == 6'h10; // @[el2_lib.scala 339:41] + wire _T_628 = _T_586[5:0] == 6'h11; // @[el2_lib.scala 339:41] + wire _T_630 = _T_586[5:0] == 6'h12; // @[el2_lib.scala 339:41] + wire _T_632 = _T_586[5:0] == 6'h13; // @[el2_lib.scala 339:41] + wire _T_634 = _T_586[5:0] == 6'h14; // @[el2_lib.scala 339:41] + wire _T_636 = _T_586[5:0] == 6'h15; // @[el2_lib.scala 339:41] + wire _T_638 = _T_586[5:0] == 6'h16; // @[el2_lib.scala 339:41] + wire _T_640 = _T_586[5:0] == 6'h17; // @[el2_lib.scala 339:41] + wire _T_642 = _T_586[5:0] == 6'h18; // @[el2_lib.scala 339:41] + wire _T_644 = _T_586[5:0] == 6'h19; // @[el2_lib.scala 339:41] + wire _T_646 = _T_586[5:0] == 6'h1a; // @[el2_lib.scala 339:41] + wire _T_648 = _T_586[5:0] == 6'h1b; // @[el2_lib.scala 339:41] + wire _T_650 = _T_586[5:0] == 6'h1c; // @[el2_lib.scala 339:41] + wire _T_652 = _T_586[5:0] == 6'h1d; // @[el2_lib.scala 339:41] + wire _T_654 = _T_586[5:0] == 6'h1e; // @[el2_lib.scala 339:41] + wire _T_656 = _T_586[5:0] == 6'h1f; // @[el2_lib.scala 339:41] + wire _T_658 = _T_586[5:0] == 6'h20; // @[el2_lib.scala 339:41] + wire _T_660 = _T_586[5:0] == 6'h21; // @[el2_lib.scala 339:41] + wire _T_662 = _T_586[5:0] == 6'h22; // @[el2_lib.scala 339:41] + wire _T_664 = _T_586[5:0] == 6'h23; // @[el2_lib.scala 339:41] + wire _T_666 = _T_586[5:0] == 6'h24; // @[el2_lib.scala 339:41] + wire _T_668 = _T_586[5:0] == 6'h25; // @[el2_lib.scala 339:41] + wire _T_670 = _T_586[5:0] == 6'h26; // @[el2_lib.scala 339:41] + wire _T_672 = _T_586[5:0] == 6'h27; // @[el2_lib.scala 339:41] + wire [7:0] _T_687 = {io_dccm_data_ecc_lo_m[3],io_dccm_rdata_lo_m[3:1],io_dccm_data_ecc_lo_m[2],io_dccm_rdata_lo_m[0],io_dccm_data_ecc_lo_m[1:0]}; // @[Cat.scala 29:58] + wire [38:0] _T_693 = {io_dccm_data_ecc_lo_m[6],io_dccm_rdata_lo_m[31:26],io_dccm_data_ecc_lo_m[5],io_dccm_rdata_lo_m[25:11],io_dccm_data_ecc_lo_m[4],io_dccm_rdata_lo_m[10:4],_T_687}; // @[Cat.scala 29:58] + wire [9:0] _T_711 = {_T_632,_T_630,_T_628,_T_626,_T_624,_T_622,_T_620,_T_618,_T_616,_T_614}; // @[el2_lib.scala 342:69] + wire [18:0] _T_712 = {_T_711,_T_612,_T_610,_T_608,_T_606,_T_604,_T_602,_T_600,_T_598,_T_596}; // @[el2_lib.scala 342:69] + wire [9:0] _T_721 = {_T_652,_T_650,_T_648,_T_646,_T_644,_T_642,_T_640,_T_638,_T_636,_T_634}; // @[el2_lib.scala 342:69] + wire [9:0] _T_730 = {_T_672,_T_670,_T_668,_T_666,_T_664,_T_662,_T_660,_T_658,_T_656,_T_654}; // @[el2_lib.scala 342:69] + wire [38:0] _T_732 = {_T_730,_T_721,_T_712}; // @[el2_lib.scala 342:69] + wire [38:0] _T_733 = _T_732 ^ _T_693; // @[el2_lib.scala 342:76] + wire [38:0] _T_734 = single_ecc_error_lo_any ? _T_733 : _T_693; // @[el2_lib.scala 342:31] + wire [3:0] _T_740 = {_T_734[6:4],_T_734[2]}; // @[Cat.scala 29:58] + wire [27:0] _T_742 = {_T_734[37:32],_T_734[30:16],_T_734[14:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_1158 = io_dma_dccm_wen ? io_dma_dccm_wdata_lo : io_stbuf_data_any; // @[el2_lsu_ecc.scala 149:87] + wire [31:0] dccm_wdata_lo_any = io_ld_single_ecc_error_r_ff ? io_sec_data_lo_r_ff : _T_1158; // @[el2_lsu_ecc.scala 149:27] + wire _T_774 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[1]; // @[el2_lib.scala 259:74] + wire _T_775 = _T_774 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_776 = _T_775 ^ dccm_wdata_lo_any[4]; // @[el2_lib.scala 259:74] + wire _T_777 = _T_776 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_778 = _T_777 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_779 = _T_778 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_780 = _T_779 ^ dccm_wdata_lo_any[11]; // @[el2_lib.scala 259:74] + wire _T_781 = _T_780 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_782 = _T_781 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_783 = _T_782 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_784 = _T_783 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_785 = _T_784 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_786 = _T_785 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_787 = _T_786 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_788 = _T_787 ^ dccm_wdata_lo_any[26]; // @[el2_lib.scala 259:74] + wire _T_789 = _T_788 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_790 = _T_789 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_809 = dccm_wdata_lo_any[0] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] + wire _T_810 = _T_809 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_811 = _T_810 ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] + wire _T_812 = _T_811 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_813 = _T_812 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_814 = _T_813 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_815 = _T_814 ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] + wire _T_816 = _T_815 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_817 = _T_816 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_818 = _T_817 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_819 = _T_818 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_820 = _T_819 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_821 = _T_820 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_822 = _T_821 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_823 = _T_822 ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] + wire _T_824 = _T_823 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_825 = _T_824 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire _T_844 = dccm_wdata_lo_any[1] ^ dccm_wdata_lo_any[2]; // @[el2_lib.scala 259:74] + wire _T_845 = _T_844 ^ dccm_wdata_lo_any[3]; // @[el2_lib.scala 259:74] + wire _T_846 = _T_845 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] + wire _T_847 = _T_846 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_848 = _T_847 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_849 = _T_848 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_850 = _T_849 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] + wire _T_851 = _T_850 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_852 = _T_851 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_853 = _T_852 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_854 = _T_853 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_855 = _T_854 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_856 = _T_855 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_857 = _T_856 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_858 = _T_857 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] + wire _T_859 = _T_858 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_860 = _T_859 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire _T_876 = dccm_wdata_lo_any[4] ^ dccm_wdata_lo_any[5]; // @[el2_lib.scala 259:74] + wire _T_877 = _T_876 ^ dccm_wdata_lo_any[6]; // @[el2_lib.scala 259:74] + wire _T_878 = _T_877 ^ dccm_wdata_lo_any[7]; // @[el2_lib.scala 259:74] + wire _T_879 = _T_878 ^ dccm_wdata_lo_any[8]; // @[el2_lib.scala 259:74] + wire _T_880 = _T_879 ^ dccm_wdata_lo_any[9]; // @[el2_lib.scala 259:74] + wire _T_881 = _T_880 ^ dccm_wdata_lo_any[10]; // @[el2_lib.scala 259:74] + wire _T_882 = _T_881 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] + wire _T_883 = _T_882 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_884 = _T_883 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_885 = _T_884 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_886 = _T_885 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_887 = _T_886 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_888 = _T_887 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_889 = _T_888 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_905 = dccm_wdata_lo_any[11] ^ dccm_wdata_lo_any[12]; // @[el2_lib.scala 259:74] + wire _T_906 = _T_905 ^ dccm_wdata_lo_any[13]; // @[el2_lib.scala 259:74] + wire _T_907 = _T_906 ^ dccm_wdata_lo_any[14]; // @[el2_lib.scala 259:74] + wire _T_908 = _T_907 ^ dccm_wdata_lo_any[15]; // @[el2_lib.scala 259:74] + wire _T_909 = _T_908 ^ dccm_wdata_lo_any[16]; // @[el2_lib.scala 259:74] + wire _T_910 = _T_909 ^ dccm_wdata_lo_any[17]; // @[el2_lib.scala 259:74] + wire _T_911 = _T_910 ^ dccm_wdata_lo_any[18]; // @[el2_lib.scala 259:74] + wire _T_912 = _T_911 ^ dccm_wdata_lo_any[19]; // @[el2_lib.scala 259:74] + wire _T_913 = _T_912 ^ dccm_wdata_lo_any[20]; // @[el2_lib.scala 259:74] + wire _T_914 = _T_913 ^ dccm_wdata_lo_any[21]; // @[el2_lib.scala 259:74] + wire _T_915 = _T_914 ^ dccm_wdata_lo_any[22]; // @[el2_lib.scala 259:74] + wire _T_916 = _T_915 ^ dccm_wdata_lo_any[23]; // @[el2_lib.scala 259:74] + wire _T_917 = _T_916 ^ dccm_wdata_lo_any[24]; // @[el2_lib.scala 259:74] + wire _T_918 = _T_917 ^ dccm_wdata_lo_any[25]; // @[el2_lib.scala 259:74] + wire _T_925 = dccm_wdata_lo_any[26] ^ dccm_wdata_lo_any[27]; // @[el2_lib.scala 259:74] + wire _T_926 = _T_925 ^ dccm_wdata_lo_any[28]; // @[el2_lib.scala 259:74] + wire _T_927 = _T_926 ^ dccm_wdata_lo_any[29]; // @[el2_lib.scala 259:74] + wire _T_928 = _T_927 ^ dccm_wdata_lo_any[30]; // @[el2_lib.scala 259:74] + wire _T_929 = _T_928 ^ dccm_wdata_lo_any[31]; // @[el2_lib.scala 259:74] + wire [5:0] _T_934 = {_T_929,_T_918,_T_889,_T_860,_T_825,_T_790}; // @[Cat.scala 29:58] + wire _T_935 = ^dccm_wdata_lo_any; // @[el2_lib.scala 267:13] + wire _T_936 = ^_T_934; // @[el2_lib.scala 267:23] + wire _T_937 = _T_935 ^ _T_936; // @[el2_lib.scala 267:18] + wire [31:0] _T_1162 = io_dma_dccm_wen ? io_dma_dccm_wdata_hi : io_stbuf_data_any; // @[el2_lsu_ecc.scala 150:87] + wire [31:0] dccm_wdata_hi_any = io_ld_single_ecc_error_r_ff ? io_sec_data_hi_r_ff : _T_1162; // @[el2_lsu_ecc.scala 150:27] + wire _T_956 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[1]; // @[el2_lib.scala 259:74] + wire _T_957 = _T_956 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_958 = _T_957 ^ dccm_wdata_hi_any[4]; // @[el2_lib.scala 259:74] + wire _T_959 = _T_958 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_960 = _T_959 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_961 = _T_960 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_962 = _T_961 ^ dccm_wdata_hi_any[11]; // @[el2_lib.scala 259:74] + wire _T_963 = _T_962 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_964 = _T_963 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_965 = _T_964 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_966 = _T_965 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_967 = _T_966 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_968 = _T_967 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_969 = _T_968 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_970 = _T_969 ^ dccm_wdata_hi_any[26]; // @[el2_lib.scala 259:74] + wire _T_971 = _T_970 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_972 = _T_971 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_991 = dccm_wdata_hi_any[0] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] + wire _T_992 = _T_991 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_993 = _T_992 ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] + wire _T_994 = _T_993 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_995 = _T_994 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_996 = _T_995 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_997 = _T_996 ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] + wire _T_998 = _T_997 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_999 = _T_998 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1000 = _T_999 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1001 = _T_1000 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1002 = _T_1001 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1003 = _T_1002 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1004 = _T_1003 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1005 = _T_1004 ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] + wire _T_1006 = _T_1005 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_1007 = _T_1006 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire _T_1026 = dccm_wdata_hi_any[1] ^ dccm_wdata_hi_any[2]; // @[el2_lib.scala 259:74] + wire _T_1027 = _T_1026 ^ dccm_wdata_hi_any[3]; // @[el2_lib.scala 259:74] + wire _T_1028 = _T_1027 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] + wire _T_1029 = _T_1028 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_1030 = _T_1029 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_1031 = _T_1030 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_1032 = _T_1031 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] + wire _T_1033 = _T_1032 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_1034 = _T_1033 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1035 = _T_1034 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1036 = _T_1035 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1037 = _T_1036 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1038 = _T_1037 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1039 = _T_1038 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1040 = _T_1039 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] + wire _T_1041 = _T_1040 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_1042 = _T_1041 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire _T_1058 = dccm_wdata_hi_any[4] ^ dccm_wdata_hi_any[5]; // @[el2_lib.scala 259:74] + wire _T_1059 = _T_1058 ^ dccm_wdata_hi_any[6]; // @[el2_lib.scala 259:74] + wire _T_1060 = _T_1059 ^ dccm_wdata_hi_any[7]; // @[el2_lib.scala 259:74] + wire _T_1061 = _T_1060 ^ dccm_wdata_hi_any[8]; // @[el2_lib.scala 259:74] + wire _T_1062 = _T_1061 ^ dccm_wdata_hi_any[9]; // @[el2_lib.scala 259:74] + wire _T_1063 = _T_1062 ^ dccm_wdata_hi_any[10]; // @[el2_lib.scala 259:74] + wire _T_1064 = _T_1063 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] + wire _T_1065 = _T_1064 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_1066 = _T_1065 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1067 = _T_1066 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1068 = _T_1067 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1069 = _T_1068 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1070 = _T_1069 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1071 = _T_1070 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1087 = dccm_wdata_hi_any[11] ^ dccm_wdata_hi_any[12]; // @[el2_lib.scala 259:74] + wire _T_1088 = _T_1087 ^ dccm_wdata_hi_any[13]; // @[el2_lib.scala 259:74] + wire _T_1089 = _T_1088 ^ dccm_wdata_hi_any[14]; // @[el2_lib.scala 259:74] + wire _T_1090 = _T_1089 ^ dccm_wdata_hi_any[15]; // @[el2_lib.scala 259:74] + wire _T_1091 = _T_1090 ^ dccm_wdata_hi_any[16]; // @[el2_lib.scala 259:74] + wire _T_1092 = _T_1091 ^ dccm_wdata_hi_any[17]; // @[el2_lib.scala 259:74] + wire _T_1093 = _T_1092 ^ dccm_wdata_hi_any[18]; // @[el2_lib.scala 259:74] + wire _T_1094 = _T_1093 ^ dccm_wdata_hi_any[19]; // @[el2_lib.scala 259:74] + wire _T_1095 = _T_1094 ^ dccm_wdata_hi_any[20]; // @[el2_lib.scala 259:74] + wire _T_1096 = _T_1095 ^ dccm_wdata_hi_any[21]; // @[el2_lib.scala 259:74] + wire _T_1097 = _T_1096 ^ dccm_wdata_hi_any[22]; // @[el2_lib.scala 259:74] + wire _T_1098 = _T_1097 ^ dccm_wdata_hi_any[23]; // @[el2_lib.scala 259:74] + wire _T_1099 = _T_1098 ^ dccm_wdata_hi_any[24]; // @[el2_lib.scala 259:74] + wire _T_1100 = _T_1099 ^ dccm_wdata_hi_any[25]; // @[el2_lib.scala 259:74] + wire _T_1107 = dccm_wdata_hi_any[26] ^ dccm_wdata_hi_any[27]; // @[el2_lib.scala 259:74] + wire _T_1108 = _T_1107 ^ dccm_wdata_hi_any[28]; // @[el2_lib.scala 259:74] + wire _T_1109 = _T_1108 ^ dccm_wdata_hi_any[29]; // @[el2_lib.scala 259:74] + wire _T_1110 = _T_1109 ^ dccm_wdata_hi_any[30]; // @[el2_lib.scala 259:74] + wire _T_1111 = _T_1110 ^ dccm_wdata_hi_any[31]; // @[el2_lib.scala 259:74] + wire [5:0] _T_1116 = {_T_1111,_T_1100,_T_1071,_T_1042,_T_1007,_T_972}; // @[Cat.scala 29:58] + wire _T_1117 = ^dccm_wdata_hi_any; // @[el2_lib.scala 267:13] + wire _T_1118 = ^_T_1116; // @[el2_lib.scala 267:23] + wire _T_1119 = _T_1117 ^ _T_1118; // @[el2_lib.scala 267:18] + reg _T_1150; // @[el2_lsu_ecc.scala 141:72] + reg _T_1151; // @[el2_lsu_ecc.scala 142:72] + reg _T_1152; // @[el2_lsu_ecc.scala 143:72] + reg _T_1153; // @[el2_lsu_ecc.scala 144:72] + reg [31:0] _T_1154; // @[el2_lsu_ecc.scala 145:72] + reg [31:0] _T_1155; // @[el2_lsu_ecc.scala 146:72] + reg [31:0] _T_1164; // @[el2_lib.scala 514:16] + reg [31:0] _T_1165; // @[el2_lib.scala 514:16] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + assign io_sec_data_hi_r = _T_1154; // @[el2_lsu_ecc.scala 114:22 el2_lsu_ecc.scala 145:62] + assign io_sec_data_lo_r = _T_1155; // @[el2_lsu_ecc.scala 117:25 el2_lsu_ecc.scala 146:62] + assign io_sec_data_hi_m = {_T_364,_T_362}; // @[el2_lsu_ecc.scala 90:32 el2_lsu_ecc.scala 134:27] + assign io_sec_data_lo_m = {_T_742,_T_740}; // @[el2_lsu_ecc.scala 91:32 el2_lsu_ecc.scala 136:27] + assign io_sec_data_hi_r_ff = _T_1164; // @[el2_lsu_ecc.scala 157:23] + assign io_sec_data_lo_r_ff = _T_1165; // @[el2_lsu_ecc.scala 158:23] + assign io_dma_dccm_wdata_ecc_hi = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 154:28] + assign io_dma_dccm_wdata_ecc_lo = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 155:28] + assign io_stbuf_ecc_any = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 153:28] + assign io_sec_data_ecc_hi_r_ff = {_T_1119,_T_1116}; // @[el2_lsu_ecc.scala 151:28] + assign io_sec_data_ecc_lo_r_ff = {_T_937,_T_934}; // @[el2_lsu_ecc.scala 152:28] + assign io_single_ecc_error_hi_r = _T_1153; // @[el2_lsu_ecc.scala 115:31 el2_lsu_ecc.scala 144:62] + assign io_single_ecc_error_lo_r = _T_1152; // @[el2_lsu_ecc.scala 118:31 el2_lsu_ecc.scala 143:62] + assign io_lsu_single_ecc_error_r = _T_1150; // @[el2_lsu_ecc.scala 120:31 el2_lsu_ecc.scala 141:62] + assign io_lsu_double_ecc_error_r = _T_1151; // @[el2_lsu_ecc.scala 121:31 el2_lsu_ecc.scala 142:62] + assign io_lsu_single_ecc_error_m = single_ecc_error_hi_any | single_ecc_error_lo_any; // @[el2_lsu_ecc.scala 92:30 el2_lsu_ecc.scala 138:33] + assign io_lsu_double_ecc_error_m = double_ecc_error_hi_any | double_ecc_error_lo_any; // @[el2_lsu_ecc.scala 93:30 el2_lsu_ecc.scala 139:33] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = io_ld_single_ecc_error_r; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2967,27 +4074,45 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_1188 = _RAND_0[0:0]; + _T_1150 = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - _T_1189 = _RAND_1[0:0]; + _T_1151 = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - _T_1190 = _RAND_2[0:0]; + _T_1152 = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - _T_1191 = _RAND_3[0:0]; + _T_1153 = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - _T_1192 = _RAND_4[31:0]; + _T_1154 = _RAND_4[31:0]; _RAND_5 = {1{`RANDOM}}; - _T_1193 = _RAND_5[31:0]; + _T_1155 = _RAND_5[31:0]; _RAND_6 = {1{`RANDOM}}; - _T_1202 = _RAND_6[31:0]; + _T_1164 = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - _T_1203 = _RAND_7[31:0]; + _T_1165 = _RAND_7[31:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - _T_1202 = 32'h0; + _T_1150 = 1'h0; end if (reset) begin - _T_1203 = 32'h0; + _T_1151 = 1'h0; + end + if (reset) begin + _T_1152 = 1'h0; + end + if (reset) begin + _T_1153 = 1'h0; + end + if (reset) begin + _T_1154 = 32'h0; + end + if (reset) begin + _T_1155 = 32'h0; + end + if (reset) begin + _T_1164 = 32'h0; + end + if (reset) begin + _T_1165 = 32'h0; end `endif // RANDOMIZE end // initial @@ -2995,26 +4120,60 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge io_lsu_c2_r_clk) begin - _T_1188 <= io_lsu_single_ecc_error_m; - _T_1189 <= io_lsu_double_ecc_error_m; - _T_1190 <= _T_595 & _T_483; - _T_1191 <= _T_210 & _T_98; - _T_1192 <= io_sec_data_hi_m; - _T_1193 <= io_sec_data_lo_m; - end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1202 <= 32'h0; - end else if (io_ld_single_ecc_error_r) begin - _T_1202 <= io_sec_data_hi_r; + _T_1150 <= 1'h0; + end else begin + _T_1150 <= io_lsu_single_ecc_error_m; end end - always @(posedge clock or posedge reset) begin + always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_1203 <= 32'h0; - end else if (io_ld_single_ecc_error_r) begin - _T_1203 <= io_sec_data_lo_r; + _T_1151 <= 1'h0; + end else begin + _T_1151 <= io_lsu_double_ecc_error_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1152 <= 1'h0; + end else begin + _T_1152 <= _T_588 & _T_586[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1153 <= 1'h0; + end else begin + _T_1153 <= _T_210 & _T_208[6]; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1154 <= 32'h0; + end else begin + _T_1154 <= io_sec_data_hi_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_1155 <= 32'h0; + end else begin + _T_1155 <= io_sec_data_lo_m; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + _T_1164 <= 32'h0; + end else begin + _T_1164 <= io_sec_data_hi_r; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + _T_1165 <= 32'h0; + end else begin + _T_1165 <= io_sec_data_lo_r; end end endmodule @@ -3050,615 +4209,626 @@ module el2_lsu_trigger( output [3:0] io_lsu_trigger_match_m ); wire [15:0] _T_1 = io_lsu_pkt_m_word ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 17:60] - wire _T_4 = io_lsu_pkt_m_half | io_lsu_pkt_m_word; // @[el2_lsu_trigger.scala 17:110] + wire [15:0] _T_3 = _T_1 & io_store_data_m[31:16]; // @[el2_lsu_trigger.scala 16:61] + wire _T_4 = io_lsu_pkt_m_half | io_lsu_pkt_m_word; // @[el2_lsu_trigger.scala 16:114] wire [7:0] _T_6 = _T_4 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 17:131] + wire [7:0] _T_8 = _T_6 & io_store_data_m[15:8]; // @[el2_lsu_trigger.scala 16:136] wire [31:0] store_data_trigger_m = {_T_3,_T_8,io_store_data_m[7:0]}; // @[Cat.scala 29:58] - wire _T_12 = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 24:107] - wire _T_13 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[el2_lsu_trigger.scala 25:35] + wire _T_12 = ~io_trigger_pkt_any_0_select; // @[el2_lsu_trigger.scala 17:53] + wire _T_13 = io_trigger_pkt_any_0_select & io_trigger_pkt_any_0_store; // @[el2_lsu_trigger.scala 17:136] wire [31:0] _T_15 = _T_12 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_16 = _T_13 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_17 = _T_15 | _T_16; // @[Mux.scala 27:72] - wire _T_23 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 194:73] - wire _T_24 = ~_T_23; // @[el2_lib.scala 194:47] - wire _T_25 = io_trigger_pkt_any_0_match_ & _T_24; // @[el2_lib.scala 194:44] - wire _T_28 = io_trigger_pkt_any_0_tdata2[0] == _T_17[0]; // @[el2_lib.scala 195:52] - wire _T_29 = _T_25 | _T_28; // @[el2_lib.scala 195:41] - wire _T_31 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 197:37] - wire _T_32 = _T_31 & _T_25; // @[el2_lib.scala 197:42] - wire _T_35 = io_trigger_pkt_any_0_tdata2[1] == _T_17[1]; // @[el2_lib.scala 197:79] - wire _T_36 = _T_32 | _T_35; // @[el2_lib.scala 197:24] - wire _T_38 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 197:37] - wire _T_39 = _T_38 & _T_25; // @[el2_lib.scala 197:42] - wire _T_42 = io_trigger_pkt_any_0_tdata2[2] == _T_17[2]; // @[el2_lib.scala 197:79] - wire _T_43 = _T_39 | _T_42; // @[el2_lib.scala 197:24] - wire _T_45 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 197:37] - wire _T_46 = _T_45 & _T_25; // @[el2_lib.scala 197:42] - wire _T_49 = io_trigger_pkt_any_0_tdata2[3] == _T_17[3]; // @[el2_lib.scala 197:79] - wire _T_50 = _T_46 | _T_49; // @[el2_lib.scala 197:24] - wire _T_52 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 197:37] - wire _T_53 = _T_52 & _T_25; // @[el2_lib.scala 197:42] - wire _T_56 = io_trigger_pkt_any_0_tdata2[4] == _T_17[4]; // @[el2_lib.scala 197:79] - wire _T_57 = _T_53 | _T_56; // @[el2_lib.scala 197:24] - wire _T_59 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 197:37] - wire _T_60 = _T_59 & _T_25; // @[el2_lib.scala 197:42] - wire _T_63 = io_trigger_pkt_any_0_tdata2[5] == _T_17[5]; // @[el2_lib.scala 197:79] - wire _T_64 = _T_60 | _T_63; // @[el2_lib.scala 197:24] - wire _T_66 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 197:37] - wire _T_67 = _T_66 & _T_25; // @[el2_lib.scala 197:42] - wire _T_70 = io_trigger_pkt_any_0_tdata2[6] == _T_17[6]; // @[el2_lib.scala 197:79] - wire _T_71 = _T_67 | _T_70; // @[el2_lib.scala 197:24] - wire _T_73 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 197:37] - wire _T_74 = _T_73 & _T_25; // @[el2_lib.scala 197:42] - wire _T_77 = io_trigger_pkt_any_0_tdata2[7] == _T_17[7]; // @[el2_lib.scala 197:79] - wire _T_78 = _T_74 | _T_77; // @[el2_lib.scala 197:24] - wire _T_80 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 197:37] - wire _T_81 = _T_80 & _T_25; // @[el2_lib.scala 197:42] - wire _T_84 = io_trigger_pkt_any_0_tdata2[8] == _T_17[8]; // @[el2_lib.scala 197:79] - wire _T_85 = _T_81 | _T_84; // @[el2_lib.scala 197:24] - wire _T_87 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 197:37] - wire _T_88 = _T_87 & _T_25; // @[el2_lib.scala 197:42] - wire _T_91 = io_trigger_pkt_any_0_tdata2[9] == _T_17[9]; // @[el2_lib.scala 197:79] - wire _T_92 = _T_88 | _T_91; // @[el2_lib.scala 197:24] - wire _T_94 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 197:37] - wire _T_95 = _T_94 & _T_25; // @[el2_lib.scala 197:42] - wire _T_98 = io_trigger_pkt_any_0_tdata2[10] == _T_17[10]; // @[el2_lib.scala 197:79] - wire _T_99 = _T_95 | _T_98; // @[el2_lib.scala 197:24] - wire _T_101 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 197:37] - wire _T_102 = _T_101 & _T_25; // @[el2_lib.scala 197:42] - wire _T_105 = io_trigger_pkt_any_0_tdata2[11] == _T_17[11]; // @[el2_lib.scala 197:79] - wire _T_106 = _T_102 | _T_105; // @[el2_lib.scala 197:24] - wire _T_108 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 197:37] - wire _T_109 = _T_108 & _T_25; // @[el2_lib.scala 197:42] - wire _T_112 = io_trigger_pkt_any_0_tdata2[12] == _T_17[12]; // @[el2_lib.scala 197:79] - wire _T_113 = _T_109 | _T_112; // @[el2_lib.scala 197:24] - wire _T_115 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 197:37] - wire _T_116 = _T_115 & _T_25; // @[el2_lib.scala 197:42] - wire _T_119 = io_trigger_pkt_any_0_tdata2[13] == _T_17[13]; // @[el2_lib.scala 197:79] - wire _T_120 = _T_116 | _T_119; // @[el2_lib.scala 197:24] - wire _T_122 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 197:37] - wire _T_123 = _T_122 & _T_25; // @[el2_lib.scala 197:42] - wire _T_126 = io_trigger_pkt_any_0_tdata2[14] == _T_17[14]; // @[el2_lib.scala 197:79] - wire _T_127 = _T_123 | _T_126; // @[el2_lib.scala 197:24] - wire _T_129 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 197:37] - wire _T_130 = _T_129 & _T_25; // @[el2_lib.scala 197:42] - wire _T_133 = io_trigger_pkt_any_0_tdata2[15] == _T_17[15]; // @[el2_lib.scala 197:79] - wire _T_134 = _T_130 | _T_133; // @[el2_lib.scala 197:24] - wire _T_136 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 197:37] - wire _T_137 = _T_136 & _T_25; // @[el2_lib.scala 197:42] - wire _T_140 = io_trigger_pkt_any_0_tdata2[16] == _T_17[16]; // @[el2_lib.scala 197:79] - wire _T_141 = _T_137 | _T_140; // @[el2_lib.scala 197:24] - wire _T_143 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 197:37] - wire _T_144 = _T_143 & _T_25; // @[el2_lib.scala 197:42] - wire _T_147 = io_trigger_pkt_any_0_tdata2[17] == _T_17[17]; // @[el2_lib.scala 197:79] - wire _T_148 = _T_144 | _T_147; // @[el2_lib.scala 197:24] - wire _T_150 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 197:37] - wire _T_151 = _T_150 & _T_25; // @[el2_lib.scala 197:42] - wire _T_154 = io_trigger_pkt_any_0_tdata2[18] == _T_17[18]; // @[el2_lib.scala 197:79] - wire _T_155 = _T_151 | _T_154; // @[el2_lib.scala 197:24] - wire _T_157 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 197:37] - wire _T_158 = _T_157 & _T_25; // @[el2_lib.scala 197:42] - wire _T_161 = io_trigger_pkt_any_0_tdata2[19] == _T_17[19]; // @[el2_lib.scala 197:79] - wire _T_162 = _T_158 | _T_161; // @[el2_lib.scala 197:24] - wire _T_164 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 197:37] - wire _T_165 = _T_164 & _T_25; // @[el2_lib.scala 197:42] - wire _T_168 = io_trigger_pkt_any_0_tdata2[20] == _T_17[20]; // @[el2_lib.scala 197:79] - wire _T_169 = _T_165 | _T_168; // @[el2_lib.scala 197:24] - wire _T_171 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 197:37] - wire _T_172 = _T_171 & _T_25; // @[el2_lib.scala 197:42] - wire _T_175 = io_trigger_pkt_any_0_tdata2[21] == _T_17[21]; // @[el2_lib.scala 197:79] - wire _T_176 = _T_172 | _T_175; // @[el2_lib.scala 197:24] - wire _T_178 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 197:37] - wire _T_179 = _T_178 & _T_25; // @[el2_lib.scala 197:42] - wire _T_182 = io_trigger_pkt_any_0_tdata2[22] == _T_17[22]; // @[el2_lib.scala 197:79] - wire _T_183 = _T_179 | _T_182; // @[el2_lib.scala 197:24] - wire _T_185 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 197:37] - wire _T_186 = _T_185 & _T_25; // @[el2_lib.scala 197:42] - wire _T_189 = io_trigger_pkt_any_0_tdata2[23] == _T_17[23]; // @[el2_lib.scala 197:79] - wire _T_190 = _T_186 | _T_189; // @[el2_lib.scala 197:24] - wire _T_192 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 197:37] - wire _T_193 = _T_192 & _T_25; // @[el2_lib.scala 197:42] - wire _T_196 = io_trigger_pkt_any_0_tdata2[24] == _T_17[24]; // @[el2_lib.scala 197:79] - wire _T_197 = _T_193 | _T_196; // @[el2_lib.scala 197:24] - wire _T_199 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 197:37] - wire _T_200 = _T_199 & _T_25; // @[el2_lib.scala 197:42] - wire _T_203 = io_trigger_pkt_any_0_tdata2[25] == _T_17[25]; // @[el2_lib.scala 197:79] - wire _T_204 = _T_200 | _T_203; // @[el2_lib.scala 197:24] - wire _T_206 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 197:37] - wire _T_207 = _T_206 & _T_25; // @[el2_lib.scala 197:42] - wire _T_210 = io_trigger_pkt_any_0_tdata2[26] == _T_17[26]; // @[el2_lib.scala 197:79] - wire _T_211 = _T_207 | _T_210; // @[el2_lib.scala 197:24] - wire _T_213 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 197:37] - wire _T_214 = _T_213 & _T_25; // @[el2_lib.scala 197:42] - wire _T_217 = io_trigger_pkt_any_0_tdata2[27] == _T_17[27]; // @[el2_lib.scala 197:79] - wire _T_218 = _T_214 | _T_217; // @[el2_lib.scala 197:24] - wire _T_220 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 197:37] - wire _T_221 = _T_220 & _T_25; // @[el2_lib.scala 197:42] - wire _T_224 = io_trigger_pkt_any_0_tdata2[28] == _T_17[28]; // @[el2_lib.scala 197:79] - wire _T_225 = _T_221 | _T_224; // @[el2_lib.scala 197:24] - wire _T_227 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 197:37] - wire _T_228 = _T_227 & _T_25; // @[el2_lib.scala 197:42] - wire _T_231 = io_trigger_pkt_any_0_tdata2[29] == _T_17[29]; // @[el2_lib.scala 197:79] - wire _T_232 = _T_228 | _T_231; // @[el2_lib.scala 197:24] - wire _T_234 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 197:37] - wire _T_235 = _T_234 & _T_25; // @[el2_lib.scala 197:42] - wire _T_238 = io_trigger_pkt_any_0_tdata2[30] == _T_17[30]; // @[el2_lib.scala 197:79] - wire _T_239 = _T_235 | _T_238; // @[el2_lib.scala 197:24] - wire _T_241 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 197:37] - wire _T_242 = _T_241 & _T_25; // @[el2_lib.scala 197:42] - wire _T_245 = io_trigger_pkt_any_0_tdata2[31] == _T_17[31]; // @[el2_lib.scala 197:79] - wire _T_246 = _T_242 | _T_245; // @[el2_lib.scala 197:24] - wire [7:0] _T_253 = {_T_78,_T_71,_T_64,_T_57,_T_50,_T_43,_T_36,_T_29}; // @[el2_lib.scala 198:14] - wire [15:0] _T_261 = {_T_134,_T_127,_T_120,_T_113,_T_106,_T_99,_T_92,_T_85,_T_253}; // @[el2_lib.scala 198:14] - wire [7:0] _T_268 = {_T_190,_T_183,_T_176,_T_169,_T_162,_T_155,_T_148,_T_141}; // @[el2_lib.scala 198:14] - wire [31:0] _T_277 = {_T_246,_T_239,_T_232,_T_225,_T_218,_T_211,_T_204,_T_197,_T_268,_T_261}; // @[el2_lib.scala 198:14] - wire lsu_trigger_data_match_0 = &_T_277; // @[el2_lib.scala 198:21] - wire _T_279 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 24:107] - wire _T_280 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[el2_lsu_trigger.scala 25:35] - wire [31:0] _T_282 = _T_279 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_283 = _T_280 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_284 = _T_282 | _T_283; // @[Mux.scala 27:72] - wire _T_290 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 194:73] - wire _T_291 = ~_T_290; // @[el2_lib.scala 194:47] - wire _T_292 = io_trigger_pkt_any_1_match_ & _T_291; // @[el2_lib.scala 194:44] - wire _T_295 = io_trigger_pkt_any_1_tdata2[0] == _T_284[0]; // @[el2_lib.scala 195:52] - wire _T_296 = _T_292 | _T_295; // @[el2_lib.scala 195:41] - wire _T_298 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 197:37] - wire _T_299 = _T_298 & _T_292; // @[el2_lib.scala 197:42] - wire _T_302 = io_trigger_pkt_any_1_tdata2[1] == _T_284[1]; // @[el2_lib.scala 197:79] - wire _T_303 = _T_299 | _T_302; // @[el2_lib.scala 197:24] - wire _T_305 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 197:37] - wire _T_306 = _T_305 & _T_292; // @[el2_lib.scala 197:42] - wire _T_309 = io_trigger_pkt_any_1_tdata2[2] == _T_284[2]; // @[el2_lib.scala 197:79] - wire _T_310 = _T_306 | _T_309; // @[el2_lib.scala 197:24] - wire _T_312 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 197:37] - wire _T_313 = _T_312 & _T_292; // @[el2_lib.scala 197:42] - wire _T_316 = io_trigger_pkt_any_1_tdata2[3] == _T_284[3]; // @[el2_lib.scala 197:79] - wire _T_317 = _T_313 | _T_316; // @[el2_lib.scala 197:24] - wire _T_319 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 197:37] - wire _T_320 = _T_319 & _T_292; // @[el2_lib.scala 197:42] - wire _T_323 = io_trigger_pkt_any_1_tdata2[4] == _T_284[4]; // @[el2_lib.scala 197:79] - wire _T_324 = _T_320 | _T_323; // @[el2_lib.scala 197:24] - wire _T_326 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 197:37] - wire _T_327 = _T_326 & _T_292; // @[el2_lib.scala 197:42] - wire _T_330 = io_trigger_pkt_any_1_tdata2[5] == _T_284[5]; // @[el2_lib.scala 197:79] - wire _T_331 = _T_327 | _T_330; // @[el2_lib.scala 197:24] - wire _T_333 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 197:37] - wire _T_334 = _T_333 & _T_292; // @[el2_lib.scala 197:42] - wire _T_337 = io_trigger_pkt_any_1_tdata2[6] == _T_284[6]; // @[el2_lib.scala 197:79] - wire _T_338 = _T_334 | _T_337; // @[el2_lib.scala 197:24] - wire _T_340 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 197:37] - wire _T_341 = _T_340 & _T_292; // @[el2_lib.scala 197:42] - wire _T_344 = io_trigger_pkt_any_1_tdata2[7] == _T_284[7]; // @[el2_lib.scala 197:79] - wire _T_345 = _T_341 | _T_344; // @[el2_lib.scala 197:24] - wire _T_347 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 197:37] - wire _T_348 = _T_347 & _T_292; // @[el2_lib.scala 197:42] - wire _T_351 = io_trigger_pkt_any_1_tdata2[8] == _T_284[8]; // @[el2_lib.scala 197:79] - wire _T_352 = _T_348 | _T_351; // @[el2_lib.scala 197:24] - wire _T_354 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 197:37] - wire _T_355 = _T_354 & _T_292; // @[el2_lib.scala 197:42] - wire _T_358 = io_trigger_pkt_any_1_tdata2[9] == _T_284[9]; // @[el2_lib.scala 197:79] - wire _T_359 = _T_355 | _T_358; // @[el2_lib.scala 197:24] - wire _T_361 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 197:37] - wire _T_362 = _T_361 & _T_292; // @[el2_lib.scala 197:42] - wire _T_365 = io_trigger_pkt_any_1_tdata2[10] == _T_284[10]; // @[el2_lib.scala 197:79] - wire _T_366 = _T_362 | _T_365; // @[el2_lib.scala 197:24] - wire _T_368 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 197:37] - wire _T_369 = _T_368 & _T_292; // @[el2_lib.scala 197:42] - wire _T_372 = io_trigger_pkt_any_1_tdata2[11] == _T_284[11]; // @[el2_lib.scala 197:79] - wire _T_373 = _T_369 | _T_372; // @[el2_lib.scala 197:24] - wire _T_375 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 197:37] - wire _T_376 = _T_375 & _T_292; // @[el2_lib.scala 197:42] - wire _T_379 = io_trigger_pkt_any_1_tdata2[12] == _T_284[12]; // @[el2_lib.scala 197:79] - wire _T_380 = _T_376 | _T_379; // @[el2_lib.scala 197:24] - wire _T_382 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 197:37] - wire _T_383 = _T_382 & _T_292; // @[el2_lib.scala 197:42] - wire _T_386 = io_trigger_pkt_any_1_tdata2[13] == _T_284[13]; // @[el2_lib.scala 197:79] - wire _T_387 = _T_383 | _T_386; // @[el2_lib.scala 197:24] - wire _T_389 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 197:37] - wire _T_390 = _T_389 & _T_292; // @[el2_lib.scala 197:42] - wire _T_393 = io_trigger_pkt_any_1_tdata2[14] == _T_284[14]; // @[el2_lib.scala 197:79] - wire _T_394 = _T_390 | _T_393; // @[el2_lib.scala 197:24] - wire _T_396 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 197:37] - wire _T_397 = _T_396 & _T_292; // @[el2_lib.scala 197:42] - wire _T_400 = io_trigger_pkt_any_1_tdata2[15] == _T_284[15]; // @[el2_lib.scala 197:79] - wire _T_401 = _T_397 | _T_400; // @[el2_lib.scala 197:24] - wire _T_403 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 197:37] - wire _T_404 = _T_403 & _T_292; // @[el2_lib.scala 197:42] - wire _T_407 = io_trigger_pkt_any_1_tdata2[16] == _T_284[16]; // @[el2_lib.scala 197:79] - wire _T_408 = _T_404 | _T_407; // @[el2_lib.scala 197:24] - wire _T_410 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 197:37] - wire _T_411 = _T_410 & _T_292; // @[el2_lib.scala 197:42] - wire _T_414 = io_trigger_pkt_any_1_tdata2[17] == _T_284[17]; // @[el2_lib.scala 197:79] - wire _T_415 = _T_411 | _T_414; // @[el2_lib.scala 197:24] - wire _T_417 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 197:37] - wire _T_418 = _T_417 & _T_292; // @[el2_lib.scala 197:42] - wire _T_421 = io_trigger_pkt_any_1_tdata2[18] == _T_284[18]; // @[el2_lib.scala 197:79] - wire _T_422 = _T_418 | _T_421; // @[el2_lib.scala 197:24] - wire _T_424 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 197:37] - wire _T_425 = _T_424 & _T_292; // @[el2_lib.scala 197:42] - wire _T_428 = io_trigger_pkt_any_1_tdata2[19] == _T_284[19]; // @[el2_lib.scala 197:79] - wire _T_429 = _T_425 | _T_428; // @[el2_lib.scala 197:24] - wire _T_431 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 197:37] - wire _T_432 = _T_431 & _T_292; // @[el2_lib.scala 197:42] - wire _T_435 = io_trigger_pkt_any_1_tdata2[20] == _T_284[20]; // @[el2_lib.scala 197:79] - wire _T_436 = _T_432 | _T_435; // @[el2_lib.scala 197:24] - wire _T_438 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 197:37] - wire _T_439 = _T_438 & _T_292; // @[el2_lib.scala 197:42] - wire _T_442 = io_trigger_pkt_any_1_tdata2[21] == _T_284[21]; // @[el2_lib.scala 197:79] - wire _T_443 = _T_439 | _T_442; // @[el2_lib.scala 197:24] - wire _T_445 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 197:37] - wire _T_446 = _T_445 & _T_292; // @[el2_lib.scala 197:42] - wire _T_449 = io_trigger_pkt_any_1_tdata2[22] == _T_284[22]; // @[el2_lib.scala 197:79] - wire _T_450 = _T_446 | _T_449; // @[el2_lib.scala 197:24] - wire _T_452 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 197:37] - wire _T_453 = _T_452 & _T_292; // @[el2_lib.scala 197:42] - wire _T_456 = io_trigger_pkt_any_1_tdata2[23] == _T_284[23]; // @[el2_lib.scala 197:79] - wire _T_457 = _T_453 | _T_456; // @[el2_lib.scala 197:24] - wire _T_459 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 197:37] - wire _T_460 = _T_459 & _T_292; // @[el2_lib.scala 197:42] - wire _T_463 = io_trigger_pkt_any_1_tdata2[24] == _T_284[24]; // @[el2_lib.scala 197:79] - wire _T_464 = _T_460 | _T_463; // @[el2_lib.scala 197:24] - wire _T_466 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 197:37] - wire _T_467 = _T_466 & _T_292; // @[el2_lib.scala 197:42] - wire _T_470 = io_trigger_pkt_any_1_tdata2[25] == _T_284[25]; // @[el2_lib.scala 197:79] - wire _T_471 = _T_467 | _T_470; // @[el2_lib.scala 197:24] - wire _T_473 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 197:37] - wire _T_474 = _T_473 & _T_292; // @[el2_lib.scala 197:42] - wire _T_477 = io_trigger_pkt_any_1_tdata2[26] == _T_284[26]; // @[el2_lib.scala 197:79] - wire _T_478 = _T_474 | _T_477; // @[el2_lib.scala 197:24] - wire _T_480 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 197:37] - wire _T_481 = _T_480 & _T_292; // @[el2_lib.scala 197:42] - wire _T_484 = io_trigger_pkt_any_1_tdata2[27] == _T_284[27]; // @[el2_lib.scala 197:79] - wire _T_485 = _T_481 | _T_484; // @[el2_lib.scala 197:24] - wire _T_487 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 197:37] - wire _T_488 = _T_487 & _T_292; // @[el2_lib.scala 197:42] - wire _T_491 = io_trigger_pkt_any_1_tdata2[28] == _T_284[28]; // @[el2_lib.scala 197:79] - wire _T_492 = _T_488 | _T_491; // @[el2_lib.scala 197:24] - wire _T_494 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 197:37] - wire _T_495 = _T_494 & _T_292; // @[el2_lib.scala 197:42] - wire _T_498 = io_trigger_pkt_any_1_tdata2[29] == _T_284[29]; // @[el2_lib.scala 197:79] - wire _T_499 = _T_495 | _T_498; // @[el2_lib.scala 197:24] - wire _T_501 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 197:37] - wire _T_502 = _T_501 & _T_292; // @[el2_lib.scala 197:42] - wire _T_505 = io_trigger_pkt_any_1_tdata2[30] == _T_284[30]; // @[el2_lib.scala 197:79] - wire _T_506 = _T_502 | _T_505; // @[el2_lib.scala 197:24] - wire _T_508 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 197:37] - wire _T_509 = _T_508 & _T_292; // @[el2_lib.scala 197:42] - wire _T_512 = io_trigger_pkt_any_1_tdata2[31] == _T_284[31]; // @[el2_lib.scala 197:79] - wire _T_513 = _T_509 | _T_512; // @[el2_lib.scala 197:24] - wire [7:0] _T_520 = {_T_345,_T_338,_T_331,_T_324,_T_317,_T_310,_T_303,_T_296}; // @[el2_lib.scala 198:14] - wire [15:0] _T_528 = {_T_401,_T_394,_T_387,_T_380,_T_373,_T_366,_T_359,_T_352,_T_520}; // @[el2_lib.scala 198:14] - wire [7:0] _T_535 = {_T_457,_T_450,_T_443,_T_436,_T_429,_T_422,_T_415,_T_408}; // @[el2_lib.scala 198:14] - wire [31:0] _T_544 = {_T_513,_T_506,_T_499,_T_492,_T_485,_T_478,_T_471,_T_464,_T_535,_T_528}; // @[el2_lib.scala 198:14] - wire lsu_trigger_data_match_1 = &_T_544; // @[el2_lib.scala 198:21] - wire _T_546 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 24:107] - wire _T_547 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[el2_lsu_trigger.scala 25:35] - wire [31:0] _T_549 = _T_546 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_550 = _T_547 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_551 = _T_549 | _T_550; // @[Mux.scala 27:72] - wire _T_557 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 194:73] - wire _T_558 = ~_T_557; // @[el2_lib.scala 194:47] - wire _T_559 = io_trigger_pkt_any_2_match_ & _T_558; // @[el2_lib.scala 194:44] - wire _T_562 = io_trigger_pkt_any_2_tdata2[0] == _T_551[0]; // @[el2_lib.scala 195:52] - wire _T_563 = _T_559 | _T_562; // @[el2_lib.scala 195:41] - wire _T_565 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 197:37] - wire _T_566 = _T_565 & _T_559; // @[el2_lib.scala 197:42] - wire _T_569 = io_trigger_pkt_any_2_tdata2[1] == _T_551[1]; // @[el2_lib.scala 197:79] - wire _T_570 = _T_566 | _T_569; // @[el2_lib.scala 197:24] - wire _T_572 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 197:37] - wire _T_573 = _T_572 & _T_559; // @[el2_lib.scala 197:42] - wire _T_576 = io_trigger_pkt_any_2_tdata2[2] == _T_551[2]; // @[el2_lib.scala 197:79] - wire _T_577 = _T_573 | _T_576; // @[el2_lib.scala 197:24] - wire _T_579 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 197:37] - wire _T_580 = _T_579 & _T_559; // @[el2_lib.scala 197:42] - wire _T_583 = io_trigger_pkt_any_2_tdata2[3] == _T_551[3]; // @[el2_lib.scala 197:79] - wire _T_584 = _T_580 | _T_583; // @[el2_lib.scala 197:24] - wire _T_586 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 197:37] - wire _T_587 = _T_586 & _T_559; // @[el2_lib.scala 197:42] - wire _T_590 = io_trigger_pkt_any_2_tdata2[4] == _T_551[4]; // @[el2_lib.scala 197:79] - wire _T_591 = _T_587 | _T_590; // @[el2_lib.scala 197:24] - wire _T_593 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 197:37] - wire _T_594 = _T_593 & _T_559; // @[el2_lib.scala 197:42] - wire _T_597 = io_trigger_pkt_any_2_tdata2[5] == _T_551[5]; // @[el2_lib.scala 197:79] - wire _T_598 = _T_594 | _T_597; // @[el2_lib.scala 197:24] - wire _T_600 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 197:37] - wire _T_601 = _T_600 & _T_559; // @[el2_lib.scala 197:42] - wire _T_604 = io_trigger_pkt_any_2_tdata2[6] == _T_551[6]; // @[el2_lib.scala 197:79] - wire _T_605 = _T_601 | _T_604; // @[el2_lib.scala 197:24] - wire _T_607 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 197:37] - wire _T_608 = _T_607 & _T_559; // @[el2_lib.scala 197:42] - wire _T_611 = io_trigger_pkt_any_2_tdata2[7] == _T_551[7]; // @[el2_lib.scala 197:79] - wire _T_612 = _T_608 | _T_611; // @[el2_lib.scala 197:24] - wire _T_614 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 197:37] - wire _T_615 = _T_614 & _T_559; // @[el2_lib.scala 197:42] - wire _T_618 = io_trigger_pkt_any_2_tdata2[8] == _T_551[8]; // @[el2_lib.scala 197:79] - wire _T_619 = _T_615 | _T_618; // @[el2_lib.scala 197:24] - wire _T_621 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 197:37] - wire _T_622 = _T_621 & _T_559; // @[el2_lib.scala 197:42] - wire _T_625 = io_trigger_pkt_any_2_tdata2[9] == _T_551[9]; // @[el2_lib.scala 197:79] - wire _T_626 = _T_622 | _T_625; // @[el2_lib.scala 197:24] - wire _T_628 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 197:37] - wire _T_629 = _T_628 & _T_559; // @[el2_lib.scala 197:42] - wire _T_632 = io_trigger_pkt_any_2_tdata2[10] == _T_551[10]; // @[el2_lib.scala 197:79] - wire _T_633 = _T_629 | _T_632; // @[el2_lib.scala 197:24] - wire _T_635 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 197:37] - wire _T_636 = _T_635 & _T_559; // @[el2_lib.scala 197:42] - wire _T_639 = io_trigger_pkt_any_2_tdata2[11] == _T_551[11]; // @[el2_lib.scala 197:79] - wire _T_640 = _T_636 | _T_639; // @[el2_lib.scala 197:24] - wire _T_642 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 197:37] - wire _T_643 = _T_642 & _T_559; // @[el2_lib.scala 197:42] - wire _T_646 = io_trigger_pkt_any_2_tdata2[12] == _T_551[12]; // @[el2_lib.scala 197:79] - wire _T_647 = _T_643 | _T_646; // @[el2_lib.scala 197:24] - wire _T_649 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 197:37] - wire _T_650 = _T_649 & _T_559; // @[el2_lib.scala 197:42] - wire _T_653 = io_trigger_pkt_any_2_tdata2[13] == _T_551[13]; // @[el2_lib.scala 197:79] - wire _T_654 = _T_650 | _T_653; // @[el2_lib.scala 197:24] - wire _T_656 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 197:37] - wire _T_657 = _T_656 & _T_559; // @[el2_lib.scala 197:42] - wire _T_660 = io_trigger_pkt_any_2_tdata2[14] == _T_551[14]; // @[el2_lib.scala 197:79] - wire _T_661 = _T_657 | _T_660; // @[el2_lib.scala 197:24] - wire _T_663 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 197:37] - wire _T_664 = _T_663 & _T_559; // @[el2_lib.scala 197:42] - wire _T_667 = io_trigger_pkt_any_2_tdata2[15] == _T_551[15]; // @[el2_lib.scala 197:79] - wire _T_668 = _T_664 | _T_667; // @[el2_lib.scala 197:24] - wire _T_670 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 197:37] - wire _T_671 = _T_670 & _T_559; // @[el2_lib.scala 197:42] - wire _T_674 = io_trigger_pkt_any_2_tdata2[16] == _T_551[16]; // @[el2_lib.scala 197:79] - wire _T_675 = _T_671 | _T_674; // @[el2_lib.scala 197:24] - wire _T_677 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 197:37] - wire _T_678 = _T_677 & _T_559; // @[el2_lib.scala 197:42] - wire _T_681 = io_trigger_pkt_any_2_tdata2[17] == _T_551[17]; // @[el2_lib.scala 197:79] - wire _T_682 = _T_678 | _T_681; // @[el2_lib.scala 197:24] - wire _T_684 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 197:37] - wire _T_685 = _T_684 & _T_559; // @[el2_lib.scala 197:42] - wire _T_688 = io_trigger_pkt_any_2_tdata2[18] == _T_551[18]; // @[el2_lib.scala 197:79] - wire _T_689 = _T_685 | _T_688; // @[el2_lib.scala 197:24] - wire _T_691 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 197:37] - wire _T_692 = _T_691 & _T_559; // @[el2_lib.scala 197:42] - wire _T_695 = io_trigger_pkt_any_2_tdata2[19] == _T_551[19]; // @[el2_lib.scala 197:79] - wire _T_696 = _T_692 | _T_695; // @[el2_lib.scala 197:24] - wire _T_698 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 197:37] - wire _T_699 = _T_698 & _T_559; // @[el2_lib.scala 197:42] - wire _T_702 = io_trigger_pkt_any_2_tdata2[20] == _T_551[20]; // @[el2_lib.scala 197:79] - wire _T_703 = _T_699 | _T_702; // @[el2_lib.scala 197:24] - wire _T_705 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 197:37] - wire _T_706 = _T_705 & _T_559; // @[el2_lib.scala 197:42] - wire _T_709 = io_trigger_pkt_any_2_tdata2[21] == _T_551[21]; // @[el2_lib.scala 197:79] - wire _T_710 = _T_706 | _T_709; // @[el2_lib.scala 197:24] - wire _T_712 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 197:37] - wire _T_713 = _T_712 & _T_559; // @[el2_lib.scala 197:42] - wire _T_716 = io_trigger_pkt_any_2_tdata2[22] == _T_551[22]; // @[el2_lib.scala 197:79] - wire _T_717 = _T_713 | _T_716; // @[el2_lib.scala 197:24] - wire _T_719 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 197:37] - wire _T_720 = _T_719 & _T_559; // @[el2_lib.scala 197:42] - wire _T_723 = io_trigger_pkt_any_2_tdata2[23] == _T_551[23]; // @[el2_lib.scala 197:79] - wire _T_724 = _T_720 | _T_723; // @[el2_lib.scala 197:24] - wire _T_726 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 197:37] - wire _T_727 = _T_726 & _T_559; // @[el2_lib.scala 197:42] - wire _T_730 = io_trigger_pkt_any_2_tdata2[24] == _T_551[24]; // @[el2_lib.scala 197:79] - wire _T_731 = _T_727 | _T_730; // @[el2_lib.scala 197:24] - wire _T_733 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 197:37] - wire _T_734 = _T_733 & _T_559; // @[el2_lib.scala 197:42] - wire _T_737 = io_trigger_pkt_any_2_tdata2[25] == _T_551[25]; // @[el2_lib.scala 197:79] - wire _T_738 = _T_734 | _T_737; // @[el2_lib.scala 197:24] - wire _T_740 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 197:37] - wire _T_741 = _T_740 & _T_559; // @[el2_lib.scala 197:42] - wire _T_744 = io_trigger_pkt_any_2_tdata2[26] == _T_551[26]; // @[el2_lib.scala 197:79] - wire _T_745 = _T_741 | _T_744; // @[el2_lib.scala 197:24] - wire _T_747 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 197:37] - wire _T_748 = _T_747 & _T_559; // @[el2_lib.scala 197:42] - wire _T_751 = io_trigger_pkt_any_2_tdata2[27] == _T_551[27]; // @[el2_lib.scala 197:79] - wire _T_752 = _T_748 | _T_751; // @[el2_lib.scala 197:24] - wire _T_754 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 197:37] - wire _T_755 = _T_754 & _T_559; // @[el2_lib.scala 197:42] - wire _T_758 = io_trigger_pkt_any_2_tdata2[28] == _T_551[28]; // @[el2_lib.scala 197:79] - wire _T_759 = _T_755 | _T_758; // @[el2_lib.scala 197:24] - wire _T_761 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 197:37] - wire _T_762 = _T_761 & _T_559; // @[el2_lib.scala 197:42] - wire _T_765 = io_trigger_pkt_any_2_tdata2[29] == _T_551[29]; // @[el2_lib.scala 197:79] - wire _T_766 = _T_762 | _T_765; // @[el2_lib.scala 197:24] - wire _T_768 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 197:37] - wire _T_769 = _T_768 & _T_559; // @[el2_lib.scala 197:42] - wire _T_772 = io_trigger_pkt_any_2_tdata2[30] == _T_551[30]; // @[el2_lib.scala 197:79] - wire _T_773 = _T_769 | _T_772; // @[el2_lib.scala 197:24] - wire _T_775 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 197:37] - wire _T_776 = _T_775 & _T_559; // @[el2_lib.scala 197:42] - wire _T_779 = io_trigger_pkt_any_2_tdata2[31] == _T_551[31]; // @[el2_lib.scala 197:79] - wire _T_780 = _T_776 | _T_779; // @[el2_lib.scala 197:24] - wire [7:0] _T_787 = {_T_612,_T_605,_T_598,_T_591,_T_584,_T_577,_T_570,_T_563}; // @[el2_lib.scala 198:14] - wire [15:0] _T_795 = {_T_668,_T_661,_T_654,_T_647,_T_640,_T_633,_T_626,_T_619,_T_787}; // @[el2_lib.scala 198:14] - wire [7:0] _T_802 = {_T_724,_T_717,_T_710,_T_703,_T_696,_T_689,_T_682,_T_675}; // @[el2_lib.scala 198:14] - wire [31:0] _T_811 = {_T_780,_T_773,_T_766,_T_759,_T_752,_T_745,_T_738,_T_731,_T_802,_T_795}; // @[el2_lib.scala 198:14] - wire lsu_trigger_data_match_2 = &_T_811; // @[el2_lib.scala 198:21] - wire _T_813 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 24:107] - wire _T_814 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[el2_lsu_trigger.scala 25:35] - wire [31:0] _T_816 = _T_813 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_817 = _T_814 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_818 = _T_816 | _T_817; // @[Mux.scala 27:72] - wire _T_824 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 194:73] - wire _T_825 = ~_T_824; // @[el2_lib.scala 194:47] - wire _T_826 = io_trigger_pkt_any_3_match_ & _T_825; // @[el2_lib.scala 194:44] - wire _T_829 = io_trigger_pkt_any_3_tdata2[0] == _T_818[0]; // @[el2_lib.scala 195:52] - wire _T_830 = _T_826 | _T_829; // @[el2_lib.scala 195:41] - wire _T_832 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 197:37] - wire _T_833 = _T_832 & _T_826; // @[el2_lib.scala 197:42] - wire _T_836 = io_trigger_pkt_any_3_tdata2[1] == _T_818[1]; // @[el2_lib.scala 197:79] - wire _T_837 = _T_833 | _T_836; // @[el2_lib.scala 197:24] - wire _T_839 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 197:37] - wire _T_840 = _T_839 & _T_826; // @[el2_lib.scala 197:42] - wire _T_843 = io_trigger_pkt_any_3_tdata2[2] == _T_818[2]; // @[el2_lib.scala 197:79] - wire _T_844 = _T_840 | _T_843; // @[el2_lib.scala 197:24] - wire _T_846 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 197:37] - wire _T_847 = _T_846 & _T_826; // @[el2_lib.scala 197:42] - wire _T_850 = io_trigger_pkt_any_3_tdata2[3] == _T_818[3]; // @[el2_lib.scala 197:79] - wire _T_851 = _T_847 | _T_850; // @[el2_lib.scala 197:24] - wire _T_853 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 197:37] - wire _T_854 = _T_853 & _T_826; // @[el2_lib.scala 197:42] - wire _T_857 = io_trigger_pkt_any_3_tdata2[4] == _T_818[4]; // @[el2_lib.scala 197:79] - wire _T_858 = _T_854 | _T_857; // @[el2_lib.scala 197:24] - wire _T_860 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 197:37] - wire _T_861 = _T_860 & _T_826; // @[el2_lib.scala 197:42] - wire _T_864 = io_trigger_pkt_any_3_tdata2[5] == _T_818[5]; // @[el2_lib.scala 197:79] - wire _T_865 = _T_861 | _T_864; // @[el2_lib.scala 197:24] - wire _T_867 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 197:37] - wire _T_868 = _T_867 & _T_826; // @[el2_lib.scala 197:42] - wire _T_871 = io_trigger_pkt_any_3_tdata2[6] == _T_818[6]; // @[el2_lib.scala 197:79] - wire _T_872 = _T_868 | _T_871; // @[el2_lib.scala 197:24] - wire _T_874 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 197:37] - wire _T_875 = _T_874 & _T_826; // @[el2_lib.scala 197:42] - wire _T_878 = io_trigger_pkt_any_3_tdata2[7] == _T_818[7]; // @[el2_lib.scala 197:79] - wire _T_879 = _T_875 | _T_878; // @[el2_lib.scala 197:24] - wire _T_881 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 197:37] - wire _T_882 = _T_881 & _T_826; // @[el2_lib.scala 197:42] - wire _T_885 = io_trigger_pkt_any_3_tdata2[8] == _T_818[8]; // @[el2_lib.scala 197:79] - wire _T_886 = _T_882 | _T_885; // @[el2_lib.scala 197:24] - wire _T_888 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 197:37] - wire _T_889 = _T_888 & _T_826; // @[el2_lib.scala 197:42] - wire _T_892 = io_trigger_pkt_any_3_tdata2[9] == _T_818[9]; // @[el2_lib.scala 197:79] - wire _T_893 = _T_889 | _T_892; // @[el2_lib.scala 197:24] - wire _T_895 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 197:37] - wire _T_896 = _T_895 & _T_826; // @[el2_lib.scala 197:42] - wire _T_899 = io_trigger_pkt_any_3_tdata2[10] == _T_818[10]; // @[el2_lib.scala 197:79] - wire _T_900 = _T_896 | _T_899; // @[el2_lib.scala 197:24] - wire _T_902 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 197:37] - wire _T_903 = _T_902 & _T_826; // @[el2_lib.scala 197:42] - wire _T_906 = io_trigger_pkt_any_3_tdata2[11] == _T_818[11]; // @[el2_lib.scala 197:79] - wire _T_907 = _T_903 | _T_906; // @[el2_lib.scala 197:24] - wire _T_909 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 197:37] - wire _T_910 = _T_909 & _T_826; // @[el2_lib.scala 197:42] - wire _T_913 = io_trigger_pkt_any_3_tdata2[12] == _T_818[12]; // @[el2_lib.scala 197:79] - wire _T_914 = _T_910 | _T_913; // @[el2_lib.scala 197:24] - wire _T_916 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 197:37] - wire _T_917 = _T_916 & _T_826; // @[el2_lib.scala 197:42] - wire _T_920 = io_trigger_pkt_any_3_tdata2[13] == _T_818[13]; // @[el2_lib.scala 197:79] - wire _T_921 = _T_917 | _T_920; // @[el2_lib.scala 197:24] - wire _T_923 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 197:37] - wire _T_924 = _T_923 & _T_826; // @[el2_lib.scala 197:42] - wire _T_927 = io_trigger_pkt_any_3_tdata2[14] == _T_818[14]; // @[el2_lib.scala 197:79] - wire _T_928 = _T_924 | _T_927; // @[el2_lib.scala 197:24] - wire _T_930 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 197:37] - wire _T_931 = _T_930 & _T_826; // @[el2_lib.scala 197:42] - wire _T_934 = io_trigger_pkt_any_3_tdata2[15] == _T_818[15]; // @[el2_lib.scala 197:79] - wire _T_935 = _T_931 | _T_934; // @[el2_lib.scala 197:24] - wire _T_937 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 197:37] - wire _T_938 = _T_937 & _T_826; // @[el2_lib.scala 197:42] - wire _T_941 = io_trigger_pkt_any_3_tdata2[16] == _T_818[16]; // @[el2_lib.scala 197:79] - wire _T_942 = _T_938 | _T_941; // @[el2_lib.scala 197:24] - wire _T_944 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 197:37] - wire _T_945 = _T_944 & _T_826; // @[el2_lib.scala 197:42] - wire _T_948 = io_trigger_pkt_any_3_tdata2[17] == _T_818[17]; // @[el2_lib.scala 197:79] - wire _T_949 = _T_945 | _T_948; // @[el2_lib.scala 197:24] - wire _T_951 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 197:37] - wire _T_952 = _T_951 & _T_826; // @[el2_lib.scala 197:42] - wire _T_955 = io_trigger_pkt_any_3_tdata2[18] == _T_818[18]; // @[el2_lib.scala 197:79] - wire _T_956 = _T_952 | _T_955; // @[el2_lib.scala 197:24] - wire _T_958 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 197:37] - wire _T_959 = _T_958 & _T_826; // @[el2_lib.scala 197:42] - wire _T_962 = io_trigger_pkt_any_3_tdata2[19] == _T_818[19]; // @[el2_lib.scala 197:79] - wire _T_963 = _T_959 | _T_962; // @[el2_lib.scala 197:24] - wire _T_965 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 197:37] - wire _T_966 = _T_965 & _T_826; // @[el2_lib.scala 197:42] - wire _T_969 = io_trigger_pkt_any_3_tdata2[20] == _T_818[20]; // @[el2_lib.scala 197:79] - wire _T_970 = _T_966 | _T_969; // @[el2_lib.scala 197:24] - wire _T_972 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 197:37] - wire _T_973 = _T_972 & _T_826; // @[el2_lib.scala 197:42] - wire _T_976 = io_trigger_pkt_any_3_tdata2[21] == _T_818[21]; // @[el2_lib.scala 197:79] - wire _T_977 = _T_973 | _T_976; // @[el2_lib.scala 197:24] - wire _T_979 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 197:37] - wire _T_980 = _T_979 & _T_826; // @[el2_lib.scala 197:42] - wire _T_983 = io_trigger_pkt_any_3_tdata2[22] == _T_818[22]; // @[el2_lib.scala 197:79] - wire _T_984 = _T_980 | _T_983; // @[el2_lib.scala 197:24] - wire _T_986 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 197:37] - wire _T_987 = _T_986 & _T_826; // @[el2_lib.scala 197:42] - wire _T_990 = io_trigger_pkt_any_3_tdata2[23] == _T_818[23]; // @[el2_lib.scala 197:79] - wire _T_991 = _T_987 | _T_990; // @[el2_lib.scala 197:24] - wire _T_993 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 197:37] - wire _T_994 = _T_993 & _T_826; // @[el2_lib.scala 197:42] - wire _T_997 = io_trigger_pkt_any_3_tdata2[24] == _T_818[24]; // @[el2_lib.scala 197:79] - wire _T_998 = _T_994 | _T_997; // @[el2_lib.scala 197:24] - wire _T_1000 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 197:37] - wire _T_1001 = _T_1000 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1004 = io_trigger_pkt_any_3_tdata2[25] == _T_818[25]; // @[el2_lib.scala 197:79] - wire _T_1005 = _T_1001 | _T_1004; // @[el2_lib.scala 197:24] - wire _T_1007 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 197:37] - wire _T_1008 = _T_1007 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1011 = io_trigger_pkt_any_3_tdata2[26] == _T_818[26]; // @[el2_lib.scala 197:79] - wire _T_1012 = _T_1008 | _T_1011; // @[el2_lib.scala 197:24] - wire _T_1014 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 197:37] - wire _T_1015 = _T_1014 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1018 = io_trigger_pkt_any_3_tdata2[27] == _T_818[27]; // @[el2_lib.scala 197:79] - wire _T_1019 = _T_1015 | _T_1018; // @[el2_lib.scala 197:24] - wire _T_1021 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 197:37] - wire _T_1022 = _T_1021 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1025 = io_trigger_pkt_any_3_tdata2[28] == _T_818[28]; // @[el2_lib.scala 197:79] - wire _T_1026 = _T_1022 | _T_1025; // @[el2_lib.scala 197:24] - wire _T_1028 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 197:37] - wire _T_1029 = _T_1028 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1032 = io_trigger_pkt_any_3_tdata2[29] == _T_818[29]; // @[el2_lib.scala 197:79] - wire _T_1033 = _T_1029 | _T_1032; // @[el2_lib.scala 197:24] - wire _T_1035 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 197:37] - wire _T_1036 = _T_1035 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1039 = io_trigger_pkt_any_3_tdata2[30] == _T_818[30]; // @[el2_lib.scala 197:79] - wire _T_1040 = _T_1036 | _T_1039; // @[el2_lib.scala 197:24] - wire _T_1042 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 197:37] - wire _T_1043 = _T_1042 & _T_826; // @[el2_lib.scala 197:42] - wire _T_1046 = io_trigger_pkt_any_3_tdata2[31] == _T_818[31]; // @[el2_lib.scala 197:79] - wire _T_1047 = _T_1043 | _T_1046; // @[el2_lib.scala 197:24] - wire [7:0] _T_1054 = {_T_879,_T_872,_T_865,_T_858,_T_851,_T_844,_T_837,_T_830}; // @[el2_lib.scala 198:14] - wire [15:0] _T_1062 = {_T_935,_T_928,_T_921,_T_914,_T_907,_T_900,_T_893,_T_886,_T_1054}; // @[el2_lib.scala 198:14] - wire [7:0] _T_1069 = {_T_991,_T_984,_T_977,_T_970,_T_963,_T_956,_T_949,_T_942}; // @[el2_lib.scala 198:14] - wire [31:0] _T_1078 = {_T_1047,_T_1040,_T_1033,_T_1026,_T_1019,_T_1012,_T_1005,_T_998,_T_1069,_T_1062}; // @[el2_lib.scala 198:14] - wire lsu_trigger_data_match_3 = &_T_1078; // @[el2_lib.scala 198:21] - wire _T_1079 = ~io_lsu_pkt_m_dma; // @[el2_lsu_trigger.scala 26:74] - wire _T_1080 = io_lsu_pkt_m_valid & _T_1079; // @[el2_lsu_trigger.scala 26:72] - wire _T_1081 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 26:123] - wire _T_1082 = _T_1080 & _T_1081; // @[el2_lsu_trigger.scala 26:92] - wire _T_1083 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 27:33] - wire _T_1085 = _T_1083 & _T_12; // @[el2_lsu_trigger.scala 27:53] - wire _T_1086 = _T_1085 & lsu_trigger_data_match_0; // @[el2_lsu_trigger.scala 27:85] - wire _T_1087 = _T_1082 | _T_1086; // @[el2_lsu_trigger.scala 26:144] - wire _T_1090 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 26:123] - wire _T_1091 = _T_1080 & _T_1090; // @[el2_lsu_trigger.scala 26:92] - wire _T_1092 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 27:33] - wire _T_1094 = _T_1092 & _T_279; // @[el2_lsu_trigger.scala 27:53] - wire _T_1095 = _T_1094 & lsu_trigger_data_match_1; // @[el2_lsu_trigger.scala 27:85] - wire _T_1096 = _T_1091 | _T_1095; // @[el2_lsu_trigger.scala 26:144] - wire _T_1099 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 26:123] - wire _T_1100 = _T_1080 & _T_1099; // @[el2_lsu_trigger.scala 26:92] - wire _T_1101 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 27:33] - wire _T_1103 = _T_1101 & _T_546; // @[el2_lsu_trigger.scala 27:53] - wire _T_1104 = _T_1103 & lsu_trigger_data_match_2; // @[el2_lsu_trigger.scala 27:85] - wire _T_1105 = _T_1100 | _T_1104; // @[el2_lsu_trigger.scala 26:144] - wire _T_1108 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 26:123] - wire _T_1109 = _T_1080 & _T_1108; // @[el2_lsu_trigger.scala 26:92] - wire _T_1110 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 27:33] - wire _T_1112 = _T_1110 & _T_813; // @[el2_lsu_trigger.scala 27:53] - wire _T_1113 = _T_1112 & lsu_trigger_data_match_3; // @[el2_lsu_trigger.scala 27:85] - wire _T_1114 = _T_1109 | _T_1113; // @[el2_lsu_trigger.scala 26:144] - wire [2:0] _T_1117 = {_T_1114,_T_1105,_T_1096}; // @[Cat.scala 29:58] - assign io_lsu_trigger_match_m = {_T_1117,_T_1087}; // @[el2_lsu_trigger.scala 15:25 el2_lsu_trigger.scala 26:26] + wire [31:0] lsu_match_data_0 = _T_15 | _T_16; // @[Mux.scala 27:72] + wire _T_19 = ~io_trigger_pkt_any_1_select; // @[el2_lsu_trigger.scala 17:53] + wire _T_20 = io_trigger_pkt_any_1_select & io_trigger_pkt_any_1_store; // @[el2_lsu_trigger.scala 17:136] + wire [31:0] _T_22 = _T_19 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_23 = _T_20 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_1 = _T_22 | _T_23; // @[Mux.scala 27:72] + wire _T_26 = ~io_trigger_pkt_any_2_select; // @[el2_lsu_trigger.scala 17:53] + wire _T_27 = io_trigger_pkt_any_2_select & io_trigger_pkt_any_2_store; // @[el2_lsu_trigger.scala 17:136] + wire [31:0] _T_29 = _T_26 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_30 = _T_27 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_2 = _T_29 | _T_30; // @[Mux.scala 27:72] + wire _T_33 = ~io_trigger_pkt_any_3_select; // @[el2_lsu_trigger.scala 17:53] + wire _T_34 = io_trigger_pkt_any_3_select & io_trigger_pkt_any_3_store; // @[el2_lsu_trigger.scala 17:136] + wire [31:0] _T_36 = _T_33 ? io_lsu_addr_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_37 = _T_34 ? store_data_trigger_m : 32'h0; // @[Mux.scala 27:72] + wire [31:0] lsu_match_data_3 = _T_36 | _T_37; // @[Mux.scala 27:72] + wire _T_39 = ~io_lsu_pkt_m_dma; // @[el2_lsu_trigger.scala 18:71] + wire _T_40 = io_lsu_pkt_m_valid & _T_39; // @[el2_lsu_trigger.scala 18:69] + wire _T_41 = io_trigger_pkt_any_0_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] + wire _T_42 = io_trigger_pkt_any_0_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_44 = _T_42 & _T_12; // @[el2_lsu_trigger.scala 19:53] + wire _T_45 = _T_41 | _T_44; // @[el2_lsu_trigger.scala 18:142] + wire _T_46 = _T_40 & _T_45; // @[el2_lsu_trigger.scala 18:89] + wire _T_49 = &io_trigger_pkt_any_0_tdata2; // @[el2_lib.scala 241:45] + wire _T_50 = ~_T_49; // @[el2_lib.scala 241:39] + wire _T_51 = io_trigger_pkt_any_0_match_ & _T_50; // @[el2_lib.scala 241:37] + wire _T_54 = io_trigger_pkt_any_0_tdata2[0] == lsu_match_data_0[0]; // @[el2_lib.scala 242:52] + wire _T_55 = _T_51 | _T_54; // @[el2_lib.scala 242:41] + wire _T_57 = &io_trigger_pkt_any_0_tdata2[0]; // @[el2_lib.scala 244:38] + wire _T_58 = _T_57 & _T_51; // @[el2_lib.scala 244:43] + wire _T_61 = io_trigger_pkt_any_0_tdata2[1] == lsu_match_data_0[1]; // @[el2_lib.scala 244:80] + wire _T_62 = _T_58 | _T_61; // @[el2_lib.scala 244:25] + wire _T_64 = &io_trigger_pkt_any_0_tdata2[1:0]; // @[el2_lib.scala 244:38] + wire _T_65 = _T_64 & _T_51; // @[el2_lib.scala 244:43] + wire _T_68 = io_trigger_pkt_any_0_tdata2[2] == lsu_match_data_0[2]; // @[el2_lib.scala 244:80] + wire _T_69 = _T_65 | _T_68; // @[el2_lib.scala 244:25] + wire _T_71 = &io_trigger_pkt_any_0_tdata2[2:0]; // @[el2_lib.scala 244:38] + wire _T_72 = _T_71 & _T_51; // @[el2_lib.scala 244:43] + wire _T_75 = io_trigger_pkt_any_0_tdata2[3] == lsu_match_data_0[3]; // @[el2_lib.scala 244:80] + wire _T_76 = _T_72 | _T_75; // @[el2_lib.scala 244:25] + wire _T_78 = &io_trigger_pkt_any_0_tdata2[3:0]; // @[el2_lib.scala 244:38] + wire _T_79 = _T_78 & _T_51; // @[el2_lib.scala 244:43] + wire _T_82 = io_trigger_pkt_any_0_tdata2[4] == lsu_match_data_0[4]; // @[el2_lib.scala 244:80] + wire _T_83 = _T_79 | _T_82; // @[el2_lib.scala 244:25] + wire _T_85 = &io_trigger_pkt_any_0_tdata2[4:0]; // @[el2_lib.scala 244:38] + wire _T_86 = _T_85 & _T_51; // @[el2_lib.scala 244:43] + wire _T_89 = io_trigger_pkt_any_0_tdata2[5] == lsu_match_data_0[5]; // @[el2_lib.scala 244:80] + wire _T_90 = _T_86 | _T_89; // @[el2_lib.scala 244:25] + wire _T_92 = &io_trigger_pkt_any_0_tdata2[5:0]; // @[el2_lib.scala 244:38] + wire _T_93 = _T_92 & _T_51; // @[el2_lib.scala 244:43] + wire _T_96 = io_trigger_pkt_any_0_tdata2[6] == lsu_match_data_0[6]; // @[el2_lib.scala 244:80] + wire _T_97 = _T_93 | _T_96; // @[el2_lib.scala 244:25] + wire _T_99 = &io_trigger_pkt_any_0_tdata2[6:0]; // @[el2_lib.scala 244:38] + wire _T_100 = _T_99 & _T_51; // @[el2_lib.scala 244:43] + wire _T_103 = io_trigger_pkt_any_0_tdata2[7] == lsu_match_data_0[7]; // @[el2_lib.scala 244:80] + wire _T_104 = _T_100 | _T_103; // @[el2_lib.scala 244:25] + wire _T_106 = &io_trigger_pkt_any_0_tdata2[7:0]; // @[el2_lib.scala 244:38] + wire _T_107 = _T_106 & _T_51; // @[el2_lib.scala 244:43] + wire _T_110 = io_trigger_pkt_any_0_tdata2[8] == lsu_match_data_0[8]; // @[el2_lib.scala 244:80] + wire _T_111 = _T_107 | _T_110; // @[el2_lib.scala 244:25] + wire _T_113 = &io_trigger_pkt_any_0_tdata2[8:0]; // @[el2_lib.scala 244:38] + wire _T_114 = _T_113 & _T_51; // @[el2_lib.scala 244:43] + wire _T_117 = io_trigger_pkt_any_0_tdata2[9] == lsu_match_data_0[9]; // @[el2_lib.scala 244:80] + wire _T_118 = _T_114 | _T_117; // @[el2_lib.scala 244:25] + wire _T_120 = &io_trigger_pkt_any_0_tdata2[9:0]; // @[el2_lib.scala 244:38] + wire _T_121 = _T_120 & _T_51; // @[el2_lib.scala 244:43] + wire _T_124 = io_trigger_pkt_any_0_tdata2[10] == lsu_match_data_0[10]; // @[el2_lib.scala 244:80] + wire _T_125 = _T_121 | _T_124; // @[el2_lib.scala 244:25] + wire _T_127 = &io_trigger_pkt_any_0_tdata2[10:0]; // @[el2_lib.scala 244:38] + wire _T_128 = _T_127 & _T_51; // @[el2_lib.scala 244:43] + wire _T_131 = io_trigger_pkt_any_0_tdata2[11] == lsu_match_data_0[11]; // @[el2_lib.scala 244:80] + wire _T_132 = _T_128 | _T_131; // @[el2_lib.scala 244:25] + wire _T_134 = &io_trigger_pkt_any_0_tdata2[11:0]; // @[el2_lib.scala 244:38] + wire _T_135 = _T_134 & _T_51; // @[el2_lib.scala 244:43] + wire _T_138 = io_trigger_pkt_any_0_tdata2[12] == lsu_match_data_0[12]; // @[el2_lib.scala 244:80] + wire _T_139 = _T_135 | _T_138; // @[el2_lib.scala 244:25] + wire _T_141 = &io_trigger_pkt_any_0_tdata2[12:0]; // @[el2_lib.scala 244:38] + wire _T_142 = _T_141 & _T_51; // @[el2_lib.scala 244:43] + wire _T_145 = io_trigger_pkt_any_0_tdata2[13] == lsu_match_data_0[13]; // @[el2_lib.scala 244:80] + wire _T_146 = _T_142 | _T_145; // @[el2_lib.scala 244:25] + wire _T_148 = &io_trigger_pkt_any_0_tdata2[13:0]; // @[el2_lib.scala 244:38] + wire _T_149 = _T_148 & _T_51; // @[el2_lib.scala 244:43] + wire _T_152 = io_trigger_pkt_any_0_tdata2[14] == lsu_match_data_0[14]; // @[el2_lib.scala 244:80] + wire _T_153 = _T_149 | _T_152; // @[el2_lib.scala 244:25] + wire _T_155 = &io_trigger_pkt_any_0_tdata2[14:0]; // @[el2_lib.scala 244:38] + wire _T_156 = _T_155 & _T_51; // @[el2_lib.scala 244:43] + wire _T_159 = io_trigger_pkt_any_0_tdata2[15] == lsu_match_data_0[15]; // @[el2_lib.scala 244:80] + wire _T_160 = _T_156 | _T_159; // @[el2_lib.scala 244:25] + wire _T_162 = &io_trigger_pkt_any_0_tdata2[15:0]; // @[el2_lib.scala 244:38] + wire _T_163 = _T_162 & _T_51; // @[el2_lib.scala 244:43] + wire _T_166 = io_trigger_pkt_any_0_tdata2[16] == lsu_match_data_0[16]; // @[el2_lib.scala 244:80] + wire _T_167 = _T_163 | _T_166; // @[el2_lib.scala 244:25] + wire _T_169 = &io_trigger_pkt_any_0_tdata2[16:0]; // @[el2_lib.scala 244:38] + wire _T_170 = _T_169 & _T_51; // @[el2_lib.scala 244:43] + wire _T_173 = io_trigger_pkt_any_0_tdata2[17] == lsu_match_data_0[17]; // @[el2_lib.scala 244:80] + wire _T_174 = _T_170 | _T_173; // @[el2_lib.scala 244:25] + wire _T_176 = &io_trigger_pkt_any_0_tdata2[17:0]; // @[el2_lib.scala 244:38] + wire _T_177 = _T_176 & _T_51; // @[el2_lib.scala 244:43] + wire _T_180 = io_trigger_pkt_any_0_tdata2[18] == lsu_match_data_0[18]; // @[el2_lib.scala 244:80] + wire _T_181 = _T_177 | _T_180; // @[el2_lib.scala 244:25] + wire _T_183 = &io_trigger_pkt_any_0_tdata2[18:0]; // @[el2_lib.scala 244:38] + wire _T_184 = _T_183 & _T_51; // @[el2_lib.scala 244:43] + wire _T_187 = io_trigger_pkt_any_0_tdata2[19] == lsu_match_data_0[19]; // @[el2_lib.scala 244:80] + wire _T_188 = _T_184 | _T_187; // @[el2_lib.scala 244:25] + wire _T_190 = &io_trigger_pkt_any_0_tdata2[19:0]; // @[el2_lib.scala 244:38] + wire _T_191 = _T_190 & _T_51; // @[el2_lib.scala 244:43] + wire _T_194 = io_trigger_pkt_any_0_tdata2[20] == lsu_match_data_0[20]; // @[el2_lib.scala 244:80] + wire _T_195 = _T_191 | _T_194; // @[el2_lib.scala 244:25] + wire _T_197 = &io_trigger_pkt_any_0_tdata2[20:0]; // @[el2_lib.scala 244:38] + wire _T_198 = _T_197 & _T_51; // @[el2_lib.scala 244:43] + wire _T_201 = io_trigger_pkt_any_0_tdata2[21] == lsu_match_data_0[21]; // @[el2_lib.scala 244:80] + wire _T_202 = _T_198 | _T_201; // @[el2_lib.scala 244:25] + wire _T_204 = &io_trigger_pkt_any_0_tdata2[21:0]; // @[el2_lib.scala 244:38] + wire _T_205 = _T_204 & _T_51; // @[el2_lib.scala 244:43] + wire _T_208 = io_trigger_pkt_any_0_tdata2[22] == lsu_match_data_0[22]; // @[el2_lib.scala 244:80] + wire _T_209 = _T_205 | _T_208; // @[el2_lib.scala 244:25] + wire _T_211 = &io_trigger_pkt_any_0_tdata2[22:0]; // @[el2_lib.scala 244:38] + wire _T_212 = _T_211 & _T_51; // @[el2_lib.scala 244:43] + wire _T_215 = io_trigger_pkt_any_0_tdata2[23] == lsu_match_data_0[23]; // @[el2_lib.scala 244:80] + wire _T_216 = _T_212 | _T_215; // @[el2_lib.scala 244:25] + wire _T_218 = &io_trigger_pkt_any_0_tdata2[23:0]; // @[el2_lib.scala 244:38] + wire _T_219 = _T_218 & _T_51; // @[el2_lib.scala 244:43] + wire _T_222 = io_trigger_pkt_any_0_tdata2[24] == lsu_match_data_0[24]; // @[el2_lib.scala 244:80] + wire _T_223 = _T_219 | _T_222; // @[el2_lib.scala 244:25] + wire _T_225 = &io_trigger_pkt_any_0_tdata2[24:0]; // @[el2_lib.scala 244:38] + wire _T_226 = _T_225 & _T_51; // @[el2_lib.scala 244:43] + wire _T_229 = io_trigger_pkt_any_0_tdata2[25] == lsu_match_data_0[25]; // @[el2_lib.scala 244:80] + wire _T_230 = _T_226 | _T_229; // @[el2_lib.scala 244:25] + wire _T_232 = &io_trigger_pkt_any_0_tdata2[25:0]; // @[el2_lib.scala 244:38] + wire _T_233 = _T_232 & _T_51; // @[el2_lib.scala 244:43] + wire _T_236 = io_trigger_pkt_any_0_tdata2[26] == lsu_match_data_0[26]; // @[el2_lib.scala 244:80] + wire _T_237 = _T_233 | _T_236; // @[el2_lib.scala 244:25] + wire _T_239 = &io_trigger_pkt_any_0_tdata2[26:0]; // @[el2_lib.scala 244:38] + wire _T_240 = _T_239 & _T_51; // @[el2_lib.scala 244:43] + wire _T_243 = io_trigger_pkt_any_0_tdata2[27] == lsu_match_data_0[27]; // @[el2_lib.scala 244:80] + wire _T_244 = _T_240 | _T_243; // @[el2_lib.scala 244:25] + wire _T_246 = &io_trigger_pkt_any_0_tdata2[27:0]; // @[el2_lib.scala 244:38] + wire _T_247 = _T_246 & _T_51; // @[el2_lib.scala 244:43] + wire _T_250 = io_trigger_pkt_any_0_tdata2[28] == lsu_match_data_0[28]; // @[el2_lib.scala 244:80] + wire _T_251 = _T_247 | _T_250; // @[el2_lib.scala 244:25] + wire _T_253 = &io_trigger_pkt_any_0_tdata2[28:0]; // @[el2_lib.scala 244:38] + wire _T_254 = _T_253 & _T_51; // @[el2_lib.scala 244:43] + wire _T_257 = io_trigger_pkt_any_0_tdata2[29] == lsu_match_data_0[29]; // @[el2_lib.scala 244:80] + wire _T_258 = _T_254 | _T_257; // @[el2_lib.scala 244:25] + wire _T_260 = &io_trigger_pkt_any_0_tdata2[29:0]; // @[el2_lib.scala 244:38] + wire _T_261 = _T_260 & _T_51; // @[el2_lib.scala 244:43] + wire _T_264 = io_trigger_pkt_any_0_tdata2[30] == lsu_match_data_0[30]; // @[el2_lib.scala 244:80] + wire _T_265 = _T_261 | _T_264; // @[el2_lib.scala 244:25] + wire _T_267 = &io_trigger_pkt_any_0_tdata2[30:0]; // @[el2_lib.scala 244:38] + wire _T_268 = _T_267 & _T_51; // @[el2_lib.scala 244:43] + wire _T_271 = io_trigger_pkt_any_0_tdata2[31] == lsu_match_data_0[31]; // @[el2_lib.scala 244:80] + wire _T_272 = _T_268 | _T_271; // @[el2_lib.scala 244:25] + wire [7:0] _T_279 = {_T_104,_T_97,_T_90,_T_83,_T_76,_T_69,_T_62,_T_55}; // @[el2_lib.scala 245:14] + wire [15:0] _T_287 = {_T_160,_T_153,_T_146,_T_139,_T_132,_T_125,_T_118,_T_111,_T_279}; // @[el2_lib.scala 245:14] + wire [7:0] _T_294 = {_T_216,_T_209,_T_202,_T_195,_T_188,_T_181,_T_174,_T_167}; // @[el2_lib.scala 245:14] + wire [31:0] _T_303 = {_T_272,_T_265,_T_258,_T_251,_T_244,_T_237,_T_230,_T_223,_T_294,_T_287}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_0 = {{31'd0}, _T_46}; // @[el2_lsu_trigger.scala 19:87] + wire [31:0] _T_304 = _GEN_0 & _T_303; // @[el2_lsu_trigger.scala 19:87] + wire _T_307 = io_trigger_pkt_any_1_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] + wire _T_308 = io_trigger_pkt_any_1_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_310 = _T_308 & _T_19; // @[el2_lsu_trigger.scala 19:53] + wire _T_311 = _T_307 | _T_310; // @[el2_lsu_trigger.scala 18:142] + wire _T_312 = _T_40 & _T_311; // @[el2_lsu_trigger.scala 18:89] + wire _T_315 = &io_trigger_pkt_any_1_tdata2; // @[el2_lib.scala 241:45] + wire _T_316 = ~_T_315; // @[el2_lib.scala 241:39] + wire _T_317 = io_trigger_pkt_any_1_match_ & _T_316; // @[el2_lib.scala 241:37] + wire _T_320 = io_trigger_pkt_any_1_tdata2[0] == lsu_match_data_1[0]; // @[el2_lib.scala 242:52] + wire _T_321 = _T_317 | _T_320; // @[el2_lib.scala 242:41] + wire _T_323 = &io_trigger_pkt_any_1_tdata2[0]; // @[el2_lib.scala 244:38] + wire _T_324 = _T_323 & _T_317; // @[el2_lib.scala 244:43] + wire _T_327 = io_trigger_pkt_any_1_tdata2[1] == lsu_match_data_1[1]; // @[el2_lib.scala 244:80] + wire _T_328 = _T_324 | _T_327; // @[el2_lib.scala 244:25] + wire _T_330 = &io_trigger_pkt_any_1_tdata2[1:0]; // @[el2_lib.scala 244:38] + wire _T_331 = _T_330 & _T_317; // @[el2_lib.scala 244:43] + wire _T_334 = io_trigger_pkt_any_1_tdata2[2] == lsu_match_data_1[2]; // @[el2_lib.scala 244:80] + wire _T_335 = _T_331 | _T_334; // @[el2_lib.scala 244:25] + wire _T_337 = &io_trigger_pkt_any_1_tdata2[2:0]; // @[el2_lib.scala 244:38] + wire _T_338 = _T_337 & _T_317; // @[el2_lib.scala 244:43] + wire _T_341 = io_trigger_pkt_any_1_tdata2[3] == lsu_match_data_1[3]; // @[el2_lib.scala 244:80] + wire _T_342 = _T_338 | _T_341; // @[el2_lib.scala 244:25] + wire _T_344 = &io_trigger_pkt_any_1_tdata2[3:0]; // @[el2_lib.scala 244:38] + wire _T_345 = _T_344 & _T_317; // @[el2_lib.scala 244:43] + wire _T_348 = io_trigger_pkt_any_1_tdata2[4] == lsu_match_data_1[4]; // @[el2_lib.scala 244:80] + wire _T_349 = _T_345 | _T_348; // @[el2_lib.scala 244:25] + wire _T_351 = &io_trigger_pkt_any_1_tdata2[4:0]; // @[el2_lib.scala 244:38] + wire _T_352 = _T_351 & _T_317; // @[el2_lib.scala 244:43] + wire _T_355 = io_trigger_pkt_any_1_tdata2[5] == lsu_match_data_1[5]; // @[el2_lib.scala 244:80] + wire _T_356 = _T_352 | _T_355; // @[el2_lib.scala 244:25] + wire _T_358 = &io_trigger_pkt_any_1_tdata2[5:0]; // @[el2_lib.scala 244:38] + wire _T_359 = _T_358 & _T_317; // @[el2_lib.scala 244:43] + wire _T_362 = io_trigger_pkt_any_1_tdata2[6] == lsu_match_data_1[6]; // @[el2_lib.scala 244:80] + wire _T_363 = _T_359 | _T_362; // @[el2_lib.scala 244:25] + wire _T_365 = &io_trigger_pkt_any_1_tdata2[6:0]; // @[el2_lib.scala 244:38] + wire _T_366 = _T_365 & _T_317; // @[el2_lib.scala 244:43] + wire _T_369 = io_trigger_pkt_any_1_tdata2[7] == lsu_match_data_1[7]; // @[el2_lib.scala 244:80] + wire _T_370 = _T_366 | _T_369; // @[el2_lib.scala 244:25] + wire _T_372 = &io_trigger_pkt_any_1_tdata2[7:0]; // @[el2_lib.scala 244:38] + wire _T_373 = _T_372 & _T_317; // @[el2_lib.scala 244:43] + wire _T_376 = io_trigger_pkt_any_1_tdata2[8] == lsu_match_data_1[8]; // @[el2_lib.scala 244:80] + wire _T_377 = _T_373 | _T_376; // @[el2_lib.scala 244:25] + wire _T_379 = &io_trigger_pkt_any_1_tdata2[8:0]; // @[el2_lib.scala 244:38] + wire _T_380 = _T_379 & _T_317; // @[el2_lib.scala 244:43] + wire _T_383 = io_trigger_pkt_any_1_tdata2[9] == lsu_match_data_1[9]; // @[el2_lib.scala 244:80] + wire _T_384 = _T_380 | _T_383; // @[el2_lib.scala 244:25] + wire _T_386 = &io_trigger_pkt_any_1_tdata2[9:0]; // @[el2_lib.scala 244:38] + wire _T_387 = _T_386 & _T_317; // @[el2_lib.scala 244:43] + wire _T_390 = io_trigger_pkt_any_1_tdata2[10] == lsu_match_data_1[10]; // @[el2_lib.scala 244:80] + wire _T_391 = _T_387 | _T_390; // @[el2_lib.scala 244:25] + wire _T_393 = &io_trigger_pkt_any_1_tdata2[10:0]; // @[el2_lib.scala 244:38] + wire _T_394 = _T_393 & _T_317; // @[el2_lib.scala 244:43] + wire _T_397 = io_trigger_pkt_any_1_tdata2[11] == lsu_match_data_1[11]; // @[el2_lib.scala 244:80] + wire _T_398 = _T_394 | _T_397; // @[el2_lib.scala 244:25] + wire _T_400 = &io_trigger_pkt_any_1_tdata2[11:0]; // @[el2_lib.scala 244:38] + wire _T_401 = _T_400 & _T_317; // @[el2_lib.scala 244:43] + wire _T_404 = io_trigger_pkt_any_1_tdata2[12] == lsu_match_data_1[12]; // @[el2_lib.scala 244:80] + wire _T_405 = _T_401 | _T_404; // @[el2_lib.scala 244:25] + wire _T_407 = &io_trigger_pkt_any_1_tdata2[12:0]; // @[el2_lib.scala 244:38] + wire _T_408 = _T_407 & _T_317; // @[el2_lib.scala 244:43] + wire _T_411 = io_trigger_pkt_any_1_tdata2[13] == lsu_match_data_1[13]; // @[el2_lib.scala 244:80] + wire _T_412 = _T_408 | _T_411; // @[el2_lib.scala 244:25] + wire _T_414 = &io_trigger_pkt_any_1_tdata2[13:0]; // @[el2_lib.scala 244:38] + wire _T_415 = _T_414 & _T_317; // @[el2_lib.scala 244:43] + wire _T_418 = io_trigger_pkt_any_1_tdata2[14] == lsu_match_data_1[14]; // @[el2_lib.scala 244:80] + wire _T_419 = _T_415 | _T_418; // @[el2_lib.scala 244:25] + wire _T_421 = &io_trigger_pkt_any_1_tdata2[14:0]; // @[el2_lib.scala 244:38] + wire _T_422 = _T_421 & _T_317; // @[el2_lib.scala 244:43] + wire _T_425 = io_trigger_pkt_any_1_tdata2[15] == lsu_match_data_1[15]; // @[el2_lib.scala 244:80] + wire _T_426 = _T_422 | _T_425; // @[el2_lib.scala 244:25] + wire _T_428 = &io_trigger_pkt_any_1_tdata2[15:0]; // @[el2_lib.scala 244:38] + wire _T_429 = _T_428 & _T_317; // @[el2_lib.scala 244:43] + wire _T_432 = io_trigger_pkt_any_1_tdata2[16] == lsu_match_data_1[16]; // @[el2_lib.scala 244:80] + wire _T_433 = _T_429 | _T_432; // @[el2_lib.scala 244:25] + wire _T_435 = &io_trigger_pkt_any_1_tdata2[16:0]; // @[el2_lib.scala 244:38] + wire _T_436 = _T_435 & _T_317; // @[el2_lib.scala 244:43] + wire _T_439 = io_trigger_pkt_any_1_tdata2[17] == lsu_match_data_1[17]; // @[el2_lib.scala 244:80] + wire _T_440 = _T_436 | _T_439; // @[el2_lib.scala 244:25] + wire _T_442 = &io_trigger_pkt_any_1_tdata2[17:0]; // @[el2_lib.scala 244:38] + wire _T_443 = _T_442 & _T_317; // @[el2_lib.scala 244:43] + wire _T_446 = io_trigger_pkt_any_1_tdata2[18] == lsu_match_data_1[18]; // @[el2_lib.scala 244:80] + wire _T_447 = _T_443 | _T_446; // @[el2_lib.scala 244:25] + wire _T_449 = &io_trigger_pkt_any_1_tdata2[18:0]; // @[el2_lib.scala 244:38] + wire _T_450 = _T_449 & _T_317; // @[el2_lib.scala 244:43] + wire _T_453 = io_trigger_pkt_any_1_tdata2[19] == lsu_match_data_1[19]; // @[el2_lib.scala 244:80] + wire _T_454 = _T_450 | _T_453; // @[el2_lib.scala 244:25] + wire _T_456 = &io_trigger_pkt_any_1_tdata2[19:0]; // @[el2_lib.scala 244:38] + wire _T_457 = _T_456 & _T_317; // @[el2_lib.scala 244:43] + wire _T_460 = io_trigger_pkt_any_1_tdata2[20] == lsu_match_data_1[20]; // @[el2_lib.scala 244:80] + wire _T_461 = _T_457 | _T_460; // @[el2_lib.scala 244:25] + wire _T_463 = &io_trigger_pkt_any_1_tdata2[20:0]; // @[el2_lib.scala 244:38] + wire _T_464 = _T_463 & _T_317; // @[el2_lib.scala 244:43] + wire _T_467 = io_trigger_pkt_any_1_tdata2[21] == lsu_match_data_1[21]; // @[el2_lib.scala 244:80] + wire _T_468 = _T_464 | _T_467; // @[el2_lib.scala 244:25] + wire _T_470 = &io_trigger_pkt_any_1_tdata2[21:0]; // @[el2_lib.scala 244:38] + wire _T_471 = _T_470 & _T_317; // @[el2_lib.scala 244:43] + wire _T_474 = io_trigger_pkt_any_1_tdata2[22] == lsu_match_data_1[22]; // @[el2_lib.scala 244:80] + wire _T_475 = _T_471 | _T_474; // @[el2_lib.scala 244:25] + wire _T_477 = &io_trigger_pkt_any_1_tdata2[22:0]; // @[el2_lib.scala 244:38] + wire _T_478 = _T_477 & _T_317; // @[el2_lib.scala 244:43] + wire _T_481 = io_trigger_pkt_any_1_tdata2[23] == lsu_match_data_1[23]; // @[el2_lib.scala 244:80] + wire _T_482 = _T_478 | _T_481; // @[el2_lib.scala 244:25] + wire _T_484 = &io_trigger_pkt_any_1_tdata2[23:0]; // @[el2_lib.scala 244:38] + wire _T_485 = _T_484 & _T_317; // @[el2_lib.scala 244:43] + wire _T_488 = io_trigger_pkt_any_1_tdata2[24] == lsu_match_data_1[24]; // @[el2_lib.scala 244:80] + wire _T_489 = _T_485 | _T_488; // @[el2_lib.scala 244:25] + wire _T_491 = &io_trigger_pkt_any_1_tdata2[24:0]; // @[el2_lib.scala 244:38] + wire _T_492 = _T_491 & _T_317; // @[el2_lib.scala 244:43] + wire _T_495 = io_trigger_pkt_any_1_tdata2[25] == lsu_match_data_1[25]; // @[el2_lib.scala 244:80] + wire _T_496 = _T_492 | _T_495; // @[el2_lib.scala 244:25] + wire _T_498 = &io_trigger_pkt_any_1_tdata2[25:0]; // @[el2_lib.scala 244:38] + wire _T_499 = _T_498 & _T_317; // @[el2_lib.scala 244:43] + wire _T_502 = io_trigger_pkt_any_1_tdata2[26] == lsu_match_data_1[26]; // @[el2_lib.scala 244:80] + wire _T_503 = _T_499 | _T_502; // @[el2_lib.scala 244:25] + wire _T_505 = &io_trigger_pkt_any_1_tdata2[26:0]; // @[el2_lib.scala 244:38] + wire _T_506 = _T_505 & _T_317; // @[el2_lib.scala 244:43] + wire _T_509 = io_trigger_pkt_any_1_tdata2[27] == lsu_match_data_1[27]; // @[el2_lib.scala 244:80] + wire _T_510 = _T_506 | _T_509; // @[el2_lib.scala 244:25] + wire _T_512 = &io_trigger_pkt_any_1_tdata2[27:0]; // @[el2_lib.scala 244:38] + wire _T_513 = _T_512 & _T_317; // @[el2_lib.scala 244:43] + wire _T_516 = io_trigger_pkt_any_1_tdata2[28] == lsu_match_data_1[28]; // @[el2_lib.scala 244:80] + wire _T_517 = _T_513 | _T_516; // @[el2_lib.scala 244:25] + wire _T_519 = &io_trigger_pkt_any_1_tdata2[28:0]; // @[el2_lib.scala 244:38] + wire _T_520 = _T_519 & _T_317; // @[el2_lib.scala 244:43] + wire _T_523 = io_trigger_pkt_any_1_tdata2[29] == lsu_match_data_1[29]; // @[el2_lib.scala 244:80] + wire _T_524 = _T_520 | _T_523; // @[el2_lib.scala 244:25] + wire _T_526 = &io_trigger_pkt_any_1_tdata2[29:0]; // @[el2_lib.scala 244:38] + wire _T_527 = _T_526 & _T_317; // @[el2_lib.scala 244:43] + wire _T_530 = io_trigger_pkt_any_1_tdata2[30] == lsu_match_data_1[30]; // @[el2_lib.scala 244:80] + wire _T_531 = _T_527 | _T_530; // @[el2_lib.scala 244:25] + wire _T_533 = &io_trigger_pkt_any_1_tdata2[30:0]; // @[el2_lib.scala 244:38] + wire _T_534 = _T_533 & _T_317; // @[el2_lib.scala 244:43] + wire _T_537 = io_trigger_pkt_any_1_tdata2[31] == lsu_match_data_1[31]; // @[el2_lib.scala 244:80] + wire _T_538 = _T_534 | _T_537; // @[el2_lib.scala 244:25] + wire [7:0] _T_545 = {_T_370,_T_363,_T_356,_T_349,_T_342,_T_335,_T_328,_T_321}; // @[el2_lib.scala 245:14] + wire [15:0] _T_553 = {_T_426,_T_419,_T_412,_T_405,_T_398,_T_391,_T_384,_T_377,_T_545}; // @[el2_lib.scala 245:14] + wire [7:0] _T_560 = {_T_482,_T_475,_T_468,_T_461,_T_454,_T_447,_T_440,_T_433}; // @[el2_lib.scala 245:14] + wire [31:0] _T_569 = {_T_538,_T_531,_T_524,_T_517,_T_510,_T_503,_T_496,_T_489,_T_560,_T_553}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_1 = {{31'd0}, _T_312}; // @[el2_lsu_trigger.scala 19:87] + wire [31:0] _T_570 = _GEN_1 & _T_569; // @[el2_lsu_trigger.scala 19:87] + wire _T_573 = io_trigger_pkt_any_2_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] + wire _T_574 = io_trigger_pkt_any_2_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_576 = _T_574 & _T_26; // @[el2_lsu_trigger.scala 19:53] + wire _T_577 = _T_573 | _T_576; // @[el2_lsu_trigger.scala 18:142] + wire _T_578 = _T_40 & _T_577; // @[el2_lsu_trigger.scala 18:89] + wire _T_581 = &io_trigger_pkt_any_2_tdata2; // @[el2_lib.scala 241:45] + wire _T_582 = ~_T_581; // @[el2_lib.scala 241:39] + wire _T_583 = io_trigger_pkt_any_2_match_ & _T_582; // @[el2_lib.scala 241:37] + wire _T_586 = io_trigger_pkt_any_2_tdata2[0] == lsu_match_data_2[0]; // @[el2_lib.scala 242:52] + wire _T_587 = _T_583 | _T_586; // @[el2_lib.scala 242:41] + wire _T_589 = &io_trigger_pkt_any_2_tdata2[0]; // @[el2_lib.scala 244:38] + wire _T_590 = _T_589 & _T_583; // @[el2_lib.scala 244:43] + wire _T_593 = io_trigger_pkt_any_2_tdata2[1] == lsu_match_data_2[1]; // @[el2_lib.scala 244:80] + wire _T_594 = _T_590 | _T_593; // @[el2_lib.scala 244:25] + wire _T_596 = &io_trigger_pkt_any_2_tdata2[1:0]; // @[el2_lib.scala 244:38] + wire _T_597 = _T_596 & _T_583; // @[el2_lib.scala 244:43] + wire _T_600 = io_trigger_pkt_any_2_tdata2[2] == lsu_match_data_2[2]; // @[el2_lib.scala 244:80] + wire _T_601 = _T_597 | _T_600; // @[el2_lib.scala 244:25] + wire _T_603 = &io_trigger_pkt_any_2_tdata2[2:0]; // @[el2_lib.scala 244:38] + wire _T_604 = _T_603 & _T_583; // @[el2_lib.scala 244:43] + wire _T_607 = io_trigger_pkt_any_2_tdata2[3] == lsu_match_data_2[3]; // @[el2_lib.scala 244:80] + wire _T_608 = _T_604 | _T_607; // @[el2_lib.scala 244:25] + wire _T_610 = &io_trigger_pkt_any_2_tdata2[3:0]; // @[el2_lib.scala 244:38] + wire _T_611 = _T_610 & _T_583; // @[el2_lib.scala 244:43] + wire _T_614 = io_trigger_pkt_any_2_tdata2[4] == lsu_match_data_2[4]; // @[el2_lib.scala 244:80] + wire _T_615 = _T_611 | _T_614; // @[el2_lib.scala 244:25] + wire _T_617 = &io_trigger_pkt_any_2_tdata2[4:0]; // @[el2_lib.scala 244:38] + wire _T_618 = _T_617 & _T_583; // @[el2_lib.scala 244:43] + wire _T_621 = io_trigger_pkt_any_2_tdata2[5] == lsu_match_data_2[5]; // @[el2_lib.scala 244:80] + wire _T_622 = _T_618 | _T_621; // @[el2_lib.scala 244:25] + wire _T_624 = &io_trigger_pkt_any_2_tdata2[5:0]; // @[el2_lib.scala 244:38] + wire _T_625 = _T_624 & _T_583; // @[el2_lib.scala 244:43] + wire _T_628 = io_trigger_pkt_any_2_tdata2[6] == lsu_match_data_2[6]; // @[el2_lib.scala 244:80] + wire _T_629 = _T_625 | _T_628; // @[el2_lib.scala 244:25] + wire _T_631 = &io_trigger_pkt_any_2_tdata2[6:0]; // @[el2_lib.scala 244:38] + wire _T_632 = _T_631 & _T_583; // @[el2_lib.scala 244:43] + wire _T_635 = io_trigger_pkt_any_2_tdata2[7] == lsu_match_data_2[7]; // @[el2_lib.scala 244:80] + wire _T_636 = _T_632 | _T_635; // @[el2_lib.scala 244:25] + wire _T_638 = &io_trigger_pkt_any_2_tdata2[7:0]; // @[el2_lib.scala 244:38] + wire _T_639 = _T_638 & _T_583; // @[el2_lib.scala 244:43] + wire _T_642 = io_trigger_pkt_any_2_tdata2[8] == lsu_match_data_2[8]; // @[el2_lib.scala 244:80] + wire _T_643 = _T_639 | _T_642; // @[el2_lib.scala 244:25] + wire _T_645 = &io_trigger_pkt_any_2_tdata2[8:0]; // @[el2_lib.scala 244:38] + wire _T_646 = _T_645 & _T_583; // @[el2_lib.scala 244:43] + wire _T_649 = io_trigger_pkt_any_2_tdata2[9] == lsu_match_data_2[9]; // @[el2_lib.scala 244:80] + wire _T_650 = _T_646 | _T_649; // @[el2_lib.scala 244:25] + wire _T_652 = &io_trigger_pkt_any_2_tdata2[9:0]; // @[el2_lib.scala 244:38] + wire _T_653 = _T_652 & _T_583; // @[el2_lib.scala 244:43] + wire _T_656 = io_trigger_pkt_any_2_tdata2[10] == lsu_match_data_2[10]; // @[el2_lib.scala 244:80] + wire _T_657 = _T_653 | _T_656; // @[el2_lib.scala 244:25] + wire _T_659 = &io_trigger_pkt_any_2_tdata2[10:0]; // @[el2_lib.scala 244:38] + wire _T_660 = _T_659 & _T_583; // @[el2_lib.scala 244:43] + wire _T_663 = io_trigger_pkt_any_2_tdata2[11] == lsu_match_data_2[11]; // @[el2_lib.scala 244:80] + wire _T_664 = _T_660 | _T_663; // @[el2_lib.scala 244:25] + wire _T_666 = &io_trigger_pkt_any_2_tdata2[11:0]; // @[el2_lib.scala 244:38] + wire _T_667 = _T_666 & _T_583; // @[el2_lib.scala 244:43] + wire _T_670 = io_trigger_pkt_any_2_tdata2[12] == lsu_match_data_2[12]; // @[el2_lib.scala 244:80] + wire _T_671 = _T_667 | _T_670; // @[el2_lib.scala 244:25] + wire _T_673 = &io_trigger_pkt_any_2_tdata2[12:0]; // @[el2_lib.scala 244:38] + wire _T_674 = _T_673 & _T_583; // @[el2_lib.scala 244:43] + wire _T_677 = io_trigger_pkt_any_2_tdata2[13] == lsu_match_data_2[13]; // @[el2_lib.scala 244:80] + wire _T_678 = _T_674 | _T_677; // @[el2_lib.scala 244:25] + wire _T_680 = &io_trigger_pkt_any_2_tdata2[13:0]; // @[el2_lib.scala 244:38] + wire _T_681 = _T_680 & _T_583; // @[el2_lib.scala 244:43] + wire _T_684 = io_trigger_pkt_any_2_tdata2[14] == lsu_match_data_2[14]; // @[el2_lib.scala 244:80] + wire _T_685 = _T_681 | _T_684; // @[el2_lib.scala 244:25] + wire _T_687 = &io_trigger_pkt_any_2_tdata2[14:0]; // @[el2_lib.scala 244:38] + wire _T_688 = _T_687 & _T_583; // @[el2_lib.scala 244:43] + wire _T_691 = io_trigger_pkt_any_2_tdata2[15] == lsu_match_data_2[15]; // @[el2_lib.scala 244:80] + wire _T_692 = _T_688 | _T_691; // @[el2_lib.scala 244:25] + wire _T_694 = &io_trigger_pkt_any_2_tdata2[15:0]; // @[el2_lib.scala 244:38] + wire _T_695 = _T_694 & _T_583; // @[el2_lib.scala 244:43] + wire _T_698 = io_trigger_pkt_any_2_tdata2[16] == lsu_match_data_2[16]; // @[el2_lib.scala 244:80] + wire _T_699 = _T_695 | _T_698; // @[el2_lib.scala 244:25] + wire _T_701 = &io_trigger_pkt_any_2_tdata2[16:0]; // @[el2_lib.scala 244:38] + wire _T_702 = _T_701 & _T_583; // @[el2_lib.scala 244:43] + wire _T_705 = io_trigger_pkt_any_2_tdata2[17] == lsu_match_data_2[17]; // @[el2_lib.scala 244:80] + wire _T_706 = _T_702 | _T_705; // @[el2_lib.scala 244:25] + wire _T_708 = &io_trigger_pkt_any_2_tdata2[17:0]; // @[el2_lib.scala 244:38] + wire _T_709 = _T_708 & _T_583; // @[el2_lib.scala 244:43] + wire _T_712 = io_trigger_pkt_any_2_tdata2[18] == lsu_match_data_2[18]; // @[el2_lib.scala 244:80] + wire _T_713 = _T_709 | _T_712; // @[el2_lib.scala 244:25] + wire _T_715 = &io_trigger_pkt_any_2_tdata2[18:0]; // @[el2_lib.scala 244:38] + wire _T_716 = _T_715 & _T_583; // @[el2_lib.scala 244:43] + wire _T_719 = io_trigger_pkt_any_2_tdata2[19] == lsu_match_data_2[19]; // @[el2_lib.scala 244:80] + wire _T_720 = _T_716 | _T_719; // @[el2_lib.scala 244:25] + wire _T_722 = &io_trigger_pkt_any_2_tdata2[19:0]; // @[el2_lib.scala 244:38] + wire _T_723 = _T_722 & _T_583; // @[el2_lib.scala 244:43] + wire _T_726 = io_trigger_pkt_any_2_tdata2[20] == lsu_match_data_2[20]; // @[el2_lib.scala 244:80] + wire _T_727 = _T_723 | _T_726; // @[el2_lib.scala 244:25] + wire _T_729 = &io_trigger_pkt_any_2_tdata2[20:0]; // @[el2_lib.scala 244:38] + wire _T_730 = _T_729 & _T_583; // @[el2_lib.scala 244:43] + wire _T_733 = io_trigger_pkt_any_2_tdata2[21] == lsu_match_data_2[21]; // @[el2_lib.scala 244:80] + wire _T_734 = _T_730 | _T_733; // @[el2_lib.scala 244:25] + wire _T_736 = &io_trigger_pkt_any_2_tdata2[21:0]; // @[el2_lib.scala 244:38] + wire _T_737 = _T_736 & _T_583; // @[el2_lib.scala 244:43] + wire _T_740 = io_trigger_pkt_any_2_tdata2[22] == lsu_match_data_2[22]; // @[el2_lib.scala 244:80] + wire _T_741 = _T_737 | _T_740; // @[el2_lib.scala 244:25] + wire _T_743 = &io_trigger_pkt_any_2_tdata2[22:0]; // @[el2_lib.scala 244:38] + wire _T_744 = _T_743 & _T_583; // @[el2_lib.scala 244:43] + wire _T_747 = io_trigger_pkt_any_2_tdata2[23] == lsu_match_data_2[23]; // @[el2_lib.scala 244:80] + wire _T_748 = _T_744 | _T_747; // @[el2_lib.scala 244:25] + wire _T_750 = &io_trigger_pkt_any_2_tdata2[23:0]; // @[el2_lib.scala 244:38] + wire _T_751 = _T_750 & _T_583; // @[el2_lib.scala 244:43] + wire _T_754 = io_trigger_pkt_any_2_tdata2[24] == lsu_match_data_2[24]; // @[el2_lib.scala 244:80] + wire _T_755 = _T_751 | _T_754; // @[el2_lib.scala 244:25] + wire _T_757 = &io_trigger_pkt_any_2_tdata2[24:0]; // @[el2_lib.scala 244:38] + wire _T_758 = _T_757 & _T_583; // @[el2_lib.scala 244:43] + wire _T_761 = io_trigger_pkt_any_2_tdata2[25] == lsu_match_data_2[25]; // @[el2_lib.scala 244:80] + wire _T_762 = _T_758 | _T_761; // @[el2_lib.scala 244:25] + wire _T_764 = &io_trigger_pkt_any_2_tdata2[25:0]; // @[el2_lib.scala 244:38] + wire _T_765 = _T_764 & _T_583; // @[el2_lib.scala 244:43] + wire _T_768 = io_trigger_pkt_any_2_tdata2[26] == lsu_match_data_2[26]; // @[el2_lib.scala 244:80] + wire _T_769 = _T_765 | _T_768; // @[el2_lib.scala 244:25] + wire _T_771 = &io_trigger_pkt_any_2_tdata2[26:0]; // @[el2_lib.scala 244:38] + wire _T_772 = _T_771 & _T_583; // @[el2_lib.scala 244:43] + wire _T_775 = io_trigger_pkt_any_2_tdata2[27] == lsu_match_data_2[27]; // @[el2_lib.scala 244:80] + wire _T_776 = _T_772 | _T_775; // @[el2_lib.scala 244:25] + wire _T_778 = &io_trigger_pkt_any_2_tdata2[27:0]; // @[el2_lib.scala 244:38] + wire _T_779 = _T_778 & _T_583; // @[el2_lib.scala 244:43] + wire _T_782 = io_trigger_pkt_any_2_tdata2[28] == lsu_match_data_2[28]; // @[el2_lib.scala 244:80] + wire _T_783 = _T_779 | _T_782; // @[el2_lib.scala 244:25] + wire _T_785 = &io_trigger_pkt_any_2_tdata2[28:0]; // @[el2_lib.scala 244:38] + wire _T_786 = _T_785 & _T_583; // @[el2_lib.scala 244:43] + wire _T_789 = io_trigger_pkt_any_2_tdata2[29] == lsu_match_data_2[29]; // @[el2_lib.scala 244:80] + wire _T_790 = _T_786 | _T_789; // @[el2_lib.scala 244:25] + wire _T_792 = &io_trigger_pkt_any_2_tdata2[29:0]; // @[el2_lib.scala 244:38] + wire _T_793 = _T_792 & _T_583; // @[el2_lib.scala 244:43] + wire _T_796 = io_trigger_pkt_any_2_tdata2[30] == lsu_match_data_2[30]; // @[el2_lib.scala 244:80] + wire _T_797 = _T_793 | _T_796; // @[el2_lib.scala 244:25] + wire _T_799 = &io_trigger_pkt_any_2_tdata2[30:0]; // @[el2_lib.scala 244:38] + wire _T_800 = _T_799 & _T_583; // @[el2_lib.scala 244:43] + wire _T_803 = io_trigger_pkt_any_2_tdata2[31] == lsu_match_data_2[31]; // @[el2_lib.scala 244:80] + wire _T_804 = _T_800 | _T_803; // @[el2_lib.scala 244:25] + wire [7:0] _T_811 = {_T_636,_T_629,_T_622,_T_615,_T_608,_T_601,_T_594,_T_587}; // @[el2_lib.scala 245:14] + wire [15:0] _T_819 = {_T_692,_T_685,_T_678,_T_671,_T_664,_T_657,_T_650,_T_643,_T_811}; // @[el2_lib.scala 245:14] + wire [7:0] _T_826 = {_T_748,_T_741,_T_734,_T_727,_T_720,_T_713,_T_706,_T_699}; // @[el2_lib.scala 245:14] + wire [31:0] _T_835 = {_T_804,_T_797,_T_790,_T_783,_T_776,_T_769,_T_762,_T_755,_T_826,_T_819}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_2 = {{31'd0}, _T_578}; // @[el2_lsu_trigger.scala 19:87] + wire [31:0] _T_836 = _GEN_2 & _T_835; // @[el2_lsu_trigger.scala 19:87] + wire _T_839 = io_trigger_pkt_any_3_store & io_lsu_pkt_m_store; // @[el2_lsu_trigger.scala 18:121] + wire _T_840 = io_trigger_pkt_any_3_load & io_lsu_pkt_m_load; // @[el2_lsu_trigger.scala 19:33] + wire _T_842 = _T_840 & _T_33; // @[el2_lsu_trigger.scala 19:53] + wire _T_843 = _T_839 | _T_842; // @[el2_lsu_trigger.scala 18:142] + wire _T_844 = _T_40 & _T_843; // @[el2_lsu_trigger.scala 18:89] + wire _T_847 = &io_trigger_pkt_any_3_tdata2; // @[el2_lib.scala 241:45] + wire _T_848 = ~_T_847; // @[el2_lib.scala 241:39] + wire _T_849 = io_trigger_pkt_any_3_match_ & _T_848; // @[el2_lib.scala 241:37] + wire _T_852 = io_trigger_pkt_any_3_tdata2[0] == lsu_match_data_3[0]; // @[el2_lib.scala 242:52] + wire _T_853 = _T_849 | _T_852; // @[el2_lib.scala 242:41] + wire _T_855 = &io_trigger_pkt_any_3_tdata2[0]; // @[el2_lib.scala 244:38] + wire _T_856 = _T_855 & _T_849; // @[el2_lib.scala 244:43] + wire _T_859 = io_trigger_pkt_any_3_tdata2[1] == lsu_match_data_3[1]; // @[el2_lib.scala 244:80] + wire _T_860 = _T_856 | _T_859; // @[el2_lib.scala 244:25] + wire _T_862 = &io_trigger_pkt_any_3_tdata2[1:0]; // @[el2_lib.scala 244:38] + wire _T_863 = _T_862 & _T_849; // @[el2_lib.scala 244:43] + wire _T_866 = io_trigger_pkt_any_3_tdata2[2] == lsu_match_data_3[2]; // @[el2_lib.scala 244:80] + wire _T_867 = _T_863 | _T_866; // @[el2_lib.scala 244:25] + wire _T_869 = &io_trigger_pkt_any_3_tdata2[2:0]; // @[el2_lib.scala 244:38] + wire _T_870 = _T_869 & _T_849; // @[el2_lib.scala 244:43] + wire _T_873 = io_trigger_pkt_any_3_tdata2[3] == lsu_match_data_3[3]; // @[el2_lib.scala 244:80] + wire _T_874 = _T_870 | _T_873; // @[el2_lib.scala 244:25] + wire _T_876 = &io_trigger_pkt_any_3_tdata2[3:0]; // @[el2_lib.scala 244:38] + wire _T_877 = _T_876 & _T_849; // @[el2_lib.scala 244:43] + wire _T_880 = io_trigger_pkt_any_3_tdata2[4] == lsu_match_data_3[4]; // @[el2_lib.scala 244:80] + wire _T_881 = _T_877 | _T_880; // @[el2_lib.scala 244:25] + wire _T_883 = &io_trigger_pkt_any_3_tdata2[4:0]; // @[el2_lib.scala 244:38] + wire _T_884 = _T_883 & _T_849; // @[el2_lib.scala 244:43] + wire _T_887 = io_trigger_pkt_any_3_tdata2[5] == lsu_match_data_3[5]; // @[el2_lib.scala 244:80] + wire _T_888 = _T_884 | _T_887; // @[el2_lib.scala 244:25] + wire _T_890 = &io_trigger_pkt_any_3_tdata2[5:0]; // @[el2_lib.scala 244:38] + wire _T_891 = _T_890 & _T_849; // @[el2_lib.scala 244:43] + wire _T_894 = io_trigger_pkt_any_3_tdata2[6] == lsu_match_data_3[6]; // @[el2_lib.scala 244:80] + wire _T_895 = _T_891 | _T_894; // @[el2_lib.scala 244:25] + wire _T_897 = &io_trigger_pkt_any_3_tdata2[6:0]; // @[el2_lib.scala 244:38] + wire _T_898 = _T_897 & _T_849; // @[el2_lib.scala 244:43] + wire _T_901 = io_trigger_pkt_any_3_tdata2[7] == lsu_match_data_3[7]; // @[el2_lib.scala 244:80] + wire _T_902 = _T_898 | _T_901; // @[el2_lib.scala 244:25] + wire _T_904 = &io_trigger_pkt_any_3_tdata2[7:0]; // @[el2_lib.scala 244:38] + wire _T_905 = _T_904 & _T_849; // @[el2_lib.scala 244:43] + wire _T_908 = io_trigger_pkt_any_3_tdata2[8] == lsu_match_data_3[8]; // @[el2_lib.scala 244:80] + wire _T_909 = _T_905 | _T_908; // @[el2_lib.scala 244:25] + wire _T_911 = &io_trigger_pkt_any_3_tdata2[8:0]; // @[el2_lib.scala 244:38] + wire _T_912 = _T_911 & _T_849; // @[el2_lib.scala 244:43] + wire _T_915 = io_trigger_pkt_any_3_tdata2[9] == lsu_match_data_3[9]; // @[el2_lib.scala 244:80] + wire _T_916 = _T_912 | _T_915; // @[el2_lib.scala 244:25] + wire _T_918 = &io_trigger_pkt_any_3_tdata2[9:0]; // @[el2_lib.scala 244:38] + wire _T_919 = _T_918 & _T_849; // @[el2_lib.scala 244:43] + wire _T_922 = io_trigger_pkt_any_3_tdata2[10] == lsu_match_data_3[10]; // @[el2_lib.scala 244:80] + wire _T_923 = _T_919 | _T_922; // @[el2_lib.scala 244:25] + wire _T_925 = &io_trigger_pkt_any_3_tdata2[10:0]; // @[el2_lib.scala 244:38] + wire _T_926 = _T_925 & _T_849; // @[el2_lib.scala 244:43] + wire _T_929 = io_trigger_pkt_any_3_tdata2[11] == lsu_match_data_3[11]; // @[el2_lib.scala 244:80] + wire _T_930 = _T_926 | _T_929; // @[el2_lib.scala 244:25] + wire _T_932 = &io_trigger_pkt_any_3_tdata2[11:0]; // @[el2_lib.scala 244:38] + wire _T_933 = _T_932 & _T_849; // @[el2_lib.scala 244:43] + wire _T_936 = io_trigger_pkt_any_3_tdata2[12] == lsu_match_data_3[12]; // @[el2_lib.scala 244:80] + wire _T_937 = _T_933 | _T_936; // @[el2_lib.scala 244:25] + wire _T_939 = &io_trigger_pkt_any_3_tdata2[12:0]; // @[el2_lib.scala 244:38] + wire _T_940 = _T_939 & _T_849; // @[el2_lib.scala 244:43] + wire _T_943 = io_trigger_pkt_any_3_tdata2[13] == lsu_match_data_3[13]; // @[el2_lib.scala 244:80] + wire _T_944 = _T_940 | _T_943; // @[el2_lib.scala 244:25] + wire _T_946 = &io_trigger_pkt_any_3_tdata2[13:0]; // @[el2_lib.scala 244:38] + wire _T_947 = _T_946 & _T_849; // @[el2_lib.scala 244:43] + wire _T_950 = io_trigger_pkt_any_3_tdata2[14] == lsu_match_data_3[14]; // @[el2_lib.scala 244:80] + wire _T_951 = _T_947 | _T_950; // @[el2_lib.scala 244:25] + wire _T_953 = &io_trigger_pkt_any_3_tdata2[14:0]; // @[el2_lib.scala 244:38] + wire _T_954 = _T_953 & _T_849; // @[el2_lib.scala 244:43] + wire _T_957 = io_trigger_pkt_any_3_tdata2[15] == lsu_match_data_3[15]; // @[el2_lib.scala 244:80] + wire _T_958 = _T_954 | _T_957; // @[el2_lib.scala 244:25] + wire _T_960 = &io_trigger_pkt_any_3_tdata2[15:0]; // @[el2_lib.scala 244:38] + wire _T_961 = _T_960 & _T_849; // @[el2_lib.scala 244:43] + wire _T_964 = io_trigger_pkt_any_3_tdata2[16] == lsu_match_data_3[16]; // @[el2_lib.scala 244:80] + wire _T_965 = _T_961 | _T_964; // @[el2_lib.scala 244:25] + wire _T_967 = &io_trigger_pkt_any_3_tdata2[16:0]; // @[el2_lib.scala 244:38] + wire _T_968 = _T_967 & _T_849; // @[el2_lib.scala 244:43] + wire _T_971 = io_trigger_pkt_any_3_tdata2[17] == lsu_match_data_3[17]; // @[el2_lib.scala 244:80] + wire _T_972 = _T_968 | _T_971; // @[el2_lib.scala 244:25] + wire _T_974 = &io_trigger_pkt_any_3_tdata2[17:0]; // @[el2_lib.scala 244:38] + wire _T_975 = _T_974 & _T_849; // @[el2_lib.scala 244:43] + wire _T_978 = io_trigger_pkt_any_3_tdata2[18] == lsu_match_data_3[18]; // @[el2_lib.scala 244:80] + wire _T_979 = _T_975 | _T_978; // @[el2_lib.scala 244:25] + wire _T_981 = &io_trigger_pkt_any_3_tdata2[18:0]; // @[el2_lib.scala 244:38] + wire _T_982 = _T_981 & _T_849; // @[el2_lib.scala 244:43] + wire _T_985 = io_trigger_pkt_any_3_tdata2[19] == lsu_match_data_3[19]; // @[el2_lib.scala 244:80] + wire _T_986 = _T_982 | _T_985; // @[el2_lib.scala 244:25] + wire _T_988 = &io_trigger_pkt_any_3_tdata2[19:0]; // @[el2_lib.scala 244:38] + wire _T_989 = _T_988 & _T_849; // @[el2_lib.scala 244:43] + wire _T_992 = io_trigger_pkt_any_3_tdata2[20] == lsu_match_data_3[20]; // @[el2_lib.scala 244:80] + wire _T_993 = _T_989 | _T_992; // @[el2_lib.scala 244:25] + wire _T_995 = &io_trigger_pkt_any_3_tdata2[20:0]; // @[el2_lib.scala 244:38] + wire _T_996 = _T_995 & _T_849; // @[el2_lib.scala 244:43] + wire _T_999 = io_trigger_pkt_any_3_tdata2[21] == lsu_match_data_3[21]; // @[el2_lib.scala 244:80] + wire _T_1000 = _T_996 | _T_999; // @[el2_lib.scala 244:25] + wire _T_1002 = &io_trigger_pkt_any_3_tdata2[21:0]; // @[el2_lib.scala 244:38] + wire _T_1003 = _T_1002 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1006 = io_trigger_pkt_any_3_tdata2[22] == lsu_match_data_3[22]; // @[el2_lib.scala 244:80] + wire _T_1007 = _T_1003 | _T_1006; // @[el2_lib.scala 244:25] + wire _T_1009 = &io_trigger_pkt_any_3_tdata2[22:0]; // @[el2_lib.scala 244:38] + wire _T_1010 = _T_1009 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1013 = io_trigger_pkt_any_3_tdata2[23] == lsu_match_data_3[23]; // @[el2_lib.scala 244:80] + wire _T_1014 = _T_1010 | _T_1013; // @[el2_lib.scala 244:25] + wire _T_1016 = &io_trigger_pkt_any_3_tdata2[23:0]; // @[el2_lib.scala 244:38] + wire _T_1017 = _T_1016 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1020 = io_trigger_pkt_any_3_tdata2[24] == lsu_match_data_3[24]; // @[el2_lib.scala 244:80] + wire _T_1021 = _T_1017 | _T_1020; // @[el2_lib.scala 244:25] + wire _T_1023 = &io_trigger_pkt_any_3_tdata2[24:0]; // @[el2_lib.scala 244:38] + wire _T_1024 = _T_1023 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1027 = io_trigger_pkt_any_3_tdata2[25] == lsu_match_data_3[25]; // @[el2_lib.scala 244:80] + wire _T_1028 = _T_1024 | _T_1027; // @[el2_lib.scala 244:25] + wire _T_1030 = &io_trigger_pkt_any_3_tdata2[25:0]; // @[el2_lib.scala 244:38] + wire _T_1031 = _T_1030 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1034 = io_trigger_pkt_any_3_tdata2[26] == lsu_match_data_3[26]; // @[el2_lib.scala 244:80] + wire _T_1035 = _T_1031 | _T_1034; // @[el2_lib.scala 244:25] + wire _T_1037 = &io_trigger_pkt_any_3_tdata2[26:0]; // @[el2_lib.scala 244:38] + wire _T_1038 = _T_1037 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1041 = io_trigger_pkt_any_3_tdata2[27] == lsu_match_data_3[27]; // @[el2_lib.scala 244:80] + wire _T_1042 = _T_1038 | _T_1041; // @[el2_lib.scala 244:25] + wire _T_1044 = &io_trigger_pkt_any_3_tdata2[27:0]; // @[el2_lib.scala 244:38] + wire _T_1045 = _T_1044 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1048 = io_trigger_pkt_any_3_tdata2[28] == lsu_match_data_3[28]; // @[el2_lib.scala 244:80] + wire _T_1049 = _T_1045 | _T_1048; // @[el2_lib.scala 244:25] + wire _T_1051 = &io_trigger_pkt_any_3_tdata2[28:0]; // @[el2_lib.scala 244:38] + wire _T_1052 = _T_1051 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1055 = io_trigger_pkt_any_3_tdata2[29] == lsu_match_data_3[29]; // @[el2_lib.scala 244:80] + wire _T_1056 = _T_1052 | _T_1055; // @[el2_lib.scala 244:25] + wire _T_1058 = &io_trigger_pkt_any_3_tdata2[29:0]; // @[el2_lib.scala 244:38] + wire _T_1059 = _T_1058 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1062 = io_trigger_pkt_any_3_tdata2[30] == lsu_match_data_3[30]; // @[el2_lib.scala 244:80] + wire _T_1063 = _T_1059 | _T_1062; // @[el2_lib.scala 244:25] + wire _T_1065 = &io_trigger_pkt_any_3_tdata2[30:0]; // @[el2_lib.scala 244:38] + wire _T_1066 = _T_1065 & _T_849; // @[el2_lib.scala 244:43] + wire _T_1069 = io_trigger_pkt_any_3_tdata2[31] == lsu_match_data_3[31]; // @[el2_lib.scala 244:80] + wire _T_1070 = _T_1066 | _T_1069; // @[el2_lib.scala 244:25] + wire [7:0] _T_1077 = {_T_902,_T_895,_T_888,_T_881,_T_874,_T_867,_T_860,_T_853}; // @[el2_lib.scala 245:14] + wire [15:0] _T_1085 = {_T_958,_T_951,_T_944,_T_937,_T_930,_T_923,_T_916,_T_909,_T_1077}; // @[el2_lib.scala 245:14] + wire [7:0] _T_1092 = {_T_1014,_T_1007,_T_1000,_T_993,_T_986,_T_979,_T_972,_T_965}; // @[el2_lib.scala 245:14] + wire [31:0] _T_1101 = {_T_1070,_T_1063,_T_1056,_T_1049,_T_1042,_T_1035,_T_1028,_T_1021,_T_1092,_T_1085}; // @[el2_lib.scala 245:14] + wire [31:0] _GEN_3 = {{31'd0}, _T_844}; // @[el2_lsu_trigger.scala 19:87] + wire [31:0] _T_1102 = _GEN_3 & _T_1101; // @[el2_lsu_trigger.scala 19:87] + wire [127:0] _T_1105 = {_T_1102,_T_836,_T_570,_T_304}; // @[Cat.scala 29:58] + assign io_lsu_trigger_match_m = _T_1105[3:0]; // @[el2_lsu_trigger.scala 18:26] endmodule module el2_lsu_clkdomain( input clock, input reset, + input io_free_clk, input io_clk_override, input io_dma_dccm_req, input io_ldst_stbuf_reqvld_r, input io_stbuf_reqvld_any, input io_stbuf_reqvld_flushed_any, + input io_lsu_busreq_r, + input io_lsu_bus_buffer_pend_any, + input io_lsu_bus_buffer_empty_any, + input io_lsu_stbuf_empty_any, input io_lsu_bus_clk_en, input io_lsu_p_valid, input io_lsu_pkt_d_store, input io_lsu_pkt_d_valid, input io_lsu_pkt_m_store, input io_lsu_pkt_m_valid, + input io_lsu_pkt_r_valid, output io_lsu_c1_m_clk, output io_lsu_c1_r_clk, output io_lsu_c2_m_clk, output io_lsu_c2_r_clk, + output io_lsu_store_c1_m_clk, output io_lsu_stbuf_c1_clk, + output io_lsu_bus_obuf_c1_clk, + output io_lsu_bus_ibuf_c1_clk, + output io_lsu_bus_buf_c1_clk, + output io_lsu_busm_clk, output io_lsu_free_c2_clk, input io_scan_mode ); @@ -3666,183 +4836,202 @@ module el2_lsu_clkdomain( reg [31:0] _RAND_0; reg [31:0] _RAND_1; reg [31:0] _RAND_2; + reg [31:0] _RAND_3; `endif // RANDOMIZE_REG_INIT - wire lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:35] - wire lsu_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 88:35] - wire lsu_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 88:35] - wire lsu_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 88:35] - wire lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:35] - wire lsu_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 89:35] - wire lsu_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 89:35] - wire lsu_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 89:35] - wire lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:35] - wire lsu_c2m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 90:35] - wire lsu_c2m_cgc_io_en; // @[el2_lsu_clkdomain.scala 90:35] - wire lsu_c2m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 90:35] - wire lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:35] - wire lsu_c2r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 91:35] - wire lsu_c2r_cgc_io_en; // @[el2_lsu_clkdomain.scala 91:35] - wire lsu_c2r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 91:35] - wire lsu_store_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 92:35] - wire lsu_store_c1m_cgc_io_clk; // @[el2_lsu_clkdomain.scala 92:35] - wire lsu_store_c1m_cgc_io_en; // @[el2_lsu_clkdomain.scala 92:35] - wire lsu_store_c1m_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 92:35] - wire lsu_store_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 93:35] - wire lsu_store_c1r_cgc_io_clk; // @[el2_lsu_clkdomain.scala 93:35] - wire lsu_store_c1r_cgc_io_en; // @[el2_lsu_clkdomain.scala 93:35] - wire lsu_store_c1r_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 93:35] - wire lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:35] - wire lsu_stbuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 94:35] - wire lsu_stbuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 94:35] - wire lsu_stbuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 94:35] - wire lsu_bus_ibuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 95:35] - wire lsu_bus_ibuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 95:35] - wire lsu_bus_ibuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 95:35] - wire lsu_bus_ibuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 95:35] - wire lsu_bus_obuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 96:35] - wire lsu_bus_obuf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 96:35] - wire lsu_bus_obuf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 96:35] - wire lsu_bus_obuf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 96:35] - wire lsu_bus_buf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 97:35] - wire lsu_bus_buf_c1_cgc_io_clk; // @[el2_lsu_clkdomain.scala 97:35] - wire lsu_bus_buf_c1_cgc_io_en; // @[el2_lsu_clkdomain.scala 97:35] - wire lsu_bus_buf_c1_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 97:35] - wire lsu_busm_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 98:35] - wire lsu_busm_cgc_io_clk; // @[el2_lsu_clkdomain.scala 98:35] - wire lsu_busm_cgc_io_en; // @[el2_lsu_clkdomain.scala 98:35] - wire lsu_busm_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 98:35] - wire lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:35] - wire lsu_free_cgc_io_clk; // @[el2_lsu_clkdomain.scala 99:35] - wire lsu_free_cgc_io_en; // @[el2_lsu_clkdomain.scala 99:35] - wire lsu_free_cgc_io_scan_mode; // @[el2_lsu_clkdomain.scala 99:35] - wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 64:51] - reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 84:67] - wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 65:51] - wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70] - reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 85:67] - wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 66:51] - wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 66:70] - wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 68:47] - reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 86:67] - wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 69:47] - wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 71:49] - wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 72:49] - wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 73:55] - wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 73:77] - rvclkhdr lsu_c1m_cgc ( // @[el2_lsu_clkdomain.scala 88:35] - .io_l1clk(lsu_c1m_cgc_io_l1clk), - .io_clk(lsu_c1m_cgc_io_clk), - .io_en(lsu_c1m_cgc_io_en), - .io_scan_mode(lsu_c1m_cgc_io_scan_mode) + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 483:22] + wire _T = io_lsu_p_valid | io_dma_dccm_req; // @[el2_lsu_clkdomain.scala 63:51] + reg lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 82:67] + wire _T_1 = io_lsu_pkt_d_valid | lsu_c1_d_clken_q; // @[el2_lsu_clkdomain.scala 64:51] + wire lsu_c1_m_clken = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 64:70] + reg lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 83:67] + wire _T_2 = io_lsu_pkt_m_valid | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 65:51] + wire lsu_c1_r_clken = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 65:70] + wire _T_3 = lsu_c1_m_clken | lsu_c1_m_clken_q; // @[el2_lsu_clkdomain.scala 67:47] + reg lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 84:67] + wire _T_4 = lsu_c1_r_clken | lsu_c1_r_clken_q; // @[el2_lsu_clkdomain.scala 68:47] + wire _T_5 = lsu_c1_m_clken & io_lsu_pkt_d_store; // @[el2_lsu_clkdomain.scala 70:49] + wire _T_6 = lsu_c1_r_clken & io_lsu_pkt_m_store; // @[el2_lsu_clkdomain.scala 71:49] + wire _T_7 = io_ldst_stbuf_reqvld_r | io_stbuf_reqvld_any; // @[el2_lsu_clkdomain.scala 72:55] + wire _T_8 = _T_7 | io_stbuf_reqvld_flushed_any; // @[el2_lsu_clkdomain.scala 72:77] + wire _T_9 = io_lsu_bus_buffer_pend_any | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 74:61] + wire _T_10 = _T_9 | io_clk_override; // @[el2_lsu_clkdomain.scala 74:79] + wire _T_11 = ~io_lsu_bus_buffer_empty_any; // @[el2_lsu_clkdomain.scala 75:32] + wire _T_12 = _T_11 | io_lsu_busreq_r; // @[el2_lsu_clkdomain.scala 75:61] + wire _T_13 = io_lsu_p_valid | io_lsu_pkt_d_valid; // @[el2_lsu_clkdomain.scala 77:48] + wire _T_14 = _T_13 | io_lsu_pkt_m_valid; // @[el2_lsu_clkdomain.scala 77:69] + wire _T_15 = _T_14 | io_lsu_pkt_r_valid; // @[el2_lsu_clkdomain.scala 77:90] + wire _T_17 = _T_15 | _T_11; // @[el2_lsu_clkdomain.scala 77:112] + wire _T_18 = ~io_lsu_stbuf_empty_any; // @[el2_lsu_clkdomain.scala 77:145] + wire _T_19 = _T_17 | _T_18; // @[el2_lsu_clkdomain.scala 77:143] + wire lsu_free_c1_clken = _T_19 | io_clk_override; // @[el2_lsu_clkdomain.scala 77:169] + reg lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 81:60] + wire _T_20 = lsu_free_c1_clken | lsu_free_c1_clken_q; // @[el2_lsu_clkdomain.scala 78:50] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr lsu_c1r_cgc ( // @[el2_lsu_clkdomain.scala 89:35] - .io_l1clk(lsu_c1r_cgc_io_l1clk), - .io_clk(lsu_c1r_cgc_io_clk), - .io_en(lsu_c1r_cgc_io_en), - .io_scan_mode(lsu_c1r_cgc_io_scan_mode) + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr lsu_c2m_cgc ( // @[el2_lsu_clkdomain.scala 90:35] - .io_l1clk(lsu_c2m_cgc_io_l1clk), - .io_clk(lsu_c2m_cgc_io_clk), - .io_en(lsu_c2m_cgc_io_en), - .io_scan_mode(lsu_c2m_cgc_io_scan_mode) + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr lsu_c2r_cgc ( // @[el2_lsu_clkdomain.scala 91:35] - .io_l1clk(lsu_c2r_cgc_io_l1clk), - .io_clk(lsu_c2r_cgc_io_clk), - .io_en(lsu_c2r_cgc_io_en), - .io_scan_mode(lsu_c2r_cgc_io_scan_mode) + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr lsu_store_c1m_cgc ( // @[el2_lsu_clkdomain.scala 92:35] - .io_l1clk(lsu_store_c1m_cgc_io_l1clk), - .io_clk(lsu_store_c1m_cgc_io_clk), - .io_en(lsu_store_c1m_cgc_io_en), - .io_scan_mode(lsu_store_c1m_cgc_io_scan_mode) + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvclkhdr lsu_store_c1r_cgc ( // @[el2_lsu_clkdomain.scala 93:35] - .io_l1clk(lsu_store_c1r_cgc_io_l1clk), - .io_clk(lsu_store_c1r_cgc_io_clk), - .io_en(lsu_store_c1r_cgc_io_en), - .io_scan_mode(lsu_store_c1r_cgc_io_scan_mode) + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) ); - rvclkhdr lsu_stbuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 94:35] - .io_l1clk(lsu_stbuf_c1_cgc_io_l1clk), - .io_clk(lsu_stbuf_c1_cgc_io_clk), - .io_en(lsu_stbuf_c1_cgc_io_en), - .io_scan_mode(lsu_stbuf_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) ); - rvclkhdr lsu_bus_ibuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 95:35] - .io_l1clk(lsu_bus_ibuf_c1_cgc_io_l1clk), - .io_clk(lsu_bus_ibuf_c1_cgc_io_clk), - .io_en(lsu_bus_ibuf_c1_cgc_io_en), - .io_scan_mode(lsu_bus_ibuf_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) ); - rvclkhdr lsu_bus_obuf_c1_cgc ( // @[el2_lsu_clkdomain.scala 96:35] - .io_l1clk(lsu_bus_obuf_c1_cgc_io_l1clk), - .io_clk(lsu_bus_obuf_c1_cgc_io_clk), - .io_en(lsu_bus_obuf_c1_cgc_io_en), - .io_scan_mode(lsu_bus_obuf_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) ); - rvclkhdr lsu_bus_buf_c1_cgc ( // @[el2_lsu_clkdomain.scala 97:35] - .io_l1clk(lsu_bus_buf_c1_cgc_io_l1clk), - .io_clk(lsu_bus_buf_c1_cgc_io_clk), - .io_en(lsu_bus_buf_c1_cgc_io_en), - .io_scan_mode(lsu_bus_buf_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) ); - rvclkhdr lsu_busm_cgc ( // @[el2_lsu_clkdomain.scala 98:35] - .io_l1clk(lsu_busm_cgc_io_l1clk), - .io_clk(lsu_busm_cgc_io_clk), - .io_en(lsu_busm_cgc_io_en), - .io_scan_mode(lsu_busm_cgc_io_scan_mode) + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) ); - rvclkhdr lsu_free_cgc ( // @[el2_lsu_clkdomain.scala 99:35] - .io_l1clk(lsu_free_cgc_io_l1clk), - .io_clk(lsu_free_cgc_io_clk), - .io_en(lsu_free_cgc_io_en), - .io_scan_mode(lsu_free_cgc_io_scan_mode) + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) ); - assign io_lsu_c1_m_clk = lsu_c1m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 88:127] - assign io_lsu_c1_r_clk = lsu_c1r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 89:127] - assign io_lsu_c2_m_clk = lsu_c2m_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 90:127] - assign io_lsu_c2_r_clk = lsu_c2r_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 91:127] - assign io_lsu_stbuf_c1_clk = lsu_stbuf_c1_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 94:127] - assign io_lsu_free_c2_clk = lsu_free_cgc_io_l1clk; // @[el2_lsu_clkdomain.scala 99:127] - assign lsu_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 101:30] - assign lsu_c1m_cgc_io_en = _T_1 | io_clk_override; // @[el2_lsu_clkdomain.scala 88:77] - assign lsu_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 101:75] - assign lsu_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 102:30] - assign lsu_c1r_cgc_io_en = _T_2 | io_clk_override; // @[el2_lsu_clkdomain.scala 89:77] - assign lsu_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 102:75] - assign lsu_c2m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 103:30] - assign lsu_c2m_cgc_io_en = _T_3 | io_clk_override; // @[el2_lsu_clkdomain.scala 90:77] - assign lsu_c2m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 103:75] - assign lsu_c2r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 104:30] - assign lsu_c2r_cgc_io_en = _T_4 | io_clk_override; // @[el2_lsu_clkdomain.scala 91:77] - assign lsu_c2r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 104:75] - assign lsu_store_c1m_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 105:30] - assign lsu_store_c1m_cgc_io_en = _T_5 | io_clk_override; // @[el2_lsu_clkdomain.scala 92:77] - assign lsu_store_c1m_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 105:75] - assign lsu_store_c1r_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 106:30] - assign lsu_store_c1r_cgc_io_en = _T_6 | io_clk_override; // @[el2_lsu_clkdomain.scala 93:77] - assign lsu_store_c1r_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 106:75] - assign lsu_stbuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 107:30] - assign lsu_stbuf_c1_cgc_io_en = _T_8 | io_clk_override; // @[el2_lsu_clkdomain.scala 94:77] - assign lsu_stbuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 107:75] - assign lsu_bus_ibuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 108:30] - assign lsu_bus_ibuf_c1_cgc_io_en = io_clk_override; // @[el2_lsu_clkdomain.scala 95:77] - assign lsu_bus_ibuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 108:75] - assign lsu_bus_obuf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 109:30] - assign lsu_bus_obuf_c1_cgc_io_en = io_clk_override & io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 96:77] - assign lsu_bus_obuf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 109:75] - assign lsu_bus_buf_c1_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 110:30] - assign lsu_bus_buf_c1_cgc_io_en = 1'h1; // @[el2_lsu_clkdomain.scala 97:77] - assign lsu_bus_buf_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 110:75] - assign lsu_busm_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 111:30] - assign lsu_busm_cgc_io_en = io_lsu_bus_clk_en; // @[el2_lsu_clkdomain.scala 98:77] - assign lsu_busm_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 111:75] - assign lsu_free_cgc_io_clk = clock; // @[el2_lsu_clkdomain.scala 112:30] - assign lsu_free_cgc_io_en = 1'h1; // @[el2_lsu_clkdomain.scala 99:77] - assign lsu_free_cgc_io_scan_mode = io_scan_mode; // @[el2_lsu_clkdomain.scala 112:75] + assign io_lsu_c1_m_clk = rvclkhdr_io_l1clk; // @[el2_lsu_clkdomain.scala 86:26] + assign io_lsu_c1_r_clk = rvclkhdr_1_io_l1clk; // @[el2_lsu_clkdomain.scala 87:26] + assign io_lsu_c2_m_clk = rvclkhdr_2_io_l1clk; // @[el2_lsu_clkdomain.scala 88:26] + assign io_lsu_c2_r_clk = rvclkhdr_3_io_l1clk; // @[el2_lsu_clkdomain.scala 89:26] + assign io_lsu_store_c1_m_clk = rvclkhdr_4_io_l1clk; // @[el2_lsu_clkdomain.scala 90:26] + assign io_lsu_stbuf_c1_clk = rvclkhdr_6_io_l1clk; // @[el2_lsu_clkdomain.scala 92:26] + assign io_lsu_bus_obuf_c1_clk = rvclkhdr_8_io_l1clk; // @[el2_lsu_clkdomain.scala 94:26] + assign io_lsu_bus_ibuf_c1_clk = rvclkhdr_7_io_l1clk; // @[el2_lsu_clkdomain.scala 93:26] + assign io_lsu_bus_buf_c1_clk = rvclkhdr_9_io_l1clk; // @[el2_lsu_clkdomain.scala 95:26] + assign io_lsu_busm_clk = rvclkhdr_10_io_l1clk; // @[el2_lsu_clkdomain.scala 96:26] + assign io_lsu_free_c2_clk = rvclkhdr_11_io_l1clk; // @[el2_lsu_clkdomain.scala 97:26] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_1 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = _T_2 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = _T_3 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = _T_4 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_4_io_en = _T_5 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_5_io_en = _T_6 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_6_io_en = _T_8 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_7_io_en = io_lsu_busreq_r | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_8_io_en = _T_10 & io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_9_io_en = _T_12 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_10_io_en = io_lsu_bus_clk_en; // @[el2_lib.scala 485:16] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_11_io_en = _T_20 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -3884,6 +5073,8 @@ initial begin lsu_c1_m_clken_q = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; lsu_c1_r_clken_q = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + lsu_free_c1_clken_q = _RAND_3[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin lsu_c1_d_clken_q = 1'h0; @@ -3894,6 +5085,9 @@ initial begin if (reset) begin lsu_c1_r_clken_q = 1'h0; end + if (reset) begin + lsu_free_c1_clken_q = 1'h0; + end `endif // RANDOMIZE end // initial `ifdef FIRRTL_AFTER_INITIAL @@ -3921,6 +5115,5173 @@ end // initial lsu_c1_r_clken_q <= _T_2 | io_clk_override; end end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_free_c1_clken_q <= 1'h0; + end else begin + lsu_free_c1_clken_q <= _T_19 | io_clk_override; + end + end +endmodule +module el2_lsu_bus_buffer( + input clock, + input reset, + input io_scan_mode, + input io_dec_tlu_external_ldfwd_disable, + input io_dec_tlu_wb_coalescing_disable, + input io_dec_tlu_sideeffect_posted_disable, + input io_dec_tlu_force_halt, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_lsu_busm_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_pkt_m_load, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_r_by, + input io_lsu_pkt_r_half, + input io_lsu_pkt_r_word, + input io_lsu_pkt_r_load, + input io_lsu_pkt_r_store, + input io_lsu_pkt_r_unsign, + input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_no_word_merge_r, + input io_no_dword_merge_r, + input io_lsu_busreq_m, + input io_ld_full_hit_m, + input io_flush_m_up, + input io_flush_r, + input io_lsu_commit_r, + input io_is_sideeffects_r, + input io_ldst_dual_d, + input io_ldst_dual_m, + input io_ldst_dual_r, + input [7:0] io_ldst_byteen_ext_m, + input io_lsu_axi_wready, + input io_lsu_axi_bvalid, + input [1:0] io_lsu_axi_bresp, + input [2:0] io_lsu_axi_bid, + input io_lsu_axi_arready, + input io_lsu_axi_rvalid, + input [2:0] io_lsu_axi_rid, + input [63:0] io_lsu_axi_rdata, + input io_lsu_bus_clk_en, + input io_lsu_bus_clk_en_q, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [3:0] io_ld_byte_hit_buf_lo, + output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, + output io_lsu_imprecise_error_load_any, + output io_lsu_imprecise_error_store_any, + output [31:0] io_lsu_imprecise_error_addr_any, + output io_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_nonblock_load_tag_m, + output io_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_nonblock_load_inv_tag_r, + output io_lsu_nonblock_load_data_valid, + output io_lsu_nonblock_load_data_error, + output [1:0] io_lsu_nonblock_load_data_tag, + output [31:0] io_lsu_nonblock_load_data, + output io_lsu_pmu_bus_trxn, + output io_lsu_pmu_bus_misaligned, + output io_lsu_pmu_bus_error, + output io_lsu_pmu_bus_busy, + output io_lsu_axi_awvalid, + input io_lsu_axi_awready, + output [2:0] io_lsu_axi_awid, + output [31:0] io_lsu_axi_awaddr, + output [3:0] io_lsu_axi_awregion, + output [2:0] io_lsu_axi_awsize, + output [3:0] io_lsu_axi_awcache, + output io_lsu_axi_wvalid, + output [63:0] io_lsu_axi_wdata, + output [7:0] io_lsu_axi_wstrb, + output io_lsu_axi_bready, + output io_lsu_axi_arvalid, + output [2:0] io_lsu_axi_arid, + output [31:0] io_lsu_axi_araddr, + output [3:0] io_lsu_axi_arregion, + output [2:0] io_lsu_axi_arsize, + output [3:0] io_lsu_axi_arcache, + output io_lsu_axi_rready +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_buffer.scala 127:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 128:46] + reg [31:0] buf_addr_0; // @[el2_lib.scala 514:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + reg _T_4360; // @[Reg.scala 27:20] + reg _T_4357; // @[Reg.scala 27:20] + reg _T_4354; // @[Reg.scala 27:20] + reg _T_4351; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 130:98] + reg [2:0] buf_state_0; // @[Reg.scala 27:20] + wire _T_5 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_6 = _T_4 & _T_5; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_1; // @[el2_lib.scala 514:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_11 = _T_9 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 130:98] + reg [2:0] buf_state_1; // @[Reg.scala 27:20] + wire _T_12 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_13 = _T_11 & _T_12; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_2; // @[el2_lib.scala 514:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_18 = _T_16 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 130:98] + reg [2:0] buf_state_2; // @[Reg.scala 27:20] + wire _T_19 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_20 = _T_18 & _T_19; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_3; // @[el2_lib.scala 514:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_25 = _T_23 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 130:98] + reg [2:0] buf_state_3; // @[Reg.scala 27:20] + wire _T_26 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_27 = _T_25 & _T_26; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_32 = _T_30 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_34 = _T_32 & _T_5; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_39 = _T_37 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_41 = _T_39 & _T_12; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_46 = _T_44 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_48 = _T_46 & _T_19; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_53 = _T_51 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1848; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 405:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:48] + reg obuf_merge; // @[Reg.scala 27:20] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 508:77] + reg obuf_valid; // @[el2_lsu_bus_buffer.scala 399:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 398:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] + wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 199:97] + reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 205:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 205:73] + reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:54] + wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 205:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 205:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 210:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 210:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] + wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] + wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] + wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 191:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51] + wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73] + wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 211:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 192:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[el2_lib.scala 514:16] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[el2_lib.scala 514:16] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[el2_lib.scala 514:16] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[el2_lib.scala 514:16] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 221:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[el2_lib.scala 514:16] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 222:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 227:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 228:32] + wire [3:0] _T_750 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 235:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 236:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 237:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 238:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 255:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 257:26] + wire _T_845 = io_lsu_pkt_r_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 259:55] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 259:34] + wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 259:79] + wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 259:77] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 260:36] + wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 260:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 260:54] + wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 262:36] + reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 305:55] + wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 268:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 268:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 287:54] + wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 287:75] + wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 287:88] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 287:124] + wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 287:101] + wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 287:147] + wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 287:145] + wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 287:170] + wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 287:168] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 288:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 268:98] + wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 268:82] + wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 268:80] + wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 269:5] + wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 263:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 263:42] + wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 263:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 263:115] + wire _T_863 = io_lsu_pkt_m_load | _T_862; // @[el2_lsu_bus_buffer.scala 263:95] + wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 263:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 269:16] + reg ibuf_sideeffect; // @[Reg.scala 27:20] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 269:35] + wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 269:55] + wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 269:53] + wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 269:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 268:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 262:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 262:49] + reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 669:49] + reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 668:49] + reg [1:0] ibuf_tag; // @[Reg.scala 27:20] + wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_word,io_lsu_pkt_r_half}; // @[Cat.scala 29:58] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 278:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 282:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 285:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 285:93] + wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 289:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 289:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 289:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:58] + wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 292:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] + reg ibuf_dual; // @[Reg.scala 27:20] + reg ibuf_samedw; // @[Reg.scala 27:20] + reg ibuf_nomerge; // @[Reg.scala 27:20] + reg ibuf_unsign; // @[Reg.scala 27:20] + reg [1:0] ibuf_sz; // @[Reg.scala 27:20] + wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 575:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 575:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:43] + wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:73] + wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:72] + wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 315:51] + reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 414:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 315:97] + wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 315:80] + wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 315:114] + wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 431:88] + wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 444:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 316:114] + reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] + reg buf_nomerge_1; // @[Reg.scala 27:20] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] + reg buf_nomerge_2; // @[Reg.scala 27:20] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] + reg buf_nomerge_3; // @[Reg.scala 27:20] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 316:31] + wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 316:29] + reg _T_4330; // @[Reg.scala 27:20] + reg _T_4327; // @[Reg.scala 27:20] + reg _T_4324; // @[Reg.scala 27:20] + reg _T_4321; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 317:5] + wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 316:140] + wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 319:58] + wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 319:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 319:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 319:101] + wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 317:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 317:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 318:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 318:95] + wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 318:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 318:123] + wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 577:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 577:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 321:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 321:31] + wire _T_1089 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 321:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 321:84] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 321:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 336:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 336:74] + wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 336:52] + wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 336:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 337:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 436:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 337:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 338:23] + wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 338:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 338:141] + wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 338:105] + wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 338:103] + reg buf_dual_3; // @[Reg.scala 27:20] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] + reg buf_samedw_3; // @[Reg.scala 27:20] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 339:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 339:150] + wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 339:148] + wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 339:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 432:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 437:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 339:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 339:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 339:269] + wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 338:164] + wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 336:98] + reg obuf_write; // @[Reg.scala 27:20] + reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 401:54] + reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 402:55] + wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 609:54] + wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:75] + wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:39] + wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 609:23] + wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 340:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 340:46] + reg obuf_nosend; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 340:60] + wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 340:29] + wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 340:77] + wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 340:75] + reg [31:0] obuf_addr; // @[el2_lib.scala 514:16] + wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72] + wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72] + wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72] + wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72] + wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72] + wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72] + wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 340:118] + wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 340:116] + wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 340:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 342:47] + wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39] + wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 612:35] + wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 611:39] + wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 612:70] + wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 612:52] + wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 612:111] + wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 612:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 342:33] + wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 342:65] + wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 342:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 342:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 342:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _T_1202; // @[el2_lsu_bus_buffer.scala 343:26] + wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] + wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 345:25] + reg [1:0] buf_sz_0; // @[Reg.scala 27:20] + wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] + wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 348:23] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 357:39] + wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 357:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 361:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 361:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 361:96] + wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 361:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 361:153] + wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 361:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 361:132] + wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 361:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 361:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 375:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 375:60] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 375:80] + wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 375:78] + wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 375:99] + wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 375:97] + wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 375:113] + wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 375:111] + wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 375:130] + wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 375:128] + wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 376:20] + wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 376:18] + reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 403:56] + wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 613:37] + reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 404:55] + wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 376:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 376:70] + wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 376:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 376:53] + wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 376:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 375:165] + wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 369:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 369:42] + wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 369:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 369:61] + wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 369:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 370:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 370:37] + wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 370:35] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 377:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 378:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 377:28] + wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 379:46] + wire [7:0] _T_1432 = {buf_byteen_0,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,buf_byteen_0}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = buf_addr_0[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 380:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 379:28] + wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 382:44] + wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72] + wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72] + wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] + wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 383:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 382:26] + wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 384:44] + wire [63:0] _T_1522 = {buf_data_0,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,buf_data_0}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = buf_addr_0[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 385:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 384:26] + wire _T_1621 = CmdPtr0 != 2'h0; // @[el2_lsu_bus_buffer.scala 391:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 391:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 391:59] + wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 391:75] + wire _T_1651 = _T_1637 & _T_2606; // @[el2_lsu_bus_buffer.scala 391:118] + wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 391:161] + wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 392:85] + wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 395:38] + reg buf_dualhi_3; // @[Reg.scala 27:20] + reg buf_dualhi_2; // @[Reg.scala 27:20] + reg buf_dualhi_1; // @[Reg.scala 27:20] + reg buf_dualhi_0; // @[Reg.scala 27:20] + wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72] + wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72] + wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72] + wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] + wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] + wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 395:109] + wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 395:107] + wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 395:179] + wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 392:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 396:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 396:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 395:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 386:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 399:58] + wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 399:93] + reg [1:0] obuf_sz; // @[Reg.scala 27:20] + reg [7:0] obuf_byteen; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[el2_lib.scala 514:16] + wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:57] + wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] + wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 423:76] + reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] + wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] + wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] + wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] + wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 435:70] + wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:77] + wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 497:97] + wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 497:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:46] + wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 614:38] + wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:46] + reg _T_4307; // @[Reg.scala 27:20] + reg _T_4305; // @[Reg.scala 27:20] + reg _T_4303; // @[Reg.scala 27:20] + reg _T_4301; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] + reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3638 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 525:58] + reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3646 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 537:21] + reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] + reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3688 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 447:10] + wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 461:23] + wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 461:41] + wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 462:35] + wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3831 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 525:58] + reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3839 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3881 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4024 = io_lsu_axi_rid == _GEN_376; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 525:58] + reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4032 = io_lsu_axi_rid == _GEN_377; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4074 = io_lsu_axi_rid == _GEN_379; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4217 = io_lsu_axi_rid == _GEN_380; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 525:58] + reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4225 = io_lsu_axi_rid == _GEN_381; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4267 = io_lsu_axi_rid == _GEN_383; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] + wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] + wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] + wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] + wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] + wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 479:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 485:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 486:47] + wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 507:89] + wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 507:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 618:58] + wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 618:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 529:143] + wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 617:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 519:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 578:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] + wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] + wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] + wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] + wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] + wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] + wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] + wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] + wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] + wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4336; // @[Reg.scala 27:20] + reg _T_4339; // @[Reg.scala 27:20] + reg _T_4342; // @[Reg.scala 27:20] + reg _T_4345; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] + reg _T_4411; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4406; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4401; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4396; // @[el2_lsu_bus_buffer.scala 571:80] + wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 571:126] + wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 574:28] + wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 574:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 574:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 574:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[el2_lsu_bus_buffer.scala 574:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 574:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 574:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 580:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 580:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 580:121] + wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 581:34] + wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 581:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 583:51] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 583:72] + wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 583:94] + wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 583:92] + wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 583:111] + wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 586:61] + reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 671:66] + wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] + wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] + wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] + wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72] + wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] + wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] + wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] + wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] + wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] + wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] + wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 590:106] + wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] + wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72] + wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] + wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] + wire _T_4657 = _T_4538 & _T_3641; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4663 = _T_4539 & _T_3834; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4669 = _T_4540 & _T_4027; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4675 = _T_4541 & _T_4220; // @[el2_lsu_bus_buffer.scala 592:105] + wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] + wire _T_4683 = io_lsu_nonblock_load_data_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4684 = io_lsu_nonblock_load_data_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4685 = io_lsu_nonblock_load_data_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4686 = io_lsu_nonblock_load_data_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123] + wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] + wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] + wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 593:83] + wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72] + wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] + wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 597:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[el2_lsu_bus_buffer.scala 597:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 597:92] + wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 599:69] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 600:81] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 600:63] + wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 601:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 601:26] + wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 602:6] + wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 602:27] + wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 603:27] + wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 604:21] + wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72] + wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72] + wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] + wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] + wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] + wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 622:36] + wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 622:51] + wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 622:49] + wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 634:50] + wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 634:48] + wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 639:36] + wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 639:50] + wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72] + wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72] + wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72] + wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72] + wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72] + wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72] + wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4941 = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:108] + wire _T_4944 = _T_2843 & buf_error[2]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4946 = _T_4944 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 653:108] + wire _T_4949 = _T_2865 & buf_error[3]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4951 = _T_4949 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 653:108] + wire [1:0] _T_4954 = _T_4946 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4955 = _T_4951 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_394 = {{1'd0}, _T_4941}; // @[Mux.scala 27:72] + wire [1:0] _T_4957 = _GEN_394 | _T_4954; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4957 | _T_4955; // @[Mux.scala 27:72] + wire _T_4959 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 655:72] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_355 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_356 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_357 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[el2_lsu_bus_buffer.scala 656:41] + wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 662:68] + wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 663:48] + wire _T_4970 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 666:48] + wire _T_4971 = io_lsu_axi_awvalid & _T_4970; // @[el2_lsu_bus_buffer.scala 666:46] + wire _T_4972 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 666:92] + wire _T_4973 = io_lsu_axi_wvalid & _T_4972; // @[el2_lsu_bus_buffer.scala 666:90] + wire _T_4974 = _T_4971 | _T_4973; // @[el2_lsu_bus_buffer.scala 666:69] + wire _T_4975 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 666:136] + wire _T_4976 = io_lsu_axi_arvalid & _T_4975; // @[el2_lsu_bus_buffer.scala 666:134] + wire _T_4980 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 670:75] + wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[el2_lsu_bus_buffer.scala 670:73] + reg _T_4984; // @[el2_lsu_bus_buffer.scala 670:56] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_lsu_busreq_r = _T_4984; // @[el2_lsu_bus_buffer.scala 670:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 579:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 580:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 581:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 191:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 192:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 218:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 224:24] + assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4959; // @[el2_lsu_bus_buffer.scala 655:35] + assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 652:36] + assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[el2_lsu_bus_buffer.scala 656:35] + assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 583:32] + assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 584:30] + assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 586:30] + assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 587:34] + assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 599:35] + assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 589:35] + assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 590:33] + assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 600:29] + assign io_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[el2_lsu_bus_buffer.scala 662:23] + assign io_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 663:29] + assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 664:24] + assign io_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[el2_lsu_bus_buffer.scala 666:23] + assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 622:22] + assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 623:19] + assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 624:21] + assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 628:23] + assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 625:21] + assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 627:22] + assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 634:21] + assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 636:20] + assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 635:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 650:21] + assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 639:22] + assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 640:19] + assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 641:21] + assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 645:23] + assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 642:21] + assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 644:22] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_addr_0 = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + _T_4360 = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + _T_4357 = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + _T_4354 = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + _T_4351 = _RAND_4[0:0]; + _RAND_5 = {1{`RANDOM}}; + buf_state_0 = _RAND_5[2:0]; + _RAND_6 = {1{`RANDOM}}; + buf_addr_1 = _RAND_6[31:0]; + _RAND_7 = {1{`RANDOM}}; + buf_state_1 = _RAND_7[2:0]; + _RAND_8 = {1{`RANDOM}}; + buf_addr_2 = _RAND_8[31:0]; + _RAND_9 = {1{`RANDOM}}; + buf_state_2 = _RAND_9[2:0]; + _RAND_10 = {1{`RANDOM}}; + buf_addr_3 = _RAND_10[31:0]; + _RAND_11 = {1{`RANDOM}}; + buf_state_3 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + buf_byteen_3 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + buf_byteen_2 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + buf_byteen_1 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + buf_byteen_0 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + buf_ageQ_3 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + _T_1848 = _RAND_17[1:0]; + _RAND_18 = {1{`RANDOM}}; + obuf_merge = _RAND_18[0:0]; + _RAND_19 = {1{`RANDOM}}; + obuf_tag1 = _RAND_19[1:0]; + _RAND_20 = {1{`RANDOM}}; + obuf_valid = _RAND_20[0:0]; + _RAND_21 = {1{`RANDOM}}; + obuf_wr_enQ = _RAND_21[0:0]; + _RAND_22 = {1{`RANDOM}}; + ibuf_addr = _RAND_22[31:0]; + _RAND_23 = {1{`RANDOM}}; + ibuf_write = _RAND_23[0:0]; + _RAND_24 = {1{`RANDOM}}; + ibuf_valid = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + ibuf_byteen = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + buf_ageQ_2 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + buf_ageQ_1 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + buf_ageQ_0 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + buf_data_0 = _RAND_29[31:0]; + _RAND_30 = {1{`RANDOM}}; + buf_data_1 = _RAND_30[31:0]; + _RAND_31 = {1{`RANDOM}}; + buf_data_2 = _RAND_31[31:0]; + _RAND_32 = {1{`RANDOM}}; + buf_data_3 = _RAND_32[31:0]; + _RAND_33 = {1{`RANDOM}}; + ibuf_data = _RAND_33[31:0]; + _RAND_34 = {1{`RANDOM}}; + ibuf_timer = _RAND_34[2:0]; + _RAND_35 = {1{`RANDOM}}; + ibuf_sideeffect = _RAND_35[0:0]; + _RAND_36 = {1{`RANDOM}}; + WrPtr1_r = _RAND_36[1:0]; + _RAND_37 = {1{`RANDOM}}; + WrPtr0_r = _RAND_37[1:0]; + _RAND_38 = {1{`RANDOM}}; + ibuf_tag = _RAND_38[1:0]; + _RAND_39 = {1{`RANDOM}}; + ibuf_dualtag = _RAND_39[1:0]; + _RAND_40 = {1{`RANDOM}}; + ibuf_dual = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + ibuf_samedw = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + ibuf_nomerge = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + ibuf_unsign = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + ibuf_sz = _RAND_44[1:0]; + _RAND_45 = {1{`RANDOM}}; + obuf_wr_timer = _RAND_45[2:0]; + _RAND_46 = {1{`RANDOM}}; + buf_nomerge_0 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + buf_nomerge_1 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + buf_nomerge_2 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + buf_nomerge_3 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + _T_4330 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + _T_4327 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + _T_4324 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + _T_4321 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + buf_dual_3 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + buf_dual_2 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + buf_dual_1 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + buf_dual_0 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + buf_samedw_3 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + buf_samedw_2 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + buf_samedw_1 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + buf_samedw_0 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + obuf_write = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + obuf_cmd_done = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + obuf_data_done = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + obuf_nosend = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + obuf_addr = _RAND_66[31:0]; + _RAND_67 = {1{`RANDOM}}; + buf_sz_0 = _RAND_67[1:0]; + _RAND_68 = {1{`RANDOM}}; + buf_sz_1 = _RAND_68[1:0]; + _RAND_69 = {1{`RANDOM}}; + buf_sz_2 = _RAND_69[1:0]; + _RAND_70 = {1{`RANDOM}}; + buf_sz_3 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + obuf_sideeffect = _RAND_71[0:0]; + _RAND_72 = {1{`RANDOM}}; + obuf_rdrsp_pend = _RAND_72[0:0]; + _RAND_73 = {1{`RANDOM}}; + obuf_rdrsp_tag = _RAND_73[2:0]; + _RAND_74 = {1{`RANDOM}}; + buf_dualhi_3 = _RAND_74[0:0]; + _RAND_75 = {1{`RANDOM}}; + buf_dualhi_2 = _RAND_75[0:0]; + _RAND_76 = {1{`RANDOM}}; + buf_dualhi_1 = _RAND_76[0:0]; + _RAND_77 = {1{`RANDOM}}; + buf_dualhi_0 = _RAND_77[0:0]; + _RAND_78 = {1{`RANDOM}}; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; + _RAND_81 = {1{`RANDOM}}; + buf_rspageQ_0 = _RAND_81[3:0]; + _RAND_82 = {1{`RANDOM}}; + buf_rspageQ_1 = _RAND_82[3:0]; + _RAND_83 = {1{`RANDOM}}; + buf_rspageQ_2 = _RAND_83[3:0]; + _RAND_84 = {1{`RANDOM}}; + buf_rspageQ_3 = _RAND_84[3:0]; + _RAND_85 = {1{`RANDOM}}; + _T_4307 = _RAND_85[0:0]; + _RAND_86 = {1{`RANDOM}}; + _T_4305 = _RAND_86[0:0]; + _RAND_87 = {1{`RANDOM}}; + _T_4303 = _RAND_87[0:0]; + _RAND_88 = {1{`RANDOM}}; + _T_4301 = _RAND_88[0:0]; + _RAND_89 = {1{`RANDOM}}; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + buf_ldfwdtag_3 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + buf_ldfwdtag_2 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + buf_ldfwdtag_1 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + buf_dualtag_1 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + buf_dualtag_2 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + buf_dualtag_3 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + _T_4336 = _RAND_97[0:0]; + _RAND_98 = {1{`RANDOM}}; + _T_4339 = _RAND_98[0:0]; + _RAND_99 = {1{`RANDOM}}; + _T_4342 = _RAND_99[0:0]; + _RAND_100 = {1{`RANDOM}}; + _T_4345 = _RAND_100[0:0]; + _RAND_101 = {1{`RANDOM}}; + _T_4411 = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + _T_4406 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + _T_4401 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + _T_4396 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + _T_4984 = _RAND_106[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_addr_0 = 32'h0; + end + if (reset) begin + _T_4360 = 1'h0; + end + if (reset) begin + _T_4357 = 1'h0; + end + if (reset) begin + _T_4354 = 1'h0; + end + if (reset) begin + _T_4351 = 1'h0; + end + if (reset) begin + buf_state_0 = 3'h0; + end + if (reset) begin + buf_addr_1 = 32'h0; + end + if (reset) begin + buf_state_1 = 3'h0; + end + if (reset) begin + buf_addr_2 = 32'h0; + end + if (reset) begin + buf_state_2 = 3'h0; + end + if (reset) begin + buf_addr_3 = 32'h0; + end + if (reset) begin + buf_state_3 = 3'h0; + end + if (reset) begin + buf_byteen_3 = 4'h0; + end + if (reset) begin + buf_byteen_2 = 4'h0; + end + if (reset) begin + buf_byteen_1 = 4'h0; + end + if (reset) begin + buf_byteen_0 = 4'h0; + end + if (reset) begin + buf_ageQ_3 = 4'h0; + end + if (reset) begin + _T_1848 = 2'h0; + end + if (reset) begin + obuf_merge = 1'h0; + end + if (reset) begin + obuf_tag1 = 2'h0; + end + if (reset) begin + obuf_valid = 1'h0; + end + if (reset) begin + obuf_wr_enQ = 1'h0; + end + if (reset) begin + ibuf_addr = 32'h0; + end + if (reset) begin + ibuf_write = 1'h0; + end + if (reset) begin + ibuf_valid = 1'h0; + end + if (reset) begin + ibuf_byteen = 4'h0; + end + if (reset) begin + buf_ageQ_2 = 4'h0; + end + if (reset) begin + buf_ageQ_1 = 4'h0; + end + if (reset) begin + buf_ageQ_0 = 4'h0; + end + if (reset) begin + buf_data_0 = 32'h0; + end + if (reset) begin + buf_data_1 = 32'h0; + end + if (reset) begin + buf_data_2 = 32'h0; + end + if (reset) begin + buf_data_3 = 32'h0; + end + if (reset) begin + ibuf_data = 32'h0; + end + if (reset) begin + ibuf_timer = 3'h0; + end + if (reset) begin + ibuf_sideeffect = 1'h0; + end + if (reset) begin + WrPtr1_r = 2'h0; + end + if (reset) begin + WrPtr0_r = 2'h0; + end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end + if (reset) begin + ibuf_dual = 1'h0; + end + if (reset) begin + ibuf_samedw = 1'h0; + end + if (reset) begin + ibuf_nomerge = 1'h0; + end + if (reset) begin + ibuf_unsign = 1'h0; + end + if (reset) begin + ibuf_sz = 2'h0; + end + if (reset) begin + obuf_wr_timer = 3'h0; + end + if (reset) begin + buf_nomerge_0 = 1'h0; + end + if (reset) begin + buf_nomerge_1 = 1'h0; + end + if (reset) begin + buf_nomerge_2 = 1'h0; + end + if (reset) begin + buf_nomerge_3 = 1'h0; + end + if (reset) begin + _T_4330 = 1'h0; + end + if (reset) begin + _T_4327 = 1'h0; + end + if (reset) begin + _T_4324 = 1'h0; + end + if (reset) begin + _T_4321 = 1'h0; + end + if (reset) begin + buf_dual_3 = 1'h0; + end + if (reset) begin + buf_dual_2 = 1'h0; + end + if (reset) begin + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; + end + if (reset) begin + buf_samedw_2 = 1'h0; + end + if (reset) begin + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; + end + if (reset) begin + obuf_write = 1'h0; + end + if (reset) begin + obuf_cmd_done = 1'h0; + end + if (reset) begin + obuf_data_done = 1'h0; + end + if (reset) begin + obuf_nosend = 1'h0; + end + if (reset) begin + obuf_addr = 32'h0; + end + if (reset) begin + buf_sz_0 = 2'h0; + end + if (reset) begin + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; + end + if (reset) begin + obuf_rdrsp_pend = 1'h0; + end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end + if (reset) begin + buf_dualhi_3 = 1'h0; + end + if (reset) begin + buf_dualhi_2 = 1'h0; + end + if (reset) begin + buf_dualhi_1 = 1'h0; + end + if (reset) begin + buf_dualhi_0 = 1'h0; + end + if (reset) begin + obuf_sz = 2'h0; + end + if (reset) begin + obuf_byteen = 8'h0; + end + if (reset) begin + obuf_data = 64'h0; + end + if (reset) begin + buf_rspageQ_0 = 4'h0; + end + if (reset) begin + buf_rspageQ_1 = 4'h0; + end + if (reset) begin + buf_rspageQ_2 = 4'h0; + end + if (reset) begin + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4307 = 1'h0; + end + if (reset) begin + _T_4305 = 1'h0; + end + if (reset) begin + _T_4303 = 1'h0; + end + if (reset) begin + _T_4301 = 1'h0; + end + if (reset) begin + buf_ldfwdtag_0 = 2'h0; + end + if (reset) begin + buf_dualtag_0 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_3 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_2 = 2'h0; + end + if (reset) begin + buf_ldfwdtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_1 = 2'h0; + end + if (reset) begin + buf_dualtag_2 = 2'h0; + end + if (reset) begin + buf_dualtag_3 = 2'h0; + end + if (reset) begin + _T_4336 = 1'h0; + end + if (reset) begin + _T_4339 = 1'h0; + end + if (reset) begin + _T_4342 = 1'h0; + end + if (reset) begin + _T_4345 = 1'h0; + end + if (reset) begin + _T_4411 = 1'h0; + end + if (reset) begin + _T_4406 = 1'h0; + end + if (reset) begin + _T_4401 = 1'h0; + end + if (reset) begin + _T_4396 = 1'h0; + end + if (reset) begin + lsu_nonblock_load_valid_r = 1'h0; + end + if (reset) begin + _T_4984 = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3343) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4360 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4360 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4357 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4357 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4354 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4354 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4351 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4351 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3528) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3551) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3555) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3559) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3589) begin + if (_T_3594) begin + buf_state_0 <= 3'h0; + end else if (_T_3602) begin + buf_state_0 <= 3'h4; + end else if (_T_3630) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3676) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3682) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3694) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3352) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3721) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3744) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3748) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3559) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3782) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3869) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3875) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3887) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3361) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3914) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3937) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3941) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3559) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3975) begin + if (_T_3980) begin + buf_state_2 <= 3'h0; + end else if (_T_3988) begin + buf_state_2 <= 3'h4; + end else if (_T_4016) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4062) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4068) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4080) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3370) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4107) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4130) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4134) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3559) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4168) begin + if (_T_4173) begin + buf_state_3 <= 3'h0; + end else if (_T_4181) begin + buf_state_3 <= 3'h4; + end else if (_T_4209) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4255) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4261) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4273) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3370) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3361) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3352) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3343) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2535,_T_2458}; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + _T_1848 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1848 <= WrPtr0_r; + end else begin + _T_1848 <= CmdPtr0; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= 2'h0; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1839 & _T_1840; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_addr <= 32'h0; + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_write <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_write <= io_lsu_pkt_r_store; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_valid <= 1'h0; + end else begin + ibuf_valid <= _T_1005 & _T_1006; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_byteen <= 4'h0; + end else if (ibuf_wr_en) begin + if (_T_866) begin + ibuf_byteen <= _T_881; + end else if (io_ldst_dual_r) begin + ibuf_byteen <= ldst_byteen_hi_r; + end else begin + ibuf_byteen <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_2 <= 4'h0; + end else begin + buf_ageQ_2 <= {_T_2433,_T_2356}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_1 <= 4'h0; + end else begin + buf_ageQ_1 <= {_T_2331,_T_2254}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_0 <= 4'h0; + end else begin + buf_ageQ_0 <= {_T_2229,_T_2152}; + end + end + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_0 <= 32'h0; + end else if (_T_3528) begin + if (_T_3543) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3551) begin + buf_data_0 <= 32'h0; + end else if (_T_3555) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3589) begin + if (_T_3669) begin + if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_0 <= 32'h0; + end + end + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_1 <= 32'h0; + end else if (_T_3721) begin + if (_T_3736) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3744) begin + buf_data_1 <= 32'h0; + end else if (_T_3748) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3782) begin + if (_T_3862) begin + if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_1 <= 32'h0; + end + end + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_2 <= 32'h0; + end else if (_T_3914) begin + if (_T_3929) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3937) begin + buf_data_2 <= 32'h0; + end else if (_T_3941) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3975) begin + if (_T_4055) begin + if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_2 <= 32'h0; + end + end + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin + if (reset) begin + buf_data_3 <= 32'h0; + end else if (_T_4107) begin + if (_T_4122) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4130) begin + buf_data_3 <= 32'h0; + end else if (_T_4134) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_4168) begin + if (_T_4248) begin + if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end + end else begin + buf_data_3 <= 32'h0; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_922,_T_893}; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + ibuf_timer <= 3'h0; + end else if (ibuf_wr_en) begin + ibuf_timer <= 3'h0; + end else if (_T_923) begin + ibuf_timer <= _T_926; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sideeffect <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_sideeffect <= io_is_sideeffects_r; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1914) begin + WrPtr1_r <= 2'h0; + end else if (_T_1928) begin + WrPtr1_r <= 2'h1; + end else if (_T_1942) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1863) begin + WrPtr0_r <= 2'h0; + end else if (_T_1874) begin + WrPtr0_r <= 2'h1; + end else if (_T_1885) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_tag <= 2'h0; + end else if (ibuf_wr_en) begin + if (!(_T_866)) begin + if (io_ldst_dual_r) begin + ibuf_tag <= WrPtr1_r; + end else begin + ibuf_tag <= WrPtr0_r; + end + end + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_dual <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_dual <= io_ldst_dual_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_samedw <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_samedw <= ldst_samedw_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_nomerge <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_nomerge <= io_no_dword_merge_r; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_unsign <= 1'h0; + end else if (ibuf_wr_en) begin + ibuf_unsign <= io_lsu_pkt_r_unsign; + end + end + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + if (reset) begin + ibuf_sz <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_sz <= ibuf_sz_in; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_timer <= 3'h0; + end else if (obuf_wr_en) begin + obuf_wr_timer <= 3'h0; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_nomerge_0 <= buf_nomerge_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_nomerge_1 <= buf_nomerge_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_nomerge_2 <= buf_nomerge_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_nomerge_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_nomerge_3 <= buf_nomerge_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4330 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4330 <= buf_sideeffect_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4327 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4327 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4324 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4324 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4321 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4321 <= buf_sideeffect_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dual_3 <= buf_dual_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_write <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_write <= io_lsu_pkt_r_store; + end else begin + obuf_write <= _T_1202; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_cmd_done <= 1'h0; + end else begin + obuf_cmd_done <= _T_1305 & _T_4860; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_data_done <= 1'h0; + end else begin + obuf_data_done <= _T_1305 & _T_4861; + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_nosend <= 1'h0; + end else if (obuf_wr_en) begin + obuf_nosend <= obuf_nosend_in; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1289; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; + end else begin + buf_sz_0 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_sz_1 <= ibuf_sz; + end else begin + buf_sz_1 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; + end else begin + buf_sz_2 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_pend <= 1'h0; + end else begin + obuf_rdrsp_pend <= _T_1330 | _T_1334; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1332) begin + obuf_rdrsp_tag <= obuf_tag0; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_3 <= 1'h0; + end else if (buf_wr_en_3) begin + buf_dualhi_3 <= buf_dualhi_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_dualhi_2 <= buf_dualhi_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dualhi_1 <= buf_dualhi_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualhi_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dualhi_0 <= buf_dualhi_in[0]; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sz <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sz <= ibuf_sz_in; + end else begin + obuf_sz <= _T_1302; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_byteen <= 8'h0; + end else if (obuf_wr_en) begin + obuf_byteen <= obuf_byteen_in; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + obuf_data <= 64'h0; + end else begin + obuf_data <= {_T_1620,_T_1579}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_0 <= 4'h0; + end else begin + buf_rspageQ_0 <= {_T_3173,_T_3162}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_1 <= 4'h0; + end else begin + buf_rspageQ_1 <= {_T_3188,_T_3177}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_2 <= 4'h0; + end else begin + buf_rspageQ_2 <= {_T_3203,_T_3192}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3218,_T_3207}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4307 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + _T_4307 <= 1'h0; + end else if (_T_4130) begin + _T_4307 <= 1'h0; + end else begin + _T_4307 <= _T_4134; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4305 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + _T_4305 <= 1'h0; + end else if (_T_3937) begin + _T_4305 <= 1'h0; + end else begin + _T_4305 <= _T_3941; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4303 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + _T_4303 <= 1'h0; + end else if (_T_3744) begin + _T_4303 <= 1'h0; + end else begin + _T_4303 <= _T_3748; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4301 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + _T_4301 <= 1'h0; + end else if (_T_3551) begin + _T_4301 <= 1'h0; + end else begin + _T_4301 <= _T_3555; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3551) begin + buf_ldfwdtag_0 <= 2'h0; + end else if (_T_3555) begin + buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_0 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_dualtag_0 <= ibuf_dualtag; + end else if (_T_3343) begin + buf_dualtag_0 <= WrPtr0_r; + end else begin + buf_dualtag_0 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4130) begin + buf_ldfwdtag_3 <= 2'h0; + end else if (_T_4134) begin + buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_3 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3937) begin + buf_ldfwdtag_2 <= 2'h0; + end else if (_T_3941) begin + buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_2 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3744) begin + buf_ldfwdtag_1 <= 2'h0; + end else if (_T_3748) begin + buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; + end else begin + buf_ldfwdtag_1 <= 2'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_1 <= 2'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_dualtag_1 <= ibuf_dualtag; + end else if (_T_3352) begin + buf_dualtag_1 <= WrPtr0_r; + end else begin + buf_dualtag_1 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_dualtag_2 <= ibuf_dualtag; + end else if (_T_3361) begin + buf_dualtag_2 <= WrPtr0_r; + end else begin + buf_dualtag_2 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dualtag_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_dualtag_3 <= ibuf_dualtag; + end else if (_T_3370) begin + buf_dualtag_3 <= WrPtr0_r; + end else begin + buf_dualtag_3 <= WrPtr1_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4336 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4336 <= buf_unsign_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4339 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4339 <= buf_unsign_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4342 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4342 <= buf_unsign_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4345 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4345 <= buf_unsign_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4411 <= 1'h0; + end else begin + _T_4411 <= _T_4408 & _T_4409; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4403 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4398 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4393 & _T_4394; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + lsu_nonblock_load_valid_r <= 1'h0; + end else begin + lsu_nonblock_load_valid_r <= io_lsu_nonblock_load_valid_m; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + _T_4984 <= 1'h0; + end else begin + _T_4984 <= _T_4981 & _T_4518; + end + end +endmodule +module el2_lsu_bus_intf( + input clock, + input reset, + input io_scan_mode, + input io_dec_tlu_external_ldfwd_disable, + input io_dec_tlu_wb_coalescing_disable, + input io_dec_tlu_sideeffect_posted_disable, + input io_lsu_c1_m_clk, + input io_lsu_c1_r_clk, + input io_lsu_c2_r_clk, + input io_lsu_bus_ibuf_c1_clk, + input io_lsu_bus_obuf_c1_clk, + input io_lsu_bus_buf_c1_clk, + input io_lsu_free_c2_clk, + input io_free_clk, + input io_lsu_busm_clk, + input io_dec_lsu_valid_raw_d, + input io_lsu_busreq_m, + input io_lsu_pkt_m_by, + input io_lsu_pkt_m_half, + input io_lsu_pkt_m_word, + input io_lsu_pkt_m_load, + input io_lsu_pkt_m_valid, + input io_lsu_pkt_r_by, + input io_lsu_pkt_r_half, + input io_lsu_pkt_r_word, + input io_lsu_pkt_r_load, + input io_lsu_pkt_r_store, + input io_lsu_pkt_r_unsign, + input io_lsu_pkt_r_valid, + input [31:0] io_lsu_addr_d, + input [31:0] io_lsu_addr_m, + input [31:0] io_lsu_addr_r, + input [31:0] io_end_addr_d, + input [31:0] io_end_addr_m, + input [31:0] io_end_addr_r, + input [31:0] io_store_data_r, + input io_dec_tlu_force_halt, + input io_lsu_commit_r, + input io_is_sideeffects_m, + input io_flush_m_up, + input io_flush_r, + output io_lsu_busreq_r, + output io_lsu_bus_buffer_pend_any, + output io_lsu_bus_buffer_full_any, + output io_lsu_bus_buffer_empty_any, + output [31:0] io_bus_read_data_m, + output io_lsu_imprecise_error_load_any, + output io_lsu_imprecise_error_store_any, + output [31:0] io_lsu_imprecise_error_addr_any, + output io_lsu_nonblock_load_valid_m, + output [1:0] io_lsu_nonblock_load_tag_m, + output io_lsu_nonblock_load_inv_r, + output [1:0] io_lsu_nonblock_load_inv_tag_r, + output io_lsu_nonblock_load_data_valid, + output io_lsu_nonblock_load_data_error, + output [1:0] io_lsu_nonblock_load_data_tag, + output [31:0] io_lsu_nonblock_load_data, + output io_lsu_pmu_bus_trxn, + output io_lsu_pmu_bus_misaligned, + output io_lsu_pmu_bus_error, + output io_lsu_pmu_bus_busy, + output io_lsu_axi_awvalid, + input io_lsu_axi_awready, + output [2:0] io_lsu_axi_awid, + output [31:0] io_lsu_axi_awaddr, + output [3:0] io_lsu_axi_awregion, + output [2:0] io_lsu_axi_awsize, + output [3:0] io_lsu_axi_awcache, + output io_lsu_axi_wvalid, + input io_lsu_axi_wready, + output [63:0] io_lsu_axi_wdata, + output [7:0] io_lsu_axi_wstrb, + input io_lsu_axi_bvalid, + input [1:0] io_lsu_axi_bresp, + input [2:0] io_lsu_axi_bid, + output io_lsu_axi_arvalid, + input io_lsu_axi_arready, + output [2:0] io_lsu_axi_arid, + output [31:0] io_lsu_axi_araddr, + output [3:0] io_lsu_axi_arregion, + output [2:0] io_lsu_axi_arsize, + output [3:0] io_lsu_axi_arcache, + input io_lsu_axi_rvalid, + input [2:0] io_lsu_axi_rid, + input [63:0] io_lsu_axi_rdata, + input io_lsu_bus_clk_en +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; +`endif // RANDOMIZE_REG_INIT + wire bus_buffer_clock; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_reset; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_scan_mode; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_store_data_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_no_word_merge_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_no_dword_merge_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ld_full_hit_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_flush_m_up; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_flush_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_is_sideeffects_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_d; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 167:39] + wire [63:0] bus_buffer_io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [63:0] bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 167:39] + wire [7:0] bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_bready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_rready; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] _T_3 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[el2_lsu_bus_intf.scala 278:51] + wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[el2_lsu_bus_intf.scala 279:71] + wire _T_18 = ~_T_17; // @[el2_lsu_bus_intf.scala 279:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[el2_lsu_bus_intf.scala 279:51] + reg ldst_dual_r; // @[el2_lsu_bus_intf.scala 324:33] + wire _T_20 = ~ldst_dual_r; // @[el2_lsu_bus_intf.scala 280:48] + wire _T_21 = io_lsu_busreq_r & _T_20; // @[el2_lsu_bus_intf.scala 280:46] + wire _T_22 = _T_21 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 280:61] + wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 280:102] + wire _T_24 = io_lsu_pkt_m_load | _T_23; // @[el2_lsu_bus_intf.scala 280:100] + wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 281:102] + wire _T_30 = io_lsu_pkt_m_load | _T_29; // @[el2_lsu_bus_intf.scala 281:100] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[el2_lsu_bus_intf.scala 283:49] + wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[el2_lsu_bus_intf.scala 283:49] + reg [3:0] ldst_byteen_r; // @[el2_lsu_bus_intf.scala 326:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_bus_intf.scala 284:49] + wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_intf.scala 284:49] + wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[el2_lsu_bus_intf.scala 285:52] + wire [62:0] _T_41 = _GEN_2 << _T_40; // @[el2_lsu_bus_intf.scala 285:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 283:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_intf.scala 286:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_intf.scala 287:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[el2_lsu_bus_intf.scala 284:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[el2_lsu_bus_intf.scala 288:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[el2_lsu_bus_intf.scala 289:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[el2_lsu_bus_intf.scala 285:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[el2_lsu_bus_intf.scala 291:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[el2_lsu_bus_intf.scala 292:46] + wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 293:51] + wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 293:76] + wire _T_52 = _T_51 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 293:97] + wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 293:118] + wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 294:51] + wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 294:76] + wire _T_58 = _T_57 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 294:97] + wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 294:118] + wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 295:51] + wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 295:76] + wire _T_64 = _T_63 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 295:97] + wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 295:118] + wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 296:51] + wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 296:76] + wire _T_70 = _T_69 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 296:97] + wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 296:118] + wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 298:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58] + wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 299:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58] + wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 300:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58] + wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 301:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58] + wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_bus_intf.scala 303:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 215:38] + wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[el2_lsu_bus_intf.scala 303:97] + wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58] + wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_bus_intf.scala 304:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 216:38] + wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[el2_lsu_bus_intf.scala 304:97] + wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58] + wire [7:0] _T_228 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_229 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_230 = _T_228 | _T_229; // @[Mux.scala 27:72] + wire [7:0] _T_236 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_237 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_238 = _T_236 | _T_237; // @[Mux.scala 27:72] + wire [7:0] _T_244 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_245 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_246 = _T_244 | _T_245; // @[Mux.scala 27:72] + wire [7:0] _T_252 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_253 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_254 = _T_252 | _T_253; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_254,_T_246,_T_238,_T_230}; // @[Cat.scala 29:58] + wire [7:0] _T_263 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_264 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_265 = _T_263 | _T_264; // @[Mux.scala 27:72] + wire [7:0] _T_271 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_272 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_273 = _T_271 | _T_272; // @[Mux.scala 27:72] + wire [7:0] _T_279 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_280 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_281 = _T_279 | _T_280; // @[Mux.scala 27:72] + wire [7:0] _T_287 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 217:38] + wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[el2_lsu_bus_intf.scala 309:54] + wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 218:38] + wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[el2_lsu_bus_intf.scala 310:54] + wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58] + wire _T_334 = ~ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_338 = ~ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_342 = ~ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_346 = ~ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_348 = _T_335 & _T_339; // @[el2_lsu_bus_intf.scala 311:111] + wire _T_349 = _T_348 & _T_343; // @[el2_lsu_bus_intf.scala 311:111] + wire ld_full_hit_lo_m = _T_349 & _T_347; // @[el2_lsu_bus_intf.scala 311:111] + wire _T_353 = ~ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_357 = ~ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_361 = ~ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_365 = ~ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_367 = _T_354 & _T_358; // @[el2_lsu_bus_intf.scala 312:111] + wire _T_368 = _T_367 & _T_362; // @[el2_lsu_bus_intf.scala 312:111] + wire ld_full_hit_hi_m = _T_368 & _T_366; // @[el2_lsu_bus_intf.scala 312:111] + wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[el2_lsu_bus_intf.scala 313:47] + wire _T_371 = _T_370 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 313:66] + wire _T_372 = _T_371 & io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 313:84] + wire _T_373 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 313:106] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[el2_lsu_bus_intf.scala 310:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[el2_lsu_bus_intf.scala 309:27] + wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_bus_intf.scala 314:83] + wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[el2_lsu_bus_intf.scala 314:83] + wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[el2_lsu_bus_intf.scala 314:76] + reg lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 318:32] + reg ldst_dual_m; // @[el2_lsu_bus_intf.scala 321:27] + reg is_sideeffects_r; // @[el2_lsu_bus_intf.scala 325:33] + el2_lsu_bus_buffer bus_buffer ( // @[el2_lsu_bus_intf.scala 167:39] + .clock(bus_buffer_clock), + .reset(bus_buffer_reset), + .io_scan_mode(bus_buffer_io_scan_mode), + .io_dec_tlu_external_ldfwd_disable(bus_buffer_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_wb_coalescing_disable(bus_buffer_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_sideeffect_posted_disable(bus_buffer_io_dec_tlu_sideeffect_posted_disable), + .io_dec_tlu_force_halt(bus_buffer_io_dec_tlu_force_halt), + .io_lsu_c2_r_clk(bus_buffer_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_buffer_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(bus_buffer_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_buffer_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_buffer_io_lsu_free_c2_clk), + .io_lsu_busm_clk(bus_buffer_io_lsu_busm_clk), + .io_dec_lsu_valid_raw_d(bus_buffer_io_dec_lsu_valid_raw_d), + .io_lsu_pkt_m_load(bus_buffer_io_lsu_pkt_m_load), + .io_lsu_pkt_m_valid(bus_buffer_io_lsu_pkt_m_valid), + .io_lsu_pkt_r_by(bus_buffer_io_lsu_pkt_r_by), + .io_lsu_pkt_r_half(bus_buffer_io_lsu_pkt_r_half), + .io_lsu_pkt_r_word(bus_buffer_io_lsu_pkt_r_word), + .io_lsu_pkt_r_load(bus_buffer_io_lsu_pkt_r_load), + .io_lsu_pkt_r_store(bus_buffer_io_lsu_pkt_r_store), + .io_lsu_pkt_r_unsign(bus_buffer_io_lsu_pkt_r_unsign), + .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), + .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), + .io_end_addr_r(bus_buffer_io_end_addr_r), + .io_store_data_r(bus_buffer_io_store_data_r), + .io_no_word_merge_r(bus_buffer_io_no_word_merge_r), + .io_no_dword_merge_r(bus_buffer_io_no_dword_merge_r), + .io_lsu_busreq_m(bus_buffer_io_lsu_busreq_m), + .io_ld_full_hit_m(bus_buffer_io_ld_full_hit_m), + .io_flush_m_up(bus_buffer_io_flush_m_up), + .io_flush_r(bus_buffer_io_flush_r), + .io_lsu_commit_r(bus_buffer_io_lsu_commit_r), + .io_is_sideeffects_r(bus_buffer_io_is_sideeffects_r), + .io_ldst_dual_d(bus_buffer_io_ldst_dual_d), + .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), + .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), + .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), + .io_lsu_axi_wready(bus_buffer_io_lsu_axi_wready), + .io_lsu_axi_bvalid(bus_buffer_io_lsu_axi_bvalid), + .io_lsu_axi_bresp(bus_buffer_io_lsu_axi_bresp), + .io_lsu_axi_bid(bus_buffer_io_lsu_axi_bid), + .io_lsu_axi_arready(bus_buffer_io_lsu_axi_arready), + .io_lsu_axi_rvalid(bus_buffer_io_lsu_axi_rvalid), + .io_lsu_axi_rid(bus_buffer_io_lsu_axi_rid), + .io_lsu_axi_rdata(bus_buffer_io_lsu_axi_rdata), + .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), + .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), + .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_buffer_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_buffer_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), + .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), + .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), + .io_lsu_imprecise_error_load_any(bus_buffer_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(bus_buffer_io_lsu_imprecise_error_store_any), + .io_lsu_imprecise_error_addr_any(bus_buffer_io_lsu_imprecise_error_addr_any), + .io_lsu_nonblock_load_valid_m(bus_buffer_io_lsu_nonblock_load_valid_m), + .io_lsu_nonblock_load_tag_m(bus_buffer_io_lsu_nonblock_load_tag_m), + .io_lsu_nonblock_load_inv_r(bus_buffer_io_lsu_nonblock_load_inv_r), + .io_lsu_nonblock_load_inv_tag_r(bus_buffer_io_lsu_nonblock_load_inv_tag_r), + .io_lsu_nonblock_load_data_valid(bus_buffer_io_lsu_nonblock_load_data_valid), + .io_lsu_nonblock_load_data_error(bus_buffer_io_lsu_nonblock_load_data_error), + .io_lsu_nonblock_load_data_tag(bus_buffer_io_lsu_nonblock_load_data_tag), + .io_lsu_nonblock_load_data(bus_buffer_io_lsu_nonblock_load_data), + .io_lsu_pmu_bus_trxn(bus_buffer_io_lsu_pmu_bus_trxn), + .io_lsu_pmu_bus_misaligned(bus_buffer_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_error(bus_buffer_io_lsu_pmu_bus_error), + .io_lsu_pmu_bus_busy(bus_buffer_io_lsu_pmu_bus_busy), + .io_lsu_axi_awvalid(bus_buffer_io_lsu_axi_awvalid), + .io_lsu_axi_awready(bus_buffer_io_lsu_axi_awready), + .io_lsu_axi_awid(bus_buffer_io_lsu_axi_awid), + .io_lsu_axi_awaddr(bus_buffer_io_lsu_axi_awaddr), + .io_lsu_axi_awregion(bus_buffer_io_lsu_axi_awregion), + .io_lsu_axi_awsize(bus_buffer_io_lsu_axi_awsize), + .io_lsu_axi_awcache(bus_buffer_io_lsu_axi_awcache), + .io_lsu_axi_wvalid(bus_buffer_io_lsu_axi_wvalid), + .io_lsu_axi_wdata(bus_buffer_io_lsu_axi_wdata), + .io_lsu_axi_wstrb(bus_buffer_io_lsu_axi_wstrb), + .io_lsu_axi_bready(bus_buffer_io_lsu_axi_bready), + .io_lsu_axi_arvalid(bus_buffer_io_lsu_axi_arvalid), + .io_lsu_axi_arid(bus_buffer_io_lsu_axi_arid), + .io_lsu_axi_araddr(bus_buffer_io_lsu_axi_araddr), + .io_lsu_axi_arregion(bus_buffer_io_lsu_axi_arregion), + .io_lsu_axi_arsize(bus_buffer_io_lsu_axi_arsize), + .io_lsu_axi_arcache(bus_buffer_io_lsu_axi_arcache), + .io_lsu_axi_rready(bus_buffer_io_lsu_axi_rready) + ); + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 210:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 211:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 212:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 213:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[el2_lsu_bus_intf.scala 315:27] + assign io_lsu_imprecise_error_load_any = bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 219:38] + assign io_lsu_imprecise_error_store_any = bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 220:38] + assign io_lsu_imprecise_error_addr_any = bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 221:38] + assign io_lsu_nonblock_load_valid_m = bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 222:38] + assign io_lsu_nonblock_load_tag_m = bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 223:38] + assign io_lsu_nonblock_load_inv_r = bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 224:38] + assign io_lsu_nonblock_load_inv_tag_r = bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 225:38] + assign io_lsu_nonblock_load_data_valid = bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 226:38] + assign io_lsu_nonblock_load_data_error = bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 227:38] + assign io_lsu_nonblock_load_data_tag = bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 228:38] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 229:38] + assign io_lsu_pmu_bus_trxn = bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 230:38] + assign io_lsu_pmu_bus_misaligned = bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 231:38] + assign io_lsu_pmu_bus_error = bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 232:38] + assign io_lsu_pmu_bus_busy = bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 233:38] + assign io_lsu_axi_awvalid = bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 234:38] + assign io_lsu_axi_awid = bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 235:38] + assign io_lsu_axi_awaddr = bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 236:38] + assign io_lsu_axi_awregion = bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 237:38] + assign io_lsu_axi_awsize = bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 239:38] + assign io_lsu_axi_awcache = bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 242:38] + assign io_lsu_axi_wvalid = bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 245:38] + assign io_lsu_axi_wdata = bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 246:38] + assign io_lsu_axi_wstrb = bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 247:38] + assign io_lsu_axi_arvalid = bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 250:38] + assign io_lsu_axi_arid = bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 251:38] + assign io_lsu_axi_araddr = bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 252:38] + assign io_lsu_axi_arregion = bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 253:38] + assign io_lsu_axi_arsize = bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 255:38] + assign io_lsu_axi_arcache = bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 258:38] + assign bus_buffer_clock = clock; + assign bus_buffer_reset = reset; + assign bus_buffer_io_scan_mode = io_scan_mode; // @[el2_lsu_bus_intf.scala 169:29] + assign bus_buffer_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 171:51] + assign bus_buffer_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 172:51] + assign bus_buffer_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 173:51] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 174:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 175:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 176:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 177:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 178:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 179:51] + assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 180:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 181:51] + assign bus_buffer_io_lsu_pkt_m_load = io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 184:27] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 184:27] + assign bus_buffer_io_lsu_pkt_r_by = io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_half = io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_word = io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_load = io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_store = io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_unsign = io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 188:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[el2_lsu_bus_intf.scala 189:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 190:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[el2_lsu_bus_intf.scala 191:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[el2_lsu_bus_intf.scala 192:51] + assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[el2_lsu_bus_intf.scala 263:51] + assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[el2_lsu_bus_intf.scala 264:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 194:51] + assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[el2_lsu_bus_intf.scala 270:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[el2_lsu_bus_intf.scala 195:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[el2_lsu_bus_intf.scala 196:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 197:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[el2_lsu_bus_intf.scala 265:51] + assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_bus_intf.scala 266:51] + assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[el2_lsu_bus_intf.scala 267:51] + assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[el2_lsu_bus_intf.scala 268:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 269:51] + assign bus_buffer_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 199:51] + assign bus_buffer_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 200:51] + assign bus_buffer_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 201:51] + assign bus_buffer_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 202:51] + assign bus_buffer_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 203:51] + assign bus_buffer_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 204:51] + assign bus_buffer_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 205:51] + assign bus_buffer_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 206:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 208:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 271:51] + assign bus_buffer_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 198:51] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ldst_dual_r = _RAND_0[0:0]; + _RAND_1 = {1{`RANDOM}}; + ldst_byteen_r = _RAND_1[3:0]; + _RAND_2 = {1{`RANDOM}}; + lsu_bus_clk_en_q = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ldst_dual_m = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + is_sideeffects_r = _RAND_4[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ldst_dual_r = 1'h0; + end + if (reset) begin + ldst_byteen_r = 4'h0; + end + if (reset) begin + lsu_bus_clk_en_q = 1'h0; + end + if (reset) begin + ldst_dual_m = 1'h0; + end + if (reset) begin + is_sideeffects_r = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_dual_r <= 1'h0; + end else begin + ldst_dual_r <= ldst_dual_m; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + ldst_byteen_r <= 4'h0; + end else begin + ldst_byteen_r <= _T_6 | _T_5; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + lsu_bus_clk_en_q <= 1'h0; + end else begin + lsu_bus_clk_en_q <= io_lsu_bus_clk_en; + end + end + always @(posedge io_lsu_c1_m_clk or posedge reset) begin + if (reset) begin + ldst_dual_m <= 1'h0; + end else begin + ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2]; + end + end + always @(posedge io_lsu_c1_r_clk or posedge reset) begin + if (reset) begin + is_sideeffects_r <= 1'h0; + end else begin + is_sideeffects_r <= io_is_sideeffects_m; + end + end endmodule module el2_lsu( input clock, @@ -3979,19 +10340,21 @@ module el2_lsu( input [31:0] io_trigger_pkt_any_3_tdata2, input io_dec_lsu_valid_raw_d, input [31:0] io_dec_tlu_mrac_ff, + output [31:0] io_lsu_result_m, + output [31:0] io_lsu_result_corr_r, output io_lsu_load_stall_any, output io_lsu_store_stall_any, output io_lsu_fastint_stall_any, output io_lsu_idle_any, - output [31:0] io_lsu_fir_addr, + output [30:0] io_lsu_fir_addr, output [1:0] io_lsu_fir_error, output io_lsu_single_ecc_error_incr, output io_lsu_error_pkt_r_exc_valid, output io_lsu_error_pkt_r_single_ecc_error, output io_lsu_error_pkt_r_inst_type, output io_lsu_error_pkt_r_exc_type, - output [3:0] io_lsu_error_pkt_r_mscause, - output [31:0] io_lsu_error_pkt_r_addr, + output io_lsu_error_pkt_r_mscause, + output io_lsu_error_pkt_r_addr, output io_lsu_imprecise_error_load_any, output io_lsu_imprecise_error_store_any, output [31:0] io_lsu_imprecise_error_addr_any, @@ -4087,347 +10450,486 @@ module el2_lsu( reg [31:0] _RAND_1; reg [31:0] _RAND_2; `endif // RANDOMIZE_REG_INIT - wire lsu_lsc_ctl_clock; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_reset; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_flush_m_up; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_flush_r; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs1_d; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs2_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_fast_int; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_by; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_half; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_word; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_dword; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_load; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_store; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_unsign; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_dma; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_store_data_bypass_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_load_ldst_bypass_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_store_data_bypass_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_p_valid; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 153:30] - wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_exc_valid; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_single_ecc_error; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_inst_type; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_error_pkt_r_exc_type; // @[el2_lsu.scala 153:30] - wire [3:0] lsu_lsc_ctl_io_lsu_error_pkt_r_mscause; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_error_pkt_r_addr; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_dma_dccm_req; // @[el2_lsu.scala 153:30] - wire [31:0] lsu_lsc_ctl_io_dma_mem_addr; // @[el2_lsu.scala 153:30] - wire [2:0] lsu_lsc_ctl_io_dma_mem_sz; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_dma_mem_write; // @[el2_lsu.scala 153:30] - wire [63:0] lsu_lsc_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_fast_int; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_by; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_half; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_unsign; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_store_data_bypass_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_load_ldst_bypass_d; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_store_data_bypass_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_fast_int; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_dword; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_unsign; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_store_data_bypass_m; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_dword; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_unsign; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 153:30] - wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 153:30] - wire dccm_ctl_reset; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_c2_m_clk; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_c2_r_clk; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_free_c2_clk; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_clk; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_commit_r; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_lsu_addr_d; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_lsu_addr_m; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_lsu_addr_r; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_end_addr_d; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_end_addr_m; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_end_addr_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_stbuf_reqvld_any; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_stbuf_data_any; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 154:30] - wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 154:30] - wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_single_ecc_error_hi_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_single_ecc_error_lo_r; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[el2_lsu.scala 154:30] - wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 154:30] - wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_store_data_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dma_dccm_wen; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dma_pic_wen; // @[el2_lsu.scala 154:30] - wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_dma_mem_addr; // @[el2_lsu.scala 154:30] - wire [63:0] dccm_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_store_data_hi_r; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_store_data_lo_r; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_lsu_dccm_rden_m; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 154:30] - wire [2:0] dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 154:30] - wire [63:0] dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 154:30] - wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 154:30] - wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 154:30] - wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 154:30] - wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 154:30] - wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_picm_wren; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_picm_rden; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_picm_mken; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 154:30] - wire [31:0] dccm_ctl_io_picm_rd_data; // @[el2_lsu.scala 154:30] - wire dccm_ctl_io_scan_mode; // @[el2_lsu.scala 154:30] - wire stbuf_clock; // @[el2_lsu.scala 155:30] - wire stbuf_reset; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_c1_m_clk; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_c1_r_clk; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_free_c2_clk; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_m_store; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_m_dma; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_m_valid; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_by; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_half; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_word; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_dword; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_store; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_dma; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_pkt_r_valid; // @[el2_lsu.scala 155:30] - wire stbuf_io_store_stbuf_reqvld_r; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_commit_r; // @[el2_lsu.scala 155:30] - wire stbuf_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_store_data_hi_r; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_store_data_lo_r; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_store_datafn_hi_r; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_store_datafn_lo_r; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 155:30] - wire [15:0] stbuf_io_lsu_addr_d; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_lsu_addr_m; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_lsu_addr_r; // @[el2_lsu.scala 155:30] - wire [15:0] stbuf_io_end_addr_d; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_end_addr_m; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_end_addr_r; // @[el2_lsu.scala 155:30] - wire stbuf_io_addr_in_dccm_m; // @[el2_lsu.scala 155:30] - wire stbuf_io_addr_in_dccm_r; // @[el2_lsu.scala 155:30] - wire stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 155:30] - wire stbuf_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 155:30] - wire [15:0] stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_stbuf_data_any; // @[el2_lsu.scala 155:30] - wire stbuf_io_lsu_stbuf_full_any; // @[el2_lsu.scala 155:30] - wire stbuf_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 155:30] - wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 155:30] - wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 155:30] - wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 155:30] - wire ecc_clock; // @[el2_lsu.scala 156:30] - wire ecc_reset; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_c2_r_clk; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_pkt_m_load; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_pkt_m_store; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_pkt_m_dma; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_pkt_m_valid; // @[el2_lsu.scala 156:30] - wire ecc_io_dec_tlu_core_ecc_disable; // @[el2_lsu.scala 156:30] - wire [15:0] ecc_io_lsu_addr_m; // @[el2_lsu.scala 156:30] - wire [15:0] ecc_io_end_addr_m; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_dccm_rdata_hi_m; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_dccm_rdata_lo_m; // @[el2_lsu.scala 156:30] - wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 156:30] - wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 156:30] - wire ecc_io_ld_single_ecc_error_r; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_dccm_rden_m; // @[el2_lsu.scala 156:30] - wire ecc_io_addr_in_dccm_m; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_hi_r; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_lo_r; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_hi_m; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_lo_m; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 156:30] - wire [31:0] ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 156:30] - wire ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 156:30] - wire ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 156:30] - wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 156:30] - wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 157:30] - wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_half; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_word; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_load; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_store; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_dma; // @[el2_lsu.scala 157:30] - wire trigger_io_lsu_pkt_m_valid; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_lsu_addr_m; // @[el2_lsu.scala 157:30] - wire [31:0] trigger_io_store_data_m; // @[el2_lsu.scala 157:30] - wire [3:0] trigger_io_lsu_trigger_match_m; // @[el2_lsu.scala 157:30] - wire clkdomain_clock; // @[el2_lsu.scala 158:30] - wire clkdomain_reset; // @[el2_lsu.scala 158:30] - wire clkdomain_io_clk_override; // @[el2_lsu.scala 158:30] - wire clkdomain_io_dma_dccm_req; // @[el2_lsu.scala 158:30] - wire clkdomain_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 158:30] - wire clkdomain_io_stbuf_reqvld_any; // @[el2_lsu.scala 158:30] - wire clkdomain_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_bus_clk_en; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_p_valid; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_pkt_d_store; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_pkt_d_valid; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_pkt_m_store; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_pkt_m_valid; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 158:30] - wire clkdomain_io_scan_mode; // @[el2_lsu.scala 158:30] - wire _T = stbuf_io_lsu_stbuf_full_any; // @[el2_lsu.scala 165:57] - wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 172:58] - wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[el2_lsu.scala 172:56] - wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 172:121] - wire _T_6 = _T_4 & _T_5; // @[el2_lsu.scala 172:88] - wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 172:153] - wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[el2_lsu.scala 173:45] - wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 173:63] - wire _T_10 = io_dma_dccm_req & io_dma_mem_write; // @[el2_lsu.scala 174:38] + wire lsu_lsc_ctl_reset; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_c1_m_clk; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_c1_r_clk; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_c2_m_clk; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_c2_r_clk; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_flush_m_up; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_flush_r; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs1_d; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_exu_lsu_rs2_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_fast_int; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_by; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_half; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_word; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_dword; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_load; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_store; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_unsign; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_dma; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_store_data_bypass_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_load_ldst_bypass_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_store_data_bypass_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_p_valid; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 154:30] + wire [11:0] lsu_lsc_ctl_io_dec_lsu_offset_d; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_bus_read_data_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_result_corr_r; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_d; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_dec_tlu_mrac_ff; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_exc_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_is_sideeffects_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_exc_valid; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_single_ecc_error; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_inst_type; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_exc_type; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_mscause; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_error_pkt_r_addr; // @[el2_lsu.scala 154:30] + wire [30:0] lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 154:30] + wire [1:0] lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_dma_dccm_req; // @[el2_lsu.scala 154:30] + wire [31:0] lsu_lsc_ctl_io_dma_mem_addr; // @[el2_lsu.scala 154:30] + wire [2:0] lsu_lsc_ctl_io_dma_mem_sz; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_dma_mem_write; // @[el2_lsu.scala 154:30] + wire [63:0] lsu_lsc_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_fast_int; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_by; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_half; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_unsign; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_store_data_bypass_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_load_ldst_bypass_d; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_store_data_bypass_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_fast_int; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_dword; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_unsign; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_store_data_bypass_m; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_dword; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_unsign; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 154:30] + wire lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 154:30] + wire dccm_ctl_clock; // @[el2_lsu.scala 157:30] + wire dccm_ctl_reset; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_c2_m_clk; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_c2_r_clk; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_free_c2_clk; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_store_c1_r_clk; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_raw_fwd_lo_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_raw_fwd_hi_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_commit_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_lsu_addr_d; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_lsu_addr_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_lsu_addr_r; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_end_addr_d; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_end_addr_m; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_end_addr_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_stbuf_reqvld_any; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_stbuf_addr_any; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_stbuf_data_any; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_stbuf_ecc_any; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 157:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 157:30] + wire [3:0] dccm_ctl_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_single_ecc_error_hi_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_single_ecc_error_lo_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_sec_data_hi_r_ff; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_sec_data_lo_r_ff; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_dccm_rdata_hi_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_dccm_rdata_lo_m; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_sec_data_hi_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_sec_data_lo_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_data_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dma_dccm_wen; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dma_pic_wen; // @[el2_lsu.scala 157:30] + wire [2:0] dccm_ctl_io_dma_mem_tag_m; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_dma_mem_addr; // @[el2_lsu.scala 157:30] + wire [63:0] dccm_ctl_io_dma_mem_wdata; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_lo; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_dma_dccm_wdata_hi; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 157:30] + wire [6:0] dccm_ctl_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_data_hi_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_data_lo_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_datafn_lo_r; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_store_data_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_lsu_dccm_rden_m; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 157:30] + wire [2:0] dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 157:30] + wire [63:0] dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 157:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 157:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_lo; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 157:30] + wire [38:0] dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 157:30] + wire [15:0] dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 157:30] + wire [38:0] dccm_ctl_io_dccm_rd_data_hi; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_picm_wren; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_picm_rden; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_picm_mken; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 157:30] + wire [31:0] dccm_ctl_io_picm_rd_data; // @[el2_lsu.scala 157:30] + wire dccm_ctl_io_scan_mode; // @[el2_lsu.scala 157:30] + wire stbuf_clock; // @[el2_lsu.scala 158:30] + wire stbuf_reset; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_c1_m_clk; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_c1_r_clk; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_free_c2_clk; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_m_store; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_m_dma; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_m_valid; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_by; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_half; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_word; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_dword; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_store; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_dma; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_pkt_r_valid; // @[el2_lsu.scala 158:30] + wire stbuf_io_store_stbuf_reqvld_r; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_commit_r; // @[el2_lsu.scala 158:30] + wire stbuf_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_store_data_hi_r; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_store_data_lo_r; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_store_datafn_hi_r; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_store_datafn_lo_r; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 158:30] + wire [15:0] stbuf_io_lsu_addr_d; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_lsu_addr_m; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_lsu_addr_r; // @[el2_lsu.scala 158:30] + wire [15:0] stbuf_io_end_addr_d; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_end_addr_m; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_end_addr_r; // @[el2_lsu.scala 158:30] + wire stbuf_io_addr_in_dccm_m; // @[el2_lsu.scala 158:30] + wire stbuf_io_addr_in_dccm_r; // @[el2_lsu.scala 158:30] + wire stbuf_io_scan_mode; // @[el2_lsu.scala 158:30] + wire stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 158:30] + wire stbuf_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 158:30] + wire [15:0] stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_stbuf_data_any; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_stbuf_full_any; // @[el2_lsu.scala 158:30] + wire stbuf_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 158:30] + wire stbuf_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 158:30] + wire [31:0] stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 158:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 158:30] + wire [3:0] stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 158:30] + wire ecc_clock; // @[el2_lsu.scala 159:30] + wire ecc_reset; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_c2_r_clk; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_pkt_m_load; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_pkt_m_store; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_pkt_m_dma; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_pkt_m_valid; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_stbuf_data_any; // @[el2_lsu.scala 159:30] + wire ecc_io_dec_tlu_core_ecc_disable; // @[el2_lsu.scala 159:30] + wire [15:0] ecc_io_lsu_addr_m; // @[el2_lsu.scala 159:30] + wire [15:0] ecc_io_end_addr_m; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_dccm_rdata_hi_m; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_dccm_rdata_lo_m; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 159:30] + wire ecc_io_ld_single_ecc_error_r; // @[el2_lsu.scala 159:30] + wire ecc_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_dccm_rden_m; // @[el2_lsu.scala 159:30] + wire ecc_io_addr_in_dccm_m; // @[el2_lsu.scala 159:30] + wire ecc_io_dma_dccm_wen; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_dma_dccm_wdata_lo; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_dma_dccm_wdata_hi; // @[el2_lsu.scala 159:30] + wire ecc_io_scan_mode; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_hi_r; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_lo_r; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_hi_m; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_lo_m; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 159:30] + wire [31:0] ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_stbuf_ecc_any; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 159:30] + wire [6:0] ecc_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 159:30] + wire ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 159:30] + wire ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 159:30] + wire ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 159:30] + wire trigger_io_trigger_pkt_any_0_select; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_store; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_0_load; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_trigger_pkt_any_0_tdata2; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_select; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_store; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_1_load; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_trigger_pkt_any_1_tdata2; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_select; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_store; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_2_load; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_trigger_pkt_any_2_tdata2; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_select; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_match_; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_store; // @[el2_lsu.scala 160:30] + wire trigger_io_trigger_pkt_any_3_load; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_trigger_pkt_any_3_tdata2; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_half; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_word; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_load; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_store; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_dma; // @[el2_lsu.scala 160:30] + wire trigger_io_lsu_pkt_m_valid; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_lsu_addr_m; // @[el2_lsu.scala 160:30] + wire [31:0] trigger_io_store_data_m; // @[el2_lsu.scala 160:30] + wire [3:0] trigger_io_lsu_trigger_match_m; // @[el2_lsu.scala 160:30] + wire clkdomain_clock; // @[el2_lsu.scala 161:30] + wire clkdomain_reset; // @[el2_lsu.scala 161:30] + wire clkdomain_io_free_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_clk_override; // @[el2_lsu.scala 161:30] + wire clkdomain_io_dma_dccm_req; // @[el2_lsu.scala 161:30] + wire clkdomain_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 161:30] + wire clkdomain_io_stbuf_reqvld_any; // @[el2_lsu.scala 161:30] + wire clkdomain_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_busreq_r; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_clk_en; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_p_valid; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_pkt_d_store; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_pkt_d_valid; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_pkt_m_store; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_pkt_m_valid; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_pkt_r_valid; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_busm_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 161:30] + wire clkdomain_io_scan_mode; // @[el2_lsu.scala 161:30] + wire bus_intf_clock; // @[el2_lsu.scala 162:30] + wire bus_intf_reset; // @[el2_lsu.scala 162:30] + wire bus_intf_io_scan_mode; // @[el2_lsu.scala 162:30] + wire bus_intf_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu.scala 162:30] + wire bus_intf_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu.scala 162:30] + wire bus_intf_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_c1_m_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_c1_r_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_c2_r_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_free_c2_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_free_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_busm_clk; // @[el2_lsu.scala 162:30] + wire bus_intf_io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_busreq_m; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_m_by; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_m_half; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_m_word; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_m_load; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_m_valid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_by; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_half; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_word; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_load; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_store; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_unsign; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pkt_r_valid; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_addr_d; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_addr_m; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_addr_r; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_end_addr_d; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_end_addr_m; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_end_addr_r; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_store_data_r; // @[el2_lsu.scala 162:30] + wire bus_intf_io_dec_tlu_force_halt; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_commit_r; // @[el2_lsu.scala 162:30] + wire bus_intf_io_is_sideeffects_m; // @[el2_lsu.scala 162:30] + wire bus_intf_io_flush_m_up; // @[el2_lsu.scala 162:30] + wire bus_intf_io_flush_r; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_busreq_r; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_buffer_full_any; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_bus_read_data_m; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_imprecise_error_load_any; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_imprecise_error_store_any; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_imprecise_error_addr_any; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_nonblock_load_valid_m; // @[el2_lsu.scala 162:30] + wire [1:0] bus_intf_io_lsu_nonblock_load_tag_m; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_nonblock_load_inv_r; // @[el2_lsu.scala 162:30] + wire [1:0] bus_intf_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_nonblock_load_data_valid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_nonblock_load_data_error; // @[el2_lsu.scala 162:30] + wire [1:0] bus_intf_io_lsu_nonblock_load_data_tag; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_nonblock_load_data; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pmu_bus_trxn; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pmu_bus_misaligned; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pmu_bus_error; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_pmu_bus_busy; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_awvalid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_awready; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_awid; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_axi_awaddr; // @[el2_lsu.scala 162:30] + wire [3:0] bus_intf_io_lsu_axi_awregion; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_awsize; // @[el2_lsu.scala 162:30] + wire [3:0] bus_intf_io_lsu_axi_awcache; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_wvalid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_wready; // @[el2_lsu.scala 162:30] + wire [63:0] bus_intf_io_lsu_axi_wdata; // @[el2_lsu.scala 162:30] + wire [7:0] bus_intf_io_lsu_axi_wstrb; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_bvalid; // @[el2_lsu.scala 162:30] + wire [1:0] bus_intf_io_lsu_axi_bresp; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_bid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_arvalid; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_arready; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_arid; // @[el2_lsu.scala 162:30] + wire [31:0] bus_intf_io_lsu_axi_araddr; // @[el2_lsu.scala 162:30] + wire [3:0] bus_intf_io_lsu_axi_arregion; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_arsize; // @[el2_lsu.scala 162:30] + wire [3:0] bus_intf_io_lsu_axi_arcache; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_axi_rvalid; // @[el2_lsu.scala 162:30] + wire [2:0] bus_intf_io_lsu_axi_rid; // @[el2_lsu.scala 162:30] + wire [63:0] bus_intf_io_lsu_axi_rdata; // @[el2_lsu.scala 162:30] + wire bus_intf_io_lsu_bus_clk_en; // @[el2_lsu.scala 162:30] + wire _T = stbuf_io_lsu_stbuf_full_any | bus_intf_io_lsu_bus_buffer_full_any; // @[el2_lsu.scala 168:57] + wire _T_3 = ~lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 175:58] + wire _T_4 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_3; // @[el2_lsu.scala 175:56] + wire _T_5 = lsu_lsc_ctl_io_addr_in_dccm_m | lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 175:121] + wire _T_6 = _T_4 & _T_5; // @[el2_lsu.scala 175:88] + wire ldst_nodma_mtor = _T_6 & lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 175:153] + wire _T_7 = io_dec_lsu_valid_raw_d | ldst_nodma_mtor; // @[el2_lsu.scala 176:45] + wire _T_8 = _T_7 | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 176:63] + wire _T_10 = io_dma_dccm_req & io_dma_mem_write; // @[el2_lsu.scala 177:38] wire [5:0] _T_13 = {io_dma_mem_addr[2:0],3'h0}; // @[Cat.scala 29:58] - wire [63:0] dma_dccm_wdata = io_dma_mem_wdata >> _T_13; // @[el2_lsu.scala 176:38] - wire _T_19 = ~lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 187:125] - wire _T_25 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 189:61] - wire _T_26 = _T_25 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 189:94] - wire _T_27 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 189:128] - wire _T_28 = _T_26 & _T_27; // @[el2_lsu.scala 189:126] - wire _T_42 = lsu_lsc_ctl_io_lsu_pkt_m_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[el2_lsu.scala 195:94] - wire _T_44 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[el2_lsu.scala 195:192] - wire _T_45 = lsu_lsc_ctl_io_lsu_pkt_m_word & _T_44; // @[el2_lsu.scala 195:159] - wire _T_46 = _T_42 | _T_45; // @[el2_lsu.scala 195:126] - wire _T_48 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 196:64] - wire _T_50 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 197:64] - reg [2:0] _T_52; // @[el2_lsu.scala 490:67] - reg lsu_raw_fwd_hi_r; // @[el2_lsu.scala 491:67] - reg lsu_raw_fwd_lo_r; // @[el2_lsu.scala 492:67] - wire [31:0] dma_mem_tag_m = {{29'd0}, _T_52}; // @[el2_lsu.scala 490:57] - el2_lsu_lsc_ctl lsu_lsc_ctl ( // @[el2_lsu.scala 153:30] - .clock(lsu_lsc_ctl_clock), + wire [63:0] dma_dccm_wdata = io_dma_mem_wdata >> _T_13; // @[el2_lsu.scala 179:38] + wire _T_19 = ~lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 190:125] + wire _T_20 = lsu_lsc_ctl_io_lsu_pkt_r_valid & _T_19; // @[el2_lsu.scala 190:123] + wire _T_21 = _T_4 | _T_20; // @[el2_lsu.scala 190:89] + wire _T_22 = ~_T_21; // @[el2_lsu.scala 190:22] + wire _T_25 = lsu_lsc_ctl_io_lsu_pkt_r_valid & lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 192:61] + wire _T_26 = _T_25 & lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 192:94] + wire _T_27 = ~io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 192:128] + wire _T_28 = _T_26 & _T_27; // @[el2_lsu.scala 192:126] + wire _T_30 = lsu_lsc_ctl_io_lsu_pkt_m_load | lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 194:85] + wire _T_34 = _T_30 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 196:121] + wire _T_35 = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_34; // @[el2_lsu.scala 196:53] + wire _T_36 = ~io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 196:157] + wire _T_37 = _T_35 & _T_36; // @[el2_lsu.scala 196:155] + wire _T_38 = ~lsu_lsc_ctl_io_lsu_exc_m; // @[el2_lsu.scala 196:171] + wire _T_39 = _T_37 & _T_38; // @[el2_lsu.scala 196:169] + wire _T_40 = ~lsu_lsc_ctl_io_lsu_pkt_m_fast_int; // @[el2_lsu.scala 196:199] + wire _T_42 = lsu_lsc_ctl_io_lsu_pkt_m_half & lsu_lsc_ctl_io_lsu_addr_m[0]; // @[el2_lsu.scala 198:95] + wire _T_44 = |lsu_lsc_ctl_io_lsu_addr_m[1:0]; // @[el2_lsu.scala 198:193] + wire _T_45 = lsu_lsc_ctl_io_lsu_pkt_m_word & _T_44; // @[el2_lsu.scala 198:160] + wire _T_46 = _T_42 | _T_45; // @[el2_lsu.scala 198:127] + wire _T_48 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 199:65] + wire _T_50 = lsu_lsc_ctl_io_lsu_pkt_m_valid & lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 200:65] + reg [2:0] dma_mem_tag_m; // @[el2_lsu.scala 492:67] + reg lsu_raw_fwd_hi_r; // @[el2_lsu.scala 493:67] + reg lsu_raw_fwd_lo_r; // @[el2_lsu.scala 494:67] + el2_lsu_lsc_ctl lsu_lsc_ctl ( // @[el2_lsu.scala 154:30] .reset(lsu_lsc_ctl_reset), + .io_lsu_c1_m_clk(lsu_lsc_ctl_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(lsu_lsc_ctl_io_lsu_c1_r_clk), + .io_lsu_c2_m_clk(lsu_lsc_ctl_io_lsu_c2_m_clk), + .io_lsu_c2_r_clk(lsu_lsc_ctl_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(lsu_lsc_ctl_io_lsu_store_c1_m_clk), .io_lsu_ld_data_corr_r(lsu_lsc_ctl_io_lsu_ld_data_corr_r), .io_lsu_single_ecc_error_r(lsu_lsc_ctl_io_lsu_single_ecc_error_r), .io_lsu_double_ecc_error_r(lsu_lsc_ctl_io_lsu_double_ecc_error_r), @@ -4454,7 +10956,9 @@ module el2_lsu( .io_dec_lsu_valid_raw_d(lsu_lsc_ctl_io_dec_lsu_valid_raw_d), .io_dec_lsu_offset_d(lsu_lsc_ctl_io_dec_lsu_offset_d), .io_picm_mask_data_m(lsu_lsc_ctl_io_picm_mask_data_m), + .io_bus_read_data_m(lsu_lsc_ctl_io_bus_read_data_m), .io_lsu_result_m(lsu_lsc_ctl_io_lsu_result_m), + .io_lsu_result_corr_r(lsu_lsc_ctl_io_lsu_result_corr_r), .io_lsu_addr_d(lsu_lsc_ctl_io_lsu_addr_d), .io_lsu_addr_m(lsu_lsc_ctl_io_lsu_addr_m), .io_lsu_addr_r(lsu_lsc_ctl_io_lsu_addr_r), @@ -4463,6 +10967,8 @@ module el2_lsu( .io_end_addr_r(lsu_lsc_ctl_io_end_addr_r), .io_store_data_m(lsu_lsc_ctl_io_store_data_m), .io_dec_tlu_mrac_ff(lsu_lsc_ctl_io_dec_tlu_mrac_ff), + .io_lsu_exc_m(lsu_lsc_ctl_io_lsu_exc_m), + .io_is_sideeffects_m(lsu_lsc_ctl_io_is_sideeffects_m), .io_lsu_commit_r(lsu_lsc_ctl_io_lsu_commit_r), .io_lsu_single_ecc_error_incr(lsu_lsc_ctl_io_lsu_single_ecc_error_incr), .io_lsu_error_pkt_r_exc_valid(lsu_lsc_ctl_io_lsu_error_pkt_r_exc_valid), @@ -4472,6 +10978,7 @@ module el2_lsu( .io_lsu_error_pkt_r_mscause(lsu_lsc_ctl_io_lsu_error_pkt_r_mscause), .io_lsu_error_pkt_r_addr(lsu_lsc_ctl_io_lsu_error_pkt_r_addr), .io_lsu_fir_addr(lsu_lsc_ctl_io_lsu_fir_addr), + .io_lsu_fir_error(lsu_lsc_ctl_io_lsu_fir_error), .io_addr_in_dccm_d(lsu_lsc_ctl_io_addr_in_dccm_d), .io_addr_in_dccm_m(lsu_lsc_ctl_io_addr_in_dccm_m), .io_addr_in_dccm_r(lsu_lsc_ctl_io_addr_in_dccm_r), @@ -4518,13 +11025,13 @@ module el2_lsu( .io_lsu_pkt_r_dma(lsu_lsc_ctl_io_lsu_pkt_r_dma), .io_lsu_pkt_r_valid(lsu_lsc_ctl_io_lsu_pkt_r_valid) ); - el2_lsu_dccm_ctl dccm_ctl ( // @[el2_lsu.scala 154:30] + el2_lsu_dccm_ctl dccm_ctl ( // @[el2_lsu.scala 157:30] + .clock(dccm_ctl_clock), .reset(dccm_ctl_reset), .io_lsu_c2_m_clk(dccm_ctl_io_lsu_c2_m_clk), .io_lsu_c2_r_clk(dccm_ctl_io_lsu_c2_r_clk), .io_lsu_free_c2_clk(dccm_ctl_io_lsu_free_c2_clk), .io_lsu_store_c1_r_clk(dccm_ctl_io_lsu_store_c1_r_clk), - .io_clk(dccm_ctl_io_clk), .io_lsu_pkt_d_word(dccm_ctl_io_lsu_pkt_d_word), .io_lsu_pkt_d_dword(dccm_ctl_io_lsu_pkt_d_dword), .io_lsu_pkt_d_load(dccm_ctl_io_lsu_pkt_d_load), @@ -4563,6 +11070,7 @@ module el2_lsu( .io_stbuf_reqvld_any(dccm_ctl_io_stbuf_reqvld_any), .io_stbuf_addr_any(dccm_ctl_io_stbuf_addr_any), .io_stbuf_data_any(dccm_ctl_io_stbuf_data_any), + .io_stbuf_ecc_any(dccm_ctl_io_stbuf_ecc_any), .io_stbuf_fwddata_hi_m(dccm_ctl_io_stbuf_fwddata_hi_m), .io_stbuf_fwddata_lo_m(dccm_ctl_io_stbuf_fwddata_lo_m), .io_stbuf_fwdbyteen_lo_m(dccm_ctl_io_stbuf_fwdbyteen_lo_m), @@ -4573,6 +11081,8 @@ module el2_lsu( .io_single_ecc_error_lo_r(dccm_ctl_io_single_ecc_error_lo_r), .io_sec_data_hi_r_ff(dccm_ctl_io_sec_data_hi_r_ff), .io_sec_data_lo_r_ff(dccm_ctl_io_sec_data_lo_r_ff), + .io_sec_data_ecc_hi_r_ff(dccm_ctl_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(dccm_ctl_io_sec_data_ecc_lo_r_ff), .io_dccm_rdata_hi_m(dccm_ctl_io_dccm_rdata_hi_m), .io_dccm_rdata_lo_m(dccm_ctl_io_dccm_rdata_lo_m), .io_dccm_data_ecc_hi_m(dccm_ctl_io_dccm_data_ecc_hi_m), @@ -4589,10 +11099,13 @@ module el2_lsu( .io_dma_mem_wdata(dccm_ctl_io_dma_mem_wdata), .io_dma_dccm_wdata_lo(dccm_ctl_io_dma_dccm_wdata_lo), .io_dma_dccm_wdata_hi(dccm_ctl_io_dma_dccm_wdata_hi), + .io_dma_dccm_wdata_ecc_hi(dccm_ctl_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(dccm_ctl_io_dma_dccm_wdata_ecc_lo), .io_store_data_hi_r(dccm_ctl_io_store_data_hi_r), .io_store_data_lo_r(dccm_ctl_io_store_data_lo_r), .io_store_datafn_hi_r(dccm_ctl_io_store_datafn_hi_r), .io_store_datafn_lo_r(dccm_ctl_io_store_datafn_lo_r), + .io_store_data_r(dccm_ctl_io_store_data_r), .io_ld_single_ecc_error_r(dccm_ctl_io_ld_single_ecc_error_r), .io_ld_single_ecc_error_r_ff(dccm_ctl_io_ld_single_ecc_error_r_ff), .io_picm_mask_data_m(dccm_ctl_io_picm_mask_data_m), @@ -4621,7 +11134,7 @@ module el2_lsu( .io_picm_rd_data(dccm_ctl_io_picm_rd_data), .io_scan_mode(dccm_ctl_io_scan_mode) ); - el2_lsu_stbuf stbuf ( // @[el2_lsu.scala 155:30] + el2_lsu_stbuf stbuf ( // @[el2_lsu.scala 158:30] .clock(stbuf_clock), .reset(stbuf_reset), .io_lsu_c1_m_clk(stbuf_io_lsu_c1_m_clk), @@ -4654,18 +11167,20 @@ module el2_lsu( .io_end_addr_r(stbuf_io_end_addr_r), .io_addr_in_dccm_m(stbuf_io_addr_in_dccm_m), .io_addr_in_dccm_r(stbuf_io_addr_in_dccm_r), + .io_scan_mode(stbuf_io_scan_mode), .io_stbuf_reqvld_any(stbuf_io_stbuf_reqvld_any), .io_stbuf_reqvld_flushed_any(stbuf_io_stbuf_reqvld_flushed_any), .io_stbuf_addr_any(stbuf_io_stbuf_addr_any), .io_stbuf_data_any(stbuf_io_stbuf_data_any), .io_lsu_stbuf_full_any(stbuf_io_lsu_stbuf_full_any), + .io_lsu_stbuf_empty_any(stbuf_io_lsu_stbuf_empty_any), .io_ldst_stbuf_reqvld_r(stbuf_io_ldst_stbuf_reqvld_r), .io_stbuf_fwddata_hi_m(stbuf_io_stbuf_fwddata_hi_m), .io_stbuf_fwddata_lo_m(stbuf_io_stbuf_fwddata_lo_m), .io_stbuf_fwdbyteen_hi_m(stbuf_io_stbuf_fwdbyteen_hi_m), .io_stbuf_fwdbyteen_lo_m(stbuf_io_stbuf_fwdbyteen_lo_m) ); - el2_lsu_ecc ecc ( // @[el2_lsu.scala 156:30] + el2_lsu_ecc ecc ( // @[el2_lsu.scala 159:30] .clock(ecc_clock), .reset(ecc_reset), .io_lsu_c2_r_clk(ecc_io_lsu_c2_r_clk), @@ -4673,6 +11188,7 @@ module el2_lsu( .io_lsu_pkt_m_store(ecc_io_lsu_pkt_m_store), .io_lsu_pkt_m_dma(ecc_io_lsu_pkt_m_dma), .io_lsu_pkt_m_valid(ecc_io_lsu_pkt_m_valid), + .io_stbuf_data_any(ecc_io_stbuf_data_any), .io_dec_tlu_core_ecc_disable(ecc_io_dec_tlu_core_ecc_disable), .io_lsu_addr_m(ecc_io_lsu_addr_m), .io_end_addr_m(ecc_io_end_addr_m), @@ -4681,14 +11197,24 @@ module el2_lsu( .io_dccm_data_ecc_hi_m(ecc_io_dccm_data_ecc_hi_m), .io_dccm_data_ecc_lo_m(ecc_io_dccm_data_ecc_lo_m), .io_ld_single_ecc_error_r(ecc_io_ld_single_ecc_error_r), + .io_ld_single_ecc_error_r_ff(ecc_io_ld_single_ecc_error_r_ff), .io_lsu_dccm_rden_m(ecc_io_lsu_dccm_rden_m), .io_addr_in_dccm_m(ecc_io_addr_in_dccm_m), + .io_dma_dccm_wen(ecc_io_dma_dccm_wen), + .io_dma_dccm_wdata_lo(ecc_io_dma_dccm_wdata_lo), + .io_dma_dccm_wdata_hi(ecc_io_dma_dccm_wdata_hi), + .io_scan_mode(ecc_io_scan_mode), .io_sec_data_hi_r(ecc_io_sec_data_hi_r), .io_sec_data_lo_r(ecc_io_sec_data_lo_r), .io_sec_data_hi_m(ecc_io_sec_data_hi_m), .io_sec_data_lo_m(ecc_io_sec_data_lo_m), .io_sec_data_hi_r_ff(ecc_io_sec_data_hi_r_ff), .io_sec_data_lo_r_ff(ecc_io_sec_data_lo_r_ff), + .io_dma_dccm_wdata_ecc_hi(ecc_io_dma_dccm_wdata_ecc_hi), + .io_dma_dccm_wdata_ecc_lo(ecc_io_dma_dccm_wdata_ecc_lo), + .io_stbuf_ecc_any(ecc_io_stbuf_ecc_any), + .io_sec_data_ecc_hi_r_ff(ecc_io_sec_data_ecc_hi_r_ff), + .io_sec_data_ecc_lo_r_ff(ecc_io_sec_data_ecc_lo_r_ff), .io_single_ecc_error_hi_r(ecc_io_single_ecc_error_hi_r), .io_single_ecc_error_lo_r(ecc_io_single_ecc_error_lo_r), .io_lsu_single_ecc_error_r(ecc_io_lsu_single_ecc_error_r), @@ -4696,7 +11222,7 @@ module el2_lsu( .io_lsu_single_ecc_error_m(ecc_io_lsu_single_ecc_error_m), .io_lsu_double_ecc_error_m(ecc_io_lsu_double_ecc_error_m) ); - el2_lsu_trigger trigger ( // @[el2_lsu.scala 157:30] + el2_lsu_trigger trigger ( // @[el2_lsu.scala 160:30] .io_trigger_pkt_any_0_select(trigger_io_trigger_pkt_any_0_select), .io_trigger_pkt_any_0_match_(trigger_io_trigger_pkt_any_0_match_), .io_trigger_pkt_any_0_store(trigger_io_trigger_pkt_any_0_store), @@ -4727,241 +11253,353 @@ module el2_lsu( .io_store_data_m(trigger_io_store_data_m), .io_lsu_trigger_match_m(trigger_io_lsu_trigger_match_m) ); - el2_lsu_clkdomain clkdomain ( // @[el2_lsu.scala 158:30] + el2_lsu_clkdomain clkdomain ( // @[el2_lsu.scala 161:30] .clock(clkdomain_clock), .reset(clkdomain_reset), + .io_free_clk(clkdomain_io_free_clk), .io_clk_override(clkdomain_io_clk_override), .io_dma_dccm_req(clkdomain_io_dma_dccm_req), .io_ldst_stbuf_reqvld_r(clkdomain_io_ldst_stbuf_reqvld_r), .io_stbuf_reqvld_any(clkdomain_io_stbuf_reqvld_any), .io_stbuf_reqvld_flushed_any(clkdomain_io_stbuf_reqvld_flushed_any), + .io_lsu_busreq_r(clkdomain_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(clkdomain_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_empty_any(clkdomain_io_lsu_bus_buffer_empty_any), + .io_lsu_stbuf_empty_any(clkdomain_io_lsu_stbuf_empty_any), .io_lsu_bus_clk_en(clkdomain_io_lsu_bus_clk_en), .io_lsu_p_valid(clkdomain_io_lsu_p_valid), .io_lsu_pkt_d_store(clkdomain_io_lsu_pkt_d_store), .io_lsu_pkt_d_valid(clkdomain_io_lsu_pkt_d_valid), .io_lsu_pkt_m_store(clkdomain_io_lsu_pkt_m_store), .io_lsu_pkt_m_valid(clkdomain_io_lsu_pkt_m_valid), + .io_lsu_pkt_r_valid(clkdomain_io_lsu_pkt_r_valid), .io_lsu_c1_m_clk(clkdomain_io_lsu_c1_m_clk), .io_lsu_c1_r_clk(clkdomain_io_lsu_c1_r_clk), .io_lsu_c2_m_clk(clkdomain_io_lsu_c2_m_clk), .io_lsu_c2_r_clk(clkdomain_io_lsu_c2_r_clk), + .io_lsu_store_c1_m_clk(clkdomain_io_lsu_store_c1_m_clk), .io_lsu_stbuf_c1_clk(clkdomain_io_lsu_stbuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(clkdomain_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_ibuf_c1_clk(clkdomain_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_buf_c1_clk(clkdomain_io_lsu_bus_buf_c1_clk), + .io_lsu_busm_clk(clkdomain_io_lsu_busm_clk), .io_lsu_free_c2_clk(clkdomain_io_lsu_free_c2_clk), .io_scan_mode(clkdomain_io_scan_mode) ); - assign io_lsu_load_stall_any = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 166:25] - assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 165:26] - assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 167:28] - assign io_lsu_idle_any = 1'h0; // @[el2_lsu.scala 187:19] - assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 233:50] - assign io_lsu_fir_error = 2'h0; // @[el2_lsu.scala 234:50] - assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 231:50] - assign io_lsu_error_pkt_r_exc_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_exc_valid; // @[el2_lsu.scala 232:50] - assign io_lsu_error_pkt_r_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_single_ecc_error; // @[el2_lsu.scala 232:50] - assign io_lsu_error_pkt_r_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_inst_type; // @[el2_lsu.scala 232:50] - assign io_lsu_error_pkt_r_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_exc_type; // @[el2_lsu.scala 232:50] - assign io_lsu_error_pkt_r_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_mscause; // @[el2_lsu.scala 232:50] - assign io_lsu_error_pkt_r_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_addr; // @[el2_lsu.scala 232:50] - assign io_lsu_imprecise_error_load_any = 1'h0; // @[el2_lsu.scala 434:50] - assign io_lsu_imprecise_error_store_any = 1'h0; // @[el2_lsu.scala 435:50] - assign io_lsu_imprecise_error_addr_any = 32'h0; // @[el2_lsu.scala 436:50] - assign io_lsu_nonblock_load_valid_m = 1'h0; // @[el2_lsu.scala 437:50] - assign io_lsu_nonblock_load_tag_m = 2'h0; // @[el2_lsu.scala 438:50] - assign io_lsu_nonblock_load_inv_r = 1'h0; // @[el2_lsu.scala 439:50] - assign io_lsu_nonblock_load_inv_tag_r = 2'h0; // @[el2_lsu.scala 440:50] - assign io_lsu_nonblock_load_data_valid = 1'h0; // @[el2_lsu.scala 441:50] - assign io_lsu_nonblock_load_data_error = 1'h0; // @[el2_lsu.scala 442:50] - assign io_lsu_nonblock_load_data_tag = 2'h0; // @[el2_lsu.scala 443:50] - assign io_lsu_nonblock_load_data = 32'h0; // @[el2_lsu.scala 444:50] - assign io_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 196:30] - assign io_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 197:30] - assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_46; // @[el2_lsu.scala 195:26] - assign io_lsu_pmu_bus_trxn = 1'h0; // @[el2_lsu.scala 445:50] - assign io_lsu_pmu_bus_misaligned = 1'h0; // @[el2_lsu.scala 446:50] - assign io_lsu_pmu_bus_error = 1'h0; // @[el2_lsu.scala 447:50] - assign io_lsu_pmu_bus_busy = 1'h0; // @[el2_lsu.scala 448:50] + el2_lsu_bus_intf bus_intf ( // @[el2_lsu.scala 162:30] + .clock(bus_intf_clock), + .reset(bus_intf_reset), + .io_scan_mode(bus_intf_io_scan_mode), + .io_dec_tlu_external_ldfwd_disable(bus_intf_io_dec_tlu_external_ldfwd_disable), + .io_dec_tlu_wb_coalescing_disable(bus_intf_io_dec_tlu_wb_coalescing_disable), + .io_dec_tlu_sideeffect_posted_disable(bus_intf_io_dec_tlu_sideeffect_posted_disable), + .io_lsu_c1_m_clk(bus_intf_io_lsu_c1_m_clk), + .io_lsu_c1_r_clk(bus_intf_io_lsu_c1_r_clk), + .io_lsu_c2_r_clk(bus_intf_io_lsu_c2_r_clk), + .io_lsu_bus_ibuf_c1_clk(bus_intf_io_lsu_bus_ibuf_c1_clk), + .io_lsu_bus_obuf_c1_clk(bus_intf_io_lsu_bus_obuf_c1_clk), + .io_lsu_bus_buf_c1_clk(bus_intf_io_lsu_bus_buf_c1_clk), + .io_lsu_free_c2_clk(bus_intf_io_lsu_free_c2_clk), + .io_free_clk(bus_intf_io_free_clk), + .io_lsu_busm_clk(bus_intf_io_lsu_busm_clk), + .io_dec_lsu_valid_raw_d(bus_intf_io_dec_lsu_valid_raw_d), + .io_lsu_busreq_m(bus_intf_io_lsu_busreq_m), + .io_lsu_pkt_m_by(bus_intf_io_lsu_pkt_m_by), + .io_lsu_pkt_m_half(bus_intf_io_lsu_pkt_m_half), + .io_lsu_pkt_m_word(bus_intf_io_lsu_pkt_m_word), + .io_lsu_pkt_m_load(bus_intf_io_lsu_pkt_m_load), + .io_lsu_pkt_m_valid(bus_intf_io_lsu_pkt_m_valid), + .io_lsu_pkt_r_by(bus_intf_io_lsu_pkt_r_by), + .io_lsu_pkt_r_half(bus_intf_io_lsu_pkt_r_half), + .io_lsu_pkt_r_word(bus_intf_io_lsu_pkt_r_word), + .io_lsu_pkt_r_load(bus_intf_io_lsu_pkt_r_load), + .io_lsu_pkt_r_store(bus_intf_io_lsu_pkt_r_store), + .io_lsu_pkt_r_unsign(bus_intf_io_lsu_pkt_r_unsign), + .io_lsu_pkt_r_valid(bus_intf_io_lsu_pkt_r_valid), + .io_lsu_addr_d(bus_intf_io_lsu_addr_d), + .io_lsu_addr_m(bus_intf_io_lsu_addr_m), + .io_lsu_addr_r(bus_intf_io_lsu_addr_r), + .io_end_addr_d(bus_intf_io_end_addr_d), + .io_end_addr_m(bus_intf_io_end_addr_m), + .io_end_addr_r(bus_intf_io_end_addr_r), + .io_store_data_r(bus_intf_io_store_data_r), + .io_dec_tlu_force_halt(bus_intf_io_dec_tlu_force_halt), + .io_lsu_commit_r(bus_intf_io_lsu_commit_r), + .io_is_sideeffects_m(bus_intf_io_is_sideeffects_m), + .io_flush_m_up(bus_intf_io_flush_m_up), + .io_flush_r(bus_intf_io_flush_r), + .io_lsu_busreq_r(bus_intf_io_lsu_busreq_r), + .io_lsu_bus_buffer_pend_any(bus_intf_io_lsu_bus_buffer_pend_any), + .io_lsu_bus_buffer_full_any(bus_intf_io_lsu_bus_buffer_full_any), + .io_lsu_bus_buffer_empty_any(bus_intf_io_lsu_bus_buffer_empty_any), + .io_bus_read_data_m(bus_intf_io_bus_read_data_m), + .io_lsu_imprecise_error_load_any(bus_intf_io_lsu_imprecise_error_load_any), + .io_lsu_imprecise_error_store_any(bus_intf_io_lsu_imprecise_error_store_any), + .io_lsu_imprecise_error_addr_any(bus_intf_io_lsu_imprecise_error_addr_any), + .io_lsu_nonblock_load_valid_m(bus_intf_io_lsu_nonblock_load_valid_m), + .io_lsu_nonblock_load_tag_m(bus_intf_io_lsu_nonblock_load_tag_m), + .io_lsu_nonblock_load_inv_r(bus_intf_io_lsu_nonblock_load_inv_r), + .io_lsu_nonblock_load_inv_tag_r(bus_intf_io_lsu_nonblock_load_inv_tag_r), + .io_lsu_nonblock_load_data_valid(bus_intf_io_lsu_nonblock_load_data_valid), + .io_lsu_nonblock_load_data_error(bus_intf_io_lsu_nonblock_load_data_error), + .io_lsu_nonblock_load_data_tag(bus_intf_io_lsu_nonblock_load_data_tag), + .io_lsu_nonblock_load_data(bus_intf_io_lsu_nonblock_load_data), + .io_lsu_pmu_bus_trxn(bus_intf_io_lsu_pmu_bus_trxn), + .io_lsu_pmu_bus_misaligned(bus_intf_io_lsu_pmu_bus_misaligned), + .io_lsu_pmu_bus_error(bus_intf_io_lsu_pmu_bus_error), + .io_lsu_pmu_bus_busy(bus_intf_io_lsu_pmu_bus_busy), + .io_lsu_axi_awvalid(bus_intf_io_lsu_axi_awvalid), + .io_lsu_axi_awready(bus_intf_io_lsu_axi_awready), + .io_lsu_axi_awid(bus_intf_io_lsu_axi_awid), + .io_lsu_axi_awaddr(bus_intf_io_lsu_axi_awaddr), + .io_lsu_axi_awregion(bus_intf_io_lsu_axi_awregion), + .io_lsu_axi_awsize(bus_intf_io_lsu_axi_awsize), + .io_lsu_axi_awcache(bus_intf_io_lsu_axi_awcache), + .io_lsu_axi_wvalid(bus_intf_io_lsu_axi_wvalid), + .io_lsu_axi_wready(bus_intf_io_lsu_axi_wready), + .io_lsu_axi_wdata(bus_intf_io_lsu_axi_wdata), + .io_lsu_axi_wstrb(bus_intf_io_lsu_axi_wstrb), + .io_lsu_axi_bvalid(bus_intf_io_lsu_axi_bvalid), + .io_lsu_axi_bresp(bus_intf_io_lsu_axi_bresp), + .io_lsu_axi_bid(bus_intf_io_lsu_axi_bid), + .io_lsu_axi_arvalid(bus_intf_io_lsu_axi_arvalid), + .io_lsu_axi_arready(bus_intf_io_lsu_axi_arready), + .io_lsu_axi_arid(bus_intf_io_lsu_axi_arid), + .io_lsu_axi_araddr(bus_intf_io_lsu_axi_araddr), + .io_lsu_axi_arregion(bus_intf_io_lsu_axi_arregion), + .io_lsu_axi_arsize(bus_intf_io_lsu_axi_arsize), + .io_lsu_axi_arcache(bus_intf_io_lsu_axi_arcache), + .io_lsu_axi_rvalid(bus_intf_io_lsu_axi_rvalid), + .io_lsu_axi_rid(bus_intf_io_lsu_axi_rid), + .io_lsu_axi_rdata(bus_intf_io_lsu_axi_rdata), + .io_lsu_bus_clk_en(bus_intf_io_lsu_bus_clk_en) + ); + assign io_lsu_result_m = lsu_lsc_ctl_io_lsu_result_m; // @[el2_lsu.scala 155:19] + assign io_lsu_result_corr_r = lsu_lsc_ctl_io_lsu_result_corr_r; // @[el2_lsu.scala 156:24] + assign io_lsu_load_stall_any = bus_intf_io_lsu_bus_buffer_full_any | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 169:25] + assign io_lsu_store_stall_any = _T | dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 168:26] + assign io_lsu_fastint_stall_any = dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 170:28] + assign io_lsu_idle_any = _T_22 & bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 190:19] + assign io_lsu_fir_addr = lsu_lsc_ctl_io_lsu_fir_addr; // @[el2_lsu.scala 236:49] + assign io_lsu_fir_error = lsu_lsc_ctl_io_lsu_fir_error; // @[el2_lsu.scala 237:49] + assign io_lsu_single_ecc_error_incr = lsu_lsc_ctl_io_lsu_single_ecc_error_incr; // @[el2_lsu.scala 234:49] + assign io_lsu_error_pkt_r_exc_valid = lsu_lsc_ctl_io_lsu_error_pkt_r_exc_valid; // @[el2_lsu.scala 235:49] + assign io_lsu_error_pkt_r_single_ecc_error = lsu_lsc_ctl_io_lsu_error_pkt_r_single_ecc_error; // @[el2_lsu.scala 235:49] + assign io_lsu_error_pkt_r_inst_type = lsu_lsc_ctl_io_lsu_error_pkt_r_inst_type; // @[el2_lsu.scala 235:49] + assign io_lsu_error_pkt_r_exc_type = lsu_lsc_ctl_io_lsu_error_pkt_r_exc_type; // @[el2_lsu.scala 235:49] + assign io_lsu_error_pkt_r_mscause = lsu_lsc_ctl_io_lsu_error_pkt_r_mscause; // @[el2_lsu.scala 235:49] + assign io_lsu_error_pkt_r_addr = lsu_lsc_ctl_io_lsu_error_pkt_r_addr; // @[el2_lsu.scala 235:49] + assign io_lsu_imprecise_error_load_any = bus_intf_io_lsu_imprecise_error_load_any; // @[el2_lsu.scala 436:49] + assign io_lsu_imprecise_error_store_any = bus_intf_io_lsu_imprecise_error_store_any; // @[el2_lsu.scala 437:49] + assign io_lsu_imprecise_error_addr_any = bus_intf_io_lsu_imprecise_error_addr_any; // @[el2_lsu.scala 438:49] + assign io_lsu_nonblock_load_valid_m = bus_intf_io_lsu_nonblock_load_valid_m; // @[el2_lsu.scala 439:49] + assign io_lsu_nonblock_load_tag_m = bus_intf_io_lsu_nonblock_load_tag_m; // @[el2_lsu.scala 440:49] + assign io_lsu_nonblock_load_inv_r = bus_intf_io_lsu_nonblock_load_inv_r; // @[el2_lsu.scala 441:49] + assign io_lsu_nonblock_load_inv_tag_r = bus_intf_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu.scala 442:49] + assign io_lsu_nonblock_load_data_valid = bus_intf_io_lsu_nonblock_load_data_valid; // @[el2_lsu.scala 443:49] + assign io_lsu_nonblock_load_data_error = bus_intf_io_lsu_nonblock_load_data_error; // @[el2_lsu.scala 444:49] + assign io_lsu_nonblock_load_data_tag = bus_intf_io_lsu_nonblock_load_data_tag; // @[el2_lsu.scala 445:49] + assign io_lsu_nonblock_load_data = bus_intf_io_lsu_nonblock_load_data; // @[el2_lsu.scala 446:49] + assign io_lsu_pmu_load_external_m = _T_48 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 199:31] + assign io_lsu_pmu_store_external_m = _T_50 & lsu_lsc_ctl_io_addr_external_m; // @[el2_lsu.scala 200:31] + assign io_lsu_pmu_misaligned_m = lsu_lsc_ctl_io_lsu_pkt_m_valid & _T_46; // @[el2_lsu.scala 198:27] + assign io_lsu_pmu_bus_trxn = bus_intf_io_lsu_pmu_bus_trxn; // @[el2_lsu.scala 447:49] + assign io_lsu_pmu_bus_misaligned = bus_intf_io_lsu_pmu_bus_misaligned; // @[el2_lsu.scala 448:49] + assign io_lsu_pmu_bus_error = bus_intf_io_lsu_pmu_bus_error; // @[el2_lsu.scala 449:49] + assign io_lsu_pmu_bus_busy = bus_intf_io_lsu_pmu_bus_busy; // @[el2_lsu.scala 450:49] assign io_lsu_trigger_match_m = trigger_io_lsu_trigger_match_m; // @[el2_lsu.scala 381:50] - assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 303:50] - assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 304:50] - assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 305:50] - assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 308:50] - assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 307:50] - assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 310:50] - assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 306:50] - assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 309:50] - assign io_picm_wren = dccm_ctl_io_picm_wren; // @[el2_lsu.scala 311:50] - assign io_picm_rden = dccm_ctl_io_picm_rden; // @[el2_lsu.scala 312:50] - assign io_picm_mken = dccm_ctl_io_picm_mken; // @[el2_lsu.scala 313:50] - assign io_picm_rdaddr = dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 314:50] - assign io_picm_wraddr = dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 315:50] - assign io_picm_wr_data = dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 316:50] - assign io_lsu_axi_awvalid = 1'h0; // @[el2_lsu.scala 449:50] - assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu.scala 457:50] - assign io_lsu_axi_awid = 3'h0; // @[el2_lsu.scala 451:50] - assign io_lsu_axi_awaddr = 32'h0; // @[el2_lsu.scala 452:50] - assign io_lsu_axi_awregion = 4'h0; // @[el2_lsu.scala 453:50] - assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu.scala 454:50] - assign io_lsu_axi_awsize = 3'h0; // @[el2_lsu.scala 455:50] - assign io_lsu_axi_awburst = 2'h0; // @[el2_lsu.scala 456:50] - assign io_lsu_axi_awcache = 4'h0; // @[el2_lsu.scala 458:50] - assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu.scala 459:50] - assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu.scala 460:50] - assign io_lsu_axi_wvalid = 1'h0; // @[el2_lsu.scala 461:50] - assign io_lsu_axi_wdata = 64'h0; // @[el2_lsu.scala 463:50] - assign io_lsu_axi_wstrb = 8'h0; // @[el2_lsu.scala 464:50] - assign io_lsu_axi_wlast = 1'h0; // @[el2_lsu.scala 465:50] - assign io_lsu_axi_bready = 1'h0; // @[el2_lsu.scala 467:50] - assign io_lsu_axi_arvalid = 1'h0; // @[el2_lsu.scala 470:50] - assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu.scala 478:50] - assign io_lsu_axi_arid = 3'h0; // @[el2_lsu.scala 472:50] - assign io_lsu_axi_araddr = 32'h0; // @[el2_lsu.scala 473:50] - assign io_lsu_axi_arregion = 4'h0; // @[el2_lsu.scala 474:50] - assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu.scala 475:50] - assign io_lsu_axi_arsize = 3'h0; // @[el2_lsu.scala 476:50] - assign io_lsu_axi_arburst = 2'h0; // @[el2_lsu.scala 477:50] - assign io_lsu_axi_arcache = 4'h0; // @[el2_lsu.scala 479:50] - assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu.scala 480:50] - assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu.scala 481:50] - assign io_lsu_axi_rready = 1'h0; // @[el2_lsu.scala 483:50] - assign io_dccm_dma_rvalid = dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 299:50] - assign io_dccm_dma_ecc_error = dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 300:50] - assign io_dccm_dma_rtag = dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 301:50] - assign io_dccm_dma_rdata = dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 302:50] - assign io_dccm_ready = ~_T_8; // @[el2_lsu.scala 173:17] - assign lsu_lsc_ctl_clock = clock; + assign io_dccm_wren = dccm_ctl_io_dccm_wren; // @[el2_lsu.scala 303:49] + assign io_dccm_rden = dccm_ctl_io_dccm_rden; // @[el2_lsu.scala 304:49] + assign io_dccm_wr_addr_lo = dccm_ctl_io_dccm_wr_addr_lo; // @[el2_lsu.scala 305:49] + assign io_dccm_wr_addr_hi = dccm_ctl_io_dccm_wr_addr_hi; // @[el2_lsu.scala 308:49] + assign io_dccm_rd_addr_lo = dccm_ctl_io_dccm_rd_addr_lo; // @[el2_lsu.scala 307:49] + assign io_dccm_rd_addr_hi = dccm_ctl_io_dccm_rd_addr_hi; // @[el2_lsu.scala 310:49] + assign io_dccm_wr_data_lo = dccm_ctl_io_dccm_wr_data_lo; // @[el2_lsu.scala 306:49] + assign io_dccm_wr_data_hi = dccm_ctl_io_dccm_wr_data_hi; // @[el2_lsu.scala 309:49] + assign io_picm_wren = dccm_ctl_io_picm_wren; // @[el2_lsu.scala 311:49] + assign io_picm_rden = dccm_ctl_io_picm_rden; // @[el2_lsu.scala 312:49] + assign io_picm_mken = dccm_ctl_io_picm_mken; // @[el2_lsu.scala 313:49] + assign io_picm_rdaddr = dccm_ctl_io_picm_rdaddr; // @[el2_lsu.scala 314:49] + assign io_picm_wraddr = dccm_ctl_io_picm_wraddr; // @[el2_lsu.scala 315:49] + assign io_picm_wr_data = dccm_ctl_io_picm_wr_data; // @[el2_lsu.scala 316:49] + assign io_lsu_axi_awvalid = bus_intf_io_lsu_axi_awvalid; // @[el2_lsu.scala 451:49] + assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu.scala 459:49] + assign io_lsu_axi_awid = bus_intf_io_lsu_axi_awid; // @[el2_lsu.scala 453:49] + assign io_lsu_axi_awaddr = bus_intf_io_lsu_axi_awaddr; // @[el2_lsu.scala 454:49] + assign io_lsu_axi_awregion = bus_intf_io_lsu_axi_awregion; // @[el2_lsu.scala 455:49] + assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu.scala 456:49] + assign io_lsu_axi_awsize = bus_intf_io_lsu_axi_awsize; // @[el2_lsu.scala 457:49] + assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu.scala 458:49] + assign io_lsu_axi_awcache = bus_intf_io_lsu_axi_awcache; // @[el2_lsu.scala 460:49] + assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu.scala 461:49] + assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu.scala 462:49] + assign io_lsu_axi_wvalid = bus_intf_io_lsu_axi_wvalid; // @[el2_lsu.scala 463:49] + assign io_lsu_axi_wdata = bus_intf_io_lsu_axi_wdata; // @[el2_lsu.scala 465:49] + assign io_lsu_axi_wstrb = bus_intf_io_lsu_axi_wstrb; // @[el2_lsu.scala 466:49] + assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu.scala 467:49] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu.scala 469:49] + assign io_lsu_axi_arvalid = bus_intf_io_lsu_axi_arvalid; // @[el2_lsu.scala 472:49] + assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu.scala 480:49] + assign io_lsu_axi_arid = bus_intf_io_lsu_axi_arid; // @[el2_lsu.scala 474:49] + assign io_lsu_axi_araddr = bus_intf_io_lsu_axi_araddr; // @[el2_lsu.scala 475:49] + assign io_lsu_axi_arregion = bus_intf_io_lsu_axi_arregion; // @[el2_lsu.scala 476:49] + assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu.scala 477:49] + assign io_lsu_axi_arsize = bus_intf_io_lsu_axi_arsize; // @[el2_lsu.scala 478:49] + assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu.scala 479:49] + assign io_lsu_axi_arcache = bus_intf_io_lsu_axi_arcache; // @[el2_lsu.scala 481:49] + assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu.scala 482:49] + assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu.scala 483:49] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu.scala 485:49] + assign io_dccm_dma_rvalid = dccm_ctl_io_dccm_dma_rvalid; // @[el2_lsu.scala 299:49] + assign io_dccm_dma_ecc_error = dccm_ctl_io_dccm_dma_ecc_error; // @[el2_lsu.scala 300:49] + assign io_dccm_dma_rtag = dccm_ctl_io_dccm_dma_rtag; // @[el2_lsu.scala 301:49] + assign io_dccm_dma_rdata = dccm_ctl_io_dccm_dma_rdata; // @[el2_lsu.scala 302:49] + assign io_dccm_ready = ~_T_8; // @[el2_lsu.scala 176:17] assign lsu_lsc_ctl_reset = reset; - assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 207:50] - assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 208:50] - assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 209:50] - assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 210:50] - assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 211:50] - assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 212:50] - assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 213:50] - assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 214:50] - assign lsu_lsc_ctl_io_exu_lsu_rs1_d = io_exu_lsu_rs1_d; // @[el2_lsu.scala 215:50] - assign lsu_lsc_ctl_io_exu_lsu_rs2_d = io_exu_lsu_rs2_d; // @[el2_lsu.scala 216:50] - assign lsu_lsc_ctl_io_lsu_p_fast_int = io_lsu_p_fast_int; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_by = io_lsu_p_by; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_half = io_lsu_p_half; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_word = io_lsu_p_word; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_dword = io_lsu_p_dword; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_load = io_lsu_p_load; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_store = io_lsu_p_store; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_unsign = io_lsu_p_unsign; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_dma = io_lsu_p_dma; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_store_data_bypass_d = io_lsu_p_store_data_bypass_d; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_load_ldst_bypass_d = io_lsu_p_load_ldst_bypass_d; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_store_data_bypass_m = io_lsu_p_store_data_bypass_m; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[el2_lsu.scala 217:50] - assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 218:50] - assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[el2_lsu.scala 219:50] - assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 220:50] - assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu.scala 227:50] - assign lsu_lsc_ctl_io_dma_dccm_req = io_dma_dccm_req; // @[el2_lsu.scala 222:50] - assign lsu_lsc_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 223:50] - assign lsu_lsc_ctl_io_dma_mem_sz = io_dma_mem_sz; // @[el2_lsu.scala 224:50] - assign lsu_lsc_ctl_io_dma_mem_write = io_dma_mem_write; // @[el2_lsu.scala 225:50] - assign lsu_lsc_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 226:50] + assign lsu_lsc_ctl_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 204:46] + assign lsu_lsc_ctl_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 205:46] + assign lsu_lsc_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 206:46] + assign lsu_lsc_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 207:46] + assign lsu_lsc_ctl_io_lsu_store_c1_m_clk = clkdomain_io_lsu_store_c1_m_clk; // @[el2_lsu.scala 208:46] + assign lsu_lsc_ctl_io_lsu_ld_data_corr_r = dccm_ctl_io_lsu_ld_data_corr_r; // @[el2_lsu.scala 210:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_r = ecc_io_lsu_single_ecc_error_r; // @[el2_lsu.scala 211:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 212:46] + assign lsu_lsc_ctl_io_lsu_ld_data_m = dccm_ctl_io_lsu_ld_data_m; // @[el2_lsu.scala 213:46] + assign lsu_lsc_ctl_io_lsu_single_ecc_error_m = ecc_io_lsu_single_ecc_error_m; // @[el2_lsu.scala 214:46] + assign lsu_lsc_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 215:46] + assign lsu_lsc_ctl_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 216:46] + assign lsu_lsc_ctl_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 217:46] + assign lsu_lsc_ctl_io_exu_lsu_rs1_d = io_exu_lsu_rs1_d; // @[el2_lsu.scala 218:46] + assign lsu_lsc_ctl_io_exu_lsu_rs2_d = io_exu_lsu_rs2_d; // @[el2_lsu.scala 219:46] + assign lsu_lsc_ctl_io_lsu_p_fast_int = io_lsu_p_fast_int; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_by = io_lsu_p_by; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_half = io_lsu_p_half; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_word = io_lsu_p_word; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_dword = io_lsu_p_dword; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_load = io_lsu_p_load; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_store = io_lsu_p_store; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_unsign = io_lsu_p_unsign; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_dma = io_lsu_p_dma; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_store_data_bypass_d = io_lsu_p_store_data_bypass_d; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_load_ldst_bypass_d = io_lsu_p_load_ldst_bypass_d; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_store_data_bypass_m = io_lsu_p_store_data_bypass_m; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_lsu_p_valid = io_lsu_p_valid; // @[el2_lsu.scala 220:46] + assign lsu_lsc_ctl_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 221:46] + assign lsu_lsc_ctl_io_dec_lsu_offset_d = io_dec_lsu_offset_d; // @[el2_lsu.scala 222:46] + assign lsu_lsc_ctl_io_picm_mask_data_m = dccm_ctl_io_picm_mask_data_m; // @[el2_lsu.scala 223:46] + assign lsu_lsc_ctl_io_bus_read_data_m = bus_intf_io_bus_read_data_m; // @[el2_lsu.scala 224:46] + assign lsu_lsc_ctl_io_dec_tlu_mrac_ff = io_dec_tlu_mrac_ff; // @[el2_lsu.scala 230:46] + assign lsu_lsc_ctl_io_dma_dccm_req = io_dma_dccm_req; // @[el2_lsu.scala 225:46] + assign lsu_lsc_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 226:46] + assign lsu_lsc_ctl_io_dma_mem_sz = io_dma_mem_sz; // @[el2_lsu.scala 227:46] + assign lsu_lsc_ctl_io_dma_mem_write = io_dma_mem_write; // @[el2_lsu.scala 228:46] + assign lsu_lsc_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 229:46] + assign dccm_ctl_clock = clock; assign dccm_ctl_reset = reset; - assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 239:50] - assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:50] - assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 241:50] - assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 243:50] - assign dccm_ctl_io_clk = clock; // @[el2_lsu.scala 244:50] - assign dccm_ctl_io_lsu_pkt_d_word = lsu_lsc_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_d_dword = lsu_lsc_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_d_load = lsu_lsc_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_d_store = lsu_lsc_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_d_dma = lsu_lsc_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 245:50] - assign dccm_ctl_io_lsu_pkt_m_by = lsu_lsc_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_half = lsu_lsc_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_word = lsu_lsc_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_load = lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_dma = lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 246:50] - assign dccm_ctl_io_lsu_pkt_r_by = lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_half = lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_word = lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_load = lsu_lsc_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_store = lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_dma = lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 247:50] - assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 248:50] - assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 249:50] - assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 250:50] - assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 251:50] - assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 252:50] - assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 253:50] - assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[el2_lsu.scala 254:50] - assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[el2_lsu.scala 255:50] - assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 256:50] - assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d[15:0]; // @[el2_lsu.scala 257:50] - assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[el2_lsu.scala 258:50] - assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r[15:0]; // @[el2_lsu.scala 259:50] - assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[el2_lsu.scala 260:50] - assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[el2_lsu.scala 261:50] - assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[el2_lsu.scala 262:50] - assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 263:50] - assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 264:50] - assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[el2_lsu.scala 265:50] - assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 267:50] - assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 268:50] - assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 269:50] - assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 270:50] - assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 271:50] - assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 272:50] - assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 273:50] - assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 276:50] - assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 277:50] - assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 280:50] - assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[el2_lsu.scala 281:50] - assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[el2_lsu.scala 282:50] - assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 283:50] - assign dccm_ctl_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 284:50] - assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 285:50] - assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m[2:0]; // @[el2_lsu.scala 286:50] - assign dccm_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 287:50] - assign dccm_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 288:50] - assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[el2_lsu.scala 289:50] - assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 290:50] - assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_lsu.scala 293:50] - assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_lsu.scala 294:50] - assign dccm_ctl_io_picm_rd_data = io_picm_rd_data; // @[el2_lsu.scala 295:50] - assign dccm_ctl_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 296:50] + assign dccm_ctl_io_lsu_c2_m_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 240:46] + assign dccm_ctl_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_m_clk; // @[el2_lsu.scala 241:46] + assign dccm_ctl_io_lsu_free_c2_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 242:46] + assign dccm_ctl_io_lsu_store_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 244:46] + assign dccm_ctl_io_lsu_pkt_d_word = lsu_lsc_ctl_io_lsu_pkt_d_word; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_d_dword = lsu_lsc_ctl_io_lsu_pkt_d_dword; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_d_load = lsu_lsc_ctl_io_lsu_pkt_d_load; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_d_store = lsu_lsc_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_d_dma = lsu_lsc_ctl_io_lsu_pkt_d_dma; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 246:46] + assign dccm_ctl_io_lsu_pkt_m_by = lsu_lsc_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_half = lsu_lsc_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_word = lsu_lsc_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_load = lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_dma = lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 247:46] + assign dccm_ctl_io_lsu_pkt_r_by = lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_half = lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_word = lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_load = lsu_lsc_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_store = lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_dma = lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 248:46] + assign dccm_ctl_io_addr_in_dccm_d = lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 249:46] + assign dccm_ctl_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 250:46] + assign dccm_ctl_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 251:46] + assign dccm_ctl_io_addr_in_pic_d = lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 252:46] + assign dccm_ctl_io_addr_in_pic_m = lsu_lsc_ctl_io_addr_in_pic_m; // @[el2_lsu.scala 253:46] + assign dccm_ctl_io_addr_in_pic_r = lsu_lsc_ctl_io_addr_in_pic_r; // @[el2_lsu.scala 254:46] + assign dccm_ctl_io_lsu_raw_fwd_lo_r = lsu_raw_fwd_lo_r; // @[el2_lsu.scala 255:46] + assign dccm_ctl_io_lsu_raw_fwd_hi_r = lsu_raw_fwd_hi_r; // @[el2_lsu.scala 256:46] + assign dccm_ctl_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 257:46] + assign dccm_ctl_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 258:46] + assign dccm_ctl_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[el2_lsu.scala 259:46] + assign dccm_ctl_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 260:46] + assign dccm_ctl_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[el2_lsu.scala 261:46] + assign dccm_ctl_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[el2_lsu.scala 262:46] + assign dccm_ctl_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r[15:0]; // @[el2_lsu.scala 263:46] + assign dccm_ctl_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 264:46] + assign dccm_ctl_io_stbuf_addr_any = stbuf_io_stbuf_addr_any; // @[el2_lsu.scala 265:46] + assign dccm_ctl_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[el2_lsu.scala 266:46] + assign dccm_ctl_io_stbuf_ecc_any = ecc_io_stbuf_ecc_any; // @[el2_lsu.scala 267:46] + assign dccm_ctl_io_stbuf_fwddata_hi_m = stbuf_io_stbuf_fwddata_hi_m; // @[el2_lsu.scala 268:46] + assign dccm_ctl_io_stbuf_fwddata_lo_m = stbuf_io_stbuf_fwddata_lo_m; // @[el2_lsu.scala 269:46] + assign dccm_ctl_io_stbuf_fwdbyteen_lo_m = stbuf_io_stbuf_fwdbyteen_lo_m; // @[el2_lsu.scala 270:46] + assign dccm_ctl_io_stbuf_fwdbyteen_hi_m = stbuf_io_stbuf_fwdbyteen_hi_m; // @[el2_lsu.scala 271:46] + assign dccm_ctl_io_lsu_double_ecc_error_r = ecc_io_lsu_double_ecc_error_r; // @[el2_lsu.scala 272:46] + assign dccm_ctl_io_single_ecc_error_hi_r = ecc_io_single_ecc_error_hi_r; // @[el2_lsu.scala 273:46] + assign dccm_ctl_io_single_ecc_error_lo_r = ecc_io_single_ecc_error_lo_r; // @[el2_lsu.scala 274:46] + assign dccm_ctl_io_sec_data_hi_r_ff = ecc_io_sec_data_hi_r_ff; // @[el2_lsu.scala 277:46] + assign dccm_ctl_io_sec_data_lo_r_ff = ecc_io_sec_data_lo_r_ff; // @[el2_lsu.scala 278:46] + assign dccm_ctl_io_sec_data_ecc_hi_r_ff = ecc_io_sec_data_ecc_hi_r_ff; // @[el2_lsu.scala 279:46] + assign dccm_ctl_io_sec_data_ecc_lo_r_ff = ecc_io_sec_data_ecc_lo_r_ff; // @[el2_lsu.scala 280:46] + assign dccm_ctl_io_lsu_double_ecc_error_m = ecc_io_lsu_double_ecc_error_m; // @[el2_lsu.scala 281:46] + assign dccm_ctl_io_sec_data_hi_m = ecc_io_sec_data_hi_m; // @[el2_lsu.scala 282:46] + assign dccm_ctl_io_sec_data_lo_m = ecc_io_sec_data_lo_m; // @[el2_lsu.scala 283:46] + assign dccm_ctl_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 284:46] + assign dccm_ctl_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 285:46] + assign dccm_ctl_io_dma_pic_wen = _T_10 & lsu_lsc_ctl_io_addr_in_pic_d; // @[el2_lsu.scala 286:46] + assign dccm_ctl_io_dma_mem_tag_m = dma_mem_tag_m; // @[el2_lsu.scala 287:46] + assign dccm_ctl_io_dma_mem_addr = io_dma_mem_addr; // @[el2_lsu.scala 288:46] + assign dccm_ctl_io_dma_mem_wdata = io_dma_mem_wdata; // @[el2_lsu.scala 289:46] + assign dccm_ctl_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[el2_lsu.scala 290:46] + assign dccm_ctl_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 291:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_hi = ecc_io_dma_dccm_wdata_ecc_hi; // @[el2_lsu.scala 292:46] + assign dccm_ctl_io_dma_dccm_wdata_ecc_lo = ecc_io_dma_dccm_wdata_ecc_lo; // @[el2_lsu.scala 293:46] + assign dccm_ctl_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[el2_lsu.scala 294:46] + assign dccm_ctl_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[el2_lsu.scala 295:46] + assign dccm_ctl_io_picm_rd_data = io_picm_rd_data; // @[el2_lsu.scala 296:46] + assign dccm_ctl_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 297:46] assign stbuf_clock = clock; assign stbuf_reset = reset; - assign stbuf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 319:50] - assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 320:56] + assign stbuf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 319:49] + assign stbuf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 320:48] assign stbuf_io_lsu_stbuf_c1_clk = clkdomain_io_lsu_stbuf_c1_clk; // @[el2_lsu.scala 321:54] assign stbuf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 322:54] - assign stbuf_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 323:56] - assign stbuf_io_lsu_pkt_m_dma = lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 323:56] - assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 323:56] - assign stbuf_io_lsu_pkt_r_by = lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_half = lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_word = lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_dword = lsu_lsc_ctl_io_lsu_pkt_r_dword; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_store = lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_dma = lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 324:56] - assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 324:56] - assign stbuf_io_store_stbuf_reqvld_r = _T_28 & _T_19; // @[el2_lsu.scala 325:56] - assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 326:50] - assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 327:50] + assign stbuf_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 323:48] + assign stbuf_io_lsu_pkt_m_dma = lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 323:48] + assign stbuf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 323:48] + assign stbuf_io_lsu_pkt_r_by = lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_half = lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_word = lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_dword = lsu_lsc_ctl_io_lsu_pkt_r_dword; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_store = lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_dma = lsu_lsc_ctl_io_lsu_pkt_r_dma; // @[el2_lsu.scala 324:48] + assign stbuf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 324:48] + assign stbuf_io_store_stbuf_reqvld_r = _T_28 & _T_19; // @[el2_lsu.scala 325:48] + assign stbuf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 326:49] + assign stbuf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 327:49] assign stbuf_io_store_data_hi_r = dccm_ctl_io_store_data_hi_r; // @[el2_lsu.scala 328:62] assign stbuf_io_store_data_lo_r = dccm_ctl_io_store_data_lo_r; // @[el2_lsu.scala 329:62] - assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 330:50] + assign stbuf_io_store_datafn_hi_r = dccm_ctl_io_store_datafn_hi_r; // @[el2_lsu.scala 330:49] assign stbuf_io_store_datafn_lo_r = dccm_ctl_io_store_datafn_lo_r; // @[el2_lsu.scala 331:56] - assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 332:60] + assign stbuf_io_lsu_stbuf_commit_any = dccm_ctl_io_lsu_stbuf_commit_any; // @[el2_lsu.scala 332:52] assign stbuf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d[15:0]; // @[el2_lsu.scala 333:64] assign stbuf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 334:64] assign stbuf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 335:64] assign stbuf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d[15:0]; // @[el2_lsu.scala 336:64] assign stbuf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 337:64] assign stbuf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 338:64] - assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 339:50] + assign stbuf_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 339:49] assign stbuf_io_addr_in_dccm_r = lsu_lsc_ctl_io_addr_in_dccm_r; // @[el2_lsu.scala 340:56] + assign stbuf_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 342:49] assign ecc_clock = clock; assign ecc_reset = reset; assign ecc_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 346:52] @@ -4969,6 +11607,7 @@ module el2_lsu( assign ecc_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 347:52] assign ecc_io_lsu_pkt_m_dma = lsu_lsc_ctl_io_lsu_pkt_m_dma; // @[el2_lsu.scala 347:52] assign ecc_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 347:52] + assign ecc_io_stbuf_data_any = stbuf_io_stbuf_data_any; // @[el2_lsu.scala 349:54] assign ecc_io_dec_tlu_core_ecc_disable = io_dec_tlu_core_ecc_disable; // @[el2_lsu.scala 350:50] assign ecc_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m[15:0]; // @[el2_lsu.scala 355:58] assign ecc_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m[15:0]; // @[el2_lsu.scala 356:58] @@ -4977,8 +11616,13 @@ module el2_lsu( assign ecc_io_dccm_data_ecc_hi_m = dccm_ctl_io_dccm_data_ecc_hi_m; // @[el2_lsu.scala 363:50] assign ecc_io_dccm_data_ecc_lo_m = dccm_ctl_io_dccm_data_ecc_lo_m; // @[el2_lsu.scala 364:50] assign ecc_io_ld_single_ecc_error_r = dccm_ctl_io_ld_single_ecc_error_r; // @[el2_lsu.scala 365:50] + assign ecc_io_ld_single_ecc_error_r_ff = dccm_ctl_io_ld_single_ecc_error_r_ff; // @[el2_lsu.scala 366:50] assign ecc_io_lsu_dccm_rden_m = dccm_ctl_io_lsu_dccm_rden_m; // @[el2_lsu.scala 367:50] assign ecc_io_addr_in_dccm_m = lsu_lsc_ctl_io_addr_in_dccm_m; // @[el2_lsu.scala 368:50] + assign ecc_io_dma_dccm_wen = _T_10 & lsu_lsc_ctl_io_addr_in_dccm_d; // @[el2_lsu.scala 369:50] + assign ecc_io_dma_dccm_wdata_lo = dma_dccm_wdata[31:0]; // @[el2_lsu.scala 370:50] + assign ecc_io_dma_dccm_wdata_hi = dma_dccm_wdata[63:32]; // @[el2_lsu.scala 371:50] + assign ecc_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 372:50] assign trigger_io_trigger_pkt_any_0_select = io_trigger_pkt_any_0_select; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_match_ = io_trigger_pkt_any_0_match_; // @[el2_lsu.scala 376:50] assign trigger_io_trigger_pkt_any_0_store = io_trigger_pkt_any_0_store; // @[el2_lsu.scala 376:50] @@ -5009,18 +11653,75 @@ module el2_lsu( assign trigger_io_store_data_m = lsu_lsc_ctl_io_store_data_m; // @[el2_lsu.scala 379:50] assign clkdomain_clock = clock; assign clkdomain_reset = reset; + assign clkdomain_io_free_clk = io_free_clk; // @[el2_lsu.scala 385:50] assign clkdomain_io_clk_override = io_clk_override; // @[el2_lsu.scala 386:50] assign clkdomain_io_dma_dccm_req = io_dma_dccm_req; // @[el2_lsu.scala 388:50] assign clkdomain_io_ldst_stbuf_reqvld_r = stbuf_io_ldst_stbuf_reqvld_r; // @[el2_lsu.scala 389:50] assign clkdomain_io_stbuf_reqvld_any = stbuf_io_stbuf_reqvld_any; // @[el2_lsu.scala 390:50] assign clkdomain_io_stbuf_reqvld_flushed_any = stbuf_io_stbuf_reqvld_flushed_any; // @[el2_lsu.scala 391:50] + assign clkdomain_io_lsu_busreq_r = bus_intf_io_lsu_busreq_r; // @[el2_lsu.scala 392:50] + assign clkdomain_io_lsu_bus_buffer_pend_any = bus_intf_io_lsu_bus_buffer_pend_any; // @[el2_lsu.scala 393:50] + assign clkdomain_io_lsu_bus_buffer_empty_any = bus_intf_io_lsu_bus_buffer_empty_any; // @[el2_lsu.scala 394:50] + assign clkdomain_io_lsu_stbuf_empty_any = stbuf_io_lsu_stbuf_empty_any; // @[el2_lsu.scala 395:50] assign clkdomain_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu.scala 396:50] assign clkdomain_io_lsu_p_valid = io_lsu_p_valid; // @[el2_lsu.scala 397:50] assign clkdomain_io_lsu_pkt_d_store = lsu_lsc_ctl_io_lsu_pkt_d_store; // @[el2_lsu.scala 398:50] assign clkdomain_io_lsu_pkt_d_valid = lsu_lsc_ctl_io_lsu_pkt_d_valid; // @[el2_lsu.scala 398:50] assign clkdomain_io_lsu_pkt_m_store = lsu_lsc_ctl_io_lsu_pkt_m_store; // @[el2_lsu.scala 399:50] assign clkdomain_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 399:50] + assign clkdomain_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 400:50] assign clkdomain_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 401:50] + assign bus_intf_clock = clock; + assign bus_intf_reset = reset; + assign bus_intf_io_scan_mode = io_scan_mode; // @[el2_lsu.scala 405:49] + assign bus_intf_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu.scala 406:49] + assign bus_intf_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu.scala 407:49] + assign bus_intf_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu.scala 408:49] + assign bus_intf_io_lsu_c1_m_clk = clkdomain_io_lsu_c1_m_clk; // @[el2_lsu.scala 409:49] + assign bus_intf_io_lsu_c1_r_clk = clkdomain_io_lsu_c1_r_clk; // @[el2_lsu.scala 410:49] + assign bus_intf_io_lsu_c2_r_clk = clkdomain_io_lsu_c2_r_clk; // @[el2_lsu.scala 411:49] + assign bus_intf_io_lsu_bus_ibuf_c1_clk = clkdomain_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu.scala 412:49] + assign bus_intf_io_lsu_bus_obuf_c1_clk = clkdomain_io_lsu_bus_obuf_c1_clk; // @[el2_lsu.scala 413:49] + assign bus_intf_io_lsu_bus_buf_c1_clk = clkdomain_io_lsu_bus_buf_c1_clk; // @[el2_lsu.scala 414:49] + assign bus_intf_io_lsu_free_c2_clk = clkdomain_io_lsu_free_c2_clk; // @[el2_lsu.scala 415:49] + assign bus_intf_io_free_clk = io_free_clk; // @[el2_lsu.scala 416:49] + assign bus_intf_io_lsu_busm_clk = clkdomain_io_lsu_busm_clk; // @[el2_lsu.scala 417:49] + assign bus_intf_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu.scala 418:49] + assign bus_intf_io_lsu_busreq_m = _T_39 & _T_40; // @[el2_lsu.scala 419:49] + assign bus_intf_io_lsu_pkt_m_by = lsu_lsc_ctl_io_lsu_pkt_m_by; // @[el2_lsu.scala 427:49] + assign bus_intf_io_lsu_pkt_m_half = lsu_lsc_ctl_io_lsu_pkt_m_half; // @[el2_lsu.scala 427:49] + assign bus_intf_io_lsu_pkt_m_word = lsu_lsc_ctl_io_lsu_pkt_m_word; // @[el2_lsu.scala 427:49] + assign bus_intf_io_lsu_pkt_m_load = lsu_lsc_ctl_io_lsu_pkt_m_load; // @[el2_lsu.scala 427:49] + assign bus_intf_io_lsu_pkt_m_valid = lsu_lsc_ctl_io_lsu_pkt_m_valid; // @[el2_lsu.scala 427:49] + assign bus_intf_io_lsu_pkt_r_by = lsu_lsc_ctl_io_lsu_pkt_r_by; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_half = lsu_lsc_ctl_io_lsu_pkt_r_half; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_word = lsu_lsc_ctl_io_lsu_pkt_r_word; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_load = lsu_lsc_ctl_io_lsu_pkt_r_load; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_store = lsu_lsc_ctl_io_lsu_pkt_r_store; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_unsign = lsu_lsc_ctl_io_lsu_pkt_r_unsign; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_pkt_r_valid = lsu_lsc_ctl_io_lsu_pkt_r_valid; // @[el2_lsu.scala 428:49] + assign bus_intf_io_lsu_addr_d = lsu_lsc_ctl_io_lsu_addr_d; // @[el2_lsu.scala 420:49] + assign bus_intf_io_lsu_addr_m = lsu_lsc_ctl_io_lsu_addr_m; // @[el2_lsu.scala 421:49] + assign bus_intf_io_lsu_addr_r = lsu_lsc_ctl_io_lsu_addr_r; // @[el2_lsu.scala 422:49] + assign bus_intf_io_end_addr_d = lsu_lsc_ctl_io_end_addr_d; // @[el2_lsu.scala 423:49] + assign bus_intf_io_end_addr_m = lsu_lsc_ctl_io_end_addr_m; // @[el2_lsu.scala 424:49] + assign bus_intf_io_end_addr_r = lsu_lsc_ctl_io_end_addr_r; // @[el2_lsu.scala 425:49] + assign bus_intf_io_store_data_r = dccm_ctl_io_store_data_r; // @[el2_lsu.scala 426:49] + assign bus_intf_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu.scala 429:49] + assign bus_intf_io_lsu_commit_r = lsu_lsc_ctl_io_lsu_commit_r; // @[el2_lsu.scala 430:49] + assign bus_intf_io_is_sideeffects_m = lsu_lsc_ctl_io_is_sideeffects_m; // @[el2_lsu.scala 431:49] + assign bus_intf_io_flush_m_up = io_dec_tlu_flush_lower_r; // @[el2_lsu.scala 432:49] + assign bus_intf_io_flush_r = io_dec_tlu_i0_kill_writeb_r; // @[el2_lsu.scala 433:49] + assign bus_intf_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu.scala 452:49] + assign bus_intf_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu.scala 464:49] + assign bus_intf_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu.scala 468:49] + assign bus_intf_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu.scala 470:49] + assign bus_intf_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu.scala 471:49] + assign bus_intf_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu.scala 473:49] + assign bus_intf_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu.scala 484:49] + assign bus_intf_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu.scala 486:49] + assign bus_intf_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu.scala 487:49] + assign bus_intf_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu.scala 490:49] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -5057,14 +11758,14 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - _T_52 = _RAND_0[2:0]; + dma_mem_tag_m = _RAND_0[2:0]; _RAND_1 = {1{`RANDOM}}; lsu_raw_fwd_hi_r = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; lsu_raw_fwd_lo_r = _RAND_2[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin - _T_52 = 3'h0; + dma_mem_tag_m = 3'h0; end if (reset) begin lsu_raw_fwd_hi_r = 1'h0; @@ -5080,9 +11781,9 @@ end // initial `endif // SYNTHESIS always @(posedge clkdomain_io_lsu_c1_m_clk or posedge reset) begin if (reset) begin - _T_52 <= 3'h0; + dma_mem_tag_m <= 3'h0; end else begin - _T_52 <= io_dma_mem_tag; + dma_mem_tag_m <= io_dma_mem_tag; end end always @(posedge clkdomain_io_lsu_c2_r_clk or posedge reset) begin diff --git a/el2_lsu_bus_buffer.anno.json b/el2_lsu_bus_buffer.anno.json index 7f0f8e5f..6d0bf36f 100644 --- a/el2_lsu_bus_buffer.anno.json +++ b/el2_lsu_bus_buffer.anno.json @@ -1,4 +1,22 @@ [ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_lo", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_fwddata_buf_hi", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_valid_m", @@ -22,6 +40,15 @@ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_wready" ] }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi", + "sources":[ + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_end_addr_m" + ] + }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_imprecise_error_store_any", @@ -61,19 +88,12 @@ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_araddr", - "sources":[ - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awaddr" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_lo", "sources":[ - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m" ] }, @@ -86,23 +106,16 @@ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arsize", - "sources":[ - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awsize" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_buffer_full_any", "sources":[ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_d", "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_dec_lsu_valid_raw_d", - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_m", - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r", - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r" + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r", + "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_r" ] }, { @@ -127,13 +140,6 @@ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_bus_clk_en_q" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_arcache", - "sources":[ - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_axi_awcache" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_tag_m", @@ -142,15 +148,6 @@ "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_dual_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ld_byte_hit_buf_hi", - "sources":[ - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_busreq_m", - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_ldst_byteen_ext_m", - "~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_addr_m" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_buffer|el2_lsu_bus_buffer>io_lsu_nonblock_load_data", @@ -162,6 +159,11 @@ "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_lsu_bus_buffer.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." diff --git a/el2_lsu_bus_buffer.fir b/el2_lsu_bus_buffer.fir index 98c048e8..bf122100 100644 --- a/el2_lsu_bus_buffer.fir +++ b/el2_lsu_bus_buffer.fir @@ -1,6226 +1,6513 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu_bus_buffer : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + module el2_lsu_bus_buffer : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_awready : UInt<1>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} - wire ldst_byteen_hi_m : UInt<4> - ldst_byteen_hi_m <= UInt<1>("h00") - wire ldst_byteen_lo_m : UInt<4> - ldst_byteen_lo_m <= UInt<1>("h00") - wire ld_addr_hitvec_lo : UInt<4> - ld_addr_hitvec_lo <= UInt<1>("h00") - wire ld_addr_hitvec_hi : UInt<4> - ld_addr_hitvec_hi <= UInt<1>("h00") - wire ld_byte_hitvec_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 138:43] - wire ld_byte_hitvec_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 139:43] - wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 140:43] - wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 141:43] - wire ld_addr_ibuf_hit_lo : UInt<1> - ld_addr_ibuf_hit_lo <= UInt<1>("h00") - wire ld_addr_ibuf_hit_hi : UInt<1> - ld_addr_ibuf_hit_hi <= UInt<1>("h00") - wire ld_byte_ibuf_hit_lo : UInt<4> - ld_byte_ibuf_hit_lo <= UInt<1>("h00") - wire ld_byte_ibuf_hit_hi : UInt<4> - ld_byte_ibuf_hit_hi <= UInt<1>("h00") - wire ldst_byteen_r : UInt<4> - ldst_byteen_r <= UInt<1>("h00") - wire ldst_byteen_hi_r : UInt<4> - ldst_byteen_hi_r <= UInt<1>("h00") - wire ldst_byteen_lo_r : UInt<4> - ldst_byteen_lo_r <= UInt<1>("h00") - wire store_data_hi_r : UInt<32> - store_data_hi_r <= UInt<1>("h00") - wire store_data_lo_r : UInt<32> - store_data_lo_r <= UInt<1>("h00") - wire is_aligned_r : UInt<1> - is_aligned_r <= UInt<1>("h00") - wire ldst_samedw_r : UInt<1> - ldst_samedw_r <= UInt<1>("h00") - wire lsu_nonblock_load_valid_r : UInt<1> - lsu_nonblock_load_valid_r <= UInt<1>("h00") - wire lsu_nonblock_load_data_hi : UInt<32> - lsu_nonblock_load_data_hi <= UInt<1>("h00") - wire lsu_nonblock_load_data_lo : UInt<32> - lsu_nonblock_load_data_lo <= UInt<1>("h00") - wire lsu_nonblock_data_unalgn : UInt<32> - lsu_nonblock_data_unalgn <= UInt<1>("h00") - wire lsu_nonblock_addr_offset : UInt<2> - lsu_nonblock_addr_offset <= UInt<1>("h00") - wire lsu_nonblock_sz : UInt<2> - lsu_nonblock_sz <= UInt<1>("h00") - wire lsu_nonblock_unsign : UInt<1> - lsu_nonblock_unsign <= UInt<1>("h00") - wire lsu_nonblock_dual : UInt<1> - lsu_nonblock_dual <= UInt<1>("h00") - wire lsu_nonblock_load_data_ready : UInt<1> - lsu_nonblock_load_data_ready <= UInt<1>("h00") - wire CmdPtr0Dec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 165:43] - wire CmdPtr1Dec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 166:43] - wire RspPtrDec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 167:43] + wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 121:22] + wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 122:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") wire CmdPtr0 : UInt<2> CmdPtr0 <= UInt<1>("h00") - wire CmdPtr1 : UInt<2> - CmdPtr1 <= UInt<1>("h00") - wire RspPtr : UInt<2> - RspPtr <= UInt<1>("h00") - wire WrPtr0_m : UInt<2> - WrPtr0_m <= UInt<1>("h00") - wire WrPtr0_r : UInt<2> - WrPtr0_r <= UInt<1>("h00") - wire WrPtr1_m : UInt<2> - WrPtr1_m <= UInt<1>("h00") - wire WrPtr1_r : UInt<2> - WrPtr1_r <= UInt<1>("h00") - wire found_cmdptr0 : UInt<1> - found_cmdptr0 <= UInt<1>("h00") - wire found_cmdptr1 : UInt<1> - found_cmdptr1 <= UInt<1>("h00") - wire buf_numvld_any : UInt<4> - buf_numvld_any <= UInt<1>("h00") - wire buf_numvld_wrcmd_any : UInt<4> - buf_numvld_wrcmd_any <= UInt<1>("h00") - wire buf_numvld_cmd_any : UInt<4> - buf_numvld_cmd_any <= UInt<1>("h00") - wire buf_numvld_pend_any : UInt<4> - buf_numvld_pend_any <= UInt<1>("h00") - wire any_done_wait_state : UInt<1> - any_done_wait_state <= UInt<1>("h00") - wire bus_sideeffect_pend : UInt<1> - bus_sideeffect_pend <= UInt<1>("h00") - wire bus_pend_trxn : UInt<8> - bus_pend_trxn <= UInt<1>("h00") - wire bus_pend_trxnQ : UInt<8> - bus_pend_trxnQ <= UInt<1>("h00") - wire bus_pend_trxn_ns : UInt<8> - bus_pend_trxn_ns <= UInt<1>("h00") - wire lsu_bus_cntr_overflow : UInt<1> - lsu_bus_cntr_overflow <= UInt<1>("h00") - wire bus_coalescing_disable : UInt<1> - bus_coalescing_disable <= UInt<1>("h00") - wire mdbhd_en : UInt<1> - mdbhd_en <= UInt<1>("h00") - wire bus_addr_match_pending : UInt<1> - bus_addr_match_pending <= UInt<1>("h00") - wire bus_cmd_sent : UInt<1> - bus_cmd_sent <= UInt<1>("h00") - wire bus_cmd_ready : UInt<1> - bus_cmd_ready <= UInt<1>("h00") - wire bus_wcmd_sent : UInt<1> - bus_wcmd_sent <= UInt<1>("h00") - wire bus_wdata_sent : UInt<1> - bus_wdata_sent <= UInt<1>("h00") - wire bus_rsp_read : UInt<1> - bus_rsp_read <= UInt<1>("h00") - wire bus_rsp_write : UInt<1> - bus_rsp_write <= UInt<1>("h00") - wire bus_rsp_read_tag : UInt<3> - bus_rsp_read_tag <= UInt<1>("h00") - wire bus_rsp_write_tag : UInt<3> - bus_rsp_write_tag <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 127:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 128:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_2 = eq(_T, _T_1) @[el2_lsu_bus_buffer.scala 130:74] + node _T_3 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 130:109] + node _T_4 = and(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 130:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_6 = and(_T_4, _T_5) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_9 = eq(_T_7, _T_8) @[el2_lsu_bus_buffer.scala 130:74] + node _T_10 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 130:109] + node _T_11 = and(_T_9, _T_10) @[el2_lsu_bus_buffer.scala 130:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_13 = and(_T_11, _T_12) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_16 = eq(_T_14, _T_15) @[el2_lsu_bus_buffer.scala 130:74] + node _T_17 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 130:109] + node _T_18 = and(_T_16, _T_17) @[el2_lsu_bus_buffer.scala 130:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_20 = and(_T_18, _T_19) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_23 = eq(_T_21, _T_22) @[el2_lsu_bus_buffer.scala 130:74] + node _T_24 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 130:109] + node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 130:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_27 = and(_T_25, _T_26) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_30 = eq(_T_28, _T_29) @[el2_lsu_bus_buffer.scala 131:74] + node _T_31 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 131:109] + node _T_32 = and(_T_30, _T_31) @[el2_lsu_bus_buffer.scala 131:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_34 = and(_T_32, _T_33) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_37 = eq(_T_35, _T_36) @[el2_lsu_bus_buffer.scala 131:74] + node _T_38 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 131:109] + node _T_39 = and(_T_37, _T_38) @[el2_lsu_bus_buffer.scala 131:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_41 = and(_T_39, _T_40) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_44 = eq(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 131:74] + node _T_45 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 131:109] + node _T_46 = and(_T_44, _T_45) @[el2_lsu_bus_buffer.scala 131:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_51 = eq(_T_49, _T_50) @[el2_lsu_bus_buffer.scala 131:74] + node _T_52 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 131:109] + node _T_53 = and(_T_51, _T_52) @[el2_lsu_bus_buffer.scala 131:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_55 = and(_T_53, _T_54) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 132:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 134:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 136:24] + buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 138:26] + buf_nxtstate[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 140:23] + buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 142:25] + buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 144:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 146:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 148:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + wire buf_data_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 150:25] + buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 152:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 154:26] + buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] wire bus_rsp_read_error : UInt<1> bus_rsp_read_error <= UInt<1>("h00") - wire bus_rsp_write_error : UInt<1> - bus_rsp_write_error <= UInt<1>("h00") wire bus_rsp_rdata : UInt<64> bus_rsp_rdata <= UInt<1>("h00") - wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 204:43] - wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 205:43] - wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 206:43] - wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 207:43] - wire buf_sideeffect : UInt<1>[4] @[el2_lsu_bus_buffer.scala 208:43] - wire buf_write : UInt<1>[4] @[el2_lsu_bus_buffer.scala 209:43] - wire buf_unsign : UInt<1>[4] @[el2_lsu_bus_buffer.scala 210:43] - wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 211:43] - wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 212:43] - wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 213:43] - wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 214:43] - wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 215:43] - wire buf_ldfwd : UInt<1>[4] @[el2_lsu_bus_buffer.scala 216:43] - wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 217:43] - wire buf_error : UInt<1>[4] @[el2_lsu_bus_buffer.scala 218:43] - wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 219:43] - wire buf_age : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 220:43] - wire buf_age_younger : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 221:43] - wire buf_rspage : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 222:43] - wire buf_rsp_pickage : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 223:43] - wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 225:43] - wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 226:43] - wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 227:43] - wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 228:43] - wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 229:43] - wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 230:43] - wire buf_dual_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 231:43] - wire buf_samedw_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 232:43] - wire buf_nomerge_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 233:43] - wire buf_sideeffect_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 234:43] - wire buf_unsign_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 235:43] - wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 236:43] - wire buf_write_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 237:43] - wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 238:43] - wire buf_dualhi_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 239:43] - wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 240:43] - wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 241:43] - wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 242:43] - wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 243:43] - wire buf_byteen_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 244:43] - wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 245:43] - wire buf_data_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 246:43] - wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 247:43] - wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 248:43] - wire buf_age_in : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 249:43] - wire buf_ageQ : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 250:43] - wire buf_rspage_set : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 251:43] - wire buf_rspage_in : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 252:43] - wire buf_rspageQ : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 253:43] - wire ibuf_valid : UInt<1> - ibuf_valid <= UInt<1>("h00") - wire ibuf_dual : UInt<1> - ibuf_dual <= UInt<1>("h00") - wire ibuf_samedw : UInt<1> - ibuf_samedw <= UInt<1>("h00") - wire ibuf_nomerge : UInt<1> - ibuf_nomerge <= UInt<1>("h00") - wire ibuf_tag : UInt<2> - ibuf_tag <= UInt<1>("h00") - wire ibuf_dualtag : UInt<2> - ibuf_dualtag <= UInt<1>("h00") - wire ibuf_sideeffect : UInt<1> - ibuf_sideeffect <= UInt<1>("h00") - wire ibuf_unsign : UInt<1> - ibuf_unsign <= UInt<1>("h00") - wire ibuf_write : UInt<1> - ibuf_write <= UInt<1>("h00") - wire ibuf_sz : UInt<2> - ibuf_sz <= UInt<1>("h00") - wire ibuf_byteen : UInt<4> - ibuf_byteen <= UInt<1>("h00") - wire ibuf_addr : UInt<32> - ibuf_addr <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 159:25] + buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 162:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 167:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 169:21] + buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 172:27] + buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 174:25] + buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 180:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 184:23] + buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") wire ibuf_data : UInt<32> ibuf_data <= UInt<1>("h00") - wire ibuf_timer : UInt<3> - ibuf_timer <= UInt<1>("h00") - wire ibuf_byp : UInt<1> - ibuf_byp <= UInt<1>("h00") - wire ibuf_wr_en : UInt<1> - ibuf_wr_en <= UInt<1>("h00") - wire ibuf_rst : UInt<1> - ibuf_rst <= UInt<1>("h00") - wire ibuf_force_drain : UInt<1> - ibuf_force_drain <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 191:98] + node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 191:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 191:98] + node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 191:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 191:98] + node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 191:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 191:98] + node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 191:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 191:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 192:98] + node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 192:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 192:98] + node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 192:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 192:98] + node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 192:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 192:98] + node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 192:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 192:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 194:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 194:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 194:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 194:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 194:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 194:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 194:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 194:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 194:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 194:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 194:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 194:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 194:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 194:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 194:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 194:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 194:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 194:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 194:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 194:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 194:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 194:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 194:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 194:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 194:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 194:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 194:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 194:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 194:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 194:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 194:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 194:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 195:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 195:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 195:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 195:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 195:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 195:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 195:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 195:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 195:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 195:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 195:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 195:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 195:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 195:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 195:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 195:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 195:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 195:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 195:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 195:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 195:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 195:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 195:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 195:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 195:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 195:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 195:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 195:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 195:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 195:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 195:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 195:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 197:29] + buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 199:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 199:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 199:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 199:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 199:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 199:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 199:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 199:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 199:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 199:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 199:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 199:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 199:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 199:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 199:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 199:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 199:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 199:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 199:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 199:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 199:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 199:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 199:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 199:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 199:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 199:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 199:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 199:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 199:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 199:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 199:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 199:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 199:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 199:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 199:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 199:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 199:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 199:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 199:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 199:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 199:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 199:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 199:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 199:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 199:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 199:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 199:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 199:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 199:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 200:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 200:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 200:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 200:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 200:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 200:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 200:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 200:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 200:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 200:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 200:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 200:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 200:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 200:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 200:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 200:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 200:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 200:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 200:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 200:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 200:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 200:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 200:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 200:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 200:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 200:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 200:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 200:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 200:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 200:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 200:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 200:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 200:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 200:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 200:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 200:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 200:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 200:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 200:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 200:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 200:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 200:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 200:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 200:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 200:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 200:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 200:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 200:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 200:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 205:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 205:64] + node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 205:51] + node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 205:73] + node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 205:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 205:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 206:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 206:64] + node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 206:51] + node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 206:73] + node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 206:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 206:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[el2_lsu_bus_buffer.scala 210:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[el2_lsu_bus_buffer.scala 210:69] + ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 210:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[el2_lsu_bus_buffer.scala 211:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[el2_lsu_bus_buffer.scala 211:69] + ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 211:23] + wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 213:22] + buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 216:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 216:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 216:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 216:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 217:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 217:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 217:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 217:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 218:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_560 = and(_T_558, _T_559) @[el2_lsu_bus_buffer.scala 218:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 218:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_565 = and(_T_563, _T_564) @[el2_lsu_bus_buffer.scala 218:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 218:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_570 = and(_T_568, _T_569) @[el2_lsu_bus_buffer.scala 218:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 218:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_575 = and(_T_573, _T_574) @[el2_lsu_bus_buffer.scala 218:91] + node _T_576 = or(_T_560, _T_565) @[el2_lsu_bus_buffer.scala 218:123] + node _T_577 = or(_T_576, _T_570) @[el2_lsu_bus_buffer.scala 218:123] + node _T_578 = or(_T_577, _T_575) @[el2_lsu_bus_buffer.scala 218:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 219:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_583 = and(_T_581, _T_582) @[el2_lsu_bus_buffer.scala 219:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 219:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_588 = and(_T_586, _T_587) @[el2_lsu_bus_buffer.scala 219:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 219:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_593 = and(_T_591, _T_592) @[el2_lsu_bus_buffer.scala 219:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 219:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_598 = and(_T_596, _T_597) @[el2_lsu_bus_buffer.scala 219:65] + node _T_599 = or(_T_583, _T_588) @[el2_lsu_bus_buffer.scala 219:97] + node _T_600 = or(_T_599, _T_593) @[el2_lsu_bus_buffer.scala 219:97] + node _T_601 = or(_T_600, _T_598) @[el2_lsu_bus_buffer.scala 219:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_606 = and(_T_604, _T_605) @[el2_lsu_bus_buffer.scala 220:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_611 = and(_T_609, _T_610) @[el2_lsu_bus_buffer.scala 220:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_616 = and(_T_614, _T_615) @[el2_lsu_bus_buffer.scala 220:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_621 = and(_T_619, _T_620) @[el2_lsu_bus_buffer.scala 220:65] + node _T_622 = or(_T_606, _T_611) @[el2_lsu_bus_buffer.scala 220:97] + node _T_623 = or(_T_622, _T_616) @[el2_lsu_bus_buffer.scala 220:97] + node _T_624 = or(_T_623, _T_621) @[el2_lsu_bus_buffer.scala 220:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_629 = and(_T_627, _T_628) @[el2_lsu_bus_buffer.scala 221:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_634 = and(_T_632, _T_633) @[el2_lsu_bus_buffer.scala 221:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_639 = and(_T_637, _T_638) @[el2_lsu_bus_buffer.scala 221:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_644 = and(_T_642, _T_643) @[el2_lsu_bus_buffer.scala 221:65] + node _T_645 = or(_T_629, _T_634) @[el2_lsu_bus_buffer.scala 221:97] + node _T_646 = or(_T_645, _T_639) @[el2_lsu_bus_buffer.scala 221:97] + node _T_647 = or(_T_646, _T_644) @[el2_lsu_bus_buffer.scala 221:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 222:32] + node _T_652 = or(_T_650, _T_651) @[el2_lsu_bus_buffer.scala 221:103] + io.ld_fwddata_buf_lo <= _T_652 @[el2_lsu_bus_buffer.scala 218:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 224:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_657 = and(_T_655, _T_656) @[el2_lsu_bus_buffer.scala 224:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 224:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_662 = and(_T_660, _T_661) @[el2_lsu_bus_buffer.scala 224:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 224:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_667 = and(_T_665, _T_666) @[el2_lsu_bus_buffer.scala 224:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 224:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_672 = and(_T_670, _T_671) @[el2_lsu_bus_buffer.scala 224:91] + node _T_673 = or(_T_657, _T_662) @[el2_lsu_bus_buffer.scala 224:123] + node _T_674 = or(_T_673, _T_667) @[el2_lsu_bus_buffer.scala 224:123] + node _T_675 = or(_T_674, _T_672) @[el2_lsu_bus_buffer.scala 224:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 225:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_680 = and(_T_678, _T_679) @[el2_lsu_bus_buffer.scala 225:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 225:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_685 = and(_T_683, _T_684) @[el2_lsu_bus_buffer.scala 225:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 225:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_690 = and(_T_688, _T_689) @[el2_lsu_bus_buffer.scala 225:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 225:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_695 = and(_T_693, _T_694) @[el2_lsu_bus_buffer.scala 225:65] + node _T_696 = or(_T_680, _T_685) @[el2_lsu_bus_buffer.scala 225:97] + node _T_697 = or(_T_696, _T_690) @[el2_lsu_bus_buffer.scala 225:97] + node _T_698 = or(_T_697, _T_695) @[el2_lsu_bus_buffer.scala 225:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 226:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_703 = and(_T_701, _T_702) @[el2_lsu_bus_buffer.scala 226:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 226:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_708 = and(_T_706, _T_707) @[el2_lsu_bus_buffer.scala 226:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 226:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_713 = and(_T_711, _T_712) @[el2_lsu_bus_buffer.scala 226:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 226:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_718 = and(_T_716, _T_717) @[el2_lsu_bus_buffer.scala 226:65] + node _T_719 = or(_T_703, _T_708) @[el2_lsu_bus_buffer.scala 226:97] + node _T_720 = or(_T_719, _T_713) @[el2_lsu_bus_buffer.scala 226:97] + node _T_721 = or(_T_720, _T_718) @[el2_lsu_bus_buffer.scala 226:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 227:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_726 = and(_T_724, _T_725) @[el2_lsu_bus_buffer.scala 227:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 227:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_731 = and(_T_729, _T_730) @[el2_lsu_bus_buffer.scala 227:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 227:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_736 = and(_T_734, _T_735) @[el2_lsu_bus_buffer.scala 227:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 227:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_741 = and(_T_739, _T_740) @[el2_lsu_bus_buffer.scala 227:65] + node _T_742 = or(_T_726, _T_731) @[el2_lsu_bus_buffer.scala 227:97] + node _T_743 = or(_T_742, _T_736) @[el2_lsu_bus_buffer.scala 227:97] + node _T_744 = or(_T_743, _T_741) @[el2_lsu_bus_buffer.scala 227:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 228:32] + node _T_749 = or(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 227:103] + io.ld_fwddata_buf_hi <= _T_749 @[el2_lsu_bus_buffer.scala 224:24] + node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 230:65] + node _T_750 = mux(io.lsu_pkt_r.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 235:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 235:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 236:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 236:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[el2_lsu_bus_buffer.scala 236:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 237:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 237:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[el2_lsu_bus_buffer.scala 237:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 238:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 238:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[el2_lsu_bus_buffer.scala 238:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 239:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 239:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 240:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 240:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[el2_lsu_bus_buffer.scala 240:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 241:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 242:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[el2_lsu_bus_buffer.scala 242:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 244:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 244:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 245:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 245:24] + node _T_801 = bits(io.store_data_r, 31, 8) @[el2_lsu_bus_buffer.scala 245:63] + node _T_802 = cat(UInt<8>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 246:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 246:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[el2_lsu_bus_buffer.scala 246:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 247:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 247:24] + node _T_809 = bits(io.store_data_r, 31, 24) @[el2_lsu_bus_buffer.scala 247:63] + node _T_810 = cat(UInt<24>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 249:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 249:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 250:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 250:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[el2_lsu_bus_buffer.scala 250:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 251:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 251:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[el2_lsu_bus_buffer.scala 251:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 252:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 252:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[el2_lsu_bus_buffer.scala 252:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[el2_lsu_bus_buffer.scala 255:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 256:67] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 256:74] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 257:40] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 257:26] + node _T_845 = mux(io.lsu_pkt_r.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 259:55] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[el2_lsu_bus_buffer.scala 259:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 259:79] + node ibuf_byp = and(_T_851, _T_852) @[el2_lsu_bus_buffer.scala 259:77] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 260:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 260:56] + node ibuf_wr_en = and(_T_853, _T_854) @[el2_lsu_bus_buffer.scala 260:54] wire ibuf_drain_vld : UInt<1> ibuf_drain_vld <= UInt<1>("h00") - wire ibuf_drainvec_vld : UInt<1>[4] @[el2_lsu_bus_buffer.scala 275:43] - wire ibuf_tag_in : UInt<2> - ibuf_tag_in <= UInt<1>("h00") - wire ibuf_dualtag_in : UInt<2> - ibuf_dualtag_in <= UInt<1>("h00") - wire ibuf_sz_in : UInt<2> - ibuf_sz_in <= UInt<1>("h00") - wire ibuf_addr_in : UInt<32> - ibuf_addr_in <= UInt<1>("h00") - wire ibuf_byteen_in : UInt<4> - ibuf_byteen_in <= UInt<1>("h00") - wire ibuf_data_in : UInt<32> - ibuf_data_in <= UInt<1>("h00") - wire ibuf_timer_in : UInt<3> - ibuf_timer_in <= UInt<1>("h00") - wire ibuf_byteen_out : UInt<4> - ibuf_byteen_out <= UInt<1>("h00") - wire ibuf_data_out : UInt<32> - ibuf_data_out <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 262:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[el2_lsu_bus_buffer.scala 262:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 262:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 263:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[el2_lsu_bus_buffer.scala 263:42] + node _T_859 = and(_T_858, ibuf_valid) @[el2_lsu_bus_buffer.scala 263:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 263:107] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 263:132] + node _T_862 = neq(_T_860, _T_861) @[el2_lsu_bus_buffer.scala 263:115] + node _T_863 = or(io.lsu_pkt_m.load, _T_862) @[el2_lsu_bus_buffer.scala 263:95] + node ibuf_force_drain = and(_T_859, _T_863) @[el2_lsu_bus_buffer.scala 263:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") wire ibuf_merge_en : UInt<1> ibuf_merge_en <= UInt<1>("h00") wire ibuf_merge_in : UInt<1> ibuf_merge_in <= UInt<1>("h00") - wire obuf_valid : UInt<1> - obuf_valid <= UInt<1>("h00") - wire obuf_write : UInt<1> - obuf_write <= UInt<1>("h00") - wire obuf_nosend : UInt<1> - obuf_nosend <= UInt<1>("h00") - wire obuf_rdrsp_pend : UInt<1> - obuf_rdrsp_pend <= UInt<1>("h00") - wire obuf_sideeffect : UInt<1> - obuf_sideeffect <= UInt<1>("h00") - wire obuf_addr : UInt<32> - obuf_addr <= UInt<1>("h00") - wire obuf_data : UInt<64> - obuf_data <= UInt<1>("h00") - wire obuf_sz : UInt<2> - obuf_sz <= UInt<1>("h00") - wire obuf_byteen : UInt<8> - obuf_byteen <= UInt<1>("h00") - wire obuf_merge : UInt<1> - obuf_merge <= UInt<1>("h00") - wire obuf_cmd_done : UInt<1> - obuf_cmd_done <= UInt<1>("h00") - wire obuf_data_done : UInt<1> - obuf_data_done <= UInt<1>("h00") - wire obuf_tag0 : UInt<3> - obuf_tag0 <= UInt<1>("h00") - wire obuf_tag1 : UInt<3> - obuf_tag1 <= UInt<1>("h00") - wire obuf_rdrsp_tag : UInt<3> - obuf_rdrsp_tag <= UInt<1>("h00") - wire ibuf_buf_byp : UInt<1> - ibuf_buf_byp <= UInt<1>("h00") - wire obuf_force_wr_en : UInt<1> - obuf_force_wr_en <= UInt<1>("h00") - wire obuf_wr_wait : UInt<1> - obuf_wr_wait <= UInt<1>("h00") - wire obuf_wr_en : UInt<1> - obuf_wr_en <= UInt<1>("h00") - wire obuf_wr_enQ : UInt<1> - obuf_wr_enQ <= UInt<1>("h00") - wire obuf_rst : UInt<1> - obuf_rst <= UInt<1>("h00") - wire obuf_write_in : UInt<1> - obuf_write_in <= UInt<1>("h00") - wire obuf_nosend_in : UInt<1> - obuf_nosend_in <= UInt<1>("h00") - wire obuf_rdrsp_pend_in : UInt<1> - obuf_rdrsp_pend_in <= UInt<1>("h00") - wire obuf_sideeffect_in : UInt<1> - obuf_sideeffect_in <= UInt<1>("h00") - wire obuf_aligned_in : UInt<1> - obuf_aligned_in <= UInt<1>("h00") - wire obuf_addr_in : UInt<64> - obuf_addr_in <= UInt<1>("h00") - wire obuf_data_in : UInt<64> - obuf_data_in <= UInt<1>("h00") - wire obuf_sz_in : UInt<2> - obuf_sz_in <= UInt<1>("h00") - wire obuf_byteen_in : UInt<8> - obuf_byteen_in <= UInt<1>("h00") - wire obuf_merge_in : UInt<1> - obuf_merge_in <= UInt<1>("h00") - wire obuf_cmd_done_in : UInt<1> - obuf_cmd_done_in <= UInt<1>("h00") - wire obuf_data_done_in : UInt<1> - obuf_data_done_in <= UInt<1>("h00") - wire obuf_tag0_in : UInt<3> - obuf_tag0_in <= UInt<1>("h00") - wire obuf_tag1_in : UInt<3> - obuf_tag1_in <= UInt<1>("h00") - wire obuf_rdrsp_tag_in : UInt<3> - obuf_rdrsp_tag_in <= UInt<1>("h00") - wire obuf_merge_en : UInt<1> - obuf_merge_en <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[el2_lsu_bus_buffer.scala 268:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 268:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:82] + node _T_868 = and(_T_865, _T_867) @[el2_lsu_bus_buffer.scala 268:80] + node _T_869 = or(_T_868, ibuf_byp) @[el2_lsu_bus_buffer.scala 269:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 269:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 269:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 269:55] + node _T_873 = or(_T_871, _T_872) @[el2_lsu_bus_buffer.scala 269:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 269:67] + node _T_875 = and(ibuf_valid, _T_874) @[el2_lsu_bus_buffer.scala 268:32] + ibuf_drain_vld <= _T_875 @[el2_lsu_bus_buffer.scala 268:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 274:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 274:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[el2_lsu_bus_buffer.scala 274:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 277:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 278:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 278:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 278:95] + node _T_881 = or(_T_879, _T_880) @[el2_lsu_bus_buffer.scala 278:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[el2_lsu_bus_buffer.scala 279:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[el2_lsu_bus_buffer.scala 278:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 283:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 283:45] + node _T_888 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 283:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 283:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[el2_lsu_bus_buffer.scala 284:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[el2_lsu_bus_buffer.scala 282:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 283:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 283:45] + node _T_897 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 283:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[el2_lsu_bus_buffer.scala 283:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[el2_lsu_bus_buffer.scala 284:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[el2_lsu_bus_buffer.scala 282:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 283:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 283:45] + node _T_906 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 283:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 283:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[el2_lsu_bus_buffer.scala 284:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[el2_lsu_bus_buffer.scala 282:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 283:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 283:45] + node _T_915 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 283:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[el2_lsu_bus_buffer.scala 283:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[el2_lsu_bus_buffer.scala 284:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[el2_lsu_bus_buffer.scala 282:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 285:59] + node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 285:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 285:93] + node _T_926 = tail(_T_925, 1) @[el2_lsu_bus_buffer.scala 285:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[el2_lsu_bus_buffer.scala 285:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[el2_lsu_bus_buffer.scala 285:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 287:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 287:54] + node _T_930 = and(_T_929, ibuf_valid) @[el2_lsu_bus_buffer.scala 287:75] + node _T_931 = and(_T_930, ibuf_write) @[el2_lsu_bus_buffer.scala 287:88] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 287:117] + node _T_933 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 287:137] + node _T_934 = eq(_T_932, _T_933) @[el2_lsu_bus_buffer.scala 287:124] + node _T_935 = and(_T_931, _T_934) @[el2_lsu_bus_buffer.scala 287:101] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:147] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_bus_buffer.scala 287:145] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:170] + node _T_939 = and(_T_937, _T_938) @[el2_lsu_bus_buffer.scala 287:168] + ibuf_merge_en <= _T_939 @[el2_lsu_bus_buffer.scala 287:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:20] + ibuf_merge_in <= _T_940 @[el2_lsu_bus_buffer.scala 288:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[el2_lsu_bus_buffer.scala 289:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 289:114] + node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 289:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[el2_lsu_bus_buffer.scala 289:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[el2_lsu_bus_buffer.scala 289:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 289:114] + node _T_952 = or(_T_950, _T_951) @[el2_lsu_bus_buffer.scala 289:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 289:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[el2_lsu_bus_buffer.scala 289:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 289:114] + node _T_959 = or(_T_957, _T_958) @[el2_lsu_bus_buffer.scala 289:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[el2_lsu_bus_buffer.scala 289:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[el2_lsu_bus_buffer.scala 289:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 289:114] + node _T_966 = or(_T_964, _T_965) @[el2_lsu_bus_buffer.scala 289:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[el2_lsu_bus_buffer.scala 289:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[el2_lsu_bus_buffer.scala 290:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 290:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 290:118] + node _T_975 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[el2_lsu_bus_buffer.scala 290:81] + node _T_977 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[el2_lsu_bus_buffer.scala 290:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[el2_lsu_bus_buffer.scala 290:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 290:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 290:118] + node _T_983 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 290:81] + node _T_985 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[el2_lsu_bus_buffer.scala 290:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[el2_lsu_bus_buffer.scala 290:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 290:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 290:118] + node _T_991 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[el2_lsu_bus_buffer.scala 290:81] + node _T_993 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[el2_lsu_bus_buffer.scala 290:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[el2_lsu_bus_buffer.scala 290:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 290:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 290:118] + node _T_999 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 290:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[el2_lsu_bus_buffer.scala 290:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 292:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 292:93] + node _T_1007 = and(_T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 292:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 292:54] + _T_1008 <= _T_1007 @[el2_lsu_bus_buffer.scala 292:54] + ibuf_valid <= _T_1008 @[el2_lsu_bus_buffer.scala 292:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[el2_lsu_bus_buffer.scala 293:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[el2_lsu_bus_buffer.scala 298:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[el2_lsu_bus_buffer.scala 300:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1012 <= ibuf_addr_in @[el2_lib.scala 514:16] + ibuf_addr <= _T_1012 @[el2_lsu_bus_buffer.scala 302:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[el2_lsu_bus_buffer.scala 303:15] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1014 <= ibuf_data_in @[el2_lib.scala 514:16] + ibuf_data <= _T_1014 @[el2_lsu_bus_buffer.scala 304:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 305:55] + _T_1015 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 305:55] + ibuf_timer <= _T_1015 @[el2_lsu_bus_buffer.scala 305:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") wire obuf_wr_timer : UInt<3> obuf_wr_timer <= UInt<1>("h00") - wire obuf_wr_timer_in : UInt<3> - obuf_wr_timer_in <= UInt<1>("h00") - wire obuf_byteen0_in : UInt<8> - obuf_byteen0_in <= UInt<1>("h00") - wire obuf_byteen1_in : UInt<8> - obuf_byteen1_in <= UInt<1>("h00") - wire obuf_data0_in : UInt<64> - obuf_data0_in <= UInt<1>("h00") - wire obuf_data1_in : UInt<64> - obuf_data1_in <= UInt<1>("h00") - wire lsu_axi_awvalid_q : UInt<1> - lsu_axi_awvalid_q <= UInt<1>("h00") - wire lsu_axi_awready_q : UInt<1> - lsu_axi_awready_q <= UInt<1>("h00") - wire lsu_axi_wvalid_q : UInt<1> - lsu_axi_wvalid_q <= UInt<1>("h00") - wire lsu_axi_wready_q : UInt<1> - lsu_axi_wready_q <= UInt<1>("h00") - wire lsu_axi_arvalid_q : UInt<1> - lsu_axi_arvalid_q <= UInt<1>("h00") - wire lsu_axi_arready_q : UInt<1> - lsu_axi_arready_q <= UInt<1>("h00") - wire lsu_axi_bvalid_q : UInt<1> - lsu_axi_bvalid_q <= UInt<1>("h00") - wire lsu_axi_bready_q : UInt<1> - lsu_axi_bready_q <= UInt<1>("h00") - wire lsu_axi_rvalid_q : UInt<1> - lsu_axi_rvalid_q <= UInt<1>("h00") - wire lsu_axi_rready_q : UInt<1> - lsu_axi_rready_q <= UInt<1>("h00") - wire lsu_axi_bid_q : UInt<3> - lsu_axi_bid_q <= UInt<1>("h00") - wire lsu_axi_rid_q : UInt<3> - lsu_axi_rid_q <= UInt<1>("h00") - wire lsu_axi_bresp_q : UInt<2> - lsu_axi_bresp_q <= UInt<1>("h00") - wire lsu_axi_rresp_q : UInt<2> - lsu_axi_rresp_q <= UInt<1>("h00") - wire lsu_imprecise_error_store_tag : UInt<2> - lsu_imprecise_error_store_tag <= UInt<1>("h00") - wire lsu_axi_rdata_q : UInt<64> - lsu_axi_rdata_q <= UInt<1>("h00") - CmdPtr0Dec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - node _T = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 400:51] - ldst_byteen_hi_m <= _T @[el2_lsu_bus_buffer.scala 400:28] - node _T_1 = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 401:51] - ldst_byteen_lo_m <= _T_1 @[el2_lsu_bus_buffer.scala 401:28] - node _T_2 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 403:45] - node _T_3 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 403:65] - node _T_4 = eq(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 403:52] - node _T_5 = and(_T_4, ibuf_write) @[el2_lsu_bus_buffer.scala 403:73] - node _T_6 = and(_T_5, ibuf_valid) @[el2_lsu_bus_buffer.scala 403:86] - node _T_7 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 403:99] - ld_addr_ibuf_hit_lo <= _T_7 @[el2_lsu_bus_buffer.scala 403:28] - node _T_8 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 404:45] - node _T_9 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 404:65] - node _T_10 = eq(_T_8, _T_9) @[el2_lsu_bus_buffer.scala 404:52] - node _T_11 = and(_T_10, ibuf_write) @[el2_lsu_bus_buffer.scala 404:73] - node _T_12 = and(_T_11, ibuf_valid) @[el2_lsu_bus_buffer.scala 404:86] - node _T_13 = and(_T_12, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 404:99] - ld_addr_ibuf_hit_hi <= _T_13 @[el2_lsu_bus_buffer.scala 404:28] - node _T_14 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 406:85] - node _T_15 = and(ld_addr_ibuf_hit_lo, _T_14) @[el2_lsu_bus_buffer.scala 406:72] - node _T_16 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 406:107] - node _T_17 = and(_T_15, _T_16) @[el2_lsu_bus_buffer.scala 406:89] - node _T_18 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 406:85] - node _T_19 = and(ld_addr_ibuf_hit_lo, _T_18) @[el2_lsu_bus_buffer.scala 406:72] - node _T_20 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 406:107] - node _T_21 = and(_T_19, _T_20) @[el2_lsu_bus_buffer.scala 406:89] - node _T_22 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 406:85] - node _T_23 = and(ld_addr_ibuf_hit_lo, _T_22) @[el2_lsu_bus_buffer.scala 406:72] - node _T_24 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 406:107] - node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 406:89] - node _T_26 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 406:85] - node _T_27 = and(ld_addr_ibuf_hit_lo, _T_26) @[el2_lsu_bus_buffer.scala 406:72] - node _T_28 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 406:107] - node _T_29 = and(_T_27, _T_28) @[el2_lsu_bus_buffer.scala 406:89] - node _T_30 = cat(_T_29, _T_25) @[Cat.scala 29:58] - node _T_31 = cat(_T_30, _T_21) @[Cat.scala 29:58] - node _T_32 = cat(_T_31, _T_17) @[Cat.scala 29:58] - ld_byte_ibuf_hit_lo <= _T_32 @[el2_lsu_bus_buffer.scala 406:28] - node _T_33 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 407:85] - node _T_34 = and(ld_addr_ibuf_hit_hi, _T_33) @[el2_lsu_bus_buffer.scala 407:72] - node _T_35 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 407:107] - node _T_36 = and(_T_34, _T_35) @[el2_lsu_bus_buffer.scala 407:89] - node _T_37 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 407:85] - node _T_38 = and(ld_addr_ibuf_hit_hi, _T_37) @[el2_lsu_bus_buffer.scala 407:72] - node _T_39 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 407:107] - node _T_40 = and(_T_38, _T_39) @[el2_lsu_bus_buffer.scala 407:89] - node _T_41 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 407:85] - node _T_42 = and(ld_addr_ibuf_hit_hi, _T_41) @[el2_lsu_bus_buffer.scala 407:72] - node _T_43 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 407:107] - node _T_44 = and(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 407:89] - node _T_45 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 407:85] - node _T_46 = and(ld_addr_ibuf_hit_hi, _T_45) @[el2_lsu_bus_buffer.scala 407:72] - node _T_47 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 407:107] - node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 407:89] - node _T_49 = cat(_T_48, _T_44) @[Cat.scala 29:58] - node _T_50 = cat(_T_49, _T_40) @[Cat.scala 29:58] - node _T_51 = cat(_T_50, _T_36) @[Cat.scala 29:58] - ld_byte_ibuf_hit_hi <= _T_51 @[el2_lsu_bus_buffer.scala 407:28] - node _T_52 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_53 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_54 = eq(_T_52, _T_53) @[el2_lsu_bus_buffer.scala 409:77] - node _T_55 = and(_T_54, buf_write[0]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_56 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_57 = and(_T_55, _T_56) @[el2_lsu_bus_buffer.scala 409:115] - node _T_58 = and(_T_57, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_59 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_60 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_61 = eq(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 409:77] - node _T_62 = and(_T_61, buf_write[1]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_63 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_64 = and(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 409:115] - node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_66 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_67 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_68 = eq(_T_66, _T_67) @[el2_lsu_bus_buffer.scala 409:77] - node _T_69 = and(_T_68, buf_write[2]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_70 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_71 = and(_T_69, _T_70) @[el2_lsu_bus_buffer.scala 409:115] - node _T_72 = and(_T_71, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_73 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_74 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_75 = eq(_T_73, _T_74) @[el2_lsu_bus_buffer.scala 409:77] - node _T_76 = and(_T_75, buf_write[3]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_77 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_78 = and(_T_76, _T_77) @[el2_lsu_bus_buffer.scala 409:115] - node _T_79 = and(_T_78, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_80 = cat(_T_79, _T_72) @[Cat.scala 29:58] - node _T_81 = cat(_T_80, _T_65) @[Cat.scala 29:58] - node _T_82 = cat(_T_81, _T_58) @[Cat.scala 29:58] - ld_addr_hitvec_lo <= _T_82 @[el2_lsu_bus_buffer.scala 409:28] - node _T_83 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_84 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_85 = eq(_T_83, _T_84) @[el2_lsu_bus_buffer.scala 410:77] - node _T_86 = and(_T_85, buf_write[0]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_87 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_88 = and(_T_86, _T_87) @[el2_lsu_bus_buffer.scala 410:115] - node _T_89 = and(_T_88, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_90 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_91 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_92 = eq(_T_90, _T_91) @[el2_lsu_bus_buffer.scala 410:77] - node _T_93 = and(_T_92, buf_write[1]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_94 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_95 = and(_T_93, _T_94) @[el2_lsu_bus_buffer.scala 410:115] - node _T_96 = and(_T_95, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_97 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_98 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_99 = eq(_T_97, _T_98) @[el2_lsu_bus_buffer.scala 410:77] - node _T_100 = and(_T_99, buf_write[2]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_101 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_102 = and(_T_100, _T_101) @[el2_lsu_bus_buffer.scala 410:115] - node _T_103 = and(_T_102, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_104 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_105 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_106 = eq(_T_104, _T_105) @[el2_lsu_bus_buffer.scala 410:77] - node _T_107 = and(_T_106, buf_write[3]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_108 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_109 = and(_T_107, _T_108) @[el2_lsu_bus_buffer.scala 410:115] - node _T_110 = and(_T_109, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_111 = cat(_T_110, _T_103) @[Cat.scala 29:58] - node _T_112 = cat(_T_111, _T_96) @[Cat.scala 29:58] - node _T_113 = cat(_T_112, _T_89) @[Cat.scala 29:58] - ld_addr_hitvec_hi <= _T_113 @[el2_lsu_bus_buffer.scala 410:28] - node _T_114 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 412:71] - node _T_115 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_116 = or(_T_114, _T_115) @[el2_lsu_bus_buffer.scala 412:75] - node _T_117 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 412:71] - node _T_118 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_119 = or(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 412:75] - node _T_120 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 412:71] - node _T_121 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_122 = or(_T_120, _T_121) @[el2_lsu_bus_buffer.scala 412:75] - node _T_123 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 412:71] - node _T_124 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_125 = or(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 412:75] - node _T_126 = cat(_T_125, _T_122) @[Cat.scala 29:58] - node _T_127 = cat(_T_126, _T_119) @[Cat.scala 29:58] - node _T_128 = cat(_T_127, _T_116) @[Cat.scala 29:58] - io.ld_byte_hit_buf_lo <= _T_128 @[el2_lsu_bus_buffer.scala 412:28] - node _T_129 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 413:71] - node _T_130 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_131 = or(_T_129, _T_130) @[el2_lsu_bus_buffer.scala 413:75] - node _T_132 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 413:71] - node _T_133 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_134 = or(_T_132, _T_133) @[el2_lsu_bus_buffer.scala 413:75] - node _T_135 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 413:71] - node _T_136 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_137 = or(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 413:75] - node _T_138 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 413:71] - node _T_139 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_140 = or(_T_138, _T_139) @[el2_lsu_bus_buffer.scala 413:75] - node _T_141 = cat(_T_140, _T_137) @[Cat.scala 29:58] - node _T_142 = cat(_T_141, _T_134) @[Cat.scala 29:58] - node _T_143 = cat(_T_142, _T_131) @[Cat.scala 29:58] - io.ld_byte_hit_buf_hi <= _T_143 @[el2_lsu_bus_buffer.scala 413:28] - node _T_144 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_145 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_146 = and(_T_144, _T_145) @[el2_lsu_bus_buffer.scala 415:97] - node _T_147 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_148 = and(_T_146, _T_147) @[el2_lsu_bus_buffer.scala 415:116] - node _T_149 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_150 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 415:97] - node _T_152 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_153 = and(_T_151, _T_152) @[el2_lsu_bus_buffer.scala 415:116] - node _T_154 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_155 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_156 = and(_T_154, _T_155) @[el2_lsu_bus_buffer.scala 415:97] - node _T_157 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_158 = and(_T_156, _T_157) @[el2_lsu_bus_buffer.scala 415:116] - node _T_159 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_160 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 415:97] - node _T_162 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_163 = and(_T_161, _T_162) @[el2_lsu_bus_buffer.scala 415:116] - node _T_164 = cat(_T_163, _T_158) @[Cat.scala 29:58] - node _T_165 = cat(_T_164, _T_153) @[Cat.scala 29:58] - node _T_166 = cat(_T_165, _T_148) @[Cat.scala 29:58] - node _T_167 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_168 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 415:97] - node _T_170 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_171 = and(_T_169, _T_170) @[el2_lsu_bus_buffer.scala 415:116] - node _T_172 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_173 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_174 = and(_T_172, _T_173) @[el2_lsu_bus_buffer.scala 415:97] - node _T_175 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_176 = and(_T_174, _T_175) @[el2_lsu_bus_buffer.scala 415:116] - node _T_177 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_178 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 415:97] - node _T_180 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_181 = and(_T_179, _T_180) @[el2_lsu_bus_buffer.scala 415:116] - node _T_182 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_183 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_184 = and(_T_182, _T_183) @[el2_lsu_bus_buffer.scala 415:97] - node _T_185 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_186 = and(_T_184, _T_185) @[el2_lsu_bus_buffer.scala 415:116] - node _T_187 = cat(_T_186, _T_181) @[Cat.scala 29:58] - node _T_188 = cat(_T_187, _T_176) @[Cat.scala 29:58] - node _T_189 = cat(_T_188, _T_171) @[Cat.scala 29:58] - node _T_190 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_191 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_192 = and(_T_190, _T_191) @[el2_lsu_bus_buffer.scala 415:97] - node _T_193 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_194 = and(_T_192, _T_193) @[el2_lsu_bus_buffer.scala 415:116] - node _T_195 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_196 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 415:97] - node _T_198 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_199 = and(_T_197, _T_198) @[el2_lsu_bus_buffer.scala 415:116] - node _T_200 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_201 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_202 = and(_T_200, _T_201) @[el2_lsu_bus_buffer.scala 415:97] - node _T_203 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_204 = and(_T_202, _T_203) @[el2_lsu_bus_buffer.scala 415:116] - node _T_205 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_207 = and(_T_205, _T_206) @[el2_lsu_bus_buffer.scala 415:97] - node _T_208 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 415:116] - node _T_210 = cat(_T_209, _T_204) @[Cat.scala 29:58] - node _T_211 = cat(_T_210, _T_199) @[Cat.scala 29:58] - node _T_212 = cat(_T_211, _T_194) @[Cat.scala 29:58] - node _T_213 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_214 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 415:97] - node _T_216 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_217 = and(_T_215, _T_216) @[el2_lsu_bus_buffer.scala 415:116] - node _T_218 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_219 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_220 = and(_T_218, _T_219) @[el2_lsu_bus_buffer.scala 415:97] - node _T_221 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_222 = and(_T_220, _T_221) @[el2_lsu_bus_buffer.scala 415:116] - node _T_223 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_224 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_225 = and(_T_223, _T_224) @[el2_lsu_bus_buffer.scala 415:97] - node _T_226 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 415:116] - node _T_228 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_229 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_230 = and(_T_228, _T_229) @[el2_lsu_bus_buffer.scala 415:97] - node _T_231 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_232 = and(_T_230, _T_231) @[el2_lsu_bus_buffer.scala 415:116] - node _T_233 = cat(_T_232, _T_227) @[Cat.scala 29:58] - node _T_234 = cat(_T_233, _T_222) @[Cat.scala 29:58] - node _T_235 = cat(_T_234, _T_217) @[Cat.scala 29:58] - ld_byte_hitvec_lo[0] <= _T_166 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[1] <= _T_189 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[2] <= _T_212 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[3] <= _T_235 @[el2_lsu_bus_buffer.scala 415:28] - node _T_236 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_237 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_238 = and(_T_236, _T_237) @[el2_lsu_bus_buffer.scala 416:97] - node _T_239 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_240 = and(_T_238, _T_239) @[el2_lsu_bus_buffer.scala 416:116] - node _T_241 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_242 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_243 = and(_T_241, _T_242) @[el2_lsu_bus_buffer.scala 416:97] - node _T_244 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_245 = and(_T_243, _T_244) @[el2_lsu_bus_buffer.scala 416:116] - node _T_246 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_247 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_248 = and(_T_246, _T_247) @[el2_lsu_bus_buffer.scala 416:97] - node _T_249 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_250 = and(_T_248, _T_249) @[el2_lsu_bus_buffer.scala 416:116] - node _T_251 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_252 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_253 = and(_T_251, _T_252) @[el2_lsu_bus_buffer.scala 416:97] - node _T_254 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_255 = and(_T_253, _T_254) @[el2_lsu_bus_buffer.scala 416:116] - node _T_256 = cat(_T_255, _T_250) @[Cat.scala 29:58] - node _T_257 = cat(_T_256, _T_245) @[Cat.scala 29:58] - node _T_258 = cat(_T_257, _T_240) @[Cat.scala 29:58] - node _T_259 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_260 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_261 = and(_T_259, _T_260) @[el2_lsu_bus_buffer.scala 416:97] - node _T_262 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_263 = and(_T_261, _T_262) @[el2_lsu_bus_buffer.scala 416:116] - node _T_264 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_265 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_266 = and(_T_264, _T_265) @[el2_lsu_bus_buffer.scala 416:97] - node _T_267 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_268 = and(_T_266, _T_267) @[el2_lsu_bus_buffer.scala 416:116] - node _T_269 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_270 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_271 = and(_T_269, _T_270) @[el2_lsu_bus_buffer.scala 416:97] - node _T_272 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_273 = and(_T_271, _T_272) @[el2_lsu_bus_buffer.scala 416:116] - node _T_274 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_275 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_276 = and(_T_274, _T_275) @[el2_lsu_bus_buffer.scala 416:97] - node _T_277 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_278 = and(_T_276, _T_277) @[el2_lsu_bus_buffer.scala 416:116] - node _T_279 = cat(_T_278, _T_273) @[Cat.scala 29:58] - node _T_280 = cat(_T_279, _T_268) @[Cat.scala 29:58] - node _T_281 = cat(_T_280, _T_263) @[Cat.scala 29:58] - node _T_282 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_283 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_284 = and(_T_282, _T_283) @[el2_lsu_bus_buffer.scala 416:97] - node _T_285 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_286 = and(_T_284, _T_285) @[el2_lsu_bus_buffer.scala 416:116] - node _T_287 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_288 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_289 = and(_T_287, _T_288) @[el2_lsu_bus_buffer.scala 416:97] - node _T_290 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_291 = and(_T_289, _T_290) @[el2_lsu_bus_buffer.scala 416:116] - node _T_292 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_293 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_294 = and(_T_292, _T_293) @[el2_lsu_bus_buffer.scala 416:97] - node _T_295 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_296 = and(_T_294, _T_295) @[el2_lsu_bus_buffer.scala 416:116] - node _T_297 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_298 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_299 = and(_T_297, _T_298) @[el2_lsu_bus_buffer.scala 416:97] - node _T_300 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_301 = and(_T_299, _T_300) @[el2_lsu_bus_buffer.scala 416:116] - node _T_302 = cat(_T_301, _T_296) @[Cat.scala 29:58] - node _T_303 = cat(_T_302, _T_291) @[Cat.scala 29:58] - node _T_304 = cat(_T_303, _T_286) @[Cat.scala 29:58] - node _T_305 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_306 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_307 = and(_T_305, _T_306) @[el2_lsu_bus_buffer.scala 416:97] - node _T_308 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_309 = and(_T_307, _T_308) @[el2_lsu_bus_buffer.scala 416:116] - node _T_310 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_311 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_312 = and(_T_310, _T_311) @[el2_lsu_bus_buffer.scala 416:97] - node _T_313 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_314 = and(_T_312, _T_313) @[el2_lsu_bus_buffer.scala 416:116] - node _T_315 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_316 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_317 = and(_T_315, _T_316) @[el2_lsu_bus_buffer.scala 416:97] - node _T_318 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_319 = and(_T_317, _T_318) @[el2_lsu_bus_buffer.scala 416:116] - node _T_320 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_321 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_322 = and(_T_320, _T_321) @[el2_lsu_bus_buffer.scala 416:97] - node _T_323 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_324 = and(_T_322, _T_323) @[el2_lsu_bus_buffer.scala 416:116] - node _T_325 = cat(_T_324, _T_319) @[Cat.scala 29:58] - node _T_326 = cat(_T_325, _T_314) @[Cat.scala 29:58] - node _T_327 = cat(_T_326, _T_309) @[Cat.scala 29:58] - ld_byte_hitvec_hi[0] <= _T_258 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[1] <= _T_281 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[2] <= _T_304 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[3] <= _T_327 @[el2_lsu_bus_buffer.scala 416:28] - node _T_328 = bits(ld_byte_hitvec_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_329 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_330 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_331 = cat(_T_330, _T_329) @[el2_lsu_bus_buffer.scala 418:147] - node _T_332 = and(ld_byte_hitvec_lo[0], _T_331) @[el2_lsu_bus_buffer.scala 418:126] - node _T_333 = orr(_T_332) @[el2_lsu_bus_buffer.scala 418:155] - node _T_334 = not(_T_333) @[el2_lsu_bus_buffer.scala 418:102] - node _T_335 = and(_T_328, _T_334) @[el2_lsu_bus_buffer.scala 418:100] - node _T_336 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_337 = not(_T_336) @[el2_lsu_bus_buffer.scala 418:162] - node _T_338 = and(_T_335, _T_337) @[el2_lsu_bus_buffer.scala 418:160] - node _T_339 = bits(ld_byte_hitvec_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_340 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_341 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_342 = cat(_T_341, _T_340) @[el2_lsu_bus_buffer.scala 418:147] - node _T_343 = and(ld_byte_hitvec_lo[0], _T_342) @[el2_lsu_bus_buffer.scala 418:126] - node _T_344 = orr(_T_343) @[el2_lsu_bus_buffer.scala 418:155] - node _T_345 = not(_T_344) @[el2_lsu_bus_buffer.scala 418:102] - node _T_346 = and(_T_339, _T_345) @[el2_lsu_bus_buffer.scala 418:100] - node _T_347 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_348 = not(_T_347) @[el2_lsu_bus_buffer.scala 418:162] - node _T_349 = and(_T_346, _T_348) @[el2_lsu_bus_buffer.scala 418:160] - node _T_350 = bits(ld_byte_hitvec_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_351 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_352 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_353 = cat(_T_352, _T_351) @[el2_lsu_bus_buffer.scala 418:147] - node _T_354 = and(ld_byte_hitvec_lo[0], _T_353) @[el2_lsu_bus_buffer.scala 418:126] - node _T_355 = orr(_T_354) @[el2_lsu_bus_buffer.scala 418:155] - node _T_356 = not(_T_355) @[el2_lsu_bus_buffer.scala 418:102] - node _T_357 = and(_T_350, _T_356) @[el2_lsu_bus_buffer.scala 418:100] - node _T_358 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_359 = not(_T_358) @[el2_lsu_bus_buffer.scala 418:162] - node _T_360 = and(_T_357, _T_359) @[el2_lsu_bus_buffer.scala 418:160] - node _T_361 = bits(ld_byte_hitvec_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_362 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_363 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_364 = cat(_T_363, _T_362) @[el2_lsu_bus_buffer.scala 418:147] - node _T_365 = and(ld_byte_hitvec_lo[0], _T_364) @[el2_lsu_bus_buffer.scala 418:126] - node _T_366 = orr(_T_365) @[el2_lsu_bus_buffer.scala 418:155] - node _T_367 = not(_T_366) @[el2_lsu_bus_buffer.scala 418:102] - node _T_368 = and(_T_361, _T_367) @[el2_lsu_bus_buffer.scala 418:100] - node _T_369 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_370 = not(_T_369) @[el2_lsu_bus_buffer.scala 418:162] - node _T_371 = and(_T_368, _T_370) @[el2_lsu_bus_buffer.scala 418:160] - node _T_372 = cat(_T_371, _T_360) @[Cat.scala 29:58] - node _T_373 = cat(_T_372, _T_349) @[Cat.scala 29:58] - node _T_374 = cat(_T_373, _T_338) @[Cat.scala 29:58] - node _T_375 = bits(ld_byte_hitvec_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_376 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_377 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_378 = cat(_T_377, _T_376) @[el2_lsu_bus_buffer.scala 418:147] - node _T_379 = and(ld_byte_hitvec_lo[1], _T_378) @[el2_lsu_bus_buffer.scala 418:126] - node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 418:155] - node _T_381 = not(_T_380) @[el2_lsu_bus_buffer.scala 418:102] - node _T_382 = and(_T_375, _T_381) @[el2_lsu_bus_buffer.scala 418:100] - node _T_383 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_384 = not(_T_383) @[el2_lsu_bus_buffer.scala 418:162] - node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 418:160] - node _T_386 = bits(ld_byte_hitvec_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_387 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_388 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_389 = cat(_T_388, _T_387) @[el2_lsu_bus_buffer.scala 418:147] - node _T_390 = and(ld_byte_hitvec_lo[1], _T_389) @[el2_lsu_bus_buffer.scala 418:126] - node _T_391 = orr(_T_390) @[el2_lsu_bus_buffer.scala 418:155] - node _T_392 = not(_T_391) @[el2_lsu_bus_buffer.scala 418:102] - node _T_393 = and(_T_386, _T_392) @[el2_lsu_bus_buffer.scala 418:100] - node _T_394 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_395 = not(_T_394) @[el2_lsu_bus_buffer.scala 418:162] - node _T_396 = and(_T_393, _T_395) @[el2_lsu_bus_buffer.scala 418:160] - node _T_397 = bits(ld_byte_hitvec_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_398 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_399 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_400 = cat(_T_399, _T_398) @[el2_lsu_bus_buffer.scala 418:147] - node _T_401 = and(ld_byte_hitvec_lo[1], _T_400) @[el2_lsu_bus_buffer.scala 418:126] - node _T_402 = orr(_T_401) @[el2_lsu_bus_buffer.scala 418:155] - node _T_403 = not(_T_402) @[el2_lsu_bus_buffer.scala 418:102] - node _T_404 = and(_T_397, _T_403) @[el2_lsu_bus_buffer.scala 418:100] - node _T_405 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_406 = not(_T_405) @[el2_lsu_bus_buffer.scala 418:162] - node _T_407 = and(_T_404, _T_406) @[el2_lsu_bus_buffer.scala 418:160] - node _T_408 = bits(ld_byte_hitvec_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_409 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_410 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_411 = cat(_T_410, _T_409) @[el2_lsu_bus_buffer.scala 418:147] - node _T_412 = and(ld_byte_hitvec_lo[1], _T_411) @[el2_lsu_bus_buffer.scala 418:126] - node _T_413 = orr(_T_412) @[el2_lsu_bus_buffer.scala 418:155] - node _T_414 = not(_T_413) @[el2_lsu_bus_buffer.scala 418:102] - node _T_415 = and(_T_408, _T_414) @[el2_lsu_bus_buffer.scala 418:100] - node _T_416 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_417 = not(_T_416) @[el2_lsu_bus_buffer.scala 418:162] - node _T_418 = and(_T_415, _T_417) @[el2_lsu_bus_buffer.scala 418:160] - node _T_419 = cat(_T_418, _T_407) @[Cat.scala 29:58] - node _T_420 = cat(_T_419, _T_396) @[Cat.scala 29:58] - node _T_421 = cat(_T_420, _T_385) @[Cat.scala 29:58] - node _T_422 = bits(ld_byte_hitvec_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_423 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_424 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_425 = cat(_T_424, _T_423) @[el2_lsu_bus_buffer.scala 418:147] - node _T_426 = and(ld_byte_hitvec_lo[2], _T_425) @[el2_lsu_bus_buffer.scala 418:126] - node _T_427 = orr(_T_426) @[el2_lsu_bus_buffer.scala 418:155] - node _T_428 = not(_T_427) @[el2_lsu_bus_buffer.scala 418:102] - node _T_429 = and(_T_422, _T_428) @[el2_lsu_bus_buffer.scala 418:100] - node _T_430 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_431 = not(_T_430) @[el2_lsu_bus_buffer.scala 418:162] - node _T_432 = and(_T_429, _T_431) @[el2_lsu_bus_buffer.scala 418:160] - node _T_433 = bits(ld_byte_hitvec_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_434 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_435 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_436 = cat(_T_435, _T_434) @[el2_lsu_bus_buffer.scala 418:147] - node _T_437 = and(ld_byte_hitvec_lo[2], _T_436) @[el2_lsu_bus_buffer.scala 418:126] - node _T_438 = orr(_T_437) @[el2_lsu_bus_buffer.scala 418:155] - node _T_439 = not(_T_438) @[el2_lsu_bus_buffer.scala 418:102] - node _T_440 = and(_T_433, _T_439) @[el2_lsu_bus_buffer.scala 418:100] - node _T_441 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_442 = not(_T_441) @[el2_lsu_bus_buffer.scala 418:162] - node _T_443 = and(_T_440, _T_442) @[el2_lsu_bus_buffer.scala 418:160] - node _T_444 = bits(ld_byte_hitvec_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_445 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_446 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_447 = cat(_T_446, _T_445) @[el2_lsu_bus_buffer.scala 418:147] - node _T_448 = and(ld_byte_hitvec_lo[2], _T_447) @[el2_lsu_bus_buffer.scala 418:126] - node _T_449 = orr(_T_448) @[el2_lsu_bus_buffer.scala 418:155] - node _T_450 = not(_T_449) @[el2_lsu_bus_buffer.scala 418:102] - node _T_451 = and(_T_444, _T_450) @[el2_lsu_bus_buffer.scala 418:100] - node _T_452 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_453 = not(_T_452) @[el2_lsu_bus_buffer.scala 418:162] - node _T_454 = and(_T_451, _T_453) @[el2_lsu_bus_buffer.scala 418:160] - node _T_455 = bits(ld_byte_hitvec_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_456 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_457 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_458 = cat(_T_457, _T_456) @[el2_lsu_bus_buffer.scala 418:147] - node _T_459 = and(ld_byte_hitvec_lo[2], _T_458) @[el2_lsu_bus_buffer.scala 418:126] - node _T_460 = orr(_T_459) @[el2_lsu_bus_buffer.scala 418:155] - node _T_461 = not(_T_460) @[el2_lsu_bus_buffer.scala 418:102] - node _T_462 = and(_T_455, _T_461) @[el2_lsu_bus_buffer.scala 418:100] - node _T_463 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_464 = not(_T_463) @[el2_lsu_bus_buffer.scala 418:162] - node _T_465 = and(_T_462, _T_464) @[el2_lsu_bus_buffer.scala 418:160] - node _T_466 = cat(_T_465, _T_454) @[Cat.scala 29:58] - node _T_467 = cat(_T_466, _T_443) @[Cat.scala 29:58] - node _T_468 = cat(_T_467, _T_432) @[Cat.scala 29:58] - node _T_469 = bits(ld_byte_hitvec_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_470 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_471 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_472 = cat(_T_471, _T_470) @[el2_lsu_bus_buffer.scala 418:147] - node _T_473 = and(ld_byte_hitvec_lo[3], _T_472) @[el2_lsu_bus_buffer.scala 418:126] - node _T_474 = orr(_T_473) @[el2_lsu_bus_buffer.scala 418:155] - node _T_475 = not(_T_474) @[el2_lsu_bus_buffer.scala 418:102] - node _T_476 = and(_T_469, _T_475) @[el2_lsu_bus_buffer.scala 418:100] - node _T_477 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_478 = not(_T_477) @[el2_lsu_bus_buffer.scala 418:162] - node _T_479 = and(_T_476, _T_478) @[el2_lsu_bus_buffer.scala 418:160] - node _T_480 = bits(ld_byte_hitvec_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_481 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_482 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_483 = cat(_T_482, _T_481) @[el2_lsu_bus_buffer.scala 418:147] - node _T_484 = and(ld_byte_hitvec_lo[3], _T_483) @[el2_lsu_bus_buffer.scala 418:126] - node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 418:155] - node _T_486 = not(_T_485) @[el2_lsu_bus_buffer.scala 418:102] - node _T_487 = and(_T_480, _T_486) @[el2_lsu_bus_buffer.scala 418:100] - node _T_488 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_489 = not(_T_488) @[el2_lsu_bus_buffer.scala 418:162] - node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 418:160] - node _T_491 = bits(ld_byte_hitvec_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_492 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_493 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_494 = cat(_T_493, _T_492) @[el2_lsu_bus_buffer.scala 418:147] - node _T_495 = and(ld_byte_hitvec_lo[3], _T_494) @[el2_lsu_bus_buffer.scala 418:126] - node _T_496 = orr(_T_495) @[el2_lsu_bus_buffer.scala 418:155] - node _T_497 = not(_T_496) @[el2_lsu_bus_buffer.scala 418:102] - node _T_498 = and(_T_491, _T_497) @[el2_lsu_bus_buffer.scala 418:100] - node _T_499 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_500 = not(_T_499) @[el2_lsu_bus_buffer.scala 418:162] - node _T_501 = and(_T_498, _T_500) @[el2_lsu_bus_buffer.scala 418:160] - node _T_502 = bits(ld_byte_hitvec_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_503 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_504 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_505 = cat(_T_504, _T_503) @[el2_lsu_bus_buffer.scala 418:147] - node _T_506 = and(ld_byte_hitvec_lo[3], _T_505) @[el2_lsu_bus_buffer.scala 418:126] - node _T_507 = orr(_T_506) @[el2_lsu_bus_buffer.scala 418:155] - node _T_508 = not(_T_507) @[el2_lsu_bus_buffer.scala 418:102] - node _T_509 = and(_T_502, _T_508) @[el2_lsu_bus_buffer.scala 418:100] - node _T_510 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_511 = not(_T_510) @[el2_lsu_bus_buffer.scala 418:162] - node _T_512 = and(_T_509, _T_511) @[el2_lsu_bus_buffer.scala 418:160] - node _T_513 = cat(_T_512, _T_501) @[Cat.scala 29:58] - node _T_514 = cat(_T_513, _T_490) @[Cat.scala 29:58] - node _T_515 = cat(_T_514, _T_479) @[Cat.scala 29:58] - ld_byte_hitvecfn_lo[0] <= _T_374 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[1] <= _T_421 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[2] <= _T_468 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[3] <= _T_515 @[el2_lsu_bus_buffer.scala 418:28] - node _T_516 = bits(ld_byte_hitvec_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_517 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_518 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_519 = cat(_T_518, _T_517) @[el2_lsu_bus_buffer.scala 419:147] - node _T_520 = and(ld_byte_hitvec_hi[0], _T_519) @[el2_lsu_bus_buffer.scala 419:126] - node _T_521 = orr(_T_520) @[el2_lsu_bus_buffer.scala 419:155] - node _T_522 = not(_T_521) @[el2_lsu_bus_buffer.scala 419:102] - node _T_523 = and(_T_516, _T_522) @[el2_lsu_bus_buffer.scala 419:100] - node _T_524 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_525 = not(_T_524) @[el2_lsu_bus_buffer.scala 419:162] - node _T_526 = and(_T_523, _T_525) @[el2_lsu_bus_buffer.scala 419:160] - node _T_527 = bits(ld_byte_hitvec_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_528 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_529 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_530 = cat(_T_529, _T_528) @[el2_lsu_bus_buffer.scala 419:147] - node _T_531 = and(ld_byte_hitvec_hi[0], _T_530) @[el2_lsu_bus_buffer.scala 419:126] - node _T_532 = orr(_T_531) @[el2_lsu_bus_buffer.scala 419:155] - node _T_533 = not(_T_532) @[el2_lsu_bus_buffer.scala 419:102] - node _T_534 = and(_T_527, _T_533) @[el2_lsu_bus_buffer.scala 419:100] - node _T_535 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_536 = not(_T_535) @[el2_lsu_bus_buffer.scala 419:162] - node _T_537 = and(_T_534, _T_536) @[el2_lsu_bus_buffer.scala 419:160] - node _T_538 = bits(ld_byte_hitvec_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_539 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_540 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_541 = cat(_T_540, _T_539) @[el2_lsu_bus_buffer.scala 419:147] - node _T_542 = and(ld_byte_hitvec_hi[0], _T_541) @[el2_lsu_bus_buffer.scala 419:126] - node _T_543 = orr(_T_542) @[el2_lsu_bus_buffer.scala 419:155] - node _T_544 = not(_T_543) @[el2_lsu_bus_buffer.scala 419:102] - node _T_545 = and(_T_538, _T_544) @[el2_lsu_bus_buffer.scala 419:100] - node _T_546 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_547 = not(_T_546) @[el2_lsu_bus_buffer.scala 419:162] - node _T_548 = and(_T_545, _T_547) @[el2_lsu_bus_buffer.scala 419:160] - node _T_549 = bits(ld_byte_hitvec_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_550 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_551 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_552 = cat(_T_551, _T_550) @[el2_lsu_bus_buffer.scala 419:147] - node _T_553 = and(ld_byte_hitvec_hi[0], _T_552) @[el2_lsu_bus_buffer.scala 419:126] - node _T_554 = orr(_T_553) @[el2_lsu_bus_buffer.scala 419:155] - node _T_555 = not(_T_554) @[el2_lsu_bus_buffer.scala 419:102] - node _T_556 = and(_T_549, _T_555) @[el2_lsu_bus_buffer.scala 419:100] - node _T_557 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_558 = not(_T_557) @[el2_lsu_bus_buffer.scala 419:162] - node _T_559 = and(_T_556, _T_558) @[el2_lsu_bus_buffer.scala 419:160] - node _T_560 = cat(_T_559, _T_548) @[Cat.scala 29:58] - node _T_561 = cat(_T_560, _T_537) @[Cat.scala 29:58] - node _T_562 = cat(_T_561, _T_526) @[Cat.scala 29:58] - node _T_563 = bits(ld_byte_hitvec_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_564 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_565 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_566 = cat(_T_565, _T_564) @[el2_lsu_bus_buffer.scala 419:147] - node _T_567 = and(ld_byte_hitvec_hi[1], _T_566) @[el2_lsu_bus_buffer.scala 419:126] - node _T_568 = orr(_T_567) @[el2_lsu_bus_buffer.scala 419:155] - node _T_569 = not(_T_568) @[el2_lsu_bus_buffer.scala 419:102] - node _T_570 = and(_T_563, _T_569) @[el2_lsu_bus_buffer.scala 419:100] - node _T_571 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_572 = not(_T_571) @[el2_lsu_bus_buffer.scala 419:162] - node _T_573 = and(_T_570, _T_572) @[el2_lsu_bus_buffer.scala 419:160] - node _T_574 = bits(ld_byte_hitvec_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_575 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_576 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_577 = cat(_T_576, _T_575) @[el2_lsu_bus_buffer.scala 419:147] - node _T_578 = and(ld_byte_hitvec_hi[1], _T_577) @[el2_lsu_bus_buffer.scala 419:126] - node _T_579 = orr(_T_578) @[el2_lsu_bus_buffer.scala 419:155] - node _T_580 = not(_T_579) @[el2_lsu_bus_buffer.scala 419:102] - node _T_581 = and(_T_574, _T_580) @[el2_lsu_bus_buffer.scala 419:100] - node _T_582 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_583 = not(_T_582) @[el2_lsu_bus_buffer.scala 419:162] - node _T_584 = and(_T_581, _T_583) @[el2_lsu_bus_buffer.scala 419:160] - node _T_585 = bits(ld_byte_hitvec_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_586 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_587 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_588 = cat(_T_587, _T_586) @[el2_lsu_bus_buffer.scala 419:147] - node _T_589 = and(ld_byte_hitvec_hi[1], _T_588) @[el2_lsu_bus_buffer.scala 419:126] - node _T_590 = orr(_T_589) @[el2_lsu_bus_buffer.scala 419:155] - node _T_591 = not(_T_590) @[el2_lsu_bus_buffer.scala 419:102] - node _T_592 = and(_T_585, _T_591) @[el2_lsu_bus_buffer.scala 419:100] - node _T_593 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_594 = not(_T_593) @[el2_lsu_bus_buffer.scala 419:162] - node _T_595 = and(_T_592, _T_594) @[el2_lsu_bus_buffer.scala 419:160] - node _T_596 = bits(ld_byte_hitvec_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_597 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_598 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_599 = cat(_T_598, _T_597) @[el2_lsu_bus_buffer.scala 419:147] - node _T_600 = and(ld_byte_hitvec_hi[1], _T_599) @[el2_lsu_bus_buffer.scala 419:126] - node _T_601 = orr(_T_600) @[el2_lsu_bus_buffer.scala 419:155] - node _T_602 = not(_T_601) @[el2_lsu_bus_buffer.scala 419:102] - node _T_603 = and(_T_596, _T_602) @[el2_lsu_bus_buffer.scala 419:100] - node _T_604 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_605 = not(_T_604) @[el2_lsu_bus_buffer.scala 419:162] - node _T_606 = and(_T_603, _T_605) @[el2_lsu_bus_buffer.scala 419:160] - node _T_607 = cat(_T_606, _T_595) @[Cat.scala 29:58] - node _T_608 = cat(_T_607, _T_584) @[Cat.scala 29:58] - node _T_609 = cat(_T_608, _T_573) @[Cat.scala 29:58] - node _T_610 = bits(ld_byte_hitvec_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_611 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_612 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_613 = cat(_T_612, _T_611) @[el2_lsu_bus_buffer.scala 419:147] - node _T_614 = and(ld_byte_hitvec_hi[2], _T_613) @[el2_lsu_bus_buffer.scala 419:126] - node _T_615 = orr(_T_614) @[el2_lsu_bus_buffer.scala 419:155] - node _T_616 = not(_T_615) @[el2_lsu_bus_buffer.scala 419:102] - node _T_617 = and(_T_610, _T_616) @[el2_lsu_bus_buffer.scala 419:100] - node _T_618 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_619 = not(_T_618) @[el2_lsu_bus_buffer.scala 419:162] - node _T_620 = and(_T_617, _T_619) @[el2_lsu_bus_buffer.scala 419:160] - node _T_621 = bits(ld_byte_hitvec_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_622 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_623 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_624 = cat(_T_623, _T_622) @[el2_lsu_bus_buffer.scala 419:147] - node _T_625 = and(ld_byte_hitvec_hi[2], _T_624) @[el2_lsu_bus_buffer.scala 419:126] - node _T_626 = orr(_T_625) @[el2_lsu_bus_buffer.scala 419:155] - node _T_627 = not(_T_626) @[el2_lsu_bus_buffer.scala 419:102] - node _T_628 = and(_T_621, _T_627) @[el2_lsu_bus_buffer.scala 419:100] - node _T_629 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_630 = not(_T_629) @[el2_lsu_bus_buffer.scala 419:162] - node _T_631 = and(_T_628, _T_630) @[el2_lsu_bus_buffer.scala 419:160] - node _T_632 = bits(ld_byte_hitvec_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_633 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_634 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_635 = cat(_T_634, _T_633) @[el2_lsu_bus_buffer.scala 419:147] - node _T_636 = and(ld_byte_hitvec_hi[2], _T_635) @[el2_lsu_bus_buffer.scala 419:126] - node _T_637 = orr(_T_636) @[el2_lsu_bus_buffer.scala 419:155] - node _T_638 = not(_T_637) @[el2_lsu_bus_buffer.scala 419:102] - node _T_639 = and(_T_632, _T_638) @[el2_lsu_bus_buffer.scala 419:100] - node _T_640 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_641 = not(_T_640) @[el2_lsu_bus_buffer.scala 419:162] - node _T_642 = and(_T_639, _T_641) @[el2_lsu_bus_buffer.scala 419:160] - node _T_643 = bits(ld_byte_hitvec_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_644 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_645 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_646 = cat(_T_645, _T_644) @[el2_lsu_bus_buffer.scala 419:147] - node _T_647 = and(ld_byte_hitvec_hi[2], _T_646) @[el2_lsu_bus_buffer.scala 419:126] - node _T_648 = orr(_T_647) @[el2_lsu_bus_buffer.scala 419:155] - node _T_649 = not(_T_648) @[el2_lsu_bus_buffer.scala 419:102] - node _T_650 = and(_T_643, _T_649) @[el2_lsu_bus_buffer.scala 419:100] - node _T_651 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_652 = not(_T_651) @[el2_lsu_bus_buffer.scala 419:162] - node _T_653 = and(_T_650, _T_652) @[el2_lsu_bus_buffer.scala 419:160] - node _T_654 = cat(_T_653, _T_642) @[Cat.scala 29:58] - node _T_655 = cat(_T_654, _T_631) @[Cat.scala 29:58] - node _T_656 = cat(_T_655, _T_620) @[Cat.scala 29:58] - node _T_657 = bits(ld_byte_hitvec_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_658 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_659 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_660 = cat(_T_659, _T_658) @[el2_lsu_bus_buffer.scala 419:147] - node _T_661 = and(ld_byte_hitvec_hi[3], _T_660) @[el2_lsu_bus_buffer.scala 419:126] - node _T_662 = orr(_T_661) @[el2_lsu_bus_buffer.scala 419:155] - node _T_663 = not(_T_662) @[el2_lsu_bus_buffer.scala 419:102] - node _T_664 = and(_T_657, _T_663) @[el2_lsu_bus_buffer.scala 419:100] - node _T_665 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_666 = not(_T_665) @[el2_lsu_bus_buffer.scala 419:162] - node _T_667 = and(_T_664, _T_666) @[el2_lsu_bus_buffer.scala 419:160] - node _T_668 = bits(ld_byte_hitvec_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_669 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_670 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_671 = cat(_T_670, _T_669) @[el2_lsu_bus_buffer.scala 419:147] - node _T_672 = and(ld_byte_hitvec_hi[3], _T_671) @[el2_lsu_bus_buffer.scala 419:126] - node _T_673 = orr(_T_672) @[el2_lsu_bus_buffer.scala 419:155] - node _T_674 = not(_T_673) @[el2_lsu_bus_buffer.scala 419:102] - node _T_675 = and(_T_668, _T_674) @[el2_lsu_bus_buffer.scala 419:100] - node _T_676 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_677 = not(_T_676) @[el2_lsu_bus_buffer.scala 419:162] - node _T_678 = and(_T_675, _T_677) @[el2_lsu_bus_buffer.scala 419:160] - node _T_679 = bits(ld_byte_hitvec_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_680 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_681 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_682 = cat(_T_681, _T_680) @[el2_lsu_bus_buffer.scala 419:147] - node _T_683 = and(ld_byte_hitvec_hi[3], _T_682) @[el2_lsu_bus_buffer.scala 419:126] - node _T_684 = orr(_T_683) @[el2_lsu_bus_buffer.scala 419:155] - node _T_685 = not(_T_684) @[el2_lsu_bus_buffer.scala 419:102] - node _T_686 = and(_T_679, _T_685) @[el2_lsu_bus_buffer.scala 419:100] - node _T_687 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_688 = not(_T_687) @[el2_lsu_bus_buffer.scala 419:162] - node _T_689 = and(_T_686, _T_688) @[el2_lsu_bus_buffer.scala 419:160] - node _T_690 = bits(ld_byte_hitvec_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_691 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_692 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_693 = cat(_T_692, _T_691) @[el2_lsu_bus_buffer.scala 419:147] - node _T_694 = and(ld_byte_hitvec_hi[3], _T_693) @[el2_lsu_bus_buffer.scala 419:126] - node _T_695 = orr(_T_694) @[el2_lsu_bus_buffer.scala 419:155] - node _T_696 = not(_T_695) @[el2_lsu_bus_buffer.scala 419:102] - node _T_697 = and(_T_690, _T_696) @[el2_lsu_bus_buffer.scala 419:100] - node _T_698 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_699 = not(_T_698) @[el2_lsu_bus_buffer.scala 419:162] - node _T_700 = and(_T_697, _T_699) @[el2_lsu_bus_buffer.scala 419:160] - node _T_701 = cat(_T_700, _T_689) @[Cat.scala 29:58] - node _T_702 = cat(_T_701, _T_678) @[Cat.scala 29:58] - node _T_703 = cat(_T_702, _T_667) @[Cat.scala 29:58] - ld_byte_hitvecfn_hi[0] <= _T_562 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[1] <= _T_609 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[2] <= _T_656 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[3] <= _T_703 @[el2_lsu_bus_buffer.scala 419:28] - node _T_704 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 422:75] - node _T_705 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 422:88] - node _T_706 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_707 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_708 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_709 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_710 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_711 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_712 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_713 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_714 = mux(_T_706, _T_707, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_715 = mux(_T_708, _T_709, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_716 = mux(_T_710, _T_711, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_717 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_718 = or(_T_714, _T_715) @[Mux.scala 27:72] - node _T_719 = or(_T_718, _T_716) @[Mux.scala 27:72] - node _T_720 = or(_T_719, _T_717) @[Mux.scala 27:72] - wire _T_721 : UInt<8> @[Mux.scala 27:72] - _T_721 <= _T_720 @[Mux.scala 27:72] - node _T_722 = mux(_T_704, _T_705, _T_721) @[el2_lsu_bus_buffer.scala 422:55] - node _T_723 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 422:75] - node _T_724 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 422:88] - node _T_725 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_726 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_727 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_728 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_729 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_730 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_731 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_732 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_733 = mux(_T_725, _T_726, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_734 = mux(_T_727, _T_728, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_735 = mux(_T_729, _T_730, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_736 = mux(_T_731, _T_732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_737 = or(_T_733, _T_734) @[Mux.scala 27:72] - node _T_738 = or(_T_737, _T_735) @[Mux.scala 27:72] - node _T_739 = or(_T_738, _T_736) @[Mux.scala 27:72] - wire _T_740 : UInt<8> @[Mux.scala 27:72] - _T_740 <= _T_739 @[Mux.scala 27:72] - node _T_741 = mux(_T_723, _T_724, _T_740) @[el2_lsu_bus_buffer.scala 422:55] - node _T_742 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 422:75] - node _T_743 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 422:88] - node _T_744 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_745 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_746 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_747 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_748 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_749 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_750 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_751 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_752 = mux(_T_744, _T_745, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_753 = mux(_T_746, _T_747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_754 = mux(_T_748, _T_749, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_755 = mux(_T_750, _T_751, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_756 = or(_T_752, _T_753) @[Mux.scala 27:72] - node _T_757 = or(_T_756, _T_754) @[Mux.scala 27:72] - node _T_758 = or(_T_757, _T_755) @[Mux.scala 27:72] - wire _T_759 : UInt<8> @[Mux.scala 27:72] - _T_759 <= _T_758 @[Mux.scala 27:72] - node _T_760 = mux(_T_742, _T_743, _T_759) @[el2_lsu_bus_buffer.scala 422:55] - node _T_761 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 422:75] - node _T_762 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 422:88] - node _T_763 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_764 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_765 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_766 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_767 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_768 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_769 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_770 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_771 = mux(_T_763, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_772 = mux(_T_765, _T_766, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_773 = mux(_T_767, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_774 = mux(_T_769, _T_770, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_775 = or(_T_771, _T_772) @[Mux.scala 27:72] - node _T_776 = or(_T_775, _T_773) @[Mux.scala 27:72] - node _T_777 = or(_T_776, _T_774) @[Mux.scala 27:72] - wire _T_778 : UInt<8> @[Mux.scala 27:72] - _T_778 <= _T_777 @[Mux.scala 27:72] - node _T_779 = mux(_T_761, _T_762, _T_778) @[el2_lsu_bus_buffer.scala 422:55] - node _T_780 = cat(_T_779, _T_760) @[Cat.scala 29:58] - node _T_781 = cat(_T_780, _T_741) @[Cat.scala 29:58] - node _T_782 = cat(_T_781, _T_722) @[Cat.scala 29:58] - io.ld_fwddata_buf_lo <= _T_782 @[el2_lsu_bus_buffer.scala 422:28] - node _T_783 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 423:75] - node _T_784 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 423:88] - node _T_785 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_786 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_787 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_788 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_789 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_790 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_791 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_792 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_793 = mux(_T_785, _T_786, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_794 = mux(_T_787, _T_788, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_795 = mux(_T_789, _T_790, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_796 = mux(_T_791, _T_792, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_797 = or(_T_793, _T_794) @[Mux.scala 27:72] - node _T_798 = or(_T_797, _T_795) @[Mux.scala 27:72] - node _T_799 = or(_T_798, _T_796) @[Mux.scala 27:72] - wire _T_800 : UInt<8> @[Mux.scala 27:72] - _T_800 <= _T_799 @[Mux.scala 27:72] - node _T_801 = mux(_T_783, _T_784, _T_800) @[el2_lsu_bus_buffer.scala 423:55] - node _T_802 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 423:75] - node _T_803 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 423:88] - node _T_804 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_805 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_806 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_807 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_808 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_809 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_810 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_811 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_812 = mux(_T_804, _T_805, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_813 = mux(_T_806, _T_807, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_814 = mux(_T_808, _T_809, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_815 = mux(_T_810, _T_811, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_816 = or(_T_812, _T_813) @[Mux.scala 27:72] - node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] - node _T_818 = or(_T_817, _T_815) @[Mux.scala 27:72] - wire _T_819 : UInt<8> @[Mux.scala 27:72] - _T_819 <= _T_818 @[Mux.scala 27:72] - node _T_820 = mux(_T_802, _T_803, _T_819) @[el2_lsu_bus_buffer.scala 423:55] - node _T_821 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 423:75] - node _T_822 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 423:88] - node _T_823 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_824 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_825 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_826 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_827 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_828 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_829 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_830 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_831 = mux(_T_823, _T_824, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_832 = mux(_T_825, _T_826, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_833 = mux(_T_827, _T_828, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_834 = mux(_T_829, _T_830, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_835 = or(_T_831, _T_832) @[Mux.scala 27:72] - node _T_836 = or(_T_835, _T_833) @[Mux.scala 27:72] - node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] - wire _T_838 : UInt<8> @[Mux.scala 27:72] - _T_838 <= _T_837 @[Mux.scala 27:72] - node _T_839 = mux(_T_821, _T_822, _T_838) @[el2_lsu_bus_buffer.scala 423:55] - node _T_840 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 423:75] - node _T_841 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 423:88] - node _T_842 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_843 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_844 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_845 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_846 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_847 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_848 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_849 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_850 = mux(_T_842, _T_843, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_851 = mux(_T_844, _T_845, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_852 = mux(_T_846, _T_847, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_853 = mux(_T_848, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_854 = or(_T_850, _T_851) @[Mux.scala 27:72] - node _T_855 = or(_T_854, _T_852) @[Mux.scala 27:72] - node _T_856 = or(_T_855, _T_853) @[Mux.scala 27:72] - wire _T_857 : UInt<8> @[Mux.scala 27:72] - _T_857 <= _T_856 @[Mux.scala 27:72] - node _T_858 = mux(_T_840, _T_841, _T_857) @[el2_lsu_bus_buffer.scala 423:55] - node _T_859 = cat(_T_858, _T_839) @[Cat.scala 29:58] - node _T_860 = cat(_T_859, _T_820) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_801) @[Cat.scala 29:58] - io.ld_fwddata_buf_hi <= _T_861 @[el2_lsu_bus_buffer.scala 423:28] - node _T_862 = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:64] - bus_coalescing_disable <= _T_862 @[el2_lsu_bus_buffer.scala 426:28] - node _T_863 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_bus_buffer.scala 428:55] - node _T_864 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_bus_buffer.scala 429:55] - node _T_865 = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_bus_buffer.scala 430:53] - node _T_866 = mux(_T_863, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_867 = mux(_T_864, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_868 = mux(_T_865, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_869 = or(_T_866, _T_867) @[Mux.scala 27:72] - node _T_870 = or(_T_869, _T_868) @[Mux.scala 27:72] - wire _T_871 : UInt<4> @[Mux.scala 27:72] - _T_871 <= _T_870 @[Mux.scala 27:72] - ldst_byteen_r <= _T_871 @[el2_lsu_bus_buffer.scala 427:28] - node _T_872 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_873 = bits(ldst_byteen_r, 3, 0) @[el2_lsu_bus_buffer.scala 432:64] - node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] - node _T_875 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 432:87] - node ldst_byteen_extended_r = dshl(_T_874, _T_875) @[el2_lsu_bus_buffer.scala 432:71] - node _T_876 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_877 = bits(io.store_data_r, 31, 0) @[el2_lsu_bus_buffer.scala 433:67] - node _T_878 = cat(_T_876, _T_877) @[Cat.scala 29:58] - node _T_879 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 433:96] - node _T_880 = mul(UInt<4>("h08"), _T_879) @[el2_lsu_bus_buffer.scala 433:82] - node store_data_extended_r = dshl(_T_878, _T_880) @[el2_lsu_bus_buffer.scala 433:75] - node _T_881 = bits(ldst_byteen_extended_r, 7, 4) @[el2_lsu_bus_buffer.scala 434:58] - ldst_byteen_hi_r <= _T_881 @[el2_lsu_bus_buffer.scala 434:33] - node _T_882 = bits(ldst_byteen_extended_r, 3, 0) @[el2_lsu_bus_buffer.scala 435:58] - ldst_byteen_lo_r <= _T_882 @[el2_lsu_bus_buffer.scala 435:33] - node _T_883 = bits(store_data_extended_r, 63, 32) @[el2_lsu_bus_buffer.scala 436:57] - store_data_hi_r <= _T_883 @[el2_lsu_bus_buffer.scala 436:33] - node _T_884 = bits(store_data_extended_r, 31, 0) @[el2_lsu_bus_buffer.scala 437:57] - store_data_lo_r <= _T_884 @[el2_lsu_bus_buffer.scala 437:33] - node _T_885 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 438:49] - node _T_886 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 438:70] - node _T_887 = eq(_T_885, _T_886) @[el2_lsu_bus_buffer.scala 438:53] - ldst_samedw_r <= _T_887 @[el2_lsu_bus_buffer.scala 438:33] - node _T_888 = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_bus_buffer.scala 440:59] - node _T_889 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_bus_buffer.scala 441:61] - node _T_890 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 441:85] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 441:96] - node _T_892 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_bus_buffer.scala 442:61] - node _T_893 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 442:85] - node _T_894 = eq(_T_893, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 442:98] - node _T_895 = mux(_T_888, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_896 = mux(_T_889, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_897 = mux(_T_892, _T_894, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_898 = or(_T_895, _T_896) @[Mux.scala 27:72] - node _T_899 = or(_T_898, _T_897) @[Mux.scala 27:72] - wire _T_900 : UInt<1> @[Mux.scala 27:72] - _T_900 <= _T_899 @[Mux.scala 27:72] - is_aligned_r <= _T_900 @[el2_lsu_bus_buffer.scala 439:33] - node _T_901 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 445:71] - node _T_902 = and(io.lsu_busreq_r, _T_901) @[el2_lsu_bus_buffer.scala 445:50] - node _T_903 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 445:95] - node _T_904 = and(_T_902, _T_903) @[el2_lsu_bus_buffer.scala 445:93] - node _T_905 = bits(_T_904, 0, 0) @[el2_lsu_bus_buffer.scala 445:108] - ibuf_byp <= _T_905 @[el2_lsu_bus_buffer.scala 445:30] - node _T_906 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 446:50] - node _T_907 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 446:70] - node _T_908 = and(_T_906, _T_907) @[el2_lsu_bus_buffer.scala 446:68] - node _T_909 = bits(_T_908, 0, 0) @[el2_lsu_bus_buffer.scala 446:81] - ibuf_wr_en <= _T_909 @[el2_lsu_bus_buffer.scala 446:30] - node _T_910 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 447:52] - node _T_911 = and(ibuf_drain_vld, _T_910) @[el2_lsu_bus_buffer.scala 447:50] - node _T_912 = or(_T_911, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 447:65] - node _T_913 = bits(_T_912, 0, 0) @[el2_lsu_bus_buffer.scala 447:90] - ibuf_rst <= _T_913 @[el2_lsu_bus_buffer.scala 447:30] - node _T_914 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 448:52] - node _T_915 = and(io.lsu_busreq_m, _T_914) @[el2_lsu_bus_buffer.scala 448:50] - node _T_916 = and(_T_915, ibuf_valid) @[el2_lsu_bus_buffer.scala 448:69] - node _T_917 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 448:115] - node _T_918 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 448:139] - node _T_919 = neq(_T_917, _T_918) @[el2_lsu_bus_buffer.scala 448:122] - node _T_920 = or(io.lsu_pkt_m.load, _T_919) @[el2_lsu_bus_buffer.scala 448:103] - node _T_921 = and(_T_916, _T_920) @[el2_lsu_bus_buffer.scala 448:82] - node _T_922 = bits(_T_921, 0, 0) @[el2_lsu_bus_buffer.scala 448:149] - ibuf_force_drain <= _T_922 @[el2_lsu_bus_buffer.scala 448:30] - node _T_923 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 449:74] - node _T_924 = or(ibuf_wr_en, _T_923) @[el2_lsu_bus_buffer.scala 449:60] - node _T_925 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 449:131] - node _T_926 = eq(_T_925, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 449:115] - node _T_927 = and(_T_924, _T_926) @[el2_lsu_bus_buffer.scala 449:113] - node _T_928 = or(_T_927, ibuf_byp) @[el2_lsu_bus_buffer.scala 449:149] - node _T_929 = or(_T_928, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 450:45] - node _T_930 = or(_T_929, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 450:64] - node _T_931 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 450:84] - node _T_932 = or(_T_930, _T_931) @[el2_lsu_bus_buffer.scala 450:82] - node _T_933 = or(_T_932, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 450:96] - node _T_934 = and(ibuf_valid, _T_933) @[el2_lsu_bus_buffer.scala 449:44] - ibuf_drain_vld <= _T_934 @[el2_lsu_bus_buffer.scala 449:30] - node _T_935 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 451:52] - node _T_936 = bits(ibuf_tag, 1, 0) @[el2_lsu_bus_buffer.scala 451:78] - node _T_937 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 451:98] - node _T_938 = mux(_T_935, _T_936, _T_937) @[el2_lsu_bus_buffer.scala 451:36] - ibuf_tag_in <= _T_938 @[el2_lsu_bus_buffer.scala 451:30] - node _T_939 = bits(WrPtr0_r, 1, 0) @[el2_lsu_bus_buffer.scala 452:41] - ibuf_dualtag_in <= _T_939 @[el2_lsu_bus_buffer.scala 452:30] - node _T_940 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - ibuf_sz_in <= _T_940 @[el2_lsu_bus_buffer.scala 453:30] - node _T_941 = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 454:36] - ibuf_addr_in <= _T_941 @[el2_lsu_bus_buffer.scala 454:30] - node _T_942 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 455:51] - node _T_943 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 455:79] - node _T_944 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:103] - node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 455:85] - node _T_946 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:146] - node _T_947 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:169] - node _T_948 = mux(io.ldst_dual_r, _T_946, _T_947) @[el2_lsu_bus_buffer.scala 455:113] - node _T_949 = mux(_T_942, _T_945, _T_948) @[el2_lsu_bus_buffer.scala 455:36] - ibuf_byteen_in <= _T_949 @[el2_lsu_bus_buffer.scala 455:30] - node _T_950 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_951 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 456:110] - node _T_952 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:129] - node _T_953 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 456:156] - node _T_954 = mux(_T_951, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 456:93] - node _T_955 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:208] - node _T_956 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:240] - node _T_957 = mux(io.ldst_dual_r, _T_955, _T_956) @[el2_lsu_bus_buffer.scala 456:176] - node _T_958 = mux(_T_950, _T_954, _T_957) @[el2_lsu_bus_buffer.scala 456:57] - node _T_959 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_960 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 456:110] - node _T_961 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:129] - node _T_962 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 456:156] - node _T_963 = mux(_T_960, _T_961, _T_962) @[el2_lsu_bus_buffer.scala 456:93] - node _T_964 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:208] - node _T_965 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:240] - node _T_966 = mux(io.ldst_dual_r, _T_964, _T_965) @[el2_lsu_bus_buffer.scala 456:176] - node _T_967 = mux(_T_959, _T_963, _T_966) @[el2_lsu_bus_buffer.scala 456:57] - node _T_968 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_969 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 456:110] - node _T_970 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:129] - node _T_971 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 456:156] - node _T_972 = mux(_T_969, _T_970, _T_971) @[el2_lsu_bus_buffer.scala 456:93] - node _T_973 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:208] - node _T_974 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:240] - node _T_975 = mux(io.ldst_dual_r, _T_973, _T_974) @[el2_lsu_bus_buffer.scala 456:176] - node _T_976 = mux(_T_968, _T_972, _T_975) @[el2_lsu_bus_buffer.scala 456:57] - node _T_977 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_978 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 456:110] - node _T_979 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:129] - node _T_980 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 456:156] - node _T_981 = mux(_T_978, _T_979, _T_980) @[el2_lsu_bus_buffer.scala 456:93] - node _T_982 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:208] - node _T_983 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:240] - node _T_984 = mux(io.ldst_dual_r, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 456:176] - node _T_985 = mux(_T_977, _T_981, _T_984) @[el2_lsu_bus_buffer.scala 456:57] - node _T_986 = cat(_T_985, _T_976) @[Cat.scala 29:58] - node _T_987 = cat(_T_986, _T_967) @[Cat.scala 29:58] - node _T_988 = cat(_T_987, _T_958) @[Cat.scala 29:58] - ibuf_data_in <= _T_988 @[el2_lsu_bus_buffer.scala 456:30] - node _T_989 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 457:69] - node _T_990 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 457:115] - node _T_991 = tail(_T_990, 1) @[el2_lsu_bus_buffer.scala 457:115] - node _T_992 = mux(_T_989, _T_991, ibuf_timer) @[el2_lsu_bus_buffer.scala 457:57] - node _T_993 = mux(ibuf_wr_en, UInt<1>("h00"), _T_992) @[el2_lsu_bus_buffer.scala 457:36] - ibuf_timer_in <= _T_993 @[el2_lsu_bus_buffer.scala 457:30] - node _T_994 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_995 = and(ibuf_merge_en, _T_994) @[el2_lsu_bus_buffer.scala 458:73] - node _T_996 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 458:102] - node _T_997 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 458:124] - node _T_998 = or(_T_996, _T_997) @[el2_lsu_bus_buffer.scala 458:106] - node _T_999 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1000 = mux(_T_995, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1001 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1002 = and(ibuf_merge_en, _T_1001) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1003 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1004 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1005 = or(_T_1003, _T_1004) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1006 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1007 = mux(_T_1002, _T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1008 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1009 = and(ibuf_merge_en, _T_1008) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1010 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1011 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1012 = or(_T_1010, _T_1011) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1013 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1014 = mux(_T_1009, _T_1012, _T_1013) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1015 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1016 = and(ibuf_merge_en, _T_1015) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1017 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1018 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1019 = or(_T_1017, _T_1018) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1020 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1021 = mux(_T_1016, _T_1019, _T_1020) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1022 = cat(_T_1021, _T_1014) @[Cat.scala 29:58] - node _T_1023 = cat(_T_1022, _T_1007) @[Cat.scala 29:58] - node _T_1024 = cat(_T_1023, _T_1000) @[Cat.scala 29:58] - ibuf_byteen_out <= _T_1024 @[el2_lsu_bus_buffer.scala 458:30] - node _T_1025 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1026 = and(ibuf_merge_en, _T_1025) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1027 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1028 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1029 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1030 = mux(_T_1027, _T_1028, _T_1029) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1031 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1032 = mux(_T_1026, _T_1030, _T_1031) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1033 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1034 = and(ibuf_merge_en, _T_1033) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1035 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1036 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1037 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1038 = mux(_T_1035, _T_1036, _T_1037) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1039 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1040 = mux(_T_1034, _T_1038, _T_1039) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1041 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1042 = and(ibuf_merge_en, _T_1041) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1043 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1044 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1045 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1046 = mux(_T_1043, _T_1044, _T_1045) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1047 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1048 = mux(_T_1042, _T_1046, _T_1047) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1049 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1050 = and(ibuf_merge_en, _T_1049) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1051 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1052 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1053 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1054 = mux(_T_1051, _T_1052, _T_1053) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1055 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1056 = mux(_T_1050, _T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1057 = cat(_T_1056, _T_1048) @[Cat.scala 29:58] - node _T_1058 = cat(_T_1057, _T_1040) @[Cat.scala 29:58] - node _T_1059 = cat(_T_1058, _T_1032) @[Cat.scala 29:58] - ibuf_data_out <= _T_1059 @[el2_lsu_bus_buffer.scala 459:30] - node _T_1060 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 460:49] - node _T_1061 = and(_T_1060, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 460:67] - node _T_1062 = and(_T_1061, ibuf_valid) @[el2_lsu_bus_buffer.scala 460:88] - node _T_1063 = and(_T_1062, ibuf_write) @[el2_lsu_bus_buffer.scala 460:101] - node _T_1064 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 460:129] - node _T_1065 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 460:147] - node _T_1066 = eq(_T_1064, _T_1065) @[el2_lsu_bus_buffer.scala 460:135] - node _T_1067 = and(_T_1063, _T_1066) @[el2_lsu_bus_buffer.scala 460:114] - node _T_1068 = not(io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 460:156] - node _T_1069 = and(_T_1067, _T_1068) @[el2_lsu_bus_buffer.scala 460:154] - node _T_1070 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 460:179] - node _T_1071 = and(_T_1069, _T_1070) @[el2_lsu_bus_buffer.scala 460:177] - ibuf_merge_en <= _T_1071 @[el2_lsu_bus_buffer.scala 460:30] - node _T_1072 = not(io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:33] - ibuf_merge_in <= _T_1072 @[el2_lsu_bus_buffer.scala 461:30] - node _T_1073 = bits(ibuf_wr_en, 0, 0) @[el2_lsu_bus_buffer.scala 464:50] - node _T_1074 = mux(_T_1073, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 464:32] - node _T_1075 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 464:72] - node _T_1076 = and(_T_1074, _T_1075) @[el2_lsu_bus_buffer.scala 464:70] - reg _T_1077 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 464:28] - _T_1077 <= _T_1076 @[el2_lsu_bus_buffer.scala 464:28] - ibuf_valid <= _T_1077 @[el2_lsu_bus_buffer.scala 464:18] - reg _T_1078 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 465:35] - _T_1078 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 465:35] - ibuf_timer <= _T_1078 @[el2_lsu_bus_buffer.scala 465:25] - reg _T_1079 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1079 <= io.ldst_dual_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_dual <= _T_1079 @[el2_lsu_bus_buffer.scala 468:25] - reg _T_1080 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1080 <= ldst_samedw_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_samedw <= _T_1080 @[el2_lsu_bus_buffer.scala 469:25] - reg _T_1081 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1081 <= io.no_dword_merge_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_nomerge <= _T_1081 @[el2_lsu_bus_buffer.scala 470:25] - reg _T_1082 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1082 <= io.is_sideeffects_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_sideeffect <= _T_1082 @[el2_lsu_bus_buffer.scala 471:25] - reg _T_1083 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1083 <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_unsign <= _T_1083 @[el2_lsu_bus_buffer.scala 472:25] - reg _T_1084 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1084 <= io.lsu_pkt_r.store @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_write <= _T_1084 @[el2_lsu_bus_buffer.scala 473:25] - node _T_1085 = bits(ibuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 474:48] - reg _T_1086 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1086 <= _T_1085 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_sz <= _T_1086 @[el2_lsu_bus_buffer.scala 474:25] - reg _T_1087 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1087 <= ibuf_byteen_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_byteen <= _T_1087 @[el2_lsu_bus_buffer.scala 475:25] - node _T_1088 = bits(ibuf_addr_in, 31, 0) @[el2_lsu_bus_buffer.scala 476:50] - reg _T_1089 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1089 <= _T_1088 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_addr <= _T_1089 @[el2_lsu_bus_buffer.scala 476:25] - node _T_1090 = bits(ibuf_data_in, 31, 0) @[el2_lsu_bus_buffer.scala 477:50] - reg _T_1091 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1091 <= _T_1090 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_data <= _T_1091 @[el2_lsu_bus_buffer.scala 477:25] - reg _T_1092 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1092 <= ibuf_tag_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_tag <= _T_1092 @[el2_lsu_bus_buffer.scala 478:25] - reg _T_1093 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1093 <= ibuf_dualtag_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_dualtag <= _T_1093 @[el2_lsu_bus_buffer.scala 479:25] - node _T_1094 = bits(buf_numvld_pend_any, 3, 0) @[el2_lsu_bus_buffer.scala 483:61] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:67] - node _T_1096 = and(ibuf_byp, _T_1095) @[el2_lsu_bus_buffer.scala 483:39] - node _T_1097 = not(io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 483:79] - node _T_1098 = or(_T_1097, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 483:99] - node _T_1099 = and(_T_1096, _T_1098) @[el2_lsu_bus_buffer.scala 483:76] - ibuf_buf_byp <= _T_1099 @[el2_lsu_bus_buffer.scala 483:26] - node _T_1100 = not(io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 484:47] - node _T_1101 = and(io.lsu_busreq_m, _T_1100) @[el2_lsu_bus_buffer.scala 484:45] - node _T_1102 = not(ibuf_valid) @[el2_lsu_bus_buffer.scala 484:66] - node _T_1103 = and(_T_1101, _T_1102) @[el2_lsu_bus_buffer.scala 484:64] - node _T_1104 = bits(buf_numvld_cmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 484:99] - node _T_1105 = eq(_T_1104, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 484:105] - node _T_1106 = and(_T_1103, _T_1105) @[el2_lsu_bus_buffer.scala 484:78] - node _T_1107 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 484:135] - node _T_1108 = bits(buf_addr[CmdPtr0], 31, 2) @[el2_lsu_bus_buffer.scala 484:163] - node _T_1109 = neq(_T_1107, _T_1108) @[el2_lsu_bus_buffer.scala 484:142] - node _T_1110 = and(_T_1106, _T_1109) @[el2_lsu_bus_buffer.scala 484:119] - obuf_force_wr_en <= _T_1110 @[el2_lsu_bus_buffer.scala 484:26] - node _T_1111 = bits(buf_numvld_wrcmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 485:50] - node _T_1112 = eq(_T_1111, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 485:56] - node _T_1113 = bits(buf_numvld_cmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 485:91] - node _T_1114 = eq(_T_1113, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 485:97] - node _T_1115 = and(_T_1112, _T_1114) @[el2_lsu_bus_buffer.scala 485:70] - node _T_1116 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 485:128] - node _T_1117 = and(_T_1115, _T_1116) @[el2_lsu_bus_buffer.scala 485:111] - node _T_1118 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 486:33] - node _T_1119 = and(_T_1117, _T_1118) @[el2_lsu_bus_buffer.scala 485:166] - node _T_1120 = not(buf_nomerge[CmdPtr0]) @[el2_lsu_bus_buffer.scala 486:59] - node _T_1121 = and(_T_1119, _T_1120) @[el2_lsu_bus_buffer.scala 486:57] - node _T_1122 = not(buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 486:83] - node _T_1123 = and(_T_1121, _T_1122) @[el2_lsu_bus_buffer.scala 486:81] - node _T_1124 = not(obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 486:110] - node _T_1125 = and(_T_1123, _T_1124) @[el2_lsu_bus_buffer.scala 486:108] - obuf_wr_wait <= _T_1125 @[el2_lsu_bus_buffer.scala 485:26] - node _T_1126 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 487:44] - node _T_1127 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 487:86] - node _T_1128 = not(_T_1127) @[el2_lsu_bus_buffer.scala 487:64] - node _T_1129 = and(_T_1126, _T_1128) @[el2_lsu_bus_buffer.scala 487:62] - node _T_1130 = eq(buf_state[CmdPtr0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 488:54] - node _T_1131 = and(_T_1130, found_cmdptr0) @[el2_lsu_bus_buffer.scala 488:65] - node _T_1132 = not(buf_cmd_state_bus_en[CmdPtr0]) @[el2_lsu_bus_buffer.scala 488:83] - node _T_1133 = and(_T_1131, _T_1132) @[el2_lsu_bus_buffer.scala 488:81] - node _T_1134 = and(buf_sideeffect[CmdPtr0], bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 488:142] - node _T_1135 = not(_T_1134) @[el2_lsu_bus_buffer.scala 488:116] - node _T_1136 = and(_T_1133, _T_1135) @[el2_lsu_bus_buffer.scala 488:114] - node _T_1137 = and(buf_dual[CmdPtr0], buf_samedw[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:58] - node _T_1138 = not(buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:82] - node _T_1139 = and(_T_1137, _T_1138) @[el2_lsu_bus_buffer.scala 489:80] - node _T_1140 = not(_T_1139) @[el2_lsu_bus_buffer.scala 489:38] - node _T_1141 = or(_T_1140, found_cmdptr1) @[el2_lsu_bus_buffer.scala 489:103] - node _T_1142 = or(_T_1141, buf_nomerge[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:119] - node _T_1143 = or(_T_1142, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 489:142] - node _T_1144 = and(_T_1136, _T_1143) @[el2_lsu_bus_buffer.scala 488:165] - node _T_1145 = or(_T_1129, _T_1144) @[el2_lsu_bus_buffer.scala 487:110] - node _T_1146 = not(obuf_valid) @[el2_lsu_bus_buffer.scala 490:57] - node _T_1147 = or(bus_cmd_ready, _T_1146) @[el2_lsu_bus_buffer.scala 490:55] - node _T_1148 = or(_T_1147, obuf_nosend) @[el2_lsu_bus_buffer.scala 490:69] - node _T_1149 = and(_T_1145, _T_1148) @[el2_lsu_bus_buffer.scala 489:164] - node _T_1150 = not(obuf_wr_wait) @[el2_lsu_bus_buffer.scala 490:86] - node _T_1151 = and(_T_1149, _T_1150) @[el2_lsu_bus_buffer.scala 490:84] - node _T_1152 = not(lsu_bus_cntr_overflow) @[el2_lsu_bus_buffer.scala 490:102] - node _T_1153 = and(_T_1151, _T_1152) @[el2_lsu_bus_buffer.scala 490:100] - node _T_1154 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 490:127] - node _T_1155 = and(_T_1153, _T_1154) @[el2_lsu_bus_buffer.scala 490:125] - node _T_1156 = and(_T_1155, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:151] - obuf_wr_en <= _T_1156 @[el2_lsu_bus_buffer.scala 487:26] - node _T_1157 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 491:58] - node _T_1158 = or(bus_cmd_sent, _T_1157) @[el2_lsu_bus_buffer.scala 491:44] - node _T_1159 = not(obuf_wr_en) @[el2_lsu_bus_buffer.scala 491:76] - node _T_1160 = and(_T_1158, _T_1159) @[el2_lsu_bus_buffer.scala 491:74] - node _T_1161 = and(_T_1160, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:88] - node _T_1162 = or(_T_1161, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 491:109] - obuf_rst <= _T_1162 @[el2_lsu_bus_buffer.scala 491:26] - node _T_1163 = mux(ibuf_buf_byp, io.lsu_pkt_r.store, buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 492:32] - obuf_write_in <= _T_1163 @[el2_lsu_bus_buffer.scala 492:26] - node _T_1164 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 493:42] - node _T_1165 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 493:62] - node _T_1166 = eq(_T_1164, _T_1165) @[el2_lsu_bus_buffer.scala 493:49] - node _T_1167 = and(_T_1166, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 493:70] - node _T_1168 = not(obuf_sideeffect) @[el2_lsu_bus_buffer.scala 493:90] - node _T_1169 = and(_T_1167, _T_1168) @[el2_lsu_bus_buffer.scala 493:88] - node _T_1170 = not(obuf_write) @[el2_lsu_bus_buffer.scala 493:109] - node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_bus_buffer.scala 493:107] - node _T_1172 = not(obuf_write_in) @[el2_lsu_bus_buffer.scala 493:123] - node _T_1173 = and(_T_1171, _T_1172) @[el2_lsu_bus_buffer.scala 493:121] - node _T_1174 = not(io.dec_tlu_external_ldfwd_disable) @[el2_lsu_bus_buffer.scala 493:140] - node _T_1175 = and(_T_1173, _T_1174) @[el2_lsu_bus_buffer.scala 493:138] - node _T_1176 = not(obuf_nosend) @[el2_lsu_bus_buffer.scala 494:48] - node _T_1177 = and(obuf_valid, _T_1176) @[el2_lsu_bus_buffer.scala 494:46] - node _T_1178 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 494:118] - node _T_1179 = and(bus_rsp_read, _T_1178) @[el2_lsu_bus_buffer.scala 494:98] - node _T_1180 = not(_T_1179) @[el2_lsu_bus_buffer.scala 494:83] - node _T_1181 = and(obuf_rdrsp_pend, _T_1180) @[el2_lsu_bus_buffer.scala 494:81] - node _T_1182 = or(_T_1177, _T_1181) @[el2_lsu_bus_buffer.scala 494:62] - node _T_1183 = and(_T_1175, _T_1182) @[el2_lsu_bus_buffer.scala 493:175] - obuf_nosend_in <= _T_1183 @[el2_lsu_bus_buffer.scala 493:26] - node _T_1184 = not(obuf_nosend_in) @[el2_lsu_bus_buffer.scala 495:45] - node _T_1185 = and(obuf_wr_en, _T_1184) @[el2_lsu_bus_buffer.scala 495:43] - node _T_1186 = not(_T_1185) @[el2_lsu_bus_buffer.scala 495:30] - node _T_1187 = and(_T_1186, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 495:62] - node _T_1188 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 495:117] - node _T_1189 = and(bus_rsp_read, _T_1188) @[el2_lsu_bus_buffer.scala 495:97] - node _T_1190 = not(_T_1189) @[el2_lsu_bus_buffer.scala 495:82] - node _T_1191 = and(_T_1187, _T_1190) @[el2_lsu_bus_buffer.scala 495:80] - node _T_1192 = not(obuf_write) @[el2_lsu_bus_buffer.scala 495:158] - node _T_1193 = and(bus_cmd_sent, _T_1192) @[el2_lsu_bus_buffer.scala 495:156] - node _T_1194 = not(io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 495:173] - node _T_1195 = and(_T_1193, _T_1194) @[el2_lsu_bus_buffer.scala 495:171] - node _T_1196 = or(_T_1191, _T_1195) @[el2_lsu_bus_buffer.scala 495:139] - obuf_rdrsp_pend_in <= _T_1196 @[el2_lsu_bus_buffer.scala 495:26] - node _T_1197 = mux(ibuf_buf_byp, io.is_sideeffects_r, buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 496:32] - obuf_sideeffect_in <= _T_1197 @[el2_lsu_bus_buffer.scala 496:26] - node _T_1198 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 497:72] - node _T_1199 = eq(_T_1198, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 497:78] - node _T_1200 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 497:104] - node _T_1201 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 497:123] - node _T_1202 = not(_T_1201) @[el2_lsu_bus_buffer.scala 497:110] - node _T_1203 = and(_T_1200, _T_1202) @[el2_lsu_bus_buffer.scala 497:108] - node _T_1204 = or(_T_1199, _T_1203) @[el2_lsu_bus_buffer.scala 497:91] - node _T_1205 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 497:141] - node _T_1206 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 497:161] - node _T_1207 = orr(_T_1206) @[el2_lsu_bus_buffer.scala 497:167] - node _T_1208 = not(_T_1207) @[el2_lsu_bus_buffer.scala 497:147] - node _T_1209 = and(_T_1205, _T_1208) @[el2_lsu_bus_buffer.scala 497:145] - node _T_1210 = or(_T_1204, _T_1209) @[el2_lsu_bus_buffer.scala 497:128] - node _T_1211 = mux(ibuf_buf_byp, is_aligned_r, _T_1210) @[el2_lsu_bus_buffer.scala 497:32] - obuf_aligned_in <= _T_1211 @[el2_lsu_bus_buffer.scala 497:26] - node _T_1212 = mux(ibuf_buf_byp, io.lsu_addr_r, buf_addr[CmdPtr0]) @[el2_lsu_bus_buffer.scala 498:32] - obuf_addr_in <= _T_1212 @[el2_lsu_bus_buffer.scala 498:26] - node _T_1213 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1214 = and(obuf_merge_en, _T_1213) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1215 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1216 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1217 = mux(_T_1214, _T_1215, _T_1216) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1218 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1219 = and(obuf_merge_en, _T_1218) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1220 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1221 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1222 = mux(_T_1219, _T_1220, _T_1221) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1223 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1224 = and(obuf_merge_en, _T_1223) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1225 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1226 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1227 = mux(_T_1224, _T_1225, _T_1226) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1228 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1229 = and(obuf_merge_en, _T_1228) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1230 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1231 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1232 = mux(_T_1229, _T_1230, _T_1231) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1233 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1234 = and(obuf_merge_en, _T_1233) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1235 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1236 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1237 = mux(_T_1234, _T_1235, _T_1236) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1238 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1239 = and(obuf_merge_en, _T_1238) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1240 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1241 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1242 = mux(_T_1239, _T_1240, _T_1241) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1243 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1244 = and(obuf_merge_en, _T_1243) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1245 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1246 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1247 = mux(_T_1244, _T_1245, _T_1246) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1248 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1249 = and(obuf_merge_en, _T_1248) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1250 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1251 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1252 = mux(_T_1249, _T_1250, _T_1251) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1253 = cat(_T_1252, _T_1247) @[Cat.scala 29:58] - node _T_1254 = cat(_T_1253, _T_1242) @[Cat.scala 29:58] - node _T_1255 = cat(_T_1254, _T_1237) @[Cat.scala 29:58] - node _T_1256 = cat(_T_1255, _T_1232) @[Cat.scala 29:58] - node _T_1257 = cat(_T_1256, _T_1227) @[Cat.scala 29:58] - node _T_1258 = cat(_T_1257, _T_1222) @[Cat.scala 29:58] - node _T_1259 = cat(_T_1258, _T_1217) @[Cat.scala 29:58] - obuf_data_in <= _T_1259 @[el2_lsu_bus_buffer.scala 499:26] - node _T_1260 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_1261 = mux(ibuf_buf_byp, _T_1260, buf_sz[CmdPtr0]) @[el2_lsu_bus_buffer.scala 500:32] - obuf_sz_in <= _T_1261 @[el2_lsu_bus_buffer.scala 500:26] - node _T_1262 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1263 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1264 = and(obuf_merge_en, _T_1263) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1265 = or(_T_1262, _T_1264) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1266 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1267 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1268 = and(obuf_merge_en, _T_1267) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1269 = or(_T_1266, _T_1268) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1270 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1271 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1272 = and(obuf_merge_en, _T_1271) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1273 = or(_T_1270, _T_1272) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1274 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1275 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1276 = and(obuf_merge_en, _T_1275) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1277 = or(_T_1274, _T_1276) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1278 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1279 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1280 = and(obuf_merge_en, _T_1279) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1281 = or(_T_1278, _T_1280) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1282 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1283 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1284 = and(obuf_merge_en, _T_1283) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1285 = or(_T_1282, _T_1284) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1286 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1287 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1288 = and(obuf_merge_en, _T_1287) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1289 = or(_T_1286, _T_1288) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1290 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1291 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1292 = and(obuf_merge_en, _T_1291) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1293 = or(_T_1290, _T_1292) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1294 = cat(_T_1293, _T_1289) @[Cat.scala 29:58] - node _T_1295 = cat(_T_1294, _T_1285) @[Cat.scala 29:58] - node _T_1296 = cat(_T_1295, _T_1281) @[Cat.scala 29:58] - node _T_1297 = cat(_T_1296, _T_1277) @[Cat.scala 29:58] - node _T_1298 = cat(_T_1297, _T_1273) @[Cat.scala 29:58] - node _T_1299 = cat(_T_1298, _T_1269) @[Cat.scala 29:58] - node _T_1300 = cat(_T_1299, _T_1265) @[Cat.scala 29:58] - obuf_byteen_in <= _T_1300 @[el2_lsu_bus_buffer.scala 501:26] - obuf_merge_in <= obuf_merge_en @[el2_lsu_bus_buffer.scala 502:26] - node _T_1301 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 503:42] - node _T_1302 = not(_T_1301) @[el2_lsu_bus_buffer.scala 503:29] - node _T_1303 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 503:72] - node _T_1304 = and(_T_1302, _T_1303) @[el2_lsu_bus_buffer.scala 503:54] - obuf_cmd_done_in <= _T_1304 @[el2_lsu_bus_buffer.scala 503:26] - node _T_1305 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 504:42] - node _T_1306 = not(_T_1305) @[el2_lsu_bus_buffer.scala 504:29] - node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 504:72] - node _T_1308 = and(_T_1306, _T_1307) @[el2_lsu_bus_buffer.scala 504:54] - obuf_data_done_in <= _T_1308 @[el2_lsu_bus_buffer.scala 504:26] - node _T_1309 = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 505:32] - obuf_tag0_in <= _T_1309 @[el2_lsu_bus_buffer.scala 505:26] - node _T_1310 = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 506:32] - obuf_tag1_in <= _T_1310 @[el2_lsu_bus_buffer.scala 506:26] - node _T_1311 = not(obuf_write) @[el2_lsu_bus_buffer.scala 507:49] - node _T_1312 = and(bus_cmd_sent, _T_1311) @[el2_lsu_bus_buffer.scala 507:47] - node _T_1313 = bits(obuf_tag0, 2, 0) @[el2_lsu_bus_buffer.scala 507:72] - node _T_1314 = bits(obuf_rdrsp_tag, 2, 0) @[el2_lsu_bus_buffer.scala 507:109] - node _T_1315 = mux(_T_1312, _T_1313, _T_1314) @[el2_lsu_bus_buffer.scala 507:32] - obuf_rdrsp_tag_in <= _T_1315 @[el2_lsu_bus_buffer.scala 507:26] - node _T_1316 = neq(CmdPtr0, CmdPtr1) @[el2_lsu_bus_buffer.scala 509:39] - node _T_1317 = and(_T_1316, found_cmdptr0) @[el2_lsu_bus_buffer.scala 509:52] - node _T_1318 = and(_T_1317, found_cmdptr1) @[el2_lsu_bus_buffer.scala 509:68] - node _T_1319 = eq(buf_state[CmdPtr0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:106] - node _T_1320 = and(_T_1318, _T_1319) @[el2_lsu_bus_buffer.scala 509:84] - node _T_1321 = eq(buf_state[CmdPtr1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:139] - node _T_1322 = and(_T_1320, _T_1321) @[el2_lsu_bus_buffer.scala 509:117] - node _T_1323 = not(buf_cmd_state_bus_en[CmdPtr0]) @[el2_lsu_bus_buffer.scala 510:31] - node _T_1324 = and(_T_1322, _T_1323) @[el2_lsu_bus_buffer.scala 509:150] - node _T_1325 = not(buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 510:64] - node _T_1326 = and(_T_1324, _T_1325) @[el2_lsu_bus_buffer.scala 510:62] - node _T_1327 = and(buf_write[CmdPtr0], buf_write[CmdPtr1]) @[el2_lsu_bus_buffer.scala 511:55] - node _T_1328 = bits(buf_addr[CmdPtr0], 31, 3) @[el2_lsu_bus_buffer.scala 511:96] - node _T_1329 = bits(buf_addr[CmdPtr1], 31, 3) @[el2_lsu_bus_buffer.scala 511:124] - node _T_1330 = eq(_T_1328, _T_1329) @[el2_lsu_bus_buffer.scala 511:103] - node _T_1331 = and(_T_1327, _T_1330) @[el2_lsu_bus_buffer.scala 511:76] - node _T_1332 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 511:134] - node _T_1333 = and(_T_1331, _T_1332) @[el2_lsu_bus_buffer.scala 511:132] - node _T_1334 = not(UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 511:160] - node _T_1335 = and(_T_1333, _T_1334) @[el2_lsu_bus_buffer.scala 511:158] - node _T_1336 = not(buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:38] - node _T_1337 = and(_T_1336, buf_dual[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:58] - node _T_1338 = not(buf_dualhi[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:80] - node _T_1339 = and(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 512:78] - node _T_1340 = and(_T_1339, buf_samedw[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:101] - node _T_1341 = or(_T_1335, _T_1340) @[el2_lsu_bus_buffer.scala 511:182] - node _T_1342 = and(_T_1326, _T_1341) @[el2_lsu_bus_buffer.scala 510:89] - node _T_1343 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 513:54] - node _T_1344 = and(_T_1343, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 513:70] - node _T_1345 = or(_T_1342, _T_1344) @[el2_lsu_bus_buffer.scala 512:126] - obuf_merge_en <= _T_1345 @[el2_lsu_bus_buffer.scala 509:26] - node _T_1346 = gt(buf_numvld_cmd_any, UInt<4>("h00")) @[el2_lsu_bus_buffer.scala 514:74] - node _T_1347 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 514:103] - node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 514:86] - node _T_1349 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 514:154] - node _T_1350 = tail(_T_1349, 1) @[el2_lsu_bus_buffer.scala 514:154] - node _T_1351 = mux(_T_1348, _T_1350, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 514:52] - node _T_1352 = mux(obuf_wr_en, UInt<1>("h00"), _T_1351) @[el2_lsu_bus_buffer.scala 514:31] - obuf_wr_timer_in <= _T_1352 @[el2_lsu_bus_buffer.scala 514:25] - node _T_1353 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 515:63] - node _T_1354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 515:88] - node _T_1355 = cat(_T_1354, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1356 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 515:135] - node _T_1357 = cat(UInt<4>("h00"), _T_1356) @[Cat.scala 29:58] - node _T_1358 = mux(_T_1353, _T_1355, _T_1357) @[el2_lsu_bus_buffer.scala 515:49] - node _T_1359 = bits(buf_addr[CmdPtr0], 2, 2) @[el2_lsu_bus_buffer.scala 515:168] - node _T_1360 = cat(buf_byteen[CmdPtr0], UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1361 = cat(UInt<4>("h00"), buf_byteen[CmdPtr0]) @[Cat.scala 29:58] - node _T_1362 = mux(_T_1359, _T_1360, _T_1361) @[el2_lsu_bus_buffer.scala 515:150] - node _T_1363 = mux(ibuf_buf_byp, _T_1358, _T_1362) @[el2_lsu_bus_buffer.scala 515:31] - obuf_byteen0_in <= _T_1363 @[el2_lsu_bus_buffer.scala 515:25] - node _T_1364 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 516:63] - node _T_1365 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 516:88] - node _T_1366 = cat(_T_1365, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1367 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 516:135] - node _T_1368 = cat(UInt<4>("h00"), _T_1367) @[Cat.scala 29:58] - node _T_1369 = mux(_T_1364, _T_1366, _T_1368) @[el2_lsu_bus_buffer.scala 516:49] - node _T_1370 = bits(buf_addr[CmdPtr1], 2, 2) @[el2_lsu_bus_buffer.scala 516:168] - node _T_1371 = cat(buf_byteen[CmdPtr1], UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1372 = cat(UInt<4>("h00"), buf_byteen[CmdPtr1]) @[Cat.scala 29:58] - node _T_1373 = mux(_T_1370, _T_1371, _T_1372) @[el2_lsu_bus_buffer.scala 516:150] - node _T_1374 = mux(ibuf_buf_byp, _T_1369, _T_1373) @[el2_lsu_bus_buffer.scala 516:31] - obuf_byteen1_in <= _T_1374 @[el2_lsu_bus_buffer.scala 516:25] - node _T_1375 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 517:63] - node _T_1376 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 517:87] - node _T_1377 = cat(_T_1376, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1378 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 517:135] - node _T_1379 = cat(UInt<32>("h00"), _T_1378) @[Cat.scala 29:58] - node _T_1380 = mux(_T_1375, _T_1377, _T_1379) @[el2_lsu_bus_buffer.scala 517:49] - node _T_1381 = bits(buf_addr[CmdPtr0], 2, 2) @[el2_lsu_bus_buffer.scala 517:168] - node _T_1382 = cat(buf_data[CmdPtr0], UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1383 = cat(UInt<32>("h00"), buf_data[CmdPtr0]) @[Cat.scala 29:58] - node _T_1384 = mux(_T_1381, _T_1382, _T_1383) @[el2_lsu_bus_buffer.scala 517:150] - node _T_1385 = mux(ibuf_buf_byp, _T_1380, _T_1384) @[el2_lsu_bus_buffer.scala 517:31] - obuf_data0_in <= _T_1385 @[el2_lsu_bus_buffer.scala 517:25] - node _T_1386 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 518:63] - node _T_1387 = bits(store_data_hi_r, 31, 0) @[el2_lsu_bus_buffer.scala 518:87] - node _T_1388 = cat(_T_1387, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1389 = bits(store_data_hi_r, 31, 0) @[el2_lsu_bus_buffer.scala 518:135] - node _T_1390 = cat(UInt<32>("h00"), _T_1389) @[Cat.scala 29:58] - node _T_1391 = mux(_T_1386, _T_1388, _T_1390) @[el2_lsu_bus_buffer.scala 518:49] - node _T_1392 = bits(buf_addr[CmdPtr1], 2, 2) @[el2_lsu_bus_buffer.scala 518:168] - node _T_1393 = cat(buf_data[CmdPtr1], UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1394 = cat(UInt<32>("h00"), buf_data[CmdPtr1]) @[Cat.scala 29:58] - node _T_1395 = mux(_T_1392, _T_1393, _T_1394) @[el2_lsu_bus_buffer.scala 518:150] - node _T_1396 = mux(ibuf_buf_byp, _T_1391, _T_1395) @[el2_lsu_bus_buffer.scala 518:31] - obuf_data1_in <= _T_1396 @[el2_lsu_bus_buffer.scala 518:25] - reg _T_1397 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 309:25] + buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:72] + node _T_1018 = and(_T_1016, _T_1017) @[el2_lsu_bus_buffer.scala 315:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 315:97] + node _T_1020 = and(_T_1018, _T_1019) @[el2_lsu_bus_buffer.scala 315:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:5] + node _T_1022 = and(_T_1020, _T_1021) @[el2_lsu_bus_buffer.scala 315:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:31] + node _T_1036 = and(_T_1022, _T_1035) @[el2_lsu_bus_buffer.scala 316:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:5] + node _T_1054 = and(_T_1036, _T_1053) @[el2_lsu_bus_buffer.scala 316:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 317:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 318:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 318:95] + node _T_1058 = and(_T_1056, _T_1057) @[el2_lsu_bus_buffer.scala 318:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 318:121] + node _T_1060 = tail(_T_1059, 1) @[el2_lsu_bus_buffer.scala 318:121] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 318:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[el2_lsu_bus_buffer.scala 318:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[el2_lsu_bus_buffer.scala 319:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:60] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_bus_buffer.scala 319:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:93] + node _T_1067 = and(_T_1065, _T_1066) @[el2_lsu_bus_buffer.scala 319:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 319:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[el2_lsu_bus_buffer.scala 319:123] + node _T_1086 = and(_T_1067, _T_1085) @[el2_lsu_bus_buffer.scala 319:101] + obuf_force_wr_en <= _T_1086 @[el2_lsu_bus_buffer.scala 319:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[el2_lsu_bus_buffer.scala 321:31] + node _T_1089 = eq(io.lsu_pkt_r.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 321:84] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[el2_lsu_bus_buffer.scala 321:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 324:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 326:22] + buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 328:24] + buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 336:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 336:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 336:52] + node _T_1094 = and(_T_1091, _T_1093) @[el2_lsu_bus_buffer.scala 336:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 337:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[el2_lsu_bus_buffer.scala 337:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1113 = bits(_T_1111, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1115 = bits(_T_1111, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1117 = bits(_T_1111, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1119 = bits(_T_1111, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:23] + node _T_1129 = and(_T_1108, _T_1128) @[el2_lsu_bus_buffer.scala 338:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 338:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:105] + node _T_1148 = and(_T_1129, _T_1147) @[el2_lsu_bus_buffer.scala 338:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1153 = bits(_T_1151, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1155 = bits(_T_1151, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1157 = bits(_T_1151, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1159 = bits(_T_1151, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1172 = bits(_T_1170, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1174 = bits(_T_1170, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1176 = bits(_T_1170, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1178 = bits(_T_1170, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[el2_lsu_bus_buffer.scala 339:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1189 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1191 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1193 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1195 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:150] + node _T_1205 = and(_T_1187, _T_1204) @[el2_lsu_bus_buffer.scala 339:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[el2_lsu_bus_buffer.scala 339:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1212 = bits(_T_1210, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1214 = bits(_T_1210, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1216 = bits(_T_1210, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1218 = bits(_T_1210, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[el2_lsu_bus_buffer.scala 339:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 339:269] + node _T_1229 = and(_T_1148, _T_1228) @[el2_lsu_bus_buffer.scala 338:164] + node _T_1230 = or(_T_1094, _T_1229) @[el2_lsu_bus_buffer.scala 336:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[el2_lsu_bus_buffer.scala 340:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[el2_lsu_bus_buffer.scala 340:60] + node _T_1234 = and(_T_1230, _T_1233) @[el2_lsu_bus_buffer.scala 340:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:77] + node _T_1236 = and(_T_1234, _T_1235) @[el2_lsu_bus_buffer.scala 340:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:93] + node _T_1238 = and(_T_1236, _T_1237) @[el2_lsu_bus_buffer.scala 340:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:118] + node _T_1240 = and(_T_1238, _T_1239) @[el2_lsu_bus_buffer.scala 340:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 340:142] + obuf_wr_en <= _T_1241 @[el2_lsu_bus_buffer.scala 336:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1242 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 342:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[el2_lsu_bus_buffer.scala 342:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 342:65] + node _T_1245 = and(_T_1243, _T_1244) @[el2_lsu_bus_buffer.scala 342:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 342:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 342:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1248 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1250 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1252 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1254 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1258 = mux(_T_1253, _T_1254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1259 = or(_T_1255, _T_1256) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1257) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] + wire _T_1262 : UInt<1> @[Mux.scala 27:72] + _T_1262 <= _T_1261 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.store, _T_1262) @[el2_lsu_bus_buffer.scala 343:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1274 = mux(_T_1269, _T_1270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1275 = or(_T_1271, _T_1272) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1273) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] + wire _T_1278 : UInt<1> @[Mux.scala 27:72] + _T_1278 <= _T_1277 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[el2_lsu_bus_buffer.scala 344:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1286 = mux(_T_1282, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1287 = or(_T_1283, _T_1284) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1285) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] + wire _T_1290 : UInt<32> @[Mux.scala 27:72] + _T_1290 <= _T_1289 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[el2_lsu_bus_buffer.scala 345:25] + wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 346:20] + buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + node _T_1291 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1299 = mux(_T_1295, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1300 = or(_T_1296, _T_1297) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1298) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] + wire _T_1303 : UInt<2> @[Mux.scala 27:72] + _T_1303 <= _T_1302 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[el2_lsu_bus_buffer.scala 348:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 351:25] + wire Cmdptr1 : UInt<2> + Cmdptr1 <= UInt<1>("h00") + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) @[el2_lsu_bus_buffer.scala 354:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1304 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 357:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 357:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 357:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[el2_lsu_bus_buffer.scala 357:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1307 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 360:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 360:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 360:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[el2_lsu_bus_buffer.scala 360:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:98] + node _T_1315 = and(_T_1312, _T_1314) @[el2_lsu_bus_buffer.scala 361:96] + node _T_1316 = or(_T_1311, _T_1315) @[el2_lsu_bus_buffer.scala 361:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 361:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:147] + node _T_1319 = orr(_T_1318) @[el2_lsu_bus_buffer.scala 361:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:134] + node _T_1321 = and(_T_1317, _T_1320) @[el2_lsu_bus_buffer.scala 361:132] + node _T_1322 = or(_T_1316, _T_1321) @[el2_lsu_bus_buffer.scala 361:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[el2_lsu_bus_buffer.scala 361:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[el2_lsu_bus_buffer.scala 369:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 369:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 369:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[el2_lsu_bus_buffer.scala 369:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:81] + node _T_1330 = and(_T_1326, _T_1329) @[el2_lsu_bus_buffer.scala 369:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[el2_lsu_bus_buffer.scala 370:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:37] + node _T_1334 = and(_T_1332, _T_1333) @[el2_lsu_bus_buffer.scala 370:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[el2_lsu_bus_buffer.scala 369:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 372:46] + node _T_1336 = or(bus_cmd_sent, _T_1335) @[el2_lsu_bus_buffer.scala 372:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 372:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1337 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 375:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 375:52] + node _T_1339 = eq(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 375:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 375:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:80] + node _T_1342 = and(_T_1340, _T_1341) @[el2_lsu_bus_buffer.scala 375:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:99] + node _T_1344 = and(_T_1342, _T_1343) @[el2_lsu_bus_buffer.scala 375:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:113] + node _T_1346 = and(_T_1344, _T_1345) @[el2_lsu_bus_buffer.scala 375:111] + node _T_1347 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:130] + node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 375:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:20] + node _T_1350 = and(obuf_valid, _T_1349) @[el2_lsu_bus_buffer.scala 376:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 376:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[el2_lsu_bus_buffer.scala 376:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[el2_lsu_bus_buffer.scala 376:53] + node _T_1355 = or(_T_1350, _T_1354) @[el2_lsu_bus_buffer.scala 376:34] + node _T_1356 = and(_T_1348, _T_1355) @[el2_lsu_bus_buffer.scala 375:165] + obuf_nosend_in <= _T_1356 @[el2_lsu_bus_buffer.scala 375:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 377:60] + node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[el2_lsu_bus_buffer.scala 377:46] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1364, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = or(_T_1365, _T_1366) @[Mux.scala 27:72] + node _T_1370 = or(_T_1369, _T_1367) @[Mux.scala 27:72] + node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] + wire _T_1372 : UInt<32> @[Mux.scala 27:72] + _T_1372 <= _T_1371 @[Mux.scala 27:72] + node _T_1373 = bits(_T_1372, 2, 2) @[el2_lsu_bus_buffer.scala 378:36] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_lsu_bus_buffer.scala 378:46] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = or(_T_1379, _T_1380) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + wire _T_1386 : UInt<4> @[Mux.scala 27:72] + _T_1386 <= _T_1385 @[Mux.scala 27:72] + node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = or(_T_1392, _T_1393) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1394) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1395) @[Mux.scala 27:72] + wire _T_1399 : UInt<4> @[Mux.scala 27:72] + _T_1399 <= _T_1398 @[Mux.scala 27:72] + node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[el2_lsu_bus_buffer.scala 378:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[el2_lsu_bus_buffer.scala 377:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 379:60] + node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[el2_lsu_bus_buffer.scala 379:46] + node _T_1406 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1407 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1408 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1409 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1413 = mux(_T_1409, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1414 = or(_T_1410, _T_1411) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1412) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] + wire _T_1417 : UInt<32> @[Mux.scala 27:72] + _T_1417 <= _T_1416 @[Mux.scala 27:72] + node _T_1418 = bits(_T_1417, 2, 2) @[el2_lsu_bus_buffer.scala 380:36] + node _T_1419 = bits(_T_1418, 0, 0) @[el2_lsu_bus_buffer.scala 380:46] + node _T_1420 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1421 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1422 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1423 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = or(_T_1424, _T_1425) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + wire _T_1431 : UInt<4> @[Mux.scala 27:72] + _T_1431 <= _T_1430 @[Mux.scala 27:72] + node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1433 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1434 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1435 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1436 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = or(_T_1437, _T_1438) @[Mux.scala 27:72] + node _T_1442 = or(_T_1441, _T_1439) @[Mux.scala 27:72] + node _T_1443 = or(_T_1442, _T_1440) @[Mux.scala 27:72] + wire _T_1444 : UInt<4> @[Mux.scala 27:72] + _T_1444 <= _T_1443 @[Mux.scala 27:72] + node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[el2_lsu_bus_buffer.scala 380:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[el2_lsu_bus_buffer.scala 379:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 382:58] + node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[el2_lsu_bus_buffer.scala 382:44] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1454, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = or(_T_1455, _T_1456) @[Mux.scala 27:72] + node _T_1460 = or(_T_1459, _T_1457) @[Mux.scala 27:72] + node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] + wire _T_1462 : UInt<32> @[Mux.scala 27:72] + _T_1462 <= _T_1461 @[Mux.scala 27:72] + node _T_1463 = bits(_T_1462, 2, 2) @[el2_lsu_bus_buffer.scala 383:36] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_lsu_bus_buffer.scala 383:46] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1468, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1474 = or(_T_1473, _T_1471) @[Mux.scala 27:72] + node _T_1475 = or(_T_1474, _T_1472) @[Mux.scala 27:72] + wire _T_1476 : UInt<32> @[Mux.scala 27:72] + _T_1476 <= _T_1475 @[Mux.scala 27:72] + node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1481, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = or(_T_1482, _T_1483) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1484) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1485) @[Mux.scala 27:72] + wire _T_1489 : UInt<32> @[Mux.scala 27:72] + _T_1489 <= _T_1488 @[Mux.scala 27:72] + node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[el2_lsu_bus_buffer.scala 383:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[el2_lsu_bus_buffer.scala 382:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 384:58] + node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[el2_lsu_bus_buffer.scala 384:44] + node _T_1496 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1497 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1498 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1499 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1499, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = or(_T_1500, _T_1501) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1502) @[Mux.scala 27:72] + node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] + wire _T_1507 : UInt<32> @[Mux.scala 27:72] + _T_1507 <= _T_1506 @[Mux.scala 27:72] + node _T_1508 = bits(_T_1507, 2, 2) @[el2_lsu_bus_buffer.scala 385:36] + node _T_1509 = bits(_T_1508, 0, 0) @[el2_lsu_bus_buffer.scala 385:46] + node _T_1510 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1511 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1512 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1513 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1513, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = or(_T_1514, _T_1515) @[Mux.scala 27:72] + node _T_1519 = or(_T_1518, _T_1516) @[Mux.scala 27:72] + node _T_1520 = or(_T_1519, _T_1517) @[Mux.scala 27:72] + wire _T_1521 : UInt<32> @[Mux.scala 27:72] + _T_1521 <= _T_1520 @[Mux.scala 27:72] + node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1523 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1524 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1525 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1526 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1526, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = or(_T_1527, _T_1528) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1529) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1530) @[Mux.scala 27:72] + wire _T_1534 : UInt<32> @[Mux.scala 27:72] + _T_1534 <= _T_1533 @[Mux.scala 27:72] + node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[el2_lsu_bus_buffer.scala 385:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[el2_lsu_bus_buffer.scala 384:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1540 = or(_T_1537, _T_1539) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1544 = or(_T_1541, _T_1543) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1548 = or(_T_1545, _T_1547) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1552 = or(_T_1549, _T_1551) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1556 = or(_T_1553, _T_1555) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1560 = or(_T_1557, _T_1559) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1564 = or(_T_1561, _T_1563) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1568 = or(_T_1565, _T_1567) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1552) @[Cat.scala 29:58] + node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] + node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1594) @[Cat.scala 29:58] + node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] + node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 389:24] + buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + node _T_1621 = neq(CmdPtr0, Cmdptr1) @[el2_lsu_bus_buffer.scala 391:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[el2_lsu_bus_buffer.scala 391:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[el2_lsu_bus_buffer.scala 391:59] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1631 = mux(_T_1627, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1632 = or(_T_1628, _T_1629) @[Mux.scala 27:72] + node _T_1633 = or(_T_1632, _T_1630) @[Mux.scala 27:72] + node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] + wire _T_1635 : UInt<3> @[Mux.scala 27:72] + _T_1635 <= _T_1634 @[Mux.scala 27:72] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:107] + node _T_1637 = and(_T_1623, _T_1636) @[el2_lsu_bus_buffer.scala 391:75] + node _T_1638 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1639 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1640 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1641 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1645 = mux(_T_1641, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1646 = or(_T_1642, _T_1643) @[Mux.scala 27:72] + node _T_1647 = or(_T_1646, _T_1644) @[Mux.scala 27:72] + node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] + wire _T_1649 : UInt<3> @[Mux.scala 27:72] + _T_1649 <= _T_1648 @[Mux.scala 27:72] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:150] + node _T_1651 = and(_T_1637, _T_1650) @[el2_lsu_bus_buffer.scala 391:118] + node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1656 = bits(_T_1654, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1658 = bits(_T_1654, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1660 = bits(_T_1654, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1662 = bits(_T_1654, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = or(_T_1663, _T_1664) @[Mux.scala 27:72] + node _T_1668 = or(_T_1667, _T_1665) @[Mux.scala 27:72] + node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] + wire _T_1670 : UInt<1> @[Mux.scala 27:72] + _T_1670 <= _T_1669 @[Mux.scala 27:72] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:5] + node _T_1672 = and(_T_1651, _T_1671) @[el2_lsu_bus_buffer.scala 391:161] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1684 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1685 = or(_T_1681, _T_1682) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1683) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] + wire _T_1688 : UInt<1> @[Mux.scala 27:72] + _T_1688 <= _T_1687 @[Mux.scala 27:72] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:87] + node _T_1690 = and(_T_1672, _T_1689) @[el2_lsu_bus_buffer.scala 392:85] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1692 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1694 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1696 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1698 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1702 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1703 = or(_T_1699, _T_1700) @[Mux.scala 27:72] + node _T_1704 = or(_T_1703, _T_1701) @[Mux.scala 27:72] + node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] + wire _T_1706 : UInt<1> @[Mux.scala 27:72] + _T_1706 <= _T_1705 @[Mux.scala 27:72] + node _T_1707 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1708 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1709 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1710 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1711 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1712 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1713 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1714 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = or(_T_1715, _T_1716) @[Mux.scala 27:72] + node _T_1720 = or(_T_1719, _T_1717) @[Mux.scala 27:72] + node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] + wire _T_1722 : UInt<1> @[Mux.scala 27:72] + _T_1722 <= _T_1721 @[Mux.scala 27:72] + node _T_1723 = and(_T_1706, _T_1722) @[el2_lsu_bus_buffer.scala 393:36] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1727, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = or(_T_1728, _T_1729) @[Mux.scala 27:72] + node _T_1733 = or(_T_1732, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + wire _T_1735 : UInt<32> @[Mux.scala 27:72] + _T_1735 <= _T_1734 @[Mux.scala 27:72] + node _T_1736 = bits(_T_1735, 31, 3) @[el2_lsu_bus_buffer.scala 394:35] + node _T_1737 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1738 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1739 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1740 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1740, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1746 = or(_T_1745, _T_1743) @[Mux.scala 27:72] + node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] + wire _T_1748 : UInt<32> @[Mux.scala 27:72] + _T_1748 <= _T_1747 @[Mux.scala 27:72] + node _T_1749 = bits(_T_1748, 31, 3) @[el2_lsu_bus_buffer.scala 394:71] + node _T_1750 = eq(_T_1736, _T_1749) @[el2_lsu_bus_buffer.scala 394:41] + node _T_1751 = and(_T_1723, _T_1750) @[el2_lsu_bus_buffer.scala 393:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:81] + node _T_1753 = and(_T_1751, _T_1752) @[el2_lsu_bus_buffer.scala 394:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:107] + node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 394:105] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1757 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1759 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1761 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1763 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1762, _T_1763, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = or(_T_1764, _T_1765) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1766) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] + wire _T_1771 : UInt<1> @[Mux.scala 27:72] + _T_1771 <= _T_1770 @[Mux.scala 27:72] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:8] + node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] + node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1777 = bits(_T_1775, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1779 = bits(_T_1775, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1781 = bits(_T_1775, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1783 = bits(_T_1775, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = or(_T_1784, _T_1785) @[Mux.scala 27:72] + node _T_1789 = or(_T_1788, _T_1786) @[Mux.scala 27:72] + node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] + wire _T_1791 : UInt<1> @[Mux.scala 27:72] + _T_1791 <= _T_1790 @[Mux.scala 27:72] + node _T_1792 = and(_T_1772, _T_1791) @[el2_lsu_bus_buffer.scala 395:38] + node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1797 = bits(_T_1795, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1799 = bits(_T_1795, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1801 = bits(_T_1795, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1803 = bits(_T_1795, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1804, _T_1805) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1806) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] + wire _T_1811 : UInt<1> @[Mux.scala 27:72] + _T_1811 <= _T_1810 @[Mux.scala 27:72] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:109] + node _T_1813 = and(_T_1792, _T_1812) @[el2_lsu_bus_buffer.scala 395:107] + node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1818 = bits(_T_1816, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1820 = bits(_T_1816, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1822 = bits(_T_1816, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1824 = bits(_T_1816, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = or(_T_1825, _T_1826) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1827) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] + wire _T_1832 : UInt<1> @[Mux.scala 27:72] + _T_1832 <= _T_1831 @[Mux.scala 27:72] + node _T_1833 = and(_T_1813, _T_1832) @[el2_lsu_bus_buffer.scala 395:179] + node _T_1834 = or(_T_1755, _T_1833) @[el2_lsu_bus_buffer.scala 394:128] + node _T_1835 = and(_T_1690, _T_1834) @[el2_lsu_bus_buffer.scala 392:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 396:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 396:35] + node _T_1838 = or(_T_1835, _T_1837) @[el2_lsu_bus_buffer.scala 395:253] + obuf_merge_en <= _T_1838 @[el2_lsu_bus_buffer.scala 391:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 398:55] + obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 398:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 399:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 399:93] + node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 399:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 399:54] + _T_1842 <= _T_1841 @[el2_lsu_bus_buffer.scala 399:54] + obuf_valid <= _T_1842 @[el2_lsu_bus_buffer.scala 399:14] + reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1397 <= obuf_addr_in @[Reg.scala 28:23] + _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_addr <= _T_1397 @[el2_lsu_bus_buffer.scala 520:25] - reg _T_1398 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_nosend <= _T_1843 @[el2_lsu_bus_buffer.scala 400:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 401:54] + _T_1844 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 401:54] + obuf_cmd_done <= _T_1844 @[el2_lsu_bus_buffer.scala 401:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 402:55] + _T_1845 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 402:55] + obuf_data_done <= _T_1845 @[el2_lsu_bus_buffer.scala 402:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 403:56] + _T_1846 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 403:56] + obuf_rdrsp_pend <= _T_1846 @[el2_lsu_bus_buffer.scala 403:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 404:55] + _T_1847 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 404:55] + obuf_rdrsp_tag <= _T_1847 @[el2_lsu_bus_buffer.scala 404:18] + reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1398 <= obuf_data_in @[Reg.scala 28:23] + _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_data <= _T_1398 @[el2_lsu_bus_buffer.scala 521:25] - reg _T_1399 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 523:35] - _T_1399 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 523:35] - obuf_rdrsp_pend <= _T_1399 @[el2_lsu_bus_buffer.scala 523:25] - reg _T_1400 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 524:35] - _T_1400 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 524:35] - obuf_rdrsp_tag <= _T_1400 @[el2_lsu_bus_buffer.scala 524:25] - reg _T_1401 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 525:35] - _T_1401 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 525:35] - obuf_cmd_done <= _T_1401 @[el2_lsu_bus_buffer.scala 525:25] - reg _T_1402 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 526:35] - _T_1402 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 526:35] - obuf_data_done <= _T_1402 @[el2_lsu_bus_buffer.scala 526:25] - reg _T_1403 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 527:35] - _T_1403 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 527:35] - obuf_wr_timer <= _T_1403 @[el2_lsu_bus_buffer.scala 527:25] - reg _T_1404 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 528:35] - _T_1404 <= obuf_wr_en @[el2_lsu_bus_buffer.scala 528:35] - obuf_wr_enQ <= _T_1404 @[el2_lsu_bus_buffer.scala 528:25] - node _T_1405 = bits(obuf_wr_en, 0, 0) @[el2_lsu_bus_buffer.scala 531:50] - node _T_1406 = mux(_T_1405, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 531:32] - node _T_1407 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 531:72] - node _T_1408 = and(_T_1406, _T_1407) @[el2_lsu_bus_buffer.scala 531:70] - reg _T_1409 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 531:28] - _T_1409 <= _T_1408 @[el2_lsu_bus_buffer.scala 531:28] - obuf_valid <= _T_1409 @[el2_lsu_bus_buffer.scala 531:18] - reg _T_1410 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_tag0 <= _T_1848 @[el2_lsu_bus_buffer.scala 405:13] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1410 <= obuf_nosend_in @[Reg.scala 28:23] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_nosend <= _T_1410 @[el2_lsu_bus_buffer.scala 532:25] - reg _T_1411 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1411 <= obuf_write_in @[Reg.scala 28:23] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_write <= _T_1411 @[el2_lsu_bus_buffer.scala 535:25] - reg _T_1412 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1849 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1412 <= obuf_sideeffect_in @[Reg.scala 28:23] + _T_1849 <= obuf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sideeffect <= _T_1412 @[el2_lsu_bus_buffer.scala 536:25] - reg _T_1413 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_write <= _T_1849 @[el2_lsu_bus_buffer.scala 408:14] + reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1413 <= obuf_sz_in @[Reg.scala 28:23] + _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sz <= _T_1413 @[el2_lsu_bus_buffer.scala 537:25] - reg _T_1414 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_sideeffect <= _T_1850 @[el2_lsu_bus_buffer.scala 409:19] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1414 <= obuf_byteen_in @[Reg.scala 28:23] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_byteen <= _T_1414 @[el2_lsu_bus_buffer.scala 538:25] - reg _T_1415 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1851 <= obuf_addr_in @[el2_lib.scala 514:16] + obuf_addr <= _T_1851 @[el2_lsu_bus_buffer.scala 411:13] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1415 <= obuf_merge_in @[Reg.scala 28:23] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_merge <= _T_1415 @[el2_lsu_bus_buffer.scala 539:25] - reg _T_1416 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when obuf_wr_en : @[Reg.scala 28:19] - _T_1416 <= obuf_tag0_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - obuf_tag0 <= _T_1416 @[el2_lsu_bus_buffer.scala 540:25] - reg _T_1417 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when obuf_wr_en : @[Reg.scala 28:19] - _T_1417 <= obuf_tag1_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - obuf_tag1 <= _T_1417 @[el2_lsu_bus_buffer.scala 541:25] - node _T_1418 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1419 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1420 = and(ibuf_valid, _T_1419) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1421 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1422 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1423 = and(io.ldst_dual_r, _T_1422) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1424 = or(_T_1421, _T_1423) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1425 = and(io.lsu_busreq_r, _T_1424) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1426 = or(_T_1420, _T_1425) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1428 = and(_T_1418, _T_1427) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1429 = bits(_T_1428, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1430 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1431 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1432 = and(ibuf_valid, _T_1431) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1433 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1434 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1435 = and(io.ldst_dual_r, _T_1434) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1436 = or(_T_1433, _T_1435) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1437 = and(io.lsu_busreq_r, _T_1436) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1438 = or(_T_1432, _T_1437) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1440 = and(_T_1430, _T_1439) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1441 = bits(_T_1440, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1442 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1443 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1444 = and(ibuf_valid, _T_1443) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1445 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1446 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1447 = and(io.ldst_dual_r, _T_1446) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1448 = or(_T_1445, _T_1447) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1449 = and(io.lsu_busreq_r, _T_1448) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1450 = or(_T_1444, _T_1449) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1451 = eq(_T_1450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1452 = and(_T_1442, _T_1451) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1453 = bits(_T_1452, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1454 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1455 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1456 = and(ibuf_valid, _T_1455) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1457 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1458 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1459 = and(io.ldst_dual_r, _T_1458) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1460 = or(_T_1457, _T_1459) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1461 = and(io.lsu_busreq_r, _T_1460) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1462 = or(_T_1456, _T_1461) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1464 = and(_T_1454, _T_1463) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1465 = bits(_T_1464, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1466 = mux(_T_1465, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1467 = mux(_T_1453, UInt<2>("h02"), _T_1466) @[Mux.scala 98:16] - node _T_1468 = mux(_T_1441, UInt<1>("h01"), _T_1467) @[Mux.scala 98:16] - node _T_1469 = mux(_T_1429, UInt<1>("h00"), _T_1468) @[Mux.scala 98:16] - WrPtr0_m <= _T_1469 @[el2_lsu_bus_buffer.scala 548:13] - node _T_1470 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1471 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1472 = and(ibuf_valid, _T_1471) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1473 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1474 = and(io.lsu_busreq_m, _T_1473) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1475 = or(_T_1472, _T_1474) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1476 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1477 = and(io.lsu_busreq_r, _T_1476) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1478 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1479 = and(io.ldst_dual_r, _T_1478) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1480 = or(_T_1477, _T_1479) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1481 = or(_T_1475, _T_1480) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1483 = and(_T_1470, _T_1482) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1484 = bits(_T_1483, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1485 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1486 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1487 = and(ibuf_valid, _T_1486) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1488 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1489 = and(io.lsu_busreq_m, _T_1488) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1490 = or(_T_1487, _T_1489) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1491 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1492 = and(io.lsu_busreq_r, _T_1491) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1493 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1494 = and(io.ldst_dual_r, _T_1493) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1495 = or(_T_1492, _T_1494) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1496 = or(_T_1490, _T_1495) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1497 = eq(_T_1496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1498 = and(_T_1485, _T_1497) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1499 = bits(_T_1498, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1500 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1501 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1502 = and(ibuf_valid, _T_1501) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1503 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1504 = and(io.lsu_busreq_m, _T_1503) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1505 = or(_T_1502, _T_1504) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1506 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1507 = and(io.lsu_busreq_r, _T_1506) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1508 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1509 = and(io.ldst_dual_r, _T_1508) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1510 = or(_T_1507, _T_1509) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1511 = or(_T_1505, _T_1510) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1513 = and(_T_1500, _T_1512) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1514 = bits(_T_1513, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1515 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1516 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1517 = and(ibuf_valid, _T_1516) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1518 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1519 = and(io.lsu_busreq_m, _T_1518) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1520 = or(_T_1517, _T_1519) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1521 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1522 = and(io.lsu_busreq_r, _T_1521) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1523 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1524 = and(io.ldst_dual_r, _T_1523) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1525 = or(_T_1522, _T_1524) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1526 = or(_T_1520, _T_1525) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1527 = eq(_T_1526, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1528 = and(_T_1515, _T_1527) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1529 = bits(_T_1528, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1530 = mux(_T_1529, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1531 = mux(_T_1514, UInt<2>("h02"), _T_1530) @[Mux.scala 98:16] - node _T_1532 = mux(_T_1499, UInt<1>("h01"), _T_1531) @[Mux.scala 98:16] - node _T_1533 = mux(_T_1484, UInt<1>("h00"), _T_1532) @[Mux.scala 98:16] - WrPtr1_m <= _T_1533 @[el2_lsu_bus_buffer.scala 552:26] - node _T_1534 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1535 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1536 = cat(_T_1535, _T_1534) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1537 = orr(_T_1536) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1538 = not(_T_1537) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1539 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1540 = and(_T_1538, _T_1539) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1541 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1542 = and(_T_1540, _T_1541) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1542 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1543 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1544 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1545 = cat(_T_1544, _T_1543) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1546 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1547 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1548 = cat(_T_1547, _T_1546) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1549 = not(_T_1548) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1550 = and(_T_1545, _T_1549) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1551 = orr(_T_1550) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1552 = not(_T_1551) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1553 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1554 = and(_T_1552, _T_1553) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1555 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1556 = and(_T_1554, _T_1555) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1557 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1558 = and(_T_1556, _T_1557) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1558 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1559 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1560 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1561 = cat(_T_1560, _T_1559) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1562 = orr(_T_1561) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1563 = not(_T_1562) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1564 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1565 = and(_T_1563, _T_1564) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1565 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1566 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1567 = and(_T_1566, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1568 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1569 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1570 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1571 = and(_T_1569, _T_1570) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1572 = or(_T_1568, _T_1571) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1573 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1574 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1575 = and(_T_1573, _T_1574) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1576 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1577 = and(_T_1575, _T_1576) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1578 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1579 = and(_T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1580 = or(_T_1572, _T_1579) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1581 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1582 = and(_T_1581, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1583 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1584 = and(_T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1585 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1586 = and(_T_1584, _T_1585) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1587 = or(_T_1580, _T_1586) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1588 = and(_T_1567, _T_1587) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1589 = or(_T_1588, buf_age[0][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][0] <= _T_1589 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1590 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1591 = and(_T_1590, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1592 = not(_T_1591) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1593 = and(buf_ageQ[0][0], _T_1592) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][0] <= _T_1593 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1594 = eq(UInt<2>("h00"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1595 = not(buf_age[0][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1596 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1597 = and(_T_1595, _T_1596) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1598 = mux(_T_1594, UInt<1>("h00"), _T_1597) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][0] <= _T_1598 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1599 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1600 = and(_T_1599, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1601 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1602 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1603 = or(_T_1601, _T_1602) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1604 = not(_T_1603) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1605 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1606 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1607 = and(_T_1605, _T_1606) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1608 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1609 = and(_T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1610 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1611 = and(_T_1609, _T_1610) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1612 = or(_T_1604, _T_1611) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1613 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1614 = and(_T_1613, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1615 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1616 = and(_T_1614, _T_1615) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1617 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1618 = and(_T_1616, _T_1617) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1619 = or(_T_1612, _T_1618) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1620 = and(_T_1600, _T_1619) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][0] <= _T_1620 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1621 = or(buf_rspage_set[0][0], buf_rspage[0][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][0] <= _T_1621 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1622 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1623 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1624 = or(_T_1622, _T_1623) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1625 = not(_T_1624) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1626 = and(buf_rspageQ[0][0], _T_1625) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][0] <= _T_1626 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1627 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1628 = and(buf_rspageQ[0][0], _T_1627) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][0] <= _T_1628 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1629 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1630 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1631 = cat(_T_1630, _T_1629) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1632 = orr(_T_1631) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1633 = not(_T_1632) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1634 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1635 = and(_T_1633, _T_1634) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1636 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1637 = and(_T_1635, _T_1636) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1637 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1638 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1639 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1640 = cat(_T_1639, _T_1638) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1641 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1642 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1643 = cat(_T_1642, _T_1641) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1644 = not(_T_1643) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1645 = and(_T_1640, _T_1644) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1646 = orr(_T_1645) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1647 = not(_T_1646) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1648 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1649 = and(_T_1647, _T_1648) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1650 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1651 = and(_T_1649, _T_1650) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1652 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1653 = and(_T_1651, _T_1652) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1653 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1654 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1655 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1656 = cat(_T_1655, _T_1654) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1657 = orr(_T_1656) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1658 = not(_T_1657) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1659 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1660 = and(_T_1658, _T_1659) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1660 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1661 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1662 = and(_T_1661, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1663 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1664 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1665 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1666 = and(_T_1664, _T_1665) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1667 = or(_T_1663, _T_1666) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1668 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1669 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1670 = and(_T_1668, _T_1669) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1671 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1672 = and(_T_1670, _T_1671) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1673 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1674 = and(_T_1672, _T_1673) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1675 = or(_T_1667, _T_1674) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1676 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1677 = and(_T_1676, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1678 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1679 = and(_T_1677, _T_1678) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1680 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1681 = and(_T_1679, _T_1680) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1682 = or(_T_1675, _T_1681) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1683 = and(_T_1662, _T_1682) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1684 = or(_T_1683, buf_age[0][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][1] <= _T_1684 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1685 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1686 = and(_T_1685, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1687 = not(_T_1686) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1688 = and(buf_ageQ[0][1], _T_1687) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][1] <= _T_1688 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1689 = eq(UInt<2>("h00"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1690 = not(buf_age[0][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1692 = and(_T_1690, _T_1691) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1693 = mux(_T_1689, UInt<1>("h00"), _T_1692) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][1] <= _T_1693 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1694 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1695 = and(_T_1694, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1696 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1697 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1698 = or(_T_1696, _T_1697) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1699 = not(_T_1698) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1700 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1701 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1702 = and(_T_1700, _T_1701) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1703 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1704 = and(_T_1702, _T_1703) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1705 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1706 = and(_T_1704, _T_1705) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1707 = or(_T_1699, _T_1706) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1708 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1709 = and(_T_1708, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1710 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1711 = and(_T_1709, _T_1710) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1712 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1713 = and(_T_1711, _T_1712) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1714 = or(_T_1707, _T_1713) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1715 = and(_T_1695, _T_1714) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][1] <= _T_1715 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1716 = or(buf_rspage_set[0][1], buf_rspage[0][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][1] <= _T_1716 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1717 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1718 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1719 = or(_T_1717, _T_1718) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1720 = not(_T_1719) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1721 = and(buf_rspageQ[0][1], _T_1720) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][1] <= _T_1721 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1722 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1723 = and(buf_rspageQ[0][1], _T_1722) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][1] <= _T_1723 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1724 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1725 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1726 = cat(_T_1725, _T_1724) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1727 = orr(_T_1726) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1728 = not(_T_1727) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1729 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1730 = and(_T_1728, _T_1729) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1731 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1732 = and(_T_1730, _T_1731) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1732 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1733 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1734 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1735 = cat(_T_1734, _T_1733) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1736 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1737 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1738 = cat(_T_1737, _T_1736) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1739 = not(_T_1738) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1740 = and(_T_1735, _T_1739) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1741 = orr(_T_1740) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1742 = not(_T_1741) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1743 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1744 = and(_T_1742, _T_1743) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1745 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1746 = and(_T_1744, _T_1745) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1747 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1748 = and(_T_1746, _T_1747) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1748 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1749 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1750 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1751 = cat(_T_1750, _T_1749) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1752 = orr(_T_1751) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1753 = not(_T_1752) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1754 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1755 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1756 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1757 = and(_T_1756, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1758 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1759 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1760 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1761 = and(_T_1759, _T_1760) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1762 = or(_T_1758, _T_1761) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1763 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1764 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1765 = and(_T_1763, _T_1764) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1766 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1767 = and(_T_1765, _T_1766) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1768 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1769 = and(_T_1767, _T_1768) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1770 = or(_T_1762, _T_1769) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1771 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1772 = and(_T_1771, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1773 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1774 = and(_T_1772, _T_1773) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1775 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1776 = and(_T_1774, _T_1775) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1777 = or(_T_1770, _T_1776) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1778 = and(_T_1757, _T_1777) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1779 = or(_T_1778, buf_age[0][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][2] <= _T_1779 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1780 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1781 = and(_T_1780, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1782 = not(_T_1781) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1783 = and(buf_ageQ[0][2], _T_1782) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][2] <= _T_1783 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1784 = eq(UInt<2>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1785 = not(buf_age[0][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1786 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1787 = and(_T_1785, _T_1786) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1788 = mux(_T_1784, UInt<1>("h00"), _T_1787) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][2] <= _T_1788 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1789 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1790 = and(_T_1789, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1791 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1792 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1793 = or(_T_1791, _T_1792) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1794 = not(_T_1793) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1796 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1797 = and(_T_1795, _T_1796) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1798 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1799 = and(_T_1797, _T_1798) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1800 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1801 = and(_T_1799, _T_1800) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1802 = or(_T_1794, _T_1801) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1803 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1804 = and(_T_1803, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1805 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1806 = and(_T_1804, _T_1805) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1807 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1808 = and(_T_1806, _T_1807) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1809 = or(_T_1802, _T_1808) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1810 = and(_T_1790, _T_1809) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][2] <= _T_1810 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1811 = or(buf_rspage_set[0][2], buf_rspage[0][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][2] <= _T_1811 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1812 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1813 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1814 = or(_T_1812, _T_1813) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1815 = not(_T_1814) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1816 = and(buf_rspageQ[0][2], _T_1815) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][2] <= _T_1816 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1817 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1818 = and(buf_rspageQ[0][2], _T_1817) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][2] <= _T_1818 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1819 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1820 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1821 = cat(_T_1820, _T_1819) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1822 = orr(_T_1821) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1823 = not(_T_1822) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1824 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1825 = and(_T_1823, _T_1824) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1826 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1827 = and(_T_1825, _T_1826) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1827 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1828 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1829 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1830 = cat(_T_1829, _T_1828) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1831 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1832 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1833 = cat(_T_1832, _T_1831) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1834 = not(_T_1833) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1835 = and(_T_1830, _T_1834) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1836 = orr(_T_1835) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1837 = not(_T_1836) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1838 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1839 = and(_T_1837, _T_1838) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1840 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1842 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1843 = and(_T_1841, _T_1842) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1843 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1844 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1845 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1846 = cat(_T_1845, _T_1844) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1847 = orr(_T_1846) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1848 = not(_T_1847) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1849 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1850 = and(_T_1848, _T_1849) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1850 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1851 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1852 = and(_T_1851, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1853 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1854 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1855 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1856 = and(_T_1854, _T_1855) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1857 = or(_T_1853, _T_1856) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1858 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1859 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1860 = and(_T_1858, _T_1859) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1861 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1862 = and(_T_1860, _T_1861) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1863 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1864 = and(_T_1862, _T_1863) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1865 = or(_T_1857, _T_1864) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1866 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1867 = and(_T_1866, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1868 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1869 = and(_T_1867, _T_1868) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1870 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1871 = and(_T_1869, _T_1870) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1872 = or(_T_1865, _T_1871) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1873 = and(_T_1852, _T_1872) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1874 = or(_T_1873, buf_age[0][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][3] <= _T_1874 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1875 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1876 = and(_T_1875, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1877 = not(_T_1876) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1878 = and(buf_ageQ[0][3], _T_1877) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][3] <= _T_1878 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1879 = eq(UInt<2>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1880 = not(buf_age[0][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1881 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1882 = and(_T_1880, _T_1881) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1883 = mux(_T_1879, UInt<1>("h00"), _T_1882) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][3] <= _T_1883 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1884 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1885 = and(_T_1884, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1887 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1888 = or(_T_1886, _T_1887) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1889 = not(_T_1888) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1890 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1891 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1892 = and(_T_1890, _T_1891) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1893 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1894 = and(_T_1892, _T_1893) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1895 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1896 = and(_T_1894, _T_1895) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1897 = or(_T_1889, _T_1896) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1898 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1899 = and(_T_1898, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1900 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1901 = and(_T_1899, _T_1900) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1902 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1903 = and(_T_1901, _T_1902) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1904 = or(_T_1897, _T_1903) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1905 = and(_T_1885, _T_1904) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][3] <= _T_1905 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1906 = or(buf_rspage_set[0][3], buf_rspage[0][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][3] <= _T_1906 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1907 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1908 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1909 = or(_T_1907, _T_1908) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1910 = not(_T_1909) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1911 = and(buf_rspageQ[0][3], _T_1910) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][3] <= _T_1911 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1912 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1913 = and(buf_rspageQ[0][3], _T_1912) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][3] <= _T_1913 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1914 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1915 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1916 = cat(_T_1915, _T_1914) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1917 = orr(_T_1916) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1918 = not(_T_1917) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1919 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1920 = and(_T_1918, _T_1919) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1921 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1922 = and(_T_1920, _T_1921) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_1922 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1923 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1924 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1925 = cat(_T_1924, _T_1923) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1926 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1927 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1928 = cat(_T_1927, _T_1926) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1929 = not(_T_1928) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1930 = and(_T_1925, _T_1929) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1931 = orr(_T_1930) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1932 = not(_T_1931) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1933 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1934 = and(_T_1932, _T_1933) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1935 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1936 = and(_T_1934, _T_1935) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1937 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1938 = and(_T_1936, _T_1937) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_1938 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1939 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1940 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1941 = cat(_T_1940, _T_1939) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1942 = orr(_T_1941) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1943 = not(_T_1942) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1944 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1945 = and(_T_1943, _T_1944) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_1945 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1946 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1947 = and(_T_1946, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1948 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1949 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1950 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1951 = and(_T_1949, _T_1950) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1952 = or(_T_1948, _T_1951) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1953 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1954 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1955 = and(_T_1953, _T_1954) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1956 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1957 = and(_T_1955, _T_1956) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1958 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1959 = and(_T_1957, _T_1958) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1960 = or(_T_1952, _T_1959) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1961 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1962 = and(_T_1961, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1963 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1965 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1967 = or(_T_1960, _T_1966) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1968 = and(_T_1947, _T_1967) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1969 = or(_T_1968, buf_age[1][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][0] <= _T_1969 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1970 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1971 = and(_T_1970, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1972 = not(_T_1971) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1973 = and(buf_ageQ[1][0], _T_1972) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][0] <= _T_1973 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1974 = eq(UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1975 = not(buf_age[1][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1976 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1977 = and(_T_1975, _T_1976) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1978 = mux(_T_1974, UInt<1>("h00"), _T_1977) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][0] <= _T_1978 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1979 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1980 = and(_T_1979, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1981 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1982 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1983 = or(_T_1981, _T_1982) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1984 = not(_T_1983) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1985 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1986 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1987 = and(_T_1985, _T_1986) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1988 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1989 = and(_T_1987, _T_1988) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1990 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1991 = and(_T_1989, _T_1990) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1992 = or(_T_1984, _T_1991) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1993 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1994 = and(_T_1993, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1995 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1996 = and(_T_1994, _T_1995) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1997 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1998 = and(_T_1996, _T_1997) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1999 = or(_T_1992, _T_1998) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2000 = and(_T_1980, _T_1999) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][0] <= _T_2000 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2001 = or(buf_rspage_set[1][0], buf_rspage[1][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][0] <= _T_2001 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2002 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2003 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2004 = or(_T_2002, _T_2003) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2005 = not(_T_2004) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2006 = and(buf_rspageQ[1][0], _T_2005) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][0] <= _T_2006 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2007 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2008 = and(buf_rspageQ[1][0], _T_2007) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][0] <= _T_2008 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2009 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2010 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2011 = cat(_T_2010, _T_2009) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2012 = orr(_T_2011) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2013 = not(_T_2012) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2014 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2015 = and(_T_2013, _T_2014) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2016 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2017 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2018 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2019 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2020 = cat(_T_2019, _T_2018) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2021 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2022 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2023 = cat(_T_2022, _T_2021) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2024 = not(_T_2023) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2025 = and(_T_2020, _T_2024) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2026 = orr(_T_2025) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2027 = not(_T_2026) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2028 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2029 = and(_T_2027, _T_2028) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2030 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2031 = and(_T_2029, _T_2030) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2032 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2033 = and(_T_2031, _T_2032) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2033 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2034 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2035 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2036 = cat(_T_2035, _T_2034) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2037 = orr(_T_2036) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2038 = not(_T_2037) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2040 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2041 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2042 = and(_T_2041, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2043 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2044 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2045 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2046 = and(_T_2044, _T_2045) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2047 = or(_T_2043, _T_2046) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2048 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2049 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2050 = and(_T_2048, _T_2049) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2051 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2052 = and(_T_2050, _T_2051) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2053 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2054 = and(_T_2052, _T_2053) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2055 = or(_T_2047, _T_2054) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2056 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2057 = and(_T_2056, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2058 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2059 = and(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2060 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2061 = and(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2062 = or(_T_2055, _T_2061) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2063 = and(_T_2042, _T_2062) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2064 = or(_T_2063, buf_age[1][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][1] <= _T_2064 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2065 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2066 = and(_T_2065, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2067 = not(_T_2066) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2068 = and(buf_ageQ[1][1], _T_2067) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][1] <= _T_2068 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2069 = eq(UInt<2>("h01"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2070 = not(buf_age[1][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2071 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2072 = and(_T_2070, _T_2071) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2073 = mux(_T_2069, UInt<1>("h00"), _T_2072) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][1] <= _T_2073 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2074 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2075 = and(_T_2074, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2076 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2077 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2078 = or(_T_2076, _T_2077) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2079 = not(_T_2078) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2080 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2081 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2082 = and(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2083 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2084 = and(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2085 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2086 = and(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2087 = or(_T_2079, _T_2086) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2088 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2089 = and(_T_2088, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2090 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2091 = and(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2092 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2093 = and(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2094 = or(_T_2087, _T_2093) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2095 = and(_T_2075, _T_2094) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][1] <= _T_2095 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2096 = or(buf_rspage_set[1][1], buf_rspage[1][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][1] <= _T_2096 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2097 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2098 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2099 = or(_T_2097, _T_2098) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2100 = not(_T_2099) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2101 = and(buf_rspageQ[1][1], _T_2100) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][1] <= _T_2101 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2102 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2103 = and(buf_rspageQ[1][1], _T_2102) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][1] <= _T_2103 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2104 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2105 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2106 = cat(_T_2105, _T_2104) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2107 = orr(_T_2106) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2108 = not(_T_2107) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2109 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2110 = and(_T_2108, _T_2109) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2111 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2112 = and(_T_2110, _T_2111) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2112 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2113 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2114 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2115 = cat(_T_2114, _T_2113) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2116 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2117 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2118 = cat(_T_2117, _T_2116) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2119 = not(_T_2118) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2120 = and(_T_2115, _T_2119) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2121 = orr(_T_2120) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2122 = not(_T_2121) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2123 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2124 = and(_T_2122, _T_2123) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2125 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2126 = and(_T_2124, _T_2125) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2127 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2128 = and(_T_2126, _T_2127) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2128 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2129 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2130 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2131 = cat(_T_2130, _T_2129) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2132 = orr(_T_2131) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2133 = not(_T_2132) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2134 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2135 = and(_T_2133, _T_2134) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2135 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2136 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2137 = and(_T_2136, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2138 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2139 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2140 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2142 = or(_T_2138, _T_2141) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2143 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2144 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2145 = and(_T_2143, _T_2144) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2146 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2147 = and(_T_2145, _T_2146) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2148 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2149 = and(_T_2147, _T_2148) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2150 = or(_T_2142, _T_2149) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2151 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2152 = and(_T_2151, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2153 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2154 = and(_T_2152, _T_2153) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2155 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2156 = and(_T_2154, _T_2155) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2157 = or(_T_2150, _T_2156) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2158 = and(_T_2137, _T_2157) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2159 = or(_T_2158, buf_age[1][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][2] <= _T_2159 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2160 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2161 = and(_T_2160, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2162 = not(_T_2161) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2163 = and(buf_ageQ[1][2], _T_2162) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][2] <= _T_2163 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2164 = eq(UInt<2>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2165 = not(buf_age[1][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2166 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2167 = and(_T_2165, _T_2166) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2168 = mux(_T_2164, UInt<1>("h00"), _T_2167) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][2] <= _T_2168 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2170 = and(_T_2169, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2171 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2172 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2173 = or(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2174 = not(_T_2173) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2175 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2176 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2177 = and(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2178 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2179 = and(_T_2177, _T_2178) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2180 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2181 = and(_T_2179, _T_2180) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2182 = or(_T_2174, _T_2181) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2183 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2184 = and(_T_2183, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2185 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2186 = and(_T_2184, _T_2185) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2187 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2188 = and(_T_2186, _T_2187) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2189 = or(_T_2182, _T_2188) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2190 = and(_T_2170, _T_2189) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][2] <= _T_2190 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2191 = or(buf_rspage_set[1][2], buf_rspage[1][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][2] <= _T_2191 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2192 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2193 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2194 = or(_T_2192, _T_2193) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2195 = not(_T_2194) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2196 = and(buf_rspageQ[1][2], _T_2195) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][2] <= _T_2196 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2197 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2198 = and(buf_rspageQ[1][2], _T_2197) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][2] <= _T_2198 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2199 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2200 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2201 = cat(_T_2200, _T_2199) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2202 = orr(_T_2201) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2203 = not(_T_2202) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2204 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2205 = and(_T_2203, _T_2204) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2206 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2207 = and(_T_2205, _T_2206) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2207 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2208 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2209 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2210 = cat(_T_2209, _T_2208) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2211 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2212 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2213 = cat(_T_2212, _T_2211) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2214 = not(_T_2213) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2215 = and(_T_2210, _T_2214) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2216 = orr(_T_2215) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2217 = not(_T_2216) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2218 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2219 = and(_T_2217, _T_2218) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2220 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2222 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2223 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2224 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2225 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2226 = cat(_T_2225, _T_2224) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2227 = orr(_T_2226) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2228 = not(_T_2227) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2229 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2230 = and(_T_2228, _T_2229) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2230 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2231 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2232 = and(_T_2231, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2233 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2234 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2235 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2236 = and(_T_2234, _T_2235) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2237 = or(_T_2233, _T_2236) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2238 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2239 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2240 = and(_T_2238, _T_2239) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2241 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2242 = and(_T_2240, _T_2241) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2243 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2244 = and(_T_2242, _T_2243) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2245 = or(_T_2237, _T_2244) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2246 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2247 = and(_T_2246, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2248 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2249 = and(_T_2247, _T_2248) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2250 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2251 = and(_T_2249, _T_2250) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2252 = or(_T_2245, _T_2251) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2253 = and(_T_2232, _T_2252) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2254 = or(_T_2253, buf_age[1][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][3] <= _T_2254 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2255 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2256 = and(_T_2255, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2257 = not(_T_2256) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2258 = and(buf_ageQ[1][3], _T_2257) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][3] <= _T_2258 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2259 = eq(UInt<2>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2260 = not(buf_age[1][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2261 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2262 = and(_T_2260, _T_2261) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2263 = mux(_T_2259, UInt<1>("h00"), _T_2262) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][3] <= _T_2263 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2264 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2265 = and(_T_2264, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2266 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2267 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2268 = or(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2269 = not(_T_2268) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2270 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2271 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2272 = and(_T_2270, _T_2271) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2273 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2274 = and(_T_2272, _T_2273) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2275 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2276 = and(_T_2274, _T_2275) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2277 = or(_T_2269, _T_2276) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2278 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2279 = and(_T_2278, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2280 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2281 = and(_T_2279, _T_2280) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2282 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2283 = and(_T_2281, _T_2282) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2284 = or(_T_2277, _T_2283) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2285 = and(_T_2265, _T_2284) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][3] <= _T_2285 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2286 = or(buf_rspage_set[1][3], buf_rspage[1][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][3] <= _T_2286 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2287 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2288 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2289 = or(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2290 = not(_T_2289) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2291 = and(buf_rspageQ[1][3], _T_2290) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][3] <= _T_2291 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2292 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2293 = and(buf_rspageQ[1][3], _T_2292) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][3] <= _T_2293 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2294 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2295 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2296 = cat(_T_2295, _T_2294) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2297 = orr(_T_2296) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2298 = not(_T_2297) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2299 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2301 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2302 = and(_T_2300, _T_2301) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2302 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2303 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2304 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2305 = cat(_T_2304, _T_2303) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2306 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2307 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2308 = cat(_T_2307, _T_2306) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2309 = not(_T_2308) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2310 = and(_T_2305, _T_2309) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2311 = orr(_T_2310) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2312 = not(_T_2311) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2313 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2315 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2317 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2318 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2319 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2320 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2321 = cat(_T_2320, _T_2319) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2322 = orr(_T_2321) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2323 = not(_T_2322) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2324 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2325 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2326 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2327 = and(_T_2326, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2328 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2329 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2330 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2331 = and(_T_2329, _T_2330) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2332 = or(_T_2328, _T_2331) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2333 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2334 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2335 = and(_T_2333, _T_2334) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2336 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2338 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2339 = and(_T_2337, _T_2338) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2340 = or(_T_2332, _T_2339) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2341 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2342 = and(_T_2341, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2343 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2344 = and(_T_2342, _T_2343) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2345 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2346 = and(_T_2344, _T_2345) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2347 = or(_T_2340, _T_2346) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2348 = and(_T_2327, _T_2347) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2349 = or(_T_2348, buf_age[2][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][0] <= _T_2349 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2350 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2351 = and(_T_2350, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2352 = not(_T_2351) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2353 = and(buf_ageQ[2][0], _T_2352) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][0] <= _T_2353 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2354 = eq(UInt<2>("h02"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2355 = not(buf_age[2][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2356 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2357 = and(_T_2355, _T_2356) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2358 = mux(_T_2354, UInt<1>("h00"), _T_2357) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][0] <= _T_2358 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2359 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2360 = and(_T_2359, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2361 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2362 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2363 = or(_T_2361, _T_2362) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2364 = not(_T_2363) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2365 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2366 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2367 = and(_T_2365, _T_2366) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2368 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2369 = and(_T_2367, _T_2368) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2370 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2371 = and(_T_2369, _T_2370) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2372 = or(_T_2364, _T_2371) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2373 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2374 = and(_T_2373, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2375 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2376 = and(_T_2374, _T_2375) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2377 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2378 = and(_T_2376, _T_2377) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2379 = or(_T_2372, _T_2378) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2380 = and(_T_2360, _T_2379) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][0] <= _T_2380 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2381 = or(buf_rspage_set[2][0], buf_rspage[2][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][0] <= _T_2381 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2382 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2383 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2384 = or(_T_2382, _T_2383) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2385 = not(_T_2384) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2386 = and(buf_rspageQ[2][0], _T_2385) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][0] <= _T_2386 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2387 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2388 = and(buf_rspageQ[2][0], _T_2387) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][0] <= _T_2388 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2389 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2390 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2391 = cat(_T_2390, _T_2389) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2392 = orr(_T_2391) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2393 = not(_T_2392) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2394 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2396 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2397 = and(_T_2395, _T_2396) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2397 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2398 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2399 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2400 = cat(_T_2399, _T_2398) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2401 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2402 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2403 = cat(_T_2402, _T_2401) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2404 = not(_T_2403) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2405 = and(_T_2400, _T_2404) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2406 = orr(_T_2405) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2407 = not(_T_2406) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2408 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2409 = and(_T_2407, _T_2408) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2410 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2411 = and(_T_2409, _T_2410) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2412 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2413 = and(_T_2411, _T_2412) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2413 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2414 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2415 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2416 = cat(_T_2415, _T_2414) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2417 = orr(_T_2416) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2418 = not(_T_2417) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2419 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2420 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2421 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2422 = and(_T_2421, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2423 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2424 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2425 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2426 = and(_T_2424, _T_2425) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2427 = or(_T_2423, _T_2426) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2428 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2429 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2430 = and(_T_2428, _T_2429) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2431 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2432 = and(_T_2430, _T_2431) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2433 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2434 = and(_T_2432, _T_2433) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2435 = or(_T_2427, _T_2434) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2436 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2437 = and(_T_2436, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2438 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2440 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2441 = and(_T_2439, _T_2440) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2442 = or(_T_2435, _T_2441) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2443 = and(_T_2422, _T_2442) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2444 = or(_T_2443, buf_age[2][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][1] <= _T_2444 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2445 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2446 = and(_T_2445, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2447 = not(_T_2446) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2448 = and(buf_ageQ[2][1], _T_2447) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][1] <= _T_2448 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2449 = eq(UInt<2>("h02"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2450 = not(buf_age[2][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2451 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2453 = mux(_T_2449, UInt<1>("h00"), _T_2452) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][1] <= _T_2453 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2454 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2455 = and(_T_2454, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2456 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2457 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2459 = not(_T_2458) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2460 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2461 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2462 = and(_T_2460, _T_2461) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2463 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2465 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2466 = and(_T_2464, _T_2465) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2467 = or(_T_2459, _T_2466) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2468 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2469 = and(_T_2468, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2470 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2471 = and(_T_2469, _T_2470) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2472 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2473 = and(_T_2471, _T_2472) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2474 = or(_T_2467, _T_2473) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2475 = and(_T_2455, _T_2474) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][1] <= _T_2475 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2476 = or(buf_rspage_set[2][1], buf_rspage[2][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][1] <= _T_2476 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2477 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2478 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2479 = or(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2480 = not(_T_2479) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2481 = and(buf_rspageQ[2][1], _T_2480) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][1] <= _T_2481 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2482 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2483 = and(buf_rspageQ[2][1], _T_2482) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][1] <= _T_2483 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2484 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2485 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2486 = cat(_T_2485, _T_2484) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2487 = orr(_T_2486) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2488 = not(_T_2487) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2489 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2490 = and(_T_2488, _T_2489) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2491 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2492 = and(_T_2490, _T_2491) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2492 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2493 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2494 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2495 = cat(_T_2494, _T_2493) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2496 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2497 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2498 = cat(_T_2497, _T_2496) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2499 = not(_T_2498) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2500 = and(_T_2495, _T_2499) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2501 = orr(_T_2500) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2502 = not(_T_2501) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2503 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2505 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2506 = and(_T_2504, _T_2505) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2507 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2508 = and(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2508 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2509 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2510 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2511 = cat(_T_2510, _T_2509) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2512 = orr(_T_2511) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2513 = not(_T_2512) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2514 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2515 = and(_T_2513, _T_2514) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2515 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2516 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2517 = and(_T_2516, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2518 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2519 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2520 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2521 = and(_T_2519, _T_2520) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2522 = or(_T_2518, _T_2521) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2523 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2524 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2525 = and(_T_2523, _T_2524) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2526 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2528 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2530 = or(_T_2522, _T_2529) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2531 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2532 = and(_T_2531, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2533 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2534 = and(_T_2532, _T_2533) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2535 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2536 = and(_T_2534, _T_2535) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2537 = or(_T_2530, _T_2536) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2538 = and(_T_2517, _T_2537) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2539 = or(_T_2538, buf_age[2][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][2] <= _T_2539 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2540 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2541 = and(_T_2540, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2542 = not(_T_2541) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2543 = and(buf_ageQ[2][2], _T_2542) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][2] <= _T_2543 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2544 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2545 = not(buf_age[2][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2546 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2547 = and(_T_2545, _T_2546) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2548 = mux(_T_2544, UInt<1>("h00"), _T_2547) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][2] <= _T_2548 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2549 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2550 = and(_T_2549, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2551 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2552 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2553 = or(_T_2551, _T_2552) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2554 = not(_T_2553) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2555 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2556 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2557 = and(_T_2555, _T_2556) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2558 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2559 = and(_T_2557, _T_2558) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2560 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2561 = and(_T_2559, _T_2560) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2562 = or(_T_2554, _T_2561) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2563 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2564 = and(_T_2563, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2565 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2566 = and(_T_2564, _T_2565) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2567 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2568 = and(_T_2566, _T_2567) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2569 = or(_T_2562, _T_2568) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2570 = and(_T_2550, _T_2569) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][2] <= _T_2570 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2571 = or(buf_rspage_set[2][2], buf_rspage[2][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][2] <= _T_2571 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2572 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2573 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2574 = or(_T_2572, _T_2573) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2575 = not(_T_2574) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2576 = and(buf_rspageQ[2][2], _T_2575) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][2] <= _T_2576 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2577 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2578 = and(buf_rspageQ[2][2], _T_2577) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][2] <= _T_2578 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2579 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2580 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2581 = cat(_T_2580, _T_2579) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2582 = orr(_T_2581) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2583 = not(_T_2582) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2584 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2585 = and(_T_2583, _T_2584) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2586 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2587 = and(_T_2585, _T_2586) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2587 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2588 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2589 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2590 = cat(_T_2589, _T_2588) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2591 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2592 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2593 = cat(_T_2592, _T_2591) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2594 = not(_T_2593) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2595 = and(_T_2590, _T_2594) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2596 = orr(_T_2595) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2597 = not(_T_2596) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2598 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2599 = and(_T_2597, _T_2598) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2600 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2601 = and(_T_2599, _T_2600) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2602 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2603 = and(_T_2601, _T_2602) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2603 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2604 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2605 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2606 = cat(_T_2605, _T_2604) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2607 = orr(_T_2606) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2608 = not(_T_2607) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2609 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2610 = and(_T_2608, _T_2609) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2610 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2611 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2612 = and(_T_2611, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2613 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2614 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2615 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2616 = and(_T_2614, _T_2615) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2617 = or(_T_2613, _T_2616) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2618 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2619 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2620 = and(_T_2618, _T_2619) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2621 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2622 = and(_T_2620, _T_2621) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2623 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2624 = and(_T_2622, _T_2623) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2625 = or(_T_2617, _T_2624) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2626 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2627 = and(_T_2626, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2628 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2629 = and(_T_2627, _T_2628) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2630 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2631 = and(_T_2629, _T_2630) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2632 = or(_T_2625, _T_2631) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2633 = and(_T_2612, _T_2632) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2634 = or(_T_2633, buf_age[2][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][3] <= _T_2634 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2635 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2636 = and(_T_2635, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2637 = not(_T_2636) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2638 = and(buf_ageQ[2][3], _T_2637) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][3] <= _T_2638 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2639 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2640 = not(buf_age[2][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2641 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2642 = and(_T_2640, _T_2641) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2643 = mux(_T_2639, UInt<1>("h00"), _T_2642) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][3] <= _T_2643 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2644 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2645 = and(_T_2644, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2646 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2647 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2648 = or(_T_2646, _T_2647) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2649 = not(_T_2648) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2650 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2651 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2652 = and(_T_2650, _T_2651) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2653 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2654 = and(_T_2652, _T_2653) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2655 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2656 = and(_T_2654, _T_2655) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2657 = or(_T_2649, _T_2656) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2658 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2659 = and(_T_2658, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2660 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2661 = and(_T_2659, _T_2660) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2662 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2663 = and(_T_2661, _T_2662) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2664 = or(_T_2657, _T_2663) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2665 = and(_T_2645, _T_2664) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][3] <= _T_2665 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2666 = or(buf_rspage_set[2][3], buf_rspage[2][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][3] <= _T_2666 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2667 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2668 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2669 = or(_T_2667, _T_2668) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2670 = not(_T_2669) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2671 = and(buf_rspageQ[2][3], _T_2670) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][3] <= _T_2671 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2672 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2673 = and(buf_rspageQ[2][3], _T_2672) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][3] <= _T_2673 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2674 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2675 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2676 = cat(_T_2675, _T_2674) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2677 = orr(_T_2676) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2678 = not(_T_2677) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2679 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2680 = and(_T_2678, _T_2679) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2681 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2682 = and(_T_2680, _T_2681) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2682 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2683 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2684 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2685 = cat(_T_2684, _T_2683) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2686 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2687 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2688 = cat(_T_2687, _T_2686) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2689 = not(_T_2688) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2690 = and(_T_2685, _T_2689) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2691 = orr(_T_2690) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2692 = not(_T_2691) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2693 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2694 = and(_T_2692, _T_2693) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2695 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2696 = and(_T_2694, _T_2695) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2697 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2698 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2699 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2700 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2701 = cat(_T_2700, _T_2699) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2702 = orr(_T_2701) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2703 = not(_T_2702) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2704 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2705 = and(_T_2703, _T_2704) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2705 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2706 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2707 = and(_T_2706, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2708 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2709 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2710 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2711 = and(_T_2709, _T_2710) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2712 = or(_T_2708, _T_2711) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2713 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2714 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2715 = and(_T_2713, _T_2714) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2716 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2717 = and(_T_2715, _T_2716) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2718 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2720 = or(_T_2712, _T_2719) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2721 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2722 = and(_T_2721, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2723 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2724 = and(_T_2722, _T_2723) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2725 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2726 = and(_T_2724, _T_2725) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2727 = or(_T_2720, _T_2726) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2728 = and(_T_2707, _T_2727) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2729 = or(_T_2728, buf_age[3][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][0] <= _T_2729 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2730 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2731 = and(_T_2730, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2732 = not(_T_2731) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2733 = and(buf_ageQ[3][0], _T_2732) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][0] <= _T_2733 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2734 = eq(UInt<2>("h03"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2735 = not(buf_age[3][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2736 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2737 = and(_T_2735, _T_2736) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2738 = mux(_T_2734, UInt<1>("h00"), _T_2737) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][0] <= _T_2738 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2739 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2740 = and(_T_2739, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2741 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2742 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2743 = or(_T_2741, _T_2742) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2744 = not(_T_2743) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2745 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2746 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2748 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2749 = and(_T_2747, _T_2748) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2750 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2751 = and(_T_2749, _T_2750) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2752 = or(_T_2744, _T_2751) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2753 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2754 = and(_T_2753, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2755 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2757 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2758 = and(_T_2756, _T_2757) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2759 = or(_T_2752, _T_2758) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2760 = and(_T_2740, _T_2759) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][0] <= _T_2760 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2761 = or(buf_rspage_set[3][0], buf_rspage[3][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][0] <= _T_2761 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2762 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2763 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2764 = or(_T_2762, _T_2763) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2765 = not(_T_2764) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2766 = and(buf_rspageQ[3][0], _T_2765) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][0] <= _T_2766 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2768 = and(buf_rspageQ[3][0], _T_2767) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][0] <= _T_2768 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2769 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2770 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2771 = cat(_T_2770, _T_2769) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2772 = orr(_T_2771) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2773 = not(_T_2772) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2774 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2775 = and(_T_2773, _T_2774) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2776 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2777 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2778 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2779 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2780 = cat(_T_2779, _T_2778) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2781 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2782 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2783 = cat(_T_2782, _T_2781) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2784 = not(_T_2783) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2785 = and(_T_2780, _T_2784) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2786 = orr(_T_2785) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2787 = not(_T_2786) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2788 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2790 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2791 = and(_T_2789, _T_2790) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2792 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2793 = and(_T_2791, _T_2792) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2793 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2794 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2795 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2796 = cat(_T_2795, _T_2794) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2797 = orr(_T_2796) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2798 = not(_T_2797) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2799 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2800 = and(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2800 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2801 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2802 = and(_T_2801, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2803 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2804 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2805 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2807 = or(_T_2803, _T_2806) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2808 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2809 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2810 = and(_T_2808, _T_2809) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2811 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2812 = and(_T_2810, _T_2811) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2813 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2814 = and(_T_2812, _T_2813) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2815 = or(_T_2807, _T_2814) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2816 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2817 = and(_T_2816, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2818 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2819 = and(_T_2817, _T_2818) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2820 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2821 = and(_T_2819, _T_2820) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2822 = or(_T_2815, _T_2821) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2823 = and(_T_2802, _T_2822) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2824 = or(_T_2823, buf_age[3][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][1] <= _T_2824 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2825 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2826 = and(_T_2825, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2827 = not(_T_2826) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2828 = and(buf_ageQ[3][1], _T_2827) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][1] <= _T_2828 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2829 = eq(UInt<2>("h03"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2830 = not(buf_age[3][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2831 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2832 = and(_T_2830, _T_2831) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2833 = mux(_T_2829, UInt<1>("h00"), _T_2832) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][1] <= _T_2833 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2834 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2835 = and(_T_2834, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2836 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2837 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2838 = or(_T_2836, _T_2837) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2839 = not(_T_2838) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2840 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2841 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2842 = and(_T_2840, _T_2841) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2843 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2844 = and(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2845 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2846 = and(_T_2844, _T_2845) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2847 = or(_T_2839, _T_2846) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2848 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2849 = and(_T_2848, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2850 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2851 = and(_T_2849, _T_2850) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2852 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2853 = and(_T_2851, _T_2852) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2854 = or(_T_2847, _T_2853) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2855 = and(_T_2835, _T_2854) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][1] <= _T_2855 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2856 = or(buf_rspage_set[3][1], buf_rspage[3][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][1] <= _T_2856 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2857 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2859 = or(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2860 = not(_T_2859) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2861 = and(buf_rspageQ[3][1], _T_2860) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][1] <= _T_2861 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2862 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2863 = and(buf_rspageQ[3][1], _T_2862) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][1] <= _T_2863 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2864 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2865 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2866 = cat(_T_2865, _T_2864) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2867 = orr(_T_2866) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2868 = not(_T_2867) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2869 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2871 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2872 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2873 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2874 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2875 = cat(_T_2874, _T_2873) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2876 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2877 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2878 = cat(_T_2877, _T_2876) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2879 = not(_T_2878) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2880 = and(_T_2875, _T_2879) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2881 = orr(_T_2880) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2882 = not(_T_2881) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2883 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2884 = and(_T_2882, _T_2883) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2885 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2886 = and(_T_2884, _T_2885) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2887 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2888 = and(_T_2886, _T_2887) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2888 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2889 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2890 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2891 = cat(_T_2890, _T_2889) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2892 = orr(_T_2891) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2893 = not(_T_2892) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2894 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2895 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2896 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2897 = and(_T_2896, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2898 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2899 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2900 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2901 = and(_T_2899, _T_2900) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2902 = or(_T_2898, _T_2901) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2903 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2904 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2905 = and(_T_2903, _T_2904) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2906 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2907 = and(_T_2905, _T_2906) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2908 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2909 = and(_T_2907, _T_2908) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2910 = or(_T_2902, _T_2909) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2911 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2912 = and(_T_2911, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2913 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2914 = and(_T_2912, _T_2913) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2915 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2916 = and(_T_2914, _T_2915) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2917 = or(_T_2910, _T_2916) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2918 = and(_T_2897, _T_2917) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2919 = or(_T_2918, buf_age[3][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][2] <= _T_2919 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2920 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2921 = and(_T_2920, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2922 = not(_T_2921) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2923 = and(buf_ageQ[3][2], _T_2922) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][2] <= _T_2923 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2924 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2925 = not(buf_age[3][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2926 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2927 = and(_T_2925, _T_2926) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2928 = mux(_T_2924, UInt<1>("h00"), _T_2927) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][2] <= _T_2928 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2929 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2930 = and(_T_2929, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2931 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2932 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2933 = or(_T_2931, _T_2932) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2934 = not(_T_2933) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2935 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2936 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2937 = and(_T_2935, _T_2936) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2938 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2940 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2942 = or(_T_2934, _T_2941) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2943 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2944 = and(_T_2943, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2945 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2946 = and(_T_2944, _T_2945) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2947 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2949 = or(_T_2942, _T_2948) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2950 = and(_T_2930, _T_2949) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][2] <= _T_2950 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2951 = or(buf_rspage_set[3][2], buf_rspage[3][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][2] <= _T_2951 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2952 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2953 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2954 = or(_T_2952, _T_2953) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2955 = not(_T_2954) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2956 = and(buf_rspageQ[3][2], _T_2955) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][2] <= _T_2956 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2957 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2958 = and(buf_rspageQ[3][2], _T_2957) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][2] <= _T_2958 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2959 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2960 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2961 = cat(_T_2960, _T_2959) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2962 = orr(_T_2961) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2963 = not(_T_2962) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2964 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2966 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2967 = and(_T_2965, _T_2966) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2967 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2968 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2969 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2970 = cat(_T_2969, _T_2968) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2971 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2972 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2973 = cat(_T_2972, _T_2971) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2974 = not(_T_2973) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2975 = and(_T_2970, _T_2974) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2976 = orr(_T_2975) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2977 = not(_T_2976) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2978 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2979 = and(_T_2977, _T_2978) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2980 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2981 = and(_T_2979, _T_2980) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2982 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2983 = and(_T_2981, _T_2982) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2983 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2984 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2985 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2986 = cat(_T_2985, _T_2984) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2987 = orr(_T_2986) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2988 = not(_T_2987) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2989 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2990 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2991 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2992 = and(_T_2991, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2993 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2994 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2995 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2996 = and(_T_2994, _T_2995) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2997 = or(_T_2993, _T_2996) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2998 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2999 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_3000 = and(_T_2998, _T_2999) @[el2_lsu_bus_buffer.scala 564:43] - node _T_3001 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_3002 = and(_T_3000, _T_3001) @[el2_lsu_bus_buffer.scala 564:73] - node _T_3003 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_3004 = and(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 564:92] - node _T_3005 = or(_T_2997, _T_3004) @[el2_lsu_bus_buffer.scala 563:93] - node _T_3006 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_3007 = and(_T_3006, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_3008 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_3009 = and(_T_3007, _T_3008) @[el2_lsu_bus_buffer.scala 565:54] - node _T_3010 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_3011 = and(_T_3009, _T_3010) @[el2_lsu_bus_buffer.scala 565:73] - node _T_3012 = or(_T_3005, _T_3011) @[el2_lsu_bus_buffer.scala 564:113] - node _T_3013 = and(_T_2992, _T_3012) @[el2_lsu_bus_buffer.scala 562:79] - node _T_3014 = or(_T_3013, buf_age[3][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][3] <= _T_3014 @[el2_lsu_bus_buffer.scala 562:29] - node _T_3015 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_3016 = and(_T_3015, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_3017 = not(_T_3016) @[el2_lsu_bus_buffer.scala 567:49] - node _T_3018 = and(buf_ageQ[3][3], _T_3017) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][3] <= _T_3018 @[el2_lsu_bus_buffer.scala 567:29] - node _T_3019 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_3020 = not(buf_age[3][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_3021 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_3022 = and(_T_3020, _T_3021) @[el2_lsu_bus_buffer.scala 568:108] - node _T_3023 = mux(_T_3019, UInt<1>("h00"), _T_3022) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][3] <= _T_3023 @[el2_lsu_bus_buffer.scala 568:29] - node _T_3024 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_3025 = and(_T_3024, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_3026 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_3027 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_3028 = or(_T_3026, _T_3027) @[el2_lsu_bus_buffer.scala 570:109] - node _T_3029 = not(_T_3028) @[el2_lsu_bus_buffer.scala 570:81] - node _T_3030 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_3031 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 571:41] - node _T_3033 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 571:71] - node _T_3035 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_3036 = and(_T_3034, _T_3035) @[el2_lsu_bus_buffer.scala 571:90] - node _T_3037 = or(_T_3029, _T_3036) @[el2_lsu_bus_buffer.scala 570:139] - node _T_3038 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_3039 = and(_T_3038, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_3040 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 572:52] - node _T_3042 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_3043 = and(_T_3041, _T_3042) @[el2_lsu_bus_buffer.scala 572:71] - node _T_3044 = or(_T_3037, _T_3043) @[el2_lsu_bus_buffer.scala 571:110] - node _T_3045 = and(_T_3025, _T_3044) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][3] <= _T_3045 @[el2_lsu_bus_buffer.scala 570:29] - node _T_3046 = or(buf_rspage_set[3][3], buf_rspage[3][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][3] <= _T_3046 @[el2_lsu_bus_buffer.scala 573:29] - node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_3048 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_3049 = or(_T_3047, _T_3048) @[el2_lsu_bus_buffer.scala 574:80] - node _T_3050 = not(_T_3049) @[el2_lsu_bus_buffer.scala 574:52] - node _T_3051 = and(buf_rspageQ[3][3], _T_3050) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][3] <= _T_3051 @[el2_lsu_bus_buffer.scala 574:29] - node _T_3052 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_3053 = and(buf_rspageQ[3][3], _T_3052) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][3] <= _T_3053 @[el2_lsu_bus_buffer.scala 575:29] - node _T_3054 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3055 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3056 = cat(_T_3055, _T_3054) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3057 = bits(_T_3056, 0, 0) @[OneHot.scala 85:71] - node _T_3058 = bits(_T_3056, 1, 1) @[OneHot.scala 85:71] - node _T_3059 = bits(_T_3056, 2, 2) @[OneHot.scala 85:71] - node _T_3060 = bits(_T_3056, 3, 3) @[OneHot.scala 85:71] - node _T_3061 = mux(_T_3060, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3062 = mux(_T_3059, UInt<4>("h04"), _T_3061) @[Mux.scala 47:69] - node _T_3063 = mux(_T_3058, UInt<4>("h02"), _T_3062) @[Mux.scala 47:69] - node _T_3064 = mux(_T_3057, UInt<4>("h01"), _T_3063) @[Mux.scala 47:69] - CmdPtr0 <= _T_3064 @[el2_lsu_bus_buffer.scala 578:27] - node _T_3065 = cat(CmdPtr1Dec[1], CmdPtr1Dec[0]) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3066 = cat(CmdPtr1Dec[3], CmdPtr1Dec[2]) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3067 = cat(_T_3066, _T_3065) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3068 = bits(_T_3067, 0, 0) @[OneHot.scala 85:71] - node _T_3069 = bits(_T_3067, 1, 1) @[OneHot.scala 85:71] - node _T_3070 = bits(_T_3067, 2, 2) @[OneHot.scala 85:71] - node _T_3071 = bits(_T_3067, 3, 3) @[OneHot.scala 85:71] - node _T_3072 = mux(_T_3071, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3073 = mux(_T_3070, UInt<4>("h04"), _T_3072) @[Mux.scala 47:69] - node _T_3074 = mux(_T_3069, UInt<4>("h02"), _T_3073) @[Mux.scala 47:69] - node _T_3075 = mux(_T_3068, UInt<4>("h01"), _T_3074) @[Mux.scala 47:69] - CmdPtr1 <= _T_3075 @[el2_lsu_bus_buffer.scala 579:27] - node _T_3076 = cat(RspPtrDec[1], RspPtrDec[0]) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3077 = cat(RspPtrDec[3], RspPtrDec[2]) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3078 = cat(_T_3077, _T_3076) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3079 = bits(_T_3078, 0, 0) @[OneHot.scala 85:71] - node _T_3080 = bits(_T_3078, 1, 1) @[OneHot.scala 85:71] - node _T_3081 = bits(_T_3078, 2, 2) @[OneHot.scala 85:71] - node _T_3082 = bits(_T_3078, 3, 3) @[OneHot.scala 85:71] - node _T_3083 = mux(_T_3082, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3084 = mux(_T_3081, UInt<4>("h04"), _T_3083) @[Mux.scala 47:69] - node _T_3085 = mux(_T_3080, UInt<4>("h02"), _T_3084) @[Mux.scala 47:69] - node _T_3086 = mux(_T_3079, UInt<4>("h01"), _T_3085) @[Mux.scala 47:69] - RspPtr <= _T_3086 @[el2_lsu_bus_buffer.scala 580:27] - node _T_3087 = or(CmdPtr0Dec[0], CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 581:49] - node _T_3088 = or(_T_3087, CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 581:49] - node _T_3089 = or(_T_3088, CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 581:49] - found_cmdptr0 <= _T_3089 @[el2_lsu_bus_buffer.scala 581:27] - node _T_3090 = or(CmdPtr1Dec[0], CmdPtr1Dec[1]) @[el2_lsu_bus_buffer.scala 582:49] - node _T_3091 = or(_T_3090, CmdPtr1Dec[2]) @[el2_lsu_bus_buffer.scala 582:49] - node _T_3092 = or(_T_3091, CmdPtr1Dec[3]) @[el2_lsu_bus_buffer.scala 582:49] - found_cmdptr1 <= _T_3092 @[el2_lsu_bus_buffer.scala 582:27] - buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3093 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3094 = and(ibuf_drain_vld, _T_3093) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[0] <= _T_3094 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3095 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3096 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3097 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3098 = and(_T_3096, _T_3097) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3099 = bits(_T_3098, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3100 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3101 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3102 = mux(_T_3099, _T_3100, _T_3101) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3103 = mux(ibuf_drainvec_vld[0], _T_3095, _T_3102) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[0] <= _T_3103 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3104 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3105 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3106 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3107 = and(_T_3105, _T_3106) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3108 = bits(_T_3107, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3109 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3110 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3111 = mux(_T_3108, _T_3109, _T_3110) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3112 = mux(ibuf_drainvec_vld[0], _T_3104, _T_3111) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[0] <= _T_3112 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3113 = mux(ibuf_drainvec_vld[0], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[0] <= _T_3113 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3114 = mux(ibuf_drainvec_vld[0], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[0] <= _T_3114 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3115 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3116 = mux(ibuf_drainvec_vld[0], _T_3115, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[0] <= _T_3116 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3117 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3118 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3119 = and(_T_3117, _T_3118) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3120 = mux(ibuf_drainvec_vld[0], ibuf_dual, _T_3119) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[0] <= _T_3120 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3121 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3122 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3124 = bits(_T_3123, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3125 = mux(_T_3124, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3126 = mux(ibuf_drainvec_vld[0], ibuf_dualtag, _T_3125) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[0] <= _T_3126 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3127 = mux(ibuf_drainvec_vld[0], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[0] <= _T_3127 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3128 = mux(ibuf_drainvec_vld[0], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[0] <= _T_3128 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3129 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3130 = mux(ibuf_drainvec_vld[0], ibuf_sz, _T_3129) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[0] <= _T_3130 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3131 = mux(ibuf_drainvec_vld[0], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[0] <= _T_3131 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3132 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3132 : @[Conditional.scala 40:58] - node _T_3133 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3134 = mux(_T_3133, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[0] <= _T_3134 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3135 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3137 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3138 = and(_T_3136, _T_3137) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3139 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3140 = and(_T_3138, _T_3139) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3141 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3142 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3144 = or(_T_3140, _T_3143) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3145 = and(_T_3135, _T_3144) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3146 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3147 = and(ibuf_drain_vld, _T_3146) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3148 = or(_T_3145, _T_3147) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[0] <= _T_3148 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3149 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3150 = and(ibuf_drain_vld, _T_3149) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3151 = bits(_T_3150, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3152 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3153 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3154 = mux(_T_3151, _T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[0] <= _T_3154 @[el2_lsu_bus_buffer.scala 620:31] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + obuf_data <= obuf_data_in @[el2_lib.scala 514:16] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 414:54] + _T_1852 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 414:54] + obuf_wr_timer <= _T_1852 @[el2_lsu_bus_buffer.scala 414:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1859 = or(_T_1856, _T_1858) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1861 = or(_T_1855, _T_1860) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1863 = and(_T_1853, _T_1862) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1870 = or(_T_1867, _T_1869) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1872 = or(_T_1866, _T_1871) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1874 = and(_T_1864, _T_1873) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1881 = or(_T_1878, _T_1880) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1883 = or(_T_1877, _T_1882) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1885 = and(_T_1875, _T_1884) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1892 = or(_T_1889, _T_1891) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1894 = or(_T_1888, _T_1893) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1896 = and(_T_1886, _T_1895) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] + WrPtr0_m <= _T_1900 @[el2_lsu_bus_buffer.scala 417:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1906 = or(_T_1903, _T_1905) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1910 = or(_T_1907, _T_1909) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1912 = or(_T_1906, _T_1911) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1914 = and(_T_1901, _T_1913) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1920 = or(_T_1917, _T_1919) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1924 = or(_T_1921, _T_1923) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1926 = or(_T_1920, _T_1925) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1928 = and(_T_1915, _T_1927) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1934 = or(_T_1931, _T_1933) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1938 = or(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1940 = or(_T_1934, _T_1939) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1942 = and(_T_1929, _T_1941) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1948 = or(_T_1945, _T_1947) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1952 = or(_T_1949, _T_1951) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1954 = or(_T_1948, _T_1953) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1956 = and(_T_1943, _T_1955) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] + node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] + node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] + WrPtr1_m <= _T_1960 @[el2_lsu_bus_buffer.scala 423:12] + wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 428:21] + buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + node _T_1961 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1967 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1970 = and(_T_1968, _T_1969) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1972 = and(_T_1970, _T_1971) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1973 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1976 = and(_T_1974, _T_1975) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1978 = and(_T_1976, _T_1977) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1979 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1982 = and(_T_1980, _T_1981) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1984 = and(_T_1982, _T_1983) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] + node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] + node _T_1987 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1988 = and(buf_age[0], _T_1987) @[el2_lsu_bus_buffer.scala 432:59] + node _T_1989 = orr(_T_1988) @[el2_lsu_bus_buffer.scala 432:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 432:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_1993 = and(_T_1990, _T_1992) @[el2_lsu_bus_buffer.scala 432:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_1995 = and(_T_1993, _T_1994) @[el2_lsu_bus_buffer.scala 432:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_1997 = and(_T_1995, _T_1996) @[el2_lsu_bus_buffer.scala 432:123] + node _T_1998 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1999 = and(buf_age[1], _T_1998) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2000 = orr(_T_1999) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2004 = and(_T_2001, _T_2003) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2006 = and(_T_2004, _T_2005) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2008 = and(_T_2006, _T_2007) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2009 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2010 = and(buf_age[2], _T_2009) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2011 = orr(_T_2010) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2015 = and(_T_2012, _T_2014) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2019 = and(_T_2017, _T_2018) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2020 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2021 = and(buf_age[3], _T_2020) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2022 = orr(_T_2021) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2026 = and(_T_2023, _T_2025) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] + node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 433:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2036 = and(_T_2034, _T_2035) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2044 = and(_T_2042, _T_2043) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2048 = and(_T_2046, _T_2047) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] + node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] + node _T_2051 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 436:31] + found_cmdptr0 <= _T_2051 @[el2_lsu_bus_buffer.scala 436:17] + node _T_2052 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 437:31] + found_cmdptr1 <= _T_2052 @[el2_lsu_bus_buffer.scala 437:17] + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_2055 = bits(_T_2054, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2056 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2057 = or(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2058 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2059 = or(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2060 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2061 = or(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2062 = bits(_T_2054, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2063 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2064 = or(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2065 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2066 = or(_T_2064, _T_2065) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2067 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2069 = bits(_T_2054, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2070 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2071 = or(_T_2069, _T_2070) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2072 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2073 = or(_T_2071, _T_2072) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2074 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2075 = or(_T_2073, _T_2074) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] + node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] + CmdPtr0 <= _T_2077 @[el2_lsu_bus_buffer.scala 444:11] + node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2080 = bits(_T_2079, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2081 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2082 = or(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2083 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2084 = or(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2085 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2086 = or(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2087 = bits(_T_2079, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2088 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2089 = or(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2090 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2091 = or(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2092 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2094 = bits(_T_2079, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2095 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2096 = or(_T_2094, _T_2095) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2097 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2098 = or(_T_2096, _T_2097) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2099 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2100 = or(_T_2098, _T_2099) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] + node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] + CmdPtr1 <= _T_2102 @[el2_lsu_bus_buffer.scala 446:11] + node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] + node _T_2105 = bits(_T_2104, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2106 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2107 = or(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2108 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2109 = or(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2110 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2111 = or(_T_2109, _T_2110) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2112 = bits(_T_2104, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2113 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2114 = or(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2115 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2116 = or(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2117 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2118 = or(_T_2116, _T_2117) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2119 = bits(_T_2104, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2120 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2121 = or(_T_2119, _T_2120) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2122 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2123 = or(_T_2121, _T_2122) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2124 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2125 = or(_T_2123, _T_2124) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] + RspPtr <= _T_2127 @[el2_lsu_bus_buffer.scala 447:10] + wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 448:26] + buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 450:25] + buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 452:28] + buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 454:27] + buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 456:24] + buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2133 = and(_T_2131, _T_2132) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2134 = or(_T_2130, _T_2133) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2137 = and(_T_2135, _T_2136) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2142 = or(_T_2134, _T_2141) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2146 = and(_T_2144, _T_2145) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2148 = and(_T_2146, _T_2147) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2149 = or(_T_2142, _T_2148) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2150 = and(_T_2129, _T_2149) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2152 = or(_T_2150, _T_2151) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2158 = and(_T_2156, _T_2157) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2159 = or(_T_2155, _T_2158) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2162 = and(_T_2160, _T_2161) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2167 = or(_T_2159, _T_2166) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2171 = and(_T_2169, _T_2170) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2173 = and(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2174 = or(_T_2167, _T_2173) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2175 = and(_T_2154, _T_2174) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2177 = or(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2183 = and(_T_2181, _T_2182) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2184 = or(_T_2180, _T_2183) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2187 = and(_T_2185, _T_2186) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2192 = or(_T_2184, _T_2191) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2196 = and(_T_2194, _T_2195) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2198 = and(_T_2196, _T_2197) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2199 = or(_T_2192, _T_2198) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2200 = and(_T_2179, _T_2199) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2202 = or(_T_2200, _T_2201) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2208 = and(_T_2206, _T_2207) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2209 = or(_T_2205, _T_2208) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2212 = and(_T_2210, _T_2211) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2214 = and(_T_2212, _T_2213) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2217 = or(_T_2209, _T_2216) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2224 = or(_T_2217, _T_2223) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2225 = and(_T_2204, _T_2224) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2227 = or(_T_2225, _T_2226) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] + node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2235 = and(_T_2233, _T_2234) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2236 = or(_T_2232, _T_2235) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2239 = and(_T_2237, _T_2238) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2244 = or(_T_2236, _T_2243) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2248 = and(_T_2246, _T_2247) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2250 = and(_T_2248, _T_2249) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2251 = or(_T_2244, _T_2250) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2252 = and(_T_2231, _T_2251) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2254 = or(_T_2252, _T_2253) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2260 = and(_T_2258, _T_2259) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2261 = or(_T_2257, _T_2260) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2264 = and(_T_2262, _T_2263) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2269 = or(_T_2261, _T_2268) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2273 = and(_T_2271, _T_2272) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2275 = and(_T_2273, _T_2274) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2276 = or(_T_2269, _T_2275) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2277 = and(_T_2256, _T_2276) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2279 = or(_T_2277, _T_2278) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2285 = and(_T_2283, _T_2284) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2286 = or(_T_2282, _T_2285) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2289 = and(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2294 = or(_T_2286, _T_2293) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2298 = and(_T_2296, _T_2297) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2301 = or(_T_2294, _T_2300) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2302 = and(_T_2281, _T_2301) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2304 = or(_T_2302, _T_2303) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2310 = and(_T_2308, _T_2309) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2311 = or(_T_2307, _T_2310) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2319 = or(_T_2311, _T_2318) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2323 = and(_T_2321, _T_2322) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2326 = or(_T_2319, _T_2325) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2327 = and(_T_2306, _T_2326) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2329 = or(_T_2327, _T_2328) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] + node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2338 = or(_T_2334, _T_2337) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2341 = and(_T_2339, _T_2340) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2346 = or(_T_2338, _T_2345) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2350 = and(_T_2348, _T_2349) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2352 = and(_T_2350, _T_2351) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2353 = or(_T_2346, _T_2352) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2354 = and(_T_2333, _T_2353) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2356 = or(_T_2354, _T_2355) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2362 = and(_T_2360, _T_2361) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2363 = or(_T_2359, _T_2362) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2366 = and(_T_2364, _T_2365) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2371 = or(_T_2363, _T_2370) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2375 = and(_T_2373, _T_2374) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2377 = and(_T_2375, _T_2376) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2378 = or(_T_2371, _T_2377) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2379 = and(_T_2358, _T_2378) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2381 = or(_T_2379, _T_2380) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2387 = and(_T_2385, _T_2386) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2388 = or(_T_2384, _T_2387) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2391 = and(_T_2389, _T_2390) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2396 = or(_T_2388, _T_2395) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2400 = and(_T_2398, _T_2399) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2402 = and(_T_2400, _T_2401) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2403 = or(_T_2396, _T_2402) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2404 = and(_T_2383, _T_2403) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2406 = or(_T_2404, _T_2405) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2412 = and(_T_2410, _T_2411) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2413 = or(_T_2409, _T_2412) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2416 = and(_T_2414, _T_2415) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2418 = and(_T_2416, _T_2417) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2421 = or(_T_2413, _T_2420) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2425 = and(_T_2423, _T_2424) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2427 = and(_T_2425, _T_2426) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2428 = or(_T_2421, _T_2427) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2429 = and(_T_2408, _T_2428) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2431 = or(_T_2429, _T_2430) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] + node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2440 = or(_T_2436, _T_2439) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2443 = and(_T_2441, _T_2442) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2445 = and(_T_2443, _T_2444) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2447 = and(_T_2445, _T_2446) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2448 = or(_T_2440, _T_2447) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2454 = and(_T_2452, _T_2453) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2455 = or(_T_2448, _T_2454) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2456 = and(_T_2435, _T_2455) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2465 = or(_T_2461, _T_2464) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2468 = and(_T_2466, _T_2467) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2470 = and(_T_2468, _T_2469) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2472 = and(_T_2470, _T_2471) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2473 = or(_T_2465, _T_2472) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2477 = and(_T_2475, _T_2476) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2479 = and(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2480 = or(_T_2473, _T_2479) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2481 = and(_T_2460, _T_2480) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2483 = or(_T_2481, _T_2482) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2489 = and(_T_2487, _T_2488) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2490 = or(_T_2486, _T_2489) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2493 = and(_T_2491, _T_2492) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2495 = and(_T_2493, _T_2494) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2497 = and(_T_2495, _T_2496) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2498 = or(_T_2490, _T_2497) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2502 = and(_T_2500, _T_2501) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2505 = or(_T_2498, _T_2504) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2506 = and(_T_2485, _T_2505) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2508 = or(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2514 = and(_T_2512, _T_2513) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2515 = or(_T_2511, _T_2514) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2518 = and(_T_2516, _T_2517) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2520 = and(_T_2518, _T_2519) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2522 = and(_T_2520, _T_2521) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2523 = or(_T_2515, _T_2522) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2530 = or(_T_2523, _T_2529) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2531 = and(_T_2510, _T_2530) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2533 = or(_T_2531, _T_2532) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 463:22] + buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2540 = and(_T_2536, _T_2539) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2545 = and(_T_2541, _T_2544) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2550 = and(_T_2546, _T_2549) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2555 = and(_T_2551, _T_2554) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2563 = and(_T_2559, _T_2562) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2568 = and(_T_2564, _T_2567) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2573 = and(_T_2569, _T_2572) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2578 = and(_T_2574, _T_2577) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] + node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] + node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2586 = and(_T_2582, _T_2585) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2591 = and(_T_2587, _T_2590) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2596 = and(_T_2592, _T_2595) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2601 = and(_T_2597, _T_2600) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] + node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] + node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2609 = and(_T_2605, _T_2608) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2614 = and(_T_2610, _T_2613) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2619 = and(_T_2615, _T_2618) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2624 = and(_T_2620, _T_2623) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] + node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] + node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] + buf_age[0] <= _T_2558 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[1] <= _T_2581 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[2] <= _T_2604 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[3] <= _T_2627 @[el2_lsu_bus_buffer.scala 465:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2632 = and(_T_2630, _T_2631) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2638 = and(_T_2636, _T_2637) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2644 = and(_T_2642, _T_2643) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2650 = and(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] + node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] + node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2659 = and(_T_2657, _T_2658) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2671 = and(_T_2669, _T_2670) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2677 = and(_T_2675, _T_2676) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] + node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] + node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2686 = and(_T_2684, _T_2685) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2692 = and(_T_2690, _T_2691) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2704 = and(_T_2702, _T_2703) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] + node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] + node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2713 = and(_T_2711, _T_2712) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2725 = and(_T_2723, _T_2724) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] + node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2654 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[1] <= _T_2681 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[2] <= _T_2708 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[3] <= _T_2735 @[el2_lsu_bus_buffer.scala 466:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2738 = and(_T_2736, _T_2737) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2741 = and(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2744 = and(_T_2742, _T_2743) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] + node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2753 = and(_T_2751, _T_2752) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2759 = and(_T_2757, _T_2758) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2762 = and(_T_2760, _T_2761) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] + node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2768 = and(_T_2766, _T_2767) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2774 = and(_T_2772, _T_2773) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] + node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] + node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2783 = and(_T_2781, _T_2782) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2786 = and(_T_2784, _T_2785) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2792 = and(_T_2790, _T_2791) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] + node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] + node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2750 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[1] <= _T_2765 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[2] <= _T_2780 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[3] <= _T_2795 @[el2_lsu_bus_buffer.scala 467:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2800 = or(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2804 = and(_T_2802, _T_2803) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2808 = and(_T_2806, _T_2807) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2809 = or(_T_2801, _T_2808) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2816 = or(_T_2809, _T_2815) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2817 = and(_T_2797, _T_2816) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2822 = or(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2826 = and(_T_2824, _T_2825) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2828 = and(_T_2826, _T_2827) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2830 = and(_T_2828, _T_2829) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2831 = or(_T_2823, _T_2830) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2835 = and(_T_2833, _T_2834) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2837 = and(_T_2835, _T_2836) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2838 = or(_T_2831, _T_2837) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2839 = and(_T_2819, _T_2838) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2844 = or(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2848 = and(_T_2846, _T_2847) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2850 = and(_T_2848, _T_2849) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2852 = and(_T_2850, _T_2851) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2853 = or(_T_2845, _T_2852) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2857 = and(_T_2855, _T_2856) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2859 = and(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2860 = or(_T_2853, _T_2859) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2861 = and(_T_2841, _T_2860) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2866 = or(_T_2864, _T_2865) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2874 = and(_T_2872, _T_2873) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2875 = or(_T_2867, _T_2874) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2879 = and(_T_2877, _T_2878) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2881 = and(_T_2879, _T_2880) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2882 = or(_T_2875, _T_2881) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2883 = and(_T_2863, _T_2882) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] + node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] + node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2891 = or(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2897 = and(_T_2895, _T_2896) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2899 = and(_T_2897, _T_2898) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2900 = or(_T_2892, _T_2899) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2907 = or(_T_2900, _T_2906) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2908 = and(_T_2888, _T_2907) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2913 = or(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2917 = and(_T_2915, _T_2916) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2919 = and(_T_2917, _T_2918) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2921 = and(_T_2919, _T_2920) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2922 = or(_T_2914, _T_2921) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2926 = and(_T_2924, _T_2925) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2928 = and(_T_2926, _T_2927) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2929 = or(_T_2922, _T_2928) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2930 = and(_T_2910, _T_2929) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2935 = or(_T_2933, _T_2934) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2943 = and(_T_2941, _T_2942) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2944 = or(_T_2936, _T_2943) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2950 = and(_T_2948, _T_2949) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2951 = or(_T_2944, _T_2950) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2952 = and(_T_2932, _T_2951) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2957 = or(_T_2955, _T_2956) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2961 = and(_T_2959, _T_2960) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2963 = and(_T_2961, _T_2962) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2966 = or(_T_2958, _T_2965) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2970 = and(_T_2968, _T_2969) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2972 = and(_T_2970, _T_2971) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2973 = or(_T_2966, _T_2972) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2974 = and(_T_2954, _T_2973) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] + node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] + node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2982 = or(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2986 = and(_T_2984, _T_2985) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2988 = and(_T_2986, _T_2987) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2991 = or(_T_2983, _T_2990) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2998 = or(_T_2991, _T_2997) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2999 = and(_T_2979, _T_2998) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3004 = or(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3008 = and(_T_3006, _T_3007) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3010 = and(_T_3008, _T_3009) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3012 = and(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3013 = or(_T_3005, _T_3012) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3017 = and(_T_3015, _T_3016) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3019 = and(_T_3017, _T_3018) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3020 = or(_T_3013, _T_3019) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3021 = and(_T_3001, _T_3020) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3026 = or(_T_3024, _T_3025) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3030 = and(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3035 = or(_T_3027, _T_3034) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3039 = and(_T_3037, _T_3038) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3042 = or(_T_3035, _T_3041) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3043 = and(_T_3023, _T_3042) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3052 = and(_T_3050, _T_3051) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3054 = and(_T_3052, _T_3053) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3056 = and(_T_3054, _T_3055) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3057 = or(_T_3049, _T_3056) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3061 = and(_T_3059, _T_3060) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3063 = and(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3064 = or(_T_3057, _T_3063) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3065 = and(_T_3045, _T_3064) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] + node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3077 = and(_T_3075, _T_3076) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3079 = and(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3081 = and(_T_3079, _T_3080) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3082 = or(_T_3074, _T_3081) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3086 = and(_T_3084, _T_3085) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3088 = and(_T_3086, _T_3087) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3089 = or(_T_3082, _T_3088) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3090 = and(_T_3070, _T_3089) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3095 = or(_T_3093, _T_3094) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3099 = and(_T_3097, _T_3098) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3101 = and(_T_3099, _T_3100) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3103 = and(_T_3101, _T_3102) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3104 = or(_T_3096, _T_3103) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3108 = and(_T_3106, _T_3107) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3110 = and(_T_3108, _T_3109) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3111 = or(_T_3104, _T_3110) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3112 = and(_T_3092, _T_3111) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3117 = or(_T_3115, _T_3116) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3121 = and(_T_3119, _T_3120) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3125 = and(_T_3123, _T_3124) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3126 = or(_T_3118, _T_3125) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3130 = and(_T_3128, _T_3129) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3132 = and(_T_3130, _T_3131) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3133 = or(_T_3126, _T_3132) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3134 = and(_T_3114, _T_3133) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3145 = and(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3147 = and(_T_3145, _T_3146) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3148 = or(_T_3140, _T_3147) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3152 = and(_T_3150, _T_3151) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3154 = and(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3155 = or(_T_3148, _T_3154) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3156 = and(_T_3136, _T_3155) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] + node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2886 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[1] <= _T_2977 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[2] <= _T_3068 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[3] <= _T_3159 @[el2_lsu_bus_buffer.scala 469:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3162 = or(_T_3160, _T_3161) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3165 = or(_T_3163, _T_3164) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3168 = or(_T_3166, _T_3167) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3171 = or(_T_3169, _T_3170) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] + node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3177 = or(_T_3175, _T_3176) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3180 = or(_T_3178, _T_3179) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3183 = or(_T_3181, _T_3182) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3186 = or(_T_3184, _T_3185) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3192 = or(_T_3190, _T_3191) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3195 = or(_T_3193, _T_3194) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3198 = or(_T_3196, _T_3197) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3201 = or(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] + node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] + node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3207 = or(_T_3205, _T_3206) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3210 = or(_T_3208, _T_3209) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3213 = or(_T_3211, _T_3212) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3216 = or(_T_3214, _T_3215) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] + node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] + node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3174 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[1] <= _T_3189 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[2] <= _T_3204 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[3] <= _T_3219 @[el2_lsu_bus_buffer.scala 473:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3223 = or(_T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3225 = and(_T_3220, _T_3224) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3229 = or(_T_3227, _T_3228) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3231 = and(_T_3226, _T_3230) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3235 = or(_T_3233, _T_3234) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3237 = and(_T_3232, _T_3236) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3241 = or(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3243 = and(_T_3238, _T_3242) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] + node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] + node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3250 = or(_T_3248, _T_3249) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3252 = and(_T_3247, _T_3251) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3256 = or(_T_3254, _T_3255) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3258 = and(_T_3253, _T_3257) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3262 = or(_T_3260, _T_3261) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3264 = and(_T_3259, _T_3263) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3268 = or(_T_3266, _T_3267) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3270 = and(_T_3265, _T_3269) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] + node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] + node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3277 = or(_T_3275, _T_3276) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3279 = and(_T_3274, _T_3278) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3283 = or(_T_3281, _T_3282) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3285 = and(_T_3280, _T_3284) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3289 = or(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3291 = and(_T_3286, _T_3290) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3295 = or(_T_3293, _T_3294) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3297 = and(_T_3292, _T_3296) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] + node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] + node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3304 = or(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3306 = and(_T_3301, _T_3305) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3310 = or(_T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3312 = and(_T_3307, _T_3311) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3316 = or(_T_3314, _T_3315) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3318 = and(_T_3313, _T_3317) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3322 = or(_T_3320, _T_3321) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3324 = and(_T_3319, _T_3323) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] + node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] + node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3246 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[1] <= _T_3273 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[2] <= _T_3300 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[3] <= _T_3327 @[el2_lsu_bus_buffer.scala 474:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] + node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] + node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3338 @[el2_lsu_bus_buffer.scala 479:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3343 = and(_T_3341, _T_3342) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3352 = and(_T_3350, _T_3351) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3361 = and(_T_3359, _T_3360) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3370 = and(_T_3368, _T_3369) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[el2_lsu_bus_buffer.scala 480:46] + buf_byteen_in[0] <= _T_3347 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[2] <= _T_3365 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[3] <= _T_3374 @[el2_lsu_bus_buffer.scala 480:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3378 = and(_T_3376, _T_3377) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3390 = and(_T_3388, _T_3389) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3396 = and(_T_3394, _T_3395) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[el2_lsu_bus_buffer.scala 482:44] + buf_addr_in[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[2] <= _T_3392 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[3] <= _T_3398 @[el2_lsu_bus_buffer.scala 482:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] + node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] + node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] + buf_dual_in <= _T_3409 @[el2_lsu_bus_buffer.scala 483:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] + node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] + node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] + buf_samedw_in <= _T_3420 @[el2_lsu_bus_buffer.scala 484:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] + node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] + node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3435 @[el2_lsu_bus_buffer.scala 485:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3439 = and(_T_3437, _T_3438) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3444 = and(_T_3442, _T_3443) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3454 = and(_T_3452, _T_3453) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] + node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] + node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3458 @[el2_lsu_bus_buffer.scala 486:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3462 = and(_T_3460, _T_3461) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3468 = and(_T_3466, _T_3467) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3474 = and(_T_3472, _T_3473) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3480 = and(_T_3478, _T_3479) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[el2_lsu_bus_buffer.scala 487:47] + buf_dualtag_in[0] <= _T_3464 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[1] <= _T_3470 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[2] <= _T_3476 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[3] <= _T_3482 @[el2_lsu_bus_buffer.scala 487:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] + node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] + node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3493 @[el2_lsu_bus_buffer.scala 488:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] + node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] + node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] + buf_unsign_in <= _T_3504 @[el2_lsu_bus_buffer.scala 489:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3506 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3509 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3512 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3515 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[el2_lsu_bus_buffer.scala 490:42] + buf_sz_in[0] <= _T_3507 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[1] <= _T_3510 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[2] <= _T_3513 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[3] <= _T_3516 @[el2_lsu_bus_buffer.scala 490:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] + node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] + node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] + buf_write_in <= _T_3527 @[el2_lsu_bus_buffer.scala 491:16] + node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3528 : @[Conditional.scala 40:58] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[0] <= _T_3530 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3534 = and(_T_3532, _T_3533) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3536 = and(_T_3534, _T_3535) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3540 = or(_T_3536, _T_3539) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3541 = and(_T_3531, _T_3540) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3544 = or(_T_3541, _T_3543) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[0] <= _T_3544 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3547 = bits(_T_3546, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[0] <= _T_3550 @[el2_lsu_bus_buffer.scala 500:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_3155 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3155 : @[Conditional.scala 39:67] - node _T_3156 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3157 = mux(_T_3156, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[0] <= _T_3157 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3158 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[0] <= _T_3158 @[el2_lsu_bus_buffer.scala 624:31] + node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3551 : @[Conditional.scala 39:67] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[0] <= _T_3553 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 504:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3159 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3159 : @[Conditional.scala 39:67] - node _T_3160 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3161 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3162 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3163 = and(_T_3161, _T_3162) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3164 = mux(_T_3163, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3165 = mux(_T_3160, UInt<3>("h00"), _T_3164) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[0] <= _T_3165 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3166 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3167 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3168 = and(obuf_merge, _T_3167) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3169 = or(_T_3166, _T_3168) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3170 = and(_T_3169, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3171 = and(_T_3170, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[0] <= _T_3171 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3172 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3173 = or(_T_3172, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[0] <= _T_3173 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3174 = eq(buf_write[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3175 = and(buf_state_en[0], _T_3174) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3176 = and(_T_3175, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3177 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3178 = and(_T_3176, _T_3177) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[0] <= _T_3178 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3179 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[0] <= _T_3179 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3180 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3181 = and(_T_3180, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3182 = and(_T_3181, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[0] <= _T_3182 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3183 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3184 = and(_T_3183, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3185 = and(_T_3184, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[0] <= _T_3185 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3186 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3187 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3188 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3189 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3190 = mux(_T_3187, _T_3188, _T_3189) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3191 = mux(buf_error_en[0], _T_3186, _T_3190) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[0] <= _T_3191 @[el2_lsu_bus_buffer.scala 636:37] + node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3555 : @[Conditional.scala 39:67] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3564 = and(obuf_merge, _T_3563) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3565 = or(_T_3562, _T_3564) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3566 = and(_T_3565, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[0] <= _T_3569 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3570 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3575 = and(_T_3573, _T_3574) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[0] <= _T_3575 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[0] <= _T_3576 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[0] <= _T_3579 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[0] <= _T_3582 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[0] <= _T_3588 @[el2_lsu_bus_buffer.scala 516:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3192 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3192 : @[Conditional.scala 39:67] - node _T_3193 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3194 = not(_T_3193) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3195 = and(buf_write[0], _T_3194) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3196 = or(io.dec_tlu_force_halt, _T_3195) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3197 = bits(_T_3196, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3198 = not(buf_samedw[0]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3199 = and(buf_dual[0], _T_3198) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3200 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3201 = and(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3202 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3203 = and(_T_3201, _T_3202) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3204 = or(buf_ldfwd[0], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3205 = not(buf_samedw[0]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3206 = and(buf_dual[0], _T_3205) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3207 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3208 = and(_T_3206, _T_3207) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3209 = and(_T_3208, buf_ldfwd[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3210 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3211 = and(_T_3209, _T_3210) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3212 = and(_T_3211, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3213 = or(_T_3204, _T_3212) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3214 = mux(_T_3213, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3215 = mux(_T_3203, UInt<3>("h04"), _T_3214) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3216 = mux(_T_3197, UInt<3>("h00"), _T_3215) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[0] <= _T_3216 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3217 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3218 = and(bus_rsp_write, _T_3217) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3219 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3220 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3221 = and(buf_ldfwd[0], _T_3220) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3222 = or(_T_3219, _T_3221) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3223 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3224 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3225 = and(_T_3223, _T_3224) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3226 = and(_T_3225, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3227 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3228 = and(_T_3226, _T_3227) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3229 = or(_T_3222, _T_3228) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3230 = and(bus_rsp_read, _T_3229) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3231 = or(_T_3218, _T_3230) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[0] <= _T_3231 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3232 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3233 = or(_T_3232, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[0] <= _T_3233 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3234 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3235 = and(_T_3234, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[0] <= _T_3235 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3236 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3237 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3238 = and(bus_rsp_read_error, _T_3237) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3239 = and(bus_rsp_read_error, buf_ldfwd[0]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3240 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3241 = and(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3242 = or(_T_3238, _T_3241) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3243 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3244 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3245 = and(_T_3243, _T_3244) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3246 = or(_T_3242, _T_3245) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3247 = and(_T_3236, _T_3246) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[0] <= _T_3247 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3248 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3249 = and(buf_state_en[0], _T_3248) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3250 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3251 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3252 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3253 = mux(_T_3250, _T_3251, _T_3252) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3254 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3255 = mux(_T_3249, _T_3253, _T_3254) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[0] <= _T_3255 @[el2_lsu_bus_buffer.scala 652:37] + node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3589 : @[Conditional.scala 39:67] + node _T_3590 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3593 = and(_T_3590, _T_3592) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3595 = bits(_T_3594, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3598 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3600 = and(_T_3597, _T_3599) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3607 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3609 = and(_T_3606, _T_3608) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = or(_T_3618, _T_3619) @[Mux.scala 27:72] + node _T_3623 = or(_T_3622, _T_3620) @[Mux.scala 27:72] + node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] + wire _T_3625 : UInt<1> @[Mux.scala 27:72] + _T_3625 <= _T_3624 @[Mux.scala 27:72] + node _T_3626 = and(_T_3609, _T_3625) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3628 = and(_T_3626, _T_3627) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3630 = or(_T_3604, _T_3629) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[0] <= _T_3633 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3639 = and(_T_3637, _T_3638) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3640 = or(_T_3636, _T_3639) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3642 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3643 = not(_T_3642) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3644 = and(_T_3641, _T_3643) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3647 = and(_T_3645, _T_3646) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3648 = or(_T_3640, _T_3647) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3650 = or(_T_3635, _T_3649) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[0] <= _T_3650 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[0] <= _T_3652 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[0] <= _T_3654 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3662 = or(_T_3657, _T_3661) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3665 = and(_T_3663, _T_3664) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3666 = or(_T_3662, _T_3665) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3667 = and(_T_3655, _T_3666) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[0] <= _T_3667 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[0] <= _T_3675 @[el2_lsu_bus_buffer.scala 532:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3256 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3256 : @[Conditional.scala 39:67] - node _T_3257 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3258 = or(buf_ldfwd[0], buf_ldfwd[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3259 = or(_T_3258, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3260 = mux(_T_3259, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3261 = mux(_T_3257, UInt<3>("h00"), _T_3260) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[0] <= _T_3261 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3262 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3263 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3264 = and(buf_ldfwd[buf_dualtag[0]], _T_3263) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3265 = or(_T_3262, _T_3264) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3266 = and(bus_rsp_read, _T_3265) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[0] <= _T_3266 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3267 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3268 = or(_T_3267, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[0] <= _T_3268 @[el2_lsu_bus_buffer.scala 658:34] + node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3676 : @[Conditional.scala 39:67] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3680 = bits(_T_3679, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[0] <= _T_3684 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3687 = bits(_T_3686, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3689 = and(_T_3687, _T_3688) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3690 = or(_T_3685, _T_3689) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[0] <= _T_3691 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[0] <= _T_3693 @[el2_lsu_bus_buffer.scala 538:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3269 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3269 : @[Conditional.scala 39:67] - node _T_3270 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3271 = mux(_T_3270, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[0] <= _T_3271 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3272 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3273 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3274 = and(buf_dual[0], _T_3273) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3275 = or(_T_3272, _T_3274) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3276 = or(_T_3275, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[0] <= _T_3276 @[el2_lsu_bus_buffer.scala 662:31] + node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3694 : @[Conditional.scala 39:67] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[0] <= _T_3696 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3700 = or(_T_3697, _T_3699) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[0] <= _T_3701 @[el2_lsu_bus_buffer.scala 542:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3277 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3277 : @[Conditional.scala 39:67] - buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 669:31] + node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3702 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 549:25] skip @[Conditional.scala 39:67] - reg _T_3278 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3278 <= buf_byteen_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[0] <= _T_3278 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3279 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[0] : @[Reg.scala 28:19] - _T_3279 <= buf_data_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[0] <= _T_3279 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3280 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[0] : @[Reg.scala 28:19] - _T_3280 <= buf_nxtstate[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[0] <= _T_3280 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3281 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3281 <= buf_dualtag_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[0] <= _T_3281 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3282 <= buf_dual_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[0] <= _T_3282 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3283 <= buf_samedw_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[0] <= _T_3283 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3284 <= buf_nomerge_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[0] <= _T_3284 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3285 <= buf_dualhi_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[0] <= _T_3285 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3286 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3286 <= buf_sideeffect_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[0] <= _T_3286 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3287 <= buf_unsign_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[0] <= _T_3287 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3288 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3288 <= buf_write_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write[0] <= _T_3288 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3289 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3289 <= buf_sz_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[0] <= _T_3289 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3290 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3290 <= buf_addr_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[0] <= _T_3290 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3291 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[0] : @[Reg.scala 28:19] - _T_3291 <= buf_ldfwd_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[0] <= _T_3291 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3292 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[0] : @[Reg.scala 28:19] - _T_3292 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwdtag[0] <= _T_3292 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3293 = not(buf_rst[0]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3294 = or(buf_error_en[0], buf_rst[0]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3295 = bits(_T_3294, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3296 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3295 : @[Reg.scala 28:19] - _T_3296 <= _T_3293 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_error[0] <= _T_3296 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3297 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3298 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3297)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[0] <= buf_age_in[0][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[1] <= buf_age_in[0][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[2] <= buf_age_in[0][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[3] <= buf_age_in[0][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[0][0] <= _T_3298[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][1] <= _T_3298[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][2] <= _T_3298[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][3] <= _T_3298[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3299 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3300 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3299)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[0] <= buf_rspage_in[0][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[1] <= buf_rspage_in[0][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[2] <= buf_rspage_in[0][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[3] <= buf_rspage_in[0][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[0][0] <= _T_3300[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][1] <= _T_3300[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][2] <= _T_3300[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][3] <= _T_3300[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3301 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3302 = and(ibuf_drain_vld, _T_3301) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[1] <= _T_3302 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3303 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3304 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3305 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3306 = and(_T_3304, _T_3305) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3307 = bits(_T_3306, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3308 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3309 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3310 = mux(_T_3307, _T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3311 = mux(ibuf_drainvec_vld[1], _T_3303, _T_3310) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[1] <= _T_3311 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3312 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3313 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3314 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3315 = and(_T_3313, _T_3314) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3316 = bits(_T_3315, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3317 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3318 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3319 = mux(_T_3316, _T_3317, _T_3318) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3320 = mux(ibuf_drainvec_vld[1], _T_3312, _T_3319) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[1] <= _T_3320 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3321 = mux(ibuf_drainvec_vld[1], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[1] <= _T_3321 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3322 = mux(ibuf_drainvec_vld[1], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[1] <= _T_3322 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3323 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3324 = mux(ibuf_drainvec_vld[1], _T_3323, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[1] <= _T_3324 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3325 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3326 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3327 = and(_T_3325, _T_3326) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3328 = mux(ibuf_drainvec_vld[1], ibuf_dual, _T_3327) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[1] <= _T_3328 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3329 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3330 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3331 = and(_T_3329, _T_3330) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3332 = bits(_T_3331, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3333 = mux(_T_3332, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3334 = mux(ibuf_drainvec_vld[1], ibuf_dualtag, _T_3333) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[1] <= _T_3334 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3335 = mux(ibuf_drainvec_vld[1], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[1] <= _T_3335 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3336 = mux(ibuf_drainvec_vld[1], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[1] <= _T_3336 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3337 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3338 = mux(ibuf_drainvec_vld[1], ibuf_sz, _T_3337) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[1] <= _T_3338 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3339 = mux(ibuf_drainvec_vld[1], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[1] <= _T_3339 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3340 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3340 : @[Conditional.scala 40:58] - node _T_3341 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3342 = mux(_T_3341, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[1] <= _T_3342 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3343 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3344 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3345 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3346 = and(_T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3347 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3348 = and(_T_3346, _T_3347) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3349 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3350 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3351 = and(_T_3349, _T_3350) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3352 = or(_T_3348, _T_3351) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3353 = and(_T_3343, _T_3352) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3354 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3355 = and(ibuf_drain_vld, _T_3354) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3356 = or(_T_3353, _T_3355) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3357 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3358 = and(ibuf_drain_vld, _T_3357) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3359 = bits(_T_3358, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3360 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3361 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3362 = mux(_T_3359, _T_3360, _T_3361) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[1] <= _T_3362 @[el2_lsu_bus_buffer.scala 620:31] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_3363 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3363 : @[Conditional.scala 39:67] - node _T_3364 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3365 = mux(_T_3364, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[1] <= _T_3365 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3366 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[1] <= _T_3366 @[el2_lsu_bus_buffer.scala 624:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3367 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3367 : @[Conditional.scala 39:67] - node _T_3368 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3369 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3370 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3371 = and(_T_3369, _T_3370) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3372 = mux(_T_3371, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3373 = mux(_T_3368, UInt<3>("h00"), _T_3372) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[1] <= _T_3373 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3374 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3375 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3376 = and(obuf_merge, _T_3375) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3377 = or(_T_3374, _T_3376) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3378 = and(_T_3377, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3379 = and(_T_3378, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[1] <= _T_3379 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3380 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3381 = or(_T_3380, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[1] <= _T_3381 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3382 = eq(buf_write[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3383 = and(buf_state_en[1], _T_3382) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3384 = and(_T_3383, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3385 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3386 = and(_T_3384, _T_3385) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3387 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[1] <= _T_3387 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3388 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3389 = and(_T_3388, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3390 = and(_T_3389, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[1] <= _T_3390 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3391 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3392 = and(_T_3391, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3393 = and(_T_3392, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[1] <= _T_3393 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3394 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3395 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3396 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3397 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3398 = mux(_T_3395, _T_3396, _T_3397) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3399 = mux(buf_error_en[1], _T_3394, _T_3398) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[1] <= _T_3399 @[el2_lsu_bus_buffer.scala 636:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3400 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3400 : @[Conditional.scala 39:67] - node _T_3401 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3402 = not(_T_3401) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3403 = and(buf_write[1], _T_3402) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3404 = or(io.dec_tlu_force_halt, _T_3403) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3405 = bits(_T_3404, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3406 = not(buf_samedw[1]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3407 = and(buf_dual[1], _T_3406) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3408 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3409 = and(_T_3407, _T_3408) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3410 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3411 = and(_T_3409, _T_3410) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3412 = or(buf_ldfwd[1], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3413 = not(buf_samedw[1]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3414 = and(buf_dual[1], _T_3413) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3415 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3416 = and(_T_3414, _T_3415) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3417 = and(_T_3416, buf_ldfwd[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3418 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3419 = and(_T_3417, _T_3418) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3420 = and(_T_3419, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3421 = or(_T_3412, _T_3420) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3422 = mux(_T_3421, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3423 = mux(_T_3411, UInt<3>("h04"), _T_3422) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3424 = mux(_T_3405, UInt<3>("h00"), _T_3423) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[1] <= _T_3424 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3425 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3426 = and(bus_rsp_write, _T_3425) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3427 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3428 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3429 = and(buf_ldfwd[1], _T_3428) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3430 = or(_T_3427, _T_3429) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3431 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3432 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3433 = and(_T_3431, _T_3432) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3434 = and(_T_3433, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3435 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3436 = and(_T_3434, _T_3435) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3437 = or(_T_3430, _T_3436) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3438 = and(bus_rsp_read, _T_3437) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3439 = or(_T_3426, _T_3438) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[1] <= _T_3439 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3440 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3441 = or(_T_3440, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[1] <= _T_3441 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3442 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3443 = and(_T_3442, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[1] <= _T_3443 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3444 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3445 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3446 = and(bus_rsp_read_error, _T_3445) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3447 = and(bus_rsp_read_error, buf_ldfwd[1]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3448 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3450 = or(_T_3446, _T_3449) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3451 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3452 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3453 = and(_T_3451, _T_3452) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3454 = or(_T_3450, _T_3453) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3455 = and(_T_3444, _T_3454) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[1] <= _T_3455 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3456 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3457 = and(buf_state_en[1], _T_3456) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3458 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3459 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3460 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3461 = mux(_T_3458, _T_3459, _T_3460) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3462 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3463 = mux(_T_3457, _T_3461, _T_3462) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[1] <= _T_3463 @[el2_lsu_bus_buffer.scala 652:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3464 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3464 : @[Conditional.scala 39:67] - node _T_3465 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3466 = or(buf_ldfwd[1], buf_ldfwd[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3467 = or(_T_3466, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3468 = mux(_T_3467, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3469 = mux(_T_3465, UInt<3>("h00"), _T_3468) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[1] <= _T_3469 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3470 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3471 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3472 = and(buf_ldfwd[buf_dualtag[1]], _T_3471) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3473 = or(_T_3470, _T_3472) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3474 = and(bus_rsp_read, _T_3473) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[1] <= _T_3474 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3475 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3476 = or(_T_3475, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[1] <= _T_3476 @[el2_lsu_bus_buffer.scala 658:34] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3477 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3477 : @[Conditional.scala 39:67] - node _T_3478 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3479 = mux(_T_3478, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[1] <= _T_3479 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3480 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3481 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3482 = and(buf_dual[1], _T_3481) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3483 = or(_T_3480, _T_3482) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3484 = or(_T_3483, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[1] <= _T_3484 @[el2_lsu_bus_buffer.scala 662:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3485 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3485 : @[Conditional.scala 39:67] - buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 669:31] - skip @[Conditional.scala 39:67] - reg _T_3486 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3486 <= buf_byteen_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[1] <= _T_3486 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3487 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[1] : @[Reg.scala 28:19] - _T_3487 <= buf_data_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[1] <= _T_3487 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3488 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[1] : @[Reg.scala 28:19] - _T_3488 <= buf_nxtstate[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[1] <= _T_3488 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3489 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3489 <= buf_dualtag_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[1] <= _T_3489 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3490 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3490 <= buf_dual_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[1] <= _T_3490 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3491 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3491 <= buf_samedw_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[1] <= _T_3491 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3492 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3492 <= buf_nomerge_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[1] <= _T_3492 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3493 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3493 <= buf_dualhi_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[1] <= _T_3493 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3494 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3494 <= buf_sideeffect_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[1] <= _T_3494 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3495 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3495 <= buf_unsign_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[1] <= _T_3495 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3496 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3496 <= buf_write_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write[1] <= _T_3496 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3497 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3497 <= buf_sz_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[1] <= _T_3497 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3498 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3498 <= buf_addr_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[1] <= _T_3498 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3499 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[1] : @[Reg.scala 28:19] - _T_3499 <= buf_ldfwd_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[1] <= _T_3499 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3500 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[1] : @[Reg.scala 28:19] - _T_3500 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwdtag[1] <= _T_3500 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3501 = not(buf_rst[1]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3502 = or(buf_error_en[1], buf_rst[1]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3503 = bits(_T_3502, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3504 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3503 : @[Reg.scala 28:19] - _T_3504 <= _T_3501 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_error[1] <= _T_3504 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3505 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3506 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3505)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[0] <= buf_age_in[1][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[1] <= buf_age_in[1][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[2] <= buf_age_in[1][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[3] <= buf_age_in[1][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[1][0] <= _T_3506[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][1] <= _T_3506[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][2] <= _T_3506[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][3] <= _T_3506[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3507 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3508 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3507)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[0] <= buf_rspage_in[1][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[1] <= buf_rspage_in[1][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[2] <= buf_rspage_in[1][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[3] <= buf_rspage_in[1][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[1][0] <= _T_3508[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][1] <= _T_3508[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][2] <= _T_3508[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][3] <= _T_3508[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3509 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3510 = and(ibuf_drain_vld, _T_3509) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[2] <= _T_3510 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3511 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3512 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3513 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3514 = and(_T_3512, _T_3513) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3515 = bits(_T_3514, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3516 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3517 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3518 = mux(_T_3515, _T_3516, _T_3517) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3519 = mux(ibuf_drainvec_vld[2], _T_3511, _T_3518) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[2] <= _T_3519 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3520 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3521 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3522 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3523 = and(_T_3521, _T_3522) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3524 = bits(_T_3523, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3525 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3526 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3527 = mux(_T_3524, _T_3525, _T_3526) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3528 = mux(ibuf_drainvec_vld[2], _T_3520, _T_3527) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[2] <= _T_3528 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3529 = mux(ibuf_drainvec_vld[2], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[2] <= _T_3529 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3530 = mux(ibuf_drainvec_vld[2], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[2] <= _T_3530 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3531 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3532 = mux(ibuf_drainvec_vld[2], _T_3531, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[2] <= _T_3532 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3533 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3534 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3535 = and(_T_3533, _T_3534) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3536 = mux(ibuf_drainvec_vld[2], ibuf_dual, _T_3535) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[2] <= _T_3536 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3538 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3540 = bits(_T_3539, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3541 = mux(_T_3540, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3542 = mux(ibuf_drainvec_vld[2], ibuf_dualtag, _T_3541) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[2] <= _T_3542 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3543 = mux(ibuf_drainvec_vld[2], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[2] <= _T_3543 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3544 = mux(ibuf_drainvec_vld[2], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[2] <= _T_3544 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3545 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3546 = mux(ibuf_drainvec_vld[2], ibuf_sz, _T_3545) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[2] <= _T_3546 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3547 = mux(ibuf_drainvec_vld[2], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[2] <= _T_3547 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3548 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3548 : @[Conditional.scala 40:58] - node _T_3549 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3550 = mux(_T_3549, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[2] <= _T_3550 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3551 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3552 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3553 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3554 = and(_T_3552, _T_3553) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3555 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3556 = and(_T_3554, _T_3555) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3557 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3558 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3560 = or(_T_3556, _T_3559) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3561 = and(_T_3551, _T_3560) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3562 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3563 = and(ibuf_drain_vld, _T_3562) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3564 = or(_T_3561, _T_3563) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[2] <= _T_3564 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3565 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3566 = and(ibuf_drain_vld, _T_3565) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3567 = bits(_T_3566, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3568 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3569 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3570 = mux(_T_3567, _T_3568, _T_3569) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[2] <= _T_3570 @[el2_lsu_bus_buffer.scala 620:31] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_3571 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3571 : @[Conditional.scala 39:67] - node _T_3572 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3573 = mux(_T_3572, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[2] <= _T_3573 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3574 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[2] <= _T_3574 @[el2_lsu_bus_buffer.scala 624:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3575 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3575 : @[Conditional.scala 39:67] - node _T_3576 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3577 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3578 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3579 = and(_T_3577, _T_3578) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3580 = mux(_T_3579, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3581 = mux(_T_3576, UInt<3>("h00"), _T_3580) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[2] <= _T_3581 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3582 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3583 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3584 = and(obuf_merge, _T_3583) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3585 = or(_T_3582, _T_3584) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3586 = and(_T_3585, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3587 = and(_T_3586, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[2] <= _T_3587 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3588 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3589 = or(_T_3588, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[2] <= _T_3589 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3590 = eq(buf_write[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3591 = and(buf_state_en[2], _T_3590) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3592 = and(_T_3591, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3593 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3594 = and(_T_3592, _T_3593) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[2] <= _T_3594 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3595 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[2] <= _T_3595 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3596 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3597 = and(_T_3596, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3598 = and(_T_3597, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[2] <= _T_3598 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3599 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3600 = and(_T_3599, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3601 = and(_T_3600, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[2] <= _T_3601 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3602 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3603 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3604 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3605 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3606 = mux(_T_3603, _T_3604, _T_3605) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3607 = mux(buf_error_en[2], _T_3602, _T_3606) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[2] <= _T_3607 @[el2_lsu_bus_buffer.scala 636:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3608 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3608 : @[Conditional.scala 39:67] - node _T_3609 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3610 = not(_T_3609) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3611 = and(buf_write[2], _T_3610) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3612 = or(io.dec_tlu_force_halt, _T_3611) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3613 = bits(_T_3612, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3614 = not(buf_samedw[2]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3615 = and(buf_dual[2], _T_3614) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3616 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3617 = and(_T_3615, _T_3616) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3618 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3619 = and(_T_3617, _T_3618) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3620 = or(buf_ldfwd[2], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3621 = not(buf_samedw[2]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3622 = and(buf_dual[2], _T_3621) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3623 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3624 = and(_T_3622, _T_3623) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3625 = and(_T_3624, buf_ldfwd[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3626 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3627 = and(_T_3625, _T_3626) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3628 = and(_T_3627, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3629 = or(_T_3620, _T_3628) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3630 = mux(_T_3629, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3631 = mux(_T_3619, UInt<3>("h04"), _T_3630) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3632 = mux(_T_3613, UInt<3>("h00"), _T_3631) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[2] <= _T_3632 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3633 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3634 = and(bus_rsp_write, _T_3633) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3635 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3636 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3637 = and(buf_ldfwd[2], _T_3636) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3638 = or(_T_3635, _T_3637) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3639 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3640 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3641 = and(_T_3639, _T_3640) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3642 = and(_T_3641, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3643 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3644 = and(_T_3642, _T_3643) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3645 = or(_T_3638, _T_3644) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3646 = and(bus_rsp_read, _T_3645) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3647 = or(_T_3634, _T_3646) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[2] <= _T_3647 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3648 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3649 = or(_T_3648, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[2] <= _T_3649 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3650 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3651 = and(_T_3650, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[2] <= _T_3651 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3652 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3653 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3654 = and(bus_rsp_read_error, _T_3653) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3655 = and(bus_rsp_read_error, buf_ldfwd[2]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3656 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3657 = and(_T_3655, _T_3656) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3658 = or(_T_3654, _T_3657) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3659 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3660 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3662 = or(_T_3658, _T_3661) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3663 = and(_T_3652, _T_3662) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[2] <= _T_3663 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3664 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3665 = and(buf_state_en[2], _T_3664) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3666 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3667 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3668 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3669 = mux(_T_3666, _T_3667, _T_3668) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3670 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3671 = mux(_T_3665, _T_3669, _T_3670) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[2] <= _T_3671 @[el2_lsu_bus_buffer.scala 652:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3672 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3672 : @[Conditional.scala 39:67] - node _T_3673 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3674 = or(buf_ldfwd[2], buf_ldfwd[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3675 = or(_T_3674, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3676 = mux(_T_3675, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3677 = mux(_T_3673, UInt<3>("h00"), _T_3676) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[2] <= _T_3677 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3678 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3679 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3680 = and(buf_ldfwd[buf_dualtag[2]], _T_3679) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3682 = and(bus_rsp_read, _T_3681) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[2] <= _T_3682 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3683 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3684 = or(_T_3683, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[2] <= _T_3684 @[el2_lsu_bus_buffer.scala 658:34] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3685 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3685 : @[Conditional.scala 39:67] - node _T_3686 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3687 = mux(_T_3686, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[2] <= _T_3687 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3688 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3689 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3690 = and(buf_dual[2], _T_3689) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3691 = or(_T_3688, _T_3690) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3692 = or(_T_3691, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[2] <= _T_3692 @[el2_lsu_bus_buffer.scala 662:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3693 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3693 : @[Conditional.scala 39:67] - buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 669:31] - skip @[Conditional.scala 39:67] - reg _T_3694 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3694 <= buf_byteen_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[2] <= _T_3694 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3695 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[2] : @[Reg.scala 28:19] - _T_3695 <= buf_data_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[2] <= _T_3695 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3696 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[2] : @[Reg.scala 28:19] - _T_3696 <= buf_nxtstate[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[2] <= _T_3696 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3697 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3697 <= buf_dualtag_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[2] <= _T_3697 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3698 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3698 <= buf_dual_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[2] <= _T_3698 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3699 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3699 <= buf_samedw_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[2] <= _T_3699 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3700 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3700 <= buf_nomerge_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[2] <= _T_3700 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3701 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3701 <= buf_dualhi_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[2] <= _T_3701 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3702 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3702 <= buf_sideeffect_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[2] <= _T_3702 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3703 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3703 <= buf_unsign_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[2] <= _T_3703 @[el2_lsu_bus_buffer.scala 683:31] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3704 <= buf_write_in[2] @[Reg.scala 28:23] + when _T_3703 : @[Reg.scala 28:19] + _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write[2] <= _T_3704 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3705 <= buf_sz_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[2] <= _T_3705 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3706 <= buf_addr_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[2] <= _T_3706 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[2] : @[Reg.scala 28:19] - _T_3707 <= buf_ldfwd_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[2] <= _T_3707 @[el2_lsu_bus_buffer.scala 687:31] + buf_state[0] <= _T_3704 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3705 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[0] <= _T_3705 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3706 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[0] <= _T_3706 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[2] : @[Reg.scala 28:19] - _T_3708 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + when _T_3707 : @[Reg.scala 28:19] + _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[2] <= _T_3708 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3709 = not(buf_rst[2]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3710 = or(buf_error_en[2], buf_rst[2]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3711 = bits(_T_3710, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3712 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3711 : @[Reg.scala 28:19] - _T_3712 <= _T_3709 @[Reg.scala 28:23] + buf_dualtag[0] <= _T_3708 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3710 : @[Reg.scala 28:19] + _T_3711 <= _T_3709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_error[2] <= _T_3712 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3713 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3714 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3713)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[0] <= buf_age_in[2][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[1] <= buf_age_in[2][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[2] <= buf_age_in[2][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[3] <= buf_age_in[2][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[2][0] <= _T_3714[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][1] <= _T_3714[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][2] <= _T_3714[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][3] <= _T_3714[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3715 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3716 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3715)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[0] <= buf_rspage_in[2][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[1] <= buf_rspage_in[2][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[2] <= buf_rspage_in[2][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[3] <= buf_rspage_in[2][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[2][0] <= _T_3716[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][1] <= _T_3716[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][2] <= _T_3716[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][3] <= _T_3716[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3717 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3718 = and(ibuf_drain_vld, _T_3717) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[3] <= _T_3718 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3719 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3720 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3721 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3722 = and(_T_3720, _T_3721) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3723 = bits(_T_3722, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3724 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3725 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3726 = mux(_T_3723, _T_3724, _T_3725) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3727 = mux(ibuf_drainvec_vld[3], _T_3719, _T_3726) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[3] <= _T_3727 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3728 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3729 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3730 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3731 = and(_T_3729, _T_3730) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3732 = bits(_T_3731, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3733 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3734 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3735 = mux(_T_3732, _T_3733, _T_3734) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3736 = mux(ibuf_drainvec_vld[3], _T_3728, _T_3735) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[3] <= _T_3736 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3737 = mux(ibuf_drainvec_vld[3], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[3] <= _T_3737 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3738 = mux(ibuf_drainvec_vld[3], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[3] <= _T_3738 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3739 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3740 = mux(ibuf_drainvec_vld[3], _T_3739, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[3] <= _T_3740 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3741 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3742 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3743 = and(_T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3744 = mux(ibuf_drainvec_vld[3], ibuf_dual, _T_3743) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[3] <= _T_3744 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3745 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3746 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3747 = and(_T_3745, _T_3746) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3748 = bits(_T_3747, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3749 = mux(_T_3748, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3750 = mux(ibuf_drainvec_vld[3], ibuf_dualtag, _T_3749) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[3] <= _T_3750 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3751 = mux(ibuf_drainvec_vld[3], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[3] <= _T_3751 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3752 = mux(ibuf_drainvec_vld[3], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[3] <= _T_3752 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3753 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3754 = mux(ibuf_drainvec_vld[3], ibuf_sz, _T_3753) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[3] <= _T_3754 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3755 = mux(ibuf_drainvec_vld[3], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[3] <= _T_3755 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3756 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3756 : @[Conditional.scala 40:58] - node _T_3757 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3758 = mux(_T_3757, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[3] <= _T_3758 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3759 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3760 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3761 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3762 = and(_T_3760, _T_3761) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3763 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3764 = and(_T_3762, _T_3763) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3765 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3766 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3767 = and(_T_3765, _T_3766) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3768 = or(_T_3764, _T_3767) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3769 = and(_T_3759, _T_3768) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3770 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3771 = and(ibuf_drain_vld, _T_3770) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3772 = or(_T_3769, _T_3771) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[3] <= _T_3772 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3773 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3774 = and(ibuf_drain_vld, _T_3773) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3775 = bits(_T_3774, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3776 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3777 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3778 = mux(_T_3775, _T_3776, _T_3777) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[3] <= _T_3778 @[el2_lsu_bus_buffer.scala 620:31] + buf_dual[0] <= _T_3711 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3713 : @[Reg.scala 28:19] + _T_3714 <= _T_3712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3714 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3716 : @[Reg.scala 28:19] + _T_3717 <= _T_3715 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3717 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3719 : @[Reg.scala 28:19] + _T_3720 <= _T_3718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3720 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3721 : @[Conditional.scala 40:58] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[1] <= _T_3723 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3727 = and(_T_3725, _T_3726) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3729 = and(_T_3727, _T_3728) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3733 = or(_T_3729, _T_3732) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3734 = and(_T_3724, _T_3733) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3737 = or(_T_3734, _T_3736) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[1] <= _T_3737 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3740 = bits(_T_3739, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[1] <= _T_3743 @[el2_lsu_bus_buffer.scala 500:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_3779 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3779 : @[Conditional.scala 39:67] - node _T_3780 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3781 = mux(_T_3780, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[3] <= _T_3781 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3782 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[3] <= _T_3782 @[el2_lsu_bus_buffer.scala 624:31] + node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3744 : @[Conditional.scala 39:67] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[1] <= _T_3746 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 504:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3783 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3783 : @[Conditional.scala 39:67] - node _T_3784 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3785 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3786 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3787 = and(_T_3785, _T_3786) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3788 = mux(_T_3787, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3789 = mux(_T_3784, UInt<3>("h00"), _T_3788) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[3] <= _T_3789 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3790 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3791 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3792 = and(obuf_merge, _T_3791) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3793 = or(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3794 = and(_T_3793, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3795 = and(_T_3794, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[3] <= _T_3795 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3796 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3797 = or(_T_3796, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[3] <= _T_3797 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3798 = eq(buf_write[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3799 = and(buf_state_en[3], _T_3798) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3800 = and(_T_3799, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3801 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3802 = and(_T_3800, _T_3801) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[3] <= _T_3802 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3803 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[3] <= _T_3803 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3804 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3805 = and(_T_3804, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3806 = and(_T_3805, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[3] <= _T_3806 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3807 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3808 = and(_T_3807, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3809 = and(_T_3808, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[3] <= _T_3809 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3810 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3811 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3812 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3813 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3814 = mux(_T_3811, _T_3812, _T_3813) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3815 = mux(buf_error_en[3], _T_3810, _T_3814) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[3] <= _T_3815 @[el2_lsu_bus_buffer.scala 636:37] + node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3748 : @[Conditional.scala 39:67] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3752 = and(_T_3750, _T_3751) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3757 = and(obuf_merge, _T_3756) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3758 = or(_T_3755, _T_3757) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3759 = and(_T_3758, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[1] <= _T_3762 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3763 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3768 = and(_T_3766, _T_3767) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[1] <= _T_3768 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[1] <= _T_3769 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[1] <= _T_3772 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[1] <= _T_3775 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[1] <= _T_3781 @[el2_lsu_bus_buffer.scala 516:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3816 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3816 : @[Conditional.scala 39:67] - node _T_3817 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3818 = not(_T_3817) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3819 = and(buf_write[3], _T_3818) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3820 = or(io.dec_tlu_force_halt, _T_3819) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3821 = bits(_T_3820, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3822 = not(buf_samedw[3]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3823 = and(buf_dual[3], _T_3822) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3824 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3825 = and(_T_3823, _T_3824) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3826 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3827 = and(_T_3825, _T_3826) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3828 = or(buf_ldfwd[3], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3829 = not(buf_samedw[3]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3830 = and(buf_dual[3], _T_3829) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3831 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3833 = and(_T_3832, buf_ldfwd[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3834 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3835 = and(_T_3833, _T_3834) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3836 = and(_T_3835, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3837 = or(_T_3828, _T_3836) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3838 = mux(_T_3837, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3839 = mux(_T_3827, UInt<3>("h04"), _T_3838) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3840 = mux(_T_3821, UInt<3>("h00"), _T_3839) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[3] <= _T_3840 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3841 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3842 = and(bus_rsp_write, _T_3841) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3843 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3844 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3845 = and(buf_ldfwd[3], _T_3844) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3846 = or(_T_3843, _T_3845) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3847 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3848 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3849 = and(_T_3847, _T_3848) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3850 = and(_T_3849, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3851 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3852 = and(_T_3850, _T_3851) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3853 = or(_T_3846, _T_3852) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3854 = and(bus_rsp_read, _T_3853) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3855 = or(_T_3842, _T_3854) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[3] <= _T_3855 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3856 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3857 = or(_T_3856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[3] <= _T_3857 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3858 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3859 = and(_T_3858, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[3] <= _T_3859 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3860 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3861 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3862 = and(bus_rsp_read_error, _T_3861) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3863 = and(bus_rsp_read_error, buf_ldfwd[3]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3864 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3865 = and(_T_3863, _T_3864) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3866 = or(_T_3862, _T_3865) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3867 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3868 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3869 = and(_T_3867, _T_3868) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3870 = or(_T_3866, _T_3869) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3871 = and(_T_3860, _T_3870) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[3] <= _T_3871 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3872 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3873 = and(buf_state_en[3], _T_3872) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3874 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3875 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3876 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3877 = mux(_T_3874, _T_3875, _T_3876) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3878 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3879 = mux(_T_3873, _T_3877, _T_3878) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[3] <= _T_3879 @[el2_lsu_bus_buffer.scala 652:37] + node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3782 : @[Conditional.scala 39:67] + node _T_3783 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3786 = and(_T_3783, _T_3785) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3788 = bits(_T_3787, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3791 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3793 = and(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3800 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3802 = and(_T_3799, _T_3801) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3821 = and(_T_3819, _T_3820) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3823 = or(_T_3797, _T_3822) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[1] <= _T_3826 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3833 = or(_T_3829, _T_3832) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3835 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3836 = not(_T_3835) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3837 = and(_T_3834, _T_3836) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3840 = and(_T_3838, _T_3839) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3841 = or(_T_3833, _T_3840) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3843 = or(_T_3828, _T_3842) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[1] <= _T_3843 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[1] <= _T_3845 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[1] <= _T_3847 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3854 = and(_T_3852, _T_3853) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3855 = or(_T_3850, _T_3854) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3858 = and(_T_3856, _T_3857) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3859 = or(_T_3855, _T_3858) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3860 = and(_T_3848, _T_3859) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[1] <= _T_3860 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[1] <= _T_3868 @[el2_lsu_bus_buffer.scala 532:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3880 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3880 : @[Conditional.scala 39:67] - node _T_3881 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3882 = or(buf_ldfwd[3], buf_ldfwd[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3883 = or(_T_3882, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3884 = mux(_T_3883, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3885 = mux(_T_3881, UInt<3>("h00"), _T_3884) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[3] <= _T_3885 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3886 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3887 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3888 = and(buf_ldfwd[buf_dualtag[3]], _T_3887) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3889 = or(_T_3886, _T_3888) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3890 = and(bus_rsp_read, _T_3889) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[3] <= _T_3890 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3891 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3892 = or(_T_3891, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[3] <= _T_3892 @[el2_lsu_bus_buffer.scala 658:34] + node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3869 : @[Conditional.scala 39:67] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3873 = bits(_T_3872, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3874 = or(_T_3871, _T_3873) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[1] <= _T_3877 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3880 = bits(_T_3879, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3882 = and(_T_3880, _T_3881) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3883 = or(_T_3878, _T_3882) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[1] <= _T_3884 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[1] <= _T_3886 @[el2_lsu_bus_buffer.scala 538:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3893 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3893 : @[Conditional.scala 39:67] - node _T_3894 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3895 = mux(_T_3894, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[3] <= _T_3895 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3896 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3897 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3898 = and(buf_dual[3], _T_3897) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3899 = or(_T_3896, _T_3898) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3900 = or(_T_3899, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[3] <= _T_3900 @[el2_lsu_bus_buffer.scala 662:31] + node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3887 : @[Conditional.scala 39:67] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[1] <= _T_3889 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3893 = or(_T_3890, _T_3892) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[1] <= _T_3894 @[el2_lsu_bus_buffer.scala 542:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3901 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3901 : @[Conditional.scala 39:67] - buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 669:31] + node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3895 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 549:25] skip @[Conditional.scala 39:67] - reg _T_3902 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3902 <= buf_byteen_in[3] @[Reg.scala 28:23] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3896 : @[Reg.scala 28:19] + _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen[3] <= _T_3902 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3903 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[3] : @[Reg.scala 28:19] - _T_3903 <= buf_data_in[3] @[Reg.scala 28:23] + buf_state[1] <= _T_3897 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3898 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[1] <= _T_3898 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3899 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[1] <= _T_3899 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3900 : @[Reg.scala 28:19] + _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_data[3] <= _T_3903 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3904 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[3] : @[Reg.scala 28:19] - _T_3904 <= buf_nxtstate[3] @[Reg.scala 28:23] + buf_dualtag[1] <= _T_3901 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3903 : @[Reg.scala 28:19] + _T_3904 <= _T_3902 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[3] <= _T_3904 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3905 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3905 <= buf_dualtag_in[3] @[Reg.scala 28:23] + buf_dual[1] <= _T_3904 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3906 : @[Reg.scala 28:19] + _T_3907 <= _T_3905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[3] <= _T_3905 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3906 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3906 <= buf_dual_in[3] @[Reg.scala 28:23] + buf_samedw[1] <= _T_3907 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3909 : @[Reg.scala 28:19] + _T_3910 <= _T_3908 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[3] <= _T_3906 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3907 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3907 <= buf_samedw_in[3] @[Reg.scala 28:23] + buf_nomerge[1] <= _T_3910 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3912 : @[Reg.scala 28:19] + _T_3913 <= _T_3911 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[3] <= _T_3907 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3908 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3908 <= buf_nomerge_in[3] @[Reg.scala 28:23] + buf_dualhi[1] <= _T_3913 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3914 : @[Conditional.scala 40:58] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[2] <= _T_3916 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3920 = and(_T_3918, _T_3919) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3922 = and(_T_3920, _T_3921) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3926 = or(_T_3922, _T_3925) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3927 = and(_T_3917, _T_3926) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3930 = or(_T_3927, _T_3929) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[2] <= _T_3930 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3933 = bits(_T_3932, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[2] <= _T_3936 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3937 : @[Conditional.scala 39:67] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[2] <= _T_3939 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3941 : @[Conditional.scala 39:67] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3950 = and(obuf_merge, _T_3949) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3951 = or(_T_3948, _T_3950) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3952 = and(_T_3951, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[2] <= _T_3955 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3956 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3961 = and(_T_3959, _T_3960) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[2] <= _T_3961 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[2] <= _T_3962 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[2] <= _T_3965 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[2] <= _T_3968 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[2] <= _T_3974 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3975 : @[Conditional.scala 39:67] + node _T_3976 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3979 = and(_T_3976, _T_3978) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3981 = bits(_T_3980, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3984 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3986 = and(_T_3983, _T_3985) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3993 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3995 = and(_T_3992, _T_3994) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4007 = mux(_T_4002, _T_4003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4008 = or(_T_4004, _T_4005) @[Mux.scala 27:72] + node _T_4009 = or(_T_4008, _T_4006) @[Mux.scala 27:72] + node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] + wire _T_4011 : UInt<1> @[Mux.scala 27:72] + _T_4011 <= _T_4010 @[Mux.scala 27:72] + node _T_4012 = and(_T_3995, _T_4011) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4014 = and(_T_4012, _T_4013) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4016 = or(_T_3990, _T_4015) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[2] <= _T_4019 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4025 = and(_T_4023, _T_4024) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4026 = or(_T_4022, _T_4025) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4028 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4029 = not(_T_4028) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4030 = and(_T_4027, _T_4029) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4033 = and(_T_4031, _T_4032) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4034 = or(_T_4026, _T_4033) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4036 = or(_T_4021, _T_4035) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[2] <= _T_4036 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[2] <= _T_4038 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[2] <= _T_4040 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4047 = and(_T_4045, _T_4046) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4048 = or(_T_4043, _T_4047) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4051 = and(_T_4049, _T_4050) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4052 = or(_T_4048, _T_4051) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4053 = and(_T_4041, _T_4052) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[2] <= _T_4053 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[2] <= _T_4061 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4062 : @[Conditional.scala 39:67] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4066 = bits(_T_4065, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4067 = or(_T_4064, _T_4066) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[2] <= _T_4070 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4073 = bits(_T_4072, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4075 = and(_T_4073, _T_4074) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4076 = or(_T_4071, _T_4075) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[2] <= _T_4077 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[2] <= _T_4079 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4080 : @[Conditional.scala 39:67] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[2] <= _T_4082 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4086 = or(_T_4083, _T_4085) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[2] <= _T_4087 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4088 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4089 : @[Reg.scala 28:19] + _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[3] <= _T_3908 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3909 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3909 <= buf_dualhi_in[3] @[Reg.scala 28:23] + buf_state[2] <= _T_4090 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4091 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[2] <= _T_4091 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4092 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[2] <= _T_4092 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[3] <= _T_3909 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3910 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3910 <= buf_sideeffect_in[3] @[Reg.scala 28:23] + buf_dualtag[2] <= _T_4094 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sideeffect[3] <= _T_3910 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3911 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3911 <= buf_unsign_in[3] @[Reg.scala 28:23] + buf_dual[2] <= _T_4097 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_unsign[3] <= _T_3911 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3912 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3912 <= buf_write_in[3] @[Reg.scala 28:23] + buf_samedw[2] <= _T_4100 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write[3] <= _T_3912 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3913 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3913 <= buf_sz_in[3] @[Reg.scala 28:23] + buf_nomerge[2] <= _T_4103 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4105 : @[Reg.scala 28:19] + _T_4106 <= _T_4104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sz[3] <= _T_3913 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3914 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3914 <= buf_addr_in[3] @[Reg.scala 28:23] + buf_dualhi[2] <= _T_4106 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4107 : @[Conditional.scala 40:58] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[3] <= _T_4109 @[el2_lsu_bus_buffer.scala 496:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_4113 = and(_T_4111, _T_4112) @[el2_lsu_bus_buffer.scala 497:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_4115 = and(_T_4113, _T_4114) @[el2_lsu_bus_buffer.scala 497:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 497:161] + node _T_4119 = or(_T_4115, _T_4118) @[el2_lsu_bus_buffer.scala 497:132] + node _T_4120 = and(_T_4110, _T_4119) @[el2_lsu_bus_buffer.scala 497:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[el2_lsu_bus_buffer.scala 497:201] + node _T_4123 = or(_T_4120, _T_4122) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[3] <= _T_4123 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 499:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[el2_lsu_bus_buffer.scala 500:47] + node _T_4126 = bits(_T_4125, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[3] <= _T_4129 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4130 : @[Conditional.scala 39:67] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[3] <= _T_4132 @[el2_lsu_bus_buffer.scala 503:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4134 : @[Conditional.scala 39:67] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_4138 = and(_T_4136, _T_4137) @[el2_lsu_bus_buffer.scala 507:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 507:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_4143 = and(obuf_merge, _T_4142) @[el2_lsu_bus_buffer.scala 508:91] + node _T_4144 = or(_T_4141, _T_4143) @[el2_lsu_bus_buffer.scala 508:77] + node _T_4145 = and(_T_4144, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 509:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[3] <= _T_4148 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_4149 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 512:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[el2_lsu_bus_buffer.scala 512:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_4154 = and(_T_4152, _T_4153) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[3] <= _T_4154 @[el2_lsu_bus_buffer.scala 512:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[3] <= _T_4155 @[el2_lsu_bus_buffer.scala 513:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[3] <= _T_4158 @[el2_lsu_bus_buffer.scala 514:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[3] <= _T_4161 @[el2_lsu_bus_buffer.scala 515:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[el2_lsu_bus_buffer.scala 516:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[3] <= _T_4167 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4168 : @[Conditional.scala 39:67] + node _T_4169 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 519:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_4172 = and(_T_4169, _T_4171) @[el2_lsu_bus_buffer.scala 519:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[el2_lsu_bus_buffer.scala 519:55] + node _T_4174 = bits(_T_4173, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[el2_lsu_bus_buffer.scala 520:28] + node _T_4177 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 520:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_4179 = and(_T_4176, _T_4178) @[el2_lsu_bus_buffer.scala 520:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_4181 = and(_T_4179, _T_4180) @[el2_lsu_bus_buffer.scala 520:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 521:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[el2_lsu_bus_buffer.scala 521:68] + node _T_4186 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 521:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_4188 = and(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 521:85] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4200 = mux(_T_4195, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4201 = or(_T_4197, _T_4198) @[Mux.scala 27:72] + node _T_4202 = or(_T_4201, _T_4199) @[Mux.scala 27:72] + node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] + wire _T_4204 : UInt<1> @[Mux.scala 27:72] + _T_4204 <= _T_4203 @[Mux.scala 27:72] + node _T_4205 = and(_T_4188, _T_4204) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4207 = and(_T_4205, _T_4206) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4209 = or(_T_4183, _T_4208) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[3] <= _T_4212 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4218 = and(_T_4216, _T_4217) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4219 = or(_T_4215, _T_4218) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4221 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4222 = not(_T_4221) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4223 = and(_T_4220, _T_4222) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4226 = and(_T_4224, _T_4225) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4227 = or(_T_4219, _T_4226) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4229 = or(_T_4214, _T_4228) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[3] <= _T_4231 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[3] <= _T_4233 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4240 = and(_T_4238, _T_4239) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4241 = or(_T_4236, _T_4240) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4244 = and(_T_4242, _T_4243) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4245 = or(_T_4241, _T_4244) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4246 = and(_T_4234, _T_4245) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[3] <= _T_4246 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[3] <= _T_4254 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4255 : @[Conditional.scala 39:67] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4259 = bits(_T_4258, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4260 = or(_T_4257, _T_4259) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[3] <= _T_4263 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4266 = bits(_T_4265, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4268 = and(_T_4266, _T_4267) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4269 = or(_T_4264, _T_4268) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[3] <= _T_4270 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[3] <= _T_4272 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4273 : @[Conditional.scala 39:67] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[3] <= _T_4275 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4279 = or(_T_4276, _T_4278) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[3] <= _T_4280 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4281 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_addr[3] <= _T_3914 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3915 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[3] : @[Reg.scala 28:19] - _T_3915 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + buf_state[3] <= _T_4283 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4284 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[3] <= _T_4284 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4285 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[3] <= _T_4285 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwd[3] <= _T_3915 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3916 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[3] : @[Reg.scala 28:19] - _T_3916 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + buf_dualtag[3] <= _T_4287 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4289 : @[Reg.scala 28:19] + _T_4290 <= _T_4288 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[3] <= _T_3916 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3917 = not(buf_rst[3]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3918 = or(buf_error_en[3], buf_rst[3]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3919 = bits(_T_3918, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3920 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3919 : @[Reg.scala 28:19] - _T_3920 <= _T_3917 @[Reg.scala 28:23] + buf_dual[3] <= _T_4290 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4292 : @[Reg.scala 28:19] + _T_4293 <= _T_4291 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_error[3] <= _T_3920 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3921 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3922 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3921)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[0] <= buf_age_in[3][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[1] <= buf_age_in[3][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[2] <= buf_age_in[3][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[3] <= buf_age_in[3][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[3][0] <= _T_3922[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][1] <= _T_3922[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][2] <= _T_3922[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][3] <= _T_3922[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3923 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3924 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3923)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[0] <= buf_rspage_in[3][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[1] <= buf_rspage_in[3][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[2] <= buf_rspage_in[3][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[3] <= buf_rspage_in[3][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[3][0] <= _T_3924[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][1] <= _T_3924[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][2] <= _T_3924[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][3] <= _T_3924[3] @[el2_lsu_bus_buffer.scala 691:31] - node _T_3925 = dshl(io.lsu_busreq_m, io.ldst_dual_m) @[el2_lsu_bus_buffer.scala 696:45] - node _T_3926 = dshl(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 696:83] - node _T_3927 = add(_T_3925, _T_3926) @[el2_lsu_bus_buffer.scala 696:64] - node _T_3928 = tail(_T_3927, 1) @[el2_lsu_bus_buffer.scala 696:64] - node _T_3929 = add(_T_3928, ibuf_valid) @[el2_lsu_bus_buffer.scala 696:102] - node _T_3930 = tail(_T_3929, 1) @[el2_lsu_bus_buffer.scala 696:102] - node _T_3931 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3932 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3933 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3934 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3935 = add(_T_3931, _T_3932) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3936 = tail(_T_3935, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3937 = add(_T_3936, _T_3933) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3938 = tail(_T_3937, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3939 = add(_T_3938, _T_3934) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3940 = tail(_T_3939, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3941 = add(_T_3930, _T_3940) @[el2_lsu_bus_buffer.scala 696:115] - node _T_3942 = tail(_T_3941, 1) @[el2_lsu_bus_buffer.scala 696:115] - buf_numvld_any <= _T_3942 @[el2_lsu_bus_buffer.scala 696:25] - node _T_3943 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3944 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3946 = and(_T_3945, buf_write[0]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3947 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3948 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3949 = and(_T_3947, _T_3948) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3950 = and(_T_3949, buf_write[1]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3951 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3952 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3953 = and(_T_3951, _T_3952) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3954 = and(_T_3953, buf_write[2]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3955 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3956 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3957 = and(_T_3955, _T_3956) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3958 = and(_T_3957, buf_write[3]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3959 = add(_T_3946, _T_3950) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3960 = tail(_T_3959, 1) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3961 = add(_T_3960, _T_3954) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3962 = tail(_T_3961, 1) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3963 = add(_T_3962, _T_3958) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3964 = tail(_T_3963, 1) @[el2_lsu_bus_buffer.scala 698:158] - buf_numvld_wrcmd_any <= _T_3964 @[el2_lsu_bus_buffer.scala 698:25] - node _T_3965 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3966 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3967 = and(_T_3965, _T_3966) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3968 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3969 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3970 = and(_T_3968, _T_3969) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3971 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3972 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3973 = and(_T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3974 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3975 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3976 = and(_T_3974, _T_3975) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3977 = add(_T_3967, _T_3970) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3978 = tail(_T_3977, 1) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3979 = add(_T_3978, _T_3973) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3980 = tail(_T_3979, 1) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3981 = add(_T_3980, _T_3976) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3982 = tail(_T_3981, 1) @[el2_lsu_bus_buffer.scala 699:158] - buf_numvld_cmd_any <= _T_3982 @[el2_lsu_bus_buffer.scala 699:25] - node _T_3983 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3984 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3985 = and(_T_3983, _T_3984) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3986 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3987 = or(_T_3985, _T_3986) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3988 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3989 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3990 = and(_T_3988, _T_3989) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3991 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3992 = or(_T_3990, _T_3991) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3993 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3994 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3995 = and(_T_3993, _T_3994) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3996 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3997 = or(_T_3995, _T_3996) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3998 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3999 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_4000 = and(_T_3998, _T_3999) @[el2_lsu_bus_buffer.scala 700:86] - node _T_4001 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_4002 = or(_T_4000, _T_4001) @[el2_lsu_bus_buffer.scala 700:114] - node _T_4003 = add(_T_3987, _T_3992) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4004 = tail(_T_4003, 1) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4005 = add(_T_4004, _T_3997) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4006 = tail(_T_4005, 1) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4007 = add(_T_4006, _T_4002) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4008 = tail(_T_4007, 1) @[el2_lsu_bus_buffer.scala 700:160] - buf_numvld_pend_any <= _T_4008 @[el2_lsu_bus_buffer.scala 700:25] - node _T_4009 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4010 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4011 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4012 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4013 = or(_T_4009, _T_4010) @[el2_lsu_bus_buffer.scala 701:158] - node _T_4014 = or(_T_4013, _T_4011) @[el2_lsu_bus_buffer.scala 701:158] - node _T_4015 = or(_T_4014, _T_4012) @[el2_lsu_bus_buffer.scala 701:158] - any_done_wait_state <= _T_4015 @[el2_lsu_bus_buffer.scala 701:25] - node _T_4016 = neq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 703:60] - io.lsu_bus_buffer_pend_any <= _T_4016 @[el2_lsu_bus_buffer.scala 703:37] - node _T_4017 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 704:60] - node _T_4018 = bits(buf_numvld_any, 3, 0) @[el2_lsu_bus_buffer.scala 704:100] - node _T_4019 = geq(_T_4018, UInt<4>("h03")) @[el2_lsu_bus_buffer.scala 704:106] - node _T_4020 = bits(buf_numvld_any, 3, 0) @[el2_lsu_bus_buffer.scala 704:146] - node _T_4021 = eq(_T_4020, UInt<4>("h04")) @[el2_lsu_bus_buffer.scala 704:152] - node _T_4022 = mux(_T_4017, _T_4019, _T_4021) @[el2_lsu_bus_buffer.scala 704:43] - io.lsu_bus_buffer_full_any <= _T_4022 @[el2_lsu_bus_buffer.scala 704:37] - node _T_4023 = or(buf_state[0], buf_state[1]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4024 = or(_T_4023, buf_state[2]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4025 = or(_T_4024, buf_state[3]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4026 = not(_T_4025) @[el2_lsu_bus_buffer.scala 705:40] - node _T_4027 = not(ibuf_valid) @[el2_lsu_bus_buffer.scala 705:104] - node _T_4028 = and(_T_4026, _T_4027) @[el2_lsu_bus_buffer.scala 705:102] - node _T_4029 = not(obuf_valid) @[el2_lsu_bus_buffer.scala 705:118] - node _T_4030 = and(_T_4028, _T_4029) @[el2_lsu_bus_buffer.scala 705:116] - io.lsu_bus_buffer_empty_any <= _T_4030 @[el2_lsu_bus_buffer.scala 705:37] - node _T_4031 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 707:56] - node _T_4032 = and(_T_4031, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 707:77] - node _T_4033 = not(io.flush_m_up) @[el2_lsu_bus_buffer.scala 707:99] - node _T_4034 = and(_T_4032, _T_4033) @[el2_lsu_bus_buffer.scala 707:97] - node _T_4035 = not(io.ld_full_hit_m) @[el2_lsu_bus_buffer.scala 707:116] - node _T_4036 = and(_T_4034, _T_4035) @[el2_lsu_bus_buffer.scala 707:114] - io.lsu_nonblock_load_valid_m <= _T_4036 @[el2_lsu_bus_buffer.scala 707:37] - node _T_4037 = bits(WrPtr0_m, 1, 0) @[el2_lsu_bus_buffer.scala 708:48] - io.lsu_nonblock_load_tag_m <= _T_4037 @[el2_lsu_bus_buffer.scala 708:37] - node _T_4038 = not(io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 709:68] - node _T_4039 = and(lsu_nonblock_load_valid_r, _T_4038) @[el2_lsu_bus_buffer.scala 709:66] - io.lsu_nonblock_load_inv_r <= _T_4039 @[el2_lsu_bus_buffer.scala 709:37] - node _T_4040 = bits(WrPtr0_r, 1, 0) @[el2_lsu_bus_buffer.scala 710:48] - io.lsu_nonblock_load_inv_tag_r <= _T_4040 @[el2_lsu_bus_buffer.scala 710:37] - node _T_4041 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4042 = and(UInt<1>("h01"), buf_write[0]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4043 = not(_T_4042) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4044 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4045 = and(UInt<1>("h01"), buf_write[1]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4046 = not(_T_4045) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4047 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4048 = and(UInt<1>("h01"), buf_write[2]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4049 = not(_T_4048) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4050 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4051 = and(UInt<1>("h01"), buf_write[3]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4052 = not(_T_4051) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4053 = mux(_T_4041, _T_4043, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4054 = mux(_T_4044, _T_4046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4055 = mux(_T_4047, _T_4049, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4056 = mux(_T_4050, _T_4052, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4057 = or(_T_4053, _T_4054) @[Mux.scala 27:72] - node _T_4058 = or(_T_4057, _T_4055) @[Mux.scala 27:72] - node _T_4059 = or(_T_4058, _T_4056) @[Mux.scala 27:72] - wire _T_4060 : UInt<1> @[Mux.scala 27:72] - _T_4060 <= _T_4059 @[Mux.scala 27:72] - lsu_nonblock_load_data_ready <= _T_4060 @[el2_lsu_bus_buffer.scala 712:37] - node _T_4061 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4062 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4063 = and(_T_4061, _T_4062) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4064 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4065 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4066 = and(_T_4064, _T_4065) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4067 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4068 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4069 = and(_T_4067, _T_4068) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4070 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4071 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4072 = and(_T_4070, _T_4071) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4073 = mux(_T_4063, buf_error[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4074 = mux(_T_4066, buf_error[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4075 = mux(_T_4069, buf_error[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4076 = mux(_T_4072, buf_error[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4077 = or(_T_4073, _T_4074) @[Mux.scala 27:72] - node _T_4078 = or(_T_4077, _T_4075) @[Mux.scala 27:72] - node _T_4079 = or(_T_4078, _T_4076) @[Mux.scala 27:72] - wire _T_4080 : UInt<1> @[Mux.scala 27:72] - _T_4080 <= _T_4079 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_error <= _T_4080 @[el2_lsu_bus_buffer.scala 713:37] - node _T_4081 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4082 = not(buf_dual[0]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4083 = not(buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4084 = or(_T_4082, _T_4083) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4085 = and(_T_4081, _T_4084) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4086 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4087 = and(_T_4085, _T_4086) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4088 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4089 = not(buf_dual[1]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4090 = not(buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4091 = or(_T_4089, _T_4090) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4092 = and(_T_4088, _T_4091) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4093 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4094 = and(_T_4092, _T_4093) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4095 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4096 = not(buf_dual[2]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4097 = not(buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4098 = or(_T_4096, _T_4097) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4099 = and(_T_4095, _T_4098) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4100 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4101 = and(_T_4099, _T_4100) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4102 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4103 = not(buf_dual[3]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4104 = not(buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4105 = or(_T_4103, _T_4104) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4106 = and(_T_4102, _T_4105) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4107 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4108 = and(_T_4106, _T_4107) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4109 = mux(_T_4087, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4110 = mux(_T_4094, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4111 = mux(_T_4101, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4112 = mux(_T_4108, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4113 = or(_T_4109, _T_4110) @[Mux.scala 27:72] - node _T_4114 = or(_T_4113, _T_4111) @[Mux.scala 27:72] - node _T_4115 = or(_T_4114, _T_4112) @[Mux.scala 27:72] - wire _T_4116 : UInt<2> @[Mux.scala 27:72] - _T_4116 <= _T_4115 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_tag <= _T_4116 @[el2_lsu_bus_buffer.scala 714:37] - node _T_4117 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4118 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4119 = and(_T_4117, _T_4118) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4120 = not(buf_dual[0]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4121 = not(buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4122 = or(_T_4120, _T_4121) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4123 = and(_T_4119, _T_4122) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4124 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4125 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4126 = and(_T_4124, _T_4125) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4127 = not(buf_dual[1]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4128 = not(buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4129 = or(_T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4130 = and(_T_4126, _T_4129) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4131 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4132 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4133 = and(_T_4131, _T_4132) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4134 = not(buf_dual[2]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4135 = not(buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4136 = or(_T_4134, _T_4135) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4137 = and(_T_4133, _T_4136) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4139 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4140 = and(_T_4138, _T_4139) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4141 = not(buf_dual[3]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4142 = not(buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4143 = or(_T_4141, _T_4142) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4144 = and(_T_4140, _T_4143) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4145 = mux(_T_4123, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4146 = mux(_T_4130, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4147 = mux(_T_4137, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4148 = mux(_T_4144, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4149 = or(_T_4145, _T_4146) @[Mux.scala 27:72] - node _T_4150 = or(_T_4149, _T_4147) @[Mux.scala 27:72] - node _T_4151 = or(_T_4150, _T_4148) @[Mux.scala 27:72] - wire _T_4152 : UInt<32> @[Mux.scala 27:72] - _T_4152 <= _T_4151 @[Mux.scala 27:72] - lsu_nonblock_load_data_lo <= _T_4152 @[el2_lsu_bus_buffer.scala 715:37] - node _T_4153 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4154 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4155 = and(_T_4153, _T_4154) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4156 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4157 = and(_T_4155, _T_4156) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4158 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4159 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4160 = and(_T_4158, _T_4159) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4161 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4162 = and(_T_4160, _T_4161) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4163 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4164 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4165 = and(_T_4163, _T_4164) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4166 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4167 = and(_T_4165, _T_4166) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4168 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4169 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4170 = and(_T_4168, _T_4169) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4171 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4172 = and(_T_4170, _T_4171) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4173 = mux(_T_4157, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4174 = mux(_T_4162, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4175 = mux(_T_4167, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4176 = mux(_T_4172, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4177 = or(_T_4173, _T_4174) @[Mux.scala 27:72] - node _T_4178 = or(_T_4177, _T_4175) @[Mux.scala 27:72] - node _T_4179 = or(_T_4178, _T_4176) @[Mux.scala 27:72] - wire _T_4180 : UInt<32> @[Mux.scala 27:72] - _T_4180 <= _T_4179 @[Mux.scala 27:72] - lsu_nonblock_load_data_hi <= _T_4180 @[el2_lsu_bus_buffer.scala 716:37] - node _T_4181 = bits(buf_addr[io.lsu_nonblock_load_data_tag], 1, 0) @[el2_lsu_bus_buffer.scala 718:79] - lsu_nonblock_addr_offset <= _T_4181 @[el2_lsu_bus_buffer.scala 718:37] - node _T_4182 = bits(buf_sz[io.lsu_nonblock_load_data_tag], 1, 0) @[el2_lsu_bus_buffer.scala 719:77] - lsu_nonblock_sz <= _T_4182 @[el2_lsu_bus_buffer.scala 719:37] - lsu_nonblock_unsign <= buf_unsign[io.lsu_nonblock_load_data_tag] @[el2_lsu_bus_buffer.scala 720:37] - lsu_nonblock_dual <= buf_dual[io.lsu_nonblock_load_data_tag] @[el2_lsu_bus_buffer.scala 721:37] - node _T_4183 = bits(lsu_nonblock_load_data_hi, 31, 0) @[el2_lsu_bus_buffer.scala 722:70] - node _T_4184 = bits(lsu_nonblock_load_data_lo, 31, 0) @[el2_lsu_bus_buffer.scala 722:103] - node _T_4185 = cat(_T_4183, _T_4184) @[Cat.scala 29:58] - node _T_4186 = bits(lsu_nonblock_addr_offset, 1, 0) @[el2_lsu_bus_buffer.scala 722:140] - node _T_4187 = mul(UInt<4>("h08"), _T_4186) @[el2_lsu_bus_buffer.scala 722:115] - node _T_4188 = dshr(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 722:111] - node _T_4189 = bits(_T_4188, 31, 0) @[el2_lsu_bus_buffer.scala 722:146] - lsu_nonblock_data_unalgn <= _T_4189 @[el2_lsu_bus_buffer.scala 722:37] - node _T_4190 = not(io.lsu_nonblock_load_data_error) @[el2_lsu_bus_buffer.scala 723:71] - node _T_4191 = and(lsu_nonblock_load_data_ready, _T_4190) @[el2_lsu_bus_buffer.scala 723:69] - io.lsu_nonblock_load_data_valid <= _T_4191 @[el2_lsu_bus_buffer.scala 723:37] - node _T_4192 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 725:83] - node _T_4193 = and(lsu_nonblock_unsign, _T_4192) @[el2_lsu_bus_buffer.scala 725:65] - node _T_4194 = mux(UInt<1>("h00"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4195 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 725:141] - node _T_4196 = cat(_T_4194, _T_4195) @[Cat.scala 29:58] - node _T_4197 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 726:83] - node _T_4198 = and(lsu_nonblock_unsign, _T_4197) @[el2_lsu_bus_buffer.scala 726:65] - node _T_4199 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4200 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 726:141] - node _T_4201 = cat(_T_4199, _T_4200) @[Cat.scala 29:58] - node _T_4202 = not(lsu_nonblock_unsign) @[el2_lsu_bus_buffer.scala 727:44] - node _T_4203 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 727:83] - node _T_4204 = and(_T_4202, _T_4203) @[el2_lsu_bus_buffer.scala 727:65] - node _T_4205 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 727:131] - node _T_4206 = bits(_T_4205, 0, 0) @[Bitwise.scala 72:15] - node _T_4207 = mux(_T_4206, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4208 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 727:160] - node _T_4209 = cat(_T_4207, _T_4208) @[Cat.scala 29:58] - node _T_4210 = not(lsu_nonblock_unsign) @[el2_lsu_bus_buffer.scala 728:44] - node _T_4211 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 728:83] - node _T_4212 = and(_T_4210, _T_4211) @[el2_lsu_bus_buffer.scala 728:65] - node _T_4213 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 728:131] - node _T_4214 = bits(_T_4213, 0, 0) @[Bitwise.scala 72:15] - node _T_4215 = mux(_T_4214, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4216 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 728:161] - node _T_4217 = cat(_T_4215, _T_4216) @[Cat.scala 29:58] - node _T_4218 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 729:83] - node _T_4219 = and(lsu_nonblock_unsign, _T_4218) @[el2_lsu_bus_buffer.scala 729:65] - node _T_4220 = bits(lsu_nonblock_data_unalgn, 31, 0) @[el2_lsu_bus_buffer.scala 729:119] - node _T_4221 = mux(_T_4193, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4222 = mux(_T_4198, _T_4201, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4223 = mux(_T_4204, _T_4209, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4224 = mux(_T_4212, _T_4217, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4225 = mux(_T_4219, _T_4220, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4226 = or(_T_4221, _T_4222) @[Mux.scala 27:72] - node _T_4227 = or(_T_4226, _T_4223) @[Mux.scala 27:72] - node _T_4228 = or(_T_4227, _T_4224) @[Mux.scala 27:72] - node _T_4229 = or(_T_4228, _T_4225) @[Mux.scala 27:72] - wire _T_4230 : UInt<32> @[Mux.scala 27:72] - _T_4230 <= _T_4229 @[Mux.scala 27:72] - io.lsu_nonblock_load_data <= _T_4230 @[el2_lsu_bus_buffer.scala 724:37] - node _T_4231 = and(obuf_sideeffect, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:62] - node _T_4232 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4233 = and(buf_sideeffect[0], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4234 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4235 = and(buf_sideeffect[1], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4236 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4237 = and(buf_sideeffect[2], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4238 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4239 = and(buf_sideeffect[3], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4240 = mux(_T_4232, _T_4233, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4241 = mux(_T_4234, _T_4235, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4242 = mux(_T_4236, _T_4237, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4243 = mux(_T_4238, _T_4239, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4244 = or(_T_4240, _T_4241) @[Mux.scala 27:72] - node _T_4245 = or(_T_4244, _T_4242) @[Mux.scala 27:72] - node _T_4246 = or(_T_4245, _T_4243) @[Mux.scala 27:72] - wire _T_4247 : UInt<1> @[Mux.scala 27:72] - _T_4247 <= _T_4246 @[Mux.scala 27:72] - node _T_4248 = mux(obuf_valid, _T_4231, _T_4247) @[el2_lsu_bus_buffer.scala 731:34] - bus_sideeffect_pend <= _T_4248 @[el2_lsu_bus_buffer.scala 731:28] - node _T_4249 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4250 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4251 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4252 = eq(_T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4253 = and(_T_4249, _T_4252) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4254 = bits(_T_4253, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4255 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4256 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4257 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4258 = and(obuf_merge, _T_4257) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4259 = or(_T_4256, _T_4258) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4260 = not(_T_4259) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4261 = and(_T_4255, _T_4260) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4262 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4263 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4264 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4265 = eq(_T_4263, _T_4264) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4266 = and(_T_4262, _T_4265) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4267 = bits(_T_4266, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4268 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4269 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4270 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4271 = and(obuf_merge, _T_4270) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4272 = or(_T_4269, _T_4271) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4273 = not(_T_4272) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4274 = and(_T_4268, _T_4273) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4275 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4276 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4277 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4278 = eq(_T_4276, _T_4277) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4279 = and(_T_4275, _T_4278) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4280 = bits(_T_4279, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4281 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4282 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4283 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4284 = and(obuf_merge, _T_4283) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4285 = or(_T_4282, _T_4284) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4286 = not(_T_4285) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4287 = and(_T_4281, _T_4286) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4288 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4289 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4290 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4291 = eq(_T_4289, _T_4290) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4292 = and(_T_4288, _T_4291) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4293 = bits(_T_4292, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4294 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4295 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4296 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4297 = and(obuf_merge, _T_4296) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4298 = or(_T_4295, _T_4297) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4299 = not(_T_4298) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4300 = and(_T_4294, _T_4299) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4301 = mux(_T_4254, _T_4261, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4302 = mux(_T_4267, _T_4274, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4303 = mux(_T_4280, _T_4287, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4304 = mux(_T_4293, _T_4300, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4305 = or(_T_4301, _T_4302) @[Mux.scala 27:72] - node _T_4306 = or(_T_4305, _T_4303) @[Mux.scala 27:72] - node _T_4307 = or(_T_4306, _T_4304) @[Mux.scala 27:72] - wire _T_4308 : UInt<1> @[Mux.scala 27:72] - _T_4308 <= _T_4307 @[Mux.scala 27:72] - bus_addr_match_pending <= _T_4308 @[el2_lsu_bus_buffer.scala 732:28] - node _T_4309 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 734:66] - node _T_4310 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 734:88] - node _T_4311 = and(io.lsu_axi_awready, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 734:164] - node _T_4312 = mux(_T_4309, _T_4310, _T_4311) @[el2_lsu_bus_buffer.scala 734:50] - node _T_4313 = mux(obuf_write, _T_4312, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 734:34] - bus_cmd_ready <= _T_4313 @[el2_lsu_bus_buffer.scala 734:28] - node _T_4314 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 735:50] - bus_wcmd_sent <= _T_4314 @[el2_lsu_bus_buffer.scala 735:28] - node _T_4315 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 736:49] - bus_wdata_sent <= _T_4315 @[el2_lsu_bus_buffer.scala 736:28] - node _T_4316 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 737:47] - node _T_4317 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 737:82] - node _T_4318 = and(_T_4316, _T_4317) @[el2_lsu_bus_buffer.scala 737:64] - node _T_4319 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 737:123] - node _T_4320 = or(_T_4318, _T_4319) @[el2_lsu_bus_buffer.scala 737:101] - bus_cmd_sent <= _T_4320 @[el2_lsu_bus_buffer.scala 737:28] - node _T_4321 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 739:49] - bus_rsp_read <= _T_4321 @[el2_lsu_bus_buffer.scala 739:28] - node _T_4322 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 740:49] - bus_rsp_write <= _T_4322 @[el2_lsu_bus_buffer.scala 740:28] - node _T_4323 = bits(io.lsu_axi_rid, 2, 0) @[el2_lsu_bus_buffer.scala 741:45] - bus_rsp_read_tag <= _T_4323 @[el2_lsu_bus_buffer.scala 741:28] - node _T_4324 = bits(io.lsu_axi_bid, 2, 0) @[el2_lsu_bus_buffer.scala 742:45] - bus_rsp_write_tag <= _T_4324 @[el2_lsu_bus_buffer.scala 742:28] - node _T_4325 = bits(io.lsu_axi_bresp, 1, 0) @[el2_lsu_bus_buffer.scala 743:64] - node _T_4326 = neq(_T_4325, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 743:70] - node _T_4327 = and(bus_rsp_write, _T_4326) @[el2_lsu_bus_buffer.scala 743:45] - bus_rsp_write_error <= _T_4327 @[el2_lsu_bus_buffer.scala 743:28] - node _T_4328 = bits(io.lsu_axi_rresp, 1, 0) @[el2_lsu_bus_buffer.scala 744:64] - node _T_4329 = neq(_T_4328, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 744:70] - node _T_4330 = and(bus_rsp_read, _T_4329) @[el2_lsu_bus_buffer.scala 744:45] - bus_rsp_read_error <= _T_4330 @[el2_lsu_bus_buffer.scala 744:28] - node _T_4331 = bits(io.lsu_axi_rdata, 63, 0) @[el2_lsu_bus_buffer.scala 745:47] - bus_rsp_rdata <= _T_4331 @[el2_lsu_bus_buffer.scala 745:28] - node _T_4332 = and(io.lsu_axi_rvalid, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 747:94] - reg _T_4333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_4332 : @[Reg.scala 28:19] - _T_4333 <= io.lsu_axi_rdata @[Reg.scala 28:23] + buf_samedw[3] <= _T_4293 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= _T_4294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - lsu_axi_rdata_q <= _T_4333 @[el2_lsu_bus_buffer.scala 747:34] - node _T_4334 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 749:64] - node _T_4335 = and(io.lsu_busreq_m, _T_4334) @[el2_lsu_bus_buffer.scala 749:62] - node _T_4336 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 749:78] - node _T_4337 = and(_T_4335, _T_4336) @[el2_lsu_bus_buffer.scala 749:76] - reg _T_4338 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 749:44] - _T_4338 <= _T_4337 @[el2_lsu_bus_buffer.scala 749:44] - io.lsu_busreq_r <= _T_4338 @[el2_lsu_bus_buffer.scala 749:34] - reg _T_4339 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 750:44] - _T_4339 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 750:44] - WrPtr0_r <= _T_4339 @[el2_lsu_bus_buffer.scala 750:34] - reg _T_4340 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 751:44] - _T_4340 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 751:44] - WrPtr1_r <= _T_4340 @[el2_lsu_bus_buffer.scala 751:34] - reg _T_4341 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 752:44] - _T_4341 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 752:44] - lsu_nonblock_load_valid_r <= _T_4341 @[el2_lsu_bus_buffer.scala 752:34] - reg _T_4342 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 755:44] - _T_4342 <= io.lsu_axi_awvalid @[el2_lsu_bus_buffer.scala 755:44] - lsu_axi_awvalid_q <= _T_4342 @[el2_lsu_bus_buffer.scala 755:34] - reg _T_4343 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 756:44] - _T_4343 <= io.lsu_axi_awready @[el2_lsu_bus_buffer.scala 756:44] - lsu_axi_awready_q <= _T_4343 @[el2_lsu_bus_buffer.scala 756:34] - reg _T_4344 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 757:44] - _T_4344 <= io.lsu_axi_wvalid @[el2_lsu_bus_buffer.scala 757:44] - lsu_axi_wvalid_q <= _T_4344 @[el2_lsu_bus_buffer.scala 757:34] - reg _T_4345 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 758:44] - _T_4345 <= io.lsu_axi_wready @[el2_lsu_bus_buffer.scala 758:44] - lsu_axi_wready_q <= _T_4345 @[el2_lsu_bus_buffer.scala 758:34] - reg _T_4346 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 759:44] - _T_4346 <= io.lsu_axi_arvalid @[el2_lsu_bus_buffer.scala 759:44] - lsu_axi_arvalid_q <= _T_4346 @[el2_lsu_bus_buffer.scala 759:34] - reg _T_4347 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 760:44] - _T_4347 <= io.lsu_axi_arready @[el2_lsu_bus_buffer.scala 760:44] - lsu_axi_arready_q <= _T_4347 @[el2_lsu_bus_buffer.scala 760:34] - reg _T_4348 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 761:44] - _T_4348 <= io.lsu_axi_bvalid @[el2_lsu_bus_buffer.scala 761:44] - lsu_axi_bvalid_q <= _T_4348 @[el2_lsu_bus_buffer.scala 761:34] - reg _T_4349 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 762:44] - _T_4349 <= io.lsu_axi_bready @[el2_lsu_bus_buffer.scala 762:44] - lsu_axi_bready_q <= _T_4349 @[el2_lsu_bus_buffer.scala 762:34] - reg _T_4350 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 763:44] - _T_4350 <= io.lsu_axi_rvalid @[el2_lsu_bus_buffer.scala 763:44] - lsu_axi_rvalid_q <= _T_4350 @[el2_lsu_bus_buffer.scala 763:34] - reg _T_4351 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 764:44] - _T_4351 <= io.lsu_axi_rready @[el2_lsu_bus_buffer.scala 764:44] - lsu_axi_rready_q <= _T_4351 @[el2_lsu_bus_buffer.scala 764:34] - reg _T_4352 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 765:44] - _T_4352 <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 765:44] - lsu_axi_bid_q <= _T_4352 @[el2_lsu_bus_buffer.scala 765:34] - reg _T_4353 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 766:44] - _T_4353 <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 766:44] - lsu_axi_rid_q <= _T_4353 @[el2_lsu_bus_buffer.scala 766:34] - reg _T_4354 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 767:44] - _T_4354 <= io.lsu_axi_bresp @[el2_lsu_bus_buffer.scala 767:44] - lsu_axi_bresp_q <= _T_4354 @[el2_lsu_bus_buffer.scala 767:34] - reg _T_4355 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 768:44] - _T_4355 <= io.lsu_axi_rresp @[el2_lsu_bus_buffer.scala 768:44] - lsu_axi_rresp_q <= _T_4355 @[el2_lsu_bus_buffer.scala 768:34] - io.ld_fwddata_buf_lo <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 772:37] - io.ld_fwddata_buf_hi <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 773:37] - node _T_4356 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4357 = and(_T_4356, buf_error[0]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4358 = and(_T_4357, buf_write[0]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4359 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4360 = and(_T_4359, buf_error[1]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4361 = and(_T_4360, buf_write[1]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4362 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4363 = and(_T_4362, buf_error[2]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4364 = and(_T_4363, buf_write[2]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4365 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4366 = and(_T_4365, buf_error[3]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4367 = and(_T_4366, buf_write[3]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4368 = mux(_T_4358, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4369 = mux(_T_4361, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4370 = mux(_T_4364, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4371 = mux(_T_4367, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4372 = or(_T_4368, _T_4369) @[Mux.scala 27:72] - node _T_4373 = or(_T_4372, _T_4370) @[Mux.scala 27:72] - node _T_4374 = or(_T_4373, _T_4371) @[Mux.scala 27:72] - wire _T_4375 : UInt<2> @[Mux.scala 27:72] - _T_4375 <= _T_4374 @[Mux.scala 27:72] - lsu_imprecise_error_store_tag <= _T_4375 @[el2_lsu_bus_buffer.scala 775:37] - node _T_4376 = not(io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 776:74] - node _T_4377 = and(io.lsu_nonblock_load_data_error, _T_4376) @[el2_lsu_bus_buffer.scala 776:72] - io.lsu_imprecise_error_load_any <= _T_4377 @[el2_lsu_bus_buffer.scala 776:37] - node _T_4378 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4379 = and(io.lsu_bus_clk_en_q, _T_4378) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4380 = and(_T_4379, buf_error[0]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4381 = and(_T_4380, buf_write[0]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4382 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4383 = and(io.lsu_bus_clk_en_q, _T_4382) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4384 = and(_T_4383, buf_error[1]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4385 = and(_T_4384, buf_write[1]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4386 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4387 = and(io.lsu_bus_clk_en_q, _T_4386) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4388 = and(_T_4387, buf_error[2]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4389 = and(_T_4388, buf_write[2]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4390 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4391 = and(io.lsu_bus_clk_en_q, _T_4390) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4392 = and(_T_4391, buf_error[3]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4393 = and(_T_4392, buf_write[3]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4394 = or(_T_4381, _T_4385) @[el2_lsu_bus_buffer.scala 777:158] - node _T_4395 = or(_T_4394, _T_4389) @[el2_lsu_bus_buffer.scala 777:158] - node _T_4396 = or(_T_4395, _T_4393) @[el2_lsu_bus_buffer.scala 777:158] - io.lsu_imprecise_error_store_any <= _T_4396 @[el2_lsu_bus_buffer.scala 777:37] - node _T_4397 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 778:43] - io.lsu_imprecise_error_addr_any <= _T_4397 @[el2_lsu_bus_buffer.scala 778:37] - bus_pend_trxnQ <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 780:37] - bus_pend_trxn <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 781:37] - bus_pend_trxn_ns <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 782:37] - lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 783:37] - io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 784:37] - node _T_4398 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 786:60] - node _T_4399 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 786:103] - node _T_4400 = or(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 786:82] - node _T_4401 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 786:146] - node _T_4402 = or(_T_4400, _T_4401) @[el2_lsu_bus_buffer.scala 786:124] - io.lsu_pmu_bus_trxn <= _T_4402 @[el2_lsu_bus_buffer.scala 786:37] - node _T_4403 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 787:56] - node _T_4404 = and(_T_4403, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 787:73] - io.lsu_pmu_bus_misaligned <= _T_4404 @[el2_lsu_bus_buffer.scala 787:37] - node _T_4405 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 788:72] - io.lsu_pmu_bus_error <= _T_4405 @[el2_lsu_bus_buffer.scala 788:37] - node _T_4406 = not(io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 789:62] - node _T_4407 = and(io.lsu_axi_awvalid, _T_4406) @[el2_lsu_bus_buffer.scala 789:60] - node _T_4408 = not(io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 789:105] - node _T_4409 = and(io.lsu_axi_wvalid, _T_4408) @[el2_lsu_bus_buffer.scala 789:103] - node _T_4410 = or(_T_4407, _T_4409) @[el2_lsu_bus_buffer.scala 789:82] - node _T_4411 = not(io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 789:149] - node _T_4412 = and(io.lsu_axi_arvalid, _T_4411) @[el2_lsu_bus_buffer.scala 789:147] - node _T_4413 = or(_T_4410, _T_4412) @[el2_lsu_bus_buffer.scala 789:125] - io.lsu_pmu_bus_busy <= _T_4413 @[el2_lsu_bus_buffer.scala 789:37] - node _T_4414 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 791:51] - node _T_4415 = not(obuf_cmd_done) @[el2_lsu_bus_buffer.scala 791:66] - node _T_4416 = and(_T_4414, _T_4415) @[el2_lsu_bus_buffer.scala 791:64] - node _T_4417 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 791:83] - node _T_4418 = and(_T_4416, _T_4417) @[el2_lsu_bus_buffer.scala 791:81] - io.lsu_axi_awvalid <= _T_4418 @[el2_lsu_bus_buffer.scala 791:37] - io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 792:37] - node _T_4419 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 793:84] - node _T_4420 = cat(_T_4419, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4421 = mux(obuf_sideeffect, obuf_addr, _T_4420) @[el2_lsu_bus_buffer.scala 793:43] - io.lsu_axi_awaddr <= _T_4421 @[el2_lsu_bus_buffer.scala 793:37] - node _T_4422 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 794:49] - io.lsu_axi_awregion <= _T_4422 @[el2_lsu_bus_buffer.scala 794:37] - io.lsu_axi_awlen <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 795:37] - node _T_4423 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4424 = mux(obuf_sideeffect, _T_4423, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 796:43] - io.lsu_axi_awsize <= _T_4424 @[el2_lsu_bus_buffer.scala 796:37] - io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 797:37] - io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 798:37] - node _T_4425 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 799:43] - io.lsu_axi_awcache <= _T_4425 @[el2_lsu_bus_buffer.scala 799:37] - io.lsu_axi_awprot <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 800:37] - io.lsu_axi_awqos <= UInt<4>("h00") @[el2_lsu_bus_buffer.scala 801:37] - node _T_4426 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 803:51] - node _T_4427 = not(obuf_data_done) @[el2_lsu_bus_buffer.scala 803:66] - node _T_4428 = and(_T_4426, _T_4427) @[el2_lsu_bus_buffer.scala 803:64] - node _T_4429 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 803:84] - node _T_4430 = and(_T_4428, _T_4429) @[el2_lsu_bus_buffer.scala 803:82] - io.lsu_axi_wvalid <= _T_4430 @[el2_lsu_bus_buffer.scala 803:37] - io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 804:37] - node _T_4431 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] - node _T_4432 = mux(_T_4431, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_4433 = and(obuf_byteen, _T_4432) @[el2_lsu_bus_buffer.scala 805:52] - io.lsu_axi_wstrb <= _T_4433 @[el2_lsu_bus_buffer.scala 805:37] - io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 806:37] - node _T_4434 = not(obuf_write) @[el2_lsu_bus_buffer.scala 808:53] - node _T_4435 = and(obuf_valid, _T_4434) @[el2_lsu_bus_buffer.scala 808:51] - node _T_4436 = not(obuf_nosend) @[el2_lsu_bus_buffer.scala 808:67] - node _T_4437 = and(_T_4435, _T_4436) @[el2_lsu_bus_buffer.scala 808:65] - node _T_4438 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 808:82] - node _T_4439 = and(_T_4437, _T_4438) @[el2_lsu_bus_buffer.scala 808:80] - io.lsu_axi_arvalid <= _T_4439 @[el2_lsu_bus_buffer.scala 808:37] - io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 809:37] - io.lsu_axi_araddr <= io.lsu_axi_awaddr @[el2_lsu_bus_buffer.scala 810:37] - node _T_4440 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 811:49] - io.lsu_axi_arregion <= _T_4440 @[el2_lsu_bus_buffer.scala 811:37] - io.lsu_axi_arlen <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 812:37] - io.lsu_axi_arsize <= io.lsu_axi_awsize @[el2_lsu_bus_buffer.scala 813:37] - io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 814:37] - io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 815:37] - io.lsu_axi_arcache <= io.lsu_axi_awcache @[el2_lsu_bus_buffer.scala 816:37] - io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 817:37] - io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 818:37] - io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 820:37] - io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 821:37] + buf_nomerge[3] <= _T_4296 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= _T_4297 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4299 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4300 : @[Reg.scala 28:19] + _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4304 : @[Reg.scala 28:19] + _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] + node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] + node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] + buf_ldfwd <= _T_4310 @[el2_lsu_bus_buffer.scala 562:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4311 : @[Reg.scala 28:19] + _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4313 : @[Reg.scala 28:19] + _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4317 : @[Reg.scala 28:19] + _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4312 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[1] <= _T_4314 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[2] <= _T_4316 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[3] <= _T_4318 @[el2_lsu_bus_buffer.scala 563:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4320 : @[Reg.scala 28:19] + _T_4321 <= _T_4319 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4323 : @[Reg.scala 28:19] + _T_4324 <= _T_4322 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= _T_4325 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4329 : @[Reg.scala 28:19] + _T_4330 <= _T_4328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] + node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] + node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] + buf_sideeffect <= _T_4333 @[el2_lsu_bus_buffer.scala 564:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4335 : @[Reg.scala 28:19] + _T_4336 <= _T_4334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= _T_4337 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4341 : @[Reg.scala 28:19] + _T_4342 <= _T_4340 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4344 : @[Reg.scala 28:19] + _T_4345 <= _T_4343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] + node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] + node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] + buf_unsign <= _T_4348 @[el2_lsu_bus_buffer.scala 565:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= _T_4349 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4352 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4353 : @[Reg.scala 28:19] + _T_4354 <= _T_4352 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4355 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4356 : @[Reg.scala 28:19] + _T_4357 <= _T_4355 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4358 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= _T_4358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] + node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] + node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] + buf_write <= _T_4363 @[el2_lsu_bus_buffer.scala 566:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4364 : @[Reg.scala 28:19] + _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4368 : @[Reg.scala 28:19] + _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4365 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[1] <= _T_4367 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[2] <= _T_4369 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[3] <= _T_4371 @[el2_lsu_bus_buffer.scala 567:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_4372 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4373 <= buf_addr_in[0] @[el2_lib.scala 514:16] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_4374 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4375 <= buf_addr_in[1] @[el2_lib.scala 514:16] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_4376 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4377 <= buf_addr_in[2] @[el2_lib.scala 514:16] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_4378 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4379 <= buf_addr_in[3] @[el2_lib.scala 514:16] + buf_addr[0] <= _T_4373 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[1] <= _T_4375 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[2] <= _T_4377 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[3] <= _T_4379 @[el2_lsu_bus_buffer.scala 568:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4380 : @[Reg.scala 28:19] + _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4384 : @[Reg.scala 28:19] + _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4381 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[1] <= _T_4383 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[2] <= _T_4385 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[3] <= _T_4387 @[el2_lsu_bus_buffer.scala 569:14] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4388 <= buf_data_in[0] @[el2_lib.scala 514:16] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4389 <= buf_data_in[1] @[el2_lib.scala 514:16] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4390 <= buf_data_in[2] @[el2_lib.scala 514:16] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4391 <= buf_data_in[3] @[el2_lib.scala 514:16] + buf_data[0] <= _T_4388 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[1] <= _T_4389 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[2] <= _T_4390 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[3] <= _T_4391 @[el2_lsu_bus_buffer.scala 570:12] + node _T_4392 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4395 = and(_T_4393, _T_4394) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4396 <= _T_4395 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4397 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4400 = and(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4401 <= _T_4400 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4402 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4405 = and(_T_4403, _T_4404) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4406 <= _T_4405 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4407 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4410 = and(_T_4408, _T_4409) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4411 <= _T_4410 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] + node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] + node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] + buf_error <= _T_4414 @[el2_lsu_bus_buffer.scala 571:13] + node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 574:28] + node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 574:94] + node _T_4419 = add(_T_4416, _T_4418) @[el2_lsu_bus_buffer.scala 574:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[el2_lsu_bus_buffer.scala 574:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4425 = add(_T_4421, _T_4422) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4426 = add(_T_4425, _T_4423) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4427 = add(_T_4426, _T_4424) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4428 = add(_T_4420, _T_4427) @[el2_lsu_bus_buffer.scala 574:169] + node buf_numvld_any = tail(_T_4428, 1) @[el2_lsu_bus_buffer.scala 574:169] + node _T_4429 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4431 = and(_T_4429, _T_4430) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4433 = and(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4434 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4436 = and(_T_4434, _T_4435) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4438 = and(_T_4436, _T_4437) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4439 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4441 = and(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4443 = and(_T_4441, _T_4442) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4444 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4446 = and(_T_4444, _T_4445) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4448 = and(_T_4446, _T_4447) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4449 = add(_T_4448, _T_4443) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4450 = add(_T_4449, _T_4438) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4451 = add(_T_4450, _T_4433) @[el2_lsu_bus_buffer.scala 575:142] + buf_numvld_wrcmd_any <= _T_4451 @[el2_lsu_bus_buffer.scala 575:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4454 = and(_T_4452, _T_4453) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4457 = and(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4460 = and(_T_4458, _T_4459) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4463 = and(_T_4461, _T_4462) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4464 = add(_T_4463, _T_4460) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4465 = add(_T_4464, _T_4457) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4466 = add(_T_4465, _T_4454) @[el2_lsu_bus_buffer.scala 576:126] + buf_numvld_cmd_any <= _T_4466 @[el2_lsu_bus_buffer.scala 576:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4470 = and(_T_4468, _T_4469) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4471 = or(_T_4467, _T_4470) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4475 = and(_T_4473, _T_4474) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4476 = or(_T_4472, _T_4475) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4480 = and(_T_4478, _T_4479) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4481 = or(_T_4477, _T_4480) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4485 = and(_T_4483, _T_4484) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4486 = or(_T_4482, _T_4485) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4487 = add(_T_4486, _T_4481) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4488 = add(_T_4487, _T_4476) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4489 = add(_T_4488, _T_4471) @[el2_lsu_bus_buffer.scala 577:154] + buf_numvld_pend_any <= _T_4489 @[el2_lsu_bus_buffer.scala 577:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4494 = or(_T_4493, _T_4492) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4495 = or(_T_4494, _T_4491) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4496 = or(_T_4495, _T_4490) @[el2_lsu_bus_buffer.scala 578:93] + any_done_wait_state <= _T_4496 @[el2_lsu_bus_buffer.scala 578:23] + node _T_4497 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 579:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[el2_lsu_bus_buffer.scala 579:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 580:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 580:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 580:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[el2_lsu_bus_buffer.scala 580:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[el2_lsu_bus_buffer.scala 580:30] + node _T_4502 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4503 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4504 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4505 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4506 = or(_T_4502, _T_4503) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4507 = or(_T_4506, _T_4504) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4508 = or(_T_4507, _T_4505) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:72] + node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 581:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:86] + node _T_4513 = and(_T_4511, _T_4512) @[el2_lsu_bus_buffer.scala 581:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[el2_lsu_bus_buffer.scala 581:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 583:51] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 583:72] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:94] + node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 583:92] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:111] + node _T_4519 = and(_T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 583:109] + io.lsu_nonblock_load_valid_m <= _T_4519 @[el2_lsu_bus_buffer.scala 583:32] + io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 584:30] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 586:61] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[el2_lsu_bus_buffer.scala 586:59] + io.lsu_nonblock_load_inv_r <= _T_4521 @[el2_lsu_bus_buffer.scala 586:30] + io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 587:34] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4523 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4527 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4531 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4535 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4541 = mux(_T_4534, _T_4537, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = or(_T_4538, _T_4539) @[Mux.scala 27:72] + node _T_4543 = or(_T_4542, _T_4540) @[Mux.scala 27:72] + node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4546 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4547 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4549 = and(_T_4546, _T_4548) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4551 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4552 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4554 = and(_T_4551, _T_4553) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4556 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4557 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4559 = and(_T_4556, _T_4558) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4561 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4562 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4564 = and(_T_4561, _T_4563) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4560, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = or(_T_4565, _T_4566) @[Mux.scala 27:72] + node _T_4570 = or(_T_4569, _T_4567) @[Mux.scala 27:72] + node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] + wire _T_4572 : UInt<1> @[Mux.scala 27:72] + _T_4572 <= _T_4571 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_error <= _T_4572 @[el2_lsu_bus_buffer.scala 589:35] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4574 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4576 = and(_T_4573, _T_4575) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4579 = or(_T_4577, _T_4578) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4580 = and(_T_4576, _T_4579) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4582 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4584 = and(_T_4581, _T_4583) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4587 = or(_T_4585, _T_4586) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4588 = and(_T_4584, _T_4587) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4590 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4592 = and(_T_4589, _T_4591) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4595 = or(_T_4593, _T_4594) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4596 = and(_T_4592, _T_4595) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4598 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4600 = and(_T_4597, _T_4599) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4603 = or(_T_4601, _T_4602) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4604 = and(_T_4600, _T_4603) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4608 = mux(_T_4604, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4609 = or(_T_4605, _T_4606) @[Mux.scala 27:72] + node _T_4610 = or(_T_4609, _T_4607) @[Mux.scala 27:72] + node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] + wire _T_4612 : UInt<2> @[Mux.scala 27:72] + _T_4612 <= _T_4611 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_tag <= _T_4612 @[el2_lsu_bus_buffer.scala 590:33] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4614 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4616 = and(_T_4613, _T_4615) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4619 = or(_T_4617, _T_4618) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4620 = and(_T_4616, _T_4619) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4622 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4624 = and(_T_4621, _T_4623) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4627 = or(_T_4625, _T_4626) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4628 = and(_T_4624, _T_4627) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4630 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4632 = and(_T_4629, _T_4631) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4635 = or(_T_4633, _T_4634) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4636 = and(_T_4632, _T_4635) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4638 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4640 = and(_T_4637, _T_4639) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4643 = or(_T_4641, _T_4642) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4644 = and(_T_4640, _T_4643) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4648 = mux(_T_4644, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4649 = or(_T_4645, _T_4646) @[Mux.scala 27:72] + node _T_4650 = or(_T_4649, _T_4647) @[Mux.scala 27:72] + node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4653 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4655 = and(_T_4652, _T_4654) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4656 = or(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4657 = and(_T_4655, _T_4656) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4659 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4661 = and(_T_4658, _T_4660) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4662 = or(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4663 = and(_T_4661, _T_4662) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4665 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4667 = and(_T_4664, _T_4666) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4668 = or(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4669 = and(_T_4667, _T_4668) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4671 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4673 = and(_T_4670, _T_4672) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4674 = or(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4675 = and(_T_4673, _T_4674) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = or(_T_4676, _T_4677) @[Mux.scala 27:72] + node _T_4681 = or(_T_4680, _T_4678) @[Mux.scala 27:72] + node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] + node _T_4683 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4684 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4685 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4686 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4690 = mux(_T_4686, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = or(_T_4687, _T_4688) @[Mux.scala 27:72] + node _T_4692 = or(_T_4691, _T_4689) @[Mux.scala 27:72] + node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] + wire _T_4694 : UInt<32> @[Mux.scala 27:72] + _T_4694 <= _T_4693 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[el2_lsu_bus_buffer.scala 593:83] + node _T_4695 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4696 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4697 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4698 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4698, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] + node _T_4706 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4708 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4710 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4712 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4717 = mux(_T_4712, _T_4713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4718 = or(_T_4714, _T_4715) @[Mux.scala 27:72] + node _T_4719 = or(_T_4718, _T_4716) @[Mux.scala 27:72] + node _T_4720 = or(_T_4719, _T_4717) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4720 @[Mux.scala 27:72] + node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] + node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] + node _T_4724 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4725 = bits(_T_4723, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4726 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4727 = bits(_T_4723, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4728 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4729 = bits(_T_4723, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4730 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4731 = bits(_T_4723, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4735 = mux(_T_4730, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4736 = or(_T_4732, _T_4733) @[Mux.scala 27:72] + node _T_4737 = or(_T_4736, _T_4734) @[Mux.scala 27:72] + node _T_4738 = or(_T_4737, _T_4735) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] + node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 597:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 597:92] + node _T_4741 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:69] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[el2_lsu_bus_buffer.scala 599:67] + io.lsu_nonblock_load_data_valid <= _T_4742 @[el2_lsu_bus_buffer.scala 599:35] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 600:81] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[el2_lsu_bus_buffer.scala 600:63] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 600:131] + node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 601:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[el2_lsu_bus_buffer.scala 601:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 601:95] + node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:45] + node _T_4753 = and(_T_4751, _T_4752) @[el2_lsu_bus_buffer.scala 602:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 602:93] + node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] + node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 602:123] + node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 603:45] + node _T_4761 = and(_T_4759, _T_4760) @[el2_lsu_bus_buffer.scala 603:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 603:93] + node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] + node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 603:124] + node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 604:21] + node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4761, _T_4766, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4767, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = or(_T_4768, _T_4769) @[Mux.scala 27:72] + node _T_4774 = or(_T_4773, _T_4770) @[Mux.scala 27:72] + node _T_4775 = or(_T_4774, _T_4771) @[Mux.scala 27:72] + node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] + wire _T_4777 : UInt<64> @[Mux.scala 27:72] + _T_4777 <= _T_4776 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4777 @[el2_lsu_bus_buffer.scala 600:29] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4780 = and(_T_4778, _T_4779) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4781 = and(_T_4780, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4784 = and(_T_4782, _T_4783) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4785 = and(_T_4784, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4789 = and(_T_4788, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4792 = and(_T_4790, _T_4791) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4793 = and(_T_4792, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4794 = or(_T_4781, _T_4785) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4795 = or(_T_4794, _T_4789) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4796 = or(_T_4795, _T_4793) @[el2_lsu_bus_buffer.scala 605:141] + bus_sideeffect_pend <= _T_4796 @[el2_lsu_bus_buffer.scala 605:23] + node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4799 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4800 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4801 = eq(_T_4799, _T_4800) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4802 = and(_T_4798, _T_4801) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4805 = and(obuf_merge, _T_4804) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4806 = or(_T_4803, _T_4805) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4808 = and(_T_4802, _T_4807) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4811 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4812 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4813 = eq(_T_4811, _T_4812) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4814 = and(_T_4810, _T_4813) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4817 = and(obuf_merge, _T_4816) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4818 = or(_T_4815, _T_4817) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4820 = and(_T_4814, _T_4819) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4823 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4824 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4825 = eq(_T_4823, _T_4824) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4826 = and(_T_4822, _T_4825) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4829 = and(obuf_merge, _T_4828) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4830 = or(_T_4827, _T_4829) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4832 = and(_T_4826, _T_4831) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4835 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4836 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4837 = eq(_T_4835, _T_4836) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4838 = and(_T_4834, _T_4837) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4841 = and(obuf_merge, _T_4840) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4842 = or(_T_4839, _T_4841) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4844 = and(_T_4838, _T_4843) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4845 = mux(_T_4797, _T_4808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4846 = mux(_T_4809, _T_4820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4847 = mux(_T_4821, _T_4832, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4848 = mux(_T_4833, _T_4844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = or(_T_4845, _T_4846) @[Mux.scala 27:72] + node _T_4850 = or(_T_4849, _T_4847) @[Mux.scala 27:72] + node _T_4851 = or(_T_4850, _T_4848) @[Mux.scala 27:72] + wire _T_4852 : UInt<1> @[Mux.scala 27:72] + _T_4852 <= _T_4851 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4852 @[el2_lsu_bus_buffer.scala 606:26] + node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 609:54] + node _T_4854 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:75] + node _T_4855 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:150] + node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[el2_lsu_bus_buffer.scala 609:39] + node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 609:23] + bus_cmd_ready <= _T_4857 @[el2_lsu_bus_buffer.scala 609:17] + node _T_4858 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:39] + bus_wcmd_sent <= _T_4858 @[el2_lsu_bus_buffer.scala 610:17] + node _T_4859 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 611:39] + bus_wdata_sent <= _T_4859 @[el2_lsu_bus_buffer.scala 611:18] + node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 612:35] + node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 612:70] + node _T_4862 = and(_T_4860, _T_4861) @[el2_lsu_bus_buffer.scala 612:52] + node _T_4863 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 612:111] + node _T_4864 = or(_T_4862, _T_4863) @[el2_lsu_bus_buffer.scala 612:89] + bus_cmd_sent <= _T_4864 @[el2_lsu_bus_buffer.scala 612:16] + node _T_4865 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 613:37] + bus_rsp_read <= _T_4865 @[el2_lsu_bus_buffer.scala 613:16] + node _T_4866 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 614:38] + bus_rsp_write <= _T_4866 @[el2_lsu_bus_buffer.scala 614:17] + bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 615:20] + bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 616:21] + node _T_4867 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:60] + node _T_4868 = and(bus_rsp_write, _T_4867) @[el2_lsu_bus_buffer.scala 617:40] + bus_rsp_write_error <= _T_4868 @[el2_lsu_bus_buffer.scala 617:23] + node _T_4869 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 618:58] + node _T_4870 = and(bus_rsp_read, _T_4869) @[el2_lsu_bus_buffer.scala 618:38] + bus_rsp_read_error <= _T_4870 @[el2_lsu_bus_buffer.scala 618:22] + bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 619:17] + node _T_4871 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 622:36] + node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:51] + node _T_4873 = and(_T_4871, _T_4872) @[el2_lsu_bus_buffer.scala 622:49] + node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:68] + node _T_4875 = and(_T_4873, _T_4874) @[el2_lsu_bus_buffer.scala 622:66] + io.lsu_axi_awvalid <= _T_4875 @[el2_lsu_bus_buffer.scala 622:22] + io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 623:19] + node _T_4876 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 624:69] + node _T_4877 = cat(_T_4876, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[el2_lsu_bus_buffer.scala 624:27] + io.lsu_axi_awaddr <= _T_4878 @[el2_lsu_bus_buffer.scala 624:21] + node _T_4879 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 625:27] + io.lsu_axi_awsize <= _T_4880 @[el2_lsu_bus_buffer.scala 625:21] + io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 626:21] + node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 627:28] + io.lsu_axi_awcache <= _T_4881 @[el2_lsu_bus_buffer.scala 627:22] + node _T_4882 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 628:35] + io.lsu_axi_awregion <= _T_4882 @[el2_lsu_bus_buffer.scala 628:23] + io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 629:20] + io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 630:22] + io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 631:20] + io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 632:21] + node _T_4883 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 634:35] + node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:50] + node _T_4885 = and(_T_4883, _T_4884) @[el2_lsu_bus_buffer.scala 634:48] + node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:68] + node _T_4887 = and(_T_4885, _T_4886) @[el2_lsu_bus_buffer.scala 634:66] + io.lsu_axi_wvalid <= _T_4887 @[el2_lsu_bus_buffer.scala 634:21] + node _T_4888 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4889 = mux(_T_4888, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4890 = and(obuf_byteen, _T_4889) @[el2_lsu_bus_buffer.scala 635:35] + io.lsu_axi_wstrb <= _T_4890 @[el2_lsu_bus_buffer.scala 635:20] + io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 636:20] + io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 637:20] + node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:38] + node _T_4892 = and(obuf_valid, _T_4891) @[el2_lsu_bus_buffer.scala 639:36] + node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:52] + node _T_4894 = and(_T_4892, _T_4893) @[el2_lsu_bus_buffer.scala 639:50] + node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:67] + node _T_4896 = and(_T_4894, _T_4895) @[el2_lsu_bus_buffer.scala 639:65] + io.lsu_axi_arvalid <= _T_4896 @[el2_lsu_bus_buffer.scala 639:22] + io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 640:19] + node _T_4897 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 641:69] + node _T_4898 = cat(_T_4897, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[el2_lsu_bus_buffer.scala 641:27] + io.lsu_axi_araddr <= _T_4899 @[el2_lsu_bus_buffer.scala 641:21] + node _T_4900 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:27] + io.lsu_axi_arsize <= _T_4901 @[el2_lsu_bus_buffer.scala 642:21] + io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 643:21] + node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 644:28] + io.lsu_axi_arcache <= _T_4902 @[el2_lsu_bus_buffer.scala 644:22] + node _T_4903 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 645:35] + io.lsu_axi_arregion <= _T_4903 @[el2_lsu_bus_buffer.scala 645:23] + io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 646:20] + io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 647:22] + io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 648:20] + io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 649:21] + io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 650:21] + io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 651:21] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4905 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4907 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4908 = and(_T_4906, _T_4907) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4910 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4912 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4913 = and(_T_4911, _T_4912) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4915 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4917 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4918 = and(_T_4916, _T_4917) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4920 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4922 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4923 = and(_T_4921, _T_4922) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4924 = mux(_T_4904, _T_4908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4909, _T_4913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4914, _T_4918, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4919, _T_4923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire _T_4931 : UInt<1> @[Mux.scala 27:72] + _T_4931 <= _T_4930 @[Mux.scala 27:72] + io.lsu_imprecise_error_store_any <= _T_4931 @[el2_lsu_bus_buffer.scala 652:36] + node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:87] + node _T_4933 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 653:109] + node _T_4934 = and(_T_4932, _T_4933) @[el2_lsu_bus_buffer.scala 653:98] + node _T_4935 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 653:124] + node _T_4936 = and(_T_4934, _T_4935) @[el2_lsu_bus_buffer.scala 653:113] + node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:87] + node _T_4938 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 653:109] + node _T_4939 = and(_T_4937, _T_4938) @[el2_lsu_bus_buffer.scala 653:98] + node _T_4940 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 653:124] + node _T_4941 = and(_T_4939, _T_4940) @[el2_lsu_bus_buffer.scala 653:113] + node _T_4942 = mux(_T_4936, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4943 = mux(_T_4941, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4944 = or(_T_4942, _T_4943) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<1> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4944 @[Mux.scala 27:72] + node _T_4945 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 655:72] + node _T_4946 = and(io.lsu_nonblock_load_data_error, _T_4945) @[el2_lsu_bus_buffer.scala 655:70] + io.lsu_imprecise_error_load_any <= _T_4946 @[el2_lsu_bus_buffer.scala 655:35] + node _T_4947 = eq(lsu_imprecise_error_store_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4948 = eq(lsu_imprecise_error_store_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4949 = mux(_T_4947, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4950 = mux(_T_4948, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4951 = or(_T_4949, _T_4950) @[Mux.scala 27:72] + wire _T_4952 : UInt<32> @[Mux.scala 27:72] + _T_4952 <= _T_4951 @[Mux.scala 27:72] + node _T_4953 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4954 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4955 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4956 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4957 = mux(_T_4953, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4958 = mux(_T_4954, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4959 = mux(_T_4955, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4960 = mux(_T_4956, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4961 = or(_T_4957, _T_4958) @[Mux.scala 27:72] + node _T_4962 = or(_T_4961, _T_4959) @[Mux.scala 27:72] + node _T_4963 = or(_T_4962, _T_4960) @[Mux.scala 27:72] + wire _T_4964 : UInt<32> @[Mux.scala 27:72] + _T_4964 <= _T_4963 @[Mux.scala 27:72] + node _T_4965 = mux(io.lsu_imprecise_error_store_any, _T_4952, _T_4964) @[el2_lsu_bus_buffer.scala 656:41] + io.lsu_imprecise_error_addr_any <= _T_4965 @[el2_lsu_bus_buffer.scala 656:35] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 657:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 659:23] + node _T_4966 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 662:46] + node _T_4967 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 662:89] + node _T_4968 = or(_T_4966, _T_4967) @[el2_lsu_bus_buffer.scala 662:68] + node _T_4969 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 662:132] + node _T_4970 = or(_T_4968, _T_4969) @[el2_lsu_bus_buffer.scala 662:110] + io.lsu_pmu_bus_trxn <= _T_4970 @[el2_lsu_bus_buffer.scala 662:23] + node _T_4971 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 663:48] + node _T_4972 = and(_T_4971, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 663:65] + io.lsu_pmu_bus_misaligned <= _T_4972 @[el2_lsu_bus_buffer.scala 663:29] + node _T_4973 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 664:59] + io.lsu_pmu_bus_error <= _T_4973 @[el2_lsu_bus_buffer.scala 664:24] + node _T_4974 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:48] + node _T_4975 = and(io.lsu_axi_awvalid, _T_4974) @[el2_lsu_bus_buffer.scala 666:46] + node _T_4976 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:92] + node _T_4977 = and(io.lsu_axi_wvalid, _T_4976) @[el2_lsu_bus_buffer.scala 666:90] + node _T_4978 = or(_T_4975, _T_4977) @[el2_lsu_bus_buffer.scala 666:69] + node _T_4979 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:136] + node _T_4980 = and(io.lsu_axi_arvalid, _T_4979) @[el2_lsu_bus_buffer.scala 666:134] + node _T_4981 = or(_T_4978, _T_4980) @[el2_lsu_bus_buffer.scala 666:112] + io.lsu_pmu_bus_busy <= _T_4981 @[el2_lsu_bus_buffer.scala 666:23] + reg _T_4982 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 668:49] + _T_4982 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 668:49] + WrPtr0_r <= _T_4982 @[el2_lsu_bus_buffer.scala 668:12] + reg _T_4983 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 669:49] + _T_4983 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 669:49] + WrPtr1_r <= _T_4983 @[el2_lsu_bus_buffer.scala 669:12] + node _T_4984 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:75] + node _T_4985 = and(io.lsu_busreq_m, _T_4984) @[el2_lsu_bus_buffer.scala 670:73] + node _T_4986 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:89] + node _T_4987 = and(_T_4985, _T_4986) @[el2_lsu_bus_buffer.scala 670:87] + reg _T_4988 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 670:56] + _T_4988 <= _T_4987 @[el2_lsu_bus_buffer.scala 670:56] + io.lsu_busreq_r <= _T_4988 @[el2_lsu_bus_buffer.scala 670:19] + reg _T_4989 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 671:66] + _T_4989 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 671:66] + lsu_nonblock_load_valid_r <= _T_4989 @[el2_lsu_bus_buffer.scala 671:29] diff --git a/el2_lsu_bus_buffer.v b/el2_lsu_bus_buffer.v index 2fce1639..38784b74 100644 --- a/el2_lsu_bus_buffer.v +++ b/el2_lsu_bus_buffer.v @@ -1,3 +1,24 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule module el2_lsu_bus_buffer( input clock, input reset, @@ -56,7 +77,6 @@ module el2_lsu_bus_buffer( input io_ldst_dual_m, input io_ldst_dual_r, input [7:0] io_ldst_byteen_ext_m, - input io_lsu_axi_awready, input io_lsu_axi_wready, input io_lsu_axi_bvalid, input [1:0] io_lsu_axi_bresp, @@ -93,6 +113,7 @@ module el2_lsu_bus_buffer( output io_lsu_pmu_bus_error, output io_lsu_pmu_bus_busy, output io_lsu_axi_awvalid, + input io_lsu_axi_awready, output [2:0] io_lsu_axi_awid, output [31:0] io_lsu_axi_awaddr, output [3:0] io_lsu_axi_awregion, @@ -201,8 +222,8 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_76; reg [31:0] _RAND_77; reg [31:0] _RAND_78; - reg [63:0] _RAND_79; - reg [31:0] _RAND_80; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -212,7 +233,7 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_87; reg [31:0] _RAND_88; reg [31:0] _RAND_89; - reg [63:0] _RAND_90; + reg [31:0] _RAND_90; reg [31:0] _RAND_91; reg [31:0] _RAND_92; reg [31:0] _RAND_93; @@ -229,1948 +250,2523 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_104; reg [31:0] _RAND_105; reg [31:0] _RAND_106; - reg [31:0] _RAND_107; - reg [31:0] _RAND_108; - reg [31:0] _RAND_109; - reg [31:0] _RAND_110; - reg [31:0] _RAND_111; - reg [31:0] _RAND_112; - reg [31:0] _RAND_113; - reg [31:0] _RAND_114; - reg [31:0] _RAND_115; - reg [31:0] _RAND_116; - reg [31:0] _RAND_117; - reg [31:0] _RAND_118; - reg [31:0] _RAND_119; - reg [31:0] _RAND_120; - reg [31:0] _RAND_121; - reg [31:0] _RAND_122; - reg [31:0] _RAND_123; - reg [31:0] _RAND_124; - reg [31:0] _RAND_125; - reg [31:0] _RAND_126; - reg [31:0] _RAND_127; - reg [31:0] _RAND_128; - reg [31:0] _RAND_129; - reg [31:0] _RAND_130; `endif // RANDOMIZE_REG_INIT - wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 401:51] - reg [31:0] ibuf_addr; // @[Reg.scala 27:20] - wire _T_4 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 403:52] - reg ibuf_write; // @[Reg.scala 27:20] - wire _T_5 = _T_4 & ibuf_write; // @[el2_lsu_bus_buffer.scala 403:73] - reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 464:28] - wire _T_6 = _T_5 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 403:86] - wire ld_addr_ibuf_hit_lo = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 403:99] - reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] - wire _T_15 = ld_addr_ibuf_hit_lo & ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_17 = _T_15 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_19 = ld_addr_ibuf_hit_lo & ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_21 = _T_19 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_23 = ld_addr_ibuf_hit_lo & ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_25 = _T_23 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_27 = ld_addr_ibuf_hit_lo & ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_29 = _T_27 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 406:89] - wire [3:0] ld_byte_ibuf_hit_lo = {_T_29,_T_25,_T_21,_T_17}; // @[Cat.scala 29:58] - reg [31:0] buf_addr_0; // @[Reg.scala 27:20] - wire _T_54 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_0; // @[Reg.scala 27:20] - wire _T_55 = _T_54 & buf_write_0; // @[el2_lsu_bus_buffer.scala 409:100] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_buffer.scala 127:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 128:46] + reg [31:0] buf_addr_0; // @[el2_lib.scala 514:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + reg _T_4360; // @[Reg.scala 27:20] + reg _T_4357; // @[Reg.scala 27:20] + reg _T_4354; // @[Reg.scala 27:20] + reg _T_4351; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_0; // @[Reg.scala 27:20] - wire _T_56 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_57 = _T_55 & _T_56; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_58 = _T_57 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_1; // @[Reg.scala 27:20] - wire _T_61 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_1; // @[Reg.scala 27:20] - wire _T_62 = _T_61 & buf_write_1; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_5 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_6 = _T_4 & _T_5; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_1; // @[el2_lib.scala 514:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_11 = _T_9 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_1; // @[Reg.scala 27:20] - wire _T_63 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_64 = _T_62 & _T_63; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_65 = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_2; // @[Reg.scala 27:20] - wire _T_68 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_2; // @[Reg.scala 27:20] - wire _T_69 = _T_68 & buf_write_2; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_12 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_13 = _T_11 & _T_12; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_2; // @[el2_lib.scala 514:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_18 = _T_16 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_2; // @[Reg.scala 27:20] - wire _T_70 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_71 = _T_69 & _T_70; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_72 = _T_71 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_3; // @[Reg.scala 27:20] - wire _T_75 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_3; // @[Reg.scala 27:20] - wire _T_76 = _T_75 & buf_write_3; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_19 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_20 = _T_18 & _T_19; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_3; // @[el2_lib.scala 514:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_25 = _T_23 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_3; // @[Reg.scala 27:20] - wire _T_77 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_78 = _T_76 & _T_77; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_79 = _T_78 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - wire [3:0] ld_addr_hitvec_lo = {_T_79,_T_72,_T_65,_T_58}; // @[Cat.scala 29:58] + wire _T_26 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_27 = _T_25 & _T_26; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_32 = _T_30 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_34 = _T_32 & _T_5; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_39 = _T_37 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_41 = _T_39 & _T_12; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_46 = _T_44 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_48 = _T_46 & _T_19; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_53 = _T_51 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] - wire _T_161 = ld_addr_hitvec_lo[3] & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_163 = _T_161 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] - wire _T_156 = ld_addr_hitvec_lo[2] & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_158 = _T_156 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] - wire _T_151 = ld_addr_hitvec_lo[1] & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_153 = _T_151 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] - wire _T_146 = ld_addr_hitvec_lo[0] & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_148 = _T_146 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_0 = {_T_163,_T_158,_T_153,_T_148}; // @[Cat.scala 29:58] - reg buf_ageQ_3_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_3015 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3756 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3779 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3783 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] - reg [2:0] obuf_tag0; // @[Reg.scala 27:20] - wire _T_3790 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 628:52] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1848; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 405:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:48] reg obuf_merge; // @[Reg.scala 27:20] - reg [2:0] obuf_tag1; // @[Reg.scala 27:20] - wire _T_3791 = obuf_tag1 == 3'h3; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3792 = obuf_merge & _T_3791; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3793 = _T_3790 | _T_3792; // @[el2_lsu_bus_buffer.scala 628:85] - reg obuf_valid; // @[el2_lsu_bus_buffer.scala 531:28] - wire _T_3794 = _T_3793 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 528:35] - wire _T_3795 = _T_3794 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_398 = _T_3783 & _T_3795; // @[Conditional.scala 39:67] - wire _GEN_411 = _T_3779 ? 1'h0 : _GEN_398; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_411; // @[Conditional.scala 40:58] - wire _T_3016 = _T_3015 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_3017 = ~_T_3016; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_3 = buf_ageQ_3_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_3_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2920 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3548 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3571 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3575 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3582 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3583 = obuf_tag1 == 3'h2; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3584 = obuf_merge & _T_3583; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3585 = _T_3582 | _T_3584; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3586 = _T_3585 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3587 = _T_3586 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_308 = _T_3575 & _T_3587; // @[Conditional.scala 39:67] - wire _GEN_321 = _T_3571 ? 1'h0 : _GEN_308; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_321; // @[Conditional.scala 40:58] - wire _T_2921 = _T_2920 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2922 = ~_T_2921; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_2 = buf_ageQ_3_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2925 = ~buf_age_3_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_2 = _T_2925 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_3_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2825 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3340 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3363 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3367 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3374 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3375 = obuf_tag1 == 3'h1; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3376 = obuf_merge & _T_3375; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3377 = _T_3374 | _T_3376; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3378 = _T_3377 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3379 = _T_3378 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_218 = _T_3367 & _T_3379; // @[Conditional.scala 39:67] - wire _GEN_231 = _T_3363 ? 1'h0 : _GEN_218; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_231; // @[Conditional.scala 40:58] - wire _T_2826 = _T_2825 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2827 = ~_T_2826; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_1 = buf_ageQ_3_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2830 = ~buf_age_3_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_1 = _T_2830 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_3_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2730 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3132 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3155 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3159 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3166 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3167 = obuf_tag1 == 3'h0; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3168 = obuf_merge & _T_3167; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3169 = _T_3166 | _T_3168; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3170 = _T_3169 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3171 = _T_3170 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_128 = _T_3159 & _T_3171; // @[Conditional.scala 39:67] - wire _GEN_141 = _T_3155 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] - wire _T_2731 = _T_2730 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2732 = ~_T_2731; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_0 = buf_ageQ_3_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2735 = ~buf_age_3_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_0 = _T_2735 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_364 = {1'h0,buf_age_younger_3_2,buf_age_younger_3_1,buf_age_younger_3_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_365 = ld_byte_hitvec_lo_0 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_366 = |_T_365; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_367 = ~_T_366; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_368 = ld_byte_hitvec_lo_0[3] & _T_367; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_370 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_371 = _T_368 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_2_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_3 = buf_ageQ_2_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2640 = ~buf_age_2_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_3 = _T_2640 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_2_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_2 = buf_ageQ_2_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_2_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_1 = buf_ageQ_2_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2450 = ~buf_age_2_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_1 = _T_2450 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_2_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_0 = buf_ageQ_2_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2355 = ~buf_age_2_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_0 = _T_2355 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_353 = {buf_age_younger_2_3,1'h0,buf_age_younger_2_1,buf_age_younger_2_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_354 = ld_byte_hitvec_lo_0 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_355 = |_T_354; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_356 = ~_T_355; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_357 = ld_byte_hitvec_lo_0[2] & _T_356; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_360 = _T_357 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_1_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_3 = buf_ageQ_1_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2260 = ~buf_age_1_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_3 = _T_2260 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_1_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_2 = buf_ageQ_1_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2165 = ~buf_age_1_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_2 = _T_2165 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_1_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_1 = buf_ageQ_1_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_1_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_0 = buf_ageQ_1_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1975 = ~buf_age_1_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_0 = _T_1975 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_342 = {buf_age_younger_1_3,buf_age_younger_1_2,1'h0,buf_age_younger_1_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_343 = ld_byte_hitvec_lo_0 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_344 = |_T_343; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_345 = ~_T_344; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_346 = ld_byte_hitvec_lo_0[1] & _T_345; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_349 = _T_346 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_0_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_3 = buf_ageQ_0_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1880 = ~buf_age_0_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_3 = _T_1880 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_2 = buf_ageQ_0_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1785 = ~buf_age_0_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_2 = _T_1785 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_1 = buf_ageQ_0_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1690 = ~buf_age_0_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_1 = _T_1690 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_0 = buf_ageQ_0_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire [3:0] _T_331 = {buf_age_younger_0_3,buf_age_younger_0_2,buf_age_younger_0_1,1'h0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_332 = ld_byte_hitvec_lo_0 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_333 = |_T_332; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_334 = ~_T_333; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_335 = ld_byte_hitvec_lo_0[0] & _T_334; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_338 = _T_335 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_371,_T_360,_T_349,_T_338}; // @[Cat.scala 29:58] - wire _T_115 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_116 = ld_byte_ibuf_hit_lo[0] | _T_115; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_184 = ld_addr_hitvec_lo[3] & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_186 = _T_184 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_179 = ld_addr_hitvec_lo[2] & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_181 = _T_179 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_174 = ld_addr_hitvec_lo[1] & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_176 = _T_174 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_169 = ld_addr_hitvec_lo[0] & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_171 = _T_169 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_1 = {_T_186,_T_181,_T_176,_T_171}; // @[Cat.scala 29:58] - wire [3:0] _T_412 = ld_byte_hitvec_lo_1 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_413 = |_T_412; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_414 = ~_T_413; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_415 = ld_byte_hitvec_lo_1[3] & _T_414; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_417 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_418 = _T_415 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_401 = ld_byte_hitvec_lo_1 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_402 = |_T_401; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_403 = ~_T_402; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_404 = ld_byte_hitvec_lo_1[2] & _T_403; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_407 = _T_404 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_390 = ld_byte_hitvec_lo_1 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_391 = |_T_390; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_392 = ~_T_391; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_393 = ld_byte_hitvec_lo_1[1] & _T_392; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_396 = _T_393 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_379 = ld_byte_hitvec_lo_1 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_382 = ld_byte_hitvec_lo_1[0] & _T_381; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_385 = _T_382 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_418,_T_407,_T_396,_T_385}; // @[Cat.scala 29:58] - wire _T_118 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_119 = ld_byte_ibuf_hit_lo[1] | _T_118; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_207 = ld_addr_hitvec_lo[3] & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_209 = _T_207 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_202 = ld_addr_hitvec_lo[2] & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_204 = _T_202 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_197 = ld_addr_hitvec_lo[1] & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_199 = _T_197 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_192 = ld_addr_hitvec_lo[0] & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_194 = _T_192 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_2 = {_T_209,_T_204,_T_199,_T_194}; // @[Cat.scala 29:58] - wire [3:0] _T_459 = ld_byte_hitvec_lo_2 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_460 = |_T_459; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_461 = ~_T_460; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_462 = ld_byte_hitvec_lo_2[3] & _T_461; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_464 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_465 = _T_462 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_448 = ld_byte_hitvec_lo_2 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_449 = |_T_448; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_450 = ~_T_449; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_451 = ld_byte_hitvec_lo_2[2] & _T_450; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_454 = _T_451 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_437 = ld_byte_hitvec_lo_2 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_438 = |_T_437; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_439 = ~_T_438; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_440 = ld_byte_hitvec_lo_2[1] & _T_439; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_443 = _T_440 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_426 = ld_byte_hitvec_lo_2 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_427 = |_T_426; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_428 = ~_T_427; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_429 = ld_byte_hitvec_lo_2[0] & _T_428; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_432 = _T_429 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_465,_T_454,_T_443,_T_432}; // @[Cat.scala 29:58] - wire _T_121 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_122 = ld_byte_ibuf_hit_lo[2] | _T_121; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_230 = ld_addr_hitvec_lo[3] & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_232 = _T_230 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_225 = ld_addr_hitvec_lo[2] & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_227 = _T_225 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_220 = ld_addr_hitvec_lo[1] & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_222 = _T_220 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_215 = ld_addr_hitvec_lo[0] & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_217 = _T_215 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_3 = {_T_232,_T_227,_T_222,_T_217}; // @[Cat.scala 29:58] - wire [3:0] _T_506 = ld_byte_hitvec_lo_3 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_507 = |_T_506; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_508 = ~_T_507; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_509 = ld_byte_hitvec_lo_3[3] & _T_508; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_511 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_512 = _T_509 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_495 = ld_byte_hitvec_lo_3 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_496 = |_T_495; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_497 = ~_T_496; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_498 = ld_byte_hitvec_lo_3[2] & _T_497; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_501 = _T_498 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_484 = ld_byte_hitvec_lo_3 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_487 = ld_byte_hitvec_lo_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_490 = _T_487 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_473 = ld_byte_hitvec_lo_3 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_474 = |_T_473; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_475 = ~_T_474; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_476 = ld_byte_hitvec_lo_3[0] & _T_475; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_479 = _T_476 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_512,_T_501,_T_490,_T_479}; // @[Cat.scala 29:58] - wire _T_124 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_125 = ld_byte_ibuf_hit_lo[3] | _T_124; // @[el2_lsu_bus_buffer.scala 412:75] - wire [2:0] _T_127 = {_T_125,_T_122,_T_119}; // @[Cat.scala 29:58] - reg [31:0] ibuf_data; // @[Reg.scala 27:20] - reg [31:0] buf_data_0; // @[Reg.scala 27:20] - reg [31:0] buf_data_1; // @[Reg.scala 27:20] - reg [31:0] buf_data_2; // @[Reg.scala 27:20] - reg [31:0] buf_data_3; // @[Reg.scala 27:20] - wire [3:0] _T_866 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_867 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_868 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_869 = _T_866 | _T_867; // @[Mux.scala 27:72] - wire [3:0] ldst_byteen_r = _T_869 | _T_868; // @[Mux.scala 27:72] - wire [7:0] _T_874 = {4'h0,ldst_byteen_r}; // @[Cat.scala 29:58] - wire [10:0] _GEN_471 = {{3'd0}, _T_874}; // @[el2_lsu_bus_buffer.scala 432:71] - wire [10:0] ldst_byteen_extended_r = _GEN_471 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_buffer.scala 432:71] - wire [63:0] _T_878 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58] - wire [3:0] _GEN_472 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_bus_buffer.scala 433:82] - wire [5:0] _T_880 = 4'h8 * _GEN_472; // @[el2_lsu_bus_buffer.scala 433:82] - wire [126:0] _GEN_473 = {{63'd0}, _T_878}; // @[el2_lsu_bus_buffer.scala 433:75] - wire [126:0] store_data_extended_r = _GEN_473 << _T_880; // @[el2_lsu_bus_buffer.scala 433:75] - wire [3:0] ldst_byteen_hi_r = ldst_byteen_extended_r[7:4]; // @[el2_lsu_bus_buffer.scala 434:58] - wire [3:0] ldst_byteen_lo_r = ldst_byteen_extended_r[3:0]; // @[el2_lsu_bus_buffer.scala 435:58] - wire [31:0] store_data_hi_r = store_data_extended_r[63:32]; // @[el2_lsu_bus_buffer.scala 436:57] - wire [31:0] store_data_lo_r = store_data_extended_r[31:0]; // @[el2_lsu_bus_buffer.scala 437:57] - wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 438:53] - wire _T_891 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 441:96] - wire _T_894 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 442:98] - wire _T_896 = io_lsu_pkt_r_half & _T_891; // @[Mux.scala 27:72] - wire _T_897 = io_lsu_pkt_r_word & _T_894; // @[Mux.scala 27:72] - wire _T_898 = io_lsu_pkt_r_by | _T_896; // @[Mux.scala 27:72] - wire is_aligned_r = _T_898 | _T_897; // @[Mux.scala 27:72] - wire _T_901 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 445:71] - wire _T_902 = io_lsu_busreq_r & _T_901; // @[el2_lsu_bus_buffer.scala 445:50] - wire _T_903 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 445:95] - wire ibuf_byp = _T_902 & _T_903; // @[el2_lsu_bus_buffer.scala 445:93] - wire _T_906 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 446:50] - wire _T_907 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 446:70] - wire ibuf_wr_en = _T_906 & _T_907; // @[el2_lsu_bus_buffer.scala 446:68] - wire _T_910 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 447:52] - reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 465:35] - wire _T_923 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 449:74] - wire _T_924 = ibuf_wr_en | _T_923; // @[el2_lsu_bus_buffer.scala 449:60] - wire _T_1061 = _T_906 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 460:67] - wire _T_1062 = _T_1061 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 460:88] - wire _T_1063 = _T_1062 & ibuf_write; // @[el2_lsu_bus_buffer.scala 460:101] - wire _T_1066 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 460:135] - wire _T_1067 = _T_1063 & _T_1066; // @[el2_lsu_bus_buffer.scala 460:114] - wire _T_1068 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 460:156] - wire _T_1069 = _T_1067 & _T_1068; // @[el2_lsu_bus_buffer.scala 460:154] - wire _T_1070 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 460:179] - wire ibuf_merge_en = _T_1069 & _T_1070; // @[el2_lsu_bus_buffer.scala 460:177] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 461:33] - wire _T_925 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 449:131] - wire _T_926 = ~_T_925; // @[el2_lsu_bus_buffer.scala 449:115] - wire _T_927 = _T_924 & _T_926; // @[el2_lsu_bus_buffer.scala 449:113] - wire _T_928 = _T_927 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 449:149] - wire _T_914 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 448:52] - wire _T_915 = io_lsu_busreq_m & _T_914; // @[el2_lsu_bus_buffer.scala 448:50] - wire _T_916 = _T_915 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 448:69] - wire _T_919 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 448:122] - wire _T_920 = io_lsu_pkt_m_load | _T_919; // @[el2_lsu_bus_buffer.scala 448:103] - wire ibuf_force_drain = _T_916 & _T_920; // @[el2_lsu_bus_buffer.scala 448:82] - wire _T_929 = _T_928 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 450:45] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_350 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4142 = _GEN_350 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 508:77] + reg obuf_valid; // @[el2_lsu_bus_buffer.scala 399:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 398:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3949 = _GEN_350 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3756 = _GEN_350 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3563 = _GEN_350 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] + wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 199:97] + reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 205:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 205:73] + reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:54] + wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 205:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 205:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 210:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 210:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] + wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] + wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] + wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 191:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51] + wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73] + wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 211:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 192:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[el2_lib.scala 514:16] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[el2_lib.scala 514:16] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[el2_lib.scala 514:16] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[el2_lib.scala 514:16] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 221:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[el2_lib.scala 514:16] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 222:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 227:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 228:32] + wire [3:0] _T_750 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 235:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 236:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 237:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 238:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 255:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 257:26] + wire _T_845 = io_lsu_pkt_r_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 259:55] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 259:34] + wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 259:79] + wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 259:77] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 260:36] + wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 260:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 260:54] + wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 262:36] + reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 305:55] + wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 268:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 268:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 287:54] + wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 287:75] + wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 287:88] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 287:124] + wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 287:101] + wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 287:147] + wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 287:145] + wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 287:170] + wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 287:168] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 288:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 268:98] + wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 268:82] + wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 268:80] + wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 269:5] + wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 263:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 263:42] + wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 263:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 263:115] + wire _T_863 = io_lsu_pkt_m_load | _T_862; // @[el2_lsu_bus_buffer.scala 263:95] + wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 263:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 269:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_930 = _T_929 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 450:64] - wire _T_931 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 450:84] - wire _T_932 = _T_930 | _T_931; // @[el2_lsu_bus_buffer.scala 450:82] - wire _T_933 = _T_932 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 450:96] - wire ibuf_drain_vld = ibuf_valid & _T_933; // @[el2_lsu_bus_buffer.scala 449:44] - wire _T_911 = ibuf_drain_vld & _T_910; // @[el2_lsu_bus_buffer.scala 447:50] - wire ibuf_rst = _T_911 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 447:65] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 269:35] + wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 269:55] + wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 269:53] + wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 269:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 268:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 262:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 262:49] + reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 669:49] + reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 668:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] - reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 751:44] - reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 750:44] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_word,io_lsu_pkt_r_half}; // @[Cat.scala 29:58] - wire [3:0] _T_945 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 455:85] - wire [7:0] _T_954 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_957 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_958 = _T_925 ? _T_954 : _T_957; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_963 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_966 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_967 = _T_925 ? _T_963 : _T_966; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_972 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_975 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_976 = _T_925 ? _T_972 : _T_975; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_981 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_984 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_985 = _T_925 ? _T_981 : _T_984; // @[el2_lsu_bus_buffer.scala 456:57] - wire [31:0] ibuf_data_in = {_T_985,_T_976,_T_967,_T_958}; // @[Cat.scala 29:58] - wire _T_989 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 457:69] - wire [2:0] _T_991 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 457:115] - wire _T_994 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 458:75] - wire _T_995 = ibuf_merge_en & _T_994; // @[el2_lsu_bus_buffer.scala 458:73] - wire _T_998 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1000 = _T_995 ? _T_998 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1005 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1007 = _T_995 ? _T_1005 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1012 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1014 = _T_995 ? _T_1012 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1019 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1021 = _T_995 ? _T_1019 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 458:57] - wire [3:0] ibuf_byteen_out = {_T_1021,_T_1014,_T_1007,_T_1000}; // @[Cat.scala 29:58] - wire [7:0] _T_1032 = _T_995 ? _T_954 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1040 = _T_995 ? _T_963 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1048 = _T_995 ? _T_972 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1056 = _T_995 ? _T_981 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [31:0] ibuf_data_out = {_T_1056,_T_1048,_T_1040,_T_1032}; // @[Cat.scala 29:58] - wire _T_1074 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 464:32] - wire _T_1075 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 464:72] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 278:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 282:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 285:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 285:93] + wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 289:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 289:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 289:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:58] + wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 292:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] reg ibuf_dual; // @[Reg.scala 27:20] reg ibuf_samedw; // @[Reg.scala 27:20] reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] - wire _T_3984 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3985 = _T_2730 & _T_3984; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3986 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3987 = _T_3985 | _T_3986; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_3989 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3990 = _T_2825 & _T_3989; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3991 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3992 = _T_3990 | _T_3991; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4004 = _T_3987 + _T_3992; // @[el2_lsu_bus_buffer.scala 700:160] - wire _T_3994 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3995 = _T_2920 & _T_3994; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3996 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3997 = _T_3995 | _T_3996; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4006 = _T_4004 + _T_3997; // @[el2_lsu_bus_buffer.scala 700:160] - wire _T_3999 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_4000 = _T_3015 & _T_3999; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_4001 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_4002 = _T_4000 | _T_4001; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4008 = _T_4006 + _T_4002; // @[el2_lsu_bus_buffer.scala 700:160] - wire [3:0] buf_numvld_pend_any = {{3'd0}, _T_4008}; // @[el2_lsu_bus_buffer.scala 700:25] - wire _T_1095 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 483:67] - wire _T_1096 = ibuf_byp & _T_1095; // @[el2_lsu_bus_buffer.scala 483:39] - wire _T_1097 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 483:79] - wire _T_1098 = _T_1097 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 483:99] - wire ibuf_buf_byp = _T_1096 & _T_1098; // @[el2_lsu_bus_buffer.scala 483:76] - wire _T_1103 = _T_915 & _T_903; // @[el2_lsu_bus_buffer.scala 484:64] - wire _T_3978 = _T_3985 + _T_3990; // @[el2_lsu_bus_buffer.scala 699:158] - wire _T_3980 = _T_3978 + _T_3995; // @[el2_lsu_bus_buffer.scala 699:158] - wire _T_3982 = _T_3980 + _T_4000; // @[el2_lsu_bus_buffer.scala 699:158] - wire [3:0] buf_numvld_cmd_any = {{3'd0}, _T_3982}; // @[el2_lsu_bus_buffer.scala 699:25] - wire _T_1105 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 484:105] - wire _T_1106 = _T_1103 & _T_1105; // @[el2_lsu_bus_buffer.scala 484:78] - wire [3:0] _T_2961 = {buf_age_3_3,buf_age_3_2,buf_age_3_1,buf_age_3_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2962 = |_T_2961; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2963 = ~_T_2962; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2965 = _T_2963 & _T_3015; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_3 = _T_2965 & _T_3999; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_2581 = {buf_age_2_3,buf_age_2_2,buf_age_2_1,buf_age_2_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2582 = |_T_2581; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2583 = ~_T_2582; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2585 = _T_2583 & _T_2920; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_2 = _T_2585 & _T_3994; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_2201 = {buf_age_1_3,buf_age_1_2,buf_age_1_1,buf_age_1_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2202 = |_T_2201; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2203 = ~_T_2202; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2205 = _T_2203 & _T_2825; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_1 = _T_2205 & _T_3989; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_1821 = {buf_age_0_3,buf_age_0_2,buf_age_0_1,buf_age_0_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_1822 = |_T_1821; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_1823 = ~_T_1822; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_1825 = _T_1823 & _T_2730; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_0 = _T_1825 & _T_3984; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_3056 = {CmdPtr0Dec_3,CmdPtr0Dec_2,CmdPtr0Dec_1,CmdPtr0Dec_0}; // @[el2_lsu_bus_buffer.scala 578:59] - wire [3:0] _T_3061 = _T_3056[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3062 = _T_3056[2] ? 4'h4 : _T_3061; // @[Mux.scala 47:69] - wire [3:0] _T_3063 = _T_3056[1] ? 4'h2 : _T_3062; // @[Mux.scala 47:69] - wire [3:0] _T_3064 = _T_3056[0] ? 4'h1 : _T_3063; // @[Mux.scala 47:69] - wire [1:0] CmdPtr0 = _T_3064[1:0]; // @[el2_lsu_bus_buffer.scala 578:27] - wire [31:0] _GEN_13 = 2'h1 == CmdPtr0 ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 484:163] - wire [31:0] _GEN_14 = 2'h2 == CmdPtr0 ? buf_addr_2 : _GEN_13; // @[el2_lsu_bus_buffer.scala 484:163] - wire [31:0] _GEN_15 = 2'h3 == CmdPtr0 ? buf_addr_3 : _GEN_14; // @[el2_lsu_bus_buffer.scala 484:163] - wire _T_1109 = io_lsu_addr_m[31:2] != _GEN_15[31:2]; // @[el2_lsu_bus_buffer.scala 484:142] - wire obuf_force_wr_en = _T_1106 & _T_1109; // @[el2_lsu_bus_buffer.scala 484:119] - wire _T_3946 = _T_3985 & buf_write_0; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3950 = _T_3990 & buf_write_1; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3960 = _T_3946 + _T_3950; // @[el2_lsu_bus_buffer.scala 698:158] - wire _T_3954 = _T_3995 & buf_write_2; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3962 = _T_3960 + _T_3954; // @[el2_lsu_bus_buffer.scala 698:158] - wire _T_3958 = _T_4000 & buf_write_3; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3964 = _T_3962 + _T_3958; // @[el2_lsu_bus_buffer.scala 698:158] - wire [3:0] buf_numvld_wrcmd_any = {{3'd0}, _T_3964}; // @[el2_lsu_bus_buffer.scala 698:25] - wire _T_1112 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 485:56] - wire _T_1115 = _T_1112 & _T_1105; // @[el2_lsu_bus_buffer.scala 485:70] - reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 527:35] - wire _T_1116 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 485:128] - wire _T_1117 = _T_1115 & _T_1116; // @[el2_lsu_bus_buffer.scala 485:111] - wire _T_1119 = _T_1117 & _T_1070; // @[el2_lsu_bus_buffer.scala 485:166] + wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 575:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _GEN_354 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_354; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 575:89] + wire [2:0] _GEN_355 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_355; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:43] + wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:73] + wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _GEN_356 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_356; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:73] + wire [2:0] _GEN_357 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_357; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:72] + wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 315:51] + reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 414:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 315:97] + wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 315:80] + wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 315:114] + wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 431:88] + wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 444:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 316:114] reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] - wire _GEN_17 = 2'h1 == CmdPtr0 ? buf_nomerge_1 : buf_nomerge_0; // @[el2_lsu_bus_buffer.scala 486:59] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] - wire _GEN_18 = 2'h2 == CmdPtr0 ? buf_nomerge_2 : _GEN_17; // @[el2_lsu_bus_buffer.scala 486:59] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] - wire _GEN_19 = 2'h3 == CmdPtr0 ? buf_nomerge_3 : _GEN_18; // @[el2_lsu_bus_buffer.scala 486:59] - wire _T_1120 = ~_GEN_19; // @[el2_lsu_bus_buffer.scala 486:59] - wire _T_1121 = _T_1119 & _T_1120; // @[el2_lsu_bus_buffer.scala 486:57] - reg buf_sideeffect_0; // @[Reg.scala 27:20] - reg buf_sideeffect_1; // @[Reg.scala 27:20] - wire _GEN_21 = 2'h1 == CmdPtr0 ? buf_sideeffect_1 : buf_sideeffect_0; // @[el2_lsu_bus_buffer.scala 486:83] - reg buf_sideeffect_2; // @[Reg.scala 27:20] - wire _GEN_22 = 2'h2 == CmdPtr0 ? buf_sideeffect_2 : _GEN_21; // @[el2_lsu_bus_buffer.scala 486:83] - reg buf_sideeffect_3; // @[Reg.scala 27:20] - wire _GEN_23 = 2'h3 == CmdPtr0 ? buf_sideeffect_3 : _GEN_22; // @[el2_lsu_bus_buffer.scala 486:83] - wire _T_1122 = ~_GEN_23; // @[el2_lsu_bus_buffer.scala 486:83] - wire _T_1123 = _T_1121 & _T_1122; // @[el2_lsu_bus_buffer.scala 486:81] - wire _T_1124 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 486:110] - wire obuf_wr_wait = _T_1123 & _T_1124; // @[el2_lsu_bus_buffer.scala 486:108] - wire _T_1126 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 487:44] - reg obuf_sideeffect; // @[Reg.scala 27:20] - wire _T_4231 = obuf_sideeffect & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:62] - wire _T_4232 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4233 = buf_sideeffect_0 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4240 = _T_4232 & _T_4233; // @[Mux.scala 27:72] - wire _T_4234 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4235 = buf_sideeffect_1 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4241 = _T_4234 & _T_4235; // @[Mux.scala 27:72] - wire _T_4244 = _T_4240 | _T_4241; // @[Mux.scala 27:72] - wire _T_4236 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4237 = buf_sideeffect_2 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4242 = _T_4236 & _T_4237; // @[Mux.scala 27:72] - wire _T_4245 = _T_4244 | _T_4242; // @[Mux.scala 27:72] - wire _T_4238 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4239 = buf_sideeffect_3 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4243 = _T_4238 & _T_4239; // @[Mux.scala 27:72] - wire _T_4246 = _T_4245 | _T_4243; // @[Mux.scala 27:72] - wire bus_sideeffect_pend = obuf_valid ? _T_4231 : _T_4246; // @[el2_lsu_bus_buffer.scala 731:34] - wire _T_1127 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 487:86] - wire _T_1128 = ~_T_1127; // @[el2_lsu_bus_buffer.scala 487:64] - wire _T_1129 = _T_1126 & _T_1128; // @[el2_lsu_bus_buffer.scala 487:62] - wire [2:0] _GEN_25 = 2'h1 == CmdPtr0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 488:54] - wire [2:0] _GEN_26 = 2'h2 == CmdPtr0 ? buf_state_2 : _GEN_25; // @[el2_lsu_bus_buffer.scala 488:54] - wire [2:0] _GEN_27 = 2'h3 == CmdPtr0 ? buf_state_3 : _GEN_26; // @[el2_lsu_bus_buffer.scala 488:54] - wire _T_1130 = _GEN_27 == 3'h2; // @[el2_lsu_bus_buffer.scala 488:54] - wire _T_3087 = CmdPtr0Dec_0 | CmdPtr0Dec_1; // @[el2_lsu_bus_buffer.scala 581:49] - wire _T_3088 = _T_3087 | CmdPtr0Dec_2; // @[el2_lsu_bus_buffer.scala 581:49] - wire found_cmdptr0 = _T_3088 | CmdPtr0Dec_3; // @[el2_lsu_bus_buffer.scala 581:49] - wire _T_1131 = _T_1130 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 488:65] - wire _GEN_29 = 2'h1 == CmdPtr0 ? buf_cmd_state_bus_en_1 : buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 488:83] - wire _GEN_30 = 2'h2 == CmdPtr0 ? buf_cmd_state_bus_en_2 : _GEN_29; // @[el2_lsu_bus_buffer.scala 488:83] - wire _GEN_31 = 2'h3 == CmdPtr0 ? buf_cmd_state_bus_en_3 : _GEN_30; // @[el2_lsu_bus_buffer.scala 488:83] - wire _T_1132 = ~_GEN_31; // @[el2_lsu_bus_buffer.scala 488:83] - wire _T_1133 = _T_1131 & _T_1132; // @[el2_lsu_bus_buffer.scala 488:81] - wire _T_1134 = _GEN_23 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 488:142] - wire _T_1135 = ~_T_1134; // @[el2_lsu_bus_buffer.scala 488:116] - wire _T_1136 = _T_1133 & _T_1135; // @[el2_lsu_bus_buffer.scala 488:114] - reg buf_dual_0; // @[Reg.scala 27:20] - reg buf_dual_1; // @[Reg.scala 27:20] - wire _GEN_33 = 2'h1 == CmdPtr0 ? buf_dual_1 : buf_dual_0; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_dual_2; // @[Reg.scala 27:20] - wire _GEN_34 = 2'h2 == CmdPtr0 ? buf_dual_2 : _GEN_33; // @[el2_lsu_bus_buffer.scala 489:58] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 316:31] + wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 316:29] + reg _T_4330; // @[Reg.scala 27:20] + reg _T_4327; // @[Reg.scala 27:20] + reg _T_4324; // @[Reg.scala 27:20] + reg _T_4321; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 317:5] + wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 316:140] + wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 319:58] + wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 319:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 319:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 319:101] + wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 317:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 317:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 318:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 318:95] + wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 318:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 318:121] + wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 577:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _GEN_358 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_358; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 577:74] + wire [2:0] _GEN_359 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_359; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 321:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 321:31] + wire _T_1089 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 321:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 321:84] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 321:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 336:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 336:74] + wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 336:52] + wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 336:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 337:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 436:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 337:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 338:23] + wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 338:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 338:141] + wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 338:105] + wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 338:103] reg buf_dual_3; // @[Reg.scala 27:20] - wire _GEN_35 = 2'h3 == CmdPtr0 ? buf_dual_3 : _GEN_34; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_samedw_0; // @[Reg.scala 27:20] - reg buf_samedw_1; // @[Reg.scala 27:20] - wire _GEN_37 = 2'h1 == CmdPtr0 ? buf_samedw_1 : buf_samedw_0; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_samedw_2; // @[Reg.scala 27:20] - wire _GEN_38 = 2'h2 == CmdPtr0 ? buf_samedw_2 : _GEN_37; // @[el2_lsu_bus_buffer.scala 489:58] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] reg buf_samedw_3; // @[Reg.scala 27:20] - wire _GEN_39 = 2'h3 == CmdPtr0 ? buf_samedw_3 : _GEN_38; // @[el2_lsu_bus_buffer.scala 489:58] - wire _T_1137 = _GEN_35 & _GEN_39; // @[el2_lsu_bus_buffer.scala 489:58] - wire _GEN_41 = 2'h1 == CmdPtr0 ? buf_write_1 : buf_write_0; // @[el2_lsu_bus_buffer.scala 489:82] - wire _GEN_42 = 2'h2 == CmdPtr0 ? buf_write_2 : _GEN_41; // @[el2_lsu_bus_buffer.scala 489:82] - wire _GEN_43 = 2'h3 == CmdPtr0 ? buf_write_3 : _GEN_42; // @[el2_lsu_bus_buffer.scala 489:82] - wire _T_1138 = ~_GEN_43; // @[el2_lsu_bus_buffer.scala 489:82] - wire _T_1139 = _T_1137 & _T_1138; // @[el2_lsu_bus_buffer.scala 489:80] - wire _T_1140 = ~_T_1139; // @[el2_lsu_bus_buffer.scala 489:38] - wire [3:0] _T_1834 = ~_T_3056; // @[el2_lsu_bus_buffer.scala 559:55] - wire [3:0] _T_1835 = _T_1821 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_1836 = |_T_1835; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_1837 = ~_T_1836; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_1838 = ~CmdPtr0Dec_0; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_1839 = _T_1837 & _T_1838; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_1841 = _T_1839 & _T_2730; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_0 = _T_1841 & _T_3984; // @[el2_lsu_bus_buffer.scala 559:126] - wire [3:0] _T_2215 = _T_2201 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2216 = |_T_2215; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2217 = ~_T_2216; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2218 = ~CmdPtr0Dec_1; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2219 = _T_2217 & _T_2218; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2221 = _T_2219 & _T_2825; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_1 = _T_2221 & _T_3989; // @[el2_lsu_bus_buffer.scala 559:126] - wire _T_3090 = CmdPtr1Dec_0 | CmdPtr1Dec_1; // @[el2_lsu_bus_buffer.scala 582:49] - wire [3:0] _T_2595 = _T_2581 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2596 = |_T_2595; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2597 = ~_T_2596; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2598 = ~CmdPtr0Dec_2; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2599 = _T_2597 & _T_2598; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2601 = _T_2599 & _T_2920; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_2 = _T_2601 & _T_3994; // @[el2_lsu_bus_buffer.scala 559:126] - wire _T_3091 = _T_3090 | CmdPtr1Dec_2; // @[el2_lsu_bus_buffer.scala 582:49] - wire [3:0] _T_2975 = _T_2961 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2976 = |_T_2975; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2977 = ~_T_2976; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2978 = ~CmdPtr0Dec_3; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2979 = _T_2977 & _T_2978; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2981 = _T_2979 & _T_3015; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_3 = _T_2981 & _T_3999; // @[el2_lsu_bus_buffer.scala 559:126] - wire found_cmdptr1 = _T_3091 | CmdPtr1Dec_3; // @[el2_lsu_bus_buffer.scala 582:49] - wire _T_1141 = _T_1140 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 489:103] - wire _T_1142 = _T_1141 | _GEN_19; // @[el2_lsu_bus_buffer.scala 489:119] - wire _T_1143 = _T_1142 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 489:142] - wire _T_1144 = _T_1136 & _T_1143; // @[el2_lsu_bus_buffer.scala 488:165] - wire _T_1145 = _T_1129 | _T_1144; // @[el2_lsu_bus_buffer.scala 487:110] - wire _T_1146 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 490:57] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 339:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 339:150] + wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 339:148] + wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 339:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 432:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 437:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 339:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 339:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 339:269] + wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 338:164] + wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 336:98] reg obuf_write; // @[Reg.scala 27:20] - reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 525:35] - reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 526:35] - wire _T_4309 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 734:66] - wire _T_4310 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 734:88] - wire _T_4311 = io_lsu_axi_awready & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 734:164] - wire _T_4312 = _T_4309 ? _T_4310 : _T_4311; // @[el2_lsu_bus_buffer.scala 734:50] - wire bus_cmd_ready = obuf_write ? _T_4312 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 734:34] - wire _T_1147 = bus_cmd_ready | _T_1146; // @[el2_lsu_bus_buffer.scala 490:55] + reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 401:54] + reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 402:55] + wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 609:54] + wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:75] + wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:39] + wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 609:23] + wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 340:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 340:46] reg obuf_nosend; // @[Reg.scala 27:20] - wire _T_1148 = _T_1147 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 490:69] - wire _T_1149 = _T_1145 & _T_1148; // @[el2_lsu_bus_buffer.scala 489:164] - wire _T_1150 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 490:86] - wire _T_1151 = _T_1149 & _T_1150; // @[el2_lsu_bus_buffer.scala 490:84] - reg [63:0] _T_1397; // @[Reg.scala 27:20] - wire [31:0] obuf_addr = _T_1397[31:0]; // @[el2_lsu_bus_buffer.scala 520:25] - wire _T_4252 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4253 = obuf_valid & _T_4252; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4260 = ~_T_3169; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4261 = _T_4232 & _T_4260; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4301 = _T_4253 & _T_4261; // @[Mux.scala 27:72] - wire _T_4265 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4266 = obuf_valid & _T_4265; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4273 = ~_T_3377; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4274 = _T_4234 & _T_4273; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4302 = _T_4266 & _T_4274; // @[Mux.scala 27:72] - wire _T_4305 = _T_4301 | _T_4302; // @[Mux.scala 27:72] - wire _T_4278 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4279 = obuf_valid & _T_4278; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4286 = ~_T_3585; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4287 = _T_4236 & _T_4286; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4303 = _T_4279 & _T_4287; // @[Mux.scala 27:72] - wire _T_4306 = _T_4305 | _T_4303; // @[Mux.scala 27:72] - wire _T_4291 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4292 = obuf_valid & _T_4291; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4299 = ~_T_3793; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4300 = _T_4238 & _T_4299; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4304 = _T_4292 & _T_4300; // @[Mux.scala 27:72] - wire bus_addr_match_pending = _T_4306 | _T_4304; // @[Mux.scala 27:72] - wire _T_1154 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 490:127] - wire _T_1155 = _T_1151 & _T_1154; // @[el2_lsu_bus_buffer.scala 490:125] - wire obuf_wr_en = _T_1155 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:151] - wire _T_1157 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 491:58] - wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 735:50] - wire _T_4316 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 737:47] - wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 736:49] - wire _T_4317 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 737:82] - wire _T_4318 = _T_4316 & _T_4317; // @[el2_lsu_bus_buffer.scala 737:64] - wire _T_4319 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 737:123] - wire bus_cmd_sent = _T_4318 | _T_4319; // @[el2_lsu_bus_buffer.scala 737:101] - wire _T_1158 = bus_cmd_sent | _T_1157; // @[el2_lsu_bus_buffer.scala 491:44] - wire _T_1159 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 491:76] - wire _T_1160 = _T_1158 & _T_1159; // @[el2_lsu_bus_buffer.scala 491:74] - wire _T_1161 = _T_1160 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 491:88] - wire obuf_rst = _T_1161 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 491:109] - wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _GEN_43; // @[el2_lsu_bus_buffer.scala 492:32] - wire [31:0] _T_1212 = ibuf_buf_byp ? io_lsu_addr_r : _GEN_15; // @[el2_lsu_bus_buffer.scala 498:32] - wire [63:0] obuf_addr_in = {{32'd0}, _T_1212}; // @[el2_lsu_bus_buffer.scala 498:26] - wire _T_1166 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 493:49] - reg [1:0] buf_sz_3; // @[Reg.scala 27:20] - reg [1:0] buf_sz_2; // @[Reg.scala 27:20] - reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 340:60] + wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 340:29] + wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 340:77] + wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 340:75] + reg [31:0] obuf_addr; // @[el2_lib.scala 514:16] + wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72] + wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72] + wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72] + wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72] + wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72] + wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72] + wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 340:118] + wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 340:116] + wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 340:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 342:47] + wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39] + wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 612:35] + wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 611:39] + wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 612:70] + wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 612:52] + wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 612:111] + wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 612:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 342:33] + wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 342:65] + wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 342:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 342:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 342:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _T_1202; // @[el2_lsu_bus_buffer.scala 343:26] + wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] + wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 345:25] reg [1:0] buf_sz_0; // @[Reg.scala 27:20] - wire [1:0] _GEN_45 = 2'h1 == CmdPtr0 ? buf_sz_1 : buf_sz_0; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] _GEN_46 = 2'h2 == CmdPtr0 ? buf_sz_2 : _GEN_45; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] _GEN_47 = 2'h3 == CmdPtr0 ? buf_sz_3 : _GEN_46; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _GEN_47; // @[el2_lsu_bus_buffer.scala 500:32] - wire _T_1199 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 497:78] - wire _T_1202 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 497:110] - wire _T_1203 = obuf_sz_in[0] & _T_1202; // @[el2_lsu_bus_buffer.scala 497:108] - wire _T_1204 = _T_1199 | _T_1203; // @[el2_lsu_bus_buffer.scala 497:91] - wire _T_1207 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 497:167] - wire _T_1208 = ~_T_1207; // @[el2_lsu_bus_buffer.scala 497:147] - wire _T_1209 = obuf_sz_in[1] & _T_1208; // @[el2_lsu_bus_buffer.scala 497:145] - wire _T_1210 = _T_1204 | _T_1209; // @[el2_lsu_bus_buffer.scala 497:128] - wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1210; // @[el2_lsu_bus_buffer.scala 497:32] - wire _T_1167 = _T_1166 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 493:70] - wire _T_1168 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 493:90] - wire _T_1169 = _T_1167 & _T_1168; // @[el2_lsu_bus_buffer.scala 493:88] - wire _T_1170 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 493:109] - wire _T_1171 = _T_1169 & _T_1170; // @[el2_lsu_bus_buffer.scala 493:107] - wire _T_1172 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 493:123] - wire _T_1173 = _T_1171 & _T_1172; // @[el2_lsu_bus_buffer.scala 493:121] - wire _T_1174 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 493:140] - wire _T_1175 = _T_1173 & _T_1174; // @[el2_lsu_bus_buffer.scala 493:138] - wire _T_1176 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 494:48] - wire _T_1177 = obuf_valid & _T_1176; // @[el2_lsu_bus_buffer.scala 494:46] - reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 524:35] - wire _T_1178 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 494:118] - wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 739:49] - wire _T_1179 = bus_rsp_read & _T_1178; // @[el2_lsu_bus_buffer.scala 494:98] - wire _T_1180 = ~_T_1179; // @[el2_lsu_bus_buffer.scala 494:83] - reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 523:35] - wire _T_1181 = obuf_rdrsp_pend & _T_1180; // @[el2_lsu_bus_buffer.scala 494:81] - wire _T_1182 = _T_1177 | _T_1181; // @[el2_lsu_bus_buffer.scala 494:62] - wire obuf_nosend_in = _T_1175 & _T_1182; // @[el2_lsu_bus_buffer.scala 493:175] - wire _T_1184 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 495:45] - wire _T_1185 = obuf_wr_en & _T_1184; // @[el2_lsu_bus_buffer.scala 495:43] - wire _T_1186 = ~_T_1185; // @[el2_lsu_bus_buffer.scala 495:30] - wire _T_1187 = _T_1186 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 495:62] - wire _T_1191 = _T_1187 & _T_1180; // @[el2_lsu_bus_buffer.scala 495:80] - wire _T_1193 = bus_cmd_sent & _T_1170; // @[el2_lsu_bus_buffer.scala 495:156] - wire _T_1194 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 495:173] - wire _T_1195 = _T_1193 & _T_1194; // @[el2_lsu_bus_buffer.scala 495:171] - wire [7:0] _T_1366 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1368 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1369 = io_end_addr_r[2] ? _T_1366 : _T_1368; // @[el2_lsu_bus_buffer.scala 516:49] - wire [3:0] _T_3067 = {CmdPtr1Dec_3,CmdPtr1Dec_2,CmdPtr1Dec_1,CmdPtr1Dec_0}; // @[el2_lsu_bus_buffer.scala 579:59] - wire [3:0] _T_3072 = _T_3067[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3073 = _T_3067[2] ? 4'h4 : _T_3072; // @[Mux.scala 47:69] - wire [3:0] _T_3074 = _T_3067[1] ? 4'h2 : _T_3073; // @[Mux.scala 47:69] - wire [3:0] _T_3075 = _T_3067[0] ? 4'h1 : _T_3074; // @[Mux.scala 47:69] - wire [1:0] CmdPtr1 = _T_3075[1:0]; // @[el2_lsu_bus_buffer.scala 579:27] - wire [31:0] _GEN_57 = 2'h1 == CmdPtr1 ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 511:124] - wire [31:0] _GEN_58 = 2'h2 == CmdPtr1 ? buf_addr_2 : _GEN_57; // @[el2_lsu_bus_buffer.scala 511:124] - wire [31:0] _GEN_59 = 2'h3 == CmdPtr1 ? buf_addr_3 : _GEN_58; // @[el2_lsu_bus_buffer.scala 511:124] - wire [3:0] _GEN_69 = 2'h1 == CmdPtr1 ? buf_byteen_1 : buf_byteen_0; // @[Cat.scala 29:58] - wire [3:0] _GEN_70 = 2'h2 == CmdPtr1 ? buf_byteen_2 : _GEN_69; // @[Cat.scala 29:58] - wire [3:0] _GEN_71 = 2'h3 == CmdPtr1 ? buf_byteen_3 : _GEN_70; // @[Cat.scala 29:58] - wire [7:0] _T_1371 = {_GEN_71,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1372 = {4'h0,_GEN_71}; // @[Cat.scala 29:58] - wire [7:0] _T_1373 = _GEN_59[2] ? _T_1371 : _T_1372; // @[el2_lsu_bus_buffer.scala 516:150] - wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1369 : _T_1373; // @[el2_lsu_bus_buffer.scala 516:31] - wire _T_1316 = CmdPtr0 != CmdPtr1; // @[el2_lsu_bus_buffer.scala 509:39] - wire _T_1317 = _T_1316 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 509:52] - wire _T_1318 = _T_1317 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 509:68] - wire _T_1320 = _T_1318 & _T_1130; // @[el2_lsu_bus_buffer.scala 509:84] - wire [2:0] _GEN_49 = 2'h1 == CmdPtr1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 509:139] - wire [2:0] _GEN_50 = 2'h2 == CmdPtr1 ? buf_state_2 : _GEN_49; // @[el2_lsu_bus_buffer.scala 509:139] - wire [2:0] _GEN_51 = 2'h3 == CmdPtr1 ? buf_state_3 : _GEN_50; // @[el2_lsu_bus_buffer.scala 509:139] - wire _T_1321 = _GEN_51 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:139] - wire _T_1322 = _T_1320 & _T_1321; // @[el2_lsu_bus_buffer.scala 509:117] - wire _T_1324 = _T_1322 & _T_1132; // @[el2_lsu_bus_buffer.scala 509:150] - wire _T_1326 = _T_1324 & _T_1122; // @[el2_lsu_bus_buffer.scala 510:62] - wire _T_1337 = _T_1138 & _GEN_35; // @[el2_lsu_bus_buffer.scala 512:58] + wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] + wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 348:23] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 357:39] + wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 357:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 361:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 361:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 361:96] + wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 361:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 361:153] + wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 361:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 361:132] + wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 361:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 361:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 375:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 375:60] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 375:80] + wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 375:78] + wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 375:99] + wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 375:97] + wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 375:113] + wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 375:111] + wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 375:130] + wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 375:128] + wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 376:20] + wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 376:18] + reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 403:56] + wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 613:37] + reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 404:55] + wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 376:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 376:70] + wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 376:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 376:53] + wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 376:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 375:165] + wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 369:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 369:42] + wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 369:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 369:61] + wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 369:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 370:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 370:37] + wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 370:35] + wire _T_1336 = bus_cmd_sent | _T_1343; // @[el2_lsu_bus_buffer.scala 372:44] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 377:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 378:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 377:28] + wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 379:46] + wire [7:0] _T_1432 = {buf_byteen_0,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,buf_byteen_0}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = buf_addr_0[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 380:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 379:28] + wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 382:44] + wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72] + wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72] + wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] + wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 383:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 382:26] + wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 384:44] + wire [63:0] _T_1522 = {buf_data_0,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,buf_data_0}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = buf_addr_0[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 385:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 384:26] + wire _T_1621 = CmdPtr0 != 2'h0; // @[el2_lsu_bus_buffer.scala 391:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 391:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 391:59] + wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 391:75] + wire _T_1651 = _T_1637 & _T_2606; // @[el2_lsu_bus_buffer.scala 391:118] + wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 391:161] + wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 392:85] + wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 395:38] reg buf_dualhi_3; // @[Reg.scala 27:20] reg buf_dualhi_2; // @[Reg.scala 27:20] reg buf_dualhi_1; // @[Reg.scala 27:20] reg buf_dualhi_0; // @[Reg.scala 27:20] - wire _GEN_61 = 2'h1 == CmdPtr0 ? buf_dualhi_1 : buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 512:80] - wire _GEN_62 = 2'h2 == CmdPtr0 ? buf_dualhi_2 : _GEN_61; // @[el2_lsu_bus_buffer.scala 512:80] - wire _GEN_63 = 2'h3 == CmdPtr0 ? buf_dualhi_3 : _GEN_62; // @[el2_lsu_bus_buffer.scala 512:80] - wire _T_1338 = ~_GEN_63; // @[el2_lsu_bus_buffer.scala 512:80] - wire _T_1339 = _T_1337 & _T_1338; // @[el2_lsu_bus_buffer.scala 512:78] - wire _T_1340 = _T_1339 & _GEN_39; // @[el2_lsu_bus_buffer.scala 512:101] - wire _T_1342 = _T_1326 & _T_1340; // @[el2_lsu_bus_buffer.scala 510:89] - wire _T_1343 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 513:54] - wire _T_1344 = _T_1343 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 513:70] - wire obuf_merge_en = _T_1342 | _T_1344; // @[el2_lsu_bus_buffer.scala 512:126] - wire _T_1214 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [63:0] _T_1388 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1390 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1391 = io_lsu_addr_r[2] ? _T_1388 : _T_1390; // @[el2_lsu_bus_buffer.scala 518:49] - wire [31:0] _GEN_77 = 2'h1 == CmdPtr1 ? buf_data_1 : buf_data_0; // @[Cat.scala 29:58] - wire [31:0] _GEN_78 = 2'h2 == CmdPtr1 ? buf_data_2 : _GEN_77; // @[Cat.scala 29:58] - wire [31:0] _GEN_79 = 2'h3 == CmdPtr1 ? buf_data_3 : _GEN_78; // @[Cat.scala 29:58] - wire [63:0] _T_1393 = {_GEN_79,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1394 = {32'h0,_GEN_79}; // @[Cat.scala 29:58] - wire [63:0] _T_1395 = _GEN_59[2] ? _T_1393 : _T_1394; // @[el2_lsu_bus_buffer.scala 518:150] - wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1391 : _T_1395; // @[el2_lsu_bus_buffer.scala 518:31] - wire [63:0] _T_1377 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1379 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1380 = io_lsu_addr_r[2] ? _T_1377 : _T_1379; // @[el2_lsu_bus_buffer.scala 517:49] - wire [31:0] _GEN_73 = 2'h1 == CmdPtr0 ? buf_data_1 : buf_data_0; // @[Cat.scala 29:58] - wire [31:0] _GEN_74 = 2'h2 == CmdPtr0 ? buf_data_2 : _GEN_73; // @[Cat.scala 29:58] - wire [31:0] _GEN_75 = 2'h3 == CmdPtr0 ? buf_data_3 : _GEN_74; // @[Cat.scala 29:58] - wire [63:0] _T_1382 = {_GEN_75,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1383 = {32'h0,_GEN_75}; // @[Cat.scala 29:58] - wire [63:0] _T_1384 = _GEN_15[2] ? _T_1382 : _T_1383; // @[el2_lsu_bus_buffer.scala 517:150] - wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1380 : _T_1384; // @[el2_lsu_bus_buffer.scala 517:31] - wire [7:0] _T_1217 = _T_1214 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1219 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1222 = _T_1219 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1224 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1227 = _T_1224 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1229 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1232 = _T_1229 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1234 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1237 = _T_1234 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1239 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1242 = _T_1239 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1244 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1247 = _T_1244 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1249 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1252 = _T_1249 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 499:53] - wire [63:0] obuf_data_in = {_T_1252,_T_1247,_T_1242,_T_1237,_T_1232,_T_1227,_T_1222,_T_1217}; // @[Cat.scala 29:58] - wire [7:0] _T_1355 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1355 : _T_1357; // @[el2_lsu_bus_buffer.scala 515:49] - wire [3:0] _GEN_65 = 2'h1 == CmdPtr0 ? buf_byteen_1 : buf_byteen_0; // @[Cat.scala 29:58] - wire [3:0] _GEN_66 = 2'h2 == CmdPtr0 ? buf_byteen_2 : _GEN_65; // @[Cat.scala 29:58] - wire [3:0] _GEN_67 = 2'h3 == CmdPtr0 ? buf_byteen_3 : _GEN_66; // @[Cat.scala 29:58] - wire [7:0] _T_1360 = {_GEN_67,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1361 = {4'h0,_GEN_67}; // @[Cat.scala 29:58] - wire [7:0] _T_1362 = _GEN_15[2] ? _T_1360 : _T_1361; // @[el2_lsu_bus_buffer.scala 515:150] - wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1362; // @[el2_lsu_bus_buffer.scala 515:31] - wire _T_1265 = obuf_byteen0_in[0] | _T_1214; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1269 = obuf_byteen0_in[1] | _T_1219; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1273 = obuf_byteen0_in[2] | _T_1224; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1277 = obuf_byteen0_in[3] | _T_1229; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1281 = obuf_byteen0_in[4] | _T_1234; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1285 = obuf_byteen0_in[5] | _T_1239; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1289 = obuf_byteen0_in[6] | _T_1244; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1293 = obuf_byteen0_in[7] | _T_1249; // @[el2_lsu_bus_buffer.scala 501:69] - wire [7:0] obuf_byteen_in = {_T_1293,_T_1289,_T_1285,_T_1281,_T_1277,_T_1273,_T_1269,_T_1265}; // @[Cat.scala 29:58] - wire _T_1301 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 503:42] - wire _T_1302 = ~_T_1301; // @[el2_lsu_bus_buffer.scala 503:29] - wire [1:0] _T_1309 = ibuf_buf_byp ? WrPtr0_r : CmdPtr0; // @[el2_lsu_bus_buffer.scala 505:32] - wire [1:0] _T_1310 = ibuf_buf_byp ? WrPtr1_r : CmdPtr0; // @[el2_lsu_bus_buffer.scala 506:32] - wire _T_1346 = buf_numvld_cmd_any > 4'h0; // @[el2_lsu_bus_buffer.scala 514:74] - wire _T_1347 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 514:103] - wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 514:86] - wire [2:0] _T_1350 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 514:154] - reg [63:0] obuf_data; // @[Reg.scala 27:20] - wire _T_1406 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 531:32] - wire _T_1407 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 531:72] + wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72] + wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72] + wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72] + wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] + wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] + wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 395:109] + wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 395:107] + wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 395:179] + wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 392:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 396:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 396:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 395:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 386:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 399:58] + wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 399:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] - wire [2:0] obuf_tag0_in = {{1'd0}, _T_1309}; // @[el2_lsu_bus_buffer.scala 505:26] - wire [2:0] obuf_tag1_in = {{1'd0}, _T_1310}; // @[el2_lsu_bus_buffer.scala 506:26] - wire _T_1418 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1419 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1420 = ibuf_valid & _T_1419; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1421 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1422 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1423 = io_ldst_dual_r & _T_1422; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1424 = _T_1421 | _T_1423; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1425 = io_lsu_busreq_r & _T_1424; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1426 = _T_1420 | _T_1425; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1427 = ~_T_1426; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1428 = _T_1418 & _T_1427; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1430 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1431 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1432 = ibuf_valid & _T_1431; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1433 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1434 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1435 = io_ldst_dual_r & _T_1434; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1436 = _T_1433 | _T_1435; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1437 = io_lsu_busreq_r & _T_1436; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1438 = _T_1432 | _T_1437; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1439 = ~_T_1438; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1440 = _T_1430 & _T_1439; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1442 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1443 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1444 = ibuf_valid & _T_1443; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1445 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1446 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1447 = io_ldst_dual_r & _T_1446; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1448 = _T_1445 | _T_1447; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1449 = io_lsu_busreq_r & _T_1448; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1450 = _T_1444 | _T_1449; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1451 = ~_T_1450; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1452 = _T_1442 & _T_1451; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1454 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1455 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1456 = ibuf_valid & _T_1455; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1457 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1458 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1459 = io_ldst_dual_r & _T_1458; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1460 = _T_1457 | _T_1459; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1461 = io_lsu_busreq_r & _T_1460; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1462 = _T_1456 | _T_1461; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1463 = ~_T_1462; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1464 = _T_1454 & _T_1463; // @[el2_lsu_bus_buffer.scala 546:67] - wire [1:0] _T_1466 = _T_1464 ? 2'h3 : 2'h0; // @[Mux.scala 98:16] - wire [1:0] _T_1467 = _T_1452 ? 2'h2 : _T_1466; // @[Mux.scala 98:16] - wire [1:0] _T_1468 = _T_1440 ? 2'h1 : _T_1467; // @[Mux.scala 98:16] - wire [1:0] WrPtr0_m = _T_1428 ? 2'h0 : _T_1468; // @[Mux.scala 98:16] - wire _T_1473 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1474 = io_lsu_busreq_m & _T_1473; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1475 = _T_1420 | _T_1474; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1477 = io_lsu_busreq_r & _T_1421; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1480 = _T_1477 | _T_1423; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1481 = _T_1475 | _T_1480; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1482 = ~_T_1481; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1483 = _T_1418 & _T_1482; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1488 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1489 = io_lsu_busreq_m & _T_1488; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1490 = _T_1432 | _T_1489; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1492 = io_lsu_busreq_r & _T_1433; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1495 = _T_1492 | _T_1435; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1496 = _T_1490 | _T_1495; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1497 = ~_T_1496; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1498 = _T_1430 & _T_1497; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1503 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1504 = io_lsu_busreq_m & _T_1503; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1505 = _T_1444 | _T_1504; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1507 = io_lsu_busreq_r & _T_1445; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1510 = _T_1507 | _T_1447; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1511 = _T_1505 | _T_1510; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1512 = ~_T_1511; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1513 = _T_1442 & _T_1512; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1518 = WrPtr0_m == 2'h3; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1519 = io_lsu_busreq_m & _T_1518; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1520 = _T_1456 | _T_1519; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1522 = io_lsu_busreq_r & _T_1457; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1525 = _T_1522 | _T_1459; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1526 = _T_1520 | _T_1525; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1527 = ~_T_1526; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1528 = _T_1454 & _T_1527; // @[el2_lsu_bus_buffer.scala 549:70] - reg buf_rspageQ_0_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1722 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_1 = buf_rspageQ_0_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1627 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_0 = buf_rspageQ_0_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1912 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_3 = buf_rspageQ_0_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1817 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_2 = buf_rspageQ_0_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_1561 = {buf_rsp_pickage_0_3,buf_rsp_pickage_0_2,buf_rsp_pickage_0_1,buf_rsp_pickage_0_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_1562 = |_T_1561; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_1563 = ~_T_1562; // @[el2_lsu_bus_buffer.scala 560:32] - wire _T_1565 = _T_1563 & _T_1627; // @[el2_lsu_bus_buffer.scala 560:67] - wire _T_3136 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 617:83] - wire _T_3137 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 617:103] - wire _T_3138 = _T_3136 & _T_3137; // @[el2_lsu_bus_buffer.scala 617:101] - wire _T_3139 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 617:123] - wire _T_3140 = _T_3138 & _T_3139; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3141 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 617:150] - wire _T_3142 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3143 = _T_3141 & _T_3142; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3144 = _T_3140 | _T_3143; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3145 = _T_906 & _T_3144; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3146 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 617:212] - wire _T_3147 = ibuf_drain_vld & _T_3146; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3148 = _T_3145 | _T_3147; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3158 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 624:52] - wire _T_3192 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] - wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 740:49] - wire _T_3217 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3218 = bus_rsp_write & _T_3217; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3219 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 643:78] - reg buf_ldfwd_0; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[el2_lib.scala 514:16] + wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:57] + wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] + wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 423:76] + reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] + wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] + wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] + wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] + wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 435:70] + wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:77] + wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 497:97] + wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 497:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:46] + wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 614:38] + wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:46] + reg _T_4307; // @[Reg.scala 27:20] + reg _T_4305; // @[Reg.scala 27:20] + reg _T_4303; // @[Reg.scala 27:20] + reg _T_4301; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_474 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3220 = io_lsu_axi_rid == _GEN_474; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3221 = buf_ldfwd_0 & _T_3220; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3222 = _T_3219 | _T_3221; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3223 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3224 = ~buf_write_0; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3225 = _T_3223 & _T_3224; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3226 = _T_3225 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_360 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3638 = io_lsu_axi_rid == _GEN_360; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_475 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3227 = io_lsu_axi_rid == _GEN_475; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3228 = _T_3226 & _T_3227; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3229 = _T_3222 | _T_3228; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3230 = bus_rsp_read & _T_3229; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3231 = _T_3218 | _T_3230; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_118 = _T_3192 & _T_3231; // @[Conditional.scala 39:67] - wire _GEN_137 = _T_3159 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] - wire _GEN_149 = _T_3155 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] - wire _T_3256 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] - reg buf_ldfwd_3; // @[Reg.scala 27:20] - reg buf_ldfwd_2; // @[Reg.scala 27:20] - reg buf_ldfwd_1; // @[Reg.scala 27:20] - wire _GEN_95 = 2'h1 == buf_dualtag_0 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_96 = 2'h2 == buf_dualtag_0 ? buf_ldfwd_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_97 = 2'h3 == buf_dualtag_0 ? buf_ldfwd_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 641:136] + wire [2:0] _GEN_361 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3646 = io_lsu_axi_rid == _GEN_361; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 537:21] reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] - wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_477 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3263 = io_lsu_axi_rid == _GEN_477; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3264 = _GEN_97 & _T_3263; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3265 = _T_3227 | _T_3264; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3266 = bus_rsp_read & _T_3265; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_112 = _T_3256 & _T_3266; // @[Conditional.scala 39:67] - wire _GEN_119 = _T_3192 ? buf_resp_state_bus_en_0 : _GEN_112; // @[Conditional.scala 39:67] - wire _GEN_129 = _T_3159 ? buf_cmd_state_bus_en_0 : _GEN_119; // @[Conditional.scala 39:67] - wire _GEN_142 = _T_3155 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] - wire buf_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] - wire _T_3172 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3173 = _T_3172 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3269 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] - reg buf_rspageQ_3_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_3 = buf_rspageQ_3_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_2 = buf_rspageQ_3_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_1 = buf_rspageQ_3_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_0 = buf_rspageQ_3_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2986 = {buf_rsp_pickage_3_3,buf_rsp_pickage_3_2,buf_rsp_pickage_3_1,buf_rsp_pickage_3_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2987 = |_T_2986; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2988 = ~_T_2987; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_3 = _T_2988 & _T_1912; // @[el2_lsu_bus_buffer.scala 560:67] - reg buf_rspageQ_2_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_3 = buf_rspageQ_2_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_2 = buf_rspageQ_2_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_1 = buf_rspageQ_2_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_0 = buf_rspageQ_2_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2606 = {buf_rsp_pickage_2_3,buf_rsp_pickage_2_2,buf_rsp_pickage_2_1,buf_rsp_pickage_2_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2607 = |_T_2606; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_2 = _T_2608 & _T_1817; // @[el2_lsu_bus_buffer.scala 560:67] - reg buf_rspageQ_1_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_3 = buf_rspageQ_1_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_2 = buf_rspageQ_1_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_1 = buf_rspageQ_1_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_0 = buf_rspageQ_1_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2226 = {buf_rsp_pickage_1_3,buf_rsp_pickage_1_2,buf_rsp_pickage_1_1,buf_rsp_pickage_1_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2227 = |_T_2226; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2228 = ~_T_2227; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_1 = _T_2228 & _T_1722; // @[el2_lsu_bus_buffer.scala 560:67] - wire [3:0] _T_3078 = {RspPtrDec_3,RspPtrDec_2,RspPtrDec_1,_T_1565}; // @[el2_lsu_bus_buffer.scala 580:58] - wire [3:0] _T_3083 = _T_3078[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3084 = _T_3078[2] ? 4'h4 : _T_3083; // @[Mux.scala 47:69] - wire [3:0] _T_3085 = _T_3078[1] ? 4'h2 : _T_3084; // @[Mux.scala 47:69] - wire [3:0] _T_3086 = _T_3078[0] ? 4'h1 : _T_3085; // @[Mux.scala 47:69] - wire [1:0] RspPtr = _T_3086[1:0]; // @[el2_lsu_bus_buffer.scala 580:27] - wire _T_3272 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3273 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3274 = buf_dual_0 & _T_3273; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3275 = _T_3272 | _T_3274; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3276 = _T_3275 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3277 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] - wire _GEN_107 = _T_3269 ? _T_3276 : _T_3277; // @[Conditional.scala 39:67] - wire _GEN_113 = _T_3256 ? _T_3173 : _GEN_107; // @[Conditional.scala 39:67] - wire _GEN_120 = _T_3192 ? _T_3173 : _GEN_113; // @[Conditional.scala 39:67] - wire _GEN_130 = _T_3159 ? _T_3173 : _GEN_120; // @[Conditional.scala 39:67] - wire _GEN_140 = _T_3155 ? _T_3158 : _GEN_130; // @[Conditional.scala 39:67] - wire buf_state_en_0 = _T_3132 ? _T_3148 : _GEN_140; // @[Conditional.scala 40:58] - wire _T_1567 = _T_1418 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_1572 = _T_3986 | _T_3985; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1573 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 564:25] - wire _T_1575 = _T_1573 & _T_3136; // @[el2_lsu_bus_buffer.scala 564:43] - wire _T_1577 = _T_1575 & _T_3139; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_1579 = _T_1577 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1580 = _T_1572 | _T_1579; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1581 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 565:19] - wire _T_1582 = _T_1581 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 565:37] - wire _T_1584 = _T_1582 & _T_3142; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_1586 = _T_1584 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1587 = _T_1580 | _T_1586; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1588 = _T_1567 & _T_1587; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1602 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1603 = _T_1418 | _T_1602; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1604 = ~_T_1603; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1612 = _T_1604 | _T_1579; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1619 = _T_1612 | _T_1586; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_0 = _T_1567 & _T_1619; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1624 = _T_1602 | _T_1418; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1625 = ~_T_1624; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_0 = buf_rspageQ_0_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1667 = _T_3991 | _T_3990; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1673 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1674 = _T_1577 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1675 = _T_1667 | _T_1674; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1680 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1681 = _T_1584 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1682 = _T_1675 | _T_1681; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1683 = _T_1567 & _T_1682; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1697 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1698 = _T_1430 | _T_1697; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1699 = ~_T_1698; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1707 = _T_1699 | _T_1674; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1714 = _T_1707 | _T_1681; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_1 = _T_1567 & _T_1714; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1719 = _T_1697 | _T_1430; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1720 = ~_T_1719; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_1 = buf_rspageQ_0_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1762 = _T_3996 | _T_3995; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1768 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1769 = _T_1577 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1770 = _T_1762 | _T_1769; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1775 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1776 = _T_1584 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1777 = _T_1770 | _T_1776; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1778 = _T_1567 & _T_1777; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1792 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1793 = _T_1442 | _T_1792; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1794 = ~_T_1793; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1802 = _T_1794 | _T_1769; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1809 = _T_1802 | _T_1776; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_2 = _T_1567 & _T_1809; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1814 = _T_1792 | _T_1442; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1815 = ~_T_1814; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_2 = buf_rspageQ_0_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1857 = _T_4001 | _T_4000; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1863 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1864 = _T_1577 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1865 = _T_1857 | _T_1864; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1870 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1871 = _T_1584 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1872 = _T_1865 | _T_1871; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1873 = _T_1567 & _T_1872; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1887 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1888 = _T_1454 | _T_1887; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1889 = ~_T_1888; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1897 = _T_1889 | _T_1864; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1904 = _T_1897 | _T_1871; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_3 = _T_1567 & _T_1904; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1909 = _T_1887 | _T_1454; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1910 = ~_T_1909; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_3 = buf_rspageQ_0_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3348 = _T_3138 & _T_1680; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3350 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3351 = _T_3141 & _T_3350; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3352 = _T_3348 | _T_3351; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3353 = _T_906 & _T_3352; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3355 = ibuf_drain_vld & _T_1673; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3356 = _T_3353 | _T_3355; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3400 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3425 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3426 = bus_rsp_write & _T_3425; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3427 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_478 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3428 = io_lsu_axi_rid == _GEN_478; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3429 = buf_ldfwd_1 & _T_3428; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3430 = _T_3427 | _T_3429; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3431 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3432 = ~buf_write_1; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3433 = _T_3431 & _T_3432; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3434 = _T_3433 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 645:94] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_363 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3688 = io_lsu_axi_rid == _GEN_363; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 447:10] + wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 461:23] + wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 461:41] + wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 462:35] + wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_364 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3831 = io_lsu_axi_rid == _GEN_364; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] - wire [2:0] _GEN_479 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3435 = io_lsu_axi_rid == _GEN_479; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3436 = _T_3434 & _T_3435; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3437 = _T_3430 | _T_3436; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3438 = bus_rsp_read & _T_3437; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3439 = _T_3426 | _T_3438; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_208 = _T_3400 & _T_3439; // @[Conditional.scala 39:67] - wire _GEN_227 = _T_3367 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] - wire _GEN_239 = _T_3363 ? 1'h0 : _GEN_227; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_239; // @[Conditional.scala 40:58] - wire _T_3464 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] - wire _GEN_185 = 2'h1 == buf_dualtag_1 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_186 = 2'h2 == buf_dualtag_1 ? buf_ldfwd_2 : _GEN_185; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_187 = 2'h3 == buf_dualtag_1 ? buf_ldfwd_3 : _GEN_186; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_189 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_190 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_189; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_191 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_190; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_481 = {{1'd0}, _GEN_191}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3471 = io_lsu_axi_rid == _GEN_481; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3472 = _GEN_187 & _T_3471; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3473 = _T_3435 | _T_3472; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3474 = bus_rsp_read & _T_3473; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_202 = _T_3464 & _T_3474; // @[Conditional.scala 39:67] - wire _GEN_209 = _T_3400 ? buf_resp_state_bus_en_1 : _GEN_202; // @[Conditional.scala 39:67] - wire _GEN_219 = _T_3367 ? buf_cmd_state_bus_en_1 : _GEN_209; // @[Conditional.scala 39:67] - wire _GEN_232 = _T_3363 ? 1'h0 : _GEN_219; // @[Conditional.scala 39:67] - wire buf_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_232; // @[Conditional.scala 40:58] - wire _T_3380 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3381 = _T_3380 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3477 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3480 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3481 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3482 = buf_dual_1 & _T_3481; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3483 = _T_3480 | _T_3482; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3484 = _T_3483 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3485 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] - wire _GEN_197 = _T_3477 ? _T_3484 : _T_3485; // @[Conditional.scala 39:67] - wire _GEN_203 = _T_3464 ? _T_3381 : _GEN_197; // @[Conditional.scala 39:67] - wire _GEN_210 = _T_3400 ? _T_3381 : _GEN_203; // @[Conditional.scala 39:67] - wire _GEN_220 = _T_3367 ? _T_3381 : _GEN_210; // @[Conditional.scala 39:67] - wire _GEN_230 = _T_3363 ? _T_3158 : _GEN_220; // @[Conditional.scala 39:67] - wire buf_state_en_1 = _T_3340 ? _T_3356 : _GEN_230; // @[Conditional.scala 40:58] - wire _T_1947 = _T_1430 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_1957 = _T_1575 & _T_1680; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_1959 = _T_1957 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1960 = _T_1572 | _T_1959; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1964 = _T_1582 & _T_3350; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_1966 = _T_1964 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1967 = _T_1960 | _T_1966; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1968 = _T_1947 & _T_1967; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1992 = _T_1604 | _T_1959; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1999 = _T_1992 | _T_1966; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_0 = _T_1947 & _T_1999; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_0 = buf_rspageQ_1_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2054 = _T_1957 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2055 = _T_1667 | _T_2054; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2061 = _T_1964 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2062 = _T_2055 | _T_2061; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2063 = _T_1947 & _T_2062; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2087 = _T_1699 | _T_2054; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2094 = _T_2087 | _T_2061; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_1 = _T_1947 & _T_2094; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_1 = buf_rspageQ_1_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2149 = _T_1957 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2150 = _T_1762 | _T_2149; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2156 = _T_1964 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2157 = _T_2150 | _T_2156; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2158 = _T_1947 & _T_2157; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2182 = _T_1794 | _T_2149; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2189 = _T_2182 | _T_2156; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_2 = _T_1947 & _T_2189; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_2 = buf_rspageQ_1_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2244 = _T_1957 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2245 = _T_1857 | _T_2244; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2251 = _T_1964 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2252 = _T_2245 | _T_2251; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2253 = _T_1947 & _T_2252; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2277 = _T_1889 | _T_2244; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2284 = _T_2277 | _T_2251; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_3 = _T_1947 & _T_2284; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_3 = buf_rspageQ_1_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3556 = _T_3138 & _T_1775; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3558 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3559 = _T_3141 & _T_3558; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3560 = _T_3556 | _T_3559; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3561 = _T_906 & _T_3560; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3563 = ibuf_drain_vld & _T_1768; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3564 = _T_3561 | _T_3563; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3608 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3633 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3634 = bus_rsp_write & _T_3633; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3635 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_482 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3636 = io_lsu_axi_rid == _GEN_482; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3637 = buf_ldfwd_2 & _T_3636; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3638 = _T_3635 | _T_3637; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3639 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3640 = ~buf_write_2; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3641 = _T_3639 & _T_3640; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3642 = _T_3641 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_365 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3839 = io_lsu_axi_rid == _GEN_365; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_367 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3881 = io_lsu_axi_rid == _GEN_367; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4024 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] - wire [2:0] _GEN_483 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3643 = io_lsu_axi_rid == _GEN_483; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3644 = _T_3642 & _T_3643; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3645 = _T_3638 | _T_3644; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3646 = bus_rsp_read & _T_3645; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3647 = _T_3634 | _T_3646; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_298 = _T_3608 & _T_3647; // @[Conditional.scala 39:67] - wire _GEN_317 = _T_3575 ? 1'h0 : _GEN_298; // @[Conditional.scala 39:67] - wire _GEN_329 = _T_3571 ? 1'h0 : _GEN_317; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_329; // @[Conditional.scala 40:58] - wire _T_3672 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] - wire _GEN_275 = 2'h1 == buf_dualtag_2 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_276 = 2'h2 == buf_dualtag_2 ? buf_ldfwd_2 : _GEN_275; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_277 = 2'h3 == buf_dualtag_2 ? buf_ldfwd_3 : _GEN_276; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_279 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_280 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_279; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_281 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_280; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_485 = {{1'd0}, _GEN_281}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3679 = io_lsu_axi_rid == _GEN_485; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3680 = _GEN_277 & _T_3679; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3681 = _T_3643 | _T_3680; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3682 = bus_rsp_read & _T_3681; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_292 = _T_3672 & _T_3682; // @[Conditional.scala 39:67] - wire _GEN_299 = _T_3608 ? buf_resp_state_bus_en_2 : _GEN_292; // @[Conditional.scala 39:67] - wire _GEN_309 = _T_3575 ? buf_cmd_state_bus_en_2 : _GEN_299; // @[Conditional.scala 39:67] - wire _GEN_322 = _T_3571 ? 1'h0 : _GEN_309; // @[Conditional.scala 39:67] - wire buf_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_322; // @[Conditional.scala 40:58] - wire _T_3588 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3589 = _T_3588 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3685 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3688 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3689 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3690 = buf_dual_2 & _T_3689; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3691 = _T_3688 | _T_3690; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3692 = _T_3691 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3693 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] - wire _GEN_287 = _T_3685 ? _T_3692 : _T_3693; // @[Conditional.scala 39:67] - wire _GEN_293 = _T_3672 ? _T_3589 : _GEN_287; // @[Conditional.scala 39:67] - wire _GEN_300 = _T_3608 ? _T_3589 : _GEN_293; // @[Conditional.scala 39:67] - wire _GEN_310 = _T_3575 ? _T_3589 : _GEN_300; // @[Conditional.scala 39:67] - wire _GEN_320 = _T_3571 ? _T_3158 : _GEN_310; // @[Conditional.scala 39:67] - wire buf_state_en_2 = _T_3548 ? _T_3564 : _GEN_320; // @[Conditional.scala 40:58] - wire _T_2327 = _T_1442 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_2337 = _T_1575 & _T_1775; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_2339 = _T_2337 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2340 = _T_1572 | _T_2339; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2344 = _T_1582 & _T_3558; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_2346 = _T_2344 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2347 = _T_2340 | _T_2346; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2348 = _T_2327 & _T_2347; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2372 = _T_1604 | _T_2339; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2379 = _T_2372 | _T_2346; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_0 = _T_2327 & _T_2379; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_0 = buf_rspageQ_2_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2434 = _T_2337 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2435 = _T_1667 | _T_2434; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2441 = _T_2344 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2442 = _T_2435 | _T_2441; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2443 = _T_2327 & _T_2442; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2467 = _T_1699 | _T_2434; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2474 = _T_2467 | _T_2441; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_1 = _T_2327 & _T_2474; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_1 = buf_rspageQ_2_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2529 = _T_2337 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2530 = _T_1762 | _T_2529; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2536 = _T_2344 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2537 = _T_2530 | _T_2536; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2538 = _T_2327 & _T_2537; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2562 = _T_1794 | _T_2529; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2569 = _T_2562 | _T_2536; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_2 = _T_2327 & _T_2569; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_2 = buf_rspageQ_2_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2624 = _T_2337 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2625 = _T_1857 | _T_2624; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2631 = _T_2344 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2632 = _T_2625 | _T_2631; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2633 = _T_2327 & _T_2632; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2657 = _T_1889 | _T_2624; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2664 = _T_2657 | _T_2631; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_3 = _T_2327 & _T_2664; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_3 = buf_rspageQ_2_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3764 = _T_3138 & _T_1870; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3766 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3767 = _T_3141 & _T_3766; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3768 = _T_3764 | _T_3767; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3769 = _T_906 & _T_3768; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3771 = ibuf_drain_vld & _T_1863; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3772 = _T_3769 | _T_3771; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3816 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3841 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3842 = bus_rsp_write & _T_3841; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3843 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_486 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3844 = io_lsu_axi_rid == _GEN_486; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3845 = buf_ldfwd_3 & _T_3844; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3846 = _T_3843 | _T_3845; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3847 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3848 = ~buf_write_3; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3849 = _T_3847 & _T_3848; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3850 = _T_3849 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4032 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4074 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4217 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] - wire [2:0] _GEN_487 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3851 = io_lsu_axi_rid == _GEN_487; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3852 = _T_3850 & _T_3851; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3853 = _T_3846 | _T_3852; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3854 = bus_rsp_read & _T_3853; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3855 = _T_3842 | _T_3854; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_388 = _T_3816 & _T_3855; // @[Conditional.scala 39:67] - wire _GEN_407 = _T_3783 ? 1'h0 : _GEN_388; // @[Conditional.scala 39:67] - wire _GEN_419 = _T_3779 ? 1'h0 : _GEN_407; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_419; // @[Conditional.scala 40:58] - wire _T_3880 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] - wire _GEN_365 = 2'h1 == buf_dualtag_3 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_366 = 2'h2 == buf_dualtag_3 ? buf_ldfwd_2 : _GEN_365; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_367 = 2'h3 == buf_dualtag_3 ? buf_ldfwd_3 : _GEN_366; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_369 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_370 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_369; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_371 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_370; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_489 = {{1'd0}, _GEN_371}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3887 = io_lsu_axi_rid == _GEN_489; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3888 = _GEN_367 & _T_3887; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3889 = _T_3851 | _T_3888; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3890 = bus_rsp_read & _T_3889; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_382 = _T_3880 & _T_3890; // @[Conditional.scala 39:67] - wire _GEN_389 = _T_3816 ? buf_resp_state_bus_en_3 : _GEN_382; // @[Conditional.scala 39:67] - wire _GEN_399 = _T_3783 ? buf_cmd_state_bus_en_3 : _GEN_389; // @[Conditional.scala 39:67] - wire _GEN_412 = _T_3779 ? 1'h0 : _GEN_399; // @[Conditional.scala 39:67] - wire buf_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_412; // @[Conditional.scala 40:58] - wire _T_3796 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3797 = _T_3796 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3893 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3896 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3897 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3898 = buf_dual_3 & _T_3897; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3899 = _T_3896 | _T_3898; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3900 = _T_3899 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3901 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] - wire _GEN_377 = _T_3893 ? _T_3900 : _T_3901; // @[Conditional.scala 39:67] - wire _GEN_383 = _T_3880 ? _T_3797 : _GEN_377; // @[Conditional.scala 39:67] - wire _GEN_390 = _T_3816 ? _T_3797 : _GEN_383; // @[Conditional.scala 39:67] - wire _GEN_400 = _T_3783 ? _T_3797 : _GEN_390; // @[Conditional.scala 39:67] - wire _GEN_410 = _T_3779 ? _T_3158 : _GEN_400; // @[Conditional.scala 39:67] - wire buf_state_en_3 = _T_3756 ? _T_3772 : _GEN_410; // @[Conditional.scala 40:58] - wire _T_2707 = _T_1454 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_2717 = _T_1575 & _T_1870; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_2719 = _T_2717 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2720 = _T_1572 | _T_2719; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2724 = _T_1582 & _T_3766; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_2726 = _T_2724 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2727 = _T_2720 | _T_2726; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2728 = _T_2707 & _T_2727; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2752 = _T_1604 | _T_2719; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2759 = _T_2752 | _T_2726; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_0 = _T_2707 & _T_2759; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_0 = buf_rspageQ_3_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2814 = _T_2717 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2815 = _T_1667 | _T_2814; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2821 = _T_2724 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2822 = _T_2815 | _T_2821; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2823 = _T_2707 & _T_2822; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2847 = _T_1699 | _T_2814; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2854 = _T_2847 | _T_2821; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_1 = _T_2707 & _T_2854; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_1 = buf_rspageQ_3_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2909 = _T_2717 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2910 = _T_1762 | _T_2909; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2916 = _T_2724 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2917 = _T_2910 | _T_2916; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2918 = _T_2707 & _T_2917; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2942 = _T_1794 | _T_2909; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2949 = _T_2942 | _T_2916; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_2 = _T_2707 & _T_2949; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_2 = buf_rspageQ_3_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3004 = _T_2717 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_3005 = _T_1857 | _T_3004; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_3011 = _T_2724 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_3012 = _T_3005 | _T_3011; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_3013 = _T_2707 & _T_3012; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_3037 = _T_1889 | _T_3004; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_3044 = _T_3037 | _T_3011; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_3 = _T_2707 & _T_3044; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_3 = buf_rspageQ_3_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3115 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 605:77] - wire _T_3161 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 627:101] - wire _T_3163 = _T_3161 & _T_1178; // @[el2_lsu_bus_buffer.scala 627:116] - wire _T_3175 = buf_state_en_0 & _T_3224; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3176 = _T_3175 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3178 = _T_3176 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3181 = _T_3172 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3182 = _T_3181 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_4329 = io_lsu_axi_rresp != 2'h0; // @[el2_lsu_bus_buffer.scala 744:70] - wire bus_rsp_read_error = bus_rsp_read & _T_4329; // @[el2_lsu_bus_buffer.scala 744:45] - wire _T_3185 = _T_3181 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3238 = bus_rsp_read_error & _T_3219; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3239 = bus_rsp_read_error & buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3241 = _T_3239 & _T_3220; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3242 = _T_3238 | _T_3241; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_4326 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 743:70] - wire bus_rsp_write_error = bus_rsp_write & _T_4326; // @[el2_lsu_bus_buffer.scala 743:45] - wire _T_3245 = bus_rsp_write_error & _T_3217; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3246 = _T_3242 | _T_3245; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3247 = _T_3172 & _T_3246; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_122 = _T_3192 & _T_3247; // @[Conditional.scala 39:67] - wire _GEN_135 = _T_3159 ? _T_3185 : _GEN_122; // @[Conditional.scala 39:67] - wire _GEN_147 = _T_3155 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] - wire buf_error_en_0 = _T_3132 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] - wire _T_3194 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 639:85] - wire _T_3195 = buf_write_0 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3196 = io_dec_tlu_force_halt | _T_3195; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3198 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3199 = buf_dual_0 & _T_3198; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3201 = _T_3199 & _T_3224; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_91 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_92 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_91; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_93 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_92; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3202 = _GEN_93 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3203 = _T_3201 & _T_3202; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_4013 = _T_1627 | _T_1722; // @[el2_lsu_bus_buffer.scala 701:158] - wire _T_4014 = _T_4013 | _T_1817; // @[el2_lsu_bus_buffer.scala 701:158] - wire any_done_wait_state = _T_4014 | _T_1912; // @[el2_lsu_bus_buffer.scala 701:158] - wire _T_3204 = buf_ldfwd_0 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3209 = _T_3201 & _GEN_97; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3210 = _GEN_93 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3211 = _T_3209 & _T_3210; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3212 = _T_3211 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3213 = _T_3204 | _T_3212; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3234 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3235 = _T_3234 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3248 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3249 = buf_state_en_0 & _T_3248; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3258 = buf_ldfwd_0 | _GEN_97; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3259 = _T_3258 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_105 = _T_3277 & buf_state_en_0; // @[Conditional.scala 39:67] - wire _GEN_108 = _T_3269 ? 1'h0 : _T_3277; // @[Conditional.scala 39:67] - wire _GEN_110 = _T_3269 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] - wire _GEN_114 = _T_3256 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] - wire _GEN_116 = _T_3256 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] - wire _GEN_121 = _T_3192 & _T_3235; // @[Conditional.scala 39:67] - wire _GEN_124 = _T_3192 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] - wire _GEN_126 = _T_3192 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] - wire _GEN_132 = _T_3159 ? _T_3178 : _GEN_126; // @[Conditional.scala 39:67] - wire _GEN_134 = _T_3159 ? _T_3182 : _GEN_121; // @[Conditional.scala 39:67] - wire _GEN_138 = _T_3159 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] - wire _GEN_144 = _T_3155 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] - wire _GEN_146 = _T_3155 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] - wire _GEN_150 = _T_3155 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] - wire buf_wr_en_0 = _T_3132 & buf_state_en_0; // @[Conditional.scala 40:58] - wire buf_data_en_0 = _T_3132 ? buf_state_en_0 : _GEN_146; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_0 = _T_3132 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] - wire buf_rst_0 = _T_3132 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] - reg buf_unsign_0; // @[Reg.scala 27:20] - wire _T_3293 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3294 = buf_error_en_0 | buf_rst_0; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_0; // @[Reg.scala 27:20] - wire _T_3383 = buf_state_en_1 & _T_3432; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3384 = _T_3383 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3386 = _T_3384 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3389 = _T_3380 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3390 = _T_3389 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3393 = _T_3389 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3446 = bus_rsp_read_error & _T_3427; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3447 = bus_rsp_read_error & buf_ldfwd_1; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3449 = _T_3447 & _T_3428; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3450 = _T_3446 | _T_3449; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3453 = bus_rsp_write_error & _T_3425; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3454 = _T_3450 | _T_3453; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3455 = _T_3380 & _T_3454; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_212 = _T_3400 & _T_3455; // @[Conditional.scala 39:67] - wire _GEN_225 = _T_3367 ? _T_3393 : _GEN_212; // @[Conditional.scala 39:67] - wire _GEN_237 = _T_3363 ? 1'h0 : _GEN_225; // @[Conditional.scala 39:67] - wire buf_error_en_1 = _T_3340 ? 1'h0 : _GEN_237; // @[Conditional.scala 40:58] - wire _T_3403 = buf_write_1 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3404 = io_dec_tlu_force_halt | _T_3403; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3406 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3407 = buf_dual_1 & _T_3406; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3409 = _T_3407 & _T_3432; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_181; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_182; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3410 = _GEN_183 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3411 = _T_3409 & _T_3410; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3412 = buf_ldfwd_1 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3417 = _T_3409 & _GEN_187; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3418 = _GEN_183 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3419 = _T_3417 & _T_3418; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3420 = _T_3419 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3421 = _T_3412 | _T_3420; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3442 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3443 = _T_3442 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3456 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3457 = buf_state_en_1 & _T_3456; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3466 = buf_ldfwd_1 | _GEN_187; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3467 = _T_3466 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_195 = _T_3485 & buf_state_en_1; // @[Conditional.scala 39:67] - wire _GEN_198 = _T_3477 ? 1'h0 : _T_3485; // @[Conditional.scala 39:67] - wire _GEN_200 = _T_3477 ? 1'h0 : _GEN_195; // @[Conditional.scala 39:67] - wire _GEN_204 = _T_3464 ? 1'h0 : _GEN_198; // @[Conditional.scala 39:67] - wire _GEN_206 = _T_3464 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] - wire _GEN_211 = _T_3400 & _T_3443; // @[Conditional.scala 39:67] - wire _GEN_214 = _T_3400 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] - wire _GEN_216 = _T_3400 ? 1'h0 : _GEN_206; // @[Conditional.scala 39:67] - wire _GEN_222 = _T_3367 ? _T_3386 : _GEN_216; // @[Conditional.scala 39:67] - wire _GEN_224 = _T_3367 ? _T_3390 : _GEN_211; // @[Conditional.scala 39:67] - wire _GEN_228 = _T_3367 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] - wire _GEN_234 = _T_3363 ? 1'h0 : _GEN_222; // @[Conditional.scala 39:67] - wire _GEN_236 = _T_3363 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] - wire _GEN_240 = _T_3363 ? 1'h0 : _GEN_228; // @[Conditional.scala 39:67] - wire buf_wr_en_1 = _T_3340 & buf_state_en_1; // @[Conditional.scala 40:58] - wire buf_data_en_1 = _T_3340 ? buf_state_en_1 : _GEN_236; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_1 = _T_3340 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] - wire buf_rst_1 = _T_3340 ? 1'h0 : _GEN_240; // @[Conditional.scala 40:58] - reg buf_unsign_1; // @[Reg.scala 27:20] - wire _T_3501 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3502 = buf_error_en_1 | buf_rst_1; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_1; // @[Reg.scala 27:20] - wire _T_3591 = buf_state_en_2 & _T_3640; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3592 = _T_3591 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3594 = _T_3592 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3597 = _T_3588 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3598 = _T_3597 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3601 = _T_3597 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3654 = bus_rsp_read_error & _T_3635; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3655 = bus_rsp_read_error & buf_ldfwd_2; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3657 = _T_3655 & _T_3636; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3658 = _T_3654 | _T_3657; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3661 = bus_rsp_write_error & _T_3633; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3662 = _T_3658 | _T_3661; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3663 = _T_3588 & _T_3662; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_302 = _T_3608 & _T_3663; // @[Conditional.scala 39:67] - wire _GEN_315 = _T_3575 ? _T_3601 : _GEN_302; // @[Conditional.scala 39:67] - wire _GEN_327 = _T_3571 ? 1'h0 : _GEN_315; // @[Conditional.scala 39:67] - wire buf_error_en_2 = _T_3548 ? 1'h0 : _GEN_327; // @[Conditional.scala 40:58] - wire _T_3611 = buf_write_2 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3612 = io_dec_tlu_force_halt | _T_3611; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3614 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3615 = buf_dual_2 & _T_3614; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3617 = _T_3615 & _T_3640; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_271 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_272 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_271; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_273 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_272; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3618 = _GEN_273 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3619 = _T_3617 & _T_3618; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3620 = buf_ldfwd_2 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3625 = _T_3617 & _GEN_277; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3626 = _GEN_273 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3627 = _T_3625 & _T_3626; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3628 = _T_3627 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3629 = _T_3620 | _T_3628; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3650 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3651 = _T_3650 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3664 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3665 = buf_state_en_2 & _T_3664; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3674 = buf_ldfwd_2 | _GEN_277; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3675 = _T_3674 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_285 = _T_3693 & buf_state_en_2; // @[Conditional.scala 39:67] - wire _GEN_288 = _T_3685 ? 1'h0 : _T_3693; // @[Conditional.scala 39:67] - wire _GEN_290 = _T_3685 ? 1'h0 : _GEN_285; // @[Conditional.scala 39:67] - wire _GEN_294 = _T_3672 ? 1'h0 : _GEN_288; // @[Conditional.scala 39:67] - wire _GEN_296 = _T_3672 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] - wire _GEN_301 = _T_3608 & _T_3651; // @[Conditional.scala 39:67] - wire _GEN_304 = _T_3608 ? 1'h0 : _GEN_294; // @[Conditional.scala 39:67] - wire _GEN_306 = _T_3608 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] - wire _GEN_312 = _T_3575 ? _T_3594 : _GEN_306; // @[Conditional.scala 39:67] - wire _GEN_314 = _T_3575 ? _T_3598 : _GEN_301; // @[Conditional.scala 39:67] - wire _GEN_318 = _T_3575 ? 1'h0 : _GEN_304; // @[Conditional.scala 39:67] - wire _GEN_324 = _T_3571 ? 1'h0 : _GEN_312; // @[Conditional.scala 39:67] - wire _GEN_326 = _T_3571 ? 1'h0 : _GEN_314; // @[Conditional.scala 39:67] - wire _GEN_330 = _T_3571 ? 1'h0 : _GEN_318; // @[Conditional.scala 39:67] - wire buf_wr_en_2 = _T_3548 & buf_state_en_2; // @[Conditional.scala 40:58] - wire buf_data_en_2 = _T_3548 ? buf_state_en_2 : _GEN_326; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_2 = _T_3548 ? 1'h0 : _GEN_324; // @[Conditional.scala 40:58] - wire buf_rst_2 = _T_3548 ? 1'h0 : _GEN_330; // @[Conditional.scala 40:58] - reg buf_unsign_2; // @[Reg.scala 27:20] - wire _T_3709 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3710 = buf_error_en_2 | buf_rst_2; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_2; // @[Reg.scala 27:20] - wire _T_3799 = buf_state_en_3 & _T_3848; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3800 = _T_3799 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3802 = _T_3800 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3805 = _T_3796 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3806 = _T_3805 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3809 = _T_3805 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3862 = bus_rsp_read_error & _T_3843; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3863 = bus_rsp_read_error & buf_ldfwd_3; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3865 = _T_3863 & _T_3844; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3866 = _T_3862 | _T_3865; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3869 = bus_rsp_write_error & _T_3841; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3870 = _T_3866 | _T_3869; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3871 = _T_3796 & _T_3870; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_392 = _T_3816 & _T_3871; // @[Conditional.scala 39:67] - wire _GEN_405 = _T_3783 ? _T_3809 : _GEN_392; // @[Conditional.scala 39:67] - wire _GEN_417 = _T_3779 ? 1'h0 : _GEN_405; // @[Conditional.scala 39:67] - wire buf_error_en_3 = _T_3756 ? 1'h0 : _GEN_417; // @[Conditional.scala 40:58] - wire _T_3819 = buf_write_3 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3820 = io_dec_tlu_force_halt | _T_3819; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3822 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3823 = buf_dual_3 & _T_3822; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3825 = _T_3823 & _T_3848; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_361 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_362 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_361; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_363 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_362; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3826 = _GEN_363 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3827 = _T_3825 & _T_3826; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3828 = buf_ldfwd_3 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3833 = _T_3825 & _GEN_367; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3834 = _GEN_363 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3835 = _T_3833 & _T_3834; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3836 = _T_3835 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3837 = _T_3828 | _T_3836; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3858 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3859 = _T_3858 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3872 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3873 = buf_state_en_3 & _T_3872; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3882 = buf_ldfwd_3 | _GEN_367; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3883 = _T_3882 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_375 = _T_3901 & buf_state_en_3; // @[Conditional.scala 39:67] - wire _GEN_378 = _T_3893 ? 1'h0 : _T_3901; // @[Conditional.scala 39:67] - wire _GEN_380 = _T_3893 ? 1'h0 : _GEN_375; // @[Conditional.scala 39:67] - wire _GEN_384 = _T_3880 ? 1'h0 : _GEN_378; // @[Conditional.scala 39:67] - wire _GEN_386 = _T_3880 ? 1'h0 : _GEN_380; // @[Conditional.scala 39:67] - wire _GEN_391 = _T_3816 & _T_3859; // @[Conditional.scala 39:67] - wire _GEN_394 = _T_3816 ? 1'h0 : _GEN_384; // @[Conditional.scala 39:67] - wire _GEN_396 = _T_3816 ? 1'h0 : _GEN_386; // @[Conditional.scala 39:67] - wire _GEN_402 = _T_3783 ? _T_3802 : _GEN_396; // @[Conditional.scala 39:67] - wire _GEN_404 = _T_3783 ? _T_3806 : _GEN_391; // @[Conditional.scala 39:67] - wire _GEN_408 = _T_3783 ? 1'h0 : _GEN_394; // @[Conditional.scala 39:67] - wire _GEN_414 = _T_3779 ? 1'h0 : _GEN_402; // @[Conditional.scala 39:67] - wire _GEN_416 = _T_3779 ? 1'h0 : _GEN_404; // @[Conditional.scala 39:67] - wire _GEN_420 = _T_3779 ? 1'h0 : _GEN_408; // @[Conditional.scala 39:67] - wire buf_wr_en_3 = _T_3756 & buf_state_en_3; // @[Conditional.scala 40:58] - wire buf_data_en_3 = _T_3756 ? buf_state_en_3 : _GEN_416; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_3 = _T_3756 ? 1'h0 : _GEN_414; // @[Conditional.scala 40:58] - wire buf_rst_3 = _T_3756 ? 1'h0 : _GEN_420; // @[Conditional.scala 40:58] - reg buf_unsign_3; // @[Reg.scala 27:20] - wire _T_3917 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3918 = buf_error_en_3 | buf_rst_3; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_3; // @[Reg.scala 27:20] - wire [1:0] _GEN_494 = {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 696:45] - wire [1:0] _T_3925 = _GEN_494 << io_ldst_dual_m; // @[el2_lsu_bus_buffer.scala 696:45] - wire [1:0] _GEN_495 = {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 696:83] - wire [1:0] _T_3926 = _GEN_495 << io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 696:83] - wire [1:0] _T_3928 = _T_3925 + _T_3926; // @[el2_lsu_bus_buffer.scala 696:64] - wire [1:0] _GEN_496 = {{1'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 696:102] - wire [1:0] _T_3930 = _T_3928 + _GEN_496; // @[el2_lsu_bus_buffer.scala 696:102] - wire _T_3936 = _T_56 + _T_63; // @[el2_lsu_bus_buffer.scala 697:158] - wire _T_3938 = _T_3936 + _T_70; // @[el2_lsu_bus_buffer.scala 697:158] - wire _T_3940 = _T_3938 + _T_77; // @[el2_lsu_bus_buffer.scala 697:158] - wire [1:0] _GEN_497 = {{1'd0}, _T_3940}; // @[el2_lsu_bus_buffer.scala 696:115] - wire [1:0] _T_3942 = _T_3930 + _GEN_497; // @[el2_lsu_bus_buffer.scala 696:115] - wire _T_4017 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 704:60] - wire [3:0] buf_numvld_any = {{2'd0}, _T_3942}; // @[el2_lsu_bus_buffer.scala 696:25] - wire _T_4019 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 704:106] - wire _T_4021 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 704:152] - wire [2:0] _T_4023 = buf_state_0 | buf_state_1; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4024 = _T_4023 | buf_state_2; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4025 = _T_4024 | buf_state_3; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4026 = ~_T_4025; // @[el2_lsu_bus_buffer.scala 705:40] - wire [2:0] _GEN_498 = {{2'd0}, _T_903}; // @[el2_lsu_bus_buffer.scala 705:102] - wire [2:0] _T_4028 = _T_4026 & _GEN_498; // @[el2_lsu_bus_buffer.scala 705:102] - wire [2:0] _GEN_499 = {{2'd0}, _T_1146}; // @[el2_lsu_bus_buffer.scala 705:116] - wire [2:0] _T_4030 = _T_4028 & _GEN_499; // @[el2_lsu_bus_buffer.scala 705:116] - wire _T_4031 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 707:56] - wire _T_4032 = _T_4031 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 707:77] - wire _T_4033 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 707:99] - wire _T_4034 = _T_4032 & _T_4033; // @[el2_lsu_bus_buffer.scala 707:97] - wire _T_4035 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 707:116] - wire _T_4038 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 709:68] - reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 752:44] - wire _T_4053 = _T_1602 & _T_3224; // @[Mux.scala 27:72] - wire _T_4054 = _T_1697 & _T_3432; // @[Mux.scala 27:72] - wire _T_4055 = _T_1792 & _T_3640; // @[Mux.scala 27:72] - wire _T_4056 = _T_1887 & _T_3848; // @[Mux.scala 27:72] - wire _T_4057 = _T_4053 | _T_4054; // @[Mux.scala 27:72] - wire _T_4058 = _T_4057 | _T_4055; // @[Mux.scala 27:72] - wire lsu_nonblock_load_data_ready = _T_4058 | _T_4056; // @[Mux.scala 27:72] - wire _T_4073 = _T_4053 & buf_error_0; // @[Mux.scala 27:72] - wire _T_4074 = _T_4054 & buf_error_1; // @[Mux.scala 27:72] - wire _T_4075 = _T_4055 & buf_error_2; // @[Mux.scala 27:72] - wire _T_4076 = _T_4056 & buf_error_3; // @[Mux.scala 27:72] - wire _T_4077 = _T_4073 | _T_4074; // @[Mux.scala 27:72] - wire _T_4078 = _T_4077 | _T_4075; // @[Mux.scala 27:72] - wire _T_4082 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4083 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4084 = _T_4082 | _T_4083; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4089 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4090 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4091 = _T_4089 | _T_4090; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4092 = _T_1697 & _T_4091; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4094 = _T_4092 & _T_3432; // @[el2_lsu_bus_buffer.scala 714:129] - wire _T_4096 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4097 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4098 = _T_4096 | _T_4097; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4099 = _T_1792 & _T_4098; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4101 = _T_4099 & _T_3640; // @[el2_lsu_bus_buffer.scala 714:129] - wire _T_4103 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4104 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4105 = _T_4103 | _T_4104; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4106 = _T_1887 & _T_4105; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4108 = _T_4106 & _T_3848; // @[el2_lsu_bus_buffer.scala 714:129] - wire [1:0] _T_4111 = _T_4101 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_4112 = _T_4108 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_500 = {{1'd0}, _T_4094}; // @[Mux.scala 27:72] - wire [1:0] _T_4114 = _GEN_500 | _T_4111; // @[Mux.scala 27:72] - wire _T_4123 = _T_4053 & _T_4084; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4130 = _T_4054 & _T_4091; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4137 = _T_4055 & _T_4098; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4144 = _T_4056 & _T_4105; // @[el2_lsu_bus_buffer.scala 715:111] - wire [31:0] _T_4145 = _T_4123 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4146 = _T_4130 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4147 = _T_4137 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4148 = _T_4144 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4149 = _T_4145 | _T_4146; // @[Mux.scala 27:72] - wire [31:0] _T_4150 = _T_4149 | _T_4147; // @[Mux.scala 27:72] - wire [31:0] lsu_nonblock_load_data_lo = _T_4150 | _T_4148; // @[Mux.scala 27:72] - wire _T_4157 = _T_4053 & _T_3223; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4162 = _T_4054 & _T_3431; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4167 = _T_4055 & _T_3639; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4172 = _T_4056 & _T_3847; // @[el2_lsu_bus_buffer.scala 716:111] - wire [31:0] _T_4173 = _T_4157 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4174 = _T_4162 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4175 = _T_4167 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4176 = _T_4172 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4177 = _T_4173 | _T_4174; // @[Mux.scala 27:72] - wire [31:0] _T_4178 = _T_4177 | _T_4175; // @[Mux.scala 27:72] - wire [31:0] lsu_nonblock_load_data_hi = _T_4178 | _T_4176; // @[Mux.scala 27:72] - wire [31:0] _GEN_451 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 718:79] - wire [31:0] _GEN_452 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_451; // @[el2_lsu_bus_buffer.scala 718:79] - wire [31:0] _GEN_453 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_452; // @[el2_lsu_bus_buffer.scala 718:79] - wire [1:0] lsu_nonblock_addr_offset = _GEN_453[1:0]; // @[el2_lsu_bus_buffer.scala 718:79] - wire [1:0] _GEN_455 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_sz_1 : buf_sz_0; // @[el2_lsu_bus_buffer.scala 719:77] - wire [1:0] _GEN_456 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_sz_2 : _GEN_455; // @[el2_lsu_bus_buffer.scala 719:77] - wire [1:0] lsu_nonblock_sz = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_sz_3 : _GEN_456; // @[el2_lsu_bus_buffer.scala 719:77] - wire _GEN_459 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_unsign_1 : buf_unsign_0; // @[el2_lsu_bus_buffer.scala 720:37] - wire _GEN_460 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_unsign_2 : _GEN_459; // @[el2_lsu_bus_buffer.scala 720:37] - wire lsu_nonblock_unsign = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_unsign_3 : _GEN_460; // @[el2_lsu_bus_buffer.scala 720:37] - wire [63:0] _T_4185 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] - wire [3:0] _GEN_501 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 722:115] - wire [5:0] _T_4187 = 4'h8 * _GEN_501; // @[el2_lsu_bus_buffer.scala 722:115] - wire [63:0] _T_4188 = _T_4185 >> _T_4187; // @[el2_lsu_bus_buffer.scala 722:111] - wire [31:0] lsu_nonblock_data_unalgn = _T_4188[31:0]; // @[el2_lsu_bus_buffer.scala 722:146] - wire _T_4190 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 723:71] - wire _T_4192 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 725:83] - wire _T_4193 = lsu_nonblock_unsign & _T_4192; // @[el2_lsu_bus_buffer.scala 725:65] - wire [31:0] _T_4196 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4197 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 726:83] - wire _T_4198 = lsu_nonblock_unsign & _T_4197; // @[el2_lsu_bus_buffer.scala 726:65] - wire [31:0] _T_4201 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4202 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 727:44] - wire _T_4204 = _T_4202 & _T_4192; // @[el2_lsu_bus_buffer.scala 727:65] - wire [23:0] _T_4207 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_4209 = {_T_4207,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4212 = _T_4202 & _T_4197; // @[el2_lsu_bus_buffer.scala 728:65] - wire [15:0] _T_4215 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_4217 = {_T_4215,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4218 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 729:83] - wire _T_4219 = lsu_nonblock_unsign & _T_4218; // @[el2_lsu_bus_buffer.scala 729:65] - wire [31:0] _T_4221 = _T_4193 ? _T_4196 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4222 = _T_4198 ? _T_4201 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4223 = _T_4204 ? _T_4209 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4224 = _T_4212 ? _T_4217 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4225 = _T_4219 ? lsu_nonblock_data_unalgn : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4226 = _T_4221 | _T_4222; // @[Mux.scala 27:72] - wire [31:0] _T_4227 = _T_4226 | _T_4223; // @[Mux.scala 27:72] - wire [31:0] _T_4228 = _T_4227 | _T_4224; // @[Mux.scala 27:72] - wire _T_4334 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 749:64] - wire _T_4335 = io_lsu_busreq_m & _T_4334; // @[el2_lsu_bus_buffer.scala 749:62] - reg _T_4338; // @[el2_lsu_bus_buffer.scala 749:44] - wire _T_4360 = _T_1697 & buf_error_1; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4361 = _T_4360 & buf_write_1; // @[el2_lsu_bus_buffer.scala 775:114] - wire _T_4363 = _T_1792 & buf_error_2; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4364 = _T_4363 & buf_write_2; // @[el2_lsu_bus_buffer.scala 775:114] - wire _T_4366 = _T_1887 & buf_error_3; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4367 = _T_4366 & buf_write_3; // @[el2_lsu_bus_buffer.scala 775:114] - wire [1:0] _T_4370 = _T_4364 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_4371 = _T_4367 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_502 = {{1'd0}, _T_4361}; // @[Mux.scala 27:72] - wire [1:0] _T_4373 = _GEN_502 | _T_4370; // @[Mux.scala 27:72] - wire [1:0] lsu_imprecise_error_store_tag = _T_4373 | _T_4371; // @[Mux.scala 27:72] - wire _T_4376 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 776:74] - wire _T_4379 = io_lsu_bus_clk_en_q & _T_1602; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4380 = _T_4379 & buf_error_0; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4381 = _T_4380 & buf_write_0; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4383 = io_lsu_bus_clk_en_q & _T_1697; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4384 = _T_4383 & buf_error_1; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4385 = _T_4384 & buf_write_1; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4387 = io_lsu_bus_clk_en_q & _T_1792; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4388 = _T_4387 & buf_error_2; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4389 = _T_4388 & buf_write_2; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4391 = io_lsu_bus_clk_en_q & _T_1887; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4392 = _T_4391 & buf_error_3; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4393 = _T_4392 & buf_write_3; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4394 = _T_4381 | _T_4385; // @[el2_lsu_bus_buffer.scala 777:158] - wire _T_4395 = _T_4394 | _T_4389; // @[el2_lsu_bus_buffer.scala 777:158] - wire [31:0] _GEN_468 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 778:43] - wire [31:0] _GEN_469 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_468; // @[el2_lsu_bus_buffer.scala 778:43] - wire [31:0] _GEN_470 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_469; // @[el2_lsu_bus_buffer.scala 778:43] - wire _T_4400 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 786:82] - wire _T_4403 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 787:56] - wire _T_4406 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 789:62] - wire _T_4407 = io_lsu_axi_awvalid & _T_4406; // @[el2_lsu_bus_buffer.scala 789:60] - wire _T_4408 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 789:105] - wire _T_4409 = io_lsu_axi_wvalid & _T_4408; // @[el2_lsu_bus_buffer.scala 789:103] - wire _T_4410 = _T_4407 | _T_4409; // @[el2_lsu_bus_buffer.scala 789:82] - wire _T_4411 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 789:149] - wire _T_4412 = io_lsu_axi_arvalid & _T_4411; // @[el2_lsu_bus_buffer.scala 789:147] - wire _T_4414 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 791:51] - wire _T_4415 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 791:66] - wire _T_4416 = _T_4414 & _T_4415; // @[el2_lsu_bus_buffer.scala 791:64] - wire [31:0] _T_4420 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] - wire [2:0] _T_4423 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] - wire _T_4427 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 803:66] - wire _T_4428 = _T_4414 & _T_4427; // @[el2_lsu_bus_buffer.scala 803:64] - wire [7:0] _T_4432 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire _T_4435 = obuf_valid & _T_1170; // @[el2_lsu_bus_buffer.scala 808:51] - wire _T_4437 = _T_4435 & _T_1176; // @[el2_lsu_bus_buffer.scala 808:65] - assign io_lsu_busreq_r = _T_4338; // @[el2_lsu_bus_buffer.scala 749:34] - assign io_lsu_bus_buffer_pend_any = buf_numvld_pend_any != 4'h0; // @[el2_lsu_bus_buffer.scala 703:37] - assign io_lsu_bus_buffer_full_any = _T_4017 ? _T_4019 : _T_4021; // @[el2_lsu_bus_buffer.scala 704:37] - assign io_lsu_bus_buffer_empty_any = _T_4030[0]; // @[el2_lsu_bus_buffer.scala 705:37] - assign io_lsu_bus_idle_any = 1'h1; // @[el2_lsu_bus_buffer.scala 784:37] - assign io_ld_byte_hit_buf_lo = {_T_127,_T_116}; // @[el2_lsu_bus_buffer.scala 412:28] - assign io_ld_byte_hit_buf_hi = {_T_127,_T_116}; // @[el2_lsu_bus_buffer.scala 413:28] - assign io_ld_fwddata_buf_lo = 32'h0; // @[el2_lsu_bus_buffer.scala 422:28 el2_lsu_bus_buffer.scala 772:37] - assign io_ld_fwddata_buf_hi = 32'h0; // @[el2_lsu_bus_buffer.scala 423:28 el2_lsu_bus_buffer.scala 773:37] - assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4376; // @[el2_lsu_bus_buffer.scala 776:37] - assign io_lsu_imprecise_error_store_any = _T_4395 | _T_4393; // @[el2_lsu_bus_buffer.scala 777:37] - assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_470 : _GEN_453; // @[el2_lsu_bus_buffer.scala 778:37] - assign io_lsu_nonblock_load_valid_m = _T_4034 & _T_4035; // @[el2_lsu_bus_buffer.scala 707:37] - assign io_lsu_nonblock_load_tag_m = _T_1428 ? 2'h0 : _T_1468; // @[el2_lsu_bus_buffer.scala 708:37] - assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4038; // @[el2_lsu_bus_buffer.scala 709:37] - assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 710:37] - assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4190; // @[el2_lsu_bus_buffer.scala 723:37] - assign io_lsu_nonblock_load_data_error = _T_4078 | _T_4076; // @[el2_lsu_bus_buffer.scala 713:37] - assign io_lsu_nonblock_load_data_tag = _T_4114 | _T_4112; // @[el2_lsu_bus_buffer.scala 714:37] - assign io_lsu_nonblock_load_data = _T_4228 | _T_4225; // @[el2_lsu_bus_buffer.scala 724:37] - assign io_lsu_pmu_bus_trxn = _T_4400 | _T_4319; // @[el2_lsu_bus_buffer.scala 786:37] - assign io_lsu_pmu_bus_misaligned = _T_4403 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 787:37] - assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 788:37] - assign io_lsu_pmu_bus_busy = _T_4410 | _T_4412; // @[el2_lsu_bus_buffer.scala 789:37] - assign io_lsu_axi_awvalid = _T_4416 & _T_1154; // @[el2_lsu_bus_buffer.scala 791:37] - assign io_lsu_axi_awid = obuf_tag0; // @[el2_lsu_bus_buffer.scala 792:37] - assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4420; // @[el2_lsu_bus_buffer.scala 793:37] - assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 794:37] - assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_buffer.scala 795:37] - assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4423 : 3'h3; // @[el2_lsu_bus_buffer.scala 796:37] - assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_buffer.scala 797:37] - assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_buffer.scala 798:37] - assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 799:37] - assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu_bus_buffer.scala 800:37] - assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu_bus_buffer.scala 801:37] - assign io_lsu_axi_wvalid = _T_4428 & _T_1154; // @[el2_lsu_bus_buffer.scala 803:37] - assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 804:37] - assign io_lsu_axi_wstrb = obuf_byteen & _T_4432; // @[el2_lsu_bus_buffer.scala 805:37] - assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu_bus_buffer.scala 806:37] - assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 820:37] - assign io_lsu_axi_arvalid = _T_4437 & _T_1154; // @[el2_lsu_bus_buffer.scala 808:37] - assign io_lsu_axi_arid = obuf_tag0; // @[el2_lsu_bus_buffer.scala 809:37] - assign io_lsu_axi_araddr = io_lsu_axi_awaddr; // @[el2_lsu_bus_buffer.scala 810:37] - assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 811:37] - assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu_bus_buffer.scala 812:37] - assign io_lsu_axi_arsize = io_lsu_axi_awsize; // @[el2_lsu_bus_buffer.scala 813:37] - assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu_bus_buffer.scala 814:37] - assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu_bus_buffer.scala 815:37] - assign io_lsu_axi_arcache = io_lsu_axi_awcache; // @[el2_lsu_bus_buffer.scala 816:37] - assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu_bus_buffer.scala 817:37] - assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu_bus_buffer.scala 818:37] - assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 821:37] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4225 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4267 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] + wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] + wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] + wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] + wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] + wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 479:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 485:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 486:47] + wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 507:89] + wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 507:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 618:58] + wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 618:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 529:143] + wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 617:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 519:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 578:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] + wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] + wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] + wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] + wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] + wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] + wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] + wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] + wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] + wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4336; // @[Reg.scala 27:20] + reg _T_4339; // @[Reg.scala 27:20] + reg _T_4342; // @[Reg.scala 27:20] + reg _T_4345; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] + reg _T_4411; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4406; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4401; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4396; // @[el2_lsu_bus_buffer.scala 571:80] + wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 571:126] + wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 574:28] + wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 574:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 574:88] + wire [2:0] _GEN_380 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 574:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_380; // @[el2_lsu_bus_buffer.scala 574:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 574:217] + wire [1:0] _GEN_381 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_381; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _GEN_382 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_382; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 574:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 580:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 580:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 580:121] + wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 581:34] + wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 581:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 583:51] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 583:72] + wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 583:94] + wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 583:92] + wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 583:111] + wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 586:61] + reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 671:66] + wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] + wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] + wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] + wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72] + wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] + wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] + wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] + wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] + wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] + wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] + wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 590:106] + wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_383 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] + wire [1:0] _T_4610 = _GEN_383 | _T_4607; // @[Mux.scala 27:72] + wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] + wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] + wire _T_4656 = buf_dual_0 | buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 592:120] + wire _T_4657 = _T_4538 & _T_4656; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4662 = buf_dual_1 | buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 592:120] + wire _T_4663 = _T_4539 & _T_4662; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4668 = buf_dual_2 | buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 592:120] + wire _T_4669 = _T_4540 & _T_4668; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4674 = buf_dual_3 | buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 592:120] + wire _T_4675 = _T_4541 & _T_4674; // @[el2_lsu_bus_buffer.scala 592:105] + wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] + wire _T_4683 = io_lsu_nonblock_load_data_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4684 = io_lsu_nonblock_load_data_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4685 = io_lsu_nonblock_load_data_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4686 = io_lsu_nonblock_load_data_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123] + wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] + wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] + wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 593:83] + wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72] + wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] + wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_384 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 597:121] + wire [5:0] _T_4740 = _GEN_384 * 4'h8; // @[el2_lsu_bus_buffer.scala 597:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 597:92] + wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 599:69] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 600:81] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 600:63] + wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 601:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 601:26] + wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 602:6] + wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 602:27] + wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 603:27] + wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 604:21] + wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72] + wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72] + wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] + wire [63:0] _GEN_385 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] + wire [63:0] _T_4776 = _GEN_385 | _T_4772; // @[Mux.scala 27:72] + wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 622:36] + wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 622:51] + wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 622:49] + wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 634:50] + wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 634:48] + wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 639:36] + wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 639:50] + wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72] + wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72] + wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72] + wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72] + wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72] + wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72] + wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:98] + wire lsu_imprecise_error_store_tag = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:113] + wire _T_4945 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 655:72] + wire _T_4947 = ~lsu_imprecise_error_store_tag; // @[el2_lsu_bus_buffer.scala 112:123] + wire [31:0] _T_4949 = _T_4947 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4950 = lsu_imprecise_error_store_tag ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4951 = _T_4949 | _T_4950; // @[Mux.scala 27:72] + wire _T_4968 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 662:68] + wire _T_4971 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 663:48] + wire _T_4974 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 666:48] + wire _T_4975 = io_lsu_axi_awvalid & _T_4974; // @[el2_lsu_bus_buffer.scala 666:46] + wire _T_4976 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 666:92] + wire _T_4977 = io_lsu_axi_wvalid & _T_4976; // @[el2_lsu_bus_buffer.scala 666:90] + wire _T_4978 = _T_4975 | _T_4977; // @[el2_lsu_bus_buffer.scala 666:69] + wire _T_4979 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 666:136] + wire _T_4980 = io_lsu_axi_arvalid & _T_4979; // @[el2_lsu_bus_buffer.scala 666:134] + wire _T_4984 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 670:75] + wire _T_4985 = io_lsu_busreq_m & _T_4984; // @[el2_lsu_bus_buffer.scala 670:73] + reg _T_4988; // @[el2_lsu_bus_buffer.scala 670:56] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_lsu_busreq_r = _T_4988; // @[el2_lsu_bus_buffer.scala 670:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 579:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 580:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 581:31] + assign io_lsu_bus_idle_any = 1'h1; // @[el2_lsu_bus_buffer.scala 659:23] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 191:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 192:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 218:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 224:24] + assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4945; // @[el2_lsu_bus_buffer.scala 655:35] + assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 652:36] + assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _T_4951 : _T_4693; // @[el2_lsu_bus_buffer.scala 656:35] + assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 583:32] + assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 584:30] + assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 586:30] + assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 587:34] + assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 599:35] + assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 589:35] + assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 590:33] + assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 600:29] + assign io_lsu_pmu_bus_trxn = _T_4968 | _T_4863; // @[el2_lsu_bus_buffer.scala 662:23] + assign io_lsu_pmu_bus_misaligned = _T_4971 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 663:29] + assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 664:24] + assign io_lsu_pmu_bus_busy = _T_4978 | _T_4980; // @[el2_lsu_bus_buffer.scala 666:23] + assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 622:22] + assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 623:19] + assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 624:21] + assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 628:23] + assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_buffer.scala 629:20] + assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 625:21] + assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_buffer.scala 630:22] + assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_buffer.scala 632:21] + assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 627:22] + assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu_bus_buffer.scala 626:21] + assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu_bus_buffer.scala 631:20] + assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 634:21] + assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 636:20] + assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 635:20] + assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu_bus_buffer.scala 637:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 650:21] + assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 639:22] + assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 640:19] + assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 641:21] + assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 645:23] + assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu_bus_buffer.scala 646:20] + assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 642:21] + assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu_bus_buffer.scala 647:22] + assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu_bus_buffer.scala 649:21] + assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 644:22] + assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu_bus_buffer.scala 643:21] + assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu_bus_buffer.scala 648:20] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2207,285 +2803,234 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - ibuf_addr = _RAND_0[31:0]; + buf_addr_0 = _RAND_0[31:0]; _RAND_1 = {1{`RANDOM}}; - ibuf_write = _RAND_1[0:0]; + _T_4360 = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - ibuf_valid = _RAND_2[0:0]; + _T_4357 = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - ibuf_byteen = _RAND_3[3:0]; + _T_4354 = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - buf_addr_0 = _RAND_4[31:0]; + _T_4351 = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - buf_write_0 = _RAND_5[0:0]; + buf_state_0 = _RAND_5[2:0]; _RAND_6 = {1{`RANDOM}}; - buf_state_0 = _RAND_6[2:0]; + buf_addr_1 = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - buf_addr_1 = _RAND_7[31:0]; + buf_state_1 = _RAND_7[2:0]; _RAND_8 = {1{`RANDOM}}; - buf_write_1 = _RAND_8[0:0]; + buf_addr_2 = _RAND_8[31:0]; _RAND_9 = {1{`RANDOM}}; - buf_state_1 = _RAND_9[2:0]; + buf_state_2 = _RAND_9[2:0]; _RAND_10 = {1{`RANDOM}}; - buf_addr_2 = _RAND_10[31:0]; + buf_addr_3 = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; - buf_write_2 = _RAND_11[0:0]; + buf_state_3 = _RAND_11[2:0]; _RAND_12 = {1{`RANDOM}}; - buf_state_2 = _RAND_12[2:0]; + buf_byteen_3 = _RAND_12[3:0]; _RAND_13 = {1{`RANDOM}}; - buf_addr_3 = _RAND_13[31:0]; + buf_byteen_2 = _RAND_13[3:0]; _RAND_14 = {1{`RANDOM}}; - buf_write_3 = _RAND_14[0:0]; + buf_byteen_1 = _RAND_14[3:0]; _RAND_15 = {1{`RANDOM}}; - buf_state_3 = _RAND_15[2:0]; + buf_byteen_0 = _RAND_15[3:0]; _RAND_16 = {1{`RANDOM}}; - buf_byteen_3 = _RAND_16[3:0]; + buf_ageQ_3 = _RAND_16[3:0]; _RAND_17 = {1{`RANDOM}}; - buf_byteen_2 = _RAND_17[3:0]; + _T_1848 = _RAND_17[1:0]; _RAND_18 = {1{`RANDOM}}; - buf_byteen_1 = _RAND_18[3:0]; + obuf_merge = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - buf_byteen_0 = _RAND_19[3:0]; + obuf_tag1 = _RAND_19[1:0]; _RAND_20 = {1{`RANDOM}}; - buf_ageQ_3_3 = _RAND_20[0:0]; + obuf_valid = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - obuf_tag0 = _RAND_21[2:0]; + obuf_wr_enQ = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - obuf_merge = _RAND_22[0:0]; + ibuf_addr = _RAND_22[31:0]; _RAND_23 = {1{`RANDOM}}; - obuf_tag1 = _RAND_23[2:0]; + ibuf_write = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - obuf_valid = _RAND_24[0:0]; + ibuf_valid = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - obuf_wr_enQ = _RAND_25[0:0]; + ibuf_byteen = _RAND_25[3:0]; _RAND_26 = {1{`RANDOM}}; - buf_ageQ_3_2 = _RAND_26[0:0]; + buf_ageQ_2 = _RAND_26[3:0]; _RAND_27 = {1{`RANDOM}}; - buf_ageQ_3_1 = _RAND_27[0:0]; + buf_ageQ_1 = _RAND_27[3:0]; _RAND_28 = {1{`RANDOM}}; - buf_ageQ_3_0 = _RAND_28[0:0]; + buf_ageQ_0 = _RAND_28[3:0]; _RAND_29 = {1{`RANDOM}}; - buf_ageQ_2_3 = _RAND_29[0:0]; + buf_data_0 = _RAND_29[31:0]; _RAND_30 = {1{`RANDOM}}; - buf_ageQ_2_2 = _RAND_30[0:0]; + buf_data_1 = _RAND_30[31:0]; _RAND_31 = {1{`RANDOM}}; - buf_ageQ_2_1 = _RAND_31[0:0]; + buf_data_2 = _RAND_31[31:0]; _RAND_32 = {1{`RANDOM}}; - buf_ageQ_2_0 = _RAND_32[0:0]; + buf_data_3 = _RAND_32[31:0]; _RAND_33 = {1{`RANDOM}}; - buf_ageQ_1_3 = _RAND_33[0:0]; + ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - buf_ageQ_1_2 = _RAND_34[0:0]; + ibuf_timer = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - buf_ageQ_1_1 = _RAND_35[0:0]; + ibuf_sideeffect = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - buf_ageQ_1_0 = _RAND_36[0:0]; + WrPtr1_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - buf_ageQ_0_3 = _RAND_37[0:0]; + WrPtr0_r = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - buf_ageQ_0_2 = _RAND_38[0:0]; + ibuf_tag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - buf_ageQ_0_1 = _RAND_39[0:0]; + ibuf_dualtag = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - buf_ageQ_0_0 = _RAND_40[0:0]; + ibuf_dual = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_data = _RAND_41[31:0]; + ibuf_samedw = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - buf_data_0 = _RAND_42[31:0]; + ibuf_nomerge = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - buf_data_1 = _RAND_43[31:0]; + ibuf_unsign = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - buf_data_2 = _RAND_44[31:0]; + ibuf_sz = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - buf_data_3 = _RAND_45[31:0]; + obuf_wr_timer = _RAND_45[2:0]; _RAND_46 = {1{`RANDOM}}; - ibuf_timer = _RAND_46[2:0]; + buf_nomerge_0 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_47[0:0]; + buf_nomerge_1 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - ibuf_tag = _RAND_48[1:0]; + buf_nomerge_2 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - WrPtr1_r = _RAND_49[1:0]; + buf_nomerge_3 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - WrPtr0_r = _RAND_50[1:0]; + _T_4330 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - ibuf_dual = _RAND_51[0:0]; + _T_4327 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - ibuf_samedw = _RAND_52[0:0]; + _T_4324 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_53[0:0]; + _T_4321 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - ibuf_unsign = _RAND_54[0:0]; + buf_dual_3 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - ibuf_sz = _RAND_55[1:0]; + buf_dual_2 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_56[1:0]; + buf_dual_1 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - obuf_wr_timer = _RAND_57[2:0]; + buf_dual_0 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_58[0:0]; + buf_samedw_3 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_59[0:0]; + buf_samedw_2 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_60[0:0]; + buf_samedw_1 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_61[0:0]; + buf_samedw_0 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - buf_sideeffect_0 = _RAND_62[0:0]; + obuf_write = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - buf_sideeffect_1 = _RAND_63[0:0]; + obuf_cmd_done = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - buf_sideeffect_2 = _RAND_64[0:0]; + obuf_data_done = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - buf_sideeffect_3 = _RAND_65[0:0]; + obuf_nosend = _RAND_65[0:0]; _RAND_66 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_66[0:0]; + obuf_addr = _RAND_66[31:0]; _RAND_67 = {1{`RANDOM}}; - buf_dual_0 = _RAND_67[0:0]; + buf_sz_0 = _RAND_67[1:0]; _RAND_68 = {1{`RANDOM}}; - buf_dual_1 = _RAND_68[0:0]; + buf_sz_1 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_dual_2 = _RAND_69[0:0]; + buf_sz_2 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - buf_dual_3 = _RAND_70[0:0]; + buf_sz_3 = _RAND_70[1:0]; _RAND_71 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_71[0:0]; + obuf_sideeffect = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_72[0:0]; + obuf_rdrsp_pend = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_73[0:0]; + obuf_rdrsp_tag = _RAND_73[2:0]; _RAND_74 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_74[0:0]; + buf_dualhi_3 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - obuf_write = _RAND_75[0:0]; + buf_dualhi_2 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_76[0:0]; + buf_dualhi_1 = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - obuf_data_done = _RAND_77[0:0]; + buf_dualhi_0 = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - obuf_nosend = _RAND_78[0:0]; - _RAND_79 = {2{`RANDOM}}; - _T_1397 = _RAND_79[63:0]; - _RAND_80 = {1{`RANDOM}}; - buf_sz_3 = _RAND_80[1:0]; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; _RAND_81 = {1{`RANDOM}}; - buf_sz_2 = _RAND_81[1:0]; + buf_rspageQ_0 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_sz_1 = _RAND_82[1:0]; + buf_rspageQ_1 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - buf_sz_0 = _RAND_83[1:0]; + buf_rspageQ_2 = _RAND_83[3:0]; _RAND_84 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_84[2:0]; + buf_rspageQ_3 = _RAND_84[3:0]; _RAND_85 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_85[0:0]; + _T_4307 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_86[0:0]; + _T_4305 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_87[0:0]; + _T_4303 = _RAND_87[0:0]; _RAND_88 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_88[0:0]; + _T_4301 = _RAND_88[0:0]; _RAND_89 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_89[0:0]; - _RAND_90 = {2{`RANDOM}}; - obuf_data = _RAND_90[63:0]; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - obuf_sz = _RAND_91[1:0]; + buf_ldfwdtag_3 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - obuf_byteen = _RAND_92[7:0]; + buf_ldfwdtag_2 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_rspageQ_0_1 = _RAND_93[0:0]; + buf_ldfwdtag_1 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_rspageQ_0_0 = _RAND_94[0:0]; + buf_dualtag_1 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - buf_rspageQ_0_3 = _RAND_95[0:0]; + buf_dualtag_2 = _RAND_95[1:0]; _RAND_96 = {1{`RANDOM}}; - buf_rspageQ_0_2 = _RAND_96[0:0]; + buf_dualtag_3 = _RAND_96[1:0]; _RAND_97 = {1{`RANDOM}}; - buf_ldfwd_0 = _RAND_97[0:0]; + _T_4336 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_98[1:0]; + _T_4339 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_99[1:0]; + _T_4342 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - buf_ldfwd_3 = _RAND_100[0:0]; + _T_4345 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - buf_ldfwd_2 = _RAND_101[0:0]; + _T_4411 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - buf_ldfwd_1 = _RAND_102[0:0]; + _T_4406 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_103[1:0]; + _T_4401 = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_104[1:0]; + _T_4396 = _RAND_104[0:0]; _RAND_105 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_105[1:0]; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; _RAND_106 = {1{`RANDOM}}; - buf_rspageQ_3_3 = _RAND_106[0:0]; - _RAND_107 = {1{`RANDOM}}; - buf_rspageQ_3_2 = _RAND_107[0:0]; - _RAND_108 = {1{`RANDOM}}; - buf_rspageQ_3_1 = _RAND_108[0:0]; - _RAND_109 = {1{`RANDOM}}; - buf_rspageQ_3_0 = _RAND_109[0:0]; - _RAND_110 = {1{`RANDOM}}; - buf_rspageQ_2_3 = _RAND_110[0:0]; - _RAND_111 = {1{`RANDOM}}; - buf_rspageQ_2_2 = _RAND_111[0:0]; - _RAND_112 = {1{`RANDOM}}; - buf_rspageQ_2_1 = _RAND_112[0:0]; - _RAND_113 = {1{`RANDOM}}; - buf_rspageQ_2_0 = _RAND_113[0:0]; - _RAND_114 = {1{`RANDOM}}; - buf_rspageQ_1_3 = _RAND_114[0:0]; - _RAND_115 = {1{`RANDOM}}; - buf_rspageQ_1_2 = _RAND_115[0:0]; - _RAND_116 = {1{`RANDOM}}; - buf_rspageQ_1_1 = _RAND_116[0:0]; - _RAND_117 = {1{`RANDOM}}; - buf_rspageQ_1_0 = _RAND_117[0:0]; - _RAND_118 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_118[1:0]; - _RAND_119 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_119[1:0]; - _RAND_120 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_120[1:0]; - _RAND_121 = {1{`RANDOM}}; - buf_unsign_0 = _RAND_121[0:0]; - _RAND_122 = {1{`RANDOM}}; - buf_error_0 = _RAND_122[0:0]; - _RAND_123 = {1{`RANDOM}}; - buf_unsign_1 = _RAND_123[0:0]; - _RAND_124 = {1{`RANDOM}}; - buf_error_1 = _RAND_124[0:0]; - _RAND_125 = {1{`RANDOM}}; - buf_unsign_2 = _RAND_125[0:0]; - _RAND_126 = {1{`RANDOM}}; - buf_error_2 = _RAND_126[0:0]; - _RAND_127 = {1{`RANDOM}}; - buf_unsign_3 = _RAND_127[0:0]; - _RAND_128 = {1{`RANDOM}}; - buf_error_3 = _RAND_128[0:0]; - _RAND_129 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_129[0:0]; - _RAND_130 = {1{`RANDOM}}; - _T_4338 = _RAND_130[0:0]; + _T_4988 = _RAND_106[0:0]; `endif // RANDOMIZE_REG_INIT - if (reset) begin - ibuf_addr = 32'h0; - end - if (reset) begin - ibuf_write = 1'h0; - end - if (reset) begin - ibuf_valid = 1'h0; - end - if (reset) begin - ibuf_byteen = 4'h0; - end if (reset) begin buf_addr_0 = 32'h0; end if (reset) begin - buf_write_0 = 1'h0; + _T_4360 = 1'h0; + end + if (reset) begin + _T_4357 = 1'h0; + end + if (reset) begin + _T_4354 = 1'h0; + end + if (reset) begin + _T_4351 = 1'h0; end if (reset) begin buf_state_0 = 3'h0; @@ -2493,27 +3038,18 @@ initial begin if (reset) begin buf_addr_1 = 32'h0; end - if (reset) begin - buf_write_1 = 1'h0; - end if (reset) begin buf_state_1 = 3'h0; end if (reset) begin buf_addr_2 = 32'h0; end - if (reset) begin - buf_write_2 = 1'h0; - end if (reset) begin buf_state_2 = 3'h0; end if (reset) begin buf_addr_3 = 32'h0; end - if (reset) begin - buf_write_3 = 1'h0; - end if (reset) begin buf_state_3 = 3'h0; end @@ -2530,16 +3066,16 @@ initial begin buf_byteen_0 = 4'h0; end if (reset) begin - buf_ageQ_3_3 = 1'h0; + buf_ageQ_3 = 4'h0; end if (reset) begin - obuf_tag0 = 3'h0; + _T_1848 = 2'h0; end if (reset) begin obuf_merge = 1'h0; end if (reset) begin - obuf_tag1 = 3'h0; + obuf_tag1 = 2'h0; end if (reset) begin obuf_valid = 1'h0; @@ -2548,52 +3084,25 @@ initial begin obuf_wr_enQ = 1'h0; end if (reset) begin - buf_ageQ_3_2 = 1'h0; + ibuf_addr = 32'h0; end if (reset) begin - buf_ageQ_3_1 = 1'h0; + ibuf_write = 1'h0; end if (reset) begin - buf_ageQ_3_0 = 1'h0; + ibuf_valid = 1'h0; end if (reset) begin - buf_ageQ_2_3 = 1'h0; + ibuf_byteen = 4'h0; end if (reset) begin - buf_ageQ_2_2 = 1'h0; + buf_ageQ_2 = 4'h0; end if (reset) begin - buf_ageQ_2_1 = 1'h0; + buf_ageQ_1 = 4'h0; end if (reset) begin - buf_ageQ_2_0 = 1'h0; - end - if (reset) begin - buf_ageQ_1_3 = 1'h0; - end - if (reset) begin - buf_ageQ_1_2 = 1'h0; - end - if (reset) begin - buf_ageQ_1_1 = 1'h0; - end - if (reset) begin - buf_ageQ_1_0 = 1'h0; - end - if (reset) begin - buf_ageQ_0_3 = 1'h0; - end - if (reset) begin - buf_ageQ_0_2 = 1'h0; - end - if (reset) begin - buf_ageQ_0_1 = 1'h0; - end - if (reset) begin - buf_ageQ_0_0 = 1'h0; - end - if (reset) begin - ibuf_data = 32'h0; + buf_ageQ_0 = 4'h0; end if (reset) begin buf_data_0 = 32'h0; @@ -2607,21 +3116,27 @@ initial begin if (reset) begin buf_data_3 = 32'h0; end + if (reset) begin + ibuf_data = 32'h0; + end if (reset) begin ibuf_timer = 3'h0; end if (reset) begin ibuf_sideeffect = 1'h0; end - if (reset) begin - ibuf_tag = 2'h0; - end if (reset) begin WrPtr1_r = 2'h0; end if (reset) begin WrPtr0_r = 2'h0; end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end if (reset) begin ibuf_dual = 1'h0; end @@ -2637,9 +3152,6 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end - if (reset) begin - ibuf_dualtag = 2'h0; - end if (reset) begin obuf_wr_timer = 3'h0; end @@ -2656,43 +3168,40 @@ initial begin buf_nomerge_3 = 1'h0; end if (reset) begin - buf_sideeffect_0 = 1'h0; + _T_4330 = 1'h0; end if (reset) begin - buf_sideeffect_1 = 1'h0; + _T_4327 = 1'h0; end if (reset) begin - buf_sideeffect_2 = 1'h0; + _T_4324 = 1'h0; end if (reset) begin - buf_sideeffect_3 = 1'h0; - end - if (reset) begin - obuf_sideeffect = 1'h0; - end - if (reset) begin - buf_dual_0 = 1'h0; - end - if (reset) begin - buf_dual_1 = 1'h0; - end - if (reset) begin - buf_dual_2 = 1'h0; + _T_4321 = 1'h0; end if (reset) begin buf_dual_3 = 1'h0; end if (reset) begin - buf_samedw_0 = 1'h0; + buf_dual_2 = 1'h0; end if (reset) begin - buf_samedw_1 = 1'h0; + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; end if (reset) begin buf_samedw_2 = 1'h0; end if (reset) begin - buf_samedw_3 = 1'h0; + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; end if (reset) begin obuf_write = 1'h0; @@ -2707,26 +3216,29 @@ initial begin obuf_nosend = 1'h0; end if (reset) begin - _T_1397 = 64'h0; - end - if (reset) begin - buf_sz_3 = 2'h0; - end - if (reset) begin - buf_sz_2 = 2'h0; - end - if (reset) begin - buf_sz_1 = 2'h0; + obuf_addr = 32'h0; end if (reset) begin buf_sz_0 = 2'h0; end if (reset) begin - obuf_rdrsp_tag = 3'h0; + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; end if (reset) begin obuf_rdrsp_pend = 1'h0; end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end if (reset) begin buf_dualhi_3 = 1'h0; end @@ -2739,9 +3251,6 @@ initial begin if (reset) begin buf_dualhi_0 = 1'h0; end - if (reset) begin - obuf_data = 64'h0; - end if (reset) begin obuf_sz = 2'h0; end @@ -2749,19 +3258,31 @@ initial begin obuf_byteen = 8'h0; end if (reset) begin - buf_rspageQ_0_1 = 1'h0; + obuf_data = 64'h0; end if (reset) begin - buf_rspageQ_0_0 = 1'h0; + buf_rspageQ_0 = 4'h0; end if (reset) begin - buf_rspageQ_0_3 = 1'h0; + buf_rspageQ_1 = 4'h0; end if (reset) begin - buf_rspageQ_0_2 = 1'h0; + buf_rspageQ_2 = 4'h0; end if (reset) begin - buf_ldfwd_0 = 1'h0; + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4307 = 1'h0; + end + if (reset) begin + _T_4305 = 1'h0; + end + if (reset) begin + _T_4303 = 1'h0; + end + if (reset) begin + _T_4301 = 1'h0; end if (reset) begin buf_ldfwdtag_0 = 2'h0; @@ -2769,15 +3290,6 @@ initial begin if (reset) begin buf_dualtag_0 = 2'h0; end - if (reset) begin - buf_ldfwd_3 = 1'h0; - end - if (reset) begin - buf_ldfwd_2 = 1'h0; - end - if (reset) begin - buf_ldfwd_1 = 1'h0; - end if (reset) begin buf_ldfwdtag_3 = 2'h0; end @@ -2787,42 +3299,6 @@ initial begin if (reset) begin buf_ldfwdtag_1 = 2'h0; end - if (reset) begin - buf_rspageQ_3_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_0 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_0 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_0 = 1'h0; - end if (reset) begin buf_dualtag_1 = 2'h0; end @@ -2833,34 +3309,34 @@ initial begin buf_dualtag_3 = 2'h0; end if (reset) begin - buf_unsign_0 = 1'h0; + _T_4336 = 1'h0; end if (reset) begin - buf_error_0 = 1'h0; + _T_4339 = 1'h0; end if (reset) begin - buf_unsign_1 = 1'h0; + _T_4342 = 1'h0; end if (reset) begin - buf_error_1 = 1'h0; + _T_4345 = 1'h0; end if (reset) begin - buf_unsign_2 = 1'h0; + _T_4411 = 1'h0; end if (reset) begin - buf_error_2 = 1'h0; + _T_4406 = 1'h0; end if (reset) begin - buf_unsign_3 = 1'h0; + _T_4401 = 1'h0; end if (reset) begin - buf_error_3 = 1'h0; + _T_4396 = 1'h0; end if (reset) begin lsu_nonblock_load_valid_r = 1'h0; end if (reset) begin - _T_4338 = 1'h0; + _T_4988 = 1'h0; end `endif // RANDOMIZE end // initial @@ -2868,15 +3344,399 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3343) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4360 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4360 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4357 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4357 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4354 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4354 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4351 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4351 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3528) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3551) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3555) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3559) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3589) begin + if (_T_3594) begin + buf_state_0 <= 3'h0; + end else if (_T_3602) begin + buf_state_0 <= 3'h4; + end else if (_T_3630) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3676) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3682) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3694) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3352) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3721) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3744) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3748) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3559) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3782) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3869) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3875) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3887) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3361) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3914) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3937) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3941) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3559) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3975) begin + if (_T_3980) begin + buf_state_2 <= 3'h0; + end else if (_T_3988) begin + buf_state_2 <= 3'h4; + end else if (_T_4016) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4062) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4068) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4080) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3370) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4107) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4130) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4134) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3559) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4168) begin + if (_T_4173) begin + buf_state_3 <= 3'h0; + end else if (_T_4181) begin + buf_state_3 <= 3'h4; + end else if (_T_4209) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4255) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4261) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4273) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3370) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3361) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3352) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3343) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2535,_T_2458}; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + _T_1848 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1848 <= WrPtr0_r; + end else begin + _T_1848 <= CmdPtr0; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= 2'h0; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1839 & _T_1840; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin ibuf_addr <= 32'h0; - end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin - ibuf_addr <= io_end_addr_r; - end else begin - ibuf_addr <= io_lsu_addr_r; - end + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -2890,15 +3750,15 @@ end // initial if (reset) begin ibuf_valid <= 1'h0; end else begin - ibuf_valid <= _T_1074 & _T_1075; + ibuf_valid <= _T_1005 & _T_1006; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (_T_925) begin - ibuf_byteen <= _T_945; + if (_T_866) begin + ibuf_byteen <= _T_881; end else if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin @@ -2908,656 +3768,162 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_addr_0 <= 32'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_addr_0 <= ibuf_addr; - end else if (_T_3143) begin - buf_addr_0 <= io_end_addr_r; - end else begin - buf_addr_0 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_write_0 <= ibuf_write; - end else begin - buf_write_0 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_0 <= 3'h0; - end else if (buf_state_en_0) begin - if (_T_3132) begin - if (io_lsu_bus_clk_en) begin - buf_state_0 <= 3'h2; - end else begin - buf_state_0 <= 3'h1; - end - end else if (_T_3155) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else begin - buf_state_0 <= 3'h2; - end - end else if (_T_3159) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else if (_T_3163) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h3; - end - end else if (_T_3192) begin - if (_T_3196) begin - buf_state_0 <= 3'h0; - end else if (_T_3203) begin - buf_state_0 <= 3'h4; - end else if (_T_3213) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h6; - end - end else if (_T_3256) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else if (_T_3259) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h6; - end - end else if (_T_3269) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else begin - buf_state_0 <= 3'h6; - end - end else begin - buf_state_0 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_1 <= 32'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_addr_1 <= ibuf_addr; - end else if (_T_3351) begin - buf_addr_1 <= io_end_addr_r; - end else begin - buf_addr_1 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_write_1 <= ibuf_write; - end else begin - buf_write_1 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_1 <= 3'h0; - end else if (buf_state_en_1) begin - if (_T_3340) begin - if (io_lsu_bus_clk_en) begin - buf_state_1 <= 3'h2; - end else begin - buf_state_1 <= 3'h1; - end - end else if (_T_3363) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else begin - buf_state_1 <= 3'h2; - end - end else if (_T_3367) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else if (_T_3163) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h3; - end - end else if (_T_3400) begin - if (_T_3404) begin - buf_state_1 <= 3'h0; - end else if (_T_3411) begin - buf_state_1 <= 3'h4; - end else if (_T_3421) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h6; - end - end else if (_T_3464) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else if (_T_3467) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h6; - end - end else if (_T_3477) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else begin - buf_state_1 <= 3'h6; - end - end else begin - buf_state_1 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_2 <= 32'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_addr_2 <= ibuf_addr; - end else if (_T_3559) begin - buf_addr_2 <= io_end_addr_r; - end else begin - buf_addr_2 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_2 <= 1'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_write_2 <= ibuf_write; - end else begin - buf_write_2 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_2 <= 3'h0; - end else if (buf_state_en_2) begin - if (_T_3548) begin - if (io_lsu_bus_clk_en) begin - buf_state_2 <= 3'h2; - end else begin - buf_state_2 <= 3'h1; - end - end else if (_T_3571) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else begin - buf_state_2 <= 3'h2; - end - end else if (_T_3575) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else if (_T_3163) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h3; - end - end else if (_T_3608) begin - if (_T_3612) begin - buf_state_2 <= 3'h0; - end else if (_T_3619) begin - buf_state_2 <= 3'h4; - end else if (_T_3629) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h6; - end - end else if (_T_3672) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else if (_T_3675) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h6; - end - end else if (_T_3685) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else begin - buf_state_2 <= 3'h6; - end - end else begin - buf_state_2 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_3 <= 32'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_addr_3 <= ibuf_addr; - end else if (_T_3767) begin - buf_addr_3 <= io_end_addr_r; - end else begin - buf_addr_3 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_3 <= 1'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_write_3 <= ibuf_write; - end else begin - buf_write_3 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_3 <= 3'h0; - end else if (buf_state_en_3) begin - if (_T_3756) begin - if (io_lsu_bus_clk_en) begin - buf_state_3 <= 3'h2; - end else begin - buf_state_3 <= 3'h1; - end - end else if (_T_3779) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else begin - buf_state_3 <= 3'h2; - end - end else if (_T_3783) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else if (_T_3163) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h3; - end - end else if (_T_3816) begin - if (_T_3820) begin - buf_state_3 <= 3'h0; - end else if (_T_3827) begin - buf_state_3 <= 3'h4; - end else if (_T_3837) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h6; - end - end else if (_T_3880) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else if (_T_3883) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h6; - end - end else if (_T_3893) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else begin - buf_state_3 <= 3'h6; - end - end else begin - buf_state_3 <= 3'h0; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_3 <= 4'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_byteen_3 <= ibuf_byteen_out; - end else if (_T_3767) begin - buf_byteen_3 <= ldst_byteen_hi_r; - end else begin - buf_byteen_3 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_2 <= 4'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_byteen_2 <= ibuf_byteen_out; - end else if (_T_3559) begin - buf_byteen_2 <= ldst_byteen_hi_r; - end else begin - buf_byteen_2 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_1 <= 4'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_byteen_1 <= ibuf_byteen_out; - end else if (_T_3351) begin - buf_byteen_1 <= ldst_byteen_hi_r; - end else begin - buf_byteen_1 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_0 <= 4'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_byteen_0 <= ibuf_byteen_out; - end else if (_T_3143) begin - buf_byteen_0 <= ldst_byteen_hi_r; - end else begin - buf_byteen_0 <= ldst_byteen_lo_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_3_3 <= 1'h0; + buf_ageQ_2 <= 4'h0; end else begin - buf_ageQ_3_3 <= _T_3013 | buf_age_3_3; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_tag0 <= 3'h0; - end else if (obuf_wr_en) begin - obuf_tag0 <= obuf_tag0_in; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_merge <= 1'h0; - end else if (obuf_wr_en) begin - obuf_merge <= obuf_merge_en; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_tag1 <= 3'h0; - end else if (obuf_wr_en) begin - obuf_tag1 <= obuf_tag1_in; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - obuf_valid <= 1'h0; - end else begin - obuf_valid <= _T_1406 & _T_1407; - end - end - always @(posedge io_lsu_busm_clk or posedge reset) begin - if (reset) begin - obuf_wr_enQ <= 1'h0; - end else begin - obuf_wr_enQ <= _T_1155 & io_lsu_bus_clk_en; + buf_ageQ_2 <= {_T_2433,_T_2356}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ageQ_3_2 <= 1'h0; + buf_ageQ_1 <= 4'h0; end else begin - buf_ageQ_3_2 <= _T_2918 | buf_age_3_2; + buf_ageQ_1 <= {_T_2331,_T_2254}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ageQ_3_1 <= 1'h0; + buf_ageQ_0 <= 4'h0; end else begin - buf_ageQ_3_1 <= _T_2823 | buf_age_3_1; + buf_ageQ_0 <= {_T_2229,_T_2152}; end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_3_0 <= 1'h0; - end else begin - buf_ageQ_3_0 <= _T_2728 | buf_age_3_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_3 <= 1'h0; - end else begin - buf_ageQ_2_3 <= _T_2633 | buf_age_2_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_2 <= 1'h0; - end else begin - buf_ageQ_2_2 <= _T_2538 | buf_age_2_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_1 <= 1'h0; - end else begin - buf_ageQ_2_1 <= _T_2443 | buf_age_2_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_0 <= 1'h0; - end else begin - buf_ageQ_2_0 <= _T_2348 | buf_age_2_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_3 <= 1'h0; - end else begin - buf_ageQ_1_3 <= _T_2253 | buf_age_1_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_2 <= 1'h0; - end else begin - buf_ageQ_1_2 <= _T_2158 | buf_age_1_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_1 <= 1'h0; - end else begin - buf_ageQ_1_1 <= _T_2063 | buf_age_1_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_0 <= 1'h0; - end else begin - buf_ageQ_1_0 <= _T_1968 | buf_age_1_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_3 <= 1'h0; - end else begin - buf_ageQ_0_3 <= _T_1873 | buf_age_0_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_2 <= 1'h0; - end else begin - buf_ageQ_0_2 <= _T_1778 | buf_age_0_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_1 <= 1'h0; - end else begin - buf_ageQ_0_1 <= _T_1683 | buf_age_0_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_0 <= 1'h0; - end else begin - buf_ageQ_0_0 <= _T_1588 | buf_age_0_0; - end - end - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin - if (reset) begin - ibuf_data <= 32'h0; - end else if (ibuf_wr_en) begin - ibuf_data <= ibuf_data_in; - end - end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin buf_data_0 <= 32'h0; - end else if (buf_data_en_0) begin - if (_T_3132) begin - if (_T_3147) begin - buf_data_0 <= ibuf_data_out; - end else begin - buf_data_0 <= store_data_lo_r; - end - end else if (_T_3155) begin - buf_data_0 <= 32'h0; - end else if (_T_3159) begin - if (buf_error_en_0) begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_0[2]) begin + end else if (_T_3528) begin + if (_T_3543) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3551) begin + buf_data_0 <= 32'h0; + end else if (_T_3555) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3589) begin + if (_T_3669) begin + if (buf_addr_0[2]) begin buf_data_0 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_0 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3192) begin - if (_T_3249) begin - if (buf_addr_0[2]) begin - buf_data_0 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_0 <= 32'h0; + buf_data_0 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_0 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin buf_data_1 <= 32'h0; - end else if (buf_data_en_1) begin - if (_T_3340) begin - if (_T_3355) begin - buf_data_1 <= ibuf_data_out; - end else begin - buf_data_1 <= store_data_lo_r; - end - end else if (_T_3363) begin - buf_data_1 <= 32'h0; - end else if (_T_3367) begin - if (buf_error_en_1) begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_1[2]) begin + end else if (_T_3721) begin + if (_T_3736) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3744) begin + buf_data_1 <= 32'h0; + end else if (_T_3748) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3782) begin + if (_T_3862) begin + if (buf_addr_1[2]) begin buf_data_1 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_1 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3400) begin - if (_T_3457) begin - if (buf_addr_1[2]) begin - buf_data_1 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_1 <= 32'h0; + buf_data_1 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_1 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin buf_data_2 <= 32'h0; - end else if (buf_data_en_2) begin - if (_T_3548) begin - if (_T_3563) begin - buf_data_2 <= ibuf_data_out; - end else begin - buf_data_2 <= store_data_lo_r; - end - end else if (_T_3571) begin - buf_data_2 <= 32'h0; - end else if (_T_3575) begin - if (buf_error_en_2) begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_2[2]) begin + end else if (_T_3914) begin + if (_T_3929) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3937) begin + buf_data_2 <= 32'h0; + end else if (_T_3941) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3975) begin + if (_T_4055) begin + if (buf_addr_2[2]) begin buf_data_2 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_2 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3608) begin - if (_T_3665) begin - if (buf_addr_2[2]) begin - buf_data_2 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_2 <= 32'h0; + buf_data_2 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_2 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin buf_data_3 <= 32'h0; - end else if (buf_data_en_3) begin - if (_T_3756) begin - if (_T_3771) begin - buf_data_3 <= ibuf_data_out; - end else begin - buf_data_3 <= store_data_lo_r; - end - end else if (_T_3779) begin - buf_data_3 <= 32'h0; - end else if (_T_3783) begin - if (buf_error_en_3) begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_3[2]) begin + end else if (_T_4107) begin + if (_T_4122) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4130) begin + buf_data_3 <= 32'h0; + end else if (_T_4134) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_4168) begin + if (_T_4248) begin + if (buf_addr_3[2]) begin buf_data_3 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_3 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3816) begin - if (_T_3873) begin - if (buf_addr_3[2]) begin - buf_data_3 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_3 <= 32'h0; + buf_data_3 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_3 <= 32'h0; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_922,_T_893}; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -3565,8 +3931,8 @@ end // initial ibuf_timer <= 3'h0; end else if (ibuf_wr_en) begin ibuf_timer <= 3'h0; - end else if (_T_989) begin - ibuf_timer <= _T_991; + end else if (_T_923) begin + ibuf_timer <= _T_926; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -3576,11 +3942,37 @@ end // initial ibuf_sideeffect <= io_is_sideeffects_r; end end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1914) begin + WrPtr1_r <= 2'h0; + end else if (_T_1928) begin + WrPtr1_r <= 2'h1; + end else if (_T_1942) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1863) begin + WrPtr0_r <= 2'h0; + end else if (_T_1874) begin + WrPtr0_r <= 2'h1; + end else if (_T_1885) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (!(_T_925)) begin + if (!(_T_866)) begin if (io_ldst_dual_r) begin ibuf_tag <= WrPtr1_r; end else begin @@ -3589,34 +3981,11 @@ end // initial end end end - always @(posedge io_lsu_c2_r_clk or posedge reset) begin + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin - WrPtr1_r <= 2'h0; - end else if (_T_1483) begin - WrPtr1_r <= 2'h0; - end else if (_T_1498) begin - WrPtr1_r <= 2'h1; - end else if (_T_1513) begin - WrPtr1_r <= 2'h2; - end else if (_T_1528) begin - WrPtr1_r <= 2'h3; - end else begin - WrPtr1_r <= 2'h0; - end - end - always @(posedge io_lsu_c2_r_clk or posedge reset) begin - if (reset) begin - WrPtr0_r <= 2'h0; - end else if (_T_1428) begin - WrPtr0_r <= 2'h0; - end else if (_T_1440) begin - WrPtr0_r <= 2'h1; - end else if (_T_1452) begin - WrPtr0_r <= 2'h2; - end else if (_T_1464) begin - WrPtr0_r <= 2'h3; - end else begin - WrPtr0_r <= 2'h0; + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -3654,213 +4023,125 @@ end // initial ibuf_sz <= ibuf_sz_in; end end - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin - if (reset) begin - ibuf_dualtag <= 2'h0; - end else if (ibuf_wr_en) begin - ibuf_dualtag <= WrPtr0_r; - end - end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_wr_timer <= 3'h0; end else if (obuf_wr_en) begin obuf_wr_timer <= 3'h0; - end else if (_T_1348) begin - obuf_wr_timer <= _T_1350; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_nomerge_0 <= _T_3115; - end else begin - buf_nomerge_0 <= io_no_dword_merge_r; - end + buf_nomerge_0 <= buf_nomerge_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_1 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_nomerge_1 <= _T_3115; - end else begin - buf_nomerge_1 <= io_no_dword_merge_r; - end + buf_nomerge_1 <= buf_nomerge_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_nomerge_2 <= _T_3115; - end else begin - buf_nomerge_2 <= io_no_dword_merge_r; - end + buf_nomerge_2 <= buf_nomerge_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_nomerge_3 <= _T_3115; - end else begin - buf_nomerge_3 <= io_no_dword_merge_r; - end + buf_nomerge_3 <= buf_nomerge_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sideeffect_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_sideeffect_0 <= ibuf_sideeffect; - end else begin - buf_sideeffect_0 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_sideeffect_1 <= ibuf_sideeffect; - end else begin - buf_sideeffect_1 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_2 <= 1'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_sideeffect_2 <= ibuf_sideeffect; - end else begin - buf_sideeffect_2 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_3 <= 1'h0; + _T_4330 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_sideeffect_3 <= ibuf_sideeffect; - end else begin - buf_sideeffect_3 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_sideeffect <= 1'h0; - end else if (obuf_wr_en) begin - if (ibuf_buf_byp) begin - obuf_sideeffect <= io_is_sideeffects_r; - end else if (2'h3 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_3; - end else if (2'h2 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_2; - end else if (2'h1 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_1; - end else begin - obuf_sideeffect <= buf_sideeffect_0; - end + _T_4330 <= buf_sideeffect_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_dual_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_dual_0 <= ibuf_dual; - end else begin - buf_dual_0 <= io_ldst_dual_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_dual_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_dual_1 <= ibuf_dual; - end else begin - buf_dual_1 <= io_ldst_dual_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_dual_2 <= 1'h0; + _T_4327 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_dual_2 <= ibuf_dual; - end else begin - buf_dual_2 <= io_ldst_dual_r; - end + _T_4327 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4324 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4324 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4321 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4321 <= buf_sideeffect_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dual_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_dual_3 <= ibuf_dual; - end else begin - buf_dual_3 <= io_ldst_dual_r; - end + buf_dual_3 <= buf_dual_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_samedw_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_samedw_0 <= ibuf_samedw; - end else begin - buf_samedw_0 <= ldst_samedw_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_samedw_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_samedw_1 <= ibuf_samedw; - end else begin - buf_samedw_1 <= ldst_samedw_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_samedw_2 <= 1'h0; + buf_dual_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_samedw_2 <= ibuf_samedw; - end else begin - buf_samedw_2 <= ldst_samedw_r; - end + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_samedw_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_samedw_3 <= ibuf_samedw; - end else begin - buf_samedw_3 <= ldst_samedw_r; - end + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; end end always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin @@ -3869,14 +4150,8 @@ end // initial end else if (obuf_wr_en) begin if (ibuf_buf_byp) begin obuf_write <= io_lsu_pkt_r_store; - end else if (2'h3 == CmdPtr0) begin - obuf_write <= buf_write_3; - end else if (2'h2 == CmdPtr0) begin - obuf_write <= buf_write_2; - end else if (2'h1 == CmdPtr0) begin - obuf_write <= buf_write_1; end else begin - obuf_write <= buf_write_0; + obuf_write <= _T_1202; end end end @@ -3884,14 +4159,14 @@ end // initial if (reset) begin obuf_cmd_done <= 1'h0; end else begin - obuf_cmd_done <= _T_1302 & _T_4316; + obuf_cmd_done <= _T_1305 & _T_4860; end end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_data_done <= 1'h0; end else begin - obuf_data_done <= _T_1302 & _T_4317; + obuf_data_done <= _T_1305 & _T_4861; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -3901,32 +4176,23 @@ end // initial obuf_nosend <= obuf_nosend_in; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin - _T_1397 <= 64'h0; - end else if (obuf_wr_en) begin - _T_1397 <= obuf_addr_in; + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1289; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sz_3 <= 2'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_sz_3 <= ibuf_sz; + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; end else begin - buf_sz_3 <= ibuf_sz_in; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sz_2 <= 2'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_sz_2 <= ibuf_sz; - end else begin - buf_sz_2 <= ibuf_sz_in; + buf_sz_0 <= ibuf_sz_in; end end end @@ -3934,7 +4200,7 @@ end // initial if (reset) begin buf_sz_1 <= 2'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin + if (ibuf_drainvec_vld[1]) begin buf_sz_1 <= ibuf_sz; end else begin buf_sz_1 <= ibuf_sz_in; @@ -3943,78 +4209,77 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sz_0 <= 2'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_sz_0 <= ibuf_sz; + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; end else begin - buf_sz_0 <= ibuf_sz_in; + buf_sz_2 <= ibuf_sz_in; end end end - always @(posedge io_lsu_busm_clk or posedge reset) begin + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - obuf_rdrsp_tag <= 3'h0; - end else if (_T_1193) begin - obuf_rdrsp_tag <= obuf_tag0; + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end end end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_rdrsp_pend <= 1'h0; end else begin - obuf_rdrsp_pend <= _T_1191 | _T_1195; + obuf_rdrsp_pend <= _T_1330 | _T_1334; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1336) begin + obuf_rdrsp_tag <= obuf_tag0; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_dualhi_3 <= ibuf_dual; - end else begin - buf_dualhi_3 <= _T_3767; - end + buf_dualhi_3 <= buf_dualhi_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_dualhi_2 <= ibuf_dual; - end else begin - buf_dualhi_2 <= _T_3559; - end + buf_dualhi_2 <= buf_dualhi_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_1 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_dualhi_1 <= ibuf_dual; - end else begin - buf_dualhi_1 <= _T_3351; - end + buf_dualhi_1 <= buf_dualhi_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_0 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_dualhi_0 <= ibuf_dual; - end else begin - buf_dualhi_0 <= _T_3143; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - obuf_data <= 64'h0; - end else if (obuf_wr_en) begin - obuf_data <= obuf_data_in; + buf_dualhi_0 <= buf_dualhi_in[0]; end end always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin @@ -4023,14 +4288,8 @@ end // initial end else if (obuf_wr_en) begin if (ibuf_buf_byp) begin obuf_sz <= ibuf_sz_in; - end else if (2'h3 == CmdPtr0) begin - obuf_sz <= buf_sz_3; - end else if (2'h2 == CmdPtr0) begin - obuf_sz <= buf_sz_2; - end else if (2'h1 == CmdPtr0) begin - obuf_sz <= buf_sz_1; end else begin - obuf_sz <= buf_sz_0; + obuf_sz <= _T_1302; end end end @@ -4041,44 +4300,90 @@ end // initial obuf_byteen <= obuf_byteen_in; end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_1 <= 1'h0; + obuf_data <= 64'h0; end else begin - buf_rspageQ_0_1 <= buf_rspage_set_0_1 | buf_rspage_0_1; + obuf_data <= {_T_1620,_T_1579}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_0 <= 1'h0; + buf_rspageQ_0 <= 4'h0; end else begin - buf_rspageQ_0_0 <= buf_rspage_set_0_0 | buf_rspage_0_0; + buf_rspageQ_0 <= {_T_3173,_T_3162}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_3 <= 1'h0; + buf_rspageQ_1 <= 4'h0; end else begin - buf_rspageQ_0_3 <= buf_rspage_set_0_3 | buf_rspage_0_3; + buf_rspageQ_1 <= {_T_3188,_T_3177}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_2 <= 1'h0; + buf_rspageQ_2 <= 4'h0; end else begin - buf_rspageQ_0_2 <= buf_rspage_set_0_2 | buf_rspage_0_2; + buf_rspageQ_2 <= {_T_3203,_T_3192}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ldfwd_0 <= 1'h0; - end else if (buf_ldfwd_en_0) begin - if (_T_3132) begin - buf_ldfwd_0 <= 1'h0; - end else if (_T_3155) begin - buf_ldfwd_0 <= 1'h0; + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3218,_T_3207}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4307 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + _T_4307 <= 1'h0; + end else if (_T_4130) begin + _T_4307 <= 1'h0; end else begin - buf_ldfwd_0 <= _T_3159; + _T_4307 <= _T_4134; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4305 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + _T_4305 <= 1'h0; + end else if (_T_3937) begin + _T_4305 <= 1'h0; + end else begin + _T_4305 <= _T_3941; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4303 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + _T_4303 <= 1'h0; + end else if (_T_3744) begin + _T_4303 <= 1'h0; + end else begin + _T_4303 <= _T_3748; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4301 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + _T_4301 <= 1'h0; + end else if (_T_3551) begin + _T_4301 <= 1'h0; + end else begin + _T_4301 <= _T_3555; end end end @@ -4086,11 +4391,11 @@ end // initial if (reset) begin buf_ldfwdtag_0 <= 2'h0; end else if (buf_ldfwd_en_0) begin - if (_T_3132) begin + if (_T_3528) begin buf_ldfwdtag_0 <= 2'h0; - end else if (_T_3155) begin + end else if (_T_3551) begin buf_ldfwdtag_0 <= 2'h0; - end else if (_T_3159) begin + end else if (_T_3555) begin buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_0 <= 2'h0; @@ -4101,63 +4406,24 @@ end // initial if (reset) begin buf_dualtag_0 <= 2'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin + if (ibuf_drainvec_vld[0]) begin buf_dualtag_0 <= ibuf_dualtag; - end else if (_T_3143) begin + end else if (_T_3343) begin buf_dualtag_0 <= WrPtr0_r; end else begin buf_dualtag_0 <= WrPtr1_r; end end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_3 <= 1'h0; - end else if (buf_ldfwd_en_3) begin - if (_T_3756) begin - buf_ldfwd_3 <= 1'h0; - end else if (_T_3779) begin - buf_ldfwd_3 <= 1'h0; - end else begin - buf_ldfwd_3 <= _T_3783; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_2 <= 1'h0; - end else if (buf_ldfwd_en_2) begin - if (_T_3548) begin - buf_ldfwd_2 <= 1'h0; - end else if (_T_3571) begin - buf_ldfwd_2 <= 1'h0; - end else begin - buf_ldfwd_2 <= _T_3575; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_1 <= 1'h0; - end else if (buf_ldfwd_en_1) begin - if (_T_3340) begin - buf_ldfwd_1 <= 1'h0; - end else if (_T_3363) begin - buf_ldfwd_1 <= 1'h0; - end else begin - buf_ldfwd_1 <= _T_3367; - end - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_ldfwdtag_3 <= 2'h0; end else if (buf_ldfwd_en_3) begin - if (_T_3756) begin + if (_T_4107) begin buf_ldfwdtag_3 <= 2'h0; - end else if (_T_3779) begin + end else if (_T_4130) begin buf_ldfwdtag_3 <= 2'h0; - end else if (_T_3783) begin + end else if (_T_4134) begin buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_3 <= 2'h0; @@ -4168,11 +4434,11 @@ end // initial if (reset) begin buf_ldfwdtag_2 <= 2'h0; end else if (buf_ldfwd_en_2) begin - if (_T_3548) begin + if (_T_3914) begin buf_ldfwdtag_2 <= 2'h0; - end else if (_T_3571) begin + end else if (_T_3937) begin buf_ldfwdtag_2 <= 2'h0; - end else if (_T_3575) begin + end else if (_T_3941) begin buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_2 <= 2'h0; @@ -4183,108 +4449,24 @@ end // initial if (reset) begin buf_ldfwdtag_1 <= 2'h0; end else if (buf_ldfwd_en_1) begin - if (_T_3340) begin + if (_T_3721) begin buf_ldfwdtag_1 <= 2'h0; - end else if (_T_3363) begin + end else if (_T_3744) begin buf_ldfwdtag_1 <= 2'h0; - end else if (_T_3367) begin + end else if (_T_3748) begin buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_1 <= 2'h0; end end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_3 <= 1'h0; - end else begin - buf_rspageQ_3_3 <= buf_rspage_set_3_3 | buf_rspage_3_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_2 <= 1'h0; - end else begin - buf_rspageQ_3_2 <= buf_rspage_set_3_2 | buf_rspage_3_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_1 <= 1'h0; - end else begin - buf_rspageQ_3_1 <= buf_rspage_set_3_1 | buf_rspage_3_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_0 <= 1'h0; - end else begin - buf_rspageQ_3_0 <= buf_rspage_set_3_0 | buf_rspage_3_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_3 <= 1'h0; - end else begin - buf_rspageQ_2_3 <= buf_rspage_set_2_3 | buf_rspage_2_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_2 <= 1'h0; - end else begin - buf_rspageQ_2_2 <= buf_rspage_set_2_2 | buf_rspage_2_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_1 <= 1'h0; - end else begin - buf_rspageQ_2_1 <= buf_rspage_set_2_1 | buf_rspage_2_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_0 <= 1'h0; - end else begin - buf_rspageQ_2_0 <= buf_rspage_set_2_0 | buf_rspage_2_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_3 <= 1'h0; - end else begin - buf_rspageQ_1_3 <= buf_rspage_set_1_3 | buf_rspage_1_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_2 <= 1'h0; - end else begin - buf_rspageQ_1_2 <= buf_rspage_set_1_2 | buf_rspage_1_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_1 <= 1'h0; - end else begin - buf_rspageQ_1_1 <= buf_rspage_set_1_1 | buf_rspage_1_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_0 <= 1'h0; - end else begin - buf_rspageQ_1_0 <= buf_rspage_set_1_0 | buf_rspage_1_0; - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualtag_1 <= 2'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin + if (ibuf_drainvec_vld[1]) begin buf_dualtag_1 <= ibuf_dualtag; - end else if (_T_3351) begin + end else if (_T_3352) begin buf_dualtag_1 <= WrPtr0_r; end else begin buf_dualtag_1 <= WrPtr1_r; @@ -4295,9 +4477,9 @@ end // initial if (reset) begin buf_dualtag_2 <= 2'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin + if (ibuf_drainvec_vld[2]) begin buf_dualtag_2 <= ibuf_dualtag; - end else if (_T_3559) begin + end else if (_T_3361) begin buf_dualtag_2 <= WrPtr0_r; end else begin buf_dualtag_2 <= WrPtr1_r; @@ -4308,9 +4490,9 @@ end // initial if (reset) begin buf_dualtag_3 <= 2'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin + if (ibuf_drainvec_vld[3]) begin buf_dualtag_3 <= ibuf_dualtag; - end else if (_T_3767) begin + end else if (_T_3370) begin buf_dualtag_3 <= WrPtr0_r; end else begin buf_dualtag_3 <= WrPtr1_r; @@ -4319,74 +4501,58 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_unsign_0 <= 1'h0; + _T_4336 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_unsign_0 <= ibuf_unsign; - end else begin - buf_unsign_0 <= io_lsu_pkt_r_unsign; - end + _T_4336 <= buf_unsign_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_0 <= 1'h0; - end else if (_T_3294) begin - buf_error_0 <= _T_3293; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_1 <= 1'h0; + _T_4339 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_unsign_1 <= ibuf_unsign; - end else begin - buf_unsign_1 <= io_lsu_pkt_r_unsign; - end + _T_4339 <= buf_unsign_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_1 <= 1'h0; - end else if (_T_3502) begin - buf_error_1 <= _T_3501; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_2 <= 1'h0; + _T_4342 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_unsign_2 <= ibuf_unsign; - end else begin - buf_unsign_2 <= io_lsu_pkt_r_unsign; - end + _T_4342 <= buf_unsign_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_2 <= 1'h0; - end else if (_T_3710) begin - buf_error_2 <= _T_3709; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_3 <= 1'h0; + _T_4345 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_unsign_3 <= ibuf_unsign; - end else begin - buf_unsign_3 <= io_lsu_pkt_r_unsign; - end + _T_4345 <= buf_unsign_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_3 <= 1'h0; - end else if (_T_3918) begin - buf_error_3 <= _T_3917; + _T_4411 <= 1'h0; + end else begin + _T_4411 <= _T_4408 & _T_4409; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4403 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4398 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4393 & _T_4394; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -4398,9 +4564,9 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_4338 <= 1'h0; + _T_4988 <= 1'h0; end else begin - _T_4338 <= _T_4335 & _T_4035; + _T_4988 <= _T_4985 & _T_4518; end end endmodule diff --git a/el2_lsu_bus_intf.anno.json b/el2_lsu_bus_intf.anno.json index 49c73215..14c64584 100644 --- a/el2_lsu_bus_intf.anno.json +++ b/el2_lsu_bus_intf.anno.json @@ -6,23 +6,6 @@ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_commit_r" ] }, - { - "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m", - "sources":[ - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half" - ] - }, { "class":"firrtl.transforms.CombinationalPath", "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_nonblock_load_inv_r", @@ -32,16 +15,24 @@ }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn", + "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_bus_read_data_m", "sources":[ - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready" + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_busreq_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_store_data_r", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r" ] }, { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy", + "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_trxn", "sources":[ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready", @@ -58,14 +49,23 @@ "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_valid", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_is_sideeffects_m", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_by", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_store", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_by", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_word", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_m_half", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_valid", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_word", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pkt_r_half", "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r", - "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_m" + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_end_addr_r" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_pmu_bus_busy", + "sources":[ + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_arready", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_awready", + "~el2_lsu_bus_intf|el2_lsu_bus_intf>io_lsu_axi_wready" ] }, { @@ -82,6 +82,11 @@ "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"el2_lsu_bus_intf.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, { "class":"firrtl.options.TargetDirAnnotation", "directory":"." diff --git a/el2_lsu_bus_intf.fir b/el2_lsu_bus_intf.fir index 22f4b059..3f689d76 100644 --- a/el2_lsu_bus_intf.fir +++ b/el2_lsu_bus_intf.fir @@ -1,6233 +1,6514 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_lsu_bus_intf : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_10 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_10 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_10 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + + extmodule gated_latch_11 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_11 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_11 @[el2_lib.scala 474:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] + module el2_lsu_bus_buffer : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_awready : UInt<1>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip dec_tlu_force_halt : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} - wire ldst_byteen_hi_m : UInt<4> - ldst_byteen_hi_m <= UInt<1>("h00") - wire ldst_byteen_lo_m : UInt<4> - ldst_byteen_lo_m <= UInt<1>("h00") - wire ld_addr_hitvec_lo : UInt<4> - ld_addr_hitvec_lo <= UInt<1>("h00") - wire ld_addr_hitvec_hi : UInt<4> - ld_addr_hitvec_hi <= UInt<1>("h00") - wire ld_byte_hitvec_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 138:43] - wire ld_byte_hitvec_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 139:43] - wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 140:43] - wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 141:43] - wire ld_addr_ibuf_hit_lo : UInt<1> - ld_addr_ibuf_hit_lo <= UInt<1>("h00") - wire ld_addr_ibuf_hit_hi : UInt<1> - ld_addr_ibuf_hit_hi <= UInt<1>("h00") - wire ld_byte_ibuf_hit_lo : UInt<4> - ld_byte_ibuf_hit_lo <= UInt<1>("h00") - wire ld_byte_ibuf_hit_hi : UInt<4> - ld_byte_ibuf_hit_hi <= UInt<1>("h00") - wire ldst_byteen_r : UInt<4> - ldst_byteen_r <= UInt<1>("h00") - wire ldst_byteen_hi_r : UInt<4> - ldst_byteen_hi_r <= UInt<1>("h00") - wire ldst_byteen_lo_r : UInt<4> - ldst_byteen_lo_r <= UInt<1>("h00") - wire store_data_hi_r : UInt<32> - store_data_hi_r <= UInt<1>("h00") - wire store_data_lo_r : UInt<32> - store_data_lo_r <= UInt<1>("h00") - wire is_aligned_r : UInt<1> - is_aligned_r <= UInt<1>("h00") - wire ldst_samedw_r : UInt<1> - ldst_samedw_r <= UInt<1>("h00") - wire lsu_nonblock_load_valid_r : UInt<1> - lsu_nonblock_load_valid_r <= UInt<1>("h00") - wire lsu_nonblock_load_data_hi : UInt<32> - lsu_nonblock_load_data_hi <= UInt<1>("h00") - wire lsu_nonblock_load_data_lo : UInt<32> - lsu_nonblock_load_data_lo <= UInt<1>("h00") - wire lsu_nonblock_data_unalgn : UInt<32> - lsu_nonblock_data_unalgn <= UInt<1>("h00") - wire lsu_nonblock_addr_offset : UInt<2> - lsu_nonblock_addr_offset <= UInt<1>("h00") - wire lsu_nonblock_sz : UInt<2> - lsu_nonblock_sz <= UInt<1>("h00") - wire lsu_nonblock_unsign : UInt<1> - lsu_nonblock_unsign <= UInt<1>("h00") - wire lsu_nonblock_dual : UInt<1> - lsu_nonblock_dual <= UInt<1>("h00") - wire lsu_nonblock_load_data_ready : UInt<1> - lsu_nonblock_load_data_ready <= UInt<1>("h00") - wire CmdPtr0Dec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 165:43] - wire CmdPtr1Dec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 166:43] - wire RspPtrDec : UInt<1>[4] @[el2_lsu_bus_buffer.scala 167:43] + wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 121:22] + wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 122:23] + wire buf_write : UInt<4> + buf_write <= UInt<1>("h00") wire CmdPtr0 : UInt<2> CmdPtr0 <= UInt<1>("h00") - wire CmdPtr1 : UInt<2> - CmdPtr1 <= UInt<1>("h00") - wire RspPtr : UInt<2> - RspPtr <= UInt<1>("h00") - wire WrPtr0_m : UInt<2> - WrPtr0_m <= UInt<1>("h00") - wire WrPtr0_r : UInt<2> - WrPtr0_r <= UInt<1>("h00") - wire WrPtr1_m : UInt<2> - WrPtr1_m <= UInt<1>("h00") - wire WrPtr1_r : UInt<2> - WrPtr1_r <= UInt<1>("h00") - wire found_cmdptr0 : UInt<1> - found_cmdptr0 <= UInt<1>("h00") - wire found_cmdptr1 : UInt<1> - found_cmdptr1 <= UInt<1>("h00") - wire buf_numvld_any : UInt<4> - buf_numvld_any <= UInt<1>("h00") - wire buf_numvld_wrcmd_any : UInt<4> - buf_numvld_wrcmd_any <= UInt<1>("h00") - wire buf_numvld_cmd_any : UInt<4> - buf_numvld_cmd_any <= UInt<1>("h00") - wire buf_numvld_pend_any : UInt<4> - buf_numvld_pend_any <= UInt<1>("h00") - wire any_done_wait_state : UInt<1> - any_done_wait_state <= UInt<1>("h00") - wire bus_sideeffect_pend : UInt<1> - bus_sideeffect_pend <= UInt<1>("h00") - wire bus_pend_trxn : UInt<8> - bus_pend_trxn <= UInt<1>("h00") - wire bus_pend_trxnQ : UInt<8> - bus_pend_trxnQ <= UInt<1>("h00") - wire bus_pend_trxn_ns : UInt<8> - bus_pend_trxn_ns <= UInt<1>("h00") - wire lsu_bus_cntr_overflow : UInt<1> - lsu_bus_cntr_overflow <= UInt<1>("h00") - wire bus_coalescing_disable : UInt<1> - bus_coalescing_disable <= UInt<1>("h00") - wire mdbhd_en : UInt<1> - mdbhd_en <= UInt<1>("h00") - wire bus_addr_match_pending : UInt<1> - bus_addr_match_pending <= UInt<1>("h00") - wire bus_cmd_sent : UInt<1> - bus_cmd_sent <= UInt<1>("h00") - wire bus_cmd_ready : UInt<1> - bus_cmd_ready <= UInt<1>("h00") - wire bus_wcmd_sent : UInt<1> - bus_wcmd_sent <= UInt<1>("h00") - wire bus_wdata_sent : UInt<1> - bus_wdata_sent <= UInt<1>("h00") - wire bus_rsp_read : UInt<1> - bus_rsp_read <= UInt<1>("h00") - wire bus_rsp_write : UInt<1> - bus_rsp_write <= UInt<1>("h00") - wire bus_rsp_read_tag : UInt<3> - bus_rsp_read_tag <= UInt<1>("h00") - wire bus_rsp_write_tag : UInt<3> - bus_rsp_write_tag <= UInt<1>("h00") + node ldst_byteen_hi_m = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 127:46] + node ldst_byteen_lo_m = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 128:46] + node _T = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_1 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_2 = eq(_T, _T_1) @[el2_lsu_bus_buffer.scala 130:74] + node _T_3 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 130:109] + node _T_4 = and(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 130:98] + node _T_5 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_6 = and(_T_4, _T_5) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_0 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_7 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_8 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_9 = eq(_T_7, _T_8) @[el2_lsu_bus_buffer.scala 130:74] + node _T_10 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 130:109] + node _T_11 = and(_T_9, _T_10) @[el2_lsu_bus_buffer.scala 130:98] + node _T_12 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_13 = and(_T_11, _T_12) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_1 = and(_T_13, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_14 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_15 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_16 = eq(_T_14, _T_15) @[el2_lsu_bus_buffer.scala 130:74] + node _T_17 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 130:109] + node _T_18 = and(_T_16, _T_17) @[el2_lsu_bus_buffer.scala 130:98] + node _T_19 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_20 = and(_T_18, _T_19) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_2 = and(_T_20, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_21 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 130:66] + node _T_22 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 130:89] + node _T_23 = eq(_T_21, _T_22) @[el2_lsu_bus_buffer.scala 130:74] + node _T_24 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 130:109] + node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 130:98] + node _T_26 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 130:129] + node _T_27 = and(_T_25, _T_26) @[el2_lsu_bus_buffer.scala 130:113] + node ld_addr_hitvec_lo_3 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 130:141] + node _T_28 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_29 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_30 = eq(_T_28, _T_29) @[el2_lsu_bus_buffer.scala 131:74] + node _T_31 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 131:109] + node _T_32 = and(_T_30, _T_31) @[el2_lsu_bus_buffer.scala 131:98] + node _T_33 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_34 = and(_T_32, _T_33) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_0 = and(_T_34, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_35 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_36 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_37 = eq(_T_35, _T_36) @[el2_lsu_bus_buffer.scala 131:74] + node _T_38 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 131:109] + node _T_39 = and(_T_37, _T_38) @[el2_lsu_bus_buffer.scala 131:98] + node _T_40 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_41 = and(_T_39, _T_40) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_1 = and(_T_41, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_42 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_43 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_44 = eq(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 131:74] + node _T_45 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 131:109] + node _T_46 = and(_T_44, _T_45) @[el2_lsu_bus_buffer.scala 131:98] + node _T_47 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_2 = and(_T_48, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + node _T_49 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 131:66] + node _T_50 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 131:89] + node _T_51 = eq(_T_49, _T_50) @[el2_lsu_bus_buffer.scala 131:74] + node _T_52 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 131:109] + node _T_53 = and(_T_51, _T_52) @[el2_lsu_bus_buffer.scala 131:98] + node _T_54 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 131:129] + node _T_55 = and(_T_53, _T_54) @[el2_lsu_bus_buffer.scala 131:113] + node ld_addr_hitvec_hi_3 = and(_T_55, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 131:141] + wire ld_byte_hitvecfn_lo : UInt<4>[4] @[el2_lsu_bus_buffer.scala 132:33] + wire ld_byte_ibuf_hit_lo : UInt<4> + ld_byte_ibuf_hit_lo <= UInt<1>("h00") + wire ld_byte_hitvecfn_hi : UInt<4>[4] @[el2_lsu_bus_buffer.scala 134:33] + wire ld_byte_ibuf_hit_hi : UInt<4> + ld_byte_ibuf_hit_hi <= UInt<1>("h00") + wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 136:24] + buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 137:14] + wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 138:26] + buf_nxtstate[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + buf_nxtstate[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 139:16] + wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 140:23] + buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 141:13] + wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 142:25] + buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 143:15] + wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 144:30] + buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 145:20] + wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 146:26] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 147:16] + wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 148:26] + buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 149:16] + wire buf_data_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 150:25] + buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 151:15] + wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 152:29] + buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 153:19] + wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 154:26] + buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] + buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 155:16] wire bus_rsp_read_error : UInt<1> bus_rsp_read_error <= UInt<1>("h00") - wire bus_rsp_write_error : UInt<1> - bus_rsp_write_error <= UInt<1>("h00") wire bus_rsp_rdata : UInt<64> bus_rsp_rdata <= UInt<1>("h00") - wire buf_state : UInt<3>[4] @[el2_lsu_bus_buffer.scala 204:43] - wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 205:43] - wire buf_addr : UInt<32>[4] @[el2_lsu_bus_buffer.scala 206:43] - wire buf_byteen : UInt<4>[4] @[el2_lsu_bus_buffer.scala 207:43] - wire buf_sideeffect : UInt<1>[4] @[el2_lsu_bus_buffer.scala 208:43] - wire buf_write : UInt<1>[4] @[el2_lsu_bus_buffer.scala 209:43] - wire buf_unsign : UInt<1>[4] @[el2_lsu_bus_buffer.scala 210:43] - wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 211:43] - wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 212:43] - wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 213:43] - wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 214:43] - wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 215:43] - wire buf_ldfwd : UInt<1>[4] @[el2_lsu_bus_buffer.scala 216:43] - wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 217:43] - wire buf_error : UInt<1>[4] @[el2_lsu_bus_buffer.scala 218:43] - wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 219:43] - wire buf_age : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 220:43] - wire buf_age_younger : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 221:43] - wire buf_rspage : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 222:43] - wire buf_rsp_pickage : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 223:43] - wire buf_nxtstate : UInt<3>[4] @[el2_lsu_bus_buffer.scala 225:43] - wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 226:43] - wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 227:43] - wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 228:43] - wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 229:43] - wire buf_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 230:43] - wire buf_dual_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 231:43] - wire buf_samedw_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 232:43] - wire buf_nomerge_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 233:43] - wire buf_sideeffect_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 234:43] - wire buf_unsign_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 235:43] - wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 236:43] - wire buf_write_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 237:43] - wire buf_wr_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 238:43] - wire buf_dualhi_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 239:43] - wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 240:43] - wire buf_ldfwd_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 241:43] - wire buf_ldfwd_in : UInt<1>[4] @[el2_lsu_bus_buffer.scala 242:43] - wire buf_ldfwdtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 243:43] - wire buf_byteen_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 244:43] - wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 245:43] - wire buf_data_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 246:43] - wire buf_error_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 247:43] - wire buf_data_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 248:43] - wire buf_age_in : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 249:43] - wire buf_ageQ : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 250:43] - wire buf_rspage_set : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 251:43] - wire buf_rspage_in : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 252:43] - wire buf_rspageQ : UInt<1>[4][4] @[el2_lsu_bus_buffer.scala 253:43] - wire ibuf_valid : UInt<1> - ibuf_valid <= UInt<1>("h00") - wire ibuf_dual : UInt<1> - ibuf_dual <= UInt<1>("h00") - wire ibuf_samedw : UInt<1> - ibuf_samedw <= UInt<1>("h00") - wire ibuf_nomerge : UInt<1> - ibuf_nomerge <= UInt<1>("h00") - wire ibuf_tag : UInt<2> - ibuf_tag <= UInt<1>("h00") - wire ibuf_dualtag : UInt<2> - ibuf_dualtag <= UInt<1>("h00") - wire ibuf_sideeffect : UInt<1> - ibuf_sideeffect <= UInt<1>("h00") - wire ibuf_unsign : UInt<1> - ibuf_unsign <= UInt<1>("h00") - wire ibuf_write : UInt<1> - ibuf_write <= UInt<1>("h00") - wire ibuf_sz : UInt<2> - ibuf_sz <= UInt<1>("h00") - wire ibuf_byteen : UInt<4> - ibuf_byteen <= UInt<1>("h00") - wire ibuf_addr : UInt<32> - ibuf_addr <= UInt<1>("h00") + wire bus_rsp_write_error : UInt<1> + bus_rsp_write_error <= UInt<1>("h00") + wire buf_dualtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 159:25] + buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 160:15] + wire buf_ldfwd : UInt<4> + buf_ldfwd <= UInt<1>("h00") + wire buf_resp_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 162:35] + buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 163:25] + wire any_done_wait_state : UInt<1> + any_done_wait_state <= UInt<1>("h00") + wire bus_rsp_write : UInt<1> + bus_rsp_write <= UInt<1>("h00") + wire bus_rsp_write_tag : UInt<3> + bus_rsp_write_tag <= UInt<1>("h00") + wire buf_ldfwdtag : UInt<2>[4] @[el2_lsu_bus_buffer.scala 167:26] + buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 168:16] + wire buf_rst : UInt<1>[4] @[el2_lsu_bus_buffer.scala 169:21] + buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 170:11] + wire ibuf_drainvec_vld : UInt<4> + ibuf_drainvec_vld <= UInt<1>("h00") + wire buf_byteen_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 172:27] + buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 173:17] + wire buf_addr_in : UInt<32>[4] @[el2_lsu_bus_buffer.scala 174:25] + buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 175:15] + wire buf_dual_in : UInt<4> + buf_dual_in <= UInt<1>("h00") + wire buf_samedw_in : UInt<4> + buf_samedw_in <= UInt<1>("h00") + wire buf_nomerge_in : UInt<4> + buf_nomerge_in <= UInt<1>("h00") + wire buf_dualhi_in : UInt<4> + buf_dualhi_in <= UInt<1>("h00") + wire buf_dualtag_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 180:28] + buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 181:18] + wire buf_sideeffect_in : UInt<4> + buf_sideeffect_in <= UInt<1>("h00") + wire buf_unsign_in : UInt<4> + buf_unsign_in <= UInt<1>("h00") + wire buf_sz_in : UInt<2>[4] @[el2_lsu_bus_buffer.scala 184:23] + buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 185:13] + wire buf_write_in : UInt<4> + buf_write_in <= UInt<1>("h00") + wire buf_unsign : UInt<4> + buf_unsign <= UInt<1>("h00") + wire buf_error : UInt<4> + buf_error <= UInt<1>("h00") wire ibuf_data : UInt<32> ibuf_data <= UInt<1>("h00") - wire ibuf_timer : UInt<3> - ibuf_timer <= UInt<1>("h00") - wire ibuf_byp : UInt<1> - ibuf_byp <= UInt<1>("h00") - wire ibuf_wr_en : UInt<1> - ibuf_wr_en <= UInt<1>("h00") - wire ibuf_rst : UInt<1> - ibuf_rst <= UInt<1>("h00") - wire ibuf_force_drain : UInt<1> - ibuf_force_drain <= UInt<1>("h00") + node _T_56 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_57 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 191:98] + node _T_58 = or(_T_56, _T_57) @[el2_lsu_bus_buffer.scala 191:77] + node _T_59 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_60 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 191:98] + node _T_61 = or(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 191:77] + node _T_62 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_63 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 191:98] + node _T_64 = or(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 191:77] + node _T_65 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 191:73] + node _T_66 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 191:98] + node _T_67 = or(_T_65, _T_66) @[el2_lsu_bus_buffer.scala 191:77] + node _T_68 = cat(_T_67, _T_64) @[Cat.scala 29:58] + node _T_69 = cat(_T_68, _T_61) @[Cat.scala 29:58] + node _T_70 = cat(_T_69, _T_58) @[Cat.scala 29:58] + io.ld_byte_hit_buf_lo <= _T_70 @[el2_lsu_bus_buffer.scala 191:25] + node _T_71 = orr(ld_byte_hitvecfn_hi[0]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_72 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 192:98] + node _T_73 = or(_T_71, _T_72) @[el2_lsu_bus_buffer.scala 192:77] + node _T_74 = orr(ld_byte_hitvecfn_hi[1]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_75 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 192:98] + node _T_76 = or(_T_74, _T_75) @[el2_lsu_bus_buffer.scala 192:77] + node _T_77 = orr(ld_byte_hitvecfn_hi[2]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_78 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 192:98] + node _T_79 = or(_T_77, _T_78) @[el2_lsu_bus_buffer.scala 192:77] + node _T_80 = orr(ld_byte_hitvecfn_hi[3]) @[el2_lsu_bus_buffer.scala 192:73] + node _T_81 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 192:98] + node _T_82 = or(_T_80, _T_81) @[el2_lsu_bus_buffer.scala 192:77] + node _T_83 = cat(_T_82, _T_79) @[Cat.scala 29:58] + node _T_84 = cat(_T_83, _T_76) @[Cat.scala 29:58] + node _T_85 = cat(_T_84, _T_73) @[Cat.scala 29:58] + io.ld_byte_hit_buf_hi <= _T_85 @[el2_lsu_bus_buffer.scala 192:25] + node _T_86 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_87 = and(ld_addr_hitvec_lo_0, _T_86) @[el2_lsu_bus_buffer.scala 194:95] + node _T_88 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_89 = and(_T_87, _T_88) @[el2_lsu_bus_buffer.scala 194:114] + node _T_90 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_91 = and(ld_addr_hitvec_lo_1, _T_90) @[el2_lsu_bus_buffer.scala 194:95] + node _T_92 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_93 = and(_T_91, _T_92) @[el2_lsu_bus_buffer.scala 194:114] + node _T_94 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_95 = and(ld_addr_hitvec_lo_2, _T_94) @[el2_lsu_bus_buffer.scala 194:95] + node _T_96 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_buffer.scala 194:114] + node _T_98 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 194:110] + node _T_99 = and(ld_addr_hitvec_lo_3, _T_98) @[el2_lsu_bus_buffer.scala 194:95] + node _T_100 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 194:132] + node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_buffer.scala 194:114] + node _T_102 = cat(_T_101, _T_97) @[Cat.scala 29:58] + node _T_103 = cat(_T_102, _T_93) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_0 = cat(_T_103, _T_89) @[Cat.scala 29:58] + node _T_104 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_105 = and(ld_addr_hitvec_lo_0, _T_104) @[el2_lsu_bus_buffer.scala 194:95] + node _T_106 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_107 = and(_T_105, _T_106) @[el2_lsu_bus_buffer.scala 194:114] + node _T_108 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_109 = and(ld_addr_hitvec_lo_1, _T_108) @[el2_lsu_bus_buffer.scala 194:95] + node _T_110 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_111 = and(_T_109, _T_110) @[el2_lsu_bus_buffer.scala 194:114] + node _T_112 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_113 = and(ld_addr_hitvec_lo_2, _T_112) @[el2_lsu_bus_buffer.scala 194:95] + node _T_114 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_115 = and(_T_113, _T_114) @[el2_lsu_bus_buffer.scala 194:114] + node _T_116 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 194:110] + node _T_117 = and(ld_addr_hitvec_lo_3, _T_116) @[el2_lsu_bus_buffer.scala 194:95] + node _T_118 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 194:132] + node _T_119 = and(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 194:114] + node _T_120 = cat(_T_119, _T_115) @[Cat.scala 29:58] + node _T_121 = cat(_T_120, _T_111) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_1 = cat(_T_121, _T_107) @[Cat.scala 29:58] + node _T_122 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_123 = and(ld_addr_hitvec_lo_0, _T_122) @[el2_lsu_bus_buffer.scala 194:95] + node _T_124 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 194:114] + node _T_126 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_127 = and(ld_addr_hitvec_lo_1, _T_126) @[el2_lsu_bus_buffer.scala 194:95] + node _T_128 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_129 = and(_T_127, _T_128) @[el2_lsu_bus_buffer.scala 194:114] + node _T_130 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_131 = and(ld_addr_hitvec_lo_2, _T_130) @[el2_lsu_bus_buffer.scala 194:95] + node _T_132 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_133 = and(_T_131, _T_132) @[el2_lsu_bus_buffer.scala 194:114] + node _T_134 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 194:110] + node _T_135 = and(ld_addr_hitvec_lo_3, _T_134) @[el2_lsu_bus_buffer.scala 194:95] + node _T_136 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 194:132] + node _T_137 = and(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 194:114] + node _T_138 = cat(_T_137, _T_133) @[Cat.scala 29:58] + node _T_139 = cat(_T_138, _T_129) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_2 = cat(_T_139, _T_125) @[Cat.scala 29:58] + node _T_140 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_141 = and(ld_addr_hitvec_lo_0, _T_140) @[el2_lsu_bus_buffer.scala 194:95] + node _T_142 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_buffer.scala 194:114] + node _T_144 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_145 = and(ld_addr_hitvec_lo_1, _T_144) @[el2_lsu_bus_buffer.scala 194:95] + node _T_146 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_buffer.scala 194:114] + node _T_148 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_149 = and(ld_addr_hitvec_lo_2, _T_148) @[el2_lsu_bus_buffer.scala 194:95] + node _T_150 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 194:114] + node _T_152 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 194:110] + node _T_153 = and(ld_addr_hitvec_lo_3, _T_152) @[el2_lsu_bus_buffer.scala 194:95] + node _T_154 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 194:132] + node _T_155 = and(_T_153, _T_154) @[el2_lsu_bus_buffer.scala 194:114] + node _T_156 = cat(_T_155, _T_151) @[Cat.scala 29:58] + node _T_157 = cat(_T_156, _T_147) @[Cat.scala 29:58] + node ld_byte_hitvec_lo_3 = cat(_T_157, _T_143) @[Cat.scala 29:58] + node _T_158 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_159 = and(ld_addr_hitvec_hi_0, _T_158) @[el2_lsu_bus_buffer.scala 195:95] + node _T_160 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 195:114] + node _T_162 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_163 = and(ld_addr_hitvec_hi_1, _T_162) @[el2_lsu_bus_buffer.scala 195:95] + node _T_164 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_165 = and(_T_163, _T_164) @[el2_lsu_bus_buffer.scala 195:114] + node _T_166 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_167 = and(ld_addr_hitvec_hi_2, _T_166) @[el2_lsu_bus_buffer.scala 195:95] + node _T_168 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 195:114] + node _T_170 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 195:110] + node _T_171 = and(ld_addr_hitvec_hi_3, _T_170) @[el2_lsu_bus_buffer.scala 195:95] + node _T_172 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 195:132] + node _T_173 = and(_T_171, _T_172) @[el2_lsu_bus_buffer.scala 195:114] + node _T_174 = cat(_T_173, _T_169) @[Cat.scala 29:58] + node _T_175 = cat(_T_174, _T_165) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_0 = cat(_T_175, _T_161) @[Cat.scala 29:58] + node _T_176 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_177 = and(ld_addr_hitvec_hi_0, _T_176) @[el2_lsu_bus_buffer.scala 195:95] + node _T_178 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 195:114] + node _T_180 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_181 = and(ld_addr_hitvec_hi_1, _T_180) @[el2_lsu_bus_buffer.scala 195:95] + node _T_182 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_183 = and(_T_181, _T_182) @[el2_lsu_bus_buffer.scala 195:114] + node _T_184 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_185 = and(ld_addr_hitvec_hi_2, _T_184) @[el2_lsu_bus_buffer.scala 195:95] + node _T_186 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_187 = and(_T_185, _T_186) @[el2_lsu_bus_buffer.scala 195:114] + node _T_188 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 195:110] + node _T_189 = and(ld_addr_hitvec_hi_3, _T_188) @[el2_lsu_bus_buffer.scala 195:95] + node _T_190 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 195:132] + node _T_191 = and(_T_189, _T_190) @[el2_lsu_bus_buffer.scala 195:114] + node _T_192 = cat(_T_191, _T_187) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_183) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_1 = cat(_T_193, _T_179) @[Cat.scala 29:58] + node _T_194 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_195 = and(ld_addr_hitvec_hi_0, _T_194) @[el2_lsu_bus_buffer.scala 195:95] + node _T_196 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 195:114] + node _T_198 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_199 = and(ld_addr_hitvec_hi_1, _T_198) @[el2_lsu_bus_buffer.scala 195:95] + node _T_200 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_201 = and(_T_199, _T_200) @[el2_lsu_bus_buffer.scala 195:114] + node _T_202 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_203 = and(ld_addr_hitvec_hi_2, _T_202) @[el2_lsu_bus_buffer.scala 195:95] + node _T_204 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_205 = and(_T_203, _T_204) @[el2_lsu_bus_buffer.scala 195:114] + node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 195:110] + node _T_207 = and(ld_addr_hitvec_hi_3, _T_206) @[el2_lsu_bus_buffer.scala 195:95] + node _T_208 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 195:132] + node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 195:114] + node _T_210 = cat(_T_209, _T_205) @[Cat.scala 29:58] + node _T_211 = cat(_T_210, _T_201) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_2 = cat(_T_211, _T_197) @[Cat.scala 29:58] + node _T_212 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_213 = and(ld_addr_hitvec_hi_0, _T_212) @[el2_lsu_bus_buffer.scala 195:95] + node _T_214 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 195:114] + node _T_216 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_217 = and(ld_addr_hitvec_hi_1, _T_216) @[el2_lsu_bus_buffer.scala 195:95] + node _T_218 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_219 = and(_T_217, _T_218) @[el2_lsu_bus_buffer.scala 195:114] + node _T_220 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_221 = and(ld_addr_hitvec_hi_2, _T_220) @[el2_lsu_bus_buffer.scala 195:95] + node _T_222 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_223 = and(_T_221, _T_222) @[el2_lsu_bus_buffer.scala 195:114] + node _T_224 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 195:110] + node _T_225 = and(ld_addr_hitvec_hi_3, _T_224) @[el2_lsu_bus_buffer.scala 195:95] + node _T_226 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 195:132] + node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 195:114] + node _T_228 = cat(_T_227, _T_223) @[Cat.scala 29:58] + node _T_229 = cat(_T_228, _T_219) @[Cat.scala 29:58] + node ld_byte_hitvec_hi_3 = cat(_T_229, _T_215) @[Cat.scala 29:58] + wire buf_age_younger : UInt<4>[4] @[el2_lsu_bus_buffer.scala 197:29] + buf_age_younger[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + buf_age_younger[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 198:19] + node _T_230 = bits(ld_byte_hitvec_lo_0, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_231 = and(ld_byte_hitvec_lo_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_232 = orr(_T_231) @[el2_lsu_bus_buffer.scala 199:144] + node _T_233 = eq(_T_232, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_234 = and(_T_230, _T_233) @[el2_lsu_bus_buffer.scala 199:97] + node _T_235 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_236 = eq(_T_235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_237 = and(_T_234, _T_236) @[el2_lsu_bus_buffer.scala 199:148] + node _T_238 = bits(ld_byte_hitvec_lo_0, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_239 = and(ld_byte_hitvec_lo_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_240 = orr(_T_239) @[el2_lsu_bus_buffer.scala 199:144] + node _T_241 = eq(_T_240, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_242 = and(_T_238, _T_241) @[el2_lsu_bus_buffer.scala 199:97] + node _T_243 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_244 = eq(_T_243, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_245 = and(_T_242, _T_244) @[el2_lsu_bus_buffer.scala 199:148] + node _T_246 = bits(ld_byte_hitvec_lo_0, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_247 = and(ld_byte_hitvec_lo_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_248 = orr(_T_247) @[el2_lsu_bus_buffer.scala 199:144] + node _T_249 = eq(_T_248, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_250 = and(_T_246, _T_249) @[el2_lsu_bus_buffer.scala 199:97] + node _T_251 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_252 = eq(_T_251, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_253 = and(_T_250, _T_252) @[el2_lsu_bus_buffer.scala 199:148] + node _T_254 = bits(ld_byte_hitvec_lo_0, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_255 = and(ld_byte_hitvec_lo_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_256 = orr(_T_255) @[el2_lsu_bus_buffer.scala 199:144] + node _T_257 = eq(_T_256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_258 = and(_T_254, _T_257) @[el2_lsu_bus_buffer.scala 199:97] + node _T_259 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 199:170] + node _T_260 = eq(_T_259, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_261 = and(_T_258, _T_260) @[el2_lsu_bus_buffer.scala 199:148] + node _T_262 = cat(_T_261, _T_253) @[Cat.scala 29:58] + node _T_263 = cat(_T_262, _T_245) @[Cat.scala 29:58] + node _T_264 = cat(_T_263, _T_237) @[Cat.scala 29:58] + node _T_265 = bits(ld_byte_hitvec_lo_1, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_266 = and(ld_byte_hitvec_lo_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_267 = orr(_T_266) @[el2_lsu_bus_buffer.scala 199:144] + node _T_268 = eq(_T_267, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_269 = and(_T_265, _T_268) @[el2_lsu_bus_buffer.scala 199:97] + node _T_270 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_271 = eq(_T_270, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_272 = and(_T_269, _T_271) @[el2_lsu_bus_buffer.scala 199:148] + node _T_273 = bits(ld_byte_hitvec_lo_1, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_274 = and(ld_byte_hitvec_lo_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_275 = orr(_T_274) @[el2_lsu_bus_buffer.scala 199:144] + node _T_276 = eq(_T_275, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_277 = and(_T_273, _T_276) @[el2_lsu_bus_buffer.scala 199:97] + node _T_278 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_279 = eq(_T_278, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_280 = and(_T_277, _T_279) @[el2_lsu_bus_buffer.scala 199:148] + node _T_281 = bits(ld_byte_hitvec_lo_1, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_282 = and(ld_byte_hitvec_lo_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_283 = orr(_T_282) @[el2_lsu_bus_buffer.scala 199:144] + node _T_284 = eq(_T_283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_285 = and(_T_281, _T_284) @[el2_lsu_bus_buffer.scala 199:97] + node _T_286 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_287 = eq(_T_286, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_288 = and(_T_285, _T_287) @[el2_lsu_bus_buffer.scala 199:148] + node _T_289 = bits(ld_byte_hitvec_lo_1, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_290 = and(ld_byte_hitvec_lo_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_291 = orr(_T_290) @[el2_lsu_bus_buffer.scala 199:144] + node _T_292 = eq(_T_291, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_293 = and(_T_289, _T_292) @[el2_lsu_bus_buffer.scala 199:97] + node _T_294 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 199:170] + node _T_295 = eq(_T_294, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_296 = and(_T_293, _T_295) @[el2_lsu_bus_buffer.scala 199:148] + node _T_297 = cat(_T_296, _T_288) @[Cat.scala 29:58] + node _T_298 = cat(_T_297, _T_280) @[Cat.scala 29:58] + node _T_299 = cat(_T_298, _T_272) @[Cat.scala 29:58] + node _T_300 = bits(ld_byte_hitvec_lo_2, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_301 = and(ld_byte_hitvec_lo_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_302 = orr(_T_301) @[el2_lsu_bus_buffer.scala 199:144] + node _T_303 = eq(_T_302, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_304 = and(_T_300, _T_303) @[el2_lsu_bus_buffer.scala 199:97] + node _T_305 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_306 = eq(_T_305, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_307 = and(_T_304, _T_306) @[el2_lsu_bus_buffer.scala 199:148] + node _T_308 = bits(ld_byte_hitvec_lo_2, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_309 = and(ld_byte_hitvec_lo_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_310 = orr(_T_309) @[el2_lsu_bus_buffer.scala 199:144] + node _T_311 = eq(_T_310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_312 = and(_T_308, _T_311) @[el2_lsu_bus_buffer.scala 199:97] + node _T_313 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_314 = eq(_T_313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_315 = and(_T_312, _T_314) @[el2_lsu_bus_buffer.scala 199:148] + node _T_316 = bits(ld_byte_hitvec_lo_2, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_317 = and(ld_byte_hitvec_lo_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_318 = orr(_T_317) @[el2_lsu_bus_buffer.scala 199:144] + node _T_319 = eq(_T_318, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_320 = and(_T_316, _T_319) @[el2_lsu_bus_buffer.scala 199:97] + node _T_321 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_322 = eq(_T_321, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_323 = and(_T_320, _T_322) @[el2_lsu_bus_buffer.scala 199:148] + node _T_324 = bits(ld_byte_hitvec_lo_2, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_325 = and(ld_byte_hitvec_lo_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_326 = orr(_T_325) @[el2_lsu_bus_buffer.scala 199:144] + node _T_327 = eq(_T_326, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_328 = and(_T_324, _T_327) @[el2_lsu_bus_buffer.scala 199:97] + node _T_329 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 199:170] + node _T_330 = eq(_T_329, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_331 = and(_T_328, _T_330) @[el2_lsu_bus_buffer.scala 199:148] + node _T_332 = cat(_T_331, _T_323) @[Cat.scala 29:58] + node _T_333 = cat(_T_332, _T_315) @[Cat.scala 29:58] + node _T_334 = cat(_T_333, _T_307) @[Cat.scala 29:58] + node _T_335 = bits(ld_byte_hitvec_lo_3, 0, 0) @[el2_lsu_bus_buffer.scala 199:93] + node _T_336 = and(ld_byte_hitvec_lo_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_337 = orr(_T_336) @[el2_lsu_bus_buffer.scala 199:144] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_339 = and(_T_335, _T_338) @[el2_lsu_bus_buffer.scala 199:97] + node _T_340 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_341 = eq(_T_340, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_342 = and(_T_339, _T_341) @[el2_lsu_bus_buffer.scala 199:148] + node _T_343 = bits(ld_byte_hitvec_lo_3, 1, 1) @[el2_lsu_bus_buffer.scala 199:93] + node _T_344 = and(ld_byte_hitvec_lo_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_345 = orr(_T_344) @[el2_lsu_bus_buffer.scala 199:144] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_347 = and(_T_343, _T_346) @[el2_lsu_bus_buffer.scala 199:97] + node _T_348 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_349 = eq(_T_348, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_350 = and(_T_347, _T_349) @[el2_lsu_bus_buffer.scala 199:148] + node _T_351 = bits(ld_byte_hitvec_lo_3, 2, 2) @[el2_lsu_bus_buffer.scala 199:93] + node _T_352 = and(ld_byte_hitvec_lo_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_353 = orr(_T_352) @[el2_lsu_bus_buffer.scala 199:144] + node _T_354 = eq(_T_353, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_355 = and(_T_351, _T_354) @[el2_lsu_bus_buffer.scala 199:97] + node _T_356 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_358 = and(_T_355, _T_357) @[el2_lsu_bus_buffer.scala 199:148] + node _T_359 = bits(ld_byte_hitvec_lo_3, 3, 3) @[el2_lsu_bus_buffer.scala 199:93] + node _T_360 = and(ld_byte_hitvec_lo_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 199:122] + node _T_361 = orr(_T_360) @[el2_lsu_bus_buffer.scala 199:144] + node _T_362 = eq(_T_361, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:99] + node _T_363 = and(_T_359, _T_362) @[el2_lsu_bus_buffer.scala 199:97] + node _T_364 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 199:170] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 199:150] + node _T_366 = and(_T_363, _T_365) @[el2_lsu_bus_buffer.scala 199:148] + node _T_367 = cat(_T_366, _T_358) @[Cat.scala 29:58] + node _T_368 = cat(_T_367, _T_350) @[Cat.scala 29:58] + node _T_369 = cat(_T_368, _T_342) @[Cat.scala 29:58] + ld_byte_hitvecfn_lo[0] <= _T_264 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[1] <= _T_299 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[2] <= _T_334 @[el2_lsu_bus_buffer.scala 199:23] + ld_byte_hitvecfn_lo[3] <= _T_369 @[el2_lsu_bus_buffer.scala 199:23] + node _T_370 = bits(ld_byte_hitvec_hi_0, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_371 = and(ld_byte_hitvec_hi_0, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_372 = orr(_T_371) @[el2_lsu_bus_buffer.scala 200:144] + node _T_373 = eq(_T_372, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_374 = and(_T_370, _T_373) @[el2_lsu_bus_buffer.scala 200:97] + node _T_375 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_376 = eq(_T_375, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_377 = and(_T_374, _T_376) @[el2_lsu_bus_buffer.scala 200:148] + node _T_378 = bits(ld_byte_hitvec_hi_0, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_379 = and(ld_byte_hitvec_hi_0, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 200:144] + node _T_381 = eq(_T_380, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_382 = and(_T_378, _T_381) @[el2_lsu_bus_buffer.scala 200:97] + node _T_383 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_384 = eq(_T_383, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 200:148] + node _T_386 = bits(ld_byte_hitvec_hi_0, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_387 = and(ld_byte_hitvec_hi_0, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_388 = orr(_T_387) @[el2_lsu_bus_buffer.scala 200:144] + node _T_389 = eq(_T_388, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_390 = and(_T_386, _T_389) @[el2_lsu_bus_buffer.scala 200:97] + node _T_391 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_392 = eq(_T_391, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_393 = and(_T_390, _T_392) @[el2_lsu_bus_buffer.scala 200:148] + node _T_394 = bits(ld_byte_hitvec_hi_0, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_395 = and(ld_byte_hitvec_hi_0, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_396 = orr(_T_395) @[el2_lsu_bus_buffer.scala 200:144] + node _T_397 = eq(_T_396, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_398 = and(_T_394, _T_397) @[el2_lsu_bus_buffer.scala 200:97] + node _T_399 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 200:170] + node _T_400 = eq(_T_399, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_401 = and(_T_398, _T_400) @[el2_lsu_bus_buffer.scala 200:148] + node _T_402 = cat(_T_401, _T_393) @[Cat.scala 29:58] + node _T_403 = cat(_T_402, _T_385) @[Cat.scala 29:58] + node _T_404 = cat(_T_403, _T_377) @[Cat.scala 29:58] + node _T_405 = bits(ld_byte_hitvec_hi_1, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_406 = and(ld_byte_hitvec_hi_1, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_407 = orr(_T_406) @[el2_lsu_bus_buffer.scala 200:144] + node _T_408 = eq(_T_407, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_409 = and(_T_405, _T_408) @[el2_lsu_bus_buffer.scala 200:97] + node _T_410 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_411 = eq(_T_410, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_412 = and(_T_409, _T_411) @[el2_lsu_bus_buffer.scala 200:148] + node _T_413 = bits(ld_byte_hitvec_hi_1, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_414 = and(ld_byte_hitvec_hi_1, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_415 = orr(_T_414) @[el2_lsu_bus_buffer.scala 200:144] + node _T_416 = eq(_T_415, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_417 = and(_T_413, _T_416) @[el2_lsu_bus_buffer.scala 200:97] + node _T_418 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_419 = eq(_T_418, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_420 = and(_T_417, _T_419) @[el2_lsu_bus_buffer.scala 200:148] + node _T_421 = bits(ld_byte_hitvec_hi_1, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_422 = and(ld_byte_hitvec_hi_1, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_423 = orr(_T_422) @[el2_lsu_bus_buffer.scala 200:144] + node _T_424 = eq(_T_423, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_425 = and(_T_421, _T_424) @[el2_lsu_bus_buffer.scala 200:97] + node _T_426 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_427 = eq(_T_426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_428 = and(_T_425, _T_427) @[el2_lsu_bus_buffer.scala 200:148] + node _T_429 = bits(ld_byte_hitvec_hi_1, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_430 = and(ld_byte_hitvec_hi_1, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_431 = orr(_T_430) @[el2_lsu_bus_buffer.scala 200:144] + node _T_432 = eq(_T_431, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_433 = and(_T_429, _T_432) @[el2_lsu_bus_buffer.scala 200:97] + node _T_434 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 200:170] + node _T_435 = eq(_T_434, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_436 = and(_T_433, _T_435) @[el2_lsu_bus_buffer.scala 200:148] + node _T_437 = cat(_T_436, _T_428) @[Cat.scala 29:58] + node _T_438 = cat(_T_437, _T_420) @[Cat.scala 29:58] + node _T_439 = cat(_T_438, _T_412) @[Cat.scala 29:58] + node _T_440 = bits(ld_byte_hitvec_hi_2, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_441 = and(ld_byte_hitvec_hi_2, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_442 = orr(_T_441) @[el2_lsu_bus_buffer.scala 200:144] + node _T_443 = eq(_T_442, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_444 = and(_T_440, _T_443) @[el2_lsu_bus_buffer.scala 200:97] + node _T_445 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_446 = eq(_T_445, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_447 = and(_T_444, _T_446) @[el2_lsu_bus_buffer.scala 200:148] + node _T_448 = bits(ld_byte_hitvec_hi_2, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_449 = and(ld_byte_hitvec_hi_2, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_450 = orr(_T_449) @[el2_lsu_bus_buffer.scala 200:144] + node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_452 = and(_T_448, _T_451) @[el2_lsu_bus_buffer.scala 200:97] + node _T_453 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_454 = eq(_T_453, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_455 = and(_T_452, _T_454) @[el2_lsu_bus_buffer.scala 200:148] + node _T_456 = bits(ld_byte_hitvec_hi_2, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_457 = and(ld_byte_hitvec_hi_2, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_458 = orr(_T_457) @[el2_lsu_bus_buffer.scala 200:144] + node _T_459 = eq(_T_458, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_460 = and(_T_456, _T_459) @[el2_lsu_bus_buffer.scala 200:97] + node _T_461 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_462 = eq(_T_461, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_463 = and(_T_460, _T_462) @[el2_lsu_bus_buffer.scala 200:148] + node _T_464 = bits(ld_byte_hitvec_hi_2, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_465 = and(ld_byte_hitvec_hi_2, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_466 = orr(_T_465) @[el2_lsu_bus_buffer.scala 200:144] + node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_468 = and(_T_464, _T_467) @[el2_lsu_bus_buffer.scala 200:97] + node _T_469 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 200:170] + node _T_470 = eq(_T_469, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_471 = and(_T_468, _T_470) @[el2_lsu_bus_buffer.scala 200:148] + node _T_472 = cat(_T_471, _T_463) @[Cat.scala 29:58] + node _T_473 = cat(_T_472, _T_455) @[Cat.scala 29:58] + node _T_474 = cat(_T_473, _T_447) @[Cat.scala 29:58] + node _T_475 = bits(ld_byte_hitvec_hi_3, 0, 0) @[el2_lsu_bus_buffer.scala 200:93] + node _T_476 = and(ld_byte_hitvec_hi_3, buf_age_younger[0]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_477 = orr(_T_476) @[el2_lsu_bus_buffer.scala 200:144] + node _T_478 = eq(_T_477, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_479 = and(_T_475, _T_478) @[el2_lsu_bus_buffer.scala 200:97] + node _T_480 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_481 = eq(_T_480, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_482 = and(_T_479, _T_481) @[el2_lsu_bus_buffer.scala 200:148] + node _T_483 = bits(ld_byte_hitvec_hi_3, 1, 1) @[el2_lsu_bus_buffer.scala 200:93] + node _T_484 = and(ld_byte_hitvec_hi_3, buf_age_younger[1]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 200:144] + node _T_486 = eq(_T_485, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_487 = and(_T_483, _T_486) @[el2_lsu_bus_buffer.scala 200:97] + node _T_488 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_489 = eq(_T_488, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 200:148] + node _T_491 = bits(ld_byte_hitvec_hi_3, 2, 2) @[el2_lsu_bus_buffer.scala 200:93] + node _T_492 = and(ld_byte_hitvec_hi_3, buf_age_younger[2]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_493 = orr(_T_492) @[el2_lsu_bus_buffer.scala 200:144] + node _T_494 = eq(_T_493, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_495 = and(_T_491, _T_494) @[el2_lsu_bus_buffer.scala 200:97] + node _T_496 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_497 = eq(_T_496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_498 = and(_T_495, _T_497) @[el2_lsu_bus_buffer.scala 200:148] + node _T_499 = bits(ld_byte_hitvec_hi_3, 3, 3) @[el2_lsu_bus_buffer.scala 200:93] + node _T_500 = and(ld_byte_hitvec_hi_3, buf_age_younger[3]) @[el2_lsu_bus_buffer.scala 200:122] + node _T_501 = orr(_T_500) @[el2_lsu_bus_buffer.scala 200:144] + node _T_502 = eq(_T_501, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:99] + node _T_503 = and(_T_499, _T_502) @[el2_lsu_bus_buffer.scala 200:97] + node _T_504 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 200:170] + node _T_505 = eq(_T_504, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 200:150] + node _T_506 = and(_T_503, _T_505) @[el2_lsu_bus_buffer.scala 200:148] + node _T_507 = cat(_T_506, _T_498) @[Cat.scala 29:58] + node _T_508 = cat(_T_507, _T_490) @[Cat.scala 29:58] + node _T_509 = cat(_T_508, _T_482) @[Cat.scala 29:58] + ld_byte_hitvecfn_hi[0] <= _T_404 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[1] <= _T_439 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[2] <= _T_474 @[el2_lsu_bus_buffer.scala 200:23] + ld_byte_hitvecfn_hi[3] <= _T_509 @[el2_lsu_bus_buffer.scala 200:23] + wire ibuf_addr : UInt<32> + ibuf_addr <= UInt<1>("h00") + wire ibuf_write : UInt<1> + ibuf_write <= UInt<1>("h00") + wire ibuf_valid : UInt<1> + ibuf_valid <= UInt<1>("h00") + node _T_510 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 205:43] + node _T_511 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 205:64] + node _T_512 = eq(_T_510, _T_511) @[el2_lsu_bus_buffer.scala 205:51] + node _T_513 = and(_T_512, ibuf_write) @[el2_lsu_bus_buffer.scala 205:73] + node _T_514 = and(_T_513, ibuf_valid) @[el2_lsu_bus_buffer.scala 205:86] + node ld_addr_ibuf_hit_lo = and(_T_514, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 205:99] + node _T_515 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 206:43] + node _T_516 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 206:64] + node _T_517 = eq(_T_515, _T_516) @[el2_lsu_bus_buffer.scala 206:51] + node _T_518 = and(_T_517, ibuf_write) @[el2_lsu_bus_buffer.scala 206:73] + node _T_519 = and(_T_518, ibuf_valid) @[el2_lsu_bus_buffer.scala 206:86] + node ld_addr_ibuf_hit_hi = and(_T_519, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 206:99] + wire ibuf_byteen : UInt<4> + ibuf_byteen <= UInt<1>("h00") + node _T_520 = bits(ld_addr_ibuf_hit_lo, 0, 0) @[Bitwise.scala 72:15] + node _T_521 = mux(_T_520, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_522 = and(_T_521, ibuf_byteen) @[el2_lsu_bus_buffer.scala 210:55] + node _T_523 = and(_T_522, ldst_byteen_lo_m) @[el2_lsu_bus_buffer.scala 210:69] + ld_byte_ibuf_hit_lo <= _T_523 @[el2_lsu_bus_buffer.scala 210:23] + node _T_524 = bits(ld_addr_ibuf_hit_hi, 0, 0) @[Bitwise.scala 72:15] + node _T_525 = mux(_T_524, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_526 = and(_T_525, ibuf_byteen) @[el2_lsu_bus_buffer.scala 211:55] + node _T_527 = and(_T_526, ldst_byteen_hi_m) @[el2_lsu_bus_buffer.scala 211:69] + ld_byte_ibuf_hit_hi <= _T_527 @[el2_lsu_bus_buffer.scala 211:23] + wire buf_data : UInt<32>[4] @[el2_lsu_bus_buffer.scala 213:22] + buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 214:12] + wire fwd_data : UInt<32> + fwd_data <= UInt<1>("h00") + node _T_528 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 216:81] + node _T_529 = bits(_T_528, 0, 0) @[Bitwise.scala 72:15] + node _T_530 = mux(_T_529, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_531 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 216:81] + node _T_532 = bits(_T_531, 0, 0) @[Bitwise.scala 72:15] + node _T_533 = mux(_T_532, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_534 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 216:81] + node _T_535 = bits(_T_534, 0, 0) @[Bitwise.scala 72:15] + node _T_536 = mux(_T_535, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_537 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 216:81] + node _T_538 = bits(_T_537, 0, 0) @[Bitwise.scala 72:15] + node _T_539 = mux(_T_538, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_540 = cat(_T_539, _T_536) @[Cat.scala 29:58] + node _T_541 = cat(_T_540, _T_533) @[Cat.scala 29:58] + node ld_fwddata_buf_lo_initial = cat(_T_541, _T_530) @[Cat.scala 29:58] + node _T_542 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 217:81] + node _T_543 = bits(_T_542, 0, 0) @[Bitwise.scala 72:15] + node _T_544 = mux(_T_543, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_545 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 217:81] + node _T_546 = bits(_T_545, 0, 0) @[Bitwise.scala 72:15] + node _T_547 = mux(_T_546, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_548 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 217:81] + node _T_549 = bits(_T_548, 0, 0) @[Bitwise.scala 72:15] + node _T_550 = mux(_T_549, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_551 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 217:81] + node _T_552 = bits(_T_551, 0, 0) @[Bitwise.scala 72:15] + node _T_553 = mux(_T_552, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_554 = cat(_T_553, _T_550) @[Cat.scala 29:58] + node _T_555 = cat(_T_554, _T_547) @[Cat.scala 29:58] + node ld_fwddata_buf_hi_initial = cat(_T_555, _T_544) @[Cat.scala 29:58] + node _T_556 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 218:86] + node _T_557 = bits(_T_556, 0, 0) @[Bitwise.scala 72:15] + node _T_558 = mux(_T_557, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_559 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_560 = and(_T_558, _T_559) @[el2_lsu_bus_buffer.scala 218:91] + node _T_561 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 218:86] + node _T_562 = bits(_T_561, 0, 0) @[Bitwise.scala 72:15] + node _T_563 = mux(_T_562, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_564 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_565 = and(_T_563, _T_564) @[el2_lsu_bus_buffer.scala 218:91] + node _T_566 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 218:86] + node _T_567 = bits(_T_566, 0, 0) @[Bitwise.scala 72:15] + node _T_568 = mux(_T_567, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_569 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_570 = and(_T_568, _T_569) @[el2_lsu_bus_buffer.scala 218:91] + node _T_571 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 218:86] + node _T_572 = bits(_T_571, 0, 0) @[Bitwise.scala 72:15] + node _T_573 = mux(_T_572, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_574 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 218:104] + node _T_575 = and(_T_573, _T_574) @[el2_lsu_bus_buffer.scala 218:91] + node _T_576 = or(_T_560, _T_565) @[el2_lsu_bus_buffer.scala 218:123] + node _T_577 = or(_T_576, _T_570) @[el2_lsu_bus_buffer.scala 218:123] + node _T_578 = or(_T_577, _T_575) @[el2_lsu_bus_buffer.scala 218:123] + node _T_579 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 219:60] + node _T_580 = bits(_T_579, 0, 0) @[Bitwise.scala 72:15] + node _T_581 = mux(_T_580, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_582 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_583 = and(_T_581, _T_582) @[el2_lsu_bus_buffer.scala 219:65] + node _T_584 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 219:60] + node _T_585 = bits(_T_584, 0, 0) @[Bitwise.scala 72:15] + node _T_586 = mux(_T_585, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_587 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_588 = and(_T_586, _T_587) @[el2_lsu_bus_buffer.scala 219:65] + node _T_589 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 219:60] + node _T_590 = bits(_T_589, 0, 0) @[Bitwise.scala 72:15] + node _T_591 = mux(_T_590, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_592 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_593 = and(_T_591, _T_592) @[el2_lsu_bus_buffer.scala 219:65] + node _T_594 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 219:60] + node _T_595 = bits(_T_594, 0, 0) @[Bitwise.scala 72:15] + node _T_596 = mux(_T_595, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_597 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 219:78] + node _T_598 = and(_T_596, _T_597) @[el2_lsu_bus_buffer.scala 219:65] + node _T_599 = or(_T_583, _T_588) @[el2_lsu_bus_buffer.scala 219:97] + node _T_600 = or(_T_599, _T_593) @[el2_lsu_bus_buffer.scala 219:97] + node _T_601 = or(_T_600, _T_598) @[el2_lsu_bus_buffer.scala 219:97] + node _T_602 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 220:60] + node _T_603 = bits(_T_602, 0, 0) @[Bitwise.scala 72:15] + node _T_604 = mux(_T_603, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_605 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_606 = and(_T_604, _T_605) @[el2_lsu_bus_buffer.scala 220:65] + node _T_607 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 220:60] + node _T_608 = bits(_T_607, 0, 0) @[Bitwise.scala 72:15] + node _T_609 = mux(_T_608, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_610 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_611 = and(_T_609, _T_610) @[el2_lsu_bus_buffer.scala 220:65] + node _T_612 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 220:60] + node _T_613 = bits(_T_612, 0, 0) @[Bitwise.scala 72:15] + node _T_614 = mux(_T_613, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_615 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_616 = and(_T_614, _T_615) @[el2_lsu_bus_buffer.scala 220:65] + node _T_617 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 220:60] + node _T_618 = bits(_T_617, 0, 0) @[Bitwise.scala 72:15] + node _T_619 = mux(_T_618, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_620 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 220:78] + node _T_621 = and(_T_619, _T_620) @[el2_lsu_bus_buffer.scala 220:65] + node _T_622 = or(_T_606, _T_611) @[el2_lsu_bus_buffer.scala 220:97] + node _T_623 = or(_T_622, _T_616) @[el2_lsu_bus_buffer.scala 220:97] + node _T_624 = or(_T_623, _T_621) @[el2_lsu_bus_buffer.scala 220:97] + node _T_625 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 221:60] + node _T_626 = bits(_T_625, 0, 0) @[Bitwise.scala 72:15] + node _T_627 = mux(_T_626, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_628 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_629 = and(_T_627, _T_628) @[el2_lsu_bus_buffer.scala 221:65] + node _T_630 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 221:60] + node _T_631 = bits(_T_630, 0, 0) @[Bitwise.scala 72:15] + node _T_632 = mux(_T_631, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_633 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_634 = and(_T_632, _T_633) @[el2_lsu_bus_buffer.scala 221:65] + node _T_635 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 221:60] + node _T_636 = bits(_T_635, 0, 0) @[Bitwise.scala 72:15] + node _T_637 = mux(_T_636, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_638 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_639 = and(_T_637, _T_638) @[el2_lsu_bus_buffer.scala 221:65] + node _T_640 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 221:60] + node _T_641 = bits(_T_640, 0, 0) @[Bitwise.scala 72:15] + node _T_642 = mux(_T_641, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_643 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 221:78] + node _T_644 = and(_T_642, _T_643) @[el2_lsu_bus_buffer.scala 221:65] + node _T_645 = or(_T_629, _T_634) @[el2_lsu_bus_buffer.scala 221:97] + node _T_646 = or(_T_645, _T_639) @[el2_lsu_bus_buffer.scala 221:97] + node _T_647 = or(_T_646, _T_644) @[el2_lsu_bus_buffer.scala 221:97] + node _T_648 = cat(_T_624, _T_647) @[Cat.scala 29:58] + node _T_649 = cat(_T_578, _T_601) @[Cat.scala 29:58] + node _T_650 = cat(_T_649, _T_648) @[Cat.scala 29:58] + node _T_651 = and(ld_fwddata_buf_lo_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 222:32] + node _T_652 = or(_T_650, _T_651) @[el2_lsu_bus_buffer.scala 221:103] + io.ld_fwddata_buf_lo <= _T_652 @[el2_lsu_bus_buffer.scala 218:24] + node _T_653 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 224:86] + node _T_654 = bits(_T_653, 0, 0) @[Bitwise.scala 72:15] + node _T_655 = mux(_T_654, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_656 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_657 = and(_T_655, _T_656) @[el2_lsu_bus_buffer.scala 224:91] + node _T_658 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 224:86] + node _T_659 = bits(_T_658, 0, 0) @[Bitwise.scala 72:15] + node _T_660 = mux(_T_659, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_661 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_662 = and(_T_660, _T_661) @[el2_lsu_bus_buffer.scala 224:91] + node _T_663 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 224:86] + node _T_664 = bits(_T_663, 0, 0) @[Bitwise.scala 72:15] + node _T_665 = mux(_T_664, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_666 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_667 = and(_T_665, _T_666) @[el2_lsu_bus_buffer.scala 224:91] + node _T_668 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 224:86] + node _T_669 = bits(_T_668, 0, 0) @[Bitwise.scala 72:15] + node _T_670 = mux(_T_669, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_671 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 224:104] + node _T_672 = and(_T_670, _T_671) @[el2_lsu_bus_buffer.scala 224:91] + node _T_673 = or(_T_657, _T_662) @[el2_lsu_bus_buffer.scala 224:123] + node _T_674 = or(_T_673, _T_667) @[el2_lsu_bus_buffer.scala 224:123] + node _T_675 = or(_T_674, _T_672) @[el2_lsu_bus_buffer.scala 224:123] + node _T_676 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 225:60] + node _T_677 = bits(_T_676, 0, 0) @[Bitwise.scala 72:15] + node _T_678 = mux(_T_677, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_679 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_680 = and(_T_678, _T_679) @[el2_lsu_bus_buffer.scala 225:65] + node _T_681 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 225:60] + node _T_682 = bits(_T_681, 0, 0) @[Bitwise.scala 72:15] + node _T_683 = mux(_T_682, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_684 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_685 = and(_T_683, _T_684) @[el2_lsu_bus_buffer.scala 225:65] + node _T_686 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 225:60] + node _T_687 = bits(_T_686, 0, 0) @[Bitwise.scala 72:15] + node _T_688 = mux(_T_687, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_689 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_690 = and(_T_688, _T_689) @[el2_lsu_bus_buffer.scala 225:65] + node _T_691 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 225:60] + node _T_692 = bits(_T_691, 0, 0) @[Bitwise.scala 72:15] + node _T_693 = mux(_T_692, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_694 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 225:78] + node _T_695 = and(_T_693, _T_694) @[el2_lsu_bus_buffer.scala 225:65] + node _T_696 = or(_T_680, _T_685) @[el2_lsu_bus_buffer.scala 225:97] + node _T_697 = or(_T_696, _T_690) @[el2_lsu_bus_buffer.scala 225:97] + node _T_698 = or(_T_697, _T_695) @[el2_lsu_bus_buffer.scala 225:97] + node _T_699 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 226:60] + node _T_700 = bits(_T_699, 0, 0) @[Bitwise.scala 72:15] + node _T_701 = mux(_T_700, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_702 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_703 = and(_T_701, _T_702) @[el2_lsu_bus_buffer.scala 226:65] + node _T_704 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 226:60] + node _T_705 = bits(_T_704, 0, 0) @[Bitwise.scala 72:15] + node _T_706 = mux(_T_705, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_707 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_708 = and(_T_706, _T_707) @[el2_lsu_bus_buffer.scala 226:65] + node _T_709 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 226:60] + node _T_710 = bits(_T_709, 0, 0) @[Bitwise.scala 72:15] + node _T_711 = mux(_T_710, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_712 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_713 = and(_T_711, _T_712) @[el2_lsu_bus_buffer.scala 226:65] + node _T_714 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 226:60] + node _T_715 = bits(_T_714, 0, 0) @[Bitwise.scala 72:15] + node _T_716 = mux(_T_715, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_717 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 226:78] + node _T_718 = and(_T_716, _T_717) @[el2_lsu_bus_buffer.scala 226:65] + node _T_719 = or(_T_703, _T_708) @[el2_lsu_bus_buffer.scala 226:97] + node _T_720 = or(_T_719, _T_713) @[el2_lsu_bus_buffer.scala 226:97] + node _T_721 = or(_T_720, _T_718) @[el2_lsu_bus_buffer.scala 226:97] + node _T_722 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 227:60] + node _T_723 = bits(_T_722, 0, 0) @[Bitwise.scala 72:15] + node _T_724 = mux(_T_723, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_725 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_726 = and(_T_724, _T_725) @[el2_lsu_bus_buffer.scala 227:65] + node _T_727 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 227:60] + node _T_728 = bits(_T_727, 0, 0) @[Bitwise.scala 72:15] + node _T_729 = mux(_T_728, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_730 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_731 = and(_T_729, _T_730) @[el2_lsu_bus_buffer.scala 227:65] + node _T_732 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 227:60] + node _T_733 = bits(_T_732, 0, 0) @[Bitwise.scala 72:15] + node _T_734 = mux(_T_733, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_735 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_736 = and(_T_734, _T_735) @[el2_lsu_bus_buffer.scala 227:65] + node _T_737 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 227:60] + node _T_738 = bits(_T_737, 0, 0) @[Bitwise.scala 72:15] + node _T_739 = mux(_T_738, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_740 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 227:78] + node _T_741 = and(_T_739, _T_740) @[el2_lsu_bus_buffer.scala 227:65] + node _T_742 = or(_T_726, _T_731) @[el2_lsu_bus_buffer.scala 227:97] + node _T_743 = or(_T_742, _T_736) @[el2_lsu_bus_buffer.scala 227:97] + node _T_744 = or(_T_743, _T_741) @[el2_lsu_bus_buffer.scala 227:97] + node _T_745 = cat(_T_721, _T_744) @[Cat.scala 29:58] + node _T_746 = cat(_T_675, _T_698) @[Cat.scala 29:58] + node _T_747 = cat(_T_746, _T_745) @[Cat.scala 29:58] + node _T_748 = and(ld_fwddata_buf_hi_initial, ibuf_data) @[el2_lsu_bus_buffer.scala 228:32] + node _T_749 = or(_T_747, _T_748) @[el2_lsu_bus_buffer.scala 227:103] + io.ld_fwddata_buf_hi <= _T_749 @[el2_lsu_bus_buffer.scala 224:24] + node bus_coalescing_disable = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 230:65] + node _T_750 = mux(io.lsu_pkt_r.by, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_751 = mux(io.lsu_pkt_r.half, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_752 = mux(io.lsu_pkt_r.word, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_753 = or(_T_750, _T_751) @[Mux.scala 27:72] + node _T_754 = or(_T_753, _T_752) @[Mux.scala 27:72] + wire ldst_byteen_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_r <= _T_754 @[Mux.scala 27:72] + node _T_755 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 235:50] + node _T_756 = eq(_T_755, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 235:55] + node _T_757 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 236:19] + node _T_758 = eq(_T_757, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 236:24] + node _T_759 = bits(ldst_byteen_r, 3, 3) @[el2_lsu_bus_buffer.scala 236:60] + node _T_760 = cat(UInt<3>("h00"), _T_759) @[Cat.scala 29:58] + node _T_761 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 237:19] + node _T_762 = eq(_T_761, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 237:24] + node _T_763 = bits(ldst_byteen_r, 3, 2) @[el2_lsu_bus_buffer.scala 237:60] + node _T_764 = cat(UInt<2>("h00"), _T_763) @[Cat.scala 29:58] + node _T_765 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 238:19] + node _T_766 = eq(_T_765, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 238:24] + node _T_767 = bits(ldst_byteen_r, 3, 1) @[el2_lsu_bus_buffer.scala 238:60] + node _T_768 = cat(UInt<1>("h00"), _T_767) @[Cat.scala 29:58] + node _T_769 = mux(_T_756, UInt<4>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_770 = mux(_T_758, _T_760, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_771 = mux(_T_762, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_772 = mux(_T_766, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_773 = or(_T_769, _T_770) @[Mux.scala 27:72] + node _T_774 = or(_T_773, _T_771) @[Mux.scala 27:72] + node _T_775 = or(_T_774, _T_772) @[Mux.scala 27:72] + wire ldst_byteen_hi_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_hi_r <= _T_775 @[Mux.scala 27:72] + node _T_776 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 239:50] + node _T_777 = eq(_T_776, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 239:55] + node _T_778 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 240:19] + node _T_779 = eq(_T_778, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 240:24] + node _T_780 = bits(ldst_byteen_r, 2, 0) @[el2_lsu_bus_buffer.scala 240:50] + node _T_781 = cat(_T_780, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_782 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:19] + node _T_783 = eq(_T_782, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 241:24] + node _T_784 = bits(ldst_byteen_r, 1, 0) @[el2_lsu_bus_buffer.scala 241:50] + node _T_785 = cat(_T_784, UInt<2>("h00")) @[Cat.scala 29:58] + node _T_786 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 242:19] + node _T_787 = eq(_T_786, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 242:24] + node _T_788 = bits(ldst_byteen_r, 0, 0) @[el2_lsu_bus_buffer.scala 242:50] + node _T_789 = cat(_T_788, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_790 = mux(_T_777, ldst_byteen_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_791 = mux(_T_779, _T_781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_792 = mux(_T_783, _T_785, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_793 = mux(_T_787, _T_789, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_794 = or(_T_790, _T_791) @[Mux.scala 27:72] + node _T_795 = or(_T_794, _T_792) @[Mux.scala 27:72] + node _T_796 = or(_T_795, _T_793) @[Mux.scala 27:72] + wire ldst_byteen_lo_r : UInt<4> @[Mux.scala 27:72] + ldst_byteen_lo_r <= _T_796 @[Mux.scala 27:72] + node _T_797 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 244:49] + node _T_798 = eq(_T_797, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 244:54] + node _T_799 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 245:19] + node _T_800 = eq(_T_799, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 245:24] + node _T_801 = bits(io.store_data_r, 31, 24) @[el2_lsu_bus_buffer.scala 245:64] + node _T_802 = cat(UInt<24>("h00"), _T_801) @[Cat.scala 29:58] + node _T_803 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 246:19] + node _T_804 = eq(_T_803, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 246:24] + node _T_805 = bits(io.store_data_r, 31, 16) @[el2_lsu_bus_buffer.scala 246:63] + node _T_806 = cat(UInt<16>("h00"), _T_805) @[Cat.scala 29:58] + node _T_807 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 247:19] + node _T_808 = eq(_T_807, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 247:24] + node _T_809 = bits(io.store_data_r, 31, 8) @[el2_lsu_bus_buffer.scala 247:62] + node _T_810 = cat(UInt<8>("h00"), _T_809) @[Cat.scala 29:58] + node _T_811 = mux(_T_798, UInt<32>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_812 = mux(_T_800, _T_802, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_813 = mux(_T_804, _T_806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_814 = mux(_T_808, _T_810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_815 = or(_T_811, _T_812) @[Mux.scala 27:72] + node _T_816 = or(_T_815, _T_813) @[Mux.scala 27:72] + node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] + wire store_data_hi_r : UInt<32> @[Mux.scala 27:72] + store_data_hi_r <= _T_817 @[Mux.scala 27:72] + node _T_818 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 249:49] + node _T_819 = eq(_T_818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 249:54] + node _T_820 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 250:19] + node _T_821 = eq(_T_820, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 250:24] + node _T_822 = bits(io.store_data_r, 23, 0) @[el2_lsu_bus_buffer.scala 250:52] + node _T_823 = cat(_T_822, UInt<8>("h00")) @[Cat.scala 29:58] + node _T_824 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 251:19] + node _T_825 = eq(_T_824, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 251:24] + node _T_826 = bits(io.store_data_r, 15, 0) @[el2_lsu_bus_buffer.scala 251:52] + node _T_827 = cat(_T_826, UInt<16>("h00")) @[Cat.scala 29:58] + node _T_828 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 252:19] + node _T_829 = eq(_T_828, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 252:24] + node _T_830 = bits(io.store_data_r, 7, 0) @[el2_lsu_bus_buffer.scala 252:52] + node _T_831 = cat(_T_830, UInt<24>("h00")) @[Cat.scala 29:58] + node _T_832 = mux(_T_819, io.store_data_r, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_833 = mux(_T_821, _T_823, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_834 = mux(_T_825, _T_827, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_835 = mux(_T_829, _T_831, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_836 = or(_T_832, _T_833) @[Mux.scala 27:72] + node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] + node _T_838 = or(_T_837, _T_835) @[Mux.scala 27:72] + wire store_data_lo_r : UInt<32> @[Mux.scala 27:72] + store_data_lo_r <= _T_838 @[Mux.scala 27:72] + node _T_839 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:36] + node _T_840 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 255:57] + node ldst_samedw_r = eq(_T_839, _T_840) @[el2_lsu_bus_buffer.scala 255:40] + node _T_841 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 256:67] + node _T_842 = eq(_T_841, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 256:74] + node _T_843 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 257:40] + node _T_844 = eq(_T_843, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 257:26] + node _T_845 = mux(io.lsu_pkt_r.word, _T_842, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_846 = mux(io.lsu_pkt_r.half, _T_844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_847 = mux(io.lsu_pkt_r.by, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_848 = or(_T_845, _T_846) @[Mux.scala 27:72] + node _T_849 = or(_T_848, _T_847) @[Mux.scala 27:72] + wire is_aligned_r : UInt<1> @[Mux.scala 27:72] + is_aligned_r <= _T_849 @[Mux.scala 27:72] + node _T_850 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 259:55] + node _T_851 = and(io.lsu_busreq_r, _T_850) @[el2_lsu_bus_buffer.scala 259:34] + node _T_852 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 259:79] + node ibuf_byp = and(_T_851, _T_852) @[el2_lsu_bus_buffer.scala 259:77] + node _T_853 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 260:36] + node _T_854 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 260:56] + node ibuf_wr_en = and(_T_853, _T_854) @[el2_lsu_bus_buffer.scala 260:54] wire ibuf_drain_vld : UInt<1> ibuf_drain_vld <= UInt<1>("h00") - wire ibuf_drainvec_vld : UInt<1>[4] @[el2_lsu_bus_buffer.scala 275:43] - wire ibuf_tag_in : UInt<2> - ibuf_tag_in <= UInt<1>("h00") - wire ibuf_dualtag_in : UInt<2> - ibuf_dualtag_in <= UInt<1>("h00") - wire ibuf_sz_in : UInt<2> - ibuf_sz_in <= UInt<1>("h00") - wire ibuf_addr_in : UInt<32> - ibuf_addr_in <= UInt<1>("h00") - wire ibuf_byteen_in : UInt<4> - ibuf_byteen_in <= UInt<1>("h00") - wire ibuf_data_in : UInt<32> - ibuf_data_in <= UInt<1>("h00") - wire ibuf_timer_in : UInt<3> - ibuf_timer_in <= UInt<1>("h00") - wire ibuf_byteen_out : UInt<4> - ibuf_byteen_out <= UInt<1>("h00") - wire ibuf_data_out : UInt<32> - ibuf_data_out <= UInt<1>("h00") + node _T_855 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 262:36] + node _T_856 = and(ibuf_drain_vld, _T_855) @[el2_lsu_bus_buffer.scala 262:34] + node ibuf_rst = or(_T_856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 262:49] + node _T_857 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 263:44] + node _T_858 = and(io.lsu_busreq_m, _T_857) @[el2_lsu_bus_buffer.scala 263:42] + node _T_859 = and(_T_858, ibuf_valid) @[el2_lsu_bus_buffer.scala 263:61] + node _T_860 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 263:107] + node _T_861 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 263:132] + node _T_862 = neq(_T_860, _T_861) @[el2_lsu_bus_buffer.scala 263:115] + node _T_863 = or(io.lsu_pkt_m.load, _T_862) @[el2_lsu_bus_buffer.scala 263:95] + node ibuf_force_drain = and(_T_859, _T_863) @[el2_lsu_bus_buffer.scala 263:74] + wire ibuf_sideeffect : UInt<1> + ibuf_sideeffect <= UInt<1>("h00") + wire ibuf_timer : UInt<3> + ibuf_timer <= UInt<1>("h00") wire ibuf_merge_en : UInt<1> ibuf_merge_en <= UInt<1>("h00") wire ibuf_merge_in : UInt<1> ibuf_merge_in <= UInt<1>("h00") - wire obuf_valid : UInt<1> - obuf_valid <= UInt<1>("h00") - wire obuf_write : UInt<1> - obuf_write <= UInt<1>("h00") - wire obuf_nosend : UInt<1> - obuf_nosend <= UInt<1>("h00") - wire obuf_rdrsp_pend : UInt<1> - obuf_rdrsp_pend <= UInt<1>("h00") - wire obuf_sideeffect : UInt<1> - obuf_sideeffect <= UInt<1>("h00") - wire obuf_addr : UInt<32> - obuf_addr <= UInt<1>("h00") - wire obuf_data : UInt<64> - obuf_data <= UInt<1>("h00") - wire obuf_sz : UInt<2> - obuf_sz <= UInt<1>("h00") - wire obuf_byteen : UInt<8> - obuf_byteen <= UInt<1>("h00") - wire obuf_merge : UInt<1> - obuf_merge <= UInt<1>("h00") - wire obuf_cmd_done : UInt<1> - obuf_cmd_done <= UInt<1>("h00") - wire obuf_data_done : UInt<1> - obuf_data_done <= UInt<1>("h00") - wire obuf_tag0 : UInt<3> - obuf_tag0 <= UInt<1>("h00") - wire obuf_tag1 : UInt<3> - obuf_tag1 <= UInt<1>("h00") - wire obuf_rdrsp_tag : UInt<3> - obuf_rdrsp_tag <= UInt<1>("h00") - wire ibuf_buf_byp : UInt<1> - ibuf_buf_byp <= UInt<1>("h00") - wire obuf_force_wr_en : UInt<1> - obuf_force_wr_en <= UInt<1>("h00") - wire obuf_wr_wait : UInt<1> - obuf_wr_wait <= UInt<1>("h00") - wire obuf_wr_en : UInt<1> - obuf_wr_en <= UInt<1>("h00") - wire obuf_wr_enQ : UInt<1> - obuf_wr_enQ <= UInt<1>("h00") - wire obuf_rst : UInt<1> - obuf_rst <= UInt<1>("h00") - wire obuf_write_in : UInt<1> - obuf_write_in <= UInt<1>("h00") - wire obuf_nosend_in : UInt<1> - obuf_nosend_in <= UInt<1>("h00") - wire obuf_rdrsp_pend_in : UInt<1> - obuf_rdrsp_pend_in <= UInt<1>("h00") - wire obuf_sideeffect_in : UInt<1> - obuf_sideeffect_in <= UInt<1>("h00") - wire obuf_aligned_in : UInt<1> - obuf_aligned_in <= UInt<1>("h00") - wire obuf_addr_in : UInt<64> - obuf_addr_in <= UInt<1>("h00") - wire obuf_data_in : UInt<64> - obuf_data_in <= UInt<1>("h00") - wire obuf_sz_in : UInt<2> - obuf_sz_in <= UInt<1>("h00") - wire obuf_byteen_in : UInt<8> - obuf_byteen_in <= UInt<1>("h00") - wire obuf_merge_in : UInt<1> - obuf_merge_in <= UInt<1>("h00") - wire obuf_cmd_done_in : UInt<1> - obuf_cmd_done_in <= UInt<1>("h00") - wire obuf_data_done_in : UInt<1> - obuf_data_done_in <= UInt<1>("h00") - wire obuf_tag0_in : UInt<3> - obuf_tag0_in <= UInt<1>("h00") - wire obuf_tag1_in : UInt<3> - obuf_tag1_in <= UInt<1>("h00") - wire obuf_rdrsp_tag_in : UInt<3> - obuf_rdrsp_tag_in <= UInt<1>("h00") - wire obuf_merge_en : UInt<1> - obuf_merge_en <= UInt<1>("h00") + node _T_864 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 268:62] + node _T_865 = or(ibuf_wr_en, _T_864) @[el2_lsu_bus_buffer.scala 268:48] + node _T_866 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 268:98] + node _T_867 = eq(_T_866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 268:82] + node _T_868 = and(_T_865, _T_867) @[el2_lsu_bus_buffer.scala 268:80] + node _T_869 = or(_T_868, ibuf_byp) @[el2_lsu_bus_buffer.scala 269:5] + node _T_870 = or(_T_869, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 269:16] + node _T_871 = or(_T_870, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 269:35] + node _T_872 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 269:55] + node _T_873 = or(_T_871, _T_872) @[el2_lsu_bus_buffer.scala 269:53] + node _T_874 = or(_T_873, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 269:67] + node _T_875 = and(ibuf_valid, _T_874) @[el2_lsu_bus_buffer.scala 268:32] + ibuf_drain_vld <= _T_875 @[el2_lsu_bus_buffer.scala 268:18] + wire ibuf_tag : UInt<2> + ibuf_tag <= UInt<1>("h00") + wire WrPtr1_r : UInt<2> + WrPtr1_r <= UInt<1>("h00") + wire WrPtr0_r : UInt<2> + WrPtr0_r <= UInt<1>("h00") + node _T_876 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 274:39] + node _T_877 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 274:69] + node ibuf_tag_in = mux(_T_876, ibuf_tag, _T_877) @[el2_lsu_bus_buffer.scala 274:24] + node ibuf_sz_in = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node ibuf_addr_in = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 277:25] + node _T_878 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 278:42] + node _T_879 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 278:70] + node _T_880 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 278:95] + node _T_881 = or(_T_879, _T_880) @[el2_lsu_bus_buffer.scala 278:77] + node _T_882 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:41] + node _T_883 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 279:65] + node _T_884 = mux(io.ldst_dual_r, _T_882, _T_883) @[el2_lsu_bus_buffer.scala 279:8] + node ibuf_byteen_in = mux(_T_878, _T_881, _T_884) @[el2_lsu_bus_buffer.scala 278:27] + node _T_885 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_886 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 283:25] + node _T_887 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 283:45] + node _T_888 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 283:76] + node _T_889 = mux(_T_886, _T_887, _T_888) @[el2_lsu_bus_buffer.scala 283:8] + node _T_890 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:40] + node _T_891 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 284:77] + node _T_892 = mux(io.ldst_dual_r, _T_890, _T_891) @[el2_lsu_bus_buffer.scala 284:8] + node _T_893 = mux(_T_885, _T_889, _T_892) @[el2_lsu_bus_buffer.scala 282:46] + node _T_894 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_895 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 283:25] + node _T_896 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 283:45] + node _T_897 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 283:76] + node _T_898 = mux(_T_895, _T_896, _T_897) @[el2_lsu_bus_buffer.scala 283:8] + node _T_899 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:40] + node _T_900 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 284:77] + node _T_901 = mux(io.ldst_dual_r, _T_899, _T_900) @[el2_lsu_bus_buffer.scala 284:8] + node _T_902 = mux(_T_894, _T_898, _T_901) @[el2_lsu_bus_buffer.scala 282:46] + node _T_903 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_904 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 283:25] + node _T_905 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 283:45] + node _T_906 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 283:76] + node _T_907 = mux(_T_904, _T_905, _T_906) @[el2_lsu_bus_buffer.scala 283:8] + node _T_908 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:40] + node _T_909 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 284:77] + node _T_910 = mux(io.ldst_dual_r, _T_908, _T_909) @[el2_lsu_bus_buffer.scala 284:8] + node _T_911 = mux(_T_903, _T_907, _T_910) @[el2_lsu_bus_buffer.scala 282:46] + node _T_912 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 282:61] + node _T_913 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 283:25] + node _T_914 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 283:45] + node _T_915 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 283:76] + node _T_916 = mux(_T_913, _T_914, _T_915) @[el2_lsu_bus_buffer.scala 283:8] + node _T_917 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:40] + node _T_918 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 284:77] + node _T_919 = mux(io.ldst_dual_r, _T_917, _T_918) @[el2_lsu_bus_buffer.scala 284:8] + node _T_920 = mux(_T_912, _T_916, _T_919) @[el2_lsu_bus_buffer.scala 282:46] + node _T_921 = cat(_T_920, _T_911) @[Cat.scala 29:58] + node _T_922 = cat(_T_921, _T_902) @[Cat.scala 29:58] + node ibuf_data_in = cat(_T_922, _T_893) @[Cat.scala 29:58] + node _T_923 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 285:59] + node _T_924 = bits(_T_923, 0, 0) @[el2_lsu_bus_buffer.scala 285:79] + node _T_925 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 285:93] + node _T_926 = tail(_T_925, 1) @[el2_lsu_bus_buffer.scala 285:93] + node _T_927 = mux(_T_924, _T_926, ibuf_timer) @[el2_lsu_bus_buffer.scala 285:47] + node ibuf_timer_in = mux(ibuf_wr_en, UInt<1>("h00"), _T_927) @[el2_lsu_bus_buffer.scala 285:26] + node _T_928 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 287:36] + node _T_929 = and(_T_928, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 287:54] + node _T_930 = and(_T_929, ibuf_valid) @[el2_lsu_bus_buffer.scala 287:75] + node _T_931 = and(_T_930, ibuf_write) @[el2_lsu_bus_buffer.scala 287:88] + node _T_932 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 287:117] + node _T_933 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 287:137] + node _T_934 = eq(_T_932, _T_933) @[el2_lsu_bus_buffer.scala 287:124] + node _T_935 = and(_T_931, _T_934) @[el2_lsu_bus_buffer.scala 287:101] + node _T_936 = eq(io.is_sideeffects_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:147] + node _T_937 = and(_T_935, _T_936) @[el2_lsu_bus_buffer.scala 287:145] + node _T_938 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 287:170] + node _T_939 = and(_T_937, _T_938) @[el2_lsu_bus_buffer.scala 287:168] + ibuf_merge_en <= _T_939 @[el2_lsu_bus_buffer.scala 287:17] + node _T_940 = eq(io.ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 288:20] + ibuf_merge_in <= _T_940 @[el2_lsu_bus_buffer.scala 288:17] + node _T_941 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_942 = and(ibuf_merge_en, _T_941) @[el2_lsu_bus_buffer.scala 289:63] + node _T_943 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:92] + node _T_944 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 289:114] + node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 289:96] + node _T_946 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 289:130] + node _T_947 = mux(_T_942, _T_945, _T_946) @[el2_lsu_bus_buffer.scala 289:48] + node _T_948 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_949 = and(ibuf_merge_en, _T_948) @[el2_lsu_bus_buffer.scala 289:63] + node _T_950 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:92] + node _T_951 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 289:114] + node _T_952 = or(_T_950, _T_951) @[el2_lsu_bus_buffer.scala 289:96] + node _T_953 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 289:130] + node _T_954 = mux(_T_949, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 289:48] + node _T_955 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_956 = and(ibuf_merge_en, _T_955) @[el2_lsu_bus_buffer.scala 289:63] + node _T_957 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:92] + node _T_958 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 289:114] + node _T_959 = or(_T_957, _T_958) @[el2_lsu_bus_buffer.scala 289:96] + node _T_960 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 289:130] + node _T_961 = mux(_T_956, _T_959, _T_960) @[el2_lsu_bus_buffer.scala 289:48] + node _T_962 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 289:65] + node _T_963 = and(ibuf_merge_en, _T_962) @[el2_lsu_bus_buffer.scala 289:63] + node _T_964 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:92] + node _T_965 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 289:114] + node _T_966 = or(_T_964, _T_965) @[el2_lsu_bus_buffer.scala 289:96] + node _T_967 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 289:130] + node _T_968 = mux(_T_963, _T_966, _T_967) @[el2_lsu_bus_buffer.scala 289:48] + node _T_969 = cat(_T_968, _T_961) @[Cat.scala 29:58] + node _T_970 = cat(_T_969, _T_954) @[Cat.scala 29:58] + node ibuf_byteen_out = cat(_T_970, _T_947) @[Cat.scala 29:58] + node _T_971 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_972 = and(ibuf_merge_en, _T_971) @[el2_lsu_bus_buffer.scala 290:60] + node _T_973 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 290:98] + node _T_974 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 290:118] + node _T_975 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:143] + node _T_976 = mux(_T_973, _T_974, _T_975) @[el2_lsu_bus_buffer.scala 290:81] + node _T_977 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 290:169] + node _T_978 = mux(_T_972, _T_976, _T_977) @[el2_lsu_bus_buffer.scala 290:45] + node _T_979 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_980 = and(ibuf_merge_en, _T_979) @[el2_lsu_bus_buffer.scala 290:60] + node _T_981 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 290:98] + node _T_982 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 290:118] + node _T_983 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:143] + node _T_984 = mux(_T_981, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 290:81] + node _T_985 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 290:169] + node _T_986 = mux(_T_980, _T_984, _T_985) @[el2_lsu_bus_buffer.scala 290:45] + node _T_987 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_988 = and(ibuf_merge_en, _T_987) @[el2_lsu_bus_buffer.scala 290:60] + node _T_989 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 290:98] + node _T_990 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 290:118] + node _T_991 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:143] + node _T_992 = mux(_T_989, _T_990, _T_991) @[el2_lsu_bus_buffer.scala 290:81] + node _T_993 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 290:169] + node _T_994 = mux(_T_988, _T_992, _T_993) @[el2_lsu_bus_buffer.scala 290:45] + node _T_995 = eq(ibuf_merge_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 290:62] + node _T_996 = and(ibuf_merge_en, _T_995) @[el2_lsu_bus_buffer.scala 290:60] + node _T_997 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 290:98] + node _T_998 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 290:118] + node _T_999 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:143] + node _T_1000 = mux(_T_997, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 290:81] + node _T_1001 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 290:169] + node _T_1002 = mux(_T_996, _T_1000, _T_1001) @[el2_lsu_bus_buffer.scala 290:45] + node _T_1003 = cat(_T_1002, _T_994) @[Cat.scala 29:58] + node _T_1004 = cat(_T_1003, _T_986) @[Cat.scala 29:58] + node ibuf_data_out = cat(_T_1004, _T_978) @[Cat.scala 29:58] + node _T_1005 = mux(ibuf_wr_en, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 292:58] + node _T_1006 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 292:93] + node _T_1007 = and(_T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 292:91] + reg _T_1008 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 292:54] + _T_1008 <= _T_1007 @[el2_lsu_bus_buffer.scala 292:54] + ibuf_valid <= _T_1008 @[el2_lsu_bus_buffer.scala 292:14] + reg _T_1009 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1009 <= ibuf_tag_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_tag <= _T_1009 @[el2_lsu_bus_buffer.scala 293:12] + reg ibuf_dualtag : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dualtag <= WrPtr0_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_dual : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_dual <= io.ldst_dual_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_samedw : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_samedw <= ldst_samedw_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg ibuf_nomerge : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_nomerge <= io.no_dword_merge_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1010 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1010 <= io.is_sideeffects_r @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_sideeffect <= _T_1010 @[el2_lsu_bus_buffer.scala 298:19] + reg ibuf_unsign : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_unsign <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + reg _T_1011 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1011 <= io.lsu_pkt_r.store @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_write <= _T_1011 @[el2_lsu_bus_buffer.scala 300:14] + reg ibuf_sz : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 508:23] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1012 <= ibuf_addr_in @[el2_lib.scala 514:16] + ibuf_addr <= _T_1012 @[el2_lsu_bus_buffer.scala 302:13] + reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when ibuf_wr_en : @[Reg.scala 28:19] + _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + ibuf_byteen <= _T_1013 @[el2_lsu_bus_buffer.scala 303:15] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 508:23] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_1.io.en <= ibuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1014 <= ibuf_data_in @[el2_lib.scala 514:16] + ibuf_data <= _T_1014 @[el2_lsu_bus_buffer.scala 304:13] + reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 305:55] + _T_1015 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 305:55] + ibuf_timer <= _T_1015 @[el2_lsu_bus_buffer.scala 305:14] + wire buf_numvld_wrcmd_any : UInt<4> + buf_numvld_wrcmd_any <= UInt<1>("h00") + wire buf_numvld_cmd_any : UInt<4> + buf_numvld_cmd_any <= UInt<1>("h00") wire obuf_wr_timer : UInt<3> obuf_wr_timer <= UInt<1>("h00") - wire obuf_wr_timer_in : UInt<3> - obuf_wr_timer_in <= UInt<1>("h00") - wire obuf_byteen0_in : UInt<8> - obuf_byteen0_in <= UInt<1>("h00") - wire obuf_byteen1_in : UInt<8> - obuf_byteen1_in <= UInt<1>("h00") - wire obuf_data0_in : UInt<64> - obuf_data0_in <= UInt<1>("h00") - wire obuf_data1_in : UInt<64> - obuf_data1_in <= UInt<1>("h00") - wire lsu_axi_awvalid_q : UInt<1> - lsu_axi_awvalid_q <= UInt<1>("h00") - wire lsu_axi_awready_q : UInt<1> - lsu_axi_awready_q <= UInt<1>("h00") - wire lsu_axi_wvalid_q : UInt<1> - lsu_axi_wvalid_q <= UInt<1>("h00") - wire lsu_axi_wready_q : UInt<1> - lsu_axi_wready_q <= UInt<1>("h00") - wire lsu_axi_arvalid_q : UInt<1> - lsu_axi_arvalid_q <= UInt<1>("h00") - wire lsu_axi_arready_q : UInt<1> - lsu_axi_arready_q <= UInt<1>("h00") - wire lsu_axi_bvalid_q : UInt<1> - lsu_axi_bvalid_q <= UInt<1>("h00") - wire lsu_axi_bready_q : UInt<1> - lsu_axi_bready_q <= UInt<1>("h00") - wire lsu_axi_rvalid_q : UInt<1> - lsu_axi_rvalid_q <= UInt<1>("h00") - wire lsu_axi_rready_q : UInt<1> - lsu_axi_rready_q <= UInt<1>("h00") - wire lsu_axi_bid_q : UInt<3> - lsu_axi_bid_q <= UInt<1>("h00") - wire lsu_axi_rid_q : UInt<3> - lsu_axi_rid_q <= UInt<1>("h00") - wire lsu_axi_bresp_q : UInt<2> - lsu_axi_bresp_q <= UInt<1>("h00") - wire lsu_axi_rresp_q : UInt<2> - lsu_axi_rresp_q <= UInt<1>("h00") - wire lsu_imprecise_error_store_tag : UInt<2> - lsu_imprecise_error_store_tag <= UInt<1>("h00") - wire lsu_axi_rdata_q : UInt<64> - lsu_axi_rdata_q <= UInt<1>("h00") - CmdPtr0Dec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[0][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[0][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[1][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[1][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[2][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[2][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - CmdPtr0Dec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 354:27] - CmdPtr1Dec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 355:27] - RspPtrDec[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 356:28] - buf_state[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 357:28] - buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 358:28] - buf_addr[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 359:28] - buf_byteen[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 360:28] - buf_sideeffect[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 361:28] - buf_write[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 362:28] - buf_unsign[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 363:28] - buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 364:28] - buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 365:28] - buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 366:28] - buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 367:28] - buf_dualtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 368:28] - buf_ldfwd[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 369:28] - buf_ldfwdtag[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 370:28] - buf_error[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 371:28] - buf_data[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 372:28] - buf_age[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 373:28] - buf_age_younger[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_age_younger[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 374:28] - buf_rspage[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rspage[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 375:28] - buf_rsp_pickage[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_rsp_pickage[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 376:28] - buf_dual_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 378:28] - buf_samedw_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 379:28] - buf_nomerge_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 380:28] - buf_sideeffect_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 382:28] - buf_unsign_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 383:28] - buf_sz_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 384:28] - buf_write_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 385:28] - buf_dualhi_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 386:28] - buf_dualtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 387:28] - buf_byteen_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 388:28] - buf_addr_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 389:28] - buf_age_in[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_age_in[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:28] - buf_ageQ[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_ageQ[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 391:28] - buf_rspage_set[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_set[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 392:28] - buf_rspage_in[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspage_in[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 393:28] - buf_rspageQ[3][0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - buf_rspageQ[3][3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 394:28] - ibuf_drainvec_vld[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 395:28] - node _T = bits(io.ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_buffer.scala 400:51] - ldst_byteen_hi_m <= _T @[el2_lsu_bus_buffer.scala 400:28] - node _T_1 = bits(io.ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_buffer.scala 401:51] - ldst_byteen_lo_m <= _T_1 @[el2_lsu_bus_buffer.scala 401:28] - node _T_2 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 403:45] - node _T_3 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 403:65] - node _T_4 = eq(_T_2, _T_3) @[el2_lsu_bus_buffer.scala 403:52] - node _T_5 = and(_T_4, ibuf_write) @[el2_lsu_bus_buffer.scala 403:73] - node _T_6 = and(_T_5, ibuf_valid) @[el2_lsu_bus_buffer.scala 403:86] - node _T_7 = and(_T_6, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 403:99] - ld_addr_ibuf_hit_lo <= _T_7 @[el2_lsu_bus_buffer.scala 403:28] - node _T_8 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 404:45] - node _T_9 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 404:65] - node _T_10 = eq(_T_8, _T_9) @[el2_lsu_bus_buffer.scala 404:52] - node _T_11 = and(_T_10, ibuf_write) @[el2_lsu_bus_buffer.scala 404:73] - node _T_12 = and(_T_11, ibuf_valid) @[el2_lsu_bus_buffer.scala 404:86] - node _T_13 = and(_T_12, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 404:99] - ld_addr_ibuf_hit_hi <= _T_13 @[el2_lsu_bus_buffer.scala 404:28] - node _T_14 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 406:85] - node _T_15 = and(ld_addr_ibuf_hit_lo, _T_14) @[el2_lsu_bus_buffer.scala 406:72] - node _T_16 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 406:107] - node _T_17 = and(_T_15, _T_16) @[el2_lsu_bus_buffer.scala 406:89] - node _T_18 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 406:85] - node _T_19 = and(ld_addr_ibuf_hit_lo, _T_18) @[el2_lsu_bus_buffer.scala 406:72] - node _T_20 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 406:107] - node _T_21 = and(_T_19, _T_20) @[el2_lsu_bus_buffer.scala 406:89] - node _T_22 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 406:85] - node _T_23 = and(ld_addr_ibuf_hit_lo, _T_22) @[el2_lsu_bus_buffer.scala 406:72] - node _T_24 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 406:107] - node _T_25 = and(_T_23, _T_24) @[el2_lsu_bus_buffer.scala 406:89] - node _T_26 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 406:85] - node _T_27 = and(ld_addr_ibuf_hit_lo, _T_26) @[el2_lsu_bus_buffer.scala 406:72] - node _T_28 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 406:107] - node _T_29 = and(_T_27, _T_28) @[el2_lsu_bus_buffer.scala 406:89] - node _T_30 = cat(_T_29, _T_25) @[Cat.scala 29:58] - node _T_31 = cat(_T_30, _T_21) @[Cat.scala 29:58] - node _T_32 = cat(_T_31, _T_17) @[Cat.scala 29:58] - ld_byte_ibuf_hit_lo <= _T_32 @[el2_lsu_bus_buffer.scala 406:28] - node _T_33 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 407:85] - node _T_34 = and(ld_addr_ibuf_hit_hi, _T_33) @[el2_lsu_bus_buffer.scala 407:72] - node _T_35 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 407:107] - node _T_36 = and(_T_34, _T_35) @[el2_lsu_bus_buffer.scala 407:89] - node _T_37 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 407:85] - node _T_38 = and(ld_addr_ibuf_hit_hi, _T_37) @[el2_lsu_bus_buffer.scala 407:72] - node _T_39 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 407:107] - node _T_40 = and(_T_38, _T_39) @[el2_lsu_bus_buffer.scala 407:89] - node _T_41 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 407:85] - node _T_42 = and(ld_addr_ibuf_hit_hi, _T_41) @[el2_lsu_bus_buffer.scala 407:72] - node _T_43 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 407:107] - node _T_44 = and(_T_42, _T_43) @[el2_lsu_bus_buffer.scala 407:89] - node _T_45 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 407:85] - node _T_46 = and(ld_addr_ibuf_hit_hi, _T_45) @[el2_lsu_bus_buffer.scala 407:72] - node _T_47 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 407:107] - node _T_48 = and(_T_46, _T_47) @[el2_lsu_bus_buffer.scala 407:89] - node _T_49 = cat(_T_48, _T_44) @[Cat.scala 29:58] - node _T_50 = cat(_T_49, _T_40) @[Cat.scala 29:58] - node _T_51 = cat(_T_50, _T_36) @[Cat.scala 29:58] - ld_byte_ibuf_hit_hi <= _T_51 @[el2_lsu_bus_buffer.scala 407:28] - node _T_52 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_53 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_54 = eq(_T_52, _T_53) @[el2_lsu_bus_buffer.scala 409:77] - node _T_55 = and(_T_54, buf_write[0]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_56 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_57 = and(_T_55, _T_56) @[el2_lsu_bus_buffer.scala 409:115] - node _T_58 = and(_T_57, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_59 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_60 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_61 = eq(_T_59, _T_60) @[el2_lsu_bus_buffer.scala 409:77] - node _T_62 = and(_T_61, buf_write[1]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_63 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_64 = and(_T_62, _T_63) @[el2_lsu_bus_buffer.scala 409:115] - node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_66 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_67 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_68 = eq(_T_66, _T_67) @[el2_lsu_bus_buffer.scala 409:77] - node _T_69 = and(_T_68, buf_write[2]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_70 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_71 = and(_T_69, _T_70) @[el2_lsu_bus_buffer.scala 409:115] - node _T_72 = and(_T_71, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_73 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 409:70] - node _T_74 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 409:92] - node _T_75 = eq(_T_73, _T_74) @[el2_lsu_bus_buffer.scala 409:77] - node _T_76 = and(_T_75, buf_write[3]) @[el2_lsu_bus_buffer.scala 409:100] - node _T_77 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 409:131] - node _T_78 = and(_T_76, _T_77) @[el2_lsu_bus_buffer.scala 409:115] - node _T_79 = and(_T_78, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 409:143] - node _T_80 = cat(_T_79, _T_72) @[Cat.scala 29:58] - node _T_81 = cat(_T_80, _T_65) @[Cat.scala 29:58] - node _T_82 = cat(_T_81, _T_58) @[Cat.scala 29:58] - ld_addr_hitvec_lo <= _T_82 @[el2_lsu_bus_buffer.scala 409:28] - node _T_83 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_84 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_85 = eq(_T_83, _T_84) @[el2_lsu_bus_buffer.scala 410:77] - node _T_86 = and(_T_85, buf_write[0]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_87 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_88 = and(_T_86, _T_87) @[el2_lsu_bus_buffer.scala 410:115] - node _T_89 = and(_T_88, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_90 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_91 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_92 = eq(_T_90, _T_91) @[el2_lsu_bus_buffer.scala 410:77] - node _T_93 = and(_T_92, buf_write[1]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_94 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_95 = and(_T_93, _T_94) @[el2_lsu_bus_buffer.scala 410:115] - node _T_96 = and(_T_95, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_97 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_98 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_99 = eq(_T_97, _T_98) @[el2_lsu_bus_buffer.scala 410:77] - node _T_100 = and(_T_99, buf_write[2]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_101 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_102 = and(_T_100, _T_101) @[el2_lsu_bus_buffer.scala 410:115] - node _T_103 = and(_T_102, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_104 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 410:70] - node _T_105 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 410:92] - node _T_106 = eq(_T_104, _T_105) @[el2_lsu_bus_buffer.scala 410:77] - node _T_107 = and(_T_106, buf_write[3]) @[el2_lsu_bus_buffer.scala 410:100] - node _T_108 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 410:131] - node _T_109 = and(_T_107, _T_108) @[el2_lsu_bus_buffer.scala 410:115] - node _T_110 = and(_T_109, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 410:143] - node _T_111 = cat(_T_110, _T_103) @[Cat.scala 29:58] - node _T_112 = cat(_T_111, _T_96) @[Cat.scala 29:58] - node _T_113 = cat(_T_112, _T_89) @[Cat.scala 29:58] - ld_addr_hitvec_hi <= _T_113 @[el2_lsu_bus_buffer.scala 410:28] - node _T_114 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 412:71] - node _T_115 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_116 = or(_T_114, _T_115) @[el2_lsu_bus_buffer.scala 412:75] - node _T_117 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 412:71] - node _T_118 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_119 = or(_T_117, _T_118) @[el2_lsu_bus_buffer.scala 412:75] - node _T_120 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 412:71] - node _T_121 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_122 = or(_T_120, _T_121) @[el2_lsu_bus_buffer.scala 412:75] - node _T_123 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 412:71] - node _T_124 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 412:100] - node _T_125 = or(_T_123, _T_124) @[el2_lsu_bus_buffer.scala 412:75] - node _T_126 = cat(_T_125, _T_122) @[Cat.scala 29:58] - node _T_127 = cat(_T_126, _T_119) @[Cat.scala 29:58] - node _T_128 = cat(_T_127, _T_116) @[Cat.scala 29:58] - io.ld_byte_hit_buf_lo <= _T_128 @[el2_lsu_bus_buffer.scala 412:28] - node _T_129 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 413:71] - node _T_130 = orr(ld_byte_hitvecfn_lo[0]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_131 = or(_T_129, _T_130) @[el2_lsu_bus_buffer.scala 413:75] - node _T_132 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 413:71] - node _T_133 = orr(ld_byte_hitvecfn_lo[1]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_134 = or(_T_132, _T_133) @[el2_lsu_bus_buffer.scala 413:75] - node _T_135 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 413:71] - node _T_136 = orr(ld_byte_hitvecfn_lo[2]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_137 = or(_T_135, _T_136) @[el2_lsu_bus_buffer.scala 413:75] - node _T_138 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 413:71] - node _T_139 = orr(ld_byte_hitvecfn_lo[3]) @[el2_lsu_bus_buffer.scala 413:100] - node _T_140 = or(_T_138, _T_139) @[el2_lsu_bus_buffer.scala 413:75] - node _T_141 = cat(_T_140, _T_137) @[Cat.scala 29:58] - node _T_142 = cat(_T_141, _T_134) @[Cat.scala 29:58] - node _T_143 = cat(_T_142, _T_131) @[Cat.scala 29:58] - io.ld_byte_hit_buf_hi <= _T_143 @[el2_lsu_bus_buffer.scala 413:28] - node _T_144 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_145 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_146 = and(_T_144, _T_145) @[el2_lsu_bus_buffer.scala 415:97] - node _T_147 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_148 = and(_T_146, _T_147) @[el2_lsu_bus_buffer.scala 415:116] - node _T_149 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_150 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_151 = and(_T_149, _T_150) @[el2_lsu_bus_buffer.scala 415:97] - node _T_152 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_153 = and(_T_151, _T_152) @[el2_lsu_bus_buffer.scala 415:116] - node _T_154 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_155 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_156 = and(_T_154, _T_155) @[el2_lsu_bus_buffer.scala 415:97] - node _T_157 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_158 = and(_T_156, _T_157) @[el2_lsu_bus_buffer.scala 415:116] - node _T_159 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_160 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 415:112] - node _T_161 = and(_T_159, _T_160) @[el2_lsu_bus_buffer.scala 415:97] - node _T_162 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_buffer.scala 415:134] - node _T_163 = and(_T_161, _T_162) @[el2_lsu_bus_buffer.scala 415:116] - node _T_164 = cat(_T_163, _T_158) @[Cat.scala 29:58] - node _T_165 = cat(_T_164, _T_153) @[Cat.scala 29:58] - node _T_166 = cat(_T_165, _T_148) @[Cat.scala 29:58] - node _T_167 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_168 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_169 = and(_T_167, _T_168) @[el2_lsu_bus_buffer.scala 415:97] - node _T_170 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_171 = and(_T_169, _T_170) @[el2_lsu_bus_buffer.scala 415:116] - node _T_172 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_173 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_174 = and(_T_172, _T_173) @[el2_lsu_bus_buffer.scala 415:97] - node _T_175 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_176 = and(_T_174, _T_175) @[el2_lsu_bus_buffer.scala 415:116] - node _T_177 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_178 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_179 = and(_T_177, _T_178) @[el2_lsu_bus_buffer.scala 415:97] - node _T_180 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_181 = and(_T_179, _T_180) @[el2_lsu_bus_buffer.scala 415:116] - node _T_182 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_183 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 415:112] - node _T_184 = and(_T_182, _T_183) @[el2_lsu_bus_buffer.scala 415:97] - node _T_185 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_buffer.scala 415:134] - node _T_186 = and(_T_184, _T_185) @[el2_lsu_bus_buffer.scala 415:116] - node _T_187 = cat(_T_186, _T_181) @[Cat.scala 29:58] - node _T_188 = cat(_T_187, _T_176) @[Cat.scala 29:58] - node _T_189 = cat(_T_188, _T_171) @[Cat.scala 29:58] - node _T_190 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_191 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_192 = and(_T_190, _T_191) @[el2_lsu_bus_buffer.scala 415:97] - node _T_193 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_194 = and(_T_192, _T_193) @[el2_lsu_bus_buffer.scala 415:116] - node _T_195 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_196 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_197 = and(_T_195, _T_196) @[el2_lsu_bus_buffer.scala 415:97] - node _T_198 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_199 = and(_T_197, _T_198) @[el2_lsu_bus_buffer.scala 415:116] - node _T_200 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_201 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_202 = and(_T_200, _T_201) @[el2_lsu_bus_buffer.scala 415:97] - node _T_203 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_204 = and(_T_202, _T_203) @[el2_lsu_bus_buffer.scala 415:116] - node _T_205 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_206 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 415:112] - node _T_207 = and(_T_205, _T_206) @[el2_lsu_bus_buffer.scala 415:97] - node _T_208 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_buffer.scala 415:134] - node _T_209 = and(_T_207, _T_208) @[el2_lsu_bus_buffer.scala 415:116] - node _T_210 = cat(_T_209, _T_204) @[Cat.scala 29:58] - node _T_211 = cat(_T_210, _T_199) @[Cat.scala 29:58] - node _T_212 = cat(_T_211, _T_194) @[Cat.scala 29:58] - node _T_213 = bits(ld_addr_hitvec_lo, 0, 0) @[el2_lsu_bus_buffer.scala 415:93] - node _T_214 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_215 = and(_T_213, _T_214) @[el2_lsu_bus_buffer.scala 415:97] - node _T_216 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_217 = and(_T_215, _T_216) @[el2_lsu_bus_buffer.scala 415:116] - node _T_218 = bits(ld_addr_hitvec_lo, 1, 1) @[el2_lsu_bus_buffer.scala 415:93] - node _T_219 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_220 = and(_T_218, _T_219) @[el2_lsu_bus_buffer.scala 415:97] - node _T_221 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_222 = and(_T_220, _T_221) @[el2_lsu_bus_buffer.scala 415:116] - node _T_223 = bits(ld_addr_hitvec_lo, 2, 2) @[el2_lsu_bus_buffer.scala 415:93] - node _T_224 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_225 = and(_T_223, _T_224) @[el2_lsu_bus_buffer.scala 415:97] - node _T_226 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_227 = and(_T_225, _T_226) @[el2_lsu_bus_buffer.scala 415:116] - node _T_228 = bits(ld_addr_hitvec_lo, 3, 3) @[el2_lsu_bus_buffer.scala 415:93] - node _T_229 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 415:112] - node _T_230 = and(_T_228, _T_229) @[el2_lsu_bus_buffer.scala 415:97] - node _T_231 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_buffer.scala 415:134] - node _T_232 = and(_T_230, _T_231) @[el2_lsu_bus_buffer.scala 415:116] - node _T_233 = cat(_T_232, _T_227) @[Cat.scala 29:58] - node _T_234 = cat(_T_233, _T_222) @[Cat.scala 29:58] - node _T_235 = cat(_T_234, _T_217) @[Cat.scala 29:58] - ld_byte_hitvec_lo[0] <= _T_166 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[1] <= _T_189 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[2] <= _T_212 @[el2_lsu_bus_buffer.scala 415:28] - ld_byte_hitvec_lo[3] <= _T_235 @[el2_lsu_bus_buffer.scala 415:28] - node _T_236 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_237 = bits(buf_byteen[0], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_238 = and(_T_236, _T_237) @[el2_lsu_bus_buffer.scala 416:97] - node _T_239 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_240 = and(_T_238, _T_239) @[el2_lsu_bus_buffer.scala 416:116] - node _T_241 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_242 = bits(buf_byteen[1], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_243 = and(_T_241, _T_242) @[el2_lsu_bus_buffer.scala 416:97] - node _T_244 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_245 = and(_T_243, _T_244) @[el2_lsu_bus_buffer.scala 416:116] - node _T_246 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_247 = bits(buf_byteen[2], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_248 = and(_T_246, _T_247) @[el2_lsu_bus_buffer.scala 416:97] - node _T_249 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_250 = and(_T_248, _T_249) @[el2_lsu_bus_buffer.scala 416:116] - node _T_251 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_252 = bits(buf_byteen[3], 0, 0) @[el2_lsu_bus_buffer.scala 416:112] - node _T_253 = and(_T_251, _T_252) @[el2_lsu_bus_buffer.scala 416:97] - node _T_254 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_buffer.scala 416:134] - node _T_255 = and(_T_253, _T_254) @[el2_lsu_bus_buffer.scala 416:116] - node _T_256 = cat(_T_255, _T_250) @[Cat.scala 29:58] - node _T_257 = cat(_T_256, _T_245) @[Cat.scala 29:58] - node _T_258 = cat(_T_257, _T_240) @[Cat.scala 29:58] - node _T_259 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_260 = bits(buf_byteen[0], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_261 = and(_T_259, _T_260) @[el2_lsu_bus_buffer.scala 416:97] - node _T_262 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_263 = and(_T_261, _T_262) @[el2_lsu_bus_buffer.scala 416:116] - node _T_264 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_265 = bits(buf_byteen[1], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_266 = and(_T_264, _T_265) @[el2_lsu_bus_buffer.scala 416:97] - node _T_267 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_268 = and(_T_266, _T_267) @[el2_lsu_bus_buffer.scala 416:116] - node _T_269 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_270 = bits(buf_byteen[2], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_271 = and(_T_269, _T_270) @[el2_lsu_bus_buffer.scala 416:97] - node _T_272 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_273 = and(_T_271, _T_272) @[el2_lsu_bus_buffer.scala 416:116] - node _T_274 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_275 = bits(buf_byteen[3], 1, 1) @[el2_lsu_bus_buffer.scala 416:112] - node _T_276 = and(_T_274, _T_275) @[el2_lsu_bus_buffer.scala 416:97] - node _T_277 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_buffer.scala 416:134] - node _T_278 = and(_T_276, _T_277) @[el2_lsu_bus_buffer.scala 416:116] - node _T_279 = cat(_T_278, _T_273) @[Cat.scala 29:58] - node _T_280 = cat(_T_279, _T_268) @[Cat.scala 29:58] - node _T_281 = cat(_T_280, _T_263) @[Cat.scala 29:58] - node _T_282 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_283 = bits(buf_byteen[0], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_284 = and(_T_282, _T_283) @[el2_lsu_bus_buffer.scala 416:97] - node _T_285 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_286 = and(_T_284, _T_285) @[el2_lsu_bus_buffer.scala 416:116] - node _T_287 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_288 = bits(buf_byteen[1], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_289 = and(_T_287, _T_288) @[el2_lsu_bus_buffer.scala 416:97] - node _T_290 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_291 = and(_T_289, _T_290) @[el2_lsu_bus_buffer.scala 416:116] - node _T_292 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_293 = bits(buf_byteen[2], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_294 = and(_T_292, _T_293) @[el2_lsu_bus_buffer.scala 416:97] - node _T_295 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_296 = and(_T_294, _T_295) @[el2_lsu_bus_buffer.scala 416:116] - node _T_297 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_298 = bits(buf_byteen[3], 2, 2) @[el2_lsu_bus_buffer.scala 416:112] - node _T_299 = and(_T_297, _T_298) @[el2_lsu_bus_buffer.scala 416:97] - node _T_300 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_buffer.scala 416:134] - node _T_301 = and(_T_299, _T_300) @[el2_lsu_bus_buffer.scala 416:116] - node _T_302 = cat(_T_301, _T_296) @[Cat.scala 29:58] - node _T_303 = cat(_T_302, _T_291) @[Cat.scala 29:58] - node _T_304 = cat(_T_303, _T_286) @[Cat.scala 29:58] - node _T_305 = bits(ld_addr_hitvec_hi, 0, 0) @[el2_lsu_bus_buffer.scala 416:93] - node _T_306 = bits(buf_byteen[0], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_307 = and(_T_305, _T_306) @[el2_lsu_bus_buffer.scala 416:97] - node _T_308 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_309 = and(_T_307, _T_308) @[el2_lsu_bus_buffer.scala 416:116] - node _T_310 = bits(ld_addr_hitvec_hi, 1, 1) @[el2_lsu_bus_buffer.scala 416:93] - node _T_311 = bits(buf_byteen[1], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_312 = and(_T_310, _T_311) @[el2_lsu_bus_buffer.scala 416:97] - node _T_313 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_314 = and(_T_312, _T_313) @[el2_lsu_bus_buffer.scala 416:116] - node _T_315 = bits(ld_addr_hitvec_hi, 2, 2) @[el2_lsu_bus_buffer.scala 416:93] - node _T_316 = bits(buf_byteen[2], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_317 = and(_T_315, _T_316) @[el2_lsu_bus_buffer.scala 416:97] - node _T_318 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_319 = and(_T_317, _T_318) @[el2_lsu_bus_buffer.scala 416:116] - node _T_320 = bits(ld_addr_hitvec_hi, 3, 3) @[el2_lsu_bus_buffer.scala 416:93] - node _T_321 = bits(buf_byteen[3], 3, 3) @[el2_lsu_bus_buffer.scala 416:112] - node _T_322 = and(_T_320, _T_321) @[el2_lsu_bus_buffer.scala 416:97] - node _T_323 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_buffer.scala 416:134] - node _T_324 = and(_T_322, _T_323) @[el2_lsu_bus_buffer.scala 416:116] - node _T_325 = cat(_T_324, _T_319) @[Cat.scala 29:58] - node _T_326 = cat(_T_325, _T_314) @[Cat.scala 29:58] - node _T_327 = cat(_T_326, _T_309) @[Cat.scala 29:58] - ld_byte_hitvec_hi[0] <= _T_258 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[1] <= _T_281 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[2] <= _T_304 @[el2_lsu_bus_buffer.scala 416:28] - ld_byte_hitvec_hi[3] <= _T_327 @[el2_lsu_bus_buffer.scala 416:28] - node _T_328 = bits(ld_byte_hitvec_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_329 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_330 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_331 = cat(_T_330, _T_329) @[el2_lsu_bus_buffer.scala 418:147] - node _T_332 = and(ld_byte_hitvec_lo[0], _T_331) @[el2_lsu_bus_buffer.scala 418:126] - node _T_333 = orr(_T_332) @[el2_lsu_bus_buffer.scala 418:155] - node _T_334 = not(_T_333) @[el2_lsu_bus_buffer.scala 418:102] - node _T_335 = and(_T_328, _T_334) @[el2_lsu_bus_buffer.scala 418:100] - node _T_336 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_337 = not(_T_336) @[el2_lsu_bus_buffer.scala 418:162] - node _T_338 = and(_T_335, _T_337) @[el2_lsu_bus_buffer.scala 418:160] - node _T_339 = bits(ld_byte_hitvec_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_340 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_341 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_342 = cat(_T_341, _T_340) @[el2_lsu_bus_buffer.scala 418:147] - node _T_343 = and(ld_byte_hitvec_lo[0], _T_342) @[el2_lsu_bus_buffer.scala 418:126] - node _T_344 = orr(_T_343) @[el2_lsu_bus_buffer.scala 418:155] - node _T_345 = not(_T_344) @[el2_lsu_bus_buffer.scala 418:102] - node _T_346 = and(_T_339, _T_345) @[el2_lsu_bus_buffer.scala 418:100] - node _T_347 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_348 = not(_T_347) @[el2_lsu_bus_buffer.scala 418:162] - node _T_349 = and(_T_346, _T_348) @[el2_lsu_bus_buffer.scala 418:160] - node _T_350 = bits(ld_byte_hitvec_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_351 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_352 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_353 = cat(_T_352, _T_351) @[el2_lsu_bus_buffer.scala 418:147] - node _T_354 = and(ld_byte_hitvec_lo[0], _T_353) @[el2_lsu_bus_buffer.scala 418:126] - node _T_355 = orr(_T_354) @[el2_lsu_bus_buffer.scala 418:155] - node _T_356 = not(_T_355) @[el2_lsu_bus_buffer.scala 418:102] - node _T_357 = and(_T_350, _T_356) @[el2_lsu_bus_buffer.scala 418:100] - node _T_358 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_359 = not(_T_358) @[el2_lsu_bus_buffer.scala 418:162] - node _T_360 = and(_T_357, _T_359) @[el2_lsu_bus_buffer.scala 418:160] - node _T_361 = bits(ld_byte_hitvec_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_362 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_363 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_364 = cat(_T_363, _T_362) @[el2_lsu_bus_buffer.scala 418:147] - node _T_365 = and(ld_byte_hitvec_lo[0], _T_364) @[el2_lsu_bus_buffer.scala 418:126] - node _T_366 = orr(_T_365) @[el2_lsu_bus_buffer.scala 418:155] - node _T_367 = not(_T_366) @[el2_lsu_bus_buffer.scala 418:102] - node _T_368 = and(_T_361, _T_367) @[el2_lsu_bus_buffer.scala 418:100] - node _T_369 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 418:182] - node _T_370 = not(_T_369) @[el2_lsu_bus_buffer.scala 418:162] - node _T_371 = and(_T_368, _T_370) @[el2_lsu_bus_buffer.scala 418:160] - node _T_372 = cat(_T_371, _T_360) @[Cat.scala 29:58] - node _T_373 = cat(_T_372, _T_349) @[Cat.scala 29:58] - node _T_374 = cat(_T_373, _T_338) @[Cat.scala 29:58] - node _T_375 = bits(ld_byte_hitvec_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_376 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_377 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_378 = cat(_T_377, _T_376) @[el2_lsu_bus_buffer.scala 418:147] - node _T_379 = and(ld_byte_hitvec_lo[1], _T_378) @[el2_lsu_bus_buffer.scala 418:126] - node _T_380 = orr(_T_379) @[el2_lsu_bus_buffer.scala 418:155] - node _T_381 = not(_T_380) @[el2_lsu_bus_buffer.scala 418:102] - node _T_382 = and(_T_375, _T_381) @[el2_lsu_bus_buffer.scala 418:100] - node _T_383 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_384 = not(_T_383) @[el2_lsu_bus_buffer.scala 418:162] - node _T_385 = and(_T_382, _T_384) @[el2_lsu_bus_buffer.scala 418:160] - node _T_386 = bits(ld_byte_hitvec_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_387 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_388 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_389 = cat(_T_388, _T_387) @[el2_lsu_bus_buffer.scala 418:147] - node _T_390 = and(ld_byte_hitvec_lo[1], _T_389) @[el2_lsu_bus_buffer.scala 418:126] - node _T_391 = orr(_T_390) @[el2_lsu_bus_buffer.scala 418:155] - node _T_392 = not(_T_391) @[el2_lsu_bus_buffer.scala 418:102] - node _T_393 = and(_T_386, _T_392) @[el2_lsu_bus_buffer.scala 418:100] - node _T_394 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_395 = not(_T_394) @[el2_lsu_bus_buffer.scala 418:162] - node _T_396 = and(_T_393, _T_395) @[el2_lsu_bus_buffer.scala 418:160] - node _T_397 = bits(ld_byte_hitvec_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_398 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_399 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_400 = cat(_T_399, _T_398) @[el2_lsu_bus_buffer.scala 418:147] - node _T_401 = and(ld_byte_hitvec_lo[1], _T_400) @[el2_lsu_bus_buffer.scala 418:126] - node _T_402 = orr(_T_401) @[el2_lsu_bus_buffer.scala 418:155] - node _T_403 = not(_T_402) @[el2_lsu_bus_buffer.scala 418:102] - node _T_404 = and(_T_397, _T_403) @[el2_lsu_bus_buffer.scala 418:100] - node _T_405 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_406 = not(_T_405) @[el2_lsu_bus_buffer.scala 418:162] - node _T_407 = and(_T_404, _T_406) @[el2_lsu_bus_buffer.scala 418:160] - node _T_408 = bits(ld_byte_hitvec_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_409 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_410 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_411 = cat(_T_410, _T_409) @[el2_lsu_bus_buffer.scala 418:147] - node _T_412 = and(ld_byte_hitvec_lo[1], _T_411) @[el2_lsu_bus_buffer.scala 418:126] - node _T_413 = orr(_T_412) @[el2_lsu_bus_buffer.scala 418:155] - node _T_414 = not(_T_413) @[el2_lsu_bus_buffer.scala 418:102] - node _T_415 = and(_T_408, _T_414) @[el2_lsu_bus_buffer.scala 418:100] - node _T_416 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 418:182] - node _T_417 = not(_T_416) @[el2_lsu_bus_buffer.scala 418:162] - node _T_418 = and(_T_415, _T_417) @[el2_lsu_bus_buffer.scala 418:160] - node _T_419 = cat(_T_418, _T_407) @[Cat.scala 29:58] - node _T_420 = cat(_T_419, _T_396) @[Cat.scala 29:58] - node _T_421 = cat(_T_420, _T_385) @[Cat.scala 29:58] - node _T_422 = bits(ld_byte_hitvec_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_423 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_424 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_425 = cat(_T_424, _T_423) @[el2_lsu_bus_buffer.scala 418:147] - node _T_426 = and(ld_byte_hitvec_lo[2], _T_425) @[el2_lsu_bus_buffer.scala 418:126] - node _T_427 = orr(_T_426) @[el2_lsu_bus_buffer.scala 418:155] - node _T_428 = not(_T_427) @[el2_lsu_bus_buffer.scala 418:102] - node _T_429 = and(_T_422, _T_428) @[el2_lsu_bus_buffer.scala 418:100] - node _T_430 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_431 = not(_T_430) @[el2_lsu_bus_buffer.scala 418:162] - node _T_432 = and(_T_429, _T_431) @[el2_lsu_bus_buffer.scala 418:160] - node _T_433 = bits(ld_byte_hitvec_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_434 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_435 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_436 = cat(_T_435, _T_434) @[el2_lsu_bus_buffer.scala 418:147] - node _T_437 = and(ld_byte_hitvec_lo[2], _T_436) @[el2_lsu_bus_buffer.scala 418:126] - node _T_438 = orr(_T_437) @[el2_lsu_bus_buffer.scala 418:155] - node _T_439 = not(_T_438) @[el2_lsu_bus_buffer.scala 418:102] - node _T_440 = and(_T_433, _T_439) @[el2_lsu_bus_buffer.scala 418:100] - node _T_441 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_442 = not(_T_441) @[el2_lsu_bus_buffer.scala 418:162] - node _T_443 = and(_T_440, _T_442) @[el2_lsu_bus_buffer.scala 418:160] - node _T_444 = bits(ld_byte_hitvec_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_445 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_446 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_447 = cat(_T_446, _T_445) @[el2_lsu_bus_buffer.scala 418:147] - node _T_448 = and(ld_byte_hitvec_lo[2], _T_447) @[el2_lsu_bus_buffer.scala 418:126] - node _T_449 = orr(_T_448) @[el2_lsu_bus_buffer.scala 418:155] - node _T_450 = not(_T_449) @[el2_lsu_bus_buffer.scala 418:102] - node _T_451 = and(_T_444, _T_450) @[el2_lsu_bus_buffer.scala 418:100] - node _T_452 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_453 = not(_T_452) @[el2_lsu_bus_buffer.scala 418:162] - node _T_454 = and(_T_451, _T_453) @[el2_lsu_bus_buffer.scala 418:160] - node _T_455 = bits(ld_byte_hitvec_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_456 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_457 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_458 = cat(_T_457, _T_456) @[el2_lsu_bus_buffer.scala 418:147] - node _T_459 = and(ld_byte_hitvec_lo[2], _T_458) @[el2_lsu_bus_buffer.scala 418:126] - node _T_460 = orr(_T_459) @[el2_lsu_bus_buffer.scala 418:155] - node _T_461 = not(_T_460) @[el2_lsu_bus_buffer.scala 418:102] - node _T_462 = and(_T_455, _T_461) @[el2_lsu_bus_buffer.scala 418:100] - node _T_463 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 418:182] - node _T_464 = not(_T_463) @[el2_lsu_bus_buffer.scala 418:162] - node _T_465 = and(_T_462, _T_464) @[el2_lsu_bus_buffer.scala 418:160] - node _T_466 = cat(_T_465, _T_454) @[Cat.scala 29:58] - node _T_467 = cat(_T_466, _T_443) @[Cat.scala 29:58] - node _T_468 = cat(_T_467, _T_432) @[Cat.scala 29:58] - node _T_469 = bits(ld_byte_hitvec_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 418:96] - node _T_470 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_471 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_472 = cat(_T_471, _T_470) @[el2_lsu_bus_buffer.scala 418:147] - node _T_473 = and(ld_byte_hitvec_lo[3], _T_472) @[el2_lsu_bus_buffer.scala 418:126] - node _T_474 = orr(_T_473) @[el2_lsu_bus_buffer.scala 418:155] - node _T_475 = not(_T_474) @[el2_lsu_bus_buffer.scala 418:102] - node _T_476 = and(_T_469, _T_475) @[el2_lsu_bus_buffer.scala 418:100] - node _T_477 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_478 = not(_T_477) @[el2_lsu_bus_buffer.scala 418:162] - node _T_479 = and(_T_476, _T_478) @[el2_lsu_bus_buffer.scala 418:160] - node _T_480 = bits(ld_byte_hitvec_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 418:96] - node _T_481 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_482 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_483 = cat(_T_482, _T_481) @[el2_lsu_bus_buffer.scala 418:147] - node _T_484 = and(ld_byte_hitvec_lo[3], _T_483) @[el2_lsu_bus_buffer.scala 418:126] - node _T_485 = orr(_T_484) @[el2_lsu_bus_buffer.scala 418:155] - node _T_486 = not(_T_485) @[el2_lsu_bus_buffer.scala 418:102] - node _T_487 = and(_T_480, _T_486) @[el2_lsu_bus_buffer.scala 418:100] - node _T_488 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_489 = not(_T_488) @[el2_lsu_bus_buffer.scala 418:162] - node _T_490 = and(_T_487, _T_489) @[el2_lsu_bus_buffer.scala 418:160] - node _T_491 = bits(ld_byte_hitvec_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 418:96] - node _T_492 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_493 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_494 = cat(_T_493, _T_492) @[el2_lsu_bus_buffer.scala 418:147] - node _T_495 = and(ld_byte_hitvec_lo[3], _T_494) @[el2_lsu_bus_buffer.scala 418:126] - node _T_496 = orr(_T_495) @[el2_lsu_bus_buffer.scala 418:155] - node _T_497 = not(_T_496) @[el2_lsu_bus_buffer.scala 418:102] - node _T_498 = and(_T_491, _T_497) @[el2_lsu_bus_buffer.scala 418:100] - node _T_499 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_500 = not(_T_499) @[el2_lsu_bus_buffer.scala 418:162] - node _T_501 = and(_T_498, _T_500) @[el2_lsu_bus_buffer.scala 418:160] - node _T_502 = bits(ld_byte_hitvec_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 418:96] - node _T_503 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_504 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 418:147] - node _T_505 = cat(_T_504, _T_503) @[el2_lsu_bus_buffer.scala 418:147] - node _T_506 = and(ld_byte_hitvec_lo[3], _T_505) @[el2_lsu_bus_buffer.scala 418:126] - node _T_507 = orr(_T_506) @[el2_lsu_bus_buffer.scala 418:155] - node _T_508 = not(_T_507) @[el2_lsu_bus_buffer.scala 418:102] - node _T_509 = and(_T_502, _T_508) @[el2_lsu_bus_buffer.scala 418:100] - node _T_510 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 418:182] - node _T_511 = not(_T_510) @[el2_lsu_bus_buffer.scala 418:162] - node _T_512 = and(_T_509, _T_511) @[el2_lsu_bus_buffer.scala 418:160] - node _T_513 = cat(_T_512, _T_501) @[Cat.scala 29:58] - node _T_514 = cat(_T_513, _T_490) @[Cat.scala 29:58] - node _T_515 = cat(_T_514, _T_479) @[Cat.scala 29:58] - ld_byte_hitvecfn_lo[0] <= _T_374 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[1] <= _T_421 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[2] <= _T_468 @[el2_lsu_bus_buffer.scala 418:28] - ld_byte_hitvecfn_lo[3] <= _T_515 @[el2_lsu_bus_buffer.scala 418:28] - node _T_516 = bits(ld_byte_hitvec_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_517 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_518 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_519 = cat(_T_518, _T_517) @[el2_lsu_bus_buffer.scala 419:147] - node _T_520 = and(ld_byte_hitvec_hi[0], _T_519) @[el2_lsu_bus_buffer.scala 419:126] - node _T_521 = orr(_T_520) @[el2_lsu_bus_buffer.scala 419:155] - node _T_522 = not(_T_521) @[el2_lsu_bus_buffer.scala 419:102] - node _T_523 = and(_T_516, _T_522) @[el2_lsu_bus_buffer.scala 419:100] - node _T_524 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_525 = not(_T_524) @[el2_lsu_bus_buffer.scala 419:162] - node _T_526 = and(_T_523, _T_525) @[el2_lsu_bus_buffer.scala 419:160] - node _T_527 = bits(ld_byte_hitvec_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_528 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_529 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_530 = cat(_T_529, _T_528) @[el2_lsu_bus_buffer.scala 419:147] - node _T_531 = and(ld_byte_hitvec_hi[0], _T_530) @[el2_lsu_bus_buffer.scala 419:126] - node _T_532 = orr(_T_531) @[el2_lsu_bus_buffer.scala 419:155] - node _T_533 = not(_T_532) @[el2_lsu_bus_buffer.scala 419:102] - node _T_534 = and(_T_527, _T_533) @[el2_lsu_bus_buffer.scala 419:100] - node _T_535 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_536 = not(_T_535) @[el2_lsu_bus_buffer.scala 419:162] - node _T_537 = and(_T_534, _T_536) @[el2_lsu_bus_buffer.scala 419:160] - node _T_538 = bits(ld_byte_hitvec_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_539 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_540 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_541 = cat(_T_540, _T_539) @[el2_lsu_bus_buffer.scala 419:147] - node _T_542 = and(ld_byte_hitvec_hi[0], _T_541) @[el2_lsu_bus_buffer.scala 419:126] - node _T_543 = orr(_T_542) @[el2_lsu_bus_buffer.scala 419:155] - node _T_544 = not(_T_543) @[el2_lsu_bus_buffer.scala 419:102] - node _T_545 = and(_T_538, _T_544) @[el2_lsu_bus_buffer.scala 419:100] - node _T_546 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_547 = not(_T_546) @[el2_lsu_bus_buffer.scala 419:162] - node _T_548 = and(_T_545, _T_547) @[el2_lsu_bus_buffer.scala 419:160] - node _T_549 = bits(ld_byte_hitvec_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_550 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_551 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_552 = cat(_T_551, _T_550) @[el2_lsu_bus_buffer.scala 419:147] - node _T_553 = and(ld_byte_hitvec_hi[0], _T_552) @[el2_lsu_bus_buffer.scala 419:126] - node _T_554 = orr(_T_553) @[el2_lsu_bus_buffer.scala 419:155] - node _T_555 = not(_T_554) @[el2_lsu_bus_buffer.scala 419:102] - node _T_556 = and(_T_549, _T_555) @[el2_lsu_bus_buffer.scala 419:100] - node _T_557 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 419:182] - node _T_558 = not(_T_557) @[el2_lsu_bus_buffer.scala 419:162] - node _T_559 = and(_T_556, _T_558) @[el2_lsu_bus_buffer.scala 419:160] - node _T_560 = cat(_T_559, _T_548) @[Cat.scala 29:58] - node _T_561 = cat(_T_560, _T_537) @[Cat.scala 29:58] - node _T_562 = cat(_T_561, _T_526) @[Cat.scala 29:58] - node _T_563 = bits(ld_byte_hitvec_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_564 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_565 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_566 = cat(_T_565, _T_564) @[el2_lsu_bus_buffer.scala 419:147] - node _T_567 = and(ld_byte_hitvec_hi[1], _T_566) @[el2_lsu_bus_buffer.scala 419:126] - node _T_568 = orr(_T_567) @[el2_lsu_bus_buffer.scala 419:155] - node _T_569 = not(_T_568) @[el2_lsu_bus_buffer.scala 419:102] - node _T_570 = and(_T_563, _T_569) @[el2_lsu_bus_buffer.scala 419:100] - node _T_571 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_572 = not(_T_571) @[el2_lsu_bus_buffer.scala 419:162] - node _T_573 = and(_T_570, _T_572) @[el2_lsu_bus_buffer.scala 419:160] - node _T_574 = bits(ld_byte_hitvec_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_575 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_576 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_577 = cat(_T_576, _T_575) @[el2_lsu_bus_buffer.scala 419:147] - node _T_578 = and(ld_byte_hitvec_hi[1], _T_577) @[el2_lsu_bus_buffer.scala 419:126] - node _T_579 = orr(_T_578) @[el2_lsu_bus_buffer.scala 419:155] - node _T_580 = not(_T_579) @[el2_lsu_bus_buffer.scala 419:102] - node _T_581 = and(_T_574, _T_580) @[el2_lsu_bus_buffer.scala 419:100] - node _T_582 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_583 = not(_T_582) @[el2_lsu_bus_buffer.scala 419:162] - node _T_584 = and(_T_581, _T_583) @[el2_lsu_bus_buffer.scala 419:160] - node _T_585 = bits(ld_byte_hitvec_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_586 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_587 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_588 = cat(_T_587, _T_586) @[el2_lsu_bus_buffer.scala 419:147] - node _T_589 = and(ld_byte_hitvec_hi[1], _T_588) @[el2_lsu_bus_buffer.scala 419:126] - node _T_590 = orr(_T_589) @[el2_lsu_bus_buffer.scala 419:155] - node _T_591 = not(_T_590) @[el2_lsu_bus_buffer.scala 419:102] - node _T_592 = and(_T_585, _T_591) @[el2_lsu_bus_buffer.scala 419:100] - node _T_593 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_594 = not(_T_593) @[el2_lsu_bus_buffer.scala 419:162] - node _T_595 = and(_T_592, _T_594) @[el2_lsu_bus_buffer.scala 419:160] - node _T_596 = bits(ld_byte_hitvec_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_597 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_598 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_599 = cat(_T_598, _T_597) @[el2_lsu_bus_buffer.scala 419:147] - node _T_600 = and(ld_byte_hitvec_hi[1], _T_599) @[el2_lsu_bus_buffer.scala 419:126] - node _T_601 = orr(_T_600) @[el2_lsu_bus_buffer.scala 419:155] - node _T_602 = not(_T_601) @[el2_lsu_bus_buffer.scala 419:102] - node _T_603 = and(_T_596, _T_602) @[el2_lsu_bus_buffer.scala 419:100] - node _T_604 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 419:182] - node _T_605 = not(_T_604) @[el2_lsu_bus_buffer.scala 419:162] - node _T_606 = and(_T_603, _T_605) @[el2_lsu_bus_buffer.scala 419:160] - node _T_607 = cat(_T_606, _T_595) @[Cat.scala 29:58] - node _T_608 = cat(_T_607, _T_584) @[Cat.scala 29:58] - node _T_609 = cat(_T_608, _T_573) @[Cat.scala 29:58] - node _T_610 = bits(ld_byte_hitvec_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_611 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_612 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_613 = cat(_T_612, _T_611) @[el2_lsu_bus_buffer.scala 419:147] - node _T_614 = and(ld_byte_hitvec_hi[2], _T_613) @[el2_lsu_bus_buffer.scala 419:126] - node _T_615 = orr(_T_614) @[el2_lsu_bus_buffer.scala 419:155] - node _T_616 = not(_T_615) @[el2_lsu_bus_buffer.scala 419:102] - node _T_617 = and(_T_610, _T_616) @[el2_lsu_bus_buffer.scala 419:100] - node _T_618 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_619 = not(_T_618) @[el2_lsu_bus_buffer.scala 419:162] - node _T_620 = and(_T_617, _T_619) @[el2_lsu_bus_buffer.scala 419:160] - node _T_621 = bits(ld_byte_hitvec_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_622 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_623 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_624 = cat(_T_623, _T_622) @[el2_lsu_bus_buffer.scala 419:147] - node _T_625 = and(ld_byte_hitvec_hi[2], _T_624) @[el2_lsu_bus_buffer.scala 419:126] - node _T_626 = orr(_T_625) @[el2_lsu_bus_buffer.scala 419:155] - node _T_627 = not(_T_626) @[el2_lsu_bus_buffer.scala 419:102] - node _T_628 = and(_T_621, _T_627) @[el2_lsu_bus_buffer.scala 419:100] - node _T_629 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_630 = not(_T_629) @[el2_lsu_bus_buffer.scala 419:162] - node _T_631 = and(_T_628, _T_630) @[el2_lsu_bus_buffer.scala 419:160] - node _T_632 = bits(ld_byte_hitvec_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_633 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_634 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_635 = cat(_T_634, _T_633) @[el2_lsu_bus_buffer.scala 419:147] - node _T_636 = and(ld_byte_hitvec_hi[2], _T_635) @[el2_lsu_bus_buffer.scala 419:126] - node _T_637 = orr(_T_636) @[el2_lsu_bus_buffer.scala 419:155] - node _T_638 = not(_T_637) @[el2_lsu_bus_buffer.scala 419:102] - node _T_639 = and(_T_632, _T_638) @[el2_lsu_bus_buffer.scala 419:100] - node _T_640 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_641 = not(_T_640) @[el2_lsu_bus_buffer.scala 419:162] - node _T_642 = and(_T_639, _T_641) @[el2_lsu_bus_buffer.scala 419:160] - node _T_643 = bits(ld_byte_hitvec_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_644 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_645 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_646 = cat(_T_645, _T_644) @[el2_lsu_bus_buffer.scala 419:147] - node _T_647 = and(ld_byte_hitvec_hi[2], _T_646) @[el2_lsu_bus_buffer.scala 419:126] - node _T_648 = orr(_T_647) @[el2_lsu_bus_buffer.scala 419:155] - node _T_649 = not(_T_648) @[el2_lsu_bus_buffer.scala 419:102] - node _T_650 = and(_T_643, _T_649) @[el2_lsu_bus_buffer.scala 419:100] - node _T_651 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 419:182] - node _T_652 = not(_T_651) @[el2_lsu_bus_buffer.scala 419:162] - node _T_653 = and(_T_650, _T_652) @[el2_lsu_bus_buffer.scala 419:160] - node _T_654 = cat(_T_653, _T_642) @[Cat.scala 29:58] - node _T_655 = cat(_T_654, _T_631) @[Cat.scala 29:58] - node _T_656 = cat(_T_655, _T_620) @[Cat.scala 29:58] - node _T_657 = bits(ld_byte_hitvec_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 419:96] - node _T_658 = cat(buf_age_younger[0][1], buf_age_younger[0][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_659 = cat(buf_age_younger[0][3], buf_age_younger[0][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_660 = cat(_T_659, _T_658) @[el2_lsu_bus_buffer.scala 419:147] - node _T_661 = and(ld_byte_hitvec_hi[3], _T_660) @[el2_lsu_bus_buffer.scala 419:126] - node _T_662 = orr(_T_661) @[el2_lsu_bus_buffer.scala 419:155] - node _T_663 = not(_T_662) @[el2_lsu_bus_buffer.scala 419:102] - node _T_664 = and(_T_657, _T_663) @[el2_lsu_bus_buffer.scala 419:100] - node _T_665 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_666 = not(_T_665) @[el2_lsu_bus_buffer.scala 419:162] - node _T_667 = and(_T_664, _T_666) @[el2_lsu_bus_buffer.scala 419:160] - node _T_668 = bits(ld_byte_hitvec_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 419:96] - node _T_669 = cat(buf_age_younger[1][1], buf_age_younger[1][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_670 = cat(buf_age_younger[1][3], buf_age_younger[1][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_671 = cat(_T_670, _T_669) @[el2_lsu_bus_buffer.scala 419:147] - node _T_672 = and(ld_byte_hitvec_hi[3], _T_671) @[el2_lsu_bus_buffer.scala 419:126] - node _T_673 = orr(_T_672) @[el2_lsu_bus_buffer.scala 419:155] - node _T_674 = not(_T_673) @[el2_lsu_bus_buffer.scala 419:102] - node _T_675 = and(_T_668, _T_674) @[el2_lsu_bus_buffer.scala 419:100] - node _T_676 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_677 = not(_T_676) @[el2_lsu_bus_buffer.scala 419:162] - node _T_678 = and(_T_675, _T_677) @[el2_lsu_bus_buffer.scala 419:160] - node _T_679 = bits(ld_byte_hitvec_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 419:96] - node _T_680 = cat(buf_age_younger[2][1], buf_age_younger[2][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_681 = cat(buf_age_younger[2][3], buf_age_younger[2][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_682 = cat(_T_681, _T_680) @[el2_lsu_bus_buffer.scala 419:147] - node _T_683 = and(ld_byte_hitvec_hi[3], _T_682) @[el2_lsu_bus_buffer.scala 419:126] - node _T_684 = orr(_T_683) @[el2_lsu_bus_buffer.scala 419:155] - node _T_685 = not(_T_684) @[el2_lsu_bus_buffer.scala 419:102] - node _T_686 = and(_T_679, _T_685) @[el2_lsu_bus_buffer.scala 419:100] - node _T_687 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_688 = not(_T_687) @[el2_lsu_bus_buffer.scala 419:162] - node _T_689 = and(_T_686, _T_688) @[el2_lsu_bus_buffer.scala 419:160] - node _T_690 = bits(ld_byte_hitvec_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 419:96] - node _T_691 = cat(buf_age_younger[3][1], buf_age_younger[3][0]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_692 = cat(buf_age_younger[3][3], buf_age_younger[3][2]) @[el2_lsu_bus_buffer.scala 419:147] - node _T_693 = cat(_T_692, _T_691) @[el2_lsu_bus_buffer.scala 419:147] - node _T_694 = and(ld_byte_hitvec_hi[3], _T_693) @[el2_lsu_bus_buffer.scala 419:126] - node _T_695 = orr(_T_694) @[el2_lsu_bus_buffer.scala 419:155] - node _T_696 = not(_T_695) @[el2_lsu_bus_buffer.scala 419:102] - node _T_697 = and(_T_690, _T_696) @[el2_lsu_bus_buffer.scala 419:100] - node _T_698 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 419:182] - node _T_699 = not(_T_698) @[el2_lsu_bus_buffer.scala 419:162] - node _T_700 = and(_T_697, _T_699) @[el2_lsu_bus_buffer.scala 419:160] - node _T_701 = cat(_T_700, _T_689) @[Cat.scala 29:58] - node _T_702 = cat(_T_701, _T_678) @[Cat.scala 29:58] - node _T_703 = cat(_T_702, _T_667) @[Cat.scala 29:58] - ld_byte_hitvecfn_hi[0] <= _T_562 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[1] <= _T_609 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[2] <= _T_656 @[el2_lsu_bus_buffer.scala 419:28] - ld_byte_hitvecfn_hi[3] <= _T_703 @[el2_lsu_bus_buffer.scala 419:28] - node _T_704 = bits(ld_byte_ibuf_hit_lo, 0, 0) @[el2_lsu_bus_buffer.scala 422:75] - node _T_705 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 422:88] - node _T_706 = bits(ld_byte_hitvecfn_lo[0], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_707 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_708 = bits(ld_byte_hitvecfn_lo[0], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_709 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_710 = bits(ld_byte_hitvecfn_lo[0], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_711 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_712 = bits(ld_byte_hitvecfn_lo[0], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_713 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 422:172] - node _T_714 = mux(_T_706, _T_707, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_715 = mux(_T_708, _T_709, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_716 = mux(_T_710, _T_711, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_717 = mux(_T_712, _T_713, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_718 = or(_T_714, _T_715) @[Mux.scala 27:72] - node _T_719 = or(_T_718, _T_716) @[Mux.scala 27:72] - node _T_720 = or(_T_719, _T_717) @[Mux.scala 27:72] - wire _T_721 : UInt<8> @[Mux.scala 27:72] - _T_721 <= _T_720 @[Mux.scala 27:72] - node _T_722 = mux(_T_704, _T_705, _T_721) @[el2_lsu_bus_buffer.scala 422:55] - node _T_723 = bits(ld_byte_ibuf_hit_lo, 1, 1) @[el2_lsu_bus_buffer.scala 422:75] - node _T_724 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 422:88] - node _T_725 = bits(ld_byte_hitvecfn_lo[1], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_726 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_727 = bits(ld_byte_hitvecfn_lo[1], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_728 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_729 = bits(ld_byte_hitvecfn_lo[1], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_730 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_731 = bits(ld_byte_hitvecfn_lo[1], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_732 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 422:172] - node _T_733 = mux(_T_725, _T_726, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_734 = mux(_T_727, _T_728, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_735 = mux(_T_729, _T_730, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_736 = mux(_T_731, _T_732, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_737 = or(_T_733, _T_734) @[Mux.scala 27:72] - node _T_738 = or(_T_737, _T_735) @[Mux.scala 27:72] - node _T_739 = or(_T_738, _T_736) @[Mux.scala 27:72] - wire _T_740 : UInt<8> @[Mux.scala 27:72] - _T_740 <= _T_739 @[Mux.scala 27:72] - node _T_741 = mux(_T_723, _T_724, _T_740) @[el2_lsu_bus_buffer.scala 422:55] - node _T_742 = bits(ld_byte_ibuf_hit_lo, 2, 2) @[el2_lsu_bus_buffer.scala 422:75] - node _T_743 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 422:88] - node _T_744 = bits(ld_byte_hitvecfn_lo[2], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_745 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_746 = bits(ld_byte_hitvecfn_lo[2], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_747 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_748 = bits(ld_byte_hitvecfn_lo[2], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_749 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_750 = bits(ld_byte_hitvecfn_lo[2], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_751 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 422:172] - node _T_752 = mux(_T_744, _T_745, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_753 = mux(_T_746, _T_747, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_754 = mux(_T_748, _T_749, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_755 = mux(_T_750, _T_751, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_756 = or(_T_752, _T_753) @[Mux.scala 27:72] - node _T_757 = or(_T_756, _T_754) @[Mux.scala 27:72] - node _T_758 = or(_T_757, _T_755) @[Mux.scala 27:72] - wire _T_759 : UInt<8> @[Mux.scala 27:72] - _T_759 <= _T_758 @[Mux.scala 27:72] - node _T_760 = mux(_T_742, _T_743, _T_759) @[el2_lsu_bus_buffer.scala 422:55] - node _T_761 = bits(ld_byte_ibuf_hit_lo, 3, 3) @[el2_lsu_bus_buffer.scala 422:75] - node _T_762 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 422:88] - node _T_763 = bits(ld_byte_hitvecfn_lo[3], 0, 0) @[el2_lsu_bus_buffer.scala 422:153] - node _T_764 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_765 = bits(ld_byte_hitvecfn_lo[3], 1, 1) @[el2_lsu_bus_buffer.scala 422:153] - node _T_766 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_767 = bits(ld_byte_hitvecfn_lo[3], 2, 2) @[el2_lsu_bus_buffer.scala 422:153] - node _T_768 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_769 = bits(ld_byte_hitvecfn_lo[3], 3, 3) @[el2_lsu_bus_buffer.scala 422:153] - node _T_770 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 422:172] - node _T_771 = mux(_T_763, _T_764, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_772 = mux(_T_765, _T_766, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_773 = mux(_T_767, _T_768, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_774 = mux(_T_769, _T_770, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_775 = or(_T_771, _T_772) @[Mux.scala 27:72] - node _T_776 = or(_T_775, _T_773) @[Mux.scala 27:72] - node _T_777 = or(_T_776, _T_774) @[Mux.scala 27:72] - wire _T_778 : UInt<8> @[Mux.scala 27:72] - _T_778 <= _T_777 @[Mux.scala 27:72] - node _T_779 = mux(_T_761, _T_762, _T_778) @[el2_lsu_bus_buffer.scala 422:55] - node _T_780 = cat(_T_779, _T_760) @[Cat.scala 29:58] - node _T_781 = cat(_T_780, _T_741) @[Cat.scala 29:58] - node _T_782 = cat(_T_781, _T_722) @[Cat.scala 29:58] - io.ld_fwddata_buf_lo <= _T_782 @[el2_lsu_bus_buffer.scala 422:28] - node _T_783 = bits(ld_byte_ibuf_hit_hi, 0, 0) @[el2_lsu_bus_buffer.scala 423:75] - node _T_784 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 423:88] - node _T_785 = bits(ld_byte_hitvecfn_hi[0], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_786 = bits(buf_data[0], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_787 = bits(ld_byte_hitvecfn_hi[0], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_788 = bits(buf_data[1], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_789 = bits(ld_byte_hitvecfn_hi[0], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_790 = bits(buf_data[2], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_791 = bits(ld_byte_hitvecfn_hi[0], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_792 = bits(buf_data[3], 7, 0) @[el2_lsu_bus_buffer.scala 423:172] - node _T_793 = mux(_T_785, _T_786, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_794 = mux(_T_787, _T_788, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_795 = mux(_T_789, _T_790, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_796 = mux(_T_791, _T_792, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_797 = or(_T_793, _T_794) @[Mux.scala 27:72] - node _T_798 = or(_T_797, _T_795) @[Mux.scala 27:72] - node _T_799 = or(_T_798, _T_796) @[Mux.scala 27:72] - wire _T_800 : UInt<8> @[Mux.scala 27:72] - _T_800 <= _T_799 @[Mux.scala 27:72] - node _T_801 = mux(_T_783, _T_784, _T_800) @[el2_lsu_bus_buffer.scala 423:55] - node _T_802 = bits(ld_byte_ibuf_hit_hi, 1, 1) @[el2_lsu_bus_buffer.scala 423:75] - node _T_803 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 423:88] - node _T_804 = bits(ld_byte_hitvecfn_hi[1], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_805 = bits(buf_data[0], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_806 = bits(ld_byte_hitvecfn_hi[1], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_807 = bits(buf_data[1], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_808 = bits(ld_byte_hitvecfn_hi[1], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_809 = bits(buf_data[2], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_810 = bits(ld_byte_hitvecfn_hi[1], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_811 = bits(buf_data[3], 15, 8) @[el2_lsu_bus_buffer.scala 423:172] - node _T_812 = mux(_T_804, _T_805, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_813 = mux(_T_806, _T_807, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_814 = mux(_T_808, _T_809, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_815 = mux(_T_810, _T_811, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_816 = or(_T_812, _T_813) @[Mux.scala 27:72] - node _T_817 = or(_T_816, _T_814) @[Mux.scala 27:72] - node _T_818 = or(_T_817, _T_815) @[Mux.scala 27:72] - wire _T_819 : UInt<8> @[Mux.scala 27:72] - _T_819 <= _T_818 @[Mux.scala 27:72] - node _T_820 = mux(_T_802, _T_803, _T_819) @[el2_lsu_bus_buffer.scala 423:55] - node _T_821 = bits(ld_byte_ibuf_hit_hi, 2, 2) @[el2_lsu_bus_buffer.scala 423:75] - node _T_822 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 423:88] - node _T_823 = bits(ld_byte_hitvecfn_hi[2], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_824 = bits(buf_data[0], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_825 = bits(ld_byte_hitvecfn_hi[2], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_826 = bits(buf_data[1], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_827 = bits(ld_byte_hitvecfn_hi[2], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_828 = bits(buf_data[2], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_829 = bits(ld_byte_hitvecfn_hi[2], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_830 = bits(buf_data[3], 23, 16) @[el2_lsu_bus_buffer.scala 423:172] - node _T_831 = mux(_T_823, _T_824, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_832 = mux(_T_825, _T_826, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_833 = mux(_T_827, _T_828, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_834 = mux(_T_829, _T_830, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_835 = or(_T_831, _T_832) @[Mux.scala 27:72] - node _T_836 = or(_T_835, _T_833) @[Mux.scala 27:72] - node _T_837 = or(_T_836, _T_834) @[Mux.scala 27:72] - wire _T_838 : UInt<8> @[Mux.scala 27:72] - _T_838 <= _T_837 @[Mux.scala 27:72] - node _T_839 = mux(_T_821, _T_822, _T_838) @[el2_lsu_bus_buffer.scala 423:55] - node _T_840 = bits(ld_byte_ibuf_hit_hi, 3, 3) @[el2_lsu_bus_buffer.scala 423:75] - node _T_841 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 423:88] - node _T_842 = bits(ld_byte_hitvecfn_hi[3], 0, 0) @[el2_lsu_bus_buffer.scala 423:153] - node _T_843 = bits(buf_data[0], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_844 = bits(ld_byte_hitvecfn_hi[3], 1, 1) @[el2_lsu_bus_buffer.scala 423:153] - node _T_845 = bits(buf_data[1], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_846 = bits(ld_byte_hitvecfn_hi[3], 2, 2) @[el2_lsu_bus_buffer.scala 423:153] - node _T_847 = bits(buf_data[2], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_848 = bits(ld_byte_hitvecfn_hi[3], 3, 3) @[el2_lsu_bus_buffer.scala 423:153] - node _T_849 = bits(buf_data[3], 31, 24) @[el2_lsu_bus_buffer.scala 423:172] - node _T_850 = mux(_T_842, _T_843, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_851 = mux(_T_844, _T_845, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_852 = mux(_T_846, _T_847, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_853 = mux(_T_848, _T_849, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_854 = or(_T_850, _T_851) @[Mux.scala 27:72] - node _T_855 = or(_T_854, _T_852) @[Mux.scala 27:72] - node _T_856 = or(_T_855, _T_853) @[Mux.scala 27:72] - wire _T_857 : UInt<8> @[Mux.scala 27:72] - _T_857 <= _T_856 @[Mux.scala 27:72] - node _T_858 = mux(_T_840, _T_841, _T_857) @[el2_lsu_bus_buffer.scala 423:55] - node _T_859 = cat(_T_858, _T_839) @[Cat.scala 29:58] - node _T_860 = cat(_T_859, _T_820) @[Cat.scala 29:58] - node _T_861 = cat(_T_860, _T_801) @[Cat.scala 29:58] - io.ld_fwddata_buf_hi <= _T_861 @[el2_lsu_bus_buffer.scala 423:28] - node _T_862 = or(io.dec_tlu_wb_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:64] - bus_coalescing_disable <= _T_862 @[el2_lsu_bus_buffer.scala 426:28] - node _T_863 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_bus_buffer.scala 428:55] - node _T_864 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_bus_buffer.scala 429:55] - node _T_865 = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_bus_buffer.scala 430:53] - node _T_866 = mux(_T_863, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_867 = mux(_T_864, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_868 = mux(_T_865, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_869 = or(_T_866, _T_867) @[Mux.scala 27:72] - node _T_870 = or(_T_869, _T_868) @[Mux.scala 27:72] - wire _T_871 : UInt<4> @[Mux.scala 27:72] - _T_871 <= _T_870 @[Mux.scala 27:72] - ldst_byteen_r <= _T_871 @[el2_lsu_bus_buffer.scala 427:28] - node _T_872 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] - node _T_873 = bits(ldst_byteen_r, 3, 0) @[el2_lsu_bus_buffer.scala 432:64] - node _T_874 = cat(_T_872, _T_873) @[Cat.scala 29:58] - node _T_875 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 432:87] - node ldst_byteen_extended_r = dshl(_T_874, _T_875) @[el2_lsu_bus_buffer.scala 432:71] - node _T_876 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_877 = bits(io.store_data_r, 31, 0) @[el2_lsu_bus_buffer.scala 433:67] - node _T_878 = cat(_T_876, _T_877) @[Cat.scala 29:58] - node _T_879 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 433:96] - node _T_880 = mul(UInt<4>("h08"), _T_879) @[el2_lsu_bus_buffer.scala 433:82] - node store_data_extended_r = dshl(_T_878, _T_880) @[el2_lsu_bus_buffer.scala 433:75] - node _T_881 = bits(ldst_byteen_extended_r, 7, 4) @[el2_lsu_bus_buffer.scala 434:58] - ldst_byteen_hi_r <= _T_881 @[el2_lsu_bus_buffer.scala 434:33] - node _T_882 = bits(ldst_byteen_extended_r, 3, 0) @[el2_lsu_bus_buffer.scala 435:58] - ldst_byteen_lo_r <= _T_882 @[el2_lsu_bus_buffer.scala 435:33] - node _T_883 = bits(store_data_extended_r, 63, 32) @[el2_lsu_bus_buffer.scala 436:57] - store_data_hi_r <= _T_883 @[el2_lsu_bus_buffer.scala 436:33] - node _T_884 = bits(store_data_extended_r, 31, 0) @[el2_lsu_bus_buffer.scala 437:57] - store_data_lo_r <= _T_884 @[el2_lsu_bus_buffer.scala 437:33] - node _T_885 = bits(io.lsu_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 438:49] - node _T_886 = bits(io.end_addr_r, 3, 3) @[el2_lsu_bus_buffer.scala 438:70] - node _T_887 = eq(_T_885, _T_886) @[el2_lsu_bus_buffer.scala 438:53] - ldst_samedw_r <= _T_887 @[el2_lsu_bus_buffer.scala 438:33] - node _T_888 = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_bus_buffer.scala 440:59] - node _T_889 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_bus_buffer.scala 441:61] - node _T_890 = bits(io.lsu_addr_r, 0, 0) @[el2_lsu_bus_buffer.scala 441:85] - node _T_891 = eq(_T_890, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 441:96] - node _T_892 = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_bus_buffer.scala 442:61] - node _T_893 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_buffer.scala 442:85] - node _T_894 = eq(_T_893, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 442:98] - node _T_895 = mux(_T_888, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_896 = mux(_T_889, _T_891, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_897 = mux(_T_892, _T_894, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_898 = or(_T_895, _T_896) @[Mux.scala 27:72] - node _T_899 = or(_T_898, _T_897) @[Mux.scala 27:72] - wire _T_900 : UInt<1> @[Mux.scala 27:72] - _T_900 <= _T_899 @[Mux.scala 27:72] - is_aligned_r <= _T_900 @[el2_lsu_bus_buffer.scala 439:33] - node _T_901 = or(io.lsu_pkt_r.load, io.no_word_merge_r) @[el2_lsu_bus_buffer.scala 445:71] - node _T_902 = and(io.lsu_busreq_r, _T_901) @[el2_lsu_bus_buffer.scala 445:50] - node _T_903 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 445:95] - node _T_904 = and(_T_902, _T_903) @[el2_lsu_bus_buffer.scala 445:93] - node _T_905 = bits(_T_904, 0, 0) @[el2_lsu_bus_buffer.scala 445:108] - ibuf_byp <= _T_905 @[el2_lsu_bus_buffer.scala 445:30] - node _T_906 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 446:50] - node _T_907 = eq(ibuf_byp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 446:70] - node _T_908 = and(_T_906, _T_907) @[el2_lsu_bus_buffer.scala 446:68] - node _T_909 = bits(_T_908, 0, 0) @[el2_lsu_bus_buffer.scala 446:81] - ibuf_wr_en <= _T_909 @[el2_lsu_bus_buffer.scala 446:30] - node _T_910 = eq(ibuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 447:52] - node _T_911 = and(ibuf_drain_vld, _T_910) @[el2_lsu_bus_buffer.scala 447:50] - node _T_912 = or(_T_911, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 447:65] - node _T_913 = bits(_T_912, 0, 0) @[el2_lsu_bus_buffer.scala 447:90] - ibuf_rst <= _T_913 @[el2_lsu_bus_buffer.scala 447:30] - node _T_914 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 448:52] - node _T_915 = and(io.lsu_busreq_m, _T_914) @[el2_lsu_bus_buffer.scala 448:50] - node _T_916 = and(_T_915, ibuf_valid) @[el2_lsu_bus_buffer.scala 448:69] - node _T_917 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 448:115] - node _T_918 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 448:139] - node _T_919 = neq(_T_917, _T_918) @[el2_lsu_bus_buffer.scala 448:122] - node _T_920 = or(io.lsu_pkt_m.load, _T_919) @[el2_lsu_bus_buffer.scala 448:103] - node _T_921 = and(_T_916, _T_920) @[el2_lsu_bus_buffer.scala 448:82] - node _T_922 = bits(_T_921, 0, 0) @[el2_lsu_bus_buffer.scala 448:149] - ibuf_force_drain <= _T_922 @[el2_lsu_bus_buffer.scala 448:30] - node _T_923 = eq(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 449:74] - node _T_924 = or(ibuf_wr_en, _T_923) @[el2_lsu_bus_buffer.scala 449:60] - node _T_925 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 449:131] - node _T_926 = eq(_T_925, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 449:115] - node _T_927 = and(_T_924, _T_926) @[el2_lsu_bus_buffer.scala 449:113] - node _T_928 = or(_T_927, ibuf_byp) @[el2_lsu_bus_buffer.scala 449:149] - node _T_929 = or(_T_928, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 450:45] - node _T_930 = or(_T_929, ibuf_sideeffect) @[el2_lsu_bus_buffer.scala 450:64] - node _T_931 = eq(ibuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 450:84] - node _T_932 = or(_T_930, _T_931) @[el2_lsu_bus_buffer.scala 450:82] - node _T_933 = or(_T_932, bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 450:96] - node _T_934 = and(ibuf_valid, _T_933) @[el2_lsu_bus_buffer.scala 449:44] - ibuf_drain_vld <= _T_934 @[el2_lsu_bus_buffer.scala 449:30] - node _T_935 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 451:52] - node _T_936 = bits(ibuf_tag, 1, 0) @[el2_lsu_bus_buffer.scala 451:78] - node _T_937 = mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r) @[el2_lsu_bus_buffer.scala 451:98] - node _T_938 = mux(_T_935, _T_936, _T_937) @[el2_lsu_bus_buffer.scala 451:36] - ibuf_tag_in <= _T_938 @[el2_lsu_bus_buffer.scala 451:30] - node _T_939 = bits(WrPtr0_r, 1, 0) @[el2_lsu_bus_buffer.scala 452:41] - ibuf_dualtag_in <= _T_939 @[el2_lsu_bus_buffer.scala 452:30] - node _T_940 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - ibuf_sz_in <= _T_940 @[el2_lsu_bus_buffer.scala 453:30] - node _T_941 = mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 454:36] - ibuf_addr_in <= _T_941 @[el2_lsu_bus_buffer.scala 454:30] - node _T_942 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 455:51] - node _T_943 = bits(ibuf_byteen, 3, 0) @[el2_lsu_bus_buffer.scala 455:79] - node _T_944 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:103] - node _T_945 = or(_T_943, _T_944) @[el2_lsu_bus_buffer.scala 455:85] - node _T_946 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:146] - node _T_947 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 455:169] - node _T_948 = mux(io.ldst_dual_r, _T_946, _T_947) @[el2_lsu_bus_buffer.scala 455:113] - node _T_949 = mux(_T_942, _T_945, _T_948) @[el2_lsu_bus_buffer.scala 455:36] - ibuf_byteen_in <= _T_949 @[el2_lsu_bus_buffer.scala 455:30] - node _T_950 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_951 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 456:110] - node _T_952 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:129] - node _T_953 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 456:156] - node _T_954 = mux(_T_951, _T_952, _T_953) @[el2_lsu_bus_buffer.scala 456:93] - node _T_955 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:208] - node _T_956 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 456:240] - node _T_957 = mux(io.ldst_dual_r, _T_955, _T_956) @[el2_lsu_bus_buffer.scala 456:176] - node _T_958 = mux(_T_950, _T_954, _T_957) @[el2_lsu_bus_buffer.scala 456:57] - node _T_959 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_960 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 456:110] - node _T_961 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:129] - node _T_962 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 456:156] - node _T_963 = mux(_T_960, _T_961, _T_962) @[el2_lsu_bus_buffer.scala 456:93] - node _T_964 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:208] - node _T_965 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 456:240] - node _T_966 = mux(io.ldst_dual_r, _T_964, _T_965) @[el2_lsu_bus_buffer.scala 456:176] - node _T_967 = mux(_T_959, _T_963, _T_966) @[el2_lsu_bus_buffer.scala 456:57] - node _T_968 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_969 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 456:110] - node _T_970 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:129] - node _T_971 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 456:156] - node _T_972 = mux(_T_969, _T_970, _T_971) @[el2_lsu_bus_buffer.scala 456:93] - node _T_973 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:208] - node _T_974 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 456:240] - node _T_975 = mux(io.ldst_dual_r, _T_973, _T_974) @[el2_lsu_bus_buffer.scala 456:176] - node _T_976 = mux(_T_968, _T_972, _T_975) @[el2_lsu_bus_buffer.scala 456:57] - node _T_977 = and(ibuf_merge_en, ibuf_merge_in) @[el2_lsu_bus_buffer.scala 456:73] - node _T_978 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 456:110] - node _T_979 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:129] - node _T_980 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 456:156] - node _T_981 = mux(_T_978, _T_979, _T_980) @[el2_lsu_bus_buffer.scala 456:93] - node _T_982 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:208] - node _T_983 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 456:240] - node _T_984 = mux(io.ldst_dual_r, _T_982, _T_983) @[el2_lsu_bus_buffer.scala 456:176] - node _T_985 = mux(_T_977, _T_981, _T_984) @[el2_lsu_bus_buffer.scala 456:57] - node _T_986 = cat(_T_985, _T_976) @[Cat.scala 29:58] - node _T_987 = cat(_T_986, _T_967) @[Cat.scala 29:58] - node _T_988 = cat(_T_987, _T_958) @[Cat.scala 29:58] - ibuf_data_in <= _T_988 @[el2_lsu_bus_buffer.scala 456:30] - node _T_989 = lt(ibuf_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 457:69] - node _T_990 = add(ibuf_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 457:115] - node _T_991 = tail(_T_990, 1) @[el2_lsu_bus_buffer.scala 457:115] - node _T_992 = mux(_T_989, _T_991, ibuf_timer) @[el2_lsu_bus_buffer.scala 457:57] - node _T_993 = mux(ibuf_wr_en, UInt<1>("h00"), _T_992) @[el2_lsu_bus_buffer.scala 457:36] - ibuf_timer_in <= _T_993 @[el2_lsu_bus_buffer.scala 457:30] - node _T_994 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_995 = and(ibuf_merge_en, _T_994) @[el2_lsu_bus_buffer.scala 458:73] - node _T_996 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 458:102] - node _T_997 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 458:124] - node _T_998 = or(_T_996, _T_997) @[el2_lsu_bus_buffer.scala 458:106] - node _T_999 = bits(ibuf_byteen, 0, 0) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1000 = mux(_T_995, _T_998, _T_999) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1001 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1002 = and(ibuf_merge_en, _T_1001) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1003 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1004 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1005 = or(_T_1003, _T_1004) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1006 = bits(ibuf_byteen, 1, 1) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1007 = mux(_T_1002, _T_1005, _T_1006) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1008 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1009 = and(ibuf_merge_en, _T_1008) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1010 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1011 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1012 = or(_T_1010, _T_1011) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1013 = bits(ibuf_byteen, 2, 2) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1014 = mux(_T_1009, _T_1012, _T_1013) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1015 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 458:75] - node _T_1016 = and(ibuf_merge_en, _T_1015) @[el2_lsu_bus_buffer.scala 458:73] - node _T_1017 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 458:102] - node _T_1018 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 458:124] - node _T_1019 = or(_T_1017, _T_1018) @[el2_lsu_bus_buffer.scala 458:106] - node _T_1020 = bits(ibuf_byteen, 3, 3) @[el2_lsu_bus_buffer.scala 458:140] - node _T_1021 = mux(_T_1016, _T_1019, _T_1020) @[el2_lsu_bus_buffer.scala 458:57] - node _T_1022 = cat(_T_1021, _T_1014) @[Cat.scala 29:58] - node _T_1023 = cat(_T_1022, _T_1007) @[Cat.scala 29:58] - node _T_1024 = cat(_T_1023, _T_1000) @[Cat.scala 29:58] - ibuf_byteen_out <= _T_1024 @[el2_lsu_bus_buffer.scala 458:30] - node _T_1025 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1026 = and(ibuf_merge_en, _T_1025) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1027 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1028 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1029 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1030 = mux(_T_1027, _T_1028, _T_1029) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1031 = bits(ibuf_data, 7, 0) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1032 = mux(_T_1026, _T_1030, _T_1031) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1033 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1034 = and(ibuf_merge_en, _T_1033) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1035 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1036 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1037 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1038 = mux(_T_1035, _T_1036, _T_1037) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1039 = bits(ibuf_data, 15, 8) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1040 = mux(_T_1034, _T_1038, _T_1039) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1041 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1042 = and(ibuf_merge_en, _T_1041) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1043 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1044 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1045 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1046 = mux(_T_1043, _T_1044, _T_1045) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1047 = bits(ibuf_data, 23, 16) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1048 = mux(_T_1042, _T_1046, _T_1047) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1049 = not(ibuf_merge_in) @[el2_lsu_bus_buffer.scala 459:75] - node _T_1050 = and(ibuf_merge_en, _T_1049) @[el2_lsu_bus_buffer.scala 459:73] - node _T_1051 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_buffer.scala 459:111] - node _T_1052 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_buffer.scala 459:130] - node _T_1053 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 459:157] - node _T_1054 = mux(_T_1051, _T_1052, _T_1053) @[el2_lsu_bus_buffer.scala 459:94] - node _T_1055 = bits(ibuf_data, 31, 24) @[el2_lsu_bus_buffer.scala 459:183] - node _T_1056 = mux(_T_1050, _T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 459:57] - node _T_1057 = cat(_T_1056, _T_1048) @[Cat.scala 29:58] - node _T_1058 = cat(_T_1057, _T_1040) @[Cat.scala 29:58] - node _T_1059 = cat(_T_1058, _T_1032) @[Cat.scala 29:58] - ibuf_data_out <= _T_1059 @[el2_lsu_bus_buffer.scala 459:30] - node _T_1060 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 460:49] - node _T_1061 = and(_T_1060, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 460:67] - node _T_1062 = and(_T_1061, ibuf_valid) @[el2_lsu_bus_buffer.scala 460:88] - node _T_1063 = and(_T_1062, ibuf_write) @[el2_lsu_bus_buffer.scala 460:101] - node _T_1064 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_buffer.scala 460:129] - node _T_1065 = bits(ibuf_addr, 31, 2) @[el2_lsu_bus_buffer.scala 460:147] - node _T_1066 = eq(_T_1064, _T_1065) @[el2_lsu_bus_buffer.scala 460:135] - node _T_1067 = and(_T_1063, _T_1066) @[el2_lsu_bus_buffer.scala 460:114] - node _T_1068 = not(io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 460:156] - node _T_1069 = and(_T_1067, _T_1068) @[el2_lsu_bus_buffer.scala 460:154] - node _T_1070 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 460:179] - node _T_1071 = and(_T_1069, _T_1070) @[el2_lsu_bus_buffer.scala 460:177] - ibuf_merge_en <= _T_1071 @[el2_lsu_bus_buffer.scala 460:30] - node _T_1072 = not(io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:33] - ibuf_merge_in <= _T_1072 @[el2_lsu_bus_buffer.scala 461:30] - node _T_1073 = bits(ibuf_wr_en, 0, 0) @[el2_lsu_bus_buffer.scala 464:50] - node _T_1074 = mux(_T_1073, UInt<1>("h01"), ibuf_valid) @[el2_lsu_bus_buffer.scala 464:32] - node _T_1075 = eq(ibuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 464:72] - node _T_1076 = and(_T_1074, _T_1075) @[el2_lsu_bus_buffer.scala 464:70] - reg _T_1077 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 464:28] - _T_1077 <= _T_1076 @[el2_lsu_bus_buffer.scala 464:28] - ibuf_valid <= _T_1077 @[el2_lsu_bus_buffer.scala 464:18] - reg _T_1078 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 465:35] - _T_1078 <= ibuf_timer_in @[el2_lsu_bus_buffer.scala 465:35] - ibuf_timer <= _T_1078 @[el2_lsu_bus_buffer.scala 465:25] - reg _T_1079 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1079 <= io.ldst_dual_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_dual <= _T_1079 @[el2_lsu_bus_buffer.scala 468:25] - reg _T_1080 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1080 <= ldst_samedw_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_samedw <= _T_1080 @[el2_lsu_bus_buffer.scala 469:25] - reg _T_1081 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1081 <= io.no_dword_merge_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_nomerge <= _T_1081 @[el2_lsu_bus_buffer.scala 470:25] - reg _T_1082 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1082 <= io.is_sideeffects_r @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_sideeffect <= _T_1082 @[el2_lsu_bus_buffer.scala 471:25] - reg _T_1083 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1083 <= io.lsu_pkt_r.unsign @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_unsign <= _T_1083 @[el2_lsu_bus_buffer.scala 472:25] - reg _T_1084 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1084 <= io.lsu_pkt_r.store @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_write <= _T_1084 @[el2_lsu_bus_buffer.scala 473:25] - node _T_1085 = bits(ibuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 474:48] - reg _T_1086 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1086 <= _T_1085 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_sz <= _T_1086 @[el2_lsu_bus_buffer.scala 474:25] - reg _T_1087 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1087 <= ibuf_byteen_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_byteen <= _T_1087 @[el2_lsu_bus_buffer.scala 475:25] - node _T_1088 = bits(ibuf_addr_in, 31, 0) @[el2_lsu_bus_buffer.scala 476:50] - reg _T_1089 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1089 <= _T_1088 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_addr <= _T_1089 @[el2_lsu_bus_buffer.scala 476:25] - node _T_1090 = bits(ibuf_data_in, 31, 0) @[el2_lsu_bus_buffer.scala 477:50] - reg _T_1091 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1091 <= _T_1090 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_data <= _T_1091 @[el2_lsu_bus_buffer.scala 477:25] - reg _T_1092 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1092 <= ibuf_tag_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_tag <= _T_1092 @[el2_lsu_bus_buffer.scala 478:25] - reg _T_1093 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when ibuf_wr_en : @[Reg.scala 28:19] - _T_1093 <= ibuf_dualtag_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - ibuf_dualtag <= _T_1093 @[el2_lsu_bus_buffer.scala 479:25] - node _T_1094 = bits(buf_numvld_pend_any, 3, 0) @[el2_lsu_bus_buffer.scala 483:61] - node _T_1095 = eq(_T_1094, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 483:67] - node _T_1096 = and(ibuf_byp, _T_1095) @[el2_lsu_bus_buffer.scala 483:39] - node _T_1097 = not(io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 483:79] - node _T_1098 = or(_T_1097, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 483:99] - node _T_1099 = and(_T_1096, _T_1098) @[el2_lsu_bus_buffer.scala 483:76] - ibuf_buf_byp <= _T_1099 @[el2_lsu_bus_buffer.scala 483:26] - node _T_1100 = not(io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 484:47] - node _T_1101 = and(io.lsu_busreq_m, _T_1100) @[el2_lsu_bus_buffer.scala 484:45] - node _T_1102 = not(ibuf_valid) @[el2_lsu_bus_buffer.scala 484:66] - node _T_1103 = and(_T_1101, _T_1102) @[el2_lsu_bus_buffer.scala 484:64] - node _T_1104 = bits(buf_numvld_cmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 484:99] - node _T_1105 = eq(_T_1104, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 484:105] - node _T_1106 = and(_T_1103, _T_1105) @[el2_lsu_bus_buffer.scala 484:78] - node _T_1107 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 484:135] - node _T_1108 = bits(buf_addr[CmdPtr0], 31, 2) @[el2_lsu_bus_buffer.scala 484:163] - node _T_1109 = neq(_T_1107, _T_1108) @[el2_lsu_bus_buffer.scala 484:142] - node _T_1110 = and(_T_1106, _T_1109) @[el2_lsu_bus_buffer.scala 484:119] - obuf_force_wr_en <= _T_1110 @[el2_lsu_bus_buffer.scala 484:26] - node _T_1111 = bits(buf_numvld_wrcmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 485:50] - node _T_1112 = eq(_T_1111, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 485:56] - node _T_1113 = bits(buf_numvld_cmd_any, 3, 0) @[el2_lsu_bus_buffer.scala 485:91] - node _T_1114 = eq(_T_1113, UInt<4>("h01")) @[el2_lsu_bus_buffer.scala 485:97] - node _T_1115 = and(_T_1112, _T_1114) @[el2_lsu_bus_buffer.scala 485:70] - node _T_1116 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 485:128] - node _T_1117 = and(_T_1115, _T_1116) @[el2_lsu_bus_buffer.scala 485:111] - node _T_1118 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 486:33] - node _T_1119 = and(_T_1117, _T_1118) @[el2_lsu_bus_buffer.scala 485:166] - node _T_1120 = not(buf_nomerge[CmdPtr0]) @[el2_lsu_bus_buffer.scala 486:59] - node _T_1121 = and(_T_1119, _T_1120) @[el2_lsu_bus_buffer.scala 486:57] - node _T_1122 = not(buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 486:83] - node _T_1123 = and(_T_1121, _T_1122) @[el2_lsu_bus_buffer.scala 486:81] - node _T_1124 = not(obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 486:110] - node _T_1125 = and(_T_1123, _T_1124) @[el2_lsu_bus_buffer.scala 486:108] - obuf_wr_wait <= _T_1125 @[el2_lsu_bus_buffer.scala 485:26] - node _T_1126 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 487:44] - node _T_1127 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 487:86] - node _T_1128 = not(_T_1127) @[el2_lsu_bus_buffer.scala 487:64] - node _T_1129 = and(_T_1126, _T_1128) @[el2_lsu_bus_buffer.scala 487:62] - node _T_1130 = eq(buf_state[CmdPtr0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 488:54] - node _T_1131 = and(_T_1130, found_cmdptr0) @[el2_lsu_bus_buffer.scala 488:65] - node _T_1132 = not(buf_cmd_state_bus_en[CmdPtr0]) @[el2_lsu_bus_buffer.scala 488:83] - node _T_1133 = and(_T_1131, _T_1132) @[el2_lsu_bus_buffer.scala 488:81] - node _T_1134 = and(buf_sideeffect[CmdPtr0], bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 488:142] - node _T_1135 = not(_T_1134) @[el2_lsu_bus_buffer.scala 488:116] - node _T_1136 = and(_T_1133, _T_1135) @[el2_lsu_bus_buffer.scala 488:114] - node _T_1137 = and(buf_dual[CmdPtr0], buf_samedw[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:58] - node _T_1138 = not(buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:82] - node _T_1139 = and(_T_1137, _T_1138) @[el2_lsu_bus_buffer.scala 489:80] - node _T_1140 = not(_T_1139) @[el2_lsu_bus_buffer.scala 489:38] - node _T_1141 = or(_T_1140, found_cmdptr1) @[el2_lsu_bus_buffer.scala 489:103] - node _T_1142 = or(_T_1141, buf_nomerge[CmdPtr0]) @[el2_lsu_bus_buffer.scala 489:119] - node _T_1143 = or(_T_1142, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 489:142] - node _T_1144 = and(_T_1136, _T_1143) @[el2_lsu_bus_buffer.scala 488:165] - node _T_1145 = or(_T_1129, _T_1144) @[el2_lsu_bus_buffer.scala 487:110] - node _T_1146 = not(obuf_valid) @[el2_lsu_bus_buffer.scala 490:57] - node _T_1147 = or(bus_cmd_ready, _T_1146) @[el2_lsu_bus_buffer.scala 490:55] - node _T_1148 = or(_T_1147, obuf_nosend) @[el2_lsu_bus_buffer.scala 490:69] - node _T_1149 = and(_T_1145, _T_1148) @[el2_lsu_bus_buffer.scala 489:164] - node _T_1150 = not(obuf_wr_wait) @[el2_lsu_bus_buffer.scala 490:86] - node _T_1151 = and(_T_1149, _T_1150) @[el2_lsu_bus_buffer.scala 490:84] - node _T_1152 = not(lsu_bus_cntr_overflow) @[el2_lsu_bus_buffer.scala 490:102] - node _T_1153 = and(_T_1151, _T_1152) @[el2_lsu_bus_buffer.scala 490:100] - node _T_1154 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 490:127] - node _T_1155 = and(_T_1153, _T_1154) @[el2_lsu_bus_buffer.scala 490:125] - node _T_1156 = and(_T_1155, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 490:151] - obuf_wr_en <= _T_1156 @[el2_lsu_bus_buffer.scala 487:26] - node _T_1157 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 491:58] - node _T_1158 = or(bus_cmd_sent, _T_1157) @[el2_lsu_bus_buffer.scala 491:44] - node _T_1159 = not(obuf_wr_en) @[el2_lsu_bus_buffer.scala 491:76] - node _T_1160 = and(_T_1158, _T_1159) @[el2_lsu_bus_buffer.scala 491:74] - node _T_1161 = and(_T_1160, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 491:88] - node _T_1162 = or(_T_1161, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 491:109] - obuf_rst <= _T_1162 @[el2_lsu_bus_buffer.scala 491:26] - node _T_1163 = mux(ibuf_buf_byp, io.lsu_pkt_r.store, buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 492:32] - obuf_write_in <= _T_1163 @[el2_lsu_bus_buffer.scala 492:26] - node _T_1164 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 493:42] - node _T_1165 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 493:62] - node _T_1166 = eq(_T_1164, _T_1165) @[el2_lsu_bus_buffer.scala 493:49] - node _T_1167 = and(_T_1166, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 493:70] - node _T_1168 = not(obuf_sideeffect) @[el2_lsu_bus_buffer.scala 493:90] - node _T_1169 = and(_T_1167, _T_1168) @[el2_lsu_bus_buffer.scala 493:88] - node _T_1170 = not(obuf_write) @[el2_lsu_bus_buffer.scala 493:109] - node _T_1171 = and(_T_1169, _T_1170) @[el2_lsu_bus_buffer.scala 493:107] - node _T_1172 = not(obuf_write_in) @[el2_lsu_bus_buffer.scala 493:123] - node _T_1173 = and(_T_1171, _T_1172) @[el2_lsu_bus_buffer.scala 493:121] - node _T_1174 = not(io.dec_tlu_external_ldfwd_disable) @[el2_lsu_bus_buffer.scala 493:140] - node _T_1175 = and(_T_1173, _T_1174) @[el2_lsu_bus_buffer.scala 493:138] - node _T_1176 = not(obuf_nosend) @[el2_lsu_bus_buffer.scala 494:48] - node _T_1177 = and(obuf_valid, _T_1176) @[el2_lsu_bus_buffer.scala 494:46] - node _T_1178 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 494:118] - node _T_1179 = and(bus_rsp_read, _T_1178) @[el2_lsu_bus_buffer.scala 494:98] - node _T_1180 = not(_T_1179) @[el2_lsu_bus_buffer.scala 494:83] - node _T_1181 = and(obuf_rdrsp_pend, _T_1180) @[el2_lsu_bus_buffer.scala 494:81] - node _T_1182 = or(_T_1177, _T_1181) @[el2_lsu_bus_buffer.scala 494:62] - node _T_1183 = and(_T_1175, _T_1182) @[el2_lsu_bus_buffer.scala 493:175] - obuf_nosend_in <= _T_1183 @[el2_lsu_bus_buffer.scala 493:26] - node _T_1184 = not(obuf_nosend_in) @[el2_lsu_bus_buffer.scala 495:45] - node _T_1185 = and(obuf_wr_en, _T_1184) @[el2_lsu_bus_buffer.scala 495:43] - node _T_1186 = not(_T_1185) @[el2_lsu_bus_buffer.scala 495:30] - node _T_1187 = and(_T_1186, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 495:62] - node _T_1188 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 495:117] - node _T_1189 = and(bus_rsp_read, _T_1188) @[el2_lsu_bus_buffer.scala 495:97] - node _T_1190 = not(_T_1189) @[el2_lsu_bus_buffer.scala 495:82] - node _T_1191 = and(_T_1187, _T_1190) @[el2_lsu_bus_buffer.scala 495:80] - node _T_1192 = not(obuf_write) @[el2_lsu_bus_buffer.scala 495:158] - node _T_1193 = and(bus_cmd_sent, _T_1192) @[el2_lsu_bus_buffer.scala 495:156] - node _T_1194 = not(io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 495:173] - node _T_1195 = and(_T_1193, _T_1194) @[el2_lsu_bus_buffer.scala 495:171] - node _T_1196 = or(_T_1191, _T_1195) @[el2_lsu_bus_buffer.scala 495:139] - obuf_rdrsp_pend_in <= _T_1196 @[el2_lsu_bus_buffer.scala 495:26] - node _T_1197 = mux(ibuf_buf_byp, io.is_sideeffects_r, buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 496:32] - obuf_sideeffect_in <= _T_1197 @[el2_lsu_bus_buffer.scala 496:26] - node _T_1198 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 497:72] - node _T_1199 = eq(_T_1198, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 497:78] - node _T_1200 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 497:104] - node _T_1201 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 497:123] - node _T_1202 = not(_T_1201) @[el2_lsu_bus_buffer.scala 497:110] - node _T_1203 = and(_T_1200, _T_1202) @[el2_lsu_bus_buffer.scala 497:108] - node _T_1204 = or(_T_1199, _T_1203) @[el2_lsu_bus_buffer.scala 497:91] - node _T_1205 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 497:141] - node _T_1206 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 497:161] - node _T_1207 = orr(_T_1206) @[el2_lsu_bus_buffer.scala 497:167] - node _T_1208 = not(_T_1207) @[el2_lsu_bus_buffer.scala 497:147] - node _T_1209 = and(_T_1205, _T_1208) @[el2_lsu_bus_buffer.scala 497:145] - node _T_1210 = or(_T_1204, _T_1209) @[el2_lsu_bus_buffer.scala 497:128] - node _T_1211 = mux(ibuf_buf_byp, is_aligned_r, _T_1210) @[el2_lsu_bus_buffer.scala 497:32] - obuf_aligned_in <= _T_1211 @[el2_lsu_bus_buffer.scala 497:26] - node _T_1212 = mux(ibuf_buf_byp, io.lsu_addr_r, buf_addr[CmdPtr0]) @[el2_lsu_bus_buffer.scala 498:32] - obuf_addr_in <= _T_1212 @[el2_lsu_bus_buffer.scala 498:26] - node _T_1213 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1214 = and(obuf_merge_en, _T_1213) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1215 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1216 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1217 = mux(_T_1214, _T_1215, _T_1216) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1218 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1219 = and(obuf_merge_en, _T_1218) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1220 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1221 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1222 = mux(_T_1219, _T_1220, _T_1221) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1223 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1224 = and(obuf_merge_en, _T_1223) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1225 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1226 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1227 = mux(_T_1224, _T_1225, _T_1226) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1228 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1229 = and(obuf_merge_en, _T_1228) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1230 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1231 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1232 = mux(_T_1229, _T_1230, _T_1231) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1233 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1234 = and(obuf_merge_en, _T_1233) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1235 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1236 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1237 = mux(_T_1234, _T_1235, _T_1236) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1238 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1239 = and(obuf_merge_en, _T_1238) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1240 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1241 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1242 = mux(_T_1239, _T_1240, _T_1241) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1243 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1244 = and(obuf_merge_en, _T_1243) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1245 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1246 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1247 = mux(_T_1244, _T_1245, _T_1246) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1248 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 499:86] - node _T_1249 = and(obuf_merge_en, _T_1248) @[el2_lsu_bus_buffer.scala 499:69] - node _T_1250 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 499:104] - node _T_1251 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 499:134] - node _T_1252 = mux(_T_1249, _T_1250, _T_1251) @[el2_lsu_bus_buffer.scala 499:53] - node _T_1253 = cat(_T_1252, _T_1247) @[Cat.scala 29:58] - node _T_1254 = cat(_T_1253, _T_1242) @[Cat.scala 29:58] - node _T_1255 = cat(_T_1254, _T_1237) @[Cat.scala 29:58] - node _T_1256 = cat(_T_1255, _T_1232) @[Cat.scala 29:58] - node _T_1257 = cat(_T_1256, _T_1227) @[Cat.scala 29:58] - node _T_1258 = cat(_T_1257, _T_1222) @[Cat.scala 29:58] - node _T_1259 = cat(_T_1258, _T_1217) @[Cat.scala 29:58] - obuf_data_in <= _T_1259 @[el2_lsu_bus_buffer.scala 499:26] - node _T_1260 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_1261 = mux(ibuf_buf_byp, _T_1260, buf_sz[CmdPtr0]) @[el2_lsu_bus_buffer.scala 500:32] - obuf_sz_in <= _T_1261 @[el2_lsu_bus_buffer.scala 500:26] - node _T_1262 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1263 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1264 = and(obuf_merge_en, _T_1263) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1265 = or(_T_1262, _T_1264) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1266 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1267 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1268 = and(obuf_merge_en, _T_1267) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1269 = or(_T_1266, _T_1268) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1270 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1271 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1272 = and(obuf_merge_en, _T_1271) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1273 = or(_T_1270, _T_1272) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1274 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1275 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1276 = and(obuf_merge_en, _T_1275) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1277 = or(_T_1274, _T_1276) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1278 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1279 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1280 = and(obuf_merge_en, _T_1279) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1281 = or(_T_1278, _T_1280) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1282 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1283 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1284 = and(obuf_merge_en, _T_1283) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1285 = or(_T_1282, _T_1284) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1286 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1287 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1288 = and(obuf_merge_en, _T_1287) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1289 = or(_T_1286, _T_1288) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1290 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 501:65] - node _T_1291 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 501:103] - node _T_1292 = and(obuf_merge_en, _T_1291) @[el2_lsu_bus_buffer.scala 501:86] - node _T_1293 = or(_T_1290, _T_1292) @[el2_lsu_bus_buffer.scala 501:69] - node _T_1294 = cat(_T_1293, _T_1289) @[Cat.scala 29:58] - node _T_1295 = cat(_T_1294, _T_1285) @[Cat.scala 29:58] - node _T_1296 = cat(_T_1295, _T_1281) @[Cat.scala 29:58] - node _T_1297 = cat(_T_1296, _T_1277) @[Cat.scala 29:58] - node _T_1298 = cat(_T_1297, _T_1273) @[Cat.scala 29:58] - node _T_1299 = cat(_T_1298, _T_1269) @[Cat.scala 29:58] - node _T_1300 = cat(_T_1299, _T_1265) @[Cat.scala 29:58] - obuf_byteen_in <= _T_1300 @[el2_lsu_bus_buffer.scala 501:26] - obuf_merge_in <= obuf_merge_en @[el2_lsu_bus_buffer.scala 502:26] - node _T_1301 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 503:42] - node _T_1302 = not(_T_1301) @[el2_lsu_bus_buffer.scala 503:29] - node _T_1303 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 503:72] - node _T_1304 = and(_T_1302, _T_1303) @[el2_lsu_bus_buffer.scala 503:54] - obuf_cmd_done_in <= _T_1304 @[el2_lsu_bus_buffer.scala 503:26] - node _T_1305 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 504:42] - node _T_1306 = not(_T_1305) @[el2_lsu_bus_buffer.scala 504:29] - node _T_1307 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 504:72] - node _T_1308 = and(_T_1306, _T_1307) @[el2_lsu_bus_buffer.scala 504:54] - obuf_data_done_in <= _T_1308 @[el2_lsu_bus_buffer.scala 504:26] - node _T_1309 = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 505:32] - obuf_tag0_in <= _T_1309 @[el2_lsu_bus_buffer.scala 505:26] - node _T_1310 = mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 506:32] - obuf_tag1_in <= _T_1310 @[el2_lsu_bus_buffer.scala 506:26] - node _T_1311 = not(obuf_write) @[el2_lsu_bus_buffer.scala 507:49] - node _T_1312 = and(bus_cmd_sent, _T_1311) @[el2_lsu_bus_buffer.scala 507:47] - node _T_1313 = bits(obuf_tag0, 2, 0) @[el2_lsu_bus_buffer.scala 507:72] - node _T_1314 = bits(obuf_rdrsp_tag, 2, 0) @[el2_lsu_bus_buffer.scala 507:109] - node _T_1315 = mux(_T_1312, _T_1313, _T_1314) @[el2_lsu_bus_buffer.scala 507:32] - obuf_rdrsp_tag_in <= _T_1315 @[el2_lsu_bus_buffer.scala 507:26] - node _T_1316 = neq(CmdPtr0, CmdPtr1) @[el2_lsu_bus_buffer.scala 509:39] - node _T_1317 = and(_T_1316, found_cmdptr0) @[el2_lsu_bus_buffer.scala 509:52] - node _T_1318 = and(_T_1317, found_cmdptr1) @[el2_lsu_bus_buffer.scala 509:68] - node _T_1319 = eq(buf_state[CmdPtr0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:106] - node _T_1320 = and(_T_1318, _T_1319) @[el2_lsu_bus_buffer.scala 509:84] - node _T_1321 = eq(buf_state[CmdPtr1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 509:139] - node _T_1322 = and(_T_1320, _T_1321) @[el2_lsu_bus_buffer.scala 509:117] - node _T_1323 = not(buf_cmd_state_bus_en[CmdPtr0]) @[el2_lsu_bus_buffer.scala 510:31] - node _T_1324 = and(_T_1322, _T_1323) @[el2_lsu_bus_buffer.scala 509:150] - node _T_1325 = not(buf_sideeffect[CmdPtr0]) @[el2_lsu_bus_buffer.scala 510:64] - node _T_1326 = and(_T_1324, _T_1325) @[el2_lsu_bus_buffer.scala 510:62] - node _T_1327 = and(buf_write[CmdPtr0], buf_write[CmdPtr1]) @[el2_lsu_bus_buffer.scala 511:55] - node _T_1328 = bits(buf_addr[CmdPtr0], 31, 3) @[el2_lsu_bus_buffer.scala 511:96] - node _T_1329 = bits(buf_addr[CmdPtr1], 31, 3) @[el2_lsu_bus_buffer.scala 511:124] - node _T_1330 = eq(_T_1328, _T_1329) @[el2_lsu_bus_buffer.scala 511:103] - node _T_1331 = and(_T_1327, _T_1330) @[el2_lsu_bus_buffer.scala 511:76] - node _T_1332 = not(bus_coalescing_disable) @[el2_lsu_bus_buffer.scala 511:134] - node _T_1333 = and(_T_1331, _T_1332) @[el2_lsu_bus_buffer.scala 511:132] - node _T_1334 = not(UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 511:160] - node _T_1335 = and(_T_1333, _T_1334) @[el2_lsu_bus_buffer.scala 511:158] - node _T_1336 = not(buf_write[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:38] - node _T_1337 = and(_T_1336, buf_dual[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:58] - node _T_1338 = not(buf_dualhi[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:80] - node _T_1339 = and(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 512:78] - node _T_1340 = and(_T_1339, buf_samedw[CmdPtr0]) @[el2_lsu_bus_buffer.scala 512:101] - node _T_1341 = or(_T_1335, _T_1340) @[el2_lsu_bus_buffer.scala 511:182] - node _T_1342 = and(_T_1326, _T_1341) @[el2_lsu_bus_buffer.scala 510:89] - node _T_1343 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 513:54] - node _T_1344 = and(_T_1343, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 513:70] - node _T_1345 = or(_T_1342, _T_1344) @[el2_lsu_bus_buffer.scala 512:126] - obuf_merge_en <= _T_1345 @[el2_lsu_bus_buffer.scala 509:26] - node _T_1346 = gt(buf_numvld_cmd_any, UInt<4>("h00")) @[el2_lsu_bus_buffer.scala 514:74] - node _T_1347 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 514:103] - node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 514:86] - node _T_1349 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 514:154] - node _T_1350 = tail(_T_1349, 1) @[el2_lsu_bus_buffer.scala 514:154] - node _T_1351 = mux(_T_1348, _T_1350, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 514:52] - node _T_1352 = mux(obuf_wr_en, UInt<1>("h00"), _T_1351) @[el2_lsu_bus_buffer.scala 514:31] - obuf_wr_timer_in <= _T_1352 @[el2_lsu_bus_buffer.scala 514:25] - node _T_1353 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 515:63] - node _T_1354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 515:88] - node _T_1355 = cat(_T_1354, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1356 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 515:135] - node _T_1357 = cat(UInt<4>("h00"), _T_1356) @[Cat.scala 29:58] - node _T_1358 = mux(_T_1353, _T_1355, _T_1357) @[el2_lsu_bus_buffer.scala 515:49] - node _T_1359 = bits(buf_addr[CmdPtr0], 2, 2) @[el2_lsu_bus_buffer.scala 515:168] - node _T_1360 = cat(buf_byteen[CmdPtr0], UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1361 = cat(UInt<4>("h00"), buf_byteen[CmdPtr0]) @[Cat.scala 29:58] - node _T_1362 = mux(_T_1359, _T_1360, _T_1361) @[el2_lsu_bus_buffer.scala 515:150] - node _T_1363 = mux(ibuf_buf_byp, _T_1358, _T_1362) @[el2_lsu_bus_buffer.scala 515:31] - obuf_byteen0_in <= _T_1363 @[el2_lsu_bus_buffer.scala 515:25] - node _T_1364 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 516:63] - node _T_1365 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 516:88] - node _T_1366 = cat(_T_1365, UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1367 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 516:135] - node _T_1368 = cat(UInt<4>("h00"), _T_1367) @[Cat.scala 29:58] - node _T_1369 = mux(_T_1364, _T_1366, _T_1368) @[el2_lsu_bus_buffer.scala 516:49] - node _T_1370 = bits(buf_addr[CmdPtr1], 2, 2) @[el2_lsu_bus_buffer.scala 516:168] - node _T_1371 = cat(buf_byteen[CmdPtr1], UInt<4>("h00")) @[Cat.scala 29:58] - node _T_1372 = cat(UInt<4>("h00"), buf_byteen[CmdPtr1]) @[Cat.scala 29:58] - node _T_1373 = mux(_T_1370, _T_1371, _T_1372) @[el2_lsu_bus_buffer.scala 516:150] - node _T_1374 = mux(ibuf_buf_byp, _T_1369, _T_1373) @[el2_lsu_bus_buffer.scala 516:31] - obuf_byteen1_in <= _T_1374 @[el2_lsu_bus_buffer.scala 516:25] - node _T_1375 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 517:63] - node _T_1376 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 517:87] - node _T_1377 = cat(_T_1376, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1378 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 517:135] - node _T_1379 = cat(UInt<32>("h00"), _T_1378) @[Cat.scala 29:58] - node _T_1380 = mux(_T_1375, _T_1377, _T_1379) @[el2_lsu_bus_buffer.scala 517:49] - node _T_1381 = bits(buf_addr[CmdPtr0], 2, 2) @[el2_lsu_bus_buffer.scala 517:168] - node _T_1382 = cat(buf_data[CmdPtr0], UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1383 = cat(UInt<32>("h00"), buf_data[CmdPtr0]) @[Cat.scala 29:58] - node _T_1384 = mux(_T_1381, _T_1382, _T_1383) @[el2_lsu_bus_buffer.scala 517:150] - node _T_1385 = mux(ibuf_buf_byp, _T_1380, _T_1384) @[el2_lsu_bus_buffer.scala 517:31] - obuf_data0_in <= _T_1385 @[el2_lsu_bus_buffer.scala 517:25] - node _T_1386 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 518:63] - node _T_1387 = bits(store_data_hi_r, 31, 0) @[el2_lsu_bus_buffer.scala 518:87] - node _T_1388 = cat(_T_1387, UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1389 = bits(store_data_hi_r, 31, 0) @[el2_lsu_bus_buffer.scala 518:135] - node _T_1390 = cat(UInt<32>("h00"), _T_1389) @[Cat.scala 29:58] - node _T_1391 = mux(_T_1386, _T_1388, _T_1390) @[el2_lsu_bus_buffer.scala 518:49] - node _T_1392 = bits(buf_addr[CmdPtr1], 2, 2) @[el2_lsu_bus_buffer.scala 518:168] - node _T_1393 = cat(buf_data[CmdPtr1], UInt<32>("h00")) @[Cat.scala 29:58] - node _T_1394 = cat(UInt<32>("h00"), buf_data[CmdPtr1]) @[Cat.scala 29:58] - node _T_1395 = mux(_T_1392, _T_1393, _T_1394) @[el2_lsu_bus_buffer.scala 518:150] - node _T_1396 = mux(ibuf_buf_byp, _T_1391, _T_1395) @[el2_lsu_bus_buffer.scala 518:31] - obuf_data1_in <= _T_1396 @[el2_lsu_bus_buffer.scala 518:25] - reg _T_1397 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + wire buf_nomerge : UInt<1>[4] @[el2_lsu_bus_buffer.scala 309:25] + buf_nomerge[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + buf_nomerge[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 310:15] + wire buf_sideeffect : UInt<4> + buf_sideeffect <= UInt<1>("h00") + wire obuf_force_wr_en : UInt<1> + obuf_force_wr_en <= UInt<1>("h00") + wire obuf_wr_en : UInt<1> + obuf_wr_en <= UInt<1>("h00") + node _T_1016 = eq(buf_numvld_wrcmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:43] + node _T_1017 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 315:72] + node _T_1018 = and(_T_1016, _T_1017) @[el2_lsu_bus_buffer.scala 315:51] + node _T_1019 = neq(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 315:97] + node _T_1020 = and(_T_1018, _T_1019) @[el2_lsu_bus_buffer.scala 315:80] + node _T_1021 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:5] + node _T_1022 = and(_T_1020, _T_1021) @[el2_lsu_bus_buffer.scala 315:114] + node _T_1023 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1024 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1025 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1026 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 316:114] + node _T_1027 = mux(_T_1023, buf_nomerge[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1028 = mux(_T_1024, buf_nomerge[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1029 = mux(_T_1025, buf_nomerge[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1030 = mux(_T_1026, buf_nomerge[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1031 = or(_T_1027, _T_1028) @[Mux.scala 27:72] + node _T_1032 = or(_T_1031, _T_1029) @[Mux.scala 27:72] + node _T_1033 = or(_T_1032, _T_1030) @[Mux.scala 27:72] + wire _T_1034 : UInt<1> @[Mux.scala 27:72] + _T_1034 <= _T_1033 @[Mux.scala 27:72] + node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 316:31] + node _T_1036 = and(_T_1022, _T_1035) @[el2_lsu_bus_buffer.scala 316:29] + node _T_1037 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1038 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1039 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1040 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1041 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1042 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1043 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 317:88] + node _T_1044 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 317:111] + node _T_1045 = mux(_T_1037, _T_1038, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1046 = mux(_T_1039, _T_1040, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1047 = mux(_T_1041, _T_1042, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1048 = mux(_T_1043, _T_1044, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1049 = or(_T_1045, _T_1046) @[Mux.scala 27:72] + node _T_1050 = or(_T_1049, _T_1047) @[Mux.scala 27:72] + node _T_1051 = or(_T_1050, _T_1048) @[Mux.scala 27:72] + wire _T_1052 : UInt<1> @[Mux.scala 27:72] + _T_1052 <= _T_1051 @[Mux.scala 27:72] + node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:5] + node _T_1054 = and(_T_1036, _T_1053) @[el2_lsu_bus_buffer.scala 316:140] + node _T_1055 = eq(obuf_force_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 317:119] + node obuf_wr_wait = and(_T_1054, _T_1055) @[el2_lsu_bus_buffer.scala 317:117] + node _T_1056 = orr(buf_numvld_cmd_any) @[el2_lsu_bus_buffer.scala 318:75] + node _T_1057 = lt(obuf_wr_timer, UInt<3>("h07")) @[el2_lsu_bus_buffer.scala 318:95] + node _T_1058 = and(_T_1056, _T_1057) @[el2_lsu_bus_buffer.scala 318:79] + node _T_1059 = add(obuf_wr_timer, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 318:123] + node _T_1060 = tail(_T_1059, 1) @[el2_lsu_bus_buffer.scala 318:123] + node _T_1061 = mux(_T_1058, _T_1060, obuf_wr_timer) @[el2_lsu_bus_buffer.scala 318:55] + node obuf_wr_timer_in = mux(obuf_wr_en, UInt<3>("h00"), _T_1061) @[el2_lsu_bus_buffer.scala 318:29] + node _T_1062 = eq(io.lsu_busreq_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:41] + node _T_1063 = and(io.lsu_busreq_m, _T_1062) @[el2_lsu_bus_buffer.scala 319:39] + node _T_1064 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:60] + node _T_1065 = and(_T_1063, _T_1064) @[el2_lsu_bus_buffer.scala 319:58] + node _T_1066 = eq(buf_numvld_cmd_any, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:93] + node _T_1067 = and(_T_1065, _T_1066) @[el2_lsu_bus_buffer.scala 319:72] + node _T_1068 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_buffer.scala 319:117] + node _T_1069 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1070 = bits(buf_addr[0], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1071 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1072 = bits(buf_addr[1], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1073 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1074 = bits(buf_addr[2], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1075 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 319:208] + node _T_1076 = bits(buf_addr[3], 31, 2) @[el2_lsu_bus_buffer.scala 319:228] + node _T_1077 = mux(_T_1069, _T_1070, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1078 = mux(_T_1071, _T_1072, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1079 = mux(_T_1073, _T_1074, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1080 = mux(_T_1075, _T_1076, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1081 = or(_T_1077, _T_1078) @[Mux.scala 27:72] + node _T_1082 = or(_T_1081, _T_1079) @[Mux.scala 27:72] + node _T_1083 = or(_T_1082, _T_1080) @[Mux.scala 27:72] + wire _T_1084 : UInt<30> @[Mux.scala 27:72] + _T_1084 <= _T_1083 @[Mux.scala 27:72] + node _T_1085 = neq(_T_1068, _T_1084) @[el2_lsu_bus_buffer.scala 319:123] + node _T_1086 = and(_T_1067, _T_1085) @[el2_lsu_bus_buffer.scala 319:101] + obuf_force_wr_en <= _T_1086 @[el2_lsu_bus_buffer.scala 319:20] + wire buf_numvld_pend_any : UInt<4> + buf_numvld_pend_any <= UInt<1>("h00") + node _T_1087 = eq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:53] + node _T_1088 = and(ibuf_byp, _T_1087) @[el2_lsu_bus_buffer.scala 321:31] + node _T_1089 = eq(io.lsu_pkt_r.store, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 321:64] + node _T_1090 = or(_T_1089, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 321:84] + node ibuf_buf_byp = and(_T_1088, _T_1090) @[el2_lsu_bus_buffer.scala 321:61] + wire bus_sideeffect_pend : UInt<1> + bus_sideeffect_pend <= UInt<1>("h00") + wire found_cmdptr0 : UInt<1> + found_cmdptr0 <= UInt<1>("h00") + wire buf_cmd_state_bus_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 324:34] + buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 325:24] + wire buf_dual : UInt<1>[4] @[el2_lsu_bus_buffer.scala 326:22] + buf_dual[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + buf_dual[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 327:12] + wire buf_samedw : UInt<1>[4] @[el2_lsu_bus_buffer.scala 328:24] + buf_samedw[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + buf_samedw[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 329:14] + wire found_cmdptr1 : UInt<1> + found_cmdptr1 <= UInt<1>("h00") + wire bus_cmd_ready : UInt<1> + bus_cmd_ready <= UInt<1>("h00") + wire obuf_valid : UInt<1> + obuf_valid <= UInt<1>("h00") + wire obuf_nosend : UInt<1> + obuf_nosend <= UInt<1>("h00") + wire lsu_bus_cntr_overflow : UInt<1> + lsu_bus_cntr_overflow <= UInt<1>("h00") + wire bus_addr_match_pending : UInt<1> + bus_addr_match_pending <= UInt<1>("h00") + node _T_1091 = and(ibuf_buf_byp, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 336:32] + node _T_1092 = and(io.is_sideeffects_r, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 336:74] + node _T_1093 = eq(_T_1092, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 336:52] + node _T_1094 = and(_T_1091, _T_1093) @[el2_lsu_bus_buffer.scala 336:50] + node _T_1095 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1096 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1097 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1098 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1099 = mux(_T_1095, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1100 = mux(_T_1096, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1101 = mux(_T_1097, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1102 = mux(_T_1098, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1103 = or(_T_1099, _T_1100) @[Mux.scala 27:72] + node _T_1104 = or(_T_1103, _T_1101) @[Mux.scala 27:72] + node _T_1105 = or(_T_1104, _T_1102) @[Mux.scala 27:72] + wire _T_1106 : UInt<3> @[Mux.scala 27:72] + _T_1106 <= _T_1105 @[Mux.scala 27:72] + node _T_1107 = eq(_T_1106, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 337:36] + node _T_1108 = and(_T_1107, found_cmdptr0) @[el2_lsu_bus_buffer.scala 337:47] + node _T_1109 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1110 = cat(_T_1109, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1111 = cat(_T_1110, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1112 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1113 = bits(_T_1111, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1114 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1115 = bits(_T_1111, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1116 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1117 = bits(_T_1111, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1118 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1119 = bits(_T_1111, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1120 = mux(_T_1112, _T_1113, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1121 = mux(_T_1114, _T_1115, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1122 = mux(_T_1116, _T_1117, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1123 = mux(_T_1118, _T_1119, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1124 = or(_T_1120, _T_1121) @[Mux.scala 27:72] + node _T_1125 = or(_T_1124, _T_1122) @[Mux.scala 27:72] + node _T_1126 = or(_T_1125, _T_1123) @[Mux.scala 27:72] + wire _T_1127 : UInt<1> @[Mux.scala 27:72] + _T_1127 <= _T_1126 @[Mux.scala 27:72] + node _T_1128 = eq(_T_1127, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:23] + node _T_1129 = and(_T_1108, _T_1128) @[el2_lsu_bus_buffer.scala 338:21] + node _T_1130 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1131 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1132 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1133 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1134 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1135 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1136 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1137 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1138 = mux(_T_1130, _T_1131, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1139 = mux(_T_1132, _T_1133, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1140 = mux(_T_1134, _T_1135, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1141 = mux(_T_1136, _T_1137, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1142 = or(_T_1138, _T_1139) @[Mux.scala 27:72] + node _T_1143 = or(_T_1142, _T_1140) @[Mux.scala 27:72] + node _T_1144 = or(_T_1143, _T_1141) @[Mux.scala 27:72] + wire _T_1145 : UInt<1> @[Mux.scala 27:72] + _T_1145 <= _T_1144 @[Mux.scala 27:72] + node _T_1146 = and(_T_1145, bus_sideeffect_pend) @[el2_lsu_bus_buffer.scala 338:141] + node _T_1147 = eq(_T_1146, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 338:105] + node _T_1148 = and(_T_1129, _T_1147) @[el2_lsu_bus_buffer.scala 338:103] + node _T_1149 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1150 = cat(_T_1149, buf_dual[1]) @[Cat.scala 29:58] + node _T_1151 = cat(_T_1150, buf_dual[0]) @[Cat.scala 29:58] + node _T_1152 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1153 = bits(_T_1151, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1154 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1155 = bits(_T_1151, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1156 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1157 = bits(_T_1151, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1158 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1159 = bits(_T_1151, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1160 = mux(_T_1152, _T_1153, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1161 = mux(_T_1154, _T_1155, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1162 = mux(_T_1156, _T_1157, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1163 = mux(_T_1158, _T_1159, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1164 = or(_T_1160, _T_1161) @[Mux.scala 27:72] + node _T_1165 = or(_T_1164, _T_1162) @[Mux.scala 27:72] + node _T_1166 = or(_T_1165, _T_1163) @[Mux.scala 27:72] + wire _T_1167 : UInt<1> @[Mux.scala 27:72] + _T_1167 <= _T_1166 @[Mux.scala 27:72] + node _T_1168 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1169 = cat(_T_1168, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1170 = cat(_T_1169, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1171 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1172 = bits(_T_1170, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1173 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1174 = bits(_T_1170, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1175 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1176 = bits(_T_1170, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1177 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1178 = bits(_T_1170, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1179 = mux(_T_1171, _T_1172, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1180 = mux(_T_1173, _T_1174, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1181 = mux(_T_1175, _T_1176, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1182 = mux(_T_1177, _T_1178, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1183 = or(_T_1179, _T_1180) @[Mux.scala 27:72] + node _T_1184 = or(_T_1183, _T_1181) @[Mux.scala 27:72] + node _T_1185 = or(_T_1184, _T_1182) @[Mux.scala 27:72] + wire _T_1186 : UInt<1> @[Mux.scala 27:72] + _T_1186 <= _T_1185 @[Mux.scala 27:72] + node _T_1187 = and(_T_1167, _T_1186) @[el2_lsu_bus_buffer.scala 339:77] + node _T_1188 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1189 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1190 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1191 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1192 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1193 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1194 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1195 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1196 = mux(_T_1188, _T_1189, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1197 = mux(_T_1190, _T_1191, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1198 = mux(_T_1192, _T_1193, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1199 = mux(_T_1194, _T_1195, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1200 = or(_T_1196, _T_1197) @[Mux.scala 27:72] + node _T_1201 = or(_T_1200, _T_1198) @[Mux.scala 27:72] + node _T_1202 = or(_T_1201, _T_1199) @[Mux.scala 27:72] + wire _T_1203 : UInt<1> @[Mux.scala 27:72] + _T_1203 <= _T_1202 @[Mux.scala 27:72] + node _T_1204 = eq(_T_1203, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:150] + node _T_1205 = and(_T_1187, _T_1204) @[el2_lsu_bus_buffer.scala 339:148] + node _T_1206 = eq(_T_1205, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 339:8] + node _T_1207 = or(_T_1206, found_cmdptr1) @[el2_lsu_bus_buffer.scala 339:181] + node _T_1208 = cat(buf_nomerge[3], buf_nomerge[2]) @[Cat.scala 29:58] + node _T_1209 = cat(_T_1208, buf_nomerge[1]) @[Cat.scala 29:58] + node _T_1210 = cat(_T_1209, buf_nomerge[0]) @[Cat.scala 29:58] + node _T_1211 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1212 = bits(_T_1210, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1213 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1214 = bits(_T_1210, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1215 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1216 = bits(_T_1210, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1217 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1218 = bits(_T_1210, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1219 = mux(_T_1211, _T_1212, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1220 = mux(_T_1213, _T_1214, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1221 = mux(_T_1215, _T_1216, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1222 = mux(_T_1217, _T_1218, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1223 = or(_T_1219, _T_1220) @[Mux.scala 27:72] + node _T_1224 = or(_T_1223, _T_1221) @[Mux.scala 27:72] + node _T_1225 = or(_T_1224, _T_1222) @[Mux.scala 27:72] + wire _T_1226 : UInt<1> @[Mux.scala 27:72] + _T_1226 <= _T_1225 @[Mux.scala 27:72] + node _T_1227 = or(_T_1207, _T_1226) @[el2_lsu_bus_buffer.scala 339:197] + node _T_1228 = or(_T_1227, obuf_force_wr_en) @[el2_lsu_bus_buffer.scala 339:269] + node _T_1229 = and(_T_1148, _T_1228) @[el2_lsu_bus_buffer.scala 338:164] + node _T_1230 = or(_T_1094, _T_1229) @[el2_lsu_bus_buffer.scala 336:98] + node _T_1231 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:48] + node _T_1232 = or(bus_cmd_ready, _T_1231) @[el2_lsu_bus_buffer.scala 340:46] + node _T_1233 = or(_T_1232, obuf_nosend) @[el2_lsu_bus_buffer.scala 340:60] + node _T_1234 = and(_T_1230, _T_1233) @[el2_lsu_bus_buffer.scala 340:29] + node _T_1235 = eq(obuf_wr_wait, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:77] + node _T_1236 = and(_T_1234, _T_1235) @[el2_lsu_bus_buffer.scala 340:75] + node _T_1237 = eq(lsu_bus_cntr_overflow, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:93] + node _T_1238 = and(_T_1236, _T_1237) @[el2_lsu_bus_buffer.scala 340:91] + node _T_1239 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 340:118] + node _T_1240 = and(_T_1238, _T_1239) @[el2_lsu_bus_buffer.scala 340:116] + node _T_1241 = and(_T_1240, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 340:142] + obuf_wr_en <= _T_1241 @[el2_lsu_bus_buffer.scala 336:14] + wire bus_cmd_sent : UInt<1> + bus_cmd_sent <= UInt<1>("h00") + node _T_1242 = and(obuf_valid, obuf_nosend) @[el2_lsu_bus_buffer.scala 342:47] + node _T_1243 = or(bus_cmd_sent, _T_1242) @[el2_lsu_bus_buffer.scala 342:33] + node _T_1244 = eq(obuf_wr_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 342:65] + node _T_1245 = and(_T_1243, _T_1244) @[el2_lsu_bus_buffer.scala 342:63] + node _T_1246 = and(_T_1245, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 342:77] + node obuf_rst = or(_T_1246, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 342:98] + node _T_1247 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1248 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1249 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1250 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1251 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1252 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1253 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1254 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1255 = mux(_T_1247, _T_1248, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1256 = mux(_T_1249, _T_1250, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1257 = mux(_T_1251, _T_1252, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1258 = mux(_T_1253, _T_1254, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1259 = or(_T_1255, _T_1256) @[Mux.scala 27:72] + node _T_1260 = or(_T_1259, _T_1257) @[Mux.scala 27:72] + node _T_1261 = or(_T_1260, _T_1258) @[Mux.scala 27:72] + wire _T_1262 : UInt<1> @[Mux.scala 27:72] + _T_1262 <= _T_1261 @[Mux.scala 27:72] + node obuf_write_in = mux(ibuf_buf_byp, io.lsu_pkt_r.store, _T_1262) @[el2_lsu_bus_buffer.scala 343:26] + node _T_1263 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1264 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1265 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1266 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1267 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1268 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1269 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1270 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1271 = mux(_T_1263, _T_1264, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1272 = mux(_T_1265, _T_1266, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1273 = mux(_T_1267, _T_1268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1274 = mux(_T_1269, _T_1270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1275 = or(_T_1271, _T_1272) @[Mux.scala 27:72] + node _T_1276 = or(_T_1275, _T_1273) @[Mux.scala 27:72] + node _T_1277 = or(_T_1276, _T_1274) @[Mux.scala 27:72] + wire _T_1278 : UInt<1> @[Mux.scala 27:72] + _T_1278 <= _T_1277 @[Mux.scala 27:72] + node obuf_sideeffect_in = mux(ibuf_buf_byp, io.is_sideeffects_r, _T_1278) @[el2_lsu_bus_buffer.scala 344:31] + node _T_1279 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1280 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1281 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1282 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1283 = mux(_T_1279, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1284 = mux(_T_1280, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1285 = mux(_T_1281, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1286 = mux(_T_1282, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1287 = or(_T_1283, _T_1284) @[Mux.scala 27:72] + node _T_1288 = or(_T_1287, _T_1285) @[Mux.scala 27:72] + node _T_1289 = or(_T_1288, _T_1286) @[Mux.scala 27:72] + wire _T_1290 : UInt<32> @[Mux.scala 27:72] + _T_1290 <= _T_1289 @[Mux.scala 27:72] + node obuf_addr_in = mux(ibuf_buf_byp, io.lsu_addr_r, _T_1290) @[el2_lsu_bus_buffer.scala 345:25] + wire buf_sz : UInt<2>[4] @[el2_lsu_bus_buffer.scala 346:20] + buf_sz[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + buf_sz[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 347:10] + node _T_1291 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_1292 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1293 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1294 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1295 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1296 = mux(_T_1292, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1297 = mux(_T_1293, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1298 = mux(_T_1294, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1299 = mux(_T_1295, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1300 = or(_T_1296, _T_1297) @[Mux.scala 27:72] + node _T_1301 = or(_T_1300, _T_1298) @[Mux.scala 27:72] + node _T_1302 = or(_T_1301, _T_1299) @[Mux.scala 27:72] + wire _T_1303 : UInt<2> @[Mux.scala 27:72] + _T_1303 <= _T_1302 @[Mux.scala 27:72] + node obuf_sz_in = mux(ibuf_buf_byp, _T_1291, _T_1303) @[el2_lsu_bus_buffer.scala 348:23] + wire obuf_merge_en : UInt<1> + obuf_merge_en <= UInt<1>("h00") + node obuf_tag0_in = mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) @[el2_lsu_bus_buffer.scala 351:25] + wire Cmdptr1 : UInt<2> + Cmdptr1 <= UInt<1>("h00") + node obuf_tag1_in = mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) @[el2_lsu_bus_buffer.scala 354:25] + wire obuf_cmd_done : UInt<1> + obuf_cmd_done <= UInt<1>("h00") + wire bus_wcmd_sent : UInt<1> + bus_wcmd_sent <= UInt<1>("h00") + node _T_1304 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 357:39] + node _T_1305 = eq(_T_1304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 357:26] + node _T_1306 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 357:68] + node obuf_cmd_done_in = and(_T_1305, _T_1306) @[el2_lsu_bus_buffer.scala 357:51] + wire obuf_data_done : UInt<1> + obuf_data_done <= UInt<1>("h00") + wire bus_wdata_sent : UInt<1> + bus_wdata_sent <= UInt<1>("h00") + node _T_1307 = or(obuf_wr_en, obuf_rst) @[el2_lsu_bus_buffer.scala 360:40] + node _T_1308 = eq(_T_1307, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 360:27] + node _T_1309 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 360:70] + node obuf_data_done_in = and(_T_1308, _T_1309) @[el2_lsu_bus_buffer.scala 360:52] + node _T_1310 = bits(obuf_sz_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:67] + node _T_1311 = eq(_T_1310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:72] + node _T_1312 = bits(obuf_sz_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:92] + node _T_1313 = bits(obuf_addr_in, 0, 0) @[el2_lsu_bus_buffer.scala 361:111] + node _T_1314 = eq(_T_1313, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:98] + node _T_1315 = and(_T_1312, _T_1314) @[el2_lsu_bus_buffer.scala 361:96] + node _T_1316 = or(_T_1311, _T_1315) @[el2_lsu_bus_buffer.scala 361:79] + node _T_1317 = bits(obuf_sz_in, 1, 1) @[el2_lsu_bus_buffer.scala 361:129] + node _T_1318 = bits(obuf_addr_in, 1, 0) @[el2_lsu_bus_buffer.scala 361:147] + node _T_1319 = orr(_T_1318) @[el2_lsu_bus_buffer.scala 361:153] + node _T_1320 = eq(_T_1319, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 361:134] + node _T_1321 = and(_T_1317, _T_1320) @[el2_lsu_bus_buffer.scala 361:132] + node _T_1322 = or(_T_1316, _T_1321) @[el2_lsu_bus_buffer.scala 361:116] + node obuf_aligned_in = mux(ibuf_buf_byp, is_aligned_r, _T_1322) @[el2_lsu_bus_buffer.scala 361:28] + wire obuf_nosend_in : UInt<1> + obuf_nosend_in <= UInt<1>("h00") + wire obuf_rdrsp_pend : UInt<1> + obuf_rdrsp_pend <= UInt<1>("h00") + wire bus_rsp_read : UInt<1> + bus_rsp_read <= UInt<1>("h00") + wire bus_rsp_read_tag : UInt<3> + bus_rsp_read_tag <= UInt<1>("h00") + wire obuf_rdrsp_tag : UInt<3> + obuf_rdrsp_tag <= UInt<1>("h00") + wire obuf_write : UInt<1> + obuf_write <= UInt<1>("h00") + node _T_1323 = eq(obuf_nosend_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:44] + node _T_1324 = and(obuf_wr_en, _T_1323) @[el2_lsu_bus_buffer.scala 369:42] + node _T_1325 = eq(_T_1324, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:29] + node _T_1326 = and(_T_1325, obuf_rdrsp_pend) @[el2_lsu_bus_buffer.scala 369:61] + node _T_1327 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 369:116] + node _T_1328 = and(bus_rsp_read, _T_1327) @[el2_lsu_bus_buffer.scala 369:96] + node _T_1329 = eq(_T_1328, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 369:81] + node _T_1330 = and(_T_1326, _T_1329) @[el2_lsu_bus_buffer.scala 369:79] + node _T_1331 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:22] + node _T_1332 = and(bus_cmd_sent, _T_1331) @[el2_lsu_bus_buffer.scala 370:20] + node _T_1333 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 370:37] + node _T_1334 = and(_T_1332, _T_1333) @[el2_lsu_bus_buffer.scala 370:35] + node obuf_rdrsp_pend_in = or(_T_1330, _T_1334) @[el2_lsu_bus_buffer.scala 369:138] + wire obuf_tag0 : UInt<3> + obuf_tag0 <= UInt<1>("h00") + node _T_1335 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 372:46] + node _T_1336 = and(bus_cmd_sent, _T_1335) @[el2_lsu_bus_buffer.scala 372:44] + node obuf_rdrsp_tag_in = mux(_T_1336, obuf_tag0, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 372:30] + wire obuf_addr : UInt<32> + obuf_addr <= UInt<1>("h00") + wire obuf_sideeffect : UInt<1> + obuf_sideeffect <= UInt<1>("h00") + node _T_1337 = bits(obuf_addr_in, 31, 3) @[el2_lsu_bus_buffer.scala 375:34] + node _T_1338 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 375:52] + node _T_1339 = eq(_T_1337, _T_1338) @[el2_lsu_bus_buffer.scala 375:40] + node _T_1340 = and(_T_1339, obuf_aligned_in) @[el2_lsu_bus_buffer.scala 375:60] + node _T_1341 = eq(obuf_sideeffect, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:80] + node _T_1342 = and(_T_1340, _T_1341) @[el2_lsu_bus_buffer.scala 375:78] + node _T_1343 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:99] + node _T_1344 = and(_T_1342, _T_1343) @[el2_lsu_bus_buffer.scala 375:97] + node _T_1345 = eq(obuf_write_in, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:113] + node _T_1346 = and(_T_1344, _T_1345) @[el2_lsu_bus_buffer.scala 375:111] + node _T_1347 = eq(io.dec_tlu_external_ldfwd_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 375:130] + node _T_1348 = and(_T_1346, _T_1347) @[el2_lsu_bus_buffer.scala 375:128] + node _T_1349 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:20] + node _T_1350 = and(obuf_valid, _T_1349) @[el2_lsu_bus_buffer.scala 376:18] + node _T_1351 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 376:90] + node _T_1352 = and(bus_rsp_read, _T_1351) @[el2_lsu_bus_buffer.scala 376:70] + node _T_1353 = eq(_T_1352, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 376:55] + node _T_1354 = and(obuf_rdrsp_pend, _T_1353) @[el2_lsu_bus_buffer.scala 376:53] + node _T_1355 = or(_T_1350, _T_1354) @[el2_lsu_bus_buffer.scala 376:34] + node _T_1356 = and(_T_1348, _T_1355) @[el2_lsu_bus_buffer.scala 375:165] + obuf_nosend_in <= _T_1356 @[el2_lsu_bus_buffer.scala 375:18] + node _T_1357 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 377:60] + node _T_1358 = cat(ldst_byteen_lo_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1359 = cat(UInt<4>("h00"), ldst_byteen_lo_r) @[Cat.scala 29:58] + node _T_1360 = mux(_T_1357, _T_1358, _T_1359) @[el2_lsu_bus_buffer.scala 377:46] + node _T_1361 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1362 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1363 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1364 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1365 = mux(_T_1361, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1366 = mux(_T_1362, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1367 = mux(_T_1363, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1368 = mux(_T_1364, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1369 = or(_T_1365, _T_1366) @[Mux.scala 27:72] + node _T_1370 = or(_T_1369, _T_1367) @[Mux.scala 27:72] + node _T_1371 = or(_T_1370, _T_1368) @[Mux.scala 27:72] + wire _T_1372 : UInt<32> @[Mux.scala 27:72] + _T_1372 <= _T_1371 @[Mux.scala 27:72] + node _T_1373 = bits(_T_1372, 2, 2) @[el2_lsu_bus_buffer.scala 378:36] + node _T_1374 = bits(_T_1373, 0, 0) @[el2_lsu_bus_buffer.scala 378:46] + node _T_1375 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1376 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1377 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1378 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1379 = mux(_T_1375, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1380 = mux(_T_1376, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1381 = mux(_T_1377, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1382 = mux(_T_1378, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1383 = or(_T_1379, _T_1380) @[Mux.scala 27:72] + node _T_1384 = or(_T_1383, _T_1381) @[Mux.scala 27:72] + node _T_1385 = or(_T_1384, _T_1382) @[Mux.scala 27:72] + wire _T_1386 : UInt<4> @[Mux.scala 27:72] + _T_1386 <= _T_1385 @[Mux.scala 27:72] + node _T_1387 = cat(_T_1386, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1388 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1389 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1390 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1391 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1392 = mux(_T_1388, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1393 = mux(_T_1389, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1394 = mux(_T_1390, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1395 = mux(_T_1391, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1396 = or(_T_1392, _T_1393) @[Mux.scala 27:72] + node _T_1397 = or(_T_1396, _T_1394) @[Mux.scala 27:72] + node _T_1398 = or(_T_1397, _T_1395) @[Mux.scala 27:72] + wire _T_1399 : UInt<4> @[Mux.scala 27:72] + _T_1399 <= _T_1398 @[Mux.scala 27:72] + node _T_1400 = cat(UInt<4>("h00"), _T_1399) @[Cat.scala 29:58] + node _T_1401 = mux(_T_1374, _T_1387, _T_1400) @[el2_lsu_bus_buffer.scala 378:8] + node obuf_byteen0_in = mux(ibuf_buf_byp, _T_1360, _T_1401) @[el2_lsu_bus_buffer.scala 377:28] + node _T_1402 = bits(io.end_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 379:60] + node _T_1403 = cat(ldst_byteen_hi_r, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1404 = cat(UInt<4>("h00"), ldst_byteen_hi_r) @[Cat.scala 29:58] + node _T_1405 = mux(_T_1402, _T_1403, _T_1404) @[el2_lsu_bus_buffer.scala 379:46] + node _T_1406 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1407 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1408 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1409 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1410 = mux(_T_1406, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1411 = mux(_T_1407, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1412 = mux(_T_1408, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1413 = mux(_T_1409, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1414 = or(_T_1410, _T_1411) @[Mux.scala 27:72] + node _T_1415 = or(_T_1414, _T_1412) @[Mux.scala 27:72] + node _T_1416 = or(_T_1415, _T_1413) @[Mux.scala 27:72] + wire _T_1417 : UInt<32> @[Mux.scala 27:72] + _T_1417 <= _T_1416 @[Mux.scala 27:72] + node _T_1418 = bits(_T_1417, 2, 2) @[el2_lsu_bus_buffer.scala 380:36] + node _T_1419 = bits(_T_1418, 0, 0) @[el2_lsu_bus_buffer.scala 380:46] + node _T_1420 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1421 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1422 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1423 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1424 = mux(_T_1420, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1425 = mux(_T_1421, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1426 = mux(_T_1422, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1427 = mux(_T_1423, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1428 = or(_T_1424, _T_1425) @[Mux.scala 27:72] + node _T_1429 = or(_T_1428, _T_1426) @[Mux.scala 27:72] + node _T_1430 = or(_T_1429, _T_1427) @[Mux.scala 27:72] + wire _T_1431 : UInt<4> @[Mux.scala 27:72] + _T_1431 <= _T_1430 @[Mux.scala 27:72] + node _T_1432 = cat(_T_1431, UInt<4>("h00")) @[Cat.scala 29:58] + node _T_1433 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1434 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1435 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1436 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1437 = mux(_T_1433, buf_byteen[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1438 = mux(_T_1434, buf_byteen[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1439 = mux(_T_1435, buf_byteen[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1440 = mux(_T_1436, buf_byteen[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1441 = or(_T_1437, _T_1438) @[Mux.scala 27:72] + node _T_1442 = or(_T_1441, _T_1439) @[Mux.scala 27:72] + node _T_1443 = or(_T_1442, _T_1440) @[Mux.scala 27:72] + wire _T_1444 : UInt<4> @[Mux.scala 27:72] + _T_1444 <= _T_1443 @[Mux.scala 27:72] + node _T_1445 = cat(UInt<4>("h00"), _T_1444) @[Cat.scala 29:58] + node _T_1446 = mux(_T_1419, _T_1432, _T_1445) @[el2_lsu_bus_buffer.scala 380:8] + node obuf_byteen1_in = mux(ibuf_buf_byp, _T_1405, _T_1446) @[el2_lsu_bus_buffer.scala 379:28] + node _T_1447 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 382:58] + node _T_1448 = cat(store_data_lo_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1449 = cat(UInt<32>("h00"), store_data_lo_r) @[Cat.scala 29:58] + node _T_1450 = mux(_T_1447, _T_1448, _T_1449) @[el2_lsu_bus_buffer.scala 382:44] + node _T_1451 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1452 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1453 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1454 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1455 = mux(_T_1451, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1456 = mux(_T_1452, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1457 = mux(_T_1453, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1458 = mux(_T_1454, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1459 = or(_T_1455, _T_1456) @[Mux.scala 27:72] + node _T_1460 = or(_T_1459, _T_1457) @[Mux.scala 27:72] + node _T_1461 = or(_T_1460, _T_1458) @[Mux.scala 27:72] + wire _T_1462 : UInt<32> @[Mux.scala 27:72] + _T_1462 <= _T_1461 @[Mux.scala 27:72] + node _T_1463 = bits(_T_1462, 2, 2) @[el2_lsu_bus_buffer.scala 383:36] + node _T_1464 = bits(_T_1463, 0, 0) @[el2_lsu_bus_buffer.scala 383:46] + node _T_1465 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1466 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1467 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1468 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1469 = mux(_T_1465, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1470 = mux(_T_1466, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1471 = mux(_T_1467, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1472 = mux(_T_1468, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1473 = or(_T_1469, _T_1470) @[Mux.scala 27:72] + node _T_1474 = or(_T_1473, _T_1471) @[Mux.scala 27:72] + node _T_1475 = or(_T_1474, _T_1472) @[Mux.scala 27:72] + wire _T_1476 : UInt<32> @[Mux.scala 27:72] + _T_1476 <= _T_1475 @[Mux.scala 27:72] + node _T_1477 = cat(_T_1476, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1478 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1479 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1480 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1481 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1482 = mux(_T_1478, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1483 = mux(_T_1479, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1484 = mux(_T_1480, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1485 = mux(_T_1481, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1486 = or(_T_1482, _T_1483) @[Mux.scala 27:72] + node _T_1487 = or(_T_1486, _T_1484) @[Mux.scala 27:72] + node _T_1488 = or(_T_1487, _T_1485) @[Mux.scala 27:72] + wire _T_1489 : UInt<32> @[Mux.scala 27:72] + _T_1489 <= _T_1488 @[Mux.scala 27:72] + node _T_1490 = cat(UInt<32>("h00"), _T_1489) @[Cat.scala 29:58] + node _T_1491 = mux(_T_1464, _T_1477, _T_1490) @[el2_lsu_bus_buffer.scala 383:8] + node obuf_data0_in = mux(ibuf_buf_byp, _T_1450, _T_1491) @[el2_lsu_bus_buffer.scala 382:26] + node _T_1492 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_buffer.scala 384:58] + node _T_1493 = cat(store_data_hi_r, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1494 = cat(UInt<32>("h00"), store_data_hi_r) @[Cat.scala 29:58] + node _T_1495 = mux(_T_1492, _T_1493, _T_1494) @[el2_lsu_bus_buffer.scala 384:44] + node _T_1496 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1497 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1498 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1499 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1500 = mux(_T_1496, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1501 = mux(_T_1497, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1502 = mux(_T_1498, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1503 = mux(_T_1499, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1504 = or(_T_1500, _T_1501) @[Mux.scala 27:72] + node _T_1505 = or(_T_1504, _T_1502) @[Mux.scala 27:72] + node _T_1506 = or(_T_1505, _T_1503) @[Mux.scala 27:72] + wire _T_1507 : UInt<32> @[Mux.scala 27:72] + _T_1507 <= _T_1506 @[Mux.scala 27:72] + node _T_1508 = bits(_T_1507, 2, 2) @[el2_lsu_bus_buffer.scala 385:36] + node _T_1509 = bits(_T_1508, 0, 0) @[el2_lsu_bus_buffer.scala 385:46] + node _T_1510 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1511 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1512 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1513 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1514 = mux(_T_1510, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1515 = mux(_T_1511, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1516 = mux(_T_1512, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1517 = mux(_T_1513, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1518 = or(_T_1514, _T_1515) @[Mux.scala 27:72] + node _T_1519 = or(_T_1518, _T_1516) @[Mux.scala 27:72] + node _T_1520 = or(_T_1519, _T_1517) @[Mux.scala 27:72] + wire _T_1521 : UInt<32> @[Mux.scala 27:72] + _T_1521 <= _T_1520 @[Mux.scala 27:72] + node _T_1522 = cat(_T_1521, UInt<32>("h00")) @[Cat.scala 29:58] + node _T_1523 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1524 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1525 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1526 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1527 = mux(_T_1523, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1528 = mux(_T_1524, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1529 = mux(_T_1525, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1530 = mux(_T_1526, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1531 = or(_T_1527, _T_1528) @[Mux.scala 27:72] + node _T_1532 = or(_T_1531, _T_1529) @[Mux.scala 27:72] + node _T_1533 = or(_T_1532, _T_1530) @[Mux.scala 27:72] + wire _T_1534 : UInt<32> @[Mux.scala 27:72] + _T_1534 <= _T_1533 @[Mux.scala 27:72] + node _T_1535 = cat(UInt<32>("h00"), _T_1534) @[Cat.scala 29:58] + node _T_1536 = mux(_T_1509, _T_1522, _T_1535) @[el2_lsu_bus_buffer.scala 385:8] + node obuf_data1_in = mux(ibuf_buf_byp, _T_1495, _T_1536) @[el2_lsu_bus_buffer.scala 384:26] + node _T_1537 = bits(obuf_byteen0_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1538 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1539 = and(obuf_merge_en, _T_1538) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1540 = or(_T_1537, _T_1539) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1541 = bits(obuf_byteen0_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1542 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1543 = and(obuf_merge_en, _T_1542) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1544 = or(_T_1541, _T_1543) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1545 = bits(obuf_byteen0_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1546 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1547 = and(obuf_merge_en, _T_1546) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1548 = or(_T_1545, _T_1547) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1549 = bits(obuf_byteen0_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1550 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1551 = and(obuf_merge_en, _T_1550) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1552 = or(_T_1549, _T_1551) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1553 = bits(obuf_byteen0_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1554 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1555 = and(obuf_merge_en, _T_1554) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1556 = or(_T_1553, _T_1555) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1557 = bits(obuf_byteen0_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1558 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1559 = and(obuf_merge_en, _T_1558) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1560 = or(_T_1557, _T_1559) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1561 = bits(obuf_byteen0_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1562 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1563 = and(obuf_merge_en, _T_1562) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1564 = or(_T_1561, _T_1563) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1565 = bits(obuf_byteen0_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:59] + node _T_1566 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 386:97] + node _T_1567 = and(obuf_merge_en, _T_1566) @[el2_lsu_bus_buffer.scala 386:80] + node _T_1568 = or(_T_1565, _T_1567) @[el2_lsu_bus_buffer.scala 386:63] + node _T_1569 = cat(_T_1568, _T_1564) @[Cat.scala 29:58] + node _T_1570 = cat(_T_1569, _T_1560) @[Cat.scala 29:58] + node _T_1571 = cat(_T_1570, _T_1556) @[Cat.scala 29:58] + node _T_1572 = cat(_T_1571, _T_1552) @[Cat.scala 29:58] + node _T_1573 = cat(_T_1572, _T_1548) @[Cat.scala 29:58] + node _T_1574 = cat(_T_1573, _T_1544) @[Cat.scala 29:58] + node obuf_byteen_in = cat(_T_1574, _T_1540) @[Cat.scala 29:58] + node _T_1575 = bits(obuf_byteen1_in, 0, 0) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1576 = and(obuf_merge_en, _T_1575) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1577 = bits(obuf_data1_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1578 = bits(obuf_data0_in, 7, 0) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1579 = mux(_T_1576, _T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1580 = bits(obuf_byteen1_in, 1, 1) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1581 = and(obuf_merge_en, _T_1580) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1582 = bits(obuf_data1_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1583 = bits(obuf_data0_in, 15, 8) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1584 = mux(_T_1581, _T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1585 = bits(obuf_byteen1_in, 2, 2) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1586 = and(obuf_merge_en, _T_1585) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1587 = bits(obuf_data1_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1588 = bits(obuf_data0_in, 23, 16) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1589 = mux(_T_1586, _T_1587, _T_1588) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1590 = bits(obuf_byteen1_in, 3, 3) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1591 = and(obuf_merge_en, _T_1590) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1592 = bits(obuf_data1_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1593 = bits(obuf_data0_in, 31, 24) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1594 = mux(_T_1591, _T_1592, _T_1593) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1595 = bits(obuf_byteen1_in, 4, 4) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1596 = and(obuf_merge_en, _T_1595) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1597 = bits(obuf_data1_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1598 = bits(obuf_data0_in, 39, 32) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1599 = mux(_T_1596, _T_1597, _T_1598) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1600 = bits(obuf_byteen1_in, 5, 5) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1601 = and(obuf_merge_en, _T_1600) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1602 = bits(obuf_data1_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1603 = bits(obuf_data0_in, 47, 40) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1604 = mux(_T_1601, _T_1602, _T_1603) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1605 = bits(obuf_byteen1_in, 6, 6) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1606 = and(obuf_merge_en, _T_1605) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1607 = bits(obuf_data1_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1608 = bits(obuf_data0_in, 55, 48) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1609 = mux(_T_1606, _T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1610 = bits(obuf_byteen1_in, 7, 7) @[el2_lsu_bus_buffer.scala 387:76] + node _T_1611 = and(obuf_merge_en, _T_1610) @[el2_lsu_bus_buffer.scala 387:59] + node _T_1612 = bits(obuf_data1_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:94] + node _T_1613 = bits(obuf_data0_in, 63, 56) @[el2_lsu_bus_buffer.scala 387:123] + node _T_1614 = mux(_T_1611, _T_1612, _T_1613) @[el2_lsu_bus_buffer.scala 387:44] + node _T_1615 = cat(_T_1614, _T_1609) @[Cat.scala 29:58] + node _T_1616 = cat(_T_1615, _T_1604) @[Cat.scala 29:58] + node _T_1617 = cat(_T_1616, _T_1599) @[Cat.scala 29:58] + node _T_1618 = cat(_T_1617, _T_1594) @[Cat.scala 29:58] + node _T_1619 = cat(_T_1618, _T_1589) @[Cat.scala 29:58] + node _T_1620 = cat(_T_1619, _T_1584) @[Cat.scala 29:58] + node obuf_data_in = cat(_T_1620, _T_1579) @[Cat.scala 29:58] + wire buf_dualhi : UInt<1>[4] @[el2_lsu_bus_buffer.scala 389:24] + buf_dualhi[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + buf_dualhi[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 390:14] + node _T_1621 = neq(CmdPtr0, Cmdptr1) @[el2_lsu_bus_buffer.scala 391:30] + node _T_1622 = and(_T_1621, found_cmdptr0) @[el2_lsu_bus_buffer.scala 391:43] + node _T_1623 = and(_T_1622, found_cmdptr1) @[el2_lsu_bus_buffer.scala 391:59] + node _T_1624 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1625 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1626 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1627 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1628 = mux(_T_1624, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1629 = mux(_T_1625, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1630 = mux(_T_1626, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1631 = mux(_T_1627, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1632 = or(_T_1628, _T_1629) @[Mux.scala 27:72] + node _T_1633 = or(_T_1632, _T_1630) @[Mux.scala 27:72] + node _T_1634 = or(_T_1633, _T_1631) @[Mux.scala 27:72] + wire _T_1635 : UInt<3> @[Mux.scala 27:72] + _T_1635 <= _T_1634 @[Mux.scala 27:72] + node _T_1636 = eq(_T_1635, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:107] + node _T_1637 = and(_T_1623, _T_1636) @[el2_lsu_bus_buffer.scala 391:75] + node _T_1638 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1639 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1640 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1641 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1642 = mux(_T_1638, buf_state[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1643 = mux(_T_1639, buf_state[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1644 = mux(_T_1640, buf_state[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1645 = mux(_T_1641, buf_state[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1646 = or(_T_1642, _T_1643) @[Mux.scala 27:72] + node _T_1647 = or(_T_1646, _T_1644) @[Mux.scala 27:72] + node _T_1648 = or(_T_1647, _T_1645) @[Mux.scala 27:72] + wire _T_1649 : UInt<3> @[Mux.scala 27:72] + _T_1649 <= _T_1648 @[Mux.scala 27:72] + node _T_1650 = eq(_T_1649, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 391:150] + node _T_1651 = and(_T_1637, _T_1650) @[el2_lsu_bus_buffer.scala 391:118] + node _T_1652 = cat(buf_cmd_state_bus_en[3], buf_cmd_state_bus_en[2]) @[Cat.scala 29:58] + node _T_1653 = cat(_T_1652, buf_cmd_state_bus_en[1]) @[Cat.scala 29:58] + node _T_1654 = cat(_T_1653, buf_cmd_state_bus_en[0]) @[Cat.scala 29:58] + node _T_1655 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1656 = bits(_T_1654, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1657 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1658 = bits(_T_1654, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1659 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1660 = bits(_T_1654, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1661 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1662 = bits(_T_1654, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1663 = mux(_T_1655, _T_1656, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1664 = mux(_T_1657, _T_1658, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1665 = mux(_T_1659, _T_1660, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1666 = mux(_T_1661, _T_1662, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1667 = or(_T_1663, _T_1664) @[Mux.scala 27:72] + node _T_1668 = or(_T_1667, _T_1665) @[Mux.scala 27:72] + node _T_1669 = or(_T_1668, _T_1666) @[Mux.scala 27:72] + wire _T_1670 : UInt<1> @[Mux.scala 27:72] + _T_1670 <= _T_1669 @[Mux.scala 27:72] + node _T_1671 = eq(_T_1670, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:5] + node _T_1672 = and(_T_1651, _T_1671) @[el2_lsu_bus_buffer.scala 391:161] + node _T_1673 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1674 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1675 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1676 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1677 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1678 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1679 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1680 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1681 = mux(_T_1673, _T_1674, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1682 = mux(_T_1675, _T_1676, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1683 = mux(_T_1677, _T_1678, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1684 = mux(_T_1679, _T_1680, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1685 = or(_T_1681, _T_1682) @[Mux.scala 27:72] + node _T_1686 = or(_T_1685, _T_1683) @[Mux.scala 27:72] + node _T_1687 = or(_T_1686, _T_1684) @[Mux.scala 27:72] + wire _T_1688 : UInt<1> @[Mux.scala 27:72] + _T_1688 <= _T_1687 @[Mux.scala 27:72] + node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 392:87] + node _T_1690 = and(_T_1672, _T_1689) @[el2_lsu_bus_buffer.scala 392:85] + node _T_1691 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1692 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1693 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1694 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1695 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1696 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1697 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1698 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1699 = mux(_T_1691, _T_1692, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1700 = mux(_T_1693, _T_1694, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1701 = mux(_T_1695, _T_1696, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1702 = mux(_T_1697, _T_1698, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1703 = or(_T_1699, _T_1700) @[Mux.scala 27:72] + node _T_1704 = or(_T_1703, _T_1701) @[Mux.scala 27:72] + node _T_1705 = or(_T_1704, _T_1702) @[Mux.scala 27:72] + wire _T_1706 : UInt<1> @[Mux.scala 27:72] + _T_1706 <= _T_1705 @[Mux.scala 27:72] + node _T_1707 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1708 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1709 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1710 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1711 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1712 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1713 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1714 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1715 = mux(_T_1707, _T_1708, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1716 = mux(_T_1709, _T_1710, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1717 = mux(_T_1711, _T_1712, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1718 = mux(_T_1713, _T_1714, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1719 = or(_T_1715, _T_1716) @[Mux.scala 27:72] + node _T_1720 = or(_T_1719, _T_1717) @[Mux.scala 27:72] + node _T_1721 = or(_T_1720, _T_1718) @[Mux.scala 27:72] + wire _T_1722 : UInt<1> @[Mux.scala 27:72] + _T_1722 <= _T_1721 @[Mux.scala 27:72] + node _T_1723 = and(_T_1706, _T_1722) @[el2_lsu_bus_buffer.scala 393:36] + node _T_1724 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1725 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1726 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1727 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1728 = mux(_T_1724, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1729 = mux(_T_1725, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1730 = mux(_T_1726, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1731 = mux(_T_1727, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1732 = or(_T_1728, _T_1729) @[Mux.scala 27:72] + node _T_1733 = or(_T_1732, _T_1730) @[Mux.scala 27:72] + node _T_1734 = or(_T_1733, _T_1731) @[Mux.scala 27:72] + wire _T_1735 : UInt<32> @[Mux.scala 27:72] + _T_1735 <= _T_1734 @[Mux.scala 27:72] + node _T_1736 = bits(_T_1735, 31, 3) @[el2_lsu_bus_buffer.scala 394:35] + node _T_1737 = eq(Cmdptr1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1738 = eq(Cmdptr1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1739 = eq(Cmdptr1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1740 = eq(Cmdptr1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_1741 = mux(_T_1737, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1742 = mux(_T_1738, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1743 = mux(_T_1739, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1744 = mux(_T_1740, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1745 = or(_T_1741, _T_1742) @[Mux.scala 27:72] + node _T_1746 = or(_T_1745, _T_1743) @[Mux.scala 27:72] + node _T_1747 = or(_T_1746, _T_1744) @[Mux.scala 27:72] + wire _T_1748 : UInt<32> @[Mux.scala 27:72] + _T_1748 <= _T_1747 @[Mux.scala 27:72] + node _T_1749 = bits(_T_1748, 31, 3) @[el2_lsu_bus_buffer.scala 394:71] + node _T_1750 = eq(_T_1736, _T_1749) @[el2_lsu_bus_buffer.scala 394:41] + node _T_1751 = and(_T_1723, _T_1750) @[el2_lsu_bus_buffer.scala 393:67] + node _T_1752 = eq(bus_coalescing_disable, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:81] + node _T_1753 = and(_T_1751, _T_1752) @[el2_lsu_bus_buffer.scala 394:79] + node _T_1754 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 394:107] + node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 394:105] + node _T_1756 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1757 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1758 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1759 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1760 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1761 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1762 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1763 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1764 = mux(_T_1756, _T_1757, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1765 = mux(_T_1758, _T_1759, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1766 = mux(_T_1760, _T_1761, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1767 = mux(_T_1762, _T_1763, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1768 = or(_T_1764, _T_1765) @[Mux.scala 27:72] + node _T_1769 = or(_T_1768, _T_1766) @[Mux.scala 27:72] + node _T_1770 = or(_T_1769, _T_1767) @[Mux.scala 27:72] + wire _T_1771 : UInt<1> @[Mux.scala 27:72] + _T_1771 <= _T_1770 @[Mux.scala 27:72] + node _T_1772 = eq(_T_1771, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:8] + node _T_1773 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_1774 = cat(_T_1773, buf_dual[1]) @[Cat.scala 29:58] + node _T_1775 = cat(_T_1774, buf_dual[0]) @[Cat.scala 29:58] + node _T_1776 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1777 = bits(_T_1775, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1778 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1779 = bits(_T_1775, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1780 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1781 = bits(_T_1775, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1782 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1783 = bits(_T_1775, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1784 = mux(_T_1776, _T_1777, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1785 = mux(_T_1778, _T_1779, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1786 = mux(_T_1780, _T_1781, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1787 = mux(_T_1782, _T_1783, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1788 = or(_T_1784, _T_1785) @[Mux.scala 27:72] + node _T_1789 = or(_T_1788, _T_1786) @[Mux.scala 27:72] + node _T_1790 = or(_T_1789, _T_1787) @[Mux.scala 27:72] + wire _T_1791 : UInt<1> @[Mux.scala 27:72] + _T_1791 <= _T_1790 @[Mux.scala 27:72] + node _T_1792 = and(_T_1772, _T_1791) @[el2_lsu_bus_buffer.scala 395:38] + node _T_1793 = cat(buf_dualhi[3], buf_dualhi[2]) @[Cat.scala 29:58] + node _T_1794 = cat(_T_1793, buf_dualhi[1]) @[Cat.scala 29:58] + node _T_1795 = cat(_T_1794, buf_dualhi[0]) @[Cat.scala 29:58] + node _T_1796 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1797 = bits(_T_1795, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1798 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1799 = bits(_T_1795, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1800 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1801 = bits(_T_1795, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1802 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1803 = bits(_T_1795, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1804 = mux(_T_1796, _T_1797, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1805 = mux(_T_1798, _T_1799, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1806 = mux(_T_1800, _T_1801, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1807 = mux(_T_1802, _T_1803, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1808 = or(_T_1804, _T_1805) @[Mux.scala 27:72] + node _T_1809 = or(_T_1808, _T_1806) @[Mux.scala 27:72] + node _T_1810 = or(_T_1809, _T_1807) @[Mux.scala 27:72] + wire _T_1811 : UInt<1> @[Mux.scala 27:72] + _T_1811 <= _T_1810 @[Mux.scala 27:72] + node _T_1812 = eq(_T_1811, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 395:109] + node _T_1813 = and(_T_1792, _T_1812) @[el2_lsu_bus_buffer.scala 395:107] + node _T_1814 = cat(buf_samedw[3], buf_samedw[2]) @[Cat.scala 29:58] + node _T_1815 = cat(_T_1814, buf_samedw[1]) @[Cat.scala 29:58] + node _T_1816 = cat(_T_1815, buf_samedw[0]) @[Cat.scala 29:58] + node _T_1817 = eq(CmdPtr0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1818 = bits(_T_1816, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1819 = eq(CmdPtr0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1820 = bits(_T_1816, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1821 = eq(CmdPtr0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1822 = bits(_T_1816, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1823 = eq(CmdPtr0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_1824 = bits(_T_1816, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_1825 = mux(_T_1817, _T_1818, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1826 = mux(_T_1819, _T_1820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1827 = mux(_T_1821, _T_1822, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1828 = mux(_T_1823, _T_1824, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1829 = or(_T_1825, _T_1826) @[Mux.scala 27:72] + node _T_1830 = or(_T_1829, _T_1827) @[Mux.scala 27:72] + node _T_1831 = or(_T_1830, _T_1828) @[Mux.scala 27:72] + wire _T_1832 : UInt<1> @[Mux.scala 27:72] + _T_1832 <= _T_1831 @[Mux.scala 27:72] + node _T_1833 = and(_T_1813, _T_1832) @[el2_lsu_bus_buffer.scala 395:179] + node _T_1834 = or(_T_1755, _T_1833) @[el2_lsu_bus_buffer.scala 394:128] + node _T_1835 = and(_T_1690, _T_1834) @[el2_lsu_bus_buffer.scala 392:122] + node _T_1836 = and(ibuf_buf_byp, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 396:19] + node _T_1837 = and(_T_1836, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 396:35] + node _T_1838 = or(_T_1835, _T_1837) @[el2_lsu_bus_buffer.scala 395:253] + obuf_merge_en <= _T_1838 @[el2_lsu_bus_buffer.scala 391:17] + reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 398:55] + obuf_wr_enQ <= obuf_wr_en @[el2_lsu_bus_buffer.scala 398:55] + node _T_1839 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 399:58] + node _T_1840 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 399:93] + node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 399:91] + reg _T_1842 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 399:54] + _T_1842 <= _T_1841 @[el2_lsu_bus_buffer.scala 399:54] + obuf_valid <= _T_1842 @[el2_lsu_bus_buffer.scala 399:14] + reg _T_1843 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1397 <= obuf_addr_in @[Reg.scala 28:23] + _T_1843 <= obuf_nosend_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_addr <= _T_1397 @[el2_lsu_bus_buffer.scala 520:25] - reg _T_1398 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_nosend <= _T_1843 @[el2_lsu_bus_buffer.scala 400:15] + reg _T_1844 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 401:54] + _T_1844 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 401:54] + obuf_cmd_done <= _T_1844 @[el2_lsu_bus_buffer.scala 401:17] + reg _T_1845 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 402:55] + _T_1845 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 402:55] + obuf_data_done <= _T_1845 @[el2_lsu_bus_buffer.scala 402:18] + reg _T_1846 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 403:56] + _T_1846 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 403:56] + obuf_rdrsp_pend <= _T_1846 @[el2_lsu_bus_buffer.scala 403:19] + reg _T_1847 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 404:55] + _T_1847 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 404:55] + obuf_rdrsp_tag <= _T_1847 @[el2_lsu_bus_buffer.scala 404:18] + reg _T_1848 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1398 <= obuf_data_in @[Reg.scala 28:23] + _T_1848 <= obuf_tag0_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_data <= _T_1398 @[el2_lsu_bus_buffer.scala 521:25] - reg _T_1399 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 523:35] - _T_1399 <= obuf_rdrsp_pend_in @[el2_lsu_bus_buffer.scala 523:35] - obuf_rdrsp_pend <= _T_1399 @[el2_lsu_bus_buffer.scala 523:25] - reg _T_1400 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 524:35] - _T_1400 <= obuf_rdrsp_tag_in @[el2_lsu_bus_buffer.scala 524:35] - obuf_rdrsp_tag <= _T_1400 @[el2_lsu_bus_buffer.scala 524:25] - reg _T_1401 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 525:35] - _T_1401 <= obuf_cmd_done_in @[el2_lsu_bus_buffer.scala 525:35] - obuf_cmd_done <= _T_1401 @[el2_lsu_bus_buffer.scala 525:25] - reg _T_1402 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 526:35] - _T_1402 <= obuf_data_done_in @[el2_lsu_bus_buffer.scala 526:35] - obuf_data_done <= _T_1402 @[el2_lsu_bus_buffer.scala 526:25] - reg _T_1403 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 527:35] - _T_1403 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 527:35] - obuf_wr_timer <= _T_1403 @[el2_lsu_bus_buffer.scala 527:25] - reg _T_1404 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 528:35] - _T_1404 <= obuf_wr_en @[el2_lsu_bus_buffer.scala 528:35] - obuf_wr_enQ <= _T_1404 @[el2_lsu_bus_buffer.scala 528:25] - node _T_1405 = bits(obuf_wr_en, 0, 0) @[el2_lsu_bus_buffer.scala 531:50] - node _T_1406 = mux(_T_1405, UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 531:32] - node _T_1407 = eq(obuf_rst, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 531:72] - node _T_1408 = and(_T_1406, _T_1407) @[el2_lsu_bus_buffer.scala 531:70] - reg _T_1409 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 531:28] - _T_1409 <= _T_1408 @[el2_lsu_bus_buffer.scala 531:28] - obuf_valid <= _T_1409 @[el2_lsu_bus_buffer.scala 531:18] - reg _T_1410 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_tag0 <= _T_1848 @[el2_lsu_bus_buffer.scala 405:13] + reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1410 <= obuf_nosend_in @[Reg.scala 28:23] + obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_nosend <= _T_1410 @[el2_lsu_bus_buffer.scala 532:25] - reg _T_1411 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1411 <= obuf_write_in @[Reg.scala 28:23] + obuf_merge <= obuf_merge_en @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_write <= _T_1411 @[el2_lsu_bus_buffer.scala 535:25] - reg _T_1412 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + reg _T_1849 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1412 <= obuf_sideeffect_in @[Reg.scala 28:23] + _T_1849 <= obuf_write_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sideeffect <= _T_1412 @[el2_lsu_bus_buffer.scala 536:25] - reg _T_1413 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_write <= _T_1849 @[el2_lsu_bus_buffer.scala 408:14] + reg _T_1850 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1413 <= obuf_sz_in @[Reg.scala 28:23] + _T_1850 <= obuf_sideeffect_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_sz <= _T_1413 @[el2_lsu_bus_buffer.scala 537:25] - reg _T_1414 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + obuf_sideeffect <= _T_1850 @[el2_lsu_bus_buffer.scala 409:19] + reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1414 <= obuf_byteen_in @[Reg.scala 28:23] + obuf_sz <= obuf_sz_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_byteen <= _T_1414 @[el2_lsu_bus_buffer.scala 538:25] - reg _T_1415 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 508:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_2.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_1851 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_1851 <= obuf_addr_in @[el2_lib.scala 514:16] + obuf_addr <= _T_1851 @[el2_lsu_bus_buffer.scala 411:13] + reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when obuf_wr_en : @[Reg.scala 28:19] - _T_1415 <= obuf_merge_in @[Reg.scala 28:23] + obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - obuf_merge <= _T_1415 @[el2_lsu_bus_buffer.scala 539:25] - reg _T_1416 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when obuf_wr_en : @[Reg.scala 28:19] - _T_1416 <= obuf_tag0_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - obuf_tag0 <= _T_1416 @[el2_lsu_bus_buffer.scala 540:25] - reg _T_1417 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when obuf_wr_en : @[Reg.scala 28:19] - _T_1417 <= obuf_tag1_in @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - obuf_tag1 <= _T_1417 @[el2_lsu_bus_buffer.scala 541:25] - node _T_1418 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1419 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1420 = and(ibuf_valid, _T_1419) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1421 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1422 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1423 = and(io.ldst_dual_r, _T_1422) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1424 = or(_T_1421, _T_1423) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1425 = and(io.lsu_busreq_r, _T_1424) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1426 = or(_T_1420, _T_1425) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1427 = eq(_T_1426, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1428 = and(_T_1418, _T_1427) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1429 = bits(_T_1428, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1430 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1431 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1432 = and(ibuf_valid, _T_1431) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1433 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1434 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1435 = and(io.ldst_dual_r, _T_1434) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1436 = or(_T_1433, _T_1435) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1437 = and(io.lsu_busreq_r, _T_1436) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1438 = or(_T_1432, _T_1437) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1439 = eq(_T_1438, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1440 = and(_T_1430, _T_1439) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1441 = bits(_T_1440, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1442 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1443 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1444 = and(ibuf_valid, _T_1443) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1445 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1446 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1447 = and(io.ldst_dual_r, _T_1446) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1448 = or(_T_1445, _T_1447) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1449 = and(io.lsu_busreq_r, _T_1448) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1450 = or(_T_1444, _T_1449) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1451 = eq(_T_1450, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1452 = and(_T_1442, _T_1451) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1453 = bits(_T_1452, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1454 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 546:56] - node _T_1455 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 546:93] - node _T_1456 = and(ibuf_valid, _T_1455) @[el2_lsu_bus_buffer.scala 546:83] - node _T_1457 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 547:35] - node _T_1458 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 547:72] - node _T_1459 = and(io.ldst_dual_r, _T_1458) @[el2_lsu_bus_buffer.scala 547:61] - node _T_1460 = or(_T_1457, _T_1459) @[el2_lsu_bus_buffer.scala 547:43] - node _T_1461 = and(io.lsu_busreq_r, _T_1460) @[el2_lsu_bus_buffer.scala 547:23] - node _T_1462 = or(_T_1456, _T_1461) @[el2_lsu_bus_buffer.scala 546:101] - node _T_1463 = eq(_T_1462, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 546:69] - node _T_1464 = and(_T_1454, _T_1463) @[el2_lsu_bus_buffer.scala 546:67] - node _T_1465 = bits(_T_1464, 0, 0) @[el2_lsu_bus_buffer.scala 547:91] - node _T_1466 = mux(_T_1465, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1467 = mux(_T_1453, UInt<2>("h02"), _T_1466) @[Mux.scala 98:16] - node _T_1468 = mux(_T_1441, UInt<1>("h01"), _T_1467) @[Mux.scala 98:16] - node _T_1469 = mux(_T_1429, UInt<1>("h00"), _T_1468) @[Mux.scala 98:16] - WrPtr0_m <= _T_1469 @[el2_lsu_bus_buffer.scala 548:13] - node _T_1470 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1471 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1472 = and(ibuf_valid, _T_1471) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1473 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1474 = and(io.lsu_busreq_m, _T_1473) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1475 = or(_T_1472, _T_1474) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1476 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1477 = and(io.lsu_busreq_r, _T_1476) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1478 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1479 = and(io.ldst_dual_r, _T_1478) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1480 = or(_T_1477, _T_1479) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1481 = or(_T_1475, _T_1480) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1482 = eq(_T_1481, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1483 = and(_T_1470, _T_1482) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1484 = bits(_T_1483, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1485 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1486 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1487 = and(ibuf_valid, _T_1486) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1488 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1489 = and(io.lsu_busreq_m, _T_1488) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1490 = or(_T_1487, _T_1489) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1491 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1492 = and(io.lsu_busreq_r, _T_1491) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1493 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1494 = and(io.ldst_dual_r, _T_1493) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1495 = or(_T_1492, _T_1494) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1496 = or(_T_1490, _T_1495) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1497 = eq(_T_1496, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1498 = and(_T_1485, _T_1497) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1499 = bits(_T_1498, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1500 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1501 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1502 = and(ibuf_valid, _T_1501) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1503 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1504 = and(io.lsu_busreq_m, _T_1503) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1505 = or(_T_1502, _T_1504) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1506 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1507 = and(io.lsu_busreq_r, _T_1506) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1508 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1509 = and(io.ldst_dual_r, _T_1508) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1510 = or(_T_1507, _T_1509) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1511 = or(_T_1505, _T_1510) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1512 = eq(_T_1511, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1513 = and(_T_1500, _T_1512) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1514 = bits(_T_1513, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1515 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 549:58] - node _T_1516 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 549:98] - node _T_1517 = and(ibuf_valid, _T_1516) @[el2_lsu_bus_buffer.scala 549:86] - node _T_1518 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 550:35] - node _T_1519 = and(io.lsu_busreq_m, _T_1518) @[el2_lsu_bus_buffer.scala 550:23] - node _T_1520 = or(_T_1517, _T_1519) @[el2_lsu_bus_buffer.scala 549:108] - node _T_1521 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 550:76] - node _T_1522 = and(io.lsu_busreq_r, _T_1521) @[el2_lsu_bus_buffer.scala 550:64] - node _T_1523 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 551:34] - node _T_1524 = and(io.ldst_dual_r, _T_1523) @[el2_lsu_bus_buffer.scala 551:22] - node _T_1525 = or(_T_1522, _T_1524) @[el2_lsu_bus_buffer.scala 550:85] - node _T_1526 = or(_T_1520, _T_1525) @[el2_lsu_bus_buffer.scala 550:45] - node _T_1527 = eq(_T_1526, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 549:72] - node _T_1528 = and(_T_1515, _T_1527) @[el2_lsu_bus_buffer.scala 549:70] - node _T_1529 = bits(_T_1528, 0, 0) @[el2_lsu_bus_buffer.scala 551:47] - node _T_1530 = mux(_T_1529, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 98:16] - node _T_1531 = mux(_T_1514, UInt<2>("h02"), _T_1530) @[Mux.scala 98:16] - node _T_1532 = mux(_T_1499, UInt<1>("h01"), _T_1531) @[Mux.scala 98:16] - node _T_1533 = mux(_T_1484, UInt<1>("h00"), _T_1532) @[Mux.scala 98:16] - WrPtr1_m <= _T_1533 @[el2_lsu_bus_buffer.scala 552:26] - node _T_1534 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1535 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1536 = cat(_T_1535, _T_1534) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1537 = orr(_T_1536) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1538 = not(_T_1537) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1539 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1540 = and(_T_1538, _T_1539) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1541 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1542 = and(_T_1540, _T_1541) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1542 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1543 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1544 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1545 = cat(_T_1544, _T_1543) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1546 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1547 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1548 = cat(_T_1547, _T_1546) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1549 = not(_T_1548) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1550 = and(_T_1545, _T_1549) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1551 = orr(_T_1550) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1552 = not(_T_1551) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1553 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1554 = and(_T_1552, _T_1553) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1555 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1556 = and(_T_1554, _T_1555) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1557 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1558 = and(_T_1556, _T_1557) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1558 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1559 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1560 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1561 = cat(_T_1560, _T_1559) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1562 = orr(_T_1561) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1563 = not(_T_1562) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1564 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1565 = and(_T_1563, _T_1564) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1565 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1566 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1567 = and(_T_1566, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1568 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1569 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1570 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1571 = and(_T_1569, _T_1570) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1572 = or(_T_1568, _T_1571) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1573 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1574 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1575 = and(_T_1573, _T_1574) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1576 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1577 = and(_T_1575, _T_1576) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1578 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1579 = and(_T_1577, _T_1578) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1580 = or(_T_1572, _T_1579) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1581 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1582 = and(_T_1581, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1583 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1584 = and(_T_1582, _T_1583) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1585 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1586 = and(_T_1584, _T_1585) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1587 = or(_T_1580, _T_1586) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1588 = and(_T_1567, _T_1587) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1589 = or(_T_1588, buf_age[0][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][0] <= _T_1589 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1590 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1591 = and(_T_1590, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1592 = not(_T_1591) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1593 = and(buf_ageQ[0][0], _T_1592) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][0] <= _T_1593 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1594 = eq(UInt<2>("h00"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1595 = not(buf_age[0][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1596 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1597 = and(_T_1595, _T_1596) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1598 = mux(_T_1594, UInt<1>("h00"), _T_1597) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][0] <= _T_1598 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1599 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1600 = and(_T_1599, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1601 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1602 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1603 = or(_T_1601, _T_1602) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1604 = not(_T_1603) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1605 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1606 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1607 = and(_T_1605, _T_1606) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1608 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1609 = and(_T_1607, _T_1608) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1610 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1611 = and(_T_1609, _T_1610) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1612 = or(_T_1604, _T_1611) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1613 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1614 = and(_T_1613, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1615 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1616 = and(_T_1614, _T_1615) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1617 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1618 = and(_T_1616, _T_1617) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1619 = or(_T_1612, _T_1618) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1620 = and(_T_1600, _T_1619) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][0] <= _T_1620 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1621 = or(buf_rspage_set[0][0], buf_rspage[0][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][0] <= _T_1621 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1622 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1623 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1624 = or(_T_1622, _T_1623) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1625 = not(_T_1624) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1626 = and(buf_rspageQ[0][0], _T_1625) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][0] <= _T_1626 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1627 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1628 = and(buf_rspageQ[0][0], _T_1627) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][0] <= _T_1628 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1629 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1630 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1631 = cat(_T_1630, _T_1629) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1632 = orr(_T_1631) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1633 = not(_T_1632) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1634 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1635 = and(_T_1633, _T_1634) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1636 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1637 = and(_T_1635, _T_1636) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1637 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1638 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1639 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1640 = cat(_T_1639, _T_1638) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1641 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1642 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1643 = cat(_T_1642, _T_1641) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1644 = not(_T_1643) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1645 = and(_T_1640, _T_1644) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1646 = orr(_T_1645) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1647 = not(_T_1646) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1648 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1649 = and(_T_1647, _T_1648) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1650 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1651 = and(_T_1649, _T_1650) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1652 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1653 = and(_T_1651, _T_1652) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1653 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1654 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1655 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1656 = cat(_T_1655, _T_1654) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1657 = orr(_T_1656) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1658 = not(_T_1657) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1659 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1660 = and(_T_1658, _T_1659) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1660 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1661 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1662 = and(_T_1661, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1663 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1664 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1665 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1666 = and(_T_1664, _T_1665) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1667 = or(_T_1663, _T_1666) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1668 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1669 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1670 = and(_T_1668, _T_1669) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1671 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1672 = and(_T_1670, _T_1671) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1673 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1674 = and(_T_1672, _T_1673) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1675 = or(_T_1667, _T_1674) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1676 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1677 = and(_T_1676, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1678 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1679 = and(_T_1677, _T_1678) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1680 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1681 = and(_T_1679, _T_1680) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1682 = or(_T_1675, _T_1681) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1683 = and(_T_1662, _T_1682) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1684 = or(_T_1683, buf_age[0][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][1] <= _T_1684 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1685 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1686 = and(_T_1685, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1687 = not(_T_1686) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1688 = and(buf_ageQ[0][1], _T_1687) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][1] <= _T_1688 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1689 = eq(UInt<2>("h00"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1690 = not(buf_age[0][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1692 = and(_T_1690, _T_1691) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1693 = mux(_T_1689, UInt<1>("h00"), _T_1692) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][1] <= _T_1693 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1694 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1695 = and(_T_1694, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1696 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1697 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1698 = or(_T_1696, _T_1697) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1699 = not(_T_1698) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1700 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1701 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1702 = and(_T_1700, _T_1701) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1703 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1704 = and(_T_1702, _T_1703) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1705 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1706 = and(_T_1704, _T_1705) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1707 = or(_T_1699, _T_1706) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1708 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1709 = and(_T_1708, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1710 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1711 = and(_T_1709, _T_1710) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1712 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1713 = and(_T_1711, _T_1712) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1714 = or(_T_1707, _T_1713) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1715 = and(_T_1695, _T_1714) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][1] <= _T_1715 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1716 = or(buf_rspage_set[0][1], buf_rspage[0][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][1] <= _T_1716 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1717 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1718 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1719 = or(_T_1717, _T_1718) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1720 = not(_T_1719) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1721 = and(buf_rspageQ[0][1], _T_1720) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][1] <= _T_1721 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1722 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1723 = and(buf_rspageQ[0][1], _T_1722) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][1] <= _T_1723 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1724 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1725 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1726 = cat(_T_1725, _T_1724) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1727 = orr(_T_1726) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1728 = not(_T_1727) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1729 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1730 = and(_T_1728, _T_1729) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1731 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1732 = and(_T_1730, _T_1731) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1732 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1733 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1734 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1735 = cat(_T_1734, _T_1733) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1736 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1737 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1738 = cat(_T_1737, _T_1736) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1739 = not(_T_1738) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1740 = and(_T_1735, _T_1739) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1741 = orr(_T_1740) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1742 = not(_T_1741) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1743 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1744 = and(_T_1742, _T_1743) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1745 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1746 = and(_T_1744, _T_1745) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1747 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1748 = and(_T_1746, _T_1747) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1748 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1749 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1750 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1751 = cat(_T_1750, _T_1749) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1752 = orr(_T_1751) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1753 = not(_T_1752) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1754 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1755 = and(_T_1753, _T_1754) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1755 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1756 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1757 = and(_T_1756, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1758 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1759 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1760 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1761 = and(_T_1759, _T_1760) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1762 = or(_T_1758, _T_1761) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1763 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1764 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1765 = and(_T_1763, _T_1764) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1766 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1767 = and(_T_1765, _T_1766) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1768 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1769 = and(_T_1767, _T_1768) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1770 = or(_T_1762, _T_1769) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1771 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1772 = and(_T_1771, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1773 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1774 = and(_T_1772, _T_1773) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1775 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1776 = and(_T_1774, _T_1775) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1777 = or(_T_1770, _T_1776) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1778 = and(_T_1757, _T_1777) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1779 = or(_T_1778, buf_age[0][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][2] <= _T_1779 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1780 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1781 = and(_T_1780, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1782 = not(_T_1781) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1783 = and(buf_ageQ[0][2], _T_1782) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][2] <= _T_1783 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1784 = eq(UInt<2>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1785 = not(buf_age[0][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1786 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1787 = and(_T_1785, _T_1786) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1788 = mux(_T_1784, UInt<1>("h00"), _T_1787) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][2] <= _T_1788 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1789 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1790 = and(_T_1789, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1791 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1792 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1793 = or(_T_1791, _T_1792) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1794 = not(_T_1793) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1795 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1796 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1797 = and(_T_1795, _T_1796) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1798 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1799 = and(_T_1797, _T_1798) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1800 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1801 = and(_T_1799, _T_1800) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1802 = or(_T_1794, _T_1801) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1803 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1804 = and(_T_1803, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1805 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1806 = and(_T_1804, _T_1805) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1807 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1808 = and(_T_1806, _T_1807) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1809 = or(_T_1802, _T_1808) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1810 = and(_T_1790, _T_1809) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][2] <= _T_1810 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1811 = or(buf_rspage_set[0][2], buf_rspage[0][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][2] <= _T_1811 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1812 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1813 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1814 = or(_T_1812, _T_1813) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1815 = not(_T_1814) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1816 = and(buf_rspageQ[0][2], _T_1815) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][2] <= _T_1816 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1817 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1818 = and(buf_rspageQ[0][2], _T_1817) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][2] <= _T_1818 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1819 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1820 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1821 = cat(_T_1820, _T_1819) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1822 = orr(_T_1821) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1823 = not(_T_1822) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1824 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1825 = and(_T_1823, _T_1824) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1826 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1827 = and(_T_1825, _T_1826) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[0] <= _T_1827 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1828 = cat(buf_age[0][1], buf_age[0][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1829 = cat(buf_age[0][3], buf_age[0][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1830 = cat(_T_1829, _T_1828) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1831 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1832 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1833 = cat(_T_1832, _T_1831) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1834 = not(_T_1833) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1835 = and(_T_1830, _T_1834) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1836 = orr(_T_1835) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1837 = not(_T_1836) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1838 = not(CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1839 = and(_T_1837, _T_1838) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1840 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1841 = and(_T_1839, _T_1840) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1842 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1843 = and(_T_1841, _T_1842) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[0] <= _T_1843 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1844 = cat(buf_rsp_pickage[0][1], buf_rsp_pickage[0][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1845 = cat(buf_rsp_pickage[0][3], buf_rsp_pickage[0][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1846 = cat(_T_1845, _T_1844) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1847 = orr(_T_1846) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1848 = not(_T_1847) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1849 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1850 = and(_T_1848, _T_1849) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[0] <= _T_1850 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1851 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1852 = and(_T_1851, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1853 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1854 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1855 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1856 = and(_T_1854, _T_1855) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1857 = or(_T_1853, _T_1856) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1858 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1859 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1860 = and(_T_1858, _T_1859) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1861 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1862 = and(_T_1860, _T_1861) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1863 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1864 = and(_T_1862, _T_1863) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1865 = or(_T_1857, _T_1864) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1866 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1867 = and(_T_1866, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1868 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1869 = and(_T_1867, _T_1868) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1870 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1871 = and(_T_1869, _T_1870) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1872 = or(_T_1865, _T_1871) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1873 = and(_T_1852, _T_1872) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1874 = or(_T_1873, buf_age[0][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[0][3] <= _T_1874 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1875 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1876 = and(_T_1875, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1877 = not(_T_1876) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1878 = and(buf_ageQ[0][3], _T_1877) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[0][3] <= _T_1878 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1879 = eq(UInt<2>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1880 = not(buf_age[0][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1881 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1882 = and(_T_1880, _T_1881) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1883 = mux(_T_1879, UInt<1>("h00"), _T_1882) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[0][3] <= _T_1883 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1884 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1885 = and(_T_1884, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1887 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1888 = or(_T_1886, _T_1887) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1889 = not(_T_1888) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1890 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1891 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1892 = and(_T_1890, _T_1891) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1893 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1894 = and(_T_1892, _T_1893) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1895 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1896 = and(_T_1894, _T_1895) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1897 = or(_T_1889, _T_1896) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1898 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1899 = and(_T_1898, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1900 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1901 = and(_T_1899, _T_1900) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1902 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1903 = and(_T_1901, _T_1902) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1904 = or(_T_1897, _T_1903) @[el2_lsu_bus_buffer.scala 571:110] - node _T_1905 = and(_T_1885, _T_1904) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[0][3] <= _T_1905 @[el2_lsu_bus_buffer.scala 570:29] - node _T_1906 = or(buf_rspage_set[0][3], buf_rspage[0][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[0][3] <= _T_1906 @[el2_lsu_bus_buffer.scala 573:29] - node _T_1907 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_1908 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_1909 = or(_T_1907, _T_1908) @[el2_lsu_bus_buffer.scala 574:80] - node _T_1910 = not(_T_1909) @[el2_lsu_bus_buffer.scala 574:52] - node _T_1911 = and(buf_rspageQ[0][3], _T_1910) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[0][3] <= _T_1911 @[el2_lsu_bus_buffer.scala 574:29] - node _T_1912 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_1913 = and(buf_rspageQ[0][3], _T_1912) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[0][3] <= _T_1913 @[el2_lsu_bus_buffer.scala 575:29] - node _T_1914 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1915 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1916 = cat(_T_1915, _T_1914) @[el2_lsu_bus_buffer.scala 558:45] - node _T_1917 = orr(_T_1916) @[el2_lsu_bus_buffer.scala 558:55] - node _T_1918 = not(_T_1917) @[el2_lsu_bus_buffer.scala 558:32] - node _T_1919 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_1920 = and(_T_1918, _T_1919) @[el2_lsu_bus_buffer.scala 558:59] - node _T_1921 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_1922 = and(_T_1920, _T_1921) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_1922 @[el2_lsu_bus_buffer.scala 558:29] - node _T_1923 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1924 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1925 = cat(_T_1924, _T_1923) @[el2_lsu_bus_buffer.scala 559:46] - node _T_1926 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1927 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1928 = cat(_T_1927, _T_1926) @[el2_lsu_bus_buffer.scala 559:67] - node _T_1929 = not(_T_1928) @[el2_lsu_bus_buffer.scala 559:55] - node _T_1930 = and(_T_1925, _T_1929) @[el2_lsu_bus_buffer.scala 559:53] - node _T_1931 = orr(_T_1930) @[el2_lsu_bus_buffer.scala 559:78] - node _T_1932 = not(_T_1931) @[el2_lsu_bus_buffer.scala 559:32] - node _T_1933 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_1934 = and(_T_1932, _T_1933) @[el2_lsu_bus_buffer.scala 559:82] - node _T_1935 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_1936 = and(_T_1934, _T_1935) @[el2_lsu_bus_buffer.scala 559:99] - node _T_1937 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_1938 = and(_T_1936, _T_1937) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_1938 @[el2_lsu_bus_buffer.scala 559:29] - node _T_1939 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1940 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1941 = cat(_T_1940, _T_1939) @[el2_lsu_bus_buffer.scala 560:53] - node _T_1942 = orr(_T_1941) @[el2_lsu_bus_buffer.scala 560:63] - node _T_1943 = not(_T_1942) @[el2_lsu_bus_buffer.scala 560:32] - node _T_1944 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_1945 = and(_T_1943, _T_1944) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_1945 @[el2_lsu_bus_buffer.scala 560:29] - node _T_1946 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_1947 = and(_T_1946, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_1948 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_1949 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_1950 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_1951 = and(_T_1949, _T_1950) @[el2_lsu_bus_buffer.scala 563:63] - node _T_1952 = or(_T_1948, _T_1951) @[el2_lsu_bus_buffer.scala 563:35] - node _T_1953 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_1954 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_1955 = and(_T_1953, _T_1954) @[el2_lsu_bus_buffer.scala 564:43] - node _T_1956 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_1957 = and(_T_1955, _T_1956) @[el2_lsu_bus_buffer.scala 564:73] - node _T_1958 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_1959 = and(_T_1957, _T_1958) @[el2_lsu_bus_buffer.scala 564:92] - node _T_1960 = or(_T_1952, _T_1959) @[el2_lsu_bus_buffer.scala 563:93] - node _T_1961 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_1962 = and(_T_1961, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_1963 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 565:54] - node _T_1965 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 565:73] - node _T_1967 = or(_T_1960, _T_1966) @[el2_lsu_bus_buffer.scala 564:113] - node _T_1968 = and(_T_1947, _T_1967) @[el2_lsu_bus_buffer.scala 562:79] - node _T_1969 = or(_T_1968, buf_age[1][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][0] <= _T_1969 @[el2_lsu_bus_buffer.scala 562:29] - node _T_1970 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_1971 = and(_T_1970, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_1972 = not(_T_1971) @[el2_lsu_bus_buffer.scala 567:49] - node _T_1973 = and(buf_ageQ[1][0], _T_1972) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][0] <= _T_1973 @[el2_lsu_bus_buffer.scala 567:29] - node _T_1974 = eq(UInt<2>("h01"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_1975 = not(buf_age[1][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_1976 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_1977 = and(_T_1975, _T_1976) @[el2_lsu_bus_buffer.scala 568:108] - node _T_1978 = mux(_T_1974, UInt<1>("h00"), _T_1977) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][0] <= _T_1978 @[el2_lsu_bus_buffer.scala 568:29] - node _T_1979 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_1980 = and(_T_1979, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_1981 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_1982 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_1983 = or(_T_1981, _T_1982) @[el2_lsu_bus_buffer.scala 570:109] - node _T_1984 = not(_T_1983) @[el2_lsu_bus_buffer.scala 570:81] - node _T_1985 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_1986 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_1987 = and(_T_1985, _T_1986) @[el2_lsu_bus_buffer.scala 571:41] - node _T_1988 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_1989 = and(_T_1987, _T_1988) @[el2_lsu_bus_buffer.scala 571:71] - node _T_1990 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_1991 = and(_T_1989, _T_1990) @[el2_lsu_bus_buffer.scala 571:90] - node _T_1992 = or(_T_1984, _T_1991) @[el2_lsu_bus_buffer.scala 570:139] - node _T_1993 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_1994 = and(_T_1993, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_1995 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_1996 = and(_T_1994, _T_1995) @[el2_lsu_bus_buffer.scala 572:52] - node _T_1997 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_1998 = and(_T_1996, _T_1997) @[el2_lsu_bus_buffer.scala 572:71] - node _T_1999 = or(_T_1992, _T_1998) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2000 = and(_T_1980, _T_1999) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][0] <= _T_2000 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2001 = or(buf_rspage_set[1][0], buf_rspage[1][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][0] <= _T_2001 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2002 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2003 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2004 = or(_T_2002, _T_2003) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2005 = not(_T_2004) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2006 = and(buf_rspageQ[1][0], _T_2005) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][0] <= _T_2006 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2007 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2008 = and(buf_rspageQ[1][0], _T_2007) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][0] <= _T_2008 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2009 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2010 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2011 = cat(_T_2010, _T_2009) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2012 = orr(_T_2011) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2013 = not(_T_2012) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2014 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2015 = and(_T_2013, _T_2014) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2016 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2017 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2018 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2019 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2020 = cat(_T_2019, _T_2018) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2021 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2022 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2023 = cat(_T_2022, _T_2021) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2024 = not(_T_2023) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2025 = and(_T_2020, _T_2024) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2026 = orr(_T_2025) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2027 = not(_T_2026) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2028 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2029 = and(_T_2027, _T_2028) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2030 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2031 = and(_T_2029, _T_2030) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2032 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2033 = and(_T_2031, _T_2032) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2033 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2034 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2035 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2036 = cat(_T_2035, _T_2034) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2037 = orr(_T_2036) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2038 = not(_T_2037) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2040 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2041 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2042 = and(_T_2041, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2043 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2044 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2045 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2046 = and(_T_2044, _T_2045) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2047 = or(_T_2043, _T_2046) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2048 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2049 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2050 = and(_T_2048, _T_2049) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2051 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2052 = and(_T_2050, _T_2051) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2053 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2054 = and(_T_2052, _T_2053) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2055 = or(_T_2047, _T_2054) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2056 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2057 = and(_T_2056, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2058 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2059 = and(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2060 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2061 = and(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2062 = or(_T_2055, _T_2061) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2063 = and(_T_2042, _T_2062) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2064 = or(_T_2063, buf_age[1][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][1] <= _T_2064 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2065 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2066 = and(_T_2065, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2067 = not(_T_2066) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2068 = and(buf_ageQ[1][1], _T_2067) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][1] <= _T_2068 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2069 = eq(UInt<2>("h01"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2070 = not(buf_age[1][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2071 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2072 = and(_T_2070, _T_2071) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2073 = mux(_T_2069, UInt<1>("h00"), _T_2072) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][1] <= _T_2073 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2074 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2075 = and(_T_2074, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2076 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2077 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2078 = or(_T_2076, _T_2077) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2079 = not(_T_2078) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2080 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2081 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2082 = and(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2083 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2084 = and(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2085 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2086 = and(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2087 = or(_T_2079, _T_2086) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2088 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2089 = and(_T_2088, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2090 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2091 = and(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2092 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2093 = and(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2094 = or(_T_2087, _T_2093) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2095 = and(_T_2075, _T_2094) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][1] <= _T_2095 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2096 = or(buf_rspage_set[1][1], buf_rspage[1][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][1] <= _T_2096 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2097 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2098 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2099 = or(_T_2097, _T_2098) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2100 = not(_T_2099) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2101 = and(buf_rspageQ[1][1], _T_2100) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][1] <= _T_2101 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2102 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2103 = and(buf_rspageQ[1][1], _T_2102) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][1] <= _T_2103 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2104 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2105 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2106 = cat(_T_2105, _T_2104) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2107 = orr(_T_2106) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2108 = not(_T_2107) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2109 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2110 = and(_T_2108, _T_2109) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2111 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2112 = and(_T_2110, _T_2111) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2112 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2113 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2114 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2115 = cat(_T_2114, _T_2113) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2116 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2117 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2118 = cat(_T_2117, _T_2116) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2119 = not(_T_2118) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2120 = and(_T_2115, _T_2119) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2121 = orr(_T_2120) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2122 = not(_T_2121) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2123 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2124 = and(_T_2122, _T_2123) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2125 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2126 = and(_T_2124, _T_2125) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2127 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2128 = and(_T_2126, _T_2127) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2128 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2129 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2130 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2131 = cat(_T_2130, _T_2129) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2132 = orr(_T_2131) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2133 = not(_T_2132) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2134 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2135 = and(_T_2133, _T_2134) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2135 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2136 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2137 = and(_T_2136, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2138 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2139 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2140 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2142 = or(_T_2138, _T_2141) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2143 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2144 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2145 = and(_T_2143, _T_2144) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2146 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2147 = and(_T_2145, _T_2146) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2148 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2149 = and(_T_2147, _T_2148) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2150 = or(_T_2142, _T_2149) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2151 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2152 = and(_T_2151, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2153 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2154 = and(_T_2152, _T_2153) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2155 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2156 = and(_T_2154, _T_2155) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2157 = or(_T_2150, _T_2156) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2158 = and(_T_2137, _T_2157) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2159 = or(_T_2158, buf_age[1][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][2] <= _T_2159 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2160 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2161 = and(_T_2160, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2162 = not(_T_2161) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2163 = and(buf_ageQ[1][2], _T_2162) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][2] <= _T_2163 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2164 = eq(UInt<2>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2165 = not(buf_age[1][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2166 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2167 = and(_T_2165, _T_2166) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2168 = mux(_T_2164, UInt<1>("h00"), _T_2167) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][2] <= _T_2168 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2169 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2170 = and(_T_2169, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2171 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2172 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2173 = or(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2174 = not(_T_2173) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2175 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2176 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2177 = and(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2178 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2179 = and(_T_2177, _T_2178) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2180 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2181 = and(_T_2179, _T_2180) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2182 = or(_T_2174, _T_2181) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2183 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2184 = and(_T_2183, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2185 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2186 = and(_T_2184, _T_2185) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2187 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2188 = and(_T_2186, _T_2187) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2189 = or(_T_2182, _T_2188) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2190 = and(_T_2170, _T_2189) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][2] <= _T_2190 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2191 = or(buf_rspage_set[1][2], buf_rspage[1][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][2] <= _T_2191 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2192 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2193 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2194 = or(_T_2192, _T_2193) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2195 = not(_T_2194) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2196 = and(buf_rspageQ[1][2], _T_2195) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][2] <= _T_2196 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2197 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2198 = and(buf_rspageQ[1][2], _T_2197) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][2] <= _T_2198 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2199 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2200 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2201 = cat(_T_2200, _T_2199) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2202 = orr(_T_2201) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2203 = not(_T_2202) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2204 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2205 = and(_T_2203, _T_2204) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2206 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2207 = and(_T_2205, _T_2206) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[1] <= _T_2207 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2208 = cat(buf_age[1][1], buf_age[1][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2209 = cat(buf_age[1][3], buf_age[1][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2210 = cat(_T_2209, _T_2208) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2211 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2212 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2213 = cat(_T_2212, _T_2211) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2214 = not(_T_2213) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2215 = and(_T_2210, _T_2214) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2216 = orr(_T_2215) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2217 = not(_T_2216) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2218 = not(CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2219 = and(_T_2217, _T_2218) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2220 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2222 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[1] <= _T_2223 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2224 = cat(buf_rsp_pickage[1][1], buf_rsp_pickage[1][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2225 = cat(buf_rsp_pickage[1][3], buf_rsp_pickage[1][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2226 = cat(_T_2225, _T_2224) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2227 = orr(_T_2226) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2228 = not(_T_2227) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2229 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2230 = and(_T_2228, _T_2229) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[1] <= _T_2230 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2231 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2232 = and(_T_2231, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2233 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2234 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2235 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2236 = and(_T_2234, _T_2235) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2237 = or(_T_2233, _T_2236) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2238 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2239 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2240 = and(_T_2238, _T_2239) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2241 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2242 = and(_T_2240, _T_2241) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2243 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2244 = and(_T_2242, _T_2243) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2245 = or(_T_2237, _T_2244) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2246 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2247 = and(_T_2246, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2248 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2249 = and(_T_2247, _T_2248) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2250 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2251 = and(_T_2249, _T_2250) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2252 = or(_T_2245, _T_2251) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2253 = and(_T_2232, _T_2252) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2254 = or(_T_2253, buf_age[1][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[1][3] <= _T_2254 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2255 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2256 = and(_T_2255, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2257 = not(_T_2256) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2258 = and(buf_ageQ[1][3], _T_2257) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[1][3] <= _T_2258 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2259 = eq(UInt<2>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2260 = not(buf_age[1][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2261 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2262 = and(_T_2260, _T_2261) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2263 = mux(_T_2259, UInt<1>("h00"), _T_2262) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[1][3] <= _T_2263 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2264 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2265 = and(_T_2264, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2266 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2267 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2268 = or(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2269 = not(_T_2268) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2270 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2271 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2272 = and(_T_2270, _T_2271) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2273 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2274 = and(_T_2272, _T_2273) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2275 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2276 = and(_T_2274, _T_2275) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2277 = or(_T_2269, _T_2276) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2278 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2279 = and(_T_2278, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2280 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2281 = and(_T_2279, _T_2280) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2282 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2283 = and(_T_2281, _T_2282) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2284 = or(_T_2277, _T_2283) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2285 = and(_T_2265, _T_2284) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[1][3] <= _T_2285 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2286 = or(buf_rspage_set[1][3], buf_rspage[1][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[1][3] <= _T_2286 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2287 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2288 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2289 = or(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2290 = not(_T_2289) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2291 = and(buf_rspageQ[1][3], _T_2290) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[1][3] <= _T_2291 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2292 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2293 = and(buf_rspageQ[1][3], _T_2292) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[1][3] <= _T_2293 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2294 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2295 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2296 = cat(_T_2295, _T_2294) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2297 = orr(_T_2296) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2298 = not(_T_2297) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2299 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2301 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2302 = and(_T_2300, _T_2301) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2302 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2303 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2304 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2305 = cat(_T_2304, _T_2303) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2306 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2307 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2308 = cat(_T_2307, _T_2306) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2309 = not(_T_2308) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2310 = and(_T_2305, _T_2309) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2311 = orr(_T_2310) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2312 = not(_T_2311) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2313 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2315 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2317 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2318 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2319 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2320 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2321 = cat(_T_2320, _T_2319) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2322 = orr(_T_2321) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2323 = not(_T_2322) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2324 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2325 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2326 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2327 = and(_T_2326, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2328 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2329 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2330 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2331 = and(_T_2329, _T_2330) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2332 = or(_T_2328, _T_2331) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2333 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2334 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2335 = and(_T_2333, _T_2334) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2336 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2338 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2339 = and(_T_2337, _T_2338) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2340 = or(_T_2332, _T_2339) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2341 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2342 = and(_T_2341, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2343 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2344 = and(_T_2342, _T_2343) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2345 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2346 = and(_T_2344, _T_2345) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2347 = or(_T_2340, _T_2346) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2348 = and(_T_2327, _T_2347) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2349 = or(_T_2348, buf_age[2][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][0] <= _T_2349 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2350 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2351 = and(_T_2350, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2352 = not(_T_2351) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2353 = and(buf_ageQ[2][0], _T_2352) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][0] <= _T_2353 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2354 = eq(UInt<2>("h02"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2355 = not(buf_age[2][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2356 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2357 = and(_T_2355, _T_2356) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2358 = mux(_T_2354, UInt<1>("h00"), _T_2357) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][0] <= _T_2358 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2359 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2360 = and(_T_2359, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2361 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2362 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2363 = or(_T_2361, _T_2362) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2364 = not(_T_2363) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2365 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2366 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2367 = and(_T_2365, _T_2366) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2368 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2369 = and(_T_2367, _T_2368) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2370 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2371 = and(_T_2369, _T_2370) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2372 = or(_T_2364, _T_2371) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2373 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2374 = and(_T_2373, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2375 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2376 = and(_T_2374, _T_2375) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2377 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2378 = and(_T_2376, _T_2377) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2379 = or(_T_2372, _T_2378) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2380 = and(_T_2360, _T_2379) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][0] <= _T_2380 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2381 = or(buf_rspage_set[2][0], buf_rspage[2][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][0] <= _T_2381 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2382 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2383 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2384 = or(_T_2382, _T_2383) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2385 = not(_T_2384) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2386 = and(buf_rspageQ[2][0], _T_2385) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][0] <= _T_2386 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2387 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2388 = and(buf_rspageQ[2][0], _T_2387) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][0] <= _T_2388 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2389 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2390 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2391 = cat(_T_2390, _T_2389) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2392 = orr(_T_2391) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2393 = not(_T_2392) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2394 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2396 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2397 = and(_T_2395, _T_2396) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2397 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2398 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2399 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2400 = cat(_T_2399, _T_2398) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2401 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2402 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2403 = cat(_T_2402, _T_2401) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2404 = not(_T_2403) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2405 = and(_T_2400, _T_2404) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2406 = orr(_T_2405) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2407 = not(_T_2406) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2408 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2409 = and(_T_2407, _T_2408) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2410 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2411 = and(_T_2409, _T_2410) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2412 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2413 = and(_T_2411, _T_2412) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2413 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2414 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2415 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2416 = cat(_T_2415, _T_2414) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2417 = orr(_T_2416) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2418 = not(_T_2417) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2419 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2420 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2421 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2422 = and(_T_2421, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2423 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2424 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2425 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2426 = and(_T_2424, _T_2425) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2427 = or(_T_2423, _T_2426) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2428 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2429 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2430 = and(_T_2428, _T_2429) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2431 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2432 = and(_T_2430, _T_2431) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2433 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2434 = and(_T_2432, _T_2433) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2435 = or(_T_2427, _T_2434) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2436 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2437 = and(_T_2436, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2438 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2440 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2441 = and(_T_2439, _T_2440) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2442 = or(_T_2435, _T_2441) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2443 = and(_T_2422, _T_2442) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2444 = or(_T_2443, buf_age[2][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][1] <= _T_2444 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2445 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2446 = and(_T_2445, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2447 = not(_T_2446) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2448 = and(buf_ageQ[2][1], _T_2447) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][1] <= _T_2448 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2449 = eq(UInt<2>("h02"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2450 = not(buf_age[2][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2451 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2453 = mux(_T_2449, UInt<1>("h00"), _T_2452) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][1] <= _T_2453 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2454 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2455 = and(_T_2454, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2456 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2457 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2459 = not(_T_2458) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2460 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2461 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2462 = and(_T_2460, _T_2461) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2463 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2465 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2466 = and(_T_2464, _T_2465) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2467 = or(_T_2459, _T_2466) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2468 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2469 = and(_T_2468, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2470 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2471 = and(_T_2469, _T_2470) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2472 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2473 = and(_T_2471, _T_2472) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2474 = or(_T_2467, _T_2473) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2475 = and(_T_2455, _T_2474) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][1] <= _T_2475 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2476 = or(buf_rspage_set[2][1], buf_rspage[2][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][1] <= _T_2476 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2477 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2478 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2479 = or(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2480 = not(_T_2479) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2481 = and(buf_rspageQ[2][1], _T_2480) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][1] <= _T_2481 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2482 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2483 = and(buf_rspageQ[2][1], _T_2482) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][1] <= _T_2483 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2484 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2485 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2486 = cat(_T_2485, _T_2484) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2487 = orr(_T_2486) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2488 = not(_T_2487) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2489 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2490 = and(_T_2488, _T_2489) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2491 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2492 = and(_T_2490, _T_2491) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2492 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2493 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2494 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2495 = cat(_T_2494, _T_2493) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2496 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2497 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2498 = cat(_T_2497, _T_2496) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2499 = not(_T_2498) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2500 = and(_T_2495, _T_2499) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2501 = orr(_T_2500) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2502 = not(_T_2501) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2503 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2505 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2506 = and(_T_2504, _T_2505) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2507 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2508 = and(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2508 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2509 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2510 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2511 = cat(_T_2510, _T_2509) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2512 = orr(_T_2511) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2513 = not(_T_2512) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2514 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2515 = and(_T_2513, _T_2514) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2515 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2516 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2517 = and(_T_2516, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2518 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2519 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2520 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2521 = and(_T_2519, _T_2520) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2522 = or(_T_2518, _T_2521) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2523 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2524 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2525 = and(_T_2523, _T_2524) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2526 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2528 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2530 = or(_T_2522, _T_2529) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2531 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2532 = and(_T_2531, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2533 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2534 = and(_T_2532, _T_2533) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2535 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2536 = and(_T_2534, _T_2535) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2537 = or(_T_2530, _T_2536) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2538 = and(_T_2517, _T_2537) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2539 = or(_T_2538, buf_age[2][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][2] <= _T_2539 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2540 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2541 = and(_T_2540, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2542 = not(_T_2541) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2543 = and(buf_ageQ[2][2], _T_2542) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][2] <= _T_2543 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2544 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2545 = not(buf_age[2][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2546 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2547 = and(_T_2545, _T_2546) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2548 = mux(_T_2544, UInt<1>("h00"), _T_2547) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][2] <= _T_2548 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2549 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2550 = and(_T_2549, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2551 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2552 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2553 = or(_T_2551, _T_2552) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2554 = not(_T_2553) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2555 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2556 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2557 = and(_T_2555, _T_2556) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2558 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2559 = and(_T_2557, _T_2558) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2560 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2561 = and(_T_2559, _T_2560) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2562 = or(_T_2554, _T_2561) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2563 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2564 = and(_T_2563, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2565 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2566 = and(_T_2564, _T_2565) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2567 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2568 = and(_T_2566, _T_2567) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2569 = or(_T_2562, _T_2568) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2570 = and(_T_2550, _T_2569) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][2] <= _T_2570 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2571 = or(buf_rspage_set[2][2], buf_rspage[2][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][2] <= _T_2571 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2572 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2573 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2574 = or(_T_2572, _T_2573) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2575 = not(_T_2574) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2576 = and(buf_rspageQ[2][2], _T_2575) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][2] <= _T_2576 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2577 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2578 = and(buf_rspageQ[2][2], _T_2577) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][2] <= _T_2578 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2579 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2580 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2581 = cat(_T_2580, _T_2579) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2582 = orr(_T_2581) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2583 = not(_T_2582) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2584 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2585 = and(_T_2583, _T_2584) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2586 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2587 = and(_T_2585, _T_2586) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[2] <= _T_2587 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2588 = cat(buf_age[2][1], buf_age[2][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2589 = cat(buf_age[2][3], buf_age[2][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2590 = cat(_T_2589, _T_2588) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2591 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2592 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2593 = cat(_T_2592, _T_2591) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2594 = not(_T_2593) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2595 = and(_T_2590, _T_2594) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2596 = orr(_T_2595) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2597 = not(_T_2596) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2598 = not(CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2599 = and(_T_2597, _T_2598) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2600 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2601 = and(_T_2599, _T_2600) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2602 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2603 = and(_T_2601, _T_2602) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[2] <= _T_2603 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2604 = cat(buf_rsp_pickage[2][1], buf_rsp_pickage[2][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2605 = cat(buf_rsp_pickage[2][3], buf_rsp_pickage[2][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2606 = cat(_T_2605, _T_2604) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2607 = orr(_T_2606) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2608 = not(_T_2607) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2609 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2610 = and(_T_2608, _T_2609) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[2] <= _T_2610 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2611 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2612 = and(_T_2611, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2613 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2614 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2615 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2616 = and(_T_2614, _T_2615) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2617 = or(_T_2613, _T_2616) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2618 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2619 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2620 = and(_T_2618, _T_2619) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2621 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2622 = and(_T_2620, _T_2621) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2623 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2624 = and(_T_2622, _T_2623) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2625 = or(_T_2617, _T_2624) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2626 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2627 = and(_T_2626, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2628 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2629 = and(_T_2627, _T_2628) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2630 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2631 = and(_T_2629, _T_2630) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2632 = or(_T_2625, _T_2631) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2633 = and(_T_2612, _T_2632) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2634 = or(_T_2633, buf_age[2][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[2][3] <= _T_2634 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2635 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2636 = and(_T_2635, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2637 = not(_T_2636) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2638 = and(buf_ageQ[2][3], _T_2637) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[2][3] <= _T_2638 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2639 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2640 = not(buf_age[2][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2641 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2642 = and(_T_2640, _T_2641) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2643 = mux(_T_2639, UInt<1>("h00"), _T_2642) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[2][3] <= _T_2643 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2644 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2645 = and(_T_2644, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2646 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2647 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2648 = or(_T_2646, _T_2647) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2649 = not(_T_2648) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2650 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2651 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2652 = and(_T_2650, _T_2651) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2653 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2654 = and(_T_2652, _T_2653) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2655 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2656 = and(_T_2654, _T_2655) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2657 = or(_T_2649, _T_2656) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2658 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2659 = and(_T_2658, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2660 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2661 = and(_T_2659, _T_2660) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2662 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2663 = and(_T_2661, _T_2662) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2664 = or(_T_2657, _T_2663) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2665 = and(_T_2645, _T_2664) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[2][3] <= _T_2665 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2666 = or(buf_rspage_set[2][3], buf_rspage[2][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[2][3] <= _T_2666 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2667 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2668 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2669 = or(_T_2667, _T_2668) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2670 = not(_T_2669) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2671 = and(buf_rspageQ[2][3], _T_2670) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[2][3] <= _T_2671 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2672 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2673 = and(buf_rspageQ[2][3], _T_2672) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[2][3] <= _T_2673 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2674 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2675 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2676 = cat(_T_2675, _T_2674) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2677 = orr(_T_2676) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2678 = not(_T_2677) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2679 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2680 = and(_T_2678, _T_2679) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2681 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2682 = and(_T_2680, _T_2681) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2682 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2683 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2684 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2685 = cat(_T_2684, _T_2683) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2686 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2687 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2688 = cat(_T_2687, _T_2686) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2689 = not(_T_2688) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2690 = and(_T_2685, _T_2689) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2691 = orr(_T_2690) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2692 = not(_T_2691) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2693 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2694 = and(_T_2692, _T_2693) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2695 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2696 = and(_T_2694, _T_2695) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2697 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2698 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2699 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2700 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2701 = cat(_T_2700, _T_2699) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2702 = orr(_T_2701) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2703 = not(_T_2702) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2704 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2705 = and(_T_2703, _T_2704) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2705 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2706 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2707 = and(_T_2706, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2708 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2709 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2710 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2711 = and(_T_2709, _T_2710) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2712 = or(_T_2708, _T_2711) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2713 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2714 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2715 = and(_T_2713, _T_2714) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2716 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2717 = and(_T_2715, _T_2716) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2718 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2720 = or(_T_2712, _T_2719) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2721 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2722 = and(_T_2721, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2723 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2724 = and(_T_2722, _T_2723) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2725 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2726 = and(_T_2724, _T_2725) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2727 = or(_T_2720, _T_2726) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2728 = and(_T_2707, _T_2727) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2729 = or(_T_2728, buf_age[3][0]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][0] <= _T_2729 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2730 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2731 = and(_T_2730, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2732 = not(_T_2731) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2733 = and(buf_ageQ[3][0], _T_2732) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][0] <= _T_2733 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2734 = eq(UInt<2>("h03"), UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2735 = not(buf_age[3][0]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2736 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2737 = and(_T_2735, _T_2736) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2738 = mux(_T_2734, UInt<1>("h00"), _T_2737) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][0] <= _T_2738 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2739 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2740 = and(_T_2739, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2741 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2742 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2743 = or(_T_2741, _T_2742) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2744 = not(_T_2743) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2745 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2746 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2748 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2749 = and(_T_2747, _T_2748) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2750 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2751 = and(_T_2749, _T_2750) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2752 = or(_T_2744, _T_2751) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2753 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2754 = and(_T_2753, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2755 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2757 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2758 = and(_T_2756, _T_2757) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2759 = or(_T_2752, _T_2758) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2760 = and(_T_2740, _T_2759) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][0] <= _T_2760 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2761 = or(buf_rspage_set[3][0], buf_rspage[3][0]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][0] <= _T_2761 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2762 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2763 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2764 = or(_T_2762, _T_2763) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2765 = not(_T_2764) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2766 = and(buf_rspageQ[3][0], _T_2765) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][0] <= _T_2766 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2768 = and(buf_rspageQ[3][0], _T_2767) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][0] <= _T_2768 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2769 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2770 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2771 = cat(_T_2770, _T_2769) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2772 = orr(_T_2771) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2773 = not(_T_2772) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2774 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2775 = and(_T_2773, _T_2774) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2776 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2777 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2778 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2779 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2780 = cat(_T_2779, _T_2778) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2781 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2782 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2783 = cat(_T_2782, _T_2781) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2784 = not(_T_2783) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2785 = and(_T_2780, _T_2784) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2786 = orr(_T_2785) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2787 = not(_T_2786) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2788 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2790 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2791 = and(_T_2789, _T_2790) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2792 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2793 = and(_T_2791, _T_2792) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2793 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2794 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2795 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2796 = cat(_T_2795, _T_2794) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2797 = orr(_T_2796) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2798 = not(_T_2797) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2799 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2800 = and(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2800 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2801 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2802 = and(_T_2801, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2803 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2804 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2805 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2807 = or(_T_2803, _T_2806) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2808 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2809 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2810 = and(_T_2808, _T_2809) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2811 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2812 = and(_T_2810, _T_2811) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2813 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2814 = and(_T_2812, _T_2813) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2815 = or(_T_2807, _T_2814) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2816 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2817 = and(_T_2816, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2818 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2819 = and(_T_2817, _T_2818) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2820 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2821 = and(_T_2819, _T_2820) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2822 = or(_T_2815, _T_2821) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2823 = and(_T_2802, _T_2822) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2824 = or(_T_2823, buf_age[3][1]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][1] <= _T_2824 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2825 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2826 = and(_T_2825, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2827 = not(_T_2826) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2828 = and(buf_ageQ[3][1], _T_2827) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][1] <= _T_2828 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2829 = eq(UInt<2>("h03"), UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2830 = not(buf_age[3][1]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2831 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2832 = and(_T_2830, _T_2831) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2833 = mux(_T_2829, UInt<1>("h00"), _T_2832) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][1] <= _T_2833 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2834 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2835 = and(_T_2834, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2836 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2837 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2838 = or(_T_2836, _T_2837) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2839 = not(_T_2838) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2840 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2841 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2842 = and(_T_2840, _T_2841) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2843 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2844 = and(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2845 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2846 = and(_T_2844, _T_2845) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2847 = or(_T_2839, _T_2846) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2848 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2849 = and(_T_2848, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2850 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2851 = and(_T_2849, _T_2850) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2852 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2853 = and(_T_2851, _T_2852) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2854 = or(_T_2847, _T_2853) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2855 = and(_T_2835, _T_2854) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][1] <= _T_2855 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2856 = or(buf_rspage_set[3][1], buf_rspage[3][1]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][1] <= _T_2856 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2857 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2858 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2859 = or(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2860 = not(_T_2859) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2861 = and(buf_rspageQ[3][1], _T_2860) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][1] <= _T_2861 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2862 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2863 = and(buf_rspageQ[3][1], _T_2862) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][1] <= _T_2863 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2864 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2865 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2866 = cat(_T_2865, _T_2864) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2867 = orr(_T_2866) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2868 = not(_T_2867) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2869 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2871 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2872 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2873 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2874 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2875 = cat(_T_2874, _T_2873) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2876 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2877 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2878 = cat(_T_2877, _T_2876) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2879 = not(_T_2878) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2880 = and(_T_2875, _T_2879) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2881 = orr(_T_2880) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2882 = not(_T_2881) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2883 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2884 = and(_T_2882, _T_2883) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2885 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2886 = and(_T_2884, _T_2885) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2887 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2888 = and(_T_2886, _T_2887) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2888 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2889 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2890 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2891 = cat(_T_2890, _T_2889) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2892 = orr(_T_2891) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2893 = not(_T_2892) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2894 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2895 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2896 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2897 = and(_T_2896, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2898 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2899 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2900 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2901 = and(_T_2899, _T_2900) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2902 = or(_T_2898, _T_2901) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2903 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2904 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_2905 = and(_T_2903, _T_2904) @[el2_lsu_bus_buffer.scala 564:43] - node _T_2906 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_2907 = and(_T_2905, _T_2906) @[el2_lsu_bus_buffer.scala 564:73] - node _T_2908 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_2909 = and(_T_2907, _T_2908) @[el2_lsu_bus_buffer.scala 564:92] - node _T_2910 = or(_T_2902, _T_2909) @[el2_lsu_bus_buffer.scala 563:93] - node _T_2911 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_2912 = and(_T_2911, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_2913 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_2914 = and(_T_2912, _T_2913) @[el2_lsu_bus_buffer.scala 565:54] - node _T_2915 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_2916 = and(_T_2914, _T_2915) @[el2_lsu_bus_buffer.scala 565:73] - node _T_2917 = or(_T_2910, _T_2916) @[el2_lsu_bus_buffer.scala 564:113] - node _T_2918 = and(_T_2897, _T_2917) @[el2_lsu_bus_buffer.scala 562:79] - node _T_2919 = or(_T_2918, buf_age[3][2]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][2] <= _T_2919 @[el2_lsu_bus_buffer.scala 562:29] - node _T_2920 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_2921 = and(_T_2920, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_2922 = not(_T_2921) @[el2_lsu_bus_buffer.scala 567:49] - node _T_2923 = and(buf_ageQ[3][2], _T_2922) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][2] <= _T_2923 @[el2_lsu_bus_buffer.scala 567:29] - node _T_2924 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_2925 = not(buf_age[3][2]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_2926 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_2927 = and(_T_2925, _T_2926) @[el2_lsu_bus_buffer.scala 568:108] - node _T_2928 = mux(_T_2924, UInt<1>("h00"), _T_2927) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][2] <= _T_2928 @[el2_lsu_bus_buffer.scala 568:29] - node _T_2929 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_2930 = and(_T_2929, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_2931 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_2932 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_2933 = or(_T_2931, _T_2932) @[el2_lsu_bus_buffer.scala 570:109] - node _T_2934 = not(_T_2933) @[el2_lsu_bus_buffer.scala 570:81] - node _T_2935 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_2936 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_2937 = and(_T_2935, _T_2936) @[el2_lsu_bus_buffer.scala 571:41] - node _T_2938 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 571:71] - node _T_2940 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 571:90] - node _T_2942 = or(_T_2934, _T_2941) @[el2_lsu_bus_buffer.scala 570:139] - node _T_2943 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_2944 = and(_T_2943, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_2945 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_2946 = and(_T_2944, _T_2945) @[el2_lsu_bus_buffer.scala 572:52] - node _T_2947 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 572:71] - node _T_2949 = or(_T_2942, _T_2948) @[el2_lsu_bus_buffer.scala 571:110] - node _T_2950 = and(_T_2930, _T_2949) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][2] <= _T_2950 @[el2_lsu_bus_buffer.scala 570:29] - node _T_2951 = or(buf_rspage_set[3][2], buf_rspage[3][2]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][2] <= _T_2951 @[el2_lsu_bus_buffer.scala 573:29] - node _T_2952 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_2953 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_2954 = or(_T_2952, _T_2953) @[el2_lsu_bus_buffer.scala 574:80] - node _T_2955 = not(_T_2954) @[el2_lsu_bus_buffer.scala 574:52] - node _T_2956 = and(buf_rspageQ[3][2], _T_2955) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][2] <= _T_2956 @[el2_lsu_bus_buffer.scala 574:29] - node _T_2957 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_2958 = and(buf_rspageQ[3][2], _T_2957) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][2] <= _T_2958 @[el2_lsu_bus_buffer.scala 575:29] - node _T_2959 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2960 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2961 = cat(_T_2960, _T_2959) @[el2_lsu_bus_buffer.scala 558:45] - node _T_2962 = orr(_T_2961) @[el2_lsu_bus_buffer.scala 558:55] - node _T_2963 = not(_T_2962) @[el2_lsu_bus_buffer.scala 558:32] - node _T_2964 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 558:75] - node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 558:59] - node _T_2966 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 558:88] - node _T_2967 = and(_T_2965, _T_2966) @[el2_lsu_bus_buffer.scala 558:86] - CmdPtr0Dec[3] <= _T_2967 @[el2_lsu_bus_buffer.scala 558:29] - node _T_2968 = cat(buf_age[3][1], buf_age[3][0]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2969 = cat(buf_age[3][3], buf_age[3][2]) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2970 = cat(_T_2969, _T_2968) @[el2_lsu_bus_buffer.scala 559:46] - node _T_2971 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2972 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2973 = cat(_T_2972, _T_2971) @[el2_lsu_bus_buffer.scala 559:67] - node _T_2974 = not(_T_2973) @[el2_lsu_bus_buffer.scala 559:55] - node _T_2975 = and(_T_2970, _T_2974) @[el2_lsu_bus_buffer.scala 559:53] - node _T_2976 = orr(_T_2975) @[el2_lsu_bus_buffer.scala 559:78] - node _T_2977 = not(_T_2976) @[el2_lsu_bus_buffer.scala 559:32] - node _T_2978 = not(CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 559:84] - node _T_2979 = and(_T_2977, _T_2978) @[el2_lsu_bus_buffer.scala 559:82] - node _T_2980 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 559:115] - node _T_2981 = and(_T_2979, _T_2980) @[el2_lsu_bus_buffer.scala 559:99] - node _T_2982 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 559:128] - node _T_2983 = and(_T_2981, _T_2982) @[el2_lsu_bus_buffer.scala 559:126] - CmdPtr1Dec[3] <= _T_2983 @[el2_lsu_bus_buffer.scala 559:29] - node _T_2984 = cat(buf_rsp_pickage[3][1], buf_rsp_pickage[3][0]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2985 = cat(buf_rsp_pickage[3][3], buf_rsp_pickage[3][2]) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2986 = cat(_T_2985, _T_2984) @[el2_lsu_bus_buffer.scala 560:53] - node _T_2987 = orr(_T_2986) @[el2_lsu_bus_buffer.scala 560:63] - node _T_2988 = not(_T_2987) @[el2_lsu_bus_buffer.scala 560:32] - node _T_2989 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 560:83] - node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 560:67] - RspPtrDec[3] <= _T_2990 @[el2_lsu_bus_buffer.scala 560:29] - node _T_2991 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 562:48] - node _T_2992 = and(_T_2991, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 562:60] - node _T_2993 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 563:23] - node _T_2994 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 563:52] - node _T_2995 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 563:65] - node _T_2996 = and(_T_2994, _T_2995) @[el2_lsu_bus_buffer.scala 563:63] - node _T_2997 = or(_T_2993, _T_2996) @[el2_lsu_bus_buffer.scala 563:35] - node _T_2998 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 564:25] - node _T_2999 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 564:55] - node _T_3000 = and(_T_2998, _T_2999) @[el2_lsu_bus_buffer.scala 564:43] - node _T_3001 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 564:78] - node _T_3002 = and(_T_3000, _T_3001) @[el2_lsu_bus_buffer.scala 564:73] - node _T_3003 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 564:97] - node _T_3004 = and(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 564:92] - node _T_3005 = or(_T_2997, _T_3004) @[el2_lsu_bus_buffer.scala 563:93] - node _T_3006 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 565:19] - node _T_3007 = and(_T_3006, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 565:37] - node _T_3008 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 565:59] - node _T_3009 = and(_T_3007, _T_3008) @[el2_lsu_bus_buffer.scala 565:54] - node _T_3010 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 565:78] - node _T_3011 = and(_T_3009, _T_3010) @[el2_lsu_bus_buffer.scala 565:73] - node _T_3012 = or(_T_3005, _T_3011) @[el2_lsu_bus_buffer.scala 564:113] - node _T_3013 = and(_T_2992, _T_3012) @[el2_lsu_bus_buffer.scala 562:79] - node _T_3014 = or(_T_3013, buf_age[3][3]) @[el2_lsu_bus_buffer.scala 565:96] - buf_age_in[3][3] <= _T_3014 @[el2_lsu_bus_buffer.scala 562:29] - node _T_3015 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 567:65] - node _T_3016 = and(_T_3015, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 567:76] - node _T_3017 = not(_T_3016) @[el2_lsu_bus_buffer.scala 567:49] - node _T_3018 = and(buf_ageQ[3][3], _T_3017) @[el2_lsu_bus_buffer.scala 567:47] - buf_age[3][3] <= _T_3018 @[el2_lsu_bus_buffer.scala 567:29] - node _T_3019 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 568:59] - node _T_3020 = not(buf_age[3][3]) @[el2_lsu_bus_buffer.scala 568:93] - node _T_3021 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 568:124] - node _T_3022 = and(_T_3020, _T_3021) @[el2_lsu_bus_buffer.scala 568:108] - node _T_3023 = mux(_T_3019, UInt<1>("h00"), _T_3022) @[el2_lsu_bus_buffer.scala 568:35] - buf_age_younger[3][3] <= _T_3023 @[el2_lsu_bus_buffer.scala 568:29] - node _T_3024 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:47] - node _T_3025 = and(_T_3024, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 570:59] - node _T_3026 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 570:97] - node _T_3027 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 570:125] - node _T_3028 = or(_T_3026, _T_3027) @[el2_lsu_bus_buffer.scala 570:109] - node _T_3029 = not(_T_3028) @[el2_lsu_bus_buffer.scala 570:81] - node _T_3030 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 571:23] - node _T_3031 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 571:53] - node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 571:41] - node _T_3033 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 571:76] - node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 571:71] - node _T_3035 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 571:95] - node _T_3036 = and(_T_3034, _T_3035) @[el2_lsu_bus_buffer.scala 571:90] - node _T_3037 = or(_T_3029, _T_3036) @[el2_lsu_bus_buffer.scala 570:139] - node _T_3038 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 572:17] - node _T_3039 = and(_T_3038, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 572:35] - node _T_3040 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 572:57] - node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 572:52] - node _T_3042 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 572:76] - node _T_3043 = and(_T_3041, _T_3042) @[el2_lsu_bus_buffer.scala 572:71] - node _T_3044 = or(_T_3037, _T_3043) @[el2_lsu_bus_buffer.scala 571:110] - node _T_3045 = and(_T_3025, _T_3044) @[el2_lsu_bus_buffer.scala 570:78] - buf_rspage_set[3][3] <= _T_3045 @[el2_lsu_bus_buffer.scala 570:29] - node _T_3046 = or(buf_rspage_set[3][3], buf_rspage[3][3]) @[el2_lsu_bus_buffer.scala 573:53] - buf_rspage_in[3][3] <= _T_3046 @[el2_lsu_bus_buffer.scala 573:29] - node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 574:68] - node _T_3048 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:96] - node _T_3049 = or(_T_3047, _T_3048) @[el2_lsu_bus_buffer.scala 574:80] - node _T_3050 = not(_T_3049) @[el2_lsu_bus_buffer.scala 574:52] - node _T_3051 = and(buf_rspageQ[3][3], _T_3050) @[el2_lsu_bus_buffer.scala 574:50] - buf_rspage[3][3] <= _T_3051 @[el2_lsu_bus_buffer.scala 574:29] - node _T_3052 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 575:66] - node _T_3053 = and(buf_rspageQ[3][3], _T_3052) @[el2_lsu_bus_buffer.scala 575:50] - buf_rsp_pickage[3][3] <= _T_3053 @[el2_lsu_bus_buffer.scala 575:29] - node _T_3054 = cat(CmdPtr0Dec[1], CmdPtr0Dec[0]) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3055 = cat(CmdPtr0Dec[3], CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3056 = cat(_T_3055, _T_3054) @[el2_lsu_bus_buffer.scala 578:59] - node _T_3057 = bits(_T_3056, 0, 0) @[OneHot.scala 85:71] - node _T_3058 = bits(_T_3056, 1, 1) @[OneHot.scala 85:71] - node _T_3059 = bits(_T_3056, 2, 2) @[OneHot.scala 85:71] - node _T_3060 = bits(_T_3056, 3, 3) @[OneHot.scala 85:71] - node _T_3061 = mux(_T_3060, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3062 = mux(_T_3059, UInt<4>("h04"), _T_3061) @[Mux.scala 47:69] - node _T_3063 = mux(_T_3058, UInt<4>("h02"), _T_3062) @[Mux.scala 47:69] - node _T_3064 = mux(_T_3057, UInt<4>("h01"), _T_3063) @[Mux.scala 47:69] - CmdPtr0 <= _T_3064 @[el2_lsu_bus_buffer.scala 578:27] - node _T_3065 = cat(CmdPtr1Dec[1], CmdPtr1Dec[0]) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3066 = cat(CmdPtr1Dec[3], CmdPtr1Dec[2]) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3067 = cat(_T_3066, _T_3065) @[el2_lsu_bus_buffer.scala 579:59] - node _T_3068 = bits(_T_3067, 0, 0) @[OneHot.scala 85:71] - node _T_3069 = bits(_T_3067, 1, 1) @[OneHot.scala 85:71] - node _T_3070 = bits(_T_3067, 2, 2) @[OneHot.scala 85:71] - node _T_3071 = bits(_T_3067, 3, 3) @[OneHot.scala 85:71] - node _T_3072 = mux(_T_3071, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3073 = mux(_T_3070, UInt<4>("h04"), _T_3072) @[Mux.scala 47:69] - node _T_3074 = mux(_T_3069, UInt<4>("h02"), _T_3073) @[Mux.scala 47:69] - node _T_3075 = mux(_T_3068, UInt<4>("h01"), _T_3074) @[Mux.scala 47:69] - CmdPtr1 <= _T_3075 @[el2_lsu_bus_buffer.scala 579:27] - node _T_3076 = cat(RspPtrDec[1], RspPtrDec[0]) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3077 = cat(RspPtrDec[3], RspPtrDec[2]) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3078 = cat(_T_3077, _T_3076) @[el2_lsu_bus_buffer.scala 580:58] - node _T_3079 = bits(_T_3078, 0, 0) @[OneHot.scala 85:71] - node _T_3080 = bits(_T_3078, 1, 1) @[OneHot.scala 85:71] - node _T_3081 = bits(_T_3078, 2, 2) @[OneHot.scala 85:71] - node _T_3082 = bits(_T_3078, 3, 3) @[OneHot.scala 85:71] - node _T_3083 = mux(_T_3082, UInt<4>("h08"), UInt<4>("h00")) @[Mux.scala 47:69] - node _T_3084 = mux(_T_3081, UInt<4>("h04"), _T_3083) @[Mux.scala 47:69] - node _T_3085 = mux(_T_3080, UInt<4>("h02"), _T_3084) @[Mux.scala 47:69] - node _T_3086 = mux(_T_3079, UInt<4>("h01"), _T_3085) @[Mux.scala 47:69] - RspPtr <= _T_3086 @[el2_lsu_bus_buffer.scala 580:27] - node _T_3087 = or(CmdPtr0Dec[0], CmdPtr0Dec[1]) @[el2_lsu_bus_buffer.scala 581:49] - node _T_3088 = or(_T_3087, CmdPtr0Dec[2]) @[el2_lsu_bus_buffer.scala 581:49] - node _T_3089 = or(_T_3088, CmdPtr0Dec[3]) @[el2_lsu_bus_buffer.scala 581:49] - found_cmdptr0 <= _T_3089 @[el2_lsu_bus_buffer.scala 581:27] - node _T_3090 = or(CmdPtr1Dec[0], CmdPtr1Dec[1]) @[el2_lsu_bus_buffer.scala 582:49] - node _T_3091 = or(_T_3090, CmdPtr1Dec[2]) @[el2_lsu_bus_buffer.scala 582:49] - node _T_3092 = or(_T_3091, CmdPtr1Dec[3]) @[el2_lsu_bus_buffer.scala 582:49] - found_cmdptr1 <= _T_3092 @[el2_lsu_bus_buffer.scala 582:27] - buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3093 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3094 = and(ibuf_drain_vld, _T_3093) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[0] <= _T_3094 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3095 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3096 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3097 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3098 = and(_T_3096, _T_3097) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3099 = bits(_T_3098, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3100 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3101 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3102 = mux(_T_3099, _T_3100, _T_3101) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3103 = mux(ibuf_drainvec_vld[0], _T_3095, _T_3102) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[0] <= _T_3103 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3104 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3105 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3106 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3107 = and(_T_3105, _T_3106) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3108 = bits(_T_3107, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3109 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3110 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3111 = mux(_T_3108, _T_3109, _T_3110) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3112 = mux(ibuf_drainvec_vld[0], _T_3104, _T_3111) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[0] <= _T_3112 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3113 = mux(ibuf_drainvec_vld[0], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[0] <= _T_3113 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3114 = mux(ibuf_drainvec_vld[0], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[0] <= _T_3114 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3115 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3116 = mux(ibuf_drainvec_vld[0], _T_3115, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[0] <= _T_3116 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3117 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3118 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3119 = and(_T_3117, _T_3118) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3120 = mux(ibuf_drainvec_vld[0], ibuf_dual, _T_3119) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[0] <= _T_3120 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3121 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3122 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3124 = bits(_T_3123, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3125 = mux(_T_3124, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3126 = mux(ibuf_drainvec_vld[0], ibuf_dualtag, _T_3125) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[0] <= _T_3126 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3127 = mux(ibuf_drainvec_vld[0], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[0] <= _T_3127 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3128 = mux(ibuf_drainvec_vld[0], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[0] <= _T_3128 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3129 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3130 = mux(ibuf_drainvec_vld[0], ibuf_sz, _T_3129) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[0] <= _T_3130 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3131 = mux(ibuf_drainvec_vld[0], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[0] <= _T_3131 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3132 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3132 : @[Conditional.scala 40:58] - node _T_3133 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3134 = mux(_T_3133, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[0] <= _T_3134 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3135 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3137 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3138 = and(_T_3136, _T_3137) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3139 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3140 = and(_T_3138, _T_3139) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3141 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3142 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3144 = or(_T_3140, _T_3143) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3145 = and(_T_3135, _T_3144) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3146 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3147 = and(ibuf_drain_vld, _T_3146) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3148 = or(_T_3145, _T_3147) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[0] <= _T_3148 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3149 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3150 = and(ibuf_drain_vld, _T_3149) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3151 = bits(_T_3150, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3152 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3153 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3154 = mux(_T_3151, _T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[0] <= _T_3154 @[el2_lsu_bus_buffer.scala 620:31] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 508:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_3.io.en <= obuf_wr_en @[el2_lib.scala 511:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + obuf_data <= obuf_data_in @[el2_lib.scala 514:16] + reg _T_1852 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 414:54] + _T_1852 <= obuf_wr_timer_in @[el2_lsu_bus_buffer.scala 414:54] + obuf_wr_timer <= _T_1852 @[el2_lsu_bus_buffer.scala 414:17] + wire WrPtr0_m : UInt<2> + WrPtr0_m <= UInt<1>("h00") + node _T_1853 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1854 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1855 = and(ibuf_valid, _T_1854) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1856 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1857 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1858 = and(io.ldst_dual_r, _T_1857) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1859 = or(_T_1856, _T_1858) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1860 = and(io.lsu_busreq_r, _T_1859) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1861 = or(_T_1855, _T_1860) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1862 = eq(_T_1861, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1863 = and(_T_1853, _T_1862) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1864 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1865 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1866 = and(ibuf_valid, _T_1865) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1867 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1868 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1869 = and(io.ldst_dual_r, _T_1868) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1870 = or(_T_1867, _T_1869) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1871 = and(io.lsu_busreq_r, _T_1870) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1872 = or(_T_1866, _T_1871) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1873 = eq(_T_1872, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1874 = and(_T_1864, _T_1873) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1875 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1876 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1877 = and(ibuf_valid, _T_1876) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1878 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1879 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1880 = and(io.ldst_dual_r, _T_1879) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1881 = or(_T_1878, _T_1880) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1882 = and(io.lsu_busreq_r, _T_1881) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1883 = or(_T_1877, _T_1882) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1884 = eq(_T_1883, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1885 = and(_T_1875, _T_1884) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1886 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 417:65] + node _T_1887 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 418:30] + node _T_1888 = and(ibuf_valid, _T_1887) @[el2_lsu_bus_buffer.scala 418:19] + node _T_1889 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:18] + node _T_1890 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 419:57] + node _T_1891 = and(io.ldst_dual_r, _T_1890) @[el2_lsu_bus_buffer.scala 419:45] + node _T_1892 = or(_T_1889, _T_1891) @[el2_lsu_bus_buffer.scala 419:27] + node _T_1893 = and(io.lsu_busreq_r, _T_1892) @[el2_lsu_bus_buffer.scala 418:58] + node _T_1894 = or(_T_1888, _T_1893) @[el2_lsu_bus_buffer.scala 418:39] + node _T_1895 = eq(_T_1894, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 418:5] + node _T_1896 = and(_T_1886, _T_1895) @[el2_lsu_bus_buffer.scala 417:76] + node _T_1897 = mux(_T_1896, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1885, UInt<2>("h02"), _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1874, UInt<1>("h01"), _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1863, UInt<1>("h00"), _T_1899) @[Mux.scala 98:16] + WrPtr0_m <= _T_1900 @[el2_lsu_bus_buffer.scala 417:12] + wire WrPtr1_m : UInt<2> + WrPtr1_m <= UInt<1>("h00") + node _T_1901 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1902 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1903 = and(ibuf_valid, _T_1902) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1904 = eq(WrPtr0_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1905 = and(io.lsu_busreq_m, _T_1904) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1906 = or(_T_1903, _T_1905) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1907 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1908 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1909 = and(io.ldst_dual_r, _T_1908) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1910 = or(_T_1907, _T_1909) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1911 = and(io.lsu_busreq_r, _T_1910) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1912 = or(_T_1906, _T_1911) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1913 = eq(_T_1912, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1914 = and(_T_1901, _T_1913) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1915 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1916 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1917 = and(ibuf_valid, _T_1916) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1918 = eq(WrPtr0_m, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1919 = and(io.lsu_busreq_m, _T_1918) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1920 = or(_T_1917, _T_1919) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1921 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1922 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1923 = and(io.ldst_dual_r, _T_1922) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1924 = or(_T_1921, _T_1923) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1925 = and(io.lsu_busreq_r, _T_1924) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1926 = or(_T_1920, _T_1925) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1927 = eq(_T_1926, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1928 = and(_T_1915, _T_1927) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1929 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1930 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1931 = and(ibuf_valid, _T_1930) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1932 = eq(WrPtr0_m, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1933 = and(io.lsu_busreq_m, _T_1932) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1934 = or(_T_1931, _T_1933) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1935 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1936 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1937 = and(io.ldst_dual_r, _T_1936) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1938 = or(_T_1935, _T_1937) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1939 = and(io.lsu_busreq_r, _T_1938) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1940 = or(_T_1934, _T_1939) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1941 = eq(_T_1940, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1942 = and(_T_1929, _T_1941) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1943 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 423:65] + node _T_1944 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 423:103] + node _T_1945 = and(ibuf_valid, _T_1944) @[el2_lsu_bus_buffer.scala 423:92] + node _T_1946 = eq(WrPtr0_m, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 424:33] + node _T_1947 = and(io.lsu_busreq_m, _T_1946) @[el2_lsu_bus_buffer.scala 424:22] + node _T_1948 = or(_T_1945, _T_1947) @[el2_lsu_bus_buffer.scala 423:112] + node _T_1949 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 425:36] + node _T_1950 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 426:34] + node _T_1951 = and(io.ldst_dual_r, _T_1950) @[el2_lsu_bus_buffer.scala 426:23] + node _T_1952 = or(_T_1949, _T_1951) @[el2_lsu_bus_buffer.scala 425:46] + node _T_1953 = and(io.lsu_busreq_r, _T_1952) @[el2_lsu_bus_buffer.scala 425:22] + node _T_1954 = or(_T_1948, _T_1953) @[el2_lsu_bus_buffer.scala 424:42] + node _T_1955 = eq(_T_1954, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 423:78] + node _T_1956 = and(_T_1943, _T_1955) @[el2_lsu_bus_buffer.scala 423:76] + node _T_1957 = mux(_T_1956, UInt<2>("h03"), UInt<2>("h03")) @[Mux.scala 98:16] + node _T_1958 = mux(_T_1942, UInt<2>("h02"), _T_1957) @[Mux.scala 98:16] + node _T_1959 = mux(_T_1928, UInt<1>("h01"), _T_1958) @[Mux.scala 98:16] + node _T_1960 = mux(_T_1914, UInt<1>("h00"), _T_1959) @[Mux.scala 98:16] + WrPtr1_m <= _T_1960 @[el2_lsu_bus_buffer.scala 423:12] + wire buf_age : UInt<4>[4] @[el2_lsu_bus_buffer.scala 428:21] + buf_age[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + buf_age[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 429:11] + node _T_1961 = orr(buf_age[0]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1962 = eq(_T_1961, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1963 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1964 = and(_T_1962, _T_1963) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1965 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1966 = and(_T_1964, _T_1965) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1967 = orr(buf_age[1]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1968 = eq(_T_1967, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1969 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1970 = and(_T_1968, _T_1969) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1971 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1972 = and(_T_1970, _T_1971) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1973 = orr(buf_age[2]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1974 = eq(_T_1973, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1975 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1976 = and(_T_1974, _T_1975) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1977 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1978 = and(_T_1976, _T_1977) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1979 = orr(buf_age[3]) @[el2_lsu_bus_buffer.scala 431:58] + node _T_1980 = eq(_T_1979, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:45] + node _T_1981 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 431:78] + node _T_1982 = and(_T_1980, _T_1981) @[el2_lsu_bus_buffer.scala 431:63] + node _T_1983 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 431:90] + node _T_1984 = and(_T_1982, _T_1983) @[el2_lsu_bus_buffer.scala 431:88] + node _T_1985 = cat(_T_1984, _T_1978) @[Cat.scala 29:58] + node _T_1986 = cat(_T_1985, _T_1972) @[Cat.scala 29:58] + node CmdPtr0Dec = cat(_T_1986, _T_1966) @[Cat.scala 29:58] + node _T_1987 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1988 = and(buf_age[0], _T_1987) @[el2_lsu_bus_buffer.scala 432:59] + node _T_1989 = orr(_T_1988) @[el2_lsu_bus_buffer.scala 432:76] + node _T_1990 = eq(_T_1989, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_1991 = bits(CmdPtr0Dec, 0, 0) @[el2_lsu_bus_buffer.scala 432:94] + node _T_1992 = eq(_T_1991, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_1993 = and(_T_1990, _T_1992) @[el2_lsu_bus_buffer.scala 432:81] + node _T_1994 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_1995 = and(_T_1993, _T_1994) @[el2_lsu_bus_buffer.scala 432:98] + node _T_1996 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_1997 = and(_T_1995, _T_1996) @[el2_lsu_bus_buffer.scala 432:123] + node _T_1998 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_1999 = and(buf_age[1], _T_1998) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2000 = orr(_T_1999) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2001 = eq(_T_2000, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2002 = bits(CmdPtr0Dec, 1, 1) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2003 = eq(_T_2002, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2004 = and(_T_2001, _T_2003) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2005 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2006 = and(_T_2004, _T_2005) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2007 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2008 = and(_T_2006, _T_2007) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2009 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2010 = and(buf_age[2], _T_2009) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2011 = orr(_T_2010) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2012 = eq(_T_2011, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2013 = bits(CmdPtr0Dec, 2, 2) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2014 = eq(_T_2013, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2015 = and(_T_2012, _T_2014) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2016 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2017 = and(_T_2015, _T_2016) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2018 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2019 = and(_T_2017, _T_2018) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2020 = not(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 432:62] + node _T_2021 = and(buf_age[3], _T_2020) @[el2_lsu_bus_buffer.scala 432:59] + node _T_2022 = orr(_T_2021) @[el2_lsu_bus_buffer.scala 432:76] + node _T_2023 = eq(_T_2022, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:45] + node _T_2024 = bits(CmdPtr0Dec, 3, 3) @[el2_lsu_bus_buffer.scala 432:94] + node _T_2025 = eq(_T_2024, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:83] + node _T_2026 = and(_T_2023, _T_2025) @[el2_lsu_bus_buffer.scala 432:81] + node _T_2027 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 432:113] + node _T_2028 = and(_T_2026, _T_2027) @[el2_lsu_bus_buffer.scala 432:98] + node _T_2029 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 432:125] + node _T_2030 = and(_T_2028, _T_2029) @[el2_lsu_bus_buffer.scala 432:123] + node _T_2031 = cat(_T_2030, _T_2019) @[Cat.scala 29:58] + node _T_2032 = cat(_T_2031, _T_2008) @[Cat.scala 29:58] + node CmdPtr1Dec = cat(_T_2032, _T_1997) @[Cat.scala 29:58] + wire buf_rsp_pickage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 433:29] + buf_rsp_pickage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + buf_rsp_pickage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 434:19] + node _T_2033 = orr(buf_rsp_pickage[0]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2034 = eq(_T_2033, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2035 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2036 = and(_T_2034, _T_2035) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2037 = orr(buf_rsp_pickage[1]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2038 = eq(_T_2037, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2039 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2040 = and(_T_2038, _T_2039) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2041 = orr(buf_rsp_pickage[2]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2042 = eq(_T_2041, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2043 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2044 = and(_T_2042, _T_2043) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2045 = orr(buf_rsp_pickage[3]) @[el2_lsu_bus_buffer.scala 435:65] + node _T_2046 = eq(_T_2045, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 435:44] + node _T_2047 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 435:85] + node _T_2048 = and(_T_2046, _T_2047) @[el2_lsu_bus_buffer.scala 435:70] + node _T_2049 = cat(_T_2048, _T_2044) @[Cat.scala 29:58] + node _T_2050 = cat(_T_2049, _T_2040) @[Cat.scala 29:58] + node RspPtrDec = cat(_T_2050, _T_2036) @[Cat.scala 29:58] + node _T_2051 = orr(CmdPtr0Dec) @[el2_lsu_bus_buffer.scala 436:31] + found_cmdptr0 <= _T_2051 @[el2_lsu_bus_buffer.scala 436:17] + node _T_2052 = orr(CmdPtr1Dec) @[el2_lsu_bus_buffer.scala 437:31] + found_cmdptr1 <= _T_2052 @[el2_lsu_bus_buffer.scala 437:17] + wire CmdPtr1 : UInt<2> + CmdPtr1 <= UInt<1>("h00") + wire RspPtr : UInt<2> + RspPtr <= UInt<1>("h00") + node _T_2053 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2054 = cat(_T_2053, CmdPtr0Dec) @[Cat.scala 29:58] + node _T_2055 = bits(_T_2054, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2056 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2057 = or(_T_2055, _T_2056) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2058 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2059 = or(_T_2057, _T_2058) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2060 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2061 = or(_T_2059, _T_2060) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2062 = bits(_T_2054, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2063 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2064 = or(_T_2062, _T_2063) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2065 = bits(_T_2054, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2066 = or(_T_2064, _T_2065) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2067 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2068 = or(_T_2066, _T_2067) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2069 = bits(_T_2054, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2070 = bits(_T_2054, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2071 = or(_T_2069, _T_2070) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2072 = bits(_T_2054, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2073 = or(_T_2071, _T_2072) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2074 = bits(_T_2054, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2075 = or(_T_2073, _T_2074) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2076 = cat(_T_2061, _T_2068) @[Cat.scala 29:58] + node _T_2077 = cat(_T_2076, _T_2075) @[Cat.scala 29:58] + CmdPtr0 <= _T_2077 @[el2_lsu_bus_buffer.scala 444:11] + node _T_2078 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2079 = cat(_T_2078, CmdPtr1Dec) @[Cat.scala 29:58] + node _T_2080 = bits(_T_2079, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2081 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2082 = or(_T_2080, _T_2081) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2083 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2084 = or(_T_2082, _T_2083) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2085 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2086 = or(_T_2084, _T_2085) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2087 = bits(_T_2079, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2088 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2089 = or(_T_2087, _T_2088) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2090 = bits(_T_2079, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2091 = or(_T_2089, _T_2090) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2092 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2093 = or(_T_2091, _T_2092) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2094 = bits(_T_2079, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2095 = bits(_T_2079, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2096 = or(_T_2094, _T_2095) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2097 = bits(_T_2079, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2098 = or(_T_2096, _T_2097) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2099 = bits(_T_2079, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2100 = or(_T_2098, _T_2099) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2101 = cat(_T_2086, _T_2093) @[Cat.scala 29:58] + node _T_2102 = cat(_T_2101, _T_2100) @[Cat.scala 29:58] + CmdPtr1 <= _T_2102 @[el2_lsu_bus_buffer.scala 446:11] + node _T_2103 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_2104 = cat(_T_2103, RspPtrDec) @[Cat.scala 29:58] + node _T_2105 = bits(_T_2104, 4, 4) @[el2_lsu_bus_buffer.scala 439:39] + node _T_2106 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:45] + node _T_2107 = or(_T_2105, _T_2106) @[el2_lsu_bus_buffer.scala 439:42] + node _T_2108 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:51] + node _T_2109 = or(_T_2107, _T_2108) @[el2_lsu_bus_buffer.scala 439:48] + node _T_2110 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:57] + node _T_2111 = or(_T_2109, _T_2110) @[el2_lsu_bus_buffer.scala 439:54] + node _T_2112 = bits(_T_2104, 2, 2) @[el2_lsu_bus_buffer.scala 439:64] + node _T_2113 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:70] + node _T_2114 = or(_T_2112, _T_2113) @[el2_lsu_bus_buffer.scala 439:67] + node _T_2115 = bits(_T_2104, 6, 6) @[el2_lsu_bus_buffer.scala 439:76] + node _T_2116 = or(_T_2114, _T_2115) @[el2_lsu_bus_buffer.scala 439:73] + node _T_2117 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:82] + node _T_2118 = or(_T_2116, _T_2117) @[el2_lsu_bus_buffer.scala 439:79] + node _T_2119 = bits(_T_2104, 1, 1) @[el2_lsu_bus_buffer.scala 439:89] + node _T_2120 = bits(_T_2104, 3, 3) @[el2_lsu_bus_buffer.scala 439:95] + node _T_2121 = or(_T_2119, _T_2120) @[el2_lsu_bus_buffer.scala 439:92] + node _T_2122 = bits(_T_2104, 5, 5) @[el2_lsu_bus_buffer.scala 439:101] + node _T_2123 = or(_T_2121, _T_2122) @[el2_lsu_bus_buffer.scala 439:98] + node _T_2124 = bits(_T_2104, 7, 7) @[el2_lsu_bus_buffer.scala 439:107] + node _T_2125 = or(_T_2123, _T_2124) @[el2_lsu_bus_buffer.scala 439:104] + node _T_2126 = cat(_T_2111, _T_2118) @[Cat.scala 29:58] + node _T_2127 = cat(_T_2126, _T_2125) @[Cat.scala 29:58] + RspPtr <= _T_2127 @[el2_lsu_bus_buffer.scala 447:10] + wire buf_state_en : UInt<1>[4] @[el2_lsu_bus_buffer.scala 448:26] + buf_state_en[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 449:16] + wire buf_rspageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 450:25] + buf_rspageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + buf_rspageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 451:15] + wire buf_rspage_set : UInt<4>[4] @[el2_lsu_bus_buffer.scala 452:28] + buf_rspage_set[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + buf_rspage_set[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 453:18] + wire buf_rspage_in : UInt<4>[4] @[el2_lsu_bus_buffer.scala 454:27] + buf_rspage_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + buf_rspage_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 455:17] + wire buf_rspage : UInt<4>[4] @[el2_lsu_bus_buffer.scala 456:24] + buf_rspage[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + buf_rspage[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 457:14] + node _T_2128 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2129 = and(_T_2128, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2130 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2131 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2132 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2133 = and(_T_2131, _T_2132) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2134 = or(_T_2130, _T_2133) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2135 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2136 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2137 = and(_T_2135, _T_2136) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2138 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2139 = and(_T_2137, _T_2138) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2140 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2141 = and(_T_2139, _T_2140) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2142 = or(_T_2134, _T_2141) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2143 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2144 = and(_T_2143, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2145 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2146 = and(_T_2144, _T_2145) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2147 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2148 = and(_T_2146, _T_2147) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2149 = or(_T_2142, _T_2148) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2150 = and(_T_2129, _T_2149) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2151 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2152 = or(_T_2150, _T_2151) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2153 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2154 = and(_T_2153, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2155 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2156 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2157 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2158 = and(_T_2156, _T_2157) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2159 = or(_T_2155, _T_2158) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2160 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2161 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2162 = and(_T_2160, _T_2161) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2163 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2164 = and(_T_2162, _T_2163) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2165 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2166 = and(_T_2164, _T_2165) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2167 = or(_T_2159, _T_2166) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2168 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2169 = and(_T_2168, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2170 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2171 = and(_T_2169, _T_2170) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2172 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2173 = and(_T_2171, _T_2172) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2174 = or(_T_2167, _T_2173) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2175 = and(_T_2154, _T_2174) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2176 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2177 = or(_T_2175, _T_2176) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2178 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2179 = and(_T_2178, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2180 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2181 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2182 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2183 = and(_T_2181, _T_2182) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2184 = or(_T_2180, _T_2183) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2185 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2186 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2187 = and(_T_2185, _T_2186) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2188 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2189 = and(_T_2187, _T_2188) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2190 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2191 = and(_T_2189, _T_2190) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2192 = or(_T_2184, _T_2191) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2193 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2194 = and(_T_2193, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2195 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2196 = and(_T_2194, _T_2195) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2197 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2198 = and(_T_2196, _T_2197) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2199 = or(_T_2192, _T_2198) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2200 = and(_T_2179, _T_2199) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2201 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2202 = or(_T_2200, _T_2201) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2203 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2204 = and(_T_2203, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2205 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2206 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2207 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2208 = and(_T_2206, _T_2207) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2209 = or(_T_2205, _T_2208) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2210 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2211 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2212 = and(_T_2210, _T_2211) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2213 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2214 = and(_T_2212, _T_2213) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2215 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2216 = and(_T_2214, _T_2215) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2217 = or(_T_2209, _T_2216) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2218 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2219 = and(_T_2218, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2220 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2221 = and(_T_2219, _T_2220) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2222 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2223 = and(_T_2221, _T_2222) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2224 = or(_T_2217, _T_2223) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2225 = and(_T_2204, _T_2224) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2226 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2227 = or(_T_2225, _T_2226) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2228 = cat(_T_2227, _T_2202) @[Cat.scala 29:58] + node _T_2229 = cat(_T_2228, _T_2177) @[Cat.scala 29:58] + node buf_age_in_0 = cat(_T_2229, _T_2152) @[Cat.scala 29:58] + node _T_2230 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2231 = and(_T_2230, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2232 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2233 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2234 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2235 = and(_T_2233, _T_2234) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2236 = or(_T_2232, _T_2235) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2237 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2238 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2239 = and(_T_2237, _T_2238) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2240 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2241 = and(_T_2239, _T_2240) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2242 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2243 = and(_T_2241, _T_2242) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2244 = or(_T_2236, _T_2243) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2245 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2246 = and(_T_2245, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2247 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2248 = and(_T_2246, _T_2247) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2249 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2250 = and(_T_2248, _T_2249) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2251 = or(_T_2244, _T_2250) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2252 = and(_T_2231, _T_2251) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2253 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2254 = or(_T_2252, _T_2253) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2256 = and(_T_2255, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2257 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2258 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2259 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2260 = and(_T_2258, _T_2259) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2261 = or(_T_2257, _T_2260) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2262 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2263 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2264 = and(_T_2262, _T_2263) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2265 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2266 = and(_T_2264, _T_2265) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2267 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2268 = and(_T_2266, _T_2267) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2269 = or(_T_2261, _T_2268) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2270 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2271 = and(_T_2270, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2272 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2273 = and(_T_2271, _T_2272) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2274 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2275 = and(_T_2273, _T_2274) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2276 = or(_T_2269, _T_2275) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2277 = and(_T_2256, _T_2276) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2278 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2279 = or(_T_2277, _T_2278) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2280 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2281 = and(_T_2280, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2282 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2283 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2284 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2285 = and(_T_2283, _T_2284) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2286 = or(_T_2282, _T_2285) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2287 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2288 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2289 = and(_T_2287, _T_2288) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2290 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2291 = and(_T_2289, _T_2290) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2292 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2293 = and(_T_2291, _T_2292) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2294 = or(_T_2286, _T_2293) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2295 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2296 = and(_T_2295, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2297 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2298 = and(_T_2296, _T_2297) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2299 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2300 = and(_T_2298, _T_2299) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2301 = or(_T_2294, _T_2300) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2302 = and(_T_2281, _T_2301) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2303 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2304 = or(_T_2302, _T_2303) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2305 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2306 = and(_T_2305, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2307 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2308 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2309 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2310 = and(_T_2308, _T_2309) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2311 = or(_T_2307, _T_2310) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2312 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2313 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2314 = and(_T_2312, _T_2313) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2315 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2316 = and(_T_2314, _T_2315) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2317 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2318 = and(_T_2316, _T_2317) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2319 = or(_T_2311, _T_2318) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2320 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2321 = and(_T_2320, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2322 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2323 = and(_T_2321, _T_2322) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2324 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2325 = and(_T_2323, _T_2324) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2326 = or(_T_2319, _T_2325) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2327 = and(_T_2306, _T_2326) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2328 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2329 = or(_T_2327, _T_2328) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2330 = cat(_T_2329, _T_2304) @[Cat.scala 29:58] + node _T_2331 = cat(_T_2330, _T_2279) @[Cat.scala 29:58] + node buf_age_in_1 = cat(_T_2331, _T_2254) @[Cat.scala 29:58] + node _T_2332 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2333 = and(_T_2332, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2334 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2335 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2336 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2337 = and(_T_2335, _T_2336) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2338 = or(_T_2334, _T_2337) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2339 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2340 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2341 = and(_T_2339, _T_2340) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2342 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2343 = and(_T_2341, _T_2342) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2344 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2345 = and(_T_2343, _T_2344) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2346 = or(_T_2338, _T_2345) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2347 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2348 = and(_T_2347, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2349 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2350 = and(_T_2348, _T_2349) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2351 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2352 = and(_T_2350, _T_2351) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2353 = or(_T_2346, _T_2352) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2354 = and(_T_2333, _T_2353) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2355 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2356 = or(_T_2354, _T_2355) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2357 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2358 = and(_T_2357, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2359 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2360 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2361 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2362 = and(_T_2360, _T_2361) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2363 = or(_T_2359, _T_2362) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2364 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2365 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2366 = and(_T_2364, _T_2365) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2367 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2368 = and(_T_2366, _T_2367) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2369 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2370 = and(_T_2368, _T_2369) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2371 = or(_T_2363, _T_2370) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2372 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2373 = and(_T_2372, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2374 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2375 = and(_T_2373, _T_2374) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2376 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2377 = and(_T_2375, _T_2376) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2378 = or(_T_2371, _T_2377) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2379 = and(_T_2358, _T_2378) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2380 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2381 = or(_T_2379, _T_2380) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2382 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2383 = and(_T_2382, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2384 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2385 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2386 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2387 = and(_T_2385, _T_2386) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2388 = or(_T_2384, _T_2387) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2389 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2390 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2391 = and(_T_2389, _T_2390) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2392 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2393 = and(_T_2391, _T_2392) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2394 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2395 = and(_T_2393, _T_2394) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2396 = or(_T_2388, _T_2395) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2397 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2398 = and(_T_2397, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2399 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2400 = and(_T_2398, _T_2399) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2401 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2402 = and(_T_2400, _T_2401) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2403 = or(_T_2396, _T_2402) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2404 = and(_T_2383, _T_2403) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2405 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2406 = or(_T_2404, _T_2405) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2407 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2408 = and(_T_2407, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2409 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2410 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2411 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2412 = and(_T_2410, _T_2411) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2413 = or(_T_2409, _T_2412) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2414 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2415 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2416 = and(_T_2414, _T_2415) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2417 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2418 = and(_T_2416, _T_2417) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2419 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2420 = and(_T_2418, _T_2419) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2421 = or(_T_2413, _T_2420) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2422 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2423 = and(_T_2422, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2424 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2425 = and(_T_2423, _T_2424) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2426 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2427 = and(_T_2425, _T_2426) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2428 = or(_T_2421, _T_2427) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2429 = and(_T_2408, _T_2428) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2430 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2431 = or(_T_2429, _T_2430) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2432 = cat(_T_2431, _T_2406) @[Cat.scala 29:58] + node _T_2433 = cat(_T_2432, _T_2381) @[Cat.scala 29:58] + node buf_age_in_2 = cat(_T_2433, _T_2356) @[Cat.scala 29:58] + node _T_2434 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2435 = and(_T_2434, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2436 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2437 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2438 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2439 = and(_T_2437, _T_2438) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2440 = or(_T_2436, _T_2439) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2441 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2442 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2443 = and(_T_2441, _T_2442) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2444 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2445 = and(_T_2443, _T_2444) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2446 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2447 = and(_T_2445, _T_2446) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2448 = or(_T_2440, _T_2447) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2449 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2450 = and(_T_2449, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2451 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2452 = and(_T_2450, _T_2451) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2453 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2454 = and(_T_2452, _T_2453) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2455 = or(_T_2448, _T_2454) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2456 = and(_T_2435, _T_2455) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2457 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2458 = or(_T_2456, _T_2457) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2459 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2460 = and(_T_2459, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2461 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2462 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2463 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2464 = and(_T_2462, _T_2463) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2465 = or(_T_2461, _T_2464) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2466 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2467 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2468 = and(_T_2466, _T_2467) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2469 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2470 = and(_T_2468, _T_2469) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2471 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2472 = and(_T_2470, _T_2471) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2473 = or(_T_2465, _T_2472) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2474 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2475 = and(_T_2474, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2476 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2477 = and(_T_2475, _T_2476) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2478 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2479 = and(_T_2477, _T_2478) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2480 = or(_T_2473, _T_2479) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2481 = and(_T_2460, _T_2480) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2482 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2483 = or(_T_2481, _T_2482) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2484 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2485 = and(_T_2484, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2486 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2487 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2488 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2489 = and(_T_2487, _T_2488) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2490 = or(_T_2486, _T_2489) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2491 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2492 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2493 = and(_T_2491, _T_2492) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2494 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2495 = and(_T_2493, _T_2494) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2496 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2497 = and(_T_2495, _T_2496) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2498 = or(_T_2490, _T_2497) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2499 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2500 = and(_T_2499, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2501 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2502 = and(_T_2500, _T_2501) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2503 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2504 = and(_T_2502, _T_2503) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2505 = or(_T_2498, _T_2504) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2506 = and(_T_2485, _T_2505) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2507 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2508 = or(_T_2506, _T_2507) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2509 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 459:83] + node _T_2510 = and(_T_2509, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 459:94] + node _T_2511 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 460:20] + node _T_2512 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 460:47] + node _T_2513 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 460:59] + node _T_2514 = and(_T_2512, _T_2513) @[el2_lsu_bus_buffer.scala 460:57] + node _T_2515 = or(_T_2511, _T_2514) @[el2_lsu_bus_buffer.scala 460:31] + node _T_2516 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 461:23] + node _T_2517 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 461:53] + node _T_2518 = and(_T_2516, _T_2517) @[el2_lsu_bus_buffer.scala 461:41] + node _T_2519 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:83] + node _T_2520 = and(_T_2518, _T_2519) @[el2_lsu_bus_buffer.scala 461:71] + node _T_2521 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 461:104] + node _T_2522 = and(_T_2520, _T_2521) @[el2_lsu_bus_buffer.scala 461:92] + node _T_2523 = or(_T_2515, _T_2522) @[el2_lsu_bus_buffer.scala 460:86] + node _T_2524 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 462:17] + node _T_2525 = and(_T_2524, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 462:35] + node _T_2526 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:64] + node _T_2527 = and(_T_2525, _T_2526) @[el2_lsu_bus_buffer.scala 462:52] + node _T_2528 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 462:85] + node _T_2529 = and(_T_2527, _T_2528) @[el2_lsu_bus_buffer.scala 462:73] + node _T_2530 = or(_T_2523, _T_2529) @[el2_lsu_bus_buffer.scala 461:114] + node _T_2531 = and(_T_2510, _T_2530) @[el2_lsu_bus_buffer.scala 459:113] + node _T_2532 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 462:109] + node _T_2533 = or(_T_2531, _T_2532) @[el2_lsu_bus_buffer.scala 462:97] + node _T_2534 = cat(_T_2533, _T_2508) @[Cat.scala 29:58] + node _T_2535 = cat(_T_2534, _T_2483) @[Cat.scala 29:58] + node buf_age_in_3 = cat(_T_2535, _T_2458) @[Cat.scala 29:58] + wire buf_ageQ : UInt<4>[4] @[el2_lsu_bus_buffer.scala 463:22] + buf_ageQ[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + buf_ageQ[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 464:12] + node _T_2536 = bits(buf_ageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2537 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2538 = and(_T_2537, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2539 = eq(_T_2538, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2540 = and(_T_2536, _T_2539) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2541 = bits(buf_ageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2542 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2543 = and(_T_2542, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2544 = eq(_T_2543, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2545 = and(_T_2541, _T_2544) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2546 = bits(buf_ageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2547 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2548 = and(_T_2547, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2549 = eq(_T_2548, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2550 = and(_T_2546, _T_2549) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2551 = bits(buf_ageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2552 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2553 = and(_T_2552, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2554 = eq(_T_2553, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2555 = and(_T_2551, _T_2554) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2556 = cat(_T_2555, _T_2550) @[Cat.scala 29:58] + node _T_2557 = cat(_T_2556, _T_2545) @[Cat.scala 29:58] + node _T_2558 = cat(_T_2557, _T_2540) @[Cat.scala 29:58] + node _T_2559 = bits(buf_ageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2560 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2561 = and(_T_2560, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2562 = eq(_T_2561, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2563 = and(_T_2559, _T_2562) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2564 = bits(buf_ageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2565 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2566 = and(_T_2565, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2567 = eq(_T_2566, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2568 = and(_T_2564, _T_2567) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2569 = bits(buf_ageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2570 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2571 = and(_T_2570, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2572 = eq(_T_2571, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2573 = and(_T_2569, _T_2572) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2574 = bits(buf_ageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2575 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2576 = and(_T_2575, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2577 = eq(_T_2576, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2578 = and(_T_2574, _T_2577) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2579 = cat(_T_2578, _T_2573) @[Cat.scala 29:58] + node _T_2580 = cat(_T_2579, _T_2568) @[Cat.scala 29:58] + node _T_2581 = cat(_T_2580, _T_2563) @[Cat.scala 29:58] + node _T_2582 = bits(buf_ageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2583 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2584 = and(_T_2583, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2585 = eq(_T_2584, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2586 = and(_T_2582, _T_2585) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2587 = bits(buf_ageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2588 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2589 = and(_T_2588, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2590 = eq(_T_2589, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2591 = and(_T_2587, _T_2590) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2592 = bits(buf_ageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2593 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2594 = and(_T_2593, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2595 = eq(_T_2594, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2596 = and(_T_2592, _T_2595) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2597 = bits(buf_ageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2598 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2599 = and(_T_2598, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2600 = eq(_T_2599, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2601 = and(_T_2597, _T_2600) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2602 = cat(_T_2601, _T_2596) @[Cat.scala 29:58] + node _T_2603 = cat(_T_2602, _T_2591) @[Cat.scala 29:58] + node _T_2604 = cat(_T_2603, _T_2586) @[Cat.scala 29:58] + node _T_2605 = bits(buf_ageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2606 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2607 = and(_T_2606, buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2608 = eq(_T_2607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2609 = and(_T_2605, _T_2608) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2610 = bits(buf_ageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2611 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2612 = and(_T_2611, buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2613 = eq(_T_2612, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2614 = and(_T_2610, _T_2613) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2615 = bits(buf_ageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2616 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2617 = and(_T_2616, buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2618 = eq(_T_2617, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2619 = and(_T_2615, _T_2618) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2620 = bits(buf_ageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 465:72] + node _T_2621 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 465:93] + node _T_2622 = and(_T_2621, buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 465:103] + node _T_2623 = eq(_T_2622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 465:78] + node _T_2624 = and(_T_2620, _T_2623) @[el2_lsu_bus_buffer.scala 465:76] + node _T_2625 = cat(_T_2624, _T_2619) @[Cat.scala 29:58] + node _T_2626 = cat(_T_2625, _T_2614) @[Cat.scala 29:58] + node _T_2627 = cat(_T_2626, _T_2609) @[Cat.scala 29:58] + buf_age[0] <= _T_2558 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[1] <= _T_2581 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[2] <= _T_2604 @[el2_lsu_bus_buffer.scala 465:11] + buf_age[3] <= _T_2627 @[el2_lsu_bus_buffer.scala 465:11] + node _T_2628 = eq(UInt<1>("h00"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2629 = bits(buf_age[0], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2630 = eq(_T_2629, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2631 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2632 = and(_T_2630, _T_2631) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2633 = mux(_T_2628, UInt<1>("h00"), _T_2632) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2634 = eq(UInt<1>("h00"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2635 = bits(buf_age[0], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2636 = eq(_T_2635, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2637 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2638 = and(_T_2636, _T_2637) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2639 = mux(_T_2634, UInt<1>("h00"), _T_2638) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2640 = eq(UInt<1>("h00"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2641 = bits(buf_age[0], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2642 = eq(_T_2641, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2643 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2644 = and(_T_2642, _T_2643) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2645 = mux(_T_2640, UInt<1>("h00"), _T_2644) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2646 = eq(UInt<1>("h00"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2647 = bits(buf_age[0], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2648 = eq(_T_2647, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2649 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2650 = and(_T_2648, _T_2649) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2651 = mux(_T_2646, UInt<1>("h00"), _T_2650) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2652 = cat(_T_2651, _T_2645) @[Cat.scala 29:58] + node _T_2653 = cat(_T_2652, _T_2639) @[Cat.scala 29:58] + node _T_2654 = cat(_T_2653, _T_2633) @[Cat.scala 29:58] + node _T_2655 = eq(UInt<1>("h01"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2656 = bits(buf_age[1], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2657 = eq(_T_2656, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2658 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2659 = and(_T_2657, _T_2658) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2660 = mux(_T_2655, UInt<1>("h00"), _T_2659) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2661 = eq(UInt<1>("h01"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2662 = bits(buf_age[1], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2663 = eq(_T_2662, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2664 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2665 = and(_T_2663, _T_2664) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2666 = mux(_T_2661, UInt<1>("h00"), _T_2665) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2667 = eq(UInt<1>("h01"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2668 = bits(buf_age[1], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2669 = eq(_T_2668, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2670 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2671 = and(_T_2669, _T_2670) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2672 = mux(_T_2667, UInt<1>("h00"), _T_2671) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2673 = eq(UInt<1>("h01"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2674 = bits(buf_age[1], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2675 = eq(_T_2674, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2676 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2677 = and(_T_2675, _T_2676) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2678 = mux(_T_2673, UInt<1>("h00"), _T_2677) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2679 = cat(_T_2678, _T_2672) @[Cat.scala 29:58] + node _T_2680 = cat(_T_2679, _T_2666) @[Cat.scala 29:58] + node _T_2681 = cat(_T_2680, _T_2660) @[Cat.scala 29:58] + node _T_2682 = eq(UInt<2>("h02"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2683 = bits(buf_age[2], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2684 = eq(_T_2683, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2685 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2686 = and(_T_2684, _T_2685) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2687 = mux(_T_2682, UInt<1>("h00"), _T_2686) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2688 = eq(UInt<2>("h02"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2689 = bits(buf_age[2], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2690 = eq(_T_2689, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2691 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2692 = and(_T_2690, _T_2691) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2693 = mux(_T_2688, UInt<1>("h00"), _T_2692) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2694 = eq(UInt<2>("h02"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2695 = bits(buf_age[2], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2696 = eq(_T_2695, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2697 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2698 = and(_T_2696, _T_2697) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2699 = mux(_T_2694, UInt<1>("h00"), _T_2698) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2700 = eq(UInt<2>("h02"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2701 = bits(buf_age[2], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2702 = eq(_T_2701, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2703 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2704 = and(_T_2702, _T_2703) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2705 = mux(_T_2700, UInt<1>("h00"), _T_2704) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2706 = cat(_T_2705, _T_2699) @[Cat.scala 29:58] + node _T_2707 = cat(_T_2706, _T_2693) @[Cat.scala 29:58] + node _T_2708 = cat(_T_2707, _T_2687) @[Cat.scala 29:58] + node _T_2709 = eq(UInt<2>("h03"), UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2710 = bits(buf_age[3], 0, 0) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2711 = eq(_T_2710, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2712 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2713 = and(_T_2711, _T_2712) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2714 = mux(_T_2709, UInt<1>("h00"), _T_2713) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2715 = eq(UInt<2>("h03"), UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2716 = bits(buf_age[3], 1, 1) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2717 = eq(_T_2716, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2718 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2719 = and(_T_2717, _T_2718) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2720 = mux(_T_2715, UInt<1>("h00"), _T_2719) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2721 = eq(UInt<2>("h03"), UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2722 = bits(buf_age[3], 2, 2) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2723 = eq(_T_2722, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2724 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2725 = and(_T_2723, _T_2724) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2726 = mux(_T_2721, UInt<1>("h00"), _T_2725) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2727 = eq(UInt<2>("h03"), UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 466:76] + node _T_2728 = bits(buf_age[3], 3, 3) @[el2_lsu_bus_buffer.scala 466:100] + node _T_2729 = eq(_T_2728, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 466:89] + node _T_2730 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 466:119] + node _T_2731 = and(_T_2729, _T_2730) @[el2_lsu_bus_buffer.scala 466:104] + node _T_2732 = mux(_T_2727, UInt<1>("h00"), _T_2731) @[el2_lsu_bus_buffer.scala 466:72] + node _T_2733 = cat(_T_2732, _T_2726) @[Cat.scala 29:58] + node _T_2734 = cat(_T_2733, _T_2720) @[Cat.scala 29:58] + node _T_2735 = cat(_T_2734, _T_2714) @[Cat.scala 29:58] + buf_age_younger[0] <= _T_2654 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[1] <= _T_2681 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[2] <= _T_2708 @[el2_lsu_bus_buffer.scala 466:19] + buf_age_younger[3] <= _T_2735 @[el2_lsu_bus_buffer.scala 466:19] + node _T_2736 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2737 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2738 = and(_T_2736, _T_2737) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2739 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2740 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2741 = and(_T_2739, _T_2740) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2742 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2743 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2744 = and(_T_2742, _T_2743) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2745 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2746 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2747 = and(_T_2745, _T_2746) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2748 = cat(_T_2747, _T_2744) @[Cat.scala 29:58] + node _T_2749 = cat(_T_2748, _T_2741) @[Cat.scala 29:58] + node _T_2750 = cat(_T_2749, _T_2738) @[Cat.scala 29:58] + node _T_2751 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2752 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2753 = and(_T_2751, _T_2752) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2754 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2755 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2756 = and(_T_2754, _T_2755) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2757 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2758 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2759 = and(_T_2757, _T_2758) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2760 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2761 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2762 = and(_T_2760, _T_2761) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2763 = cat(_T_2762, _T_2759) @[Cat.scala 29:58] + node _T_2764 = cat(_T_2763, _T_2756) @[Cat.scala 29:58] + node _T_2765 = cat(_T_2764, _T_2753) @[Cat.scala 29:58] + node _T_2766 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2767 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2768 = and(_T_2766, _T_2767) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2769 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2770 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2771 = and(_T_2769, _T_2770) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2772 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2773 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2774 = and(_T_2772, _T_2773) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2775 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2776 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2777 = and(_T_2775, _T_2776) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2778 = cat(_T_2777, _T_2774) @[Cat.scala 29:58] + node _T_2779 = cat(_T_2778, _T_2771) @[Cat.scala 29:58] + node _T_2780 = cat(_T_2779, _T_2768) @[Cat.scala 29:58] + node _T_2781 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2782 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2783 = and(_T_2781, _T_2782) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2784 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2785 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2786 = and(_T_2784, _T_2785) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2787 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2788 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2789 = and(_T_2787, _T_2788) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2790 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 467:83] + node _T_2791 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 467:102] + node _T_2792 = and(_T_2790, _T_2791) @[el2_lsu_bus_buffer.scala 467:87] + node _T_2793 = cat(_T_2792, _T_2789) @[Cat.scala 29:58] + node _T_2794 = cat(_T_2793, _T_2786) @[Cat.scala 29:58] + node _T_2795 = cat(_T_2794, _T_2783) @[Cat.scala 29:58] + buf_rsp_pickage[0] <= _T_2750 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[1] <= _T_2765 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[2] <= _T_2780 @[el2_lsu_bus_buffer.scala 467:19] + buf_rsp_pickage[3] <= _T_2795 @[el2_lsu_bus_buffer.scala 467:19] + node _T_2796 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2797 = and(_T_2796, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2798 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2799 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2800 = or(_T_2798, _T_2799) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2801 = eq(_T_2800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2802 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2803 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2804 = and(_T_2802, _T_2803) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2805 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2806 = and(_T_2804, _T_2805) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2807 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2808 = and(_T_2806, _T_2807) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2809 = or(_T_2801, _T_2808) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2810 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2811 = and(_T_2810, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2812 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2813 = and(_T_2811, _T_2812) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2814 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2815 = and(_T_2813, _T_2814) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2816 = or(_T_2809, _T_2815) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2817 = and(_T_2797, _T_2816) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2818 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2819 = and(_T_2818, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2820 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2821 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2822 = or(_T_2820, _T_2821) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2823 = eq(_T_2822, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2824 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2825 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2826 = and(_T_2824, _T_2825) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2827 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2828 = and(_T_2826, _T_2827) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2829 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2830 = and(_T_2828, _T_2829) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2831 = or(_T_2823, _T_2830) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2832 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2833 = and(_T_2832, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2834 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2835 = and(_T_2833, _T_2834) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2836 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2837 = and(_T_2835, _T_2836) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2838 = or(_T_2831, _T_2837) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2839 = and(_T_2819, _T_2838) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2840 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2841 = and(_T_2840, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2842 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2843 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2844 = or(_T_2842, _T_2843) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2845 = eq(_T_2844, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2846 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2847 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2848 = and(_T_2846, _T_2847) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2849 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2850 = and(_T_2848, _T_2849) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2851 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2852 = and(_T_2850, _T_2851) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2853 = or(_T_2845, _T_2852) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2854 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2855 = and(_T_2854, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2856 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2857 = and(_T_2855, _T_2856) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2858 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2859 = and(_T_2857, _T_2858) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2860 = or(_T_2853, _T_2859) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2861 = and(_T_2841, _T_2860) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2862 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2863 = and(_T_2862, buf_state_en[0]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2864 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2865 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2866 = or(_T_2864, _T_2865) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2867 = eq(_T_2866, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2868 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2869 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2870 = and(_T_2868, _T_2869) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2871 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2872 = and(_T_2870, _T_2871) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2873 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2874 = and(_T_2872, _T_2873) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2875 = or(_T_2867, _T_2874) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2876 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2877 = and(_T_2876, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2878 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2879 = and(_T_2877, _T_2878) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2880 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2881 = and(_T_2879, _T_2880) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2882 = or(_T_2875, _T_2881) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2883 = and(_T_2863, _T_2882) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2884 = cat(_T_2883, _T_2861) @[Cat.scala 29:58] + node _T_2885 = cat(_T_2884, _T_2839) @[Cat.scala 29:58] + node _T_2886 = cat(_T_2885, _T_2817) @[Cat.scala 29:58] + node _T_2887 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2888 = and(_T_2887, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2889 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2890 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2891 = or(_T_2889, _T_2890) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2892 = eq(_T_2891, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2893 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2894 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2895 = and(_T_2893, _T_2894) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2896 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2897 = and(_T_2895, _T_2896) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2898 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2899 = and(_T_2897, _T_2898) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2900 = or(_T_2892, _T_2899) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2901 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2902 = and(_T_2901, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2903 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2904 = and(_T_2902, _T_2903) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2905 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2906 = and(_T_2904, _T_2905) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2907 = or(_T_2900, _T_2906) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2908 = and(_T_2888, _T_2907) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2909 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2910 = and(_T_2909, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2911 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2912 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2913 = or(_T_2911, _T_2912) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2914 = eq(_T_2913, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2915 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2916 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2917 = and(_T_2915, _T_2916) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2918 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2919 = and(_T_2917, _T_2918) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2920 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2921 = and(_T_2919, _T_2920) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2922 = or(_T_2914, _T_2921) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2923 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2924 = and(_T_2923, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2925 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2926 = and(_T_2924, _T_2925) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2927 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2928 = and(_T_2926, _T_2927) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2929 = or(_T_2922, _T_2928) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2930 = and(_T_2910, _T_2929) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2931 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2932 = and(_T_2931, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2933 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2934 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2935 = or(_T_2933, _T_2934) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2936 = eq(_T_2935, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2937 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2938 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2939 = and(_T_2937, _T_2938) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2940 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2941 = and(_T_2939, _T_2940) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2942 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2943 = and(_T_2941, _T_2942) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2944 = or(_T_2936, _T_2943) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2945 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2946 = and(_T_2945, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2947 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2948 = and(_T_2946, _T_2947) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2949 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2950 = and(_T_2948, _T_2949) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2951 = or(_T_2944, _T_2950) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2952 = and(_T_2932, _T_2951) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2953 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2954 = and(_T_2953, buf_state_en[1]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2955 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2956 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2957 = or(_T_2955, _T_2956) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2958 = eq(_T_2957, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2959 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2960 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2961 = and(_T_2959, _T_2960) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2962 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2963 = and(_T_2961, _T_2962) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2964 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2965 = and(_T_2963, _T_2964) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2966 = or(_T_2958, _T_2965) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2967 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2968 = and(_T_2967, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2969 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2970 = and(_T_2968, _T_2969) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2971 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2972 = and(_T_2970, _T_2971) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2973 = or(_T_2966, _T_2972) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2974 = and(_T_2954, _T_2973) @[el2_lsu_bus_buffer.scala 469:112] + node _T_2975 = cat(_T_2974, _T_2952) @[Cat.scala 29:58] + node _T_2976 = cat(_T_2975, _T_2930) @[Cat.scala 29:58] + node _T_2977 = cat(_T_2976, _T_2908) @[Cat.scala 29:58] + node _T_2978 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_2979 = and(_T_2978, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_2980 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_2981 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_2982 = or(_T_2980, _T_2981) @[el2_lsu_bus_buffer.scala 470:32] + node _T_2983 = eq(_T_2982, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_2984 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_2985 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_2986 = and(_T_2984, _T_2985) @[el2_lsu_bus_buffer.scala 471:41] + node _T_2987 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_2988 = and(_T_2986, _T_2987) @[el2_lsu_bus_buffer.scala 471:71] + node _T_2989 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_2990 = and(_T_2988, _T_2989) @[el2_lsu_bus_buffer.scala 471:90] + node _T_2991 = or(_T_2983, _T_2990) @[el2_lsu_bus_buffer.scala 470:59] + node _T_2992 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_2993 = and(_T_2992, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_2994 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_2995 = and(_T_2993, _T_2994) @[el2_lsu_bus_buffer.scala 472:52] + node _T_2996 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_2997 = and(_T_2995, _T_2996) @[el2_lsu_bus_buffer.scala 472:71] + node _T_2998 = or(_T_2991, _T_2997) @[el2_lsu_bus_buffer.scala 471:110] + node _T_2999 = and(_T_2979, _T_2998) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3000 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3001 = and(_T_3000, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3002 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3003 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3004 = or(_T_3002, _T_3003) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3005 = eq(_T_3004, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3006 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3007 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3008 = and(_T_3006, _T_3007) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3009 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3010 = and(_T_3008, _T_3009) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3011 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3012 = and(_T_3010, _T_3011) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3013 = or(_T_3005, _T_3012) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3014 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3015 = and(_T_3014, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3016 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3017 = and(_T_3015, _T_3016) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3018 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3019 = and(_T_3017, _T_3018) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3020 = or(_T_3013, _T_3019) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3021 = and(_T_3001, _T_3020) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3022 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3023 = and(_T_3022, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3024 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3025 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3026 = or(_T_3024, _T_3025) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3027 = eq(_T_3026, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3028 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3029 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3030 = and(_T_3028, _T_3029) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3031 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3032 = and(_T_3030, _T_3031) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3033 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3034 = and(_T_3032, _T_3033) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3035 = or(_T_3027, _T_3034) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3036 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3037 = and(_T_3036, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3038 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3039 = and(_T_3037, _T_3038) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3040 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3041 = and(_T_3039, _T_3040) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3042 = or(_T_3035, _T_3041) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3043 = and(_T_3023, _T_3042) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3044 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3045 = and(_T_3044, buf_state_en[2]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3046 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3047 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3048 = or(_T_3046, _T_3047) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3049 = eq(_T_3048, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3050 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3051 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3052 = and(_T_3050, _T_3051) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3053 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3054 = and(_T_3052, _T_3053) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3055 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3056 = and(_T_3054, _T_3055) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3057 = or(_T_3049, _T_3056) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3058 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3059 = and(_T_3058, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3060 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3061 = and(_T_3059, _T_3060) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3062 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3063 = and(_T_3061, _T_3062) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3064 = or(_T_3057, _T_3063) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3065 = and(_T_3045, _T_3064) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3066 = cat(_T_3065, _T_3043) @[Cat.scala 29:58] + node _T_3067 = cat(_T_3066, _T_3021) @[Cat.scala 29:58] + node _T_3068 = cat(_T_3067, _T_2999) @[Cat.scala 29:58] + node _T_3069 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3070 = and(_T_3069, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3071 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3072 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3073 = or(_T_3071, _T_3072) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3074 = eq(_T_3073, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3075 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3076 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3077 = and(_T_3075, _T_3076) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3078 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3079 = and(_T_3077, _T_3078) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3080 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3081 = and(_T_3079, _T_3080) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3082 = or(_T_3074, _T_3081) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3083 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3084 = and(_T_3083, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3085 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3086 = and(_T_3084, _T_3085) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3087 = eq(WrPtr0_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3088 = and(_T_3086, _T_3087) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3089 = or(_T_3082, _T_3088) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3090 = and(_T_3070, _T_3089) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3091 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3092 = and(_T_3091, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3093 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3094 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3095 = or(_T_3093, _T_3094) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3096 = eq(_T_3095, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3097 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3098 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3099 = and(_T_3097, _T_3098) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3100 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3101 = and(_T_3099, _T_3100) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3102 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3103 = and(_T_3101, _T_3102) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3104 = or(_T_3096, _T_3103) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3105 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3106 = and(_T_3105, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3107 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3108 = and(_T_3106, _T_3107) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3109 = eq(WrPtr0_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3110 = and(_T_3108, _T_3109) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3111 = or(_T_3104, _T_3110) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3112 = and(_T_3092, _T_3111) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3113 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3114 = and(_T_3113, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3115 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3116 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3117 = or(_T_3115, _T_3116) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3118 = eq(_T_3117, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3119 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3120 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3121 = and(_T_3119, _T_3120) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3122 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3123 = and(_T_3121, _T_3122) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3124 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3125 = and(_T_3123, _T_3124) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3126 = or(_T_3118, _T_3125) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3127 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3128 = and(_T_3127, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3129 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3130 = and(_T_3128, _T_3129) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3131 = eq(WrPtr0_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3132 = and(_T_3130, _T_3131) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3133 = or(_T_3126, _T_3132) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3134 = and(_T_3114, _T_3133) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3135 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 469:82] + node _T_3136 = and(_T_3135, buf_state_en[3]) @[el2_lsu_bus_buffer.scala 469:93] + node _T_3137 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 470:21] + node _T_3138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 470:47] + node _T_3139 = or(_T_3137, _T_3138) @[el2_lsu_bus_buffer.scala 470:32] + node _T_3140 = eq(_T_3139, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 470:6] + node _T_3141 = and(ibuf_drain_vld, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 471:23] + node _T_3142 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 471:53] + node _T_3143 = and(_T_3141, _T_3142) @[el2_lsu_bus_buffer.scala 471:41] + node _T_3144 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:82] + node _T_3145 = and(_T_3143, _T_3144) @[el2_lsu_bus_buffer.scala 471:71] + node _T_3146 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 471:101] + node _T_3147 = and(_T_3145, _T_3146) @[el2_lsu_bus_buffer.scala 471:90] + node _T_3148 = or(_T_3140, _T_3147) @[el2_lsu_bus_buffer.scala 470:59] + node _T_3149 = and(ibuf_byp, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 472:17] + node _T_3150 = and(_T_3149, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 472:35] + node _T_3151 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:63] + node _T_3152 = and(_T_3150, _T_3151) @[el2_lsu_bus_buffer.scala 472:52] + node _T_3153 = eq(WrPtr0_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 472:82] + node _T_3154 = and(_T_3152, _T_3153) @[el2_lsu_bus_buffer.scala 472:71] + node _T_3155 = or(_T_3148, _T_3154) @[el2_lsu_bus_buffer.scala 471:110] + node _T_3156 = and(_T_3136, _T_3155) @[el2_lsu_bus_buffer.scala 469:112] + node _T_3157 = cat(_T_3156, _T_3134) @[Cat.scala 29:58] + node _T_3158 = cat(_T_3157, _T_3112) @[Cat.scala 29:58] + node _T_3159 = cat(_T_3158, _T_3090) @[Cat.scala 29:58] + buf_rspage_set[0] <= _T_2886 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[1] <= _T_2977 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[2] <= _T_3068 @[el2_lsu_bus_buffer.scala 469:18] + buf_rspage_set[3] <= _T_3159 @[el2_lsu_bus_buffer.scala 469:18] + node _T_3160 = bits(buf_rspage_set[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3161 = bits(buf_rspage[0], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3162 = or(_T_3160, _T_3161) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3163 = bits(buf_rspage_set[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3164 = bits(buf_rspage[0], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3165 = or(_T_3163, _T_3164) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3166 = bits(buf_rspage_set[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3167 = bits(buf_rspage[0], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3168 = or(_T_3166, _T_3167) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3169 = bits(buf_rspage_set[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3170 = bits(buf_rspage[0], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3171 = or(_T_3169, _T_3170) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3172 = cat(_T_3171, _T_3168) @[Cat.scala 29:58] + node _T_3173 = cat(_T_3172, _T_3165) @[Cat.scala 29:58] + node _T_3174 = cat(_T_3173, _T_3162) @[Cat.scala 29:58] + node _T_3175 = bits(buf_rspage_set[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3176 = bits(buf_rspage[1], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3177 = or(_T_3175, _T_3176) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3178 = bits(buf_rspage_set[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3179 = bits(buf_rspage[1], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3180 = or(_T_3178, _T_3179) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3181 = bits(buf_rspage_set[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3182 = bits(buf_rspage[1], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3183 = or(_T_3181, _T_3182) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3184 = bits(buf_rspage_set[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3185 = bits(buf_rspage[1], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3186 = or(_T_3184, _T_3185) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3187 = cat(_T_3186, _T_3183) @[Cat.scala 29:58] + node _T_3188 = cat(_T_3187, _T_3180) @[Cat.scala 29:58] + node _T_3189 = cat(_T_3188, _T_3177) @[Cat.scala 29:58] + node _T_3190 = bits(buf_rspage_set[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3191 = bits(buf_rspage[2], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3192 = or(_T_3190, _T_3191) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3193 = bits(buf_rspage_set[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3194 = bits(buf_rspage[2], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3195 = or(_T_3193, _T_3194) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3196 = bits(buf_rspage_set[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3197 = bits(buf_rspage[2], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3198 = or(_T_3196, _T_3197) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3199 = bits(buf_rspage_set[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3200 = bits(buf_rspage[2], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3201 = or(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3202 = cat(_T_3201, _T_3198) @[Cat.scala 29:58] + node _T_3203 = cat(_T_3202, _T_3195) @[Cat.scala 29:58] + node _T_3204 = cat(_T_3203, _T_3192) @[Cat.scala 29:58] + node _T_3205 = bits(buf_rspage_set[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3206 = bits(buf_rspage[3], 0, 0) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3207 = or(_T_3205, _T_3206) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3208 = bits(buf_rspage_set[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3209 = bits(buf_rspage[3], 1, 1) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3210 = or(_T_3208, _T_3209) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3211 = bits(buf_rspage_set[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3212 = bits(buf_rspage[3], 2, 2) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3213 = or(_T_3211, _T_3212) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3214 = bits(buf_rspage_set[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:84] + node _T_3215 = bits(buf_rspage[3], 3, 3) @[el2_lsu_bus_buffer.scala 473:103] + node _T_3216 = or(_T_3214, _T_3215) @[el2_lsu_bus_buffer.scala 473:88] + node _T_3217 = cat(_T_3216, _T_3213) @[Cat.scala 29:58] + node _T_3218 = cat(_T_3217, _T_3210) @[Cat.scala 29:58] + node _T_3219 = cat(_T_3218, _T_3207) @[Cat.scala 29:58] + buf_rspage_in[0] <= _T_3174 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[1] <= _T_3189 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[2] <= _T_3204 @[el2_lsu_bus_buffer.scala 473:17] + buf_rspage_in[3] <= _T_3219 @[el2_lsu_bus_buffer.scala 473:17] + node _T_3220 = bits(buf_rspageQ[0], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3221 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3222 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3223 = or(_T_3221, _T_3222) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3224 = eq(_T_3223, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3225 = and(_T_3220, _T_3224) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3226 = bits(buf_rspageQ[0], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3227 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3228 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3229 = or(_T_3227, _T_3228) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3230 = eq(_T_3229, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3231 = and(_T_3226, _T_3230) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3232 = bits(buf_rspageQ[0], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3233 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3234 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3235 = or(_T_3233, _T_3234) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3236 = eq(_T_3235, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3237 = and(_T_3232, _T_3236) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3238 = bits(buf_rspageQ[0], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3239 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3240 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3241 = or(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3242 = eq(_T_3241, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3243 = and(_T_3238, _T_3242) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3244 = cat(_T_3243, _T_3237) @[Cat.scala 29:58] + node _T_3245 = cat(_T_3244, _T_3231) @[Cat.scala 29:58] + node _T_3246 = cat(_T_3245, _T_3225) @[Cat.scala 29:58] + node _T_3247 = bits(buf_rspageQ[1], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3248 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3249 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3250 = or(_T_3248, _T_3249) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3251 = eq(_T_3250, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3252 = and(_T_3247, _T_3251) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3253 = bits(buf_rspageQ[1], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3254 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3255 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3256 = or(_T_3254, _T_3255) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3257 = eq(_T_3256, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3258 = and(_T_3253, _T_3257) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3259 = bits(buf_rspageQ[1], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3260 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3261 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3262 = or(_T_3260, _T_3261) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3263 = eq(_T_3262, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3264 = and(_T_3259, _T_3263) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3265 = bits(buf_rspageQ[1], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3266 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3267 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3268 = or(_T_3266, _T_3267) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3269 = eq(_T_3268, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3270 = and(_T_3265, _T_3269) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3271 = cat(_T_3270, _T_3264) @[Cat.scala 29:58] + node _T_3272 = cat(_T_3271, _T_3258) @[Cat.scala 29:58] + node _T_3273 = cat(_T_3272, _T_3252) @[Cat.scala 29:58] + node _T_3274 = bits(buf_rspageQ[2], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3275 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3276 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3277 = or(_T_3275, _T_3276) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3278 = eq(_T_3277, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3279 = and(_T_3274, _T_3278) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3280 = bits(buf_rspageQ[2], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3281 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3282 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3283 = or(_T_3281, _T_3282) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3284 = eq(_T_3283, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3285 = and(_T_3280, _T_3284) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3286 = bits(buf_rspageQ[2], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3287 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3288 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3289 = or(_T_3287, _T_3288) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3290 = eq(_T_3289, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3291 = and(_T_3286, _T_3290) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3292 = bits(buf_rspageQ[2], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3293 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3294 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3295 = or(_T_3293, _T_3294) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3296 = eq(_T_3295, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3297 = and(_T_3292, _T_3296) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3298 = cat(_T_3297, _T_3291) @[Cat.scala 29:58] + node _T_3299 = cat(_T_3298, _T_3285) @[Cat.scala 29:58] + node _T_3300 = cat(_T_3299, _T_3279) @[Cat.scala 29:58] + node _T_3301 = bits(buf_rspageQ[3], 0, 0) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3302 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3303 = eq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3304 = or(_T_3302, _T_3303) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3305 = eq(_T_3304, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3306 = and(_T_3301, _T_3305) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3307 = bits(buf_rspageQ[3], 1, 1) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3308 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3309 = eq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3310 = or(_T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3311 = eq(_T_3310, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3312 = and(_T_3307, _T_3311) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3313 = bits(buf_rspageQ[3], 2, 2) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3314 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3315 = eq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3316 = or(_T_3314, _T_3315) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3317 = eq(_T_3316, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3318 = and(_T_3313, _T_3317) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3319 = bits(buf_rspageQ[3], 3, 3) @[el2_lsu_bus_buffer.scala 474:78] + node _T_3320 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 474:99] + node _T_3321 = eq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 474:125] + node _T_3322 = or(_T_3320, _T_3321) @[el2_lsu_bus_buffer.scala 474:110] + node _T_3323 = eq(_T_3322, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 474:84] + node _T_3324 = and(_T_3319, _T_3323) @[el2_lsu_bus_buffer.scala 474:82] + node _T_3325 = cat(_T_3324, _T_3318) @[Cat.scala 29:58] + node _T_3326 = cat(_T_3325, _T_3312) @[Cat.scala 29:58] + node _T_3327 = cat(_T_3326, _T_3306) @[Cat.scala 29:58] + buf_rspage[0] <= _T_3246 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[1] <= _T_3273 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[2] <= _T_3300 @[el2_lsu_bus_buffer.scala 474:14] + buf_rspage[3] <= _T_3327 @[el2_lsu_bus_buffer.scala 474:14] + node _T_3328 = eq(ibuf_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3329 = and(ibuf_drain_vld, _T_3328) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3330 = eq(ibuf_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3331 = and(ibuf_drain_vld, _T_3330) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3332 = eq(ibuf_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3333 = and(ibuf_drain_vld, _T_3332) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3334 = eq(ibuf_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 479:75] + node _T_3335 = and(ibuf_drain_vld, _T_3334) @[el2_lsu_bus_buffer.scala 479:63] + node _T_3336 = cat(_T_3335, _T_3333) @[Cat.scala 29:58] + node _T_3337 = cat(_T_3336, _T_3331) @[Cat.scala 29:58] + node _T_3338 = cat(_T_3337, _T_3329) @[Cat.scala 29:58] + ibuf_drainvec_vld <= _T_3338 @[el2_lsu_bus_buffer.scala 479:21] + node _T_3339 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3340 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3341 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3342 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3343 = and(_T_3341, _T_3342) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3344 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3345 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3346 = mux(_T_3343, _T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3347 = mux(_T_3339, _T_3340, _T_3346) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3348 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3349 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3350 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3351 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3352 = and(_T_3350, _T_3351) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3353 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3354 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3355 = mux(_T_3352, _T_3353, _T_3354) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3356 = mux(_T_3348, _T_3349, _T_3355) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3357 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3358 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3359 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3360 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3361 = and(_T_3359, _T_3360) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3362 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3363 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3364 = mux(_T_3361, _T_3362, _T_3363) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3365 = mux(_T_3357, _T_3358, _T_3364) @[el2_lsu_bus_buffer.scala 480:46] + node _T_3366 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 480:64] + node _T_3367 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 480:84] + node _T_3368 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 481:18] + node _T_3369 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 481:46] + node _T_3370 = and(_T_3368, _T_3369) @[el2_lsu_bus_buffer.scala 481:35] + node _T_3371 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:71] + node _T_3372 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 481:94] + node _T_3373 = mux(_T_3370, _T_3371, _T_3372) @[el2_lsu_bus_buffer.scala 481:8] + node _T_3374 = mux(_T_3366, _T_3367, _T_3373) @[el2_lsu_bus_buffer.scala 480:46] + buf_byteen_in[0] <= _T_3347 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[2] <= _T_3365 @[el2_lsu_bus_buffer.scala 480:17] + buf_byteen_in[3] <= _T_3374 @[el2_lsu_bus_buffer.scala 480:17] + node _T_3375 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3376 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3377 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3378 = and(_T_3376, _T_3377) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3379 = mux(_T_3378, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3380 = mux(_T_3375, ibuf_addr, _T_3379) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3381 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3382 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3383 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3384 = and(_T_3382, _T_3383) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3385 = mux(_T_3384, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3386 = mux(_T_3381, ibuf_addr, _T_3385) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3387 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3388 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3389 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3390 = and(_T_3388, _T_3389) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3391 = mux(_T_3390, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3392 = mux(_T_3387, ibuf_addr, _T_3391) @[el2_lsu_bus_buffer.scala 482:44] + node _T_3393 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 482:62] + node _T_3394 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 482:91] + node _T_3395 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 482:119] + node _T_3396 = and(_T_3394, _T_3395) @[el2_lsu_bus_buffer.scala 482:108] + node _T_3397 = mux(_T_3396, io.end_addr_r, io.lsu_addr_r) @[el2_lsu_bus_buffer.scala 482:81] + node _T_3398 = mux(_T_3393, ibuf_addr, _T_3397) @[el2_lsu_bus_buffer.scala 482:44] + buf_addr_in[0] <= _T_3380 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[2] <= _T_3392 @[el2_lsu_bus_buffer.scala 482:15] + buf_addr_in[3] <= _T_3398 @[el2_lsu_bus_buffer.scala 482:15] + node _T_3399 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3400 = mux(_T_3399, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3401 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3402 = mux(_T_3401, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3403 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3404 = mux(_T_3403, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3405 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 483:63] + node _T_3406 = mux(_T_3405, ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 483:45] + node _T_3407 = cat(_T_3406, _T_3404) @[Cat.scala 29:58] + node _T_3408 = cat(_T_3407, _T_3402) @[Cat.scala 29:58] + node _T_3409 = cat(_T_3408, _T_3400) @[Cat.scala 29:58] + buf_dual_in <= _T_3409 @[el2_lsu_bus_buffer.scala 483:15] + node _T_3410 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3411 = mux(_T_3410, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3412 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3413 = mux(_T_3412, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3414 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3415 = mux(_T_3414, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3416 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 484:65] + node _T_3417 = mux(_T_3416, ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 484:47] + node _T_3418 = cat(_T_3417, _T_3415) @[Cat.scala 29:58] + node _T_3419 = cat(_T_3418, _T_3413) @[Cat.scala 29:58] + node _T_3420 = cat(_T_3419, _T_3411) @[Cat.scala 29:58] + buf_samedw_in <= _T_3420 @[el2_lsu_bus_buffer.scala 484:17] + node _T_3421 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3422 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3423 = mux(_T_3421, _T_3422, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3424 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3425 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3426 = mux(_T_3424, _T_3425, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3427 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3428 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3429 = mux(_T_3427, _T_3428, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3430 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 485:66] + node _T_3431 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 485:84] + node _T_3432 = mux(_T_3430, _T_3431, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 485:48] + node _T_3433 = cat(_T_3432, _T_3429) @[Cat.scala 29:58] + node _T_3434 = cat(_T_3433, _T_3426) @[Cat.scala 29:58] + node _T_3435 = cat(_T_3434, _T_3423) @[Cat.scala 29:58] + buf_nomerge_in <= _T_3435 @[el2_lsu_bus_buffer.scala 485:18] + node _T_3436 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3437 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3438 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3439 = and(_T_3437, _T_3438) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3440 = mux(_T_3436, ibuf_dual, _T_3439) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3441 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3442 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3443 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3444 = and(_T_3442, _T_3443) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3445 = mux(_T_3441, ibuf_dual, _T_3444) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3446 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3447 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3448 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3450 = mux(_T_3446, ibuf_dual, _T_3449) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3451 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 486:65] + node _T_3452 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 486:90] + node _T_3453 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 486:118] + node _T_3454 = and(_T_3452, _T_3453) @[el2_lsu_bus_buffer.scala 486:107] + node _T_3455 = mux(_T_3451, ibuf_dual, _T_3454) @[el2_lsu_bus_buffer.scala 486:47] + node _T_3456 = cat(_T_3455, _T_3450) @[Cat.scala 29:58] + node _T_3457 = cat(_T_3456, _T_3445) @[Cat.scala 29:58] + node _T_3458 = cat(_T_3457, _T_3440) @[Cat.scala 29:58] + buf_dualhi_in <= _T_3458 @[el2_lsu_bus_buffer.scala 486:17] + node _T_3459 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3460 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3461 = eq(WrPtr1_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3462 = and(_T_3460, _T_3461) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3463 = mux(_T_3462, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3464 = mux(_T_3459, ibuf_dualtag, _T_3463) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3465 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3466 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3467 = eq(WrPtr1_r, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3468 = and(_T_3466, _T_3467) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3469 = mux(_T_3468, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3470 = mux(_T_3465, ibuf_dualtag, _T_3469) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3471 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3472 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3473 = eq(WrPtr1_r, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3474 = and(_T_3472, _T_3473) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3475 = mux(_T_3474, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3476 = mux(_T_3471, ibuf_dualtag, _T_3475) @[el2_lsu_bus_buffer.scala 487:47] + node _T_3477 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 487:65] + node _T_3478 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 487:97] + node _T_3479 = eq(WrPtr1_r, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 487:125] + node _T_3480 = and(_T_3478, _T_3479) @[el2_lsu_bus_buffer.scala 487:114] + node _T_3481 = mux(_T_3480, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 487:87] + node _T_3482 = mux(_T_3477, ibuf_dualtag, _T_3481) @[el2_lsu_bus_buffer.scala 487:47] + buf_dualtag_in[0] <= _T_3464 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[1] <= _T_3470 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[2] <= _T_3476 @[el2_lsu_bus_buffer.scala 487:18] + buf_dualtag_in[3] <= _T_3482 @[el2_lsu_bus_buffer.scala 487:18] + node _T_3483 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3484 = mux(_T_3483, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3485 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3486 = mux(_T_3485, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3487 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3488 = mux(_T_3487, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3489 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 488:69] + node _T_3490 = mux(_T_3489, ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 488:51] + node _T_3491 = cat(_T_3490, _T_3488) @[Cat.scala 29:58] + node _T_3492 = cat(_T_3491, _T_3486) @[Cat.scala 29:58] + node _T_3493 = cat(_T_3492, _T_3484) @[Cat.scala 29:58] + buf_sideeffect_in <= _T_3493 @[el2_lsu_bus_buffer.scala 488:21] + node _T_3494 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3495 = mux(_T_3494, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3496 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3497 = mux(_T_3496, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3498 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3499 = mux(_T_3498, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3500 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 489:65] + node _T_3501 = mux(_T_3500, ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 489:47] + node _T_3502 = cat(_T_3501, _T_3499) @[Cat.scala 29:58] + node _T_3503 = cat(_T_3502, _T_3497) @[Cat.scala 29:58] + node _T_3504 = cat(_T_3503, _T_3495) @[Cat.scala 29:58] + buf_unsign_in <= _T_3504 @[el2_lsu_bus_buffer.scala 489:17] + node _T_3505 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3506 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3507 = mux(_T_3505, ibuf_sz, _T_3506) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3508 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3509 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3510 = mux(_T_3508, ibuf_sz, _T_3509) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3511 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3512 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3513 = mux(_T_3511, ibuf_sz, _T_3512) @[el2_lsu_bus_buffer.scala 490:42] + node _T_3514 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 490:60] + node _T_3515 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] + node _T_3516 = mux(_T_3514, ibuf_sz, _T_3515) @[el2_lsu_bus_buffer.scala 490:42] + buf_sz_in[0] <= _T_3507 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[1] <= _T_3510 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[2] <= _T_3513 @[el2_lsu_bus_buffer.scala 490:13] + buf_sz_in[3] <= _T_3516 @[el2_lsu_bus_buffer.scala 490:13] + node _T_3517 = bits(ibuf_drainvec_vld, 0, 0) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3518 = mux(_T_3517, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3519 = bits(ibuf_drainvec_vld, 1, 1) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3520 = mux(_T_3519, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3521 = bits(ibuf_drainvec_vld, 2, 2) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3522 = mux(_T_3521, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3523 = bits(ibuf_drainvec_vld, 3, 3) @[el2_lsu_bus_buffer.scala 491:64] + node _T_3524 = mux(_T_3523, ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 491:46] + node _T_3525 = cat(_T_3524, _T_3522) @[Cat.scala 29:58] + node _T_3526 = cat(_T_3525, _T_3520) @[Cat.scala 29:58] + node _T_3527 = cat(_T_3526, _T_3518) @[Cat.scala 29:58] + buf_write_in <= _T_3527 @[el2_lsu_bus_buffer.scala 491:16] + node _T_3528 = eq(UInt<3>("h00"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3528 : @[Conditional.scala 40:58] + node _T_3529 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3530 = mux(_T_3529, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[0] <= _T_3530 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3531 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3532 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3533 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3534 = and(_T_3532, _T_3533) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3535 = eq(UInt<1>("h00"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3536 = and(_T_3534, _T_3535) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3538 = eq(UInt<1>("h00"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3540 = or(_T_3536, _T_3539) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3541 = and(_T_3531, _T_3540) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3542 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3543 = and(ibuf_drain_vld, _T_3542) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3544 = or(_T_3541, _T_3543) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[0] <= _T_3544 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3545 = eq(UInt<1>("h00"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3546 = and(ibuf_drain_vld, _T_3545) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3547 = bits(_T_3546, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3548 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3549 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3550 = mux(_T_3547, _T_3548, _T_3549) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[0] <= _T_3550 @[el2_lsu_bus_buffer.scala 500:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_3155 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3155 : @[Conditional.scala 39:67] - node _T_3156 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3157 = mux(_T_3156, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[0] <= _T_3157 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3158 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[0] <= _T_3158 @[el2_lsu_bus_buffer.scala 624:31] + node _T_3551 = eq(UInt<3>("h01"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3551 : @[Conditional.scala 39:67] + node _T_3552 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3553 = mux(_T_3552, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[0] <= _T_3553 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3554 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[0] <= _T_3554 @[el2_lsu_bus_buffer.scala 504:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3159 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3159 : @[Conditional.scala 39:67] - node _T_3160 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3161 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3162 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3163 = and(_T_3161, _T_3162) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3164 = mux(_T_3163, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3165 = mux(_T_3160, UInt<3>("h00"), _T_3164) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[0] <= _T_3165 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3166 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3167 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3168 = and(obuf_merge, _T_3167) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3169 = or(_T_3166, _T_3168) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3170 = and(_T_3169, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3171 = and(_T_3170, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[0] <= _T_3171 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3172 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3173 = or(_T_3172, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[0] <= _T_3173 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3174 = eq(buf_write[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3175 = and(buf_state_en[0], _T_3174) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3176 = and(_T_3175, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3177 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3178 = and(_T_3176, _T_3177) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[0] <= _T_3178 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3179 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[0] <= _T_3179 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3180 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3181 = and(_T_3180, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3182 = and(_T_3181, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[0] <= _T_3182 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3183 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3184 = and(_T_3183, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3185 = and(_T_3184, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[0] <= _T_3185 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3186 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3187 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3188 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3189 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3190 = mux(_T_3187, _T_3188, _T_3189) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3191 = mux(buf_error_en[0], _T_3186, _T_3190) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[0] <= _T_3191 @[el2_lsu_bus_buffer.scala 636:37] + node _T_3555 = eq(UInt<3>("h02"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3555 : @[Conditional.scala 39:67] + node _T_3556 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3557 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3558 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3560 = mux(_T_3559, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3561 = mux(_T_3556, UInt<3>("h00"), _T_3560) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[0] <= _T_3561 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3562 = eq(obuf_tag0, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3563 = eq(obuf_tag1, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3564 = and(obuf_merge, _T_3563) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3565 = or(_T_3562, _T_3564) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3566 = and(_T_3565, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3567 = and(_T_3566, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[0] <= _T_3567 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[0] <= buf_cmd_state_bus_en[0] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3568 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3569 = or(_T_3568, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[0] <= _T_3569 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3570 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3571 = eq(_T_3570, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3572 = and(buf_state_en[0], _T_3571) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3573 = and(_T_3572, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3574 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3575 = and(_T_3573, _T_3574) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[0] <= _T_3575 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3576 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[0] <= _T_3576 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3577 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3578 = and(_T_3577, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3579 = and(_T_3578, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[0] <= _T_3579 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3580 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3581 = and(_T_3580, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3582 = and(_T_3581, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[0] <= _T_3582 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3583 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3584 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3585 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3586 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3587 = mux(_T_3584, _T_3585, _T_3586) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3588 = mux(buf_error_en[0], _T_3583, _T_3587) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[0] <= _T_3588 @[el2_lsu_bus_buffer.scala 516:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3192 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3192 : @[Conditional.scala 39:67] - node _T_3193 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3194 = not(_T_3193) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3195 = and(buf_write[0], _T_3194) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3196 = or(io.dec_tlu_force_halt, _T_3195) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3197 = bits(_T_3196, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3198 = not(buf_samedw[0]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3199 = and(buf_dual[0], _T_3198) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3200 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3201 = and(_T_3199, _T_3200) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3202 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3203 = and(_T_3201, _T_3202) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3204 = or(buf_ldfwd[0], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3205 = not(buf_samedw[0]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3206 = and(buf_dual[0], _T_3205) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3207 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3208 = and(_T_3206, _T_3207) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3209 = and(_T_3208, buf_ldfwd[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3210 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3211 = and(_T_3209, _T_3210) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3212 = and(_T_3211, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3213 = or(_T_3204, _T_3212) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3214 = mux(_T_3213, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3215 = mux(_T_3203, UInt<3>("h04"), _T_3214) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3216 = mux(_T_3197, UInt<3>("h00"), _T_3215) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[0] <= _T_3216 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3217 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3218 = and(bus_rsp_write, _T_3217) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3219 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3220 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3221 = and(buf_ldfwd[0], _T_3220) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3222 = or(_T_3219, _T_3221) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3223 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3224 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3225 = and(_T_3223, _T_3224) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3226 = and(_T_3225, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3227 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3228 = and(_T_3226, _T_3227) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3229 = or(_T_3222, _T_3228) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3230 = and(bus_rsp_read, _T_3229) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3231 = or(_T_3218, _T_3230) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[0] <= _T_3231 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3232 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3233 = or(_T_3232, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[0] <= _T_3233 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3234 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3235 = and(_T_3234, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[0] <= _T_3235 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3236 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3237 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3238 = and(bus_rsp_read_error, _T_3237) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3239 = and(bus_rsp_read_error, buf_ldfwd[0]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3240 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3241 = and(_T_3239, _T_3240) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3242 = or(_T_3238, _T_3241) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3243 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3244 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3245 = and(_T_3243, _T_3244) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3246 = or(_T_3242, _T_3245) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3247 = and(_T_3236, _T_3246) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[0] <= _T_3247 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3248 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3249 = and(buf_state_en[0], _T_3248) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3250 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3251 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3252 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3253 = mux(_T_3250, _T_3251, _T_3252) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3254 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3255 = mux(_T_3249, _T_3253, _T_3254) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[0] <= _T_3255 @[el2_lsu_bus_buffer.scala 652:37] + node _T_3589 = eq(UInt<3>("h03"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3589 : @[Conditional.scala 39:67] + node _T_3590 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3591 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3592 = eq(_T_3591, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3593 = and(_T_3590, _T_3592) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3594 = or(io.dec_tlu_force_halt, _T_3593) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3595 = bits(_T_3594, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3596 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3597 = and(buf_dual[0], _T_3596) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3598 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3599 = eq(_T_3598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3600 = and(_T_3597, _T_3599) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3601 = neq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3602 = and(_T_3600, _T_3601) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3603 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3604 = or(_T_3603, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3605 = eq(buf_samedw[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3606 = and(buf_dual[0], _T_3605) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3607 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3608 = eq(_T_3607, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3609 = and(_T_3606, _T_3608) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3610 = eq(buf_dualtag[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3611 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3612 = eq(buf_dualtag[0], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3613 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3614 = eq(buf_dualtag[0], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3615 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3616 = eq(buf_dualtag[0], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3617 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3618 = mux(_T_3610, _T_3611, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3619 = mux(_T_3612, _T_3613, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3620 = mux(_T_3614, _T_3615, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3621 = mux(_T_3616, _T_3617, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3622 = or(_T_3618, _T_3619) @[Mux.scala 27:72] + node _T_3623 = or(_T_3622, _T_3620) @[Mux.scala 27:72] + node _T_3624 = or(_T_3623, _T_3621) @[Mux.scala 27:72] + wire _T_3625 : UInt<1> @[Mux.scala 27:72] + _T_3625 <= _T_3624 @[Mux.scala 27:72] + node _T_3626 = and(_T_3609, _T_3625) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3627 = eq(buf_state[buf_dualtag[0]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3628 = and(_T_3626, _T_3627) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3629 = and(_T_3628, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3630 = or(_T_3604, _T_3629) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3631 = mux(_T_3630, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3632 = mux(_T_3602, UInt<3>("h04"), _T_3631) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3633 = mux(_T_3595, UInt<3>("h00"), _T_3632) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[0] <= _T_3633 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3634 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3635 = and(bus_rsp_write, _T_3634) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3636 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3637 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3638 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3639 = and(_T_3637, _T_3638) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3640 = or(_T_3636, _T_3639) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3641 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3642 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3643 = not(_T_3642) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3644 = and(_T_3641, _T_3643) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3645 = and(_T_3644, buf_samedw[0]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3646 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3647 = and(_T_3645, _T_3646) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3648 = or(_T_3640, _T_3647) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3649 = and(bus_rsp_read, _T_3648) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3650 = or(_T_3635, _T_3649) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[0] <= _T_3650 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[0] <= buf_resp_state_bus_en[0] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3651 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3652 = or(_T_3651, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[0] <= _T_3652 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3653 = and(buf_state_bus_en[0], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3654 = and(_T_3653, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[0] <= _T_3654 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3655 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3656 = eq(bus_rsp_read_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3657 = and(bus_rsp_read_error, _T_3656) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3658 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3659 = and(bus_rsp_read_error, _T_3658) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3660 = eq(bus_rsp_read_tag, buf_ldfwdtag[0]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3662 = or(_T_3657, _T_3661) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3663 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3664 = eq(bus_rsp_write_tag, UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3665 = and(_T_3663, _T_3664) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3666 = or(_T_3662, _T_3665) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3667 = and(_T_3655, _T_3666) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[0] <= _T_3667 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3668 = eq(buf_error_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3669 = and(buf_state_en[0], _T_3668) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3670 = bits(buf_addr[0], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3671 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3672 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3673 = mux(_T_3670, _T_3671, _T_3672) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3674 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3675 = mux(_T_3669, _T_3673, _T_3674) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[0] <= _T_3675 @[el2_lsu_bus_buffer.scala 532:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3256 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3256 : @[Conditional.scala 39:67] - node _T_3257 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3258 = or(buf_ldfwd[0], buf_ldfwd[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3259 = or(_T_3258, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3260 = mux(_T_3259, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3261 = mux(_T_3257, UInt<3>("h00"), _T_3260) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[0] <= _T_3261 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3262 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3263 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3264 = and(buf_ldfwd[buf_dualtag[0]], _T_3263) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3265 = or(_T_3262, _T_3264) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3266 = and(bus_rsp_read, _T_3265) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[0] <= _T_3266 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3267 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3268 = or(_T_3267, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[0] <= _T_3268 @[el2_lsu_bus_buffer.scala 658:34] + node _T_3676 = eq(UInt<3>("h04"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3676 : @[Conditional.scala 39:67] + node _T_3677 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3678 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3679 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3680 = bits(_T_3679, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3682 = or(_T_3681, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3683 = mux(_T_3682, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3684 = mux(_T_3677, UInt<3>("h00"), _T_3683) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[0] <= _T_3684 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3685 = eq(bus_rsp_read_tag, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3686 = dshr(buf_ldfwd, buf_dualtag[0]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3687 = bits(_T_3686, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3688 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[0]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3689 = and(_T_3687, _T_3688) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3690 = or(_T_3685, _T_3689) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3691 = and(bus_rsp_read, _T_3690) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[0] <= _T_3691 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3692 = and(buf_state_bus_en[0], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3693 = or(_T_3692, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[0] <= _T_3693 @[el2_lsu_bus_buffer.scala 538:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3269 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3269 : @[Conditional.scala 39:67] - node _T_3270 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3271 = mux(_T_3270, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[0] <= _T_3271 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3272 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3273 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3274 = and(buf_dual[0], _T_3273) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3275 = or(_T_3272, _T_3274) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3276 = or(_T_3275, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[0] <= _T_3276 @[el2_lsu_bus_buffer.scala 662:31] + node _T_3694 = eq(UInt<3>("h05"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3694 : @[Conditional.scala 39:67] + node _T_3695 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3696 = mux(_T_3695, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[0] <= _T_3696 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3697 = eq(RspPtr, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3698 = eq(buf_dualtag[0], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3699 = and(buf_dual[0], _T_3698) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3700 = or(_T_3697, _T_3699) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3701 = or(_T_3700, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[0] <= _T_3701 @[el2_lsu_bus_buffer.scala 542:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3277 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] - when _T_3277 : @[Conditional.scala 39:67] - buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 669:31] + node _T_3702 = eq(UInt<3>("h06"), buf_state[0]) @[Conditional.scala 37:30] + when _T_3702 : @[Conditional.scala 39:67] + buf_nxtstate[0] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[0] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[0] <= buf_state_en[0] @[el2_lsu_bus_buffer.scala 549:25] skip @[Conditional.scala 39:67] - reg _T_3278 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3278 <= buf_byteen_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[0] <= _T_3278 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3279 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[0] : @[Reg.scala 28:19] - _T_3279 <= buf_data_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[0] <= _T_3279 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3280 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[0] : @[Reg.scala 28:19] - _T_3280 <= buf_nxtstate[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[0] <= _T_3280 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3281 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3281 <= buf_dualtag_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[0] <= _T_3281 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3282 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3282 <= buf_dual_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[0] <= _T_3282 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3283 <= buf_samedw_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[0] <= _T_3283 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3284 <= buf_nomerge_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[0] <= _T_3284 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3285 <= buf_dualhi_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[0] <= _T_3285 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3286 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3286 <= buf_sideeffect_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[0] <= _T_3286 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3287 <= buf_unsign_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[0] <= _T_3287 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3288 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3288 <= buf_write_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write[0] <= _T_3288 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3289 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3289 <= buf_sz_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[0] <= _T_3289 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3290 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[0] : @[Reg.scala 28:19] - _T_3290 <= buf_addr_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[0] <= _T_3290 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3291 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[0] : @[Reg.scala 28:19] - _T_3291 <= buf_ldfwd_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[0] <= _T_3291 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3292 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[0] : @[Reg.scala 28:19] - _T_3292 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwdtag[0] <= _T_3292 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3293 = not(buf_rst[0]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3294 = or(buf_error_en[0], buf_rst[0]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3295 = bits(_T_3294, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3296 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3295 : @[Reg.scala 28:19] - _T_3296 <= _T_3293 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_error[0] <= _T_3296 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3297 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3297[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3298 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3297)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[0] <= buf_age_in[0][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[1] <= buf_age_in[0][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[2] <= buf_age_in[0][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3298[3] <= buf_age_in[0][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[0][0] <= _T_3298[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][1] <= _T_3298[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][2] <= _T_3298[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[0][3] <= _T_3298[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3299 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3299[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3300 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3299)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[0] <= buf_rspage_in[0][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[1] <= buf_rspage_in[0][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[2] <= buf_rspage_in[0][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3300[3] <= buf_rspage_in[0][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[0][0] <= _T_3300[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][1] <= _T_3300[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][2] <= _T_3300[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[0][3] <= _T_3300[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3301 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3302 = and(ibuf_drain_vld, _T_3301) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[1] <= _T_3302 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3303 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3304 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3305 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3306 = and(_T_3304, _T_3305) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3307 = bits(_T_3306, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3308 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3309 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3310 = mux(_T_3307, _T_3308, _T_3309) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3311 = mux(ibuf_drainvec_vld[1], _T_3303, _T_3310) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[1] <= _T_3311 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3312 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3313 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3314 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3315 = and(_T_3313, _T_3314) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3316 = bits(_T_3315, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3317 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3318 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3319 = mux(_T_3316, _T_3317, _T_3318) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3320 = mux(ibuf_drainvec_vld[1], _T_3312, _T_3319) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[1] <= _T_3320 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3321 = mux(ibuf_drainvec_vld[1], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[1] <= _T_3321 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3322 = mux(ibuf_drainvec_vld[1], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[1] <= _T_3322 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3323 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3324 = mux(ibuf_drainvec_vld[1], _T_3323, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[1] <= _T_3324 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3325 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3326 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3327 = and(_T_3325, _T_3326) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3328 = mux(ibuf_drainvec_vld[1], ibuf_dual, _T_3327) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[1] <= _T_3328 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3329 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3330 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3331 = and(_T_3329, _T_3330) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3332 = bits(_T_3331, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3333 = mux(_T_3332, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3334 = mux(ibuf_drainvec_vld[1], ibuf_dualtag, _T_3333) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[1] <= _T_3334 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3335 = mux(ibuf_drainvec_vld[1], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[1] <= _T_3335 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3336 = mux(ibuf_drainvec_vld[1], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[1] <= _T_3336 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3337 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3338 = mux(ibuf_drainvec_vld[1], ibuf_sz, _T_3337) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[1] <= _T_3338 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3339 = mux(ibuf_drainvec_vld[1], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[1] <= _T_3339 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3340 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3340 : @[Conditional.scala 40:58] - node _T_3341 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3342 = mux(_T_3341, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[1] <= _T_3342 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3343 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3344 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3345 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3346 = and(_T_3344, _T_3345) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3347 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3348 = and(_T_3346, _T_3347) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3349 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3350 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3351 = and(_T_3349, _T_3350) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3352 = or(_T_3348, _T_3351) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3353 = and(_T_3343, _T_3352) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3354 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3355 = and(ibuf_drain_vld, _T_3354) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3356 = or(_T_3353, _T_3355) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[1] <= _T_3356 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3357 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3358 = and(ibuf_drain_vld, _T_3357) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3359 = bits(_T_3358, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3360 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3361 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3362 = mux(_T_3359, _T_3360, _T_3361) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[1] <= _T_3362 @[el2_lsu_bus_buffer.scala 620:31] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_3363 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3363 : @[Conditional.scala 39:67] - node _T_3364 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3365 = mux(_T_3364, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[1] <= _T_3365 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3366 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[1] <= _T_3366 @[el2_lsu_bus_buffer.scala 624:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3367 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3367 : @[Conditional.scala 39:67] - node _T_3368 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3369 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3370 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3371 = and(_T_3369, _T_3370) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3372 = mux(_T_3371, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3373 = mux(_T_3368, UInt<3>("h00"), _T_3372) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[1] <= _T_3373 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3374 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3375 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3376 = and(obuf_merge, _T_3375) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3377 = or(_T_3374, _T_3376) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3378 = and(_T_3377, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3379 = and(_T_3378, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[1] <= _T_3379 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3380 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3381 = or(_T_3380, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[1] <= _T_3381 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3382 = eq(buf_write[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3383 = and(buf_state_en[1], _T_3382) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3384 = and(_T_3383, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3385 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3386 = and(_T_3384, _T_3385) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[1] <= _T_3386 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3387 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[1] <= _T_3387 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3388 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3389 = and(_T_3388, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3390 = and(_T_3389, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[1] <= _T_3390 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3391 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3392 = and(_T_3391, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3393 = and(_T_3392, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[1] <= _T_3393 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3394 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3395 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3396 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3397 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3398 = mux(_T_3395, _T_3396, _T_3397) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3399 = mux(buf_error_en[1], _T_3394, _T_3398) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[1] <= _T_3399 @[el2_lsu_bus_buffer.scala 636:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3400 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3400 : @[Conditional.scala 39:67] - node _T_3401 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3402 = not(_T_3401) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3403 = and(buf_write[1], _T_3402) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3404 = or(io.dec_tlu_force_halt, _T_3403) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3405 = bits(_T_3404, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3406 = not(buf_samedw[1]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3407 = and(buf_dual[1], _T_3406) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3408 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3409 = and(_T_3407, _T_3408) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3410 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3411 = and(_T_3409, _T_3410) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3412 = or(buf_ldfwd[1], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3413 = not(buf_samedw[1]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3414 = and(buf_dual[1], _T_3413) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3415 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3416 = and(_T_3414, _T_3415) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3417 = and(_T_3416, buf_ldfwd[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3418 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3419 = and(_T_3417, _T_3418) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3420 = and(_T_3419, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3421 = or(_T_3412, _T_3420) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3422 = mux(_T_3421, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3423 = mux(_T_3411, UInt<3>("h04"), _T_3422) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3424 = mux(_T_3405, UInt<3>("h00"), _T_3423) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[1] <= _T_3424 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3425 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3426 = and(bus_rsp_write, _T_3425) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3427 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3428 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3429 = and(buf_ldfwd[1], _T_3428) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3430 = or(_T_3427, _T_3429) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3431 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3432 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3433 = and(_T_3431, _T_3432) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3434 = and(_T_3433, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3435 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3436 = and(_T_3434, _T_3435) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3437 = or(_T_3430, _T_3436) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3438 = and(bus_rsp_read, _T_3437) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3439 = or(_T_3426, _T_3438) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[1] <= _T_3439 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3440 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3441 = or(_T_3440, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[1] <= _T_3441 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3442 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3443 = and(_T_3442, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[1] <= _T_3443 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3444 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3445 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3446 = and(bus_rsp_read_error, _T_3445) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3447 = and(bus_rsp_read_error, buf_ldfwd[1]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3448 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3449 = and(_T_3447, _T_3448) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3450 = or(_T_3446, _T_3449) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3451 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3452 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3453 = and(_T_3451, _T_3452) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3454 = or(_T_3450, _T_3453) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3455 = and(_T_3444, _T_3454) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[1] <= _T_3455 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3456 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3457 = and(buf_state_en[1], _T_3456) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3458 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3459 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3460 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3461 = mux(_T_3458, _T_3459, _T_3460) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3462 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3463 = mux(_T_3457, _T_3461, _T_3462) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[1] <= _T_3463 @[el2_lsu_bus_buffer.scala 652:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3464 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3464 : @[Conditional.scala 39:67] - node _T_3465 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3466 = or(buf_ldfwd[1], buf_ldfwd[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3467 = or(_T_3466, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3468 = mux(_T_3467, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3469 = mux(_T_3465, UInt<3>("h00"), _T_3468) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[1] <= _T_3469 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3470 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3471 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3472 = and(buf_ldfwd[buf_dualtag[1]], _T_3471) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3473 = or(_T_3470, _T_3472) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3474 = and(bus_rsp_read, _T_3473) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[1] <= _T_3474 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3475 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3476 = or(_T_3475, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[1] <= _T_3476 @[el2_lsu_bus_buffer.scala 658:34] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3477 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3477 : @[Conditional.scala 39:67] - node _T_3478 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3479 = mux(_T_3478, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[1] <= _T_3479 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3480 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3481 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3482 = and(buf_dual[1], _T_3481) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3483 = or(_T_3480, _T_3482) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3484 = or(_T_3483, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[1] <= _T_3484 @[el2_lsu_bus_buffer.scala 662:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3485 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] - when _T_3485 : @[Conditional.scala 39:67] - buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 669:31] - skip @[Conditional.scala 39:67] - reg _T_3486 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3486 <= buf_byteen_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[1] <= _T_3486 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3487 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[1] : @[Reg.scala 28:19] - _T_3487 <= buf_data_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[1] <= _T_3487 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3488 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[1] : @[Reg.scala 28:19] - _T_3488 <= buf_nxtstate[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[1] <= _T_3488 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3489 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3489 <= buf_dualtag_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[1] <= _T_3489 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3490 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3490 <= buf_dual_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[1] <= _T_3490 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3491 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3491 <= buf_samedw_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[1] <= _T_3491 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3492 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3492 <= buf_nomerge_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[1] <= _T_3492 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3493 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3493 <= buf_dualhi_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[1] <= _T_3493 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3494 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3494 <= buf_sideeffect_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[1] <= _T_3494 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3495 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3495 <= buf_unsign_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[1] <= _T_3495 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3496 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3496 <= buf_write_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_write[1] <= _T_3496 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3497 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3497 <= buf_sz_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[1] <= _T_3497 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3498 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[1] : @[Reg.scala 28:19] - _T_3498 <= buf_addr_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[1] <= _T_3498 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3499 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[1] : @[Reg.scala 28:19] - _T_3499 <= buf_ldfwd_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[1] <= _T_3499 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3500 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[1] : @[Reg.scala 28:19] - _T_3500 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwdtag[1] <= _T_3500 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3501 = not(buf_rst[1]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3502 = or(buf_error_en[1], buf_rst[1]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3503 = bits(_T_3502, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3504 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3503 : @[Reg.scala 28:19] - _T_3504 <= _T_3501 @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_error[1] <= _T_3504 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3505 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3505[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3506 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3505)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[0] <= buf_age_in[1][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[1] <= buf_age_in[1][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[2] <= buf_age_in[1][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3506[3] <= buf_age_in[1][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[1][0] <= _T_3506[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][1] <= _T_3506[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][2] <= _T_3506[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[1][3] <= _T_3506[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3507 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3507[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3508 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3507)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[0] <= buf_rspage_in[1][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[1] <= buf_rspage_in[1][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[2] <= buf_rspage_in[1][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3508[3] <= buf_rspage_in[1][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[1][0] <= _T_3508[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][1] <= _T_3508[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][2] <= _T_3508[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[1][3] <= _T_3508[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3509 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3510 = and(ibuf_drain_vld, _T_3509) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[2] <= _T_3510 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3511 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3512 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3513 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3514 = and(_T_3512, _T_3513) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3515 = bits(_T_3514, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3516 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3517 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3518 = mux(_T_3515, _T_3516, _T_3517) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3519 = mux(ibuf_drainvec_vld[2], _T_3511, _T_3518) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[2] <= _T_3519 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3520 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3521 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3522 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3523 = and(_T_3521, _T_3522) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3524 = bits(_T_3523, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3525 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3526 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3527 = mux(_T_3524, _T_3525, _T_3526) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3528 = mux(ibuf_drainvec_vld[2], _T_3520, _T_3527) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[2] <= _T_3528 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3529 = mux(ibuf_drainvec_vld[2], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[2] <= _T_3529 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3530 = mux(ibuf_drainvec_vld[2], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[2] <= _T_3530 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3531 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3532 = mux(ibuf_drainvec_vld[2], _T_3531, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[2] <= _T_3532 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3533 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3534 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3535 = and(_T_3533, _T_3534) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3536 = mux(ibuf_drainvec_vld[2], ibuf_dual, _T_3535) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[2] <= _T_3536 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3537 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3538 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3539 = and(_T_3537, _T_3538) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3540 = bits(_T_3539, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3541 = mux(_T_3540, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3542 = mux(ibuf_drainvec_vld[2], ibuf_dualtag, _T_3541) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[2] <= _T_3542 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3543 = mux(ibuf_drainvec_vld[2], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[2] <= _T_3543 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3544 = mux(ibuf_drainvec_vld[2], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[2] <= _T_3544 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3545 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3546 = mux(ibuf_drainvec_vld[2], ibuf_sz, _T_3545) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[2] <= _T_3546 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3547 = mux(ibuf_drainvec_vld[2], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[2] <= _T_3547 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3548 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3548 : @[Conditional.scala 40:58] - node _T_3549 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3550 = mux(_T_3549, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[2] <= _T_3550 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3551 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3552 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3553 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3554 = and(_T_3552, _T_3553) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3555 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3556 = and(_T_3554, _T_3555) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3557 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3558 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3559 = and(_T_3557, _T_3558) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3560 = or(_T_3556, _T_3559) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3561 = and(_T_3551, _T_3560) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3562 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3563 = and(ibuf_drain_vld, _T_3562) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3564 = or(_T_3561, _T_3563) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[2] <= _T_3564 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3565 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3566 = and(ibuf_drain_vld, _T_3565) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3567 = bits(_T_3566, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3568 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3569 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3570 = mux(_T_3567, _T_3568, _T_3569) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[2] <= _T_3570 @[el2_lsu_bus_buffer.scala 620:31] - skip @[Conditional.scala 40:58] - else : @[Conditional.scala 39:67] - node _T_3571 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3571 : @[Conditional.scala 39:67] - node _T_3572 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3573 = mux(_T_3572, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[2] <= _T_3573 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3574 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[2] <= _T_3574 @[el2_lsu_bus_buffer.scala 624:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3575 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3575 : @[Conditional.scala 39:67] - node _T_3576 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3577 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3578 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3579 = and(_T_3577, _T_3578) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3580 = mux(_T_3579, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3581 = mux(_T_3576, UInt<3>("h00"), _T_3580) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[2] <= _T_3581 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3582 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3583 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3584 = and(obuf_merge, _T_3583) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3585 = or(_T_3582, _T_3584) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3586 = and(_T_3585, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3587 = and(_T_3586, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[2] <= _T_3587 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3588 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3589 = or(_T_3588, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[2] <= _T_3589 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3590 = eq(buf_write[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3591 = and(buf_state_en[2], _T_3590) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3592 = and(_T_3591, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3593 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3594 = and(_T_3592, _T_3593) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[2] <= _T_3594 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3595 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[2] <= _T_3595 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3596 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3597 = and(_T_3596, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3598 = and(_T_3597, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[2] <= _T_3598 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3599 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3600 = and(_T_3599, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3601 = and(_T_3600, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[2] <= _T_3601 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3602 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3603 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3604 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3605 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3606 = mux(_T_3603, _T_3604, _T_3605) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3607 = mux(buf_error_en[2], _T_3602, _T_3606) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[2] <= _T_3607 @[el2_lsu_bus_buffer.scala 636:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3608 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3608 : @[Conditional.scala 39:67] - node _T_3609 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3610 = not(_T_3609) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3611 = and(buf_write[2], _T_3610) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3612 = or(io.dec_tlu_force_halt, _T_3611) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3613 = bits(_T_3612, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3614 = not(buf_samedw[2]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3615 = and(buf_dual[2], _T_3614) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3616 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3617 = and(_T_3615, _T_3616) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3618 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3619 = and(_T_3617, _T_3618) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3620 = or(buf_ldfwd[2], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3621 = not(buf_samedw[2]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3622 = and(buf_dual[2], _T_3621) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3623 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3624 = and(_T_3622, _T_3623) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3625 = and(_T_3624, buf_ldfwd[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3626 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3627 = and(_T_3625, _T_3626) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3628 = and(_T_3627, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3629 = or(_T_3620, _T_3628) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3630 = mux(_T_3629, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3631 = mux(_T_3619, UInt<3>("h04"), _T_3630) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3632 = mux(_T_3613, UInt<3>("h00"), _T_3631) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[2] <= _T_3632 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3633 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3634 = and(bus_rsp_write, _T_3633) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3635 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3636 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3637 = and(buf_ldfwd[2], _T_3636) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3638 = or(_T_3635, _T_3637) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3639 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3640 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3641 = and(_T_3639, _T_3640) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3642 = and(_T_3641, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3643 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3644 = and(_T_3642, _T_3643) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3645 = or(_T_3638, _T_3644) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3646 = and(bus_rsp_read, _T_3645) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3647 = or(_T_3634, _T_3646) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[2] <= _T_3647 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3648 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3649 = or(_T_3648, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[2] <= _T_3649 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3650 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3651 = and(_T_3650, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[2] <= _T_3651 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3652 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3653 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3654 = and(bus_rsp_read_error, _T_3653) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3655 = and(bus_rsp_read_error, buf_ldfwd[2]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3656 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3657 = and(_T_3655, _T_3656) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3658 = or(_T_3654, _T_3657) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3659 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3660 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3661 = and(_T_3659, _T_3660) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3662 = or(_T_3658, _T_3661) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3663 = and(_T_3652, _T_3662) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[2] <= _T_3663 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3664 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3665 = and(buf_state_en[2], _T_3664) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3666 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3667 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3668 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3669 = mux(_T_3666, _T_3667, _T_3668) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3670 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3671 = mux(_T_3665, _T_3669, _T_3670) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[2] <= _T_3671 @[el2_lsu_bus_buffer.scala 652:37] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3672 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3672 : @[Conditional.scala 39:67] - node _T_3673 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3674 = or(buf_ldfwd[2], buf_ldfwd[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3675 = or(_T_3674, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3676 = mux(_T_3675, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3677 = mux(_T_3673, UInt<3>("h00"), _T_3676) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[2] <= _T_3677 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3678 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3679 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3680 = and(buf_ldfwd[buf_dualtag[2]], _T_3679) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3681 = or(_T_3678, _T_3680) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3682 = and(bus_rsp_read, _T_3681) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[2] <= _T_3682 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3683 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3684 = or(_T_3683, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[2] <= _T_3684 @[el2_lsu_bus_buffer.scala 658:34] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3685 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3685 : @[Conditional.scala 39:67] - node _T_3686 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3687 = mux(_T_3686, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[2] <= _T_3687 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3688 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3689 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3690 = and(buf_dual[2], _T_3689) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3691 = or(_T_3688, _T_3690) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3692 = or(_T_3691, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[2] <= _T_3692 @[el2_lsu_bus_buffer.scala 662:31] - skip @[Conditional.scala 39:67] - else : @[Conditional.scala 39:67] - node _T_3693 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] - when _T_3693 : @[Conditional.scala 39:67] - buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 669:31] - skip @[Conditional.scala 39:67] - reg _T_3694 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3694 <= buf_byteen_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_byteen[2] <= _T_3694 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3695 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[2] : @[Reg.scala 28:19] - _T_3695 <= buf_data_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_data[2] <= _T_3695 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3696 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[2] : @[Reg.scala 28:19] - _T_3696 <= buf_nxtstate[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_state[2] <= _T_3696 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3697 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3697 <= buf_dualtag_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualtag[2] <= _T_3697 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3698 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3698 <= buf_dual_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dual[2] <= _T_3698 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3699 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3699 <= buf_samedw_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_samedw[2] <= _T_3699 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3700 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3700 <= buf_nomerge_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_nomerge[2] <= _T_3700 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3701 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3701 <= buf_dualhi_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_dualhi[2] <= _T_3701 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3702 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3702 <= buf_sideeffect_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sideeffect[2] <= _T_3702 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3703 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3703 <= buf_unsign_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_unsign[2] <= _T_3703 @[el2_lsu_bus_buffer.scala 683:31] + node _T_3703 = bits(buf_state_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] reg _T_3704 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3704 <= buf_write_in[2] @[Reg.scala 28:23] + when _T_3703 : @[Reg.scala 28:19] + _T_3704 <= buf_nxtstate[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write[2] <= _T_3704 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3705 <= buf_sz_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_sz[2] <= _T_3705 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[2] : @[Reg.scala 28:19] - _T_3706 <= buf_addr_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_addr[2] <= _T_3706 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3707 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[2] : @[Reg.scala 28:19] - _T_3707 <= buf_ldfwd_in[2] @[Reg.scala 28:23] - skip @[Reg.scala 28:19] - buf_ldfwd[2] <= _T_3707 @[el2_lsu_bus_buffer.scala 687:31] + buf_state[0] <= _T_3704 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3705 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3705 <= buf_age_in_0 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[0] <= _T_3705 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3706 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3706 <= buf_rspage_in[0] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[0] <= _T_3706 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3707 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] reg _T_3708 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[2] : @[Reg.scala 28:19] - _T_3708 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + when _T_3707 : @[Reg.scala 28:19] + _T_3708 <= buf_dualtag_in[0] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[2] <= _T_3708 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3709 = not(buf_rst[2]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3710 = or(buf_error_en[2], buf_rst[2]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3711 = bits(_T_3710, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3712 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3711 : @[Reg.scala 28:19] - _T_3712 <= _T_3709 @[Reg.scala 28:23] + buf_dualtag[0] <= _T_3708 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3709 = bits(buf_dual_in, 0, 0) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3710 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3711 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3710 : @[Reg.scala 28:19] + _T_3711 <= _T_3709 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_error[2] <= _T_3712 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3713 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3713[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3714 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3713)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[0] <= buf_age_in[2][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[1] <= buf_age_in[2][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[2] <= buf_age_in[2][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3714[3] <= buf_age_in[2][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[2][0] <= _T_3714[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][1] <= _T_3714[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][2] <= _T_3714[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[2][3] <= _T_3714[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3715 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3715[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3716 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3715)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[0] <= buf_rspage_in[2][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[1] <= buf_rspage_in[2][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[2] <= buf_rspage_in[2][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3716[3] <= buf_rspage_in[2][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[2][0] <= _T_3716[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][1] <= _T_3716[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][2] <= _T_3716[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[2][3] <= _T_3716[3] @[el2_lsu_bus_buffer.scala 691:31] - buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 586:34] - buf_state_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 587:34] - buf_cmd_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 588:34] - buf_resp_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 589:34] - buf_state_bus_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 590:34] - buf_wr_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 591:34] - buf_data_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 592:34] - buf_data_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 593:34] - buf_error_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 594:34] - buf_rst[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 595:34] - buf_ldfwd_en[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 596:34] - buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 597:34] - buf_ldfwdtag_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 598:34] - node _T_3717 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 600:58] - node _T_3718 = and(ibuf_drain_vld, _T_3717) @[el2_lsu_bus_buffer.scala 600:53] - ibuf_drainvec_vld[3] <= _T_3718 @[el2_lsu_bus_buffer.scala 600:34] - node _T_3719 = bits(ibuf_byteen_out, 3, 0) @[el2_lsu_bus_buffer.scala 601:78] - node _T_3720 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 601:99] - node _T_3721 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 601:121] - node _T_3722 = and(_T_3720, _T_3721) @[el2_lsu_bus_buffer.scala 601:116] - node _T_3723 = bits(_T_3722, 0, 0) @[el2_lsu_bus_buffer.scala 601:142] - node _T_3724 = bits(ldst_byteen_hi_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:162] - node _T_3725 = bits(ldst_byteen_lo_r, 3, 0) @[el2_lsu_bus_buffer.scala 601:186] - node _T_3726 = mux(_T_3723, _T_3724, _T_3725) @[el2_lsu_bus_buffer.scala 601:88] - node _T_3727 = mux(ibuf_drainvec_vld[3], _T_3719, _T_3726) @[el2_lsu_bus_buffer.scala 601:40] - buf_byteen_in[3] <= _T_3727 @[el2_lsu_bus_buffer.scala 601:34] - node _T_3728 = bits(ibuf_addr, 31, 0) @[el2_lsu_bus_buffer.scala 602:72] - node _T_3729 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 602:94] - node _T_3730 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 602:116] - node _T_3731 = and(_T_3729, _T_3730) @[el2_lsu_bus_buffer.scala 602:111] - node _T_3732 = bits(_T_3731, 0, 0) @[el2_lsu_bus_buffer.scala 602:137] - node _T_3733 = bits(io.end_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:154] - node _T_3734 = bits(io.lsu_addr_r, 31, 0) @[el2_lsu_bus_buffer.scala 602:176] - node _T_3735 = mux(_T_3732, _T_3733, _T_3734) @[el2_lsu_bus_buffer.scala 602:83] - node _T_3736 = mux(ibuf_drainvec_vld[3], _T_3728, _T_3735) @[el2_lsu_bus_buffer.scala 602:40] - buf_addr_in[3] <= _T_3736 @[el2_lsu_bus_buffer.scala 602:34] - node _T_3737 = mux(ibuf_drainvec_vld[3], ibuf_dual, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 603:40] - buf_dual_in[3] <= _T_3737 @[el2_lsu_bus_buffer.scala 603:34] - node _T_3738 = mux(ibuf_drainvec_vld[3], ibuf_samedw, ldst_samedw_r) @[el2_lsu_bus_buffer.scala 604:40] - buf_samedw_in[3] <= _T_3738 @[el2_lsu_bus_buffer.scala 604:34] - node _T_3739 = or(ibuf_nomerge, ibuf_force_drain) @[el2_lsu_bus_buffer.scala 605:77] - node _T_3740 = mux(ibuf_drainvec_vld[3], _T_3739, io.no_dword_merge_r) @[el2_lsu_bus_buffer.scala 605:40] - buf_nomerge_in[3] <= _T_3740 @[el2_lsu_bus_buffer.scala 605:34] - node _T_3741 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 606:84] - node _T_3742 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 606:106] - node _T_3743 = and(_T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 606:101] - node _T_3744 = mux(ibuf_drainvec_vld[3], ibuf_dual, _T_3743) @[el2_lsu_bus_buffer.scala 606:40] - buf_dualhi_in[3] <= _T_3744 @[el2_lsu_bus_buffer.scala 606:34] - node _T_3745 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 607:91] - node _T_3746 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:113] - node _T_3747 = and(_T_3745, _T_3746) @[el2_lsu_bus_buffer.scala 607:108] - node _T_3748 = bits(_T_3747, 0, 0) @[el2_lsu_bus_buffer.scala 607:134] - node _T_3749 = mux(_T_3748, WrPtr0_r, WrPtr1_r) @[el2_lsu_bus_buffer.scala 607:80] - node _T_3750 = mux(ibuf_drainvec_vld[3], ibuf_dualtag, _T_3749) @[el2_lsu_bus_buffer.scala 607:40] - buf_dualtag_in[3] <= _T_3750 @[el2_lsu_bus_buffer.scala 607:34] - node _T_3751 = mux(ibuf_drainvec_vld[3], ibuf_sideeffect, io.is_sideeffects_r) @[el2_lsu_bus_buffer.scala 608:40] - buf_sideeffect_in[3] <= _T_3751 @[el2_lsu_bus_buffer.scala 608:34] - node _T_3752 = mux(ibuf_drainvec_vld[3], ibuf_unsign, io.lsu_pkt_r.unsign) @[el2_lsu_bus_buffer.scala 609:40] - buf_unsign_in[3] <= _T_3752 @[el2_lsu_bus_buffer.scala 609:34] - node _T_3753 = cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) @[Cat.scala 29:58] - node _T_3754 = mux(ibuf_drainvec_vld[3], ibuf_sz, _T_3753) @[el2_lsu_bus_buffer.scala 610:40] - buf_sz_in[3] <= _T_3754 @[el2_lsu_bus_buffer.scala 610:34] - node _T_3755 = mux(ibuf_drainvec_vld[3], ibuf_write, io.lsu_pkt_r.store) @[el2_lsu_bus_buffer.scala 611:40] - buf_write_in[3] <= _T_3755 @[el2_lsu_bus_buffer.scala 611:34] - node _T_3756 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3756 : @[Conditional.scala 40:58] - node _T_3757 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 616:62] - node _T_3758 = mux(_T_3757, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 616:37] - buf_nxtstate[3] <= _T_3758 @[el2_lsu_bus_buffer.scala 616:31] - node _T_3759 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 617:51] - node _T_3760 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:83] - node _T_3761 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:103] - node _T_3762 = and(_T_3760, _T_3761) @[el2_lsu_bus_buffer.scala 617:101] - node _T_3763 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 617:123] - node _T_3764 = and(_T_3762, _T_3763) @[el2_lsu_bus_buffer.scala 617:118] - node _T_3765 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 617:150] - node _T_3766 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 617:172] - node _T_3767 = and(_T_3765, _T_3766) @[el2_lsu_bus_buffer.scala 617:167] - node _T_3768 = or(_T_3764, _T_3767) @[el2_lsu_bus_buffer.scala 617:138] - node _T_3769 = and(_T_3759, _T_3768) @[el2_lsu_bus_buffer.scala 617:69] - node _T_3770 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 617:212] - node _T_3771 = and(ibuf_drain_vld, _T_3770) @[el2_lsu_bus_buffer.scala 617:207] - node _T_3772 = or(_T_3769, _T_3771) @[el2_lsu_bus_buffer.scala 617:189] - buf_state_en[3] <= _T_3772 @[el2_lsu_bus_buffer.scala 617:31] - buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 618:31] - buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 619:31] - node _T_3773 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 620:59] - node _T_3774 = and(ibuf_drain_vld, _T_3773) @[el2_lsu_bus_buffer.scala 620:54] - node _T_3775 = bits(_T_3774, 0, 0) @[el2_lsu_bus_buffer.scala 620:80] - node _T_3776 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 620:97] - node _T_3777 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 620:121] - node _T_3778 = mux(_T_3775, _T_3776, _T_3777) @[el2_lsu_bus_buffer.scala 620:37] - buf_data_in[3] <= _T_3778 @[el2_lsu_bus_buffer.scala 620:31] + buf_dual[0] <= _T_3711 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3712 = bits(buf_samedw_in, 0, 0) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3713 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3714 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3713 : @[Reg.scala 28:19] + _T_3714 <= _T_3712 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_samedw[0] <= _T_3714 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3715 = bits(buf_nomerge_in, 0, 0) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3716 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3717 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3716 : @[Reg.scala 28:19] + _T_3717 <= _T_3715 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_nomerge[0] <= _T_3717 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3718 = bits(buf_dualhi_in, 0, 0) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3719 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3720 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3719 : @[Reg.scala 28:19] + _T_3720 <= _T_3718 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[0] <= _T_3720 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3721 = eq(UInt<3>("h00"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3721 : @[Conditional.scala 40:58] + node _T_3722 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3723 = mux(_T_3722, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[1] <= _T_3723 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3724 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3725 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3726 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3727 = and(_T_3725, _T_3726) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3728 = eq(UInt<1>("h01"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3729 = and(_T_3727, _T_3728) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3730 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3731 = eq(UInt<1>("h01"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3732 = and(_T_3730, _T_3731) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3733 = or(_T_3729, _T_3732) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3734 = and(_T_3724, _T_3733) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3735 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3736 = and(ibuf_drain_vld, _T_3735) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3737 = or(_T_3734, _T_3736) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[1] <= _T_3737 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3738 = eq(UInt<1>("h01"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3739 = and(ibuf_drain_vld, _T_3738) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3740 = bits(_T_3739, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3741 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3742 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3743 = mux(_T_3740, _T_3741, _T_3742) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[1] <= _T_3743 @[el2_lsu_bus_buffer.scala 500:24] skip @[Conditional.scala 40:58] else : @[Conditional.scala 39:67] - node _T_3779 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3779 : @[Conditional.scala 39:67] - node _T_3780 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 623:66] - node _T_3781 = mux(_T_3780, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 623:37] - buf_nxtstate[3] <= _T_3781 @[el2_lsu_bus_buffer.scala 623:31] - node _T_3782 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 624:52] - buf_state_en[3] <= _T_3782 @[el2_lsu_bus_buffer.scala 624:31] + node _T_3744 = eq(UInt<3>("h01"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3744 : @[Conditional.scala 39:67] + node _T_3745 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3746 = mux(_T_3745, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[1] <= _T_3746 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3747 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[1] <= _T_3747 @[el2_lsu_bus_buffer.scala 504:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3783 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3783 : @[Conditional.scala 39:67] - node _T_3784 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 627:72] - node _T_3785 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 627:101] - node _T_3786 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 627:136] - node _T_3787 = and(_T_3785, _T_3786) @[el2_lsu_bus_buffer.scala 627:116] - node _T_3788 = mux(_T_3787, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 627:87] - node _T_3789 = mux(_T_3784, UInt<3>("h00"), _T_3788) @[el2_lsu_bus_buffer.scala 627:43] - buf_nxtstate[3] <= _T_3789 @[el2_lsu_bus_buffer.scala 627:37] - node _T_3790 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 628:52] - node _T_3791 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 628:112] - node _T_3792 = and(obuf_merge, _T_3791) @[el2_lsu_bus_buffer.scala 628:99] - node _T_3793 = or(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 628:85] - node _T_3794 = and(_T_3793, obuf_valid) @[el2_lsu_bus_buffer.scala 628:147] - node _T_3795 = and(_T_3794, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 628:160] - buf_cmd_state_bus_en[3] <= _T_3795 @[el2_lsu_bus_buffer.scala 628:37] - buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 629:37] - node _T_3796 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 630:61] - node _T_3797 = or(_T_3796, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 630:82] - buf_state_en[3] <= _T_3797 @[el2_lsu_bus_buffer.scala 630:37] - buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 631:37] - node _T_3798 = eq(buf_write[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:58] - node _T_3799 = and(buf_state_en[3], _T_3798) @[el2_lsu_bus_buffer.scala 632:56] - node _T_3800 = and(_T_3799, obuf_nosend) @[el2_lsu_bus_buffer.scala 632:72] - node _T_3801 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 632:88] - node _T_3802 = and(_T_3800, _T_3801) @[el2_lsu_bus_buffer.scala 632:86] - buf_ldfwd_en[3] <= _T_3802 @[el2_lsu_bus_buffer.scala 632:37] - node _T_3803 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 633:55] - buf_ldfwdtag_in[3] <= _T_3803 @[el2_lsu_bus_buffer.scala 633:37] - node _T_3804 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 634:60] - node _T_3805 = and(_T_3804, obuf_nosend) @[el2_lsu_bus_buffer.scala 634:80] - node _T_3806 = and(_T_3805, bus_rsp_read) @[el2_lsu_bus_buffer.scala 634:94] - buf_data_en[3] <= _T_3806 @[el2_lsu_bus_buffer.scala 634:37] - node _T_3807 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 635:60] - node _T_3808 = and(_T_3807, obuf_nosend) @[el2_lsu_bus_buffer.scala 635:80] - node _T_3809 = and(_T_3808, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 635:94] - buf_error_en[3] <= _T_3809 @[el2_lsu_bus_buffer.scala 635:37] - node _T_3810 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:74] - node _T_3811 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 636:97] - node _T_3812 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 636:115] - node _T_3813 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 636:138] - node _T_3814 = mux(_T_3811, _T_3812, _T_3813) @[el2_lsu_bus_buffer.scala 636:85] - node _T_3815 = mux(buf_error_en[3], _T_3810, _T_3814) @[el2_lsu_bus_buffer.scala 636:43] - buf_data_in[3] <= _T_3815 @[el2_lsu_bus_buffer.scala 636:37] + node _T_3748 = eq(UInt<3>("h02"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3748 : @[Conditional.scala 39:67] + node _T_3749 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3750 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3751 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3752 = and(_T_3750, _T_3751) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3753 = mux(_T_3752, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3754 = mux(_T_3749, UInt<3>("h00"), _T_3753) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[1] <= _T_3754 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3755 = eq(obuf_tag0, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3756 = eq(obuf_tag1, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3757 = and(obuf_merge, _T_3756) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3758 = or(_T_3755, _T_3757) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3759 = and(_T_3758, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3760 = and(_T_3759, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[1] <= _T_3760 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[1] <= buf_cmd_state_bus_en[1] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3761 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3762 = or(_T_3761, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[1] <= _T_3762 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3763 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3764 = eq(_T_3763, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3765 = and(buf_state_en[1], _T_3764) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3766 = and(_T_3765, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3767 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3768 = and(_T_3766, _T_3767) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[1] <= _T_3768 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3769 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[1] <= _T_3769 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3770 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3771 = and(_T_3770, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3772 = and(_T_3771, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[1] <= _T_3772 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3773 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3774 = and(_T_3773, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3775 = and(_T_3774, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[1] <= _T_3775 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3776 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3777 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3778 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3779 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3780 = mux(_T_3777, _T_3778, _T_3779) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3781 = mux(buf_error_en[1], _T_3776, _T_3780) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[1] <= _T_3781 @[el2_lsu_bus_buffer.scala 516:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3816 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3816 : @[Conditional.scala 39:67] - node _T_3817 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 639:107] - node _T_3818 = not(_T_3817) @[el2_lsu_bus_buffer.scala 639:85] - node _T_3819 = and(buf_write[3], _T_3818) @[el2_lsu_bus_buffer.scala 639:83] - node _T_3820 = or(io.dec_tlu_force_halt, _T_3819) @[el2_lsu_bus_buffer.scala 639:67] - node _T_3821 = bits(_T_3820, 0, 0) @[el2_lsu_bus_buffer.scala 639:138] - node _T_3822 = not(buf_samedw[3]) @[el2_lsu_bus_buffer.scala 640:62] - node _T_3823 = and(buf_dual[3], _T_3822) @[el2_lsu_bus_buffer.scala 640:60] - node _T_3824 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 640:80] - node _T_3825 = and(_T_3823, _T_3824) @[el2_lsu_bus_buffer.scala 640:78] - node _T_3826 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 640:123] - node _T_3827 = and(_T_3825, _T_3826) @[el2_lsu_bus_buffer.scala 640:95] - node _T_3828 = or(buf_ldfwd[3], any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:64] - node _T_3829 = not(buf_samedw[3]) @[el2_lsu_bus_buffer.scala 641:103] - node _T_3830 = and(buf_dual[3], _T_3829) @[el2_lsu_bus_buffer.scala 641:101] - node _T_3831 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 641:121] - node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 641:119] - node _T_3833 = and(_T_3832, buf_ldfwd[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 641:136] - node _T_3834 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 641:193] - node _T_3835 = and(_T_3833, _T_3834) @[el2_lsu_bus_buffer.scala 641:164] - node _T_3836 = and(_T_3835, any_done_wait_state) @[el2_lsu_bus_buffer.scala 641:213] - node _T_3837 = or(_T_3828, _T_3836) @[el2_lsu_bus_buffer.scala 641:86] - node _T_3838 = mux(_T_3837, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 641:49] - node _T_3839 = mux(_T_3827, UInt<3>("h04"), _T_3838) @[el2_lsu_bus_buffer.scala 640:46] - node _T_3840 = mux(_T_3821, UInt<3>("h00"), _T_3839) @[el2_lsu_bus_buffer.scala 639:43] - buf_nxtstate[3] <= _T_3840 @[el2_lsu_bus_buffer.scala 639:37] - node _T_3841 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:76] - node _T_3842 = and(bus_rsp_write, _T_3841) @[el2_lsu_bus_buffer.scala 642:55] - node _T_3843 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 643:78] - node _T_3844 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 644:80] - node _T_3845 = and(buf_ldfwd[3], _T_3844) @[el2_lsu_bus_buffer.scala 644:60] - node _T_3846 = or(_T_3843, _T_3845) @[el2_lsu_bus_buffer.scala 643:113] - node _T_3847 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 645:62] - node _T_3848 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 645:80] - node _T_3849 = and(_T_3847, _T_3848) @[el2_lsu_bus_buffer.scala 645:78] - node _T_3850 = and(_T_3849, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 645:94] - node _T_3851 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 645:130] - node _T_3852 = and(_T_3850, _T_3851) @[el2_lsu_bus_buffer.scala 645:110] - node _T_3853 = or(_T_3846, _T_3852) @[el2_lsu_bus_buffer.scala 644:104] - node _T_3854 = and(bus_rsp_read, _T_3853) @[el2_lsu_bus_buffer.scala 643:57] - node _T_3855 = or(_T_3842, _T_3854) @[el2_lsu_bus_buffer.scala 642:112] - buf_resp_state_bus_en[3] <= _T_3855 @[el2_lsu_bus_buffer.scala 642:37] - buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 646:37] - node _T_3856 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 647:61] - node _T_3857 = or(_T_3856, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 647:82] - buf_state_en[3] <= _T_3857 @[el2_lsu_bus_buffer.scala 647:37] - node _T_3858 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 648:60] - node _T_3859 = and(_T_3858, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 648:75] - buf_data_en[3] <= _T_3859 @[el2_lsu_bus_buffer.scala 648:37] - node _T_3860 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 649:60] - node _T_3861 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 649:123] - node _T_3862 = and(bus_rsp_read_error, _T_3861) @[el2_lsu_bus_buffer.scala 649:103] - node _T_3863 = and(bus_rsp_read_error, buf_ldfwd[3]) @[el2_lsu_bus_buffer.scala 650:63] - node _T_3864 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 650:98] - node _T_3865 = and(_T_3863, _T_3864) @[el2_lsu_bus_buffer.scala 650:78] - node _T_3866 = or(_T_3862, _T_3865) @[el2_lsu_bus_buffer.scala 649:160] - node _T_3867 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 651:67] - node _T_3868 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 651:110] - node _T_3869 = and(_T_3867, _T_3868) @[el2_lsu_bus_buffer.scala 651:89] - node _T_3870 = or(_T_3866, _T_3869) @[el2_lsu_bus_buffer.scala 650:120] - node _T_3871 = and(_T_3860, _T_3870) @[el2_lsu_bus_buffer.scala 649:80] - buf_error_en[3] <= _T_3871 @[el2_lsu_bus_buffer.scala 649:37] - node _T_3872 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 652:63] - node _T_3873 = and(buf_state_en[3], _T_3872) @[el2_lsu_bus_buffer.scala 652:61] - node _T_3874 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 652:97] - node _T_3875 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 652:115] - node _T_3876 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:138] - node _T_3877 = mux(_T_3874, _T_3875, _T_3876) @[el2_lsu_bus_buffer.scala 652:85] - node _T_3878 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 652:161] - node _T_3879 = mux(_T_3873, _T_3877, _T_3878) @[el2_lsu_bus_buffer.scala 652:43] - buf_data_in[3] <= _T_3879 @[el2_lsu_bus_buffer.scala 652:37] + node _T_3782 = eq(UInt<3>("h03"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3782 : @[Conditional.scala 39:67] + node _T_3783 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3784 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3785 = eq(_T_3784, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3786 = and(_T_3783, _T_3785) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3787 = or(io.dec_tlu_force_halt, _T_3786) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3788 = bits(_T_3787, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3789 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3790 = and(buf_dual[1], _T_3789) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3791 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3792 = eq(_T_3791, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3793 = and(_T_3790, _T_3792) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3794 = neq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3795 = and(_T_3793, _T_3794) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3796 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3797 = or(_T_3796, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3798 = eq(buf_samedw[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3799 = and(buf_dual[1], _T_3798) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3800 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3801 = eq(_T_3800, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3802 = and(_T_3799, _T_3801) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3803 = eq(buf_dualtag[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3804 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3805 = eq(buf_dualtag[1], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3806 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3807 = eq(buf_dualtag[1], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3808 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3809 = eq(buf_dualtag[1], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3810 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3811 = mux(_T_3803, _T_3804, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3812 = mux(_T_3805, _T_3806, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3813 = mux(_T_3807, _T_3808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3814 = mux(_T_3809, _T_3810, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_3815 = or(_T_3811, _T_3812) @[Mux.scala 27:72] + node _T_3816 = or(_T_3815, _T_3813) @[Mux.scala 27:72] + node _T_3817 = or(_T_3816, _T_3814) @[Mux.scala 27:72] + wire _T_3818 : UInt<1> @[Mux.scala 27:72] + _T_3818 <= _T_3817 @[Mux.scala 27:72] + node _T_3819 = and(_T_3802, _T_3818) @[el2_lsu_bus_buffer.scala 521:101] + node _T_3820 = eq(buf_state[buf_dualtag[1]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_3821 = and(_T_3819, _T_3820) @[el2_lsu_bus_buffer.scala 521:138] + node _T_3822 = and(_T_3821, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_3823 = or(_T_3797, _T_3822) @[el2_lsu_bus_buffer.scala 521:53] + node _T_3824 = mux(_T_3823, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_3825 = mux(_T_3795, UInt<3>("h04"), _T_3824) @[el2_lsu_bus_buffer.scala 520:14] + node _T_3826 = mux(_T_3788, UInt<3>("h00"), _T_3825) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[1] <= _T_3826 @[el2_lsu_bus_buffer.scala 519:25] + node _T_3827 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_3828 = and(bus_rsp_write, _T_3827) @[el2_lsu_bus_buffer.scala 522:52] + node _T_3829 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_3830 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 524:23] + node _T_3831 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_3832 = and(_T_3830, _T_3831) @[el2_lsu_bus_buffer.scala 524:27] + node _T_3833 = or(_T_3829, _T_3832) @[el2_lsu_bus_buffer.scala 523:77] + node _T_3834 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_3835 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 525:54] + node _T_3836 = not(_T_3835) @[el2_lsu_bus_buffer.scala 525:44] + node _T_3837 = and(_T_3834, _T_3836) @[el2_lsu_bus_buffer.scala 525:42] + node _T_3838 = and(_T_3837, buf_samedw[1]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_3839 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_3840 = and(_T_3838, _T_3839) @[el2_lsu_bus_buffer.scala 525:74] + node _T_3841 = or(_T_3833, _T_3840) @[el2_lsu_bus_buffer.scala 524:71] + node _T_3842 = and(bus_rsp_read, _T_3841) @[el2_lsu_bus_buffer.scala 523:25] + node _T_3843 = or(_T_3828, _T_3842) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[1] <= _T_3843 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[1] <= buf_resp_state_bus_en[1] @[el2_lsu_bus_buffer.scala 526:29] + node _T_3844 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_3845 = or(_T_3844, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[1] <= _T_3845 @[el2_lsu_bus_buffer.scala 527:25] + node _T_3846 = and(buf_state_bus_en[1], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_3847 = and(_T_3846, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[1] <= _T_3847 @[el2_lsu_bus_buffer.scala 528:24] + node _T_3848 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_3849 = eq(bus_rsp_read_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_3850 = and(bus_rsp_read_error, _T_3849) @[el2_lsu_bus_buffer.scala 529:91] + node _T_3851 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 530:42] + node _T_3852 = and(bus_rsp_read_error, _T_3851) @[el2_lsu_bus_buffer.scala 530:31] + node _T_3853 = eq(bus_rsp_read_tag, buf_ldfwdtag[1]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_3854 = and(_T_3852, _T_3853) @[el2_lsu_bus_buffer.scala 530:46] + node _T_3855 = or(_T_3850, _T_3854) @[el2_lsu_bus_buffer.scala 529:143] + node _T_3856 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_3857 = eq(bus_rsp_write_tag, UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_3858 = and(_T_3856, _T_3857) @[el2_lsu_bus_buffer.scala 531:53] + node _T_3859 = or(_T_3855, _T_3858) @[el2_lsu_bus_buffer.scala 530:88] + node _T_3860 = and(_T_3848, _T_3859) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[1] <= _T_3860 @[el2_lsu_bus_buffer.scala 529:25] + node _T_3861 = eq(buf_error_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_3862 = and(buf_state_en[1], _T_3861) @[el2_lsu_bus_buffer.scala 532:48] + node _T_3863 = bits(buf_addr[1], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_3864 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_3865 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_3866 = mux(_T_3863, _T_3864, _T_3865) @[el2_lsu_bus_buffer.scala 532:72] + node _T_3867 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_3868 = mux(_T_3862, _T_3866, _T_3867) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[1] <= _T_3868 @[el2_lsu_bus_buffer.scala 532:24] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3880 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3880 : @[Conditional.scala 39:67] - node _T_3881 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 655:69] - node _T_3882 = or(buf_ldfwd[3], buf_ldfwd[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 655:99] - node _T_3883 = or(_T_3882, any_done_wait_state) @[el2_lsu_bus_buffer.scala 655:127] - node _T_3884 = mux(_T_3883, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 655:84] - node _T_3885 = mux(_T_3881, UInt<3>("h00"), _T_3884) @[el2_lsu_bus_buffer.scala 655:40] - buf_nxtstate[3] <= _T_3885 @[el2_lsu_bus_buffer.scala 655:34] - node _T_3886 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 656:71] - node _T_3887 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 657:87] - node _T_3888 = and(buf_ldfwd[buf_dualtag[3]], _T_3887) @[el2_lsu_bus_buffer.scala 657:67] - node _T_3889 = or(_T_3886, _T_3888) @[el2_lsu_bus_buffer.scala 656:100] - node _T_3890 = and(bus_rsp_read, _T_3889) @[el2_lsu_bus_buffer.scala 656:50] - buf_state_bus_en[3] <= _T_3890 @[el2_lsu_bus_buffer.scala 656:34] - node _T_3891 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 658:58] - node _T_3892 = or(_T_3891, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 658:79] - buf_state_en[3] <= _T_3892 @[el2_lsu_bus_buffer.scala 658:34] + node _T_3869 = eq(UInt<3>("h04"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3869 : @[Conditional.scala 39:67] + node _T_3870 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_3871 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 535:86] + node _T_3872 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3873 = bits(_T_3872, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_3874 = or(_T_3871, _T_3873) @[el2_lsu_bus_buffer.scala 535:90] + node _T_3875 = or(_T_3874, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_3876 = mux(_T_3875, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_3877 = mux(_T_3870, UInt<3>("h00"), _T_3876) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[1] <= _T_3877 @[el2_lsu_bus_buffer.scala 535:25] + node _T_3878 = eq(bus_rsp_read_tag, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_3879 = dshr(buf_ldfwd, buf_dualtag[1]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3880 = bits(_T_3879, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_3881 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[1]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_3882 = and(_T_3880, _T_3881) @[el2_lsu_bus_buffer.scala 537:38] + node _T_3883 = or(_T_3878, _T_3882) @[el2_lsu_bus_buffer.scala 536:95] + node _T_3884 = and(bus_rsp_read, _T_3883) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[1] <= _T_3884 @[el2_lsu_bus_buffer.scala 536:29] + node _T_3885 = and(buf_state_bus_en[1], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_3886 = or(_T_3885, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[1] <= _T_3886 @[el2_lsu_bus_buffer.scala 538:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3893 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3893 : @[Conditional.scala 39:67] - node _T_3894 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 661:66] - node _T_3895 = mux(_T_3894, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 661:37] - buf_nxtstate[3] <= _T_3895 @[el2_lsu_bus_buffer.scala 661:31] - node _T_3896 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 662:43] - node _T_3897 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 662:103] - node _T_3898 = and(buf_dual[3], _T_3897) @[el2_lsu_bus_buffer.scala 662:85] - node _T_3899 = or(_T_3896, _T_3898) @[el2_lsu_bus_buffer.scala 662:71] - node _T_3900 = or(_T_3899, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 662:117] - buf_state_en[3] <= _T_3900 @[el2_lsu_bus_buffer.scala 662:31] + node _T_3887 = eq(UInt<3>("h05"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3887 : @[Conditional.scala 39:67] + node _T_3888 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_3889 = mux(_T_3888, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[1] <= _T_3889 @[el2_lsu_bus_buffer.scala 541:25] + node _T_3890 = eq(RspPtr, UInt<2>("h01")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_3891 = eq(buf_dualtag[1], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_3892 = and(buf_dual[1], _T_3891) @[el2_lsu_bus_buffer.scala 542:80] + node _T_3893 = or(_T_3890, _T_3892) @[el2_lsu_bus_buffer.scala 542:65] + node _T_3894 = or(_T_3893, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[1] <= _T_3894 @[el2_lsu_bus_buffer.scala 542:25] skip @[Conditional.scala 39:67] else : @[Conditional.scala 39:67] - node _T_3901 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] - when _T_3901 : @[Conditional.scala 39:67] - buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 665:31] - buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 666:31] - buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 667:31] - buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 668:31] - buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 669:31] + node _T_3895 = eq(UInt<3>("h06"), buf_state[1]) @[Conditional.scala 37:30] + when _T_3895 : @[Conditional.scala 39:67] + buf_nxtstate[1] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[1] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[1] <= buf_state_en[1] @[el2_lsu_bus_buffer.scala 549:25] skip @[Conditional.scala 39:67] - reg _T_3902 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3902 <= buf_byteen_in[3] @[Reg.scala 28:23] + node _T_3896 = bits(buf_state_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_3897 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3896 : @[Reg.scala 28:19] + _T_3897 <= buf_nxtstate[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_byteen[3] <= _T_3902 @[el2_lsu_bus_buffer.scala 673:31] - reg _T_3903 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_data_en[3] : @[Reg.scala 28:19] - _T_3903 <= buf_data_in[3] @[Reg.scala 28:23] + buf_state[1] <= _T_3897 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_3898 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_3898 <= buf_age_in_1 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[1] <= _T_3898 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_3899 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_3899 <= buf_rspage_in[1] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[1] <= _T_3899 @[el2_lsu_bus_buffer.scala 554:20] + node _T_3900 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_3901 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3900 : @[Reg.scala 28:19] + _T_3901 <= buf_dualtag_in[1] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_data[3] <= _T_3903 @[el2_lsu_bus_buffer.scala 674:31] - reg _T_3904 : UInt<3>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<3>("h00"))) @[Reg.scala 27:20] - when buf_state_en[3] : @[Reg.scala 28:19] - _T_3904 <= buf_nxtstate[3] @[Reg.scala 28:23] + buf_dualtag[1] <= _T_3901 @[el2_lsu_bus_buffer.scala 555:20] + node _T_3902 = bits(buf_dual_in, 1, 1) @[el2_lsu_bus_buffer.scala 556:74] + node _T_3903 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_3904 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3903 : @[Reg.scala 28:19] + _T_3904 <= _T_3902 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_state[3] <= _T_3904 @[el2_lsu_bus_buffer.scala 676:31] - reg _T_3905 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3905 <= buf_dualtag_in[3] @[Reg.scala 28:23] + buf_dual[1] <= _T_3904 @[el2_lsu_bus_buffer.scala 556:17] + node _T_3905 = bits(buf_samedw_in, 1, 1) @[el2_lsu_bus_buffer.scala 557:78] + node _T_3906 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_3907 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3906 : @[Reg.scala 28:19] + _T_3907 <= _T_3905 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualtag[3] <= _T_3905 @[el2_lsu_bus_buffer.scala 677:31] - reg _T_3906 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3906 <= buf_dual_in[3] @[Reg.scala 28:23] + buf_samedw[1] <= _T_3907 @[el2_lsu_bus_buffer.scala 557:19] + node _T_3908 = bits(buf_nomerge_in, 1, 1) @[el2_lsu_bus_buffer.scala 558:80] + node _T_3909 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_3910 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3909 : @[Reg.scala 28:19] + _T_3910 <= _T_3908 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dual[3] <= _T_3906 @[el2_lsu_bus_buffer.scala 678:31] - reg _T_3907 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3907 <= buf_samedw_in[3] @[Reg.scala 28:23] + buf_nomerge[1] <= _T_3910 @[el2_lsu_bus_buffer.scala 558:20] + node _T_3911 = bits(buf_dualhi_in, 1, 1) @[el2_lsu_bus_buffer.scala 559:78] + node _T_3912 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_3913 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_3912 : @[Reg.scala 28:19] + _T_3913 <= _T_3911 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_samedw[3] <= _T_3907 @[el2_lsu_bus_buffer.scala 679:31] - reg _T_3908 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3908 <= buf_nomerge_in[3] @[Reg.scala 28:23] + buf_dualhi[1] <= _T_3913 @[el2_lsu_bus_buffer.scala 559:19] + node _T_3914 = eq(UInt<3>("h00"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3914 : @[Conditional.scala 40:58] + node _T_3915 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_3916 = mux(_T_3915, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[2] <= _T_3916 @[el2_lsu_bus_buffer.scala 496:25] + node _T_3917 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_3918 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_3919 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_3920 = and(_T_3918, _T_3919) @[el2_lsu_bus_buffer.scala 497:95] + node _T_3921 = eq(UInt<2>("h02"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_3922 = and(_T_3920, _T_3921) @[el2_lsu_bus_buffer.scala 497:112] + node _T_3923 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_3924 = eq(UInt<2>("h02"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_3925 = and(_T_3923, _T_3924) @[el2_lsu_bus_buffer.scala 497:161] + node _T_3926 = or(_T_3922, _T_3925) @[el2_lsu_bus_buffer.scala 497:132] + node _T_3927 = and(_T_3917, _T_3926) @[el2_lsu_bus_buffer.scala 497:63] + node _T_3928 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_3929 = and(ibuf_drain_vld, _T_3928) @[el2_lsu_bus_buffer.scala 497:201] + node _T_3930 = or(_T_3927, _T_3929) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[2] <= _T_3930 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 499:24] + node _T_3931 = eq(UInt<2>("h02"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_3932 = and(ibuf_drain_vld, _T_3931) @[el2_lsu_bus_buffer.scala 500:47] + node _T_3933 = bits(_T_3932, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_3934 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_3935 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_3936 = mux(_T_3933, _T_3934, _T_3935) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[2] <= _T_3936 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_3937 = eq(UInt<3>("h01"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3937 : @[Conditional.scala 39:67] + node _T_3938 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_3939 = mux(_T_3938, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[2] <= _T_3939 @[el2_lsu_bus_buffer.scala 503:25] + node _T_3940 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[2] <= _T_3940 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3941 = eq(UInt<3>("h02"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3941 : @[Conditional.scala 39:67] + node _T_3942 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_3943 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_3944 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 507:104] + node _T_3946 = mux(_T_3945, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_3947 = mux(_T_3942, UInt<3>("h00"), _T_3946) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[2] <= _T_3947 @[el2_lsu_bus_buffer.scala 507:25] + node _T_3948 = eq(obuf_tag0, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_3949 = eq(obuf_tag1, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_3950 = and(obuf_merge, _T_3949) @[el2_lsu_bus_buffer.scala 508:91] + node _T_3951 = or(_T_3948, _T_3950) @[el2_lsu_bus_buffer.scala 508:77] + node _T_3952 = and(_T_3951, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_3953 = and(_T_3952, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[2] <= _T_3953 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[2] <= buf_cmd_state_bus_en[2] @[el2_lsu_bus_buffer.scala 509:29] + node _T_3954 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_3955 = or(_T_3954, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[2] <= _T_3955 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_3956 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 512:56] + node _T_3957 = eq(_T_3956, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_3958 = and(buf_state_en[2], _T_3957) @[el2_lsu_bus_buffer.scala 512:44] + node _T_3959 = and(_T_3958, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_3960 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_3961 = and(_T_3959, _T_3960) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[2] <= _T_3961 @[el2_lsu_bus_buffer.scala 512:25] + node _T_3962 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[2] <= _T_3962 @[el2_lsu_bus_buffer.scala 513:28] + node _T_3963 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_3964 = and(_T_3963, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_3965 = and(_T_3964, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[2] <= _T_3965 @[el2_lsu_bus_buffer.scala 514:24] + node _T_3966 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_3967 = and(_T_3966, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_3968 = and(_T_3967, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[2] <= _T_3968 @[el2_lsu_bus_buffer.scala 515:25] + node _T_3969 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_3970 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_3971 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_3972 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_3973 = mux(_T_3970, _T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 516:73] + node _T_3974 = mux(buf_error_en[2], _T_3969, _T_3973) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[2] <= _T_3974 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_3975 = eq(UInt<3>("h03"), buf_state[2]) @[Conditional.scala 37:30] + when _T_3975 : @[Conditional.scala 39:67] + node _T_3976 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 519:67] + node _T_3977 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_3978 = eq(_T_3977, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_3979 = and(_T_3976, _T_3978) @[el2_lsu_bus_buffer.scala 519:71] + node _T_3980 = or(io.dec_tlu_force_halt, _T_3979) @[el2_lsu_bus_buffer.scala 519:55] + node _T_3981 = bits(_T_3980, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_3982 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_3983 = and(buf_dual[2], _T_3982) @[el2_lsu_bus_buffer.scala 520:28] + node _T_3984 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 520:57] + node _T_3985 = eq(_T_3984, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_3986 = and(_T_3983, _T_3985) @[el2_lsu_bus_buffer.scala 520:45] + node _T_3987 = neq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_3988 = and(_T_3986, _T_3987) @[el2_lsu_bus_buffer.scala 520:61] + node _T_3989 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 521:27] + node _T_3990 = or(_T_3989, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_3991 = eq(buf_samedw[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_3992 = and(buf_dual[2], _T_3991) @[el2_lsu_bus_buffer.scala 521:68] + node _T_3993 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 521:97] + node _T_3994 = eq(_T_3993, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_3995 = and(_T_3992, _T_3994) @[el2_lsu_bus_buffer.scala 521:85] + node _T_3996 = eq(buf_dualtag[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3997 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_3998 = eq(buf_dualtag[2], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_3999 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4000 = eq(buf_dualtag[2], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4001 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4002 = eq(buf_dualtag[2], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4003 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4004 = mux(_T_3996, _T_3997, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4005 = mux(_T_3998, _T_3999, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4006 = mux(_T_4000, _T_4001, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4007 = mux(_T_4002, _T_4003, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4008 = or(_T_4004, _T_4005) @[Mux.scala 27:72] + node _T_4009 = or(_T_4008, _T_4006) @[Mux.scala 27:72] + node _T_4010 = or(_T_4009, _T_4007) @[Mux.scala 27:72] + wire _T_4011 : UInt<1> @[Mux.scala 27:72] + _T_4011 <= _T_4010 @[Mux.scala 27:72] + node _T_4012 = and(_T_3995, _T_4011) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4013 = eq(buf_state[buf_dualtag[2]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4014 = and(_T_4012, _T_4013) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4015 = and(_T_4014, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4016 = or(_T_3990, _T_4015) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4017 = mux(_T_4016, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4018 = mux(_T_3988, UInt<3>("h04"), _T_4017) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4019 = mux(_T_3981, UInt<3>("h00"), _T_4018) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[2] <= _T_4019 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4020 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4021 = and(bus_rsp_write, _T_4020) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4022 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4023 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4024 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4025 = and(_T_4023, _T_4024) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4026 = or(_T_4022, _T_4025) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4027 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4028 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4029 = not(_T_4028) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4030 = and(_T_4027, _T_4029) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4031 = and(_T_4030, buf_samedw[2]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4032 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4033 = and(_T_4031, _T_4032) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4034 = or(_T_4026, _T_4033) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4035 = and(bus_rsp_read, _T_4034) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4036 = or(_T_4021, _T_4035) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[2] <= _T_4036 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[2] <= buf_resp_state_bus_en[2] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4037 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4038 = or(_T_4037, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[2] <= _T_4038 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4039 = and(buf_state_bus_en[2], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4040 = and(_T_4039, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[2] <= _T_4040 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4041 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4042 = eq(bus_rsp_read_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4043 = and(bus_rsp_read_error, _T_4042) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4044 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4045 = and(bus_rsp_read_error, _T_4044) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4046 = eq(bus_rsp_read_tag, buf_ldfwdtag[2]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4047 = and(_T_4045, _T_4046) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4048 = or(_T_4043, _T_4047) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4049 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4050 = eq(bus_rsp_write_tag, UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4051 = and(_T_4049, _T_4050) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4052 = or(_T_4048, _T_4051) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4053 = and(_T_4041, _T_4052) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[2] <= _T_4053 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4054 = eq(buf_error_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4055 = and(buf_state_en[2], _T_4054) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4056 = bits(buf_addr[2], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4057 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4058 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4059 = mux(_T_4056, _T_4057, _T_4058) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4060 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4061 = mux(_T_4055, _T_4059, _T_4060) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[2] <= _T_4061 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4062 = eq(UInt<3>("h04"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4062 : @[Conditional.scala 39:67] + node _T_4063 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4064 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4065 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4066 = bits(_T_4065, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4067 = or(_T_4064, _T_4066) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4068 = or(_T_4067, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4069 = mux(_T_4068, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4070 = mux(_T_4063, UInt<3>("h00"), _T_4069) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[2] <= _T_4070 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4071 = eq(bus_rsp_read_tag, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4072 = dshr(buf_ldfwd, buf_dualtag[2]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4073 = bits(_T_4072, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4074 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[2]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4075 = and(_T_4073, _T_4074) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4076 = or(_T_4071, _T_4075) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4077 = and(bus_rsp_read, _T_4076) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[2] <= _T_4077 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4078 = and(buf_state_bus_en[2], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4079 = or(_T_4078, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[2] <= _T_4079 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4080 = eq(UInt<3>("h05"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4080 : @[Conditional.scala 39:67] + node _T_4081 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4082 = mux(_T_4081, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[2] <= _T_4082 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4083 = eq(RspPtr, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4084 = eq(buf_dualtag[2], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4085 = and(buf_dual[2], _T_4084) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4086 = or(_T_4083, _T_4085) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4087 = or(_T_4086, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[2] <= _T_4087 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4088 = eq(UInt<3>("h06"), buf_state[2]) @[Conditional.scala 37:30] + when _T_4088 : @[Conditional.scala 39:67] + buf_nxtstate[2] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[2] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[2] <= buf_state_en[2] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4089 = bits(buf_state_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4090 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4089 : @[Reg.scala 28:19] + _T_4090 <= buf_nxtstate[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_nomerge[3] <= _T_3908 @[el2_lsu_bus_buffer.scala 680:31] - reg _T_3909 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3909 <= buf_dualhi_in[3] @[Reg.scala 28:23] + buf_state[2] <= _T_4090 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4091 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4091 <= buf_age_in_2 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[2] <= _T_4091 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4092 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4092 <= buf_rspage_in[2] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[2] <= _T_4092 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4093 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4094 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4093 : @[Reg.scala 28:19] + _T_4094 <= buf_dualtag_in[2] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_dualhi[3] <= _T_3909 @[el2_lsu_bus_buffer.scala 681:31] - reg _T_3910 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3910 <= buf_sideeffect_in[3] @[Reg.scala 28:23] + buf_dualtag[2] <= _T_4094 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4095 = bits(buf_dual_in, 2, 2) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4096 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4097 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4096 : @[Reg.scala 28:19] + _T_4097 <= _T_4095 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sideeffect[3] <= _T_3910 @[el2_lsu_bus_buffer.scala 682:31] - reg _T_3911 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3911 <= buf_unsign_in[3] @[Reg.scala 28:23] + buf_dual[2] <= _T_4097 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4098 = bits(buf_samedw_in, 2, 2) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4099 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4100 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4099 : @[Reg.scala 28:19] + _T_4100 <= _T_4098 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_unsign[3] <= _T_3911 @[el2_lsu_bus_buffer.scala 683:31] - reg _T_3912 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3912 <= buf_write_in[3] @[Reg.scala 28:23] + buf_samedw[2] <= _T_4100 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4101 = bits(buf_nomerge_in, 2, 2) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4102 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4103 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4102 : @[Reg.scala 28:19] + _T_4103 <= _T_4101 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_write[3] <= _T_3912 @[el2_lsu_bus_buffer.scala 684:31] - reg _T_3913 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3913 <= buf_sz_in[3] @[Reg.scala 28:23] + buf_nomerge[2] <= _T_4103 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4104 = bits(buf_dualhi_in, 2, 2) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4105 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4106 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4105 : @[Reg.scala 28:19] + _T_4106 <= _T_4104 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_sz[3] <= _T_3913 @[el2_lsu_bus_buffer.scala 685:31] - reg _T_3914 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_wr_en[3] : @[Reg.scala 28:19] - _T_3914 <= buf_addr_in[3] @[Reg.scala 28:23] + buf_dualhi[2] <= _T_4106 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4107 = eq(UInt<3>("h00"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4107 : @[Conditional.scala 40:58] + node _T_4108 = bits(io.lsu_bus_clk_en, 0, 0) @[el2_lsu_bus_buffer.scala 496:56] + node _T_4109 = mux(_T_4108, UInt<3>("h02"), UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 496:31] + buf_nxtstate[3] <= _T_4109 @[el2_lsu_bus_buffer.scala 496:25] + node _T_4110 = and(io.lsu_busreq_r, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 497:45] + node _T_4111 = or(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:77] + node _T_4112 = eq(ibuf_merge_en, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 497:97] + node _T_4113 = and(_T_4111, _T_4112) @[el2_lsu_bus_buffer.scala 497:95] + node _T_4114 = eq(UInt<2>("h03"), WrPtr0_r) @[el2_lsu_bus_buffer.scala 497:117] + node _T_4115 = and(_T_4113, _T_4114) @[el2_lsu_bus_buffer.scala 497:112] + node _T_4116 = and(ibuf_byp, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 497:144] + node _T_4117 = eq(UInt<2>("h03"), WrPtr1_r) @[el2_lsu_bus_buffer.scala 497:166] + node _T_4118 = and(_T_4116, _T_4117) @[el2_lsu_bus_buffer.scala 497:161] + node _T_4119 = or(_T_4115, _T_4118) @[el2_lsu_bus_buffer.scala 497:132] + node _T_4120 = and(_T_4110, _T_4119) @[el2_lsu_bus_buffer.scala 497:63] + node _T_4121 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 497:206] + node _T_4122 = and(ibuf_drain_vld, _T_4121) @[el2_lsu_bus_buffer.scala 497:201] + node _T_4123 = or(_T_4120, _T_4122) @[el2_lsu_bus_buffer.scala 497:183] + buf_state_en[3] <= _T_4123 @[el2_lsu_bus_buffer.scala 497:25] + buf_wr_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 498:22] + buf_data_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 499:24] + node _T_4124 = eq(UInt<2>("h03"), ibuf_tag) @[el2_lsu_bus_buffer.scala 500:52] + node _T_4125 = and(ibuf_drain_vld, _T_4124) @[el2_lsu_bus_buffer.scala 500:47] + node _T_4126 = bits(_T_4125, 0, 0) @[el2_lsu_bus_buffer.scala 500:73] + node _T_4127 = bits(ibuf_data_out, 31, 0) @[el2_lsu_bus_buffer.scala 500:90] + node _T_4128 = bits(store_data_lo_r, 31, 0) @[el2_lsu_bus_buffer.scala 500:114] + node _T_4129 = mux(_T_4126, _T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 500:30] + buf_data_in[3] <= _T_4129 @[el2_lsu_bus_buffer.scala 500:24] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_4130 = eq(UInt<3>("h01"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4130 : @[Conditional.scala 39:67] + node _T_4131 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 503:60] + node _T_4132 = mux(_T_4131, UInt<3>("h00"), UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 503:31] + buf_nxtstate[3] <= _T_4132 @[el2_lsu_bus_buffer.scala 503:25] + node _T_4133 = or(io.lsu_bus_clk_en, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 504:46] + buf_state_en[3] <= _T_4133 @[el2_lsu_bus_buffer.scala 504:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4134 = eq(UInt<3>("h02"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4134 : @[Conditional.scala 39:67] + node _T_4135 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 507:60] + node _T_4136 = and(obuf_nosend, bus_rsp_read) @[el2_lsu_bus_buffer.scala 507:89] + node _T_4137 = eq(bus_rsp_read_tag, obuf_rdrsp_tag) @[el2_lsu_bus_buffer.scala 507:124] + node _T_4138 = and(_T_4136, _T_4137) @[el2_lsu_bus_buffer.scala 507:104] + node _T_4139 = mux(_T_4138, UInt<3>("h05"), UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 507:75] + node _T_4140 = mux(_T_4135, UInt<3>("h00"), _T_4139) @[el2_lsu_bus_buffer.scala 507:31] + buf_nxtstate[3] <= _T_4140 @[el2_lsu_bus_buffer.scala 507:25] + node _T_4141 = eq(obuf_tag0, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:48] + node _T_4142 = eq(obuf_tag1, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 508:104] + node _T_4143 = and(obuf_merge, _T_4142) @[el2_lsu_bus_buffer.scala 508:91] + node _T_4144 = or(_T_4141, _T_4143) @[el2_lsu_bus_buffer.scala 508:77] + node _T_4145 = and(_T_4144, obuf_valid) @[el2_lsu_bus_buffer.scala 508:135] + node _T_4146 = and(_T_4145, obuf_wr_enQ) @[el2_lsu_bus_buffer.scala 508:148] + buf_cmd_state_bus_en[3] <= _T_4146 @[el2_lsu_bus_buffer.scala 508:33] + buf_state_bus_en[3] <= buf_cmd_state_bus_en[3] @[el2_lsu_bus_buffer.scala 509:29] + node _T_4147 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 510:49] + node _T_4148 = or(_T_4147, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 510:70] + buf_state_en[3] <= _T_4148 @[el2_lsu_bus_buffer.scala 510:25] + buf_ldfwd_in[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 511:25] + node _T_4149 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 512:56] + node _T_4150 = eq(_T_4149, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:46] + node _T_4151 = and(buf_state_en[3], _T_4150) @[el2_lsu_bus_buffer.scala 512:44] + node _T_4152 = and(_T_4151, obuf_nosend) @[el2_lsu_bus_buffer.scala 512:60] + node _T_4153 = eq(io.dec_tlu_force_halt, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 512:76] + node _T_4154 = and(_T_4152, _T_4153) @[el2_lsu_bus_buffer.scala 512:74] + buf_ldfwd_en[3] <= _T_4154 @[el2_lsu_bus_buffer.scala 512:25] + node _T_4155 = bits(obuf_rdrsp_tag, 1, 0) @[el2_lsu_bus_buffer.scala 513:46] + buf_ldfwdtag_in[3] <= _T_4155 @[el2_lsu_bus_buffer.scala 513:28] + node _T_4156 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 514:47] + node _T_4157 = and(_T_4156, obuf_nosend) @[el2_lsu_bus_buffer.scala 514:67] + node _T_4158 = and(_T_4157, bus_rsp_read) @[el2_lsu_bus_buffer.scala 514:81] + buf_data_en[3] <= _T_4158 @[el2_lsu_bus_buffer.scala 514:24] + node _T_4159 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 515:48] + node _T_4160 = and(_T_4159, obuf_nosend) @[el2_lsu_bus_buffer.scala 515:68] + node _T_4161 = and(_T_4160, bus_rsp_read_error) @[el2_lsu_bus_buffer.scala 515:82] + buf_error_en[3] <= _T_4161 @[el2_lsu_bus_buffer.scala 515:25] + node _T_4162 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:61] + node _T_4163 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 516:85] + node _T_4164 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 516:103] + node _T_4165 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 516:126] + node _T_4166 = mux(_T_4163, _T_4164, _T_4165) @[el2_lsu_bus_buffer.scala 516:73] + node _T_4167 = mux(buf_error_en[3], _T_4162, _T_4166) @[el2_lsu_bus_buffer.scala 516:30] + buf_data_in[3] <= _T_4167 @[el2_lsu_bus_buffer.scala 516:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4168 = eq(UInt<3>("h03"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4168 : @[Conditional.scala 39:67] + node _T_4169 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 519:67] + node _T_4170 = and(UInt<1>("h01"), bus_rsp_write_error) @[el2_lsu_bus_buffer.scala 519:94] + node _T_4171 = eq(_T_4170, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 519:73] + node _T_4172 = and(_T_4169, _T_4171) @[el2_lsu_bus_buffer.scala 519:71] + node _T_4173 = or(io.dec_tlu_force_halt, _T_4172) @[el2_lsu_bus_buffer.scala 519:55] + node _T_4174 = bits(_T_4173, 0, 0) @[el2_lsu_bus_buffer.scala 519:125] + node _T_4175 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:30] + node _T_4176 = and(buf_dual[3], _T_4175) @[el2_lsu_bus_buffer.scala 520:28] + node _T_4177 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 520:57] + node _T_4178 = eq(_T_4177, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 520:47] + node _T_4179 = and(_T_4176, _T_4178) @[el2_lsu_bus_buffer.scala 520:45] + node _T_4180 = neq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 520:90] + node _T_4181 = and(_T_4179, _T_4180) @[el2_lsu_bus_buffer.scala 520:61] + node _T_4182 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 521:27] + node _T_4183 = or(_T_4182, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:31] + node _T_4184 = eq(buf_samedw[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:70] + node _T_4185 = and(buf_dual[3], _T_4184) @[el2_lsu_bus_buffer.scala 521:68] + node _T_4186 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 521:97] + node _T_4187 = eq(_T_4186, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 521:87] + node _T_4188 = and(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 521:85] + node _T_4189 = eq(buf_dualtag[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4190 = bits(buf_ldfwd, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4191 = eq(buf_dualtag[3], UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4192 = bits(buf_ldfwd, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4193 = eq(buf_dualtag[3], UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4194 = bits(buf_ldfwd, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4195 = eq(buf_dualtag[3], UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4196 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4197 = mux(_T_4189, _T_4190, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4198 = mux(_T_4191, _T_4192, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4199 = mux(_T_4193, _T_4194, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4200 = mux(_T_4195, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4201 = or(_T_4197, _T_4198) @[Mux.scala 27:72] + node _T_4202 = or(_T_4201, _T_4199) @[Mux.scala 27:72] + node _T_4203 = or(_T_4202, _T_4200) @[Mux.scala 27:72] + wire _T_4204 : UInt<1> @[Mux.scala 27:72] + _T_4204 <= _T_4203 @[Mux.scala 27:72] + node _T_4205 = and(_T_4188, _T_4204) @[el2_lsu_bus_buffer.scala 521:101] + node _T_4206 = eq(buf_state[buf_dualtag[3]], UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 521:167] + node _T_4207 = and(_T_4205, _T_4206) @[el2_lsu_bus_buffer.scala 521:138] + node _T_4208 = and(_T_4207, any_done_wait_state) @[el2_lsu_bus_buffer.scala 521:187] + node _T_4209 = or(_T_4183, _T_4208) @[el2_lsu_bus_buffer.scala 521:53] + node _T_4210 = mux(_T_4209, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 521:16] + node _T_4211 = mux(_T_4181, UInt<3>("h04"), _T_4210) @[el2_lsu_bus_buffer.scala 520:14] + node _T_4212 = mux(_T_4174, UInt<3>("h00"), _T_4211) @[el2_lsu_bus_buffer.scala 519:31] + buf_nxtstate[3] <= _T_4212 @[el2_lsu_bus_buffer.scala 519:25] + node _T_4213 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 522:73] + node _T_4214 = and(bus_rsp_write, _T_4213) @[el2_lsu_bus_buffer.scala 522:52] + node _T_4215 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 523:46] + node _T_4216 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 524:23] + node _T_4217 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 524:47] + node _T_4218 = and(_T_4216, _T_4217) @[el2_lsu_bus_buffer.scala 524:27] + node _T_4219 = or(_T_4215, _T_4218) @[el2_lsu_bus_buffer.scala 523:77] + node _T_4220 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 525:26] + node _T_4221 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 525:54] + node _T_4222 = not(_T_4221) @[el2_lsu_bus_buffer.scala 525:44] + node _T_4223 = and(_T_4220, _T_4222) @[el2_lsu_bus_buffer.scala 525:42] + node _T_4224 = and(_T_4223, buf_samedw[3]) @[el2_lsu_bus_buffer.scala 525:58] + node _T_4225 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 525:94] + node _T_4226 = and(_T_4224, _T_4225) @[el2_lsu_bus_buffer.scala 525:74] + node _T_4227 = or(_T_4219, _T_4226) @[el2_lsu_bus_buffer.scala 524:71] + node _T_4228 = and(bus_rsp_read, _T_4227) @[el2_lsu_bus_buffer.scala 523:25] + node _T_4229 = or(_T_4214, _T_4228) @[el2_lsu_bus_buffer.scala 522:105] + buf_resp_state_bus_en[3] <= _T_4229 @[el2_lsu_bus_buffer.scala 522:34] + buf_state_bus_en[3] <= buf_resp_state_bus_en[3] @[el2_lsu_bus_buffer.scala 526:29] + node _T_4230 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 527:49] + node _T_4231 = or(_T_4230, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 527:70] + buf_state_en[3] <= _T_4231 @[el2_lsu_bus_buffer.scala 527:25] + node _T_4232 = and(buf_state_bus_en[3], bus_rsp_read) @[el2_lsu_bus_buffer.scala 528:47] + node _T_4233 = and(_T_4232, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 528:62] + buf_data_en[3] <= _T_4233 @[el2_lsu_bus_buffer.scala 528:24] + node _T_4234 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 529:48] + node _T_4235 = eq(bus_rsp_read_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 529:111] + node _T_4236 = and(bus_rsp_read_error, _T_4235) @[el2_lsu_bus_buffer.scala 529:91] + node _T_4237 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 530:42] + node _T_4238 = and(bus_rsp_read_error, _T_4237) @[el2_lsu_bus_buffer.scala 530:31] + node _T_4239 = eq(bus_rsp_read_tag, buf_ldfwdtag[3]) @[el2_lsu_bus_buffer.scala 530:66] + node _T_4240 = and(_T_4238, _T_4239) @[el2_lsu_bus_buffer.scala 530:46] + node _T_4241 = or(_T_4236, _T_4240) @[el2_lsu_bus_buffer.scala 529:143] + node _T_4242 = and(bus_rsp_write_error, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 531:32] + node _T_4243 = eq(bus_rsp_write_tag, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 531:74] + node _T_4244 = and(_T_4242, _T_4243) @[el2_lsu_bus_buffer.scala 531:53] + node _T_4245 = or(_T_4241, _T_4244) @[el2_lsu_bus_buffer.scala 530:88] + node _T_4246 = and(_T_4234, _T_4245) @[el2_lsu_bus_buffer.scala 529:68] + buf_error_en[3] <= _T_4246 @[el2_lsu_bus_buffer.scala 529:25] + node _T_4247 = eq(buf_error_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 532:50] + node _T_4248 = and(buf_state_en[3], _T_4247) @[el2_lsu_bus_buffer.scala 532:48] + node _T_4249 = bits(buf_addr[3], 2, 2) @[el2_lsu_bus_buffer.scala 532:84] + node _T_4250 = bits(bus_rsp_rdata, 63, 32) @[el2_lsu_bus_buffer.scala 532:102] + node _T_4251 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:125] + node _T_4252 = mux(_T_4249, _T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 532:72] + node _T_4253 = bits(bus_rsp_rdata, 31, 0) @[el2_lsu_bus_buffer.scala 532:148] + node _T_4254 = mux(_T_4248, _T_4252, _T_4253) @[el2_lsu_bus_buffer.scala 532:30] + buf_data_in[3] <= _T_4254 @[el2_lsu_bus_buffer.scala 532:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4255 = eq(UInt<3>("h04"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4255 : @[Conditional.scala 39:67] + node _T_4256 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 535:60] + node _T_4257 = bits(buf_ldfwd, 3, 3) @[el2_lsu_bus_buffer.scala 535:86] + node _T_4258 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4259 = bits(_T_4258, 0, 0) @[el2_lsu_bus_buffer.scala 535:101] + node _T_4260 = or(_T_4257, _T_4259) @[el2_lsu_bus_buffer.scala 535:90] + node _T_4261 = or(_T_4260, any_done_wait_state) @[el2_lsu_bus_buffer.scala 535:118] + node _T_4262 = mux(_T_4261, UInt<3>("h05"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 535:75] + node _T_4263 = mux(_T_4256, UInt<3>("h00"), _T_4262) @[el2_lsu_bus_buffer.scala 535:31] + buf_nxtstate[3] <= _T_4263 @[el2_lsu_bus_buffer.scala 535:25] + node _T_4264 = eq(bus_rsp_read_tag, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 536:66] + node _T_4265 = dshr(buf_ldfwd, buf_dualtag[3]) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4266 = bits(_T_4265, 0, 0) @[el2_lsu_bus_buffer.scala 537:21] + node _T_4267 = eq(bus_rsp_read_tag, buf_ldfwdtag[buf_dualtag[3]]) @[el2_lsu_bus_buffer.scala 537:58] + node _T_4268 = and(_T_4266, _T_4267) @[el2_lsu_bus_buffer.scala 537:38] + node _T_4269 = or(_T_4264, _T_4268) @[el2_lsu_bus_buffer.scala 536:95] + node _T_4270 = and(bus_rsp_read, _T_4269) @[el2_lsu_bus_buffer.scala 536:45] + buf_state_bus_en[3] <= _T_4270 @[el2_lsu_bus_buffer.scala 536:29] + node _T_4271 = and(buf_state_bus_en[3], io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 538:49] + node _T_4272 = or(_T_4271, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 538:70] + buf_state_en[3] <= _T_4272 @[el2_lsu_bus_buffer.scala 538:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4273 = eq(UInt<3>("h05"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4273 : @[Conditional.scala 39:67] + node _T_4274 = bits(io.dec_tlu_force_halt, 0, 0) @[el2_lsu_bus_buffer.scala 541:60] + node _T_4275 = mux(_T_4274, UInt<3>("h00"), UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 541:31] + buf_nxtstate[3] <= _T_4275 @[el2_lsu_bus_buffer.scala 541:25] + node _T_4276 = eq(RspPtr, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 542:37] + node _T_4277 = eq(buf_dualtag[3], RspPtr) @[el2_lsu_bus_buffer.scala 542:98] + node _T_4278 = and(buf_dual[3], _T_4277) @[el2_lsu_bus_buffer.scala 542:80] + node _T_4279 = or(_T_4276, _T_4278) @[el2_lsu_bus_buffer.scala 542:65] + node _T_4280 = or(_T_4279, io.dec_tlu_force_halt) @[el2_lsu_bus_buffer.scala 542:112] + buf_state_en[3] <= _T_4280 @[el2_lsu_bus_buffer.scala 542:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_4281 = eq(UInt<3>("h06"), buf_state[3]) @[Conditional.scala 37:30] + when _T_4281 : @[Conditional.scala 39:67] + buf_nxtstate[3] <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 545:25] + buf_rst[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 546:20] + buf_state_en[3] <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 547:25] + buf_ldfwd_in[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 548:25] + buf_ldfwd_en[3] <= buf_state_en[3] @[el2_lsu_bus_buffer.scala 549:25] + skip @[Conditional.scala 39:67] + node _T_4282 = bits(buf_state_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 552:108] + reg _T_4283 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4282 : @[Reg.scala 28:19] + _T_4283 <= buf_nxtstate[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_addr[3] <= _T_3914 @[el2_lsu_bus_buffer.scala 686:31] - reg _T_3915 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[3] : @[Reg.scala 28:19] - _T_3915 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + buf_state[3] <= _T_4283 @[el2_lsu_bus_buffer.scala 552:18] + reg _T_4284 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 553:60] + _T_4284 <= buf_age_in_3 @[el2_lsu_bus_buffer.scala 553:60] + buf_ageQ[3] <= _T_4284 @[el2_lsu_bus_buffer.scala 553:17] + reg _T_4285 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 554:63] + _T_4285 <= buf_rspage_in[3] @[el2_lsu_bus_buffer.scala 554:63] + buf_rspageQ[3] <= _T_4285 @[el2_lsu_bus_buffer.scala 554:20] + node _T_4286 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 555:109] + reg _T_4287 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4286 : @[Reg.scala 28:19] + _T_4287 <= buf_dualtag_in[3] @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwd[3] <= _T_3915 @[el2_lsu_bus_buffer.scala 687:31] - reg _T_3916 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when buf_ldfwd_en[3] : @[Reg.scala 28:19] - _T_3916 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + buf_dualtag[3] <= _T_4287 @[el2_lsu_bus_buffer.scala 555:20] + node _T_4288 = bits(buf_dual_in, 3, 3) @[el2_lsu_bus_buffer.scala 556:74] + node _T_4289 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 556:107] + reg _T_4290 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4289 : @[Reg.scala 28:19] + _T_4290 <= _T_4288 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_ldfwdtag[3] <= _T_3916 @[el2_lsu_bus_buffer.scala 688:31] - node _T_3917 = not(buf_rst[3]) @[el2_lsu_bus_buffer.scala 689:44] - node _T_3918 = or(buf_error_en[3], buf_rst[3]) @[el2_lsu_bus_buffer.scala 689:99] - node _T_3919 = bits(_T_3918, 0, 0) @[el2_lsu_bus_buffer.scala 689:112] - reg _T_3920 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_3919 : @[Reg.scala 28:19] - _T_3920 <= _T_3917 @[Reg.scala 28:23] + buf_dual[3] <= _T_4290 @[el2_lsu_bus_buffer.scala 556:17] + node _T_4291 = bits(buf_samedw_in, 3, 3) @[el2_lsu_bus_buffer.scala 557:78] + node _T_4292 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 557:111] + reg _T_4293 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4292 : @[Reg.scala 28:19] + _T_4293 <= _T_4291 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - buf_error[3] <= _T_3920 @[el2_lsu_bus_buffer.scala 689:31] - wire _T_3921 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - _T_3921[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 690:83] - reg _T_3922 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3921)) @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[0] <= buf_age_in[3][0] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[1] <= buf_age_in[3][1] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[2] <= buf_age_in[3][2] @[el2_lsu_bus_buffer.scala 690:41] - _T_3922[3] <= buf_age_in[3][3] @[el2_lsu_bus_buffer.scala 690:41] - buf_ageQ[3][0] <= _T_3922[0] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][1] <= _T_3922[1] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][2] <= _T_3922[2] @[el2_lsu_bus_buffer.scala 690:31] - buf_ageQ[3][3] <= _T_3922[3] @[el2_lsu_bus_buffer.scala 690:31] - wire _T_3923 : UInt<1>[4] @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[0] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[1] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[2] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - _T_3923[3] <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 691:83] - reg _T_3924 : UInt<1>[4], io.lsu_bus_buf_c1_clk with : (reset => (reset, _T_3923)) @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[0] <= buf_rspage_in[3][0] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[1] <= buf_rspage_in[3][1] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[2] <= buf_rspage_in[3][2] @[el2_lsu_bus_buffer.scala 691:41] - _T_3924[3] <= buf_rspage_in[3][3] @[el2_lsu_bus_buffer.scala 691:41] - buf_rspageQ[3][0] <= _T_3924[0] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][1] <= _T_3924[1] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][2] <= _T_3924[2] @[el2_lsu_bus_buffer.scala 691:31] - buf_rspageQ[3][3] <= _T_3924[3] @[el2_lsu_bus_buffer.scala 691:31] - node _T_3925 = dshl(io.lsu_busreq_m, io.ldst_dual_m) @[el2_lsu_bus_buffer.scala 696:45] - node _T_3926 = dshl(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 696:83] - node _T_3927 = add(_T_3925, _T_3926) @[el2_lsu_bus_buffer.scala 696:64] - node _T_3928 = tail(_T_3927, 1) @[el2_lsu_bus_buffer.scala 696:64] - node _T_3929 = add(_T_3928, ibuf_valid) @[el2_lsu_bus_buffer.scala 696:102] - node _T_3930 = tail(_T_3929, 1) @[el2_lsu_bus_buffer.scala 696:102] - node _T_3931 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3932 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3933 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3934 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 697:75] - node _T_3935 = add(_T_3931, _T_3932) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3936 = tail(_T_3935, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3937 = add(_T_3936, _T_3933) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3938 = tail(_T_3937, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3939 = add(_T_3938, _T_3934) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3940 = tail(_T_3939, 1) @[el2_lsu_bus_buffer.scala 697:158] - node _T_3941 = add(_T_3930, _T_3940) @[el2_lsu_bus_buffer.scala 696:115] - node _T_3942 = tail(_T_3941, 1) @[el2_lsu_bus_buffer.scala 696:115] - buf_numvld_any <= _T_3942 @[el2_lsu_bus_buffer.scala 696:25] - node _T_3943 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3944 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3945 = and(_T_3943, _T_3944) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3946 = and(_T_3945, buf_write[0]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3947 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3948 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3949 = and(_T_3947, _T_3948) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3950 = and(_T_3949, buf_write[1]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3951 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3952 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3953 = and(_T_3951, _T_3952) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3954 = and(_T_3953, buf_write[2]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3955 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 698:75] - node _T_3956 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 698:88] - node _T_3957 = and(_T_3955, _T_3956) @[el2_lsu_bus_buffer.scala 698:86] - node _T_3958 = and(_T_3957, buf_write[3]) @[el2_lsu_bus_buffer.scala 698:113] - node _T_3959 = add(_T_3946, _T_3950) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3960 = tail(_T_3959, 1) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3961 = add(_T_3960, _T_3954) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3962 = tail(_T_3961, 1) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3963 = add(_T_3962, _T_3958) @[el2_lsu_bus_buffer.scala 698:158] - node _T_3964 = tail(_T_3963, 1) @[el2_lsu_bus_buffer.scala 698:158] - buf_numvld_wrcmd_any <= _T_3964 @[el2_lsu_bus_buffer.scala 698:25] - node _T_3965 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3966 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3967 = and(_T_3965, _T_3966) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3968 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3969 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3970 = and(_T_3968, _T_3969) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3971 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3972 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3973 = and(_T_3971, _T_3972) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3974 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 699:75] - node _T_3975 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 699:88] - node _T_3976 = and(_T_3974, _T_3975) @[el2_lsu_bus_buffer.scala 699:86] - node _T_3977 = add(_T_3967, _T_3970) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3978 = tail(_T_3977, 1) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3979 = add(_T_3978, _T_3973) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3980 = tail(_T_3979, 1) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3981 = add(_T_3980, _T_3976) @[el2_lsu_bus_buffer.scala 699:158] - node _T_3982 = tail(_T_3981, 1) @[el2_lsu_bus_buffer.scala 699:158] - buf_numvld_cmd_any <= _T_3982 @[el2_lsu_bus_buffer.scala 699:25] - node _T_3983 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3984 = not(buf_cmd_state_bus_en[0]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3985 = and(_T_3983, _T_3984) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3986 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3987 = or(_T_3985, _T_3986) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3988 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3989 = not(buf_cmd_state_bus_en[1]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3990 = and(_T_3988, _T_3989) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3991 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3992 = or(_T_3990, _T_3991) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3993 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3994 = not(buf_cmd_state_bus_en[2]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_3995 = and(_T_3993, _T_3994) @[el2_lsu_bus_buffer.scala 700:86] - node _T_3996 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_3997 = or(_T_3995, _T_3996) @[el2_lsu_bus_buffer.scala 700:114] - node _T_3998 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 700:75] - node _T_3999 = not(buf_cmd_state_bus_en[3]) @[el2_lsu_bus_buffer.scala 700:88] - node _T_4000 = and(_T_3998, _T_3999) @[el2_lsu_bus_buffer.scala 700:86] - node _T_4001 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 700:130] - node _T_4002 = or(_T_4000, _T_4001) @[el2_lsu_bus_buffer.scala 700:114] - node _T_4003 = add(_T_3987, _T_3992) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4004 = tail(_T_4003, 1) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4005 = add(_T_4004, _T_3997) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4006 = tail(_T_4005, 1) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4007 = add(_T_4006, _T_4002) @[el2_lsu_bus_buffer.scala 700:160] - node _T_4008 = tail(_T_4007, 1) @[el2_lsu_bus_buffer.scala 700:160] - buf_numvld_pend_any <= _T_4008 @[el2_lsu_bus_buffer.scala 700:25] - node _T_4009 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4010 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4011 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4012 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 701:75] - node _T_4013 = or(_T_4009, _T_4010) @[el2_lsu_bus_buffer.scala 701:158] - node _T_4014 = or(_T_4013, _T_4011) @[el2_lsu_bus_buffer.scala 701:158] - node _T_4015 = or(_T_4014, _T_4012) @[el2_lsu_bus_buffer.scala 701:158] - any_done_wait_state <= _T_4015 @[el2_lsu_bus_buffer.scala 701:25] - node _T_4016 = neq(buf_numvld_pend_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 703:60] - io.lsu_bus_buffer_pend_any <= _T_4016 @[el2_lsu_bus_buffer.scala 703:37] - node _T_4017 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 704:60] - node _T_4018 = bits(buf_numvld_any, 3, 0) @[el2_lsu_bus_buffer.scala 704:100] - node _T_4019 = geq(_T_4018, UInt<4>("h03")) @[el2_lsu_bus_buffer.scala 704:106] - node _T_4020 = bits(buf_numvld_any, 3, 0) @[el2_lsu_bus_buffer.scala 704:146] - node _T_4021 = eq(_T_4020, UInt<4>("h04")) @[el2_lsu_bus_buffer.scala 704:152] - node _T_4022 = mux(_T_4017, _T_4019, _T_4021) @[el2_lsu_bus_buffer.scala 704:43] - io.lsu_bus_buffer_full_any <= _T_4022 @[el2_lsu_bus_buffer.scala 704:37] - node _T_4023 = or(buf_state[0], buf_state[1]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4024 = or(_T_4023, buf_state[2]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4025 = or(_T_4024, buf_state[3]) @[el2_lsu_bus_buffer.scala 705:97] - node _T_4026 = not(_T_4025) @[el2_lsu_bus_buffer.scala 705:40] - node _T_4027 = not(ibuf_valid) @[el2_lsu_bus_buffer.scala 705:104] - node _T_4028 = and(_T_4026, _T_4027) @[el2_lsu_bus_buffer.scala 705:102] - node _T_4029 = not(obuf_valid) @[el2_lsu_bus_buffer.scala 705:118] - node _T_4030 = and(_T_4028, _T_4029) @[el2_lsu_bus_buffer.scala 705:116] - io.lsu_bus_buffer_empty_any <= _T_4030 @[el2_lsu_bus_buffer.scala 705:37] - node _T_4031 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 707:56] - node _T_4032 = and(_T_4031, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 707:77] - node _T_4033 = not(io.flush_m_up) @[el2_lsu_bus_buffer.scala 707:99] - node _T_4034 = and(_T_4032, _T_4033) @[el2_lsu_bus_buffer.scala 707:97] - node _T_4035 = not(io.ld_full_hit_m) @[el2_lsu_bus_buffer.scala 707:116] - node _T_4036 = and(_T_4034, _T_4035) @[el2_lsu_bus_buffer.scala 707:114] - io.lsu_nonblock_load_valid_m <= _T_4036 @[el2_lsu_bus_buffer.scala 707:37] - node _T_4037 = bits(WrPtr0_m, 1, 0) @[el2_lsu_bus_buffer.scala 708:48] - io.lsu_nonblock_load_tag_m <= _T_4037 @[el2_lsu_bus_buffer.scala 708:37] - node _T_4038 = not(io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 709:68] - node _T_4039 = and(lsu_nonblock_load_valid_r, _T_4038) @[el2_lsu_bus_buffer.scala 709:66] - io.lsu_nonblock_load_inv_r <= _T_4039 @[el2_lsu_bus_buffer.scala 709:37] - node _T_4040 = bits(WrPtr0_r, 1, 0) @[el2_lsu_bus_buffer.scala 710:48] - io.lsu_nonblock_load_inv_tag_r <= _T_4040 @[el2_lsu_bus_buffer.scala 710:37] - node _T_4041 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4042 = and(UInt<1>("h01"), buf_write[0]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4043 = not(_T_4042) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4044 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4045 = and(UInt<1>("h01"), buf_write[1]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4046 = not(_T_4045) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4047 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4048 = and(UInt<1>("h01"), buf_write[2]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4049 = not(_T_4048) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4050 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 712:84] - node _T_4051 = and(UInt<1>("h01"), buf_write[3]) @[el2_lsu_bus_buffer.scala 712:122] - node _T_4052 = not(_T_4051) @[el2_lsu_bus_buffer.scala 712:100] - node _T_4053 = mux(_T_4041, _T_4043, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4054 = mux(_T_4044, _T_4046, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4055 = mux(_T_4047, _T_4049, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4056 = mux(_T_4050, _T_4052, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4057 = or(_T_4053, _T_4054) @[Mux.scala 27:72] - node _T_4058 = or(_T_4057, _T_4055) @[Mux.scala 27:72] - node _T_4059 = or(_T_4058, _T_4056) @[Mux.scala 27:72] - wire _T_4060 : UInt<1> @[Mux.scala 27:72] - _T_4060 <= _T_4059 @[Mux.scala 27:72] - lsu_nonblock_load_data_ready <= _T_4060 @[el2_lsu_bus_buffer.scala 712:37] - node _T_4061 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4062 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4063 = and(_T_4061, _T_4062) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4064 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4065 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4066 = and(_T_4064, _T_4065) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4067 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4068 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4069 = and(_T_4067, _T_4068) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4070 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 713:84] - node _T_4071 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 713:97] - node _T_4072 = and(_T_4070, _T_4071) @[el2_lsu_bus_buffer.scala 713:95] - node _T_4073 = mux(_T_4063, buf_error[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4074 = mux(_T_4066, buf_error[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4075 = mux(_T_4069, buf_error[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4076 = mux(_T_4072, buf_error[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4077 = or(_T_4073, _T_4074) @[Mux.scala 27:72] - node _T_4078 = or(_T_4077, _T_4075) @[Mux.scala 27:72] - node _T_4079 = or(_T_4078, _T_4076) @[Mux.scala 27:72] - wire _T_4080 : UInt<1> @[Mux.scala 27:72] - _T_4080 <= _T_4079 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_error <= _T_4080 @[el2_lsu_bus_buffer.scala 713:37] - node _T_4081 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4082 = not(buf_dual[0]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4083 = not(buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4084 = or(_T_4082, _T_4083) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4085 = and(_T_4081, _T_4084) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4086 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4087 = and(_T_4085, _T_4086) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4088 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4089 = not(buf_dual[1]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4090 = not(buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4091 = or(_T_4089, _T_4090) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4092 = and(_T_4088, _T_4091) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4093 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4094 = and(_T_4092, _T_4093) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4095 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4096 = not(buf_dual[2]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4097 = not(buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4098 = or(_T_4096, _T_4097) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4099 = and(_T_4095, _T_4098) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4100 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4101 = and(_T_4099, _T_4100) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4102 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 714:84] - node _T_4103 = not(buf_dual[3]) @[el2_lsu_bus_buffer.scala 714:98] - node _T_4104 = not(buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 714:113] - node _T_4105 = or(_T_4103, _T_4104) @[el2_lsu_bus_buffer.scala 714:111] - node _T_4106 = and(_T_4102, _T_4105) @[el2_lsu_bus_buffer.scala 714:95] - node _T_4107 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 714:131] - node _T_4108 = and(_T_4106, _T_4107) @[el2_lsu_bus_buffer.scala 714:129] - node _T_4109 = mux(_T_4087, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4110 = mux(_T_4094, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4111 = mux(_T_4101, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4112 = mux(_T_4108, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4113 = or(_T_4109, _T_4110) @[Mux.scala 27:72] - node _T_4114 = or(_T_4113, _T_4111) @[Mux.scala 27:72] - node _T_4115 = or(_T_4114, _T_4112) @[Mux.scala 27:72] - wire _T_4116 : UInt<2> @[Mux.scala 27:72] - _T_4116 <= _T_4115 @[Mux.scala 27:72] - io.lsu_nonblock_load_data_tag <= _T_4116 @[el2_lsu_bus_buffer.scala 714:37] - node _T_4117 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4118 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4119 = and(_T_4117, _T_4118) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4120 = not(buf_dual[0]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4121 = not(buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4122 = or(_T_4120, _T_4121) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4123 = and(_T_4119, _T_4122) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4124 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4125 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4126 = and(_T_4124, _T_4125) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4127 = not(buf_dual[1]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4128 = not(buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4129 = or(_T_4127, _T_4128) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4130 = and(_T_4126, _T_4129) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4131 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4132 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4133 = and(_T_4131, _T_4132) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4134 = not(buf_dual[2]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4135 = not(buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4136 = or(_T_4134, _T_4135) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4137 = and(_T_4133, _T_4136) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4138 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 715:84] - node _T_4139 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 715:97] - node _T_4140 = and(_T_4138, _T_4139) @[el2_lsu_bus_buffer.scala 715:95] - node _T_4141 = not(buf_dual[3]) @[el2_lsu_bus_buffer.scala 715:114] - node _T_4142 = not(buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 715:129] - node _T_4143 = or(_T_4141, _T_4142) @[el2_lsu_bus_buffer.scala 715:127] - node _T_4144 = and(_T_4140, _T_4143) @[el2_lsu_bus_buffer.scala 715:111] - node _T_4145 = mux(_T_4123, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4146 = mux(_T_4130, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4147 = mux(_T_4137, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4148 = mux(_T_4144, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4149 = or(_T_4145, _T_4146) @[Mux.scala 27:72] - node _T_4150 = or(_T_4149, _T_4147) @[Mux.scala 27:72] - node _T_4151 = or(_T_4150, _T_4148) @[Mux.scala 27:72] - wire _T_4152 : UInt<32> @[Mux.scala 27:72] - _T_4152 <= _T_4151 @[Mux.scala 27:72] - lsu_nonblock_load_data_lo <= _T_4152 @[el2_lsu_bus_buffer.scala 715:37] - node _T_4153 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4154 = not(buf_write[0]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4155 = and(_T_4153, _T_4154) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4156 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4157 = and(_T_4155, _T_4156) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4158 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4159 = not(buf_write[1]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4160 = and(_T_4158, _T_4159) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4161 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4162 = and(_T_4160, _T_4161) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4163 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4164 = not(buf_write[2]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4165 = and(_T_4163, _T_4164) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4166 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4167 = and(_T_4165, _T_4166) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4168 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 716:84] - node _T_4169 = not(buf_write[3]) @[el2_lsu_bus_buffer.scala 716:97] - node _T_4170 = and(_T_4168, _T_4169) @[el2_lsu_bus_buffer.scala 716:95] - node _T_4171 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 716:127] - node _T_4172 = and(_T_4170, _T_4171) @[el2_lsu_bus_buffer.scala 716:111] - node _T_4173 = mux(_T_4157, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4174 = mux(_T_4162, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4175 = mux(_T_4167, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4176 = mux(_T_4172, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4177 = or(_T_4173, _T_4174) @[Mux.scala 27:72] - node _T_4178 = or(_T_4177, _T_4175) @[Mux.scala 27:72] - node _T_4179 = or(_T_4178, _T_4176) @[Mux.scala 27:72] - wire _T_4180 : UInt<32> @[Mux.scala 27:72] - _T_4180 <= _T_4179 @[Mux.scala 27:72] - lsu_nonblock_load_data_hi <= _T_4180 @[el2_lsu_bus_buffer.scala 716:37] - node _T_4181 = bits(buf_addr[io.lsu_nonblock_load_data_tag], 1, 0) @[el2_lsu_bus_buffer.scala 718:79] - lsu_nonblock_addr_offset <= _T_4181 @[el2_lsu_bus_buffer.scala 718:37] - node _T_4182 = bits(buf_sz[io.lsu_nonblock_load_data_tag], 1, 0) @[el2_lsu_bus_buffer.scala 719:77] - lsu_nonblock_sz <= _T_4182 @[el2_lsu_bus_buffer.scala 719:37] - lsu_nonblock_unsign <= buf_unsign[io.lsu_nonblock_load_data_tag] @[el2_lsu_bus_buffer.scala 720:37] - lsu_nonblock_dual <= buf_dual[io.lsu_nonblock_load_data_tag] @[el2_lsu_bus_buffer.scala 721:37] - node _T_4183 = bits(lsu_nonblock_load_data_hi, 31, 0) @[el2_lsu_bus_buffer.scala 722:70] - node _T_4184 = bits(lsu_nonblock_load_data_lo, 31, 0) @[el2_lsu_bus_buffer.scala 722:103] - node _T_4185 = cat(_T_4183, _T_4184) @[Cat.scala 29:58] - node _T_4186 = bits(lsu_nonblock_addr_offset, 1, 0) @[el2_lsu_bus_buffer.scala 722:140] - node _T_4187 = mul(UInt<4>("h08"), _T_4186) @[el2_lsu_bus_buffer.scala 722:115] - node _T_4188 = dshr(_T_4185, _T_4187) @[el2_lsu_bus_buffer.scala 722:111] - node _T_4189 = bits(_T_4188, 31, 0) @[el2_lsu_bus_buffer.scala 722:146] - lsu_nonblock_data_unalgn <= _T_4189 @[el2_lsu_bus_buffer.scala 722:37] - node _T_4190 = not(io.lsu_nonblock_load_data_error) @[el2_lsu_bus_buffer.scala 723:71] - node _T_4191 = and(lsu_nonblock_load_data_ready, _T_4190) @[el2_lsu_bus_buffer.scala 723:69] - io.lsu_nonblock_load_data_valid <= _T_4191 @[el2_lsu_bus_buffer.scala 723:37] - node _T_4192 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 725:83] - node _T_4193 = and(lsu_nonblock_unsign, _T_4192) @[el2_lsu_bus_buffer.scala 725:65] - node _T_4194 = mux(UInt<1>("h00"), UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4195 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 725:141] - node _T_4196 = cat(_T_4194, _T_4195) @[Cat.scala 29:58] - node _T_4197 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 726:83] - node _T_4198 = and(lsu_nonblock_unsign, _T_4197) @[el2_lsu_bus_buffer.scala 726:65] - node _T_4199 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4200 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 726:141] - node _T_4201 = cat(_T_4199, _T_4200) @[Cat.scala 29:58] - node _T_4202 = not(lsu_nonblock_unsign) @[el2_lsu_bus_buffer.scala 727:44] - node _T_4203 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 727:83] - node _T_4204 = and(_T_4202, _T_4203) @[el2_lsu_bus_buffer.scala 727:65] - node _T_4205 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 727:131] - node _T_4206 = bits(_T_4205, 0, 0) @[Bitwise.scala 72:15] - node _T_4207 = mux(_T_4206, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] - node _T_4208 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 727:160] - node _T_4209 = cat(_T_4207, _T_4208) @[Cat.scala 29:58] - node _T_4210 = not(lsu_nonblock_unsign) @[el2_lsu_bus_buffer.scala 728:44] - node _T_4211 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 728:83] - node _T_4212 = and(_T_4210, _T_4211) @[el2_lsu_bus_buffer.scala 728:65] - node _T_4213 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 728:131] - node _T_4214 = bits(_T_4213, 0, 0) @[Bitwise.scala 72:15] - node _T_4215 = mux(_T_4214, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] - node _T_4216 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 728:161] - node _T_4217 = cat(_T_4215, _T_4216) @[Cat.scala 29:58] - node _T_4218 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 729:83] - node _T_4219 = and(lsu_nonblock_unsign, _T_4218) @[el2_lsu_bus_buffer.scala 729:65] - node _T_4220 = bits(lsu_nonblock_data_unalgn, 31, 0) @[el2_lsu_bus_buffer.scala 729:119] - node _T_4221 = mux(_T_4193, _T_4196, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4222 = mux(_T_4198, _T_4201, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4223 = mux(_T_4204, _T_4209, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4224 = mux(_T_4212, _T_4217, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4225 = mux(_T_4219, _T_4220, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4226 = or(_T_4221, _T_4222) @[Mux.scala 27:72] - node _T_4227 = or(_T_4226, _T_4223) @[Mux.scala 27:72] - node _T_4228 = or(_T_4227, _T_4224) @[Mux.scala 27:72] - node _T_4229 = or(_T_4228, _T_4225) @[Mux.scala 27:72] - wire _T_4230 : UInt<32> @[Mux.scala 27:72] - _T_4230 <= _T_4229 @[Mux.scala 27:72] - io.lsu_nonblock_load_data <= _T_4230 @[el2_lsu_bus_buffer.scala 724:37] - node _T_4231 = and(obuf_sideeffect, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:62] - node _T_4232 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4233 = and(buf_sideeffect[0], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4234 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4235 = and(buf_sideeffect[1], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4236 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4237 = and(buf_sideeffect[2], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4238 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 731:145] - node _T_4239 = and(buf_sideeffect[3], io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 731:179] - node _T_4240 = mux(_T_4232, _T_4233, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4241 = mux(_T_4234, _T_4235, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4242 = mux(_T_4236, _T_4237, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4243 = mux(_T_4238, _T_4239, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4244 = or(_T_4240, _T_4241) @[Mux.scala 27:72] - node _T_4245 = or(_T_4244, _T_4242) @[Mux.scala 27:72] - node _T_4246 = or(_T_4245, _T_4243) @[Mux.scala 27:72] - wire _T_4247 : UInt<1> @[Mux.scala 27:72] - _T_4247 <= _T_4246 @[Mux.scala 27:72] - node _T_4248 = mux(obuf_valid, _T_4231, _T_4247) @[el2_lsu_bus_buffer.scala 731:34] - bus_sideeffect_pend <= _T_4248 @[el2_lsu_bus_buffer.scala 731:28] - node _T_4249 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4250 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4251 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4252 = eq(_T_4250, _T_4251) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4253 = and(_T_4249, _T_4252) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4254 = bits(_T_4253, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4255 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4256 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4257 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4258 = and(obuf_merge, _T_4257) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4259 = or(_T_4256, _T_4258) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4260 = not(_T_4259) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4261 = and(_T_4255, _T_4260) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4262 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4263 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4264 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4265 = eq(_T_4263, _T_4264) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4266 = and(_T_4262, _T_4265) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4267 = bits(_T_4266, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4268 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4269 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4270 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4271 = and(obuf_merge, _T_4270) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4272 = or(_T_4269, _T_4271) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4273 = not(_T_4272) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4274 = and(_T_4268, _T_4273) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4275 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4276 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4277 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4278 = eq(_T_4276, _T_4277) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4279 = and(_T_4275, _T_4278) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4280 = bits(_T_4279, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4281 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4282 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4283 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4284 = and(obuf_merge, _T_4283) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4285 = or(_T_4282, _T_4284) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4286 = not(_T_4285) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4287 = and(_T_4281, _T_4286) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4288 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 732:82] - node _T_4289 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 732:107] - node _T_4290 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 732:129] - node _T_4291 = eq(_T_4289, _T_4290) @[el2_lsu_bus_buffer.scala 732:114] - node _T_4292 = and(_T_4288, _T_4291) @[el2_lsu_bus_buffer.scala 732:95] - node _T_4293 = bits(_T_4292, 0, 0) @[el2_lsu_bus_buffer.scala 732:138] - node _T_4294 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 732:163] - node _T_4295 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 732:190] - node _T_4296 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 732:235] - node _T_4297 = and(obuf_merge, _T_4296) @[el2_lsu_bus_buffer.scala 732:222] - node _T_4298 = or(_T_4295, _T_4297) @[el2_lsu_bus_buffer.scala 732:208] - node _T_4299 = not(_T_4298) @[el2_lsu_bus_buffer.scala 732:177] - node _T_4300 = and(_T_4294, _T_4299) @[el2_lsu_bus_buffer.scala 732:175] - node _T_4301 = mux(_T_4254, _T_4261, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4302 = mux(_T_4267, _T_4274, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4303 = mux(_T_4280, _T_4287, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4304 = mux(_T_4293, _T_4300, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4305 = or(_T_4301, _T_4302) @[Mux.scala 27:72] - node _T_4306 = or(_T_4305, _T_4303) @[Mux.scala 27:72] - node _T_4307 = or(_T_4306, _T_4304) @[Mux.scala 27:72] - wire _T_4308 : UInt<1> @[Mux.scala 27:72] - _T_4308 <= _T_4307 @[Mux.scala 27:72] - bus_addr_match_pending <= _T_4308 @[el2_lsu_bus_buffer.scala 732:28] - node _T_4309 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 734:66] - node _T_4310 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 734:88] - node _T_4311 = and(io.lsu_axi_awready, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 734:164] - node _T_4312 = mux(_T_4309, _T_4310, _T_4311) @[el2_lsu_bus_buffer.scala 734:50] - node _T_4313 = mux(obuf_write, _T_4312, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 734:34] - bus_cmd_ready <= _T_4313 @[el2_lsu_bus_buffer.scala 734:28] - node _T_4314 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 735:50] - bus_wcmd_sent <= _T_4314 @[el2_lsu_bus_buffer.scala 735:28] - node _T_4315 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 736:49] - bus_wdata_sent <= _T_4315 @[el2_lsu_bus_buffer.scala 736:28] - node _T_4316 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 737:47] - node _T_4317 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 737:82] - node _T_4318 = and(_T_4316, _T_4317) @[el2_lsu_bus_buffer.scala 737:64] - node _T_4319 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 737:123] - node _T_4320 = or(_T_4318, _T_4319) @[el2_lsu_bus_buffer.scala 737:101] - bus_cmd_sent <= _T_4320 @[el2_lsu_bus_buffer.scala 737:28] - node _T_4321 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 739:49] - bus_rsp_read <= _T_4321 @[el2_lsu_bus_buffer.scala 739:28] - node _T_4322 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 740:49] - bus_rsp_write <= _T_4322 @[el2_lsu_bus_buffer.scala 740:28] - node _T_4323 = bits(io.lsu_axi_rid, 2, 0) @[el2_lsu_bus_buffer.scala 741:45] - bus_rsp_read_tag <= _T_4323 @[el2_lsu_bus_buffer.scala 741:28] - node _T_4324 = bits(io.lsu_axi_bid, 2, 0) @[el2_lsu_bus_buffer.scala 742:45] - bus_rsp_write_tag <= _T_4324 @[el2_lsu_bus_buffer.scala 742:28] - node _T_4325 = bits(io.lsu_axi_bresp, 1, 0) @[el2_lsu_bus_buffer.scala 743:64] - node _T_4326 = neq(_T_4325, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 743:70] - node _T_4327 = and(bus_rsp_write, _T_4326) @[el2_lsu_bus_buffer.scala 743:45] - bus_rsp_write_error <= _T_4327 @[el2_lsu_bus_buffer.scala 743:28] - node _T_4328 = bits(io.lsu_axi_rresp, 1, 0) @[el2_lsu_bus_buffer.scala 744:64] - node _T_4329 = neq(_T_4328, UInt<2>("h00")) @[el2_lsu_bus_buffer.scala 744:70] - node _T_4330 = and(bus_rsp_read, _T_4329) @[el2_lsu_bus_buffer.scala 744:45] - bus_rsp_read_error <= _T_4330 @[el2_lsu_bus_buffer.scala 744:28] - node _T_4331 = bits(io.lsu_axi_rdata, 63, 0) @[el2_lsu_bus_buffer.scala 745:47] - bus_rsp_rdata <= _T_4331 @[el2_lsu_bus_buffer.scala 745:28] - node _T_4332 = and(io.lsu_axi_rvalid, io.lsu_bus_clk_en) @[el2_lsu_bus_buffer.scala 747:94] - reg _T_4333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_4332 : @[Reg.scala 28:19] - _T_4333 <= io.lsu_axi_rdata @[Reg.scala 28:23] + buf_samedw[3] <= _T_4293 @[el2_lsu_bus_buffer.scala 557:19] + node _T_4294 = bits(buf_nomerge_in, 3, 3) @[el2_lsu_bus_buffer.scala 558:80] + node _T_4295 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 558:113] + reg _T_4296 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4295 : @[Reg.scala 28:19] + _T_4296 <= _T_4294 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - lsu_axi_rdata_q <= _T_4333 @[el2_lsu_bus_buffer.scala 747:34] - node _T_4334 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 749:64] - node _T_4335 = and(io.lsu_busreq_m, _T_4334) @[el2_lsu_bus_buffer.scala 749:62] - node _T_4336 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 749:78] - node _T_4337 = and(_T_4335, _T_4336) @[el2_lsu_bus_buffer.scala 749:76] - reg _T_4338 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 749:44] - _T_4338 <= _T_4337 @[el2_lsu_bus_buffer.scala 749:44] - io.lsu_busreq_r <= _T_4338 @[el2_lsu_bus_buffer.scala 749:34] - reg _T_4339 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 750:44] - _T_4339 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 750:44] - WrPtr0_r <= _T_4339 @[el2_lsu_bus_buffer.scala 750:34] - reg _T_4340 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 751:44] - _T_4340 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 751:44] - WrPtr1_r <= _T_4340 @[el2_lsu_bus_buffer.scala 751:34] - reg _T_4341 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 752:44] - _T_4341 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 752:44] - lsu_nonblock_load_valid_r <= _T_4341 @[el2_lsu_bus_buffer.scala 752:34] - reg _T_4342 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 755:44] - _T_4342 <= io.lsu_axi_awvalid @[el2_lsu_bus_buffer.scala 755:44] - lsu_axi_awvalid_q <= _T_4342 @[el2_lsu_bus_buffer.scala 755:34] - reg _T_4343 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 756:44] - _T_4343 <= io.lsu_axi_awready @[el2_lsu_bus_buffer.scala 756:44] - lsu_axi_awready_q <= _T_4343 @[el2_lsu_bus_buffer.scala 756:34] - reg _T_4344 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 757:44] - _T_4344 <= io.lsu_axi_wvalid @[el2_lsu_bus_buffer.scala 757:44] - lsu_axi_wvalid_q <= _T_4344 @[el2_lsu_bus_buffer.scala 757:34] - reg _T_4345 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 758:44] - _T_4345 <= io.lsu_axi_wready @[el2_lsu_bus_buffer.scala 758:44] - lsu_axi_wready_q <= _T_4345 @[el2_lsu_bus_buffer.scala 758:34] - reg _T_4346 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 759:44] - _T_4346 <= io.lsu_axi_arvalid @[el2_lsu_bus_buffer.scala 759:44] - lsu_axi_arvalid_q <= _T_4346 @[el2_lsu_bus_buffer.scala 759:34] - reg _T_4347 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 760:44] - _T_4347 <= io.lsu_axi_arready @[el2_lsu_bus_buffer.scala 760:44] - lsu_axi_arready_q <= _T_4347 @[el2_lsu_bus_buffer.scala 760:34] - reg _T_4348 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 761:44] - _T_4348 <= io.lsu_axi_bvalid @[el2_lsu_bus_buffer.scala 761:44] - lsu_axi_bvalid_q <= _T_4348 @[el2_lsu_bus_buffer.scala 761:34] - reg _T_4349 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 762:44] - _T_4349 <= io.lsu_axi_bready @[el2_lsu_bus_buffer.scala 762:44] - lsu_axi_bready_q <= _T_4349 @[el2_lsu_bus_buffer.scala 762:34] - reg _T_4350 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 763:44] - _T_4350 <= io.lsu_axi_rvalid @[el2_lsu_bus_buffer.scala 763:44] - lsu_axi_rvalid_q <= _T_4350 @[el2_lsu_bus_buffer.scala 763:34] - reg _T_4351 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 764:44] - _T_4351 <= io.lsu_axi_rready @[el2_lsu_bus_buffer.scala 764:44] - lsu_axi_rready_q <= _T_4351 @[el2_lsu_bus_buffer.scala 764:34] - reg _T_4352 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 765:44] - _T_4352 <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 765:44] - lsu_axi_bid_q <= _T_4352 @[el2_lsu_bus_buffer.scala 765:34] - reg _T_4353 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 766:44] - _T_4353 <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 766:44] - lsu_axi_rid_q <= _T_4353 @[el2_lsu_bus_buffer.scala 766:34] - reg _T_4354 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 767:44] - _T_4354 <= io.lsu_axi_bresp @[el2_lsu_bus_buffer.scala 767:44] - lsu_axi_bresp_q <= _T_4354 @[el2_lsu_bus_buffer.scala 767:34] - reg _T_4355 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 768:44] - _T_4355 <= io.lsu_axi_rresp @[el2_lsu_bus_buffer.scala 768:44] - lsu_axi_rresp_q <= _T_4355 @[el2_lsu_bus_buffer.scala 768:34] - io.ld_fwddata_buf_lo <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 772:37] - io.ld_fwddata_buf_hi <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 773:37] - node _T_4356 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4357 = and(_T_4356, buf_error[0]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4358 = and(_T_4357, buf_write[0]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4359 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4360 = and(_T_4359, buf_error[1]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4361 = and(_T_4360, buf_write[1]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4362 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4363 = and(_T_4362, buf_error[2]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4364 = and(_T_4363, buf_write[2]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4365 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 775:87] - node _T_4366 = and(_T_4365, buf_error[3]) @[el2_lsu_bus_buffer.scala 775:99] - node _T_4367 = and(_T_4366, buf_write[3]) @[el2_lsu_bus_buffer.scala 775:114] - node _T_4368 = mux(_T_4358, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4369 = mux(_T_4361, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4370 = mux(_T_4364, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4371 = mux(_T_4367, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] - node _T_4372 = or(_T_4368, _T_4369) @[Mux.scala 27:72] - node _T_4373 = or(_T_4372, _T_4370) @[Mux.scala 27:72] - node _T_4374 = or(_T_4373, _T_4371) @[Mux.scala 27:72] - wire _T_4375 : UInt<2> @[Mux.scala 27:72] - _T_4375 <= _T_4374 @[Mux.scala 27:72] - lsu_imprecise_error_store_tag <= _T_4375 @[el2_lsu_bus_buffer.scala 775:37] - node _T_4376 = not(io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 776:74] - node _T_4377 = and(io.lsu_nonblock_load_data_error, _T_4376) @[el2_lsu_bus_buffer.scala 776:72] - io.lsu_imprecise_error_load_any <= _T_4377 @[el2_lsu_bus_buffer.scala 776:37] - node _T_4378 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4379 = and(io.lsu_bus_clk_en_q, _T_4378) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4380 = and(_T_4379, buf_error[0]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4381 = and(_T_4380, buf_write[0]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4382 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4383 = and(io.lsu_bus_clk_en_q, _T_4382) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4384 = and(_T_4383, buf_error[1]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4385 = and(_T_4384, buf_write[1]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4386 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4387 = and(io.lsu_bus_clk_en_q, _T_4386) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4388 = and(_T_4387, buf_error[2]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4389 = and(_T_4388, buf_write[2]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4390 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 777:107] - node _T_4391 = and(io.lsu_bus_clk_en_q, _T_4390) @[el2_lsu_bus_buffer.scala 777:91] - node _T_4392 = and(_T_4391, buf_error[3]) @[el2_lsu_bus_buffer.scala 777:119] - node _T_4393 = and(_T_4392, buf_write[3]) @[el2_lsu_bus_buffer.scala 777:134] - node _T_4394 = or(_T_4381, _T_4385) @[el2_lsu_bus_buffer.scala 777:158] - node _T_4395 = or(_T_4394, _T_4389) @[el2_lsu_bus_buffer.scala 777:158] - node _T_4396 = or(_T_4395, _T_4393) @[el2_lsu_bus_buffer.scala 777:158] - io.lsu_imprecise_error_store_any <= _T_4396 @[el2_lsu_bus_buffer.scala 777:37] - node _T_4397 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 778:43] - io.lsu_imprecise_error_addr_any <= _T_4397 @[el2_lsu_bus_buffer.scala 778:37] - bus_pend_trxnQ <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 780:37] - bus_pend_trxn <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 781:37] - bus_pend_trxn_ns <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 782:37] - lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 783:37] - io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 784:37] - node _T_4398 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 786:60] - node _T_4399 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 786:103] - node _T_4400 = or(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 786:82] - node _T_4401 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 786:146] - node _T_4402 = or(_T_4400, _T_4401) @[el2_lsu_bus_buffer.scala 786:124] - io.lsu_pmu_bus_trxn <= _T_4402 @[el2_lsu_bus_buffer.scala 786:37] - node _T_4403 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 787:56] - node _T_4404 = and(_T_4403, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 787:73] - io.lsu_pmu_bus_misaligned <= _T_4404 @[el2_lsu_bus_buffer.scala 787:37] - node _T_4405 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 788:72] - io.lsu_pmu_bus_error <= _T_4405 @[el2_lsu_bus_buffer.scala 788:37] - node _T_4406 = not(io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 789:62] - node _T_4407 = and(io.lsu_axi_awvalid, _T_4406) @[el2_lsu_bus_buffer.scala 789:60] - node _T_4408 = not(io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 789:105] - node _T_4409 = and(io.lsu_axi_wvalid, _T_4408) @[el2_lsu_bus_buffer.scala 789:103] - node _T_4410 = or(_T_4407, _T_4409) @[el2_lsu_bus_buffer.scala 789:82] - node _T_4411 = not(io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 789:149] - node _T_4412 = and(io.lsu_axi_arvalid, _T_4411) @[el2_lsu_bus_buffer.scala 789:147] - node _T_4413 = or(_T_4410, _T_4412) @[el2_lsu_bus_buffer.scala 789:125] - io.lsu_pmu_bus_busy <= _T_4413 @[el2_lsu_bus_buffer.scala 789:37] - node _T_4414 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 791:51] - node _T_4415 = not(obuf_cmd_done) @[el2_lsu_bus_buffer.scala 791:66] - node _T_4416 = and(_T_4414, _T_4415) @[el2_lsu_bus_buffer.scala 791:64] - node _T_4417 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 791:83] - node _T_4418 = and(_T_4416, _T_4417) @[el2_lsu_bus_buffer.scala 791:81] - io.lsu_axi_awvalid <= _T_4418 @[el2_lsu_bus_buffer.scala 791:37] - io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 792:37] - node _T_4419 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 793:84] - node _T_4420 = cat(_T_4419, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_4421 = mux(obuf_sideeffect, obuf_addr, _T_4420) @[el2_lsu_bus_buffer.scala 793:43] - io.lsu_axi_awaddr <= _T_4421 @[el2_lsu_bus_buffer.scala 793:37] - node _T_4422 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 794:49] - io.lsu_axi_awregion <= _T_4422 @[el2_lsu_bus_buffer.scala 794:37] - io.lsu_axi_awlen <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 795:37] - node _T_4423 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] - node _T_4424 = mux(obuf_sideeffect, _T_4423, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 796:43] - io.lsu_axi_awsize <= _T_4424 @[el2_lsu_bus_buffer.scala 796:37] - io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 797:37] - io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 798:37] - node _T_4425 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 799:43] - io.lsu_axi_awcache <= _T_4425 @[el2_lsu_bus_buffer.scala 799:37] - io.lsu_axi_awprot <= UInt<3>("h00") @[el2_lsu_bus_buffer.scala 800:37] - io.lsu_axi_awqos <= UInt<4>("h00") @[el2_lsu_bus_buffer.scala 801:37] - node _T_4426 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 803:51] - node _T_4427 = not(obuf_data_done) @[el2_lsu_bus_buffer.scala 803:66] - node _T_4428 = and(_T_4426, _T_4427) @[el2_lsu_bus_buffer.scala 803:64] - node _T_4429 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 803:84] - node _T_4430 = and(_T_4428, _T_4429) @[el2_lsu_bus_buffer.scala 803:82] - io.lsu_axi_wvalid <= _T_4430 @[el2_lsu_bus_buffer.scala 803:37] - io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 804:37] - node _T_4431 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] - node _T_4432 = mux(_T_4431, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] - node _T_4433 = and(obuf_byteen, _T_4432) @[el2_lsu_bus_buffer.scala 805:52] - io.lsu_axi_wstrb <= _T_4433 @[el2_lsu_bus_buffer.scala 805:37] - io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 806:37] - node _T_4434 = not(obuf_write) @[el2_lsu_bus_buffer.scala 808:53] - node _T_4435 = and(obuf_valid, _T_4434) @[el2_lsu_bus_buffer.scala 808:51] - node _T_4436 = not(obuf_nosend) @[el2_lsu_bus_buffer.scala 808:67] - node _T_4437 = and(_T_4435, _T_4436) @[el2_lsu_bus_buffer.scala 808:65] - node _T_4438 = not(bus_addr_match_pending) @[el2_lsu_bus_buffer.scala 808:82] - node _T_4439 = and(_T_4437, _T_4438) @[el2_lsu_bus_buffer.scala 808:80] - io.lsu_axi_arvalid <= _T_4439 @[el2_lsu_bus_buffer.scala 808:37] - io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 809:37] - io.lsu_axi_araddr <= io.lsu_axi_awaddr @[el2_lsu_bus_buffer.scala 810:37] - node _T_4440 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 811:49] - io.lsu_axi_arregion <= _T_4440 @[el2_lsu_bus_buffer.scala 811:37] - io.lsu_axi_arlen <= UInt<8>("h00") @[el2_lsu_bus_buffer.scala 812:37] - io.lsu_axi_arsize <= io.lsu_axi_awsize @[el2_lsu_bus_buffer.scala 813:37] - io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 814:37] - io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 815:37] - io.lsu_axi_arcache <= io.lsu_axi_awcache @[el2_lsu_bus_buffer.scala 816:37] - io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 817:37] - io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 818:37] - io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 820:37] - io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 821:37] + buf_nomerge[3] <= _T_4296 @[el2_lsu_bus_buffer.scala 558:20] + node _T_4297 = bits(buf_dualhi_in, 3, 3) @[el2_lsu_bus_buffer.scala 559:78] + node _T_4298 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 559:111] + reg _T_4299 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4298 : @[Reg.scala 28:19] + _T_4299 <= _T_4297 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_dualhi[3] <= _T_4299 @[el2_lsu_bus_buffer.scala 559:19] + node _T_4300 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4301 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4300 : @[Reg.scala 28:19] + _T_4301 <= buf_ldfwd_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4302 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4303 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4302 : @[Reg.scala 28:19] + _T_4303 <= buf_ldfwd_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4304 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4305 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4304 : @[Reg.scala 28:19] + _T_4305 <= buf_ldfwd_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4306 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 562:131] + reg _T_4307 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4306 : @[Reg.scala 28:19] + _T_4307 <= buf_ldfwd_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4308 = cat(_T_4307, _T_4305) @[Cat.scala 29:58] + node _T_4309 = cat(_T_4308, _T_4303) @[Cat.scala 29:58] + node _T_4310 = cat(_T_4309, _T_4301) @[Cat.scala 29:58] + buf_ldfwd <= _T_4310 @[el2_lsu_bus_buffer.scala 562:13] + node _T_4311 = bits(buf_ldfwd_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4312 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4311 : @[Reg.scala 28:19] + _T_4312 <= buf_ldfwdtag_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4313 = bits(buf_ldfwd_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4314 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4313 : @[Reg.scala 28:19] + _T_4314 <= buf_ldfwdtag_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4315 = bits(buf_ldfwd_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4316 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4315 : @[Reg.scala 28:19] + _T_4316 <= buf_ldfwdtag_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4317 = bits(buf_ldfwd_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 563:132] + reg _T_4318 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4317 : @[Reg.scala 28:19] + _T_4318 <= buf_ldfwdtag_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_ldfwdtag[0] <= _T_4312 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[1] <= _T_4314 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[2] <= _T_4316 @[el2_lsu_bus_buffer.scala 563:16] + buf_ldfwdtag[3] <= _T_4318 @[el2_lsu_bus_buffer.scala 563:16] + node _T_4319 = bits(buf_sideeffect_in, 0, 0) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4320 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4321 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4320 : @[Reg.scala 28:19] + _T_4321 <= _T_4319 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4322 = bits(buf_sideeffect_in, 1, 1) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4323 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4324 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4323 : @[Reg.scala 28:19] + _T_4324 <= _T_4322 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4325 = bits(buf_sideeffect_in, 2, 2) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4326 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4327 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4326 : @[Reg.scala 28:19] + _T_4327 <= _T_4325 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4328 = bits(buf_sideeffect_in, 3, 3) @[el2_lsu_bus_buffer.scala 564:105] + node _T_4329 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 564:138] + reg _T_4330 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4329 : @[Reg.scala 28:19] + _T_4330 <= _T_4328 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4331 = cat(_T_4330, _T_4327) @[Cat.scala 29:58] + node _T_4332 = cat(_T_4331, _T_4324) @[Cat.scala 29:58] + node _T_4333 = cat(_T_4332, _T_4321) @[Cat.scala 29:58] + buf_sideeffect <= _T_4333 @[el2_lsu_bus_buffer.scala 564:18] + node _T_4334 = bits(buf_unsign_in, 0, 0) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4335 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4336 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4335 : @[Reg.scala 28:19] + _T_4336 <= _T_4334 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4337 = bits(buf_unsign_in, 1, 1) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4338 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4339 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4338 : @[Reg.scala 28:19] + _T_4339 <= _T_4337 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4340 = bits(buf_unsign_in, 2, 2) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4341 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4342 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4341 : @[Reg.scala 28:19] + _T_4342 <= _T_4340 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4343 = bits(buf_unsign_in, 3, 3) @[el2_lsu_bus_buffer.scala 565:97] + node _T_4344 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 565:130] + reg _T_4345 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4344 : @[Reg.scala 28:19] + _T_4345 <= _T_4343 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4346 = cat(_T_4345, _T_4342) @[Cat.scala 29:58] + node _T_4347 = cat(_T_4346, _T_4339) @[Cat.scala 29:58] + node _T_4348 = cat(_T_4347, _T_4336) @[Cat.scala 29:58] + buf_unsign <= _T_4348 @[el2_lsu_bus_buffer.scala 565:14] + node _T_4349 = bits(buf_write_in, 0, 0) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4350 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4351 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4350 : @[Reg.scala 28:19] + _T_4351 <= _T_4349 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4352 = bits(buf_write_in, 1, 1) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4353 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4354 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4353 : @[Reg.scala 28:19] + _T_4354 <= _T_4352 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4355 = bits(buf_write_in, 2, 2) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4356 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4357 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4356 : @[Reg.scala 28:19] + _T_4357 <= _T_4355 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4358 = bits(buf_write_in, 3, 3) @[el2_lsu_bus_buffer.scala 566:95] + node _T_4359 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 566:128] + reg _T_4360 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4359 : @[Reg.scala 28:19] + _T_4360 <= _T_4358 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4361 = cat(_T_4360, _T_4357) @[Cat.scala 29:58] + node _T_4362 = cat(_T_4361, _T_4354) @[Cat.scala 29:58] + node _T_4363 = cat(_T_4362, _T_4351) @[Cat.scala 29:58] + buf_write <= _T_4363 @[el2_lsu_bus_buffer.scala 566:13] + node _T_4364 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4365 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4364 : @[Reg.scala 28:19] + _T_4365 <= buf_sz_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4366 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4367 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4366 : @[Reg.scala 28:19] + _T_4367 <= buf_sz_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4368 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4369 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4368 : @[Reg.scala 28:19] + _T_4369 <= buf_sz_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4370 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 567:117] + reg _T_4371 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4370 : @[Reg.scala 28:19] + _T_4371 <= buf_sz_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_sz[0] <= _T_4365 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[1] <= _T_4367 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[2] <= _T_4369 @[el2_lsu_bus_buffer.scala 567:10] + buf_sz[3] <= _T_4371 @[el2_lsu_bus_buffer.scala 567:10] + node _T_4372 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 508:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_4.io.en <= _T_4372 @[el2_lib.scala 511:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4373 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4373 <= buf_addr_in[0] @[el2_lib.scala 514:16] + node _T_4374 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_5 of rvclkhdr_5 @[el2_lib.scala 508:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_5.io.en <= _T_4374 @[el2_lib.scala 511:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4375 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4375 <= buf_addr_in[1] @[el2_lib.scala 514:16] + node _T_4376 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_6 of rvclkhdr_6 @[el2_lib.scala 508:23] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_6.io.en <= _T_4376 @[el2_lib.scala 511:17] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4377 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4377 <= buf_addr_in[2] @[el2_lib.scala 514:16] + node _T_4378 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 568:80] + inst rvclkhdr_7 of rvclkhdr_7 @[el2_lib.scala 508:23] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_7.io.en <= _T_4378 @[el2_lib.scala 511:17] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4379 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4379 <= buf_addr_in[3] @[el2_lib.scala 514:16] + buf_addr[0] <= _T_4373 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[1] <= _T_4375 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[2] <= _T_4377 @[el2_lsu_bus_buffer.scala 568:12] + buf_addr[3] <= _T_4379 @[el2_lsu_bus_buffer.scala 568:12] + node _T_4380 = bits(buf_wr_en[0], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4381 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4380 : @[Reg.scala 28:19] + _T_4381 <= buf_byteen_in[0] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4382 = bits(buf_wr_en[1], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4383 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4382 : @[Reg.scala 28:19] + _T_4383 <= buf_byteen_in[1] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4384 = bits(buf_wr_en[2], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4385 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4384 : @[Reg.scala 28:19] + _T_4385 <= buf_byteen_in[2] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + node _T_4386 = bits(buf_wr_en[3], 0, 0) @[el2_lsu_bus_buffer.scala 569:125] + reg _T_4387 : UInt, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_4386 : @[Reg.scala 28:19] + _T_4387 <= buf_byteen_in[3] @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen[0] <= _T_4381 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[1] <= _T_4383 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[2] <= _T_4385 @[el2_lsu_bus_buffer.scala 569:14] + buf_byteen[3] <= _T_4387 @[el2_lsu_bus_buffer.scala 569:14] + inst rvclkhdr_8 of rvclkhdr_8 @[el2_lib.scala 508:23] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_8.io.en <= buf_data_en[0] @[el2_lib.scala 511:17] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4388 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4388 <= buf_data_in[0] @[el2_lib.scala 514:16] + inst rvclkhdr_9 of rvclkhdr_9 @[el2_lib.scala 508:23] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_9.io.en <= buf_data_en[1] @[el2_lib.scala 511:17] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4389 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4389 <= buf_data_in[1] @[el2_lib.scala 514:16] + inst rvclkhdr_10 of rvclkhdr_10 @[el2_lib.scala 508:23] + rvclkhdr_10.clock <= clock + rvclkhdr_10.reset <= reset + rvclkhdr_10.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_10.io.en <= buf_data_en[2] @[el2_lib.scala 511:17] + rvclkhdr_10.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4390 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4390 <= buf_data_in[2] @[el2_lib.scala 514:16] + inst rvclkhdr_11 of rvclkhdr_11 @[el2_lib.scala 508:23] + rvclkhdr_11.clock <= clock + rvclkhdr_11.reset <= reset + rvclkhdr_11.io.clk <= clock @[el2_lib.scala 510:18] + rvclkhdr_11.io.en <= buf_data_en[3] @[el2_lib.scala 511:17] + rvclkhdr_11.io.scan_mode <= io.scan_mode @[el2_lib.scala 512:24] + reg _T_4391 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 514:16] + _T_4391 <= buf_data_in[3] @[el2_lib.scala 514:16] + buf_data[0] <= _T_4388 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[1] <= _T_4389 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[2] <= _T_4390 @[el2_lsu_bus_buffer.scala 570:12] + buf_data[3] <= _T_4391 @[el2_lsu_bus_buffer.scala 570:12] + node _T_4392 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4393 = mux(buf_error_en[0], UInt<1>("h01"), _T_4392) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4394 = eq(buf_rst[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4395 = and(_T_4393, _T_4394) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4396 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4396 <= _T_4395 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4397 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4398 = mux(buf_error_en[1], UInt<1>("h01"), _T_4397) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4399 = eq(buf_rst[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4400 = and(_T_4398, _T_4399) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4401 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4401 <= _T_4400 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4402 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4403 = mux(buf_error_en[2], UInt<1>("h01"), _T_4402) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4404 = eq(buf_rst[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4405 = and(_T_4403, _T_4404) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4406 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4406 <= _T_4405 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4407 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 571:119] + node _T_4408 = mux(buf_error_en[3], UInt<1>("h01"), _T_4407) @[el2_lsu_bus_buffer.scala 571:84] + node _T_4409 = eq(buf_rst[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 571:126] + node _T_4410 = and(_T_4408, _T_4409) @[el2_lsu_bus_buffer.scala 571:124] + reg _T_4411 : UInt<1>, io.lsu_bus_buf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 571:80] + _T_4411 <= _T_4410 @[el2_lsu_bus_buffer.scala 571:80] + node _T_4412 = cat(_T_4411, _T_4406) @[Cat.scala 29:58] + node _T_4413 = cat(_T_4412, _T_4401) @[Cat.scala 29:58] + node _T_4414 = cat(_T_4413, _T_4396) @[Cat.scala 29:58] + buf_error <= _T_4414 @[el2_lsu_bus_buffer.scala 571:13] + node _T_4415 = cat(io.lsu_busreq_m, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4416 = mux(io.ldst_dual_m, _T_4415, io.lsu_busreq_m) @[el2_lsu_bus_buffer.scala 574:28] + node _T_4417 = cat(io.lsu_busreq_r, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_4418 = mux(io.ldst_dual_r, _T_4417, io.lsu_busreq_r) @[el2_lsu_bus_buffer.scala 574:94] + node _T_4419 = add(_T_4416, _T_4418) @[el2_lsu_bus_buffer.scala 574:88] + node _T_4420 = add(_T_4419, ibuf_valid) @[el2_lsu_bus_buffer.scala 574:154] + node _T_4421 = neq(buf_state[0], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4422 = neq(buf_state[1], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4423 = neq(buf_state[2], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4424 = neq(buf_state[3], UInt<3>("h00")) @[el2_lsu_bus_buffer.scala 574:190] + node _T_4425 = add(_T_4421, _T_4422) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4426 = add(_T_4425, _T_4423) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4427 = add(_T_4426, _T_4424) @[el2_lsu_bus_buffer.scala 574:217] + node _T_4428 = add(_T_4420, _T_4427) @[el2_lsu_bus_buffer.scala 574:169] + node buf_numvld_any = tail(_T_4428, 1) @[el2_lsu_bus_buffer.scala 574:169] + node _T_4429 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4430 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4431 = and(_T_4429, _T_4430) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4432 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4433 = and(_T_4431, _T_4432) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4434 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4435 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4436 = and(_T_4434, _T_4435) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4437 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4438 = and(_T_4436, _T_4437) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4439 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4440 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4441 = and(_T_4439, _T_4440) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4442 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4443 = and(_T_4441, _T_4442) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4444 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 575:60] + node _T_4445 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 575:79] + node _T_4446 = and(_T_4444, _T_4445) @[el2_lsu_bus_buffer.scala 575:64] + node _T_4447 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 575:91] + node _T_4448 = and(_T_4446, _T_4447) @[el2_lsu_bus_buffer.scala 575:89] + node _T_4449 = add(_T_4448, _T_4443) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4450 = add(_T_4449, _T_4438) @[el2_lsu_bus_buffer.scala 575:142] + node _T_4451 = add(_T_4450, _T_4433) @[el2_lsu_bus_buffer.scala 575:142] + buf_numvld_wrcmd_any <= _T_4451 @[el2_lsu_bus_buffer.scala 575:24] + node _T_4452 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4453 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4454 = and(_T_4452, _T_4453) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4455 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4456 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4457 = and(_T_4455, _T_4456) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4458 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4459 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4460 = and(_T_4458, _T_4459) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4461 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 576:63] + node _T_4462 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 576:75] + node _T_4463 = and(_T_4461, _T_4462) @[el2_lsu_bus_buffer.scala 576:73] + node _T_4464 = add(_T_4463, _T_4460) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4465 = add(_T_4464, _T_4457) @[el2_lsu_bus_buffer.scala 576:126] + node _T_4466 = add(_T_4465, _T_4454) @[el2_lsu_bus_buffer.scala 576:126] + buf_numvld_cmd_any <= _T_4466 @[el2_lsu_bus_buffer.scala 576:22] + node _T_4467 = eq(buf_state[0], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4468 = eq(buf_state[0], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4469 = eq(buf_cmd_state_bus_en[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4470 = and(_T_4468, _T_4469) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4471 = or(_T_4467, _T_4470) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4472 = eq(buf_state[1], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4473 = eq(buf_state[1], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4474 = eq(buf_cmd_state_bus_en[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4475 = and(_T_4473, _T_4474) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4476 = or(_T_4472, _T_4475) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4477 = eq(buf_state[2], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4478 = eq(buf_state[2], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4479 = eq(buf_cmd_state_bus_en[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4480 = and(_T_4478, _T_4479) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4481 = or(_T_4477, _T_4480) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4482 = eq(buf_state[3], UInt<3>("h01")) @[el2_lsu_bus_buffer.scala 577:63] + node _T_4483 = eq(buf_state[3], UInt<3>("h02")) @[el2_lsu_bus_buffer.scala 577:90] + node _T_4484 = eq(buf_cmd_state_bus_en[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 577:102] + node _T_4485 = and(_T_4483, _T_4484) @[el2_lsu_bus_buffer.scala 577:100] + node _T_4486 = or(_T_4482, _T_4485) @[el2_lsu_bus_buffer.scala 577:74] + node _T_4487 = add(_T_4486, _T_4481) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4488 = add(_T_4487, _T_4476) @[el2_lsu_bus_buffer.scala 577:154] + node _T_4489 = add(_T_4488, _T_4471) @[el2_lsu_bus_buffer.scala 577:154] + buf_numvld_pend_any <= _T_4489 @[el2_lsu_bus_buffer.scala 577:23] + node _T_4490 = eq(buf_state[0], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4491 = eq(buf_state[1], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4492 = eq(buf_state[2], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4493 = eq(buf_state[3], UInt<3>("h05")) @[el2_lsu_bus_buffer.scala 578:61] + node _T_4494 = or(_T_4493, _T_4492) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4495 = or(_T_4494, _T_4491) @[el2_lsu_bus_buffer.scala 578:93] + node _T_4496 = or(_T_4495, _T_4490) @[el2_lsu_bus_buffer.scala 578:93] + any_done_wait_state <= _T_4496 @[el2_lsu_bus_buffer.scala 578:23] + node _T_4497 = orr(buf_numvld_pend_any) @[el2_lsu_bus_buffer.scala 579:53] + io.lsu_bus_buffer_pend_any <= _T_4497 @[el2_lsu_bus_buffer.scala 579:30] + node _T_4498 = and(io.ldst_dual_d, io.dec_lsu_valid_raw_d) @[el2_lsu_bus_buffer.scala 580:52] + node _T_4499 = geq(buf_numvld_any, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 580:92] + node _T_4500 = eq(buf_numvld_any, UInt<3>("h04")) @[el2_lsu_bus_buffer.scala 580:121] + node _T_4501 = mux(_T_4498, _T_4499, _T_4500) @[el2_lsu_bus_buffer.scala 580:36] + io.lsu_bus_buffer_full_any <= _T_4501 @[el2_lsu_bus_buffer.scala 580:30] + node _T_4502 = orr(buf_state[0]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4503 = orr(buf_state[1]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4504 = orr(buf_state[2]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4505 = orr(buf_state[3]) @[el2_lsu_bus_buffer.scala 581:52] + node _T_4506 = or(_T_4502, _T_4503) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4507 = or(_T_4506, _T_4504) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4508 = or(_T_4507, _T_4505) @[el2_lsu_bus_buffer.scala 581:65] + node _T_4509 = eq(_T_4508, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:34] + node _T_4510 = eq(ibuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:72] + node _T_4511 = and(_T_4509, _T_4510) @[el2_lsu_bus_buffer.scala 581:70] + node _T_4512 = eq(obuf_valid, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 581:86] + node _T_4513 = and(_T_4511, _T_4512) @[el2_lsu_bus_buffer.scala 581:84] + io.lsu_bus_buffer_empty_any <= _T_4513 @[el2_lsu_bus_buffer.scala 581:31] + node _T_4514 = and(io.lsu_busreq_m, io.lsu_pkt_m.valid) @[el2_lsu_bus_buffer.scala 583:51] + node _T_4515 = and(_T_4514, io.lsu_pkt_m.load) @[el2_lsu_bus_buffer.scala 583:72] + node _T_4516 = eq(io.flush_m_up, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:94] + node _T_4517 = and(_T_4515, _T_4516) @[el2_lsu_bus_buffer.scala 583:92] + node _T_4518 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 583:111] + node _T_4519 = and(_T_4517, _T_4518) @[el2_lsu_bus_buffer.scala 583:109] + io.lsu_nonblock_load_valid_m <= _T_4519 @[el2_lsu_bus_buffer.scala 583:32] + io.lsu_nonblock_load_tag_m <= WrPtr0_m @[el2_lsu_bus_buffer.scala 584:30] + wire lsu_nonblock_load_valid_r : UInt<1> + lsu_nonblock_load_valid_r <= UInt<1>("h00") + node _T_4520 = eq(io.lsu_commit_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 586:61] + node _T_4521 = and(lsu_nonblock_load_valid_r, _T_4520) @[el2_lsu_bus_buffer.scala 586:59] + io.lsu_nonblock_load_inv_r <= _T_4521 @[el2_lsu_bus_buffer.scala 586:30] + io.lsu_nonblock_load_inv_tag_r <= WrPtr0_r @[el2_lsu_bus_buffer.scala 587:34] + node _T_4522 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4523 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4524 = and(UInt<1>("h01"), _T_4523) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4525 = eq(_T_4524, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4526 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4527 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4528 = and(UInt<1>("h01"), _T_4527) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4529 = eq(_T_4528, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4530 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4531 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4532 = and(UInt<1>("h01"), _T_4531) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4533 = eq(_T_4532, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4534 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 588:80] + node _T_4535 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 588:127] + node _T_4536 = and(UInt<1>("h01"), _T_4535) @[el2_lsu_bus_buffer.scala 588:116] + node _T_4537 = eq(_T_4536, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 588:95] + node _T_4538 = mux(_T_4522, _T_4525, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4539 = mux(_T_4526, _T_4529, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4540 = mux(_T_4530, _T_4533, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4541 = mux(_T_4534, _T_4537, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4542 = or(_T_4538, _T_4539) @[Mux.scala 27:72] + node _T_4543 = or(_T_4542, _T_4540) @[Mux.scala 27:72] + node _T_4544 = or(_T_4543, _T_4541) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_load_data_ready <= _T_4544 @[Mux.scala 27:72] + node _T_4545 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4546 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4547 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4548 = eq(_T_4547, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4549 = and(_T_4546, _T_4548) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4550 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4551 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4552 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4553 = eq(_T_4552, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4554 = and(_T_4551, _T_4553) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4555 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4556 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4557 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4558 = eq(_T_4557, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4559 = and(_T_4556, _T_4558) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4560 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 589:80] + node _T_4561 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 589:104] + node _T_4562 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 589:120] + node _T_4563 = eq(_T_4562, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 589:110] + node _T_4564 = and(_T_4561, _T_4563) @[el2_lsu_bus_buffer.scala 589:108] + node _T_4565 = mux(_T_4545, _T_4549, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4566 = mux(_T_4550, _T_4554, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4567 = mux(_T_4555, _T_4559, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4568 = mux(_T_4560, _T_4564, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4569 = or(_T_4565, _T_4566) @[Mux.scala 27:72] + node _T_4570 = or(_T_4569, _T_4567) @[Mux.scala 27:72] + node _T_4571 = or(_T_4570, _T_4568) @[Mux.scala 27:72] + wire _T_4572 : UInt<1> @[Mux.scala 27:72] + _T_4572 <= _T_4571 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_error <= _T_4572 @[el2_lsu_bus_buffer.scala 589:35] + node _T_4573 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4574 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4575 = eq(_T_4574, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4576 = and(_T_4573, _T_4575) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4577 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4578 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4579 = or(_T_4577, _T_4578) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4580 = and(_T_4576, _T_4579) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4581 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4582 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4583 = eq(_T_4582, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4584 = and(_T_4581, _T_4583) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4585 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4586 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4587 = or(_T_4585, _T_4586) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4588 = and(_T_4584, _T_4587) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4589 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4590 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4591 = eq(_T_4590, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4592 = and(_T_4589, _T_4591) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4593 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4594 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4595 = or(_T_4593, _T_4594) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4596 = and(_T_4592, _T_4595) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4597 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 590:79] + node _T_4598 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 590:102] + node _T_4599 = eq(_T_4598, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:92] + node _T_4600 = and(_T_4597, _T_4599) @[el2_lsu_bus_buffer.scala 590:90] + node _T_4601 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:109] + node _T_4602 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 590:124] + node _T_4603 = or(_T_4601, _T_4602) @[el2_lsu_bus_buffer.scala 590:122] + node _T_4604 = and(_T_4600, _T_4603) @[el2_lsu_bus_buffer.scala 590:106] + node _T_4605 = mux(_T_4580, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4606 = mux(_T_4588, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4607 = mux(_T_4596, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4608 = mux(_T_4604, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4609 = or(_T_4605, _T_4606) @[Mux.scala 27:72] + node _T_4610 = or(_T_4609, _T_4607) @[Mux.scala 27:72] + node _T_4611 = or(_T_4610, _T_4608) @[Mux.scala 27:72] + wire _T_4612 : UInt<2> @[Mux.scala 27:72] + _T_4612 <= _T_4611 @[Mux.scala 27:72] + io.lsu_nonblock_load_data_tag <= _T_4612 @[el2_lsu_bus_buffer.scala 590:33] + node _T_4613 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4614 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4615 = eq(_T_4614, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4616 = and(_T_4613, _T_4615) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4617 = eq(buf_dual[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4618 = eq(buf_dualhi[0], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4619 = or(_T_4617, _T_4618) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4620 = and(_T_4616, _T_4619) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4621 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4622 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4623 = eq(_T_4622, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4624 = and(_T_4621, _T_4623) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4625 = eq(buf_dual[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4626 = eq(buf_dualhi[1], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4627 = or(_T_4625, _T_4626) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4628 = and(_T_4624, _T_4627) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4629 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4630 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4631 = eq(_T_4630, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4632 = and(_T_4629, _T_4631) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4633 = eq(buf_dual[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4634 = eq(buf_dualhi[2], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4635 = or(_T_4633, _T_4634) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4636 = and(_T_4632, _T_4635) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4637 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 591:78] + node _T_4638 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 591:101] + node _T_4639 = eq(_T_4638, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:91] + node _T_4640 = and(_T_4637, _T_4639) @[el2_lsu_bus_buffer.scala 591:89] + node _T_4641 = eq(buf_dual[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:108] + node _T_4642 = eq(buf_dualhi[3], UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 591:123] + node _T_4643 = or(_T_4641, _T_4642) @[el2_lsu_bus_buffer.scala 591:121] + node _T_4644 = and(_T_4640, _T_4643) @[el2_lsu_bus_buffer.scala 591:105] + node _T_4645 = mux(_T_4620, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4646 = mux(_T_4628, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4647 = mux(_T_4636, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4648 = mux(_T_4644, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4649 = or(_T_4645, _T_4646) @[Mux.scala 27:72] + node _T_4650 = or(_T_4649, _T_4647) @[Mux.scala 27:72] + node _T_4651 = or(_T_4650, _T_4648) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_lo : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_lo <= _T_4651 @[Mux.scala 27:72] + node _T_4652 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4653 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4654 = eq(_T_4653, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4655 = and(_T_4652, _T_4654) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4656 = and(buf_dual[0], buf_dualhi[0]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4657 = and(_T_4655, _T_4656) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4658 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4659 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4660 = eq(_T_4659, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4661 = and(_T_4658, _T_4660) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4662 = and(buf_dual[1], buf_dualhi[1]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4663 = and(_T_4661, _T_4662) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4664 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4665 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4666 = eq(_T_4665, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4667 = and(_T_4664, _T_4666) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4668 = and(buf_dual[2], buf_dualhi[2]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4669 = and(_T_4667, _T_4668) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4670 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 592:78] + node _T_4671 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 592:101] + node _T_4672 = eq(_T_4671, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 592:91] + node _T_4673 = and(_T_4670, _T_4672) @[el2_lsu_bus_buffer.scala 592:89] + node _T_4674 = and(buf_dual[3], buf_dualhi[3]) @[el2_lsu_bus_buffer.scala 592:120] + node _T_4675 = and(_T_4673, _T_4674) @[el2_lsu_bus_buffer.scala 592:105] + node _T_4676 = mux(_T_4657, buf_data[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4677 = mux(_T_4663, buf_data[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4678 = mux(_T_4669, buf_data[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4679 = mux(_T_4675, buf_data[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4680 = or(_T_4676, _T_4677) @[Mux.scala 27:72] + node _T_4681 = or(_T_4680, _T_4678) @[Mux.scala 27:72] + node _T_4682 = or(_T_4681, _T_4679) @[Mux.scala 27:72] + wire lsu_nonblock_load_data_hi : UInt<32> @[Mux.scala 27:72] + lsu_nonblock_load_data_hi <= _T_4682 @[Mux.scala 27:72] + node _T_4683 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4684 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4685 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4686 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4687 = mux(_T_4683, buf_addr[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4688 = mux(_T_4684, buf_addr[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4689 = mux(_T_4685, buf_addr[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4690 = mux(_T_4686, buf_addr[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4691 = or(_T_4687, _T_4688) @[Mux.scala 27:72] + node _T_4692 = or(_T_4691, _T_4689) @[Mux.scala 27:72] + node _T_4693 = or(_T_4692, _T_4690) @[Mux.scala 27:72] + wire _T_4694 : UInt<32> @[Mux.scala 27:72] + _T_4694 <= _T_4693 @[Mux.scala 27:72] + node lsu_nonblock_addr_offset = bits(_T_4694, 1, 0) @[el2_lsu_bus_buffer.scala 593:83] + node _T_4695 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4696 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4697 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4698 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 112:123] + node _T_4699 = mux(_T_4695, buf_sz[0], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4700 = mux(_T_4696, buf_sz[1], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4701 = mux(_T_4697, buf_sz[2], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4702 = mux(_T_4698, buf_sz[3], UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4703 = or(_T_4699, _T_4700) @[Mux.scala 27:72] + node _T_4704 = or(_T_4703, _T_4701) @[Mux.scala 27:72] + node _T_4705 = or(_T_4704, _T_4702) @[Mux.scala 27:72] + wire lsu_nonblock_sz : UInt<2> @[Mux.scala 27:72] + lsu_nonblock_sz <= _T_4705 @[Mux.scala 27:72] + node _T_4706 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4707 = bits(buf_unsign, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4708 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4709 = bits(buf_unsign, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4710 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4711 = bits(buf_unsign, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4712 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4713 = bits(buf_unsign, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4714 = mux(_T_4706, _T_4707, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4715 = mux(_T_4708, _T_4709, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4716 = mux(_T_4710, _T_4711, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4717 = mux(_T_4712, _T_4713, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4718 = or(_T_4714, _T_4715) @[Mux.scala 27:72] + node _T_4719 = or(_T_4718, _T_4716) @[Mux.scala 27:72] + node _T_4720 = or(_T_4719, _T_4717) @[Mux.scala 27:72] + wire lsu_nonblock_unsign : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_unsign <= _T_4720 @[Mux.scala 27:72] + node _T_4721 = cat(buf_dual[3], buf_dual[2]) @[Cat.scala 29:58] + node _T_4722 = cat(_T_4721, buf_dual[1]) @[Cat.scala 29:58] + node _T_4723 = cat(_T_4722, buf_dual[0]) @[Cat.scala 29:58] + node _T_4724 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4725 = bits(_T_4723, 0, 0) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4726 = eq(io.lsu_nonblock_load_data_tag, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4727 = bits(_T_4723, 1, 1) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4728 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4729 = bits(_T_4723, 2, 2) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4730 = eq(io.lsu_nonblock_load_data_tag, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 111:118] + node _T_4731 = bits(_T_4723, 3, 3) @[el2_lsu_bus_buffer.scala 111:129] + node _T_4732 = mux(_T_4724, _T_4725, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4733 = mux(_T_4726, _T_4727, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4734 = mux(_T_4728, _T_4729, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4735 = mux(_T_4730, _T_4731, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4736 = or(_T_4732, _T_4733) @[Mux.scala 27:72] + node _T_4737 = or(_T_4736, _T_4734) @[Mux.scala 27:72] + node _T_4738 = or(_T_4737, _T_4735) @[Mux.scala 27:72] + wire lsu_nonblock_dual : UInt<1> @[Mux.scala 27:72] + lsu_nonblock_dual <= _T_4738 @[Mux.scala 27:72] + node _T_4739 = cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) @[Cat.scala 29:58] + node _T_4740 = mul(lsu_nonblock_addr_offset, UInt<4>("h08")) @[el2_lsu_bus_buffer.scala 597:121] + node lsu_nonblock_data_unalgn = dshr(_T_4739, _T_4740) @[el2_lsu_bus_buffer.scala 597:92] + node _T_4741 = eq(io.lsu_nonblock_load_data_error, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 599:69] + node _T_4742 = and(lsu_nonblock_load_data_ready, _T_4741) @[el2_lsu_bus_buffer.scala 599:67] + io.lsu_nonblock_load_data_valid <= _T_4742 @[el2_lsu_bus_buffer.scala 599:35] + node _T_4743 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 600:81] + node _T_4744 = and(lsu_nonblock_unsign, _T_4743) @[el2_lsu_bus_buffer.scala 600:63] + node _T_4745 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 600:131] + node _T_4746 = cat(UInt<24>("h00"), _T_4745) @[Cat.scala 29:58] + node _T_4747 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 601:45] + node _T_4748 = and(lsu_nonblock_unsign, _T_4747) @[el2_lsu_bus_buffer.scala 601:26] + node _T_4749 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 601:95] + node _T_4750 = cat(UInt<16>("h00"), _T_4749) @[Cat.scala 29:58] + node _T_4751 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:6] + node _T_4752 = eq(lsu_nonblock_sz, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 602:45] + node _T_4753 = and(_T_4751, _T_4752) @[el2_lsu_bus_buffer.scala 602:27] + node _T_4754 = bits(lsu_nonblock_data_unalgn, 7, 7) @[el2_lsu_bus_buffer.scala 602:93] + node _T_4755 = bits(_T_4754, 0, 0) @[Bitwise.scala 72:15] + node _T_4756 = mux(_T_4755, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12] + node _T_4757 = bits(lsu_nonblock_data_unalgn, 7, 0) @[el2_lsu_bus_buffer.scala 602:123] + node _T_4758 = cat(_T_4756, _T_4757) @[Cat.scala 29:58] + node _T_4759 = eq(lsu_nonblock_unsign, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 603:6] + node _T_4760 = eq(lsu_nonblock_sz, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 603:45] + node _T_4761 = and(_T_4759, _T_4760) @[el2_lsu_bus_buffer.scala 603:27] + node _T_4762 = bits(lsu_nonblock_data_unalgn, 15, 15) @[el2_lsu_bus_buffer.scala 603:93] + node _T_4763 = bits(_T_4762, 0, 0) @[Bitwise.scala 72:15] + node _T_4764 = mux(_T_4763, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] + node _T_4765 = bits(lsu_nonblock_data_unalgn, 15, 0) @[el2_lsu_bus_buffer.scala 603:124] + node _T_4766 = cat(_T_4764, _T_4765) @[Cat.scala 29:58] + node _T_4767 = eq(lsu_nonblock_sz, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 604:21] + node _T_4768 = mux(_T_4744, _T_4746, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4769 = mux(_T_4748, _T_4750, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4770 = mux(_T_4753, _T_4758, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4771 = mux(_T_4761, _T_4766, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4772 = mux(_T_4767, lsu_nonblock_data_unalgn, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4773 = or(_T_4768, _T_4769) @[Mux.scala 27:72] + node _T_4774 = or(_T_4773, _T_4770) @[Mux.scala 27:72] + node _T_4775 = or(_T_4774, _T_4771) @[Mux.scala 27:72] + node _T_4776 = or(_T_4775, _T_4772) @[Mux.scala 27:72] + wire _T_4777 : UInt<64> @[Mux.scala 27:72] + _T_4777 <= _T_4776 @[Mux.scala 27:72] + io.lsu_nonblock_load_data <= _T_4777 @[el2_lsu_bus_buffer.scala 600:29] + node _T_4778 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4779 = bits(buf_sideeffect, 0, 0) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4780 = and(_T_4778, _T_4779) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4781 = and(_T_4780, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4782 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4783 = bits(buf_sideeffect, 1, 1) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4784 = and(_T_4782, _T_4783) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4785 = and(_T_4784, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4786 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4787 = bits(buf_sideeffect, 2, 2) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4788 = and(_T_4786, _T_4787) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4789 = and(_T_4788, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4790 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 605:62] + node _T_4791 = bits(buf_sideeffect, 3, 3) @[el2_lsu_bus_buffer.scala 605:89] + node _T_4792 = and(_T_4790, _T_4791) @[el2_lsu_bus_buffer.scala 605:73] + node _T_4793 = and(_T_4792, io.dec_tlu_sideeffect_posted_disable) @[el2_lsu_bus_buffer.scala 605:93] + node _T_4794 = or(_T_4781, _T_4785) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4795 = or(_T_4794, _T_4789) @[el2_lsu_bus_buffer.scala 605:141] + node _T_4796 = or(_T_4795, _T_4793) @[el2_lsu_bus_buffer.scala 605:141] + bus_sideeffect_pend <= _T_4796 @[el2_lsu_bus_buffer.scala 605:23] + node _T_4797 = eq(buf_state[0], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4798 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4799 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4800 = bits(buf_addr[0], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4801 = eq(_T_4799, _T_4800) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4802 = and(_T_4798, _T_4801) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4803 = eq(obuf_tag0, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4804 = eq(obuf_tag1, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4805 = and(obuf_merge, _T_4804) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4806 = or(_T_4803, _T_4805) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4807 = eq(_T_4806, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4808 = and(_T_4802, _T_4807) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4809 = eq(buf_state[1], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4810 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4811 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4812 = bits(buf_addr[1], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4813 = eq(_T_4811, _T_4812) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4814 = and(_T_4810, _T_4813) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4815 = eq(obuf_tag0, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4816 = eq(obuf_tag1, UInt<1>("h01")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4817 = and(obuf_merge, _T_4816) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4818 = or(_T_4815, _T_4817) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4819 = eq(_T_4818, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4820 = and(_T_4814, _T_4819) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4821 = eq(buf_state[2], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4822 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4823 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4824 = bits(buf_addr[2], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4825 = eq(_T_4823, _T_4824) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4826 = and(_T_4822, _T_4825) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4827 = eq(obuf_tag0, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4828 = eq(obuf_tag1, UInt<2>("h02")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4829 = and(obuf_merge, _T_4828) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4830 = or(_T_4827, _T_4829) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4831 = eq(_T_4830, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4832 = and(_T_4826, _T_4831) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4833 = eq(buf_state[3], UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 606:71] + node _T_4834 = and(UInt<1>("h01"), obuf_valid) @[el2_lsu_bus_buffer.scala 607:25] + node _T_4835 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 607:50] + node _T_4836 = bits(buf_addr[3], 31, 3) @[el2_lsu_bus_buffer.scala 607:70] + node _T_4837 = eq(_T_4835, _T_4836) @[el2_lsu_bus_buffer.scala 607:56] + node _T_4838 = and(_T_4834, _T_4837) @[el2_lsu_bus_buffer.scala 607:38] + node _T_4839 = eq(obuf_tag0, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:92] + node _T_4840 = eq(obuf_tag1, UInt<2>("h03")) @[el2_lsu_bus_buffer.scala 607:126] + node _T_4841 = and(obuf_merge, _T_4840) @[el2_lsu_bus_buffer.scala 607:114] + node _T_4842 = or(_T_4839, _T_4841) @[el2_lsu_bus_buffer.scala 607:100] + node _T_4843 = eq(_T_4842, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 607:80] + node _T_4844 = and(_T_4838, _T_4843) @[el2_lsu_bus_buffer.scala 607:78] + node _T_4845 = mux(_T_4797, _T_4808, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4846 = mux(_T_4809, _T_4820, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4847 = mux(_T_4821, _T_4832, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4848 = mux(_T_4833, _T_4844, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4849 = or(_T_4845, _T_4846) @[Mux.scala 27:72] + node _T_4850 = or(_T_4849, _T_4847) @[Mux.scala 27:72] + node _T_4851 = or(_T_4850, _T_4848) @[Mux.scala 27:72] + wire _T_4852 : UInt<1> @[Mux.scala 27:72] + _T_4852 <= _T_4851 @[Mux.scala 27:72] + bus_addr_match_pending <= _T_4852 @[el2_lsu_bus_buffer.scala 606:26] + node _T_4853 = or(obuf_cmd_done, obuf_data_done) @[el2_lsu_bus_buffer.scala 609:54] + node _T_4854 = mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:75] + node _T_4855 = and(io.lsu_axi_awready, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 609:150] + node _T_4856 = mux(_T_4853, _T_4854, _T_4855) @[el2_lsu_bus_buffer.scala 609:39] + node _T_4857 = mux(obuf_write, _T_4856, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 609:23] + bus_cmd_ready <= _T_4857 @[el2_lsu_bus_buffer.scala 609:17] + node _T_4858 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 610:39] + bus_wcmd_sent <= _T_4858 @[el2_lsu_bus_buffer.scala 610:17] + node _T_4859 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 611:39] + bus_wdata_sent <= _T_4859 @[el2_lsu_bus_buffer.scala 611:18] + node _T_4860 = or(obuf_cmd_done, bus_wcmd_sent) @[el2_lsu_bus_buffer.scala 612:35] + node _T_4861 = or(obuf_data_done, bus_wdata_sent) @[el2_lsu_bus_buffer.scala 612:70] + node _T_4862 = and(_T_4860, _T_4861) @[el2_lsu_bus_buffer.scala 612:52] + node _T_4863 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 612:111] + node _T_4864 = or(_T_4862, _T_4863) @[el2_lsu_bus_buffer.scala 612:89] + bus_cmd_sent <= _T_4864 @[el2_lsu_bus_buffer.scala 612:16] + node _T_4865 = and(io.lsu_axi_rvalid, io.lsu_axi_rready) @[el2_lsu_bus_buffer.scala 613:37] + bus_rsp_read <= _T_4865 @[el2_lsu_bus_buffer.scala 613:16] + node _T_4866 = and(io.lsu_axi_bvalid, io.lsu_axi_bready) @[el2_lsu_bus_buffer.scala 614:38] + bus_rsp_write <= _T_4866 @[el2_lsu_bus_buffer.scala 614:17] + bus_rsp_read_tag <= io.lsu_axi_rid @[el2_lsu_bus_buffer.scala 615:20] + bus_rsp_write_tag <= io.lsu_axi_bid @[el2_lsu_bus_buffer.scala 616:21] + node _T_4867 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 617:60] + node _T_4868 = and(bus_rsp_write, _T_4867) @[el2_lsu_bus_buffer.scala 617:40] + bus_rsp_write_error <= _T_4868 @[el2_lsu_bus_buffer.scala 617:23] + node _T_4869 = neq(io.lsu_axi_bresp, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 618:58] + node _T_4870 = and(bus_rsp_read, _T_4869) @[el2_lsu_bus_buffer.scala 618:38] + bus_rsp_read_error <= _T_4870 @[el2_lsu_bus_buffer.scala 618:22] + bus_rsp_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_buffer.scala 619:17] + node _T_4871 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 622:36] + node _T_4872 = eq(obuf_cmd_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:51] + node _T_4873 = and(_T_4871, _T_4872) @[el2_lsu_bus_buffer.scala 622:49] + node _T_4874 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 622:68] + node _T_4875 = and(_T_4873, _T_4874) @[el2_lsu_bus_buffer.scala 622:66] + io.lsu_axi_awvalid <= _T_4875 @[el2_lsu_bus_buffer.scala 622:22] + io.lsu_axi_awid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 623:19] + node _T_4876 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 624:69] + node _T_4877 = cat(_T_4876, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4878 = mux(obuf_sideeffect, obuf_addr, _T_4877) @[el2_lsu_bus_buffer.scala 624:27] + io.lsu_axi_awaddr <= _T_4878 @[el2_lsu_bus_buffer.scala 624:21] + node _T_4879 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4880 = mux(obuf_sideeffect, _T_4879, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 625:27] + io.lsu_axi_awsize <= _T_4880 @[el2_lsu_bus_buffer.scala 625:21] + io.lsu_axi_awprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 626:21] + node _T_4881 = mux(obuf_sideeffect, UInt<1>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 627:28] + io.lsu_axi_awcache <= _T_4881 @[el2_lsu_bus_buffer.scala 627:22] + node _T_4882 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 628:35] + io.lsu_axi_awregion <= _T_4882 @[el2_lsu_bus_buffer.scala 628:23] + io.lsu_axi_awlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 629:20] + io.lsu_axi_awburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 630:22] + io.lsu_axi_awqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 631:20] + io.lsu_axi_awlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 632:21] + node _T_4883 = and(obuf_valid, obuf_write) @[el2_lsu_bus_buffer.scala 634:35] + node _T_4884 = eq(obuf_data_done, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:50] + node _T_4885 = and(_T_4883, _T_4884) @[el2_lsu_bus_buffer.scala 634:48] + node _T_4886 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 634:68] + node _T_4887 = and(_T_4885, _T_4886) @[el2_lsu_bus_buffer.scala 634:66] + io.lsu_axi_wvalid <= _T_4887 @[el2_lsu_bus_buffer.scala 634:21] + node _T_4888 = bits(obuf_write, 0, 0) @[Bitwise.scala 72:15] + node _T_4889 = mux(_T_4888, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_4890 = and(obuf_byteen, _T_4889) @[el2_lsu_bus_buffer.scala 635:35] + io.lsu_axi_wstrb <= _T_4890 @[el2_lsu_bus_buffer.scala 635:20] + io.lsu_axi_wdata <= obuf_data @[el2_lsu_bus_buffer.scala 636:20] + io.lsu_axi_wlast <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 637:20] + node _T_4891 = eq(obuf_write, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:38] + node _T_4892 = and(obuf_valid, _T_4891) @[el2_lsu_bus_buffer.scala 639:36] + node _T_4893 = eq(obuf_nosend, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:52] + node _T_4894 = and(_T_4892, _T_4893) @[el2_lsu_bus_buffer.scala 639:50] + node _T_4895 = eq(bus_addr_match_pending, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 639:67] + node _T_4896 = and(_T_4894, _T_4895) @[el2_lsu_bus_buffer.scala 639:65] + io.lsu_axi_arvalid <= _T_4896 @[el2_lsu_bus_buffer.scala 639:22] + io.lsu_axi_arid <= obuf_tag0 @[el2_lsu_bus_buffer.scala 640:19] + node _T_4897 = bits(obuf_addr, 31, 3) @[el2_lsu_bus_buffer.scala 641:69] + node _T_4898 = cat(_T_4897, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_4899 = mux(obuf_sideeffect, obuf_addr, _T_4898) @[el2_lsu_bus_buffer.scala 641:27] + io.lsu_axi_araddr <= _T_4899 @[el2_lsu_bus_buffer.scala 641:21] + node _T_4900 = cat(UInt<1>("h00"), obuf_sz) @[Cat.scala 29:58] + node _T_4901 = mux(obuf_sideeffect, _T_4900, UInt<3>("h03")) @[el2_lsu_bus_buffer.scala 642:27] + io.lsu_axi_arsize <= _T_4901 @[el2_lsu_bus_buffer.scala 642:21] + io.lsu_axi_arprot <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 643:21] + node _T_4902 = mux(obuf_sideeffect, UInt<4>("h00"), UInt<4>("h0f")) @[el2_lsu_bus_buffer.scala 644:28] + io.lsu_axi_arcache <= _T_4902 @[el2_lsu_bus_buffer.scala 644:22] + node _T_4903 = bits(obuf_addr, 31, 28) @[el2_lsu_bus_buffer.scala 645:35] + io.lsu_axi_arregion <= _T_4903 @[el2_lsu_bus_buffer.scala 645:23] + io.lsu_axi_arlen <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 646:20] + io.lsu_axi_arburst <= UInt<2>("h01") @[el2_lsu_bus_buffer.scala 647:22] + io.lsu_axi_arqos <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 648:20] + io.lsu_axi_arlock <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 649:21] + io.lsu_axi_bready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 650:21] + io.lsu_axi_rready <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 651:21] + node _T_4904 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4905 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4906 = and(io.lsu_bus_clk_en_q, _T_4905) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4907 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4908 = and(_T_4906, _T_4907) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4909 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4910 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4911 = and(io.lsu_bus_clk_en_q, _T_4910) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4912 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4913 = and(_T_4911, _T_4912) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4914 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4915 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4916 = and(io.lsu_bus_clk_en_q, _T_4915) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4917 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4918 = and(_T_4916, _T_4917) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4919 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 652:81] + node _T_4920 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 652:125] + node _T_4921 = and(io.lsu_bus_clk_en_q, _T_4920) @[el2_lsu_bus_buffer.scala 652:114] + node _T_4922 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 652:140] + node _T_4923 = and(_T_4921, _T_4922) @[el2_lsu_bus_buffer.scala 652:129] + node _T_4924 = mux(_T_4904, _T_4908, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4925 = mux(_T_4909, _T_4913, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4926 = mux(_T_4914, _T_4918, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4927 = mux(_T_4919, _T_4923, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4928 = or(_T_4924, _T_4925) @[Mux.scala 27:72] + node _T_4929 = or(_T_4928, _T_4926) @[Mux.scala 27:72] + node _T_4930 = or(_T_4929, _T_4927) @[Mux.scala 27:72] + wire _T_4931 : UInt<1> @[Mux.scala 27:72] + _T_4931 <= _T_4930 @[Mux.scala 27:72] + io.lsu_imprecise_error_store_any <= _T_4931 @[el2_lsu_bus_buffer.scala 652:36] + node _T_4932 = eq(buf_state[0], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4933 = bits(buf_error, 0, 0) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4934 = and(_T_4932, _T_4933) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4935 = bits(buf_write, 0, 0) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4936 = and(_T_4934, _T_4935) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4937 = eq(buf_state[1], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4938 = bits(buf_error, 1, 1) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4939 = and(_T_4937, _T_4938) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4940 = bits(buf_write, 1, 1) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4941 = and(_T_4939, _T_4940) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4942 = eq(buf_state[2], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4943 = bits(buf_error, 2, 2) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4944 = and(_T_4942, _T_4943) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4945 = bits(buf_write, 2, 2) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4946 = and(_T_4944, _T_4945) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4947 = eq(buf_state[3], UInt<3>("h06")) @[el2_lsu_bus_buffer.scala 653:82] + node _T_4948 = bits(buf_error, 3, 3) @[el2_lsu_bus_buffer.scala 653:104] + node _T_4949 = and(_T_4947, _T_4948) @[el2_lsu_bus_buffer.scala 653:93] + node _T_4950 = bits(buf_write, 3, 3) @[el2_lsu_bus_buffer.scala 653:119] + node _T_4951 = and(_T_4949, _T_4950) @[el2_lsu_bus_buffer.scala 653:108] + node _T_4952 = mux(_T_4936, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4953 = mux(_T_4941, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4954 = mux(_T_4946, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4955 = mux(_T_4951, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] + node _T_4956 = or(_T_4952, _T_4953) @[Mux.scala 27:72] + node _T_4957 = or(_T_4956, _T_4954) @[Mux.scala 27:72] + node _T_4958 = or(_T_4957, _T_4955) @[Mux.scala 27:72] + wire lsu_imprecise_error_store_tag : UInt<2> @[Mux.scala 27:72] + lsu_imprecise_error_store_tag <= _T_4958 @[Mux.scala 27:72] + node _T_4959 = eq(io.lsu_imprecise_error_store_any, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 655:72] + node _T_4960 = and(io.lsu_nonblock_load_data_error, _T_4959) @[el2_lsu_bus_buffer.scala 655:70] + io.lsu_imprecise_error_load_any <= _T_4960 @[el2_lsu_bus_buffer.scala 655:35] + node _T_4961 = mux(io.lsu_imprecise_error_store_any, buf_addr[lsu_imprecise_error_store_tag], buf_addr[io.lsu_nonblock_load_data_tag]) @[el2_lsu_bus_buffer.scala 656:41] + io.lsu_imprecise_error_addr_any <= _T_4961 @[el2_lsu_bus_buffer.scala 656:35] + lsu_bus_cntr_overflow <= UInt<1>("h00") @[el2_lsu_bus_buffer.scala 657:25] + io.lsu_bus_idle_any <= UInt<1>("h01") @[el2_lsu_bus_buffer.scala 659:23] + node _T_4962 = and(io.lsu_axi_awvalid, io.lsu_axi_awready) @[el2_lsu_bus_buffer.scala 662:46] + node _T_4963 = and(io.lsu_axi_wvalid, io.lsu_axi_wready) @[el2_lsu_bus_buffer.scala 662:89] + node _T_4964 = or(_T_4962, _T_4963) @[el2_lsu_bus_buffer.scala 662:68] + node _T_4965 = and(io.lsu_axi_arvalid, io.lsu_axi_arready) @[el2_lsu_bus_buffer.scala 662:132] + node _T_4966 = or(_T_4964, _T_4965) @[el2_lsu_bus_buffer.scala 662:110] + io.lsu_pmu_bus_trxn <= _T_4966 @[el2_lsu_bus_buffer.scala 662:23] + node _T_4967 = and(io.lsu_busreq_r, io.ldst_dual_r) @[el2_lsu_bus_buffer.scala 663:48] + node _T_4968 = and(_T_4967, io.lsu_commit_r) @[el2_lsu_bus_buffer.scala 663:65] + io.lsu_pmu_bus_misaligned <= _T_4968 @[el2_lsu_bus_buffer.scala 663:29] + node _T_4969 = or(io.lsu_imprecise_error_load_any, io.lsu_imprecise_error_store_any) @[el2_lsu_bus_buffer.scala 664:59] + io.lsu_pmu_bus_error <= _T_4969 @[el2_lsu_bus_buffer.scala 664:24] + node _T_4970 = eq(io.lsu_axi_awready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:48] + node _T_4971 = and(io.lsu_axi_awvalid, _T_4970) @[el2_lsu_bus_buffer.scala 666:46] + node _T_4972 = eq(io.lsu_axi_wready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:92] + node _T_4973 = and(io.lsu_axi_wvalid, _T_4972) @[el2_lsu_bus_buffer.scala 666:90] + node _T_4974 = or(_T_4971, _T_4973) @[el2_lsu_bus_buffer.scala 666:69] + node _T_4975 = eq(io.lsu_axi_arready, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 666:136] + node _T_4976 = and(io.lsu_axi_arvalid, _T_4975) @[el2_lsu_bus_buffer.scala 666:134] + node _T_4977 = or(_T_4974, _T_4976) @[el2_lsu_bus_buffer.scala 666:112] + io.lsu_pmu_bus_busy <= _T_4977 @[el2_lsu_bus_buffer.scala 666:23] + reg _T_4978 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 668:49] + _T_4978 <= WrPtr0_m @[el2_lsu_bus_buffer.scala 668:49] + WrPtr0_r <= _T_4978 @[el2_lsu_bus_buffer.scala 668:12] + reg _T_4979 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 669:49] + _T_4979 <= WrPtr1_m @[el2_lsu_bus_buffer.scala 669:49] + WrPtr1_r <= _T_4979 @[el2_lsu_bus_buffer.scala 669:12] + node _T_4980 = eq(io.flush_r, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:75] + node _T_4981 = and(io.lsu_busreq_m, _T_4980) @[el2_lsu_bus_buffer.scala 670:73] + node _T_4982 = eq(io.ld_full_hit_m, UInt<1>("h00")) @[el2_lsu_bus_buffer.scala 670:89] + node _T_4983 = and(_T_4981, _T_4982) @[el2_lsu_bus_buffer.scala 670:87] + reg _T_4984 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 670:56] + _T_4984 <= _T_4983 @[el2_lsu_bus_buffer.scala 670:56] + io.lsu_busreq_r <= _T_4984 @[el2_lsu_bus_buffer.scala 670:19] + reg _T_4985 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_buffer.scala 671:66] + _T_4985 <= io.lsu_nonblock_load_valid_m @[el2_lsu_bus_buffer.scala 671:66] + lsu_nonblock_load_valid_r <= _T_4985 @[el2_lsu_bus_buffer.scala 671:29] module el2_lsu_bus_intf : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_axi_awready : UInt<1>, flip lsu_axi_wready : UInt<1>, flip lsu_axi_bvalid : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, flip lsu_axi_arready : UInt<1>, flip lsu_axi_rvalid : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, lsu_axi_bready : UInt<1>, lsu_axi_arvalid : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, lsu_axi_rready : UInt<1>} + output io : {flip scan_mode : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip free_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_busreq_m : UInt<1>, flip lsu_pkt_m : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_pkt_r : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>, valid : UInt<1>}, flip lsu_addr_d : UInt<32>, flip lsu_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_d : UInt<32>, flip end_addr_m : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip dec_tlu_force_halt : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, lsu_bus_idle_any : UInt<1>, bus_read_data_m : UInt<32>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>, lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>, lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, lsu_axi_awvalid : UInt<1>, flip lsu_axi_awready : UInt<1>, lsu_axi_awid : UInt<3>, lsu_axi_awaddr : UInt<32>, lsu_axi_awregion : UInt<4>, lsu_axi_awlen : UInt<8>, lsu_axi_awsize : UInt<3>, lsu_axi_awburst : UInt<2>, lsu_axi_awlock : UInt<1>, lsu_axi_awcache : UInt<4>, lsu_axi_awprot : UInt<3>, lsu_axi_awqos : UInt<4>, lsu_axi_wvalid : UInt<1>, flip lsu_axi_wready : UInt<1>, lsu_axi_wdata : UInt<64>, lsu_axi_wstrb : UInt<8>, lsu_axi_wlast : UInt<1>, flip lsu_axi_bvalid : UInt<1>, lsu_axi_bready : UInt<1>, flip lsu_axi_bresp : UInt<2>, flip lsu_axi_bid : UInt<3>, lsu_axi_arvalid : UInt<1>, flip lsu_axi_arready : UInt<1>, lsu_axi_arid : UInt<3>, lsu_axi_araddr : UInt<32>, lsu_axi_arregion : UInt<4>, lsu_axi_arlen : UInt<8>, lsu_axi_arsize : UInt<3>, lsu_axi_arburst : UInt<2>, lsu_axi_arlock : UInt<1>, lsu_axi_arcache : UInt<4>, lsu_axi_arprot : UInt<3>, lsu_axi_arqos : UInt<4>, flip lsu_axi_rvalid : UInt<1>, lsu_axi_rready : UInt<1>, flip lsu_axi_rid : UInt<3>, flip lsu_axi_rdata : UInt<64>, flip lsu_axi_rresp : UInt<2>, flip lsu_axi_rlast : UInt<1>, flip lsu_bus_clk_en : UInt<1>} wire lsu_bus_clk_en_q : UInt<1> lsu_bus_clk_en_q <= UInt<1>("h00") @@ -6317,131 +6598,131 @@ circuit el2_lsu_bus_intf : ld_full_hit_lo_m <= UInt<1>("h01") wire ld_full_hit_m : UInt<1> ld_full_hit_m <= UInt<1>("h00") - inst bus_buffer of el2_lsu_bus_buffer @[el2_lsu_bus_intf.scala 148:40] + inst bus_buffer of el2_lsu_bus_buffer @[el2_lsu_bus_intf.scala 167:39] bus_buffer.clock <= clock bus_buffer.reset <= reset - bus_buffer.io.scan_mode <= io.scan_mode @[el2_lsu_bus_intf.scala 149:52] - bus_buffer.io.dec_tlu_external_ldfwd_disable <= io.dec_tlu_external_ldfwd_disable @[el2_lsu_bus_intf.scala 150:52] - bus_buffer.io.dec_tlu_wb_coalescing_disable <= io.dec_tlu_wb_coalescing_disable @[el2_lsu_bus_intf.scala 151:52] - bus_buffer.io.dec_tlu_sideeffect_posted_disable <= io.dec_tlu_sideeffect_posted_disable @[el2_lsu_bus_intf.scala 152:52] - bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[el2_lsu_bus_intf.scala 153:52] - bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[el2_lsu_bus_intf.scala 154:52] - bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[el2_lsu_bus_intf.scala 155:52] - bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[el2_lsu_bus_intf.scala 156:52] - bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[el2_lsu_bus_intf.scala 157:52] - bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[el2_lsu_bus_intf.scala 158:52] - bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[el2_lsu_bus_intf.scala 159:52] - bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu_bus_intf.scala 160:52] - bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.dma <= io.lsu_pkt_m.dma @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.store <= io.lsu_pkt_m.store @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.load <= io.lsu_pkt_m.load @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.dword <= io.lsu_pkt_m.dword @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.word <= io.lsu_pkt_m.word @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.half <= io.lsu_pkt_m.half @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.by <= io.lsu_pkt_m.by @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_m.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_bus_intf.scala 161:52] - bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.store_data_bypass_m <= io.lsu_pkt_r.store_data_bypass_m @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.load_ldst_bypass_d <= io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.store_data_bypass_d <= io.lsu_pkt_r.store_data_bypass_d @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.dma <= io.lsu_pkt_r.dma @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.unsign <= io.lsu_pkt_r.unsign @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.store <= io.lsu_pkt_r.store @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.load <= io.lsu_pkt_r.load @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.dword <= io.lsu_pkt_r.dword @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.word <= io.lsu_pkt_r.word @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.half <= io.lsu_pkt_r.half @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.by <= io.lsu_pkt_r.by @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_pkt_r.fast_int <= io.lsu_pkt_r.fast_int @[el2_lsu_bus_intf.scala 162:52] - bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[el2_lsu_bus_intf.scala 163:52] - bus_buffer.io.end_addr_m <= io.end_addr_m @[el2_lsu_bus_intf.scala 164:52] - bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[el2_lsu_bus_intf.scala 165:52] - bus_buffer.io.end_addr_r <= io.end_addr_r @[el2_lsu_bus_intf.scala 166:52] - bus_buffer.io.store_data_r <= io.store_data_r @[el2_lsu_bus_intf.scala 167:52] - bus_buffer.io.no_word_merge_r <= no_word_merge_r @[el2_lsu_bus_intf.scala 168:52] - bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[el2_lsu_bus_intf.scala 169:52] - bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[el2_lsu_bus_intf.scala 170:52] - bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[el2_lsu_bus_intf.scala 171:52] - bus_buffer.io.flush_m_up <= io.flush_m_up @[el2_lsu_bus_intf.scala 172:52] - bus_buffer.io.flush_r <= io.flush_r @[el2_lsu_bus_intf.scala 173:52] - bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[el2_lsu_bus_intf.scala 174:52] - bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[el2_lsu_bus_intf.scala 175:52] - bus_buffer.io.ldst_dual_d <= ldst_dual_d @[el2_lsu_bus_intf.scala 176:52] - bus_buffer.io.ldst_dual_m <= ldst_dual_m @[el2_lsu_bus_intf.scala 177:52] - bus_buffer.io.ldst_dual_r <= ldst_dual_r @[el2_lsu_bus_intf.scala 178:52] - bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[el2_lsu_bus_intf.scala 179:52] - bus_buffer.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_lsu_bus_intf.scala 180:52] - bus_buffer.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_lsu_bus_intf.scala 181:52] - bus_buffer.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_lsu_bus_intf.scala 182:52] - bus_buffer.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_lsu_bus_intf.scala 183:52] - bus_buffer.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_lsu_bus_intf.scala 184:52] - bus_buffer.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_lsu_bus_intf.scala 185:52] - bus_buffer.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_lsu_bus_intf.scala 186:52] - bus_buffer.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_lsu_bus_intf.scala 187:52] - bus_buffer.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_intf.scala 188:52] - bus_buffer.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_lsu_bus_intf.scala 189:52] - bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 190:52] - bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[el2_lsu_bus_intf.scala 191:52] - io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[el2_lsu_bus_intf.scala 193:39] - io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[el2_lsu_bus_intf.scala 194:39] - io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[el2_lsu_bus_intf.scala 195:39] - io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[el2_lsu_bus_intf.scala 196:39] - io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[el2_lsu_bus_intf.scala 197:39] - ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[el2_lsu_bus_intf.scala 198:39] - ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[el2_lsu_bus_intf.scala 199:39] - ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[el2_lsu_bus_intf.scala 200:39] - ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[el2_lsu_bus_intf.scala 201:39] - io.lsu_imprecise_error_load_any <= bus_buffer.io.lsu_imprecise_error_load_any @[el2_lsu_bus_intf.scala 202:39] - io.lsu_imprecise_error_store_any <= bus_buffer.io.lsu_imprecise_error_store_any @[el2_lsu_bus_intf.scala 203:39] - io.lsu_imprecise_error_addr_any <= bus_buffer.io.lsu_imprecise_error_addr_any @[el2_lsu_bus_intf.scala 204:39] - io.lsu_nonblock_load_valid_m <= bus_buffer.io.lsu_nonblock_load_valid_m @[el2_lsu_bus_intf.scala 205:39] - io.lsu_nonblock_load_tag_m <= bus_buffer.io.lsu_nonblock_load_tag_m @[el2_lsu_bus_intf.scala 206:39] - io.lsu_nonblock_load_inv_r <= bus_buffer.io.lsu_nonblock_load_inv_r @[el2_lsu_bus_intf.scala 207:39] - io.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.lsu_nonblock_load_inv_tag_r @[el2_lsu_bus_intf.scala 208:39] - io.lsu_nonblock_load_data_valid <= bus_buffer.io.lsu_nonblock_load_data_valid @[el2_lsu_bus_intf.scala 209:39] - io.lsu_nonblock_load_data_error <= bus_buffer.io.lsu_nonblock_load_data_error @[el2_lsu_bus_intf.scala 210:39] - io.lsu_nonblock_load_data_tag <= bus_buffer.io.lsu_nonblock_load_data_tag @[el2_lsu_bus_intf.scala 211:39] - io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[el2_lsu_bus_intf.scala 212:39] - io.lsu_pmu_bus_trxn <= bus_buffer.io.lsu_pmu_bus_trxn @[el2_lsu_bus_intf.scala 213:39] - io.lsu_pmu_bus_misaligned <= bus_buffer.io.lsu_pmu_bus_misaligned @[el2_lsu_bus_intf.scala 214:39] - io.lsu_pmu_bus_error <= bus_buffer.io.lsu_pmu_bus_error @[el2_lsu_bus_intf.scala 215:39] - io.lsu_pmu_bus_busy <= bus_buffer.io.lsu_pmu_bus_busy @[el2_lsu_bus_intf.scala 216:39] - io.lsu_axi_awvalid <= bus_buffer.io.lsu_axi_awvalid @[el2_lsu_bus_intf.scala 217:39] - io.lsu_axi_awid <= bus_buffer.io.lsu_axi_awid @[el2_lsu_bus_intf.scala 218:39] - io.lsu_axi_awaddr <= bus_buffer.io.lsu_axi_awaddr @[el2_lsu_bus_intf.scala 219:39] - io.lsu_axi_awregion <= bus_buffer.io.lsu_axi_awregion @[el2_lsu_bus_intf.scala 220:39] - io.lsu_axi_awlen <= bus_buffer.io.lsu_axi_awlen @[el2_lsu_bus_intf.scala 221:39] - io.lsu_axi_awsize <= bus_buffer.io.lsu_axi_awsize @[el2_lsu_bus_intf.scala 222:39] - io.lsu_axi_awburst <= bus_buffer.io.lsu_axi_awburst @[el2_lsu_bus_intf.scala 223:39] - io.lsu_axi_awlock <= bus_buffer.io.lsu_axi_awlock @[el2_lsu_bus_intf.scala 224:39] - io.lsu_axi_awcache <= bus_buffer.io.lsu_axi_awcache @[el2_lsu_bus_intf.scala 225:39] - io.lsu_axi_awprot <= bus_buffer.io.lsu_axi_awprot @[el2_lsu_bus_intf.scala 226:39] - io.lsu_axi_awqos <= bus_buffer.io.lsu_axi_awqos @[el2_lsu_bus_intf.scala 227:39] - io.lsu_axi_wvalid <= bus_buffer.io.lsu_axi_wvalid @[el2_lsu_bus_intf.scala 228:39] - io.lsu_axi_wdata <= bus_buffer.io.lsu_axi_wdata @[el2_lsu_bus_intf.scala 229:39] - io.lsu_axi_wstrb <= bus_buffer.io.lsu_axi_wstrb @[el2_lsu_bus_intf.scala 230:39] - io.lsu_axi_wlast <= bus_buffer.io.lsu_axi_wlast @[el2_lsu_bus_intf.scala 231:39] - io.lsu_axi_bready <= bus_buffer.io.lsu_axi_bready @[el2_lsu_bus_intf.scala 232:39] - io.lsu_axi_arvalid <= bus_buffer.io.lsu_axi_arvalid @[el2_lsu_bus_intf.scala 233:39] - io.lsu_axi_arid <= bus_buffer.io.lsu_axi_arid @[el2_lsu_bus_intf.scala 234:39] - io.lsu_axi_araddr <= bus_buffer.io.lsu_axi_araddr @[el2_lsu_bus_intf.scala 235:39] - io.lsu_axi_arregion <= bus_buffer.io.lsu_axi_arregion @[el2_lsu_bus_intf.scala 236:39] - io.lsu_axi_arlen <= bus_buffer.io.lsu_axi_arlen @[el2_lsu_bus_intf.scala 237:39] - io.lsu_axi_arsize <= bus_buffer.io.lsu_axi_arsize @[el2_lsu_bus_intf.scala 238:39] - io.lsu_axi_arburst <= bus_buffer.io.lsu_axi_arburst @[el2_lsu_bus_intf.scala 239:39] - io.lsu_axi_arlock <= bus_buffer.io.lsu_axi_arlock @[el2_lsu_bus_intf.scala 240:39] - io.lsu_axi_arcache <= bus_buffer.io.lsu_axi_arcache @[el2_lsu_bus_intf.scala 241:39] - io.lsu_axi_arprot <= bus_buffer.io.lsu_axi_arprot @[el2_lsu_bus_intf.scala 242:39] - io.lsu_axi_arqos <= bus_buffer.io.lsu_axi_arqos @[el2_lsu_bus_intf.scala 243:39] - io.lsu_axi_rready <= bus_buffer.io.lsu_axi_rready @[el2_lsu_bus_intf.scala 244:39] - node _T = bits(io.lsu_pkt_r.word, 0, 0) @[el2_lsu_bus_intf.scala 246:59] - node _T_1 = bits(io.lsu_pkt_r.half, 0, 0) @[el2_lsu_bus_intf.scala 246:98] - node _T_2 = bits(io.lsu_pkt_r.by, 0, 0) @[el2_lsu_bus_intf.scala 246:134] + bus_buffer.io.scan_mode <= io.scan_mode @[el2_lsu_bus_intf.scala 169:29] + bus_buffer.io.dec_tlu_external_ldfwd_disable <= io.dec_tlu_external_ldfwd_disable @[el2_lsu_bus_intf.scala 171:51] + bus_buffer.io.dec_tlu_wb_coalescing_disable <= io.dec_tlu_wb_coalescing_disable @[el2_lsu_bus_intf.scala 172:51] + bus_buffer.io.dec_tlu_sideeffect_posted_disable <= io.dec_tlu_sideeffect_posted_disable @[el2_lsu_bus_intf.scala 173:51] + bus_buffer.io.dec_tlu_force_halt <= io.dec_tlu_force_halt @[el2_lsu_bus_intf.scala 174:51] + bus_buffer.io.lsu_c2_r_clk <= io.lsu_c2_r_clk @[el2_lsu_bus_intf.scala 175:51] + bus_buffer.io.lsu_bus_ibuf_c1_clk <= io.lsu_bus_ibuf_c1_clk @[el2_lsu_bus_intf.scala 176:51] + bus_buffer.io.lsu_bus_obuf_c1_clk <= io.lsu_bus_obuf_c1_clk @[el2_lsu_bus_intf.scala 177:51] + bus_buffer.io.lsu_bus_buf_c1_clk <= io.lsu_bus_buf_c1_clk @[el2_lsu_bus_intf.scala 178:51] + bus_buffer.io.lsu_free_c2_clk <= io.lsu_free_c2_clk @[el2_lsu_bus_intf.scala 179:51] + bus_buffer.io.lsu_busm_clk <= io.lsu_busm_clk @[el2_lsu_bus_intf.scala 180:51] + bus_buffer.io.dec_lsu_valid_raw_d <= io.dec_lsu_valid_raw_d @[el2_lsu_bus_intf.scala 181:51] + bus_buffer.io.lsu_pkt_m.valid <= io.lsu_pkt_m.valid @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store_data_bypass_m <= io.lsu_pkt_m.store_data_bypass_m @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.load_ldst_bypass_d <= io.lsu_pkt_m.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store_data_bypass_d <= io.lsu_pkt_m.store_data_bypass_d @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.dma <= io.lsu_pkt_m.dma @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.unsign <= io.lsu_pkt_m.unsign @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.store <= io.lsu_pkt_m.store @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.load <= io.lsu_pkt_m.load @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.dword <= io.lsu_pkt_m.dword @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.word <= io.lsu_pkt_m.word @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.half <= io.lsu_pkt_m.half @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.by <= io.lsu_pkt_m.by @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_m.fast_int <= io.lsu_pkt_m.fast_int @[el2_lsu_bus_intf.scala 184:27] + bus_buffer.io.lsu_pkt_r.valid <= io.lsu_pkt_r.valid @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store_data_bypass_m <= io.lsu_pkt_r.store_data_bypass_m @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.load_ldst_bypass_d <= io.lsu_pkt_r.load_ldst_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store_data_bypass_d <= io.lsu_pkt_r.store_data_bypass_d @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.dma <= io.lsu_pkt_r.dma @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.unsign <= io.lsu_pkt_r.unsign @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.store <= io.lsu_pkt_r.store @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.load <= io.lsu_pkt_r.load @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.dword <= io.lsu_pkt_r.dword @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.word <= io.lsu_pkt_r.word @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.half <= io.lsu_pkt_r.half @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.by <= io.lsu_pkt_r.by @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_pkt_r.fast_int <= io.lsu_pkt_r.fast_int @[el2_lsu_bus_intf.scala 185:27] + bus_buffer.io.lsu_addr_m <= io.lsu_addr_m @[el2_lsu_bus_intf.scala 188:51] + bus_buffer.io.end_addr_m <= io.end_addr_m @[el2_lsu_bus_intf.scala 189:51] + bus_buffer.io.lsu_addr_r <= io.lsu_addr_r @[el2_lsu_bus_intf.scala 190:51] + bus_buffer.io.end_addr_r <= io.end_addr_r @[el2_lsu_bus_intf.scala 191:51] + bus_buffer.io.store_data_r <= io.store_data_r @[el2_lsu_bus_intf.scala 192:51] + bus_buffer.io.lsu_busreq_m <= io.lsu_busreq_m @[el2_lsu_bus_intf.scala 194:51] + bus_buffer.io.flush_m_up <= io.flush_m_up @[el2_lsu_bus_intf.scala 195:51] + bus_buffer.io.flush_r <= io.flush_r @[el2_lsu_bus_intf.scala 196:51] + bus_buffer.io.lsu_commit_r <= io.lsu_commit_r @[el2_lsu_bus_intf.scala 197:51] + bus_buffer.io.lsu_axi_awready <= io.lsu_axi_awready @[el2_lsu_bus_intf.scala 198:51] + bus_buffer.io.lsu_axi_wready <= io.lsu_axi_wready @[el2_lsu_bus_intf.scala 199:51] + bus_buffer.io.lsu_axi_bvalid <= io.lsu_axi_bvalid @[el2_lsu_bus_intf.scala 200:51] + bus_buffer.io.lsu_axi_bresp <= io.lsu_axi_bresp @[el2_lsu_bus_intf.scala 201:51] + bus_buffer.io.lsu_axi_bid <= io.lsu_axi_bid @[el2_lsu_bus_intf.scala 202:51] + bus_buffer.io.lsu_axi_arready <= io.lsu_axi_arready @[el2_lsu_bus_intf.scala 203:51] + bus_buffer.io.lsu_axi_rvalid <= io.lsu_axi_rvalid @[el2_lsu_bus_intf.scala 204:51] + bus_buffer.io.lsu_axi_rid <= io.lsu_axi_rid @[el2_lsu_bus_intf.scala 205:51] + bus_buffer.io.lsu_axi_rdata <= io.lsu_axi_rdata @[el2_lsu_bus_intf.scala 206:51] + bus_buffer.io.lsu_axi_rresp <= io.lsu_axi_rresp @[el2_lsu_bus_intf.scala 207:51] + bus_buffer.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 208:51] + io.lsu_busreq_r <= bus_buffer.io.lsu_busreq_r @[el2_lsu_bus_intf.scala 210:38] + io.lsu_bus_buffer_pend_any <= bus_buffer.io.lsu_bus_buffer_pend_any @[el2_lsu_bus_intf.scala 211:38] + io.lsu_bus_buffer_full_any <= bus_buffer.io.lsu_bus_buffer_full_any @[el2_lsu_bus_intf.scala 212:38] + io.lsu_bus_buffer_empty_any <= bus_buffer.io.lsu_bus_buffer_empty_any @[el2_lsu_bus_intf.scala 213:38] + io.lsu_bus_idle_any <= bus_buffer.io.lsu_bus_idle_any @[el2_lsu_bus_intf.scala 214:38] + ld_byte_hit_buf_lo <= bus_buffer.io.ld_byte_hit_buf_lo @[el2_lsu_bus_intf.scala 215:38] + ld_byte_hit_buf_hi <= bus_buffer.io.ld_byte_hit_buf_hi @[el2_lsu_bus_intf.scala 216:38] + ld_fwddata_buf_lo <= bus_buffer.io.ld_fwddata_buf_lo @[el2_lsu_bus_intf.scala 217:38] + ld_fwddata_buf_hi <= bus_buffer.io.ld_fwddata_buf_hi @[el2_lsu_bus_intf.scala 218:38] + io.lsu_imprecise_error_load_any <= bus_buffer.io.lsu_imprecise_error_load_any @[el2_lsu_bus_intf.scala 219:38] + io.lsu_imprecise_error_store_any <= bus_buffer.io.lsu_imprecise_error_store_any @[el2_lsu_bus_intf.scala 220:38] + io.lsu_imprecise_error_addr_any <= bus_buffer.io.lsu_imprecise_error_addr_any @[el2_lsu_bus_intf.scala 221:38] + io.lsu_nonblock_load_valid_m <= bus_buffer.io.lsu_nonblock_load_valid_m @[el2_lsu_bus_intf.scala 222:38] + io.lsu_nonblock_load_tag_m <= bus_buffer.io.lsu_nonblock_load_tag_m @[el2_lsu_bus_intf.scala 223:38] + io.lsu_nonblock_load_inv_r <= bus_buffer.io.lsu_nonblock_load_inv_r @[el2_lsu_bus_intf.scala 224:38] + io.lsu_nonblock_load_inv_tag_r <= bus_buffer.io.lsu_nonblock_load_inv_tag_r @[el2_lsu_bus_intf.scala 225:38] + io.lsu_nonblock_load_data_valid <= bus_buffer.io.lsu_nonblock_load_data_valid @[el2_lsu_bus_intf.scala 226:38] + io.lsu_nonblock_load_data_error <= bus_buffer.io.lsu_nonblock_load_data_error @[el2_lsu_bus_intf.scala 227:38] + io.lsu_nonblock_load_data_tag <= bus_buffer.io.lsu_nonblock_load_data_tag @[el2_lsu_bus_intf.scala 228:38] + io.lsu_nonblock_load_data <= bus_buffer.io.lsu_nonblock_load_data @[el2_lsu_bus_intf.scala 229:38] + io.lsu_pmu_bus_trxn <= bus_buffer.io.lsu_pmu_bus_trxn @[el2_lsu_bus_intf.scala 230:38] + io.lsu_pmu_bus_misaligned <= bus_buffer.io.lsu_pmu_bus_misaligned @[el2_lsu_bus_intf.scala 231:38] + io.lsu_pmu_bus_error <= bus_buffer.io.lsu_pmu_bus_error @[el2_lsu_bus_intf.scala 232:38] + io.lsu_pmu_bus_busy <= bus_buffer.io.lsu_pmu_bus_busy @[el2_lsu_bus_intf.scala 233:38] + io.lsu_axi_awvalid <= bus_buffer.io.lsu_axi_awvalid @[el2_lsu_bus_intf.scala 234:38] + io.lsu_axi_awid <= bus_buffer.io.lsu_axi_awid @[el2_lsu_bus_intf.scala 235:38] + io.lsu_axi_awaddr <= bus_buffer.io.lsu_axi_awaddr @[el2_lsu_bus_intf.scala 236:38] + io.lsu_axi_awregion <= bus_buffer.io.lsu_axi_awregion @[el2_lsu_bus_intf.scala 237:38] + io.lsu_axi_awlen <= bus_buffer.io.lsu_axi_awlen @[el2_lsu_bus_intf.scala 238:38] + io.lsu_axi_awsize <= bus_buffer.io.lsu_axi_awsize @[el2_lsu_bus_intf.scala 239:38] + io.lsu_axi_awburst <= bus_buffer.io.lsu_axi_awburst @[el2_lsu_bus_intf.scala 240:38] + io.lsu_axi_awlock <= bus_buffer.io.lsu_axi_awlock @[el2_lsu_bus_intf.scala 241:38] + io.lsu_axi_awcache <= bus_buffer.io.lsu_axi_awcache @[el2_lsu_bus_intf.scala 242:38] + io.lsu_axi_awprot <= bus_buffer.io.lsu_axi_awprot @[el2_lsu_bus_intf.scala 243:38] + io.lsu_axi_awqos <= bus_buffer.io.lsu_axi_awqos @[el2_lsu_bus_intf.scala 244:38] + io.lsu_axi_wvalid <= bus_buffer.io.lsu_axi_wvalid @[el2_lsu_bus_intf.scala 245:38] + io.lsu_axi_wdata <= bus_buffer.io.lsu_axi_wdata @[el2_lsu_bus_intf.scala 246:38] + io.lsu_axi_wstrb <= bus_buffer.io.lsu_axi_wstrb @[el2_lsu_bus_intf.scala 247:38] + io.lsu_axi_wlast <= bus_buffer.io.lsu_axi_wlast @[el2_lsu_bus_intf.scala 248:38] + io.lsu_axi_bready <= bus_buffer.io.lsu_axi_bready @[el2_lsu_bus_intf.scala 249:38] + io.lsu_axi_arvalid <= bus_buffer.io.lsu_axi_arvalid @[el2_lsu_bus_intf.scala 250:38] + io.lsu_axi_arid <= bus_buffer.io.lsu_axi_arid @[el2_lsu_bus_intf.scala 251:38] + io.lsu_axi_araddr <= bus_buffer.io.lsu_axi_araddr @[el2_lsu_bus_intf.scala 252:38] + io.lsu_axi_arregion <= bus_buffer.io.lsu_axi_arregion @[el2_lsu_bus_intf.scala 253:38] + io.lsu_axi_arlen <= bus_buffer.io.lsu_axi_arlen @[el2_lsu_bus_intf.scala 254:38] + io.lsu_axi_arsize <= bus_buffer.io.lsu_axi_arsize @[el2_lsu_bus_intf.scala 255:38] + io.lsu_axi_arburst <= bus_buffer.io.lsu_axi_arburst @[el2_lsu_bus_intf.scala 256:38] + io.lsu_axi_arlock <= bus_buffer.io.lsu_axi_arlock @[el2_lsu_bus_intf.scala 257:38] + io.lsu_axi_arcache <= bus_buffer.io.lsu_axi_arcache @[el2_lsu_bus_intf.scala 258:38] + io.lsu_axi_arprot <= bus_buffer.io.lsu_axi_arprot @[el2_lsu_bus_intf.scala 259:38] + io.lsu_axi_arqos <= bus_buffer.io.lsu_axi_arqos @[el2_lsu_bus_intf.scala 260:38] + io.lsu_axi_rready <= bus_buffer.io.lsu_axi_rready @[el2_lsu_bus_intf.scala 261:38] + bus_buffer.io.no_word_merge_r <= no_word_merge_r @[el2_lsu_bus_intf.scala 263:51] + bus_buffer.io.no_dword_merge_r <= no_dword_merge_r @[el2_lsu_bus_intf.scala 264:51] + bus_buffer.io.is_sideeffects_r <= is_sideeffects_r @[el2_lsu_bus_intf.scala 265:51] + bus_buffer.io.ldst_dual_d <= ldst_dual_d @[el2_lsu_bus_intf.scala 266:51] + bus_buffer.io.ldst_dual_m <= ldst_dual_m @[el2_lsu_bus_intf.scala 267:51] + bus_buffer.io.ldst_dual_r <= ldst_dual_r @[el2_lsu_bus_intf.scala 268:51] + bus_buffer.io.ldst_byteen_ext_m <= ldst_byteen_ext_m @[el2_lsu_bus_intf.scala 269:51] + bus_buffer.io.ld_full_hit_m <= ld_full_hit_m @[el2_lsu_bus_intf.scala 270:51] + bus_buffer.io.lsu_bus_clk_en_q <= lsu_bus_clk_en_q @[el2_lsu_bus_intf.scala 271:51] + node _T = bits(io.lsu_pkt_m.word, 0, 0) @[el2_lsu_bus_intf.scala 276:58] + node _T_1 = bits(io.lsu_pkt_m.half, 0, 0) @[el2_lsu_bus_intf.scala 276:97] + node _T_2 = bits(io.lsu_pkt_m.by, 0, 0) @[el2_lsu_bus_intf.scala 276:133] node _T_3 = mux(_T, UInt<4>("h0f"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_4 = mux(_T_1, UInt<4>("h03"), UInt<1>("h00")) @[Mux.scala 27:72] node _T_5 = mux(_T_2, UInt<4>("h01"), UInt<1>("h00")) @[Mux.scala 27:72] @@ -6449,439 +6730,436 @@ circuit el2_lsu_bus_intf : node _T_7 = or(_T_6, _T_5) @[Mux.scala 27:72] wire _T_8 : UInt<4> @[Mux.scala 27:72] _T_8 <= _T_7 @[Mux.scala 27:72] - ldst_byteen_m <= _T_8 @[el2_lsu_bus_intf.scala 246:28] - node _T_9 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 247:44] - node _T_10 = bits(io.end_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 247:65] - node _T_11 = neq(_T_9, _T_10) @[el2_lsu_bus_intf.scala 247:48] - ldst_dual_d <= _T_11 @[el2_lsu_bus_intf.scala 247:28] - node _T_12 = bits(io.lsu_addr_r, 31, 3) @[el2_lsu_bus_intf.scala 248:45] - node _T_13 = bits(io.lsu_addr_m, 31, 3) @[el2_lsu_bus_intf.scala 248:69] - node _T_14 = eq(_T_12, _T_13) @[el2_lsu_bus_intf.scala 248:52] - addr_match_dw_lo_r_m <= _T_14 @[el2_lsu_bus_intf.scala 248:28] - node _T_15 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_intf.scala 249:69] - node _T_16 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_bus_intf.scala 249:86] - node _T_17 = xor(_T_15, _T_16) @[el2_lsu_bus_intf.scala 249:72] - node _T_18 = not(_T_17) @[el2_lsu_bus_intf.scala 249:54] - node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[el2_lsu_bus_intf.scala 249:52] - addr_match_word_lo_r_m <= _T_19 @[el2_lsu_bus_intf.scala 249:28] - node _T_20 = not(ldst_dual_r) @[el2_lsu_bus_intf.scala 250:49] - node _T_21 = and(io.lsu_busreq_r, _T_20) @[el2_lsu_bus_intf.scala 250:47] - node _T_22 = and(_T_21, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 250:62] - node _T_23 = not(addr_match_word_lo_r_m) @[el2_lsu_bus_intf.scala 250:103] - node _T_24 = or(io.lsu_pkt_m.load, _T_23) @[el2_lsu_bus_intf.scala 250:101] - node _T_25 = and(_T_22, _T_24) @[el2_lsu_bus_intf.scala 250:80] - no_word_merge_r <= _T_25 @[el2_lsu_bus_intf.scala 250:28] - node _T_26 = not(ldst_dual_r) @[el2_lsu_bus_intf.scala 251:49] - node _T_27 = and(io.lsu_busreq_r, _T_26) @[el2_lsu_bus_intf.scala 251:47] - node _T_28 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 251:62] - node _T_29 = not(addr_match_dw_lo_r_m) @[el2_lsu_bus_intf.scala 251:103] - node _T_30 = or(io.lsu_pkt_m.load, _T_29) @[el2_lsu_bus_intf.scala 251:101] - node _T_31 = and(_T_28, _T_30) @[el2_lsu_bus_intf.scala 251:80] - no_dword_merge_r <= _T_31 @[el2_lsu_bus_intf.scala 251:28] - node _T_32 = bits(ldst_byteen_m, 3, 0) @[el2_lsu_bus_intf.scala 252:57] - node _T_33 = cat(UInt<4>("h00"), _T_32) @[Cat.scala 29:58] - node _T_34 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 252:80] - node _T_35 = dshl(_T_33, _T_34) @[el2_lsu_bus_intf.scala 252:64] - ldst_byteen_ext_m <= _T_35 @[el2_lsu_bus_intf.scala 252:28] - node _T_36 = bits(ldst_byteen_r, 3, 0) @[el2_lsu_bus_intf.scala 253:57] - node _T_37 = cat(UInt<4>("h00"), _T_36) @[Cat.scala 29:58] - node _T_38 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 253:80] - node _T_39 = dshl(_T_37, _T_38) @[el2_lsu_bus_intf.scala 253:64] - ldst_byteen_ext_r <= _T_39 @[el2_lsu_bus_intf.scala 253:28] - node _T_40 = bits(io.store_data_r, 31, 0) @[el2_lsu_bus_intf.scala 254:60] - node _T_41 = cat(UInt<32>("h00"), _T_40) @[Cat.scala 29:58] - node _T_42 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 254:88] - node _T_43 = cat(_T_42, UInt<3>("h00")) @[Cat.scala 29:58] - node _T_44 = dshl(_T_41, _T_43) @[el2_lsu_bus_intf.scala 254:68] - store_data_ext_r <= _T_44 @[el2_lsu_bus_intf.scala 254:28] - node _T_45 = bits(ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_intf.scala 255:48] - ldst_byteen_hi_m <= _T_45 @[el2_lsu_bus_intf.scala 255:28] - node _T_46 = bits(ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_intf.scala 256:48] - ldst_byteen_lo_m <= _T_46 @[el2_lsu_bus_intf.scala 256:28] - node _T_47 = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_bus_intf.scala 257:48] - ldst_byteen_hi_r <= _T_47 @[el2_lsu_bus_intf.scala 257:28] - node _T_48 = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_bus_intf.scala 258:48] - ldst_byteen_lo_r <= _T_48 @[el2_lsu_bus_intf.scala 258:28] - node _T_49 = bits(store_data_ext_r, 63, 32) @[el2_lsu_bus_intf.scala 259:47] - store_data_hi_r <= _T_49 @[el2_lsu_bus_intf.scala 259:28] - node _T_50 = bits(store_data_ext_r, 31, 0) @[el2_lsu_bus_intf.scala 260:47] - store_data_lo_r <= _T_50 @[el2_lsu_bus_intf.scala 260:28] - node _T_51 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 261:45] - node _T_52 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 261:69] - node _T_53 = eq(_T_51, _T_52) @[el2_lsu_bus_intf.scala 261:52] - node _T_54 = and(_T_53, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 261:77] - node _T_55 = and(_T_54, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 261:98] - node _T_56 = and(_T_55, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 261:119] - ld_addr_rhit_lo_lo <= _T_56 @[el2_lsu_bus_intf.scala 261:28] - node _T_57 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 262:45] - node _T_58 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 262:69] - node _T_59 = eq(_T_57, _T_58) @[el2_lsu_bus_intf.scala 262:52] - node _T_60 = and(_T_59, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 262:77] - node _T_61 = and(_T_60, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 262:98] - node _T_62 = and(_T_61, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 262:119] - ld_addr_rhit_lo_hi <= _T_62 @[el2_lsu_bus_intf.scala 262:28] - node _T_63 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 263:45] - node _T_64 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 263:69] - node _T_65 = eq(_T_63, _T_64) @[el2_lsu_bus_intf.scala 263:52] - node _T_66 = and(_T_65, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 263:77] - node _T_67 = and(_T_66, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 263:98] - node _T_68 = and(_T_67, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 263:119] - ld_addr_rhit_hi_lo <= _T_68 @[el2_lsu_bus_intf.scala 263:28] - node _T_69 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 264:45] - node _T_70 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 264:69] - node _T_71 = eq(_T_69, _T_70) @[el2_lsu_bus_intf.scala 264:52] - node _T_72 = and(_T_71, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 264:77] - node _T_73 = and(_T_72, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 264:98] - node _T_74 = and(_T_73, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 264:119] - ld_addr_rhit_hi_hi <= _T_74 @[el2_lsu_bus_intf.scala 264:28] - node _T_75 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 265:89] - node _T_76 = and(ld_addr_rhit_lo_lo, _T_75) @[el2_lsu_bus_intf.scala 265:71] - node _T_77 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 265:111] - node _T_78 = and(_T_76, _T_77) @[el2_lsu_bus_intf.scala 265:93] - node _T_79 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 265:89] - node _T_80 = and(ld_addr_rhit_lo_lo, _T_79) @[el2_lsu_bus_intf.scala 265:71] - node _T_81 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 265:111] - node _T_82 = and(_T_80, _T_81) @[el2_lsu_bus_intf.scala 265:93] - node _T_83 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 265:89] - node _T_84 = and(ld_addr_rhit_lo_lo, _T_83) @[el2_lsu_bus_intf.scala 265:71] - node _T_85 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 265:111] - node _T_86 = and(_T_84, _T_85) @[el2_lsu_bus_intf.scala 265:93] - node _T_87 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 265:89] - node _T_88 = and(ld_addr_rhit_lo_lo, _T_87) @[el2_lsu_bus_intf.scala 265:71] - node _T_89 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 265:111] - node _T_90 = and(_T_88, _T_89) @[el2_lsu_bus_intf.scala 265:93] - node _T_91 = cat(_T_90, _T_86) @[Cat.scala 29:58] - node _T_92 = cat(_T_91, _T_82) @[Cat.scala 29:58] - node _T_93 = cat(_T_92, _T_78) @[Cat.scala 29:58] - ld_byte_rhit_lo_lo <= _T_93 @[el2_lsu_bus_intf.scala 265:28] - node _T_94 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 266:89] - node _T_95 = and(ld_addr_rhit_lo_hi, _T_94) @[el2_lsu_bus_intf.scala 266:71] - node _T_96 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 266:111] - node _T_97 = and(_T_95, _T_96) @[el2_lsu_bus_intf.scala 266:93] - node _T_98 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 266:89] - node _T_99 = and(ld_addr_rhit_lo_hi, _T_98) @[el2_lsu_bus_intf.scala 266:71] - node _T_100 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 266:111] - node _T_101 = and(_T_99, _T_100) @[el2_lsu_bus_intf.scala 266:93] - node _T_102 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 266:89] - node _T_103 = and(ld_addr_rhit_lo_hi, _T_102) @[el2_lsu_bus_intf.scala 266:71] - node _T_104 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 266:111] - node _T_105 = and(_T_103, _T_104) @[el2_lsu_bus_intf.scala 266:93] - node _T_106 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 266:89] - node _T_107 = and(ld_addr_rhit_lo_hi, _T_106) @[el2_lsu_bus_intf.scala 266:71] - node _T_108 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 266:111] - node _T_109 = and(_T_107, _T_108) @[el2_lsu_bus_intf.scala 266:93] - node _T_110 = cat(_T_109, _T_105) @[Cat.scala 29:58] - node _T_111 = cat(_T_110, _T_101) @[Cat.scala 29:58] - node _T_112 = cat(_T_111, _T_97) @[Cat.scala 29:58] - ld_byte_rhit_lo_hi <= _T_112 @[el2_lsu_bus_intf.scala 266:28] - node _T_113 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 267:89] - node _T_114 = and(ld_addr_rhit_hi_lo, _T_113) @[el2_lsu_bus_intf.scala 267:71] - node _T_115 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 267:111] - node _T_116 = and(_T_114, _T_115) @[el2_lsu_bus_intf.scala 267:93] - node _T_117 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 267:89] - node _T_118 = and(ld_addr_rhit_hi_lo, _T_117) @[el2_lsu_bus_intf.scala 267:71] - node _T_119 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 267:111] - node _T_120 = and(_T_118, _T_119) @[el2_lsu_bus_intf.scala 267:93] - node _T_121 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 267:89] - node _T_122 = and(ld_addr_rhit_hi_lo, _T_121) @[el2_lsu_bus_intf.scala 267:71] - node _T_123 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 267:111] - node _T_124 = and(_T_122, _T_123) @[el2_lsu_bus_intf.scala 267:93] - node _T_125 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 267:89] - node _T_126 = and(ld_addr_rhit_hi_lo, _T_125) @[el2_lsu_bus_intf.scala 267:71] - node _T_127 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 267:111] - node _T_128 = and(_T_126, _T_127) @[el2_lsu_bus_intf.scala 267:93] - node _T_129 = cat(_T_128, _T_124) @[Cat.scala 29:58] - node _T_130 = cat(_T_129, _T_120) @[Cat.scala 29:58] - node _T_131 = cat(_T_130, _T_116) @[Cat.scala 29:58] - ld_byte_rhit_hi_lo <= _T_131 @[el2_lsu_bus_intf.scala 267:28] - node _T_132 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 268:89] - node _T_133 = and(ld_addr_rhit_hi_hi, _T_132) @[el2_lsu_bus_intf.scala 268:71] - node _T_134 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 268:111] - node _T_135 = and(_T_133, _T_134) @[el2_lsu_bus_intf.scala 268:93] - node _T_136 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 268:89] - node _T_137 = and(ld_addr_rhit_hi_hi, _T_136) @[el2_lsu_bus_intf.scala 268:71] - node _T_138 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 268:111] - node _T_139 = and(_T_137, _T_138) @[el2_lsu_bus_intf.scala 268:93] - node _T_140 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 268:89] - node _T_141 = and(ld_addr_rhit_hi_hi, _T_140) @[el2_lsu_bus_intf.scala 268:71] - node _T_142 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 268:111] - node _T_143 = and(_T_141, _T_142) @[el2_lsu_bus_intf.scala 268:93] - node _T_144 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 268:89] - node _T_145 = and(ld_addr_rhit_hi_hi, _T_144) @[el2_lsu_bus_intf.scala 268:71] - node _T_146 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 268:111] - node _T_147 = and(_T_145, _T_146) @[el2_lsu_bus_intf.scala 268:93] - node _T_148 = cat(_T_147, _T_143) @[Cat.scala 29:58] - node _T_149 = cat(_T_148, _T_139) @[Cat.scala 29:58] - node _T_150 = cat(_T_149, _T_135) @[Cat.scala 29:58] - ld_byte_rhit_hi_hi <= _T_150 @[el2_lsu_bus_intf.scala 268:28] - node _T_151 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 269:70] - node _T_152 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 269:94] - node _T_153 = or(_T_151, _T_152) @[el2_lsu_bus_intf.scala 269:74] - node _T_154 = bits(ld_byte_hit_buf_lo, 0, 0) @[el2_lsu_bus_intf.scala 269:118] - node _T_155 = or(_T_153, _T_154) @[el2_lsu_bus_intf.scala 269:98] - node _T_156 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 269:70] - node _T_157 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 269:94] - node _T_158 = or(_T_156, _T_157) @[el2_lsu_bus_intf.scala 269:74] - node _T_159 = bits(ld_byte_hit_buf_lo, 1, 1) @[el2_lsu_bus_intf.scala 269:118] - node _T_160 = or(_T_158, _T_159) @[el2_lsu_bus_intf.scala 269:98] - node _T_161 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 269:70] - node _T_162 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 269:94] - node _T_163 = or(_T_161, _T_162) @[el2_lsu_bus_intf.scala 269:74] - node _T_164 = bits(ld_byte_hit_buf_lo, 2, 2) @[el2_lsu_bus_intf.scala 269:118] - node _T_165 = or(_T_163, _T_164) @[el2_lsu_bus_intf.scala 269:98] - node _T_166 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 269:70] - node _T_167 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 269:94] - node _T_168 = or(_T_166, _T_167) @[el2_lsu_bus_intf.scala 269:74] - node _T_169 = bits(ld_byte_hit_buf_lo, 3, 3) @[el2_lsu_bus_intf.scala 269:118] - node _T_170 = or(_T_168, _T_169) @[el2_lsu_bus_intf.scala 269:98] - node _T_171 = cat(_T_170, _T_165) @[Cat.scala 29:58] - node _T_172 = cat(_T_171, _T_160) @[Cat.scala 29:58] - node _T_173 = cat(_T_172, _T_155) @[Cat.scala 29:58] - ld_byte_hit_lo <= _T_173 @[el2_lsu_bus_intf.scala 269:28] - node _T_174 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 270:70] - node _T_175 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 270:94] - node _T_176 = or(_T_174, _T_175) @[el2_lsu_bus_intf.scala 270:74] - node _T_177 = bits(ld_byte_hit_buf_hi, 0, 0) @[el2_lsu_bus_intf.scala 270:118] - node _T_178 = or(_T_176, _T_177) @[el2_lsu_bus_intf.scala 270:98] - node _T_179 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 270:70] - node _T_180 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 270:94] - node _T_181 = or(_T_179, _T_180) @[el2_lsu_bus_intf.scala 270:74] - node _T_182 = bits(ld_byte_hit_buf_hi, 1, 1) @[el2_lsu_bus_intf.scala 270:118] - node _T_183 = or(_T_181, _T_182) @[el2_lsu_bus_intf.scala 270:98] - node _T_184 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 270:70] - node _T_185 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 270:94] - node _T_186 = or(_T_184, _T_185) @[el2_lsu_bus_intf.scala 270:74] - node _T_187 = bits(ld_byte_hit_buf_hi, 2, 2) @[el2_lsu_bus_intf.scala 270:118] - node _T_188 = or(_T_186, _T_187) @[el2_lsu_bus_intf.scala 270:98] - node _T_189 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 270:70] - node _T_190 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 270:94] - node _T_191 = or(_T_189, _T_190) @[el2_lsu_bus_intf.scala 270:74] - node _T_192 = bits(ld_byte_hit_buf_hi, 3, 3) @[el2_lsu_bus_intf.scala 270:118] - node _T_193 = or(_T_191, _T_192) @[el2_lsu_bus_intf.scala 270:98] - node _T_194 = cat(_T_193, _T_188) @[Cat.scala 29:58] - node _T_195 = cat(_T_194, _T_183) @[Cat.scala 29:58] - node _T_196 = cat(_T_195, _T_178) @[Cat.scala 29:58] - ld_byte_hit_hi <= _T_196 @[el2_lsu_bus_intf.scala 270:28] - node _T_197 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 271:70] - node _T_198 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 271:94] - node _T_199 = or(_T_197, _T_198) @[el2_lsu_bus_intf.scala 271:74] - node _T_200 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 271:70] - node _T_201 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 271:94] - node _T_202 = or(_T_200, _T_201) @[el2_lsu_bus_intf.scala 271:74] - node _T_203 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 271:70] - node _T_204 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 271:94] - node _T_205 = or(_T_203, _T_204) @[el2_lsu_bus_intf.scala 271:74] - node _T_206 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 271:70] - node _T_207 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 271:94] - node _T_208 = or(_T_206, _T_207) @[el2_lsu_bus_intf.scala 271:74] - node _T_209 = cat(_T_208, _T_205) @[Cat.scala 29:58] - node _T_210 = cat(_T_209, _T_202) @[Cat.scala 29:58] - node _T_211 = cat(_T_210, _T_199) @[Cat.scala 29:58] - ld_byte_rhit_lo <= _T_211 @[el2_lsu_bus_intf.scala 271:28] - node _T_212 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 272:70] - node _T_213 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 272:94] - node _T_214 = or(_T_212, _T_213) @[el2_lsu_bus_intf.scala 272:74] - node _T_215 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 272:70] - node _T_216 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 272:94] - node _T_217 = or(_T_215, _T_216) @[el2_lsu_bus_intf.scala 272:74] - node _T_218 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 272:70] - node _T_219 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 272:94] - node _T_220 = or(_T_218, _T_219) @[el2_lsu_bus_intf.scala 272:74] - node _T_221 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 272:70] - node _T_222 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 272:94] - node _T_223 = or(_T_221, _T_222) @[el2_lsu_bus_intf.scala 272:74] - node _T_224 = cat(_T_223, _T_220) @[Cat.scala 29:58] - node _T_225 = cat(_T_224, _T_217) @[Cat.scala 29:58] - node _T_226 = cat(_T_225, _T_214) @[Cat.scala 29:58] - ld_byte_rhit_hi <= _T_226 @[el2_lsu_bus_intf.scala 272:28] - node _T_227 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 273:80] - node _T_228 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 273:102] - node _T_229 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 273:137] - node _T_230 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 273:159] - node _T_231 = mux(_T_227, _T_228, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_232 = mux(_T_229, _T_230, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_233 = or(_T_231, _T_232) @[Mux.scala 27:72] - wire _T_234 : UInt<8> @[Mux.scala 27:72] - _T_234 <= _T_233 @[Mux.scala 27:72] - node _T_235 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 273:80] - node _T_236 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 273:102] - node _T_237 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 273:137] - node _T_238 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 273:159] - node _T_239 = mux(_T_235, _T_236, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_240 = mux(_T_237, _T_238, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_241 = or(_T_239, _T_240) @[Mux.scala 27:72] - wire _T_242 : UInt<8> @[Mux.scala 27:72] - _T_242 <= _T_241 @[Mux.scala 27:72] - node _T_243 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 273:80] - node _T_244 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 273:102] - node _T_245 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 273:137] - node _T_246 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 273:159] - node _T_247 = mux(_T_243, _T_244, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_248 = mux(_T_245, _T_246, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_249 = or(_T_247, _T_248) @[Mux.scala 27:72] - wire _T_250 : UInt<8> @[Mux.scala 27:72] - _T_250 <= _T_249 @[Mux.scala 27:72] - node _T_251 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 273:80] - node _T_252 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 273:102] - node _T_253 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 273:137] - node _T_254 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 273:159] - node _T_255 = mux(_T_251, _T_252, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_256 = mux(_T_253, _T_254, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_257 = or(_T_255, _T_256) @[Mux.scala 27:72] - wire _T_258 : UInt<8> @[Mux.scala 27:72] - _T_258 <= _T_257 @[Mux.scala 27:72] - node _T_259 = cat(_T_258, _T_250) @[Cat.scala 29:58] - node _T_260 = cat(_T_259, _T_242) @[Cat.scala 29:58] - node _T_261 = cat(_T_260, _T_234) @[Cat.scala 29:58] - ld_fwddata_rpipe_lo <= _T_261 @[el2_lsu_bus_intf.scala 273:28] - node _T_262 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 274:80] - node _T_263 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 274:102] - node _T_264 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 274:137] - node _T_265 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 274:159] - node _T_266 = mux(_T_262, _T_263, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_267 = mux(_T_264, _T_265, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_268 = or(_T_266, _T_267) @[Mux.scala 27:72] - wire _T_269 : UInt<8> @[Mux.scala 27:72] - _T_269 <= _T_268 @[Mux.scala 27:72] - node _T_270 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 274:80] - node _T_271 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 274:102] - node _T_272 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 274:137] - node _T_273 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 274:159] - node _T_274 = mux(_T_270, _T_271, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_275 = mux(_T_272, _T_273, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_276 = or(_T_274, _T_275) @[Mux.scala 27:72] - wire _T_277 : UInt<8> @[Mux.scala 27:72] - _T_277 <= _T_276 @[Mux.scala 27:72] - node _T_278 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 274:80] - node _T_279 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 274:102] - node _T_280 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 274:137] - node _T_281 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 274:159] - node _T_282 = mux(_T_278, _T_279, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_283 = mux(_T_280, _T_281, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_284 = or(_T_282, _T_283) @[Mux.scala 27:72] - wire _T_285 : UInt<8> @[Mux.scala 27:72] - _T_285 <= _T_284 @[Mux.scala 27:72] - node _T_286 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 274:80] - node _T_287 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 274:102] - node _T_288 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 274:137] - node _T_289 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 274:159] - node _T_290 = mux(_T_286, _T_287, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_291 = mux(_T_288, _T_289, UInt<1>("h00")) @[Mux.scala 27:72] - node _T_292 = or(_T_290, _T_291) @[Mux.scala 27:72] - wire _T_293 : UInt<8> @[Mux.scala 27:72] - _T_293 <= _T_292 @[Mux.scala 27:72] - node _T_294 = cat(_T_293, _T_285) @[Cat.scala 29:58] - node _T_295 = cat(_T_294, _T_277) @[Cat.scala 29:58] - node _T_296 = cat(_T_295, _T_269) @[Cat.scala 29:58] - ld_fwddata_rpipe_hi <= _T_296 @[el2_lsu_bus_intf.scala 274:28] - node _T_297 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_bus_intf.scala 275:71] - node _T_298 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_bus_intf.scala 275:95] - node _T_299 = bits(ld_fwddata_buf_lo, 7, 0) @[el2_lsu_bus_intf.scala 275:129] - node _T_300 = mux(_T_297, _T_298, _T_299) @[el2_lsu_bus_intf.scala 275:55] - node _T_301 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_bus_intf.scala 275:71] - node _T_302 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_bus_intf.scala 275:95] - node _T_303 = bits(ld_fwddata_buf_lo, 15, 8) @[el2_lsu_bus_intf.scala 275:129] - node _T_304 = mux(_T_301, _T_302, _T_303) @[el2_lsu_bus_intf.scala 275:55] - node _T_305 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_bus_intf.scala 275:71] - node _T_306 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_bus_intf.scala 275:95] - node _T_307 = bits(ld_fwddata_buf_lo, 23, 16) @[el2_lsu_bus_intf.scala 275:129] - node _T_308 = mux(_T_305, _T_306, _T_307) @[el2_lsu_bus_intf.scala 275:55] - node _T_309 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_bus_intf.scala 275:71] - node _T_310 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_bus_intf.scala 275:95] - node _T_311 = bits(ld_fwddata_buf_lo, 31, 24) @[el2_lsu_bus_intf.scala 275:129] - node _T_312 = mux(_T_309, _T_310, _T_311) @[el2_lsu_bus_intf.scala 275:55] - node _T_313 = cat(_T_312, _T_308) @[Cat.scala 29:58] - node _T_314 = cat(_T_313, _T_304) @[Cat.scala 29:58] - node _T_315 = cat(_T_314, _T_300) @[Cat.scala 29:58] - ld_fwddata_lo <= _T_315 @[el2_lsu_bus_intf.scala 275:28] - node _T_316 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_bus_intf.scala 276:71] - node _T_317 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_bus_intf.scala 276:95] - node _T_318 = bits(ld_fwddata_buf_hi, 7, 0) @[el2_lsu_bus_intf.scala 276:129] - node _T_319 = mux(_T_316, _T_317, _T_318) @[el2_lsu_bus_intf.scala 276:55] - node _T_320 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_bus_intf.scala 276:71] - node _T_321 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_bus_intf.scala 276:95] - node _T_322 = bits(ld_fwddata_buf_hi, 15, 8) @[el2_lsu_bus_intf.scala 276:129] - node _T_323 = mux(_T_320, _T_321, _T_322) @[el2_lsu_bus_intf.scala 276:55] - node _T_324 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_bus_intf.scala 276:71] - node _T_325 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_bus_intf.scala 276:95] - node _T_326 = bits(ld_fwddata_buf_hi, 23, 16) @[el2_lsu_bus_intf.scala 276:129] - node _T_327 = mux(_T_324, _T_325, _T_326) @[el2_lsu_bus_intf.scala 276:55] - node _T_328 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_bus_intf.scala 276:71] - node _T_329 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_bus_intf.scala 276:95] - node _T_330 = bits(ld_fwddata_buf_hi, 31, 24) @[el2_lsu_bus_intf.scala 276:129] - node _T_331 = mux(_T_328, _T_329, _T_330) @[el2_lsu_bus_intf.scala 276:55] - node _T_332 = cat(_T_331, _T_327) @[Cat.scala 29:58] - node _T_333 = cat(_T_332, _T_323) @[Cat.scala 29:58] - node _T_334 = cat(_T_333, _T_319) @[Cat.scala 29:58] - ld_fwddata_hi <= _T_334 @[el2_lsu_bus_intf.scala 276:28] - node _T_335 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_bus_intf.scala 277:67] - node _T_336 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 277:90] - node _T_337 = not(_T_336) @[el2_lsu_bus_intf.scala 277:73] - node _T_338 = or(_T_335, _T_337) @[el2_lsu_bus_intf.scala 277:71] - node _T_339 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_bus_intf.scala 277:67] - node _T_340 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 277:90] - node _T_341 = not(_T_340) @[el2_lsu_bus_intf.scala 277:73] - node _T_342 = or(_T_339, _T_341) @[el2_lsu_bus_intf.scala 277:71] - node _T_343 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_bus_intf.scala 277:67] - node _T_344 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 277:90] - node _T_345 = not(_T_344) @[el2_lsu_bus_intf.scala 277:73] - node _T_346 = or(_T_343, _T_345) @[el2_lsu_bus_intf.scala 277:71] - node _T_347 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_bus_intf.scala 277:67] - node _T_348 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 277:90] - node _T_349 = not(_T_348) @[el2_lsu_bus_intf.scala 277:73] - node _T_350 = or(_T_347, _T_349) @[el2_lsu_bus_intf.scala 277:71] - node _T_351 = and(_T_338, _T_342) @[el2_lsu_bus_intf.scala 277:112] - node _T_352 = and(_T_351, _T_346) @[el2_lsu_bus_intf.scala 277:112] - node _T_353 = and(_T_352, _T_350) @[el2_lsu_bus_intf.scala 277:112] - ld_full_hit_lo_m <= _T_353 @[el2_lsu_bus_intf.scala 277:28] - node _T_354 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_bus_intf.scala 278:67] - node _T_355 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 278:90] - node _T_356 = not(_T_355) @[el2_lsu_bus_intf.scala 278:73] - node _T_357 = or(_T_354, _T_356) @[el2_lsu_bus_intf.scala 278:71] - node _T_358 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_bus_intf.scala 278:67] - node _T_359 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 278:90] - node _T_360 = not(_T_359) @[el2_lsu_bus_intf.scala 278:73] - node _T_361 = or(_T_358, _T_360) @[el2_lsu_bus_intf.scala 278:71] - node _T_362 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_bus_intf.scala 278:67] - node _T_363 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 278:90] - node _T_364 = not(_T_363) @[el2_lsu_bus_intf.scala 278:73] - node _T_365 = or(_T_362, _T_364) @[el2_lsu_bus_intf.scala 278:71] - node _T_366 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_bus_intf.scala 278:67] - node _T_367 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 278:90] - node _T_368 = not(_T_367) @[el2_lsu_bus_intf.scala 278:73] - node _T_369 = or(_T_366, _T_368) @[el2_lsu_bus_intf.scala 278:71] - node _T_370 = and(_T_357, _T_361) @[el2_lsu_bus_intf.scala 278:112] - node _T_371 = and(_T_370, _T_365) @[el2_lsu_bus_intf.scala 278:112] - node _T_372 = and(_T_371, _T_369) @[el2_lsu_bus_intf.scala 278:112] - ld_full_hit_hi_m <= _T_372 @[el2_lsu_bus_intf.scala 278:28] - node _T_373 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[el2_lsu_bus_intf.scala 279:48] - node _T_374 = and(_T_373, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 279:67] - node _T_375 = and(_T_374, io.lsu_pkt_m.load) @[el2_lsu_bus_intf.scala 279:85] - node _T_376 = not(io.is_sideeffects_m) @[el2_lsu_bus_intf.scala 279:107] - node _T_377 = and(_T_375, _T_376) @[el2_lsu_bus_intf.scala 279:105] - ld_full_hit_m <= _T_377 @[el2_lsu_bus_intf.scala 279:28] - node _T_378 = bits(ld_fwddata_hi, 31, 0) @[el2_lsu_bus_intf.scala 280:48] - node _T_379 = bits(ld_fwddata_lo, 31, 0) @[el2_lsu_bus_intf.scala 280:69] - node _T_380 = cat(_T_378, _T_379) @[Cat.scala 29:58] - node _T_381 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 280:98] - node _T_382 = mul(UInt<4>("h08"), _T_381) @[el2_lsu_bus_intf.scala 280:84] - node _T_383 = dshr(_T_380, _T_382) @[el2_lsu_bus_intf.scala 280:77] - ld_fwddata_m <= _T_383 @[el2_lsu_bus_intf.scala 280:28] - node _T_384 = bits(ld_fwddata_m, 31, 0) @[el2_lsu_bus_intf.scala 281:43] - io.bus_read_data_m <= _T_384 @[el2_lsu_bus_intf.scala 281:28] - reg _T_385 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 284:34] - _T_385 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 284:34] - lsu_bus_clk_en_q <= _T_385 @[el2_lsu_bus_intf.scala 284:24] - reg _T_386 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 287:29] - _T_386 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 287:29] - ldst_dual_m <= _T_386 @[el2_lsu_bus_intf.scala 287:19] - reg _T_387 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 290:35] - _T_387 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 290:35] - ldst_dual_r <= _T_387 @[el2_lsu_bus_intf.scala 290:25] - reg _T_388 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 291:35] - _T_388 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 291:35] - is_sideeffects_r <= _T_388 @[el2_lsu_bus_intf.scala 291:25] - reg _T_389 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[el2_lsu_bus_intf.scala 292:35] - _T_389 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 292:35] - ldst_byteen_r <= _T_389 @[el2_lsu_bus_intf.scala 292:25] + ldst_byteen_m <= _T_8 @[el2_lsu_bus_intf.scala 276:27] + node _T_9 = bits(io.lsu_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 277:43] + node _T_10 = bits(io.end_addr_d, 2, 2) @[el2_lsu_bus_intf.scala 277:64] + node _T_11 = neq(_T_9, _T_10) @[el2_lsu_bus_intf.scala 277:47] + ldst_dual_d <= _T_11 @[el2_lsu_bus_intf.scala 277:27] + node _T_12 = bits(io.lsu_addr_r, 31, 3) @[el2_lsu_bus_intf.scala 278:44] + node _T_13 = bits(io.lsu_addr_m, 31, 3) @[el2_lsu_bus_intf.scala 278:68] + node _T_14 = eq(_T_12, _T_13) @[el2_lsu_bus_intf.scala 278:51] + addr_match_dw_lo_r_m <= _T_14 @[el2_lsu_bus_intf.scala 278:27] + node _T_15 = bits(io.lsu_addr_r, 2, 2) @[el2_lsu_bus_intf.scala 279:68] + node _T_16 = bits(io.lsu_addr_m, 2, 2) @[el2_lsu_bus_intf.scala 279:85] + node _T_17 = xor(_T_15, _T_16) @[el2_lsu_bus_intf.scala 279:71] + node _T_18 = eq(_T_17, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 279:53] + node _T_19 = and(addr_match_dw_lo_r_m, _T_18) @[el2_lsu_bus_intf.scala 279:51] + addr_match_word_lo_r_m <= _T_19 @[el2_lsu_bus_intf.scala 279:27] + node _T_20 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:48] + node _T_21 = and(io.lsu_busreq_r, _T_20) @[el2_lsu_bus_intf.scala 280:46] + node _T_22 = and(_T_21, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 280:61] + node _T_23 = eq(addr_match_word_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 280:102] + node _T_24 = or(io.lsu_pkt_m.load, _T_23) @[el2_lsu_bus_intf.scala 280:100] + node _T_25 = and(_T_22, _T_24) @[el2_lsu_bus_intf.scala 280:79] + no_word_merge_r <= _T_25 @[el2_lsu_bus_intf.scala 280:27] + node _T_26 = eq(ldst_dual_r, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:48] + node _T_27 = and(io.lsu_busreq_r, _T_26) @[el2_lsu_bus_intf.scala 281:46] + node _T_28 = and(_T_27, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 281:61] + node _T_29 = eq(addr_match_dw_lo_r_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 281:102] + node _T_30 = or(io.lsu_pkt_m.load, _T_29) @[el2_lsu_bus_intf.scala 281:100] + node _T_31 = and(_T_28, _T_30) @[el2_lsu_bus_intf.scala 281:79] + no_dword_merge_r <= _T_31 @[el2_lsu_bus_intf.scala 281:27] + node _T_32 = bits(ldst_byteen_m, 3, 0) @[el2_lsu_bus_intf.scala 283:43] + node _T_33 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 283:65] + node _T_34 = dshl(_T_32, _T_33) @[el2_lsu_bus_intf.scala 283:49] + ldst_byteen_ext_m <= _T_34 @[el2_lsu_bus_intf.scala 283:27] + node _T_35 = bits(ldst_byteen_r, 3, 0) @[el2_lsu_bus_intf.scala 284:43] + node _T_36 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 284:65] + node _T_37 = dshl(_T_35, _T_36) @[el2_lsu_bus_intf.scala 284:49] + ldst_byteen_ext_r <= _T_37 @[el2_lsu_bus_intf.scala 284:27] + node _T_38 = bits(io.store_data_r, 31, 0) @[el2_lsu_bus_intf.scala 285:45] + node _T_39 = bits(io.lsu_addr_r, 1, 0) @[el2_lsu_bus_intf.scala 285:72] + node _T_40 = cat(_T_39, UInt<3>("h00")) @[Cat.scala 29:58] + node _T_41 = dshl(_T_38, _T_40) @[el2_lsu_bus_intf.scala 285:52] + store_data_ext_r <= _T_41 @[el2_lsu_bus_intf.scala 285:27] + node _T_42 = bits(ldst_byteen_ext_m, 7, 4) @[el2_lsu_bus_intf.scala 286:47] + ldst_byteen_hi_m <= _T_42 @[el2_lsu_bus_intf.scala 286:27] + node _T_43 = bits(ldst_byteen_ext_m, 3, 0) @[el2_lsu_bus_intf.scala 287:47] + ldst_byteen_lo_m <= _T_43 @[el2_lsu_bus_intf.scala 287:27] + node _T_44 = bits(ldst_byteen_ext_r, 7, 4) @[el2_lsu_bus_intf.scala 288:47] + ldst_byteen_hi_r <= _T_44 @[el2_lsu_bus_intf.scala 288:27] + node _T_45 = bits(ldst_byteen_ext_r, 3, 0) @[el2_lsu_bus_intf.scala 289:47] + ldst_byteen_lo_r <= _T_45 @[el2_lsu_bus_intf.scala 289:27] + node _T_46 = bits(store_data_ext_r, 63, 32) @[el2_lsu_bus_intf.scala 291:46] + store_data_hi_r <= _T_46 @[el2_lsu_bus_intf.scala 291:27] + node _T_47 = bits(store_data_ext_r, 31, 0) @[el2_lsu_bus_intf.scala 292:46] + store_data_lo_r <= _T_47 @[el2_lsu_bus_intf.scala 292:27] + node _T_48 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 293:44] + node _T_49 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 293:68] + node _T_50 = eq(_T_48, _T_49) @[el2_lsu_bus_intf.scala 293:51] + node _T_51 = and(_T_50, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 293:76] + node _T_52 = and(_T_51, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 293:97] + node _T_53 = and(_T_52, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 293:118] + ld_addr_rhit_lo_lo <= _T_53 @[el2_lsu_bus_intf.scala 293:27] + node _T_54 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 294:44] + node _T_55 = bits(io.lsu_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 294:68] + node _T_56 = eq(_T_54, _T_55) @[el2_lsu_bus_intf.scala 294:51] + node _T_57 = and(_T_56, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 294:76] + node _T_58 = and(_T_57, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 294:97] + node _T_59 = and(_T_58, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 294:118] + ld_addr_rhit_lo_hi <= _T_59 @[el2_lsu_bus_intf.scala 294:27] + node _T_60 = bits(io.lsu_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 295:44] + node _T_61 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 295:68] + node _T_62 = eq(_T_60, _T_61) @[el2_lsu_bus_intf.scala 295:51] + node _T_63 = and(_T_62, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 295:76] + node _T_64 = and(_T_63, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 295:97] + node _T_65 = and(_T_64, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 295:118] + ld_addr_rhit_hi_lo <= _T_65 @[el2_lsu_bus_intf.scala 295:27] + node _T_66 = bits(io.end_addr_m, 31, 2) @[el2_lsu_bus_intf.scala 296:44] + node _T_67 = bits(io.end_addr_r, 31, 2) @[el2_lsu_bus_intf.scala 296:68] + node _T_68 = eq(_T_66, _T_67) @[el2_lsu_bus_intf.scala 296:51] + node _T_69 = and(_T_68, io.lsu_pkt_r.valid) @[el2_lsu_bus_intf.scala 296:76] + node _T_70 = and(_T_69, io.lsu_pkt_r.store) @[el2_lsu_bus_intf.scala 296:97] + node _T_71 = and(_T_70, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 296:118] + ld_addr_rhit_hi_hi <= _T_71 @[el2_lsu_bus_intf.scala 296:27] + node _T_72 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 298:88] + node _T_73 = and(ld_addr_rhit_lo_lo, _T_72) @[el2_lsu_bus_intf.scala 298:70] + node _T_74 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 298:110] + node _T_75 = and(_T_73, _T_74) @[el2_lsu_bus_intf.scala 298:92] + node _T_76 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 298:88] + node _T_77 = and(ld_addr_rhit_lo_lo, _T_76) @[el2_lsu_bus_intf.scala 298:70] + node _T_78 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 298:110] + node _T_79 = and(_T_77, _T_78) @[el2_lsu_bus_intf.scala 298:92] + node _T_80 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 298:88] + node _T_81 = and(ld_addr_rhit_lo_lo, _T_80) @[el2_lsu_bus_intf.scala 298:70] + node _T_82 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 298:110] + node _T_83 = and(_T_81, _T_82) @[el2_lsu_bus_intf.scala 298:92] + node _T_84 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 298:88] + node _T_85 = and(ld_addr_rhit_lo_lo, _T_84) @[el2_lsu_bus_intf.scala 298:70] + node _T_86 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 298:110] + node _T_87 = and(_T_85, _T_86) @[el2_lsu_bus_intf.scala 298:92] + node _T_88 = cat(_T_87, _T_83) @[Cat.scala 29:58] + node _T_89 = cat(_T_88, _T_79) @[Cat.scala 29:58] + node _T_90 = cat(_T_89, _T_75) @[Cat.scala 29:58] + ld_byte_rhit_lo_lo <= _T_90 @[el2_lsu_bus_intf.scala 298:27] + node _T_91 = bits(ldst_byteen_lo_r, 0, 0) @[el2_lsu_bus_intf.scala 299:88] + node _T_92 = and(ld_addr_rhit_lo_hi, _T_91) @[el2_lsu_bus_intf.scala 299:70] + node _T_93 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 299:110] + node _T_94 = and(_T_92, _T_93) @[el2_lsu_bus_intf.scala 299:92] + node _T_95 = bits(ldst_byteen_lo_r, 1, 1) @[el2_lsu_bus_intf.scala 299:88] + node _T_96 = and(ld_addr_rhit_lo_hi, _T_95) @[el2_lsu_bus_intf.scala 299:70] + node _T_97 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 299:110] + node _T_98 = and(_T_96, _T_97) @[el2_lsu_bus_intf.scala 299:92] + node _T_99 = bits(ldst_byteen_lo_r, 2, 2) @[el2_lsu_bus_intf.scala 299:88] + node _T_100 = and(ld_addr_rhit_lo_hi, _T_99) @[el2_lsu_bus_intf.scala 299:70] + node _T_101 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 299:110] + node _T_102 = and(_T_100, _T_101) @[el2_lsu_bus_intf.scala 299:92] + node _T_103 = bits(ldst_byteen_lo_r, 3, 3) @[el2_lsu_bus_intf.scala 299:88] + node _T_104 = and(ld_addr_rhit_lo_hi, _T_103) @[el2_lsu_bus_intf.scala 299:70] + node _T_105 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 299:110] + node _T_106 = and(_T_104, _T_105) @[el2_lsu_bus_intf.scala 299:92] + node _T_107 = cat(_T_106, _T_102) @[Cat.scala 29:58] + node _T_108 = cat(_T_107, _T_98) @[Cat.scala 29:58] + node _T_109 = cat(_T_108, _T_94) @[Cat.scala 29:58] + ld_byte_rhit_lo_hi <= _T_109 @[el2_lsu_bus_intf.scala 299:27] + node _T_110 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 300:88] + node _T_111 = and(ld_addr_rhit_hi_lo, _T_110) @[el2_lsu_bus_intf.scala 300:70] + node _T_112 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 300:110] + node _T_113 = and(_T_111, _T_112) @[el2_lsu_bus_intf.scala 300:92] + node _T_114 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 300:88] + node _T_115 = and(ld_addr_rhit_hi_lo, _T_114) @[el2_lsu_bus_intf.scala 300:70] + node _T_116 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 300:110] + node _T_117 = and(_T_115, _T_116) @[el2_lsu_bus_intf.scala 300:92] + node _T_118 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 300:88] + node _T_119 = and(ld_addr_rhit_hi_lo, _T_118) @[el2_lsu_bus_intf.scala 300:70] + node _T_120 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 300:110] + node _T_121 = and(_T_119, _T_120) @[el2_lsu_bus_intf.scala 300:92] + node _T_122 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 300:88] + node _T_123 = and(ld_addr_rhit_hi_lo, _T_122) @[el2_lsu_bus_intf.scala 300:70] + node _T_124 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 300:110] + node _T_125 = and(_T_123, _T_124) @[el2_lsu_bus_intf.scala 300:92] + node _T_126 = cat(_T_125, _T_121) @[Cat.scala 29:58] + node _T_127 = cat(_T_126, _T_117) @[Cat.scala 29:58] + node _T_128 = cat(_T_127, _T_113) @[Cat.scala 29:58] + ld_byte_rhit_hi_lo <= _T_128 @[el2_lsu_bus_intf.scala 300:27] + node _T_129 = bits(ldst_byteen_hi_r, 0, 0) @[el2_lsu_bus_intf.scala 301:88] + node _T_130 = and(ld_addr_rhit_hi_hi, _T_129) @[el2_lsu_bus_intf.scala 301:70] + node _T_131 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 301:110] + node _T_132 = and(_T_130, _T_131) @[el2_lsu_bus_intf.scala 301:92] + node _T_133 = bits(ldst_byteen_hi_r, 1, 1) @[el2_lsu_bus_intf.scala 301:88] + node _T_134 = and(ld_addr_rhit_hi_hi, _T_133) @[el2_lsu_bus_intf.scala 301:70] + node _T_135 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 301:110] + node _T_136 = and(_T_134, _T_135) @[el2_lsu_bus_intf.scala 301:92] + node _T_137 = bits(ldst_byteen_hi_r, 2, 2) @[el2_lsu_bus_intf.scala 301:88] + node _T_138 = and(ld_addr_rhit_hi_hi, _T_137) @[el2_lsu_bus_intf.scala 301:70] + node _T_139 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 301:110] + node _T_140 = and(_T_138, _T_139) @[el2_lsu_bus_intf.scala 301:92] + node _T_141 = bits(ldst_byteen_hi_r, 3, 3) @[el2_lsu_bus_intf.scala 301:88] + node _T_142 = and(ld_addr_rhit_hi_hi, _T_141) @[el2_lsu_bus_intf.scala 301:70] + node _T_143 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 301:110] + node _T_144 = and(_T_142, _T_143) @[el2_lsu_bus_intf.scala 301:92] + node _T_145 = cat(_T_144, _T_140) @[Cat.scala 29:58] + node _T_146 = cat(_T_145, _T_136) @[Cat.scala 29:58] + node _T_147 = cat(_T_146, _T_132) @[Cat.scala 29:58] + ld_byte_rhit_hi_hi <= _T_147 @[el2_lsu_bus_intf.scala 301:27] + node _T_148 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:69] + node _T_149 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:93] + node _T_150 = or(_T_148, _T_149) @[el2_lsu_bus_intf.scala 303:73] + node _T_151 = bits(ld_byte_hit_buf_lo, 0, 0) @[el2_lsu_bus_intf.scala 303:117] + node _T_152 = or(_T_150, _T_151) @[el2_lsu_bus_intf.scala 303:97] + node _T_153 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:69] + node _T_154 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:93] + node _T_155 = or(_T_153, _T_154) @[el2_lsu_bus_intf.scala 303:73] + node _T_156 = bits(ld_byte_hit_buf_lo, 1, 1) @[el2_lsu_bus_intf.scala 303:117] + node _T_157 = or(_T_155, _T_156) @[el2_lsu_bus_intf.scala 303:97] + node _T_158 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:69] + node _T_159 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:93] + node _T_160 = or(_T_158, _T_159) @[el2_lsu_bus_intf.scala 303:73] + node _T_161 = bits(ld_byte_hit_buf_lo, 2, 2) @[el2_lsu_bus_intf.scala 303:117] + node _T_162 = or(_T_160, _T_161) @[el2_lsu_bus_intf.scala 303:97] + node _T_163 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:69] + node _T_164 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:93] + node _T_165 = or(_T_163, _T_164) @[el2_lsu_bus_intf.scala 303:73] + node _T_166 = bits(ld_byte_hit_buf_lo, 3, 3) @[el2_lsu_bus_intf.scala 303:117] + node _T_167 = or(_T_165, _T_166) @[el2_lsu_bus_intf.scala 303:97] + node _T_168 = cat(_T_167, _T_162) @[Cat.scala 29:58] + node _T_169 = cat(_T_168, _T_157) @[Cat.scala 29:58] + node _T_170 = cat(_T_169, _T_152) @[Cat.scala 29:58] + ld_byte_hit_lo <= _T_170 @[el2_lsu_bus_intf.scala 303:27] + node _T_171 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:69] + node _T_172 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:93] + node _T_173 = or(_T_171, _T_172) @[el2_lsu_bus_intf.scala 304:73] + node _T_174 = bits(ld_byte_hit_buf_hi, 0, 0) @[el2_lsu_bus_intf.scala 304:117] + node _T_175 = or(_T_173, _T_174) @[el2_lsu_bus_intf.scala 304:97] + node _T_176 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:69] + node _T_177 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:93] + node _T_178 = or(_T_176, _T_177) @[el2_lsu_bus_intf.scala 304:73] + node _T_179 = bits(ld_byte_hit_buf_hi, 1, 1) @[el2_lsu_bus_intf.scala 304:117] + node _T_180 = or(_T_178, _T_179) @[el2_lsu_bus_intf.scala 304:97] + node _T_181 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:69] + node _T_182 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:93] + node _T_183 = or(_T_181, _T_182) @[el2_lsu_bus_intf.scala 304:73] + node _T_184 = bits(ld_byte_hit_buf_hi, 2, 2) @[el2_lsu_bus_intf.scala 304:117] + node _T_185 = or(_T_183, _T_184) @[el2_lsu_bus_intf.scala 304:97] + node _T_186 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:69] + node _T_187 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:93] + node _T_188 = or(_T_186, _T_187) @[el2_lsu_bus_intf.scala 304:73] + node _T_189 = bits(ld_byte_hit_buf_hi, 3, 3) @[el2_lsu_bus_intf.scala 304:117] + node _T_190 = or(_T_188, _T_189) @[el2_lsu_bus_intf.scala 304:97] + node _T_191 = cat(_T_190, _T_185) @[Cat.scala 29:58] + node _T_192 = cat(_T_191, _T_180) @[Cat.scala 29:58] + node _T_193 = cat(_T_192, _T_175) @[Cat.scala 29:58] + ld_byte_hit_hi <= _T_193 @[el2_lsu_bus_intf.scala 304:27] + node _T_194 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 305:69] + node _T_195 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 305:93] + node _T_196 = or(_T_194, _T_195) @[el2_lsu_bus_intf.scala 305:73] + node _T_197 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 305:69] + node _T_198 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 305:93] + node _T_199 = or(_T_197, _T_198) @[el2_lsu_bus_intf.scala 305:73] + node _T_200 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 305:69] + node _T_201 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 305:93] + node _T_202 = or(_T_200, _T_201) @[el2_lsu_bus_intf.scala 305:73] + node _T_203 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 305:69] + node _T_204 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 305:93] + node _T_205 = or(_T_203, _T_204) @[el2_lsu_bus_intf.scala 305:73] + node _T_206 = cat(_T_205, _T_202) @[Cat.scala 29:58] + node _T_207 = cat(_T_206, _T_199) @[Cat.scala 29:58] + node _T_208 = cat(_T_207, _T_196) @[Cat.scala 29:58] + ld_byte_rhit_lo <= _T_208 @[el2_lsu_bus_intf.scala 305:27] + node _T_209 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 306:69] + node _T_210 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 306:93] + node _T_211 = or(_T_209, _T_210) @[el2_lsu_bus_intf.scala 306:73] + node _T_212 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 306:69] + node _T_213 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 306:93] + node _T_214 = or(_T_212, _T_213) @[el2_lsu_bus_intf.scala 306:73] + node _T_215 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 306:69] + node _T_216 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 306:93] + node _T_217 = or(_T_215, _T_216) @[el2_lsu_bus_intf.scala 306:73] + node _T_218 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 306:69] + node _T_219 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 306:93] + node _T_220 = or(_T_218, _T_219) @[el2_lsu_bus_intf.scala 306:73] + node _T_221 = cat(_T_220, _T_217) @[Cat.scala 29:58] + node _T_222 = cat(_T_221, _T_214) @[Cat.scala 29:58] + node _T_223 = cat(_T_222, _T_211) @[Cat.scala 29:58] + ld_byte_rhit_hi <= _T_223 @[el2_lsu_bus_intf.scala 306:27] + node _T_224 = bits(ld_byte_rhit_lo_lo, 0, 0) @[el2_lsu_bus_intf.scala 307:79] + node _T_225 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 307:101] + node _T_226 = bits(ld_byte_rhit_hi_lo, 0, 0) @[el2_lsu_bus_intf.scala 307:136] + node _T_227 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 307:158] + node _T_228 = mux(_T_224, _T_225, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_229 = mux(_T_226, _T_227, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_230 = or(_T_228, _T_229) @[Mux.scala 27:72] + wire _T_231 : UInt<8> @[Mux.scala 27:72] + _T_231 <= _T_230 @[Mux.scala 27:72] + node _T_232 = bits(ld_byte_rhit_lo_lo, 1, 1) @[el2_lsu_bus_intf.scala 307:79] + node _T_233 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 307:101] + node _T_234 = bits(ld_byte_rhit_hi_lo, 1, 1) @[el2_lsu_bus_intf.scala 307:136] + node _T_235 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 307:158] + node _T_236 = mux(_T_232, _T_233, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_237 = mux(_T_234, _T_235, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_238 = or(_T_236, _T_237) @[Mux.scala 27:72] + wire _T_239 : UInt<8> @[Mux.scala 27:72] + _T_239 <= _T_238 @[Mux.scala 27:72] + node _T_240 = bits(ld_byte_rhit_lo_lo, 2, 2) @[el2_lsu_bus_intf.scala 307:79] + node _T_241 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 307:101] + node _T_242 = bits(ld_byte_rhit_hi_lo, 2, 2) @[el2_lsu_bus_intf.scala 307:136] + node _T_243 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 307:158] + node _T_244 = mux(_T_240, _T_241, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_245 = mux(_T_242, _T_243, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_246 = or(_T_244, _T_245) @[Mux.scala 27:72] + wire _T_247 : UInt<8> @[Mux.scala 27:72] + _T_247 <= _T_246 @[Mux.scala 27:72] + node _T_248 = bits(ld_byte_rhit_lo_lo, 3, 3) @[el2_lsu_bus_intf.scala 307:79] + node _T_249 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 307:101] + node _T_250 = bits(ld_byte_rhit_hi_lo, 3, 3) @[el2_lsu_bus_intf.scala 307:136] + node _T_251 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 307:158] + node _T_252 = mux(_T_248, _T_249, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_253 = mux(_T_250, _T_251, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_254 = or(_T_252, _T_253) @[Mux.scala 27:72] + wire _T_255 : UInt<8> @[Mux.scala 27:72] + _T_255 <= _T_254 @[Mux.scala 27:72] + node _T_256 = cat(_T_255, _T_247) @[Cat.scala 29:58] + node _T_257 = cat(_T_256, _T_239) @[Cat.scala 29:58] + node _T_258 = cat(_T_257, _T_231) @[Cat.scala 29:58] + ld_fwddata_rpipe_lo <= _T_258 @[el2_lsu_bus_intf.scala 307:27] + node _T_259 = bits(ld_byte_rhit_lo_hi, 0, 0) @[el2_lsu_bus_intf.scala 308:79] + node _T_260 = bits(store_data_lo_r, 7, 0) @[el2_lsu_bus_intf.scala 308:101] + node _T_261 = bits(ld_byte_rhit_hi_hi, 0, 0) @[el2_lsu_bus_intf.scala 308:136] + node _T_262 = bits(store_data_hi_r, 7, 0) @[el2_lsu_bus_intf.scala 308:158] + node _T_263 = mux(_T_259, _T_260, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_264 = mux(_T_261, _T_262, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_265 = or(_T_263, _T_264) @[Mux.scala 27:72] + wire _T_266 : UInt<8> @[Mux.scala 27:72] + _T_266 <= _T_265 @[Mux.scala 27:72] + node _T_267 = bits(ld_byte_rhit_lo_hi, 1, 1) @[el2_lsu_bus_intf.scala 308:79] + node _T_268 = bits(store_data_lo_r, 15, 8) @[el2_lsu_bus_intf.scala 308:101] + node _T_269 = bits(ld_byte_rhit_hi_hi, 1, 1) @[el2_lsu_bus_intf.scala 308:136] + node _T_270 = bits(store_data_hi_r, 15, 8) @[el2_lsu_bus_intf.scala 308:158] + node _T_271 = mux(_T_267, _T_268, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_272 = mux(_T_269, _T_270, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_273 = or(_T_271, _T_272) @[Mux.scala 27:72] + wire _T_274 : UInt<8> @[Mux.scala 27:72] + _T_274 <= _T_273 @[Mux.scala 27:72] + node _T_275 = bits(ld_byte_rhit_lo_hi, 2, 2) @[el2_lsu_bus_intf.scala 308:79] + node _T_276 = bits(store_data_lo_r, 23, 16) @[el2_lsu_bus_intf.scala 308:101] + node _T_277 = bits(ld_byte_rhit_hi_hi, 2, 2) @[el2_lsu_bus_intf.scala 308:136] + node _T_278 = bits(store_data_hi_r, 23, 16) @[el2_lsu_bus_intf.scala 308:158] + node _T_279 = mux(_T_275, _T_276, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_280 = mux(_T_277, _T_278, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_281 = or(_T_279, _T_280) @[Mux.scala 27:72] + wire _T_282 : UInt<8> @[Mux.scala 27:72] + _T_282 <= _T_281 @[Mux.scala 27:72] + node _T_283 = bits(ld_byte_rhit_lo_hi, 3, 3) @[el2_lsu_bus_intf.scala 308:79] + node _T_284 = bits(store_data_lo_r, 31, 24) @[el2_lsu_bus_intf.scala 308:101] + node _T_285 = bits(ld_byte_rhit_hi_hi, 3, 3) @[el2_lsu_bus_intf.scala 308:136] + node _T_286 = bits(store_data_hi_r, 31, 24) @[el2_lsu_bus_intf.scala 308:158] + node _T_287 = mux(_T_283, _T_284, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_288 = mux(_T_285, _T_286, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_289 = or(_T_287, _T_288) @[Mux.scala 27:72] + wire _T_290 : UInt<8> @[Mux.scala 27:72] + _T_290 <= _T_289 @[Mux.scala 27:72] + node _T_291 = cat(_T_290, _T_282) @[Cat.scala 29:58] + node _T_292 = cat(_T_291, _T_274) @[Cat.scala 29:58] + node _T_293 = cat(_T_292, _T_266) @[Cat.scala 29:58] + ld_fwddata_rpipe_hi <= _T_293 @[el2_lsu_bus_intf.scala 308:27] + node _T_294 = bits(ld_byte_rhit_lo, 0, 0) @[el2_lsu_bus_intf.scala 309:70] + node _T_295 = bits(ld_fwddata_rpipe_lo, 7, 0) @[el2_lsu_bus_intf.scala 309:94] + node _T_296 = bits(ld_fwddata_buf_lo, 7, 0) @[el2_lsu_bus_intf.scala 309:128] + node _T_297 = mux(_T_294, _T_295, _T_296) @[el2_lsu_bus_intf.scala 309:54] + node _T_298 = bits(ld_byte_rhit_lo, 1, 1) @[el2_lsu_bus_intf.scala 309:70] + node _T_299 = bits(ld_fwddata_rpipe_lo, 15, 8) @[el2_lsu_bus_intf.scala 309:94] + node _T_300 = bits(ld_fwddata_buf_lo, 15, 8) @[el2_lsu_bus_intf.scala 309:128] + node _T_301 = mux(_T_298, _T_299, _T_300) @[el2_lsu_bus_intf.scala 309:54] + node _T_302 = bits(ld_byte_rhit_lo, 2, 2) @[el2_lsu_bus_intf.scala 309:70] + node _T_303 = bits(ld_fwddata_rpipe_lo, 23, 16) @[el2_lsu_bus_intf.scala 309:94] + node _T_304 = bits(ld_fwddata_buf_lo, 23, 16) @[el2_lsu_bus_intf.scala 309:128] + node _T_305 = mux(_T_302, _T_303, _T_304) @[el2_lsu_bus_intf.scala 309:54] + node _T_306 = bits(ld_byte_rhit_lo, 3, 3) @[el2_lsu_bus_intf.scala 309:70] + node _T_307 = bits(ld_fwddata_rpipe_lo, 31, 24) @[el2_lsu_bus_intf.scala 309:94] + node _T_308 = bits(ld_fwddata_buf_lo, 31, 24) @[el2_lsu_bus_intf.scala 309:128] + node _T_309 = mux(_T_306, _T_307, _T_308) @[el2_lsu_bus_intf.scala 309:54] + node _T_310 = cat(_T_309, _T_305) @[Cat.scala 29:58] + node _T_311 = cat(_T_310, _T_301) @[Cat.scala 29:58] + node _T_312 = cat(_T_311, _T_297) @[Cat.scala 29:58] + ld_fwddata_lo <= _T_312 @[el2_lsu_bus_intf.scala 309:27] + node _T_313 = bits(ld_byte_rhit_hi, 0, 0) @[el2_lsu_bus_intf.scala 310:70] + node _T_314 = bits(ld_fwddata_rpipe_hi, 7, 0) @[el2_lsu_bus_intf.scala 310:94] + node _T_315 = bits(ld_fwddata_buf_hi, 7, 0) @[el2_lsu_bus_intf.scala 310:128] + node _T_316 = mux(_T_313, _T_314, _T_315) @[el2_lsu_bus_intf.scala 310:54] + node _T_317 = bits(ld_byte_rhit_hi, 1, 1) @[el2_lsu_bus_intf.scala 310:70] + node _T_318 = bits(ld_fwddata_rpipe_hi, 15, 8) @[el2_lsu_bus_intf.scala 310:94] + node _T_319 = bits(ld_fwddata_buf_hi, 15, 8) @[el2_lsu_bus_intf.scala 310:128] + node _T_320 = mux(_T_317, _T_318, _T_319) @[el2_lsu_bus_intf.scala 310:54] + node _T_321 = bits(ld_byte_rhit_hi, 2, 2) @[el2_lsu_bus_intf.scala 310:70] + node _T_322 = bits(ld_fwddata_rpipe_hi, 23, 16) @[el2_lsu_bus_intf.scala 310:94] + node _T_323 = bits(ld_fwddata_buf_hi, 23, 16) @[el2_lsu_bus_intf.scala 310:128] + node _T_324 = mux(_T_321, _T_322, _T_323) @[el2_lsu_bus_intf.scala 310:54] + node _T_325 = bits(ld_byte_rhit_hi, 3, 3) @[el2_lsu_bus_intf.scala 310:70] + node _T_326 = bits(ld_fwddata_rpipe_hi, 31, 24) @[el2_lsu_bus_intf.scala 310:94] + node _T_327 = bits(ld_fwddata_buf_hi, 31, 24) @[el2_lsu_bus_intf.scala 310:128] + node _T_328 = mux(_T_325, _T_326, _T_327) @[el2_lsu_bus_intf.scala 310:54] + node _T_329 = cat(_T_328, _T_324) @[Cat.scala 29:58] + node _T_330 = cat(_T_329, _T_320) @[Cat.scala 29:58] + node _T_331 = cat(_T_330, _T_316) @[Cat.scala 29:58] + ld_fwddata_hi <= _T_331 @[el2_lsu_bus_intf.scala 310:27] + node _T_332 = bits(ld_byte_hit_lo, 0, 0) @[el2_lsu_bus_intf.scala 311:66] + node _T_333 = bits(ldst_byteen_lo_m, 0, 0) @[el2_lsu_bus_intf.scala 311:89] + node _T_334 = eq(_T_333, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_335 = or(_T_332, _T_334) @[el2_lsu_bus_intf.scala 311:70] + node _T_336 = bits(ld_byte_hit_lo, 1, 1) @[el2_lsu_bus_intf.scala 311:66] + node _T_337 = bits(ldst_byteen_lo_m, 1, 1) @[el2_lsu_bus_intf.scala 311:89] + node _T_338 = eq(_T_337, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_339 = or(_T_336, _T_338) @[el2_lsu_bus_intf.scala 311:70] + node _T_340 = bits(ld_byte_hit_lo, 2, 2) @[el2_lsu_bus_intf.scala 311:66] + node _T_341 = bits(ldst_byteen_lo_m, 2, 2) @[el2_lsu_bus_intf.scala 311:89] + node _T_342 = eq(_T_341, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_343 = or(_T_340, _T_342) @[el2_lsu_bus_intf.scala 311:70] + node _T_344 = bits(ld_byte_hit_lo, 3, 3) @[el2_lsu_bus_intf.scala 311:66] + node _T_345 = bits(ldst_byteen_lo_m, 3, 3) @[el2_lsu_bus_intf.scala 311:89] + node _T_346 = eq(_T_345, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 311:72] + node _T_347 = or(_T_344, _T_346) @[el2_lsu_bus_intf.scala 311:70] + node _T_348 = and(_T_335, _T_339) @[el2_lsu_bus_intf.scala 311:111] + node _T_349 = and(_T_348, _T_343) @[el2_lsu_bus_intf.scala 311:111] + node _T_350 = and(_T_349, _T_347) @[el2_lsu_bus_intf.scala 311:111] + ld_full_hit_lo_m <= _T_350 @[el2_lsu_bus_intf.scala 311:27] + node _T_351 = bits(ld_byte_hit_hi, 0, 0) @[el2_lsu_bus_intf.scala 312:66] + node _T_352 = bits(ldst_byteen_hi_m, 0, 0) @[el2_lsu_bus_intf.scala 312:89] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_354 = or(_T_351, _T_353) @[el2_lsu_bus_intf.scala 312:70] + node _T_355 = bits(ld_byte_hit_hi, 1, 1) @[el2_lsu_bus_intf.scala 312:66] + node _T_356 = bits(ldst_byteen_hi_m, 1, 1) @[el2_lsu_bus_intf.scala 312:89] + node _T_357 = eq(_T_356, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_358 = or(_T_355, _T_357) @[el2_lsu_bus_intf.scala 312:70] + node _T_359 = bits(ld_byte_hit_hi, 2, 2) @[el2_lsu_bus_intf.scala 312:66] + node _T_360 = bits(ldst_byteen_hi_m, 2, 2) @[el2_lsu_bus_intf.scala 312:89] + node _T_361 = eq(_T_360, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_362 = or(_T_359, _T_361) @[el2_lsu_bus_intf.scala 312:70] + node _T_363 = bits(ld_byte_hit_hi, 3, 3) @[el2_lsu_bus_intf.scala 312:66] + node _T_364 = bits(ldst_byteen_hi_m, 3, 3) @[el2_lsu_bus_intf.scala 312:89] + node _T_365 = eq(_T_364, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 312:72] + node _T_366 = or(_T_363, _T_365) @[el2_lsu_bus_intf.scala 312:70] + node _T_367 = and(_T_354, _T_358) @[el2_lsu_bus_intf.scala 312:111] + node _T_368 = and(_T_367, _T_362) @[el2_lsu_bus_intf.scala 312:111] + node _T_369 = and(_T_368, _T_366) @[el2_lsu_bus_intf.scala 312:111] + ld_full_hit_hi_m <= _T_369 @[el2_lsu_bus_intf.scala 312:27] + node _T_370 = and(ld_full_hit_lo_m, ld_full_hit_hi_m) @[el2_lsu_bus_intf.scala 313:47] + node _T_371 = and(_T_370, io.lsu_busreq_m) @[el2_lsu_bus_intf.scala 313:66] + node _T_372 = and(_T_371, io.lsu_pkt_m.load) @[el2_lsu_bus_intf.scala 313:84] + node _T_373 = eq(io.is_sideeffects_m, UInt<1>("h00")) @[el2_lsu_bus_intf.scala 313:106] + node _T_374 = and(_T_372, _T_373) @[el2_lsu_bus_intf.scala 313:104] + ld_full_hit_m <= _T_374 @[el2_lsu_bus_intf.scala 313:27] + node _T_375 = bits(ld_fwddata_hi, 31, 0) @[el2_lsu_bus_intf.scala 314:47] + node _T_376 = bits(ld_fwddata_lo, 31, 0) @[el2_lsu_bus_intf.scala 314:68] + node _T_377 = cat(_T_375, _T_376) @[Cat.scala 29:58] + node _T_378 = bits(io.lsu_addr_m, 1, 0) @[el2_lsu_bus_intf.scala 314:97] + node _T_379 = mul(UInt<4>("h08"), _T_378) @[el2_lsu_bus_intf.scala 314:83] + node _T_380 = dshr(_T_377, _T_379) @[el2_lsu_bus_intf.scala 314:76] + ld_fwddata_m <= _T_380 @[el2_lsu_bus_intf.scala 314:27] + node _T_381 = bits(ld_fwddata_m, 31, 0) @[el2_lsu_bus_intf.scala 315:42] + io.bus_read_data_m <= _T_381 @[el2_lsu_bus_intf.scala 315:27] + reg _T_382 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 318:32] + _T_382 <= io.lsu_bus_clk_en @[el2_lsu_bus_intf.scala 318:32] + lsu_bus_clk_en_q <= _T_382 @[el2_lsu_bus_intf.scala 318:22] + reg _T_383 : UInt<1>, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 321:27] + _T_383 <= ldst_dual_d @[el2_lsu_bus_intf.scala 321:27] + ldst_dual_m <= _T_383 @[el2_lsu_bus_intf.scala 321:17] + reg _T_384 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 324:33] + _T_384 <= ldst_dual_m @[el2_lsu_bus_intf.scala 324:33] + ldst_dual_r <= _T_384 @[el2_lsu_bus_intf.scala 324:23] + reg _T_385 : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lsu_bus_intf.scala 325:33] + _T_385 <= io.is_sideeffects_m @[el2_lsu_bus_intf.scala 325:33] + is_sideeffects_r <= _T_385 @[el2_lsu_bus_intf.scala 325:23] + reg _T_386 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<4>("h00"))) @[el2_lsu_bus_intf.scala 326:33] + _T_386 <= ldst_byteen_m @[el2_lsu_bus_intf.scala 326:33] + ldst_byteen_r <= _T_386 @[el2_lsu_bus_intf.scala 326:23] diff --git a/el2_lsu_bus_intf.v b/el2_lsu_bus_intf.v index 4f378b2e..5987290c 100644 --- a/el2_lsu_bus_intf.v +++ b/el2_lsu_bus_intf.v @@ -1,6 +1,28 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] +endmodule module el2_lsu_bus_buffer( input clock, input reset, + input io_scan_mode, input io_dec_tlu_external_ldfwd_disable, input io_dec_tlu_wb_coalescing_disable, input io_dec_tlu_sideeffect_posted_disable, @@ -21,6 +43,7 @@ module el2_lsu_bus_buffer( input io_lsu_pkt_r_store, input io_lsu_pkt_r_unsign, input [31:0] io_lsu_addr_m, + input [31:0] io_end_addr_m, input [31:0] io_lsu_addr_r, input [31:0] io_end_addr_r, input [31:0] io_store_data_r, @@ -36,7 +59,6 @@ module el2_lsu_bus_buffer( input io_ldst_dual_m, input io_ldst_dual_r, input [7:0] io_ldst_byteen_ext_m, - input io_lsu_axi_awready, input io_lsu_axi_wready, input io_lsu_axi_bvalid, input [1:0] io_lsu_axi_bresp, @@ -45,7 +67,6 @@ module el2_lsu_bus_buffer( input io_lsu_axi_rvalid, input [2:0] io_lsu_axi_rid, input [63:0] io_lsu_axi_rdata, - input [1:0] io_lsu_axi_rresp, input io_lsu_bus_clk_en, input io_lsu_bus_clk_en_q, output io_lsu_busreq_r, @@ -54,6 +75,8 @@ module el2_lsu_bus_buffer( output io_lsu_bus_buffer_empty_any, output [3:0] io_ld_byte_hit_buf_lo, output [3:0] io_ld_byte_hit_buf_hi, + output [31:0] io_ld_fwddata_buf_lo, + output [31:0] io_ld_fwddata_buf_hi, output io_lsu_imprecise_error_load_any, output io_lsu_imprecise_error_store_any, output [31:0] io_lsu_imprecise_error_addr_any, @@ -70,6 +93,7 @@ module el2_lsu_bus_buffer( output io_lsu_pmu_bus_error, output io_lsu_pmu_bus_busy, output io_lsu_axi_awvalid, + input io_lsu_axi_awready, output [2:0] io_lsu_axi_awid, output [31:0] io_lsu_axi_awaddr, output [3:0] io_lsu_axi_awregion, @@ -167,8 +191,8 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_76; reg [31:0] _RAND_77; reg [31:0] _RAND_78; - reg [63:0] _RAND_79; - reg [31:0] _RAND_80; + reg [31:0] _RAND_79; + reg [63:0] _RAND_80; reg [31:0] _RAND_81; reg [31:0] _RAND_82; reg [31:0] _RAND_83; @@ -178,7 +202,7 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_87; reg [31:0] _RAND_88; reg [31:0] _RAND_89; - reg [63:0] _RAND_90; + reg [31:0] _RAND_90; reg [31:0] _RAND_91; reg [31:0] _RAND_92; reg [31:0] _RAND_93; @@ -195,1934 +219,2517 @@ module el2_lsu_bus_buffer( reg [31:0] _RAND_104; reg [31:0] _RAND_105; reg [31:0] _RAND_106; - reg [31:0] _RAND_107; - reg [31:0] _RAND_108; - reg [31:0] _RAND_109; - reg [31:0] _RAND_110; - reg [31:0] _RAND_111; - reg [31:0] _RAND_112; - reg [31:0] _RAND_113; - reg [31:0] _RAND_114; - reg [31:0] _RAND_115; - reg [31:0] _RAND_116; - reg [31:0] _RAND_117; - reg [31:0] _RAND_118; - reg [31:0] _RAND_119; - reg [31:0] _RAND_120; - reg [31:0] _RAND_121; - reg [31:0] _RAND_122; - reg [31:0] _RAND_123; - reg [31:0] _RAND_124; - reg [31:0] _RAND_125; - reg [31:0] _RAND_126; - reg [31:0] _RAND_127; - reg [31:0] _RAND_128; - reg [31:0] _RAND_129; - reg [31:0] _RAND_130; `endif // RANDOMIZE_REG_INIT - wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 401:51] - reg [31:0] ibuf_addr; // @[Reg.scala 27:20] - wire _T_4 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 403:52] - reg ibuf_write; // @[Reg.scala 27:20] - wire _T_5 = _T_4 & ibuf_write; // @[el2_lsu_bus_buffer.scala 403:73] - reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 464:28] - wire _T_6 = _T_5 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 403:86] - wire ld_addr_ibuf_hit_lo = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 403:99] - reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] - wire _T_15 = ld_addr_ibuf_hit_lo & ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_17 = _T_15 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_19 = ld_addr_ibuf_hit_lo & ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_21 = _T_19 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_23 = ld_addr_ibuf_hit_lo & ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_25 = _T_23 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 406:89] - wire _T_27 = ld_addr_ibuf_hit_lo & ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 406:72] - wire _T_29 = _T_27 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 406:89] - wire [3:0] ld_byte_ibuf_hit_lo = {_T_29,_T_25,_T_21,_T_17}; // @[Cat.scala 29:58] - reg [31:0] buf_addr_0; // @[Reg.scala 27:20] - wire _T_54 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_0; // @[Reg.scala 27:20] - wire _T_55 = _T_54 & buf_write_0; // @[el2_lsu_bus_buffer.scala 409:100] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_5_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_6_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_7_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_8_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_9_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_10_io_scan_mode; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_l1clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_clk; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_en; // @[el2_lib.scala 508:23] + wire rvclkhdr_11_io_scan_mode; // @[el2_lib.scala 508:23] + wire [3:0] ldst_byteen_hi_m = io_ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_buffer.scala 127:46] + wire [3:0] ldst_byteen_lo_m = io_ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_buffer.scala 128:46] + reg [31:0] buf_addr_0; // @[el2_lib.scala 514:16] + wire _T_2 = io_lsu_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + reg _T_4360; // @[Reg.scala 27:20] + reg _T_4357; // @[Reg.scala 27:20] + reg _T_4354; // @[Reg.scala 27:20] + reg _T_4351; // @[Reg.scala 27:20] + wire [3:0] buf_write = {_T_4360,_T_4357,_T_4354,_T_4351}; // @[Cat.scala 29:58] + wire _T_4 = _T_2 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_0; // @[Reg.scala 27:20] - wire _T_56 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_57 = _T_55 & _T_56; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_58 = _T_57 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_1; // @[Reg.scala 27:20] - wire _T_61 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_1; // @[Reg.scala 27:20] - wire _T_62 = _T_61 & buf_write_1; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_5 = buf_state_0 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_6 = _T_4 & _T_5; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_0 = _T_6 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_1; // @[el2_lib.scala 514:16] + wire _T_9 = io_lsu_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_11 = _T_9 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_1; // @[Reg.scala 27:20] - wire _T_63 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_64 = _T_62 & _T_63; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_65 = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_2; // @[Reg.scala 27:20] - wire _T_68 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_2; // @[Reg.scala 27:20] - wire _T_69 = _T_68 & buf_write_2; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_12 = buf_state_1 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_13 = _T_11 & _T_12; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_1 = _T_13 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_2; // @[el2_lib.scala 514:16] + wire _T_16 = io_lsu_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_18 = _T_16 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_2; // @[Reg.scala 27:20] - wire _T_70 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_71 = _T_69 & _T_70; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_72 = _T_71 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - reg [31:0] buf_addr_3; // @[Reg.scala 27:20] - wire _T_75 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 409:77] - reg buf_write_3; // @[Reg.scala 27:20] - wire _T_76 = _T_75 & buf_write_3; // @[el2_lsu_bus_buffer.scala 409:100] + wire _T_19 = buf_state_2 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_20 = _T_18 & _T_19; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_2 = _T_20 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + reg [31:0] buf_addr_3; // @[el2_lib.scala 514:16] + wire _T_23 = io_lsu_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 130:74] + wire _T_25 = _T_23 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 130:98] reg [2:0] buf_state_3; // @[Reg.scala 27:20] - wire _T_77 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 409:131] - wire _T_78 = _T_76 & _T_77; // @[el2_lsu_bus_buffer.scala 409:115] - wire _T_79 = _T_78 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 409:143] - wire [3:0] ld_addr_hitvec_lo = {_T_79,_T_72,_T_65,_T_58}; // @[Cat.scala 29:58] + wire _T_26 = buf_state_3 != 3'h0; // @[el2_lsu_bus_buffer.scala 130:129] + wire _T_27 = _T_25 & _T_26; // @[el2_lsu_bus_buffer.scala 130:113] + wire ld_addr_hitvec_lo_3 = _T_27 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 130:141] + wire _T_30 = io_end_addr_m[31:2] == buf_addr_0[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_32 = _T_30 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_34 = _T_32 & _T_5; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_0 = _T_34 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_37 = io_end_addr_m[31:2] == buf_addr_1[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_39 = _T_37 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_41 = _T_39 & _T_12; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_1 = _T_41 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_44 = io_end_addr_m[31:2] == buf_addr_2[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_46 = _T_44 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_48 = _T_46 & _T_19; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_2 = _T_48 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] + wire _T_51 = io_end_addr_m[31:2] == buf_addr_3[31:2]; // @[el2_lsu_bus_buffer.scala 131:74] + wire _T_53 = _T_51 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 131:98] + wire _T_55 = _T_53 & _T_26; // @[el2_lsu_bus_buffer.scala 131:113] + wire ld_addr_hitvec_hi_3 = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 131:141] reg [3:0] buf_byteen_3; // @[Reg.scala 27:20] - wire _T_161 = ld_addr_hitvec_lo[3] & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_163 = _T_161 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_99 = ld_addr_hitvec_lo_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_101 = _T_99 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_2; // @[Reg.scala 27:20] - wire _T_156 = ld_addr_hitvec_lo[2] & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_158 = _T_156 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_95 = ld_addr_hitvec_lo_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_97 = _T_95 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_1; // @[Reg.scala 27:20] - wire _T_151 = ld_addr_hitvec_lo[1] & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_153 = _T_151 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] + wire _T_91 = ld_addr_hitvec_lo_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_93 = _T_91 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] reg [3:0] buf_byteen_0; // @[Reg.scala 27:20] - wire _T_146 = ld_addr_hitvec_lo[0] & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_148 = _T_146 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_0 = {_T_163,_T_158,_T_153,_T_148}; // @[Cat.scala 29:58] - reg buf_ageQ_3_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_3015 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3756 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3779 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3783 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] - reg [2:0] obuf_tag0; // @[Reg.scala 27:20] - wire _T_3790 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 628:52] + wire _T_87 = ld_addr_hitvec_lo_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_89 = _T_87 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_0 = {_T_101,_T_97,_T_93,_T_89}; // @[Cat.scala 29:58] + reg [3:0] buf_ageQ_3; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2621 = buf_state_3 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_4107 = 3'h0 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4130 = 3'h1 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4134 = 3'h2 == buf_state_3; // @[Conditional.scala 37:30] + reg [1:0] _T_1848; // @[Reg.scala 27:20] + wire [2:0] obuf_tag0 = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 405:13] + wire _T_4141 = obuf_tag0 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:48] reg obuf_merge; // @[Reg.scala 27:20] - reg [2:0] obuf_tag1; // @[Reg.scala 27:20] - wire _T_3791 = obuf_tag1 == 3'h3; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3792 = obuf_merge & _T_3791; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3793 = _T_3790 | _T_3792; // @[el2_lsu_bus_buffer.scala 628:85] - reg obuf_valid; // @[el2_lsu_bus_buffer.scala 531:28] - wire _T_3794 = _T_3793 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 528:35] - wire _T_3795 = _T_3794 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_398 = _T_3783 & _T_3795; // @[Conditional.scala 39:67] - wire _GEN_411 = _T_3779 ? 1'h0 : _GEN_398; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_411; // @[Conditional.scala 40:58] - wire _T_3016 = _T_3015 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_3017 = ~_T_3016; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_3 = buf_ageQ_3_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_3_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2920 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3548 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3571 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3575 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3582 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3583 = obuf_tag1 == 3'h2; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3584 = obuf_merge & _T_3583; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3585 = _T_3582 | _T_3584; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3586 = _T_3585 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3587 = _T_3586 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_308 = _T_3575 & _T_3587; // @[Conditional.scala 39:67] - wire _GEN_321 = _T_3571 ? 1'h0 : _GEN_308; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_321; // @[Conditional.scala 40:58] - wire _T_2921 = _T_2920 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2922 = ~_T_2921; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_2 = buf_ageQ_3_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2925 = ~buf_age_3_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_2 = _T_2925 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_3_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2825 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3340 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3363 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3367 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3374 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3375 = obuf_tag1 == 3'h1; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3376 = obuf_merge & _T_3375; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3377 = _T_3374 | _T_3376; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3378 = _T_3377 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3379 = _T_3378 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_218 = _T_3367 & _T_3379; // @[Conditional.scala 39:67] - wire _GEN_231 = _T_3363 ? 1'h0 : _GEN_218; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_231; // @[Conditional.scala 40:58] - wire _T_2826 = _T_2825 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2827 = ~_T_2826; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_1 = buf_ageQ_3_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2830 = ~buf_age_3_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_1 = _T_2830 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_3_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire _T_2730 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 567:65] - wire _T_3132 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3155 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3159 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] - wire _T_3166 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 628:52] - wire _T_3167 = obuf_tag1 == 3'h0; // @[el2_lsu_bus_buffer.scala 628:112] - wire _T_3168 = obuf_merge & _T_3167; // @[el2_lsu_bus_buffer.scala 628:99] - wire _T_3169 = _T_3166 | _T_3168; // @[el2_lsu_bus_buffer.scala 628:85] - wire _T_3170 = _T_3169 & obuf_valid; // @[el2_lsu_bus_buffer.scala 628:147] - wire _T_3171 = _T_3170 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 628:160] - wire _GEN_128 = _T_3159 & _T_3171; // @[Conditional.scala 39:67] - wire _GEN_141 = _T_3155 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] - wire buf_cmd_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] - wire _T_2731 = _T_2730 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 567:76] - wire _T_2732 = ~_T_2731; // @[el2_lsu_bus_buffer.scala 567:49] - wire buf_age_3_0 = buf_ageQ_3_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2735 = ~buf_age_3_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_3_0 = _T_2735 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_364 = {1'h0,buf_age_younger_3_2,buf_age_younger_3_1,buf_age_younger_3_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_365 = ld_byte_hitvec_lo_0 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_366 = |_T_365; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_367 = ~_T_366; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_368 = ld_byte_hitvec_lo_0[3] & _T_367; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_370 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_371 = _T_368 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_2_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_3 = buf_ageQ_2_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2640 = ~buf_age_2_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_3 = _T_2640 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_2_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_2 = buf_ageQ_2_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_2_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_1 = buf_ageQ_2_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2450 = ~buf_age_2_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_1 = _T_2450 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_2_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_2_0 = buf_ageQ_2_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2355 = ~buf_age_2_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_2_0 = _T_2355 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_353 = {buf_age_younger_2_3,1'h0,buf_age_younger_2_1,buf_age_younger_2_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_354 = ld_byte_hitvec_lo_0 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_355 = |_T_354; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_356 = ~_T_355; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_357 = ld_byte_hitvec_lo_0[2] & _T_356; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_360 = _T_357 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_1_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_3 = buf_ageQ_1_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2260 = ~buf_age_1_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_3 = _T_2260 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_1_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_2 = buf_ageQ_1_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_2165 = ~buf_age_1_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_2 = _T_2165 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_1_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_1 = buf_ageQ_1_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - reg buf_ageQ_1_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_1_0 = buf_ageQ_1_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1975 = ~buf_age_1_0; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_1_0 = _T_1975 & _T_56; // @[el2_lsu_bus_buffer.scala 568:108] - wire [3:0] _T_342 = {buf_age_younger_1_3,buf_age_younger_1_2,1'h0,buf_age_younger_1_0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_343 = ld_byte_hitvec_lo_0 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_344 = |_T_343; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_345 = ~_T_344; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_346 = ld_byte_hitvec_lo_0[1] & _T_345; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_349 = _T_346 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - reg buf_ageQ_0_3; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_3 = buf_ageQ_0_3 & _T_3017; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1880 = ~buf_age_0_3; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_3 = _T_1880 & _T_77; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_2; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_2 = buf_ageQ_0_2 & _T_2922; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1785 = ~buf_age_0_2; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_2 = _T_1785 & _T_70; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_1; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_1 = buf_ageQ_0_1 & _T_2827; // @[el2_lsu_bus_buffer.scala 567:47] - wire _T_1690 = ~buf_age_0_1; // @[el2_lsu_bus_buffer.scala 568:93] - wire buf_age_younger_0_1 = _T_1690 & _T_63; // @[el2_lsu_bus_buffer.scala 568:108] - reg buf_ageQ_0_0; // @[el2_lsu_bus_buffer.scala 690:41] - wire buf_age_0_0 = buf_ageQ_0_0 & _T_2732; // @[el2_lsu_bus_buffer.scala 567:47] - wire [3:0] _T_331 = {buf_age_younger_0_3,buf_age_younger_0_2,buf_age_younger_0_1,1'h0}; // @[el2_lsu_bus_buffer.scala 418:147] - wire [3:0] _T_332 = ld_byte_hitvec_lo_0 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_333 = |_T_332; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_334 = ~_T_333; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_335 = ld_byte_hitvec_lo_0[0] & _T_334; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_338 = _T_335 & _T_370; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_371,_T_360,_T_349,_T_338}; // @[Cat.scala 29:58] - wire _T_115 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_116 = ld_byte_ibuf_hit_lo[0] | _T_115; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_184 = ld_addr_hitvec_lo[3] & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_186 = _T_184 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_179 = ld_addr_hitvec_lo[2] & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_181 = _T_179 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_174 = ld_addr_hitvec_lo[1] & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_176 = _T_174 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_169 = ld_addr_hitvec_lo[0] & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_171 = _T_169 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_1 = {_T_186,_T_181,_T_176,_T_171}; // @[Cat.scala 29:58] - wire [3:0] _T_412 = ld_byte_hitvec_lo_1 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_413 = |_T_412; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_414 = ~_T_413; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_415 = ld_byte_hitvec_lo_1[3] & _T_414; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_417 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_418 = _T_415 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_401 = ld_byte_hitvec_lo_1 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_402 = |_T_401; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_403 = ~_T_402; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_404 = ld_byte_hitvec_lo_1[2] & _T_403; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_407 = _T_404 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_390 = ld_byte_hitvec_lo_1 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_391 = |_T_390; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_392 = ~_T_391; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_393 = ld_byte_hitvec_lo_1[1] & _T_392; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_396 = _T_393 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_379 = ld_byte_hitvec_lo_1 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_382 = ld_byte_hitvec_lo_1[0] & _T_381; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_385 = _T_382 & _T_417; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_418,_T_407,_T_396,_T_385}; // @[Cat.scala 29:58] - wire _T_118 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_119 = ld_byte_ibuf_hit_lo[1] | _T_118; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_207 = ld_addr_hitvec_lo[3] & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_209 = _T_207 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_202 = ld_addr_hitvec_lo[2] & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_204 = _T_202 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_197 = ld_addr_hitvec_lo[1] & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_199 = _T_197 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_192 = ld_addr_hitvec_lo[0] & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_194 = _T_192 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_2 = {_T_209,_T_204,_T_199,_T_194}; // @[Cat.scala 29:58] - wire [3:0] _T_459 = ld_byte_hitvec_lo_2 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_460 = |_T_459; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_461 = ~_T_460; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_462 = ld_byte_hitvec_lo_2[3] & _T_461; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_464 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_465 = _T_462 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_448 = ld_byte_hitvec_lo_2 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_449 = |_T_448; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_450 = ~_T_449; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_451 = ld_byte_hitvec_lo_2[2] & _T_450; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_454 = _T_451 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_437 = ld_byte_hitvec_lo_2 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_438 = |_T_437; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_439 = ~_T_438; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_440 = ld_byte_hitvec_lo_2[1] & _T_439; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_443 = _T_440 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_426 = ld_byte_hitvec_lo_2 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_427 = |_T_426; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_428 = ~_T_427; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_429 = ld_byte_hitvec_lo_2[0] & _T_428; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_432 = _T_429 & _T_464; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_465,_T_454,_T_443,_T_432}; // @[Cat.scala 29:58] - wire _T_121 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_122 = ld_byte_ibuf_hit_lo[2] | _T_121; // @[el2_lsu_bus_buffer.scala 412:75] - wire _T_230 = ld_addr_hitvec_lo[3] & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_232 = _T_230 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_225 = ld_addr_hitvec_lo[2] & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_227 = _T_225 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_220 = ld_addr_hitvec_lo[1] & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_222 = _T_220 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire _T_215 = ld_addr_hitvec_lo[0] & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 415:97] - wire _T_217 = _T_215 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 415:116] - wire [3:0] ld_byte_hitvec_lo_3 = {_T_232,_T_227,_T_222,_T_217}; // @[Cat.scala 29:58] - wire [3:0] _T_506 = ld_byte_hitvec_lo_3 & _T_364; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_507 = |_T_506; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_508 = ~_T_507; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_509 = ld_byte_hitvec_lo_3[3] & _T_508; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_511 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 418:162] - wire _T_512 = _T_509 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_495 = ld_byte_hitvec_lo_3 & _T_353; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_496 = |_T_495; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_497 = ~_T_496; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_498 = ld_byte_hitvec_lo_3[2] & _T_497; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_501 = _T_498 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_484 = ld_byte_hitvec_lo_3 & _T_342; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_487 = ld_byte_hitvec_lo_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_490 = _T_487 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] _T_473 = ld_byte_hitvec_lo_3 & _T_331; // @[el2_lsu_bus_buffer.scala 418:126] - wire _T_474 = |_T_473; // @[el2_lsu_bus_buffer.scala 418:155] - wire _T_475 = ~_T_474; // @[el2_lsu_bus_buffer.scala 418:102] - wire _T_476 = ld_byte_hitvec_lo_3[0] & _T_475; // @[el2_lsu_bus_buffer.scala 418:100] - wire _T_479 = _T_476 & _T_511; // @[el2_lsu_bus_buffer.scala 418:160] - wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_512,_T_501,_T_490,_T_479}; // @[Cat.scala 29:58] - wire _T_124 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 412:100] - wire _T_125 = ld_byte_ibuf_hit_lo[3] | _T_124; // @[el2_lsu_bus_buffer.scala 412:75] - wire [2:0] _T_127 = {_T_125,_T_122,_T_119}; // @[Cat.scala 29:58] - reg [31:0] ibuf_data; // @[Reg.scala 27:20] - reg [31:0] buf_data_0; // @[Reg.scala 27:20] - reg [31:0] buf_data_1; // @[Reg.scala 27:20] - reg [31:0] buf_data_2; // @[Reg.scala 27:20] - reg [31:0] buf_data_3; // @[Reg.scala 27:20] - wire [3:0] _T_866 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_867 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_868 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_869 = _T_866 | _T_867; // @[Mux.scala 27:72] - wire [3:0] ldst_byteen_r = _T_869 | _T_868; // @[Mux.scala 27:72] - wire [7:0] _T_874 = {4'h0,ldst_byteen_r}; // @[Cat.scala 29:58] - wire [10:0] _GEN_471 = {{3'd0}, _T_874}; // @[el2_lsu_bus_buffer.scala 432:71] - wire [10:0] ldst_byteen_extended_r = _GEN_471 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_buffer.scala 432:71] - wire [63:0] _T_878 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58] - wire [3:0] _GEN_472 = {{2'd0}, io_lsu_addr_r[1:0]}; // @[el2_lsu_bus_buffer.scala 433:82] - wire [5:0] _T_880 = 4'h8 * _GEN_472; // @[el2_lsu_bus_buffer.scala 433:82] - wire [126:0] _GEN_473 = {{63'd0}, _T_878}; // @[el2_lsu_bus_buffer.scala 433:75] - wire [126:0] store_data_extended_r = _GEN_473 << _T_880; // @[el2_lsu_bus_buffer.scala 433:75] - wire [3:0] ldst_byteen_hi_r = ldst_byteen_extended_r[7:4]; // @[el2_lsu_bus_buffer.scala 434:58] - wire [3:0] ldst_byteen_lo_r = ldst_byteen_extended_r[3:0]; // @[el2_lsu_bus_buffer.scala 435:58] - wire [31:0] store_data_hi_r = store_data_extended_r[63:32]; // @[el2_lsu_bus_buffer.scala 436:57] - wire [31:0] store_data_lo_r = store_data_extended_r[31:0]; // @[el2_lsu_bus_buffer.scala 437:57] - wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 438:53] - wire _T_891 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 441:96] - wire _T_894 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 442:98] - wire _T_896 = io_lsu_pkt_r_half & _T_891; // @[Mux.scala 27:72] - wire _T_897 = io_lsu_pkt_r_word & _T_894; // @[Mux.scala 27:72] - wire _T_898 = io_lsu_pkt_r_by | _T_896; // @[Mux.scala 27:72] - wire is_aligned_r = _T_898 | _T_897; // @[Mux.scala 27:72] - wire _T_901 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 445:71] - wire _T_902 = io_lsu_busreq_r & _T_901; // @[el2_lsu_bus_buffer.scala 445:50] - wire _T_903 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 445:95] - wire ibuf_byp = _T_902 & _T_903; // @[el2_lsu_bus_buffer.scala 445:93] - wire _T_906 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 446:50] - wire _T_907 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 446:70] - wire ibuf_wr_en = _T_906 & _T_907; // @[el2_lsu_bus_buffer.scala 446:68] - wire _T_910 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 447:52] - reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 465:35] - wire _T_923 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 449:74] - wire _T_924 = ibuf_wr_en | _T_923; // @[el2_lsu_bus_buffer.scala 449:60] - wire _T_1061 = _T_906 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 460:67] - wire _T_1062 = _T_1061 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 460:88] - wire _T_1063 = _T_1062 & ibuf_write; // @[el2_lsu_bus_buffer.scala 460:101] - wire _T_1066 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 460:135] - wire _T_1067 = _T_1063 & _T_1066; // @[el2_lsu_bus_buffer.scala 460:114] - wire _T_1068 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 460:156] - wire _T_1069 = _T_1067 & _T_1068; // @[el2_lsu_bus_buffer.scala 460:154] - wire _T_1070 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 460:179] - wire ibuf_merge_en = _T_1069 & _T_1070; // @[el2_lsu_bus_buffer.scala 460:177] - wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 461:33] - wire _T_925 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 449:131] - wire _T_926 = ~_T_925; // @[el2_lsu_bus_buffer.scala 449:115] - wire _T_927 = _T_924 & _T_926; // @[el2_lsu_bus_buffer.scala 449:113] - wire _T_928 = _T_927 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 449:149] - wire _T_914 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 448:52] - wire _T_915 = io_lsu_busreq_m & _T_914; // @[el2_lsu_bus_buffer.scala 448:50] - wire _T_916 = _T_915 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 448:69] - wire _T_919 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 448:122] - wire _T_920 = io_lsu_pkt_m_load | _T_919; // @[el2_lsu_bus_buffer.scala 448:103] - wire ibuf_force_drain = _T_916 & _T_920; // @[el2_lsu_bus_buffer.scala 448:82] - wire _T_929 = _T_928 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 450:45] + reg [1:0] obuf_tag1; // @[Reg.scala 27:20] + wire [2:0] _GEN_358 = {{1'd0}, obuf_tag1}; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4142 = _GEN_358 == 3'h3; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_4143 = obuf_merge & _T_4142; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_4144 = _T_4141 | _T_4143; // @[el2_lsu_bus_buffer.scala 508:77] + reg obuf_valid; // @[el2_lsu_bus_buffer.scala 399:54] + wire _T_4145 = _T_4144 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + reg obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 398:55] + wire _T_4146 = _T_4145 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_280 = _T_4134 & _T_4146; // @[Conditional.scala 39:67] + wire _GEN_293 = _T_4130 ? 1'h0 : _GEN_280; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_293; // @[Conditional.scala 40:58] + wire _T_2622 = _T_2621 & buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2623 = ~_T_2622; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2624 = buf_ageQ_3[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2616 = buf_state_2 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3914 = 3'h0 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3937 = 3'h1 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3941 = 3'h2 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_3948 = obuf_tag0 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3949 = _GEN_358 == 3'h2; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3950 = obuf_merge & _T_3949; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3951 = _T_3948 | _T_3950; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3952 = _T_3951 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3953 = _T_3952 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_204 = _T_3941 & _T_3953; // @[Conditional.scala 39:67] + wire _GEN_217 = _T_3937 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_217; // @[Conditional.scala 40:58] + wire _T_2617 = _T_2616 & buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2618 = ~_T_2617; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2619 = buf_ageQ_3[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2611 = buf_state_1 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3721 = 3'h0 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3744 = 3'h1 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3748 = 3'h2 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3755 = obuf_tag0 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3756 = _GEN_358 == 3'h1; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3757 = obuf_merge & _T_3756; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3758 = _T_3755 | _T_3757; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3759 = _T_3758 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3760 = _T_3759 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_128 = _T_3748 & _T_3760; // @[Conditional.scala 39:67] + wire _GEN_141 = _T_3744 ? 1'h0 : _GEN_128; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_141; // @[Conditional.scala 40:58] + wire _T_2612 = _T_2611 & buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2613 = ~_T_2612; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2614 = buf_ageQ_3[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2606 = buf_state_0 == 3'h2; // @[el2_lsu_bus_buffer.scala 465:93] + wire _T_3528 = 3'h0 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3551 = 3'h1 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3555 = 3'h2 == buf_state_0; // @[Conditional.scala 37:30] + wire _T_3562 = obuf_tag0 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:48] + wire _T_3563 = _GEN_358 == 3'h0; // @[el2_lsu_bus_buffer.scala 508:104] + wire _T_3564 = obuf_merge & _T_3563; // @[el2_lsu_bus_buffer.scala 508:91] + wire _T_3565 = _T_3562 | _T_3564; // @[el2_lsu_bus_buffer.scala 508:77] + wire _T_3566 = _T_3565 & obuf_valid; // @[el2_lsu_bus_buffer.scala 508:135] + wire _T_3567 = _T_3566 & obuf_wr_enQ; // @[el2_lsu_bus_buffer.scala 508:148] + wire _GEN_52 = _T_3555 & _T_3567; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_3551 ? 1'h0 : _GEN_52; // @[Conditional.scala 39:67] + wire buf_cmd_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_65; // @[Conditional.scala 40:58] + wire _T_2607 = _T_2606 & buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 465:103] + wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 465:78] + wire _T_2609 = buf_ageQ_3[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_3 = {_T_2624,_T_2619,_T_2614,_T_2609}; // @[Cat.scala 29:58] + wire _T_2723 = ~buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2725 = _T_2723 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2717 = ~buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2719 = _T_2717 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2711 = ~buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2713 = _T_2711 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_3 = {1'h0,_T_2725,_T_2719,_T_2713}; // @[Cat.scala 29:58] + wire [3:0] _T_255 = ld_byte_hitvec_lo_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_256 = |_T_255; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_257 = ~_T_256; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_258 = ld_byte_hitvec_lo_0[3] & _T_257; // @[el2_lsu_bus_buffer.scala 199:97] + reg [31:0] ibuf_addr; // @[el2_lib.scala 514:16] + wire _T_512 = io_lsu_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 205:51] + reg ibuf_write; // @[Reg.scala 27:20] + wire _T_513 = _T_512 & ibuf_write; // @[el2_lsu_bus_buffer.scala 205:73] + reg ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:54] + wire _T_514 = _T_513 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 205:86] + wire ld_addr_ibuf_hit_lo = _T_514 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 205:99] + wire [3:0] _T_521 = ld_addr_ibuf_hit_lo ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + reg [3:0] ibuf_byteen; // @[Reg.scala 27:20] + wire [3:0] _T_522 = _T_521 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 210:55] + wire [3:0] ld_byte_ibuf_hit_lo = _T_522 & ldst_byteen_lo_m; // @[el2_lsu_bus_buffer.scala 210:69] + wire _T_260 = ~ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_261 = _T_258 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_2; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2601 = buf_ageQ_2[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2596 = buf_ageQ_2[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2591 = buf_ageQ_2[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2586 = buf_ageQ_2[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_2 = {_T_2601,_T_2596,_T_2591,_T_2586}; // @[Cat.scala 29:58] + wire _T_2702 = ~buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2704 = _T_2702 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2690 = ~buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2692 = _T_2690 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2684 = ~buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2686 = _T_2684 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_2 = {_T_2704,1'h0,_T_2692,_T_2686}; // @[Cat.scala 29:58] + wire [3:0] _T_247 = ld_byte_hitvec_lo_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_248 = |_T_247; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_249 = ~_T_248; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_250 = ld_byte_hitvec_lo_0[2] & _T_249; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_253 = _T_250 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_1; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2578 = buf_ageQ_1[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2573 = buf_ageQ_1[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2568 = buf_ageQ_1[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2563 = buf_ageQ_1[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_1 = {_T_2578,_T_2573,_T_2568,_T_2563}; // @[Cat.scala 29:58] + wire _T_2675 = ~buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2677 = _T_2675 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2669 = ~buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2671 = _T_2669 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2657 = ~buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2659 = _T_2657 & _T_5; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_1 = {_T_2677,_T_2671,1'h0,_T_2659}; // @[Cat.scala 29:58] + wire [3:0] _T_239 = ld_byte_hitvec_lo_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_240 = |_T_239; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_241 = ~_T_240; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_242 = ld_byte_hitvec_lo_0[1] & _T_241; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_245 = _T_242 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + reg [3:0] buf_ageQ_0; // @[el2_lsu_bus_buffer.scala 553:60] + wire _T_2555 = buf_ageQ_0[3] & _T_2623; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2550 = buf_ageQ_0[2] & _T_2618; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2545 = buf_ageQ_0[1] & _T_2613; // @[el2_lsu_bus_buffer.scala 465:76] + wire _T_2540 = buf_ageQ_0[0] & _T_2608; // @[el2_lsu_bus_buffer.scala 465:76] + wire [3:0] buf_age_0 = {_T_2555,_T_2550,_T_2545,_T_2540}; // @[Cat.scala 29:58] + wire _T_2648 = ~buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2650 = _T_2648 & _T_26; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2642 = ~buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2644 = _T_2642 & _T_19; // @[el2_lsu_bus_buffer.scala 466:104] + wire _T_2636 = ~buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 466:89] + wire _T_2638 = _T_2636 & _T_12; // @[el2_lsu_bus_buffer.scala 466:104] + wire [3:0] buf_age_younger_0 = {_T_2650,_T_2644,_T_2638,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_231 = ld_byte_hitvec_lo_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_232 = |_T_231; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_233 = ~_T_232; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_234 = ld_byte_hitvec_lo_0[0] & _T_233; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_237 = _T_234 & _T_260; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_0 = {_T_261,_T_253,_T_245,_T_237}; // @[Cat.scala 29:58] + wire _T_56 = |ld_byte_hitvecfn_lo_0; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_58 = _T_56 | ld_byte_ibuf_hit_lo[0]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_117 = ld_addr_hitvec_lo_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_119 = _T_117 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_113 = ld_addr_hitvec_lo_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_115 = _T_113 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_109 = ld_addr_hitvec_lo_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_111 = _T_109 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_105 = ld_addr_hitvec_lo_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_107 = _T_105 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_1 = {_T_119,_T_115,_T_111,_T_107}; // @[Cat.scala 29:58] + wire [3:0] _T_290 = ld_byte_hitvec_lo_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_291 = |_T_290; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_292 = ~_T_291; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_293 = ld_byte_hitvec_lo_1[3] & _T_292; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_295 = ~ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_296 = _T_293 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_282 = ld_byte_hitvec_lo_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_283 = |_T_282; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_284 = ~_T_283; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_285 = ld_byte_hitvec_lo_1[2] & _T_284; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_288 = _T_285 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_274 = ld_byte_hitvec_lo_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_275 = |_T_274; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_276 = ~_T_275; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_277 = ld_byte_hitvec_lo_1[1] & _T_276; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_280 = _T_277 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_266 = ld_byte_hitvec_lo_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_267 = |_T_266; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_268 = ~_T_267; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_269 = ld_byte_hitvec_lo_1[0] & _T_268; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_272 = _T_269 & _T_295; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_1 = {_T_296,_T_288,_T_280,_T_272}; // @[Cat.scala 29:58] + wire _T_59 = |ld_byte_hitvecfn_lo_1; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_61 = _T_59 | ld_byte_ibuf_hit_lo[1]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_135 = ld_addr_hitvec_lo_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_137 = _T_135 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_131 = ld_addr_hitvec_lo_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_133 = _T_131 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_127 = ld_addr_hitvec_lo_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_129 = _T_127 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_123 = ld_addr_hitvec_lo_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_125 = _T_123 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_2 = {_T_137,_T_133,_T_129,_T_125}; // @[Cat.scala 29:58] + wire [3:0] _T_325 = ld_byte_hitvec_lo_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_326 = |_T_325; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_327 = ~_T_326; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_328 = ld_byte_hitvec_lo_2[3] & _T_327; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_330 = ~ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_331 = _T_328 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_317 = ld_byte_hitvec_lo_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_318 = |_T_317; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_319 = ~_T_318; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_320 = ld_byte_hitvec_lo_2[2] & _T_319; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_323 = _T_320 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_309 = ld_byte_hitvec_lo_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_310 = |_T_309; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_311 = ~_T_310; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_312 = ld_byte_hitvec_lo_2[1] & _T_311; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_315 = _T_312 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_301 = ld_byte_hitvec_lo_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_302 = |_T_301; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_303 = ~_T_302; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_304 = ld_byte_hitvec_lo_2[0] & _T_303; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_307 = _T_304 & _T_330; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_2 = {_T_331,_T_323,_T_315,_T_307}; // @[Cat.scala 29:58] + wire _T_62 = |ld_byte_hitvecfn_lo_2; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_64 = _T_62 | ld_byte_ibuf_hit_lo[2]; // @[el2_lsu_bus_buffer.scala 191:77] + wire _T_153 = ld_addr_hitvec_lo_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_155 = _T_153 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_149 = ld_addr_hitvec_lo_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_151 = _T_149 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_145 = ld_addr_hitvec_lo_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_147 = _T_145 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire _T_141 = ld_addr_hitvec_lo_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 194:95] + wire _T_143 = _T_141 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_buffer.scala 194:114] + wire [3:0] ld_byte_hitvec_lo_3 = {_T_155,_T_151,_T_147,_T_143}; // @[Cat.scala 29:58] + wire [3:0] _T_360 = ld_byte_hitvec_lo_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_361 = |_T_360; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_362 = ~_T_361; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_363 = ld_byte_hitvec_lo_3[3] & _T_362; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_365 = ~ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 199:150] + wire _T_366 = _T_363 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_352 = ld_byte_hitvec_lo_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_353 = |_T_352; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_354 = ~_T_353; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_355 = ld_byte_hitvec_lo_3[2] & _T_354; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_358 = _T_355 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_344 = ld_byte_hitvec_lo_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_345 = |_T_344; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_346 = ~_T_345; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_347 = ld_byte_hitvec_lo_3[1] & _T_346; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_350 = _T_347 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] _T_336 = ld_byte_hitvec_lo_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 199:122] + wire _T_337 = |_T_336; // @[el2_lsu_bus_buffer.scala 199:144] + wire _T_338 = ~_T_337; // @[el2_lsu_bus_buffer.scala 199:99] + wire _T_339 = ld_byte_hitvec_lo_3[0] & _T_338; // @[el2_lsu_bus_buffer.scala 199:97] + wire _T_342 = _T_339 & _T_365; // @[el2_lsu_bus_buffer.scala 199:148] + wire [3:0] ld_byte_hitvecfn_lo_3 = {_T_366,_T_358,_T_350,_T_342}; // @[Cat.scala 29:58] + wire _T_65 = |ld_byte_hitvecfn_lo_3; // @[el2_lsu_bus_buffer.scala 191:73] + wire _T_67 = _T_65 | ld_byte_ibuf_hit_lo[3]; // @[el2_lsu_bus_buffer.scala 191:77] + wire [2:0] _T_69 = {_T_67,_T_64,_T_61}; // @[Cat.scala 29:58] + wire _T_171 = ld_addr_hitvec_hi_3 & buf_byteen_3[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_173 = _T_171 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_167 = ld_addr_hitvec_hi_2 & buf_byteen_2[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_169 = _T_167 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_163 = ld_addr_hitvec_hi_1 & buf_byteen_1[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_165 = _T_163 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_159 = ld_addr_hitvec_hi_0 & buf_byteen_0[0]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_161 = _T_159 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_0 = {_T_173,_T_169,_T_165,_T_161}; // @[Cat.scala 29:58] + wire [3:0] _T_395 = ld_byte_hitvec_hi_0 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_396 = |_T_395; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_397 = ~_T_396; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_398 = ld_byte_hitvec_hi_0[3] & _T_397; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_517 = io_end_addr_m[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 206:51] + wire _T_518 = _T_517 & ibuf_write; // @[el2_lsu_bus_buffer.scala 206:73] + wire _T_519 = _T_518 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 206:86] + wire ld_addr_ibuf_hit_hi = _T_519 & io_lsu_busreq_m; // @[el2_lsu_bus_buffer.scala 206:99] + wire [3:0] _T_525 = ld_addr_ibuf_hit_hi ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] _T_526 = _T_525 & ibuf_byteen; // @[el2_lsu_bus_buffer.scala 211:55] + wire [3:0] ld_byte_ibuf_hit_hi = _T_526 & ldst_byteen_hi_m; // @[el2_lsu_bus_buffer.scala 211:69] + wire _T_400 = ~ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_401 = _T_398 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_387 = ld_byte_hitvec_hi_0 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_388 = |_T_387; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_389 = ~_T_388; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_390 = ld_byte_hitvec_hi_0[2] & _T_389; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_393 = _T_390 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_379 = ld_byte_hitvec_hi_0 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_380 = |_T_379; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_381 = ~_T_380; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_382 = ld_byte_hitvec_hi_0[1] & _T_381; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_385 = _T_382 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_371 = ld_byte_hitvec_hi_0 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_372 = |_T_371; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_373 = ~_T_372; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_374 = ld_byte_hitvec_hi_0[0] & _T_373; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_377 = _T_374 & _T_400; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_0 = {_T_401,_T_393,_T_385,_T_377}; // @[Cat.scala 29:58] + wire _T_71 = |ld_byte_hitvecfn_hi_0; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_73 = _T_71 | ld_byte_ibuf_hit_hi[0]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_189 = ld_addr_hitvec_hi_3 & buf_byteen_3[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_191 = _T_189 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_185 = ld_addr_hitvec_hi_2 & buf_byteen_2[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_187 = _T_185 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_181 = ld_addr_hitvec_hi_1 & buf_byteen_1[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_183 = _T_181 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_177 = ld_addr_hitvec_hi_0 & buf_byteen_0[1]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_179 = _T_177 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_1 = {_T_191,_T_187,_T_183,_T_179}; // @[Cat.scala 29:58] + wire [3:0] _T_430 = ld_byte_hitvec_hi_1 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_431 = |_T_430; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_432 = ~_T_431; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_433 = ld_byte_hitvec_hi_1[3] & _T_432; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_435 = ~ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_436 = _T_433 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_422 = ld_byte_hitvec_hi_1 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_423 = |_T_422; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_424 = ~_T_423; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_425 = ld_byte_hitvec_hi_1[2] & _T_424; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_428 = _T_425 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_414 = ld_byte_hitvec_hi_1 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_415 = |_T_414; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_416 = ~_T_415; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_417 = ld_byte_hitvec_hi_1[1] & _T_416; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_420 = _T_417 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_406 = ld_byte_hitvec_hi_1 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_407 = |_T_406; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_408 = ~_T_407; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_409 = ld_byte_hitvec_hi_1[0] & _T_408; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_412 = _T_409 & _T_435; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_1 = {_T_436,_T_428,_T_420,_T_412}; // @[Cat.scala 29:58] + wire _T_74 = |ld_byte_hitvecfn_hi_1; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_76 = _T_74 | ld_byte_ibuf_hit_hi[1]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_207 = ld_addr_hitvec_hi_3 & buf_byteen_3[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_209 = _T_207 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_203 = ld_addr_hitvec_hi_2 & buf_byteen_2[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_205 = _T_203 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_199 = ld_addr_hitvec_hi_1 & buf_byteen_1[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_201 = _T_199 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_195 = ld_addr_hitvec_hi_0 & buf_byteen_0[2]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_197 = _T_195 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_2 = {_T_209,_T_205,_T_201,_T_197}; // @[Cat.scala 29:58] + wire [3:0] _T_465 = ld_byte_hitvec_hi_2 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_466 = |_T_465; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_467 = ~_T_466; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_468 = ld_byte_hitvec_hi_2[3] & _T_467; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_470 = ~ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_471 = _T_468 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_457 = ld_byte_hitvec_hi_2 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_458 = |_T_457; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_459 = ~_T_458; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_460 = ld_byte_hitvec_hi_2[2] & _T_459; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_463 = _T_460 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_449 = ld_byte_hitvec_hi_2 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_450 = |_T_449; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_451 = ~_T_450; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_452 = ld_byte_hitvec_hi_2[1] & _T_451; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_455 = _T_452 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_441 = ld_byte_hitvec_hi_2 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_442 = |_T_441; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_443 = ~_T_442; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_444 = ld_byte_hitvec_hi_2[0] & _T_443; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_447 = _T_444 & _T_470; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_2 = {_T_471,_T_463,_T_455,_T_447}; // @[Cat.scala 29:58] + wire _T_77 = |ld_byte_hitvecfn_hi_2; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_79 = _T_77 | ld_byte_ibuf_hit_hi[2]; // @[el2_lsu_bus_buffer.scala 192:77] + wire _T_225 = ld_addr_hitvec_hi_3 & buf_byteen_3[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_227 = _T_225 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_221 = ld_addr_hitvec_hi_2 & buf_byteen_2[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_223 = _T_221 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_217 = ld_addr_hitvec_hi_1 & buf_byteen_1[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_219 = _T_217 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire _T_213 = ld_addr_hitvec_hi_0 & buf_byteen_0[3]; // @[el2_lsu_bus_buffer.scala 195:95] + wire _T_215 = _T_213 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_buffer.scala 195:114] + wire [3:0] ld_byte_hitvec_hi_3 = {_T_227,_T_223,_T_219,_T_215}; // @[Cat.scala 29:58] + wire [3:0] _T_500 = ld_byte_hitvec_hi_3 & buf_age_younger_3; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_501 = |_T_500; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_502 = ~_T_501; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_503 = ld_byte_hitvec_hi_3[3] & _T_502; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_505 = ~ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 200:150] + wire _T_506 = _T_503 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_492 = ld_byte_hitvec_hi_3 & buf_age_younger_2; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_493 = |_T_492; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_494 = ~_T_493; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_495 = ld_byte_hitvec_hi_3[2] & _T_494; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_498 = _T_495 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_484 = ld_byte_hitvec_hi_3 & buf_age_younger_1; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_485 = |_T_484; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_486 = ~_T_485; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_487 = ld_byte_hitvec_hi_3[1] & _T_486; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_490 = _T_487 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] _T_476 = ld_byte_hitvec_hi_3 & buf_age_younger_0; // @[el2_lsu_bus_buffer.scala 200:122] + wire _T_477 = |_T_476; // @[el2_lsu_bus_buffer.scala 200:144] + wire _T_478 = ~_T_477; // @[el2_lsu_bus_buffer.scala 200:99] + wire _T_479 = ld_byte_hitvec_hi_3[0] & _T_478; // @[el2_lsu_bus_buffer.scala 200:97] + wire _T_482 = _T_479 & _T_505; // @[el2_lsu_bus_buffer.scala 200:148] + wire [3:0] ld_byte_hitvecfn_hi_3 = {_T_506,_T_498,_T_490,_T_482}; // @[Cat.scala 29:58] + wire _T_80 = |ld_byte_hitvecfn_hi_3; // @[el2_lsu_bus_buffer.scala 192:73] + wire _T_82 = _T_80 | ld_byte_ibuf_hit_hi[3]; // @[el2_lsu_bus_buffer.scala 192:77] + wire [2:0] _T_84 = {_T_82,_T_79,_T_76}; // @[Cat.scala 29:58] + wire [7:0] _T_530 = ld_byte_ibuf_hit_lo[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_533 = ld_byte_ibuf_hit_lo[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_536 = ld_byte_ibuf_hit_lo[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_539 = ld_byte_ibuf_hit_lo[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_lo_initial = {_T_539,_T_536,_T_533,_T_530}; // @[Cat.scala 29:58] + wire [7:0] _T_544 = ld_byte_ibuf_hit_hi[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_547 = ld_byte_ibuf_hit_hi[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_550 = ld_byte_ibuf_hit_hi[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_553 = ld_byte_ibuf_hit_hi[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [31:0] ld_fwddata_buf_hi_initial = {_T_553,_T_550,_T_547,_T_544}; // @[Cat.scala 29:58] + wire [7:0] _T_558 = ld_byte_hitvecfn_lo_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_0; // @[el2_lib.scala 514:16] + wire [7:0] _T_560 = _T_558 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_563 = ld_byte_hitvecfn_lo_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_1; // @[el2_lib.scala 514:16] + wire [7:0] _T_565 = _T_563 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_568 = ld_byte_hitvecfn_lo_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_2; // @[el2_lib.scala 514:16] + wire [7:0] _T_570 = _T_568 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_573 = ld_byte_hitvecfn_lo_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + reg [31:0] buf_data_3; // @[el2_lib.scala 514:16] + wire [7:0] _T_575 = _T_573 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 218:91] + wire [7:0] _T_576 = _T_560 | _T_565; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_577 = _T_576 | _T_570; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_578 = _T_577 | _T_575; // @[el2_lsu_bus_buffer.scala 218:123] + wire [7:0] _T_581 = ld_byte_hitvecfn_lo_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_583 = _T_581 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_586 = ld_byte_hitvecfn_lo_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_588 = _T_586 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_591 = ld_byte_hitvecfn_lo_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_593 = _T_591 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_596 = ld_byte_hitvecfn_lo_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_598 = _T_596 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 219:65] + wire [7:0] _T_599 = _T_583 | _T_588; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_600 = _T_599 | _T_593; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_601 = _T_600 | _T_598; // @[el2_lsu_bus_buffer.scala 219:97] + wire [7:0] _T_604 = ld_byte_hitvecfn_lo_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_606 = _T_604 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_609 = ld_byte_hitvecfn_lo_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_611 = _T_609 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_614 = ld_byte_hitvecfn_lo_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_616 = _T_614 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_619 = ld_byte_hitvecfn_lo_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_621 = _T_619 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 220:65] + wire [7:0] _T_622 = _T_606 | _T_611; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_623 = _T_622 | _T_616; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_624 = _T_623 | _T_621; // @[el2_lsu_bus_buffer.scala 220:97] + wire [7:0] _T_627 = ld_byte_hitvecfn_lo_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_629 = _T_627 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_632 = ld_byte_hitvecfn_lo_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_634 = _T_632 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_637 = ld_byte_hitvecfn_lo_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_639 = _T_637 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_642 = ld_byte_hitvecfn_lo_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_644 = _T_642 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 221:65] + wire [7:0] _T_645 = _T_629 | _T_634; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_646 = _T_645 | _T_639; // @[el2_lsu_bus_buffer.scala 221:97] + wire [7:0] _T_647 = _T_646 | _T_644; // @[el2_lsu_bus_buffer.scala 221:97] + wire [31:0] _T_650 = {_T_578,_T_601,_T_624,_T_647}; // @[Cat.scala 29:58] + reg [31:0] ibuf_data; // @[el2_lib.scala 514:16] + wire [31:0] _T_651 = ld_fwddata_buf_lo_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 222:32] + wire [7:0] _T_655 = ld_byte_hitvecfn_hi_3[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_657 = _T_655 & buf_data_0[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_660 = ld_byte_hitvecfn_hi_3[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_662 = _T_660 & buf_data_1[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_665 = ld_byte_hitvecfn_hi_3[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_667 = _T_665 & buf_data_2[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_670 = ld_byte_hitvecfn_hi_3[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_672 = _T_670 & buf_data_3[31:24]; // @[el2_lsu_bus_buffer.scala 224:91] + wire [7:0] _T_673 = _T_657 | _T_662; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_674 = _T_673 | _T_667; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_675 = _T_674 | _T_672; // @[el2_lsu_bus_buffer.scala 224:123] + wire [7:0] _T_678 = ld_byte_hitvecfn_hi_2[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_680 = _T_678 & buf_data_0[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_683 = ld_byte_hitvecfn_hi_2[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_685 = _T_683 & buf_data_1[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_688 = ld_byte_hitvecfn_hi_2[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_690 = _T_688 & buf_data_2[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_693 = ld_byte_hitvecfn_hi_2[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_695 = _T_693 & buf_data_3[23:16]; // @[el2_lsu_bus_buffer.scala 225:65] + wire [7:0] _T_696 = _T_680 | _T_685; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_697 = _T_696 | _T_690; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_698 = _T_697 | _T_695; // @[el2_lsu_bus_buffer.scala 225:97] + wire [7:0] _T_701 = ld_byte_hitvecfn_hi_1[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_703 = _T_701 & buf_data_0[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_706 = ld_byte_hitvecfn_hi_1[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_708 = _T_706 & buf_data_1[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_711 = ld_byte_hitvecfn_hi_1[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_713 = _T_711 & buf_data_2[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_716 = ld_byte_hitvecfn_hi_1[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_718 = _T_716 & buf_data_3[15:8]; // @[el2_lsu_bus_buffer.scala 226:65] + wire [7:0] _T_719 = _T_703 | _T_708; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_720 = _T_719 | _T_713; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_721 = _T_720 | _T_718; // @[el2_lsu_bus_buffer.scala 226:97] + wire [7:0] _T_724 = ld_byte_hitvecfn_hi_0[0] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_726 = _T_724 & buf_data_0[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_729 = ld_byte_hitvecfn_hi_0[1] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_731 = _T_729 & buf_data_1[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_734 = ld_byte_hitvecfn_hi_0[2] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_736 = _T_734 & buf_data_2[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_739 = ld_byte_hitvecfn_hi_0[3] ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_741 = _T_739 & buf_data_3[7:0]; // @[el2_lsu_bus_buffer.scala 227:65] + wire [7:0] _T_742 = _T_726 | _T_731; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_743 = _T_742 | _T_736; // @[el2_lsu_bus_buffer.scala 227:97] + wire [7:0] _T_744 = _T_743 | _T_741; // @[el2_lsu_bus_buffer.scala 227:97] + wire [31:0] _T_747 = {_T_675,_T_698,_T_721,_T_744}; // @[Cat.scala 29:58] + wire [31:0] _T_748 = ld_fwddata_buf_hi_initial & ibuf_data; // @[el2_lsu_bus_buffer.scala 228:32] + wire [3:0] _T_750 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_751 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_752 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_753 = _T_750 | _T_751; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_r = _T_753 | _T_752; // @[Mux.scala 27:72] + wire _T_756 = io_lsu_addr_r[1:0] == 2'h0; // @[el2_lsu_bus_buffer.scala 235:55] + wire _T_758 = io_lsu_addr_r[1:0] == 2'h1; // @[el2_lsu_bus_buffer.scala 236:24] + wire [3:0] _T_760 = {3'h0,ldst_byteen_r[3]}; // @[Cat.scala 29:58] + wire _T_762 = io_lsu_addr_r[1:0] == 2'h2; // @[el2_lsu_bus_buffer.scala 237:24] + wire [3:0] _T_764 = {2'h0,ldst_byteen_r[3:2]}; // @[Cat.scala 29:58] + wire _T_766 = io_lsu_addr_r[1:0] == 2'h3; // @[el2_lsu_bus_buffer.scala 238:24] + wire [3:0] _T_768 = {1'h0,ldst_byteen_r[3:1]}; // @[Cat.scala 29:58] + wire [3:0] _T_770 = _T_758 ? _T_760 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_771 = _T_762 ? _T_764 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_772 = _T_766 ? _T_768 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_774 = _T_770 | _T_771; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_hi_r = _T_774 | _T_772; // @[Mux.scala 27:72] + wire [3:0] _T_781 = {ldst_byteen_r[2:0],1'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_785 = {ldst_byteen_r[1:0],2'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_789 = {ldst_byteen_r[0],3'h0}; // @[Cat.scala 29:58] + wire [3:0] _T_790 = _T_756 ? ldst_byteen_r : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_791 = _T_758 ? _T_781 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_792 = _T_762 ? _T_785 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_793 = _T_766 ? _T_789 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_794 = _T_790 | _T_791; // @[Mux.scala 27:72] + wire [3:0] _T_795 = _T_794 | _T_792; // @[Mux.scala 27:72] + wire [3:0] ldst_byteen_lo_r = _T_795 | _T_793; // @[Mux.scala 27:72] + wire [31:0] _T_802 = {24'h0,io_store_data_r[31:24]}; // @[Cat.scala 29:58] + wire [31:0] _T_806 = {16'h0,io_store_data_r[31:16]}; // @[Cat.scala 29:58] + wire [31:0] _T_810 = {8'h0,io_store_data_r[31:8]}; // @[Cat.scala 29:58] + wire [31:0] _T_812 = _T_758 ? _T_802 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_813 = _T_762 ? _T_806 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_814 = _T_766 ? _T_810 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_816 = _T_812 | _T_813; // @[Mux.scala 27:72] + wire [31:0] store_data_hi_r = _T_816 | _T_814; // @[Mux.scala 27:72] + wire [31:0] _T_823 = {io_store_data_r[23:0],8'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_827 = {io_store_data_r[15:0],16'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_831 = {io_store_data_r[7:0],24'h0}; // @[Cat.scala 29:58] + wire [31:0] _T_832 = _T_756 ? io_store_data_r : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_833 = _T_758 ? _T_823 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_834 = _T_762 ? _T_827 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_835 = _T_766 ? _T_831 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_836 = _T_832 | _T_833; // @[Mux.scala 27:72] + wire [31:0] _T_837 = _T_836 | _T_834; // @[Mux.scala 27:72] + wire [31:0] store_data_lo_r = _T_837 | _T_835; // @[Mux.scala 27:72] + wire ldst_samedw_r = io_lsu_addr_r[3] == io_end_addr_r[3]; // @[el2_lsu_bus_buffer.scala 255:40] + wire _T_844 = ~io_lsu_addr_r[0]; // @[el2_lsu_bus_buffer.scala 257:26] + wire _T_845 = io_lsu_pkt_r_word & _T_756; // @[Mux.scala 27:72] + wire _T_846 = io_lsu_pkt_r_half & _T_844; // @[Mux.scala 27:72] + wire _T_848 = _T_845 | _T_846; // @[Mux.scala 27:72] + wire is_aligned_r = _T_848 | io_lsu_pkt_r_by; // @[Mux.scala 27:72] + wire _T_850 = io_lsu_pkt_r_load | io_no_word_merge_r; // @[el2_lsu_bus_buffer.scala 259:55] + wire _T_851 = io_lsu_busreq_r & _T_850; // @[el2_lsu_bus_buffer.scala 259:34] + wire _T_852 = ~ibuf_valid; // @[el2_lsu_bus_buffer.scala 259:79] + wire ibuf_byp = _T_851 & _T_852; // @[el2_lsu_bus_buffer.scala 259:77] + wire _T_853 = io_lsu_busreq_r & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 260:36] + wire _T_854 = ~ibuf_byp; // @[el2_lsu_bus_buffer.scala 260:56] + wire ibuf_wr_en = _T_853 & _T_854; // @[el2_lsu_bus_buffer.scala 260:54] + wire _T_855 = ~ibuf_wr_en; // @[el2_lsu_bus_buffer.scala 262:36] + reg [2:0] ibuf_timer; // @[el2_lsu_bus_buffer.scala 305:55] + wire _T_864 = ibuf_timer == 3'h7; // @[el2_lsu_bus_buffer.scala 268:62] + wire _T_865 = ibuf_wr_en | _T_864; // @[el2_lsu_bus_buffer.scala 268:48] + wire _T_929 = _T_853 & io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 287:54] + wire _T_930 = _T_929 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 287:75] + wire _T_931 = _T_930 & ibuf_write; // @[el2_lsu_bus_buffer.scala 287:88] + wire _T_934 = io_lsu_addr_r[31:2] == ibuf_addr[31:2]; // @[el2_lsu_bus_buffer.scala 287:124] + wire _T_935 = _T_931 & _T_934; // @[el2_lsu_bus_buffer.scala 287:101] + wire _T_936 = ~io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 287:147] + wire _T_937 = _T_935 & _T_936; // @[el2_lsu_bus_buffer.scala 287:145] + wire _T_938 = ~io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 287:170] + wire ibuf_merge_en = _T_937 & _T_938; // @[el2_lsu_bus_buffer.scala 287:168] + wire ibuf_merge_in = ~io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 288:20] + wire _T_866 = ibuf_merge_en & ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 268:98] + wire _T_867 = ~_T_866; // @[el2_lsu_bus_buffer.scala 268:82] + wire _T_868 = _T_865 & _T_867; // @[el2_lsu_bus_buffer.scala 268:80] + wire _T_869 = _T_868 | ibuf_byp; // @[el2_lsu_bus_buffer.scala 269:5] + wire _T_857 = ~io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 263:44] + wire _T_858 = io_lsu_busreq_m & _T_857; // @[el2_lsu_bus_buffer.scala 263:42] + wire _T_859 = _T_858 & ibuf_valid; // @[el2_lsu_bus_buffer.scala 263:61] + wire _T_862 = ibuf_addr[31:2] != io_lsu_addr_m[31:2]; // @[el2_lsu_bus_buffer.scala 263:115] + wire _T_863 = io_lsu_pkt_m_load | _T_862; // @[el2_lsu_bus_buffer.scala 263:95] + wire ibuf_force_drain = _T_859 & _T_863; // @[el2_lsu_bus_buffer.scala 263:74] + wire _T_870 = _T_869 | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 269:16] reg ibuf_sideeffect; // @[Reg.scala 27:20] - wire _T_930 = _T_929 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 450:64] - wire _T_931 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 450:84] - wire _T_932 = _T_930 | _T_931; // @[el2_lsu_bus_buffer.scala 450:82] - wire _T_933 = _T_932 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 450:96] - wire ibuf_drain_vld = ibuf_valid & _T_933; // @[el2_lsu_bus_buffer.scala 449:44] - wire _T_911 = ibuf_drain_vld & _T_910; // @[el2_lsu_bus_buffer.scala 447:50] - wire ibuf_rst = _T_911 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 447:65] + wire _T_871 = _T_870 | ibuf_sideeffect; // @[el2_lsu_bus_buffer.scala 269:35] + wire _T_872 = ~ibuf_write; // @[el2_lsu_bus_buffer.scala 269:55] + wire _T_873 = _T_871 | _T_872; // @[el2_lsu_bus_buffer.scala 269:53] + wire _T_874 = _T_873 | io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_buffer.scala 269:67] + wire ibuf_drain_vld = ibuf_valid & _T_874; // @[el2_lsu_bus_buffer.scala 268:32] + wire _T_856 = ibuf_drain_vld & _T_855; // @[el2_lsu_bus_buffer.scala 262:34] + wire ibuf_rst = _T_856 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 262:49] + reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 669:49] + reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 668:49] reg [1:0] ibuf_tag; // @[Reg.scala 27:20] - reg [1:0] WrPtr1_r; // @[el2_lsu_bus_buffer.scala 751:44] - reg [1:0] WrPtr0_r; // @[el2_lsu_bus_buffer.scala 750:44] wire [1:0] ibuf_sz_in = {io_lsu_pkt_r_word,io_lsu_pkt_r_half}; // @[Cat.scala 29:58] - wire [3:0] _T_945 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 455:85] - wire [7:0] _T_954 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_957 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_958 = _T_925 ? _T_954 : _T_957; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_963 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_966 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_967 = _T_925 ? _T_963 : _T_966; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_972 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_975 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_976 = _T_925 ? _T_972 : _T_975; // @[el2_lsu_bus_buffer.scala 456:57] - wire [7:0] _T_981 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 456:93] - wire [7:0] _T_984 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 456:176] - wire [7:0] _T_985 = _T_925 ? _T_981 : _T_984; // @[el2_lsu_bus_buffer.scala 456:57] - wire [31:0] ibuf_data_in = {_T_985,_T_976,_T_967,_T_958}; // @[Cat.scala 29:58] - wire _T_989 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 457:69] - wire [2:0] _T_991 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 457:115] - wire _T_994 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 458:75] - wire _T_995 = ibuf_merge_en & _T_994; // @[el2_lsu_bus_buffer.scala 458:73] - wire _T_998 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1000 = _T_995 ? _T_998 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1005 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1007 = _T_995 ? _T_1005 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1012 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1014 = _T_995 ? _T_1012 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 458:57] - wire _T_1019 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 458:106] - wire _T_1021 = _T_995 ? _T_1019 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 458:57] - wire [3:0] ibuf_byteen_out = {_T_1021,_T_1014,_T_1007,_T_1000}; // @[Cat.scala 29:58] - wire [7:0] _T_1032 = _T_995 ? _T_954 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1040 = _T_995 ? _T_963 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1048 = _T_995 ? _T_972 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [7:0] _T_1056 = _T_995 ? _T_981 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 459:57] - wire [31:0] ibuf_data_out = {_T_1056,_T_1048,_T_1040,_T_1032}; // @[Cat.scala 29:58] - wire _T_1074 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 464:32] - wire _T_1075 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 464:72] + wire [3:0] _T_881 = ibuf_byteen | ldst_byteen_lo_r; // @[el2_lsu_bus_buffer.scala 278:77] + wire [7:0] _T_889 = ldst_byteen_lo_r[0] ? store_data_lo_r[7:0] : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_892 = io_ldst_dual_r ? store_data_hi_r[7:0] : store_data_lo_r[7:0]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_893 = _T_866 ? _T_889 : _T_892; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_898 = ldst_byteen_lo_r[1] ? store_data_lo_r[15:8] : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_901 = io_ldst_dual_r ? store_data_hi_r[15:8] : store_data_lo_r[15:8]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_902 = _T_866 ? _T_898 : _T_901; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_907 = ldst_byteen_lo_r[2] ? store_data_lo_r[23:16] : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_910 = io_ldst_dual_r ? store_data_hi_r[23:16] : store_data_lo_r[23:16]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_911 = _T_866 ? _T_907 : _T_910; // @[el2_lsu_bus_buffer.scala 282:46] + wire [7:0] _T_916 = ldst_byteen_lo_r[3] ? store_data_lo_r[31:24] : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 283:8] + wire [7:0] _T_919 = io_ldst_dual_r ? store_data_hi_r[31:24] : store_data_lo_r[31:24]; // @[el2_lsu_bus_buffer.scala 284:8] + wire [7:0] _T_920 = _T_866 ? _T_916 : _T_919; // @[el2_lsu_bus_buffer.scala 282:46] + wire [23:0] _T_922 = {_T_920,_T_911,_T_902}; // @[Cat.scala 29:58] + wire _T_923 = ibuf_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 285:59] + wire [2:0] _T_926 = ibuf_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 285:93] + wire _T_941 = ~ibuf_merge_in; // @[el2_lsu_bus_buffer.scala 289:65] + wire _T_942 = ibuf_merge_en & _T_941; // @[el2_lsu_bus_buffer.scala 289:63] + wire _T_945 = ibuf_byteen[0] | ldst_byteen_lo_r[0]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_947 = _T_942 ? _T_945 : ibuf_byteen[0]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_952 = ibuf_byteen[1] | ldst_byteen_lo_r[1]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_954 = _T_942 ? _T_952 : ibuf_byteen[1]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_959 = ibuf_byteen[2] | ldst_byteen_lo_r[2]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_961 = _T_942 ? _T_959 : ibuf_byteen[2]; // @[el2_lsu_bus_buffer.scala 289:48] + wire _T_966 = ibuf_byteen[3] | ldst_byteen_lo_r[3]; // @[el2_lsu_bus_buffer.scala 289:96] + wire _T_968 = _T_942 ? _T_966 : ibuf_byteen[3]; // @[el2_lsu_bus_buffer.scala 289:48] + wire [3:0] ibuf_byteen_out = {_T_968,_T_961,_T_954,_T_947}; // @[Cat.scala 29:58] + wire [7:0] _T_978 = _T_942 ? _T_889 : ibuf_data[7:0]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_986 = _T_942 ? _T_898 : ibuf_data[15:8]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_994 = _T_942 ? _T_907 : ibuf_data[23:16]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [7:0] _T_1002 = _T_942 ? _T_916 : ibuf_data[31:24]; // @[el2_lsu_bus_buffer.scala 290:45] + wire [31:0] ibuf_data_out = {_T_1002,_T_994,_T_986,_T_978}; // @[Cat.scala 29:58] + wire _T_1005 = ibuf_wr_en | ibuf_valid; // @[el2_lsu_bus_buffer.scala 292:58] + wire _T_1006 = ~ibuf_rst; // @[el2_lsu_bus_buffer.scala 292:93] + reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] reg ibuf_dual; // @[Reg.scala 27:20] reg ibuf_samedw; // @[Reg.scala 27:20] reg ibuf_nomerge; // @[Reg.scala 27:20] reg ibuf_unsign; // @[Reg.scala 27:20] reg [1:0] ibuf_sz; // @[Reg.scala 27:20] - reg [1:0] ibuf_dualtag; // @[Reg.scala 27:20] - wire _T_3984 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3985 = _T_2730 & _T_3984; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3986 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3987 = _T_3985 | _T_3986; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_3989 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3990 = _T_2825 & _T_3989; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3991 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3992 = _T_3990 | _T_3991; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4004 = _T_3987 + _T_3992; // @[el2_lsu_bus_buffer.scala 700:160] - wire _T_3994 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_3995 = _T_2920 & _T_3994; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_3996 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_3997 = _T_3995 | _T_3996; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4006 = _T_4004 + _T_3997; // @[el2_lsu_bus_buffer.scala 700:160] - wire _T_3999 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 700:88] - wire _T_4000 = _T_3015 & _T_3999; // @[el2_lsu_bus_buffer.scala 700:86] - wire _T_4001 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 700:130] - wire _T_4002 = _T_4000 | _T_4001; // @[el2_lsu_bus_buffer.scala 700:114] - wire _T_4008 = _T_4006 + _T_4002; // @[el2_lsu_bus_buffer.scala 700:160] - wire [3:0] buf_numvld_pend_any = {{3'd0}, _T_4008}; // @[el2_lsu_bus_buffer.scala 700:25] - wire _T_1095 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 483:67] - wire _T_1096 = ibuf_byp & _T_1095; // @[el2_lsu_bus_buffer.scala 483:39] - wire _T_1097 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 483:79] - wire _T_1098 = _T_1097 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 483:99] - wire ibuf_buf_byp = _T_1096 & _T_1098; // @[el2_lsu_bus_buffer.scala 483:76] - wire _T_1103 = _T_915 & _T_903; // @[el2_lsu_bus_buffer.scala 484:64] - wire _T_3978 = _T_3985 + _T_3990; // @[el2_lsu_bus_buffer.scala 699:158] - wire _T_3980 = _T_3978 + _T_3995; // @[el2_lsu_bus_buffer.scala 699:158] - wire _T_3982 = _T_3980 + _T_4000; // @[el2_lsu_bus_buffer.scala 699:158] - wire [3:0] buf_numvld_cmd_any = {{3'd0}, _T_3982}; // @[el2_lsu_bus_buffer.scala 699:25] - wire _T_1105 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 484:105] - wire _T_1106 = _T_1103 & _T_1105; // @[el2_lsu_bus_buffer.scala 484:78] - wire [3:0] _T_2961 = {buf_age_3_3,buf_age_3_2,buf_age_3_1,buf_age_3_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2962 = |_T_2961; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2963 = ~_T_2962; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2965 = _T_2963 & _T_3015; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_3 = _T_2965 & _T_3999; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_2581 = {buf_age_2_3,buf_age_2_2,buf_age_2_1,buf_age_2_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2582 = |_T_2581; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2583 = ~_T_2582; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2585 = _T_2583 & _T_2920; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_2 = _T_2585 & _T_3994; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_2201 = {buf_age_1_3,buf_age_1_2,buf_age_1_1,buf_age_1_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_2202 = |_T_2201; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_2203 = ~_T_2202; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_2205 = _T_2203 & _T_2825; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_1 = _T_2205 & _T_3989; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_1821 = {buf_age_0_3,buf_age_0_2,buf_age_0_1,buf_age_0_0}; // @[el2_lsu_bus_buffer.scala 558:45] - wire _T_1822 = |_T_1821; // @[el2_lsu_bus_buffer.scala 558:55] - wire _T_1823 = ~_T_1822; // @[el2_lsu_bus_buffer.scala 558:32] - wire _T_1825 = _T_1823 & _T_2730; // @[el2_lsu_bus_buffer.scala 558:59] - wire CmdPtr0Dec_0 = _T_1825 & _T_3984; // @[el2_lsu_bus_buffer.scala 558:86] - wire [3:0] _T_3056 = {CmdPtr0Dec_3,CmdPtr0Dec_2,CmdPtr0Dec_1,CmdPtr0Dec_0}; // @[el2_lsu_bus_buffer.scala 578:59] - wire [3:0] _T_3061 = _T_3056[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3062 = _T_3056[2] ? 4'h4 : _T_3061; // @[Mux.scala 47:69] - wire [3:0] _T_3063 = _T_3056[1] ? 4'h2 : _T_3062; // @[Mux.scala 47:69] - wire [3:0] _T_3064 = _T_3056[0] ? 4'h1 : _T_3063; // @[Mux.scala 47:69] - wire [1:0] CmdPtr0 = _T_3064[1:0]; // @[el2_lsu_bus_buffer.scala 578:27] - wire [31:0] _GEN_13 = 2'h1 == CmdPtr0 ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 484:163] - wire [31:0] _GEN_14 = 2'h2 == CmdPtr0 ? buf_addr_2 : _GEN_13; // @[el2_lsu_bus_buffer.scala 484:163] - wire [31:0] _GEN_15 = 2'h3 == CmdPtr0 ? buf_addr_3 : _GEN_14; // @[el2_lsu_bus_buffer.scala 484:163] - wire _T_1109 = io_lsu_addr_m[31:2] != _GEN_15[31:2]; // @[el2_lsu_bus_buffer.scala 484:142] - wire obuf_force_wr_en = _T_1106 & _T_1109; // @[el2_lsu_bus_buffer.scala 484:119] - wire _T_3946 = _T_3985 & buf_write_0; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3950 = _T_3990 & buf_write_1; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3960 = _T_3946 + _T_3950; // @[el2_lsu_bus_buffer.scala 698:158] - wire _T_3954 = _T_3995 & buf_write_2; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3962 = _T_3960 + _T_3954; // @[el2_lsu_bus_buffer.scala 698:158] - wire _T_3958 = _T_4000 & buf_write_3; // @[el2_lsu_bus_buffer.scala 698:113] - wire _T_3964 = _T_3962 + _T_3958; // @[el2_lsu_bus_buffer.scala 698:158] - wire [3:0] buf_numvld_wrcmd_any = {{3'd0}, _T_3964}; // @[el2_lsu_bus_buffer.scala 698:25] - wire _T_1112 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 485:56] - wire _T_1115 = _T_1112 & _T_1105; // @[el2_lsu_bus_buffer.scala 485:70] - reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 527:35] - wire _T_1116 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 485:128] - wire _T_1117 = _T_1115 & _T_1116; // @[el2_lsu_bus_buffer.scala 485:111] - wire _T_1119 = _T_1117 & _T_1070; // @[el2_lsu_bus_buffer.scala 485:166] + wire _T_4446 = buf_write[3] & _T_2621; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4447 = ~buf_cmd_state_bus_en_3; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4448 = _T_4446 & _T_4447; // @[el2_lsu_bus_buffer.scala 575:89] + wire _T_4441 = buf_write[2] & _T_2616; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4442 = ~buf_cmd_state_bus_en_2; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4443 = _T_4441 & _T_4442; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _T_4449 = _T_4448 + _T_4443; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4436 = buf_write[1] & _T_2611; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4437 = ~buf_cmd_state_bus_en_1; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4438 = _T_4436 & _T_4437; // @[el2_lsu_bus_buffer.scala 575:89] + wire [1:0] _GEN_362 = {{1'd0}, _T_4438}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [2:0] _T_4450 = _T_4449 + _GEN_362; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_4431 = buf_write[0] & _T_2606; // @[el2_lsu_bus_buffer.scala 575:64] + wire _T_4432 = ~buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 575:91] + wire _T_4433 = _T_4431 & _T_4432; // @[el2_lsu_bus_buffer.scala 575:89] + wire [2:0] _GEN_363 = {{2'd0}, _T_4433}; // @[el2_lsu_bus_buffer.scala 575:142] + wire [3:0] buf_numvld_wrcmd_any = _T_4450 + _GEN_363; // @[el2_lsu_bus_buffer.scala 575:142] + wire _T_1016 = buf_numvld_wrcmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:43] + wire _T_4463 = _T_2621 & _T_4447; // @[el2_lsu_bus_buffer.scala 576:73] + wire _T_4460 = _T_2616 & _T_4442; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _T_4464 = _T_4463 + _T_4460; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4457 = _T_2611 & _T_4437; // @[el2_lsu_bus_buffer.scala 576:73] + wire [1:0] _GEN_364 = {{1'd0}, _T_4457}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [2:0] _T_4465 = _T_4464 + _GEN_364; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_4454 = _T_2606 & _T_4432; // @[el2_lsu_bus_buffer.scala 576:73] + wire [2:0] _GEN_365 = {{2'd0}, _T_4454}; // @[el2_lsu_bus_buffer.scala 576:126] + wire [3:0] buf_numvld_cmd_any = _T_4465 + _GEN_365; // @[el2_lsu_bus_buffer.scala 576:126] + wire _T_1017 = buf_numvld_cmd_any == 4'h1; // @[el2_lsu_bus_buffer.scala 315:72] + wire _T_1018 = _T_1016 & _T_1017; // @[el2_lsu_bus_buffer.scala 315:51] + reg [2:0] obuf_wr_timer; // @[el2_lsu_bus_buffer.scala 414:54] + wire _T_1019 = obuf_wr_timer != 3'h7; // @[el2_lsu_bus_buffer.scala 315:97] + wire _T_1020 = _T_1018 & _T_1019; // @[el2_lsu_bus_buffer.scala 315:80] + wire _T_1022 = _T_1020 & _T_938; // @[el2_lsu_bus_buffer.scala 315:114] + wire _T_1979 = |buf_age_3; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1980 = ~_T_1979; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1982 = _T_1980 & _T_2621; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1984 = _T_1982 & _T_4447; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1973 = |buf_age_2; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1974 = ~_T_1973; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1976 = _T_1974 & _T_2616; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1978 = _T_1976 & _T_4442; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1967 = |buf_age_1; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1968 = ~_T_1967; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1970 = _T_1968 & _T_2611; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1972 = _T_1970 & _T_4437; // @[el2_lsu_bus_buffer.scala 431:88] + wire _T_1961 = |buf_age_0; // @[el2_lsu_bus_buffer.scala 431:58] + wire _T_1962 = ~_T_1961; // @[el2_lsu_bus_buffer.scala 431:45] + wire _T_1964 = _T_1962 & _T_2606; // @[el2_lsu_bus_buffer.scala 431:63] + wire _T_1966 = _T_1964 & _T_4432; // @[el2_lsu_bus_buffer.scala 431:88] + wire [3:0] CmdPtr0Dec = {_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire [7:0] _T_2054 = {4'h0,_T_1984,_T_1978,_T_1972,_T_1966}; // @[Cat.scala 29:58] + wire _T_2057 = _T_2054[4] | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2059 = _T_2057 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2061 = _T_2059 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2064 = _T_2054[2] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2066 = _T_2064 | _T_2054[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2068 = _T_2066 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2071 = _T_2054[1] | _T_2054[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2073 = _T_2071 | _T_2054[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2075 = _T_2073 | _T_2054[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2077 = {_T_2061,_T_2068,_T_2075}; // @[Cat.scala 29:58] + wire [1:0] CmdPtr0 = _T_2077[1:0]; // @[el2_lsu_bus_buffer.scala 444:11] + wire _T_1023 = CmdPtr0 == 2'h0; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1024 = CmdPtr0 == 2'h1; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1025 = CmdPtr0 == 2'h2; // @[el2_lsu_bus_buffer.scala 316:114] + wire _T_1026 = CmdPtr0 == 2'h3; // @[el2_lsu_bus_buffer.scala 316:114] reg buf_nomerge_0; // @[Reg.scala 27:20] + wire _T_1027 = _T_1023 & buf_nomerge_0; // @[Mux.scala 27:72] reg buf_nomerge_1; // @[Reg.scala 27:20] - wire _GEN_17 = 2'h1 == CmdPtr0 ? buf_nomerge_1 : buf_nomerge_0; // @[el2_lsu_bus_buffer.scala 486:59] + wire _T_1028 = _T_1024 & buf_nomerge_1; // @[Mux.scala 27:72] reg buf_nomerge_2; // @[Reg.scala 27:20] - wire _GEN_18 = 2'h2 == CmdPtr0 ? buf_nomerge_2 : _GEN_17; // @[el2_lsu_bus_buffer.scala 486:59] + wire _T_1029 = _T_1025 & buf_nomerge_2; // @[Mux.scala 27:72] reg buf_nomerge_3; // @[Reg.scala 27:20] - wire _GEN_19 = 2'h3 == CmdPtr0 ? buf_nomerge_3 : _GEN_18; // @[el2_lsu_bus_buffer.scala 486:59] - wire _T_1120 = ~_GEN_19; // @[el2_lsu_bus_buffer.scala 486:59] - wire _T_1121 = _T_1119 & _T_1120; // @[el2_lsu_bus_buffer.scala 486:57] - reg buf_sideeffect_0; // @[Reg.scala 27:20] - reg buf_sideeffect_1; // @[Reg.scala 27:20] - wire _GEN_21 = 2'h1 == CmdPtr0 ? buf_sideeffect_1 : buf_sideeffect_0; // @[el2_lsu_bus_buffer.scala 486:83] - reg buf_sideeffect_2; // @[Reg.scala 27:20] - wire _GEN_22 = 2'h2 == CmdPtr0 ? buf_sideeffect_2 : _GEN_21; // @[el2_lsu_bus_buffer.scala 486:83] - reg buf_sideeffect_3; // @[Reg.scala 27:20] - wire _GEN_23 = 2'h3 == CmdPtr0 ? buf_sideeffect_3 : _GEN_22; // @[el2_lsu_bus_buffer.scala 486:83] - wire _T_1122 = ~_GEN_23; // @[el2_lsu_bus_buffer.scala 486:83] - wire _T_1123 = _T_1121 & _T_1122; // @[el2_lsu_bus_buffer.scala 486:81] - wire _T_1124 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 486:110] - wire obuf_wr_wait = _T_1123 & _T_1124; // @[el2_lsu_bus_buffer.scala 486:108] - wire _T_1126 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 487:44] - reg obuf_sideeffect; // @[Reg.scala 27:20] - wire _T_4231 = obuf_sideeffect & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:62] - wire _T_4232 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4233 = buf_sideeffect_0 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4240 = _T_4232 & _T_4233; // @[Mux.scala 27:72] - wire _T_4234 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4235 = buf_sideeffect_1 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4241 = _T_4234 & _T_4235; // @[Mux.scala 27:72] - wire _T_4244 = _T_4240 | _T_4241; // @[Mux.scala 27:72] - wire _T_4236 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4237 = buf_sideeffect_2 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4242 = _T_4236 & _T_4237; // @[Mux.scala 27:72] - wire _T_4245 = _T_4244 | _T_4242; // @[Mux.scala 27:72] - wire _T_4238 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 731:145] - wire _T_4239 = buf_sideeffect_3 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 731:179] - wire _T_4243 = _T_4238 & _T_4239; // @[Mux.scala 27:72] - wire _T_4246 = _T_4245 | _T_4243; // @[Mux.scala 27:72] - wire bus_sideeffect_pend = obuf_valid ? _T_4231 : _T_4246; // @[el2_lsu_bus_buffer.scala 731:34] - wire _T_1127 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 487:86] - wire _T_1128 = ~_T_1127; // @[el2_lsu_bus_buffer.scala 487:64] - wire _T_1129 = _T_1126 & _T_1128; // @[el2_lsu_bus_buffer.scala 487:62] - wire [2:0] _GEN_25 = 2'h1 == CmdPtr0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 488:54] - wire [2:0] _GEN_26 = 2'h2 == CmdPtr0 ? buf_state_2 : _GEN_25; // @[el2_lsu_bus_buffer.scala 488:54] - wire [2:0] _GEN_27 = 2'h3 == CmdPtr0 ? buf_state_3 : _GEN_26; // @[el2_lsu_bus_buffer.scala 488:54] - wire _T_1130 = _GEN_27 == 3'h2; // @[el2_lsu_bus_buffer.scala 488:54] - wire _T_3087 = CmdPtr0Dec_0 | CmdPtr0Dec_1; // @[el2_lsu_bus_buffer.scala 581:49] - wire _T_3088 = _T_3087 | CmdPtr0Dec_2; // @[el2_lsu_bus_buffer.scala 581:49] - wire found_cmdptr0 = _T_3088 | CmdPtr0Dec_3; // @[el2_lsu_bus_buffer.scala 581:49] - wire _T_1131 = _T_1130 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 488:65] - wire _GEN_29 = 2'h1 == CmdPtr0 ? buf_cmd_state_bus_en_1 : buf_cmd_state_bus_en_0; // @[el2_lsu_bus_buffer.scala 488:83] - wire _GEN_30 = 2'h2 == CmdPtr0 ? buf_cmd_state_bus_en_2 : _GEN_29; // @[el2_lsu_bus_buffer.scala 488:83] - wire _GEN_31 = 2'h3 == CmdPtr0 ? buf_cmd_state_bus_en_3 : _GEN_30; // @[el2_lsu_bus_buffer.scala 488:83] - wire _T_1132 = ~_GEN_31; // @[el2_lsu_bus_buffer.scala 488:83] - wire _T_1133 = _T_1131 & _T_1132; // @[el2_lsu_bus_buffer.scala 488:81] - wire _T_1134 = _GEN_23 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 488:142] - wire _T_1135 = ~_T_1134; // @[el2_lsu_bus_buffer.scala 488:116] - wire _T_1136 = _T_1133 & _T_1135; // @[el2_lsu_bus_buffer.scala 488:114] - reg buf_dual_0; // @[Reg.scala 27:20] - reg buf_dual_1; // @[Reg.scala 27:20] - wire _GEN_33 = 2'h1 == CmdPtr0 ? buf_dual_1 : buf_dual_0; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_dual_2; // @[Reg.scala 27:20] - wire _GEN_34 = 2'h2 == CmdPtr0 ? buf_dual_2 : _GEN_33; // @[el2_lsu_bus_buffer.scala 489:58] + wire _T_1030 = _T_1026 & buf_nomerge_3; // @[Mux.scala 27:72] + wire _T_1031 = _T_1027 | _T_1028; // @[Mux.scala 27:72] + wire _T_1032 = _T_1031 | _T_1029; // @[Mux.scala 27:72] + wire _T_1033 = _T_1032 | _T_1030; // @[Mux.scala 27:72] + wire _T_1035 = ~_T_1033; // @[el2_lsu_bus_buffer.scala 316:31] + wire _T_1036 = _T_1022 & _T_1035; // @[el2_lsu_bus_buffer.scala 316:29] + reg _T_4330; // @[Reg.scala 27:20] + reg _T_4327; // @[Reg.scala 27:20] + reg _T_4324; // @[Reg.scala 27:20] + reg _T_4321; // @[Reg.scala 27:20] + wire [3:0] buf_sideeffect = {_T_4330,_T_4327,_T_4324,_T_4321}; // @[Cat.scala 29:58] + wire _T_1045 = _T_1023 & buf_sideeffect[0]; // @[Mux.scala 27:72] + wire _T_1046 = _T_1024 & buf_sideeffect[1]; // @[Mux.scala 27:72] + wire _T_1047 = _T_1025 & buf_sideeffect[2]; // @[Mux.scala 27:72] + wire _T_1048 = _T_1026 & buf_sideeffect[3]; // @[Mux.scala 27:72] + wire _T_1049 = _T_1045 | _T_1046; // @[Mux.scala 27:72] + wire _T_1050 = _T_1049 | _T_1047; // @[Mux.scala 27:72] + wire _T_1051 = _T_1050 | _T_1048; // @[Mux.scala 27:72] + wire _T_1053 = ~_T_1051; // @[el2_lsu_bus_buffer.scala 317:5] + wire _T_1054 = _T_1036 & _T_1053; // @[el2_lsu_bus_buffer.scala 316:140] + wire _T_1065 = _T_858 & _T_852; // @[el2_lsu_bus_buffer.scala 319:58] + wire _T_1067 = _T_1065 & _T_1017; // @[el2_lsu_bus_buffer.scala 319:72] + wire [29:0] _T_1077 = _T_1023 ? buf_addr_0[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1078 = _T_1024 ? buf_addr_1[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1081 = _T_1077 | _T_1078; // @[Mux.scala 27:72] + wire [29:0] _T_1079 = _T_1025 ? buf_addr_2[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1082 = _T_1081 | _T_1079; // @[Mux.scala 27:72] + wire [29:0] _T_1080 = _T_1026 ? buf_addr_3[31:2] : 30'h0; // @[Mux.scala 27:72] + wire [29:0] _T_1083 = _T_1082 | _T_1080; // @[Mux.scala 27:72] + wire _T_1085 = io_lsu_addr_m[31:2] != _T_1083; // @[el2_lsu_bus_buffer.scala 319:123] + wire obuf_force_wr_en = _T_1067 & _T_1085; // @[el2_lsu_bus_buffer.scala 319:101] + wire _T_1055 = ~obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 317:119] + wire obuf_wr_wait = _T_1054 & _T_1055; // @[el2_lsu_bus_buffer.scala 317:117] + wire _T_1056 = |buf_numvld_cmd_any; // @[el2_lsu_bus_buffer.scala 318:75] + wire _T_1057 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 318:95] + wire _T_1058 = _T_1056 & _T_1057; // @[el2_lsu_bus_buffer.scala 318:79] + wire [2:0] _T_1060 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 318:123] + wire _T_4482 = buf_state_3 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4486 = _T_4482 | _T_4463; // @[el2_lsu_bus_buffer.scala 577:74] + wire _T_4477 = buf_state_2 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4481 = _T_4477 | _T_4460; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _T_4487 = _T_4486 + _T_4481; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4472 = buf_state_1 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4476 = _T_4472 | _T_4457; // @[el2_lsu_bus_buffer.scala 577:74] + wire [1:0] _GEN_366 = {{1'd0}, _T_4476}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [2:0] _T_4488 = _T_4487 + _GEN_366; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_4467 = buf_state_0 == 3'h1; // @[el2_lsu_bus_buffer.scala 577:63] + wire _T_4471 = _T_4467 | _T_4454; // @[el2_lsu_bus_buffer.scala 577:74] + wire [2:0] _GEN_367 = {{2'd0}, _T_4471}; // @[el2_lsu_bus_buffer.scala 577:154] + wire [3:0] buf_numvld_pend_any = _T_4488 + _GEN_367; // @[el2_lsu_bus_buffer.scala 577:154] + wire _T_1087 = buf_numvld_pend_any == 4'h0; // @[el2_lsu_bus_buffer.scala 321:53] + wire _T_1088 = ibuf_byp & _T_1087; // @[el2_lsu_bus_buffer.scala 321:31] + wire _T_1089 = ~io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 321:64] + wire _T_1090 = _T_1089 | io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 321:84] + wire ibuf_buf_byp = _T_1088 & _T_1090; // @[el2_lsu_bus_buffer.scala 321:61] + wire _T_1091 = ibuf_buf_byp & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 336:32] + wire _T_4778 = buf_state_0 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4780 = _T_4778 & buf_sideeffect[0]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4781 = _T_4780 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4782 = buf_state_1 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4784 = _T_4782 & buf_sideeffect[1]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4785 = _T_4784 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4794 = _T_4781 | _T_4785; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4786 = buf_state_2 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4788 = _T_4786 & buf_sideeffect[2]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4789 = _T_4788 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire _T_4795 = _T_4794 | _T_4789; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_4790 = buf_state_3 == 3'h3; // @[el2_lsu_bus_buffer.scala 605:62] + wire _T_4792 = _T_4790 & buf_sideeffect[3]; // @[el2_lsu_bus_buffer.scala 605:73] + wire _T_4793 = _T_4792 & io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_buffer.scala 605:93] + wire bus_sideeffect_pend = _T_4795 | _T_4793; // @[el2_lsu_bus_buffer.scala 605:141] + wire _T_1092 = io_is_sideeffects_r & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 336:74] + wire _T_1093 = ~_T_1092; // @[el2_lsu_bus_buffer.scala 336:52] + wire _T_1094 = _T_1091 & _T_1093; // @[el2_lsu_bus_buffer.scala 336:50] + wire [2:0] _T_1099 = _T_1023 ? buf_state_0 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1100 = _T_1024 ? buf_state_1 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1103 = _T_1099 | _T_1100; // @[Mux.scala 27:72] + wire [2:0] _T_1101 = _T_1025 ? buf_state_2 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1104 = _T_1103 | _T_1101; // @[Mux.scala 27:72] + wire [2:0] _T_1102 = _T_1026 ? buf_state_3 : 3'h0; // @[Mux.scala 27:72] + wire [2:0] _T_1105 = _T_1104 | _T_1102; // @[Mux.scala 27:72] + wire _T_1107 = _T_1105 == 3'h2; // @[el2_lsu_bus_buffer.scala 337:36] + wire found_cmdptr0 = |CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 436:31] + wire _T_1108 = _T_1107 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 337:47] + wire [3:0] _T_1111 = {buf_cmd_state_bus_en_3,buf_cmd_state_bus_en_2,buf_cmd_state_bus_en_1,buf_cmd_state_bus_en_0}; // @[Cat.scala 29:58] + wire _T_1120 = _T_1023 & _T_1111[0]; // @[Mux.scala 27:72] + wire _T_1121 = _T_1024 & _T_1111[1]; // @[Mux.scala 27:72] + wire _T_1124 = _T_1120 | _T_1121; // @[Mux.scala 27:72] + wire _T_1122 = _T_1025 & _T_1111[2]; // @[Mux.scala 27:72] + wire _T_1125 = _T_1124 | _T_1122; // @[Mux.scala 27:72] + wire _T_1123 = _T_1026 & _T_1111[3]; // @[Mux.scala 27:72] + wire _T_1126 = _T_1125 | _T_1123; // @[Mux.scala 27:72] + wire _T_1128 = ~_T_1126; // @[el2_lsu_bus_buffer.scala 338:23] + wire _T_1129 = _T_1108 & _T_1128; // @[el2_lsu_bus_buffer.scala 338:21] + wire _T_1146 = _T_1051 & bus_sideeffect_pend; // @[el2_lsu_bus_buffer.scala 338:141] + wire _T_1147 = ~_T_1146; // @[el2_lsu_bus_buffer.scala 338:105] + wire _T_1148 = _T_1129 & _T_1147; // @[el2_lsu_bus_buffer.scala 338:103] reg buf_dual_3; // @[Reg.scala 27:20] - wire _GEN_35 = 2'h3 == CmdPtr0 ? buf_dual_3 : _GEN_34; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_samedw_0; // @[Reg.scala 27:20] - reg buf_samedw_1; // @[Reg.scala 27:20] - wire _GEN_37 = 2'h1 == CmdPtr0 ? buf_samedw_1 : buf_samedw_0; // @[el2_lsu_bus_buffer.scala 489:58] - reg buf_samedw_2; // @[Reg.scala 27:20] - wire _GEN_38 = 2'h2 == CmdPtr0 ? buf_samedw_2 : _GEN_37; // @[el2_lsu_bus_buffer.scala 489:58] + reg buf_dual_2; // @[Reg.scala 27:20] + reg buf_dual_1; // @[Reg.scala 27:20] + reg buf_dual_0; // @[Reg.scala 27:20] + wire [3:0] _T_1151 = {buf_dual_3,buf_dual_2,buf_dual_1,buf_dual_0}; // @[Cat.scala 29:58] + wire _T_1160 = _T_1023 & _T_1151[0]; // @[Mux.scala 27:72] + wire _T_1161 = _T_1024 & _T_1151[1]; // @[Mux.scala 27:72] + wire _T_1164 = _T_1160 | _T_1161; // @[Mux.scala 27:72] + wire _T_1162 = _T_1025 & _T_1151[2]; // @[Mux.scala 27:72] + wire _T_1165 = _T_1164 | _T_1162; // @[Mux.scala 27:72] + wire _T_1163 = _T_1026 & _T_1151[3]; // @[Mux.scala 27:72] + wire _T_1166 = _T_1165 | _T_1163; // @[Mux.scala 27:72] reg buf_samedw_3; // @[Reg.scala 27:20] - wire _GEN_39 = 2'h3 == CmdPtr0 ? buf_samedw_3 : _GEN_38; // @[el2_lsu_bus_buffer.scala 489:58] - wire _T_1137 = _GEN_35 & _GEN_39; // @[el2_lsu_bus_buffer.scala 489:58] - wire _GEN_41 = 2'h1 == CmdPtr0 ? buf_write_1 : buf_write_0; // @[el2_lsu_bus_buffer.scala 489:82] - wire _GEN_42 = 2'h2 == CmdPtr0 ? buf_write_2 : _GEN_41; // @[el2_lsu_bus_buffer.scala 489:82] - wire _GEN_43 = 2'h3 == CmdPtr0 ? buf_write_3 : _GEN_42; // @[el2_lsu_bus_buffer.scala 489:82] - wire _T_1138 = ~_GEN_43; // @[el2_lsu_bus_buffer.scala 489:82] - wire _T_1139 = _T_1137 & _T_1138; // @[el2_lsu_bus_buffer.scala 489:80] - wire _T_1140 = ~_T_1139; // @[el2_lsu_bus_buffer.scala 489:38] - wire [3:0] _T_1834 = ~_T_3056; // @[el2_lsu_bus_buffer.scala 559:55] - wire [3:0] _T_1835 = _T_1821 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_1836 = |_T_1835; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_1837 = ~_T_1836; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_1838 = ~CmdPtr0Dec_0; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_1839 = _T_1837 & _T_1838; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_1841 = _T_1839 & _T_2730; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_0 = _T_1841 & _T_3984; // @[el2_lsu_bus_buffer.scala 559:126] - wire [3:0] _T_2215 = _T_2201 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2216 = |_T_2215; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2217 = ~_T_2216; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2218 = ~CmdPtr0Dec_1; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2219 = _T_2217 & _T_2218; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2221 = _T_2219 & _T_2825; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_1 = _T_2221 & _T_3989; // @[el2_lsu_bus_buffer.scala 559:126] - wire _T_3090 = CmdPtr1Dec_0 | CmdPtr1Dec_1; // @[el2_lsu_bus_buffer.scala 582:49] - wire [3:0] _T_2595 = _T_2581 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2596 = |_T_2595; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2597 = ~_T_2596; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2598 = ~CmdPtr0Dec_2; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2599 = _T_2597 & _T_2598; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2601 = _T_2599 & _T_2920; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_2 = _T_2601 & _T_3994; // @[el2_lsu_bus_buffer.scala 559:126] - wire _T_3091 = _T_3090 | CmdPtr1Dec_2; // @[el2_lsu_bus_buffer.scala 582:49] - wire [3:0] _T_2975 = _T_2961 & _T_1834; // @[el2_lsu_bus_buffer.scala 559:53] - wire _T_2976 = |_T_2975; // @[el2_lsu_bus_buffer.scala 559:78] - wire _T_2977 = ~_T_2976; // @[el2_lsu_bus_buffer.scala 559:32] - wire _T_2978 = ~CmdPtr0Dec_3; // @[el2_lsu_bus_buffer.scala 559:84] - wire _T_2979 = _T_2977 & _T_2978; // @[el2_lsu_bus_buffer.scala 559:82] - wire _T_2981 = _T_2979 & _T_3015; // @[el2_lsu_bus_buffer.scala 559:99] - wire CmdPtr1Dec_3 = _T_2981 & _T_3999; // @[el2_lsu_bus_buffer.scala 559:126] - wire found_cmdptr1 = _T_3091 | CmdPtr1Dec_3; // @[el2_lsu_bus_buffer.scala 582:49] - wire _T_1141 = _T_1140 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 489:103] - wire _T_1142 = _T_1141 | _GEN_19; // @[el2_lsu_bus_buffer.scala 489:119] - wire _T_1143 = _T_1142 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 489:142] - wire _T_1144 = _T_1136 & _T_1143; // @[el2_lsu_bus_buffer.scala 488:165] - wire _T_1145 = _T_1129 | _T_1144; // @[el2_lsu_bus_buffer.scala 487:110] - wire _T_1146 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 490:57] + reg buf_samedw_2; // @[Reg.scala 27:20] + reg buf_samedw_1; // @[Reg.scala 27:20] + reg buf_samedw_0; // @[Reg.scala 27:20] + wire [3:0] _T_1170 = {buf_samedw_3,buf_samedw_2,buf_samedw_1,buf_samedw_0}; // @[Cat.scala 29:58] + wire _T_1179 = _T_1023 & _T_1170[0]; // @[Mux.scala 27:72] + wire _T_1180 = _T_1024 & _T_1170[1]; // @[Mux.scala 27:72] + wire _T_1183 = _T_1179 | _T_1180; // @[Mux.scala 27:72] + wire _T_1181 = _T_1025 & _T_1170[2]; // @[Mux.scala 27:72] + wire _T_1184 = _T_1183 | _T_1181; // @[Mux.scala 27:72] + wire _T_1182 = _T_1026 & _T_1170[3]; // @[Mux.scala 27:72] + wire _T_1185 = _T_1184 | _T_1182; // @[Mux.scala 27:72] + wire _T_1187 = _T_1166 & _T_1185; // @[el2_lsu_bus_buffer.scala 339:77] + wire _T_1196 = _T_1023 & buf_write[0]; // @[Mux.scala 27:72] + wire _T_1197 = _T_1024 & buf_write[1]; // @[Mux.scala 27:72] + wire _T_1200 = _T_1196 | _T_1197; // @[Mux.scala 27:72] + wire _T_1198 = _T_1025 & buf_write[2]; // @[Mux.scala 27:72] + wire _T_1201 = _T_1200 | _T_1198; // @[Mux.scala 27:72] + wire _T_1199 = _T_1026 & buf_write[3]; // @[Mux.scala 27:72] + wire _T_1202 = _T_1201 | _T_1199; // @[Mux.scala 27:72] + wire _T_1204 = ~_T_1202; // @[el2_lsu_bus_buffer.scala 339:150] + wire _T_1205 = _T_1187 & _T_1204; // @[el2_lsu_bus_buffer.scala 339:148] + wire _T_1206 = ~_T_1205; // @[el2_lsu_bus_buffer.scala 339:8] + wire [3:0] _T_2020 = ~CmdPtr0Dec; // @[el2_lsu_bus_buffer.scala 432:62] + wire [3:0] _T_2021 = buf_age_3 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2022 = |_T_2021; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2023 = ~_T_2022; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2025 = ~CmdPtr0Dec[3]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2026 = _T_2023 & _T_2025; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2028 = _T_2026 & _T_2621; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2030 = _T_2028 & _T_4447; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_2010 = buf_age_2 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2011 = |_T_2010; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2012 = ~_T_2011; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2014 = ~CmdPtr0Dec[2]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2015 = _T_2012 & _T_2014; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2017 = _T_2015 & _T_2616; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2019 = _T_2017 & _T_4442; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1999 = buf_age_1 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_2000 = |_T_1999; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_2001 = ~_T_2000; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_2003 = ~CmdPtr0Dec[1]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_2004 = _T_2001 & _T_2003; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_2006 = _T_2004 & _T_2611; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_2008 = _T_2006 & _T_4437; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] _T_1988 = buf_age_0 & _T_2020; // @[el2_lsu_bus_buffer.scala 432:59] + wire _T_1989 = |_T_1988; // @[el2_lsu_bus_buffer.scala 432:76] + wire _T_1990 = ~_T_1989; // @[el2_lsu_bus_buffer.scala 432:45] + wire _T_1992 = ~CmdPtr0Dec[0]; // @[el2_lsu_bus_buffer.scala 432:83] + wire _T_1993 = _T_1990 & _T_1992; // @[el2_lsu_bus_buffer.scala 432:81] + wire _T_1995 = _T_1993 & _T_2606; // @[el2_lsu_bus_buffer.scala 432:98] + wire _T_1997 = _T_1995 & _T_4432; // @[el2_lsu_bus_buffer.scala 432:123] + wire [3:0] CmdPtr1Dec = {_T_2030,_T_2019,_T_2008,_T_1997}; // @[Cat.scala 29:58] + wire found_cmdptr1 = |CmdPtr1Dec; // @[el2_lsu_bus_buffer.scala 437:31] + wire _T_1207 = _T_1206 | found_cmdptr1; // @[el2_lsu_bus_buffer.scala 339:181] + wire [3:0] _T_1210 = {buf_nomerge_3,buf_nomerge_2,buf_nomerge_1,buf_nomerge_0}; // @[Cat.scala 29:58] + wire _T_1219 = _T_1023 & _T_1210[0]; // @[Mux.scala 27:72] + wire _T_1220 = _T_1024 & _T_1210[1]; // @[Mux.scala 27:72] + wire _T_1223 = _T_1219 | _T_1220; // @[Mux.scala 27:72] + wire _T_1221 = _T_1025 & _T_1210[2]; // @[Mux.scala 27:72] + wire _T_1224 = _T_1223 | _T_1221; // @[Mux.scala 27:72] + wire _T_1222 = _T_1026 & _T_1210[3]; // @[Mux.scala 27:72] + wire _T_1225 = _T_1224 | _T_1222; // @[Mux.scala 27:72] + wire _T_1227 = _T_1207 | _T_1225; // @[el2_lsu_bus_buffer.scala 339:197] + wire _T_1228 = _T_1227 | obuf_force_wr_en; // @[el2_lsu_bus_buffer.scala 339:269] + wire _T_1229 = _T_1148 & _T_1228; // @[el2_lsu_bus_buffer.scala 338:164] + wire _T_1230 = _T_1094 | _T_1229; // @[el2_lsu_bus_buffer.scala 336:98] reg obuf_write; // @[Reg.scala 27:20] - reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 525:35] - reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 526:35] - wire _T_4309 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 734:66] - wire _T_4310 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 734:88] - wire _T_4311 = io_lsu_axi_awready & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 734:164] - wire _T_4312 = _T_4309 ? _T_4310 : _T_4311; // @[el2_lsu_bus_buffer.scala 734:50] - wire bus_cmd_ready = obuf_write ? _T_4312 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 734:34] - wire _T_1147 = bus_cmd_ready | _T_1146; // @[el2_lsu_bus_buffer.scala 490:55] + reg obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 401:54] + reg obuf_data_done; // @[el2_lsu_bus_buffer.scala 402:55] + wire _T_4853 = obuf_cmd_done | obuf_data_done; // @[el2_lsu_bus_buffer.scala 609:54] + wire _T_4854 = obuf_cmd_done ? io_lsu_axi_wready : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:75] + wire _T_4856 = _T_4853 ? _T_4854 : io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 609:39] + wire bus_cmd_ready = obuf_write ? _T_4856 : io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 609:23] + wire _T_1231 = ~obuf_valid; // @[el2_lsu_bus_buffer.scala 340:48] + wire _T_1232 = bus_cmd_ready | _T_1231; // @[el2_lsu_bus_buffer.scala 340:46] reg obuf_nosend; // @[Reg.scala 27:20] - wire _T_1148 = _T_1147 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 490:69] - wire _T_1149 = _T_1145 & _T_1148; // @[el2_lsu_bus_buffer.scala 489:164] - wire _T_1150 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 490:86] - wire _T_1151 = _T_1149 & _T_1150; // @[el2_lsu_bus_buffer.scala 490:84] - reg [63:0] _T_1397; // @[Reg.scala 27:20] - wire [31:0] obuf_addr = _T_1397[31:0]; // @[el2_lsu_bus_buffer.scala 520:25] - wire _T_4252 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4253 = obuf_valid & _T_4252; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4260 = ~_T_3169; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4261 = _T_4232 & _T_4260; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4301 = _T_4253 & _T_4261; // @[Mux.scala 27:72] - wire _T_4265 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4266 = obuf_valid & _T_4265; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4273 = ~_T_3377; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4274 = _T_4234 & _T_4273; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4302 = _T_4266 & _T_4274; // @[Mux.scala 27:72] - wire _T_4305 = _T_4301 | _T_4302; // @[Mux.scala 27:72] - wire _T_4278 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4279 = obuf_valid & _T_4278; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4286 = ~_T_3585; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4287 = _T_4236 & _T_4286; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4303 = _T_4279 & _T_4287; // @[Mux.scala 27:72] - wire _T_4306 = _T_4305 | _T_4303; // @[Mux.scala 27:72] - wire _T_4291 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 732:114] - wire _T_4292 = obuf_valid & _T_4291; // @[el2_lsu_bus_buffer.scala 732:95] - wire _T_4299 = ~_T_3793; // @[el2_lsu_bus_buffer.scala 732:177] - wire _T_4300 = _T_4238 & _T_4299; // @[el2_lsu_bus_buffer.scala 732:175] - wire _T_4304 = _T_4292 & _T_4300; // @[Mux.scala 27:72] - wire bus_addr_match_pending = _T_4306 | _T_4304; // @[Mux.scala 27:72] - wire _T_1154 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 490:127] - wire _T_1155 = _T_1151 & _T_1154; // @[el2_lsu_bus_buffer.scala 490:125] - wire obuf_wr_en = _T_1155 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 490:151] - wire _T_1157 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 491:58] - wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 735:50] - wire _T_4316 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 737:47] - wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 736:49] - wire _T_4317 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 737:82] - wire _T_4318 = _T_4316 & _T_4317; // @[el2_lsu_bus_buffer.scala 737:64] - wire _T_4319 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 737:123] - wire bus_cmd_sent = _T_4318 | _T_4319; // @[el2_lsu_bus_buffer.scala 737:101] - wire _T_1158 = bus_cmd_sent | _T_1157; // @[el2_lsu_bus_buffer.scala 491:44] - wire _T_1159 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 491:76] - wire _T_1160 = _T_1158 & _T_1159; // @[el2_lsu_bus_buffer.scala 491:74] - wire _T_1161 = _T_1160 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 491:88] - wire obuf_rst = _T_1161 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 491:109] - wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _GEN_43; // @[el2_lsu_bus_buffer.scala 492:32] - wire [31:0] _T_1212 = ibuf_buf_byp ? io_lsu_addr_r : _GEN_15; // @[el2_lsu_bus_buffer.scala 498:32] - wire [63:0] obuf_addr_in = {{32'd0}, _T_1212}; // @[el2_lsu_bus_buffer.scala 498:26] - wire _T_1166 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 493:49] - reg [1:0] buf_sz_3; // @[Reg.scala 27:20] - reg [1:0] buf_sz_2; // @[Reg.scala 27:20] - reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire _T_1233 = _T_1232 | obuf_nosend; // @[el2_lsu_bus_buffer.scala 340:60] + wire _T_1234 = _T_1230 & _T_1233; // @[el2_lsu_bus_buffer.scala 340:29] + wire _T_1235 = ~obuf_wr_wait; // @[el2_lsu_bus_buffer.scala 340:77] + wire _T_1236 = _T_1234 & _T_1235; // @[el2_lsu_bus_buffer.scala 340:75] + reg [31:0] obuf_addr; // @[el2_lib.scala 514:16] + wire _T_4801 = obuf_addr[31:3] == buf_addr_0[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4802 = obuf_valid & _T_4801; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4804 = obuf_tag1 == 2'h0; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4805 = obuf_merge & _T_4804; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4806 = _T_3562 | _T_4805; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4807 = ~_T_4806; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4808 = _T_4802 & _T_4807; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4845 = _T_4778 & _T_4808; // @[Mux.scala 27:72] + wire _T_4813 = obuf_addr[31:3] == buf_addr_1[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4814 = obuf_valid & _T_4813; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4816 = obuf_tag1 == 2'h1; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4817 = obuf_merge & _T_4816; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4818 = _T_3755 | _T_4817; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4819 = ~_T_4818; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4820 = _T_4814 & _T_4819; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4846 = _T_4782 & _T_4820; // @[Mux.scala 27:72] + wire _T_4849 = _T_4845 | _T_4846; // @[Mux.scala 27:72] + wire _T_4825 = obuf_addr[31:3] == buf_addr_2[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4826 = obuf_valid & _T_4825; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4828 = obuf_tag1 == 2'h2; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4829 = obuf_merge & _T_4828; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4830 = _T_3948 | _T_4829; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4831 = ~_T_4830; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4832 = _T_4826 & _T_4831; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4847 = _T_4786 & _T_4832; // @[Mux.scala 27:72] + wire _T_4850 = _T_4849 | _T_4847; // @[Mux.scala 27:72] + wire _T_4837 = obuf_addr[31:3] == buf_addr_3[31:3]; // @[el2_lsu_bus_buffer.scala 607:56] + wire _T_4838 = obuf_valid & _T_4837; // @[el2_lsu_bus_buffer.scala 607:38] + wire _T_4840 = obuf_tag1 == 2'h3; // @[el2_lsu_bus_buffer.scala 607:126] + wire _T_4841 = obuf_merge & _T_4840; // @[el2_lsu_bus_buffer.scala 607:114] + wire _T_4842 = _T_4141 | _T_4841; // @[el2_lsu_bus_buffer.scala 607:100] + wire _T_4843 = ~_T_4842; // @[el2_lsu_bus_buffer.scala 607:80] + wire _T_4844 = _T_4838 & _T_4843; // @[el2_lsu_bus_buffer.scala 607:78] + wire _T_4848 = _T_4790 & _T_4844; // @[Mux.scala 27:72] + wire bus_addr_match_pending = _T_4850 | _T_4848; // @[Mux.scala 27:72] + wire _T_1239 = ~bus_addr_match_pending; // @[el2_lsu_bus_buffer.scala 340:118] + wire _T_1240 = _T_1236 & _T_1239; // @[el2_lsu_bus_buffer.scala 340:116] + wire obuf_wr_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 340:142] + wire _T_1242 = obuf_valid & obuf_nosend; // @[el2_lsu_bus_buffer.scala 342:47] + wire bus_wcmd_sent = io_lsu_axi_awvalid & io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 610:39] + wire _T_4860 = obuf_cmd_done | bus_wcmd_sent; // @[el2_lsu_bus_buffer.scala 612:35] + wire bus_wdata_sent = io_lsu_axi_wvalid & io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 611:39] + wire _T_4861 = obuf_data_done | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 612:70] + wire _T_4862 = _T_4860 & _T_4861; // @[el2_lsu_bus_buffer.scala 612:52] + wire _T_4863 = io_lsu_axi_arvalid & io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 612:111] + wire bus_cmd_sent = _T_4862 | _T_4863; // @[el2_lsu_bus_buffer.scala 612:89] + wire _T_1243 = bus_cmd_sent | _T_1242; // @[el2_lsu_bus_buffer.scala 342:33] + wire _T_1244 = ~obuf_wr_en; // @[el2_lsu_bus_buffer.scala 342:65] + wire _T_1245 = _T_1243 & _T_1244; // @[el2_lsu_bus_buffer.scala 342:63] + wire _T_1246 = _T_1245 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 342:77] + wire obuf_rst = _T_1246 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 342:98] + wire obuf_write_in = ibuf_buf_byp ? io_lsu_pkt_r_store : _T_1202; // @[el2_lsu_bus_buffer.scala 343:26] + wire [31:0] _T_1283 = _T_1023 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1284 = _T_1024 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1285 = _T_1025 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1286 = _T_1026 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1287 = _T_1283 | _T_1284; // @[Mux.scala 27:72] + wire [31:0] _T_1288 = _T_1287 | _T_1285; // @[Mux.scala 27:72] + wire [31:0] _T_1289 = _T_1288 | _T_1286; // @[Mux.scala 27:72] + wire [31:0] obuf_addr_in = ibuf_buf_byp ? io_lsu_addr_r : _T_1289; // @[el2_lsu_bus_buffer.scala 345:25] reg [1:0] buf_sz_0; // @[Reg.scala 27:20] - wire [1:0] _GEN_45 = 2'h1 == CmdPtr0 ? buf_sz_1 : buf_sz_0; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] _GEN_46 = 2'h2 == CmdPtr0 ? buf_sz_2 : _GEN_45; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] _GEN_47 = 2'h3 == CmdPtr0 ? buf_sz_3 : _GEN_46; // @[el2_lsu_bus_buffer.scala 500:32] - wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _GEN_47; // @[el2_lsu_bus_buffer.scala 500:32] - wire _T_1199 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 497:78] - wire _T_1202 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 497:110] - wire _T_1203 = obuf_sz_in[0] & _T_1202; // @[el2_lsu_bus_buffer.scala 497:108] - wire _T_1204 = _T_1199 | _T_1203; // @[el2_lsu_bus_buffer.scala 497:91] - wire _T_1207 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 497:167] - wire _T_1208 = ~_T_1207; // @[el2_lsu_bus_buffer.scala 497:147] - wire _T_1209 = obuf_sz_in[1] & _T_1208; // @[el2_lsu_bus_buffer.scala 497:145] - wire _T_1210 = _T_1204 | _T_1209; // @[el2_lsu_bus_buffer.scala 497:128] - wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1210; // @[el2_lsu_bus_buffer.scala 497:32] - wire _T_1167 = _T_1166 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 493:70] - wire _T_1168 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 493:90] - wire _T_1169 = _T_1167 & _T_1168; // @[el2_lsu_bus_buffer.scala 493:88] - wire _T_1170 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 493:109] - wire _T_1171 = _T_1169 & _T_1170; // @[el2_lsu_bus_buffer.scala 493:107] - wire _T_1172 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 493:123] - wire _T_1173 = _T_1171 & _T_1172; // @[el2_lsu_bus_buffer.scala 493:121] - wire _T_1174 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 493:140] - wire _T_1175 = _T_1173 & _T_1174; // @[el2_lsu_bus_buffer.scala 493:138] - wire _T_1176 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 494:48] - wire _T_1177 = obuf_valid & _T_1176; // @[el2_lsu_bus_buffer.scala 494:46] - reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 524:35] - wire _T_1178 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 494:118] - wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 739:49] - wire _T_1179 = bus_rsp_read & _T_1178; // @[el2_lsu_bus_buffer.scala 494:98] - wire _T_1180 = ~_T_1179; // @[el2_lsu_bus_buffer.scala 494:83] - reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 523:35] - wire _T_1181 = obuf_rdrsp_pend & _T_1180; // @[el2_lsu_bus_buffer.scala 494:81] - wire _T_1182 = _T_1177 | _T_1181; // @[el2_lsu_bus_buffer.scala 494:62] - wire obuf_nosend_in = _T_1175 & _T_1182; // @[el2_lsu_bus_buffer.scala 493:175] - wire _T_1184 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 495:45] - wire _T_1185 = obuf_wr_en & _T_1184; // @[el2_lsu_bus_buffer.scala 495:43] - wire _T_1186 = ~_T_1185; // @[el2_lsu_bus_buffer.scala 495:30] - wire _T_1187 = _T_1186 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 495:62] - wire _T_1191 = _T_1187 & _T_1180; // @[el2_lsu_bus_buffer.scala 495:80] - wire _T_1193 = bus_cmd_sent & _T_1170; // @[el2_lsu_bus_buffer.scala 495:156] - wire _T_1194 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 495:173] - wire _T_1195 = _T_1193 & _T_1194; // @[el2_lsu_bus_buffer.scala 495:171] - wire [7:0] _T_1366 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1368 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1369 = io_end_addr_r[2] ? _T_1366 : _T_1368; // @[el2_lsu_bus_buffer.scala 516:49] - wire [3:0] _T_3067 = {CmdPtr1Dec_3,CmdPtr1Dec_2,CmdPtr1Dec_1,CmdPtr1Dec_0}; // @[el2_lsu_bus_buffer.scala 579:59] - wire [3:0] _T_3072 = _T_3067[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3073 = _T_3067[2] ? 4'h4 : _T_3072; // @[Mux.scala 47:69] - wire [3:0] _T_3074 = _T_3067[1] ? 4'h2 : _T_3073; // @[Mux.scala 47:69] - wire [3:0] _T_3075 = _T_3067[0] ? 4'h1 : _T_3074; // @[Mux.scala 47:69] - wire [1:0] CmdPtr1 = _T_3075[1:0]; // @[el2_lsu_bus_buffer.scala 579:27] - wire [31:0] _GEN_57 = 2'h1 == CmdPtr1 ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 511:124] - wire [31:0] _GEN_58 = 2'h2 == CmdPtr1 ? buf_addr_2 : _GEN_57; // @[el2_lsu_bus_buffer.scala 511:124] - wire [31:0] _GEN_59 = 2'h3 == CmdPtr1 ? buf_addr_3 : _GEN_58; // @[el2_lsu_bus_buffer.scala 511:124] - wire [3:0] _GEN_69 = 2'h1 == CmdPtr1 ? buf_byteen_1 : buf_byteen_0; // @[Cat.scala 29:58] - wire [3:0] _GEN_70 = 2'h2 == CmdPtr1 ? buf_byteen_2 : _GEN_69; // @[Cat.scala 29:58] - wire [3:0] _GEN_71 = 2'h3 == CmdPtr1 ? buf_byteen_3 : _GEN_70; // @[Cat.scala 29:58] - wire [7:0] _T_1371 = {_GEN_71,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1372 = {4'h0,_GEN_71}; // @[Cat.scala 29:58] - wire [7:0] _T_1373 = _GEN_59[2] ? _T_1371 : _T_1372; // @[el2_lsu_bus_buffer.scala 516:150] - wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1369 : _T_1373; // @[el2_lsu_bus_buffer.scala 516:31] - wire _T_1316 = CmdPtr0 != CmdPtr1; // @[el2_lsu_bus_buffer.scala 509:39] - wire _T_1317 = _T_1316 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 509:52] - wire _T_1318 = _T_1317 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 509:68] - wire _T_1320 = _T_1318 & _T_1130; // @[el2_lsu_bus_buffer.scala 509:84] - wire [2:0] _GEN_49 = 2'h1 == CmdPtr1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 509:139] - wire [2:0] _GEN_50 = 2'h2 == CmdPtr1 ? buf_state_2 : _GEN_49; // @[el2_lsu_bus_buffer.scala 509:139] - wire [2:0] _GEN_51 = 2'h3 == CmdPtr1 ? buf_state_3 : _GEN_50; // @[el2_lsu_bus_buffer.scala 509:139] - wire _T_1321 = _GEN_51 == 3'h2; // @[el2_lsu_bus_buffer.scala 509:139] - wire _T_1322 = _T_1320 & _T_1321; // @[el2_lsu_bus_buffer.scala 509:117] - wire _T_1324 = _T_1322 & _T_1132; // @[el2_lsu_bus_buffer.scala 509:150] - wire _T_1326 = _T_1324 & _T_1122; // @[el2_lsu_bus_buffer.scala 510:62] - wire _T_1337 = _T_1138 & _GEN_35; // @[el2_lsu_bus_buffer.scala 512:58] + wire [1:0] _T_1296 = _T_1023 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_1; // @[Reg.scala 27:20] + wire [1:0] _T_1297 = _T_1024 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_2; // @[Reg.scala 27:20] + wire [1:0] _T_1298 = _T_1025 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + reg [1:0] buf_sz_3; // @[Reg.scala 27:20] + wire [1:0] _T_1299 = _T_1026 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_1300 = _T_1296 | _T_1297; // @[Mux.scala 27:72] + wire [1:0] _T_1301 = _T_1300 | _T_1298; // @[Mux.scala 27:72] + wire [1:0] _T_1302 = _T_1301 | _T_1299; // @[Mux.scala 27:72] + wire [1:0] obuf_sz_in = ibuf_buf_byp ? ibuf_sz_in : _T_1302; // @[el2_lsu_bus_buffer.scala 348:23] + wire _T_1304 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 357:39] + wire _T_1305 = ~_T_1304; // @[el2_lsu_bus_buffer.scala 357:26] + wire _T_1311 = obuf_sz_in == 2'h0; // @[el2_lsu_bus_buffer.scala 361:72] + wire _T_1314 = ~obuf_addr_in[0]; // @[el2_lsu_bus_buffer.scala 361:98] + wire _T_1315 = obuf_sz_in[0] & _T_1314; // @[el2_lsu_bus_buffer.scala 361:96] + wire _T_1316 = _T_1311 | _T_1315; // @[el2_lsu_bus_buffer.scala 361:79] + wire _T_1319 = |obuf_addr_in[1:0]; // @[el2_lsu_bus_buffer.scala 361:153] + wire _T_1320 = ~_T_1319; // @[el2_lsu_bus_buffer.scala 361:134] + wire _T_1321 = obuf_sz_in[1] & _T_1320; // @[el2_lsu_bus_buffer.scala 361:132] + wire _T_1322 = _T_1316 | _T_1321; // @[el2_lsu_bus_buffer.scala 361:116] + wire obuf_aligned_in = ibuf_buf_byp ? is_aligned_r : _T_1322; // @[el2_lsu_bus_buffer.scala 361:28] + wire _T_1339 = obuf_addr_in[31:3] == obuf_addr[31:3]; // @[el2_lsu_bus_buffer.scala 375:40] + wire _T_1340 = _T_1339 & obuf_aligned_in; // @[el2_lsu_bus_buffer.scala 375:60] + reg obuf_sideeffect; // @[Reg.scala 27:20] + wire _T_1341 = ~obuf_sideeffect; // @[el2_lsu_bus_buffer.scala 375:80] + wire _T_1342 = _T_1340 & _T_1341; // @[el2_lsu_bus_buffer.scala 375:78] + wire _T_1343 = ~obuf_write; // @[el2_lsu_bus_buffer.scala 375:99] + wire _T_1344 = _T_1342 & _T_1343; // @[el2_lsu_bus_buffer.scala 375:97] + wire _T_1345 = ~obuf_write_in; // @[el2_lsu_bus_buffer.scala 375:113] + wire _T_1346 = _T_1344 & _T_1345; // @[el2_lsu_bus_buffer.scala 375:111] + wire _T_1347 = ~io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_buffer.scala 375:130] + wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 375:128] + wire _T_1349 = ~obuf_nosend; // @[el2_lsu_bus_buffer.scala 376:20] + wire _T_1350 = obuf_valid & _T_1349; // @[el2_lsu_bus_buffer.scala 376:18] + reg obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 403:56] + wire bus_rsp_read = io_lsu_axi_rvalid & io_lsu_axi_rready; // @[el2_lsu_bus_buffer.scala 613:37] + reg [2:0] obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 404:55] + wire _T_1351 = io_lsu_axi_rid == obuf_rdrsp_tag; // @[el2_lsu_bus_buffer.scala 376:90] + wire _T_1352 = bus_rsp_read & _T_1351; // @[el2_lsu_bus_buffer.scala 376:70] + wire _T_1353 = ~_T_1352; // @[el2_lsu_bus_buffer.scala 376:55] + wire _T_1354 = obuf_rdrsp_pend & _T_1353; // @[el2_lsu_bus_buffer.scala 376:53] + wire _T_1355 = _T_1350 | _T_1354; // @[el2_lsu_bus_buffer.scala 376:34] + wire obuf_nosend_in = _T_1348 & _T_1355; // @[el2_lsu_bus_buffer.scala 375:165] + wire _T_1323 = ~obuf_nosend_in; // @[el2_lsu_bus_buffer.scala 369:44] + wire _T_1324 = obuf_wr_en & _T_1323; // @[el2_lsu_bus_buffer.scala 369:42] + wire _T_1325 = ~_T_1324; // @[el2_lsu_bus_buffer.scala 369:29] + wire _T_1326 = _T_1325 & obuf_rdrsp_pend; // @[el2_lsu_bus_buffer.scala 369:61] + wire _T_1330 = _T_1326 & _T_1353; // @[el2_lsu_bus_buffer.scala 369:79] + wire _T_1332 = bus_cmd_sent & _T_1343; // @[el2_lsu_bus_buffer.scala 370:20] + wire _T_1333 = ~io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 370:37] + wire _T_1334 = _T_1332 & _T_1333; // @[el2_lsu_bus_buffer.scala 370:35] + wire [7:0] _T_1358 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1359 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1360 = io_lsu_addr_r[2] ? _T_1358 : _T_1359; // @[el2_lsu_bus_buffer.scala 377:46] + wire [3:0] _T_1379 = _T_1023 ? buf_byteen_0 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1380 = _T_1024 ? buf_byteen_1 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1381 = _T_1025 ? buf_byteen_2 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1382 = _T_1026 ? buf_byteen_3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_1383 = _T_1379 | _T_1380; // @[Mux.scala 27:72] + wire [3:0] _T_1384 = _T_1383 | _T_1381; // @[Mux.scala 27:72] + wire [3:0] _T_1385 = _T_1384 | _T_1382; // @[Mux.scala 27:72] + wire [7:0] _T_1387 = {_T_1385,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1400 = {4'h0,_T_1385}; // @[Cat.scala 29:58] + wire [7:0] _T_1401 = _T_1289[2] ? _T_1387 : _T_1400; // @[el2_lsu_bus_buffer.scala 378:8] + wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1360 : _T_1401; // @[el2_lsu_bus_buffer.scala 377:28] + wire [7:0] _T_1403 = {ldst_byteen_hi_r,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1404 = {4'h0,ldst_byteen_hi_r}; // @[Cat.scala 29:58] + wire [7:0] _T_1405 = io_end_addr_r[2] ? _T_1403 : _T_1404; // @[el2_lsu_bus_buffer.scala 379:46] + wire [7:0] _T_1432 = {buf_byteen_0,4'h0}; // @[Cat.scala 29:58] + wire [7:0] _T_1445 = {4'h0,buf_byteen_0}; // @[Cat.scala 29:58] + wire [7:0] _T_1446 = buf_addr_0[2] ? _T_1432 : _T_1445; // @[el2_lsu_bus_buffer.scala 380:8] + wire [7:0] obuf_byteen1_in = ibuf_buf_byp ? _T_1405 : _T_1446; // @[el2_lsu_bus_buffer.scala 379:28] + wire [63:0] _T_1448 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1449 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1450 = io_lsu_addr_r[2] ? _T_1448 : _T_1449; // @[el2_lsu_bus_buffer.scala 382:44] + wire [31:0] _T_1469 = _T_1023 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1470 = _T_1024 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1471 = _T_1025 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1472 = _T_1026 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1473 = _T_1469 | _T_1470; // @[Mux.scala 27:72] + wire [31:0] _T_1474 = _T_1473 | _T_1471; // @[Mux.scala 27:72] + wire [31:0] _T_1475 = _T_1474 | _T_1472; // @[Mux.scala 27:72] + wire [63:0] _T_1477 = {_T_1475,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1490 = {32'h0,_T_1475}; // @[Cat.scala 29:58] + wire [63:0] _T_1491 = _T_1289[2] ? _T_1477 : _T_1490; // @[el2_lsu_bus_buffer.scala 383:8] + wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1450 : _T_1491; // @[el2_lsu_bus_buffer.scala 382:26] + wire [63:0] _T_1493 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1494 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] + wire [63:0] _T_1495 = io_lsu_addr_r[2] ? _T_1493 : _T_1494; // @[el2_lsu_bus_buffer.scala 384:44] + wire [63:0] _T_1522 = {buf_data_0,32'h0}; // @[Cat.scala 29:58] + wire [63:0] _T_1535 = {32'h0,buf_data_0}; // @[Cat.scala 29:58] + wire [63:0] _T_1536 = buf_addr_0[2] ? _T_1522 : _T_1535; // @[el2_lsu_bus_buffer.scala 385:8] + wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1495 : _T_1536; // @[el2_lsu_bus_buffer.scala 384:26] + wire _T_1621 = CmdPtr0 != 2'h0; // @[el2_lsu_bus_buffer.scala 391:30] + wire _T_1622 = _T_1621 & found_cmdptr0; // @[el2_lsu_bus_buffer.scala 391:43] + wire _T_1623 = _T_1622 & found_cmdptr1; // @[el2_lsu_bus_buffer.scala 391:59] + wire _T_1637 = _T_1623 & _T_1107; // @[el2_lsu_bus_buffer.scala 391:75] + wire _T_1651 = _T_1637 & _T_2606; // @[el2_lsu_bus_buffer.scala 391:118] + wire _T_1672 = _T_1651 & _T_1128; // @[el2_lsu_bus_buffer.scala 391:161] + wire _T_1690 = _T_1672 & _T_1053; // @[el2_lsu_bus_buffer.scala 392:85] + wire _T_1792 = _T_1204 & _T_1166; // @[el2_lsu_bus_buffer.scala 395:38] reg buf_dualhi_3; // @[Reg.scala 27:20] reg buf_dualhi_2; // @[Reg.scala 27:20] reg buf_dualhi_1; // @[Reg.scala 27:20] reg buf_dualhi_0; // @[Reg.scala 27:20] - wire _GEN_61 = 2'h1 == CmdPtr0 ? buf_dualhi_1 : buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 512:80] - wire _GEN_62 = 2'h2 == CmdPtr0 ? buf_dualhi_2 : _GEN_61; // @[el2_lsu_bus_buffer.scala 512:80] - wire _GEN_63 = 2'h3 == CmdPtr0 ? buf_dualhi_3 : _GEN_62; // @[el2_lsu_bus_buffer.scala 512:80] - wire _T_1338 = ~_GEN_63; // @[el2_lsu_bus_buffer.scala 512:80] - wire _T_1339 = _T_1337 & _T_1338; // @[el2_lsu_bus_buffer.scala 512:78] - wire _T_1340 = _T_1339 & _GEN_39; // @[el2_lsu_bus_buffer.scala 512:101] - wire _T_1342 = _T_1326 & _T_1340; // @[el2_lsu_bus_buffer.scala 510:89] - wire _T_1343 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 513:54] - wire _T_1344 = _T_1343 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 513:70] - wire obuf_merge_en = _T_1342 | _T_1344; // @[el2_lsu_bus_buffer.scala 512:126] - wire _T_1214 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [63:0] _T_1388 = {store_data_hi_r,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1390 = {32'h0,store_data_hi_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1391 = io_lsu_addr_r[2] ? _T_1388 : _T_1390; // @[el2_lsu_bus_buffer.scala 518:49] - wire [31:0] _GEN_77 = 2'h1 == CmdPtr1 ? buf_data_1 : buf_data_0; // @[Cat.scala 29:58] - wire [31:0] _GEN_78 = 2'h2 == CmdPtr1 ? buf_data_2 : _GEN_77; // @[Cat.scala 29:58] - wire [31:0] _GEN_79 = 2'h3 == CmdPtr1 ? buf_data_3 : _GEN_78; // @[Cat.scala 29:58] - wire [63:0] _T_1393 = {_GEN_79,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1394 = {32'h0,_GEN_79}; // @[Cat.scala 29:58] - wire [63:0] _T_1395 = _GEN_59[2] ? _T_1393 : _T_1394; // @[el2_lsu_bus_buffer.scala 518:150] - wire [63:0] obuf_data1_in = ibuf_buf_byp ? _T_1391 : _T_1395; // @[el2_lsu_bus_buffer.scala 518:31] - wire [63:0] _T_1377 = {store_data_lo_r,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1379 = {32'h0,store_data_lo_r}; // @[Cat.scala 29:58] - wire [63:0] _T_1380 = io_lsu_addr_r[2] ? _T_1377 : _T_1379; // @[el2_lsu_bus_buffer.scala 517:49] - wire [31:0] _GEN_73 = 2'h1 == CmdPtr0 ? buf_data_1 : buf_data_0; // @[Cat.scala 29:58] - wire [31:0] _GEN_74 = 2'h2 == CmdPtr0 ? buf_data_2 : _GEN_73; // @[Cat.scala 29:58] - wire [31:0] _GEN_75 = 2'h3 == CmdPtr0 ? buf_data_3 : _GEN_74; // @[Cat.scala 29:58] - wire [63:0] _T_1382 = {_GEN_75,32'h0}; // @[Cat.scala 29:58] - wire [63:0] _T_1383 = {32'h0,_GEN_75}; // @[Cat.scala 29:58] - wire [63:0] _T_1384 = _GEN_15[2] ? _T_1382 : _T_1383; // @[el2_lsu_bus_buffer.scala 517:150] - wire [63:0] obuf_data0_in = ibuf_buf_byp ? _T_1380 : _T_1384; // @[el2_lsu_bus_buffer.scala 517:31] - wire [7:0] _T_1217 = _T_1214 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1219 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1222 = _T_1219 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1224 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1227 = _T_1224 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1229 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1232 = _T_1229 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1234 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1237 = _T_1234 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1239 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1242 = _T_1239 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1244 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1247 = _T_1244 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 499:53] - wire _T_1249 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 499:69] - wire [7:0] _T_1252 = _T_1249 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 499:53] - wire [63:0] obuf_data_in = {_T_1252,_T_1247,_T_1242,_T_1237,_T_1232,_T_1227,_T_1222,_T_1217}; // @[Cat.scala 29:58] - wire [7:0] _T_1355 = {ldst_byteen_lo_r,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1357 = {4'h0,ldst_byteen_lo_r}; // @[Cat.scala 29:58] - wire [7:0] _T_1358 = io_lsu_addr_r[2] ? _T_1355 : _T_1357; // @[el2_lsu_bus_buffer.scala 515:49] - wire [3:0] _GEN_65 = 2'h1 == CmdPtr0 ? buf_byteen_1 : buf_byteen_0; // @[Cat.scala 29:58] - wire [3:0] _GEN_66 = 2'h2 == CmdPtr0 ? buf_byteen_2 : _GEN_65; // @[Cat.scala 29:58] - wire [3:0] _GEN_67 = 2'h3 == CmdPtr0 ? buf_byteen_3 : _GEN_66; // @[Cat.scala 29:58] - wire [7:0] _T_1360 = {_GEN_67,4'h0}; // @[Cat.scala 29:58] - wire [7:0] _T_1361 = {4'h0,_GEN_67}; // @[Cat.scala 29:58] - wire [7:0] _T_1362 = _GEN_15[2] ? _T_1360 : _T_1361; // @[el2_lsu_bus_buffer.scala 515:150] - wire [7:0] obuf_byteen0_in = ibuf_buf_byp ? _T_1358 : _T_1362; // @[el2_lsu_bus_buffer.scala 515:31] - wire _T_1265 = obuf_byteen0_in[0] | _T_1214; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1269 = obuf_byteen0_in[1] | _T_1219; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1273 = obuf_byteen0_in[2] | _T_1224; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1277 = obuf_byteen0_in[3] | _T_1229; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1281 = obuf_byteen0_in[4] | _T_1234; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1285 = obuf_byteen0_in[5] | _T_1239; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1289 = obuf_byteen0_in[6] | _T_1244; // @[el2_lsu_bus_buffer.scala 501:69] - wire _T_1293 = obuf_byteen0_in[7] | _T_1249; // @[el2_lsu_bus_buffer.scala 501:69] - wire [7:0] obuf_byteen_in = {_T_1293,_T_1289,_T_1285,_T_1281,_T_1277,_T_1273,_T_1269,_T_1265}; // @[Cat.scala 29:58] - wire _T_1301 = obuf_wr_en | obuf_rst; // @[el2_lsu_bus_buffer.scala 503:42] - wire _T_1302 = ~_T_1301; // @[el2_lsu_bus_buffer.scala 503:29] - wire [1:0] _T_1309 = ibuf_buf_byp ? WrPtr0_r : CmdPtr0; // @[el2_lsu_bus_buffer.scala 505:32] - wire [1:0] _T_1310 = ibuf_buf_byp ? WrPtr1_r : CmdPtr0; // @[el2_lsu_bus_buffer.scala 506:32] - wire _T_1346 = buf_numvld_cmd_any > 4'h0; // @[el2_lsu_bus_buffer.scala 514:74] - wire _T_1347 = obuf_wr_timer < 3'h7; // @[el2_lsu_bus_buffer.scala 514:103] - wire _T_1348 = _T_1346 & _T_1347; // @[el2_lsu_bus_buffer.scala 514:86] - wire [2:0] _T_1350 = obuf_wr_timer + 3'h1; // @[el2_lsu_bus_buffer.scala 514:154] - reg [63:0] obuf_data; // @[Reg.scala 27:20] - wire _T_1406 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 531:32] - wire _T_1407 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 531:72] + wire [3:0] _T_1795 = {buf_dualhi_3,buf_dualhi_2,buf_dualhi_1,buf_dualhi_0}; // @[Cat.scala 29:58] + wire _T_1804 = _T_1023 & _T_1795[0]; // @[Mux.scala 27:72] + wire _T_1805 = _T_1024 & _T_1795[1]; // @[Mux.scala 27:72] + wire _T_1808 = _T_1804 | _T_1805; // @[Mux.scala 27:72] + wire _T_1806 = _T_1025 & _T_1795[2]; // @[Mux.scala 27:72] + wire _T_1809 = _T_1808 | _T_1806; // @[Mux.scala 27:72] + wire _T_1807 = _T_1026 & _T_1795[3]; // @[Mux.scala 27:72] + wire _T_1810 = _T_1809 | _T_1807; // @[Mux.scala 27:72] + wire _T_1812 = ~_T_1810; // @[el2_lsu_bus_buffer.scala 395:109] + wire _T_1813 = _T_1792 & _T_1812; // @[el2_lsu_bus_buffer.scala 395:107] + wire _T_1833 = _T_1813 & _T_1185; // @[el2_lsu_bus_buffer.scala 395:179] + wire _T_1835 = _T_1690 & _T_1833; // @[el2_lsu_bus_buffer.scala 392:122] + wire _T_1836 = ibuf_buf_byp & ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 396:19] + wire _T_1837 = _T_1836 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 396:35] + wire obuf_merge_en = _T_1835 | _T_1837; // @[el2_lsu_bus_buffer.scala 395:253] + wire _T_1539 = obuf_merge_en & obuf_byteen1_in[0]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1540 = obuf_byteen0_in[0] | _T_1539; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1543 = obuf_merge_en & obuf_byteen1_in[1]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1544 = obuf_byteen0_in[1] | _T_1543; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1547 = obuf_merge_en & obuf_byteen1_in[2]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1548 = obuf_byteen0_in[2] | _T_1547; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1551 = obuf_merge_en & obuf_byteen1_in[3]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1552 = obuf_byteen0_in[3] | _T_1551; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1555 = obuf_merge_en & obuf_byteen1_in[4]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1556 = obuf_byteen0_in[4] | _T_1555; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1559 = obuf_merge_en & obuf_byteen1_in[5]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1560 = obuf_byteen0_in[5] | _T_1559; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1563 = obuf_merge_en & obuf_byteen1_in[6]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1564 = obuf_byteen0_in[6] | _T_1563; // @[el2_lsu_bus_buffer.scala 386:63] + wire _T_1567 = obuf_merge_en & obuf_byteen1_in[7]; // @[el2_lsu_bus_buffer.scala 386:80] + wire _T_1568 = obuf_byteen0_in[7] | _T_1567; // @[el2_lsu_bus_buffer.scala 386:63] + wire [7:0] obuf_byteen_in = {_T_1568,_T_1564,_T_1560,_T_1556,_T_1552,_T_1548,_T_1544,_T_1540}; // @[Cat.scala 29:58] + wire [7:0] _T_1579 = _T_1539 ? obuf_data1_in[7:0] : obuf_data0_in[7:0]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1584 = _T_1543 ? obuf_data1_in[15:8] : obuf_data0_in[15:8]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1589 = _T_1547 ? obuf_data1_in[23:16] : obuf_data0_in[23:16]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1594 = _T_1551 ? obuf_data1_in[31:24] : obuf_data0_in[31:24]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1599 = _T_1555 ? obuf_data1_in[39:32] : obuf_data0_in[39:32]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1604 = _T_1559 ? obuf_data1_in[47:40] : obuf_data0_in[47:40]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1609 = _T_1563 ? obuf_data1_in[55:48] : obuf_data0_in[55:48]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [7:0] _T_1614 = _T_1567 ? obuf_data1_in[63:56] : obuf_data0_in[63:56]; // @[el2_lsu_bus_buffer.scala 387:44] + wire [55:0] _T_1620 = {_T_1614,_T_1609,_T_1604,_T_1599,_T_1594,_T_1589,_T_1584}; // @[Cat.scala 29:58] + wire _T_1839 = obuf_wr_en | obuf_valid; // @[el2_lsu_bus_buffer.scala 399:58] + wire _T_1840 = ~obuf_rst; // @[el2_lsu_bus_buffer.scala 399:93] reg [1:0] obuf_sz; // @[Reg.scala 27:20] reg [7:0] obuf_byteen; // @[Reg.scala 27:20] - wire [2:0] obuf_tag0_in = {{1'd0}, _T_1309}; // @[el2_lsu_bus_buffer.scala 505:26] - wire [2:0] obuf_tag1_in = {{1'd0}, _T_1310}; // @[el2_lsu_bus_buffer.scala 506:26] - wire _T_1418 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1419 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1420 = ibuf_valid & _T_1419; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1421 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1422 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1423 = io_ldst_dual_r & _T_1422; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1424 = _T_1421 | _T_1423; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1425 = io_lsu_busreq_r & _T_1424; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1426 = _T_1420 | _T_1425; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1427 = ~_T_1426; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1428 = _T_1418 & _T_1427; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1430 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1431 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1432 = ibuf_valid & _T_1431; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1433 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1434 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1435 = io_ldst_dual_r & _T_1434; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1436 = _T_1433 | _T_1435; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1437 = io_lsu_busreq_r & _T_1436; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1438 = _T_1432 | _T_1437; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1439 = ~_T_1438; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1440 = _T_1430 & _T_1439; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1442 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1443 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1444 = ibuf_valid & _T_1443; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1445 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1446 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1447 = io_ldst_dual_r & _T_1446; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1448 = _T_1445 | _T_1447; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1449 = io_lsu_busreq_r & _T_1448; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1450 = _T_1444 | _T_1449; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1451 = ~_T_1450; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1452 = _T_1442 & _T_1451; // @[el2_lsu_bus_buffer.scala 546:67] - wire _T_1454 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 546:56] - wire _T_1455 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 546:93] - wire _T_1456 = ibuf_valid & _T_1455; // @[el2_lsu_bus_buffer.scala 546:83] - wire _T_1457 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 547:35] - wire _T_1458 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 547:72] - wire _T_1459 = io_ldst_dual_r & _T_1458; // @[el2_lsu_bus_buffer.scala 547:61] - wire _T_1460 = _T_1457 | _T_1459; // @[el2_lsu_bus_buffer.scala 547:43] - wire _T_1461 = io_lsu_busreq_r & _T_1460; // @[el2_lsu_bus_buffer.scala 547:23] - wire _T_1462 = _T_1456 | _T_1461; // @[el2_lsu_bus_buffer.scala 546:101] - wire _T_1463 = ~_T_1462; // @[el2_lsu_bus_buffer.scala 546:69] - wire _T_1464 = _T_1454 & _T_1463; // @[el2_lsu_bus_buffer.scala 546:67] - wire [1:0] _T_1466 = _T_1464 ? 2'h3 : 2'h0; // @[Mux.scala 98:16] - wire [1:0] _T_1467 = _T_1452 ? 2'h2 : _T_1466; // @[Mux.scala 98:16] - wire [1:0] _T_1468 = _T_1440 ? 2'h1 : _T_1467; // @[Mux.scala 98:16] - wire [1:0] WrPtr0_m = _T_1428 ? 2'h0 : _T_1468; // @[Mux.scala 98:16] - wire _T_1473 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1474 = io_lsu_busreq_m & _T_1473; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1475 = _T_1420 | _T_1474; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1477 = io_lsu_busreq_r & _T_1421; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1480 = _T_1477 | _T_1423; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1481 = _T_1475 | _T_1480; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1482 = ~_T_1481; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1483 = _T_1418 & _T_1482; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1488 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1489 = io_lsu_busreq_m & _T_1488; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1490 = _T_1432 | _T_1489; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1492 = io_lsu_busreq_r & _T_1433; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1495 = _T_1492 | _T_1435; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1496 = _T_1490 | _T_1495; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1497 = ~_T_1496; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1498 = _T_1430 & _T_1497; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1503 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1504 = io_lsu_busreq_m & _T_1503; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1505 = _T_1444 | _T_1504; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1507 = io_lsu_busreq_r & _T_1445; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1510 = _T_1507 | _T_1447; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1511 = _T_1505 | _T_1510; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1512 = ~_T_1511; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1513 = _T_1442 & _T_1512; // @[el2_lsu_bus_buffer.scala 549:70] - wire _T_1518 = WrPtr0_m == 2'h3; // @[el2_lsu_bus_buffer.scala 550:35] - wire _T_1519 = io_lsu_busreq_m & _T_1518; // @[el2_lsu_bus_buffer.scala 550:23] - wire _T_1520 = _T_1456 | _T_1519; // @[el2_lsu_bus_buffer.scala 549:108] - wire _T_1522 = io_lsu_busreq_r & _T_1457; // @[el2_lsu_bus_buffer.scala 550:64] - wire _T_1525 = _T_1522 | _T_1459; // @[el2_lsu_bus_buffer.scala 550:85] - wire _T_1526 = _T_1520 | _T_1525; // @[el2_lsu_bus_buffer.scala 550:45] - wire _T_1527 = ~_T_1526; // @[el2_lsu_bus_buffer.scala 549:72] - wire _T_1528 = _T_1454 & _T_1527; // @[el2_lsu_bus_buffer.scala 549:70] - reg buf_rspageQ_0_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1722 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_1 = buf_rspageQ_0_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1627 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_0 = buf_rspageQ_0_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1912 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_3 = buf_rspageQ_0_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_0_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire _T_1817 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 575:66] - wire buf_rsp_pickage_0_2 = buf_rspageQ_0_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_1561 = {buf_rsp_pickage_0_3,buf_rsp_pickage_0_2,buf_rsp_pickage_0_1,buf_rsp_pickage_0_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_1562 = |_T_1561; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_1563 = ~_T_1562; // @[el2_lsu_bus_buffer.scala 560:32] - wire _T_1565 = _T_1563 & _T_1627; // @[el2_lsu_bus_buffer.scala 560:67] - wire _T_3136 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 617:83] - wire _T_3137 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 617:103] - wire _T_3138 = _T_3136 & _T_3137; // @[el2_lsu_bus_buffer.scala 617:101] - wire _T_3139 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 617:123] - wire _T_3140 = _T_3138 & _T_3139; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3141 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 617:150] - wire _T_3142 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3143 = _T_3141 & _T_3142; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3144 = _T_3140 | _T_3143; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3145 = _T_906 & _T_3144; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3146 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 617:212] - wire _T_3147 = ibuf_drain_vld & _T_3146; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3148 = _T_3145 | _T_3147; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3158 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 624:52] - wire _T_3192 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] - wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 740:49] - wire _T_3217 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3218 = bus_rsp_write & _T_3217; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3219 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 643:78] - reg buf_ldfwd_0; // @[Reg.scala 27:20] + reg [63:0] obuf_data; // @[el2_lib.scala 514:16] + wire _T_1853 = buf_state_0 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1854 = ibuf_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1855 = ibuf_valid & _T_1854; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1856 = WrPtr0_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1857 = WrPtr1_r == 2'h0; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1858 = io_ldst_dual_r & _T_1857; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1859 = _T_1856 | _T_1858; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1860 = io_lsu_busreq_r & _T_1859; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1861 = _T_1855 | _T_1860; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1862 = ~_T_1861; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1863 = _T_1853 & _T_1862; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1864 = buf_state_1 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1865 = ibuf_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1866 = ibuf_valid & _T_1865; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1867 = WrPtr0_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1868 = WrPtr1_r == 2'h1; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1869 = io_ldst_dual_r & _T_1868; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1870 = _T_1867 | _T_1869; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1871 = io_lsu_busreq_r & _T_1870; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1872 = _T_1866 | _T_1871; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1873 = ~_T_1872; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1874 = _T_1864 & _T_1873; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1875 = buf_state_2 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1876 = ibuf_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1877 = ibuf_valid & _T_1876; // @[el2_lsu_bus_buffer.scala 418:19] + wire _T_1878 = WrPtr0_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1879 = WrPtr1_r == 2'h2; // @[el2_lsu_bus_buffer.scala 419:57] + wire _T_1880 = io_ldst_dual_r & _T_1879; // @[el2_lsu_bus_buffer.scala 419:45] + wire _T_1881 = _T_1878 | _T_1880; // @[el2_lsu_bus_buffer.scala 419:27] + wire _T_1882 = io_lsu_busreq_r & _T_1881; // @[el2_lsu_bus_buffer.scala 418:58] + wire _T_1883 = _T_1877 | _T_1882; // @[el2_lsu_bus_buffer.scala 418:39] + wire _T_1884 = ~_T_1883; // @[el2_lsu_bus_buffer.scala 418:5] + wire _T_1885 = _T_1875 & _T_1884; // @[el2_lsu_bus_buffer.scala 417:76] + wire _T_1886 = buf_state_3 == 3'h0; // @[el2_lsu_bus_buffer.scala 417:65] + wire _T_1887 = ibuf_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 418:30] + wire _T_1889 = WrPtr0_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:18] + wire _T_1890 = WrPtr1_r == 2'h3; // @[el2_lsu_bus_buffer.scala 419:57] + wire [1:0] _T_1898 = _T_1885 ? 2'h2 : 2'h3; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = _T_1874 ? 2'h1 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] WrPtr0_m = _T_1863 ? 2'h0 : _T_1899; // @[Mux.scala 98:16] + wire _T_1904 = WrPtr0_m == 2'h0; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1905 = io_lsu_busreq_m & _T_1904; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1906 = _T_1855 | _T_1905; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1912 = _T_1906 | _T_1860; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1913 = ~_T_1912; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1914 = _T_1853 & _T_1913; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1918 = WrPtr0_m == 2'h1; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1919 = io_lsu_busreq_m & _T_1918; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1920 = _T_1866 | _T_1919; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1926 = _T_1920 | _T_1871; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1927 = ~_T_1926; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1928 = _T_1864 & _T_1927; // @[el2_lsu_bus_buffer.scala 423:76] + wire _T_1932 = WrPtr0_m == 2'h2; // @[el2_lsu_bus_buffer.scala 424:33] + wire _T_1933 = io_lsu_busreq_m & _T_1932; // @[el2_lsu_bus_buffer.scala 424:22] + wire _T_1934 = _T_1877 | _T_1933; // @[el2_lsu_bus_buffer.scala 423:112] + wire _T_1940 = _T_1934 | _T_1882; // @[el2_lsu_bus_buffer.scala 424:42] + wire _T_1941 = ~_T_1940; // @[el2_lsu_bus_buffer.scala 423:78] + wire _T_1942 = _T_1875 & _T_1941; // @[el2_lsu_bus_buffer.scala 423:76] + reg [3:0] buf_rspageQ_0; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2746 = buf_state_3 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2747 = buf_rspageQ_0[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2743 = buf_state_2 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2744 = buf_rspageQ_0[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2740 = buf_state_1 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2741 = buf_rspageQ_0[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2737 = buf_state_0 == 3'h5; // @[el2_lsu_bus_buffer.scala 467:102] + wire _T_2738 = buf_rspageQ_0[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_0 = {_T_2747,_T_2744,_T_2741,_T_2738}; // @[Cat.scala 29:58] + wire _T_2033 = |buf_rsp_pickage_0; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2034 = ~_T_2033; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2036 = _T_2034 & _T_2737; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_1; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2762 = buf_rspageQ_1[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2759 = buf_rspageQ_1[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2756 = buf_rspageQ_1[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2753 = buf_rspageQ_1[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_1 = {_T_2762,_T_2759,_T_2756,_T_2753}; // @[Cat.scala 29:58] + wire _T_2037 = |buf_rsp_pickage_1; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2038 = ~_T_2037; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2040 = _T_2038 & _T_2740; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_2; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2777 = buf_rspageQ_2[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2774 = buf_rspageQ_2[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2771 = buf_rspageQ_2[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2768 = buf_rspageQ_2[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_2 = {_T_2777,_T_2774,_T_2771,_T_2768}; // @[Cat.scala 29:58] + wire _T_2041 = |buf_rsp_pickage_2; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2042 = ~_T_2041; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2044 = _T_2042 & _T_2743; // @[el2_lsu_bus_buffer.scala 435:70] + reg [3:0] buf_rspageQ_3; // @[el2_lsu_bus_buffer.scala 554:63] + wire _T_2792 = buf_rspageQ_3[3] & _T_2746; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2789 = buf_rspageQ_3[2] & _T_2743; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2786 = buf_rspageQ_3[1] & _T_2740; // @[el2_lsu_bus_buffer.scala 467:87] + wire _T_2783 = buf_rspageQ_3[0] & _T_2737; // @[el2_lsu_bus_buffer.scala 467:87] + wire [3:0] buf_rsp_pickage_3 = {_T_2792,_T_2789,_T_2786,_T_2783}; // @[Cat.scala 29:58] + wire _T_2045 = |buf_rsp_pickage_3; // @[el2_lsu_bus_buffer.scala 435:65] + wire _T_2046 = ~_T_2045; // @[el2_lsu_bus_buffer.scala 435:44] + wire _T_2048 = _T_2046 & _T_2746; // @[el2_lsu_bus_buffer.scala 435:70] + wire [7:0] _T_2104 = {4'h0,_T_2048,_T_2044,_T_2040,_T_2036}; // @[Cat.scala 29:58] + wire _T_2107 = _T_2104[4] | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:42] + wire _T_2109 = _T_2107 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:48] + wire _T_2111 = _T_2109 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:54] + wire _T_2114 = _T_2104[2] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:67] + wire _T_2116 = _T_2114 | _T_2104[6]; // @[el2_lsu_bus_buffer.scala 439:73] + wire _T_2118 = _T_2116 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:79] + wire _T_2121 = _T_2104[1] | _T_2104[3]; // @[el2_lsu_bus_buffer.scala 439:92] + wire _T_2123 = _T_2121 | _T_2104[5]; // @[el2_lsu_bus_buffer.scala 439:98] + wire _T_2125 = _T_2123 | _T_2104[7]; // @[el2_lsu_bus_buffer.scala 439:104] + wire [2:0] _T_2127 = {_T_2111,_T_2118,_T_2125}; // @[Cat.scala 29:58] + wire _T_3532 = ibuf_byp | io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:77] + wire _T_3533 = ~ibuf_merge_en; // @[el2_lsu_bus_buffer.scala 497:97] + wire _T_3534 = _T_3532 & _T_3533; // @[el2_lsu_bus_buffer.scala 497:95] + wire _T_3535 = 2'h0 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3536 = _T_3534 & _T_3535; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3537 = ibuf_byp & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 497:144] + wire _T_3538 = 2'h0 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3539 = _T_3537 & _T_3538; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3540 = _T_3536 | _T_3539; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3541 = _T_853 & _T_3540; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3542 = 2'h0 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3543 = ibuf_drain_vld & _T_3542; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3544 = _T_3541 | _T_3543; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3554 = io_lsu_bus_clk_en | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 504:46] + wire _T_3589 = 3'h3 == buf_state_0; // @[Conditional.scala 37:30] + wire bus_rsp_write = io_lsu_axi_bvalid & io_lsu_axi_bready; // @[el2_lsu_bus_buffer.scala 614:38] + wire _T_3634 = io_lsu_axi_bid == 3'h0; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3635 = bus_rsp_write & _T_3634; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3636 = io_lsu_axi_rid == 3'h0; // @[el2_lsu_bus_buffer.scala 523:46] + reg _T_4307; // @[Reg.scala 27:20] + reg _T_4305; // @[Reg.scala 27:20] + reg _T_4303; // @[Reg.scala 27:20] + reg _T_4301; // @[Reg.scala 27:20] + wire [3:0] buf_ldfwd = {_T_4307,_T_4305,_T_4303,_T_4301}; // @[Cat.scala 29:58] reg [1:0] buf_ldfwdtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_474 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3220 = io_lsu_axi_rid == _GEN_474; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3221 = buf_ldfwd_0 & _T_3220; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3222 = _T_3219 | _T_3221; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3223 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3224 = ~buf_write_0; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3225 = _T_3223 & _T_3224; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3226 = _T_3225 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_368 = {{1'd0}, buf_ldfwdtag_0}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3638 = io_lsu_axi_rid == _GEN_368; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3639 = buf_ldfwd[0] & _T_3638; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3640 = _T_3636 | _T_3639; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3641 = buf_dual_0 & buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3643 = ~buf_write[0]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3644 = _T_3641 & _T_3643; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3645 = _T_3644 & buf_samedw_0; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_0; // @[Reg.scala 27:20] - wire [2:0] _GEN_475 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3227 = io_lsu_axi_rid == _GEN_475; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3228 = _T_3226 & _T_3227; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3229 = _T_3222 | _T_3228; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3230 = bus_rsp_read & _T_3229; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3231 = _T_3218 | _T_3230; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_118 = _T_3192 & _T_3231; // @[Conditional.scala 39:67] - wire _GEN_137 = _T_3159 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] - wire _GEN_149 = _T_3155 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] - wire _T_3256 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] - reg buf_ldfwd_3; // @[Reg.scala 27:20] - reg buf_ldfwd_2; // @[Reg.scala 27:20] - reg buf_ldfwd_1; // @[Reg.scala 27:20] - wire _GEN_95 = 2'h1 == buf_dualtag_0 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_96 = 2'h2 == buf_dualtag_0 ? buf_ldfwd_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_97 = 2'h3 == buf_dualtag_0 ? buf_ldfwd_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 641:136] + wire [2:0] _GEN_369 = {{1'd0}, buf_dualtag_0}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3646 = io_lsu_axi_rid == _GEN_369; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3647 = _T_3645 & _T_3646; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3648 = _T_3640 | _T_3647; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3649 = bus_rsp_read & _T_3648; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3650 = _T_3635 | _T_3649; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_42 = _T_3589 & _T_3650; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_3555 ? 1'h0 : _GEN_42; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_3551 ? 1'h0 : _GEN_61; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_73; // @[Conditional.scala 40:58] + wire _T_3676 = 3'h4 == buf_state_0; // @[Conditional.scala 37:30] + wire [3:0] _T_3686 = buf_ldfwd >> buf_dualtag_0; // @[el2_lsu_bus_buffer.scala 537:21] reg [1:0] buf_ldfwdtag_3; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_2; // @[Reg.scala 27:20] reg [1:0] buf_ldfwdtag_1; // @[Reg.scala 27:20] - wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_477 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3263 = io_lsu_axi_rid == _GEN_477; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3264 = _GEN_97 & _T_3263; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3265 = _T_3227 | _T_3264; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3266 = bus_rsp_read & _T_3265; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_112 = _T_3256 & _T_3266; // @[Conditional.scala 39:67] - wire _GEN_119 = _T_3192 ? buf_resp_state_bus_en_0 : _GEN_112; // @[Conditional.scala 39:67] - wire _GEN_129 = _T_3159 ? buf_cmd_state_bus_en_0 : _GEN_119; // @[Conditional.scala 39:67] - wire _GEN_142 = _T_3155 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] - wire buf_state_bus_en_0 = _T_3132 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] - wire _T_3172 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3173 = _T_3172 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3269 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] - reg buf_rspageQ_3_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_3 = buf_rspageQ_3_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_2 = buf_rspageQ_3_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_1 = buf_rspageQ_3_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_3_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_3_0 = buf_rspageQ_3_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2986 = {buf_rsp_pickage_3_3,buf_rsp_pickage_3_2,buf_rsp_pickage_3_1,buf_rsp_pickage_3_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2987 = |_T_2986; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2988 = ~_T_2987; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_3 = _T_2988 & _T_1912; // @[el2_lsu_bus_buffer.scala 560:67] - reg buf_rspageQ_2_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_3 = buf_rspageQ_2_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_2 = buf_rspageQ_2_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_1 = buf_rspageQ_2_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_2_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_2_0 = buf_rspageQ_2_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2606 = {buf_rsp_pickage_2_3,buf_rsp_pickage_2_2,buf_rsp_pickage_2_1,buf_rsp_pickage_2_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2607 = |_T_2606; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2608 = ~_T_2607; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_2 = _T_2608 & _T_1817; // @[el2_lsu_bus_buffer.scala 560:67] - reg buf_rspageQ_1_3; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_3 = buf_rspageQ_1_3 & _T_1912; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_2; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_2 = buf_rspageQ_1_2 & _T_1817; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_1; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_1 = buf_rspageQ_1_1 & _T_1722; // @[el2_lsu_bus_buffer.scala 575:50] - reg buf_rspageQ_1_0; // @[el2_lsu_bus_buffer.scala 691:41] - wire buf_rsp_pickage_1_0 = buf_rspageQ_1_0 & _T_1627; // @[el2_lsu_bus_buffer.scala 575:50] - wire [3:0] _T_2226 = {buf_rsp_pickage_1_3,buf_rsp_pickage_1_2,buf_rsp_pickage_1_1,buf_rsp_pickage_1_0}; // @[el2_lsu_bus_buffer.scala 560:53] - wire _T_2227 = |_T_2226; // @[el2_lsu_bus_buffer.scala 560:63] - wire _T_2228 = ~_T_2227; // @[el2_lsu_bus_buffer.scala 560:32] - wire RspPtrDec_1 = _T_2228 & _T_1722; // @[el2_lsu_bus_buffer.scala 560:67] - wire [3:0] _T_3078 = {RspPtrDec_3,RspPtrDec_2,RspPtrDec_1,_T_1565}; // @[el2_lsu_bus_buffer.scala 580:58] - wire [3:0] _T_3083 = _T_3078[3] ? 4'h8 : 4'h0; // @[Mux.scala 47:69] - wire [3:0] _T_3084 = _T_3078[2] ? 4'h4 : _T_3083; // @[Mux.scala 47:69] - wire [3:0] _T_3085 = _T_3078[1] ? 4'h2 : _T_3084; // @[Mux.scala 47:69] - wire [3:0] _T_3086 = _T_3078[0] ? 4'h1 : _T_3085; // @[Mux.scala 47:69] - wire [1:0] RspPtr = _T_3086[1:0]; // @[el2_lsu_bus_buffer.scala 580:27] - wire _T_3272 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3273 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3274 = buf_dual_0 & _T_3273; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3275 = _T_3272 | _T_3274; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3276 = _T_3275 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3277 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] - wire _GEN_107 = _T_3269 ? _T_3276 : _T_3277; // @[Conditional.scala 39:67] - wire _GEN_113 = _T_3256 ? _T_3173 : _GEN_107; // @[Conditional.scala 39:67] - wire _GEN_120 = _T_3192 ? _T_3173 : _GEN_113; // @[Conditional.scala 39:67] - wire _GEN_130 = _T_3159 ? _T_3173 : _GEN_120; // @[Conditional.scala 39:67] - wire _GEN_140 = _T_3155 ? _T_3158 : _GEN_130; // @[Conditional.scala 39:67] - wire buf_state_en_0 = _T_3132 ? _T_3148 : _GEN_140; // @[Conditional.scala 40:58] - wire _T_1567 = _T_1418 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_1572 = _T_3986 | _T_3985; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1573 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 564:25] - wire _T_1575 = _T_1573 & _T_3136; // @[el2_lsu_bus_buffer.scala 564:43] - wire _T_1577 = _T_1575 & _T_3139; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_1579 = _T_1577 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1580 = _T_1572 | _T_1579; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1581 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 565:19] - wire _T_1582 = _T_1581 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 565:37] - wire _T_1584 = _T_1582 & _T_3142; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_1586 = _T_1584 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1587 = _T_1580 | _T_1586; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1588 = _T_1567 & _T_1587; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1602 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1603 = _T_1418 | _T_1602; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1604 = ~_T_1603; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1612 = _T_1604 | _T_1579; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1619 = _T_1612 | _T_1586; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_0 = _T_1567 & _T_1619; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1624 = _T_1602 | _T_1418; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1625 = ~_T_1624; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_0 = buf_rspageQ_0_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1667 = _T_3991 | _T_3990; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1673 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1674 = _T_1577 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1675 = _T_1667 | _T_1674; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1680 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1681 = _T_1584 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1682 = _T_1675 | _T_1681; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1683 = _T_1567 & _T_1682; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1697 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1698 = _T_1430 | _T_1697; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1699 = ~_T_1698; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1707 = _T_1699 | _T_1674; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1714 = _T_1707 | _T_1681; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_1 = _T_1567 & _T_1714; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1719 = _T_1697 | _T_1430; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1720 = ~_T_1719; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_1 = buf_rspageQ_0_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1762 = _T_3996 | _T_3995; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1768 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1769 = _T_1577 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1770 = _T_1762 | _T_1769; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1775 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1776 = _T_1584 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1777 = _T_1770 | _T_1776; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1778 = _T_1567 & _T_1777; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1792 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1793 = _T_1442 | _T_1792; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1794 = ~_T_1793; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1802 = _T_1794 | _T_1769; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1809 = _T_1802 | _T_1776; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_2 = _T_1567 & _T_1809; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1814 = _T_1792 | _T_1442; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1815 = ~_T_1814; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_2 = buf_rspageQ_0_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_1857 = _T_4001 | _T_4000; // @[el2_lsu_bus_buffer.scala 563:35] - wire _T_1863 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 564:97] - wire _T_1864 = _T_1577 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1865 = _T_1857 | _T_1864; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1870 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 565:78] - wire _T_1871 = _T_1584 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1872 = _T_1865 | _T_1871; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1873 = _T_1567 & _T_1872; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1887 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 570:125] - wire _T_1888 = _T_1454 | _T_1887; // @[el2_lsu_bus_buffer.scala 570:109] - wire _T_1889 = ~_T_1888; // @[el2_lsu_bus_buffer.scala 570:81] - wire _T_1897 = _T_1889 | _T_1864; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1904 = _T_1897 | _T_1871; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_0_3 = _T_1567 & _T_1904; // @[el2_lsu_bus_buffer.scala 570:78] - wire _T_1909 = _T_1887 | _T_1454; // @[el2_lsu_bus_buffer.scala 574:80] - wire _T_1910 = ~_T_1909; // @[el2_lsu_bus_buffer.scala 574:52] - wire buf_rspage_0_3 = buf_rspageQ_0_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3348 = _T_3138 & _T_1680; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3350 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3351 = _T_3141 & _T_3350; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3352 = _T_3348 | _T_3351; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3353 = _T_906 & _T_3352; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3355 = ibuf_drain_vld & _T_1673; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3356 = _T_3353 | _T_3355; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3400 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3425 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3426 = bus_rsp_write & _T_3425; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3427 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_478 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3428 = io_lsu_axi_rid == _GEN_478; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3429 = buf_ldfwd_1 & _T_3428; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3430 = _T_3427 | _T_3429; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3431 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3432 = ~buf_write_1; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3433 = _T_3431 & _T_3432; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3434 = _T_3433 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 645:94] + wire [1:0] _GEN_23 = 2'h1 == buf_dualtag_0 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_24 = 2'h2 == buf_dualtag_0 ? buf_ldfwdtag_2 : _GEN_23; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_25 = 2'h3 == buf_dualtag_0 ? buf_ldfwdtag_3 : _GEN_24; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_371 = {{1'd0}, _GEN_25}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3688 = io_lsu_axi_rid == _GEN_371; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3689 = _T_3686[0] & _T_3688; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3690 = _T_3646 | _T_3689; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3691 = bus_rsp_read & _T_3690; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_36 = _T_3676 & _T_3691; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_3589 ? buf_resp_state_bus_en_0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_3555 ? buf_cmd_state_bus_en_0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_3551 ? 1'h0 : _GEN_53; // @[Conditional.scala 39:67] + wire buf_state_bus_en_0 = _T_3528 ? 1'h0 : _GEN_66; // @[Conditional.scala 40:58] + wire _T_3568 = buf_state_bus_en_0 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3569 = _T_3568 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3694 = 3'h5 == buf_state_0; // @[Conditional.scala 37:30] + wire [1:0] RspPtr = _T_2127[1:0]; // @[el2_lsu_bus_buffer.scala 447:10] + wire _T_3697 = RspPtr == 2'h0; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3698 = buf_dualtag_0 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3699 = buf_dual_0 & _T_3698; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3700 = _T_3697 | _T_3699; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3701 = _T_3700 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3702 = 3'h6 == buf_state_0; // @[Conditional.scala 37:30] + wire _GEN_31 = _T_3694 ? _T_3701 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_37 = _T_3676 ? _T_3569 : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_44 = _T_3589 ? _T_3569 : _GEN_37; // @[Conditional.scala 39:67] + wire _GEN_54 = _T_3555 ? _T_3569 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_3551 ? _T_3554 : _GEN_54; // @[Conditional.scala 39:67] + wire buf_state_en_0 = _T_3528 ? _T_3544 : _GEN_64; // @[Conditional.scala 40:58] + wire _T_2129 = _T_1853 & buf_state_en_0; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2135 = ibuf_drain_vld & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 461:23] + wire _T_2137 = _T_2135 & _T_3532; // @[el2_lsu_bus_buffer.scala 461:41] + wire _T_2139 = _T_2137 & _T_1856; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2141 = _T_2139 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2142 = _T_4471 | _T_2141; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2143 = ibuf_byp & io_lsu_busreq_r; // @[el2_lsu_bus_buffer.scala 462:17] + wire _T_2144 = _T_2143 & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 462:35] + wire _T_2146 = _T_2144 & _T_1857; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2148 = _T_2146 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2149 = _T_2142 | _T_2148; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2150 = _T_2129 & _T_2149; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2152 = _T_2150 | buf_age_0[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2166 = _T_2139 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2167 = _T_4476 | _T_2166; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2173 = _T_2146 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2174 = _T_2167 | _T_2173; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2175 = _T_2129 & _T_2174; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2177 = _T_2175 | buf_age_0[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2191 = _T_2139 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2192 = _T_4481 | _T_2191; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2198 = _T_2146 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2199 = _T_2192 | _T_2198; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2200 = _T_2129 & _T_2199; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2202 = _T_2200 | buf_age_0[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2216 = _T_2139 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2217 = _T_4486 | _T_2216; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2223 = _T_2146 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2224 = _T_2217 | _T_2223; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2225 = _T_2129 & _T_2224; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2227 = _T_2225 | buf_age_0[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2229 = {_T_2227,_T_2202,_T_2177}; // @[Cat.scala 29:58] + wire _T_3728 = 2'h1 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3729 = _T_3534 & _T_3728; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3731 = 2'h1 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3732 = _T_3537 & _T_3731; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3733 = _T_3729 | _T_3732; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3734 = _T_853 & _T_3733; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3735 = 2'h1 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3736 = ibuf_drain_vld & _T_3735; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3737 = _T_3734 | _T_3736; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3782 = 3'h3 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3827 = io_lsu_axi_bid == 3'h1; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_3828 = bus_rsp_write & _T_3827; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_3829 = io_lsu_axi_rid == 3'h1; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_372 = {{1'd0}, buf_ldfwdtag_1}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3831 = io_lsu_axi_rid == _GEN_372; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_3832 = buf_ldfwd[1] & _T_3831; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_3833 = _T_3829 | _T_3832; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_3834 = buf_dual_1 & buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_3836 = ~buf_write[1]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_3837 = _T_3834 & _T_3836; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_3838 = _T_3837 & buf_samedw_1; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_1; // @[Reg.scala 27:20] - wire [2:0] _GEN_479 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3435 = io_lsu_axi_rid == _GEN_479; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3436 = _T_3434 & _T_3435; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3437 = _T_3430 | _T_3436; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3438 = bus_rsp_read & _T_3437; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3439 = _T_3426 | _T_3438; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_208 = _T_3400 & _T_3439; // @[Conditional.scala 39:67] - wire _GEN_227 = _T_3367 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] - wire _GEN_239 = _T_3363 ? 1'h0 : _GEN_227; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_239; // @[Conditional.scala 40:58] - wire _T_3464 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] - wire _GEN_185 = 2'h1 == buf_dualtag_1 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_186 = 2'h2 == buf_dualtag_1 ? buf_ldfwd_2 : _GEN_185; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_187 = 2'h3 == buf_dualtag_1 ? buf_ldfwd_3 : _GEN_186; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_189 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_190 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_189; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_191 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_190; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_481 = {{1'd0}, _GEN_191}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3471 = io_lsu_axi_rid == _GEN_481; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3472 = _GEN_187 & _T_3471; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3473 = _T_3435 | _T_3472; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3474 = bus_rsp_read & _T_3473; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_202 = _T_3464 & _T_3474; // @[Conditional.scala 39:67] - wire _GEN_209 = _T_3400 ? buf_resp_state_bus_en_1 : _GEN_202; // @[Conditional.scala 39:67] - wire _GEN_219 = _T_3367 ? buf_cmd_state_bus_en_1 : _GEN_209; // @[Conditional.scala 39:67] - wire _GEN_232 = _T_3363 ? 1'h0 : _GEN_219; // @[Conditional.scala 39:67] - wire buf_state_bus_en_1 = _T_3340 ? 1'h0 : _GEN_232; // @[Conditional.scala 40:58] - wire _T_3380 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3381 = _T_3380 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3477 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] - wire _T_3480 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3481 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3482 = buf_dual_1 & _T_3481; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3483 = _T_3480 | _T_3482; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3484 = _T_3483 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3485 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] - wire _GEN_197 = _T_3477 ? _T_3484 : _T_3485; // @[Conditional.scala 39:67] - wire _GEN_203 = _T_3464 ? _T_3381 : _GEN_197; // @[Conditional.scala 39:67] - wire _GEN_210 = _T_3400 ? _T_3381 : _GEN_203; // @[Conditional.scala 39:67] - wire _GEN_220 = _T_3367 ? _T_3381 : _GEN_210; // @[Conditional.scala 39:67] - wire _GEN_230 = _T_3363 ? _T_3158 : _GEN_220; // @[Conditional.scala 39:67] - wire buf_state_en_1 = _T_3340 ? _T_3356 : _GEN_230; // @[Conditional.scala 40:58] - wire _T_1947 = _T_1430 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_1957 = _T_1575 & _T_1680; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_1959 = _T_1957 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_1960 = _T_1572 | _T_1959; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_1964 = _T_1582 & _T_3350; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_1966 = _T_1964 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_1967 = _T_1960 | _T_1966; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_1968 = _T_1947 & _T_1967; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_1992 = _T_1604 | _T_1959; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_1999 = _T_1992 | _T_1966; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_0 = _T_1947 & _T_1999; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_0 = buf_rspageQ_1_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2054 = _T_1957 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2055 = _T_1667 | _T_2054; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2061 = _T_1964 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2062 = _T_2055 | _T_2061; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2063 = _T_1947 & _T_2062; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2087 = _T_1699 | _T_2054; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2094 = _T_2087 | _T_2061; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_1 = _T_1947 & _T_2094; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_1 = buf_rspageQ_1_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2149 = _T_1957 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2150 = _T_1762 | _T_2149; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2156 = _T_1964 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2157 = _T_2150 | _T_2156; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2158 = _T_1947 & _T_2157; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2182 = _T_1794 | _T_2149; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2189 = _T_2182 | _T_2156; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_2 = _T_1947 & _T_2189; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_2 = buf_rspageQ_1_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2244 = _T_1957 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2245 = _T_1857 | _T_2244; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2251 = _T_1964 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2252 = _T_2245 | _T_2251; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2253 = _T_1947 & _T_2252; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2277 = _T_1889 | _T_2244; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2284 = _T_2277 | _T_2251; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_1_3 = _T_1947 & _T_2284; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_1_3 = buf_rspageQ_1_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3556 = _T_3138 & _T_1775; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3558 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3559 = _T_3141 & _T_3558; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3560 = _T_3556 | _T_3559; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3561 = _T_906 & _T_3560; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3563 = ibuf_drain_vld & _T_1768; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3564 = _T_3561 | _T_3563; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3608 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3633 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3634 = bus_rsp_write & _T_3633; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3635 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_482 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3636 = io_lsu_axi_rid == _GEN_482; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3637 = buf_ldfwd_2 & _T_3636; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3638 = _T_3635 | _T_3637; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3639 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3640 = ~buf_write_2; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3641 = _T_3639 & _T_3640; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3642 = _T_3641 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_373 = {{1'd0}, buf_dualtag_1}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3839 = io_lsu_axi_rid == _GEN_373; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_3840 = _T_3838 & _T_3839; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_3841 = _T_3833 | _T_3840; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_3842 = bus_rsp_read & _T_3841; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_3843 = _T_3828 | _T_3842; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_118 = _T_3782 & _T_3843; // @[Conditional.scala 39:67] + wire _GEN_137 = _T_3748 ? 1'h0 : _GEN_118; // @[Conditional.scala 39:67] + wire _GEN_149 = _T_3744 ? 1'h0 : _GEN_137; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_149; // @[Conditional.scala 40:58] + wire _T_3869 = 3'h4 == buf_state_1; // @[Conditional.scala 37:30] + wire [3:0] _T_3879 = buf_ldfwd >> buf_dualtag_1; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_99 = 2'h1 == buf_dualtag_1 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_100 = 2'h2 == buf_dualtag_1 ? buf_ldfwdtag_2 : _GEN_99; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_101 = 2'h3 == buf_dualtag_1 ? buf_ldfwdtag_3 : _GEN_100; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_375 = {{1'd0}, _GEN_101}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3881 = io_lsu_axi_rid == _GEN_375; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_3882 = _T_3879[0] & _T_3881; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_3883 = _T_3839 | _T_3882; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_3884 = bus_rsp_read & _T_3883; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_112 = _T_3869 & _T_3884; // @[Conditional.scala 39:67] + wire _GEN_119 = _T_3782 ? buf_resp_state_bus_en_1 : _GEN_112; // @[Conditional.scala 39:67] + wire _GEN_129 = _T_3748 ? buf_cmd_state_bus_en_1 : _GEN_119; // @[Conditional.scala 39:67] + wire _GEN_142 = _T_3744 ? 1'h0 : _GEN_129; // @[Conditional.scala 39:67] + wire buf_state_bus_en_1 = _T_3721 ? 1'h0 : _GEN_142; // @[Conditional.scala 40:58] + wire _T_3761 = buf_state_bus_en_1 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3762 = _T_3761 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_3887 = 3'h5 == buf_state_1; // @[Conditional.scala 37:30] + wire _T_3890 = RspPtr == 2'h1; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_3891 = buf_dualtag_1 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_3892 = buf_dual_1 & _T_3891; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_3893 = _T_3890 | _T_3892; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_3894 = _T_3893 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_3895 = 3'h6 == buf_state_1; // @[Conditional.scala 37:30] + wire _GEN_107 = _T_3887 ? _T_3894 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_113 = _T_3869 ? _T_3762 : _GEN_107; // @[Conditional.scala 39:67] + wire _GEN_120 = _T_3782 ? _T_3762 : _GEN_113; // @[Conditional.scala 39:67] + wire _GEN_130 = _T_3748 ? _T_3762 : _GEN_120; // @[Conditional.scala 39:67] + wire _GEN_140 = _T_3744 ? _T_3554 : _GEN_130; // @[Conditional.scala 39:67] + wire buf_state_en_1 = _T_3721 ? _T_3737 : _GEN_140; // @[Conditional.scala 40:58] + wire _T_2231 = _T_1864 & buf_state_en_1; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2241 = _T_2137 & _T_1867; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2243 = _T_2241 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2244 = _T_4471 | _T_2243; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2248 = _T_2144 & _T_1868; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2250 = _T_2248 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2251 = _T_2244 | _T_2250; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2252 = _T_2231 & _T_2251; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2254 = _T_2252 | buf_age_1[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2268 = _T_2241 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2269 = _T_4476 | _T_2268; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2275 = _T_2248 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2276 = _T_2269 | _T_2275; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2277 = _T_2231 & _T_2276; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2279 = _T_2277 | buf_age_1[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2293 = _T_2241 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2294 = _T_4481 | _T_2293; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2300 = _T_2248 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2301 = _T_2294 | _T_2300; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2302 = _T_2231 & _T_2301; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2304 = _T_2302 | buf_age_1[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2318 = _T_2241 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2319 = _T_4486 | _T_2318; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2325 = _T_2248 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2326 = _T_2319 | _T_2325; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2327 = _T_2231 & _T_2326; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2329 = _T_2327 | buf_age_1[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2331 = {_T_2329,_T_2304,_T_2279}; // @[Cat.scala 29:58] + wire _T_3921 = 2'h2 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_3922 = _T_3534 & _T_3921; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_3924 = 2'h2 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_3925 = _T_3537 & _T_3924; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_3926 = _T_3922 | _T_3925; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_3927 = _T_853 & _T_3926; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_3928 = 2'h2 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_3929 = ibuf_drain_vld & _T_3928; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_3930 = _T_3927 | _T_3929; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_3975 = 3'h3 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4020 = io_lsu_axi_bid == 3'h2; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4021 = bus_rsp_write & _T_4020; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4022 = io_lsu_axi_rid == 3'h2; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_376 = {{1'd0}, buf_ldfwdtag_2}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4024 = io_lsu_axi_rid == _GEN_376; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4025 = buf_ldfwd[2] & _T_4024; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4026 = _T_4022 | _T_4025; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4027 = buf_dual_2 & buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4029 = ~buf_write[2]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4030 = _T_4027 & _T_4029; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4031 = _T_4030 & buf_samedw_2; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_2; // @[Reg.scala 27:20] - wire [2:0] _GEN_483 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3643 = io_lsu_axi_rid == _GEN_483; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3644 = _T_3642 & _T_3643; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3645 = _T_3638 | _T_3644; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3646 = bus_rsp_read & _T_3645; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3647 = _T_3634 | _T_3646; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_298 = _T_3608 & _T_3647; // @[Conditional.scala 39:67] - wire _GEN_317 = _T_3575 ? 1'h0 : _GEN_298; // @[Conditional.scala 39:67] - wire _GEN_329 = _T_3571 ? 1'h0 : _GEN_317; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_329; // @[Conditional.scala 40:58] - wire _T_3672 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] - wire _GEN_275 = 2'h1 == buf_dualtag_2 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_276 = 2'h2 == buf_dualtag_2 ? buf_ldfwd_2 : _GEN_275; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_277 = 2'h3 == buf_dualtag_2 ? buf_ldfwd_3 : _GEN_276; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_279 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_280 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_279; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_281 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_280; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_485 = {{1'd0}, _GEN_281}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3679 = io_lsu_axi_rid == _GEN_485; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3680 = _GEN_277 & _T_3679; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3681 = _T_3643 | _T_3680; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3682 = bus_rsp_read & _T_3681; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_292 = _T_3672 & _T_3682; // @[Conditional.scala 39:67] - wire _GEN_299 = _T_3608 ? buf_resp_state_bus_en_2 : _GEN_292; // @[Conditional.scala 39:67] - wire _GEN_309 = _T_3575 ? buf_cmd_state_bus_en_2 : _GEN_299; // @[Conditional.scala 39:67] - wire _GEN_322 = _T_3571 ? 1'h0 : _GEN_309; // @[Conditional.scala 39:67] - wire buf_state_bus_en_2 = _T_3548 ? 1'h0 : _GEN_322; // @[Conditional.scala 40:58] - wire _T_3588 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3589 = _T_3588 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3685 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] - wire _T_3688 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3689 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3690 = buf_dual_2 & _T_3689; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3691 = _T_3688 | _T_3690; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3692 = _T_3691 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3693 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] - wire _GEN_287 = _T_3685 ? _T_3692 : _T_3693; // @[Conditional.scala 39:67] - wire _GEN_293 = _T_3672 ? _T_3589 : _GEN_287; // @[Conditional.scala 39:67] - wire _GEN_300 = _T_3608 ? _T_3589 : _GEN_293; // @[Conditional.scala 39:67] - wire _GEN_310 = _T_3575 ? _T_3589 : _GEN_300; // @[Conditional.scala 39:67] - wire _GEN_320 = _T_3571 ? _T_3158 : _GEN_310; // @[Conditional.scala 39:67] - wire buf_state_en_2 = _T_3548 ? _T_3564 : _GEN_320; // @[Conditional.scala 40:58] - wire _T_2327 = _T_1442 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_2337 = _T_1575 & _T_1775; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_2339 = _T_2337 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2340 = _T_1572 | _T_2339; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2344 = _T_1582 & _T_3558; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_2346 = _T_2344 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2347 = _T_2340 | _T_2346; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2348 = _T_2327 & _T_2347; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2372 = _T_1604 | _T_2339; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2379 = _T_2372 | _T_2346; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_0 = _T_2327 & _T_2379; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_0 = buf_rspageQ_2_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2434 = _T_2337 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2435 = _T_1667 | _T_2434; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2441 = _T_2344 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2442 = _T_2435 | _T_2441; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2443 = _T_2327 & _T_2442; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2467 = _T_1699 | _T_2434; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2474 = _T_2467 | _T_2441; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_1 = _T_2327 & _T_2474; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_1 = buf_rspageQ_2_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2529 = _T_2337 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2530 = _T_1762 | _T_2529; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2536 = _T_2344 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2537 = _T_2530 | _T_2536; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2538 = _T_2327 & _T_2537; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2562 = _T_1794 | _T_2529; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2569 = _T_2562 | _T_2536; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_2 = _T_2327 & _T_2569; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_2 = buf_rspageQ_2_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2624 = _T_2337 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2625 = _T_1857 | _T_2624; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2631 = _T_2344 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2632 = _T_2625 | _T_2631; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2633 = _T_2327 & _T_2632; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2657 = _T_1889 | _T_2624; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2664 = _T_2657 | _T_2631; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_2_3 = _T_2327 & _T_2664; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_2_3 = buf_rspageQ_2_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3764 = _T_3138 & _T_1870; // @[el2_lsu_bus_buffer.scala 617:118] - wire _T_3766 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 617:172] - wire _T_3767 = _T_3141 & _T_3766; // @[el2_lsu_bus_buffer.scala 617:167] - wire _T_3768 = _T_3764 | _T_3767; // @[el2_lsu_bus_buffer.scala 617:138] - wire _T_3769 = _T_906 & _T_3768; // @[el2_lsu_bus_buffer.scala 617:69] - wire _T_3771 = ibuf_drain_vld & _T_1863; // @[el2_lsu_bus_buffer.scala 617:207] - wire _T_3772 = _T_3769 | _T_3771; // @[el2_lsu_bus_buffer.scala 617:189] - wire _T_3816 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3841 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 642:76] - wire _T_3842 = bus_rsp_write & _T_3841; // @[el2_lsu_bus_buffer.scala 642:55] - wire _T_3843 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 643:78] - wire [2:0] _GEN_486 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3844 = io_lsu_axi_rid == _GEN_486; // @[el2_lsu_bus_buffer.scala 644:80] - wire _T_3845 = buf_ldfwd_3 & _T_3844; // @[el2_lsu_bus_buffer.scala 644:60] - wire _T_3846 = _T_3843 | _T_3845; // @[el2_lsu_bus_buffer.scala 643:113] - wire _T_3847 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 645:62] - wire _T_3848 = ~buf_write_3; // @[el2_lsu_bus_buffer.scala 645:80] - wire _T_3849 = _T_3847 & _T_3848; // @[el2_lsu_bus_buffer.scala 645:78] - wire _T_3850 = _T_3849 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 645:94] + wire [2:0] _GEN_377 = {{1'd0}, buf_dualtag_2}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4032 = io_lsu_axi_rid == _GEN_377; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4033 = _T_4031 & _T_4032; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4034 = _T_4026 | _T_4033; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4035 = bus_rsp_read & _T_4034; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4036 = _T_4021 | _T_4035; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_194 = _T_3975 & _T_4036; // @[Conditional.scala 39:67] + wire _GEN_213 = _T_3941 ? 1'h0 : _GEN_194; // @[Conditional.scala 39:67] + wire _GEN_225 = _T_3937 ? 1'h0 : _GEN_213; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_225; // @[Conditional.scala 40:58] + wire _T_4062 = 3'h4 == buf_state_2; // @[Conditional.scala 37:30] + wire [3:0] _T_4072 = buf_ldfwd >> buf_dualtag_2; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_175 = 2'h1 == buf_dualtag_2 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_176 = 2'h2 == buf_dualtag_2 ? buf_ldfwdtag_2 : _GEN_175; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_177 = 2'h3 == buf_dualtag_2 ? buf_ldfwdtag_3 : _GEN_176; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_379 = {{1'd0}, _GEN_177}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4074 = io_lsu_axi_rid == _GEN_379; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4075 = _T_4072[0] & _T_4074; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4076 = _T_4032 | _T_4075; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4077 = bus_rsp_read & _T_4076; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_188 = _T_4062 & _T_4077; // @[Conditional.scala 39:67] + wire _GEN_195 = _T_3975 ? buf_resp_state_bus_en_2 : _GEN_188; // @[Conditional.scala 39:67] + wire _GEN_205 = _T_3941 ? buf_cmd_state_bus_en_2 : _GEN_195; // @[Conditional.scala 39:67] + wire _GEN_218 = _T_3937 ? 1'h0 : _GEN_205; // @[Conditional.scala 39:67] + wire buf_state_bus_en_2 = _T_3914 ? 1'h0 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_3954 = buf_state_bus_en_2 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_3955 = _T_3954 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4080 = 3'h5 == buf_state_2; // @[Conditional.scala 37:30] + wire _T_4083 = RspPtr == 2'h2; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4084 = buf_dualtag_2 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4085 = buf_dual_2 & _T_4084; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4086 = _T_4083 | _T_4085; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4087 = _T_4086 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4088 = 3'h6 == buf_state_2; // @[Conditional.scala 37:30] + wire _GEN_183 = _T_4080 ? _T_4087 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_189 = _T_4062 ? _T_3955 : _GEN_183; // @[Conditional.scala 39:67] + wire _GEN_196 = _T_3975 ? _T_3955 : _GEN_189; // @[Conditional.scala 39:67] + wire _GEN_206 = _T_3941 ? _T_3955 : _GEN_196; // @[Conditional.scala 39:67] + wire _GEN_216 = _T_3937 ? _T_3554 : _GEN_206; // @[Conditional.scala 39:67] + wire buf_state_en_2 = _T_3914 ? _T_3930 : _GEN_216; // @[Conditional.scala 40:58] + wire _T_2333 = _T_1875 & buf_state_en_2; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2343 = _T_2137 & _T_1878; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2345 = _T_2343 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2346 = _T_4471 | _T_2345; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2350 = _T_2144 & _T_1879; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2352 = _T_2350 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2353 = _T_2346 | _T_2352; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2354 = _T_2333 & _T_2353; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2356 = _T_2354 | buf_age_2[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2370 = _T_2343 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2371 = _T_4476 | _T_2370; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2377 = _T_2350 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2378 = _T_2371 | _T_2377; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2379 = _T_2333 & _T_2378; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2381 = _T_2379 | buf_age_2[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2395 = _T_2343 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2396 = _T_4481 | _T_2395; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2402 = _T_2350 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2403 = _T_2396 | _T_2402; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2404 = _T_2333 & _T_2403; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2406 = _T_2404 | buf_age_2[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2420 = _T_2343 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2421 = _T_4486 | _T_2420; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2427 = _T_2350 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2428 = _T_2421 | _T_2427; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2429 = _T_2333 & _T_2428; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2431 = _T_2429 | buf_age_2[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2433 = {_T_2431,_T_2406,_T_2381}; // @[Cat.scala 29:58] + wire _T_4114 = 2'h3 == WrPtr0_r; // @[el2_lsu_bus_buffer.scala 497:117] + wire _T_4115 = _T_3534 & _T_4114; // @[el2_lsu_bus_buffer.scala 497:112] + wire _T_4117 = 2'h3 == WrPtr1_r; // @[el2_lsu_bus_buffer.scala 497:166] + wire _T_4118 = _T_3537 & _T_4117; // @[el2_lsu_bus_buffer.scala 497:161] + wire _T_4119 = _T_4115 | _T_4118; // @[el2_lsu_bus_buffer.scala 497:132] + wire _T_4120 = _T_853 & _T_4119; // @[el2_lsu_bus_buffer.scala 497:63] + wire _T_4121 = 2'h3 == ibuf_tag; // @[el2_lsu_bus_buffer.scala 497:206] + wire _T_4122 = ibuf_drain_vld & _T_4121; // @[el2_lsu_bus_buffer.scala 497:201] + wire _T_4123 = _T_4120 | _T_4122; // @[el2_lsu_bus_buffer.scala 497:183] + wire _T_4168 = 3'h3 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4213 = io_lsu_axi_bid == 3'h3; // @[el2_lsu_bus_buffer.scala 522:73] + wire _T_4214 = bus_rsp_write & _T_4213; // @[el2_lsu_bus_buffer.scala 522:52] + wire _T_4215 = io_lsu_axi_rid == 3'h3; // @[el2_lsu_bus_buffer.scala 523:46] + wire [2:0] _GEN_380 = {{1'd0}, buf_ldfwdtag_3}; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4217 = io_lsu_axi_rid == _GEN_380; // @[el2_lsu_bus_buffer.scala 524:47] + wire _T_4218 = buf_ldfwd[3] & _T_4217; // @[el2_lsu_bus_buffer.scala 524:27] + wire _T_4219 = _T_4215 | _T_4218; // @[el2_lsu_bus_buffer.scala 523:77] + wire _T_4220 = buf_dual_3 & buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 525:26] + wire _T_4222 = ~buf_write[3]; // @[el2_lsu_bus_buffer.scala 525:44] + wire _T_4223 = _T_4220 & _T_4222; // @[el2_lsu_bus_buffer.scala 525:42] + wire _T_4224 = _T_4223 & buf_samedw_3; // @[el2_lsu_bus_buffer.scala 525:58] reg [1:0] buf_dualtag_3; // @[Reg.scala 27:20] - wire [2:0] _GEN_487 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3851 = io_lsu_axi_rid == _GEN_487; // @[el2_lsu_bus_buffer.scala 645:130] - wire _T_3852 = _T_3850 & _T_3851; // @[el2_lsu_bus_buffer.scala 645:110] - wire _T_3853 = _T_3846 | _T_3852; // @[el2_lsu_bus_buffer.scala 644:104] - wire _T_3854 = bus_rsp_read & _T_3853; // @[el2_lsu_bus_buffer.scala 643:57] - wire _T_3855 = _T_3842 | _T_3854; // @[el2_lsu_bus_buffer.scala 642:112] - wire _GEN_388 = _T_3816 & _T_3855; // @[Conditional.scala 39:67] - wire _GEN_407 = _T_3783 ? 1'h0 : _GEN_388; // @[Conditional.scala 39:67] - wire _GEN_419 = _T_3779 ? 1'h0 : _GEN_407; // @[Conditional.scala 39:67] - wire buf_resp_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_419; // @[Conditional.scala 40:58] - wire _T_3880 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] - wire _GEN_365 = 2'h1 == buf_dualtag_3 ? buf_ldfwd_1 : buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_366 = 2'h2 == buf_dualtag_3 ? buf_ldfwd_2 : _GEN_365; // @[el2_lsu_bus_buffer.scala 641:136] - wire _GEN_367 = 2'h3 == buf_dualtag_3 ? buf_ldfwd_3 : _GEN_366; // @[el2_lsu_bus_buffer.scala 641:136] - wire [1:0] _GEN_369 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_370 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_369; // @[el2_lsu_bus_buffer.scala 657:87] - wire [1:0] _GEN_371 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_370; // @[el2_lsu_bus_buffer.scala 657:87] - wire [2:0] _GEN_489 = {{1'd0}, _GEN_371}; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3887 = io_lsu_axi_rid == _GEN_489; // @[el2_lsu_bus_buffer.scala 657:87] - wire _T_3888 = _GEN_367 & _T_3887; // @[el2_lsu_bus_buffer.scala 657:67] - wire _T_3889 = _T_3851 | _T_3888; // @[el2_lsu_bus_buffer.scala 656:100] - wire _T_3890 = bus_rsp_read & _T_3889; // @[el2_lsu_bus_buffer.scala 656:50] - wire _GEN_382 = _T_3880 & _T_3890; // @[Conditional.scala 39:67] - wire _GEN_389 = _T_3816 ? buf_resp_state_bus_en_3 : _GEN_382; // @[Conditional.scala 39:67] - wire _GEN_399 = _T_3783 ? buf_cmd_state_bus_en_3 : _GEN_389; // @[Conditional.scala 39:67] - wire _GEN_412 = _T_3779 ? 1'h0 : _GEN_399; // @[Conditional.scala 39:67] - wire buf_state_bus_en_3 = _T_3756 ? 1'h0 : _GEN_412; // @[Conditional.scala 40:58] - wire _T_3796 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 630:61] - wire _T_3797 = _T_3796 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 630:82] - wire _T_3893 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] - wire _T_3896 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 662:43] - wire _T_3897 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 662:103] - wire _T_3898 = buf_dual_3 & _T_3897; // @[el2_lsu_bus_buffer.scala 662:85] - wire _T_3899 = _T_3896 | _T_3898; // @[el2_lsu_bus_buffer.scala 662:71] - wire _T_3900 = _T_3899 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 662:117] - wire _T_3901 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] - wire _GEN_377 = _T_3893 ? _T_3900 : _T_3901; // @[Conditional.scala 39:67] - wire _GEN_383 = _T_3880 ? _T_3797 : _GEN_377; // @[Conditional.scala 39:67] - wire _GEN_390 = _T_3816 ? _T_3797 : _GEN_383; // @[Conditional.scala 39:67] - wire _GEN_400 = _T_3783 ? _T_3797 : _GEN_390; // @[Conditional.scala 39:67] - wire _GEN_410 = _T_3779 ? _T_3158 : _GEN_400; // @[Conditional.scala 39:67] - wire buf_state_en_3 = _T_3756 ? _T_3772 : _GEN_410; // @[Conditional.scala 40:58] - wire _T_2707 = _T_1454 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 562:60] - wire _T_2717 = _T_1575 & _T_1870; // @[el2_lsu_bus_buffer.scala 564:73] - wire _T_2719 = _T_2717 & _T_3146; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2720 = _T_1572 | _T_2719; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2724 = _T_1582 & _T_3766; // @[el2_lsu_bus_buffer.scala 565:54] - wire _T_2726 = _T_2724 & _T_3139; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2727 = _T_2720 | _T_2726; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2728 = _T_2707 & _T_2727; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2752 = _T_1604 | _T_2719; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2759 = _T_2752 | _T_2726; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_0 = _T_2707 & _T_2759; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_0 = buf_rspageQ_3_0 & _T_1625; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2814 = _T_2717 & _T_1673; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2815 = _T_1667 | _T_2814; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2821 = _T_2724 & _T_1680; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2822 = _T_2815 | _T_2821; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2823 = _T_2707 & _T_2822; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2847 = _T_1699 | _T_2814; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2854 = _T_2847 | _T_2821; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_1 = _T_2707 & _T_2854; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_1 = buf_rspageQ_3_1 & _T_1720; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_2909 = _T_2717 & _T_1768; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_2910 = _T_1762 | _T_2909; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_2916 = _T_2724 & _T_1775; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_2917 = _T_2910 | _T_2916; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_2918 = _T_2707 & _T_2917; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_2942 = _T_1794 | _T_2909; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_2949 = _T_2942 | _T_2916; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_2 = _T_2707 & _T_2949; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_2 = buf_rspageQ_3_2 & _T_1815; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3004 = _T_2717 & _T_1863; // @[el2_lsu_bus_buffer.scala 564:92] - wire _T_3005 = _T_1857 | _T_3004; // @[el2_lsu_bus_buffer.scala 563:93] - wire _T_3011 = _T_2724 & _T_1870; // @[el2_lsu_bus_buffer.scala 565:73] - wire _T_3012 = _T_3005 | _T_3011; // @[el2_lsu_bus_buffer.scala 564:113] - wire _T_3013 = _T_2707 & _T_3012; // @[el2_lsu_bus_buffer.scala 562:79] - wire _T_3037 = _T_1889 | _T_3004; // @[el2_lsu_bus_buffer.scala 570:139] - wire _T_3044 = _T_3037 | _T_3011; // @[el2_lsu_bus_buffer.scala 571:110] - wire buf_rspage_set_3_3 = _T_2707 & _T_3044; // @[el2_lsu_bus_buffer.scala 570:78] - wire buf_rspage_3_3 = buf_rspageQ_3_3 & _T_1910; // @[el2_lsu_bus_buffer.scala 574:50] - wire _T_3115 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 605:77] - wire _T_3161 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 627:101] - wire _T_3163 = _T_3161 & _T_1178; // @[el2_lsu_bus_buffer.scala 627:116] - wire _T_3175 = buf_state_en_0 & _T_3224; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3176 = _T_3175 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3178 = _T_3176 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3181 = _T_3172 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3182 = _T_3181 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_4329 = io_lsu_axi_rresp != 2'h0; // @[el2_lsu_bus_buffer.scala 744:70] - wire bus_rsp_read_error = bus_rsp_read & _T_4329; // @[el2_lsu_bus_buffer.scala 744:45] - wire _T_3185 = _T_3181 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3238 = bus_rsp_read_error & _T_3219; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3239 = bus_rsp_read_error & buf_ldfwd_0; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3241 = _T_3239 & _T_3220; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3242 = _T_3238 | _T_3241; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_4326 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 743:70] - wire bus_rsp_write_error = bus_rsp_write & _T_4326; // @[el2_lsu_bus_buffer.scala 743:45] - wire _T_3245 = bus_rsp_write_error & _T_3217; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3246 = _T_3242 | _T_3245; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3247 = _T_3172 & _T_3246; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_122 = _T_3192 & _T_3247; // @[Conditional.scala 39:67] - wire _GEN_135 = _T_3159 ? _T_3185 : _GEN_122; // @[Conditional.scala 39:67] - wire _GEN_147 = _T_3155 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] - wire buf_error_en_0 = _T_3132 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] - wire _T_3194 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 639:85] - wire _T_3195 = buf_write_0 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3196 = io_dec_tlu_force_halt | _T_3195; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3198 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3199 = buf_dual_0 & _T_3198; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3201 = _T_3199 & _T_3224; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_91 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_92 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_91; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_93 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_92; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3202 = _GEN_93 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3203 = _T_3201 & _T_3202; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_4013 = _T_1627 | _T_1722; // @[el2_lsu_bus_buffer.scala 701:158] - wire _T_4014 = _T_4013 | _T_1817; // @[el2_lsu_bus_buffer.scala 701:158] - wire any_done_wait_state = _T_4014 | _T_1912; // @[el2_lsu_bus_buffer.scala 701:158] - wire _T_3204 = buf_ldfwd_0 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3209 = _T_3201 & _GEN_97; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3210 = _GEN_93 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3211 = _T_3209 & _T_3210; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3212 = _T_3211 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3213 = _T_3204 | _T_3212; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3234 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3235 = _T_3234 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3248 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3249 = buf_state_en_0 & _T_3248; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3258 = buf_ldfwd_0 | _GEN_97; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3259 = _T_3258 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_105 = _T_3277 & buf_state_en_0; // @[Conditional.scala 39:67] - wire _GEN_108 = _T_3269 ? 1'h0 : _T_3277; // @[Conditional.scala 39:67] - wire _GEN_110 = _T_3269 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] - wire _GEN_114 = _T_3256 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] - wire _GEN_116 = _T_3256 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] - wire _GEN_121 = _T_3192 & _T_3235; // @[Conditional.scala 39:67] - wire _GEN_124 = _T_3192 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] - wire _GEN_126 = _T_3192 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] - wire _GEN_132 = _T_3159 ? _T_3178 : _GEN_126; // @[Conditional.scala 39:67] - wire _GEN_134 = _T_3159 ? _T_3182 : _GEN_121; // @[Conditional.scala 39:67] - wire _GEN_138 = _T_3159 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] - wire _GEN_144 = _T_3155 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] - wire _GEN_146 = _T_3155 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] - wire _GEN_150 = _T_3155 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] - wire buf_wr_en_0 = _T_3132 & buf_state_en_0; // @[Conditional.scala 40:58] - wire buf_data_en_0 = _T_3132 ? buf_state_en_0 : _GEN_146; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_0 = _T_3132 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] - wire buf_rst_0 = _T_3132 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] - reg buf_unsign_0; // @[Reg.scala 27:20] - wire _T_3293 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3294 = buf_error_en_0 | buf_rst_0; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_0; // @[Reg.scala 27:20] - wire _T_3383 = buf_state_en_1 & _T_3432; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3384 = _T_3383 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3386 = _T_3384 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3389 = _T_3380 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3390 = _T_3389 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3393 = _T_3389 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3446 = bus_rsp_read_error & _T_3427; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3447 = bus_rsp_read_error & buf_ldfwd_1; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3449 = _T_3447 & _T_3428; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3450 = _T_3446 | _T_3449; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3453 = bus_rsp_write_error & _T_3425; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3454 = _T_3450 | _T_3453; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3455 = _T_3380 & _T_3454; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_212 = _T_3400 & _T_3455; // @[Conditional.scala 39:67] - wire _GEN_225 = _T_3367 ? _T_3393 : _GEN_212; // @[Conditional.scala 39:67] - wire _GEN_237 = _T_3363 ? 1'h0 : _GEN_225; // @[Conditional.scala 39:67] - wire buf_error_en_1 = _T_3340 ? 1'h0 : _GEN_237; // @[Conditional.scala 40:58] - wire _T_3403 = buf_write_1 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3404 = io_dec_tlu_force_halt | _T_3403; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3406 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3407 = buf_dual_1 & _T_3406; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3409 = _T_3407 & _T_3432; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_181 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_182 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_181; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_183 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_182; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3410 = _GEN_183 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3411 = _T_3409 & _T_3410; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3412 = buf_ldfwd_1 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3417 = _T_3409 & _GEN_187; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3418 = _GEN_183 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3419 = _T_3417 & _T_3418; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3420 = _T_3419 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3421 = _T_3412 | _T_3420; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3442 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3443 = _T_3442 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3456 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3457 = buf_state_en_1 & _T_3456; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3466 = buf_ldfwd_1 | _GEN_187; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3467 = _T_3466 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_195 = _T_3485 & buf_state_en_1; // @[Conditional.scala 39:67] - wire _GEN_198 = _T_3477 ? 1'h0 : _T_3485; // @[Conditional.scala 39:67] - wire _GEN_200 = _T_3477 ? 1'h0 : _GEN_195; // @[Conditional.scala 39:67] - wire _GEN_204 = _T_3464 ? 1'h0 : _GEN_198; // @[Conditional.scala 39:67] - wire _GEN_206 = _T_3464 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] - wire _GEN_211 = _T_3400 & _T_3443; // @[Conditional.scala 39:67] - wire _GEN_214 = _T_3400 ? 1'h0 : _GEN_204; // @[Conditional.scala 39:67] - wire _GEN_216 = _T_3400 ? 1'h0 : _GEN_206; // @[Conditional.scala 39:67] - wire _GEN_222 = _T_3367 ? _T_3386 : _GEN_216; // @[Conditional.scala 39:67] - wire _GEN_224 = _T_3367 ? _T_3390 : _GEN_211; // @[Conditional.scala 39:67] - wire _GEN_228 = _T_3367 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] - wire _GEN_234 = _T_3363 ? 1'h0 : _GEN_222; // @[Conditional.scala 39:67] - wire _GEN_236 = _T_3363 ? 1'h0 : _GEN_224; // @[Conditional.scala 39:67] - wire _GEN_240 = _T_3363 ? 1'h0 : _GEN_228; // @[Conditional.scala 39:67] - wire buf_wr_en_1 = _T_3340 & buf_state_en_1; // @[Conditional.scala 40:58] - wire buf_data_en_1 = _T_3340 ? buf_state_en_1 : _GEN_236; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_1 = _T_3340 ? 1'h0 : _GEN_234; // @[Conditional.scala 40:58] - wire buf_rst_1 = _T_3340 ? 1'h0 : _GEN_240; // @[Conditional.scala 40:58] - reg buf_unsign_1; // @[Reg.scala 27:20] - wire _T_3501 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3502 = buf_error_en_1 | buf_rst_1; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_1; // @[Reg.scala 27:20] - wire _T_3591 = buf_state_en_2 & _T_3640; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3592 = _T_3591 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3594 = _T_3592 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3597 = _T_3588 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3598 = _T_3597 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3601 = _T_3597 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3654 = bus_rsp_read_error & _T_3635; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3655 = bus_rsp_read_error & buf_ldfwd_2; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3657 = _T_3655 & _T_3636; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3658 = _T_3654 | _T_3657; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3661 = bus_rsp_write_error & _T_3633; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3662 = _T_3658 | _T_3661; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3663 = _T_3588 & _T_3662; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_302 = _T_3608 & _T_3663; // @[Conditional.scala 39:67] - wire _GEN_315 = _T_3575 ? _T_3601 : _GEN_302; // @[Conditional.scala 39:67] - wire _GEN_327 = _T_3571 ? 1'h0 : _GEN_315; // @[Conditional.scala 39:67] - wire buf_error_en_2 = _T_3548 ? 1'h0 : _GEN_327; // @[Conditional.scala 40:58] - wire _T_3611 = buf_write_2 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3612 = io_dec_tlu_force_halt | _T_3611; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3614 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3615 = buf_dual_2 & _T_3614; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3617 = _T_3615 & _T_3640; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_271 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_272 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_271; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_273 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_272; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3618 = _GEN_273 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3619 = _T_3617 & _T_3618; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3620 = buf_ldfwd_2 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3625 = _T_3617 & _GEN_277; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3626 = _GEN_273 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3627 = _T_3625 & _T_3626; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3628 = _T_3627 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3629 = _T_3620 | _T_3628; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3650 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3651 = _T_3650 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3664 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3665 = buf_state_en_2 & _T_3664; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3674 = buf_ldfwd_2 | _GEN_277; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3675 = _T_3674 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_285 = _T_3693 & buf_state_en_2; // @[Conditional.scala 39:67] - wire _GEN_288 = _T_3685 ? 1'h0 : _T_3693; // @[Conditional.scala 39:67] - wire _GEN_290 = _T_3685 ? 1'h0 : _GEN_285; // @[Conditional.scala 39:67] - wire _GEN_294 = _T_3672 ? 1'h0 : _GEN_288; // @[Conditional.scala 39:67] - wire _GEN_296 = _T_3672 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] - wire _GEN_301 = _T_3608 & _T_3651; // @[Conditional.scala 39:67] - wire _GEN_304 = _T_3608 ? 1'h0 : _GEN_294; // @[Conditional.scala 39:67] - wire _GEN_306 = _T_3608 ? 1'h0 : _GEN_296; // @[Conditional.scala 39:67] - wire _GEN_312 = _T_3575 ? _T_3594 : _GEN_306; // @[Conditional.scala 39:67] - wire _GEN_314 = _T_3575 ? _T_3598 : _GEN_301; // @[Conditional.scala 39:67] - wire _GEN_318 = _T_3575 ? 1'h0 : _GEN_304; // @[Conditional.scala 39:67] - wire _GEN_324 = _T_3571 ? 1'h0 : _GEN_312; // @[Conditional.scala 39:67] - wire _GEN_326 = _T_3571 ? 1'h0 : _GEN_314; // @[Conditional.scala 39:67] - wire _GEN_330 = _T_3571 ? 1'h0 : _GEN_318; // @[Conditional.scala 39:67] - wire buf_wr_en_2 = _T_3548 & buf_state_en_2; // @[Conditional.scala 40:58] - wire buf_data_en_2 = _T_3548 ? buf_state_en_2 : _GEN_326; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_2 = _T_3548 ? 1'h0 : _GEN_324; // @[Conditional.scala 40:58] - wire buf_rst_2 = _T_3548 ? 1'h0 : _GEN_330; // @[Conditional.scala 40:58] - reg buf_unsign_2; // @[Reg.scala 27:20] - wire _T_3709 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3710 = buf_error_en_2 | buf_rst_2; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_2; // @[Reg.scala 27:20] - wire _T_3799 = buf_state_en_3 & _T_3848; // @[el2_lsu_bus_buffer.scala 632:56] - wire _T_3800 = _T_3799 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 632:72] - wire _T_3802 = _T_3800 & _T_1194; // @[el2_lsu_bus_buffer.scala 632:86] - wire _T_3805 = _T_3796 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 634:80] - wire _T_3806 = _T_3805 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 634:94] - wire _T_3809 = _T_3805 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 635:94] - wire _T_3862 = bus_rsp_read_error & _T_3843; // @[el2_lsu_bus_buffer.scala 649:103] - wire _T_3863 = bus_rsp_read_error & buf_ldfwd_3; // @[el2_lsu_bus_buffer.scala 650:63] - wire _T_3865 = _T_3863 & _T_3844; // @[el2_lsu_bus_buffer.scala 650:78] - wire _T_3866 = _T_3862 | _T_3865; // @[el2_lsu_bus_buffer.scala 649:160] - wire _T_3869 = bus_rsp_write_error & _T_3841; // @[el2_lsu_bus_buffer.scala 651:89] - wire _T_3870 = _T_3866 | _T_3869; // @[el2_lsu_bus_buffer.scala 650:120] - wire _T_3871 = _T_3796 & _T_3870; // @[el2_lsu_bus_buffer.scala 649:80] - wire _GEN_392 = _T_3816 & _T_3871; // @[Conditional.scala 39:67] - wire _GEN_405 = _T_3783 ? _T_3809 : _GEN_392; // @[Conditional.scala 39:67] - wire _GEN_417 = _T_3779 ? 1'h0 : _GEN_405; // @[Conditional.scala 39:67] - wire buf_error_en_3 = _T_3756 ? 1'h0 : _GEN_417; // @[Conditional.scala 40:58] - wire _T_3819 = buf_write_3 & _T_3194; // @[el2_lsu_bus_buffer.scala 639:83] - wire _T_3820 = io_dec_tlu_force_halt | _T_3819; // @[el2_lsu_bus_buffer.scala 639:67] - wire _T_3822 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 640:62] - wire _T_3823 = buf_dual_3 & _T_3822; // @[el2_lsu_bus_buffer.scala 640:60] - wire _T_3825 = _T_3823 & _T_3848; // @[el2_lsu_bus_buffer.scala 640:78] - wire [2:0] _GEN_361 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_362 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_361; // @[el2_lsu_bus_buffer.scala 640:123] - wire [2:0] _GEN_363 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_362; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3826 = _GEN_363 != 3'h4; // @[el2_lsu_bus_buffer.scala 640:123] - wire _T_3827 = _T_3825 & _T_3826; // @[el2_lsu_bus_buffer.scala 640:95] - wire _T_3828 = buf_ldfwd_3 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:64] - wire _T_3833 = _T_3825 & _GEN_367; // @[el2_lsu_bus_buffer.scala 641:136] - wire _T_3834 = _GEN_363 == 3'h4; // @[el2_lsu_bus_buffer.scala 641:193] - wire _T_3835 = _T_3833 & _T_3834; // @[el2_lsu_bus_buffer.scala 641:164] - wire _T_3836 = _T_3835 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 641:213] - wire _T_3837 = _T_3828 | _T_3836; // @[el2_lsu_bus_buffer.scala 641:86] - wire _T_3858 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 648:60] - wire _T_3859 = _T_3858 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 648:75] - wire _T_3872 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 652:63] - wire _T_3873 = buf_state_en_3 & _T_3872; // @[el2_lsu_bus_buffer.scala 652:61] - wire _T_3882 = buf_ldfwd_3 | _GEN_367; // @[el2_lsu_bus_buffer.scala 655:99] - wire _T_3883 = _T_3882 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 655:127] - wire _GEN_375 = _T_3901 & buf_state_en_3; // @[Conditional.scala 39:67] - wire _GEN_378 = _T_3893 ? 1'h0 : _T_3901; // @[Conditional.scala 39:67] - wire _GEN_380 = _T_3893 ? 1'h0 : _GEN_375; // @[Conditional.scala 39:67] - wire _GEN_384 = _T_3880 ? 1'h0 : _GEN_378; // @[Conditional.scala 39:67] - wire _GEN_386 = _T_3880 ? 1'h0 : _GEN_380; // @[Conditional.scala 39:67] - wire _GEN_391 = _T_3816 & _T_3859; // @[Conditional.scala 39:67] - wire _GEN_394 = _T_3816 ? 1'h0 : _GEN_384; // @[Conditional.scala 39:67] - wire _GEN_396 = _T_3816 ? 1'h0 : _GEN_386; // @[Conditional.scala 39:67] - wire _GEN_402 = _T_3783 ? _T_3802 : _GEN_396; // @[Conditional.scala 39:67] - wire _GEN_404 = _T_3783 ? _T_3806 : _GEN_391; // @[Conditional.scala 39:67] - wire _GEN_408 = _T_3783 ? 1'h0 : _GEN_394; // @[Conditional.scala 39:67] - wire _GEN_414 = _T_3779 ? 1'h0 : _GEN_402; // @[Conditional.scala 39:67] - wire _GEN_416 = _T_3779 ? 1'h0 : _GEN_404; // @[Conditional.scala 39:67] - wire _GEN_420 = _T_3779 ? 1'h0 : _GEN_408; // @[Conditional.scala 39:67] - wire buf_wr_en_3 = _T_3756 & buf_state_en_3; // @[Conditional.scala 40:58] - wire buf_data_en_3 = _T_3756 ? buf_state_en_3 : _GEN_416; // @[Conditional.scala 40:58] - wire buf_ldfwd_en_3 = _T_3756 ? 1'h0 : _GEN_414; // @[Conditional.scala 40:58] - wire buf_rst_3 = _T_3756 ? 1'h0 : _GEN_420; // @[Conditional.scala 40:58] - reg buf_unsign_3; // @[Reg.scala 27:20] - wire _T_3917 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 689:44] - wire _T_3918 = buf_error_en_3 | buf_rst_3; // @[el2_lsu_bus_buffer.scala 689:99] - reg buf_error_3; // @[Reg.scala 27:20] - wire [1:0] _GEN_494 = {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 696:45] - wire [1:0] _T_3925 = _GEN_494 << io_ldst_dual_m; // @[el2_lsu_bus_buffer.scala 696:45] - wire [1:0] _GEN_495 = {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 696:83] - wire [1:0] _T_3926 = _GEN_495 << io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 696:83] - wire [1:0] _T_3928 = _T_3925 + _T_3926; // @[el2_lsu_bus_buffer.scala 696:64] - wire [1:0] _GEN_496 = {{1'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 696:102] - wire [1:0] _T_3930 = _T_3928 + _GEN_496; // @[el2_lsu_bus_buffer.scala 696:102] - wire _T_3936 = _T_56 + _T_63; // @[el2_lsu_bus_buffer.scala 697:158] - wire _T_3938 = _T_3936 + _T_70; // @[el2_lsu_bus_buffer.scala 697:158] - wire _T_3940 = _T_3938 + _T_77; // @[el2_lsu_bus_buffer.scala 697:158] - wire [1:0] _GEN_497 = {{1'd0}, _T_3940}; // @[el2_lsu_bus_buffer.scala 696:115] - wire [1:0] _T_3942 = _T_3930 + _GEN_497; // @[el2_lsu_bus_buffer.scala 696:115] - wire _T_4017 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 704:60] - wire [3:0] buf_numvld_any = {{2'd0}, _T_3942}; // @[el2_lsu_bus_buffer.scala 696:25] - wire _T_4019 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 704:106] - wire _T_4021 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 704:152] - wire [2:0] _T_4023 = buf_state_0 | buf_state_1; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4024 = _T_4023 | buf_state_2; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4025 = _T_4024 | buf_state_3; // @[el2_lsu_bus_buffer.scala 705:97] - wire [2:0] _T_4026 = ~_T_4025; // @[el2_lsu_bus_buffer.scala 705:40] - wire [2:0] _GEN_498 = {{2'd0}, _T_903}; // @[el2_lsu_bus_buffer.scala 705:102] - wire [2:0] _T_4028 = _T_4026 & _GEN_498; // @[el2_lsu_bus_buffer.scala 705:102] - wire [2:0] _GEN_499 = {{2'd0}, _T_1146}; // @[el2_lsu_bus_buffer.scala 705:116] - wire [2:0] _T_4030 = _T_4028 & _GEN_499; // @[el2_lsu_bus_buffer.scala 705:116] - wire _T_4031 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 707:56] - wire _T_4032 = _T_4031 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 707:77] - wire _T_4033 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 707:99] - wire _T_4034 = _T_4032 & _T_4033; // @[el2_lsu_bus_buffer.scala 707:97] - wire _T_4035 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 707:116] - wire _T_4038 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 709:68] - reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 752:44] - wire _T_4053 = _T_1602 & _T_3224; // @[Mux.scala 27:72] - wire _T_4054 = _T_1697 & _T_3432; // @[Mux.scala 27:72] - wire _T_4055 = _T_1792 & _T_3640; // @[Mux.scala 27:72] - wire _T_4056 = _T_1887 & _T_3848; // @[Mux.scala 27:72] - wire _T_4057 = _T_4053 | _T_4054; // @[Mux.scala 27:72] - wire _T_4058 = _T_4057 | _T_4055; // @[Mux.scala 27:72] - wire lsu_nonblock_load_data_ready = _T_4058 | _T_4056; // @[Mux.scala 27:72] - wire _T_4073 = _T_4053 & buf_error_0; // @[Mux.scala 27:72] - wire _T_4074 = _T_4054 & buf_error_1; // @[Mux.scala 27:72] - wire _T_4075 = _T_4055 & buf_error_2; // @[Mux.scala 27:72] - wire _T_4076 = _T_4056 & buf_error_3; // @[Mux.scala 27:72] - wire _T_4077 = _T_4073 | _T_4074; // @[Mux.scala 27:72] - wire _T_4078 = _T_4077 | _T_4075; // @[Mux.scala 27:72] - wire _T_4082 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4083 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4084 = _T_4082 | _T_4083; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4089 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4090 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4091 = _T_4089 | _T_4090; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4092 = _T_1697 & _T_4091; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4094 = _T_4092 & _T_3432; // @[el2_lsu_bus_buffer.scala 714:129] - wire _T_4096 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4097 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4098 = _T_4096 | _T_4097; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4099 = _T_1792 & _T_4098; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4101 = _T_4099 & _T_3640; // @[el2_lsu_bus_buffer.scala 714:129] - wire _T_4103 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 714:98] - wire _T_4104 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 714:113] - wire _T_4105 = _T_4103 | _T_4104; // @[el2_lsu_bus_buffer.scala 714:111] - wire _T_4106 = _T_1887 & _T_4105; // @[el2_lsu_bus_buffer.scala 714:95] - wire _T_4108 = _T_4106 & _T_3848; // @[el2_lsu_bus_buffer.scala 714:129] - wire [1:0] _T_4111 = _T_4101 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_4112 = _T_4108 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_500 = {{1'd0}, _T_4094}; // @[Mux.scala 27:72] - wire [1:0] _T_4114 = _GEN_500 | _T_4111; // @[Mux.scala 27:72] - wire _T_4123 = _T_4053 & _T_4084; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4130 = _T_4054 & _T_4091; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4137 = _T_4055 & _T_4098; // @[el2_lsu_bus_buffer.scala 715:111] - wire _T_4144 = _T_4056 & _T_4105; // @[el2_lsu_bus_buffer.scala 715:111] - wire [31:0] _T_4145 = _T_4123 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4146 = _T_4130 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4147 = _T_4137 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4148 = _T_4144 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4149 = _T_4145 | _T_4146; // @[Mux.scala 27:72] - wire [31:0] _T_4150 = _T_4149 | _T_4147; // @[Mux.scala 27:72] - wire [31:0] lsu_nonblock_load_data_lo = _T_4150 | _T_4148; // @[Mux.scala 27:72] - wire _T_4157 = _T_4053 & _T_3223; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4162 = _T_4054 & _T_3431; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4167 = _T_4055 & _T_3639; // @[el2_lsu_bus_buffer.scala 716:111] - wire _T_4172 = _T_4056 & _T_3847; // @[el2_lsu_bus_buffer.scala 716:111] - wire [31:0] _T_4173 = _T_4157 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4174 = _T_4162 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4175 = _T_4167 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4176 = _T_4172 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4177 = _T_4173 | _T_4174; // @[Mux.scala 27:72] - wire [31:0] _T_4178 = _T_4177 | _T_4175; // @[Mux.scala 27:72] - wire [31:0] lsu_nonblock_load_data_hi = _T_4178 | _T_4176; // @[Mux.scala 27:72] - wire [31:0] _GEN_451 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 718:79] - wire [31:0] _GEN_452 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_451; // @[el2_lsu_bus_buffer.scala 718:79] - wire [31:0] _GEN_453 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_452; // @[el2_lsu_bus_buffer.scala 718:79] - wire [1:0] lsu_nonblock_addr_offset = _GEN_453[1:0]; // @[el2_lsu_bus_buffer.scala 718:79] - wire [1:0] _GEN_455 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_sz_1 : buf_sz_0; // @[el2_lsu_bus_buffer.scala 719:77] - wire [1:0] _GEN_456 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_sz_2 : _GEN_455; // @[el2_lsu_bus_buffer.scala 719:77] - wire [1:0] lsu_nonblock_sz = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_sz_3 : _GEN_456; // @[el2_lsu_bus_buffer.scala 719:77] - wire _GEN_459 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_unsign_1 : buf_unsign_0; // @[el2_lsu_bus_buffer.scala 720:37] - wire _GEN_460 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_unsign_2 : _GEN_459; // @[el2_lsu_bus_buffer.scala 720:37] - wire lsu_nonblock_unsign = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_unsign_3 : _GEN_460; // @[el2_lsu_bus_buffer.scala 720:37] - wire [63:0] _T_4185 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] - wire [3:0] _GEN_501 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 722:115] - wire [5:0] _T_4187 = 4'h8 * _GEN_501; // @[el2_lsu_bus_buffer.scala 722:115] - wire [63:0] _T_4188 = _T_4185 >> _T_4187; // @[el2_lsu_bus_buffer.scala 722:111] - wire [31:0] lsu_nonblock_data_unalgn = _T_4188[31:0]; // @[el2_lsu_bus_buffer.scala 722:146] - wire _T_4190 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 723:71] - wire _T_4192 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 725:83] - wire _T_4193 = lsu_nonblock_unsign & _T_4192; // @[el2_lsu_bus_buffer.scala 725:65] - wire [31:0] _T_4196 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4197 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 726:83] - wire _T_4198 = lsu_nonblock_unsign & _T_4197; // @[el2_lsu_bus_buffer.scala 726:65] - wire [31:0] _T_4201 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4202 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 727:44] - wire _T_4204 = _T_4202 & _T_4192; // @[el2_lsu_bus_buffer.scala 727:65] - wire [23:0] _T_4207 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_4209 = {_T_4207,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] - wire _T_4212 = _T_4202 & _T_4197; // @[el2_lsu_bus_buffer.scala 728:65] - wire [15:0] _T_4215 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] - wire [31:0] _T_4217 = {_T_4215,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] - wire _T_4218 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 729:83] - wire _T_4219 = lsu_nonblock_unsign & _T_4218; // @[el2_lsu_bus_buffer.scala 729:65] - wire [31:0] _T_4221 = _T_4193 ? _T_4196 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4222 = _T_4198 ? _T_4201 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4223 = _T_4204 ? _T_4209 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4224 = _T_4212 ? _T_4217 : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4225 = _T_4219 ? lsu_nonblock_data_unalgn : 32'h0; // @[Mux.scala 27:72] - wire [31:0] _T_4226 = _T_4221 | _T_4222; // @[Mux.scala 27:72] - wire [31:0] _T_4227 = _T_4226 | _T_4223; // @[Mux.scala 27:72] - wire [31:0] _T_4228 = _T_4227 | _T_4224; // @[Mux.scala 27:72] - wire _T_4334 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 749:64] - wire _T_4335 = io_lsu_busreq_m & _T_4334; // @[el2_lsu_bus_buffer.scala 749:62] - reg _T_4338; // @[el2_lsu_bus_buffer.scala 749:44] - wire _T_4360 = _T_1697 & buf_error_1; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4361 = _T_4360 & buf_write_1; // @[el2_lsu_bus_buffer.scala 775:114] - wire _T_4363 = _T_1792 & buf_error_2; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4364 = _T_4363 & buf_write_2; // @[el2_lsu_bus_buffer.scala 775:114] - wire _T_4366 = _T_1887 & buf_error_3; // @[el2_lsu_bus_buffer.scala 775:99] - wire _T_4367 = _T_4366 & buf_write_3; // @[el2_lsu_bus_buffer.scala 775:114] - wire [1:0] _T_4370 = _T_4364 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _T_4371 = _T_4367 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] - wire [1:0] _GEN_502 = {{1'd0}, _T_4361}; // @[Mux.scala 27:72] - wire [1:0] _T_4373 = _GEN_502 | _T_4370; // @[Mux.scala 27:72] - wire [1:0] lsu_imprecise_error_store_tag = _T_4373 | _T_4371; // @[Mux.scala 27:72] - wire _T_4376 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 776:74] - wire _T_4379 = io_lsu_bus_clk_en_q & _T_1602; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4380 = _T_4379 & buf_error_0; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4381 = _T_4380 & buf_write_0; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4383 = io_lsu_bus_clk_en_q & _T_1697; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4384 = _T_4383 & buf_error_1; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4385 = _T_4384 & buf_write_1; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4387 = io_lsu_bus_clk_en_q & _T_1792; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4388 = _T_4387 & buf_error_2; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4389 = _T_4388 & buf_write_2; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4391 = io_lsu_bus_clk_en_q & _T_1887; // @[el2_lsu_bus_buffer.scala 777:91] - wire _T_4392 = _T_4391 & buf_error_3; // @[el2_lsu_bus_buffer.scala 777:119] - wire _T_4393 = _T_4392 & buf_write_3; // @[el2_lsu_bus_buffer.scala 777:134] - wire _T_4394 = _T_4381 | _T_4385; // @[el2_lsu_bus_buffer.scala 777:158] - wire _T_4395 = _T_4394 | _T_4389; // @[el2_lsu_bus_buffer.scala 777:158] - wire [31:0] _GEN_468 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 778:43] - wire [31:0] _GEN_469 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_468; // @[el2_lsu_bus_buffer.scala 778:43] - wire [31:0] _GEN_470 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_469; // @[el2_lsu_bus_buffer.scala 778:43] - wire _T_4400 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 786:82] - wire _T_4403 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 787:56] - wire _T_4406 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 789:62] - wire _T_4407 = io_lsu_axi_awvalid & _T_4406; // @[el2_lsu_bus_buffer.scala 789:60] - wire _T_4408 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 789:105] - wire _T_4409 = io_lsu_axi_wvalid & _T_4408; // @[el2_lsu_bus_buffer.scala 789:103] - wire _T_4410 = _T_4407 | _T_4409; // @[el2_lsu_bus_buffer.scala 789:82] - wire _T_4411 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 789:149] - wire _T_4412 = io_lsu_axi_arvalid & _T_4411; // @[el2_lsu_bus_buffer.scala 789:147] - wire _T_4414 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 791:51] - wire _T_4415 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 791:66] - wire _T_4416 = _T_4414 & _T_4415; // @[el2_lsu_bus_buffer.scala 791:64] - wire [31:0] _T_4420 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] - wire [2:0] _T_4423 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] - wire _T_4427 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 803:66] - wire _T_4428 = _T_4414 & _T_4427; // @[el2_lsu_bus_buffer.scala 803:64] - wire [7:0] _T_4432 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] - wire _T_4435 = obuf_valid & _T_1170; // @[el2_lsu_bus_buffer.scala 808:51] - wire _T_4437 = _T_4435 & _T_1176; // @[el2_lsu_bus_buffer.scala 808:65] - assign io_lsu_busreq_r = _T_4338; // @[el2_lsu_bus_buffer.scala 749:34] - assign io_lsu_bus_buffer_pend_any = buf_numvld_pend_any != 4'h0; // @[el2_lsu_bus_buffer.scala 703:37] - assign io_lsu_bus_buffer_full_any = _T_4017 ? _T_4019 : _T_4021; // @[el2_lsu_bus_buffer.scala 704:37] - assign io_lsu_bus_buffer_empty_any = _T_4030[0]; // @[el2_lsu_bus_buffer.scala 705:37] - assign io_ld_byte_hit_buf_lo = {_T_127,_T_116}; // @[el2_lsu_bus_buffer.scala 412:28] - assign io_ld_byte_hit_buf_hi = {_T_127,_T_116}; // @[el2_lsu_bus_buffer.scala 413:28] - assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4376; // @[el2_lsu_bus_buffer.scala 776:37] - assign io_lsu_imprecise_error_store_any = _T_4395 | _T_4393; // @[el2_lsu_bus_buffer.scala 777:37] - assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_470 : _GEN_453; // @[el2_lsu_bus_buffer.scala 778:37] - assign io_lsu_nonblock_load_valid_m = _T_4034 & _T_4035; // @[el2_lsu_bus_buffer.scala 707:37] - assign io_lsu_nonblock_load_tag_m = _T_1428 ? 2'h0 : _T_1468; // @[el2_lsu_bus_buffer.scala 708:37] - assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4038; // @[el2_lsu_bus_buffer.scala 709:37] - assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 710:37] - assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4190; // @[el2_lsu_bus_buffer.scala 723:37] - assign io_lsu_nonblock_load_data_error = _T_4078 | _T_4076; // @[el2_lsu_bus_buffer.scala 713:37] - assign io_lsu_nonblock_load_data_tag = _T_4114 | _T_4112; // @[el2_lsu_bus_buffer.scala 714:37] - assign io_lsu_nonblock_load_data = _T_4228 | _T_4225; // @[el2_lsu_bus_buffer.scala 724:37] - assign io_lsu_pmu_bus_trxn = _T_4400 | _T_4319; // @[el2_lsu_bus_buffer.scala 786:37] - assign io_lsu_pmu_bus_misaligned = _T_4403 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 787:37] - assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 788:37] - assign io_lsu_pmu_bus_busy = _T_4410 | _T_4412; // @[el2_lsu_bus_buffer.scala 789:37] - assign io_lsu_axi_awvalid = _T_4416 & _T_1154; // @[el2_lsu_bus_buffer.scala 791:37] - assign io_lsu_axi_awid = obuf_tag0; // @[el2_lsu_bus_buffer.scala 792:37] - assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4420; // @[el2_lsu_bus_buffer.scala 793:37] - assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 794:37] - assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4423 : 3'h3; // @[el2_lsu_bus_buffer.scala 796:37] - assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 799:37] - assign io_lsu_axi_wvalid = _T_4428 & _T_1154; // @[el2_lsu_bus_buffer.scala 803:37] - assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 804:37] - assign io_lsu_axi_wstrb = obuf_byteen & _T_4432; // @[el2_lsu_bus_buffer.scala 805:37] - assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 820:37] - assign io_lsu_axi_arvalid = _T_4437 & _T_1154; // @[el2_lsu_bus_buffer.scala 808:37] - assign io_lsu_axi_arid = obuf_tag0; // @[el2_lsu_bus_buffer.scala 809:37] - assign io_lsu_axi_araddr = io_lsu_axi_awaddr; // @[el2_lsu_bus_buffer.scala 810:37] - assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 811:37] - assign io_lsu_axi_arsize = io_lsu_axi_awsize; // @[el2_lsu_bus_buffer.scala 813:37] - assign io_lsu_axi_arcache = io_lsu_axi_awcache; // @[el2_lsu_bus_buffer.scala 816:37] - assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 821:37] + wire [2:0] _GEN_381 = {{1'd0}, buf_dualtag_3}; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4225 = io_lsu_axi_rid == _GEN_381; // @[el2_lsu_bus_buffer.scala 525:94] + wire _T_4226 = _T_4224 & _T_4225; // @[el2_lsu_bus_buffer.scala 525:74] + wire _T_4227 = _T_4219 | _T_4226; // @[el2_lsu_bus_buffer.scala 524:71] + wire _T_4228 = bus_rsp_read & _T_4227; // @[el2_lsu_bus_buffer.scala 523:25] + wire _T_4229 = _T_4214 | _T_4228; // @[el2_lsu_bus_buffer.scala 522:105] + wire _GEN_270 = _T_4168 & _T_4229; // @[Conditional.scala 39:67] + wire _GEN_289 = _T_4134 ? 1'h0 : _GEN_270; // @[Conditional.scala 39:67] + wire _GEN_301 = _T_4130 ? 1'h0 : _GEN_289; // @[Conditional.scala 39:67] + wire buf_resp_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_301; // @[Conditional.scala 40:58] + wire _T_4255 = 3'h4 == buf_state_3; // @[Conditional.scala 37:30] + wire [3:0] _T_4265 = buf_ldfwd >> buf_dualtag_3; // @[el2_lsu_bus_buffer.scala 537:21] + wire [1:0] _GEN_251 = 2'h1 == buf_dualtag_3 ? buf_ldfwdtag_1 : buf_ldfwdtag_0; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_252 = 2'h2 == buf_dualtag_3 ? buf_ldfwdtag_2 : _GEN_251; // @[el2_lsu_bus_buffer.scala 537:58] + wire [1:0] _GEN_253 = 2'h3 == buf_dualtag_3 ? buf_ldfwdtag_3 : _GEN_252; // @[el2_lsu_bus_buffer.scala 537:58] + wire [2:0] _GEN_383 = {{1'd0}, _GEN_253}; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4267 = io_lsu_axi_rid == _GEN_383; // @[el2_lsu_bus_buffer.scala 537:58] + wire _T_4268 = _T_4265[0] & _T_4267; // @[el2_lsu_bus_buffer.scala 537:38] + wire _T_4269 = _T_4225 | _T_4268; // @[el2_lsu_bus_buffer.scala 536:95] + wire _T_4270 = bus_rsp_read & _T_4269; // @[el2_lsu_bus_buffer.scala 536:45] + wire _GEN_264 = _T_4255 & _T_4270; // @[Conditional.scala 39:67] + wire _GEN_271 = _T_4168 ? buf_resp_state_bus_en_3 : _GEN_264; // @[Conditional.scala 39:67] + wire _GEN_281 = _T_4134 ? buf_cmd_state_bus_en_3 : _GEN_271; // @[Conditional.scala 39:67] + wire _GEN_294 = _T_4130 ? 1'h0 : _GEN_281; // @[Conditional.scala 39:67] + wire buf_state_bus_en_3 = _T_4107 ? 1'h0 : _GEN_294; // @[Conditional.scala 40:58] + wire _T_4147 = buf_state_bus_en_3 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 510:49] + wire _T_4148 = _T_4147 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 510:70] + wire _T_4273 = 3'h5 == buf_state_3; // @[Conditional.scala 37:30] + wire _T_4276 = RspPtr == 2'h3; // @[el2_lsu_bus_buffer.scala 542:37] + wire _T_4277 = buf_dualtag_3 == RspPtr; // @[el2_lsu_bus_buffer.scala 542:98] + wire _T_4278 = buf_dual_3 & _T_4277; // @[el2_lsu_bus_buffer.scala 542:80] + wire _T_4279 = _T_4276 | _T_4278; // @[el2_lsu_bus_buffer.scala 542:65] + wire _T_4280 = _T_4279 | io_dec_tlu_force_halt; // @[el2_lsu_bus_buffer.scala 542:112] + wire _T_4281 = 3'h6 == buf_state_3; // @[Conditional.scala 37:30] + wire _GEN_259 = _T_4273 ? _T_4280 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_265 = _T_4255 ? _T_4148 : _GEN_259; // @[Conditional.scala 39:67] + wire _GEN_272 = _T_4168 ? _T_4148 : _GEN_265; // @[Conditional.scala 39:67] + wire _GEN_282 = _T_4134 ? _T_4148 : _GEN_272; // @[Conditional.scala 39:67] + wire _GEN_292 = _T_4130 ? _T_3554 : _GEN_282; // @[Conditional.scala 39:67] + wire buf_state_en_3 = _T_4107 ? _T_4123 : _GEN_292; // @[Conditional.scala 40:58] + wire _T_2435 = _T_1886 & buf_state_en_3; // @[el2_lsu_bus_buffer.scala 459:94] + wire _T_2445 = _T_2137 & _T_1889; // @[el2_lsu_bus_buffer.scala 461:71] + wire _T_2447 = _T_2445 & _T_1854; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2448 = _T_4471 | _T_2447; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2452 = _T_2144 & _T_1890; // @[el2_lsu_bus_buffer.scala 462:52] + wire _T_2454 = _T_2452 & _T_1856; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2455 = _T_2448 | _T_2454; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2456 = _T_2435 & _T_2455; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2458 = _T_2456 | buf_age_3[0]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2472 = _T_2445 & _T_1865; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2473 = _T_4476 | _T_2472; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2479 = _T_2452 & _T_1867; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2480 = _T_2473 | _T_2479; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2481 = _T_2435 & _T_2480; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2483 = _T_2481 | buf_age_3[1]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2497 = _T_2445 & _T_1876; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2498 = _T_4481 | _T_2497; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2504 = _T_2452 & _T_1878; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2505 = _T_2498 | _T_2504; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2506 = _T_2435 & _T_2505; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2508 = _T_2506 | buf_age_3[2]; // @[el2_lsu_bus_buffer.scala 462:97] + wire _T_2522 = _T_2445 & _T_1887; // @[el2_lsu_bus_buffer.scala 461:92] + wire _T_2523 = _T_4486 | _T_2522; // @[el2_lsu_bus_buffer.scala 460:86] + wire _T_2529 = _T_2452 & _T_1889; // @[el2_lsu_bus_buffer.scala 462:73] + wire _T_2530 = _T_2523 | _T_2529; // @[el2_lsu_bus_buffer.scala 461:114] + wire _T_2531 = _T_2435 & _T_2530; // @[el2_lsu_bus_buffer.scala 459:113] + wire _T_2533 = _T_2531 | buf_age_3[3]; // @[el2_lsu_bus_buffer.scala 462:97] + wire [2:0] _T_2535 = {_T_2533,_T_2508,_T_2483}; // @[Cat.scala 29:58] + wire _T_2799 = buf_state_0 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2800 = _T_1853 | _T_2799; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2801 = ~_T_2800; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2809 = _T_2801 | _T_2141; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2816 = _T_2809 | _T_2148; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2817 = _T_2129 & _T_2816; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2821 = buf_state_1 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2822 = _T_1864 | _T_2821; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2823 = ~_T_2822; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2831 = _T_2823 | _T_2166; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2838 = _T_2831 | _T_2173; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2839 = _T_2129 & _T_2838; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2843 = buf_state_2 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2844 = _T_1875 | _T_2843; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2845 = ~_T_2844; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2853 = _T_2845 | _T_2191; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2860 = _T_2853 | _T_2198; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2861 = _T_2129 & _T_2860; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2865 = buf_state_3 == 3'h6; // @[el2_lsu_bus_buffer.scala 470:47] + wire _T_2866 = _T_1886 | _T_2865; // @[el2_lsu_bus_buffer.scala 470:32] + wire _T_2867 = ~_T_2866; // @[el2_lsu_bus_buffer.scala 470:6] + wire _T_2875 = _T_2867 | _T_2216; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2882 = _T_2875 | _T_2223; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2883 = _T_2129 & _T_2882; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_0 = {_T_2883,_T_2861,_T_2839,_T_2817}; // @[Cat.scala 29:58] + wire _T_2900 = _T_2801 | _T_2243; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2907 = _T_2900 | _T_2250; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2908 = _T_2231 & _T_2907; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2922 = _T_2823 | _T_2268; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2929 = _T_2922 | _T_2275; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2930 = _T_2231 & _T_2929; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2944 = _T_2845 | _T_2293; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2951 = _T_2944 | _T_2300; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2952 = _T_2231 & _T_2951; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_2966 = _T_2867 | _T_2318; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2973 = _T_2966 | _T_2325; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2974 = _T_2231 & _T_2973; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_1 = {_T_2974,_T_2952,_T_2930,_T_2908}; // @[Cat.scala 29:58] + wire _T_2991 = _T_2801 | _T_2345; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_2998 = _T_2991 | _T_2352; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_2999 = _T_2333 & _T_2998; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3013 = _T_2823 | _T_2370; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3020 = _T_3013 | _T_2377; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3021 = _T_2333 & _T_3020; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3035 = _T_2845 | _T_2395; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3042 = _T_3035 | _T_2402; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3043 = _T_2333 & _T_3042; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3057 = _T_2867 | _T_2420; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3064 = _T_3057 | _T_2427; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3065 = _T_2333 & _T_3064; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_2 = {_T_3065,_T_3043,_T_3021,_T_2999}; // @[Cat.scala 29:58] + wire _T_3082 = _T_2801 | _T_2447; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3089 = _T_3082 | _T_2454; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3090 = _T_2435 & _T_3089; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3104 = _T_2823 | _T_2472; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3111 = _T_3104 | _T_2479; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3112 = _T_2435 & _T_3111; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3126 = _T_2845 | _T_2497; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3133 = _T_3126 | _T_2504; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3134 = _T_2435 & _T_3133; // @[el2_lsu_bus_buffer.scala 469:112] + wire _T_3148 = _T_2867 | _T_2522; // @[el2_lsu_bus_buffer.scala 470:59] + wire _T_3155 = _T_3148 | _T_2529; // @[el2_lsu_bus_buffer.scala 471:110] + wire _T_3156 = _T_2435 & _T_3155; // @[el2_lsu_bus_buffer.scala 469:112] + wire [3:0] buf_rspage_set_3 = {_T_3156,_T_3134,_T_3112,_T_3090}; // @[Cat.scala 29:58] + wire _T_3241 = _T_2865 | _T_1886; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3242 = ~_T_3241; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3243 = buf_rspageQ_0[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3235 = _T_2843 | _T_1875; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3236 = ~_T_3235; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3237 = buf_rspageQ_0[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3229 = _T_2821 | _T_1864; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3230 = ~_T_3229; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3231 = buf_rspageQ_0[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3223 = _T_2799 | _T_1853; // @[el2_lsu_bus_buffer.scala 474:110] + wire _T_3224 = ~_T_3223; // @[el2_lsu_bus_buffer.scala 474:84] + wire _T_3225 = buf_rspageQ_0[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_0 = {_T_3243,_T_3237,_T_3231,_T_3225}; // @[Cat.scala 29:58] + wire _T_3162 = buf_rspage_set_0[0] | buf_rspage_0[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3165 = buf_rspage_set_0[1] | buf_rspage_0[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3168 = buf_rspage_set_0[2] | buf_rspage_0[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3171 = buf_rspage_set_0[3] | buf_rspage_0[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3173 = {_T_3171,_T_3168,_T_3165}; // @[Cat.scala 29:58] + wire _T_3270 = buf_rspageQ_1[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3264 = buf_rspageQ_1[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3258 = buf_rspageQ_1[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3252 = buf_rspageQ_1[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_1 = {_T_3270,_T_3264,_T_3258,_T_3252}; // @[Cat.scala 29:58] + wire _T_3177 = buf_rspage_set_1[0] | buf_rspage_1[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3180 = buf_rspage_set_1[1] | buf_rspage_1[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3183 = buf_rspage_set_1[2] | buf_rspage_1[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3186 = buf_rspage_set_1[3] | buf_rspage_1[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3188 = {_T_3186,_T_3183,_T_3180}; // @[Cat.scala 29:58] + wire _T_3297 = buf_rspageQ_2[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3291 = buf_rspageQ_2[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3285 = buf_rspageQ_2[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3279 = buf_rspageQ_2[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_2 = {_T_3297,_T_3291,_T_3285,_T_3279}; // @[Cat.scala 29:58] + wire _T_3192 = buf_rspage_set_2[0] | buf_rspage_2[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3195 = buf_rspage_set_2[1] | buf_rspage_2[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3198 = buf_rspage_set_2[2] | buf_rspage_2[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3201 = buf_rspage_set_2[3] | buf_rspage_2[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3203 = {_T_3201,_T_3198,_T_3195}; // @[Cat.scala 29:58] + wire _T_3324 = buf_rspageQ_3[3] & _T_3242; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3318 = buf_rspageQ_3[2] & _T_3236; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3312 = buf_rspageQ_3[1] & _T_3230; // @[el2_lsu_bus_buffer.scala 474:82] + wire _T_3306 = buf_rspageQ_3[0] & _T_3224; // @[el2_lsu_bus_buffer.scala 474:82] + wire [3:0] buf_rspage_3 = {_T_3324,_T_3318,_T_3312,_T_3306}; // @[Cat.scala 29:58] + wire _T_3207 = buf_rspage_set_3[0] | buf_rspage_3[0]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3210 = buf_rspage_set_3[1] | buf_rspage_3[1]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3213 = buf_rspage_set_3[2] | buf_rspage_3[2]; // @[el2_lsu_bus_buffer.scala 473:88] + wire _T_3216 = buf_rspage_set_3[3] | buf_rspage_3[3]; // @[el2_lsu_bus_buffer.scala 473:88] + wire [2:0] _T_3218 = {_T_3216,_T_3213,_T_3210}; // @[Cat.scala 29:58] + wire _T_3329 = ibuf_drain_vld & _T_1854; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3331 = ibuf_drain_vld & _T_1865; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3333 = ibuf_drain_vld & _T_1876; // @[el2_lsu_bus_buffer.scala 479:63] + wire _T_3335 = ibuf_drain_vld & _T_1887; // @[el2_lsu_bus_buffer.scala 479:63] + wire [3:0] ibuf_drainvec_vld = {_T_3335,_T_3333,_T_3331,_T_3329}; // @[Cat.scala 29:58] + wire _T_3343 = _T_3537 & _T_1857; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3352 = _T_3537 & _T_1868; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3361 = _T_3537 & _T_1879; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3370 = _T_3537 & _T_1890; // @[el2_lsu_bus_buffer.scala 481:35] + wire _T_3400 = ibuf_drainvec_vld[0] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3402 = ibuf_drainvec_vld[1] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3404 = ibuf_drainvec_vld[2] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire _T_3406 = ibuf_drainvec_vld[3] ? ibuf_dual : io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 483:45] + wire [3:0] buf_dual_in = {_T_3406,_T_3404,_T_3402,_T_3400}; // @[Cat.scala 29:58] + wire _T_3411 = ibuf_drainvec_vld[0] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3413 = ibuf_drainvec_vld[1] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3415 = ibuf_drainvec_vld[2] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire _T_3417 = ibuf_drainvec_vld[3] ? ibuf_samedw : ldst_samedw_r; // @[el2_lsu_bus_buffer.scala 484:47] + wire [3:0] buf_samedw_in = {_T_3417,_T_3415,_T_3413,_T_3411}; // @[Cat.scala 29:58] + wire _T_3422 = ibuf_nomerge | ibuf_force_drain; // @[el2_lsu_bus_buffer.scala 485:84] + wire _T_3423 = ibuf_drainvec_vld[0] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3426 = ibuf_drainvec_vld[1] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3429 = ibuf_drainvec_vld[2] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire _T_3432 = ibuf_drainvec_vld[3] ? _T_3422 : io_no_dword_merge_r; // @[el2_lsu_bus_buffer.scala 485:48] + wire [3:0] buf_nomerge_in = {_T_3432,_T_3429,_T_3426,_T_3423}; // @[Cat.scala 29:58] + wire _T_3440 = ibuf_drainvec_vld[0] ? ibuf_dual : _T_3343; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3445 = ibuf_drainvec_vld[1] ? ibuf_dual : _T_3352; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3450 = ibuf_drainvec_vld[2] ? ibuf_dual : _T_3361; // @[el2_lsu_bus_buffer.scala 486:47] + wire _T_3455 = ibuf_drainvec_vld[3] ? ibuf_dual : _T_3370; // @[el2_lsu_bus_buffer.scala 486:47] + wire [3:0] buf_dualhi_in = {_T_3455,_T_3450,_T_3445,_T_3440}; // @[Cat.scala 29:58] + wire _T_3484 = ibuf_drainvec_vld[0] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3486 = ibuf_drainvec_vld[1] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3488 = ibuf_drainvec_vld[2] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire _T_3490 = ibuf_drainvec_vld[3] ? ibuf_sideeffect : io_is_sideeffects_r; // @[el2_lsu_bus_buffer.scala 488:51] + wire [3:0] buf_sideeffect_in = {_T_3490,_T_3488,_T_3486,_T_3484}; // @[Cat.scala 29:58] + wire _T_3495 = ibuf_drainvec_vld[0] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3497 = ibuf_drainvec_vld[1] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3499 = ibuf_drainvec_vld[2] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire _T_3501 = ibuf_drainvec_vld[3] ? ibuf_unsign : io_lsu_pkt_r_unsign; // @[el2_lsu_bus_buffer.scala 489:47] + wire [3:0] buf_unsign_in = {_T_3501,_T_3499,_T_3497,_T_3495}; // @[Cat.scala 29:58] + wire _T_3518 = ibuf_drainvec_vld[0] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3520 = ibuf_drainvec_vld[1] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3522 = ibuf_drainvec_vld[2] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire _T_3524 = ibuf_drainvec_vld[3] ? ibuf_write : io_lsu_pkt_r_store; // @[el2_lsu_bus_buffer.scala 491:46] + wire [3:0] buf_write_in = {_T_3524,_T_3522,_T_3520,_T_3518}; // @[Cat.scala 29:58] + wire _T_3557 = obuf_nosend & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 507:89] + wire _T_3559 = _T_3557 & _T_1351; // @[el2_lsu_bus_buffer.scala 507:104] + wire _T_3572 = buf_state_en_0 & _T_3643; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3573 = _T_3572 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3575 = _T_3573 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3578 = _T_3568 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3579 = _T_3578 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4869 = io_lsu_axi_bresp != 2'h0; // @[el2_lsu_bus_buffer.scala 618:58] + wire bus_rsp_read_error = bus_rsp_read & _T_4869; // @[el2_lsu_bus_buffer.scala 618:38] + wire _T_3582 = _T_3578 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3657 = bus_rsp_read_error & _T_3636; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3659 = bus_rsp_read_error & buf_ldfwd[0]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3661 = _T_3659 & _T_3638; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3662 = _T_3657 | _T_3661; // @[el2_lsu_bus_buffer.scala 529:143] + wire bus_rsp_write_error = bus_rsp_write & _T_4869; // @[el2_lsu_bus_buffer.scala 617:40] + wire _T_3665 = bus_rsp_write_error & _T_3634; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3666 = _T_3662 | _T_3665; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3667 = _T_3568 & _T_3666; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_46 = _T_3589 & _T_3667; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_3555 ? _T_3582 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_71 = _T_3551 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire buf_error_en_0 = _T_3528 ? 1'h0 : _GEN_71; // @[Conditional.scala 40:58] + wire _T_3592 = ~bus_rsp_write_error; // @[el2_lsu_bus_buffer.scala 519:73] + wire _T_3593 = buf_write[0] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3594 = io_dec_tlu_force_halt | _T_3593; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3596 = ~buf_samedw_0; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3597 = buf_dual_0 & _T_3596; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3600 = _T_3597 & _T_3643; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_19 = 2'h1 == buf_dualtag_0 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_20 = 2'h2 == buf_dualtag_0 ? buf_state_2 : _GEN_19; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_21 = 2'h3 == buf_dualtag_0 ? buf_state_3 : _GEN_20; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3601 = _GEN_21 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3602 = _T_3600 & _T_3601; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4494 = _T_2746 | _T_2743; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_4495 = _T_4494 | _T_2740; // @[el2_lsu_bus_buffer.scala 578:93] + wire any_done_wait_state = _T_4495 | _T_2737; // @[el2_lsu_bus_buffer.scala 578:93] + wire _T_3604 = buf_ldfwd[0] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3610 = buf_dualtag_0 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3612 = buf_dualtag_0 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3614 = buf_dualtag_0 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3616 = buf_dualtag_0 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3618 = _T_3610 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3619 = _T_3612 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3620 = _T_3614 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3621 = _T_3616 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3622 = _T_3618 | _T_3619; // @[Mux.scala 27:72] + wire _T_3623 = _T_3622 | _T_3620; // @[Mux.scala 27:72] + wire _T_3624 = _T_3623 | _T_3621; // @[Mux.scala 27:72] + wire _T_3626 = _T_3600 & _T_3624; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3627 = _GEN_21 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3628 = _T_3626 & _T_3627; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3629 = _T_3628 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3630 = _T_3604 | _T_3629; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3653 = buf_state_bus_en_0 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3654 = _T_3653 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3668 = ~buf_error_en_0; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3669 = buf_state_en_0 & _T_3668; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3681 = buf_ldfwd[0] | _T_3686[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3682 = _T_3681 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_29 = _T_3702 & buf_state_en_0; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_3694 ? 1'h0 : _T_3702; // @[Conditional.scala 39:67] + wire _GEN_34 = _T_3694 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_3676 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_3676 ? 1'h0 : _GEN_34; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_3589 & _T_3654; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_3589 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_50 = _T_3589 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_3555 ? _T_3575 : _GEN_50; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_3555 ? _T_3579 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_3555 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_68 = _T_3551 ? 1'h0 : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_3551 ? 1'h0 : _GEN_58; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_3551 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire buf_wr_en_0 = _T_3528 & buf_state_en_0; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_0 = _T_3528 ? 1'h0 : _GEN_68; // @[Conditional.scala 40:58] + wire buf_rst_0 = _T_3528 ? 1'h0 : _GEN_74; // @[Conditional.scala 40:58] + wire _T_3765 = buf_state_en_1 & _T_3836; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3766 = _T_3765 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3768 = _T_3766 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3771 = _T_3761 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3772 = _T_3771 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3775 = _T_3771 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_3850 = bus_rsp_read_error & _T_3829; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_3852 = bus_rsp_read_error & buf_ldfwd[1]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_3854 = _T_3852 & _T_3831; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_3855 = _T_3850 | _T_3854; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_3858 = bus_rsp_write_error & _T_3827; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_3859 = _T_3855 | _T_3858; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_3860 = _T_3761 & _T_3859; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_122 = _T_3782 & _T_3860; // @[Conditional.scala 39:67] + wire _GEN_135 = _T_3748 ? _T_3775 : _GEN_122; // @[Conditional.scala 39:67] + wire _GEN_147 = _T_3744 ? 1'h0 : _GEN_135; // @[Conditional.scala 39:67] + wire buf_error_en_1 = _T_3721 ? 1'h0 : _GEN_147; // @[Conditional.scala 40:58] + wire _T_3786 = buf_write[1] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3787 = io_dec_tlu_force_halt | _T_3786; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3789 = ~buf_samedw_1; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3790 = buf_dual_1 & _T_3789; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3793 = _T_3790 & _T_3836; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_95 = 2'h1 == buf_dualtag_1 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_96 = 2'h2 == buf_dualtag_1 ? buf_state_2 : _GEN_95; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_97 = 2'h3 == buf_dualtag_1 ? buf_state_3 : _GEN_96; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3794 = _GEN_97 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3795 = _T_3793 & _T_3794; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3797 = buf_ldfwd[1] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3803 = buf_dualtag_1 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3805 = buf_dualtag_1 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3807 = buf_dualtag_1 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3809 = buf_dualtag_1 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3811 = _T_3803 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_3812 = _T_3805 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_3813 = _T_3807 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_3814 = _T_3809 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_3815 = _T_3811 | _T_3812; // @[Mux.scala 27:72] + wire _T_3816 = _T_3815 | _T_3813; // @[Mux.scala 27:72] + wire _T_3817 = _T_3816 | _T_3814; // @[Mux.scala 27:72] + wire _T_3819 = _T_3793 & _T_3817; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_3820 = _GEN_97 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_3821 = _T_3819 & _T_3820; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_3822 = _T_3821 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_3823 = _T_3797 | _T_3822; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_3846 = buf_state_bus_en_1 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_3847 = _T_3846 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_3861 = ~buf_error_en_1; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_3862 = buf_state_en_1 & _T_3861; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_3874 = buf_ldfwd[1] | _T_3879[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_3875 = _T_3874 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_105 = _T_3895 & buf_state_en_1; // @[Conditional.scala 39:67] + wire _GEN_108 = _T_3887 ? 1'h0 : _T_3895; // @[Conditional.scala 39:67] + wire _GEN_110 = _T_3887 ? 1'h0 : _GEN_105; // @[Conditional.scala 39:67] + wire _GEN_114 = _T_3869 ? 1'h0 : _GEN_108; // @[Conditional.scala 39:67] + wire _GEN_116 = _T_3869 ? 1'h0 : _GEN_110; // @[Conditional.scala 39:67] + wire _GEN_121 = _T_3782 & _T_3847; // @[Conditional.scala 39:67] + wire _GEN_124 = _T_3782 ? 1'h0 : _GEN_114; // @[Conditional.scala 39:67] + wire _GEN_126 = _T_3782 ? 1'h0 : _GEN_116; // @[Conditional.scala 39:67] + wire _GEN_132 = _T_3748 ? _T_3768 : _GEN_126; // @[Conditional.scala 39:67] + wire _GEN_134 = _T_3748 ? _T_3772 : _GEN_121; // @[Conditional.scala 39:67] + wire _GEN_138 = _T_3748 ? 1'h0 : _GEN_124; // @[Conditional.scala 39:67] + wire _GEN_144 = _T_3744 ? 1'h0 : _GEN_132; // @[Conditional.scala 39:67] + wire _GEN_146 = _T_3744 ? 1'h0 : _GEN_134; // @[Conditional.scala 39:67] + wire _GEN_150 = _T_3744 ? 1'h0 : _GEN_138; // @[Conditional.scala 39:67] + wire buf_wr_en_1 = _T_3721 & buf_state_en_1; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_1 = _T_3721 ? 1'h0 : _GEN_144; // @[Conditional.scala 40:58] + wire buf_rst_1 = _T_3721 ? 1'h0 : _GEN_150; // @[Conditional.scala 40:58] + wire _T_3958 = buf_state_en_2 & _T_4029; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_3959 = _T_3958 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_3961 = _T_3959 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_3964 = _T_3954 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_3965 = _T_3964 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_3968 = _T_3964 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4043 = bus_rsp_read_error & _T_4022; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4045 = bus_rsp_read_error & buf_ldfwd[2]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4047 = _T_4045 & _T_4024; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4048 = _T_4043 | _T_4047; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4051 = bus_rsp_write_error & _T_4020; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4052 = _T_4048 | _T_4051; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4053 = _T_3954 & _T_4052; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_198 = _T_3975 & _T_4053; // @[Conditional.scala 39:67] + wire _GEN_211 = _T_3941 ? _T_3968 : _GEN_198; // @[Conditional.scala 39:67] + wire _GEN_223 = _T_3937 ? 1'h0 : _GEN_211; // @[Conditional.scala 39:67] + wire buf_error_en_2 = _T_3914 ? 1'h0 : _GEN_223; // @[Conditional.scala 40:58] + wire _T_3979 = buf_write[2] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_3980 = io_dec_tlu_force_halt | _T_3979; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_3982 = ~buf_samedw_2; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_3983 = buf_dual_2 & _T_3982; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_3986 = _T_3983 & _T_4029; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_171 = 2'h1 == buf_dualtag_2 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_172 = 2'h2 == buf_dualtag_2 ? buf_state_2 : _GEN_171; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_173 = 2'h3 == buf_dualtag_2 ? buf_state_3 : _GEN_172; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3987 = _GEN_173 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_3988 = _T_3986 & _T_3987; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_3990 = buf_ldfwd[2] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_3996 = buf_dualtag_2 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_3998 = buf_dualtag_2 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4000 = buf_dualtag_2 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4002 = buf_dualtag_2 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4004 = _T_3996 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4005 = _T_3998 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4006 = _T_4000 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4007 = _T_4002 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4008 = _T_4004 | _T_4005; // @[Mux.scala 27:72] + wire _T_4009 = _T_4008 | _T_4006; // @[Mux.scala 27:72] + wire _T_4010 = _T_4009 | _T_4007; // @[Mux.scala 27:72] + wire _T_4012 = _T_3986 & _T_4010; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4013 = _GEN_173 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4014 = _T_4012 & _T_4013; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4015 = _T_4014 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4016 = _T_3990 | _T_4015; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4039 = buf_state_bus_en_2 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4040 = _T_4039 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4054 = ~buf_error_en_2; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4055 = buf_state_en_2 & _T_4054; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4067 = buf_ldfwd[2] | _T_4072[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4068 = _T_4067 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_181 = _T_4088 & buf_state_en_2; // @[Conditional.scala 39:67] + wire _GEN_184 = _T_4080 ? 1'h0 : _T_4088; // @[Conditional.scala 39:67] + wire _GEN_186 = _T_4080 ? 1'h0 : _GEN_181; // @[Conditional.scala 39:67] + wire _GEN_190 = _T_4062 ? 1'h0 : _GEN_184; // @[Conditional.scala 39:67] + wire _GEN_192 = _T_4062 ? 1'h0 : _GEN_186; // @[Conditional.scala 39:67] + wire _GEN_197 = _T_3975 & _T_4040; // @[Conditional.scala 39:67] + wire _GEN_200 = _T_3975 ? 1'h0 : _GEN_190; // @[Conditional.scala 39:67] + wire _GEN_202 = _T_3975 ? 1'h0 : _GEN_192; // @[Conditional.scala 39:67] + wire _GEN_208 = _T_3941 ? _T_3961 : _GEN_202; // @[Conditional.scala 39:67] + wire _GEN_210 = _T_3941 ? _T_3965 : _GEN_197; // @[Conditional.scala 39:67] + wire _GEN_214 = _T_3941 ? 1'h0 : _GEN_200; // @[Conditional.scala 39:67] + wire _GEN_220 = _T_3937 ? 1'h0 : _GEN_208; // @[Conditional.scala 39:67] + wire _GEN_222 = _T_3937 ? 1'h0 : _GEN_210; // @[Conditional.scala 39:67] + wire _GEN_226 = _T_3937 ? 1'h0 : _GEN_214; // @[Conditional.scala 39:67] + wire buf_wr_en_2 = _T_3914 & buf_state_en_2; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_2 = _T_3914 ? 1'h0 : _GEN_220; // @[Conditional.scala 40:58] + wire buf_rst_2 = _T_3914 ? 1'h0 : _GEN_226; // @[Conditional.scala 40:58] + wire _T_4151 = buf_state_en_3 & _T_4222; // @[el2_lsu_bus_buffer.scala 512:44] + wire _T_4152 = _T_4151 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 512:60] + wire _T_4154 = _T_4152 & _T_1333; // @[el2_lsu_bus_buffer.scala 512:74] + wire _T_4157 = _T_4147 & obuf_nosend; // @[el2_lsu_bus_buffer.scala 514:67] + wire _T_4158 = _T_4157 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 514:81] + wire _T_4161 = _T_4157 & bus_rsp_read_error; // @[el2_lsu_bus_buffer.scala 515:82] + wire _T_4236 = bus_rsp_read_error & _T_4215; // @[el2_lsu_bus_buffer.scala 529:91] + wire _T_4238 = bus_rsp_read_error & buf_ldfwd[3]; // @[el2_lsu_bus_buffer.scala 530:31] + wire _T_4240 = _T_4238 & _T_4217; // @[el2_lsu_bus_buffer.scala 530:46] + wire _T_4241 = _T_4236 | _T_4240; // @[el2_lsu_bus_buffer.scala 529:143] + wire _T_4244 = bus_rsp_write_error & _T_4213; // @[el2_lsu_bus_buffer.scala 531:53] + wire _T_4245 = _T_4241 | _T_4244; // @[el2_lsu_bus_buffer.scala 530:88] + wire _T_4246 = _T_4147 & _T_4245; // @[el2_lsu_bus_buffer.scala 529:68] + wire _GEN_274 = _T_4168 & _T_4246; // @[Conditional.scala 39:67] + wire _GEN_287 = _T_4134 ? _T_4161 : _GEN_274; // @[Conditional.scala 39:67] + wire _GEN_299 = _T_4130 ? 1'h0 : _GEN_287; // @[Conditional.scala 39:67] + wire buf_error_en_3 = _T_4107 ? 1'h0 : _GEN_299; // @[Conditional.scala 40:58] + wire _T_4172 = buf_write[3] & _T_3592; // @[el2_lsu_bus_buffer.scala 519:71] + wire _T_4173 = io_dec_tlu_force_halt | _T_4172; // @[el2_lsu_bus_buffer.scala 519:55] + wire _T_4175 = ~buf_samedw_3; // @[el2_lsu_bus_buffer.scala 520:30] + wire _T_4176 = buf_dual_3 & _T_4175; // @[el2_lsu_bus_buffer.scala 520:28] + wire _T_4179 = _T_4176 & _T_4222; // @[el2_lsu_bus_buffer.scala 520:45] + wire [2:0] _GEN_247 = 2'h1 == buf_dualtag_3 ? buf_state_1 : buf_state_0; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_248 = 2'h2 == buf_dualtag_3 ? buf_state_2 : _GEN_247; // @[el2_lsu_bus_buffer.scala 520:90] + wire [2:0] _GEN_249 = 2'h3 == buf_dualtag_3 ? buf_state_3 : _GEN_248; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4180 = _GEN_249 != 3'h4; // @[el2_lsu_bus_buffer.scala 520:90] + wire _T_4181 = _T_4179 & _T_4180; // @[el2_lsu_bus_buffer.scala 520:61] + wire _T_4183 = buf_ldfwd[3] | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:31] + wire _T_4189 = buf_dualtag_3 == 2'h0; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4191 = buf_dualtag_3 == 2'h1; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4193 = buf_dualtag_3 == 2'h2; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4195 = buf_dualtag_3 == 2'h3; // @[el2_lsu_bus_buffer.scala 111:118] + wire _T_4197 = _T_4189 & buf_ldfwd[0]; // @[Mux.scala 27:72] + wire _T_4198 = _T_4191 & buf_ldfwd[1]; // @[Mux.scala 27:72] + wire _T_4199 = _T_4193 & buf_ldfwd[2]; // @[Mux.scala 27:72] + wire _T_4200 = _T_4195 & buf_ldfwd[3]; // @[Mux.scala 27:72] + wire _T_4201 = _T_4197 | _T_4198; // @[Mux.scala 27:72] + wire _T_4202 = _T_4201 | _T_4199; // @[Mux.scala 27:72] + wire _T_4203 = _T_4202 | _T_4200; // @[Mux.scala 27:72] + wire _T_4205 = _T_4179 & _T_4203; // @[el2_lsu_bus_buffer.scala 521:101] + wire _T_4206 = _GEN_249 == 3'h4; // @[el2_lsu_bus_buffer.scala 521:167] + wire _T_4207 = _T_4205 & _T_4206; // @[el2_lsu_bus_buffer.scala 521:138] + wire _T_4208 = _T_4207 & any_done_wait_state; // @[el2_lsu_bus_buffer.scala 521:187] + wire _T_4209 = _T_4183 | _T_4208; // @[el2_lsu_bus_buffer.scala 521:53] + wire _T_4232 = buf_state_bus_en_3 & bus_rsp_read; // @[el2_lsu_bus_buffer.scala 528:47] + wire _T_4233 = _T_4232 & io_lsu_bus_clk_en; // @[el2_lsu_bus_buffer.scala 528:62] + wire _T_4247 = ~buf_error_en_3; // @[el2_lsu_bus_buffer.scala 532:50] + wire _T_4248 = buf_state_en_3 & _T_4247; // @[el2_lsu_bus_buffer.scala 532:48] + wire _T_4260 = buf_ldfwd[3] | _T_4265[0]; // @[el2_lsu_bus_buffer.scala 535:90] + wire _T_4261 = _T_4260 | any_done_wait_state; // @[el2_lsu_bus_buffer.scala 535:118] + wire _GEN_257 = _T_4281 & buf_state_en_3; // @[Conditional.scala 39:67] + wire _GEN_260 = _T_4273 ? 1'h0 : _T_4281; // @[Conditional.scala 39:67] + wire _GEN_262 = _T_4273 ? 1'h0 : _GEN_257; // @[Conditional.scala 39:67] + wire _GEN_266 = _T_4255 ? 1'h0 : _GEN_260; // @[Conditional.scala 39:67] + wire _GEN_268 = _T_4255 ? 1'h0 : _GEN_262; // @[Conditional.scala 39:67] + wire _GEN_273 = _T_4168 & _T_4233; // @[Conditional.scala 39:67] + wire _GEN_276 = _T_4168 ? 1'h0 : _GEN_266; // @[Conditional.scala 39:67] + wire _GEN_278 = _T_4168 ? 1'h0 : _GEN_268; // @[Conditional.scala 39:67] + wire _GEN_284 = _T_4134 ? _T_4154 : _GEN_278; // @[Conditional.scala 39:67] + wire _GEN_286 = _T_4134 ? _T_4158 : _GEN_273; // @[Conditional.scala 39:67] + wire _GEN_290 = _T_4134 ? 1'h0 : _GEN_276; // @[Conditional.scala 39:67] + wire _GEN_296 = _T_4130 ? 1'h0 : _GEN_284; // @[Conditional.scala 39:67] + wire _GEN_298 = _T_4130 ? 1'h0 : _GEN_286; // @[Conditional.scala 39:67] + wire _GEN_302 = _T_4130 ? 1'h0 : _GEN_290; // @[Conditional.scala 39:67] + wire buf_wr_en_3 = _T_4107 & buf_state_en_3; // @[Conditional.scala 40:58] + wire buf_ldfwd_en_3 = _T_4107 ? 1'h0 : _GEN_296; // @[Conditional.scala 40:58] + wire buf_rst_3 = _T_4107 ? 1'h0 : _GEN_302; // @[Conditional.scala 40:58] + reg _T_4336; // @[Reg.scala 27:20] + reg _T_4339; // @[Reg.scala 27:20] + reg _T_4342; // @[Reg.scala 27:20] + reg _T_4345; // @[Reg.scala 27:20] + wire [3:0] buf_unsign = {_T_4345,_T_4342,_T_4339,_T_4336}; // @[Cat.scala 29:58] + reg _T_4411; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4406; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4401; // @[el2_lsu_bus_buffer.scala 571:80] + reg _T_4396; // @[el2_lsu_bus_buffer.scala 571:80] + wire [3:0] buf_error = {_T_4411,_T_4406,_T_4401,_T_4396}; // @[Cat.scala 29:58] + wire _T_4393 = buf_error_en_0 | buf_error[0]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4394 = ~buf_rst_0; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4398 = buf_error_en_1 | buf_error[1]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4399 = ~buf_rst_1; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4403 = buf_error_en_2 | buf_error[2]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4404 = ~buf_rst_2; // @[el2_lsu_bus_buffer.scala 571:126] + wire _T_4408 = buf_error_en_3 | buf_error[3]; // @[el2_lsu_bus_buffer.scala 571:84] + wire _T_4409 = ~buf_rst_3; // @[el2_lsu_bus_buffer.scala 571:126] + wire [1:0] _T_4415 = {io_lsu_busreq_m,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4416 = io_ldst_dual_m ? _T_4415 : {{1'd0}, io_lsu_busreq_m}; // @[el2_lsu_bus_buffer.scala 574:28] + wire [1:0] _T_4417 = {io_lsu_busreq_r,1'h0}; // @[Cat.scala 29:58] + wire [1:0] _T_4418 = io_ldst_dual_r ? _T_4417 : {{1'd0}, io_lsu_busreq_r}; // @[el2_lsu_bus_buffer.scala 574:94] + wire [2:0] _T_4419 = _T_4416 + _T_4418; // @[el2_lsu_bus_buffer.scala 574:88] + wire [2:0] _GEN_388 = {{2'd0}, ibuf_valid}; // @[el2_lsu_bus_buffer.scala 574:154] + wire [3:0] _T_4420 = _T_4419 + _GEN_388; // @[el2_lsu_bus_buffer.scala 574:154] + wire [1:0] _T_4425 = _T_5 + _T_12; // @[el2_lsu_bus_buffer.scala 574:217] + wire [1:0] _GEN_389 = {{1'd0}, _T_19}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _T_4426 = _T_4425 + _GEN_389; // @[el2_lsu_bus_buffer.scala 574:217] + wire [2:0] _GEN_390 = {{2'd0}, _T_26}; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] _T_4427 = _T_4426 + _GEN_390; // @[el2_lsu_bus_buffer.scala 574:217] + wire [3:0] buf_numvld_any = _T_4420 + _T_4427; // @[el2_lsu_bus_buffer.scala 574:169] + wire _T_4498 = io_ldst_dual_d & io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_buffer.scala 580:52] + wire _T_4499 = buf_numvld_any >= 4'h3; // @[el2_lsu_bus_buffer.scala 580:92] + wire _T_4500 = buf_numvld_any == 4'h4; // @[el2_lsu_bus_buffer.scala 580:121] + wire _T_4502 = |buf_state_0; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4503 = |buf_state_1; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4504 = |buf_state_2; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4505 = |buf_state_3; // @[el2_lsu_bus_buffer.scala 581:52] + wire _T_4506 = _T_4502 | _T_4503; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4507 = _T_4506 | _T_4504; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4508 = _T_4507 | _T_4505; // @[el2_lsu_bus_buffer.scala 581:65] + wire _T_4509 = ~_T_4508; // @[el2_lsu_bus_buffer.scala 581:34] + wire _T_4511 = _T_4509 & _T_852; // @[el2_lsu_bus_buffer.scala 581:70] + wire _T_4514 = io_lsu_busreq_m & io_lsu_pkt_m_valid; // @[el2_lsu_bus_buffer.scala 583:51] + wire _T_4515 = _T_4514 & io_lsu_pkt_m_load; // @[el2_lsu_bus_buffer.scala 583:72] + wire _T_4516 = ~io_flush_m_up; // @[el2_lsu_bus_buffer.scala 583:94] + wire _T_4517 = _T_4515 & _T_4516; // @[el2_lsu_bus_buffer.scala 583:92] + wire _T_4518 = ~io_ld_full_hit_m; // @[el2_lsu_bus_buffer.scala 583:111] + wire _T_4520 = ~io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 586:61] + reg lsu_nonblock_load_valid_r; // @[el2_lsu_bus_buffer.scala 671:66] + wire _T_4538 = _T_2799 & _T_3643; // @[Mux.scala 27:72] + wire _T_4539 = _T_2821 & _T_3836; // @[Mux.scala 27:72] + wire _T_4540 = _T_2843 & _T_4029; // @[Mux.scala 27:72] + wire _T_4541 = _T_2865 & _T_4222; // @[Mux.scala 27:72] + wire _T_4542 = _T_4538 | _T_4539; // @[Mux.scala 27:72] + wire _T_4543 = _T_4542 | _T_4540; // @[Mux.scala 27:72] + wire lsu_nonblock_load_data_ready = _T_4543 | _T_4541; // @[Mux.scala 27:72] + wire _T_4549 = buf_error[0] & _T_3643; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4554 = buf_error[1] & _T_3836; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4559 = buf_error[2] & _T_4029; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4564 = buf_error[3] & _T_4222; // @[el2_lsu_bus_buffer.scala 589:108] + wire _T_4565 = _T_2799 & _T_4549; // @[Mux.scala 27:72] + wire _T_4566 = _T_2821 & _T_4554; // @[Mux.scala 27:72] + wire _T_4567 = _T_2843 & _T_4559; // @[Mux.scala 27:72] + wire _T_4568 = _T_2865 & _T_4564; // @[Mux.scala 27:72] + wire _T_4569 = _T_4565 | _T_4566; // @[Mux.scala 27:72] + wire _T_4570 = _T_4569 | _T_4567; // @[Mux.scala 27:72] + wire _T_4577 = ~buf_dual_0; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4578 = ~buf_dualhi_0; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4579 = _T_4577 | _T_4578; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4580 = _T_4538 & _T_4579; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4585 = ~buf_dual_1; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4586 = ~buf_dualhi_1; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4587 = _T_4585 | _T_4586; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4588 = _T_4539 & _T_4587; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4593 = ~buf_dual_2; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4594 = ~buf_dualhi_2; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4595 = _T_4593 | _T_4594; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4596 = _T_4540 & _T_4595; // @[el2_lsu_bus_buffer.scala 590:106] + wire _T_4601 = ~buf_dual_3; // @[el2_lsu_bus_buffer.scala 590:109] + wire _T_4602 = ~buf_dualhi_3; // @[el2_lsu_bus_buffer.scala 590:124] + wire _T_4603 = _T_4601 | _T_4602; // @[el2_lsu_bus_buffer.scala 590:122] + wire _T_4604 = _T_4541 & _T_4603; // @[el2_lsu_bus_buffer.scala 590:106] + wire [1:0] _T_4607 = _T_4596 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4608 = _T_4604 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_391 = {{1'd0}, _T_4588}; // @[Mux.scala 27:72] + wire [1:0] _T_4610 = _GEN_391 | _T_4607; // @[Mux.scala 27:72] + wire [31:0] _T_4645 = _T_4580 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4646 = _T_4588 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4647 = _T_4596 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4648 = _T_4604 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4649 = _T_4645 | _T_4646; // @[Mux.scala 27:72] + wire [31:0] _T_4650 = _T_4649 | _T_4647; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_lo = _T_4650 | _T_4648; // @[Mux.scala 27:72] + wire _T_4657 = _T_4538 & _T_3641; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4663 = _T_4539 & _T_3834; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4669 = _T_4540 & _T_4027; // @[el2_lsu_bus_buffer.scala 592:105] + wire _T_4675 = _T_4541 & _T_4220; // @[el2_lsu_bus_buffer.scala 592:105] + wire [31:0] _T_4676 = _T_4657 ? buf_data_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4677 = _T_4663 ? buf_data_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4678 = _T_4669 ? buf_data_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4679 = _T_4675 ? buf_data_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4680 = _T_4676 | _T_4677; // @[Mux.scala 27:72] + wire [31:0] _T_4681 = _T_4680 | _T_4678; // @[Mux.scala 27:72] + wire [31:0] lsu_nonblock_load_data_hi = _T_4681 | _T_4679; // @[Mux.scala 27:72] + wire _T_4683 = io_lsu_nonblock_load_data_tag == 2'h0; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4684 = io_lsu_nonblock_load_data_tag == 2'h1; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4685 = io_lsu_nonblock_load_data_tag == 2'h2; // @[el2_lsu_bus_buffer.scala 112:123] + wire _T_4686 = io_lsu_nonblock_load_data_tag == 2'h3; // @[el2_lsu_bus_buffer.scala 112:123] + wire [31:0] _T_4687 = _T_4683 ? buf_addr_0 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4688 = _T_4684 ? buf_addr_1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4689 = _T_4685 ? buf_addr_2 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4690 = _T_4686 ? buf_addr_3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4691 = _T_4687 | _T_4688; // @[Mux.scala 27:72] + wire [31:0] _T_4692 = _T_4691 | _T_4689; // @[Mux.scala 27:72] + wire [31:0] _T_4693 = _T_4692 | _T_4690; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_addr_offset = _T_4693[1:0]; // @[el2_lsu_bus_buffer.scala 593:83] + wire [1:0] _T_4699 = _T_4683 ? buf_sz_0 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4700 = _T_4684 ? buf_sz_1 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4701 = _T_4685 ? buf_sz_2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4702 = _T_4686 ? buf_sz_3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4703 = _T_4699 | _T_4700; // @[Mux.scala 27:72] + wire [1:0] _T_4704 = _T_4703 | _T_4701; // @[Mux.scala 27:72] + wire [1:0] lsu_nonblock_sz = _T_4704 | _T_4702; // @[Mux.scala 27:72] + wire _T_4714 = _T_4683 & buf_unsign[0]; // @[Mux.scala 27:72] + wire _T_4715 = _T_4684 & buf_unsign[1]; // @[Mux.scala 27:72] + wire _T_4716 = _T_4685 & buf_unsign[2]; // @[Mux.scala 27:72] + wire _T_4717 = _T_4686 & buf_unsign[3]; // @[Mux.scala 27:72] + wire _T_4718 = _T_4714 | _T_4715; // @[Mux.scala 27:72] + wire _T_4719 = _T_4718 | _T_4716; // @[Mux.scala 27:72] + wire lsu_nonblock_unsign = _T_4719 | _T_4717; // @[Mux.scala 27:72] + wire [63:0] _T_4739 = {lsu_nonblock_load_data_hi,lsu_nonblock_load_data_lo}; // @[Cat.scala 29:58] + wire [3:0] _GEN_392 = {{2'd0}, lsu_nonblock_addr_offset}; // @[el2_lsu_bus_buffer.scala 597:121] + wire [5:0] _T_4740 = _GEN_392 * 4'h8; // @[el2_lsu_bus_buffer.scala 597:121] + wire [63:0] lsu_nonblock_data_unalgn = _T_4739 >> _T_4740; // @[el2_lsu_bus_buffer.scala 597:92] + wire _T_4741 = ~io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_buffer.scala 599:69] + wire _T_4743 = lsu_nonblock_sz == 2'h0; // @[el2_lsu_bus_buffer.scala 600:81] + wire _T_4744 = lsu_nonblock_unsign & _T_4743; // @[el2_lsu_bus_buffer.scala 600:63] + wire [31:0] _T_4746 = {24'h0,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4747 = lsu_nonblock_sz == 2'h1; // @[el2_lsu_bus_buffer.scala 601:45] + wire _T_4748 = lsu_nonblock_unsign & _T_4747; // @[el2_lsu_bus_buffer.scala 601:26] + wire [31:0] _T_4750 = {16'h0,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4751 = ~lsu_nonblock_unsign; // @[el2_lsu_bus_buffer.scala 602:6] + wire _T_4753 = _T_4751 & _T_4743; // @[el2_lsu_bus_buffer.scala 602:27] + wire [23:0] _T_4756 = lsu_nonblock_data_unalgn[7] ? 24'hffffff : 24'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4758 = {_T_4756,lsu_nonblock_data_unalgn[7:0]}; // @[Cat.scala 29:58] + wire _T_4761 = _T_4751 & _T_4747; // @[el2_lsu_bus_buffer.scala 603:27] + wire [15:0] _T_4764 = lsu_nonblock_data_unalgn[15] ? 16'hffff : 16'h0; // @[Bitwise.scala 72:12] + wire [31:0] _T_4766 = {_T_4764,lsu_nonblock_data_unalgn[15:0]}; // @[Cat.scala 29:58] + wire _T_4767 = lsu_nonblock_sz == 2'h2; // @[el2_lsu_bus_buffer.scala 604:21] + wire [31:0] _T_4768 = _T_4744 ? _T_4746 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4769 = _T_4748 ? _T_4750 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4770 = _T_4753 ? _T_4758 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4771 = _T_4761 ? _T_4766 : 32'h0; // @[Mux.scala 27:72] + wire [63:0] _T_4772 = _T_4767 ? lsu_nonblock_data_unalgn : 64'h0; // @[Mux.scala 27:72] + wire [31:0] _T_4773 = _T_4768 | _T_4769; // @[Mux.scala 27:72] + wire [31:0] _T_4774 = _T_4773 | _T_4770; // @[Mux.scala 27:72] + wire [31:0] _T_4775 = _T_4774 | _T_4771; // @[Mux.scala 27:72] + wire [63:0] _GEN_393 = {{32'd0}, _T_4775}; // @[Mux.scala 27:72] + wire [63:0] _T_4776 = _GEN_393 | _T_4772; // @[Mux.scala 27:72] + wire _T_4871 = obuf_valid & obuf_write; // @[el2_lsu_bus_buffer.scala 622:36] + wire _T_4872 = ~obuf_cmd_done; // @[el2_lsu_bus_buffer.scala 622:51] + wire _T_4873 = _T_4871 & _T_4872; // @[el2_lsu_bus_buffer.scala 622:49] + wire [31:0] _T_4877 = {obuf_addr[31:3],3'h0}; // @[Cat.scala 29:58] + wire [2:0] _T_4879 = {1'h0,obuf_sz}; // @[Cat.scala 29:58] + wire _T_4884 = ~obuf_data_done; // @[el2_lsu_bus_buffer.scala 634:50] + wire _T_4885 = _T_4871 & _T_4884; // @[el2_lsu_bus_buffer.scala 634:48] + wire [7:0] _T_4889 = obuf_write ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire _T_4892 = obuf_valid & _T_1343; // @[el2_lsu_bus_buffer.scala 639:36] + wire _T_4894 = _T_4892 & _T_1349; // @[el2_lsu_bus_buffer.scala 639:50] + wire _T_4906 = io_lsu_bus_clk_en_q & buf_error[0]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4908 = _T_4906 & buf_write[0]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4911 = io_lsu_bus_clk_en_q & buf_error[1]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4913 = _T_4911 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4916 = io_lsu_bus_clk_en_q & buf_error[2]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4918 = _T_4916 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4921 = io_lsu_bus_clk_en_q & buf_error[3]; // @[el2_lsu_bus_buffer.scala 652:114] + wire _T_4923 = _T_4921 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 652:129] + wire _T_4924 = _T_2799 & _T_4908; // @[Mux.scala 27:72] + wire _T_4925 = _T_2821 & _T_4913; // @[Mux.scala 27:72] + wire _T_4926 = _T_2843 & _T_4918; // @[Mux.scala 27:72] + wire _T_4927 = _T_2865 & _T_4923; // @[Mux.scala 27:72] + wire _T_4928 = _T_4924 | _T_4925; // @[Mux.scala 27:72] + wire _T_4929 = _T_4928 | _T_4926; // @[Mux.scala 27:72] + wire _T_4939 = _T_2821 & buf_error[1]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4941 = _T_4939 & buf_write[1]; // @[el2_lsu_bus_buffer.scala 653:108] + wire _T_4944 = _T_2843 & buf_error[2]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4946 = _T_4944 & buf_write[2]; // @[el2_lsu_bus_buffer.scala 653:108] + wire _T_4949 = _T_2865 & buf_error[3]; // @[el2_lsu_bus_buffer.scala 653:93] + wire _T_4951 = _T_4949 & buf_write[3]; // @[el2_lsu_bus_buffer.scala 653:108] + wire [1:0] _T_4954 = _T_4946 ? 2'h2 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _T_4955 = _T_4951 ? 2'h3 : 2'h0; // @[Mux.scala 27:72] + wire [1:0] _GEN_394 = {{1'd0}, _T_4941}; // @[Mux.scala 27:72] + wire [1:0] _T_4957 = _GEN_394 | _T_4954; // @[Mux.scala 27:72] + wire [1:0] lsu_imprecise_error_store_tag = _T_4957 | _T_4955; // @[Mux.scala 27:72] + wire _T_4959 = ~io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 655:72] + wire [31:0] _GEN_351 = 2'h1 == lsu_imprecise_error_store_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_352 = 2'h2 == lsu_imprecise_error_store_tag ? buf_addr_2 : _GEN_351; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_353 = 2'h3 == lsu_imprecise_error_store_tag ? buf_addr_3 : _GEN_352; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_355 = 2'h1 == io_lsu_nonblock_load_data_tag ? buf_addr_1 : buf_addr_0; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_356 = 2'h2 == io_lsu_nonblock_load_data_tag ? buf_addr_2 : _GEN_355; // @[el2_lsu_bus_buffer.scala 656:41] + wire [31:0] _GEN_357 = 2'h3 == io_lsu_nonblock_load_data_tag ? buf_addr_3 : _GEN_356; // @[el2_lsu_bus_buffer.scala 656:41] + wire _T_4964 = bus_wcmd_sent | bus_wdata_sent; // @[el2_lsu_bus_buffer.scala 662:68] + wire _T_4967 = io_lsu_busreq_r & io_ldst_dual_r; // @[el2_lsu_bus_buffer.scala 663:48] + wire _T_4970 = ~io_lsu_axi_awready; // @[el2_lsu_bus_buffer.scala 666:48] + wire _T_4971 = io_lsu_axi_awvalid & _T_4970; // @[el2_lsu_bus_buffer.scala 666:46] + wire _T_4972 = ~io_lsu_axi_wready; // @[el2_lsu_bus_buffer.scala 666:92] + wire _T_4973 = io_lsu_axi_wvalid & _T_4972; // @[el2_lsu_bus_buffer.scala 666:90] + wire _T_4974 = _T_4971 | _T_4973; // @[el2_lsu_bus_buffer.scala 666:69] + wire _T_4975 = ~io_lsu_axi_arready; // @[el2_lsu_bus_buffer.scala 666:136] + wire _T_4976 = io_lsu_axi_arvalid & _T_4975; // @[el2_lsu_bus_buffer.scala 666:134] + wire _T_4980 = ~io_flush_r; // @[el2_lsu_bus_buffer.scala 670:75] + wire _T_4981 = io_lsu_busreq_m & _T_4980; // @[el2_lsu_bus_buffer.scala 670:73] + reg _T_4984; // @[el2_lsu_bus_buffer.scala 670:56] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + rvclkhdr rvclkhdr_10 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_10_io_l1clk), + .io_clk(rvclkhdr_10_io_clk), + .io_en(rvclkhdr_10_io_en), + .io_scan_mode(rvclkhdr_10_io_scan_mode) + ); + rvclkhdr rvclkhdr_11 ( // @[el2_lib.scala 508:23] + .io_l1clk(rvclkhdr_11_io_l1clk), + .io_clk(rvclkhdr_11_io_clk), + .io_en(rvclkhdr_11_io_en), + .io_scan_mode(rvclkhdr_11_io_scan_mode) + ); + assign io_lsu_busreq_r = _T_4984; // @[el2_lsu_bus_buffer.scala 670:19] + assign io_lsu_bus_buffer_pend_any = |buf_numvld_pend_any; // @[el2_lsu_bus_buffer.scala 579:30] + assign io_lsu_bus_buffer_full_any = _T_4498 ? _T_4499 : _T_4500; // @[el2_lsu_bus_buffer.scala 580:30] + assign io_lsu_bus_buffer_empty_any = _T_4511 & _T_1231; // @[el2_lsu_bus_buffer.scala 581:31] + assign io_ld_byte_hit_buf_lo = {_T_69,_T_58}; // @[el2_lsu_bus_buffer.scala 191:25] + assign io_ld_byte_hit_buf_hi = {_T_84,_T_73}; // @[el2_lsu_bus_buffer.scala 192:25] + assign io_ld_fwddata_buf_lo = _T_650 | _T_651; // @[el2_lsu_bus_buffer.scala 218:24] + assign io_ld_fwddata_buf_hi = _T_747 | _T_748; // @[el2_lsu_bus_buffer.scala 224:24] + assign io_lsu_imprecise_error_load_any = io_lsu_nonblock_load_data_error & _T_4959; // @[el2_lsu_bus_buffer.scala 655:35] + assign io_lsu_imprecise_error_store_any = _T_4929 | _T_4927; // @[el2_lsu_bus_buffer.scala 652:36] + assign io_lsu_imprecise_error_addr_any = io_lsu_imprecise_error_store_any ? _GEN_353 : _GEN_357; // @[el2_lsu_bus_buffer.scala 656:35] + assign io_lsu_nonblock_load_valid_m = _T_4517 & _T_4518; // @[el2_lsu_bus_buffer.scala 583:32] + assign io_lsu_nonblock_load_tag_m = _T_1863 ? 2'h0 : _T_1899; // @[el2_lsu_bus_buffer.scala 584:30] + assign io_lsu_nonblock_load_inv_r = lsu_nonblock_load_valid_r & _T_4520; // @[el2_lsu_bus_buffer.scala 586:30] + assign io_lsu_nonblock_load_inv_tag_r = WrPtr0_r; // @[el2_lsu_bus_buffer.scala 587:34] + assign io_lsu_nonblock_load_data_valid = lsu_nonblock_load_data_ready & _T_4741; // @[el2_lsu_bus_buffer.scala 599:35] + assign io_lsu_nonblock_load_data_error = _T_4570 | _T_4568; // @[el2_lsu_bus_buffer.scala 589:35] + assign io_lsu_nonblock_load_data_tag = _T_4610 | _T_4608; // @[el2_lsu_bus_buffer.scala 590:33] + assign io_lsu_nonblock_load_data = _T_4776[31:0]; // @[el2_lsu_bus_buffer.scala 600:29] + assign io_lsu_pmu_bus_trxn = _T_4964 | _T_4863; // @[el2_lsu_bus_buffer.scala 662:23] + assign io_lsu_pmu_bus_misaligned = _T_4967 & io_lsu_commit_r; // @[el2_lsu_bus_buffer.scala 663:29] + assign io_lsu_pmu_bus_error = io_lsu_imprecise_error_load_any | io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_buffer.scala 664:24] + assign io_lsu_pmu_bus_busy = _T_4974 | _T_4976; // @[el2_lsu_bus_buffer.scala 666:23] + assign io_lsu_axi_awvalid = _T_4873 & _T_1239; // @[el2_lsu_bus_buffer.scala 622:22] + assign io_lsu_axi_awid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 623:19] + assign io_lsu_axi_awaddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 624:21] + assign io_lsu_axi_awregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 628:23] + assign io_lsu_axi_awsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 625:21] + assign io_lsu_axi_awcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 627:22] + assign io_lsu_axi_wvalid = _T_4885 & _T_1239; // @[el2_lsu_bus_buffer.scala 634:21] + assign io_lsu_axi_wdata = obuf_data; // @[el2_lsu_bus_buffer.scala 636:20] + assign io_lsu_axi_wstrb = obuf_byteen & _T_4889; // @[el2_lsu_bus_buffer.scala 635:20] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_buffer.scala 650:21] + assign io_lsu_axi_arvalid = _T_4894 & _T_1239; // @[el2_lsu_bus_buffer.scala 639:22] + assign io_lsu_axi_arid = {{1'd0}, _T_1848}; // @[el2_lsu_bus_buffer.scala 640:19] + assign io_lsu_axi_araddr = obuf_sideeffect ? obuf_addr : _T_4877; // @[el2_lsu_bus_buffer.scala 641:21] + assign io_lsu_axi_arregion = obuf_addr[31:28]; // @[el2_lsu_bus_buffer.scala 645:23] + assign io_lsu_axi_arsize = obuf_sideeffect ? _T_4879 : 3'h3; // @[el2_lsu_bus_buffer.scala 642:21] + assign io_lsu_axi_arcache = obuf_sideeffect ? 4'h0 : 4'hf; // @[el2_lsu_bus_buffer.scala 644:22] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_buffer.scala 651:21] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_1_io_en = _T_853 & _T_854; // @[el2_lib.scala 511:17] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_2_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_3_io_en = _T_1240 & io_lsu_bus_clk_en; // @[el2_lib.scala 511:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_4_io_en = _T_3528 & buf_state_en_0; // @[el2_lib.scala 511:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_5_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_5_io_en = _T_3721 & buf_state_en_1; // @[el2_lib.scala 511:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_6_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_6_io_en = _T_3914 & buf_state_en_2; // @[el2_lib.scala 511:17] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_7_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_7_io_en = _T_4107 & buf_state_en_3; // @[el2_lib.scala 511:17] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_8_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_8_io_en = _T_3528 ? buf_state_en_0 : _GEN_70; // @[el2_lib.scala 511:17] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_9_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_9_io_en = _T_3721 ? buf_state_en_1 : _GEN_146; // @[el2_lib.scala 511:17] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_10_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_10_io_en = _T_3914 ? buf_state_en_2 : _GEN_222; // @[el2_lib.scala 511:17] + assign rvclkhdr_10_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] + assign rvclkhdr_11_io_clk = clock; // @[el2_lib.scala 510:18] + assign rvclkhdr_11_io_en = _T_4107 ? buf_state_en_3 : _GEN_298; // @[el2_lib.scala 511:17] + assign rvclkhdr_11_io_scan_mode = io_scan_mode; // @[el2_lib.scala 512:24] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -2159,285 +2766,234 @@ initial begin `endif `ifdef RANDOMIZE_REG_INIT _RAND_0 = {1{`RANDOM}}; - ibuf_addr = _RAND_0[31:0]; + buf_addr_0 = _RAND_0[31:0]; _RAND_1 = {1{`RANDOM}}; - ibuf_write = _RAND_1[0:0]; + _T_4360 = _RAND_1[0:0]; _RAND_2 = {1{`RANDOM}}; - ibuf_valid = _RAND_2[0:0]; + _T_4357 = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; - ibuf_byteen = _RAND_3[3:0]; + _T_4354 = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - buf_addr_0 = _RAND_4[31:0]; + _T_4351 = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - buf_write_0 = _RAND_5[0:0]; + buf_state_0 = _RAND_5[2:0]; _RAND_6 = {1{`RANDOM}}; - buf_state_0 = _RAND_6[2:0]; + buf_addr_1 = _RAND_6[31:0]; _RAND_7 = {1{`RANDOM}}; - buf_addr_1 = _RAND_7[31:0]; + buf_state_1 = _RAND_7[2:0]; _RAND_8 = {1{`RANDOM}}; - buf_write_1 = _RAND_8[0:0]; + buf_addr_2 = _RAND_8[31:0]; _RAND_9 = {1{`RANDOM}}; - buf_state_1 = _RAND_9[2:0]; + buf_state_2 = _RAND_9[2:0]; _RAND_10 = {1{`RANDOM}}; - buf_addr_2 = _RAND_10[31:0]; + buf_addr_3 = _RAND_10[31:0]; _RAND_11 = {1{`RANDOM}}; - buf_write_2 = _RAND_11[0:0]; + buf_state_3 = _RAND_11[2:0]; _RAND_12 = {1{`RANDOM}}; - buf_state_2 = _RAND_12[2:0]; + buf_byteen_3 = _RAND_12[3:0]; _RAND_13 = {1{`RANDOM}}; - buf_addr_3 = _RAND_13[31:0]; + buf_byteen_2 = _RAND_13[3:0]; _RAND_14 = {1{`RANDOM}}; - buf_write_3 = _RAND_14[0:0]; + buf_byteen_1 = _RAND_14[3:0]; _RAND_15 = {1{`RANDOM}}; - buf_state_3 = _RAND_15[2:0]; + buf_byteen_0 = _RAND_15[3:0]; _RAND_16 = {1{`RANDOM}}; - buf_byteen_3 = _RAND_16[3:0]; + buf_ageQ_3 = _RAND_16[3:0]; _RAND_17 = {1{`RANDOM}}; - buf_byteen_2 = _RAND_17[3:0]; + _T_1848 = _RAND_17[1:0]; _RAND_18 = {1{`RANDOM}}; - buf_byteen_1 = _RAND_18[3:0]; + obuf_merge = _RAND_18[0:0]; _RAND_19 = {1{`RANDOM}}; - buf_byteen_0 = _RAND_19[3:0]; + obuf_tag1 = _RAND_19[1:0]; _RAND_20 = {1{`RANDOM}}; - buf_ageQ_3_3 = _RAND_20[0:0]; + obuf_valid = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - obuf_tag0 = _RAND_21[2:0]; + obuf_wr_enQ = _RAND_21[0:0]; _RAND_22 = {1{`RANDOM}}; - obuf_merge = _RAND_22[0:0]; + ibuf_addr = _RAND_22[31:0]; _RAND_23 = {1{`RANDOM}}; - obuf_tag1 = _RAND_23[2:0]; + ibuf_write = _RAND_23[0:0]; _RAND_24 = {1{`RANDOM}}; - obuf_valid = _RAND_24[0:0]; + ibuf_valid = _RAND_24[0:0]; _RAND_25 = {1{`RANDOM}}; - obuf_wr_enQ = _RAND_25[0:0]; + ibuf_byteen = _RAND_25[3:0]; _RAND_26 = {1{`RANDOM}}; - buf_ageQ_3_2 = _RAND_26[0:0]; + buf_ageQ_2 = _RAND_26[3:0]; _RAND_27 = {1{`RANDOM}}; - buf_ageQ_3_1 = _RAND_27[0:0]; + buf_ageQ_1 = _RAND_27[3:0]; _RAND_28 = {1{`RANDOM}}; - buf_ageQ_3_0 = _RAND_28[0:0]; + buf_ageQ_0 = _RAND_28[3:0]; _RAND_29 = {1{`RANDOM}}; - buf_ageQ_2_3 = _RAND_29[0:0]; + buf_data_0 = _RAND_29[31:0]; _RAND_30 = {1{`RANDOM}}; - buf_ageQ_2_2 = _RAND_30[0:0]; + buf_data_1 = _RAND_30[31:0]; _RAND_31 = {1{`RANDOM}}; - buf_ageQ_2_1 = _RAND_31[0:0]; + buf_data_2 = _RAND_31[31:0]; _RAND_32 = {1{`RANDOM}}; - buf_ageQ_2_0 = _RAND_32[0:0]; + buf_data_3 = _RAND_32[31:0]; _RAND_33 = {1{`RANDOM}}; - buf_ageQ_1_3 = _RAND_33[0:0]; + ibuf_data = _RAND_33[31:0]; _RAND_34 = {1{`RANDOM}}; - buf_ageQ_1_2 = _RAND_34[0:0]; + ibuf_timer = _RAND_34[2:0]; _RAND_35 = {1{`RANDOM}}; - buf_ageQ_1_1 = _RAND_35[0:0]; + ibuf_sideeffect = _RAND_35[0:0]; _RAND_36 = {1{`RANDOM}}; - buf_ageQ_1_0 = _RAND_36[0:0]; + WrPtr1_r = _RAND_36[1:0]; _RAND_37 = {1{`RANDOM}}; - buf_ageQ_0_3 = _RAND_37[0:0]; + WrPtr0_r = _RAND_37[1:0]; _RAND_38 = {1{`RANDOM}}; - buf_ageQ_0_2 = _RAND_38[0:0]; + ibuf_tag = _RAND_38[1:0]; _RAND_39 = {1{`RANDOM}}; - buf_ageQ_0_1 = _RAND_39[0:0]; + ibuf_dualtag = _RAND_39[1:0]; _RAND_40 = {1{`RANDOM}}; - buf_ageQ_0_0 = _RAND_40[0:0]; + ibuf_dual = _RAND_40[0:0]; _RAND_41 = {1{`RANDOM}}; - ibuf_data = _RAND_41[31:0]; + ibuf_samedw = _RAND_41[0:0]; _RAND_42 = {1{`RANDOM}}; - buf_data_0 = _RAND_42[31:0]; + ibuf_nomerge = _RAND_42[0:0]; _RAND_43 = {1{`RANDOM}}; - buf_data_1 = _RAND_43[31:0]; + ibuf_unsign = _RAND_43[0:0]; _RAND_44 = {1{`RANDOM}}; - buf_data_2 = _RAND_44[31:0]; + ibuf_sz = _RAND_44[1:0]; _RAND_45 = {1{`RANDOM}}; - buf_data_3 = _RAND_45[31:0]; + obuf_wr_timer = _RAND_45[2:0]; _RAND_46 = {1{`RANDOM}}; - ibuf_timer = _RAND_46[2:0]; + buf_nomerge_0 = _RAND_46[0:0]; _RAND_47 = {1{`RANDOM}}; - ibuf_sideeffect = _RAND_47[0:0]; + buf_nomerge_1 = _RAND_47[0:0]; _RAND_48 = {1{`RANDOM}}; - ibuf_tag = _RAND_48[1:0]; + buf_nomerge_2 = _RAND_48[0:0]; _RAND_49 = {1{`RANDOM}}; - WrPtr1_r = _RAND_49[1:0]; + buf_nomerge_3 = _RAND_49[0:0]; _RAND_50 = {1{`RANDOM}}; - WrPtr0_r = _RAND_50[1:0]; + _T_4330 = _RAND_50[0:0]; _RAND_51 = {1{`RANDOM}}; - ibuf_dual = _RAND_51[0:0]; + _T_4327 = _RAND_51[0:0]; _RAND_52 = {1{`RANDOM}}; - ibuf_samedw = _RAND_52[0:0]; + _T_4324 = _RAND_52[0:0]; _RAND_53 = {1{`RANDOM}}; - ibuf_nomerge = _RAND_53[0:0]; + _T_4321 = _RAND_53[0:0]; _RAND_54 = {1{`RANDOM}}; - ibuf_unsign = _RAND_54[0:0]; + buf_dual_3 = _RAND_54[0:0]; _RAND_55 = {1{`RANDOM}}; - ibuf_sz = _RAND_55[1:0]; + buf_dual_2 = _RAND_55[0:0]; _RAND_56 = {1{`RANDOM}}; - ibuf_dualtag = _RAND_56[1:0]; + buf_dual_1 = _RAND_56[0:0]; _RAND_57 = {1{`RANDOM}}; - obuf_wr_timer = _RAND_57[2:0]; + buf_dual_0 = _RAND_57[0:0]; _RAND_58 = {1{`RANDOM}}; - buf_nomerge_0 = _RAND_58[0:0]; + buf_samedw_3 = _RAND_58[0:0]; _RAND_59 = {1{`RANDOM}}; - buf_nomerge_1 = _RAND_59[0:0]; + buf_samedw_2 = _RAND_59[0:0]; _RAND_60 = {1{`RANDOM}}; - buf_nomerge_2 = _RAND_60[0:0]; + buf_samedw_1 = _RAND_60[0:0]; _RAND_61 = {1{`RANDOM}}; - buf_nomerge_3 = _RAND_61[0:0]; + buf_samedw_0 = _RAND_61[0:0]; _RAND_62 = {1{`RANDOM}}; - buf_sideeffect_0 = _RAND_62[0:0]; + obuf_write = _RAND_62[0:0]; _RAND_63 = {1{`RANDOM}}; - buf_sideeffect_1 = _RAND_63[0:0]; + obuf_cmd_done = _RAND_63[0:0]; _RAND_64 = {1{`RANDOM}}; - buf_sideeffect_2 = _RAND_64[0:0]; + obuf_data_done = _RAND_64[0:0]; _RAND_65 = {1{`RANDOM}}; - buf_sideeffect_3 = _RAND_65[0:0]; + obuf_nosend = _RAND_65[0:0]; _RAND_66 = {1{`RANDOM}}; - obuf_sideeffect = _RAND_66[0:0]; + obuf_addr = _RAND_66[31:0]; _RAND_67 = {1{`RANDOM}}; - buf_dual_0 = _RAND_67[0:0]; + buf_sz_0 = _RAND_67[1:0]; _RAND_68 = {1{`RANDOM}}; - buf_dual_1 = _RAND_68[0:0]; + buf_sz_1 = _RAND_68[1:0]; _RAND_69 = {1{`RANDOM}}; - buf_dual_2 = _RAND_69[0:0]; + buf_sz_2 = _RAND_69[1:0]; _RAND_70 = {1{`RANDOM}}; - buf_dual_3 = _RAND_70[0:0]; + buf_sz_3 = _RAND_70[1:0]; _RAND_71 = {1{`RANDOM}}; - buf_samedw_0 = _RAND_71[0:0]; + obuf_sideeffect = _RAND_71[0:0]; _RAND_72 = {1{`RANDOM}}; - buf_samedw_1 = _RAND_72[0:0]; + obuf_rdrsp_pend = _RAND_72[0:0]; _RAND_73 = {1{`RANDOM}}; - buf_samedw_2 = _RAND_73[0:0]; + obuf_rdrsp_tag = _RAND_73[2:0]; _RAND_74 = {1{`RANDOM}}; - buf_samedw_3 = _RAND_74[0:0]; + buf_dualhi_3 = _RAND_74[0:0]; _RAND_75 = {1{`RANDOM}}; - obuf_write = _RAND_75[0:0]; + buf_dualhi_2 = _RAND_75[0:0]; _RAND_76 = {1{`RANDOM}}; - obuf_cmd_done = _RAND_76[0:0]; + buf_dualhi_1 = _RAND_76[0:0]; _RAND_77 = {1{`RANDOM}}; - obuf_data_done = _RAND_77[0:0]; + buf_dualhi_0 = _RAND_77[0:0]; _RAND_78 = {1{`RANDOM}}; - obuf_nosend = _RAND_78[0:0]; - _RAND_79 = {2{`RANDOM}}; - _T_1397 = _RAND_79[63:0]; - _RAND_80 = {1{`RANDOM}}; - buf_sz_3 = _RAND_80[1:0]; + obuf_sz = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + obuf_byteen = _RAND_79[7:0]; + _RAND_80 = {2{`RANDOM}}; + obuf_data = _RAND_80[63:0]; _RAND_81 = {1{`RANDOM}}; - buf_sz_2 = _RAND_81[1:0]; + buf_rspageQ_0 = _RAND_81[3:0]; _RAND_82 = {1{`RANDOM}}; - buf_sz_1 = _RAND_82[1:0]; + buf_rspageQ_1 = _RAND_82[3:0]; _RAND_83 = {1{`RANDOM}}; - buf_sz_0 = _RAND_83[1:0]; + buf_rspageQ_2 = _RAND_83[3:0]; _RAND_84 = {1{`RANDOM}}; - obuf_rdrsp_tag = _RAND_84[2:0]; + buf_rspageQ_3 = _RAND_84[3:0]; _RAND_85 = {1{`RANDOM}}; - obuf_rdrsp_pend = _RAND_85[0:0]; + _T_4307 = _RAND_85[0:0]; _RAND_86 = {1{`RANDOM}}; - buf_dualhi_3 = _RAND_86[0:0]; + _T_4305 = _RAND_86[0:0]; _RAND_87 = {1{`RANDOM}}; - buf_dualhi_2 = _RAND_87[0:0]; + _T_4303 = _RAND_87[0:0]; _RAND_88 = {1{`RANDOM}}; - buf_dualhi_1 = _RAND_88[0:0]; + _T_4301 = _RAND_88[0:0]; _RAND_89 = {1{`RANDOM}}; - buf_dualhi_0 = _RAND_89[0:0]; - _RAND_90 = {2{`RANDOM}}; - obuf_data = _RAND_90[63:0]; + buf_ldfwdtag_0 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + buf_dualtag_0 = _RAND_90[1:0]; _RAND_91 = {1{`RANDOM}}; - obuf_sz = _RAND_91[1:0]; + buf_ldfwdtag_3 = _RAND_91[1:0]; _RAND_92 = {1{`RANDOM}}; - obuf_byteen = _RAND_92[7:0]; + buf_ldfwdtag_2 = _RAND_92[1:0]; _RAND_93 = {1{`RANDOM}}; - buf_rspageQ_0_1 = _RAND_93[0:0]; + buf_ldfwdtag_1 = _RAND_93[1:0]; _RAND_94 = {1{`RANDOM}}; - buf_rspageQ_0_0 = _RAND_94[0:0]; + buf_dualtag_1 = _RAND_94[1:0]; _RAND_95 = {1{`RANDOM}}; - buf_rspageQ_0_3 = _RAND_95[0:0]; + buf_dualtag_2 = _RAND_95[1:0]; _RAND_96 = {1{`RANDOM}}; - buf_rspageQ_0_2 = _RAND_96[0:0]; + buf_dualtag_3 = _RAND_96[1:0]; _RAND_97 = {1{`RANDOM}}; - buf_ldfwd_0 = _RAND_97[0:0]; + _T_4336 = _RAND_97[0:0]; _RAND_98 = {1{`RANDOM}}; - buf_ldfwdtag_0 = _RAND_98[1:0]; + _T_4339 = _RAND_98[0:0]; _RAND_99 = {1{`RANDOM}}; - buf_dualtag_0 = _RAND_99[1:0]; + _T_4342 = _RAND_99[0:0]; _RAND_100 = {1{`RANDOM}}; - buf_ldfwd_3 = _RAND_100[0:0]; + _T_4345 = _RAND_100[0:0]; _RAND_101 = {1{`RANDOM}}; - buf_ldfwd_2 = _RAND_101[0:0]; + _T_4411 = _RAND_101[0:0]; _RAND_102 = {1{`RANDOM}}; - buf_ldfwd_1 = _RAND_102[0:0]; + _T_4406 = _RAND_102[0:0]; _RAND_103 = {1{`RANDOM}}; - buf_ldfwdtag_3 = _RAND_103[1:0]; + _T_4401 = _RAND_103[0:0]; _RAND_104 = {1{`RANDOM}}; - buf_ldfwdtag_2 = _RAND_104[1:0]; + _T_4396 = _RAND_104[0:0]; _RAND_105 = {1{`RANDOM}}; - buf_ldfwdtag_1 = _RAND_105[1:0]; + lsu_nonblock_load_valid_r = _RAND_105[0:0]; _RAND_106 = {1{`RANDOM}}; - buf_rspageQ_3_3 = _RAND_106[0:0]; - _RAND_107 = {1{`RANDOM}}; - buf_rspageQ_3_2 = _RAND_107[0:0]; - _RAND_108 = {1{`RANDOM}}; - buf_rspageQ_3_1 = _RAND_108[0:0]; - _RAND_109 = {1{`RANDOM}}; - buf_rspageQ_3_0 = _RAND_109[0:0]; - _RAND_110 = {1{`RANDOM}}; - buf_rspageQ_2_3 = _RAND_110[0:0]; - _RAND_111 = {1{`RANDOM}}; - buf_rspageQ_2_2 = _RAND_111[0:0]; - _RAND_112 = {1{`RANDOM}}; - buf_rspageQ_2_1 = _RAND_112[0:0]; - _RAND_113 = {1{`RANDOM}}; - buf_rspageQ_2_0 = _RAND_113[0:0]; - _RAND_114 = {1{`RANDOM}}; - buf_rspageQ_1_3 = _RAND_114[0:0]; - _RAND_115 = {1{`RANDOM}}; - buf_rspageQ_1_2 = _RAND_115[0:0]; - _RAND_116 = {1{`RANDOM}}; - buf_rspageQ_1_1 = _RAND_116[0:0]; - _RAND_117 = {1{`RANDOM}}; - buf_rspageQ_1_0 = _RAND_117[0:0]; - _RAND_118 = {1{`RANDOM}}; - buf_dualtag_1 = _RAND_118[1:0]; - _RAND_119 = {1{`RANDOM}}; - buf_dualtag_2 = _RAND_119[1:0]; - _RAND_120 = {1{`RANDOM}}; - buf_dualtag_3 = _RAND_120[1:0]; - _RAND_121 = {1{`RANDOM}}; - buf_unsign_0 = _RAND_121[0:0]; - _RAND_122 = {1{`RANDOM}}; - buf_error_0 = _RAND_122[0:0]; - _RAND_123 = {1{`RANDOM}}; - buf_unsign_1 = _RAND_123[0:0]; - _RAND_124 = {1{`RANDOM}}; - buf_error_1 = _RAND_124[0:0]; - _RAND_125 = {1{`RANDOM}}; - buf_unsign_2 = _RAND_125[0:0]; - _RAND_126 = {1{`RANDOM}}; - buf_error_2 = _RAND_126[0:0]; - _RAND_127 = {1{`RANDOM}}; - buf_unsign_3 = _RAND_127[0:0]; - _RAND_128 = {1{`RANDOM}}; - buf_error_3 = _RAND_128[0:0]; - _RAND_129 = {1{`RANDOM}}; - lsu_nonblock_load_valid_r = _RAND_129[0:0]; - _RAND_130 = {1{`RANDOM}}; - _T_4338 = _RAND_130[0:0]; + _T_4984 = _RAND_106[0:0]; `endif // RANDOMIZE_REG_INIT - if (reset) begin - ibuf_addr = 32'h0; - end - if (reset) begin - ibuf_write = 1'h0; - end - if (reset) begin - ibuf_valid = 1'h0; - end - if (reset) begin - ibuf_byteen = 4'h0; - end if (reset) begin buf_addr_0 = 32'h0; end if (reset) begin - buf_write_0 = 1'h0; + _T_4360 = 1'h0; + end + if (reset) begin + _T_4357 = 1'h0; + end + if (reset) begin + _T_4354 = 1'h0; + end + if (reset) begin + _T_4351 = 1'h0; end if (reset) begin buf_state_0 = 3'h0; @@ -2445,27 +3001,18 @@ initial begin if (reset) begin buf_addr_1 = 32'h0; end - if (reset) begin - buf_write_1 = 1'h0; - end if (reset) begin buf_state_1 = 3'h0; end if (reset) begin buf_addr_2 = 32'h0; end - if (reset) begin - buf_write_2 = 1'h0; - end if (reset) begin buf_state_2 = 3'h0; end if (reset) begin buf_addr_3 = 32'h0; end - if (reset) begin - buf_write_3 = 1'h0; - end if (reset) begin buf_state_3 = 3'h0; end @@ -2482,16 +3029,16 @@ initial begin buf_byteen_0 = 4'h0; end if (reset) begin - buf_ageQ_3_3 = 1'h0; + buf_ageQ_3 = 4'h0; end if (reset) begin - obuf_tag0 = 3'h0; + _T_1848 = 2'h0; end if (reset) begin obuf_merge = 1'h0; end if (reset) begin - obuf_tag1 = 3'h0; + obuf_tag1 = 2'h0; end if (reset) begin obuf_valid = 1'h0; @@ -2500,52 +3047,25 @@ initial begin obuf_wr_enQ = 1'h0; end if (reset) begin - buf_ageQ_3_2 = 1'h0; + ibuf_addr = 32'h0; end if (reset) begin - buf_ageQ_3_1 = 1'h0; + ibuf_write = 1'h0; end if (reset) begin - buf_ageQ_3_0 = 1'h0; + ibuf_valid = 1'h0; end if (reset) begin - buf_ageQ_2_3 = 1'h0; + ibuf_byteen = 4'h0; end if (reset) begin - buf_ageQ_2_2 = 1'h0; + buf_ageQ_2 = 4'h0; end if (reset) begin - buf_ageQ_2_1 = 1'h0; + buf_ageQ_1 = 4'h0; end if (reset) begin - buf_ageQ_2_0 = 1'h0; - end - if (reset) begin - buf_ageQ_1_3 = 1'h0; - end - if (reset) begin - buf_ageQ_1_2 = 1'h0; - end - if (reset) begin - buf_ageQ_1_1 = 1'h0; - end - if (reset) begin - buf_ageQ_1_0 = 1'h0; - end - if (reset) begin - buf_ageQ_0_3 = 1'h0; - end - if (reset) begin - buf_ageQ_0_2 = 1'h0; - end - if (reset) begin - buf_ageQ_0_1 = 1'h0; - end - if (reset) begin - buf_ageQ_0_0 = 1'h0; - end - if (reset) begin - ibuf_data = 32'h0; + buf_ageQ_0 = 4'h0; end if (reset) begin buf_data_0 = 32'h0; @@ -2559,21 +3079,27 @@ initial begin if (reset) begin buf_data_3 = 32'h0; end + if (reset) begin + ibuf_data = 32'h0; + end if (reset) begin ibuf_timer = 3'h0; end if (reset) begin ibuf_sideeffect = 1'h0; end - if (reset) begin - ibuf_tag = 2'h0; - end if (reset) begin WrPtr1_r = 2'h0; end if (reset) begin WrPtr0_r = 2'h0; end + if (reset) begin + ibuf_tag = 2'h0; + end + if (reset) begin + ibuf_dualtag = 2'h0; + end if (reset) begin ibuf_dual = 1'h0; end @@ -2589,9 +3115,6 @@ initial begin if (reset) begin ibuf_sz = 2'h0; end - if (reset) begin - ibuf_dualtag = 2'h0; - end if (reset) begin obuf_wr_timer = 3'h0; end @@ -2608,43 +3131,40 @@ initial begin buf_nomerge_3 = 1'h0; end if (reset) begin - buf_sideeffect_0 = 1'h0; + _T_4330 = 1'h0; end if (reset) begin - buf_sideeffect_1 = 1'h0; + _T_4327 = 1'h0; end if (reset) begin - buf_sideeffect_2 = 1'h0; + _T_4324 = 1'h0; end if (reset) begin - buf_sideeffect_3 = 1'h0; - end - if (reset) begin - obuf_sideeffect = 1'h0; - end - if (reset) begin - buf_dual_0 = 1'h0; - end - if (reset) begin - buf_dual_1 = 1'h0; - end - if (reset) begin - buf_dual_2 = 1'h0; + _T_4321 = 1'h0; end if (reset) begin buf_dual_3 = 1'h0; end if (reset) begin - buf_samedw_0 = 1'h0; + buf_dual_2 = 1'h0; end if (reset) begin - buf_samedw_1 = 1'h0; + buf_dual_1 = 1'h0; + end + if (reset) begin + buf_dual_0 = 1'h0; + end + if (reset) begin + buf_samedw_3 = 1'h0; end if (reset) begin buf_samedw_2 = 1'h0; end if (reset) begin - buf_samedw_3 = 1'h0; + buf_samedw_1 = 1'h0; + end + if (reset) begin + buf_samedw_0 = 1'h0; end if (reset) begin obuf_write = 1'h0; @@ -2659,26 +3179,29 @@ initial begin obuf_nosend = 1'h0; end if (reset) begin - _T_1397 = 64'h0; - end - if (reset) begin - buf_sz_3 = 2'h0; - end - if (reset) begin - buf_sz_2 = 2'h0; - end - if (reset) begin - buf_sz_1 = 2'h0; + obuf_addr = 32'h0; end if (reset) begin buf_sz_0 = 2'h0; end if (reset) begin - obuf_rdrsp_tag = 3'h0; + buf_sz_1 = 2'h0; + end + if (reset) begin + buf_sz_2 = 2'h0; + end + if (reset) begin + buf_sz_3 = 2'h0; + end + if (reset) begin + obuf_sideeffect = 1'h0; end if (reset) begin obuf_rdrsp_pend = 1'h0; end + if (reset) begin + obuf_rdrsp_tag = 3'h0; + end if (reset) begin buf_dualhi_3 = 1'h0; end @@ -2691,9 +3214,6 @@ initial begin if (reset) begin buf_dualhi_0 = 1'h0; end - if (reset) begin - obuf_data = 64'h0; - end if (reset) begin obuf_sz = 2'h0; end @@ -2701,19 +3221,31 @@ initial begin obuf_byteen = 8'h0; end if (reset) begin - buf_rspageQ_0_1 = 1'h0; + obuf_data = 64'h0; end if (reset) begin - buf_rspageQ_0_0 = 1'h0; + buf_rspageQ_0 = 4'h0; end if (reset) begin - buf_rspageQ_0_3 = 1'h0; + buf_rspageQ_1 = 4'h0; end if (reset) begin - buf_rspageQ_0_2 = 1'h0; + buf_rspageQ_2 = 4'h0; end if (reset) begin - buf_ldfwd_0 = 1'h0; + buf_rspageQ_3 = 4'h0; + end + if (reset) begin + _T_4307 = 1'h0; + end + if (reset) begin + _T_4305 = 1'h0; + end + if (reset) begin + _T_4303 = 1'h0; + end + if (reset) begin + _T_4301 = 1'h0; end if (reset) begin buf_ldfwdtag_0 = 2'h0; @@ -2721,15 +3253,6 @@ initial begin if (reset) begin buf_dualtag_0 = 2'h0; end - if (reset) begin - buf_ldfwd_3 = 1'h0; - end - if (reset) begin - buf_ldfwd_2 = 1'h0; - end - if (reset) begin - buf_ldfwd_1 = 1'h0; - end if (reset) begin buf_ldfwdtag_3 = 2'h0; end @@ -2739,42 +3262,6 @@ initial begin if (reset) begin buf_ldfwdtag_1 = 2'h0; end - if (reset) begin - buf_rspageQ_3_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_3_0 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_2_0 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_3 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_2 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_1 = 1'h0; - end - if (reset) begin - buf_rspageQ_1_0 = 1'h0; - end if (reset) begin buf_dualtag_1 = 2'h0; end @@ -2785,34 +3272,34 @@ initial begin buf_dualtag_3 = 2'h0; end if (reset) begin - buf_unsign_0 = 1'h0; + _T_4336 = 1'h0; end if (reset) begin - buf_error_0 = 1'h0; + _T_4339 = 1'h0; end if (reset) begin - buf_unsign_1 = 1'h0; + _T_4342 = 1'h0; end if (reset) begin - buf_error_1 = 1'h0; + _T_4345 = 1'h0; end if (reset) begin - buf_unsign_2 = 1'h0; + _T_4411 = 1'h0; end if (reset) begin - buf_error_2 = 1'h0; + _T_4406 = 1'h0; end if (reset) begin - buf_unsign_3 = 1'h0; + _T_4401 = 1'h0; end if (reset) begin - buf_error_3 = 1'h0; + _T_4396 = 1'h0; end if (reset) begin lsu_nonblock_load_valid_r = 1'h0; end if (reset) begin - _T_4338 = 1'h0; + _T_4984 = 1'h0; end `endif // RANDOMIZE end // initial @@ -2820,15 +3307,399 @@ end // initial `FIRRTL_AFTER_INITIAL `endif `endif // SYNTHESIS - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_0 <= 32'h0; + end else if (ibuf_drainvec_vld[0]) begin + buf_addr_0 <= ibuf_addr; + end else if (_T_3343) begin + buf_addr_0 <= io_end_addr_r; + end else begin + buf_addr_0 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4360 <= 1'h0; + end else if (buf_wr_en_3) begin + _T_4360 <= buf_write_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4357 <= 1'h0; + end else if (buf_wr_en_2) begin + _T_4357 <= buf_write_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4354 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4354 <= buf_write_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4351 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4351 <= buf_write_in[0]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_0 <= 3'h0; + end else if (buf_state_en_0) begin + if (_T_3528) begin + if (io_lsu_bus_clk_en) begin + buf_state_0 <= 3'h2; + end else begin + buf_state_0 <= 3'h1; + end + end else if (_T_3551) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h2; + end + end else if (_T_3555) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3559) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h3; + end + end else if (_T_3589) begin + if (_T_3594) begin + buf_state_0 <= 3'h0; + end else if (_T_3602) begin + buf_state_0 <= 3'h4; + end else if (_T_3630) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3676) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else if (_T_3682) begin + buf_state_0 <= 3'h5; + end else begin + buf_state_0 <= 3'h6; + end + end else if (_T_3694) begin + if (io_dec_tlu_force_halt) begin + buf_state_0 <= 3'h0; + end else begin + buf_state_0 <= 3'h6; + end + end else begin + buf_state_0 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_1 <= 32'h0; + end else if (ibuf_drainvec_vld[1]) begin + buf_addr_1 <= ibuf_addr; + end else if (_T_3352) begin + buf_addr_1 <= io_end_addr_r; + end else begin + buf_addr_1 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_1 <= 3'h0; + end else if (buf_state_en_1) begin + if (_T_3721) begin + if (io_lsu_bus_clk_en) begin + buf_state_1 <= 3'h2; + end else begin + buf_state_1 <= 3'h1; + end + end else if (_T_3744) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h2; + end + end else if (_T_3748) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3559) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h3; + end + end else if (_T_3782) begin + if (_T_3787) begin + buf_state_1 <= 3'h0; + end else if (_T_3795) begin + buf_state_1 <= 3'h4; + end else if (_T_3823) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3869) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else if (_T_3875) begin + buf_state_1 <= 3'h5; + end else begin + buf_state_1 <= 3'h6; + end + end else if (_T_3887) begin + if (io_dec_tlu_force_halt) begin + buf_state_1 <= 3'h0; + end else begin + buf_state_1 <= 3'h6; + end + end else begin + buf_state_1 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_6_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_2 <= 32'h0; + end else if (ibuf_drainvec_vld[2]) begin + buf_addr_2 <= ibuf_addr; + end else if (_T_3361) begin + buf_addr_2 <= io_end_addr_r; + end else begin + buf_addr_2 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_2 <= 3'h0; + end else if (buf_state_en_2) begin + if (_T_3914) begin + if (io_lsu_bus_clk_en) begin + buf_state_2 <= 3'h2; + end else begin + buf_state_2 <= 3'h1; + end + end else if (_T_3937) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h2; + end + end else if (_T_3941) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_3559) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h3; + end + end else if (_T_3975) begin + if (_T_3980) begin + buf_state_2 <= 3'h0; + end else if (_T_3988) begin + buf_state_2 <= 3'h4; + end else if (_T_4016) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4062) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else if (_T_4068) begin + buf_state_2 <= 3'h5; + end else begin + buf_state_2 <= 3'h6; + end + end else if (_T_4080) begin + if (io_dec_tlu_force_halt) begin + buf_state_2 <= 3'h0; + end else begin + buf_state_2 <= 3'h6; + end + end else begin + buf_state_2 <= 3'h0; + end + end + end + always @(posedge rvclkhdr_7_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr_3 <= 32'h0; + end else if (ibuf_drainvec_vld[3]) begin + buf_addr_3 <= ibuf_addr; + end else if (_T_3370) begin + buf_addr_3 <= io_end_addr_r; + end else begin + buf_addr_3 <= io_lsu_addr_r; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_state_3 <= 3'h0; + end else if (buf_state_en_3) begin + if (_T_4107) begin + if (io_lsu_bus_clk_en) begin + buf_state_3 <= 3'h2; + end else begin + buf_state_3 <= 3'h1; + end + end else if (_T_4130) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h2; + end + end else if (_T_4134) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_3559) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h3; + end + end else if (_T_4168) begin + if (_T_4173) begin + buf_state_3 <= 3'h0; + end else if (_T_4181) begin + buf_state_3 <= 3'h4; + end else if (_T_4209) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4255) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else if (_T_4261) begin + buf_state_3 <= 3'h5; + end else begin + buf_state_3 <= 3'h6; + end + end else if (_T_4273) begin + if (io_dec_tlu_force_halt) begin + buf_state_3 <= 3'h0; + end else begin + buf_state_3 <= 3'h6; + end + end else begin + buf_state_3 <= 3'h0; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_3 <= 4'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_byteen_3 <= ibuf_byteen_out; + end else if (_T_3370) begin + buf_byteen_3 <= ldst_byteen_hi_r; + end else begin + buf_byteen_3 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_2 <= 4'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_byteen_2 <= ibuf_byteen_out; + end else if (_T_3361) begin + buf_byteen_2 <= ldst_byteen_hi_r; + end else begin + buf_byteen_2 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_1 <= 4'h0; + end else if (buf_wr_en_1) begin + if (ibuf_drainvec_vld[1]) begin + buf_byteen_1 <= ibuf_byteen_out; + end else if (_T_3352) begin + buf_byteen_1 <= ldst_byteen_hi_r; + end else begin + buf_byteen_1 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_byteen_0 <= 4'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_byteen_0 <= ibuf_byteen_out; + end else if (_T_3343) begin + buf_byteen_0 <= ldst_byteen_hi_r; + end else begin + buf_byteen_0 <= ldst_byteen_lo_r; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_ageQ_3 <= 4'h0; + end else begin + buf_ageQ_3 <= {_T_2535,_T_2458}; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + _T_1848 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + _T_1848 <= WrPtr0_r; + end else begin + _T_1848 <= CmdPtr0; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_merge <= 1'h0; + end else if (obuf_wr_en) begin + obuf_merge <= obuf_merge_en; + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_tag1 <= 2'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_tag1 <= WrPtr1_r; + end else begin + obuf_tag1 <= 2'h0; + end + end + end + always @(posedge io_lsu_free_c2_clk or posedge reset) begin + if (reset) begin + obuf_valid <= 1'h0; + end else begin + obuf_valid <= _T_1839 & _T_1840; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_wr_enQ <= 1'h0; + end else begin + obuf_wr_enQ <= _T_1240 & io_lsu_bus_clk_en; + end + end + always @(posedge rvclkhdr_io_l1clk or posedge reset) begin if (reset) begin ibuf_addr <= 32'h0; - end else if (ibuf_wr_en) begin - if (io_ldst_dual_r) begin - ibuf_addr <= io_end_addr_r; - end else begin - ibuf_addr <= io_lsu_addr_r; - end + end else if (io_ldst_dual_r) begin + ibuf_addr <= io_end_addr_r; + end else begin + ibuf_addr <= io_lsu_addr_r; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -2842,15 +3713,15 @@ end // initial if (reset) begin ibuf_valid <= 1'h0; end else begin - ibuf_valid <= _T_1074 & _T_1075; + ibuf_valid <= _T_1005 & _T_1006; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin ibuf_byteen <= 4'h0; end else if (ibuf_wr_en) begin - if (_T_925) begin - ibuf_byteen <= _T_945; + if (_T_866) begin + ibuf_byteen <= _T_881; end else if (io_ldst_dual_r) begin ibuf_byteen <= ldst_byteen_hi_r; end else begin @@ -2860,656 +3731,162 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_addr_0 <= 32'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_addr_0 <= ibuf_addr; - end else if (_T_3143) begin - buf_addr_0 <= io_end_addr_r; - end else begin - buf_addr_0 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_write_0 <= ibuf_write; - end else begin - buf_write_0 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_0 <= 3'h0; - end else if (buf_state_en_0) begin - if (_T_3132) begin - if (io_lsu_bus_clk_en) begin - buf_state_0 <= 3'h2; - end else begin - buf_state_0 <= 3'h1; - end - end else if (_T_3155) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else begin - buf_state_0 <= 3'h2; - end - end else if (_T_3159) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else if (_T_3163) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h3; - end - end else if (_T_3192) begin - if (_T_3196) begin - buf_state_0 <= 3'h0; - end else if (_T_3203) begin - buf_state_0 <= 3'h4; - end else if (_T_3213) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h6; - end - end else if (_T_3256) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else if (_T_3259) begin - buf_state_0 <= 3'h5; - end else begin - buf_state_0 <= 3'h6; - end - end else if (_T_3269) begin - if (io_dec_tlu_force_halt) begin - buf_state_0 <= 3'h0; - end else begin - buf_state_0 <= 3'h6; - end - end else begin - buf_state_0 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_1 <= 32'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_addr_1 <= ibuf_addr; - end else if (_T_3351) begin - buf_addr_1 <= io_end_addr_r; - end else begin - buf_addr_1 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_write_1 <= ibuf_write; - end else begin - buf_write_1 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_1 <= 3'h0; - end else if (buf_state_en_1) begin - if (_T_3340) begin - if (io_lsu_bus_clk_en) begin - buf_state_1 <= 3'h2; - end else begin - buf_state_1 <= 3'h1; - end - end else if (_T_3363) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else begin - buf_state_1 <= 3'h2; - end - end else if (_T_3367) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else if (_T_3163) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h3; - end - end else if (_T_3400) begin - if (_T_3404) begin - buf_state_1 <= 3'h0; - end else if (_T_3411) begin - buf_state_1 <= 3'h4; - end else if (_T_3421) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h6; - end - end else if (_T_3464) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else if (_T_3467) begin - buf_state_1 <= 3'h5; - end else begin - buf_state_1 <= 3'h6; - end - end else if (_T_3477) begin - if (io_dec_tlu_force_halt) begin - buf_state_1 <= 3'h0; - end else begin - buf_state_1 <= 3'h6; - end - end else begin - buf_state_1 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_2 <= 32'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_addr_2 <= ibuf_addr; - end else if (_T_3559) begin - buf_addr_2 <= io_end_addr_r; - end else begin - buf_addr_2 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_2 <= 1'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_write_2 <= ibuf_write; - end else begin - buf_write_2 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_2 <= 3'h0; - end else if (buf_state_en_2) begin - if (_T_3548) begin - if (io_lsu_bus_clk_en) begin - buf_state_2 <= 3'h2; - end else begin - buf_state_2 <= 3'h1; - end - end else if (_T_3571) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else begin - buf_state_2 <= 3'h2; - end - end else if (_T_3575) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else if (_T_3163) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h3; - end - end else if (_T_3608) begin - if (_T_3612) begin - buf_state_2 <= 3'h0; - end else if (_T_3619) begin - buf_state_2 <= 3'h4; - end else if (_T_3629) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h6; - end - end else if (_T_3672) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else if (_T_3675) begin - buf_state_2 <= 3'h5; - end else begin - buf_state_2 <= 3'h6; - end - end else if (_T_3685) begin - if (io_dec_tlu_force_halt) begin - buf_state_2 <= 3'h0; - end else begin - buf_state_2 <= 3'h6; - end - end else begin - buf_state_2 <= 3'h0; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_addr_3 <= 32'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_addr_3 <= ibuf_addr; - end else if (_T_3767) begin - buf_addr_3 <= io_end_addr_r; - end else begin - buf_addr_3 <= io_lsu_addr_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_write_3 <= 1'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_write_3 <= ibuf_write; - end else begin - buf_write_3 <= io_lsu_pkt_r_store; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_state_3 <= 3'h0; - end else if (buf_state_en_3) begin - if (_T_3756) begin - if (io_lsu_bus_clk_en) begin - buf_state_3 <= 3'h2; - end else begin - buf_state_3 <= 3'h1; - end - end else if (_T_3779) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else begin - buf_state_3 <= 3'h2; - end - end else if (_T_3783) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else if (_T_3163) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h3; - end - end else if (_T_3816) begin - if (_T_3820) begin - buf_state_3 <= 3'h0; - end else if (_T_3827) begin - buf_state_3 <= 3'h4; - end else if (_T_3837) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h6; - end - end else if (_T_3880) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else if (_T_3883) begin - buf_state_3 <= 3'h5; - end else begin - buf_state_3 <= 3'h6; - end - end else if (_T_3893) begin - if (io_dec_tlu_force_halt) begin - buf_state_3 <= 3'h0; - end else begin - buf_state_3 <= 3'h6; - end - end else begin - buf_state_3 <= 3'h0; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_3 <= 4'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_byteen_3 <= ibuf_byteen_out; - end else if (_T_3767) begin - buf_byteen_3 <= ldst_byteen_hi_r; - end else begin - buf_byteen_3 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_2 <= 4'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_byteen_2 <= ibuf_byteen_out; - end else if (_T_3559) begin - buf_byteen_2 <= ldst_byteen_hi_r; - end else begin - buf_byteen_2 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_1 <= 4'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_byteen_1 <= ibuf_byteen_out; - end else if (_T_3351) begin - buf_byteen_1 <= ldst_byteen_hi_r; - end else begin - buf_byteen_1 <= ldst_byteen_lo_r; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - buf_byteen_0 <= 4'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_byteen_0 <= ibuf_byteen_out; - end else if (_T_3143) begin - buf_byteen_0 <= ldst_byteen_hi_r; - end else begin - buf_byteen_0 <= ldst_byteen_lo_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_3_3 <= 1'h0; + buf_ageQ_2 <= 4'h0; end else begin - buf_ageQ_3_3 <= _T_3013 | buf_age_3_3; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_tag0 <= 3'h0; - end else if (obuf_wr_en) begin - obuf_tag0 <= obuf_tag0_in; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_merge <= 1'h0; - end else if (obuf_wr_en) begin - obuf_merge <= obuf_merge_en; - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_tag1 <= 3'h0; - end else if (obuf_wr_en) begin - obuf_tag1 <= obuf_tag1_in; - end - end - always @(posedge io_lsu_free_c2_clk or posedge reset) begin - if (reset) begin - obuf_valid <= 1'h0; - end else begin - obuf_valid <= _T_1406 & _T_1407; - end - end - always @(posedge io_lsu_busm_clk or posedge reset) begin - if (reset) begin - obuf_wr_enQ <= 1'h0; - end else begin - obuf_wr_enQ <= _T_1155 & io_lsu_bus_clk_en; + buf_ageQ_2 <= {_T_2433,_T_2356}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ageQ_3_2 <= 1'h0; + buf_ageQ_1 <= 4'h0; end else begin - buf_ageQ_3_2 <= _T_2918 | buf_age_3_2; + buf_ageQ_1 <= {_T_2331,_T_2254}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ageQ_3_1 <= 1'h0; + buf_ageQ_0 <= 4'h0; end else begin - buf_ageQ_3_1 <= _T_2823 | buf_age_3_1; + buf_ageQ_0 <= {_T_2229,_T_2152}; end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_3_0 <= 1'h0; - end else begin - buf_ageQ_3_0 <= _T_2728 | buf_age_3_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_3 <= 1'h0; - end else begin - buf_ageQ_2_3 <= _T_2633 | buf_age_2_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_2 <= 1'h0; - end else begin - buf_ageQ_2_2 <= _T_2538 | buf_age_2_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_1 <= 1'h0; - end else begin - buf_ageQ_2_1 <= _T_2443 | buf_age_2_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_2_0 <= 1'h0; - end else begin - buf_ageQ_2_0 <= _T_2348 | buf_age_2_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_3 <= 1'h0; - end else begin - buf_ageQ_1_3 <= _T_2253 | buf_age_1_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_2 <= 1'h0; - end else begin - buf_ageQ_1_2 <= _T_2158 | buf_age_1_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_1 <= 1'h0; - end else begin - buf_ageQ_1_1 <= _T_2063 | buf_age_1_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_1_0 <= 1'h0; - end else begin - buf_ageQ_1_0 <= _T_1968 | buf_age_1_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_3 <= 1'h0; - end else begin - buf_ageQ_0_3 <= _T_1873 | buf_age_0_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_2 <= 1'h0; - end else begin - buf_ageQ_0_2 <= _T_1778 | buf_age_0_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_1 <= 1'h0; - end else begin - buf_ageQ_0_1 <= _T_1683 | buf_age_0_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ageQ_0_0 <= 1'h0; - end else begin - buf_ageQ_0_0 <= _T_1588 | buf_age_0_0; - end - end - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin - if (reset) begin - ibuf_data <= 32'h0; - end else if (ibuf_wr_en) begin - ibuf_data <= ibuf_data_in; - end - end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_8_io_l1clk or posedge reset) begin if (reset) begin buf_data_0 <= 32'h0; - end else if (buf_data_en_0) begin - if (_T_3132) begin - if (_T_3147) begin - buf_data_0 <= ibuf_data_out; - end else begin - buf_data_0 <= store_data_lo_r; - end - end else if (_T_3155) begin - buf_data_0 <= 32'h0; - end else if (_T_3159) begin - if (buf_error_en_0) begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_0[2]) begin + end else if (_T_3528) begin + if (_T_3543) begin + buf_data_0 <= ibuf_data_out; + end else begin + buf_data_0 <= store_data_lo_r; + end + end else if (_T_3551) begin + buf_data_0 <= 32'h0; + end else if (_T_3555) begin + if (buf_error_en_0) begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_0[2]) begin + buf_data_0 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_0 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3589) begin + if (_T_3669) begin + if (buf_addr_0[2]) begin buf_data_0 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_0 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3192) begin - if (_T_3249) begin - if (buf_addr_0[2]) begin - buf_data_0 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_0 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_0 <= 32'h0; + buf_data_0 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_0 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_9_io_l1clk or posedge reset) begin if (reset) begin buf_data_1 <= 32'h0; - end else if (buf_data_en_1) begin - if (_T_3340) begin - if (_T_3355) begin - buf_data_1 <= ibuf_data_out; - end else begin - buf_data_1 <= store_data_lo_r; - end - end else if (_T_3363) begin - buf_data_1 <= 32'h0; - end else if (_T_3367) begin - if (buf_error_en_1) begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_1[2]) begin + end else if (_T_3721) begin + if (_T_3736) begin + buf_data_1 <= ibuf_data_out; + end else begin + buf_data_1 <= store_data_lo_r; + end + end else if (_T_3744) begin + buf_data_1 <= 32'h0; + end else if (_T_3748) begin + if (buf_error_en_1) begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_1[2]) begin + buf_data_1 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_1 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3782) begin + if (_T_3862) begin + if (buf_addr_1[2]) begin buf_data_1 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_1 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3400) begin - if (_T_3457) begin - if (buf_addr_1[2]) begin - buf_data_1 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_1 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_1 <= 32'h0; + buf_data_1 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_1 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_10_io_l1clk or posedge reset) begin if (reset) begin buf_data_2 <= 32'h0; - end else if (buf_data_en_2) begin - if (_T_3548) begin - if (_T_3563) begin - buf_data_2 <= ibuf_data_out; - end else begin - buf_data_2 <= store_data_lo_r; - end - end else if (_T_3571) begin - buf_data_2 <= 32'h0; - end else if (_T_3575) begin - if (buf_error_en_2) begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_2[2]) begin + end else if (_T_3914) begin + if (_T_3929) begin + buf_data_2 <= ibuf_data_out; + end else begin + buf_data_2 <= store_data_lo_r; + end + end else if (_T_3937) begin + buf_data_2 <= 32'h0; + end else if (_T_3941) begin + if (buf_error_en_2) begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_2[2]) begin + buf_data_2 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_2 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_3975) begin + if (_T_4055) begin + if (buf_addr_2[2]) begin buf_data_2 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_2 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3608) begin - if (_T_3665) begin - if (buf_addr_2[2]) begin - buf_data_2 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_2 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_2 <= 32'h0; + buf_data_2 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_2 <= 32'h0; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_11_io_l1clk or posedge reset) begin if (reset) begin buf_data_3 <= 32'h0; - end else if (buf_data_en_3) begin - if (_T_3756) begin - if (_T_3771) begin - buf_data_3 <= ibuf_data_out; - end else begin - buf_data_3 <= store_data_lo_r; - end - end else if (_T_3779) begin - buf_data_3 <= 32'h0; - end else if (_T_3783) begin - if (buf_error_en_3) begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end else if (buf_addr_3[2]) begin + end else if (_T_4107) begin + if (_T_4122) begin + buf_data_3 <= ibuf_data_out; + end else begin + buf_data_3 <= store_data_lo_r; + end + end else if (_T_4130) begin + buf_data_3 <= 32'h0; + end else if (_T_4134) begin + if (buf_error_en_3) begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end else if (buf_addr_3[2]) begin + buf_data_3 <= io_lsu_axi_rdata[63:32]; + end else begin + buf_data_3 <= io_lsu_axi_rdata[31:0]; + end + end else if (_T_4168) begin + if (_T_4248) begin + if (buf_addr_3[2]) begin buf_data_3 <= io_lsu_axi_rdata[63:32]; end else begin buf_data_3 <= io_lsu_axi_rdata[31:0]; end - end else if (_T_3816) begin - if (_T_3873) begin - if (buf_addr_3[2]) begin - buf_data_3 <= io_lsu_axi_rdata[63:32]; - end else begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end - end else begin - buf_data_3 <= io_lsu_axi_rdata[31:0]; - end end else begin - buf_data_3 <= 32'h0; + buf_data_3 <= io_lsu_axi_rdata[31:0]; end + end else begin + buf_data_3 <= 32'h0; + end + end + always @(posedge rvclkhdr_1_io_l1clk or posedge reset) begin + if (reset) begin + ibuf_data <= 32'h0; + end else begin + ibuf_data <= {_T_922,_T_893}; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -3517,8 +3894,8 @@ end // initial ibuf_timer <= 3'h0; end else if (ibuf_wr_en) begin ibuf_timer <= 3'h0; - end else if (_T_989) begin - ibuf_timer <= _T_991; + end else if (_T_923) begin + ibuf_timer <= _T_926; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -3528,11 +3905,37 @@ end // initial ibuf_sideeffect <= io_is_sideeffects_r; end end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr1_r <= 2'h0; + end else if (_T_1914) begin + WrPtr1_r <= 2'h0; + end else if (_T_1928) begin + WrPtr1_r <= 2'h1; + end else if (_T_1942) begin + WrPtr1_r <= 2'h2; + end else begin + WrPtr1_r <= 2'h3; + end + end + always @(posedge io_lsu_c2_r_clk or posedge reset) begin + if (reset) begin + WrPtr0_r <= 2'h0; + end else if (_T_1863) begin + WrPtr0_r <= 2'h0; + end else if (_T_1874) begin + WrPtr0_r <= 2'h1; + end else if (_T_1885) begin + WrPtr0_r <= 2'h2; + end else begin + WrPtr0_r <= 2'h3; + end + end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin ibuf_tag <= 2'h0; end else if (ibuf_wr_en) begin - if (!(_T_925)) begin + if (!(_T_866)) begin if (io_ldst_dual_r) begin ibuf_tag <= WrPtr1_r; end else begin @@ -3541,34 +3944,11 @@ end // initial end end end - always @(posedge io_lsu_c2_r_clk or posedge reset) begin + always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin if (reset) begin - WrPtr1_r <= 2'h0; - end else if (_T_1483) begin - WrPtr1_r <= 2'h0; - end else if (_T_1498) begin - WrPtr1_r <= 2'h1; - end else if (_T_1513) begin - WrPtr1_r <= 2'h2; - end else if (_T_1528) begin - WrPtr1_r <= 2'h3; - end else begin - WrPtr1_r <= 2'h0; - end - end - always @(posedge io_lsu_c2_r_clk or posedge reset) begin - if (reset) begin - WrPtr0_r <= 2'h0; - end else if (_T_1428) begin - WrPtr0_r <= 2'h0; - end else if (_T_1440) begin - WrPtr0_r <= 2'h1; - end else if (_T_1452) begin - WrPtr0_r <= 2'h2; - end else if (_T_1464) begin - WrPtr0_r <= 2'h3; - end else begin - WrPtr0_r <= 2'h0; + ibuf_dualtag <= 2'h0; + end else if (ibuf_wr_en) begin + ibuf_dualtag <= WrPtr0_r; end end always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin @@ -3606,213 +3986,125 @@ end // initial ibuf_sz <= ibuf_sz_in; end end - always @(posedge io_lsu_bus_ibuf_c1_clk or posedge reset) begin - if (reset) begin - ibuf_dualtag <= 2'h0; - end else if (ibuf_wr_en) begin - ibuf_dualtag <= WrPtr0_r; - end - end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_wr_timer <= 3'h0; end else if (obuf_wr_en) begin obuf_wr_timer <= 3'h0; - end else if (_T_1348) begin - obuf_wr_timer <= _T_1350; + end else if (_T_1058) begin + obuf_wr_timer <= _T_1060; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_0 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_nomerge_0 <= _T_3115; - end else begin - buf_nomerge_0 <= io_no_dword_merge_r; - end + buf_nomerge_0 <= buf_nomerge_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_1 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_nomerge_1 <= _T_3115; - end else begin - buf_nomerge_1 <= io_no_dword_merge_r; - end + buf_nomerge_1 <= buf_nomerge_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_nomerge_2 <= _T_3115; - end else begin - buf_nomerge_2 <= io_no_dword_merge_r; - end + buf_nomerge_2 <= buf_nomerge_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_nomerge_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_nomerge_3 <= _T_3115; - end else begin - buf_nomerge_3 <= io_no_dword_merge_r; - end + buf_nomerge_3 <= buf_nomerge_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sideeffect_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_sideeffect_0 <= ibuf_sideeffect; - end else begin - buf_sideeffect_0 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_sideeffect_1 <= ibuf_sideeffect; - end else begin - buf_sideeffect_1 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_2 <= 1'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_sideeffect_2 <= ibuf_sideeffect; - end else begin - buf_sideeffect_2 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sideeffect_3 <= 1'h0; + _T_4330 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_sideeffect_3 <= ibuf_sideeffect; - end else begin - buf_sideeffect_3 <= io_is_sideeffects_r; - end - end - end - always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin - if (reset) begin - obuf_sideeffect <= 1'h0; - end else if (obuf_wr_en) begin - if (ibuf_buf_byp) begin - obuf_sideeffect <= io_is_sideeffects_r; - end else if (2'h3 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_3; - end else if (2'h2 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_2; - end else if (2'h1 == CmdPtr0) begin - obuf_sideeffect <= buf_sideeffect_1; - end else begin - obuf_sideeffect <= buf_sideeffect_0; - end + _T_4330 <= buf_sideeffect_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_dual_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_dual_0 <= ibuf_dual; - end else begin - buf_dual_0 <= io_ldst_dual_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_dual_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_dual_1 <= ibuf_dual; - end else begin - buf_dual_1 <= io_ldst_dual_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_dual_2 <= 1'h0; + _T_4327 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_dual_2 <= ibuf_dual; - end else begin - buf_dual_2 <= io_ldst_dual_r; - end + _T_4327 <= buf_sideeffect_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4324 <= 1'h0; + end else if (buf_wr_en_1) begin + _T_4324 <= buf_sideeffect_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4321 <= 1'h0; + end else if (buf_wr_en_0) begin + _T_4321 <= buf_sideeffect_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dual_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_dual_3 <= ibuf_dual; - end else begin - buf_dual_3 <= io_ldst_dual_r; - end + buf_dual_3 <= buf_dual_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_samedw_0 <= 1'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_samedw_0 <= ibuf_samedw; - end else begin - buf_samedw_0 <= ldst_samedw_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_samedw_1 <= 1'h0; - end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_samedw_1 <= ibuf_samedw; - end else begin - buf_samedw_1 <= ldst_samedw_r; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_samedw_2 <= 1'h0; + buf_dual_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_samedw_2 <= ibuf_samedw; - end else begin - buf_samedw_2 <= ldst_samedw_r; - end + buf_dual_2 <= buf_dual_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_dual_1 <= buf_dual_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_dual_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_dual_0 <= buf_dual_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_samedw_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_samedw_3 <= ibuf_samedw; - end else begin - buf_samedw_3 <= ldst_samedw_r; - end + buf_samedw_3 <= buf_samedw_in[3]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_2 <= 1'h0; + end else if (buf_wr_en_2) begin + buf_samedw_2 <= buf_samedw_in[2]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_1 <= 1'h0; + end else if (buf_wr_en_1) begin + buf_samedw_1 <= buf_samedw_in[1]; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + buf_samedw_0 <= 1'h0; + end else if (buf_wr_en_0) begin + buf_samedw_0 <= buf_samedw_in[0]; end end always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin @@ -3821,14 +4113,8 @@ end // initial end else if (obuf_wr_en) begin if (ibuf_buf_byp) begin obuf_write <= io_lsu_pkt_r_store; - end else if (2'h3 == CmdPtr0) begin - obuf_write <= buf_write_3; - end else if (2'h2 == CmdPtr0) begin - obuf_write <= buf_write_2; - end else if (2'h1 == CmdPtr0) begin - obuf_write <= buf_write_1; end else begin - obuf_write <= buf_write_0; + obuf_write <= _T_1202; end end end @@ -3836,14 +4122,14 @@ end // initial if (reset) begin obuf_cmd_done <= 1'h0; end else begin - obuf_cmd_done <= _T_1302 & _T_4316; + obuf_cmd_done <= _T_1305 & _T_4860; end end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_data_done <= 1'h0; end else begin - obuf_data_done <= _T_1302 & _T_4317; + obuf_data_done <= _T_1305 & _T_4861; end end always @(posedge io_lsu_free_c2_clk or posedge reset) begin @@ -3853,32 +4139,23 @@ end // initial obuf_nosend <= obuf_nosend_in; end end - always @(posedge clock or posedge reset) begin + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin if (reset) begin - _T_1397 <= 64'h0; - end else if (obuf_wr_en) begin - _T_1397 <= obuf_addr_in; + obuf_addr <= 32'h0; + end else if (ibuf_buf_byp) begin + obuf_addr <= io_lsu_addr_r; + end else begin + obuf_addr <= _T_1289; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sz_3 <= 2'h0; - end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_sz_3 <= ibuf_sz; + buf_sz_0 <= 2'h0; + end else if (buf_wr_en_0) begin + if (ibuf_drainvec_vld[0]) begin + buf_sz_0 <= ibuf_sz; end else begin - buf_sz_3 <= ibuf_sz_in; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_sz_2 <= 2'h0; - end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_sz_2 <= ibuf_sz; - end else begin - buf_sz_2 <= ibuf_sz_in; + buf_sz_0 <= ibuf_sz_in; end end end @@ -3886,7 +4163,7 @@ end // initial if (reset) begin buf_sz_1 <= 2'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin + if (ibuf_drainvec_vld[1]) begin buf_sz_1 <= ibuf_sz; end else begin buf_sz_1 <= ibuf_sz_in; @@ -3895,78 +4172,77 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_sz_0 <= 2'h0; - end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_sz_0 <= ibuf_sz; + buf_sz_2 <= 2'h0; + end else if (buf_wr_en_2) begin + if (ibuf_drainvec_vld[2]) begin + buf_sz_2 <= ibuf_sz; end else begin - buf_sz_0 <= ibuf_sz_in; + buf_sz_2 <= ibuf_sz_in; end end end - always @(posedge io_lsu_busm_clk or posedge reset) begin + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - obuf_rdrsp_tag <= 3'h0; - end else if (_T_1193) begin - obuf_rdrsp_tag <= obuf_tag0; + buf_sz_3 <= 2'h0; + end else if (buf_wr_en_3) begin + if (ibuf_drainvec_vld[3]) begin + buf_sz_3 <= ibuf_sz; + end else begin + buf_sz_3 <= ibuf_sz_in; + end + end + end + always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin + if (reset) begin + obuf_sideeffect <= 1'h0; + end else if (obuf_wr_en) begin + if (ibuf_buf_byp) begin + obuf_sideeffect <= io_is_sideeffects_r; + end else begin + obuf_sideeffect <= _T_1051; + end end end always @(posedge io_lsu_busm_clk or posedge reset) begin if (reset) begin obuf_rdrsp_pend <= 1'h0; end else begin - obuf_rdrsp_pend <= _T_1191 | _T_1195; + obuf_rdrsp_pend <= _T_1330 | _T_1334; + end + end + always @(posedge io_lsu_busm_clk or posedge reset) begin + if (reset) begin + obuf_rdrsp_tag <= 3'h0; + end else if (_T_1332) begin + obuf_rdrsp_tag <= obuf_tag0; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_3 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_dualhi_3 <= ibuf_dual; - end else begin - buf_dualhi_3 <= _T_3767; - end + buf_dualhi_3 <= buf_dualhi_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_2 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_dualhi_2 <= ibuf_dual; - end else begin - buf_dualhi_2 <= _T_3559; - end + buf_dualhi_2 <= buf_dualhi_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_1 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_dualhi_1 <= ibuf_dual; - end else begin - buf_dualhi_1 <= _T_3351; - end + buf_dualhi_1 <= buf_dualhi_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualhi_0 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_dualhi_0 <= ibuf_dual; - end else begin - buf_dualhi_0 <= _T_3143; - end - end - end - always @(posedge clock or posedge reset) begin - if (reset) begin - obuf_data <= 64'h0; - end else if (obuf_wr_en) begin - obuf_data <= obuf_data_in; + buf_dualhi_0 <= buf_dualhi_in[0]; end end always @(posedge io_lsu_bus_obuf_c1_clk or posedge reset) begin @@ -3975,14 +4251,8 @@ end // initial end else if (obuf_wr_en) begin if (ibuf_buf_byp) begin obuf_sz <= ibuf_sz_in; - end else if (2'h3 == CmdPtr0) begin - obuf_sz <= buf_sz_3; - end else if (2'h2 == CmdPtr0) begin - obuf_sz <= buf_sz_2; - end else if (2'h1 == CmdPtr0) begin - obuf_sz <= buf_sz_1; end else begin - obuf_sz <= buf_sz_0; + obuf_sz <= _T_1302; end end end @@ -3993,44 +4263,90 @@ end // initial obuf_byteen <= obuf_byteen_in; end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_1 <= 1'h0; + obuf_data <= 64'h0; end else begin - buf_rspageQ_0_1 <= buf_rspage_set_0_1 | buf_rspage_0_1; + obuf_data <= {_T_1620,_T_1579}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_0 <= 1'h0; + buf_rspageQ_0 <= 4'h0; end else begin - buf_rspageQ_0_0 <= buf_rspage_set_0_0 | buf_rspage_0_0; + buf_rspageQ_0 <= {_T_3173,_T_3162}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_3 <= 1'h0; + buf_rspageQ_1 <= 4'h0; end else begin - buf_rspageQ_0_3 <= buf_rspage_set_0_3 | buf_rspage_0_3; + buf_rspageQ_1 <= {_T_3188,_T_3177}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_rspageQ_0_2 <= 1'h0; + buf_rspageQ_2 <= 4'h0; end else begin - buf_rspageQ_0_2 <= buf_rspage_set_0_2 | buf_rspage_0_2; + buf_rspageQ_2 <= {_T_3203,_T_3192}; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_ldfwd_0 <= 1'h0; - end else if (buf_ldfwd_en_0) begin - if (_T_3132) begin - buf_ldfwd_0 <= 1'h0; - end else if (_T_3155) begin - buf_ldfwd_0 <= 1'h0; + buf_rspageQ_3 <= 4'h0; + end else begin + buf_rspageQ_3 <= {_T_3218,_T_3207}; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4307 <= 1'h0; + end else if (buf_ldfwd_en_3) begin + if (_T_4107) begin + _T_4307 <= 1'h0; + end else if (_T_4130) begin + _T_4307 <= 1'h0; end else begin - buf_ldfwd_0 <= _T_3159; + _T_4307 <= _T_4134; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4305 <= 1'h0; + end else if (buf_ldfwd_en_2) begin + if (_T_3914) begin + _T_4305 <= 1'h0; + end else if (_T_3937) begin + _T_4305 <= 1'h0; + end else begin + _T_4305 <= _T_3941; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4303 <= 1'h0; + end else if (buf_ldfwd_en_1) begin + if (_T_3721) begin + _T_4303 <= 1'h0; + end else if (_T_3744) begin + _T_4303 <= 1'h0; + end else begin + _T_4303 <= _T_3748; + end + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4301 <= 1'h0; + end else if (buf_ldfwd_en_0) begin + if (_T_3528) begin + _T_4301 <= 1'h0; + end else if (_T_3551) begin + _T_4301 <= 1'h0; + end else begin + _T_4301 <= _T_3555; end end end @@ -4038,11 +4354,11 @@ end // initial if (reset) begin buf_ldfwdtag_0 <= 2'h0; end else if (buf_ldfwd_en_0) begin - if (_T_3132) begin + if (_T_3528) begin buf_ldfwdtag_0 <= 2'h0; - end else if (_T_3155) begin + end else if (_T_3551) begin buf_ldfwdtag_0 <= 2'h0; - end else if (_T_3159) begin + end else if (_T_3555) begin buf_ldfwdtag_0 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_0 <= 2'h0; @@ -4053,63 +4369,24 @@ end // initial if (reset) begin buf_dualtag_0 <= 2'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin + if (ibuf_drainvec_vld[0]) begin buf_dualtag_0 <= ibuf_dualtag; - end else if (_T_3143) begin + end else if (_T_3343) begin buf_dualtag_0 <= WrPtr0_r; end else begin buf_dualtag_0 <= WrPtr1_r; end end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_3 <= 1'h0; - end else if (buf_ldfwd_en_3) begin - if (_T_3756) begin - buf_ldfwd_3 <= 1'h0; - end else if (_T_3779) begin - buf_ldfwd_3 <= 1'h0; - end else begin - buf_ldfwd_3 <= _T_3783; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_2 <= 1'h0; - end else if (buf_ldfwd_en_2) begin - if (_T_3548) begin - buf_ldfwd_2 <= 1'h0; - end else if (_T_3571) begin - buf_ldfwd_2 <= 1'h0; - end else begin - buf_ldfwd_2 <= _T_3575; - end - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_ldfwd_1 <= 1'h0; - end else if (buf_ldfwd_en_1) begin - if (_T_3340) begin - buf_ldfwd_1 <= 1'h0; - end else if (_T_3363) begin - buf_ldfwd_1 <= 1'h0; - end else begin - buf_ldfwd_1 <= _T_3367; - end - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_ldfwdtag_3 <= 2'h0; end else if (buf_ldfwd_en_3) begin - if (_T_3756) begin + if (_T_4107) begin buf_ldfwdtag_3 <= 2'h0; - end else if (_T_3779) begin + end else if (_T_4130) begin buf_ldfwdtag_3 <= 2'h0; - end else if (_T_3783) begin + end else if (_T_4134) begin buf_ldfwdtag_3 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_3 <= 2'h0; @@ -4120,11 +4397,11 @@ end // initial if (reset) begin buf_ldfwdtag_2 <= 2'h0; end else if (buf_ldfwd_en_2) begin - if (_T_3548) begin + if (_T_3914) begin buf_ldfwdtag_2 <= 2'h0; - end else if (_T_3571) begin + end else if (_T_3937) begin buf_ldfwdtag_2 <= 2'h0; - end else if (_T_3575) begin + end else if (_T_3941) begin buf_ldfwdtag_2 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_2 <= 2'h0; @@ -4135,108 +4412,24 @@ end // initial if (reset) begin buf_ldfwdtag_1 <= 2'h0; end else if (buf_ldfwd_en_1) begin - if (_T_3340) begin + if (_T_3721) begin buf_ldfwdtag_1 <= 2'h0; - end else if (_T_3363) begin + end else if (_T_3744) begin buf_ldfwdtag_1 <= 2'h0; - end else if (_T_3367) begin + end else if (_T_3748) begin buf_ldfwdtag_1 <= obuf_rdrsp_tag[1:0]; end else begin buf_ldfwdtag_1 <= 2'h0; end end end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_3 <= 1'h0; - end else begin - buf_rspageQ_3_3 <= buf_rspage_set_3_3 | buf_rspage_3_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_2 <= 1'h0; - end else begin - buf_rspageQ_3_2 <= buf_rspage_set_3_2 | buf_rspage_3_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_1 <= 1'h0; - end else begin - buf_rspageQ_3_1 <= buf_rspage_set_3_1 | buf_rspage_3_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_3_0 <= 1'h0; - end else begin - buf_rspageQ_3_0 <= buf_rspage_set_3_0 | buf_rspage_3_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_3 <= 1'h0; - end else begin - buf_rspageQ_2_3 <= buf_rspage_set_2_3 | buf_rspage_2_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_2 <= 1'h0; - end else begin - buf_rspageQ_2_2 <= buf_rspage_set_2_2 | buf_rspage_2_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_1 <= 1'h0; - end else begin - buf_rspageQ_2_1 <= buf_rspage_set_2_1 | buf_rspage_2_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_2_0 <= 1'h0; - end else begin - buf_rspageQ_2_0 <= buf_rspage_set_2_0 | buf_rspage_2_0; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_3 <= 1'h0; - end else begin - buf_rspageQ_1_3 <= buf_rspage_set_1_3 | buf_rspage_1_3; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_2 <= 1'h0; - end else begin - buf_rspageQ_1_2 <= buf_rspage_set_1_2 | buf_rspage_1_2; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_1 <= 1'h0; - end else begin - buf_rspageQ_1_1 <= buf_rspage_set_1_1 | buf_rspage_1_1; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_rspageQ_1_0 <= 1'h0; - end else begin - buf_rspageQ_1_0 <= buf_rspage_set_1_0 | buf_rspage_1_0; - end - end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin buf_dualtag_1 <= 2'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin + if (ibuf_drainvec_vld[1]) begin buf_dualtag_1 <= ibuf_dualtag; - end else if (_T_3351) begin + end else if (_T_3352) begin buf_dualtag_1 <= WrPtr0_r; end else begin buf_dualtag_1 <= WrPtr1_r; @@ -4247,9 +4440,9 @@ end // initial if (reset) begin buf_dualtag_2 <= 2'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin + if (ibuf_drainvec_vld[2]) begin buf_dualtag_2 <= ibuf_dualtag; - end else if (_T_3559) begin + end else if (_T_3361) begin buf_dualtag_2 <= WrPtr0_r; end else begin buf_dualtag_2 <= WrPtr1_r; @@ -4260,9 +4453,9 @@ end // initial if (reset) begin buf_dualtag_3 <= 2'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin + if (ibuf_drainvec_vld[3]) begin buf_dualtag_3 <= ibuf_dualtag; - end else if (_T_3767) begin + end else if (_T_3370) begin buf_dualtag_3 <= WrPtr0_r; end else begin buf_dualtag_3 <= WrPtr1_r; @@ -4271,74 +4464,58 @@ end // initial end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_unsign_0 <= 1'h0; + _T_4336 <= 1'h0; end else if (buf_wr_en_0) begin - if (_T_3147) begin - buf_unsign_0 <= ibuf_unsign; - end else begin - buf_unsign_0 <= io_lsu_pkt_r_unsign; - end + _T_4336 <= buf_unsign_in[0]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_0 <= 1'h0; - end else if (_T_3294) begin - buf_error_0 <= _T_3293; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_1 <= 1'h0; + _T_4339 <= 1'h0; end else if (buf_wr_en_1) begin - if (_T_3355) begin - buf_unsign_1 <= ibuf_unsign; - end else begin - buf_unsign_1 <= io_lsu_pkt_r_unsign; - end + _T_4339 <= buf_unsign_in[1]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_1 <= 1'h0; - end else if (_T_3502) begin - buf_error_1 <= _T_3501; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_2 <= 1'h0; + _T_4342 <= 1'h0; end else if (buf_wr_en_2) begin - if (_T_3563) begin - buf_unsign_2 <= ibuf_unsign; - end else begin - buf_unsign_2 <= io_lsu_pkt_r_unsign; - end + _T_4342 <= buf_unsign_in[2]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_2 <= 1'h0; - end else if (_T_3710) begin - buf_error_2 <= _T_3709; - end - end - always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin - if (reset) begin - buf_unsign_3 <= 1'h0; + _T_4345 <= 1'h0; end else if (buf_wr_en_3) begin - if (_T_3771) begin - buf_unsign_3 <= ibuf_unsign; - end else begin - buf_unsign_3 <= io_lsu_pkt_r_unsign; - end + _T_4345 <= buf_unsign_in[3]; end end always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin if (reset) begin - buf_error_3 <= 1'h0; - end else if (_T_3918) begin - buf_error_3 <= _T_3917; + _T_4411 <= 1'h0; + end else begin + _T_4411 <= _T_4408 & _T_4409; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4406 <= 1'h0; + end else begin + _T_4406 <= _T_4403 & _T_4404; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4401 <= 1'h0; + end else begin + _T_4401 <= _T_4398 & _T_4399; + end + end + always @(posedge io_lsu_bus_buf_c1_clk or posedge reset) begin + if (reset) begin + _T_4396 <= 1'h0; + end else begin + _T_4396 <= _T_4393 & _T_4394; end end always @(posedge io_lsu_c2_r_clk or posedge reset) begin @@ -4350,9 +4527,9 @@ end // initial end always @(posedge io_lsu_c2_r_clk or posedge reset) begin if (reset) begin - _T_4338 <= 1'h0; + _T_4984 <= 1'h0; end else begin - _T_4338 <= _T_4335 & _T_4035; + _T_4984 <= _T_4981 & _T_4518; end end endmodule @@ -4412,18 +4589,6 @@ module el2_lsu_bus_intf( input io_is_sideeffects_m, input io_flush_m_up, input io_flush_r, - input io_lsu_axi_awready, - input io_lsu_axi_wready, - input io_lsu_axi_bvalid, - input [1:0] io_lsu_axi_bresp, - input [2:0] io_lsu_axi_bid, - input io_lsu_axi_arready, - input io_lsu_axi_rvalid, - input [2:0] io_lsu_axi_rid, - input [63:0] io_lsu_axi_rdata, - input [1:0] io_lsu_axi_rresp, - input io_lsu_axi_rlast, - input io_lsu_bus_clk_en, output io_lsu_busreq_r, output io_lsu_bus_buffer_pend_any, output io_lsu_bus_buffer_full_any, @@ -4446,6 +4611,7 @@ module el2_lsu_bus_intf( output io_lsu_pmu_bus_error, output io_lsu_pmu_bus_busy, output io_lsu_axi_awvalid, + input io_lsu_axi_awready, output [2:0] io_lsu_axi_awid, output [31:0] io_lsu_axi_awaddr, output [3:0] io_lsu_axi_awregion, @@ -4457,11 +4623,16 @@ module el2_lsu_bus_intf( output [2:0] io_lsu_axi_awprot, output [3:0] io_lsu_axi_awqos, output io_lsu_axi_wvalid, + input io_lsu_axi_wready, output [63:0] io_lsu_axi_wdata, output [7:0] io_lsu_axi_wstrb, output io_lsu_axi_wlast, + input io_lsu_axi_bvalid, output io_lsu_axi_bready, + input [1:0] io_lsu_axi_bresp, + input [2:0] io_lsu_axi_bid, output io_lsu_axi_arvalid, + input io_lsu_axi_arready, output [2:0] io_lsu_axi_arid, output [31:0] io_lsu_axi_araddr, output [3:0] io_lsu_axi_arregion, @@ -4472,7 +4643,13 @@ module el2_lsu_bus_intf( output [3:0] io_lsu_axi_arcache, output [2:0] io_lsu_axi_arprot, output [3:0] io_lsu_axi_arqos, - output io_lsu_axi_rready + input io_lsu_axi_rvalid, + output io_lsu_axi_rready, + input [2:0] io_lsu_axi_rid, + input [63:0] io_lsu_axi_rdata, + input [1:0] io_lsu_axi_rresp, + input io_lsu_axi_rlast, + input io_lsu_bus_clk_en ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -4481,279 +4658,281 @@ module el2_lsu_bus_intf( reg [31:0] _RAND_3; reg [31:0] _RAND_4; `endif // RANDOMIZE_REG_INIT - wire bus_buffer_clock; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_reset; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_end_addr_r; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_store_data_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_no_word_merge_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_no_dword_merge_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_ld_full_hit_m; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_flush_m_up; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_flush_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_is_sideeffects_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_ldst_dual_d; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_ldst_dual_m; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_ldst_dual_r; // @[el2_lsu_bus_intf.scala 148:40] - wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 148:40] - wire [1:0] bus_buffer_io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 148:40] - wire [63:0] bus_buffer_io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 148:40] - wire [1:0] bus_buffer_io_lsu_axi_rresp; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 148:40] - wire [1:0] bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 148:40] - wire [1:0] bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 148:40] - wire [1:0] bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 148:40] - wire [63:0] bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 148:40] - wire [7:0] bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_bready; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 148:40] - wire [31:0] bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 148:40] - wire [2:0] bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 148:40] - wire bus_buffer_io_lsu_axi_rready; // @[el2_lsu_bus_intf.scala 148:40] - wire [3:0] _T_3 = io_lsu_pkt_r_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_4 = io_lsu_pkt_r_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] - wire [3:0] _T_5 = io_lsu_pkt_r_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] + wire bus_buffer_clock; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_reset; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_scan_mode; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_end_addr_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_end_addr_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_store_data_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_no_word_merge_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_no_dword_merge_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ld_full_hit_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_flush_m_up; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_flush_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_is_sideeffects_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_d; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_ldst_dual_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [7:0] bus_buffer_io_ldst_byteen_ext_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 167:39] + wire [63:0] bus_buffer_io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 167:39] + wire [1:0] bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [63:0] bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 167:39] + wire [7:0] bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_bready; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 167:39] + wire [31:0] bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 167:39] + wire [2:0] bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 167:39] + wire bus_buffer_io_lsu_axi_rready; // @[el2_lsu_bus_intf.scala 167:39] + wire [3:0] _T_3 = io_lsu_pkt_m_word ? 4'hf : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_4 = io_lsu_pkt_m_half ? 4'h3 : 4'h0; // @[Mux.scala 27:72] + wire [3:0] _T_5 = io_lsu_pkt_m_by ? 4'h1 : 4'h0; // @[Mux.scala 27:72] wire [3:0] _T_6 = _T_3 | _T_4; // @[Mux.scala 27:72] wire [3:0] ldst_byteen_m = _T_6 | _T_5; // @[Mux.scala 27:72] - wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[el2_lsu_bus_intf.scala 248:52] - wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[el2_lsu_bus_intf.scala 249:72] - wire _T_18 = ~_T_17; // @[el2_lsu_bus_intf.scala 249:54] - wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[el2_lsu_bus_intf.scala 249:52] - reg ldst_dual_r; // @[el2_lsu_bus_intf.scala 290:35] - wire _T_20 = ~ldst_dual_r; // @[el2_lsu_bus_intf.scala 250:49] - wire _T_21 = io_lsu_busreq_r & _T_20; // @[el2_lsu_bus_intf.scala 250:47] - wire _T_22 = _T_21 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 250:62] - wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 250:103] - wire _T_24 = io_lsu_pkt_m_load | _T_23; // @[el2_lsu_bus_intf.scala 250:101] - wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 251:103] - wire _T_30 = io_lsu_pkt_m_load | _T_29; // @[el2_lsu_bus_intf.scala 251:101] - wire [7:0] _T_33 = {4'h0,ldst_byteen_m}; // @[Cat.scala 29:58] - wire [10:0] _GEN_0 = {{3'd0}, _T_33}; // @[el2_lsu_bus_intf.scala 252:64] - wire [10:0] _T_35 = _GEN_0 << io_lsu_addr_m[1:0]; // @[el2_lsu_bus_intf.scala 252:64] - reg _T_389; // @[el2_lsu_bus_intf.scala 292:35] - wire [3:0] ldst_byteen_r = {{3'd0}, _T_389}; // @[el2_lsu_bus_intf.scala 292:25] - wire [7:0] _T_37 = {4'h0,ldst_byteen_r}; // @[Cat.scala 29:58] - wire [10:0] _GEN_1 = {{3'd0}, _T_37}; // @[el2_lsu_bus_intf.scala 253:64] - wire [10:0] _T_39 = _GEN_1 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_intf.scala 253:64] - wire [63:0] _T_41 = {32'h0,io_store_data_r}; // @[Cat.scala 29:58] - wire [4:0] _T_43 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] - wire [94:0] _GEN_2 = {{31'd0}, _T_41}; // @[el2_lsu_bus_intf.scala 254:68] - wire [94:0] _T_44 = _GEN_2 << _T_43; // @[el2_lsu_bus_intf.scala 254:68] - wire [7:0] ldst_byteen_ext_m = _T_35[7:0]; // @[el2_lsu_bus_intf.scala 252:28] - wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_intf.scala 255:48] - wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_intf.scala 256:48] - wire [7:0] ldst_byteen_ext_r = _T_39[7:0]; // @[el2_lsu_bus_intf.scala 253:28] - wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[el2_lsu_bus_intf.scala 257:48] - wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[el2_lsu_bus_intf.scala 258:48] - wire [63:0] store_data_ext_r = _T_44[63:0]; // @[el2_lsu_bus_intf.scala 254:28] - wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[el2_lsu_bus_intf.scala 259:47] - wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[el2_lsu_bus_intf.scala 260:47] - wire _T_53 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 261:52] - wire _T_54 = _T_53 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 261:77] - wire _T_55 = _T_54 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 261:98] - wire ld_addr_rhit_lo_lo = _T_55 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 261:119] - wire _T_59 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 262:52] - wire _T_60 = _T_59 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 262:77] - wire _T_61 = _T_60 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 262:98] - wire ld_addr_rhit_lo_hi = _T_61 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 262:119] - wire _T_65 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 263:52] - wire _T_66 = _T_65 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 263:77] - wire _T_67 = _T_66 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 263:98] - wire ld_addr_rhit_hi_lo = _T_67 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 263:119] - wire _T_71 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 264:52] - wire _T_72 = _T_71 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 264:77] - wire _T_73 = _T_72 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 264:98] - wire ld_addr_rhit_hi_hi = _T_73 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 264:119] - wire _T_76 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 265:71] - wire _T_78 = _T_76 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 265:93] - wire _T_80 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 265:71] - wire _T_82 = _T_80 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 265:93] - wire _T_84 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 265:71] - wire _T_86 = _T_84 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 265:93] - wire _T_88 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 265:71] - wire _T_90 = _T_88 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 265:93] - wire [3:0] ld_byte_rhit_lo_lo = {_T_90,_T_86,_T_82,_T_78}; // @[Cat.scala 29:58] - wire _T_95 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 266:71] - wire _T_97 = _T_95 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 266:93] - wire _T_99 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 266:71] - wire _T_101 = _T_99 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 266:93] - wire _T_103 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 266:71] - wire _T_105 = _T_103 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 266:93] - wire _T_107 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 266:71] - wire _T_109 = _T_107 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 266:93] - wire [3:0] ld_byte_rhit_lo_hi = {_T_109,_T_105,_T_101,_T_97}; // @[Cat.scala 29:58] - wire _T_114 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 267:71] - wire _T_116 = _T_114 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 267:93] - wire _T_118 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 267:71] - wire _T_120 = _T_118 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 267:93] - wire _T_122 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 267:71] - wire _T_124 = _T_122 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 267:93] - wire _T_126 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 267:71] - wire _T_128 = _T_126 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 267:93] - wire [3:0] ld_byte_rhit_hi_lo = {_T_128,_T_124,_T_120,_T_116}; // @[Cat.scala 29:58] - wire _T_133 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 268:71] - wire _T_135 = _T_133 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 268:93] - wire _T_137 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 268:71] - wire _T_139 = _T_137 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 268:93] - wire _T_141 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 268:71] - wire _T_143 = _T_141 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 268:93] - wire _T_145 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 268:71] - wire _T_147 = _T_145 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 268:93] - wire [3:0] ld_byte_rhit_hi_hi = {_T_147,_T_143,_T_139,_T_135}; // @[Cat.scala 29:58] - wire _T_153 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_bus_intf.scala 269:74] - wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 198:39] - wire _T_155 = _T_153 | ld_byte_hit_buf_lo[0]; // @[el2_lsu_bus_intf.scala 269:98] - wire _T_158 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_bus_intf.scala 269:74] - wire _T_160 = _T_158 | ld_byte_hit_buf_lo[1]; // @[el2_lsu_bus_intf.scala 269:98] - wire _T_163 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_bus_intf.scala 269:74] - wire _T_165 = _T_163 | ld_byte_hit_buf_lo[2]; // @[el2_lsu_bus_intf.scala 269:98] - wire _T_168 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_bus_intf.scala 269:74] - wire _T_170 = _T_168 | ld_byte_hit_buf_lo[3]; // @[el2_lsu_bus_intf.scala 269:98] - wire [3:0] ld_byte_hit_lo = {_T_170,_T_165,_T_160,_T_155}; // @[Cat.scala 29:58] - wire _T_176 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_bus_intf.scala 270:74] - wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 199:39] - wire _T_178 = _T_176 | ld_byte_hit_buf_hi[0]; // @[el2_lsu_bus_intf.scala 270:98] - wire _T_181 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_bus_intf.scala 270:74] - wire _T_183 = _T_181 | ld_byte_hit_buf_hi[1]; // @[el2_lsu_bus_intf.scala 270:98] - wire _T_186 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_bus_intf.scala 270:74] - wire _T_188 = _T_186 | ld_byte_hit_buf_hi[2]; // @[el2_lsu_bus_intf.scala 270:98] - wire _T_191 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_bus_intf.scala 270:74] - wire _T_193 = _T_191 | ld_byte_hit_buf_hi[3]; // @[el2_lsu_bus_intf.scala 270:98] - wire [3:0] ld_byte_hit_hi = {_T_193,_T_188,_T_183,_T_178}; // @[Cat.scala 29:58] - wire [3:0] ld_byte_rhit_lo = {_T_168,_T_163,_T_158,_T_153}; // @[Cat.scala 29:58] - wire [3:0] ld_byte_rhit_hi = {_T_191,_T_186,_T_181,_T_176}; // @[Cat.scala 29:58] - wire [7:0] _T_231 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_232 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_233 = _T_231 | _T_232; // @[Mux.scala 27:72] - wire [7:0] _T_239 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_240 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_241 = _T_239 | _T_240; // @[Mux.scala 27:72] - wire [7:0] _T_247 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_248 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_249 = _T_247 | _T_248; // @[Mux.scala 27:72] - wire [7:0] _T_255 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_256 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_257 = _T_255 | _T_256; // @[Mux.scala 27:72] - wire [31:0] ld_fwddata_rpipe_lo = {_T_257,_T_249,_T_241,_T_233}; // @[Cat.scala 29:58] - wire [7:0] _T_266 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_267 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_268 = _T_266 | _T_267; // @[Mux.scala 27:72] - wire [7:0] _T_274 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_275 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_276 = _T_274 | _T_275; // @[Mux.scala 27:72] - wire [7:0] _T_282 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_283 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_284 = _T_282 | _T_283; // @[Mux.scala 27:72] - wire [7:0] _T_290 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_291 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] - wire [7:0] _T_292 = _T_290 | _T_291; // @[Mux.scala 27:72] - wire [31:0] ld_fwddata_rpipe_hi = {_T_292,_T_284,_T_276,_T_268}; // @[Cat.scala 29:58] - wire [7:0] _T_300 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : 8'h0; // @[el2_lsu_bus_intf.scala 275:55] - wire [7:0] _T_304 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : 8'h0; // @[el2_lsu_bus_intf.scala 275:55] - wire [7:0] _T_308 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : 8'h0; // @[el2_lsu_bus_intf.scala 275:55] - wire [7:0] _T_312 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : 8'h0; // @[el2_lsu_bus_intf.scala 275:55] - wire [31:0] _T_315 = {_T_312,_T_308,_T_304,_T_300}; // @[Cat.scala 29:58] - wire [7:0] _T_319 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : 8'h0; // @[el2_lsu_bus_intf.scala 276:55] - wire [7:0] _T_323 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : 8'h0; // @[el2_lsu_bus_intf.scala 276:55] - wire [7:0] _T_327 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : 8'h0; // @[el2_lsu_bus_intf.scala 276:55] - wire [7:0] _T_331 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : 8'h0; // @[el2_lsu_bus_intf.scala 276:55] - wire [31:0] _T_334 = {_T_331,_T_327,_T_323,_T_319}; // @[Cat.scala 29:58] - wire _T_337 = ~ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 277:73] - wire _T_338 = ld_byte_hit_lo[0] | _T_337; // @[el2_lsu_bus_intf.scala 277:71] - wire _T_341 = ~ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 277:73] - wire _T_342 = ld_byte_hit_lo[1] | _T_341; // @[el2_lsu_bus_intf.scala 277:71] - wire _T_345 = ~ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 277:73] - wire _T_346 = ld_byte_hit_lo[2] | _T_345; // @[el2_lsu_bus_intf.scala 277:71] - wire _T_349 = ~ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 277:73] - wire _T_350 = ld_byte_hit_lo[3] | _T_349; // @[el2_lsu_bus_intf.scala 277:71] - wire _T_351 = _T_338 & _T_342; // @[el2_lsu_bus_intf.scala 277:112] - wire _T_352 = _T_351 & _T_346; // @[el2_lsu_bus_intf.scala 277:112] - wire ld_full_hit_lo_m = _T_352 & _T_350; // @[el2_lsu_bus_intf.scala 277:112] - wire _T_356 = ~ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 278:73] - wire _T_357 = ld_byte_hit_hi[0] | _T_356; // @[el2_lsu_bus_intf.scala 278:71] - wire _T_360 = ~ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 278:73] - wire _T_361 = ld_byte_hit_hi[1] | _T_360; // @[el2_lsu_bus_intf.scala 278:71] - wire _T_364 = ~ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 278:73] - wire _T_365 = ld_byte_hit_hi[2] | _T_364; // @[el2_lsu_bus_intf.scala 278:71] - wire _T_368 = ~ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 278:73] - wire _T_369 = ld_byte_hit_hi[3] | _T_368; // @[el2_lsu_bus_intf.scala 278:71] - wire _T_370 = _T_357 & _T_361; // @[el2_lsu_bus_intf.scala 278:112] - wire _T_371 = _T_370 & _T_365; // @[el2_lsu_bus_intf.scala 278:112] - wire ld_full_hit_hi_m = _T_371 & _T_369; // @[el2_lsu_bus_intf.scala 278:112] - wire _T_373 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[el2_lsu_bus_intf.scala 279:48] - wire _T_374 = _T_373 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 279:67] - wire _T_375 = _T_374 & io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 279:85] - wire _T_376 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 279:107] - wire [63:0] ld_fwddata_hi = {{32'd0}, _T_334}; // @[el2_lsu_bus_intf.scala 276:28] - wire [63:0] ld_fwddata_lo = {{32'd0}, _T_315}; // @[el2_lsu_bus_intf.scala 275:28] - wire [63:0] _T_380 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] - wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_bus_intf.scala 280:84] - wire [5:0] _T_382 = 4'h8 * _GEN_3; // @[el2_lsu_bus_intf.scala 280:84] - wire [63:0] ld_fwddata_m = _T_380 >> _T_382; // @[el2_lsu_bus_intf.scala 280:77] - reg lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 284:34] - reg ldst_dual_m; // @[el2_lsu_bus_intf.scala 287:29] - reg is_sideeffects_r; // @[el2_lsu_bus_intf.scala 291:35] - el2_lsu_bus_buffer bus_buffer ( // @[el2_lsu_bus_intf.scala 148:40] + wire addr_match_dw_lo_r_m = io_lsu_addr_r[31:3] == io_lsu_addr_m[31:3]; // @[el2_lsu_bus_intf.scala 278:51] + wire _T_17 = io_lsu_addr_r[2] ^ io_lsu_addr_m[2]; // @[el2_lsu_bus_intf.scala 279:71] + wire _T_18 = ~_T_17; // @[el2_lsu_bus_intf.scala 279:53] + wire addr_match_word_lo_r_m = addr_match_dw_lo_r_m & _T_18; // @[el2_lsu_bus_intf.scala 279:51] + reg ldst_dual_r; // @[el2_lsu_bus_intf.scala 324:33] + wire _T_20 = ~ldst_dual_r; // @[el2_lsu_bus_intf.scala 280:48] + wire _T_21 = io_lsu_busreq_r & _T_20; // @[el2_lsu_bus_intf.scala 280:46] + wire _T_22 = _T_21 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 280:61] + wire _T_23 = ~addr_match_word_lo_r_m; // @[el2_lsu_bus_intf.scala 280:102] + wire _T_24 = io_lsu_pkt_m_load | _T_23; // @[el2_lsu_bus_intf.scala 280:100] + wire _T_29 = ~addr_match_dw_lo_r_m; // @[el2_lsu_bus_intf.scala 281:102] + wire _T_30 = io_lsu_pkt_m_load | _T_29; // @[el2_lsu_bus_intf.scala 281:100] + wire [6:0] _GEN_0 = {{3'd0}, ldst_byteen_m}; // @[el2_lsu_bus_intf.scala 283:49] + wire [6:0] _T_34 = _GEN_0 << io_lsu_addr_m[1:0]; // @[el2_lsu_bus_intf.scala 283:49] + reg [3:0] ldst_byteen_r; // @[el2_lsu_bus_intf.scala 326:33] + wire [6:0] _GEN_1 = {{3'd0}, ldst_byteen_r}; // @[el2_lsu_bus_intf.scala 284:49] + wire [6:0] _T_37 = _GEN_1 << io_lsu_addr_r[1:0]; // @[el2_lsu_bus_intf.scala 284:49] + wire [4:0] _T_40 = {io_lsu_addr_r[1:0],3'h0}; // @[Cat.scala 29:58] + wire [62:0] _GEN_2 = {{31'd0}, io_store_data_r}; // @[el2_lsu_bus_intf.scala 285:52] + wire [62:0] _T_41 = _GEN_2 << _T_40; // @[el2_lsu_bus_intf.scala 285:52] + wire [7:0] ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 283:27] + wire [3:0] ldst_byteen_hi_m = ldst_byteen_ext_m[7:4]; // @[el2_lsu_bus_intf.scala 286:47] + wire [3:0] ldst_byteen_lo_m = ldst_byteen_ext_m[3:0]; // @[el2_lsu_bus_intf.scala 287:47] + wire [7:0] ldst_byteen_ext_r = {{1'd0}, _T_37}; // @[el2_lsu_bus_intf.scala 284:27] + wire [3:0] ldst_byteen_hi_r = ldst_byteen_ext_r[7:4]; // @[el2_lsu_bus_intf.scala 288:47] + wire [3:0] ldst_byteen_lo_r = ldst_byteen_ext_r[3:0]; // @[el2_lsu_bus_intf.scala 289:47] + wire [63:0] store_data_ext_r = {{1'd0}, _T_41}; // @[el2_lsu_bus_intf.scala 285:27] + wire [31:0] store_data_hi_r = store_data_ext_r[63:32]; // @[el2_lsu_bus_intf.scala 291:46] + wire [31:0] store_data_lo_r = store_data_ext_r[31:0]; // @[el2_lsu_bus_intf.scala 292:46] + wire _T_50 = io_lsu_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 293:51] + wire _T_51 = _T_50 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 293:76] + wire _T_52 = _T_51 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 293:97] + wire ld_addr_rhit_lo_lo = _T_52 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 293:118] + wire _T_56 = io_end_addr_m[31:2] == io_lsu_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 294:51] + wire _T_57 = _T_56 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 294:76] + wire _T_58 = _T_57 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 294:97] + wire ld_addr_rhit_lo_hi = _T_58 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 294:118] + wire _T_62 = io_lsu_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 295:51] + wire _T_63 = _T_62 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 295:76] + wire _T_64 = _T_63 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 295:97] + wire ld_addr_rhit_hi_lo = _T_64 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 295:118] + wire _T_68 = io_end_addr_m[31:2] == io_end_addr_r[31:2]; // @[el2_lsu_bus_intf.scala 296:51] + wire _T_69 = _T_68 & io_lsu_pkt_r_valid; // @[el2_lsu_bus_intf.scala 296:76] + wire _T_70 = _T_69 & io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 296:97] + wire ld_addr_rhit_hi_hi = _T_70 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 296:118] + wire _T_73 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_75 = _T_73 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_77 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_79 = _T_77 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_81 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_83 = _T_81 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 298:92] + wire _T_85 = ld_addr_rhit_lo_lo & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 298:70] + wire _T_87 = _T_85 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 298:92] + wire [3:0] ld_byte_rhit_lo_lo = {_T_87,_T_83,_T_79,_T_75}; // @[Cat.scala 29:58] + wire _T_92 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[0]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_94 = _T_92 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_96 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[1]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_98 = _T_96 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_100 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[2]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_102 = _T_100 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 299:92] + wire _T_104 = ld_addr_rhit_lo_hi & ldst_byteen_lo_r[3]; // @[el2_lsu_bus_intf.scala 299:70] + wire _T_106 = _T_104 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 299:92] + wire [3:0] ld_byte_rhit_lo_hi = {_T_106,_T_102,_T_98,_T_94}; // @[Cat.scala 29:58] + wire _T_111 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_113 = _T_111 & ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_115 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_117 = _T_115 & ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_119 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_121 = _T_119 & ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 300:92] + wire _T_123 = ld_addr_rhit_hi_lo & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 300:70] + wire _T_125 = _T_123 & ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 300:92] + wire [3:0] ld_byte_rhit_hi_lo = {_T_125,_T_121,_T_117,_T_113}; // @[Cat.scala 29:58] + wire _T_130 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[0]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_132 = _T_130 & ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_134 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[1]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_136 = _T_134 & ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_138 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[2]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_140 = _T_138 & ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 301:92] + wire _T_142 = ld_addr_rhit_hi_hi & ldst_byteen_hi_r[3]; // @[el2_lsu_bus_intf.scala 301:70] + wire _T_144 = _T_142 & ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 301:92] + wire [3:0] ld_byte_rhit_hi_hi = {_T_144,_T_140,_T_136,_T_132}; // @[Cat.scala 29:58] + wire _T_150 = ld_byte_rhit_lo_lo[0] | ld_byte_rhit_hi_lo[0]; // @[el2_lsu_bus_intf.scala 303:73] + wire [3:0] ld_byte_hit_buf_lo = bus_buffer_io_ld_byte_hit_buf_lo; // @[el2_lsu_bus_intf.scala 215:38] + wire _T_152 = _T_150 | ld_byte_hit_buf_lo[0]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_155 = ld_byte_rhit_lo_lo[1] | ld_byte_rhit_hi_lo[1]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_157 = _T_155 | ld_byte_hit_buf_lo[1]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_160 = ld_byte_rhit_lo_lo[2] | ld_byte_rhit_hi_lo[2]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_162 = _T_160 | ld_byte_hit_buf_lo[2]; // @[el2_lsu_bus_intf.scala 303:97] + wire _T_165 = ld_byte_rhit_lo_lo[3] | ld_byte_rhit_hi_lo[3]; // @[el2_lsu_bus_intf.scala 303:73] + wire _T_167 = _T_165 | ld_byte_hit_buf_lo[3]; // @[el2_lsu_bus_intf.scala 303:97] + wire [3:0] ld_byte_hit_lo = {_T_167,_T_162,_T_157,_T_152}; // @[Cat.scala 29:58] + wire _T_173 = ld_byte_rhit_lo_hi[0] | ld_byte_rhit_hi_hi[0]; // @[el2_lsu_bus_intf.scala 304:73] + wire [3:0] ld_byte_hit_buf_hi = bus_buffer_io_ld_byte_hit_buf_hi; // @[el2_lsu_bus_intf.scala 216:38] + wire _T_175 = _T_173 | ld_byte_hit_buf_hi[0]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_178 = ld_byte_rhit_lo_hi[1] | ld_byte_rhit_hi_hi[1]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_180 = _T_178 | ld_byte_hit_buf_hi[1]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_183 = ld_byte_rhit_lo_hi[2] | ld_byte_rhit_hi_hi[2]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_185 = _T_183 | ld_byte_hit_buf_hi[2]; // @[el2_lsu_bus_intf.scala 304:97] + wire _T_188 = ld_byte_rhit_lo_hi[3] | ld_byte_rhit_hi_hi[3]; // @[el2_lsu_bus_intf.scala 304:73] + wire _T_190 = _T_188 | ld_byte_hit_buf_hi[3]; // @[el2_lsu_bus_intf.scala 304:97] + wire [3:0] ld_byte_hit_hi = {_T_190,_T_185,_T_180,_T_175}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_lo = {_T_165,_T_160,_T_155,_T_150}; // @[Cat.scala 29:58] + wire [3:0] ld_byte_rhit_hi = {_T_188,_T_183,_T_178,_T_173}; // @[Cat.scala 29:58] + wire [7:0] _T_228 = ld_byte_rhit_lo_lo[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_229 = ld_byte_rhit_hi_lo[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_230 = _T_228 | _T_229; // @[Mux.scala 27:72] + wire [7:0] _T_236 = ld_byte_rhit_lo_lo[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_237 = ld_byte_rhit_hi_lo[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_238 = _T_236 | _T_237; // @[Mux.scala 27:72] + wire [7:0] _T_244 = ld_byte_rhit_lo_lo[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_245 = ld_byte_rhit_hi_lo[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_246 = _T_244 | _T_245; // @[Mux.scala 27:72] + wire [7:0] _T_252 = ld_byte_rhit_lo_lo[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_253 = ld_byte_rhit_hi_lo[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_254 = _T_252 | _T_253; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_lo = {_T_254,_T_246,_T_238,_T_230}; // @[Cat.scala 29:58] + wire [7:0] _T_263 = ld_byte_rhit_lo_hi[0] ? store_data_lo_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_264 = ld_byte_rhit_hi_hi[0] ? store_data_hi_r[7:0] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_265 = _T_263 | _T_264; // @[Mux.scala 27:72] + wire [7:0] _T_271 = ld_byte_rhit_lo_hi[1] ? store_data_lo_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_272 = ld_byte_rhit_hi_hi[1] ? store_data_hi_r[15:8] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_273 = _T_271 | _T_272; // @[Mux.scala 27:72] + wire [7:0] _T_279 = ld_byte_rhit_lo_hi[2] ? store_data_lo_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_280 = ld_byte_rhit_hi_hi[2] ? store_data_hi_r[23:16] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_281 = _T_279 | _T_280; // @[Mux.scala 27:72] + wire [7:0] _T_287 = ld_byte_rhit_lo_hi[3] ? store_data_lo_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_288 = ld_byte_rhit_hi_hi[3] ? store_data_hi_r[31:24] : 8'h0; // @[Mux.scala 27:72] + wire [7:0] _T_289 = _T_287 | _T_288; // @[Mux.scala 27:72] + wire [31:0] ld_fwddata_rpipe_hi = {_T_289,_T_281,_T_273,_T_265}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_lo = bus_buffer_io_ld_fwddata_buf_lo; // @[el2_lsu_bus_intf.scala 217:38] + wire [7:0] _T_297 = ld_byte_rhit_lo[0] ? ld_fwddata_rpipe_lo[7:0] : ld_fwddata_buf_lo[7:0]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_301 = ld_byte_rhit_lo[1] ? ld_fwddata_rpipe_lo[15:8] : ld_fwddata_buf_lo[15:8]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_305 = ld_byte_rhit_lo[2] ? ld_fwddata_rpipe_lo[23:16] : ld_fwddata_buf_lo[23:16]; // @[el2_lsu_bus_intf.scala 309:54] + wire [7:0] _T_309 = ld_byte_rhit_lo[3] ? ld_fwddata_rpipe_lo[31:24] : ld_fwddata_buf_lo[31:24]; // @[el2_lsu_bus_intf.scala 309:54] + wire [31:0] _T_312 = {_T_309,_T_305,_T_301,_T_297}; // @[Cat.scala 29:58] + wire [31:0] ld_fwddata_buf_hi = bus_buffer_io_ld_fwddata_buf_hi; // @[el2_lsu_bus_intf.scala 218:38] + wire [7:0] _T_316 = ld_byte_rhit_hi[0] ? ld_fwddata_rpipe_hi[7:0] : ld_fwddata_buf_hi[7:0]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_320 = ld_byte_rhit_hi[1] ? ld_fwddata_rpipe_hi[15:8] : ld_fwddata_buf_hi[15:8]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_324 = ld_byte_rhit_hi[2] ? ld_fwddata_rpipe_hi[23:16] : ld_fwddata_buf_hi[23:16]; // @[el2_lsu_bus_intf.scala 310:54] + wire [7:0] _T_328 = ld_byte_rhit_hi[3] ? ld_fwddata_rpipe_hi[31:24] : ld_fwddata_buf_hi[31:24]; // @[el2_lsu_bus_intf.scala 310:54] + wire [31:0] _T_331 = {_T_328,_T_324,_T_320,_T_316}; // @[Cat.scala 29:58] + wire _T_334 = ~ldst_byteen_lo_m[0]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_335 = ld_byte_hit_lo[0] | _T_334; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_338 = ~ldst_byteen_lo_m[1]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_339 = ld_byte_hit_lo[1] | _T_338; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_342 = ~ldst_byteen_lo_m[2]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_343 = ld_byte_hit_lo[2] | _T_342; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_346 = ~ldst_byteen_lo_m[3]; // @[el2_lsu_bus_intf.scala 311:72] + wire _T_347 = ld_byte_hit_lo[3] | _T_346; // @[el2_lsu_bus_intf.scala 311:70] + wire _T_348 = _T_335 & _T_339; // @[el2_lsu_bus_intf.scala 311:111] + wire _T_349 = _T_348 & _T_343; // @[el2_lsu_bus_intf.scala 311:111] + wire ld_full_hit_lo_m = _T_349 & _T_347; // @[el2_lsu_bus_intf.scala 311:111] + wire _T_353 = ~ldst_byteen_hi_m[0]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_354 = ld_byte_hit_hi[0] | _T_353; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_357 = ~ldst_byteen_hi_m[1]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_358 = ld_byte_hit_hi[1] | _T_357; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_361 = ~ldst_byteen_hi_m[2]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_362 = ld_byte_hit_hi[2] | _T_361; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_365 = ~ldst_byteen_hi_m[3]; // @[el2_lsu_bus_intf.scala 312:72] + wire _T_366 = ld_byte_hit_hi[3] | _T_365; // @[el2_lsu_bus_intf.scala 312:70] + wire _T_367 = _T_354 & _T_358; // @[el2_lsu_bus_intf.scala 312:111] + wire _T_368 = _T_367 & _T_362; // @[el2_lsu_bus_intf.scala 312:111] + wire ld_full_hit_hi_m = _T_368 & _T_366; // @[el2_lsu_bus_intf.scala 312:111] + wire _T_370 = ld_full_hit_lo_m & ld_full_hit_hi_m; // @[el2_lsu_bus_intf.scala 313:47] + wire _T_371 = _T_370 & io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 313:66] + wire _T_372 = _T_371 & io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 313:84] + wire _T_373 = ~io_is_sideeffects_m; // @[el2_lsu_bus_intf.scala 313:106] + wire [63:0] ld_fwddata_hi = {{32'd0}, _T_331}; // @[el2_lsu_bus_intf.scala 310:27] + wire [63:0] ld_fwddata_lo = {{32'd0}, _T_312}; // @[el2_lsu_bus_intf.scala 309:27] + wire [63:0] _T_377 = {ld_fwddata_hi[31:0],ld_fwddata_lo[31:0]}; // @[Cat.scala 29:58] + wire [3:0] _GEN_3 = {{2'd0}, io_lsu_addr_m[1:0]}; // @[el2_lsu_bus_intf.scala 314:83] + wire [5:0] _T_379 = 4'h8 * _GEN_3; // @[el2_lsu_bus_intf.scala 314:83] + wire [63:0] ld_fwddata_m = _T_377 >> _T_379; // @[el2_lsu_bus_intf.scala 314:76] + reg lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 318:32] + reg ldst_dual_m; // @[el2_lsu_bus_intf.scala 321:27] + reg is_sideeffects_r; // @[el2_lsu_bus_intf.scala 325:33] + el2_lsu_bus_buffer bus_buffer ( // @[el2_lsu_bus_intf.scala 167:39] .clock(bus_buffer_clock), .reset(bus_buffer_reset), + .io_scan_mode(bus_buffer_io_scan_mode), .io_dec_tlu_external_ldfwd_disable(bus_buffer_io_dec_tlu_external_ldfwd_disable), .io_dec_tlu_wb_coalescing_disable(bus_buffer_io_dec_tlu_wb_coalescing_disable), .io_dec_tlu_sideeffect_posted_disable(bus_buffer_io_dec_tlu_sideeffect_posted_disable), @@ -4774,6 +4953,7 @@ module el2_lsu_bus_intf( .io_lsu_pkt_r_store(bus_buffer_io_lsu_pkt_r_store), .io_lsu_pkt_r_unsign(bus_buffer_io_lsu_pkt_r_unsign), .io_lsu_addr_m(bus_buffer_io_lsu_addr_m), + .io_end_addr_m(bus_buffer_io_end_addr_m), .io_lsu_addr_r(bus_buffer_io_lsu_addr_r), .io_end_addr_r(bus_buffer_io_end_addr_r), .io_store_data_r(bus_buffer_io_store_data_r), @@ -4789,7 +4969,6 @@ module el2_lsu_bus_intf( .io_ldst_dual_m(bus_buffer_io_ldst_dual_m), .io_ldst_dual_r(bus_buffer_io_ldst_dual_r), .io_ldst_byteen_ext_m(bus_buffer_io_ldst_byteen_ext_m), - .io_lsu_axi_awready(bus_buffer_io_lsu_axi_awready), .io_lsu_axi_wready(bus_buffer_io_lsu_axi_wready), .io_lsu_axi_bvalid(bus_buffer_io_lsu_axi_bvalid), .io_lsu_axi_bresp(bus_buffer_io_lsu_axi_bresp), @@ -4798,7 +4977,6 @@ module el2_lsu_bus_intf( .io_lsu_axi_rvalid(bus_buffer_io_lsu_axi_rvalid), .io_lsu_axi_rid(bus_buffer_io_lsu_axi_rid), .io_lsu_axi_rdata(bus_buffer_io_lsu_axi_rdata), - .io_lsu_axi_rresp(bus_buffer_io_lsu_axi_rresp), .io_lsu_bus_clk_en(bus_buffer_io_lsu_bus_clk_en), .io_lsu_bus_clk_en_q(bus_buffer_io_lsu_bus_clk_en_q), .io_lsu_busreq_r(bus_buffer_io_lsu_busreq_r), @@ -4807,6 +4985,8 @@ module el2_lsu_bus_intf( .io_lsu_bus_buffer_empty_any(bus_buffer_io_lsu_bus_buffer_empty_any), .io_ld_byte_hit_buf_lo(bus_buffer_io_ld_byte_hit_buf_lo), .io_ld_byte_hit_buf_hi(bus_buffer_io_ld_byte_hit_buf_hi), + .io_ld_fwddata_buf_lo(bus_buffer_io_ld_fwddata_buf_lo), + .io_ld_fwddata_buf_hi(bus_buffer_io_ld_fwddata_buf_hi), .io_lsu_imprecise_error_load_any(bus_buffer_io_lsu_imprecise_error_load_any), .io_lsu_imprecise_error_store_any(bus_buffer_io_lsu_imprecise_error_store_any), .io_lsu_imprecise_error_addr_any(bus_buffer_io_lsu_imprecise_error_addr_any), @@ -4823,6 +5003,7 @@ module el2_lsu_bus_intf( .io_lsu_pmu_bus_error(bus_buffer_io_lsu_pmu_bus_error), .io_lsu_pmu_bus_busy(bus_buffer_io_lsu_pmu_bus_busy), .io_lsu_axi_awvalid(bus_buffer_io_lsu_axi_awvalid), + .io_lsu_axi_awready(bus_buffer_io_lsu_axi_awready), .io_lsu_axi_awid(bus_buffer_io_lsu_axi_awid), .io_lsu_axi_awaddr(bus_buffer_io_lsu_axi_awaddr), .io_lsu_axi_awregion(bus_buffer_io_lsu_axi_awregion), @@ -4840,104 +5021,105 @@ module el2_lsu_bus_intf( .io_lsu_axi_arcache(bus_buffer_io_lsu_axi_arcache), .io_lsu_axi_rready(bus_buffer_io_lsu_axi_rready) ); - assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 193:39] - assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 194:39] - assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 195:39] - assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 196:39] - assign io_lsu_bus_idle_any = 1'h1; // @[el2_lsu_bus_intf.scala 197:39] - assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[el2_lsu_bus_intf.scala 281:28] - assign io_lsu_imprecise_error_load_any = bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 202:39] - assign io_lsu_imprecise_error_store_any = bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 203:39] - assign io_lsu_imprecise_error_addr_any = bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 204:39] - assign io_lsu_nonblock_load_valid_m = bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 205:39] - assign io_lsu_nonblock_load_tag_m = bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 206:39] - assign io_lsu_nonblock_load_inv_r = bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 207:39] - assign io_lsu_nonblock_load_inv_tag_r = bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 208:39] - assign io_lsu_nonblock_load_data_valid = bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 209:39] - assign io_lsu_nonblock_load_data_error = bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 210:39] - assign io_lsu_nonblock_load_data_tag = bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 211:39] - assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 212:39] - assign io_lsu_pmu_bus_trxn = bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 213:39] - assign io_lsu_pmu_bus_misaligned = bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 214:39] - assign io_lsu_pmu_bus_error = bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 215:39] - assign io_lsu_pmu_bus_busy = bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 216:39] - assign io_lsu_axi_awvalid = bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 217:39] - assign io_lsu_axi_awid = bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 218:39] - assign io_lsu_axi_awaddr = bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 219:39] - assign io_lsu_axi_awregion = bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 220:39] - assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_intf.scala 221:39] - assign io_lsu_axi_awsize = bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 222:39] - assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_intf.scala 223:39] - assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_intf.scala 224:39] - assign io_lsu_axi_awcache = bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 225:39] - assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu_bus_intf.scala 226:39] - assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu_bus_intf.scala 227:39] - assign io_lsu_axi_wvalid = bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 228:39] - assign io_lsu_axi_wdata = bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 229:39] - assign io_lsu_axi_wstrb = bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 230:39] - assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu_bus_intf.scala 231:39] - assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_intf.scala 232:39] - assign io_lsu_axi_arvalid = bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 233:39] - assign io_lsu_axi_arid = bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 234:39] - assign io_lsu_axi_araddr = bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 235:39] - assign io_lsu_axi_arregion = bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 236:39] - assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu_bus_intf.scala 237:39] - assign io_lsu_axi_arsize = bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 238:39] - assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu_bus_intf.scala 239:39] - assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu_bus_intf.scala 240:39] - assign io_lsu_axi_arcache = bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 241:39] - assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu_bus_intf.scala 242:39] - assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu_bus_intf.scala 243:39] - assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_intf.scala 244:39] + assign io_lsu_busreq_r = bus_buffer_io_lsu_busreq_r; // @[el2_lsu_bus_intf.scala 210:38] + assign io_lsu_bus_buffer_pend_any = bus_buffer_io_lsu_bus_buffer_pend_any; // @[el2_lsu_bus_intf.scala 211:38] + assign io_lsu_bus_buffer_full_any = bus_buffer_io_lsu_bus_buffer_full_any; // @[el2_lsu_bus_intf.scala 212:38] + assign io_lsu_bus_buffer_empty_any = bus_buffer_io_lsu_bus_buffer_empty_any; // @[el2_lsu_bus_intf.scala 213:38] + assign io_lsu_bus_idle_any = 1'h1; // @[el2_lsu_bus_intf.scala 214:38] + assign io_bus_read_data_m = ld_fwddata_m[31:0]; // @[el2_lsu_bus_intf.scala 315:27] + assign io_lsu_imprecise_error_load_any = bus_buffer_io_lsu_imprecise_error_load_any; // @[el2_lsu_bus_intf.scala 219:38] + assign io_lsu_imprecise_error_store_any = bus_buffer_io_lsu_imprecise_error_store_any; // @[el2_lsu_bus_intf.scala 220:38] + assign io_lsu_imprecise_error_addr_any = bus_buffer_io_lsu_imprecise_error_addr_any; // @[el2_lsu_bus_intf.scala 221:38] + assign io_lsu_nonblock_load_valid_m = bus_buffer_io_lsu_nonblock_load_valid_m; // @[el2_lsu_bus_intf.scala 222:38] + assign io_lsu_nonblock_load_tag_m = bus_buffer_io_lsu_nonblock_load_tag_m; // @[el2_lsu_bus_intf.scala 223:38] + assign io_lsu_nonblock_load_inv_r = bus_buffer_io_lsu_nonblock_load_inv_r; // @[el2_lsu_bus_intf.scala 224:38] + assign io_lsu_nonblock_load_inv_tag_r = bus_buffer_io_lsu_nonblock_load_inv_tag_r; // @[el2_lsu_bus_intf.scala 225:38] + assign io_lsu_nonblock_load_data_valid = bus_buffer_io_lsu_nonblock_load_data_valid; // @[el2_lsu_bus_intf.scala 226:38] + assign io_lsu_nonblock_load_data_error = bus_buffer_io_lsu_nonblock_load_data_error; // @[el2_lsu_bus_intf.scala 227:38] + assign io_lsu_nonblock_load_data_tag = bus_buffer_io_lsu_nonblock_load_data_tag; // @[el2_lsu_bus_intf.scala 228:38] + assign io_lsu_nonblock_load_data = bus_buffer_io_lsu_nonblock_load_data; // @[el2_lsu_bus_intf.scala 229:38] + assign io_lsu_pmu_bus_trxn = bus_buffer_io_lsu_pmu_bus_trxn; // @[el2_lsu_bus_intf.scala 230:38] + assign io_lsu_pmu_bus_misaligned = bus_buffer_io_lsu_pmu_bus_misaligned; // @[el2_lsu_bus_intf.scala 231:38] + assign io_lsu_pmu_bus_error = bus_buffer_io_lsu_pmu_bus_error; // @[el2_lsu_bus_intf.scala 232:38] + assign io_lsu_pmu_bus_busy = bus_buffer_io_lsu_pmu_bus_busy; // @[el2_lsu_bus_intf.scala 233:38] + assign io_lsu_axi_awvalid = bus_buffer_io_lsu_axi_awvalid; // @[el2_lsu_bus_intf.scala 234:38] + assign io_lsu_axi_awid = bus_buffer_io_lsu_axi_awid; // @[el2_lsu_bus_intf.scala 235:38] + assign io_lsu_axi_awaddr = bus_buffer_io_lsu_axi_awaddr; // @[el2_lsu_bus_intf.scala 236:38] + assign io_lsu_axi_awregion = bus_buffer_io_lsu_axi_awregion; // @[el2_lsu_bus_intf.scala 237:38] + assign io_lsu_axi_awlen = 8'h0; // @[el2_lsu_bus_intf.scala 238:38] + assign io_lsu_axi_awsize = bus_buffer_io_lsu_axi_awsize; // @[el2_lsu_bus_intf.scala 239:38] + assign io_lsu_axi_awburst = 2'h1; // @[el2_lsu_bus_intf.scala 240:38] + assign io_lsu_axi_awlock = 1'h0; // @[el2_lsu_bus_intf.scala 241:38] + assign io_lsu_axi_awcache = bus_buffer_io_lsu_axi_awcache; // @[el2_lsu_bus_intf.scala 242:38] + assign io_lsu_axi_awprot = 3'h0; // @[el2_lsu_bus_intf.scala 243:38] + assign io_lsu_axi_awqos = 4'h0; // @[el2_lsu_bus_intf.scala 244:38] + assign io_lsu_axi_wvalid = bus_buffer_io_lsu_axi_wvalid; // @[el2_lsu_bus_intf.scala 245:38] + assign io_lsu_axi_wdata = bus_buffer_io_lsu_axi_wdata; // @[el2_lsu_bus_intf.scala 246:38] + assign io_lsu_axi_wstrb = bus_buffer_io_lsu_axi_wstrb; // @[el2_lsu_bus_intf.scala 247:38] + assign io_lsu_axi_wlast = 1'h1; // @[el2_lsu_bus_intf.scala 248:38] + assign io_lsu_axi_bready = 1'h1; // @[el2_lsu_bus_intf.scala 249:38] + assign io_lsu_axi_arvalid = bus_buffer_io_lsu_axi_arvalid; // @[el2_lsu_bus_intf.scala 250:38] + assign io_lsu_axi_arid = bus_buffer_io_lsu_axi_arid; // @[el2_lsu_bus_intf.scala 251:38] + assign io_lsu_axi_araddr = bus_buffer_io_lsu_axi_araddr; // @[el2_lsu_bus_intf.scala 252:38] + assign io_lsu_axi_arregion = bus_buffer_io_lsu_axi_arregion; // @[el2_lsu_bus_intf.scala 253:38] + assign io_lsu_axi_arlen = 8'h0; // @[el2_lsu_bus_intf.scala 254:38] + assign io_lsu_axi_arsize = bus_buffer_io_lsu_axi_arsize; // @[el2_lsu_bus_intf.scala 255:38] + assign io_lsu_axi_arburst = 2'h1; // @[el2_lsu_bus_intf.scala 256:38] + assign io_lsu_axi_arlock = 1'h0; // @[el2_lsu_bus_intf.scala 257:38] + assign io_lsu_axi_arcache = bus_buffer_io_lsu_axi_arcache; // @[el2_lsu_bus_intf.scala 258:38] + assign io_lsu_axi_arprot = 3'h0; // @[el2_lsu_bus_intf.scala 259:38] + assign io_lsu_axi_arqos = 4'h0; // @[el2_lsu_bus_intf.scala 260:38] + assign io_lsu_axi_rready = 1'h1; // @[el2_lsu_bus_intf.scala 261:38] assign bus_buffer_clock = clock; assign bus_buffer_reset = reset; - assign bus_buffer_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 150:52] - assign bus_buffer_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 151:52] - assign bus_buffer_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 152:52] - assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 153:52] - assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 154:52] - assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 155:52] - assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 156:52] - assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 157:52] - assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 158:52] - assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 159:52] - assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 160:52] - assign bus_buffer_io_lsu_pkt_m_load = io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 161:52] - assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 161:52] - assign bus_buffer_io_lsu_pkt_r_by = io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_pkt_r_half = io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_pkt_r_word = io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_pkt_r_load = io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_pkt_r_store = io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_pkt_r_unsign = io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 162:52] - assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 163:52] - assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 165:52] - assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[el2_lsu_bus_intf.scala 166:52] - assign bus_buffer_io_store_data_r = io_store_data_r; // @[el2_lsu_bus_intf.scala 167:52] - assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[el2_lsu_bus_intf.scala 168:52] - assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[el2_lsu_bus_intf.scala 169:52] - assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 170:52] - assign bus_buffer_io_ld_full_hit_m = _T_375 & _T_376; // @[el2_lsu_bus_intf.scala 171:52] - assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[el2_lsu_bus_intf.scala 172:52] - assign bus_buffer_io_flush_r = io_flush_r; // @[el2_lsu_bus_intf.scala 173:52] - assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 174:52] - assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[el2_lsu_bus_intf.scala 175:52] - assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_bus_intf.scala 176:52] - assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[el2_lsu_bus_intf.scala 177:52] - assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[el2_lsu_bus_intf.scala 178:52] - assign bus_buffer_io_ldst_byteen_ext_m = _T_35[7:0]; // @[el2_lsu_bus_intf.scala 179:52] - assign bus_buffer_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 180:52] - assign bus_buffer_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 181:52] - assign bus_buffer_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 182:52] - assign bus_buffer_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 183:52] - assign bus_buffer_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 184:52] - assign bus_buffer_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 185:52] - assign bus_buffer_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 186:52] - assign bus_buffer_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 187:52] - assign bus_buffer_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 188:52] - assign bus_buffer_io_lsu_axi_rresp = io_lsu_axi_rresp; // @[el2_lsu_bus_intf.scala 189:52] - assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 190:52] - assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 191:52] + assign bus_buffer_io_scan_mode = io_scan_mode; // @[el2_lsu_bus_intf.scala 169:29] + assign bus_buffer_io_dec_tlu_external_ldfwd_disable = io_dec_tlu_external_ldfwd_disable; // @[el2_lsu_bus_intf.scala 171:51] + assign bus_buffer_io_dec_tlu_wb_coalescing_disable = io_dec_tlu_wb_coalescing_disable; // @[el2_lsu_bus_intf.scala 172:51] + assign bus_buffer_io_dec_tlu_sideeffect_posted_disable = io_dec_tlu_sideeffect_posted_disable; // @[el2_lsu_bus_intf.scala 173:51] + assign bus_buffer_io_dec_tlu_force_halt = io_dec_tlu_force_halt; // @[el2_lsu_bus_intf.scala 174:51] + assign bus_buffer_io_lsu_c2_r_clk = io_lsu_c2_r_clk; // @[el2_lsu_bus_intf.scala 175:51] + assign bus_buffer_io_lsu_bus_ibuf_c1_clk = io_lsu_bus_ibuf_c1_clk; // @[el2_lsu_bus_intf.scala 176:51] + assign bus_buffer_io_lsu_bus_obuf_c1_clk = io_lsu_bus_obuf_c1_clk; // @[el2_lsu_bus_intf.scala 177:51] + assign bus_buffer_io_lsu_bus_buf_c1_clk = io_lsu_bus_buf_c1_clk; // @[el2_lsu_bus_intf.scala 178:51] + assign bus_buffer_io_lsu_free_c2_clk = io_lsu_free_c2_clk; // @[el2_lsu_bus_intf.scala 179:51] + assign bus_buffer_io_lsu_busm_clk = io_lsu_busm_clk; // @[el2_lsu_bus_intf.scala 180:51] + assign bus_buffer_io_dec_lsu_valid_raw_d = io_dec_lsu_valid_raw_d; // @[el2_lsu_bus_intf.scala 181:51] + assign bus_buffer_io_lsu_pkt_m_load = io_lsu_pkt_m_load; // @[el2_lsu_bus_intf.scala 184:27] + assign bus_buffer_io_lsu_pkt_m_valid = io_lsu_pkt_m_valid; // @[el2_lsu_bus_intf.scala 184:27] + assign bus_buffer_io_lsu_pkt_r_by = io_lsu_pkt_r_by; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_half = io_lsu_pkt_r_half; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_word = io_lsu_pkt_r_word; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_load = io_lsu_pkt_r_load; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_store = io_lsu_pkt_r_store; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_pkt_r_unsign = io_lsu_pkt_r_unsign; // @[el2_lsu_bus_intf.scala 185:27] + assign bus_buffer_io_lsu_addr_m = io_lsu_addr_m; // @[el2_lsu_bus_intf.scala 188:51] + assign bus_buffer_io_end_addr_m = io_end_addr_m; // @[el2_lsu_bus_intf.scala 189:51] + assign bus_buffer_io_lsu_addr_r = io_lsu_addr_r; // @[el2_lsu_bus_intf.scala 190:51] + assign bus_buffer_io_end_addr_r = io_end_addr_r; // @[el2_lsu_bus_intf.scala 191:51] + assign bus_buffer_io_store_data_r = io_store_data_r; // @[el2_lsu_bus_intf.scala 192:51] + assign bus_buffer_io_no_word_merge_r = _T_22 & _T_24; // @[el2_lsu_bus_intf.scala 263:51] + assign bus_buffer_io_no_dword_merge_r = _T_22 & _T_30; // @[el2_lsu_bus_intf.scala 264:51] + assign bus_buffer_io_lsu_busreq_m = io_lsu_busreq_m; // @[el2_lsu_bus_intf.scala 194:51] + assign bus_buffer_io_ld_full_hit_m = _T_372 & _T_373; // @[el2_lsu_bus_intf.scala 270:51] + assign bus_buffer_io_flush_m_up = io_flush_m_up; // @[el2_lsu_bus_intf.scala 195:51] + assign bus_buffer_io_flush_r = io_flush_r; // @[el2_lsu_bus_intf.scala 196:51] + assign bus_buffer_io_lsu_commit_r = io_lsu_commit_r; // @[el2_lsu_bus_intf.scala 197:51] + assign bus_buffer_io_is_sideeffects_r = is_sideeffects_r; // @[el2_lsu_bus_intf.scala 265:51] + assign bus_buffer_io_ldst_dual_d = io_lsu_addr_d[2] != io_end_addr_d[2]; // @[el2_lsu_bus_intf.scala 266:51] + assign bus_buffer_io_ldst_dual_m = ldst_dual_m; // @[el2_lsu_bus_intf.scala 267:51] + assign bus_buffer_io_ldst_dual_r = ldst_dual_r; // @[el2_lsu_bus_intf.scala 268:51] + assign bus_buffer_io_ldst_byteen_ext_m = {{1'd0}, _T_34}; // @[el2_lsu_bus_intf.scala 269:51] + assign bus_buffer_io_lsu_axi_wready = io_lsu_axi_wready; // @[el2_lsu_bus_intf.scala 199:51] + assign bus_buffer_io_lsu_axi_bvalid = io_lsu_axi_bvalid; // @[el2_lsu_bus_intf.scala 200:51] + assign bus_buffer_io_lsu_axi_bresp = io_lsu_axi_bresp; // @[el2_lsu_bus_intf.scala 201:51] + assign bus_buffer_io_lsu_axi_bid = io_lsu_axi_bid; // @[el2_lsu_bus_intf.scala 202:51] + assign bus_buffer_io_lsu_axi_arready = io_lsu_axi_arready; // @[el2_lsu_bus_intf.scala 203:51] + assign bus_buffer_io_lsu_axi_rvalid = io_lsu_axi_rvalid; // @[el2_lsu_bus_intf.scala 204:51] + assign bus_buffer_io_lsu_axi_rid = io_lsu_axi_rid; // @[el2_lsu_bus_intf.scala 205:51] + assign bus_buffer_io_lsu_axi_rdata = io_lsu_axi_rdata; // @[el2_lsu_bus_intf.scala 206:51] + assign bus_buffer_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[el2_lsu_bus_intf.scala 208:51] + assign bus_buffer_io_lsu_bus_clk_en_q = lsu_bus_clk_en_q; // @[el2_lsu_bus_intf.scala 271:51] + assign bus_buffer_io_lsu_axi_awready = io_lsu_axi_awready; // @[el2_lsu_bus_intf.scala 198:51] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -4976,7 +5158,7 @@ initial begin _RAND_0 = {1{`RANDOM}}; ldst_dual_r = _RAND_0[0:0]; _RAND_1 = {1{`RANDOM}}; - _T_389 = _RAND_1[0:0]; + ldst_byteen_r = _RAND_1[3:0]; _RAND_2 = {1{`RANDOM}}; lsu_bus_clk_en_q = _RAND_2[0:0]; _RAND_3 = {1{`RANDOM}}; @@ -4988,7 +5170,7 @@ initial begin ldst_dual_r = 1'h0; end if (reset) begin - _T_389 = 1'h0; + ldst_byteen_r = 4'h0; end if (reset) begin lsu_bus_clk_en_q = 1'h0; @@ -5009,14 +5191,14 @@ end // initial if (reset) begin ldst_dual_r <= 1'h0; end else begin - ldst_dual_r <= io_lsu_bus_clk_en; + ldst_dual_r <= ldst_dual_m; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin - _T_389 <= 1'h0; + ldst_byteen_r <= 4'h0; end else begin - _T_389 <= io_lsu_bus_clk_en; + ldst_byteen_r <= _T_6 | _T_5; end end always @(posedge io_free_clk or posedge reset) begin @@ -5030,14 +5212,14 @@ end // initial if (reset) begin ldst_dual_m <= 1'h0; end else begin - ldst_dual_m <= io_lsu_bus_clk_en; + ldst_dual_m <= io_lsu_addr_d[2] != io_end_addr_d[2]; end end always @(posedge io_lsu_c1_r_clk or posedge reset) begin if (reset) begin is_sideeffects_r <= 1'h0; end else begin - is_sideeffects_r <= io_lsu_bus_clk_en; + is_sideeffects_r <= io_is_sideeffects_m; end end endmodule diff --git a/el2_pic_ctrl.anno.json b/el2_pic_ctrl.anno.json index 25feb095..2317d16a 100644 --- a/el2_pic_ctrl.anno.json +++ b/el2_pic_ctrl.anno.json @@ -1,7 +1,7 @@ [ { "class":"firrtl.transforms.CombinationalPath", - "sink":"~el2_pic_ctrl|el2_pic_ctrl>io_test", + "sink":"~el2_pic_ctrl|el2_pic_ctrl>io_picm_rd_data", "sources":[ "~el2_pic_ctrl|el2_pic_ctrl>io_extintsrc_req" ] @@ -10,10 +10,966 @@ "class":"firrtl.EmitCircuitAnnotation", "emitter":"firrtl.VerilogEmitter" }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>selected_int_priority" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_w_prior_en_0_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_0_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_1_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_2_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_3_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_4_33" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_0" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_1" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_2" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_3" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_4" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_5" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_6" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_7" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_8" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_9" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_10" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_11" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_12" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_13" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_14" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_15" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_16" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_17" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_18" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_19" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_20" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_21" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_22" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_23" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_24" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_25" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_26" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_27" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_28" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_29" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_30" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_31" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_32" + }, + { + "class":"firrtl.transforms.DontTouchAnnotation", + "target":"~el2_pic_ctrl|el2_pic_ctrl>level_intpend_id_5_33" + }, { "class":"firrtl.transforms.BlackBoxResourceAnno", - "target":"el2_pic_ctrl.TEC_RV_ICG", - "resourceId":"/vsrc/TEC_RV_ICG.v" + "target":"el2_pic_ctrl.gated_latch", + "resourceId":"/vsrc/gated_latch.v" }, { "class":"firrtl.options.TargetDirAnnotation", diff --git a/el2_pic_ctrl.fir b/el2_pic_ctrl.fir index ea0b7ce4..bd132cfd 100644 --- a/el2_pic_ctrl.fir +++ b/el2_pic_ctrl.fir @@ -1,12 +1,12 @@ ;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 circuit el2_pic_ctrl : - extmodule TEC_RV_ICG : + extmodule gated_latch : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr : @@ -14,23 +14,23 @@ circuit el2_pic_ctrl : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG @[beh_lib.scala 331:24] + inst clkhdr of gated_latch @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_1 : + extmodule gated_latch_1 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_1 : @@ -38,23 +38,23 @@ circuit el2_pic_ctrl : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_1 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_1 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_2 : + extmodule gated_latch_2 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_2 : @@ -62,23 +62,23 @@ circuit el2_pic_ctrl : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_2 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_2 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_3 : + extmodule gated_latch_3 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_3 : @@ -86,23 +86,23 @@ circuit el2_pic_ctrl : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_3 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_3 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] - extmodule TEC_RV_ICG_4 : + extmodule gated_latch_4 : output Q : Clock input CK : Clock input EN : UInt<1> input SE : UInt<1> - defname = TEC_RV_ICG + defname = gated_latch module rvclkhdr_4 : @@ -110,71 +110,138 @@ circuit el2_pic_ctrl : input reset : Reset output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} - inst clkhdr of TEC_RV_ICG_4 @[beh_lib.scala 331:24] + inst clkhdr of gated_latch_4 @[el2_lib.scala 474:26] clkhdr.SE is invalid clkhdr.EN is invalid clkhdr.CK is invalid clkhdr.Q is invalid - io.l1clk <= clkhdr.Q @[beh_lib.scala 332:12] - clkhdr.CK <= io.clk @[beh_lib.scala 333:16] - clkhdr.EN <= io.en @[beh_lib.scala 334:16] - clkhdr.SE <= io.scan_mode @[beh_lib.scala 335:16] - - module rvsyncss : - input clock : Clock - input reset : Reset - output io : {flip din : UInt<31>, dout : UInt<31>, flip clk : Clock} - - reg sync_ff1 : UInt, io.clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 32:43] - sync_ff1 <= io.din @[beh_lib.scala 32:43] - reg sync_ff2 : UInt, io.clk with : (reset => (reset, UInt<1>("h00"))) @[beh_lib.scala 33:43] - sync_ff2 <= sync_ff1 @[beh_lib.scala 33:43] - io.dout <= sync_ff2 @[beh_lib.scala 37:12] + io.l1clk <= clkhdr.Q @[el2_lib.scala 475:14] + clkhdr.CK <= io.clk @[el2_lib.scala 476:18] + clkhdr.EN <= io.en @[el2_lib.scala 477:18] + clkhdr.SE <= io.scan_mode @[el2_lib.scala 478:18] module el2_pic_ctrl : input clock : Clock input reset : AsyncReset - output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip picm_rdaddr : UInt<32>, flip picm_wraddr : UInt<32>, flip picm_wr_data : UInt<32>, flip picm_wren : UInt<1>, flip picm_rden : UInt<1>, flip picm_mken : UInt<1>, flip meicurpl : UInt<4>, flip meipt : UInt<4>, mexintpend : UInt<1>, claimid : UInt<8>, pl : UInt<4>, picm_rd_data : UInt<32>, mhwakeup : UInt<1>, test : UInt} + output io : {flip scan_mode : UInt<1>, flip free_clk : Clock, flip active_clk : Clock, flip clk_override : UInt<1>, flip extintsrc_req : UInt<32>, flip picm_rdaddr : UInt<32>, flip picm_wraddr : UInt<32>, flip picm_wr_data : UInt<32>, flip picm_wren : UInt<1>, flip picm_rden : UInt<1>, flip picm_mken : UInt<1>, flip meicurpl : UInt<4>, flip meipt : UInt<4>, mexintpend : UInt<1>, claimid : UInt<8>, pl : UInt<4>, picm_rd_data : UInt<32>, mhwakeup : UInt<1>} - io.mexintpend <= UInt<1>("h00") @[el2_pic_ctrl.scala 31:20] - io.claimid <= UInt<1>("h00") @[el2_pic_ctrl.scala 32:20] - io.pl <= UInt<1>("h00") @[el2_pic_ctrl.scala 33:20] - io.picm_rd_data <= UInt<1>("h00") @[el2_pic_ctrl.scala 34:20] - io.mhwakeup <= UInt<1>("h00") @[el2_pic_ctrl.scala 35:20] wire GW_CONFIG : UInt<32> GW_CONFIG <= UInt<1>("h00") - wire picm_rd_data_in : UInt<32> - picm_rd_data_in <= UInt<32>("h00") wire intpend_rd_out : UInt<32> intpend_rd_out <= UInt<32>("h00") wire intenable_rd_out : UInt<1> intenable_rd_out <= UInt<1>("h00") - wire intpriority_rd_out : UInt<4> - intpriority_rd_out <= UInt<4>("h00") - wire gw_config_rd_out : UInt<2> - gw_config_rd_out <= UInt<2>("h00") - wire intpriority_reg_we : UInt<32> - intpriority_reg_we <= UInt<32>("h00") - wire intpriority_reg_re : UInt<32> - intpriority_reg_re <= UInt<32>("h00") - wire intenable_reg : UInt<32> - intenable_reg <= UInt<32>("h00") - wire intenable_reg_we : UInt<32> - intenable_reg_we <= UInt<32>("h00") - wire intenable_reg_re : UInt<32> - intenable_reg_re <= UInt<32>("h00") - wire gw_config_reg_we : UInt<32> - gw_config_reg_we <= UInt<32>("h00") - wire gw_config_reg_re : UInt<32> - gw_config_reg_re <= UInt<32>("h00") - wire gw_clear_reg_we : UInt<32> - gw_clear_reg_we <= UInt<32>("h00") + wire intpriority_reg_inv : UInt<4>[32] @[el2_pic_ctl.scala 81:42] wire intpend_reg_extended : UInt<64> intpend_reg_extended <= UInt<64>("h00") wire selected_int_priority : UInt<4> selected_int_priority <= UInt<4>("h00") + wire intpend_w_prior_en : UInt<4>[32] @[el2_pic_ctl.scala 84:42] + wire intpend_id : UInt<8>[32] @[el2_pic_ctl.scala 85:42] + wire levelx_intpend_w_prior_en : UInt<4>[10][4] @[el2_pic_ctl.scala 86:42] + levelx_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + levelx_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 87:158] + wire levelx_intpend_id : UInt<8>[10][4] @[el2_pic_ctl.scala 88:42] + levelx_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + levelx_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 89:150] + wire l2_intpend_w_prior_en_ff : UInt<4>[8] @[el2_pic_ctl.scala 90:42] + l2_intpend_w_prior_en_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + l2_intpend_w_prior_en_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 91:109] + wire l2_intpend_id_ff : UInt<8>[8] @[el2_pic_ctl.scala 92:42] + l2_intpend_id_ff[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[1] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[2] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[3] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[4] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[5] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[6] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] + l2_intpend_id_ff[7] <= UInt<1>("h00") @[el2_pic_ctl.scala 93:101] wire config_reg : UInt<1> config_reg <= UInt<1>("h00") + wire intpriord : UInt<1> + intpriord <= UInt<1>("h00") wire prithresh_reg_write : UInt<1> prithresh_reg_write <= UInt<1>("h00") wire prithresh_reg_read : UInt<1> @@ -195,178 +262,4412 @@ circuit el2_pic_ctrl : picm_mken_ff <= UInt<1>("h00") wire claimid_in : UInt<8> claimid_in <= UInt<8>("h00") - wire pl_in : UInt<4> - pl_in <= UInt<4>("h00") - wire extintsrc_req_sync : UInt<32> - extintsrc_req_sync <= UInt<32>("h00") - wire extintsrc_req_gw : UInt<32> - extintsrc_req_gw <= UInt<32>("h00") - wire pic_raddr_c1_clk : Clock @[el2_pic_ctrl.scala 127:42] - wire pic_data_c1_clk : Clock @[el2_pic_ctrl.scala 128:42] - wire pic_pri_c1_clk : Clock @[el2_pic_ctrl.scala 129:42] - wire pic_int_c1_clk : Clock @[el2_pic_ctrl.scala 130:42] - wire gw_config_c1_clk : Clock @[el2_pic_ctrl.scala 131:42] - reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 133:56] - _T <= io.picm_rdaddr @[el2_pic_ctrl.scala 133:56] - picm_raddr_ff <= _T @[el2_pic_ctrl.scala 133:46] - reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 134:57] - _T_1 <= io.picm_wraddr @[el2_pic_ctrl.scala 134:57] - picm_waddr_ff <= _T_1 @[el2_pic_ctrl.scala 134:46] - reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 135:55] - _T_2 <= io.picm_wren @[el2_pic_ctrl.scala 135:55] - picm_wren_ff <= _T_2 @[el2_pic_ctrl.scala 135:45] - reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 136:55] - _T_3 <= io.picm_rden @[el2_pic_ctrl.scala 136:55] - picm_rden_ff <= _T_3 @[el2_pic_ctrl.scala 136:45] - reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 137:55] - _T_4 <= io.picm_mken @[el2_pic_ctrl.scala 137:55] - picm_mken_ff <= _T_4 @[el2_pic_ctrl.scala 137:45] - reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 138:58] - _T_5 <= io.picm_wr_data @[el2_pic_ctrl.scala 138:58] - picm_wr_data_ff <= _T_5 @[el2_pic_ctrl.scala 138:48] - node _T_6 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 140:53] - node raddr_intenable_base_match = eq(_T_6, UInt<25>("h01e01840")) @[el2_pic_ctrl.scala 140:71] - node _T_7 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 141:53] - node raddr_intpriority_base_match = eq(_T_7, UInt<25>("h01e01800")) @[el2_pic_ctrl.scala 141:71] - node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctrl.scala 142:53] - node raddr_config_gw_base_match = eq(_T_8, UInt<25>("h01e01880")) @[el2_pic_ctrl.scala 142:71] - node _T_9 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctrl.scala 143:53] - node raddr_config_pic_match = eq(_T_9, UInt<32>("h0f00c3000")) @[el2_pic_ctrl.scala 143:71] - node _T_10 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctrl.scala 144:53] - node addr_intpend_base_match = eq(_T_10, UInt<26>("h03c03040")) @[el2_pic_ctrl.scala 144:71] - node _T_11 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctrl.scala 146:53] - node waddr_config_pic_match = eq(_T_11, UInt<32>("h0f00c3000")) @[el2_pic_ctrl.scala 146:71] - node _T_12 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 147:53] - node addr_clear_gw_base_match = eq(_T_12, UInt<25>("h01e018a0")) @[el2_pic_ctrl.scala 147:71] - node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 148:53] - node waddr_intpriority_base_match = eq(_T_13, UInt<25>("h01e01800")) @[el2_pic_ctrl.scala 148:71] - node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 149:53] - node waddr_intenable_base_match = eq(_T_14, UInt<25>("h01e01840")) @[el2_pic_ctrl.scala 149:71] - node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctrl.scala 150:53] - node waddr_config_gw_base_match = eq(_T_15, UInt<25>("h01e01880")) @[el2_pic_ctrl.scala 150:71] - node _T_16 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctrl.scala 151:53] - node _T_17 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctrl.scala 151:86] - node picm_bypass_ff = and(_T_16, _T_17) @[el2_pic_ctrl.scala 151:68] - node _T_18 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctrl.scala 155:42] - node pic_raddr_c1_clken = or(_T_18, io.clk_override) @[el2_pic_ctrl.scala 155:57] - node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctrl.scala 156:42] - node _T_19 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 157:59] - node _T_20 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 157:108] - node _T_21 = or(_T_19, _T_20) @[el2_pic_ctrl.scala 157:76] - node pic_pri_c1_clken = or(_T_21, io.clk_override) @[el2_pic_ctrl.scala 157:124] - node _T_22 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 158:59] - node _T_23 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 158:106] - node _T_24 = or(_T_22, _T_23) @[el2_pic_ctrl.scala 158:76] - node pic_int_c1_clken = or(_T_24, io.clk_override) @[el2_pic_ctrl.scala 158:122] - node _T_25 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctrl.scala 159:59] - node _T_26 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 159:108] - node _T_27 = or(_T_25, _T_26) @[el2_pic_ctrl.scala 159:76] - node gw_config_c1_clken = or(_T_27, io.clk_override) @[el2_pic_ctrl.scala 159:124] - inst pic_addr_c1_cgc of rvclkhdr @[el2_pic_ctrl.scala 162:32] - pic_addr_c1_cgc.clock <= clock - pic_addr_c1_cgc.reset <= reset - pic_addr_c1_cgc.io.en <= pic_raddr_c1_clken @[el2_pic_ctrl.scala 163:34] - pic_raddr_c1_clk <= pic_addr_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 163:89] - pic_addr_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 164:34] - pic_addr_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 164:89] - inst pic_data_c1_cgc of rvclkhdr_1 @[el2_pic_ctrl.scala 166:32] - pic_data_c1_cgc.clock <= clock - pic_data_c1_cgc.reset <= reset - pic_data_c1_cgc.io.en <= pic_data_c1_clken @[el2_pic_ctrl.scala 167:34] - pic_data_c1_clk <= pic_data_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 167:89] - pic_data_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 168:34] - pic_data_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 168:89] - inst pic_pri_c1_cgc of rvclkhdr_2 @[el2_pic_ctrl.scala 170:31] - pic_pri_c1_cgc.clock <= clock - pic_pri_c1_cgc.reset <= reset - pic_pri_c1_cgc.io.en <= pic_pri_c1_clken @[el2_pic_ctrl.scala 171:33] - pic_pri_c1_clk <= pic_pri_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 171:87] - pic_pri_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 172:33] - pic_pri_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 172:87] - inst pic_int_c1_cgc of rvclkhdr_3 @[el2_pic_ctrl.scala 174:32] - pic_int_c1_cgc.clock <= clock - pic_int_c1_cgc.reset <= reset - pic_int_c1_cgc.io.en <= pic_int_c1_clken @[el2_pic_ctrl.scala 175:33] - pic_int_c1_clk <= pic_int_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 175:87] - pic_int_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 176:33] - pic_int_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 176:87] - inst gw_config_c1_cgc of rvclkhdr_4 @[el2_pic_ctrl.scala 178:33] - gw_config_c1_cgc.clock <= clock - gw_config_c1_cgc.reset <= reset - gw_config_c1_cgc.io.en <= gw_config_c1_clken @[el2_pic_ctrl.scala 179:35] - gw_config_c1_clk <= gw_config_c1_cgc.io.l1clk @[el2_pic_ctrl.scala 179:90] - gw_config_c1_cgc.io.clk <= clock @[el2_pic_ctrl.scala 180:35] - gw_config_c1_cgc.io.scan_mode <= io.scan_mode @[el2_pic_ctrl.scala 180:91] - inst sync_inst of rvsyncss @[el2_pic_ctrl.scala 185:26] - sync_inst.clock <= clock - sync_inst.reset <= reset - node _T_28 = shr(io.extintsrc_req, 1) @[el2_pic_ctrl.scala 186:48] - sync_inst.io.din <= _T_28 @[el2_pic_ctrl.scala 186:29] - node _T_29 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctrl.scala 187:71] - node _T_30 = cat(sync_inst.io.dout, _T_29) @[Cat.scala 29:58] - extintsrc_req_sync <= _T_30 @[el2_pic_ctrl.scala 187:29] - sync_inst.io.clk <= io.free_clk @[el2_pic_ctrl.scala 188:29] - io.test <= extintsrc_req_sync @[el2_pic_ctrl.scala 190:11] - node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctrl.scala 195:47] - node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctrl.scala 196:47] - node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctrl.scala 197:39] - node _T_31 = bits(config_reg_we, 0, 0) @[el2_pic_ctrl.scala 198:82] - reg _T_32 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] - when _T_31 : @[Reg.scala 28:19] - _T_32 <= config_reg_in @[Reg.scala 28:23] + wire pic_raddr_c1_clk : Clock @[el2_pic_ctl.scala 109:42] + wire pic_data_c1_clk : Clock @[el2_pic_ctl.scala 110:42] + wire pic_pri_c1_clk : Clock @[el2_pic_ctl.scala 111:42] + wire pic_int_c1_clk : Clock @[el2_pic_ctl.scala 112:42] + wire gw_config_c1_clk : Clock @[el2_pic_ctl.scala 113:42] + reg _T : UInt, pic_raddr_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 115:56] + _T <= io.picm_rdaddr @[el2_pic_ctl.scala 115:56] + picm_raddr_ff <= _T @[el2_pic_ctl.scala 115:46] + reg _T_1 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 116:57] + _T_1 <= io.picm_wraddr @[el2_pic_ctl.scala 116:57] + picm_waddr_ff <= _T_1 @[el2_pic_ctl.scala 116:46] + reg _T_2 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 117:55] + _T_2 <= io.picm_wren @[el2_pic_ctl.scala 117:55] + picm_wren_ff <= _T_2 @[el2_pic_ctl.scala 117:45] + reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 118:55] + _T_3 <= io.picm_rden @[el2_pic_ctl.scala 118:55] + picm_rden_ff <= _T_3 @[el2_pic_ctl.scala 118:45] + reg _T_4 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 119:55] + _T_4 <= io.picm_mken @[el2_pic_ctl.scala 119:55] + picm_mken_ff <= _T_4 @[el2_pic_ctl.scala 119:45] + reg _T_5 : UInt, pic_data_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 120:58] + _T_5 <= io.picm_wr_data @[el2_pic_ctl.scala 120:58] + picm_wr_data_ff <= _T_5 @[el2_pic_ctl.scala 120:48] + node _T_6 = xor(picm_raddr_ff, UInt<32>("h0f00c2000")) @[el2_pic_ctl.scala 122:59] + node temp_raddr_intenable_base_match = not(_T_6) @[el2_pic_ctl.scala 122:43] + node _T_7 = bits(temp_raddr_intenable_base_match, 31, 7) @[el2_pic_ctl.scala 123:71] + node raddr_intenable_base_match = andr(_T_7) @[el2_pic_ctl.scala 123:89] + node _T_8 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 125:53] + node raddr_intpriority_base_match = eq(_T_8, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 125:71] + node _T_9 = bits(picm_raddr_ff, 31, 7) @[el2_pic_ctl.scala 126:53] + node raddr_config_gw_base_match = eq(_T_9, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 126:71] + node _T_10 = bits(picm_raddr_ff, 31, 0) @[el2_pic_ctl.scala 127:53] + node raddr_config_pic_match = eq(_T_10, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 127:71] + node _T_11 = bits(picm_raddr_ff, 31, 6) @[el2_pic_ctl.scala 128:53] + node addr_intpend_base_match = eq(_T_11, UInt<26>("h03c03040")) @[el2_pic_ctl.scala 128:71] + node _T_12 = bits(picm_waddr_ff, 31, 0) @[el2_pic_ctl.scala 130:53] + node waddr_config_pic_match = eq(_T_12, UInt<32>("h0f00c3000")) @[el2_pic_ctl.scala 130:71] + node _T_13 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 131:53] + node addr_clear_gw_base_match = eq(_T_13, UInt<25>("h01e018a0")) @[el2_pic_ctl.scala 131:71] + node _T_14 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 132:53] + node waddr_intpriority_base_match = eq(_T_14, UInt<25>("h01e01800")) @[el2_pic_ctl.scala 132:71] + node _T_15 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 133:53] + node waddr_intenable_base_match = eq(_T_15, UInt<25>("h01e01840")) @[el2_pic_ctl.scala 133:71] + node _T_16 = bits(picm_waddr_ff, 31, 7) @[el2_pic_ctl.scala 134:53] + node waddr_config_gw_base_match = eq(_T_16, UInt<25>("h01e01880")) @[el2_pic_ctl.scala 134:71] + node _T_17 = and(picm_rden_ff, picm_wren_ff) @[el2_pic_ctl.scala 135:53] + node _T_18 = eq(picm_raddr_ff, picm_waddr_ff) @[el2_pic_ctl.scala 135:86] + node picm_bypass_ff = and(_T_17, _T_18) @[el2_pic_ctl.scala 135:68] + node _T_19 = or(io.picm_mken, io.picm_rden) @[el2_pic_ctl.scala 139:42] + node pic_raddr_c1_clken = or(_T_19, io.clk_override) @[el2_pic_ctl.scala 139:57] + node pic_data_c1_clken = or(io.picm_wren, io.clk_override) @[el2_pic_ctl.scala 140:42] + node _T_20 = and(waddr_intpriority_base_match, picm_wren_ff) @[el2_pic_ctl.scala 141:59] + node _T_21 = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 141:108] + node _T_22 = or(_T_20, _T_21) @[el2_pic_ctl.scala 141:76] + node pic_pri_c1_clken = or(_T_22, io.clk_override) @[el2_pic_ctl.scala 141:124] + node _T_23 = and(waddr_intenable_base_match, picm_wren_ff) @[el2_pic_ctl.scala 142:57] + node _T_24 = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 142:104] + node _T_25 = or(_T_23, _T_24) @[el2_pic_ctl.scala 142:74] + node pic_int_c1_clken = or(_T_25, io.clk_override) @[el2_pic_ctl.scala 142:120] + node _T_26 = and(waddr_config_gw_base_match, picm_wren_ff) @[el2_pic_ctl.scala 143:59] + node _T_27 = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 143:108] + node _T_28 = or(_T_26, _T_27) @[el2_pic_ctl.scala 143:76] + node gw_config_c1_clken = or(_T_28, io.clk_override) @[el2_pic_ctl.scala 143:124] + inst rvclkhdr of rvclkhdr @[el2_lib.scala 483:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr.io.en <= pic_raddr_c1_clken @[el2_lib.scala 485:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + pic_raddr_c1_clk <= rvclkhdr.io.l1clk @[el2_pic_ctl.scala 146:21] + inst rvclkhdr_1 of rvclkhdr_1 @[el2_lib.scala 483:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_1.io.en <= pic_data_c1_clken @[el2_lib.scala 485:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + pic_data_c1_clk <= rvclkhdr_1.io.l1clk @[el2_pic_ctl.scala 147:21] + node _T_29 = bits(pic_pri_c1_clken, 0, 0) @[el2_pic_ctl.scala 148:56] + inst rvclkhdr_2 of rvclkhdr_2 @[el2_lib.scala 483:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_2.io.en <= _T_29 @[el2_lib.scala 485:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + pic_pri_c1_clk <= rvclkhdr_2.io.l1clk @[el2_pic_ctl.scala 148:21] + node _T_30 = bits(pic_int_c1_clken, 0, 0) @[el2_pic_ctl.scala 149:56] + inst rvclkhdr_3 of rvclkhdr_3 @[el2_lib.scala 483:22] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_3.io.en <= _T_30 @[el2_lib.scala 485:16] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + pic_int_c1_clk <= rvclkhdr_3.io.l1clk @[el2_pic_ctl.scala 149:21] + node _T_31 = bits(gw_config_c1_clken, 0, 0) @[el2_pic_ctl.scala 150:58] + inst rvclkhdr_4 of rvclkhdr_4 @[el2_lib.scala 483:22] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[el2_lib.scala 484:17] + rvclkhdr_4.io.en <= _T_31 @[el2_lib.scala 485:16] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[el2_lib.scala 486:23] + gw_config_c1_clk <= rvclkhdr_4.io.l1clk @[el2_pic_ctl.scala 150:21] + node _T_32 = bits(io.extintsrc_req, 31, 1) @[el2_pic_ctl.scala 153:58] + reg _T_33 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:81] + _T_33 <= _T_32 @[el2_lib.scala 176:81] + reg _T_34 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_lib.scala 176:58] + _T_34 <= _T_33 @[el2_lib.scala 176:58] + node _T_35 = bits(io.extintsrc_req, 0, 0) @[el2_pic_ctl.scala 153:113] + node extintsrc_req_sync = cat(_T_34, _T_35) @[Cat.scala 29:58] + node _T_36 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_37 = eq(_T_36, UInt<1>("h01")) @[el2_pic_ctl.scala 155:139] + node _T_38 = and(waddr_intpriority_base_match, _T_37) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_1 = and(_T_38, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_39 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_40 = eq(_T_39, UInt<2>("h02")) @[el2_pic_ctl.scala 155:139] + node _T_41 = and(waddr_intpriority_base_match, _T_40) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_2 = and(_T_41, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_42 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_43 = eq(_T_42, UInt<2>("h03")) @[el2_pic_ctl.scala 155:139] + node _T_44 = and(waddr_intpriority_base_match, _T_43) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_3 = and(_T_44, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_45 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_46 = eq(_T_45, UInt<3>("h04")) @[el2_pic_ctl.scala 155:139] + node _T_47 = and(waddr_intpriority_base_match, _T_46) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_4 = and(_T_47, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_48 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_49 = eq(_T_48, UInt<3>("h05")) @[el2_pic_ctl.scala 155:139] + node _T_50 = and(waddr_intpriority_base_match, _T_49) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_5 = and(_T_50, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_51 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_52 = eq(_T_51, UInt<3>("h06")) @[el2_pic_ctl.scala 155:139] + node _T_53 = and(waddr_intpriority_base_match, _T_52) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_6 = and(_T_53, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_54 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_55 = eq(_T_54, UInt<3>("h07")) @[el2_pic_ctl.scala 155:139] + node _T_56 = and(waddr_intpriority_base_match, _T_55) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_7 = and(_T_56, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_57 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_58 = eq(_T_57, UInt<4>("h08")) @[el2_pic_ctl.scala 155:139] + node _T_59 = and(waddr_intpriority_base_match, _T_58) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_8 = and(_T_59, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_60 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_61 = eq(_T_60, UInt<4>("h09")) @[el2_pic_ctl.scala 155:139] + node _T_62 = and(waddr_intpriority_base_match, _T_61) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_9 = and(_T_62, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_63 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_64 = eq(_T_63, UInt<4>("h0a")) @[el2_pic_ctl.scala 155:139] + node _T_65 = and(waddr_intpriority_base_match, _T_64) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_10 = and(_T_65, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_66 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_67 = eq(_T_66, UInt<4>("h0b")) @[el2_pic_ctl.scala 155:139] + node _T_68 = and(waddr_intpriority_base_match, _T_67) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_11 = and(_T_68, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_69 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_70 = eq(_T_69, UInt<4>("h0c")) @[el2_pic_ctl.scala 155:139] + node _T_71 = and(waddr_intpriority_base_match, _T_70) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_12 = and(_T_71, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_72 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_73 = eq(_T_72, UInt<4>("h0d")) @[el2_pic_ctl.scala 155:139] + node _T_74 = and(waddr_intpriority_base_match, _T_73) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_13 = and(_T_74, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_75 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_76 = eq(_T_75, UInt<4>("h0e")) @[el2_pic_ctl.scala 155:139] + node _T_77 = and(waddr_intpriority_base_match, _T_76) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_14 = and(_T_77, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_78 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_79 = eq(_T_78, UInt<4>("h0f")) @[el2_pic_ctl.scala 155:139] + node _T_80 = and(waddr_intpriority_base_match, _T_79) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_15 = and(_T_80, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_81 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_82 = eq(_T_81, UInt<5>("h010")) @[el2_pic_ctl.scala 155:139] + node _T_83 = and(waddr_intpriority_base_match, _T_82) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_16 = and(_T_83, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_84 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_85 = eq(_T_84, UInt<5>("h011")) @[el2_pic_ctl.scala 155:139] + node _T_86 = and(waddr_intpriority_base_match, _T_85) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_17 = and(_T_86, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_87 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_88 = eq(_T_87, UInt<5>("h012")) @[el2_pic_ctl.scala 155:139] + node _T_89 = and(waddr_intpriority_base_match, _T_88) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_18 = and(_T_89, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_90 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_91 = eq(_T_90, UInt<5>("h013")) @[el2_pic_ctl.scala 155:139] + node _T_92 = and(waddr_intpriority_base_match, _T_91) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_19 = and(_T_92, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_93 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_94 = eq(_T_93, UInt<5>("h014")) @[el2_pic_ctl.scala 155:139] + node _T_95 = and(waddr_intpriority_base_match, _T_94) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_20 = and(_T_95, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_96 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_97 = eq(_T_96, UInt<5>("h015")) @[el2_pic_ctl.scala 155:139] + node _T_98 = and(waddr_intpriority_base_match, _T_97) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_21 = and(_T_98, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_99 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_100 = eq(_T_99, UInt<5>("h016")) @[el2_pic_ctl.scala 155:139] + node _T_101 = and(waddr_intpriority_base_match, _T_100) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_22 = and(_T_101, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_102 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_103 = eq(_T_102, UInt<5>("h017")) @[el2_pic_ctl.scala 155:139] + node _T_104 = and(waddr_intpriority_base_match, _T_103) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_23 = and(_T_104, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_105 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_106 = eq(_T_105, UInt<5>("h018")) @[el2_pic_ctl.scala 155:139] + node _T_107 = and(waddr_intpriority_base_match, _T_106) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_24 = and(_T_107, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_108 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_109 = eq(_T_108, UInt<5>("h019")) @[el2_pic_ctl.scala 155:139] + node _T_110 = and(waddr_intpriority_base_match, _T_109) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_25 = and(_T_110, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_111 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_112 = eq(_T_111, UInt<5>("h01a")) @[el2_pic_ctl.scala 155:139] + node _T_113 = and(waddr_intpriority_base_match, _T_112) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_26 = and(_T_113, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_114 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_115 = eq(_T_114, UInt<5>("h01b")) @[el2_pic_ctl.scala 155:139] + node _T_116 = and(waddr_intpriority_base_match, _T_115) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_27 = and(_T_116, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_117 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_118 = eq(_T_117, UInt<5>("h01c")) @[el2_pic_ctl.scala 155:139] + node _T_119 = and(waddr_intpriority_base_match, _T_118) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_28 = and(_T_119, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_120 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_121 = eq(_T_120, UInt<5>("h01d")) @[el2_pic_ctl.scala 155:139] + node _T_122 = and(waddr_intpriority_base_match, _T_121) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_29 = and(_T_122, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_123 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_124 = eq(_T_123, UInt<5>("h01e")) @[el2_pic_ctl.scala 155:139] + node _T_125 = and(waddr_intpriority_base_match, _T_124) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_30 = and(_T_125, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_126 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 155:122] + node _T_127 = eq(_T_126, UInt<5>("h01f")) @[el2_pic_ctl.scala 155:139] + node _T_128 = and(waddr_intpriority_base_match, _T_127) @[el2_pic_ctl.scala 155:106] + node intpriority_reg_we_31 = and(_T_128, picm_wren_ff) @[el2_pic_ctl.scala 155:153] + node _T_129 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_130 = eq(_T_129, UInt<1>("h01")) @[el2_pic_ctl.scala 156:139] + node _T_131 = and(raddr_intpriority_base_match, _T_130) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_1 = and(_T_131, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_132 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_133 = eq(_T_132, UInt<2>("h02")) @[el2_pic_ctl.scala 156:139] + node _T_134 = and(raddr_intpriority_base_match, _T_133) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_2 = and(_T_134, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_135 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_136 = eq(_T_135, UInt<2>("h03")) @[el2_pic_ctl.scala 156:139] + node _T_137 = and(raddr_intpriority_base_match, _T_136) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_3 = and(_T_137, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_138 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_139 = eq(_T_138, UInt<3>("h04")) @[el2_pic_ctl.scala 156:139] + node _T_140 = and(raddr_intpriority_base_match, _T_139) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_4 = and(_T_140, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_141 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_142 = eq(_T_141, UInt<3>("h05")) @[el2_pic_ctl.scala 156:139] + node _T_143 = and(raddr_intpriority_base_match, _T_142) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_5 = and(_T_143, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_144 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_145 = eq(_T_144, UInt<3>("h06")) @[el2_pic_ctl.scala 156:139] + node _T_146 = and(raddr_intpriority_base_match, _T_145) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_6 = and(_T_146, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_147 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_148 = eq(_T_147, UInt<3>("h07")) @[el2_pic_ctl.scala 156:139] + node _T_149 = and(raddr_intpriority_base_match, _T_148) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_7 = and(_T_149, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_150 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_151 = eq(_T_150, UInt<4>("h08")) @[el2_pic_ctl.scala 156:139] + node _T_152 = and(raddr_intpriority_base_match, _T_151) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_8 = and(_T_152, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_153 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_154 = eq(_T_153, UInt<4>("h09")) @[el2_pic_ctl.scala 156:139] + node _T_155 = and(raddr_intpriority_base_match, _T_154) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_9 = and(_T_155, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_156 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_157 = eq(_T_156, UInt<4>("h0a")) @[el2_pic_ctl.scala 156:139] + node _T_158 = and(raddr_intpriority_base_match, _T_157) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_10 = and(_T_158, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_159 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_160 = eq(_T_159, UInt<4>("h0b")) @[el2_pic_ctl.scala 156:139] + node _T_161 = and(raddr_intpriority_base_match, _T_160) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_11 = and(_T_161, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_162 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_163 = eq(_T_162, UInt<4>("h0c")) @[el2_pic_ctl.scala 156:139] + node _T_164 = and(raddr_intpriority_base_match, _T_163) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_12 = and(_T_164, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_165 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_166 = eq(_T_165, UInt<4>("h0d")) @[el2_pic_ctl.scala 156:139] + node _T_167 = and(raddr_intpriority_base_match, _T_166) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_13 = and(_T_167, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_168 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_169 = eq(_T_168, UInt<4>("h0e")) @[el2_pic_ctl.scala 156:139] + node _T_170 = and(raddr_intpriority_base_match, _T_169) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_14 = and(_T_170, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_171 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_172 = eq(_T_171, UInt<4>("h0f")) @[el2_pic_ctl.scala 156:139] + node _T_173 = and(raddr_intpriority_base_match, _T_172) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_15 = and(_T_173, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_174 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_175 = eq(_T_174, UInt<5>("h010")) @[el2_pic_ctl.scala 156:139] + node _T_176 = and(raddr_intpriority_base_match, _T_175) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_16 = and(_T_176, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_177 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_178 = eq(_T_177, UInt<5>("h011")) @[el2_pic_ctl.scala 156:139] + node _T_179 = and(raddr_intpriority_base_match, _T_178) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_17 = and(_T_179, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_180 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_181 = eq(_T_180, UInt<5>("h012")) @[el2_pic_ctl.scala 156:139] + node _T_182 = and(raddr_intpriority_base_match, _T_181) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_18 = and(_T_182, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_183 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_184 = eq(_T_183, UInt<5>("h013")) @[el2_pic_ctl.scala 156:139] + node _T_185 = and(raddr_intpriority_base_match, _T_184) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_19 = and(_T_185, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_186 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_187 = eq(_T_186, UInt<5>("h014")) @[el2_pic_ctl.scala 156:139] + node _T_188 = and(raddr_intpriority_base_match, _T_187) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_20 = and(_T_188, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_189 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_190 = eq(_T_189, UInt<5>("h015")) @[el2_pic_ctl.scala 156:139] + node _T_191 = and(raddr_intpriority_base_match, _T_190) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_21 = and(_T_191, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_192 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_193 = eq(_T_192, UInt<5>("h016")) @[el2_pic_ctl.scala 156:139] + node _T_194 = and(raddr_intpriority_base_match, _T_193) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_22 = and(_T_194, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_195 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_196 = eq(_T_195, UInt<5>("h017")) @[el2_pic_ctl.scala 156:139] + node _T_197 = and(raddr_intpriority_base_match, _T_196) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_23 = and(_T_197, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_198 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_199 = eq(_T_198, UInt<5>("h018")) @[el2_pic_ctl.scala 156:139] + node _T_200 = and(raddr_intpriority_base_match, _T_199) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_24 = and(_T_200, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_201 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_202 = eq(_T_201, UInt<5>("h019")) @[el2_pic_ctl.scala 156:139] + node _T_203 = and(raddr_intpriority_base_match, _T_202) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_25 = and(_T_203, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_204 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_205 = eq(_T_204, UInt<5>("h01a")) @[el2_pic_ctl.scala 156:139] + node _T_206 = and(raddr_intpriority_base_match, _T_205) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_26 = and(_T_206, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_207 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_208 = eq(_T_207, UInt<5>("h01b")) @[el2_pic_ctl.scala 156:139] + node _T_209 = and(raddr_intpriority_base_match, _T_208) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_27 = and(_T_209, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_210 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_211 = eq(_T_210, UInt<5>("h01c")) @[el2_pic_ctl.scala 156:139] + node _T_212 = and(raddr_intpriority_base_match, _T_211) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_28 = and(_T_212, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_213 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_214 = eq(_T_213, UInt<5>("h01d")) @[el2_pic_ctl.scala 156:139] + node _T_215 = and(raddr_intpriority_base_match, _T_214) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_29 = and(_T_215, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_216 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_217 = eq(_T_216, UInt<5>("h01e")) @[el2_pic_ctl.scala 156:139] + node _T_218 = and(raddr_intpriority_base_match, _T_217) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_30 = and(_T_218, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_219 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 156:122] + node _T_220 = eq(_T_219, UInt<5>("h01f")) @[el2_pic_ctl.scala 156:139] + node _T_221 = and(raddr_intpriority_base_match, _T_220) @[el2_pic_ctl.scala 156:106] + node intpriority_reg_re_31 = and(_T_221, picm_rden_ff) @[el2_pic_ctl.scala 156:153] + node _T_222 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_223 = eq(_T_222, UInt<1>("h01")) @[el2_pic_ctl.scala 157:139] + node _T_224 = and(waddr_intenable_base_match, _T_223) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_1 = and(_T_224, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_225 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_226 = eq(_T_225, UInt<2>("h02")) @[el2_pic_ctl.scala 157:139] + node _T_227 = and(waddr_intenable_base_match, _T_226) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_2 = and(_T_227, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_228 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_229 = eq(_T_228, UInt<2>("h03")) @[el2_pic_ctl.scala 157:139] + node _T_230 = and(waddr_intenable_base_match, _T_229) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_3 = and(_T_230, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_231 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_232 = eq(_T_231, UInt<3>("h04")) @[el2_pic_ctl.scala 157:139] + node _T_233 = and(waddr_intenable_base_match, _T_232) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_4 = and(_T_233, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_234 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_235 = eq(_T_234, UInt<3>("h05")) @[el2_pic_ctl.scala 157:139] + node _T_236 = and(waddr_intenable_base_match, _T_235) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_5 = and(_T_236, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_237 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_238 = eq(_T_237, UInt<3>("h06")) @[el2_pic_ctl.scala 157:139] + node _T_239 = and(waddr_intenable_base_match, _T_238) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_6 = and(_T_239, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_240 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_241 = eq(_T_240, UInt<3>("h07")) @[el2_pic_ctl.scala 157:139] + node _T_242 = and(waddr_intenable_base_match, _T_241) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_7 = and(_T_242, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_243 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_244 = eq(_T_243, UInt<4>("h08")) @[el2_pic_ctl.scala 157:139] + node _T_245 = and(waddr_intenable_base_match, _T_244) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_8 = and(_T_245, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_246 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_247 = eq(_T_246, UInt<4>("h09")) @[el2_pic_ctl.scala 157:139] + node _T_248 = and(waddr_intenable_base_match, _T_247) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_9 = and(_T_248, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_249 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_250 = eq(_T_249, UInt<4>("h0a")) @[el2_pic_ctl.scala 157:139] + node _T_251 = and(waddr_intenable_base_match, _T_250) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_10 = and(_T_251, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_252 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_253 = eq(_T_252, UInt<4>("h0b")) @[el2_pic_ctl.scala 157:139] + node _T_254 = and(waddr_intenable_base_match, _T_253) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_11 = and(_T_254, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_255 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_256 = eq(_T_255, UInt<4>("h0c")) @[el2_pic_ctl.scala 157:139] + node _T_257 = and(waddr_intenable_base_match, _T_256) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_12 = and(_T_257, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_258 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_259 = eq(_T_258, UInt<4>("h0d")) @[el2_pic_ctl.scala 157:139] + node _T_260 = and(waddr_intenable_base_match, _T_259) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_13 = and(_T_260, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_261 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_262 = eq(_T_261, UInt<4>("h0e")) @[el2_pic_ctl.scala 157:139] + node _T_263 = and(waddr_intenable_base_match, _T_262) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_14 = and(_T_263, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_264 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_265 = eq(_T_264, UInt<4>("h0f")) @[el2_pic_ctl.scala 157:139] + node _T_266 = and(waddr_intenable_base_match, _T_265) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_15 = and(_T_266, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_267 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_268 = eq(_T_267, UInt<5>("h010")) @[el2_pic_ctl.scala 157:139] + node _T_269 = and(waddr_intenable_base_match, _T_268) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_16 = and(_T_269, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_270 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_271 = eq(_T_270, UInt<5>("h011")) @[el2_pic_ctl.scala 157:139] + node _T_272 = and(waddr_intenable_base_match, _T_271) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_17 = and(_T_272, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_273 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_274 = eq(_T_273, UInt<5>("h012")) @[el2_pic_ctl.scala 157:139] + node _T_275 = and(waddr_intenable_base_match, _T_274) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_18 = and(_T_275, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_276 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_277 = eq(_T_276, UInt<5>("h013")) @[el2_pic_ctl.scala 157:139] + node _T_278 = and(waddr_intenable_base_match, _T_277) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_19 = and(_T_278, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_279 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_280 = eq(_T_279, UInt<5>("h014")) @[el2_pic_ctl.scala 157:139] + node _T_281 = and(waddr_intenable_base_match, _T_280) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_20 = and(_T_281, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_282 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_283 = eq(_T_282, UInt<5>("h015")) @[el2_pic_ctl.scala 157:139] + node _T_284 = and(waddr_intenable_base_match, _T_283) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_21 = and(_T_284, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_285 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_286 = eq(_T_285, UInt<5>("h016")) @[el2_pic_ctl.scala 157:139] + node _T_287 = and(waddr_intenable_base_match, _T_286) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_22 = and(_T_287, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_288 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_289 = eq(_T_288, UInt<5>("h017")) @[el2_pic_ctl.scala 157:139] + node _T_290 = and(waddr_intenable_base_match, _T_289) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_23 = and(_T_290, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_291 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_292 = eq(_T_291, UInt<5>("h018")) @[el2_pic_ctl.scala 157:139] + node _T_293 = and(waddr_intenable_base_match, _T_292) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_24 = and(_T_293, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_294 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_295 = eq(_T_294, UInt<5>("h019")) @[el2_pic_ctl.scala 157:139] + node _T_296 = and(waddr_intenable_base_match, _T_295) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_25 = and(_T_296, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_297 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_298 = eq(_T_297, UInt<5>("h01a")) @[el2_pic_ctl.scala 157:139] + node _T_299 = and(waddr_intenable_base_match, _T_298) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_26 = and(_T_299, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_300 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_301 = eq(_T_300, UInt<5>("h01b")) @[el2_pic_ctl.scala 157:139] + node _T_302 = and(waddr_intenable_base_match, _T_301) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_27 = and(_T_302, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_303 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_304 = eq(_T_303, UInt<5>("h01c")) @[el2_pic_ctl.scala 157:139] + node _T_305 = and(waddr_intenable_base_match, _T_304) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_28 = and(_T_305, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_306 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_307 = eq(_T_306, UInt<5>("h01d")) @[el2_pic_ctl.scala 157:139] + node _T_308 = and(waddr_intenable_base_match, _T_307) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_29 = and(_T_308, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_309 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_310 = eq(_T_309, UInt<5>("h01e")) @[el2_pic_ctl.scala 157:139] + node _T_311 = and(waddr_intenable_base_match, _T_310) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_30 = and(_T_311, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_312 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 157:122] + node _T_313 = eq(_T_312, UInt<5>("h01f")) @[el2_pic_ctl.scala 157:139] + node _T_314 = and(waddr_intenable_base_match, _T_313) @[el2_pic_ctl.scala 157:106] + node intenable_reg_we_31 = and(_T_314, picm_wren_ff) @[el2_pic_ctl.scala 157:153] + node _T_315 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_316 = eq(_T_315, UInt<1>("h01")) @[el2_pic_ctl.scala 158:139] + node _T_317 = and(raddr_intenable_base_match, _T_316) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_1 = and(_T_317, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_318 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_319 = eq(_T_318, UInt<2>("h02")) @[el2_pic_ctl.scala 158:139] + node _T_320 = and(raddr_intenable_base_match, _T_319) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_2 = and(_T_320, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_321 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_322 = eq(_T_321, UInt<2>("h03")) @[el2_pic_ctl.scala 158:139] + node _T_323 = and(raddr_intenable_base_match, _T_322) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_3 = and(_T_323, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_324 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_325 = eq(_T_324, UInt<3>("h04")) @[el2_pic_ctl.scala 158:139] + node _T_326 = and(raddr_intenable_base_match, _T_325) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_4 = and(_T_326, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_327 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_328 = eq(_T_327, UInt<3>("h05")) @[el2_pic_ctl.scala 158:139] + node _T_329 = and(raddr_intenable_base_match, _T_328) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_5 = and(_T_329, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_330 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_331 = eq(_T_330, UInt<3>("h06")) @[el2_pic_ctl.scala 158:139] + node _T_332 = and(raddr_intenable_base_match, _T_331) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_6 = and(_T_332, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_333 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_334 = eq(_T_333, UInt<3>("h07")) @[el2_pic_ctl.scala 158:139] + node _T_335 = and(raddr_intenable_base_match, _T_334) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_7 = and(_T_335, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_336 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_337 = eq(_T_336, UInt<4>("h08")) @[el2_pic_ctl.scala 158:139] + node _T_338 = and(raddr_intenable_base_match, _T_337) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_8 = and(_T_338, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_339 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_340 = eq(_T_339, UInt<4>("h09")) @[el2_pic_ctl.scala 158:139] + node _T_341 = and(raddr_intenable_base_match, _T_340) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_9 = and(_T_341, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_342 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_343 = eq(_T_342, UInt<4>("h0a")) @[el2_pic_ctl.scala 158:139] + node _T_344 = and(raddr_intenable_base_match, _T_343) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_10 = and(_T_344, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_345 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_346 = eq(_T_345, UInt<4>("h0b")) @[el2_pic_ctl.scala 158:139] + node _T_347 = and(raddr_intenable_base_match, _T_346) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_11 = and(_T_347, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_348 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_349 = eq(_T_348, UInt<4>("h0c")) @[el2_pic_ctl.scala 158:139] + node _T_350 = and(raddr_intenable_base_match, _T_349) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_12 = and(_T_350, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_351 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_352 = eq(_T_351, UInt<4>("h0d")) @[el2_pic_ctl.scala 158:139] + node _T_353 = and(raddr_intenable_base_match, _T_352) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_13 = and(_T_353, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_354 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_355 = eq(_T_354, UInt<4>("h0e")) @[el2_pic_ctl.scala 158:139] + node _T_356 = and(raddr_intenable_base_match, _T_355) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_14 = and(_T_356, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_357 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_358 = eq(_T_357, UInt<4>("h0f")) @[el2_pic_ctl.scala 158:139] + node _T_359 = and(raddr_intenable_base_match, _T_358) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_15 = and(_T_359, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_360 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_361 = eq(_T_360, UInt<5>("h010")) @[el2_pic_ctl.scala 158:139] + node _T_362 = and(raddr_intenable_base_match, _T_361) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_16 = and(_T_362, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_363 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_364 = eq(_T_363, UInt<5>("h011")) @[el2_pic_ctl.scala 158:139] + node _T_365 = and(raddr_intenable_base_match, _T_364) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_17 = and(_T_365, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_366 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_367 = eq(_T_366, UInt<5>("h012")) @[el2_pic_ctl.scala 158:139] + node _T_368 = and(raddr_intenable_base_match, _T_367) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_18 = and(_T_368, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_369 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_370 = eq(_T_369, UInt<5>("h013")) @[el2_pic_ctl.scala 158:139] + node _T_371 = and(raddr_intenable_base_match, _T_370) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_19 = and(_T_371, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_372 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_373 = eq(_T_372, UInt<5>("h014")) @[el2_pic_ctl.scala 158:139] + node _T_374 = and(raddr_intenable_base_match, _T_373) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_20 = and(_T_374, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_375 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_376 = eq(_T_375, UInt<5>("h015")) @[el2_pic_ctl.scala 158:139] + node _T_377 = and(raddr_intenable_base_match, _T_376) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_21 = and(_T_377, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_378 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_379 = eq(_T_378, UInt<5>("h016")) @[el2_pic_ctl.scala 158:139] + node _T_380 = and(raddr_intenable_base_match, _T_379) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_22 = and(_T_380, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_381 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_382 = eq(_T_381, UInt<5>("h017")) @[el2_pic_ctl.scala 158:139] + node _T_383 = and(raddr_intenable_base_match, _T_382) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_23 = and(_T_383, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_384 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_385 = eq(_T_384, UInt<5>("h018")) @[el2_pic_ctl.scala 158:139] + node _T_386 = and(raddr_intenable_base_match, _T_385) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_24 = and(_T_386, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_387 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_388 = eq(_T_387, UInt<5>("h019")) @[el2_pic_ctl.scala 158:139] + node _T_389 = and(raddr_intenable_base_match, _T_388) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_25 = and(_T_389, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_390 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_391 = eq(_T_390, UInt<5>("h01a")) @[el2_pic_ctl.scala 158:139] + node _T_392 = and(raddr_intenable_base_match, _T_391) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_26 = and(_T_392, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_393 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_394 = eq(_T_393, UInt<5>("h01b")) @[el2_pic_ctl.scala 158:139] + node _T_395 = and(raddr_intenable_base_match, _T_394) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_27 = and(_T_395, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_396 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_397 = eq(_T_396, UInt<5>("h01c")) @[el2_pic_ctl.scala 158:139] + node _T_398 = and(raddr_intenable_base_match, _T_397) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_28 = and(_T_398, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_399 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_400 = eq(_T_399, UInt<5>("h01d")) @[el2_pic_ctl.scala 158:139] + node _T_401 = and(raddr_intenable_base_match, _T_400) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_29 = and(_T_401, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_402 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_403 = eq(_T_402, UInt<5>("h01e")) @[el2_pic_ctl.scala 158:139] + node _T_404 = and(raddr_intenable_base_match, _T_403) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_30 = and(_T_404, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_405 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 158:122] + node _T_406 = eq(_T_405, UInt<5>("h01f")) @[el2_pic_ctl.scala 158:139] + node _T_407 = and(raddr_intenable_base_match, _T_406) @[el2_pic_ctl.scala 158:106] + node intenable_reg_re_31 = and(_T_407, picm_rden_ff) @[el2_pic_ctl.scala 158:153] + node _T_408 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_409 = eq(_T_408, UInt<1>("h01")) @[el2_pic_ctl.scala 159:139] + node _T_410 = and(waddr_config_gw_base_match, _T_409) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_1 = and(_T_410, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_411 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_412 = eq(_T_411, UInt<2>("h02")) @[el2_pic_ctl.scala 159:139] + node _T_413 = and(waddr_config_gw_base_match, _T_412) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_2 = and(_T_413, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_414 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_415 = eq(_T_414, UInt<2>("h03")) @[el2_pic_ctl.scala 159:139] + node _T_416 = and(waddr_config_gw_base_match, _T_415) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_3 = and(_T_416, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_417 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_418 = eq(_T_417, UInt<3>("h04")) @[el2_pic_ctl.scala 159:139] + node _T_419 = and(waddr_config_gw_base_match, _T_418) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_4 = and(_T_419, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_420 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_421 = eq(_T_420, UInt<3>("h05")) @[el2_pic_ctl.scala 159:139] + node _T_422 = and(waddr_config_gw_base_match, _T_421) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_5 = and(_T_422, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_423 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_424 = eq(_T_423, UInt<3>("h06")) @[el2_pic_ctl.scala 159:139] + node _T_425 = and(waddr_config_gw_base_match, _T_424) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_6 = and(_T_425, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_426 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_427 = eq(_T_426, UInt<3>("h07")) @[el2_pic_ctl.scala 159:139] + node _T_428 = and(waddr_config_gw_base_match, _T_427) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_7 = and(_T_428, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_429 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_430 = eq(_T_429, UInt<4>("h08")) @[el2_pic_ctl.scala 159:139] + node _T_431 = and(waddr_config_gw_base_match, _T_430) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_8 = and(_T_431, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_432 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_433 = eq(_T_432, UInt<4>("h09")) @[el2_pic_ctl.scala 159:139] + node _T_434 = and(waddr_config_gw_base_match, _T_433) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_9 = and(_T_434, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_435 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_436 = eq(_T_435, UInt<4>("h0a")) @[el2_pic_ctl.scala 159:139] + node _T_437 = and(waddr_config_gw_base_match, _T_436) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_10 = and(_T_437, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_438 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_439 = eq(_T_438, UInt<4>("h0b")) @[el2_pic_ctl.scala 159:139] + node _T_440 = and(waddr_config_gw_base_match, _T_439) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_11 = and(_T_440, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_441 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_442 = eq(_T_441, UInt<4>("h0c")) @[el2_pic_ctl.scala 159:139] + node _T_443 = and(waddr_config_gw_base_match, _T_442) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_12 = and(_T_443, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_444 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_445 = eq(_T_444, UInt<4>("h0d")) @[el2_pic_ctl.scala 159:139] + node _T_446 = and(waddr_config_gw_base_match, _T_445) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_13 = and(_T_446, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_447 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_448 = eq(_T_447, UInt<4>("h0e")) @[el2_pic_ctl.scala 159:139] + node _T_449 = and(waddr_config_gw_base_match, _T_448) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_14 = and(_T_449, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_450 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_451 = eq(_T_450, UInt<4>("h0f")) @[el2_pic_ctl.scala 159:139] + node _T_452 = and(waddr_config_gw_base_match, _T_451) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_15 = and(_T_452, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_453 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_454 = eq(_T_453, UInt<5>("h010")) @[el2_pic_ctl.scala 159:139] + node _T_455 = and(waddr_config_gw_base_match, _T_454) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_16 = and(_T_455, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_456 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_457 = eq(_T_456, UInt<5>("h011")) @[el2_pic_ctl.scala 159:139] + node _T_458 = and(waddr_config_gw_base_match, _T_457) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_17 = and(_T_458, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_459 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_460 = eq(_T_459, UInt<5>("h012")) @[el2_pic_ctl.scala 159:139] + node _T_461 = and(waddr_config_gw_base_match, _T_460) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_18 = and(_T_461, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_462 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_463 = eq(_T_462, UInt<5>("h013")) @[el2_pic_ctl.scala 159:139] + node _T_464 = and(waddr_config_gw_base_match, _T_463) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_19 = and(_T_464, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_465 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_466 = eq(_T_465, UInt<5>("h014")) @[el2_pic_ctl.scala 159:139] + node _T_467 = and(waddr_config_gw_base_match, _T_466) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_20 = and(_T_467, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_468 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_469 = eq(_T_468, UInt<5>("h015")) @[el2_pic_ctl.scala 159:139] + node _T_470 = and(waddr_config_gw_base_match, _T_469) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_21 = and(_T_470, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_471 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_472 = eq(_T_471, UInt<5>("h016")) @[el2_pic_ctl.scala 159:139] + node _T_473 = and(waddr_config_gw_base_match, _T_472) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_22 = and(_T_473, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_474 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_475 = eq(_T_474, UInt<5>("h017")) @[el2_pic_ctl.scala 159:139] + node _T_476 = and(waddr_config_gw_base_match, _T_475) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_23 = and(_T_476, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_477 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_478 = eq(_T_477, UInt<5>("h018")) @[el2_pic_ctl.scala 159:139] + node _T_479 = and(waddr_config_gw_base_match, _T_478) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_24 = and(_T_479, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_480 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_481 = eq(_T_480, UInt<5>("h019")) @[el2_pic_ctl.scala 159:139] + node _T_482 = and(waddr_config_gw_base_match, _T_481) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_25 = and(_T_482, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_483 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_484 = eq(_T_483, UInt<5>("h01a")) @[el2_pic_ctl.scala 159:139] + node _T_485 = and(waddr_config_gw_base_match, _T_484) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_26 = and(_T_485, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_486 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_487 = eq(_T_486, UInt<5>("h01b")) @[el2_pic_ctl.scala 159:139] + node _T_488 = and(waddr_config_gw_base_match, _T_487) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_27 = and(_T_488, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_489 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_490 = eq(_T_489, UInt<5>("h01c")) @[el2_pic_ctl.scala 159:139] + node _T_491 = and(waddr_config_gw_base_match, _T_490) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_28 = and(_T_491, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_492 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_493 = eq(_T_492, UInt<5>("h01d")) @[el2_pic_ctl.scala 159:139] + node _T_494 = and(waddr_config_gw_base_match, _T_493) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_29 = and(_T_494, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_495 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_496 = eq(_T_495, UInt<5>("h01e")) @[el2_pic_ctl.scala 159:139] + node _T_497 = and(waddr_config_gw_base_match, _T_496) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_30 = and(_T_497, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_498 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 159:122] + node _T_499 = eq(_T_498, UInt<5>("h01f")) @[el2_pic_ctl.scala 159:139] + node _T_500 = and(waddr_config_gw_base_match, _T_499) @[el2_pic_ctl.scala 159:106] + node gw_config_reg_we_31 = and(_T_500, picm_wren_ff) @[el2_pic_ctl.scala 159:153] + node _T_501 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_502 = eq(_T_501, UInt<1>("h01")) @[el2_pic_ctl.scala 160:139] + node _T_503 = and(raddr_config_gw_base_match, _T_502) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_1 = and(_T_503, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_504 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_505 = eq(_T_504, UInt<2>("h02")) @[el2_pic_ctl.scala 160:139] + node _T_506 = and(raddr_config_gw_base_match, _T_505) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_2 = and(_T_506, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_507 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_508 = eq(_T_507, UInt<2>("h03")) @[el2_pic_ctl.scala 160:139] + node _T_509 = and(raddr_config_gw_base_match, _T_508) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_3 = and(_T_509, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_510 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_511 = eq(_T_510, UInt<3>("h04")) @[el2_pic_ctl.scala 160:139] + node _T_512 = and(raddr_config_gw_base_match, _T_511) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_4 = and(_T_512, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_513 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_514 = eq(_T_513, UInt<3>("h05")) @[el2_pic_ctl.scala 160:139] + node _T_515 = and(raddr_config_gw_base_match, _T_514) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_5 = and(_T_515, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_516 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_517 = eq(_T_516, UInt<3>("h06")) @[el2_pic_ctl.scala 160:139] + node _T_518 = and(raddr_config_gw_base_match, _T_517) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_6 = and(_T_518, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_519 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_520 = eq(_T_519, UInt<3>("h07")) @[el2_pic_ctl.scala 160:139] + node _T_521 = and(raddr_config_gw_base_match, _T_520) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_7 = and(_T_521, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_522 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_523 = eq(_T_522, UInt<4>("h08")) @[el2_pic_ctl.scala 160:139] + node _T_524 = and(raddr_config_gw_base_match, _T_523) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_8 = and(_T_524, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_525 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_526 = eq(_T_525, UInt<4>("h09")) @[el2_pic_ctl.scala 160:139] + node _T_527 = and(raddr_config_gw_base_match, _T_526) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_9 = and(_T_527, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_528 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_529 = eq(_T_528, UInt<4>("h0a")) @[el2_pic_ctl.scala 160:139] + node _T_530 = and(raddr_config_gw_base_match, _T_529) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_10 = and(_T_530, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_531 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_532 = eq(_T_531, UInt<4>("h0b")) @[el2_pic_ctl.scala 160:139] + node _T_533 = and(raddr_config_gw_base_match, _T_532) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_11 = and(_T_533, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_534 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_535 = eq(_T_534, UInt<4>("h0c")) @[el2_pic_ctl.scala 160:139] + node _T_536 = and(raddr_config_gw_base_match, _T_535) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_12 = and(_T_536, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_537 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_538 = eq(_T_537, UInt<4>("h0d")) @[el2_pic_ctl.scala 160:139] + node _T_539 = and(raddr_config_gw_base_match, _T_538) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_13 = and(_T_539, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_540 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_541 = eq(_T_540, UInt<4>("h0e")) @[el2_pic_ctl.scala 160:139] + node _T_542 = and(raddr_config_gw_base_match, _T_541) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_14 = and(_T_542, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_543 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_544 = eq(_T_543, UInt<4>("h0f")) @[el2_pic_ctl.scala 160:139] + node _T_545 = and(raddr_config_gw_base_match, _T_544) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_15 = and(_T_545, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_546 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_547 = eq(_T_546, UInt<5>("h010")) @[el2_pic_ctl.scala 160:139] + node _T_548 = and(raddr_config_gw_base_match, _T_547) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_16 = and(_T_548, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_549 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_550 = eq(_T_549, UInt<5>("h011")) @[el2_pic_ctl.scala 160:139] + node _T_551 = and(raddr_config_gw_base_match, _T_550) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_17 = and(_T_551, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_552 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_553 = eq(_T_552, UInt<5>("h012")) @[el2_pic_ctl.scala 160:139] + node _T_554 = and(raddr_config_gw_base_match, _T_553) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_18 = and(_T_554, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_555 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_556 = eq(_T_555, UInt<5>("h013")) @[el2_pic_ctl.scala 160:139] + node _T_557 = and(raddr_config_gw_base_match, _T_556) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_19 = and(_T_557, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_558 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_559 = eq(_T_558, UInt<5>("h014")) @[el2_pic_ctl.scala 160:139] + node _T_560 = and(raddr_config_gw_base_match, _T_559) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_20 = and(_T_560, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_561 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_562 = eq(_T_561, UInt<5>("h015")) @[el2_pic_ctl.scala 160:139] + node _T_563 = and(raddr_config_gw_base_match, _T_562) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_21 = and(_T_563, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_564 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_565 = eq(_T_564, UInt<5>("h016")) @[el2_pic_ctl.scala 160:139] + node _T_566 = and(raddr_config_gw_base_match, _T_565) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_22 = and(_T_566, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_567 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_568 = eq(_T_567, UInt<5>("h017")) @[el2_pic_ctl.scala 160:139] + node _T_569 = and(raddr_config_gw_base_match, _T_568) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_23 = and(_T_569, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_570 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_571 = eq(_T_570, UInt<5>("h018")) @[el2_pic_ctl.scala 160:139] + node _T_572 = and(raddr_config_gw_base_match, _T_571) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_24 = and(_T_572, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_573 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_574 = eq(_T_573, UInt<5>("h019")) @[el2_pic_ctl.scala 160:139] + node _T_575 = and(raddr_config_gw_base_match, _T_574) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_25 = and(_T_575, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_576 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_577 = eq(_T_576, UInt<5>("h01a")) @[el2_pic_ctl.scala 160:139] + node _T_578 = and(raddr_config_gw_base_match, _T_577) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_26 = and(_T_578, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_579 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_580 = eq(_T_579, UInt<5>("h01b")) @[el2_pic_ctl.scala 160:139] + node _T_581 = and(raddr_config_gw_base_match, _T_580) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_27 = and(_T_581, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_582 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_583 = eq(_T_582, UInt<5>("h01c")) @[el2_pic_ctl.scala 160:139] + node _T_584 = and(raddr_config_gw_base_match, _T_583) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_28 = and(_T_584, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_585 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_586 = eq(_T_585, UInt<5>("h01d")) @[el2_pic_ctl.scala 160:139] + node _T_587 = and(raddr_config_gw_base_match, _T_586) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_29 = and(_T_587, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_588 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_589 = eq(_T_588, UInt<5>("h01e")) @[el2_pic_ctl.scala 160:139] + node _T_590 = and(raddr_config_gw_base_match, _T_589) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_30 = and(_T_590, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_591 = bits(picm_raddr_ff, 6, 2) @[el2_pic_ctl.scala 160:122] + node _T_592 = eq(_T_591, UInt<5>("h01f")) @[el2_pic_ctl.scala 160:139] + node _T_593 = and(raddr_config_gw_base_match, _T_592) @[el2_pic_ctl.scala 160:106] + node gw_config_reg_re_31 = and(_T_593, picm_rden_ff) @[el2_pic_ctl.scala 160:153] + node _T_594 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_595 = eq(_T_594, UInt<1>("h01")) @[el2_pic_ctl.scala 161:139] + node _T_596 = and(addr_clear_gw_base_match, _T_595) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_1 = and(_T_596, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_597 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_598 = eq(_T_597, UInt<2>("h02")) @[el2_pic_ctl.scala 161:139] + node _T_599 = and(addr_clear_gw_base_match, _T_598) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_2 = and(_T_599, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_600 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_601 = eq(_T_600, UInt<2>("h03")) @[el2_pic_ctl.scala 161:139] + node _T_602 = and(addr_clear_gw_base_match, _T_601) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_3 = and(_T_602, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_603 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_604 = eq(_T_603, UInt<3>("h04")) @[el2_pic_ctl.scala 161:139] + node _T_605 = and(addr_clear_gw_base_match, _T_604) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_4 = and(_T_605, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_606 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_607 = eq(_T_606, UInt<3>("h05")) @[el2_pic_ctl.scala 161:139] + node _T_608 = and(addr_clear_gw_base_match, _T_607) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_5 = and(_T_608, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_609 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_610 = eq(_T_609, UInt<3>("h06")) @[el2_pic_ctl.scala 161:139] + node _T_611 = and(addr_clear_gw_base_match, _T_610) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_6 = and(_T_611, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_612 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_613 = eq(_T_612, UInt<3>("h07")) @[el2_pic_ctl.scala 161:139] + node _T_614 = and(addr_clear_gw_base_match, _T_613) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_7 = and(_T_614, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_615 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_616 = eq(_T_615, UInt<4>("h08")) @[el2_pic_ctl.scala 161:139] + node _T_617 = and(addr_clear_gw_base_match, _T_616) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_8 = and(_T_617, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_618 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_619 = eq(_T_618, UInt<4>("h09")) @[el2_pic_ctl.scala 161:139] + node _T_620 = and(addr_clear_gw_base_match, _T_619) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_9 = and(_T_620, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_621 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_622 = eq(_T_621, UInt<4>("h0a")) @[el2_pic_ctl.scala 161:139] + node _T_623 = and(addr_clear_gw_base_match, _T_622) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_10 = and(_T_623, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_624 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_625 = eq(_T_624, UInt<4>("h0b")) @[el2_pic_ctl.scala 161:139] + node _T_626 = and(addr_clear_gw_base_match, _T_625) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_11 = and(_T_626, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_627 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_628 = eq(_T_627, UInt<4>("h0c")) @[el2_pic_ctl.scala 161:139] + node _T_629 = and(addr_clear_gw_base_match, _T_628) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_12 = and(_T_629, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_630 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_631 = eq(_T_630, UInt<4>("h0d")) @[el2_pic_ctl.scala 161:139] + node _T_632 = and(addr_clear_gw_base_match, _T_631) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_13 = and(_T_632, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_633 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_634 = eq(_T_633, UInt<4>("h0e")) @[el2_pic_ctl.scala 161:139] + node _T_635 = and(addr_clear_gw_base_match, _T_634) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_14 = and(_T_635, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_636 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_637 = eq(_T_636, UInt<4>("h0f")) @[el2_pic_ctl.scala 161:139] + node _T_638 = and(addr_clear_gw_base_match, _T_637) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_15 = and(_T_638, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_639 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_640 = eq(_T_639, UInt<5>("h010")) @[el2_pic_ctl.scala 161:139] + node _T_641 = and(addr_clear_gw_base_match, _T_640) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_16 = and(_T_641, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_642 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_643 = eq(_T_642, UInt<5>("h011")) @[el2_pic_ctl.scala 161:139] + node _T_644 = and(addr_clear_gw_base_match, _T_643) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_17 = and(_T_644, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_645 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_646 = eq(_T_645, UInt<5>("h012")) @[el2_pic_ctl.scala 161:139] + node _T_647 = and(addr_clear_gw_base_match, _T_646) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_18 = and(_T_647, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_648 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_649 = eq(_T_648, UInt<5>("h013")) @[el2_pic_ctl.scala 161:139] + node _T_650 = and(addr_clear_gw_base_match, _T_649) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_19 = and(_T_650, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_651 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_652 = eq(_T_651, UInt<5>("h014")) @[el2_pic_ctl.scala 161:139] + node _T_653 = and(addr_clear_gw_base_match, _T_652) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_20 = and(_T_653, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_654 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_655 = eq(_T_654, UInt<5>("h015")) @[el2_pic_ctl.scala 161:139] + node _T_656 = and(addr_clear_gw_base_match, _T_655) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_21 = and(_T_656, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_657 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_658 = eq(_T_657, UInt<5>("h016")) @[el2_pic_ctl.scala 161:139] + node _T_659 = and(addr_clear_gw_base_match, _T_658) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_22 = and(_T_659, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_660 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_661 = eq(_T_660, UInt<5>("h017")) @[el2_pic_ctl.scala 161:139] + node _T_662 = and(addr_clear_gw_base_match, _T_661) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_23 = and(_T_662, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_663 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_664 = eq(_T_663, UInt<5>("h018")) @[el2_pic_ctl.scala 161:139] + node _T_665 = and(addr_clear_gw_base_match, _T_664) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_24 = and(_T_665, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_666 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_667 = eq(_T_666, UInt<5>("h019")) @[el2_pic_ctl.scala 161:139] + node _T_668 = and(addr_clear_gw_base_match, _T_667) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_25 = and(_T_668, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_669 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_670 = eq(_T_669, UInt<5>("h01a")) @[el2_pic_ctl.scala 161:139] + node _T_671 = and(addr_clear_gw_base_match, _T_670) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_26 = and(_T_671, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_672 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_673 = eq(_T_672, UInt<5>("h01b")) @[el2_pic_ctl.scala 161:139] + node _T_674 = and(addr_clear_gw_base_match, _T_673) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_27 = and(_T_674, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_675 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_676 = eq(_T_675, UInt<5>("h01c")) @[el2_pic_ctl.scala 161:139] + node _T_677 = and(addr_clear_gw_base_match, _T_676) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_28 = and(_T_677, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_678 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_679 = eq(_T_678, UInt<5>("h01d")) @[el2_pic_ctl.scala 161:139] + node _T_680 = and(addr_clear_gw_base_match, _T_679) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_29 = and(_T_680, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_681 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_682 = eq(_T_681, UInt<5>("h01e")) @[el2_pic_ctl.scala 161:139] + node _T_683 = and(addr_clear_gw_base_match, _T_682) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_30 = and(_T_683, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + node _T_684 = bits(picm_waddr_ff, 6, 2) @[el2_pic_ctl.scala 161:122] + node _T_685 = eq(_T_684, UInt<5>("h01f")) @[el2_pic_ctl.scala 161:139] + node _T_686 = and(addr_clear_gw_base_match, _T_685) @[el2_pic_ctl.scala 161:106] + node gw_clear_reg_we_31 = and(_T_686, picm_wren_ff) @[el2_pic_ctl.scala 161:153] + wire intpriority_reg : UInt<4>[32] @[el2_pic_ctl.scala 162:32] + intpriority_reg[0] <= UInt<4>("h00") @[el2_pic_ctl.scala 163:208] + node _T_687 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_688 = bits(intpriority_reg_we_1, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_689 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_688 : @[Reg.scala 28:19] + _T_689 <= _T_687 @[Reg.scala 28:23] skip @[Reg.scala 28:19] - config_reg <= _T_32 @[el2_pic_ctrl.scala 198:37] - node _T_33 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 204:31] - node _T_34 = not(pl_in) @[el2_pic_ctrl.scala 204:38] - node pl_in_q = mux(_T_33, _T_34, pl_in) @[el2_pic_ctrl.scala 204:20] - reg _T_35 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 205:47] - _T_35 <= claimid_in @[el2_pic_ctrl.scala 205:47] - io.claimid <= _T_35 @[el2_pic_ctrl.scala 205:37] - reg _T_36 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 206:42] - _T_36 <= pl_in_q @[el2_pic_ctrl.scala 206:42] - io.pl <= _T_36 @[el2_pic_ctrl.scala 206:32] - node _T_37 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 207:33] - node _T_38 = eq(io.meipt, UInt<1>("h00")) @[el2_pic_ctrl.scala 207:40] - node meipt_inv = mux(_T_37, _T_38, io.meipt) @[el2_pic_ctrl.scala 207:22] - node _T_39 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 208:36] - node _T_40 = eq(io.meicurpl, UInt<1>("h00")) @[el2_pic_ctrl.scala 208:43] - node meicurpl_inv = mux(_T_39, _T_40, io.meicurpl) @[el2_pic_ctrl.scala 208:25] - node _T_41 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctrl.scala 209:47] - node _T_42 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctrl.scala 209:86] - node mexintpend_in = and(_T_41, _T_42) @[el2_pic_ctrl.scala 209:60] - reg _T_43 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 210:50] - _T_43 <= mexintpend_in @[el2_pic_ctrl.scala 210:50] - io.mexintpend <= _T_43 @[el2_pic_ctrl.scala 210:40] - node _T_44 = bits(config_reg, 0, 0) @[el2_pic_ctrl.scala 211:30] - node maxint = mux(_T_44, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctrl.scala 211:19] - node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctrl.scala 212:29] - reg _T_45 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctrl.scala 213:48] - _T_45 <= mhwakeup_in @[el2_pic_ctrl.scala 213:48] - io.mhwakeup <= _T_45 @[el2_pic_ctrl.scala 213:38] - node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 219:60] - node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 220:60] - node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 221:60] - node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctrl.scala 222:60] - node _T_46 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctrl.scala 227:98] - node _T_47 = eq(_T_46, UInt<1>("h00")) @[el2_pic_ctrl.scala 227:104] - node _T_48 = and(intpend_reg_read, _T_47) @[el2_pic_ctrl.scala 227:83] - node _T_49 = bits(_T_48, 0, 0) @[Bitwise.scala 72:15] - node _T_50 = mux(_T_49, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_51 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctrl.scala 227:140] - node _T_52 = and(_T_50, _T_51) @[el2_pic_ctrl.scala 227:118] - node _T_53 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctrl.scala 227:98] - node _T_54 = eq(_T_53, UInt<1>("h01")) @[el2_pic_ctrl.scala 227:104] - node _T_55 = and(intpend_reg_read, _T_54) @[el2_pic_ctrl.scala 227:83] - node _T_56 = bits(_T_55, 0, 0) @[Bitwise.scala 72:15] - node _T_57 = mux(_T_56, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] - node _T_58 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctrl.scala 227:140] - node _T_59 = and(_T_57, _T_58) @[el2_pic_ctrl.scala 227:118] - node intpend_rd_part_out = cat(_T_59, _T_52) @[Cat.scala 29:58] - node _T_60 = bits(intpend_rd_part_out, 0, 0) @[el2_pic_ctrl.scala 228:79] - node _T_61 = bits(intpend_rd_part_out, 1, 1) @[el2_pic_ctrl.scala 228:79] - wire _T_62 : UInt<1>[2] @[el2_pic_ctrl.scala 228:56] - _T_62[0] <= _T_60 @[el2_pic_ctrl.scala 228:56] - _T_62[1] <= _T_61 @[el2_pic_ctrl.scala 228:56] - node _T_63 = or(_T_62[0], _T_62[1]) @[el2_pic_ctrl.scala 228:93] - intpend_rd_out <= _T_63 @[el2_pic_ctrl.scala 228:27] + intpriority_reg[1] <= _T_689 @[el2_pic_ctl.scala 163:71] + node _T_690 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_691 = bits(intpriority_reg_we_2, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_692 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_691 : @[Reg.scala 28:19] + _T_692 <= _T_690 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[2] <= _T_692 @[el2_pic_ctl.scala 163:71] + node _T_693 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_694 = bits(intpriority_reg_we_3, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_695 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_694 : @[Reg.scala 28:19] + _T_695 <= _T_693 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[3] <= _T_695 @[el2_pic_ctl.scala 163:71] + node _T_696 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_697 = bits(intpriority_reg_we_4, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_698 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_697 : @[Reg.scala 28:19] + _T_698 <= _T_696 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[4] <= _T_698 @[el2_pic_ctl.scala 163:71] + node _T_699 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_700 = bits(intpriority_reg_we_5, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_701 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_700 : @[Reg.scala 28:19] + _T_701 <= _T_699 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[5] <= _T_701 @[el2_pic_ctl.scala 163:71] + node _T_702 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_703 = bits(intpriority_reg_we_6, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_704 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_703 : @[Reg.scala 28:19] + _T_704 <= _T_702 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[6] <= _T_704 @[el2_pic_ctl.scala 163:71] + node _T_705 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_706 = bits(intpriority_reg_we_7, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_707 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_706 : @[Reg.scala 28:19] + _T_707 <= _T_705 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[7] <= _T_707 @[el2_pic_ctl.scala 163:71] + node _T_708 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_709 = bits(intpriority_reg_we_8, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_710 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_709 : @[Reg.scala 28:19] + _T_710 <= _T_708 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[8] <= _T_710 @[el2_pic_ctl.scala 163:71] + node _T_711 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_712 = bits(intpriority_reg_we_9, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_713 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_712 : @[Reg.scala 28:19] + _T_713 <= _T_711 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[9] <= _T_713 @[el2_pic_ctl.scala 163:71] + node _T_714 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_715 = bits(intpriority_reg_we_10, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_716 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_715 : @[Reg.scala 28:19] + _T_716 <= _T_714 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[10] <= _T_716 @[el2_pic_ctl.scala 163:71] + node _T_717 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_718 = bits(intpriority_reg_we_11, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_719 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_718 : @[Reg.scala 28:19] + _T_719 <= _T_717 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[11] <= _T_719 @[el2_pic_ctl.scala 163:71] + node _T_720 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_721 = bits(intpriority_reg_we_12, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_722 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_721 : @[Reg.scala 28:19] + _T_722 <= _T_720 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[12] <= _T_722 @[el2_pic_ctl.scala 163:71] + node _T_723 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_724 = bits(intpriority_reg_we_13, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_725 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_724 : @[Reg.scala 28:19] + _T_725 <= _T_723 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[13] <= _T_725 @[el2_pic_ctl.scala 163:71] + node _T_726 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_727 = bits(intpriority_reg_we_14, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_728 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_727 : @[Reg.scala 28:19] + _T_728 <= _T_726 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[14] <= _T_728 @[el2_pic_ctl.scala 163:71] + node _T_729 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_730 = bits(intpriority_reg_we_15, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_731 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_730 : @[Reg.scala 28:19] + _T_731 <= _T_729 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[15] <= _T_731 @[el2_pic_ctl.scala 163:71] + node _T_732 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_733 = bits(intpriority_reg_we_16, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_734 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_733 : @[Reg.scala 28:19] + _T_734 <= _T_732 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[16] <= _T_734 @[el2_pic_ctl.scala 163:71] + node _T_735 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_736 = bits(intpriority_reg_we_17, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_737 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_736 : @[Reg.scala 28:19] + _T_737 <= _T_735 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[17] <= _T_737 @[el2_pic_ctl.scala 163:71] + node _T_738 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_739 = bits(intpriority_reg_we_18, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_740 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_739 : @[Reg.scala 28:19] + _T_740 <= _T_738 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[18] <= _T_740 @[el2_pic_ctl.scala 163:71] + node _T_741 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_742 = bits(intpriority_reg_we_19, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_743 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_742 : @[Reg.scala 28:19] + _T_743 <= _T_741 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[19] <= _T_743 @[el2_pic_ctl.scala 163:71] + node _T_744 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_745 = bits(intpriority_reg_we_20, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_746 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_745 : @[Reg.scala 28:19] + _T_746 <= _T_744 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[20] <= _T_746 @[el2_pic_ctl.scala 163:71] + node _T_747 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_748 = bits(intpriority_reg_we_21, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_749 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_748 : @[Reg.scala 28:19] + _T_749 <= _T_747 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[21] <= _T_749 @[el2_pic_ctl.scala 163:71] + node _T_750 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_751 = bits(intpriority_reg_we_22, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_752 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_751 : @[Reg.scala 28:19] + _T_752 <= _T_750 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[22] <= _T_752 @[el2_pic_ctl.scala 163:71] + node _T_753 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_754 = bits(intpriority_reg_we_23, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_755 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_754 : @[Reg.scala 28:19] + _T_755 <= _T_753 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[23] <= _T_755 @[el2_pic_ctl.scala 163:71] + node _T_756 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_757 = bits(intpriority_reg_we_24, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_758 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_757 : @[Reg.scala 28:19] + _T_758 <= _T_756 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[24] <= _T_758 @[el2_pic_ctl.scala 163:71] + node _T_759 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_760 = bits(intpriority_reg_we_25, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_761 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_760 : @[Reg.scala 28:19] + _T_761 <= _T_759 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[25] <= _T_761 @[el2_pic_ctl.scala 163:71] + node _T_762 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_763 = bits(intpriority_reg_we_26, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_764 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_763 : @[Reg.scala 28:19] + _T_764 <= _T_762 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[26] <= _T_764 @[el2_pic_ctl.scala 163:71] + node _T_765 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_766 = bits(intpriority_reg_we_27, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_767 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_766 : @[Reg.scala 28:19] + _T_767 <= _T_765 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[27] <= _T_767 @[el2_pic_ctl.scala 163:71] + node _T_768 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_769 = bits(intpriority_reg_we_28, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_770 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_769 : @[Reg.scala 28:19] + _T_770 <= _T_768 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[28] <= _T_770 @[el2_pic_ctl.scala 163:71] + node _T_771 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_772 = bits(intpriority_reg_we_29, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_773 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_772 : @[Reg.scala 28:19] + _T_773 <= _T_771 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[29] <= _T_773 @[el2_pic_ctl.scala 163:71] + node _T_774 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_775 = bits(intpriority_reg_we_30, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_776 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_775 : @[Reg.scala 28:19] + _T_776 <= _T_774 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[30] <= _T_776 @[el2_pic_ctl.scala 163:71] + node _T_777 = bits(picm_wr_data_ff, 3, 0) @[el2_pic_ctl.scala 163:125] + node _T_778 = bits(intpriority_reg_we_31, 0, 0) @[el2_pic_ctl.scala 163:174] + reg _T_779 : UInt, pic_pri_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_778 : @[Reg.scala 28:19] + _T_779 <= _T_777 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intpriority_reg[31] <= _T_779 @[el2_pic_ctl.scala 163:71] + wire intenable_reg : UInt<1>[32] @[el2_pic_ctl.scala 164:32] + intenable_reg[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 165:182] + node _T_780 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_781 = bits(intenable_reg_we_1, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_782 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_781 : @[Reg.scala 28:19] + _T_782 <= _T_780 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[1] <= _T_782 @[el2_pic_ctl.scala 165:68] + node _T_783 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_784 = bits(intenable_reg_we_2, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_785 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_784 : @[Reg.scala 28:19] + _T_785 <= _T_783 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[2] <= _T_785 @[el2_pic_ctl.scala 165:68] + node _T_786 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_787 = bits(intenable_reg_we_3, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_788 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_787 : @[Reg.scala 28:19] + _T_788 <= _T_786 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[3] <= _T_788 @[el2_pic_ctl.scala 165:68] + node _T_789 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_790 = bits(intenable_reg_we_4, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_791 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_790 : @[Reg.scala 28:19] + _T_791 <= _T_789 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[4] <= _T_791 @[el2_pic_ctl.scala 165:68] + node _T_792 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_793 = bits(intenable_reg_we_5, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_794 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_793 : @[Reg.scala 28:19] + _T_794 <= _T_792 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[5] <= _T_794 @[el2_pic_ctl.scala 165:68] + node _T_795 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_796 = bits(intenable_reg_we_6, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_797 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_796 : @[Reg.scala 28:19] + _T_797 <= _T_795 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[6] <= _T_797 @[el2_pic_ctl.scala 165:68] + node _T_798 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_799 = bits(intenable_reg_we_7, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_800 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_799 : @[Reg.scala 28:19] + _T_800 <= _T_798 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[7] <= _T_800 @[el2_pic_ctl.scala 165:68] + node _T_801 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_802 = bits(intenable_reg_we_8, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_803 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_802 : @[Reg.scala 28:19] + _T_803 <= _T_801 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[8] <= _T_803 @[el2_pic_ctl.scala 165:68] + node _T_804 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_805 = bits(intenable_reg_we_9, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_806 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_805 : @[Reg.scala 28:19] + _T_806 <= _T_804 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[9] <= _T_806 @[el2_pic_ctl.scala 165:68] + node _T_807 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_808 = bits(intenable_reg_we_10, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_809 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_808 : @[Reg.scala 28:19] + _T_809 <= _T_807 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[10] <= _T_809 @[el2_pic_ctl.scala 165:68] + node _T_810 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_811 = bits(intenable_reg_we_11, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_812 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_811 : @[Reg.scala 28:19] + _T_812 <= _T_810 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[11] <= _T_812 @[el2_pic_ctl.scala 165:68] + node _T_813 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_814 = bits(intenable_reg_we_12, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_815 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_814 : @[Reg.scala 28:19] + _T_815 <= _T_813 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[12] <= _T_815 @[el2_pic_ctl.scala 165:68] + node _T_816 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_817 = bits(intenable_reg_we_13, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_818 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_817 : @[Reg.scala 28:19] + _T_818 <= _T_816 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[13] <= _T_818 @[el2_pic_ctl.scala 165:68] + node _T_819 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_820 = bits(intenable_reg_we_14, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_821 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_820 : @[Reg.scala 28:19] + _T_821 <= _T_819 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[14] <= _T_821 @[el2_pic_ctl.scala 165:68] + node _T_822 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_823 = bits(intenable_reg_we_15, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_824 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_823 : @[Reg.scala 28:19] + _T_824 <= _T_822 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[15] <= _T_824 @[el2_pic_ctl.scala 165:68] + node _T_825 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_826 = bits(intenable_reg_we_16, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_827 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_826 : @[Reg.scala 28:19] + _T_827 <= _T_825 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[16] <= _T_827 @[el2_pic_ctl.scala 165:68] + node _T_828 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_829 = bits(intenable_reg_we_17, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_830 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_829 : @[Reg.scala 28:19] + _T_830 <= _T_828 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[17] <= _T_830 @[el2_pic_ctl.scala 165:68] + node _T_831 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_832 = bits(intenable_reg_we_18, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_833 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_832 : @[Reg.scala 28:19] + _T_833 <= _T_831 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[18] <= _T_833 @[el2_pic_ctl.scala 165:68] + node _T_834 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_835 = bits(intenable_reg_we_19, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_836 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_835 : @[Reg.scala 28:19] + _T_836 <= _T_834 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[19] <= _T_836 @[el2_pic_ctl.scala 165:68] + node _T_837 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_838 = bits(intenable_reg_we_20, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_839 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_838 : @[Reg.scala 28:19] + _T_839 <= _T_837 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[20] <= _T_839 @[el2_pic_ctl.scala 165:68] + node _T_840 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_841 = bits(intenable_reg_we_21, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_842 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_841 : @[Reg.scala 28:19] + _T_842 <= _T_840 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[21] <= _T_842 @[el2_pic_ctl.scala 165:68] + node _T_843 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_844 = bits(intenable_reg_we_22, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_845 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_844 : @[Reg.scala 28:19] + _T_845 <= _T_843 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[22] <= _T_845 @[el2_pic_ctl.scala 165:68] + node _T_846 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_847 = bits(intenable_reg_we_23, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_848 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_847 : @[Reg.scala 28:19] + _T_848 <= _T_846 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[23] <= _T_848 @[el2_pic_ctl.scala 165:68] + node _T_849 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_850 = bits(intenable_reg_we_24, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_851 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_850 : @[Reg.scala 28:19] + _T_851 <= _T_849 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[24] <= _T_851 @[el2_pic_ctl.scala 165:68] + node _T_852 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_853 = bits(intenable_reg_we_25, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_854 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_853 : @[Reg.scala 28:19] + _T_854 <= _T_852 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[25] <= _T_854 @[el2_pic_ctl.scala 165:68] + node _T_855 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_856 = bits(intenable_reg_we_26, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_857 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_856 : @[Reg.scala 28:19] + _T_857 <= _T_855 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[26] <= _T_857 @[el2_pic_ctl.scala 165:68] + node _T_858 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_859 = bits(intenable_reg_we_27, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_860 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_859 : @[Reg.scala 28:19] + _T_860 <= _T_858 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[27] <= _T_860 @[el2_pic_ctl.scala 165:68] + node _T_861 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_862 = bits(intenable_reg_we_28, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_863 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_862 : @[Reg.scala 28:19] + _T_863 <= _T_861 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[28] <= _T_863 @[el2_pic_ctl.scala 165:68] + node _T_864 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_865 = bits(intenable_reg_we_29, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_866 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_865 : @[Reg.scala 28:19] + _T_866 <= _T_864 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[29] <= _T_866 @[el2_pic_ctl.scala 165:68] + node _T_867 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_868 = bits(intenable_reg_we_30, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_869 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_868 : @[Reg.scala 28:19] + _T_869 <= _T_867 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[30] <= _T_869 @[el2_pic_ctl.scala 165:68] + node _T_870 = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 165:122] + node _T_871 = bits(intenable_reg_we_31, 0, 0) @[el2_pic_ctl.scala 165:150] + reg _T_872 : UInt, pic_int_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_871 : @[Reg.scala 28:19] + _T_872 <= _T_870 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + intenable_reg[31] <= _T_872 @[el2_pic_ctl.scala 165:68] + wire gw_config_reg : UInt<2>[32] @[el2_pic_ctl.scala 166:32] + gw_config_reg[0] <= UInt<2>("h00") @[el2_pic_ctl.scala 167:190] + node _T_873 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_874 = bits(gw_config_reg_we_1, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_875 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_874 : @[Reg.scala 28:19] + _T_875 <= _T_873 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[1] <= _T_875 @[el2_pic_ctl.scala 167:70] + node _T_876 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_877 = bits(gw_config_reg_we_2, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_878 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_877 : @[Reg.scala 28:19] + _T_878 <= _T_876 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[2] <= _T_878 @[el2_pic_ctl.scala 167:70] + node _T_879 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_880 = bits(gw_config_reg_we_3, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_881 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_880 : @[Reg.scala 28:19] + _T_881 <= _T_879 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[3] <= _T_881 @[el2_pic_ctl.scala 167:70] + node _T_882 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_883 = bits(gw_config_reg_we_4, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_884 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_883 : @[Reg.scala 28:19] + _T_884 <= _T_882 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[4] <= _T_884 @[el2_pic_ctl.scala 167:70] + node _T_885 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_886 = bits(gw_config_reg_we_5, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_887 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_886 : @[Reg.scala 28:19] + _T_887 <= _T_885 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[5] <= _T_887 @[el2_pic_ctl.scala 167:70] + node _T_888 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_889 = bits(gw_config_reg_we_6, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_890 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_889 : @[Reg.scala 28:19] + _T_890 <= _T_888 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[6] <= _T_890 @[el2_pic_ctl.scala 167:70] + node _T_891 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_892 = bits(gw_config_reg_we_7, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_893 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_892 : @[Reg.scala 28:19] + _T_893 <= _T_891 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[7] <= _T_893 @[el2_pic_ctl.scala 167:70] + node _T_894 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_895 = bits(gw_config_reg_we_8, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_896 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_895 : @[Reg.scala 28:19] + _T_896 <= _T_894 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[8] <= _T_896 @[el2_pic_ctl.scala 167:70] + node _T_897 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_898 = bits(gw_config_reg_we_9, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_899 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_898 : @[Reg.scala 28:19] + _T_899 <= _T_897 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[9] <= _T_899 @[el2_pic_ctl.scala 167:70] + node _T_900 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_901 = bits(gw_config_reg_we_10, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_902 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_901 : @[Reg.scala 28:19] + _T_902 <= _T_900 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[10] <= _T_902 @[el2_pic_ctl.scala 167:70] + node _T_903 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_904 = bits(gw_config_reg_we_11, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_905 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_904 : @[Reg.scala 28:19] + _T_905 <= _T_903 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[11] <= _T_905 @[el2_pic_ctl.scala 167:70] + node _T_906 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_907 = bits(gw_config_reg_we_12, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_908 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_907 : @[Reg.scala 28:19] + _T_908 <= _T_906 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[12] <= _T_908 @[el2_pic_ctl.scala 167:70] + node _T_909 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_910 = bits(gw_config_reg_we_13, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_911 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_910 : @[Reg.scala 28:19] + _T_911 <= _T_909 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[13] <= _T_911 @[el2_pic_ctl.scala 167:70] + node _T_912 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_913 = bits(gw_config_reg_we_14, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_914 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_913 : @[Reg.scala 28:19] + _T_914 <= _T_912 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[14] <= _T_914 @[el2_pic_ctl.scala 167:70] + node _T_915 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_916 = bits(gw_config_reg_we_15, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_917 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_916 : @[Reg.scala 28:19] + _T_917 <= _T_915 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[15] <= _T_917 @[el2_pic_ctl.scala 167:70] + node _T_918 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_919 = bits(gw_config_reg_we_16, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_920 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_919 : @[Reg.scala 28:19] + _T_920 <= _T_918 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[16] <= _T_920 @[el2_pic_ctl.scala 167:70] + node _T_921 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_922 = bits(gw_config_reg_we_17, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_923 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_922 : @[Reg.scala 28:19] + _T_923 <= _T_921 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[17] <= _T_923 @[el2_pic_ctl.scala 167:70] + node _T_924 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_925 = bits(gw_config_reg_we_18, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_926 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_925 : @[Reg.scala 28:19] + _T_926 <= _T_924 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[18] <= _T_926 @[el2_pic_ctl.scala 167:70] + node _T_927 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_928 = bits(gw_config_reg_we_19, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_929 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_928 : @[Reg.scala 28:19] + _T_929 <= _T_927 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[19] <= _T_929 @[el2_pic_ctl.scala 167:70] + node _T_930 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_931 = bits(gw_config_reg_we_20, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_932 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_931 : @[Reg.scala 28:19] + _T_932 <= _T_930 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[20] <= _T_932 @[el2_pic_ctl.scala 167:70] + node _T_933 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_934 = bits(gw_config_reg_we_21, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_935 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_934 : @[Reg.scala 28:19] + _T_935 <= _T_933 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[21] <= _T_935 @[el2_pic_ctl.scala 167:70] + node _T_936 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_937 = bits(gw_config_reg_we_22, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_938 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_937 : @[Reg.scala 28:19] + _T_938 <= _T_936 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[22] <= _T_938 @[el2_pic_ctl.scala 167:70] + node _T_939 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_940 = bits(gw_config_reg_we_23, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_941 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_940 : @[Reg.scala 28:19] + _T_941 <= _T_939 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[23] <= _T_941 @[el2_pic_ctl.scala 167:70] + node _T_942 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_943 = bits(gw_config_reg_we_24, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_944 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_943 : @[Reg.scala 28:19] + _T_944 <= _T_942 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[24] <= _T_944 @[el2_pic_ctl.scala 167:70] + node _T_945 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_946 = bits(gw_config_reg_we_25, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_947 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_946 : @[Reg.scala 28:19] + _T_947 <= _T_945 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[25] <= _T_947 @[el2_pic_ctl.scala 167:70] + node _T_948 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_949 = bits(gw_config_reg_we_26, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_950 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_949 : @[Reg.scala 28:19] + _T_950 <= _T_948 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[26] <= _T_950 @[el2_pic_ctl.scala 167:70] + node _T_951 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_952 = bits(gw_config_reg_we_27, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_953 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_952 : @[Reg.scala 28:19] + _T_953 <= _T_951 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[27] <= _T_953 @[el2_pic_ctl.scala 167:70] + node _T_954 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_955 = bits(gw_config_reg_we_28, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_956 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_955 : @[Reg.scala 28:19] + _T_956 <= _T_954 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[28] <= _T_956 @[el2_pic_ctl.scala 167:70] + node _T_957 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_958 = bits(gw_config_reg_we_29, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_959 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_958 : @[Reg.scala 28:19] + _T_959 <= _T_957 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[29] <= _T_959 @[el2_pic_ctl.scala 167:70] + node _T_960 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_961 = bits(gw_config_reg_we_30, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_962 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_961 : @[Reg.scala 28:19] + _T_962 <= _T_960 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[30] <= _T_962 @[el2_pic_ctl.scala 167:70] + node _T_963 = bits(picm_wr_data_ff, 1, 0) @[el2_pic_ctl.scala 167:126] + node _T_964 = bits(gw_config_reg_we_31, 0, 0) @[el2_pic_ctl.scala 167:156] + reg _T_965 : UInt, gw_config_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_964 : @[Reg.scala 28:19] + _T_965 <= _T_963 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + gw_config_reg[31] <= _T_965 @[el2_pic_ctl.scala 167:70] + node _T_966 = bits(extintsrc_req_sync, 1, 1) @[el2_pic_ctl.scala 170:43] + node _T_967 = bits(gw_config_reg[1], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_968 = bits(gw_config_reg[1], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_969 = bits(gw_clear_reg_we_1, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending : UInt<1> + gw_int_pending <= UInt<1>("h00") + node _T_970 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 45:50] + node _T_971 = eq(_T_969, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_972 = and(gw_int_pending, _T_971) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in = or(_T_970, _T_972) @[el2_pic_ctl.scala 45:72] + reg _T_973 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_973 <= gw_int_pending_in @[el2_pic_ctl.scala 46:30] + gw_int_pending <= _T_973 @[el2_pic_ctl.scala 46:20] + node _T_974 = bits(_T_968, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_975 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:55] + node _T_976 = or(_T_975, gw_int_pending) @[el2_pic_ctl.scala 47:78] + node _T_977 = xor(_T_966, _T_967) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_1 = mux(_T_974, _T_976, _T_977) @[el2_pic_ctl.scala 47:8] + node _T_978 = bits(extintsrc_req_sync, 2, 2) @[el2_pic_ctl.scala 170:43] + node _T_979 = bits(gw_config_reg[2], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_980 = bits(gw_config_reg[2], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_981 = bits(gw_clear_reg_we_2, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_1 : UInt<1> + gw_int_pending_1 <= UInt<1>("h00") + node _T_982 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 45:50] + node _T_983 = eq(_T_981, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_984 = and(gw_int_pending_1, _T_983) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_1 = or(_T_982, _T_984) @[el2_pic_ctl.scala 45:72] + reg _T_985 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_985 <= gw_int_pending_in_1 @[el2_pic_ctl.scala 46:30] + gw_int_pending_1 <= _T_985 @[el2_pic_ctl.scala 46:20] + node _T_986 = bits(_T_980, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_987 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:55] + node _T_988 = or(_T_987, gw_int_pending_1) @[el2_pic_ctl.scala 47:78] + node _T_989 = xor(_T_978, _T_979) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_2 = mux(_T_986, _T_988, _T_989) @[el2_pic_ctl.scala 47:8] + node _T_990 = bits(extintsrc_req_sync, 3, 3) @[el2_pic_ctl.scala 170:43] + node _T_991 = bits(gw_config_reg[3], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_992 = bits(gw_config_reg[3], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_993 = bits(gw_clear_reg_we_3, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_2 : UInt<1> + gw_int_pending_2 <= UInt<1>("h00") + node _T_994 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 45:50] + node _T_995 = eq(_T_993, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_996 = and(gw_int_pending_2, _T_995) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_2 = or(_T_994, _T_996) @[el2_pic_ctl.scala 45:72] + reg _T_997 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_997 <= gw_int_pending_in_2 @[el2_pic_ctl.scala 46:30] + gw_int_pending_2 <= _T_997 @[el2_pic_ctl.scala 46:20] + node _T_998 = bits(_T_992, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_999 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:55] + node _T_1000 = or(_T_999, gw_int_pending_2) @[el2_pic_ctl.scala 47:78] + node _T_1001 = xor(_T_990, _T_991) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_3 = mux(_T_998, _T_1000, _T_1001) @[el2_pic_ctl.scala 47:8] + node _T_1002 = bits(extintsrc_req_sync, 4, 4) @[el2_pic_ctl.scala 170:43] + node _T_1003 = bits(gw_config_reg[4], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1004 = bits(gw_config_reg[4], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1005 = bits(gw_clear_reg_we_4, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_3 : UInt<1> + gw_int_pending_3 <= UInt<1>("h00") + node _T_1006 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 45:50] + node _T_1007 = eq(_T_1005, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1008 = and(gw_int_pending_3, _T_1007) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_3 = or(_T_1006, _T_1008) @[el2_pic_ctl.scala 45:72] + reg _T_1009 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1009 <= gw_int_pending_in_3 @[el2_pic_ctl.scala 46:30] + gw_int_pending_3 <= _T_1009 @[el2_pic_ctl.scala 46:20] + node _T_1010 = bits(_T_1004, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1011 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:55] + node _T_1012 = or(_T_1011, gw_int_pending_3) @[el2_pic_ctl.scala 47:78] + node _T_1013 = xor(_T_1002, _T_1003) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_4 = mux(_T_1010, _T_1012, _T_1013) @[el2_pic_ctl.scala 47:8] + node _T_1014 = bits(extintsrc_req_sync, 5, 5) @[el2_pic_ctl.scala 170:43] + node _T_1015 = bits(gw_config_reg[5], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1016 = bits(gw_config_reg[5], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1017 = bits(gw_clear_reg_we_5, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_4 : UInt<1> + gw_int_pending_4 <= UInt<1>("h00") + node _T_1018 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 45:50] + node _T_1019 = eq(_T_1017, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1020 = and(gw_int_pending_4, _T_1019) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_4 = or(_T_1018, _T_1020) @[el2_pic_ctl.scala 45:72] + reg _T_1021 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1021 <= gw_int_pending_in_4 @[el2_pic_ctl.scala 46:30] + gw_int_pending_4 <= _T_1021 @[el2_pic_ctl.scala 46:20] + node _T_1022 = bits(_T_1016, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1023 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:55] + node _T_1024 = or(_T_1023, gw_int_pending_4) @[el2_pic_ctl.scala 47:78] + node _T_1025 = xor(_T_1014, _T_1015) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_5 = mux(_T_1022, _T_1024, _T_1025) @[el2_pic_ctl.scala 47:8] + node _T_1026 = bits(extintsrc_req_sync, 6, 6) @[el2_pic_ctl.scala 170:43] + node _T_1027 = bits(gw_config_reg[6], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1028 = bits(gw_config_reg[6], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1029 = bits(gw_clear_reg_we_6, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_5 : UInt<1> + gw_int_pending_5 <= UInt<1>("h00") + node _T_1030 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 45:50] + node _T_1031 = eq(_T_1029, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1032 = and(gw_int_pending_5, _T_1031) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_5 = or(_T_1030, _T_1032) @[el2_pic_ctl.scala 45:72] + reg _T_1033 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1033 <= gw_int_pending_in_5 @[el2_pic_ctl.scala 46:30] + gw_int_pending_5 <= _T_1033 @[el2_pic_ctl.scala 46:20] + node _T_1034 = bits(_T_1028, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1035 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:55] + node _T_1036 = or(_T_1035, gw_int_pending_5) @[el2_pic_ctl.scala 47:78] + node _T_1037 = xor(_T_1026, _T_1027) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_6 = mux(_T_1034, _T_1036, _T_1037) @[el2_pic_ctl.scala 47:8] + node _T_1038 = bits(extintsrc_req_sync, 7, 7) @[el2_pic_ctl.scala 170:43] + node _T_1039 = bits(gw_config_reg[7], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1040 = bits(gw_config_reg[7], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1041 = bits(gw_clear_reg_we_7, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_6 : UInt<1> + gw_int_pending_6 <= UInt<1>("h00") + node _T_1042 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 45:50] + node _T_1043 = eq(_T_1041, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1044 = and(gw_int_pending_6, _T_1043) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_6 = or(_T_1042, _T_1044) @[el2_pic_ctl.scala 45:72] + reg _T_1045 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1045 <= gw_int_pending_in_6 @[el2_pic_ctl.scala 46:30] + gw_int_pending_6 <= _T_1045 @[el2_pic_ctl.scala 46:20] + node _T_1046 = bits(_T_1040, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1047 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:55] + node _T_1048 = or(_T_1047, gw_int_pending_6) @[el2_pic_ctl.scala 47:78] + node _T_1049 = xor(_T_1038, _T_1039) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_7 = mux(_T_1046, _T_1048, _T_1049) @[el2_pic_ctl.scala 47:8] + node _T_1050 = bits(extintsrc_req_sync, 8, 8) @[el2_pic_ctl.scala 170:43] + node _T_1051 = bits(gw_config_reg[8], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1052 = bits(gw_config_reg[8], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1053 = bits(gw_clear_reg_we_8, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_7 : UInt<1> + gw_int_pending_7 <= UInt<1>("h00") + node _T_1054 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 45:50] + node _T_1055 = eq(_T_1053, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1056 = and(gw_int_pending_7, _T_1055) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_7 = or(_T_1054, _T_1056) @[el2_pic_ctl.scala 45:72] + reg _T_1057 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1057 <= gw_int_pending_in_7 @[el2_pic_ctl.scala 46:30] + gw_int_pending_7 <= _T_1057 @[el2_pic_ctl.scala 46:20] + node _T_1058 = bits(_T_1052, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1059 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:55] + node _T_1060 = or(_T_1059, gw_int_pending_7) @[el2_pic_ctl.scala 47:78] + node _T_1061 = xor(_T_1050, _T_1051) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_8 = mux(_T_1058, _T_1060, _T_1061) @[el2_pic_ctl.scala 47:8] + node _T_1062 = bits(extintsrc_req_sync, 9, 9) @[el2_pic_ctl.scala 170:43] + node _T_1063 = bits(gw_config_reg[9], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1064 = bits(gw_config_reg[9], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1065 = bits(gw_clear_reg_we_9, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_8 : UInt<1> + gw_int_pending_8 <= UInt<1>("h00") + node _T_1066 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 45:50] + node _T_1067 = eq(_T_1065, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1068 = and(gw_int_pending_8, _T_1067) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_8 = or(_T_1066, _T_1068) @[el2_pic_ctl.scala 45:72] + reg _T_1069 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1069 <= gw_int_pending_in_8 @[el2_pic_ctl.scala 46:30] + gw_int_pending_8 <= _T_1069 @[el2_pic_ctl.scala 46:20] + node _T_1070 = bits(_T_1064, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1071 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:55] + node _T_1072 = or(_T_1071, gw_int_pending_8) @[el2_pic_ctl.scala 47:78] + node _T_1073 = xor(_T_1062, _T_1063) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_9 = mux(_T_1070, _T_1072, _T_1073) @[el2_pic_ctl.scala 47:8] + node _T_1074 = bits(extintsrc_req_sync, 10, 10) @[el2_pic_ctl.scala 170:43] + node _T_1075 = bits(gw_config_reg[10], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1076 = bits(gw_config_reg[10], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1077 = bits(gw_clear_reg_we_10, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_9 : UInt<1> + gw_int_pending_9 <= UInt<1>("h00") + node _T_1078 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 45:50] + node _T_1079 = eq(_T_1077, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1080 = and(gw_int_pending_9, _T_1079) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_9 = or(_T_1078, _T_1080) @[el2_pic_ctl.scala 45:72] + reg _T_1081 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1081 <= gw_int_pending_in_9 @[el2_pic_ctl.scala 46:30] + gw_int_pending_9 <= _T_1081 @[el2_pic_ctl.scala 46:20] + node _T_1082 = bits(_T_1076, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1083 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:55] + node _T_1084 = or(_T_1083, gw_int_pending_9) @[el2_pic_ctl.scala 47:78] + node _T_1085 = xor(_T_1074, _T_1075) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_10 = mux(_T_1082, _T_1084, _T_1085) @[el2_pic_ctl.scala 47:8] + node _T_1086 = bits(extintsrc_req_sync, 11, 11) @[el2_pic_ctl.scala 170:43] + node _T_1087 = bits(gw_config_reg[11], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1088 = bits(gw_config_reg[11], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1089 = bits(gw_clear_reg_we_11, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_10 : UInt<1> + gw_int_pending_10 <= UInt<1>("h00") + node _T_1090 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 45:50] + node _T_1091 = eq(_T_1089, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1092 = and(gw_int_pending_10, _T_1091) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_10 = or(_T_1090, _T_1092) @[el2_pic_ctl.scala 45:72] + reg _T_1093 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1093 <= gw_int_pending_in_10 @[el2_pic_ctl.scala 46:30] + gw_int_pending_10 <= _T_1093 @[el2_pic_ctl.scala 46:20] + node _T_1094 = bits(_T_1088, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1095 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:55] + node _T_1096 = or(_T_1095, gw_int_pending_10) @[el2_pic_ctl.scala 47:78] + node _T_1097 = xor(_T_1086, _T_1087) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_11 = mux(_T_1094, _T_1096, _T_1097) @[el2_pic_ctl.scala 47:8] + node _T_1098 = bits(extintsrc_req_sync, 12, 12) @[el2_pic_ctl.scala 170:43] + node _T_1099 = bits(gw_config_reg[12], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1100 = bits(gw_config_reg[12], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1101 = bits(gw_clear_reg_we_12, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_11 : UInt<1> + gw_int_pending_11 <= UInt<1>("h00") + node _T_1102 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 45:50] + node _T_1103 = eq(_T_1101, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1104 = and(gw_int_pending_11, _T_1103) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_11 = or(_T_1102, _T_1104) @[el2_pic_ctl.scala 45:72] + reg _T_1105 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1105 <= gw_int_pending_in_11 @[el2_pic_ctl.scala 46:30] + gw_int_pending_11 <= _T_1105 @[el2_pic_ctl.scala 46:20] + node _T_1106 = bits(_T_1100, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1107 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:55] + node _T_1108 = or(_T_1107, gw_int_pending_11) @[el2_pic_ctl.scala 47:78] + node _T_1109 = xor(_T_1098, _T_1099) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_12 = mux(_T_1106, _T_1108, _T_1109) @[el2_pic_ctl.scala 47:8] + node _T_1110 = bits(extintsrc_req_sync, 13, 13) @[el2_pic_ctl.scala 170:43] + node _T_1111 = bits(gw_config_reg[13], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1112 = bits(gw_config_reg[13], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1113 = bits(gw_clear_reg_we_13, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_12 : UInt<1> + gw_int_pending_12 <= UInt<1>("h00") + node _T_1114 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 45:50] + node _T_1115 = eq(_T_1113, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1116 = and(gw_int_pending_12, _T_1115) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_12 = or(_T_1114, _T_1116) @[el2_pic_ctl.scala 45:72] + reg _T_1117 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1117 <= gw_int_pending_in_12 @[el2_pic_ctl.scala 46:30] + gw_int_pending_12 <= _T_1117 @[el2_pic_ctl.scala 46:20] + node _T_1118 = bits(_T_1112, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1119 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:55] + node _T_1120 = or(_T_1119, gw_int_pending_12) @[el2_pic_ctl.scala 47:78] + node _T_1121 = xor(_T_1110, _T_1111) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_13 = mux(_T_1118, _T_1120, _T_1121) @[el2_pic_ctl.scala 47:8] + node _T_1122 = bits(extintsrc_req_sync, 14, 14) @[el2_pic_ctl.scala 170:43] + node _T_1123 = bits(gw_config_reg[14], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1124 = bits(gw_config_reg[14], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1125 = bits(gw_clear_reg_we_14, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_13 : UInt<1> + gw_int_pending_13 <= UInt<1>("h00") + node _T_1126 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 45:50] + node _T_1127 = eq(_T_1125, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1128 = and(gw_int_pending_13, _T_1127) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_13 = or(_T_1126, _T_1128) @[el2_pic_ctl.scala 45:72] + reg _T_1129 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1129 <= gw_int_pending_in_13 @[el2_pic_ctl.scala 46:30] + gw_int_pending_13 <= _T_1129 @[el2_pic_ctl.scala 46:20] + node _T_1130 = bits(_T_1124, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1131 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:55] + node _T_1132 = or(_T_1131, gw_int_pending_13) @[el2_pic_ctl.scala 47:78] + node _T_1133 = xor(_T_1122, _T_1123) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_14 = mux(_T_1130, _T_1132, _T_1133) @[el2_pic_ctl.scala 47:8] + node _T_1134 = bits(extintsrc_req_sync, 15, 15) @[el2_pic_ctl.scala 170:43] + node _T_1135 = bits(gw_config_reg[15], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1136 = bits(gw_config_reg[15], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1137 = bits(gw_clear_reg_we_15, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_14 : UInt<1> + gw_int_pending_14 <= UInt<1>("h00") + node _T_1138 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 45:50] + node _T_1139 = eq(_T_1137, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1140 = and(gw_int_pending_14, _T_1139) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_14 = or(_T_1138, _T_1140) @[el2_pic_ctl.scala 45:72] + reg _T_1141 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1141 <= gw_int_pending_in_14 @[el2_pic_ctl.scala 46:30] + gw_int_pending_14 <= _T_1141 @[el2_pic_ctl.scala 46:20] + node _T_1142 = bits(_T_1136, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1143 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:55] + node _T_1144 = or(_T_1143, gw_int_pending_14) @[el2_pic_ctl.scala 47:78] + node _T_1145 = xor(_T_1134, _T_1135) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_15 = mux(_T_1142, _T_1144, _T_1145) @[el2_pic_ctl.scala 47:8] + node _T_1146 = bits(extintsrc_req_sync, 16, 16) @[el2_pic_ctl.scala 170:43] + node _T_1147 = bits(gw_config_reg[16], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1148 = bits(gw_config_reg[16], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1149 = bits(gw_clear_reg_we_16, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_15 : UInt<1> + gw_int_pending_15 <= UInt<1>("h00") + node _T_1150 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 45:50] + node _T_1151 = eq(_T_1149, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1152 = and(gw_int_pending_15, _T_1151) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_15 = or(_T_1150, _T_1152) @[el2_pic_ctl.scala 45:72] + reg _T_1153 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1153 <= gw_int_pending_in_15 @[el2_pic_ctl.scala 46:30] + gw_int_pending_15 <= _T_1153 @[el2_pic_ctl.scala 46:20] + node _T_1154 = bits(_T_1148, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1155 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:55] + node _T_1156 = or(_T_1155, gw_int_pending_15) @[el2_pic_ctl.scala 47:78] + node _T_1157 = xor(_T_1146, _T_1147) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_16 = mux(_T_1154, _T_1156, _T_1157) @[el2_pic_ctl.scala 47:8] + node _T_1158 = bits(extintsrc_req_sync, 17, 17) @[el2_pic_ctl.scala 170:43] + node _T_1159 = bits(gw_config_reg[17], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1160 = bits(gw_config_reg[17], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1161 = bits(gw_clear_reg_we_17, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_16 : UInt<1> + gw_int_pending_16 <= UInt<1>("h00") + node _T_1162 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 45:50] + node _T_1163 = eq(_T_1161, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1164 = and(gw_int_pending_16, _T_1163) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_16 = or(_T_1162, _T_1164) @[el2_pic_ctl.scala 45:72] + reg _T_1165 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1165 <= gw_int_pending_in_16 @[el2_pic_ctl.scala 46:30] + gw_int_pending_16 <= _T_1165 @[el2_pic_ctl.scala 46:20] + node _T_1166 = bits(_T_1160, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1167 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:55] + node _T_1168 = or(_T_1167, gw_int_pending_16) @[el2_pic_ctl.scala 47:78] + node _T_1169 = xor(_T_1158, _T_1159) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_17 = mux(_T_1166, _T_1168, _T_1169) @[el2_pic_ctl.scala 47:8] + node _T_1170 = bits(extintsrc_req_sync, 18, 18) @[el2_pic_ctl.scala 170:43] + node _T_1171 = bits(gw_config_reg[18], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1172 = bits(gw_config_reg[18], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1173 = bits(gw_clear_reg_we_18, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_17 : UInt<1> + gw_int_pending_17 <= UInt<1>("h00") + node _T_1174 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 45:50] + node _T_1175 = eq(_T_1173, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1176 = and(gw_int_pending_17, _T_1175) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_17 = or(_T_1174, _T_1176) @[el2_pic_ctl.scala 45:72] + reg _T_1177 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1177 <= gw_int_pending_in_17 @[el2_pic_ctl.scala 46:30] + gw_int_pending_17 <= _T_1177 @[el2_pic_ctl.scala 46:20] + node _T_1178 = bits(_T_1172, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1179 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:55] + node _T_1180 = or(_T_1179, gw_int_pending_17) @[el2_pic_ctl.scala 47:78] + node _T_1181 = xor(_T_1170, _T_1171) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_18 = mux(_T_1178, _T_1180, _T_1181) @[el2_pic_ctl.scala 47:8] + node _T_1182 = bits(extintsrc_req_sync, 19, 19) @[el2_pic_ctl.scala 170:43] + node _T_1183 = bits(gw_config_reg[19], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1184 = bits(gw_config_reg[19], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1185 = bits(gw_clear_reg_we_19, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_18 : UInt<1> + gw_int_pending_18 <= UInt<1>("h00") + node _T_1186 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 45:50] + node _T_1187 = eq(_T_1185, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1188 = and(gw_int_pending_18, _T_1187) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_18 = or(_T_1186, _T_1188) @[el2_pic_ctl.scala 45:72] + reg _T_1189 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1189 <= gw_int_pending_in_18 @[el2_pic_ctl.scala 46:30] + gw_int_pending_18 <= _T_1189 @[el2_pic_ctl.scala 46:20] + node _T_1190 = bits(_T_1184, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1191 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:55] + node _T_1192 = or(_T_1191, gw_int_pending_18) @[el2_pic_ctl.scala 47:78] + node _T_1193 = xor(_T_1182, _T_1183) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_19 = mux(_T_1190, _T_1192, _T_1193) @[el2_pic_ctl.scala 47:8] + node _T_1194 = bits(extintsrc_req_sync, 20, 20) @[el2_pic_ctl.scala 170:43] + node _T_1195 = bits(gw_config_reg[20], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1196 = bits(gw_config_reg[20], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1197 = bits(gw_clear_reg_we_20, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_19 : UInt<1> + gw_int_pending_19 <= UInt<1>("h00") + node _T_1198 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 45:50] + node _T_1199 = eq(_T_1197, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1200 = and(gw_int_pending_19, _T_1199) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_19 = or(_T_1198, _T_1200) @[el2_pic_ctl.scala 45:72] + reg _T_1201 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1201 <= gw_int_pending_in_19 @[el2_pic_ctl.scala 46:30] + gw_int_pending_19 <= _T_1201 @[el2_pic_ctl.scala 46:20] + node _T_1202 = bits(_T_1196, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1203 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:55] + node _T_1204 = or(_T_1203, gw_int_pending_19) @[el2_pic_ctl.scala 47:78] + node _T_1205 = xor(_T_1194, _T_1195) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_20 = mux(_T_1202, _T_1204, _T_1205) @[el2_pic_ctl.scala 47:8] + node _T_1206 = bits(extintsrc_req_sync, 21, 21) @[el2_pic_ctl.scala 170:43] + node _T_1207 = bits(gw_config_reg[21], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1208 = bits(gw_config_reg[21], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1209 = bits(gw_clear_reg_we_21, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_20 : UInt<1> + gw_int_pending_20 <= UInt<1>("h00") + node _T_1210 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 45:50] + node _T_1211 = eq(_T_1209, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1212 = and(gw_int_pending_20, _T_1211) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_20 = or(_T_1210, _T_1212) @[el2_pic_ctl.scala 45:72] + reg _T_1213 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1213 <= gw_int_pending_in_20 @[el2_pic_ctl.scala 46:30] + gw_int_pending_20 <= _T_1213 @[el2_pic_ctl.scala 46:20] + node _T_1214 = bits(_T_1208, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1215 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:55] + node _T_1216 = or(_T_1215, gw_int_pending_20) @[el2_pic_ctl.scala 47:78] + node _T_1217 = xor(_T_1206, _T_1207) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_21 = mux(_T_1214, _T_1216, _T_1217) @[el2_pic_ctl.scala 47:8] + node _T_1218 = bits(extintsrc_req_sync, 22, 22) @[el2_pic_ctl.scala 170:43] + node _T_1219 = bits(gw_config_reg[22], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1220 = bits(gw_config_reg[22], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1221 = bits(gw_clear_reg_we_22, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_21 : UInt<1> + gw_int_pending_21 <= UInt<1>("h00") + node _T_1222 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 45:50] + node _T_1223 = eq(_T_1221, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1224 = and(gw_int_pending_21, _T_1223) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_21 = or(_T_1222, _T_1224) @[el2_pic_ctl.scala 45:72] + reg _T_1225 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1225 <= gw_int_pending_in_21 @[el2_pic_ctl.scala 46:30] + gw_int_pending_21 <= _T_1225 @[el2_pic_ctl.scala 46:20] + node _T_1226 = bits(_T_1220, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1227 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:55] + node _T_1228 = or(_T_1227, gw_int_pending_21) @[el2_pic_ctl.scala 47:78] + node _T_1229 = xor(_T_1218, _T_1219) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_22 = mux(_T_1226, _T_1228, _T_1229) @[el2_pic_ctl.scala 47:8] + node _T_1230 = bits(extintsrc_req_sync, 23, 23) @[el2_pic_ctl.scala 170:43] + node _T_1231 = bits(gw_config_reg[23], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1232 = bits(gw_config_reg[23], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1233 = bits(gw_clear_reg_we_23, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_22 : UInt<1> + gw_int_pending_22 <= UInt<1>("h00") + node _T_1234 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 45:50] + node _T_1235 = eq(_T_1233, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1236 = and(gw_int_pending_22, _T_1235) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_22 = or(_T_1234, _T_1236) @[el2_pic_ctl.scala 45:72] + reg _T_1237 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1237 <= gw_int_pending_in_22 @[el2_pic_ctl.scala 46:30] + gw_int_pending_22 <= _T_1237 @[el2_pic_ctl.scala 46:20] + node _T_1238 = bits(_T_1232, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1239 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:55] + node _T_1240 = or(_T_1239, gw_int_pending_22) @[el2_pic_ctl.scala 47:78] + node _T_1241 = xor(_T_1230, _T_1231) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_23 = mux(_T_1238, _T_1240, _T_1241) @[el2_pic_ctl.scala 47:8] + node _T_1242 = bits(extintsrc_req_sync, 24, 24) @[el2_pic_ctl.scala 170:43] + node _T_1243 = bits(gw_config_reg[24], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1244 = bits(gw_config_reg[24], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1245 = bits(gw_clear_reg_we_24, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_23 : UInt<1> + gw_int_pending_23 <= UInt<1>("h00") + node _T_1246 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 45:50] + node _T_1247 = eq(_T_1245, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1248 = and(gw_int_pending_23, _T_1247) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_23 = or(_T_1246, _T_1248) @[el2_pic_ctl.scala 45:72] + reg _T_1249 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1249 <= gw_int_pending_in_23 @[el2_pic_ctl.scala 46:30] + gw_int_pending_23 <= _T_1249 @[el2_pic_ctl.scala 46:20] + node _T_1250 = bits(_T_1244, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1251 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:55] + node _T_1252 = or(_T_1251, gw_int_pending_23) @[el2_pic_ctl.scala 47:78] + node _T_1253 = xor(_T_1242, _T_1243) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_24 = mux(_T_1250, _T_1252, _T_1253) @[el2_pic_ctl.scala 47:8] + node _T_1254 = bits(extintsrc_req_sync, 25, 25) @[el2_pic_ctl.scala 170:43] + node _T_1255 = bits(gw_config_reg[25], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1256 = bits(gw_config_reg[25], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1257 = bits(gw_clear_reg_we_25, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_24 : UInt<1> + gw_int_pending_24 <= UInt<1>("h00") + node _T_1258 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 45:50] + node _T_1259 = eq(_T_1257, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1260 = and(gw_int_pending_24, _T_1259) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_24 = or(_T_1258, _T_1260) @[el2_pic_ctl.scala 45:72] + reg _T_1261 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1261 <= gw_int_pending_in_24 @[el2_pic_ctl.scala 46:30] + gw_int_pending_24 <= _T_1261 @[el2_pic_ctl.scala 46:20] + node _T_1262 = bits(_T_1256, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1263 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:55] + node _T_1264 = or(_T_1263, gw_int_pending_24) @[el2_pic_ctl.scala 47:78] + node _T_1265 = xor(_T_1254, _T_1255) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_25 = mux(_T_1262, _T_1264, _T_1265) @[el2_pic_ctl.scala 47:8] + node _T_1266 = bits(extintsrc_req_sync, 26, 26) @[el2_pic_ctl.scala 170:43] + node _T_1267 = bits(gw_config_reg[26], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1268 = bits(gw_config_reg[26], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1269 = bits(gw_clear_reg_we_26, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_25 : UInt<1> + gw_int_pending_25 <= UInt<1>("h00") + node _T_1270 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 45:50] + node _T_1271 = eq(_T_1269, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1272 = and(gw_int_pending_25, _T_1271) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_25 = or(_T_1270, _T_1272) @[el2_pic_ctl.scala 45:72] + reg _T_1273 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1273 <= gw_int_pending_in_25 @[el2_pic_ctl.scala 46:30] + gw_int_pending_25 <= _T_1273 @[el2_pic_ctl.scala 46:20] + node _T_1274 = bits(_T_1268, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1275 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:55] + node _T_1276 = or(_T_1275, gw_int_pending_25) @[el2_pic_ctl.scala 47:78] + node _T_1277 = xor(_T_1266, _T_1267) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_26 = mux(_T_1274, _T_1276, _T_1277) @[el2_pic_ctl.scala 47:8] + node _T_1278 = bits(extintsrc_req_sync, 27, 27) @[el2_pic_ctl.scala 170:43] + node _T_1279 = bits(gw_config_reg[27], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1280 = bits(gw_config_reg[27], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1281 = bits(gw_clear_reg_we_27, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_26 : UInt<1> + gw_int_pending_26 <= UInt<1>("h00") + node _T_1282 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 45:50] + node _T_1283 = eq(_T_1281, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1284 = and(gw_int_pending_26, _T_1283) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_26 = or(_T_1282, _T_1284) @[el2_pic_ctl.scala 45:72] + reg _T_1285 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1285 <= gw_int_pending_in_26 @[el2_pic_ctl.scala 46:30] + gw_int_pending_26 <= _T_1285 @[el2_pic_ctl.scala 46:20] + node _T_1286 = bits(_T_1280, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1287 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:55] + node _T_1288 = or(_T_1287, gw_int_pending_26) @[el2_pic_ctl.scala 47:78] + node _T_1289 = xor(_T_1278, _T_1279) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_27 = mux(_T_1286, _T_1288, _T_1289) @[el2_pic_ctl.scala 47:8] + node _T_1290 = bits(extintsrc_req_sync, 28, 28) @[el2_pic_ctl.scala 170:43] + node _T_1291 = bits(gw_config_reg[28], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1292 = bits(gw_config_reg[28], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1293 = bits(gw_clear_reg_we_28, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_27 : UInt<1> + gw_int_pending_27 <= UInt<1>("h00") + node _T_1294 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 45:50] + node _T_1295 = eq(_T_1293, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1296 = and(gw_int_pending_27, _T_1295) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_27 = or(_T_1294, _T_1296) @[el2_pic_ctl.scala 45:72] + reg _T_1297 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1297 <= gw_int_pending_in_27 @[el2_pic_ctl.scala 46:30] + gw_int_pending_27 <= _T_1297 @[el2_pic_ctl.scala 46:20] + node _T_1298 = bits(_T_1292, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1299 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:55] + node _T_1300 = or(_T_1299, gw_int_pending_27) @[el2_pic_ctl.scala 47:78] + node _T_1301 = xor(_T_1290, _T_1291) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_28 = mux(_T_1298, _T_1300, _T_1301) @[el2_pic_ctl.scala 47:8] + node _T_1302 = bits(extintsrc_req_sync, 29, 29) @[el2_pic_ctl.scala 170:43] + node _T_1303 = bits(gw_config_reg[29], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1304 = bits(gw_config_reg[29], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1305 = bits(gw_clear_reg_we_29, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_28 : UInt<1> + gw_int_pending_28 <= UInt<1>("h00") + node _T_1306 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 45:50] + node _T_1307 = eq(_T_1305, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1308 = and(gw_int_pending_28, _T_1307) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_28 = or(_T_1306, _T_1308) @[el2_pic_ctl.scala 45:72] + reg _T_1309 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1309 <= gw_int_pending_in_28 @[el2_pic_ctl.scala 46:30] + gw_int_pending_28 <= _T_1309 @[el2_pic_ctl.scala 46:20] + node _T_1310 = bits(_T_1304, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1311 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:55] + node _T_1312 = or(_T_1311, gw_int_pending_28) @[el2_pic_ctl.scala 47:78] + node _T_1313 = xor(_T_1302, _T_1303) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_29 = mux(_T_1310, _T_1312, _T_1313) @[el2_pic_ctl.scala 47:8] + node _T_1314 = bits(extintsrc_req_sync, 30, 30) @[el2_pic_ctl.scala 170:43] + node _T_1315 = bits(gw_config_reg[30], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1316 = bits(gw_config_reg[30], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1317 = bits(gw_clear_reg_we_30, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_29 : UInt<1> + gw_int_pending_29 <= UInt<1>("h00") + node _T_1318 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 45:50] + node _T_1319 = eq(_T_1317, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1320 = and(gw_int_pending_29, _T_1319) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_29 = or(_T_1318, _T_1320) @[el2_pic_ctl.scala 45:72] + reg _T_1321 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1321 <= gw_int_pending_in_29 @[el2_pic_ctl.scala 46:30] + gw_int_pending_29 <= _T_1321 @[el2_pic_ctl.scala 46:20] + node _T_1322 = bits(_T_1316, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1323 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:55] + node _T_1324 = or(_T_1323, gw_int_pending_29) @[el2_pic_ctl.scala 47:78] + node _T_1325 = xor(_T_1314, _T_1315) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_30 = mux(_T_1322, _T_1324, _T_1325) @[el2_pic_ctl.scala 47:8] + node _T_1326 = bits(extintsrc_req_sync, 31, 31) @[el2_pic_ctl.scala 170:43] + node _T_1327 = bits(gw_config_reg[31], 0, 0) @[el2_pic_ctl.scala 170:64] + node _T_1328 = bits(gw_config_reg[31], 1, 1) @[el2_pic_ctl.scala 170:85] + node _T_1329 = bits(gw_clear_reg_we_31, 0, 0) @[el2_pic_ctl.scala 170:115] + wire gw_int_pending_30 : UInt<1> + gw_int_pending_30 <= UInt<1>("h00") + node _T_1330 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 45:50] + node _T_1331 = eq(_T_1329, UInt<1>("h00")) @[el2_pic_ctl.scala 45:92] + node _T_1332 = and(gw_int_pending_30, _T_1331) @[el2_pic_ctl.scala 45:90] + node gw_int_pending_in_30 = or(_T_1330, _T_1332) @[el2_pic_ctl.scala 45:72] + reg _T_1333 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 46:30] + _T_1333 <= gw_int_pending_in_30 @[el2_pic_ctl.scala 46:30] + gw_int_pending_30 <= _T_1333 @[el2_pic_ctl.scala 46:20] + node _T_1334 = bits(_T_1328, 0, 0) @[el2_pic_ctl.scala 47:30] + node _T_1335 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:55] + node _T_1336 = or(_T_1335, gw_int_pending_30) @[el2_pic_ctl.scala 47:78] + node _T_1337 = xor(_T_1326, _T_1327) @[el2_pic_ctl.scala 47:117] + node extintsrc_req_gw_31 = mux(_T_1334, _T_1336, _T_1337) @[el2_pic_ctl.scala 47:8] + node _T_1338 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1339 = not(intpriority_reg[0]) @[el2_pic_ctl.scala 174:89] + node _T_1340 = mux(_T_1338, _T_1339, intpriority_reg[0]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[0] <= _T_1340 @[el2_pic_ctl.scala 174:64] + node _T_1341 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1342 = not(intpriority_reg[1]) @[el2_pic_ctl.scala 174:89] + node _T_1343 = mux(_T_1341, _T_1342, intpriority_reg[1]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[1] <= _T_1343 @[el2_pic_ctl.scala 174:64] + node _T_1344 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1345 = not(intpriority_reg[2]) @[el2_pic_ctl.scala 174:89] + node _T_1346 = mux(_T_1344, _T_1345, intpriority_reg[2]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[2] <= _T_1346 @[el2_pic_ctl.scala 174:64] + node _T_1347 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1348 = not(intpriority_reg[3]) @[el2_pic_ctl.scala 174:89] + node _T_1349 = mux(_T_1347, _T_1348, intpriority_reg[3]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[3] <= _T_1349 @[el2_pic_ctl.scala 174:64] + node _T_1350 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1351 = not(intpriority_reg[4]) @[el2_pic_ctl.scala 174:89] + node _T_1352 = mux(_T_1350, _T_1351, intpriority_reg[4]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[4] <= _T_1352 @[el2_pic_ctl.scala 174:64] + node _T_1353 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1354 = not(intpriority_reg[5]) @[el2_pic_ctl.scala 174:89] + node _T_1355 = mux(_T_1353, _T_1354, intpriority_reg[5]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[5] <= _T_1355 @[el2_pic_ctl.scala 174:64] + node _T_1356 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1357 = not(intpriority_reg[6]) @[el2_pic_ctl.scala 174:89] + node _T_1358 = mux(_T_1356, _T_1357, intpriority_reg[6]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[6] <= _T_1358 @[el2_pic_ctl.scala 174:64] + node _T_1359 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1360 = not(intpriority_reg[7]) @[el2_pic_ctl.scala 174:89] + node _T_1361 = mux(_T_1359, _T_1360, intpriority_reg[7]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[7] <= _T_1361 @[el2_pic_ctl.scala 174:64] + node _T_1362 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1363 = not(intpriority_reg[8]) @[el2_pic_ctl.scala 174:89] + node _T_1364 = mux(_T_1362, _T_1363, intpriority_reg[8]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[8] <= _T_1364 @[el2_pic_ctl.scala 174:64] + node _T_1365 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1366 = not(intpriority_reg[9]) @[el2_pic_ctl.scala 174:89] + node _T_1367 = mux(_T_1365, _T_1366, intpriority_reg[9]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[9] <= _T_1367 @[el2_pic_ctl.scala 174:64] + node _T_1368 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1369 = not(intpriority_reg[10]) @[el2_pic_ctl.scala 174:89] + node _T_1370 = mux(_T_1368, _T_1369, intpriority_reg[10]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[10] <= _T_1370 @[el2_pic_ctl.scala 174:64] + node _T_1371 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1372 = not(intpriority_reg[11]) @[el2_pic_ctl.scala 174:89] + node _T_1373 = mux(_T_1371, _T_1372, intpriority_reg[11]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[11] <= _T_1373 @[el2_pic_ctl.scala 174:64] + node _T_1374 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1375 = not(intpriority_reg[12]) @[el2_pic_ctl.scala 174:89] + node _T_1376 = mux(_T_1374, _T_1375, intpriority_reg[12]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[12] <= _T_1376 @[el2_pic_ctl.scala 174:64] + node _T_1377 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1378 = not(intpriority_reg[13]) @[el2_pic_ctl.scala 174:89] + node _T_1379 = mux(_T_1377, _T_1378, intpriority_reg[13]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[13] <= _T_1379 @[el2_pic_ctl.scala 174:64] + node _T_1380 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1381 = not(intpriority_reg[14]) @[el2_pic_ctl.scala 174:89] + node _T_1382 = mux(_T_1380, _T_1381, intpriority_reg[14]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[14] <= _T_1382 @[el2_pic_ctl.scala 174:64] + node _T_1383 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1384 = not(intpriority_reg[15]) @[el2_pic_ctl.scala 174:89] + node _T_1385 = mux(_T_1383, _T_1384, intpriority_reg[15]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[15] <= _T_1385 @[el2_pic_ctl.scala 174:64] + node _T_1386 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1387 = not(intpriority_reg[16]) @[el2_pic_ctl.scala 174:89] + node _T_1388 = mux(_T_1386, _T_1387, intpriority_reg[16]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[16] <= _T_1388 @[el2_pic_ctl.scala 174:64] + node _T_1389 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1390 = not(intpriority_reg[17]) @[el2_pic_ctl.scala 174:89] + node _T_1391 = mux(_T_1389, _T_1390, intpriority_reg[17]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[17] <= _T_1391 @[el2_pic_ctl.scala 174:64] + node _T_1392 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1393 = not(intpriority_reg[18]) @[el2_pic_ctl.scala 174:89] + node _T_1394 = mux(_T_1392, _T_1393, intpriority_reg[18]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[18] <= _T_1394 @[el2_pic_ctl.scala 174:64] + node _T_1395 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1396 = not(intpriority_reg[19]) @[el2_pic_ctl.scala 174:89] + node _T_1397 = mux(_T_1395, _T_1396, intpriority_reg[19]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[19] <= _T_1397 @[el2_pic_ctl.scala 174:64] + node _T_1398 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1399 = not(intpriority_reg[20]) @[el2_pic_ctl.scala 174:89] + node _T_1400 = mux(_T_1398, _T_1399, intpriority_reg[20]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[20] <= _T_1400 @[el2_pic_ctl.scala 174:64] + node _T_1401 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1402 = not(intpriority_reg[21]) @[el2_pic_ctl.scala 174:89] + node _T_1403 = mux(_T_1401, _T_1402, intpriority_reg[21]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[21] <= _T_1403 @[el2_pic_ctl.scala 174:64] + node _T_1404 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1405 = not(intpriority_reg[22]) @[el2_pic_ctl.scala 174:89] + node _T_1406 = mux(_T_1404, _T_1405, intpriority_reg[22]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[22] <= _T_1406 @[el2_pic_ctl.scala 174:64] + node _T_1407 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1408 = not(intpriority_reg[23]) @[el2_pic_ctl.scala 174:89] + node _T_1409 = mux(_T_1407, _T_1408, intpriority_reg[23]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[23] <= _T_1409 @[el2_pic_ctl.scala 174:64] + node _T_1410 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1411 = not(intpriority_reg[24]) @[el2_pic_ctl.scala 174:89] + node _T_1412 = mux(_T_1410, _T_1411, intpriority_reg[24]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[24] <= _T_1412 @[el2_pic_ctl.scala 174:64] + node _T_1413 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1414 = not(intpriority_reg[25]) @[el2_pic_ctl.scala 174:89] + node _T_1415 = mux(_T_1413, _T_1414, intpriority_reg[25]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[25] <= _T_1415 @[el2_pic_ctl.scala 174:64] + node _T_1416 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1417 = not(intpriority_reg[26]) @[el2_pic_ctl.scala 174:89] + node _T_1418 = mux(_T_1416, _T_1417, intpriority_reg[26]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[26] <= _T_1418 @[el2_pic_ctl.scala 174:64] + node _T_1419 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1420 = not(intpriority_reg[27]) @[el2_pic_ctl.scala 174:89] + node _T_1421 = mux(_T_1419, _T_1420, intpriority_reg[27]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[27] <= _T_1421 @[el2_pic_ctl.scala 174:64] + node _T_1422 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1423 = not(intpriority_reg[28]) @[el2_pic_ctl.scala 174:89] + node _T_1424 = mux(_T_1422, _T_1423, intpriority_reg[28]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[28] <= _T_1424 @[el2_pic_ctl.scala 174:64] + node _T_1425 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1426 = not(intpriority_reg[29]) @[el2_pic_ctl.scala 174:89] + node _T_1427 = mux(_T_1425, _T_1426, intpriority_reg[29]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[29] <= _T_1427 @[el2_pic_ctl.scala 174:64] + node _T_1428 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1429 = not(intpriority_reg[30]) @[el2_pic_ctl.scala 174:89] + node _T_1430 = mux(_T_1428, _T_1429, intpriority_reg[30]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[30] <= _T_1430 @[el2_pic_ctl.scala 174:64] + node _T_1431 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 174:81] + node _T_1432 = not(intpriority_reg[31]) @[el2_pic_ctl.scala 174:89] + node _T_1433 = mux(_T_1431, _T_1432, intpriority_reg[31]) @[el2_pic_ctl.scala 174:70] + intpriority_reg_inv[31] <= _T_1433 @[el2_pic_ctl.scala 174:64] + node _T_1434 = and(UInt<1>("h00"), intenable_reg[0]) @[el2_pic_ctl.scala 175:109] + node _T_1435 = bits(_T_1434, 0, 0) @[Bitwise.scala 72:15] + node _T_1436 = mux(_T_1435, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1437 = and(_T_1436, intpriority_reg_inv[0]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[0] <= _T_1437 @[el2_pic_ctl.scala 175:63] + node _T_1438 = and(extintsrc_req_gw_1, intenable_reg[1]) @[el2_pic_ctl.scala 175:109] + node _T_1439 = bits(_T_1438, 0, 0) @[Bitwise.scala 72:15] + node _T_1440 = mux(_T_1439, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1441 = and(_T_1440, intpriority_reg_inv[1]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[1] <= _T_1441 @[el2_pic_ctl.scala 175:63] + node _T_1442 = and(extintsrc_req_gw_2, intenable_reg[2]) @[el2_pic_ctl.scala 175:109] + node _T_1443 = bits(_T_1442, 0, 0) @[Bitwise.scala 72:15] + node _T_1444 = mux(_T_1443, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1445 = and(_T_1444, intpriority_reg_inv[2]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[2] <= _T_1445 @[el2_pic_ctl.scala 175:63] + node _T_1446 = and(extintsrc_req_gw_3, intenable_reg[3]) @[el2_pic_ctl.scala 175:109] + node _T_1447 = bits(_T_1446, 0, 0) @[Bitwise.scala 72:15] + node _T_1448 = mux(_T_1447, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1449 = and(_T_1448, intpriority_reg_inv[3]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[3] <= _T_1449 @[el2_pic_ctl.scala 175:63] + node _T_1450 = and(extintsrc_req_gw_4, intenable_reg[4]) @[el2_pic_ctl.scala 175:109] + node _T_1451 = bits(_T_1450, 0, 0) @[Bitwise.scala 72:15] + node _T_1452 = mux(_T_1451, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1453 = and(_T_1452, intpriority_reg_inv[4]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[4] <= _T_1453 @[el2_pic_ctl.scala 175:63] + node _T_1454 = and(extintsrc_req_gw_5, intenable_reg[5]) @[el2_pic_ctl.scala 175:109] + node _T_1455 = bits(_T_1454, 0, 0) @[Bitwise.scala 72:15] + node _T_1456 = mux(_T_1455, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1457 = and(_T_1456, intpriority_reg_inv[5]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[5] <= _T_1457 @[el2_pic_ctl.scala 175:63] + node _T_1458 = and(extintsrc_req_gw_6, intenable_reg[6]) @[el2_pic_ctl.scala 175:109] + node _T_1459 = bits(_T_1458, 0, 0) @[Bitwise.scala 72:15] + node _T_1460 = mux(_T_1459, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1461 = and(_T_1460, intpriority_reg_inv[6]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[6] <= _T_1461 @[el2_pic_ctl.scala 175:63] + node _T_1462 = and(extintsrc_req_gw_7, intenable_reg[7]) @[el2_pic_ctl.scala 175:109] + node _T_1463 = bits(_T_1462, 0, 0) @[Bitwise.scala 72:15] + node _T_1464 = mux(_T_1463, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1465 = and(_T_1464, intpriority_reg_inv[7]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[7] <= _T_1465 @[el2_pic_ctl.scala 175:63] + node _T_1466 = and(extintsrc_req_gw_8, intenable_reg[8]) @[el2_pic_ctl.scala 175:109] + node _T_1467 = bits(_T_1466, 0, 0) @[Bitwise.scala 72:15] + node _T_1468 = mux(_T_1467, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1469 = and(_T_1468, intpriority_reg_inv[8]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[8] <= _T_1469 @[el2_pic_ctl.scala 175:63] + node _T_1470 = and(extintsrc_req_gw_9, intenable_reg[9]) @[el2_pic_ctl.scala 175:109] + node _T_1471 = bits(_T_1470, 0, 0) @[Bitwise.scala 72:15] + node _T_1472 = mux(_T_1471, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1473 = and(_T_1472, intpriority_reg_inv[9]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[9] <= _T_1473 @[el2_pic_ctl.scala 175:63] + node _T_1474 = and(extintsrc_req_gw_10, intenable_reg[10]) @[el2_pic_ctl.scala 175:109] + node _T_1475 = bits(_T_1474, 0, 0) @[Bitwise.scala 72:15] + node _T_1476 = mux(_T_1475, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1477 = and(_T_1476, intpriority_reg_inv[10]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[10] <= _T_1477 @[el2_pic_ctl.scala 175:63] + node _T_1478 = and(extintsrc_req_gw_11, intenable_reg[11]) @[el2_pic_ctl.scala 175:109] + node _T_1479 = bits(_T_1478, 0, 0) @[Bitwise.scala 72:15] + node _T_1480 = mux(_T_1479, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1481 = and(_T_1480, intpriority_reg_inv[11]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[11] <= _T_1481 @[el2_pic_ctl.scala 175:63] + node _T_1482 = and(extintsrc_req_gw_12, intenable_reg[12]) @[el2_pic_ctl.scala 175:109] + node _T_1483 = bits(_T_1482, 0, 0) @[Bitwise.scala 72:15] + node _T_1484 = mux(_T_1483, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1485 = and(_T_1484, intpriority_reg_inv[12]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[12] <= _T_1485 @[el2_pic_ctl.scala 175:63] + node _T_1486 = and(extintsrc_req_gw_13, intenable_reg[13]) @[el2_pic_ctl.scala 175:109] + node _T_1487 = bits(_T_1486, 0, 0) @[Bitwise.scala 72:15] + node _T_1488 = mux(_T_1487, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1489 = and(_T_1488, intpriority_reg_inv[13]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[13] <= _T_1489 @[el2_pic_ctl.scala 175:63] + node _T_1490 = and(extintsrc_req_gw_14, intenable_reg[14]) @[el2_pic_ctl.scala 175:109] + node _T_1491 = bits(_T_1490, 0, 0) @[Bitwise.scala 72:15] + node _T_1492 = mux(_T_1491, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1493 = and(_T_1492, intpriority_reg_inv[14]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[14] <= _T_1493 @[el2_pic_ctl.scala 175:63] + node _T_1494 = and(extintsrc_req_gw_15, intenable_reg[15]) @[el2_pic_ctl.scala 175:109] + node _T_1495 = bits(_T_1494, 0, 0) @[Bitwise.scala 72:15] + node _T_1496 = mux(_T_1495, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1497 = and(_T_1496, intpriority_reg_inv[15]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[15] <= _T_1497 @[el2_pic_ctl.scala 175:63] + node _T_1498 = and(extintsrc_req_gw_16, intenable_reg[16]) @[el2_pic_ctl.scala 175:109] + node _T_1499 = bits(_T_1498, 0, 0) @[Bitwise.scala 72:15] + node _T_1500 = mux(_T_1499, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1501 = and(_T_1500, intpriority_reg_inv[16]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[16] <= _T_1501 @[el2_pic_ctl.scala 175:63] + node _T_1502 = and(extintsrc_req_gw_17, intenable_reg[17]) @[el2_pic_ctl.scala 175:109] + node _T_1503 = bits(_T_1502, 0, 0) @[Bitwise.scala 72:15] + node _T_1504 = mux(_T_1503, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1505 = and(_T_1504, intpriority_reg_inv[17]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[17] <= _T_1505 @[el2_pic_ctl.scala 175:63] + node _T_1506 = and(extintsrc_req_gw_18, intenable_reg[18]) @[el2_pic_ctl.scala 175:109] + node _T_1507 = bits(_T_1506, 0, 0) @[Bitwise.scala 72:15] + node _T_1508 = mux(_T_1507, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1509 = and(_T_1508, intpriority_reg_inv[18]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[18] <= _T_1509 @[el2_pic_ctl.scala 175:63] + node _T_1510 = and(extintsrc_req_gw_19, intenable_reg[19]) @[el2_pic_ctl.scala 175:109] + node _T_1511 = bits(_T_1510, 0, 0) @[Bitwise.scala 72:15] + node _T_1512 = mux(_T_1511, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1513 = and(_T_1512, intpriority_reg_inv[19]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[19] <= _T_1513 @[el2_pic_ctl.scala 175:63] + node _T_1514 = and(extintsrc_req_gw_20, intenable_reg[20]) @[el2_pic_ctl.scala 175:109] + node _T_1515 = bits(_T_1514, 0, 0) @[Bitwise.scala 72:15] + node _T_1516 = mux(_T_1515, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1517 = and(_T_1516, intpriority_reg_inv[20]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[20] <= _T_1517 @[el2_pic_ctl.scala 175:63] + node _T_1518 = and(extintsrc_req_gw_21, intenable_reg[21]) @[el2_pic_ctl.scala 175:109] + node _T_1519 = bits(_T_1518, 0, 0) @[Bitwise.scala 72:15] + node _T_1520 = mux(_T_1519, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1521 = and(_T_1520, intpriority_reg_inv[21]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[21] <= _T_1521 @[el2_pic_ctl.scala 175:63] + node _T_1522 = and(extintsrc_req_gw_22, intenable_reg[22]) @[el2_pic_ctl.scala 175:109] + node _T_1523 = bits(_T_1522, 0, 0) @[Bitwise.scala 72:15] + node _T_1524 = mux(_T_1523, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1525 = and(_T_1524, intpriority_reg_inv[22]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[22] <= _T_1525 @[el2_pic_ctl.scala 175:63] + node _T_1526 = and(extintsrc_req_gw_23, intenable_reg[23]) @[el2_pic_ctl.scala 175:109] + node _T_1527 = bits(_T_1526, 0, 0) @[Bitwise.scala 72:15] + node _T_1528 = mux(_T_1527, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1529 = and(_T_1528, intpriority_reg_inv[23]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[23] <= _T_1529 @[el2_pic_ctl.scala 175:63] + node _T_1530 = and(extintsrc_req_gw_24, intenable_reg[24]) @[el2_pic_ctl.scala 175:109] + node _T_1531 = bits(_T_1530, 0, 0) @[Bitwise.scala 72:15] + node _T_1532 = mux(_T_1531, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1533 = and(_T_1532, intpriority_reg_inv[24]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[24] <= _T_1533 @[el2_pic_ctl.scala 175:63] + node _T_1534 = and(extintsrc_req_gw_25, intenable_reg[25]) @[el2_pic_ctl.scala 175:109] + node _T_1535 = bits(_T_1534, 0, 0) @[Bitwise.scala 72:15] + node _T_1536 = mux(_T_1535, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1537 = and(_T_1536, intpriority_reg_inv[25]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[25] <= _T_1537 @[el2_pic_ctl.scala 175:63] + node _T_1538 = and(extintsrc_req_gw_26, intenable_reg[26]) @[el2_pic_ctl.scala 175:109] + node _T_1539 = bits(_T_1538, 0, 0) @[Bitwise.scala 72:15] + node _T_1540 = mux(_T_1539, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1541 = and(_T_1540, intpriority_reg_inv[26]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[26] <= _T_1541 @[el2_pic_ctl.scala 175:63] + node _T_1542 = and(extintsrc_req_gw_27, intenable_reg[27]) @[el2_pic_ctl.scala 175:109] + node _T_1543 = bits(_T_1542, 0, 0) @[Bitwise.scala 72:15] + node _T_1544 = mux(_T_1543, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1545 = and(_T_1544, intpriority_reg_inv[27]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[27] <= _T_1545 @[el2_pic_ctl.scala 175:63] + node _T_1546 = and(extintsrc_req_gw_28, intenable_reg[28]) @[el2_pic_ctl.scala 175:109] + node _T_1547 = bits(_T_1546, 0, 0) @[Bitwise.scala 72:15] + node _T_1548 = mux(_T_1547, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1549 = and(_T_1548, intpriority_reg_inv[28]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[28] <= _T_1549 @[el2_pic_ctl.scala 175:63] + node _T_1550 = and(extintsrc_req_gw_29, intenable_reg[29]) @[el2_pic_ctl.scala 175:109] + node _T_1551 = bits(_T_1550, 0, 0) @[Bitwise.scala 72:15] + node _T_1552 = mux(_T_1551, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1553 = and(_T_1552, intpriority_reg_inv[29]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[29] <= _T_1553 @[el2_pic_ctl.scala 175:63] + node _T_1554 = and(extintsrc_req_gw_30, intenable_reg[30]) @[el2_pic_ctl.scala 175:109] + node _T_1555 = bits(_T_1554, 0, 0) @[Bitwise.scala 72:15] + node _T_1556 = mux(_T_1555, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1557 = and(_T_1556, intpriority_reg_inv[30]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[30] <= _T_1557 @[el2_pic_ctl.scala 175:63] + node _T_1558 = and(extintsrc_req_gw_31, intenable_reg[31]) @[el2_pic_ctl.scala 175:109] + node _T_1559 = bits(_T_1558, 0, 0) @[Bitwise.scala 72:15] + node _T_1560 = mux(_T_1559, UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1561 = and(_T_1560, intpriority_reg_inv[31]) @[el2_pic_ctl.scala 175:129] + intpend_w_prior_en[31] <= _T_1561 @[el2_pic_ctl.scala 175:63] + intpend_id[0] <= UInt<1>("h00") @[el2_pic_ctl.scala 176:55] + intpend_id[1] <= UInt<1>("h01") @[el2_pic_ctl.scala 176:55] + intpend_id[2] <= UInt<2>("h02") @[el2_pic_ctl.scala 176:55] + intpend_id[3] <= UInt<2>("h03") @[el2_pic_ctl.scala 176:55] + intpend_id[4] <= UInt<3>("h04") @[el2_pic_ctl.scala 176:55] + intpend_id[5] <= UInt<3>("h05") @[el2_pic_ctl.scala 176:55] + intpend_id[6] <= UInt<3>("h06") @[el2_pic_ctl.scala 176:55] + intpend_id[7] <= UInt<3>("h07") @[el2_pic_ctl.scala 176:55] + intpend_id[8] <= UInt<4>("h08") @[el2_pic_ctl.scala 176:55] + intpend_id[9] <= UInt<4>("h09") @[el2_pic_ctl.scala 176:55] + intpend_id[10] <= UInt<4>("h0a") @[el2_pic_ctl.scala 176:55] + intpend_id[11] <= UInt<4>("h0b") @[el2_pic_ctl.scala 176:55] + intpend_id[12] <= UInt<4>("h0c") @[el2_pic_ctl.scala 176:55] + intpend_id[13] <= UInt<4>("h0d") @[el2_pic_ctl.scala 176:55] + intpend_id[14] <= UInt<4>("h0e") @[el2_pic_ctl.scala 176:55] + intpend_id[15] <= UInt<4>("h0f") @[el2_pic_ctl.scala 176:55] + intpend_id[16] <= UInt<5>("h010") @[el2_pic_ctl.scala 176:55] + intpend_id[17] <= UInt<5>("h011") @[el2_pic_ctl.scala 176:55] + intpend_id[18] <= UInt<5>("h012") @[el2_pic_ctl.scala 176:55] + intpend_id[19] <= UInt<5>("h013") @[el2_pic_ctl.scala 176:55] + intpend_id[20] <= UInt<5>("h014") @[el2_pic_ctl.scala 176:55] + intpend_id[21] <= UInt<5>("h015") @[el2_pic_ctl.scala 176:55] + intpend_id[22] <= UInt<5>("h016") @[el2_pic_ctl.scala 176:55] + intpend_id[23] <= UInt<5>("h017") @[el2_pic_ctl.scala 176:55] + intpend_id[24] <= UInt<5>("h018") @[el2_pic_ctl.scala 176:55] + intpend_id[25] <= UInt<5>("h019") @[el2_pic_ctl.scala 176:55] + intpend_id[26] <= UInt<5>("h01a") @[el2_pic_ctl.scala 176:55] + intpend_id[27] <= UInt<5>("h01b") @[el2_pic_ctl.scala 176:55] + intpend_id[28] <= UInt<5>("h01c") @[el2_pic_ctl.scala 176:55] + intpend_id[29] <= UInt<5>("h01d") @[el2_pic_ctl.scala 176:55] + intpend_id[30] <= UInt<5>("h01e") @[el2_pic_ctl.scala 176:55] + intpend_id[31] <= UInt<5>("h01f") @[el2_pic_ctl.scala 176:55] + wire level_intpend_w_prior_en : UInt<4>[34][6] @[el2_pic_ctl.scala 227:40] + wire level_intpend_id : UInt<8>[34][6] @[el2_pic_ctl.scala 228:32] + level_intpend_w_prior_en[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[0][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[1][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[2][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[3][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[4][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][0] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][1] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][4] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][6] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][7] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][8] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][10] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][11] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][12] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][13] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][14] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][15] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][16] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][18] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][19] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][20] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][21] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][22] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][23] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][24] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][25] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][26] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][27] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][28] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][29] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][30] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][31] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][32] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + level_intpend_w_prior_en[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 231:38] + level_intpend_id[5][33] <= UInt<1>("h00") @[el2_pic_ctl.scala 232:30] + node _T_1562 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + node _T_1563 = mux(UInt<1>("h00"), UInt<4>("h0f"), UInt<4>("h00")) @[Bitwise.scala 72:12] + level_intpend_w_prior_en[0][0] <= intpend_w_prior_en[0] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][1] <= intpend_w_prior_en[1] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][2] <= intpend_w_prior_en[2] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][3] <= intpend_w_prior_en[3] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][4] <= intpend_w_prior_en[4] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][5] <= intpend_w_prior_en[5] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][6] <= intpend_w_prior_en[6] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][7] <= intpend_w_prior_en[7] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][8] <= intpend_w_prior_en[8] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][9] <= intpend_w_prior_en[9] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][10] <= intpend_w_prior_en[10] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][11] <= intpend_w_prior_en[11] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][12] <= intpend_w_prior_en[12] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][13] <= intpend_w_prior_en[13] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][14] <= intpend_w_prior_en[14] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][15] <= intpend_w_prior_en[15] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][16] <= intpend_w_prior_en[16] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][17] <= intpend_w_prior_en[17] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][18] <= intpend_w_prior_en[18] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][19] <= intpend_w_prior_en[19] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][20] <= intpend_w_prior_en[20] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][21] <= intpend_w_prior_en[21] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][22] <= intpend_w_prior_en[22] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][23] <= intpend_w_prior_en[23] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][24] <= intpend_w_prior_en[24] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][25] <= intpend_w_prior_en[25] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][26] <= intpend_w_prior_en[26] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][27] <= intpend_w_prior_en[27] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][28] <= intpend_w_prior_en[28] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][29] <= intpend_w_prior_en[29] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][30] <= intpend_w_prior_en[30] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][31] <= intpend_w_prior_en[31] @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][32] <= _T_1562 @[el2_pic_ctl.scala 234:33] + level_intpend_w_prior_en[0][33] <= _T_1563 @[el2_pic_ctl.scala 234:33] + node _T_1564 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_1565 = mux(UInt<1>("h01"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + level_intpend_id[0][0] <= intpend_id[0] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][1] <= intpend_id[1] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][2] <= intpend_id[2] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][3] <= intpend_id[3] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][4] <= intpend_id[4] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][5] <= intpend_id[5] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][6] <= intpend_id[6] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][7] <= intpend_id[7] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][8] <= intpend_id[8] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][9] <= intpend_id[9] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][10] <= intpend_id[10] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][11] <= intpend_id[11] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][12] <= intpend_id[12] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][13] <= intpend_id[13] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][14] <= intpend_id[14] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][15] <= intpend_id[15] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][16] <= intpend_id[16] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][17] <= intpend_id[17] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][18] <= intpend_id[18] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][19] <= intpend_id[19] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][20] <= intpend_id[20] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][21] <= intpend_id[21] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][22] <= intpend_id[22] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][23] <= intpend_id[23] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][24] <= intpend_id[24] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][25] <= intpend_id[25] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][26] <= intpend_id[26] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][27] <= intpend_id[27] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][28] <= intpend_id[28] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][29] <= intpend_id[29] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][30] <= intpend_id[30] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][31] <= intpend_id[31] @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][32] <= _T_1564 @[el2_pic_ctl.scala 235:33] + level_intpend_id[0][33] <= _T_1565 @[el2_pic_ctl.scala 235:33] + wire out_id : UInt<8> + out_id <= UInt<1>("h00") + wire out_priority : UInt<4> + out_priority <= UInt<1>("h00") + node _T_1566 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 38:29] + node _T_1567 = mux(_T_1566, level_intpend_id[0][1], level_intpend_id[0][0]) @[el2_pic_ctl.scala 38:18] + out_id <= _T_1567 @[el2_pic_ctl.scala 38:12] + node _T_1568 = lt(level_intpend_w_prior_en[0][0], level_intpend_w_prior_en[0][1]) @[el2_pic_ctl.scala 39:35] + node _T_1569 = mux(_T_1568, level_intpend_w_prior_en[0][1], level_intpend_w_prior_en[0][0]) @[el2_pic_ctl.scala 39:24] + out_priority <= _T_1569 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][0] <= out_id @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][0] <= out_priority @[el2_pic_ctl.scala 247:43] + wire out_id_1 : UInt<8> + out_id_1 <= UInt<1>("h00") + wire out_priority_1 : UInt<4> + out_priority_1 <= UInt<1>("h00") + node _T_1570 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 38:29] + node _T_1571 = mux(_T_1570, level_intpend_id[0][3], level_intpend_id[0][2]) @[el2_pic_ctl.scala 38:18] + out_id_1 <= _T_1571 @[el2_pic_ctl.scala 38:12] + node _T_1572 = lt(level_intpend_w_prior_en[0][2], level_intpend_w_prior_en[0][3]) @[el2_pic_ctl.scala 39:35] + node _T_1573 = mux(_T_1572, level_intpend_w_prior_en[0][3], level_intpend_w_prior_en[0][2]) @[el2_pic_ctl.scala 39:24] + out_priority_1 <= _T_1573 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][1] <= out_id_1 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][1] <= out_priority_1 @[el2_pic_ctl.scala 247:43] + wire out_id_2 : UInt<8> + out_id_2 <= UInt<1>("h00") + wire out_priority_2 : UInt<4> + out_priority_2 <= UInt<1>("h00") + node _T_1574 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 38:29] + node _T_1575 = mux(_T_1574, level_intpend_id[0][5], level_intpend_id[0][4]) @[el2_pic_ctl.scala 38:18] + out_id_2 <= _T_1575 @[el2_pic_ctl.scala 38:12] + node _T_1576 = lt(level_intpend_w_prior_en[0][4], level_intpend_w_prior_en[0][5]) @[el2_pic_ctl.scala 39:35] + node _T_1577 = mux(_T_1576, level_intpend_w_prior_en[0][5], level_intpend_w_prior_en[0][4]) @[el2_pic_ctl.scala 39:24] + out_priority_2 <= _T_1577 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][2] <= out_id_2 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][2] <= out_priority_2 @[el2_pic_ctl.scala 247:43] + wire out_id_3 : UInt<8> + out_id_3 <= UInt<1>("h00") + wire out_priority_3 : UInt<4> + out_priority_3 <= UInt<1>("h00") + node _T_1578 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 38:29] + node _T_1579 = mux(_T_1578, level_intpend_id[0][7], level_intpend_id[0][6]) @[el2_pic_ctl.scala 38:18] + out_id_3 <= _T_1579 @[el2_pic_ctl.scala 38:12] + node _T_1580 = lt(level_intpend_w_prior_en[0][6], level_intpend_w_prior_en[0][7]) @[el2_pic_ctl.scala 39:35] + node _T_1581 = mux(_T_1580, level_intpend_w_prior_en[0][7], level_intpend_w_prior_en[0][6]) @[el2_pic_ctl.scala 39:24] + out_priority_3 <= _T_1581 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][3] <= out_id_3 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][3] <= out_priority_3 @[el2_pic_ctl.scala 247:43] + wire out_id_4 : UInt<8> + out_id_4 <= UInt<1>("h00") + wire out_priority_4 : UInt<4> + out_priority_4 <= UInt<1>("h00") + node _T_1582 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 38:29] + node _T_1583 = mux(_T_1582, level_intpend_id[0][9], level_intpend_id[0][8]) @[el2_pic_ctl.scala 38:18] + out_id_4 <= _T_1583 @[el2_pic_ctl.scala 38:12] + node _T_1584 = lt(level_intpend_w_prior_en[0][8], level_intpend_w_prior_en[0][9]) @[el2_pic_ctl.scala 39:35] + node _T_1585 = mux(_T_1584, level_intpend_w_prior_en[0][9], level_intpend_w_prior_en[0][8]) @[el2_pic_ctl.scala 39:24] + out_priority_4 <= _T_1585 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][4] <= out_id_4 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][4] <= out_priority_4 @[el2_pic_ctl.scala 247:43] + wire out_id_5 : UInt<8> + out_id_5 <= UInt<1>("h00") + wire out_priority_5 : UInt<4> + out_priority_5 <= UInt<1>("h00") + node _T_1586 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 38:29] + node _T_1587 = mux(_T_1586, level_intpend_id[0][11], level_intpend_id[0][10]) @[el2_pic_ctl.scala 38:18] + out_id_5 <= _T_1587 @[el2_pic_ctl.scala 38:12] + node _T_1588 = lt(level_intpend_w_prior_en[0][10], level_intpend_w_prior_en[0][11]) @[el2_pic_ctl.scala 39:35] + node _T_1589 = mux(_T_1588, level_intpend_w_prior_en[0][11], level_intpend_w_prior_en[0][10]) @[el2_pic_ctl.scala 39:24] + out_priority_5 <= _T_1589 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][5] <= out_id_5 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][5] <= out_priority_5 @[el2_pic_ctl.scala 247:43] + wire out_id_6 : UInt<8> + out_id_6 <= UInt<1>("h00") + wire out_priority_6 : UInt<4> + out_priority_6 <= UInt<1>("h00") + node _T_1590 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 38:29] + node _T_1591 = mux(_T_1590, level_intpend_id[0][13], level_intpend_id[0][12]) @[el2_pic_ctl.scala 38:18] + out_id_6 <= _T_1591 @[el2_pic_ctl.scala 38:12] + node _T_1592 = lt(level_intpend_w_prior_en[0][12], level_intpend_w_prior_en[0][13]) @[el2_pic_ctl.scala 39:35] + node _T_1593 = mux(_T_1592, level_intpend_w_prior_en[0][13], level_intpend_w_prior_en[0][12]) @[el2_pic_ctl.scala 39:24] + out_priority_6 <= _T_1593 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][6] <= out_id_6 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][6] <= out_priority_6 @[el2_pic_ctl.scala 247:43] + wire out_id_7 : UInt<8> + out_id_7 <= UInt<1>("h00") + wire out_priority_7 : UInt<4> + out_priority_7 <= UInt<1>("h00") + node _T_1594 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 38:29] + node _T_1595 = mux(_T_1594, level_intpend_id[0][15], level_intpend_id[0][14]) @[el2_pic_ctl.scala 38:18] + out_id_7 <= _T_1595 @[el2_pic_ctl.scala 38:12] + node _T_1596 = lt(level_intpend_w_prior_en[0][14], level_intpend_w_prior_en[0][15]) @[el2_pic_ctl.scala 39:35] + node _T_1597 = mux(_T_1596, level_intpend_w_prior_en[0][15], level_intpend_w_prior_en[0][14]) @[el2_pic_ctl.scala 39:24] + out_priority_7 <= _T_1597 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][7] <= out_id_7 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][7] <= out_priority_7 @[el2_pic_ctl.scala 247:43] + wire out_id_8 : UInt<8> + out_id_8 <= UInt<1>("h00") + wire out_priority_8 : UInt<4> + out_priority_8 <= UInt<1>("h00") + node _T_1598 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 38:29] + node _T_1599 = mux(_T_1598, level_intpend_id[0][17], level_intpend_id[0][16]) @[el2_pic_ctl.scala 38:18] + out_id_8 <= _T_1599 @[el2_pic_ctl.scala 38:12] + node _T_1600 = lt(level_intpend_w_prior_en[0][16], level_intpend_w_prior_en[0][17]) @[el2_pic_ctl.scala 39:35] + node _T_1601 = mux(_T_1600, level_intpend_w_prior_en[0][17], level_intpend_w_prior_en[0][16]) @[el2_pic_ctl.scala 39:24] + out_priority_8 <= _T_1601 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][8] <= out_id_8 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][8] <= out_priority_8 @[el2_pic_ctl.scala 247:43] + wire out_id_9 : UInt<8> + out_id_9 <= UInt<1>("h00") + wire out_priority_9 : UInt<4> + out_priority_9 <= UInt<1>("h00") + node _T_1602 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 38:29] + node _T_1603 = mux(_T_1602, level_intpend_id[0][19], level_intpend_id[0][18]) @[el2_pic_ctl.scala 38:18] + out_id_9 <= _T_1603 @[el2_pic_ctl.scala 38:12] + node _T_1604 = lt(level_intpend_w_prior_en[0][18], level_intpend_w_prior_en[0][19]) @[el2_pic_ctl.scala 39:35] + node _T_1605 = mux(_T_1604, level_intpend_w_prior_en[0][19], level_intpend_w_prior_en[0][18]) @[el2_pic_ctl.scala 39:24] + out_priority_9 <= _T_1605 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][9] <= out_id_9 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][9] <= out_priority_9 @[el2_pic_ctl.scala 247:43] + wire out_id_10 : UInt<8> + out_id_10 <= UInt<1>("h00") + wire out_priority_10 : UInt<4> + out_priority_10 <= UInt<1>("h00") + node _T_1606 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 38:29] + node _T_1607 = mux(_T_1606, level_intpend_id[0][21], level_intpend_id[0][20]) @[el2_pic_ctl.scala 38:18] + out_id_10 <= _T_1607 @[el2_pic_ctl.scala 38:12] + node _T_1608 = lt(level_intpend_w_prior_en[0][20], level_intpend_w_prior_en[0][21]) @[el2_pic_ctl.scala 39:35] + node _T_1609 = mux(_T_1608, level_intpend_w_prior_en[0][21], level_intpend_w_prior_en[0][20]) @[el2_pic_ctl.scala 39:24] + out_priority_10 <= _T_1609 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][10] <= out_id_10 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][10] <= out_priority_10 @[el2_pic_ctl.scala 247:43] + wire out_id_11 : UInt<8> + out_id_11 <= UInt<1>("h00") + wire out_priority_11 : UInt<4> + out_priority_11 <= UInt<1>("h00") + node _T_1610 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 38:29] + node _T_1611 = mux(_T_1610, level_intpend_id[0][23], level_intpend_id[0][22]) @[el2_pic_ctl.scala 38:18] + out_id_11 <= _T_1611 @[el2_pic_ctl.scala 38:12] + node _T_1612 = lt(level_intpend_w_prior_en[0][22], level_intpend_w_prior_en[0][23]) @[el2_pic_ctl.scala 39:35] + node _T_1613 = mux(_T_1612, level_intpend_w_prior_en[0][23], level_intpend_w_prior_en[0][22]) @[el2_pic_ctl.scala 39:24] + out_priority_11 <= _T_1613 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][11] <= out_id_11 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][11] <= out_priority_11 @[el2_pic_ctl.scala 247:43] + wire out_id_12 : UInt<8> + out_id_12 <= UInt<1>("h00") + wire out_priority_12 : UInt<4> + out_priority_12 <= UInt<1>("h00") + node _T_1614 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 38:29] + node _T_1615 = mux(_T_1614, level_intpend_id[0][25], level_intpend_id[0][24]) @[el2_pic_ctl.scala 38:18] + out_id_12 <= _T_1615 @[el2_pic_ctl.scala 38:12] + node _T_1616 = lt(level_intpend_w_prior_en[0][24], level_intpend_w_prior_en[0][25]) @[el2_pic_ctl.scala 39:35] + node _T_1617 = mux(_T_1616, level_intpend_w_prior_en[0][25], level_intpend_w_prior_en[0][24]) @[el2_pic_ctl.scala 39:24] + out_priority_12 <= _T_1617 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][12] <= out_id_12 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][12] <= out_priority_12 @[el2_pic_ctl.scala 247:43] + wire out_id_13 : UInt<8> + out_id_13 <= UInt<1>("h00") + wire out_priority_13 : UInt<4> + out_priority_13 <= UInt<1>("h00") + node _T_1618 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 38:29] + node _T_1619 = mux(_T_1618, level_intpend_id[0][27], level_intpend_id[0][26]) @[el2_pic_ctl.scala 38:18] + out_id_13 <= _T_1619 @[el2_pic_ctl.scala 38:12] + node _T_1620 = lt(level_intpend_w_prior_en[0][26], level_intpend_w_prior_en[0][27]) @[el2_pic_ctl.scala 39:35] + node _T_1621 = mux(_T_1620, level_intpend_w_prior_en[0][27], level_intpend_w_prior_en[0][26]) @[el2_pic_ctl.scala 39:24] + out_priority_13 <= _T_1621 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][13] <= out_id_13 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][13] <= out_priority_13 @[el2_pic_ctl.scala 247:43] + wire out_id_14 : UInt<8> + out_id_14 <= UInt<1>("h00") + wire out_priority_14 : UInt<4> + out_priority_14 <= UInt<1>("h00") + node _T_1622 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 38:29] + node _T_1623 = mux(_T_1622, level_intpend_id[0][29], level_intpend_id[0][28]) @[el2_pic_ctl.scala 38:18] + out_id_14 <= _T_1623 @[el2_pic_ctl.scala 38:12] + node _T_1624 = lt(level_intpend_w_prior_en[0][28], level_intpend_w_prior_en[0][29]) @[el2_pic_ctl.scala 39:35] + node _T_1625 = mux(_T_1624, level_intpend_w_prior_en[0][29], level_intpend_w_prior_en[0][28]) @[el2_pic_ctl.scala 39:24] + out_priority_14 <= _T_1625 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][14] <= out_id_14 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][14] <= out_priority_14 @[el2_pic_ctl.scala 247:43] + wire out_id_15 : UInt<8> + out_id_15 <= UInt<1>("h00") + wire out_priority_15 : UInt<4> + out_priority_15 <= UInt<1>("h00") + node _T_1626 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 38:29] + node _T_1627 = mux(_T_1626, level_intpend_id[0][31], level_intpend_id[0][30]) @[el2_pic_ctl.scala 38:18] + out_id_15 <= _T_1627 @[el2_pic_ctl.scala 38:12] + node _T_1628 = lt(level_intpend_w_prior_en[0][30], level_intpend_w_prior_en[0][31]) @[el2_pic_ctl.scala 39:35] + node _T_1629 = mux(_T_1628, level_intpend_w_prior_en[0][31], level_intpend_w_prior_en[0][30]) @[el2_pic_ctl.scala 39:24] + out_priority_15 <= _T_1629 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][15] <= out_id_15 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][15] <= out_priority_15 @[el2_pic_ctl.scala 247:43] + level_intpend_w_prior_en[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] + level_intpend_id[1][17] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] + wire out_id_16 : UInt<8> + out_id_16 <= UInt<1>("h00") + wire out_priority_16 : UInt<4> + out_priority_16 <= UInt<1>("h00") + node _T_1630 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 38:29] + node _T_1631 = mux(_T_1630, level_intpend_id[0][33], level_intpend_id[0][32]) @[el2_pic_ctl.scala 38:18] + out_id_16 <= _T_1631 @[el2_pic_ctl.scala 38:12] + node _T_1632 = lt(level_intpend_w_prior_en[0][32], level_intpend_w_prior_en[0][33]) @[el2_pic_ctl.scala 39:35] + node _T_1633 = mux(_T_1632, level_intpend_w_prior_en[0][33], level_intpend_w_prior_en[0][32]) @[el2_pic_ctl.scala 39:24] + out_priority_16 <= _T_1633 @[el2_pic_ctl.scala 39:18] + level_intpend_id[1][16] <= out_id_16 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[1][16] <= out_priority_16 @[el2_pic_ctl.scala 247:43] + wire out_id_17 : UInt<8> + out_id_17 <= UInt<1>("h00") + wire out_priority_17 : UInt<4> + out_priority_17 <= UInt<1>("h00") + node _T_1634 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 38:29] + node _T_1635 = mux(_T_1634, level_intpend_id[1][1], level_intpend_id[1][0]) @[el2_pic_ctl.scala 38:18] + out_id_17 <= _T_1635 @[el2_pic_ctl.scala 38:12] + node _T_1636 = lt(level_intpend_w_prior_en[1][0], level_intpend_w_prior_en[1][1]) @[el2_pic_ctl.scala 39:35] + node _T_1637 = mux(_T_1636, level_intpend_w_prior_en[1][1], level_intpend_w_prior_en[1][0]) @[el2_pic_ctl.scala 39:24] + out_priority_17 <= _T_1637 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][0] <= out_id_17 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][0] <= out_priority_17 @[el2_pic_ctl.scala 247:43] + wire out_id_18 : UInt<8> + out_id_18 <= UInt<1>("h00") + wire out_priority_18 : UInt<4> + out_priority_18 <= UInt<1>("h00") + node _T_1638 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 38:29] + node _T_1639 = mux(_T_1638, level_intpend_id[1][3], level_intpend_id[1][2]) @[el2_pic_ctl.scala 38:18] + out_id_18 <= _T_1639 @[el2_pic_ctl.scala 38:12] + node _T_1640 = lt(level_intpend_w_prior_en[1][2], level_intpend_w_prior_en[1][3]) @[el2_pic_ctl.scala 39:35] + node _T_1641 = mux(_T_1640, level_intpend_w_prior_en[1][3], level_intpend_w_prior_en[1][2]) @[el2_pic_ctl.scala 39:24] + out_priority_18 <= _T_1641 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][1] <= out_id_18 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][1] <= out_priority_18 @[el2_pic_ctl.scala 247:43] + wire out_id_19 : UInt<8> + out_id_19 <= UInt<1>("h00") + wire out_priority_19 : UInt<4> + out_priority_19 <= UInt<1>("h00") + node _T_1642 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 38:29] + node _T_1643 = mux(_T_1642, level_intpend_id[1][5], level_intpend_id[1][4]) @[el2_pic_ctl.scala 38:18] + out_id_19 <= _T_1643 @[el2_pic_ctl.scala 38:12] + node _T_1644 = lt(level_intpend_w_prior_en[1][4], level_intpend_w_prior_en[1][5]) @[el2_pic_ctl.scala 39:35] + node _T_1645 = mux(_T_1644, level_intpend_w_prior_en[1][5], level_intpend_w_prior_en[1][4]) @[el2_pic_ctl.scala 39:24] + out_priority_19 <= _T_1645 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][2] <= out_id_19 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][2] <= out_priority_19 @[el2_pic_ctl.scala 247:43] + wire out_id_20 : UInt<8> + out_id_20 <= UInt<1>("h00") + wire out_priority_20 : UInt<4> + out_priority_20 <= UInt<1>("h00") + node _T_1646 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 38:29] + node _T_1647 = mux(_T_1646, level_intpend_id[1][7], level_intpend_id[1][6]) @[el2_pic_ctl.scala 38:18] + out_id_20 <= _T_1647 @[el2_pic_ctl.scala 38:12] + node _T_1648 = lt(level_intpend_w_prior_en[1][6], level_intpend_w_prior_en[1][7]) @[el2_pic_ctl.scala 39:35] + node _T_1649 = mux(_T_1648, level_intpend_w_prior_en[1][7], level_intpend_w_prior_en[1][6]) @[el2_pic_ctl.scala 39:24] + out_priority_20 <= _T_1649 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][3] <= out_id_20 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][3] <= out_priority_20 @[el2_pic_ctl.scala 247:43] + wire out_id_21 : UInt<8> + out_id_21 <= UInt<1>("h00") + wire out_priority_21 : UInt<4> + out_priority_21 <= UInt<1>("h00") + node _T_1650 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 38:29] + node _T_1651 = mux(_T_1650, level_intpend_id[1][9], level_intpend_id[1][8]) @[el2_pic_ctl.scala 38:18] + out_id_21 <= _T_1651 @[el2_pic_ctl.scala 38:12] + node _T_1652 = lt(level_intpend_w_prior_en[1][8], level_intpend_w_prior_en[1][9]) @[el2_pic_ctl.scala 39:35] + node _T_1653 = mux(_T_1652, level_intpend_w_prior_en[1][9], level_intpend_w_prior_en[1][8]) @[el2_pic_ctl.scala 39:24] + out_priority_21 <= _T_1653 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][4] <= out_id_21 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][4] <= out_priority_21 @[el2_pic_ctl.scala 247:43] + wire out_id_22 : UInt<8> + out_id_22 <= UInt<1>("h00") + wire out_priority_22 : UInt<4> + out_priority_22 <= UInt<1>("h00") + node _T_1654 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 38:29] + node _T_1655 = mux(_T_1654, level_intpend_id[1][11], level_intpend_id[1][10]) @[el2_pic_ctl.scala 38:18] + out_id_22 <= _T_1655 @[el2_pic_ctl.scala 38:12] + node _T_1656 = lt(level_intpend_w_prior_en[1][10], level_intpend_w_prior_en[1][11]) @[el2_pic_ctl.scala 39:35] + node _T_1657 = mux(_T_1656, level_intpend_w_prior_en[1][11], level_intpend_w_prior_en[1][10]) @[el2_pic_ctl.scala 39:24] + out_priority_22 <= _T_1657 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][5] <= out_id_22 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][5] <= out_priority_22 @[el2_pic_ctl.scala 247:43] + wire out_id_23 : UInt<8> + out_id_23 <= UInt<1>("h00") + wire out_priority_23 : UInt<4> + out_priority_23 <= UInt<1>("h00") + node _T_1658 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 38:29] + node _T_1659 = mux(_T_1658, level_intpend_id[1][13], level_intpend_id[1][12]) @[el2_pic_ctl.scala 38:18] + out_id_23 <= _T_1659 @[el2_pic_ctl.scala 38:12] + node _T_1660 = lt(level_intpend_w_prior_en[1][12], level_intpend_w_prior_en[1][13]) @[el2_pic_ctl.scala 39:35] + node _T_1661 = mux(_T_1660, level_intpend_w_prior_en[1][13], level_intpend_w_prior_en[1][12]) @[el2_pic_ctl.scala 39:24] + out_priority_23 <= _T_1661 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][6] <= out_id_23 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][6] <= out_priority_23 @[el2_pic_ctl.scala 247:43] + wire out_id_24 : UInt<8> + out_id_24 <= UInt<1>("h00") + wire out_priority_24 : UInt<4> + out_priority_24 <= UInt<1>("h00") + node _T_1662 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 38:29] + node _T_1663 = mux(_T_1662, level_intpend_id[1][15], level_intpend_id[1][14]) @[el2_pic_ctl.scala 38:18] + out_id_24 <= _T_1663 @[el2_pic_ctl.scala 38:12] + node _T_1664 = lt(level_intpend_w_prior_en[1][14], level_intpend_w_prior_en[1][15]) @[el2_pic_ctl.scala 39:35] + node _T_1665 = mux(_T_1664, level_intpend_w_prior_en[1][15], level_intpend_w_prior_en[1][14]) @[el2_pic_ctl.scala 39:24] + out_priority_24 <= _T_1665 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][7] <= out_id_24 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][7] <= out_priority_24 @[el2_pic_ctl.scala 247:43] + level_intpend_w_prior_en[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] + level_intpend_id[2][9] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] + wire out_id_25 : UInt<8> + out_id_25 <= UInt<1>("h00") + wire out_priority_25 : UInt<4> + out_priority_25 <= UInt<1>("h00") + node _T_1666 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 38:29] + node _T_1667 = mux(_T_1666, level_intpend_id[1][17], level_intpend_id[1][16]) @[el2_pic_ctl.scala 38:18] + out_id_25 <= _T_1667 @[el2_pic_ctl.scala 38:12] + node _T_1668 = lt(level_intpend_w_prior_en[1][16], level_intpend_w_prior_en[1][17]) @[el2_pic_ctl.scala 39:35] + node _T_1669 = mux(_T_1668, level_intpend_w_prior_en[1][17], level_intpend_w_prior_en[1][16]) @[el2_pic_ctl.scala 39:24] + out_priority_25 <= _T_1669 @[el2_pic_ctl.scala 39:18] + level_intpend_id[2][8] <= out_id_25 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[2][8] <= out_priority_25 @[el2_pic_ctl.scala 247:43] + wire out_id_26 : UInt<8> + out_id_26 <= UInt<1>("h00") + wire out_priority_26 : UInt<4> + out_priority_26 <= UInt<1>("h00") + node _T_1670 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 38:29] + node _T_1671 = mux(_T_1670, level_intpend_id[2][1], level_intpend_id[2][0]) @[el2_pic_ctl.scala 38:18] + out_id_26 <= _T_1671 @[el2_pic_ctl.scala 38:12] + node _T_1672 = lt(level_intpend_w_prior_en[2][0], level_intpend_w_prior_en[2][1]) @[el2_pic_ctl.scala 39:35] + node _T_1673 = mux(_T_1672, level_intpend_w_prior_en[2][1], level_intpend_w_prior_en[2][0]) @[el2_pic_ctl.scala 39:24] + out_priority_26 <= _T_1673 @[el2_pic_ctl.scala 39:18] + level_intpend_id[3][0] <= out_id_26 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[3][0] <= out_priority_26 @[el2_pic_ctl.scala 247:43] + wire out_id_27 : UInt<8> + out_id_27 <= UInt<1>("h00") + wire out_priority_27 : UInt<4> + out_priority_27 <= UInt<1>("h00") + node _T_1674 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 38:29] + node _T_1675 = mux(_T_1674, level_intpend_id[2][3], level_intpend_id[2][2]) @[el2_pic_ctl.scala 38:18] + out_id_27 <= _T_1675 @[el2_pic_ctl.scala 38:12] + node _T_1676 = lt(level_intpend_w_prior_en[2][2], level_intpend_w_prior_en[2][3]) @[el2_pic_ctl.scala 39:35] + node _T_1677 = mux(_T_1676, level_intpend_w_prior_en[2][3], level_intpend_w_prior_en[2][2]) @[el2_pic_ctl.scala 39:24] + out_priority_27 <= _T_1677 @[el2_pic_ctl.scala 39:18] + level_intpend_id[3][1] <= out_id_27 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[3][1] <= out_priority_27 @[el2_pic_ctl.scala 247:43] + wire out_id_28 : UInt<8> + out_id_28 <= UInt<1>("h00") + wire out_priority_28 : UInt<4> + out_priority_28 <= UInt<1>("h00") + node _T_1678 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 38:29] + node _T_1679 = mux(_T_1678, level_intpend_id[2][5], level_intpend_id[2][4]) @[el2_pic_ctl.scala 38:18] + out_id_28 <= _T_1679 @[el2_pic_ctl.scala 38:12] + node _T_1680 = lt(level_intpend_w_prior_en[2][4], level_intpend_w_prior_en[2][5]) @[el2_pic_ctl.scala 39:35] + node _T_1681 = mux(_T_1680, level_intpend_w_prior_en[2][5], level_intpend_w_prior_en[2][4]) @[el2_pic_ctl.scala 39:24] + out_priority_28 <= _T_1681 @[el2_pic_ctl.scala 39:18] + level_intpend_id[3][2] <= out_id_28 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[3][2] <= out_priority_28 @[el2_pic_ctl.scala 247:43] + wire out_id_29 : UInt<8> + out_id_29 <= UInt<1>("h00") + wire out_priority_29 : UInt<4> + out_priority_29 <= UInt<1>("h00") + node _T_1682 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 38:29] + node _T_1683 = mux(_T_1682, level_intpend_id[2][7], level_intpend_id[2][6]) @[el2_pic_ctl.scala 38:18] + out_id_29 <= _T_1683 @[el2_pic_ctl.scala 38:12] + node _T_1684 = lt(level_intpend_w_prior_en[2][6], level_intpend_w_prior_en[2][7]) @[el2_pic_ctl.scala 39:35] + node _T_1685 = mux(_T_1684, level_intpend_w_prior_en[2][7], level_intpend_w_prior_en[2][6]) @[el2_pic_ctl.scala 39:24] + out_priority_29 <= _T_1685 @[el2_pic_ctl.scala 39:18] + level_intpend_id[3][3] <= out_id_29 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[3][3] <= out_priority_29 @[el2_pic_ctl.scala 247:43] + level_intpend_w_prior_en[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] + level_intpend_id[3][5] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] + wire out_id_30 : UInt<8> + out_id_30 <= UInt<1>("h00") + wire out_priority_30 : UInt<4> + out_priority_30 <= UInt<1>("h00") + node _T_1686 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 38:29] + node _T_1687 = mux(_T_1686, level_intpend_id[2][9], level_intpend_id[2][8]) @[el2_pic_ctl.scala 38:18] + out_id_30 <= _T_1687 @[el2_pic_ctl.scala 38:12] + node _T_1688 = lt(level_intpend_w_prior_en[2][8], level_intpend_w_prior_en[2][9]) @[el2_pic_ctl.scala 39:35] + node _T_1689 = mux(_T_1688, level_intpend_w_prior_en[2][9], level_intpend_w_prior_en[2][8]) @[el2_pic_ctl.scala 39:24] + out_priority_30 <= _T_1689 @[el2_pic_ctl.scala 39:18] + level_intpend_id[3][4] <= out_id_30 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[3][4] <= out_priority_30 @[el2_pic_ctl.scala 247:43] + wire out_id_31 : UInt<8> + out_id_31 <= UInt<1>("h00") + wire out_priority_31 : UInt<4> + out_priority_31 <= UInt<1>("h00") + node _T_1690 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 38:29] + node _T_1691 = mux(_T_1690, level_intpend_id[3][1], level_intpend_id[3][0]) @[el2_pic_ctl.scala 38:18] + out_id_31 <= _T_1691 @[el2_pic_ctl.scala 38:12] + node _T_1692 = lt(level_intpend_w_prior_en[3][0], level_intpend_w_prior_en[3][1]) @[el2_pic_ctl.scala 39:35] + node _T_1693 = mux(_T_1692, level_intpend_w_prior_en[3][1], level_intpend_w_prior_en[3][0]) @[el2_pic_ctl.scala 39:24] + out_priority_31 <= _T_1693 @[el2_pic_ctl.scala 39:18] + level_intpend_id[4][0] <= out_id_31 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[4][0] <= out_priority_31 @[el2_pic_ctl.scala 247:43] + wire out_id_32 : UInt<8> + out_id_32 <= UInt<1>("h00") + wire out_priority_32 : UInt<4> + out_priority_32 <= UInt<1>("h00") + node _T_1694 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 38:29] + node _T_1695 = mux(_T_1694, level_intpend_id[3][3], level_intpend_id[3][2]) @[el2_pic_ctl.scala 38:18] + out_id_32 <= _T_1695 @[el2_pic_ctl.scala 38:12] + node _T_1696 = lt(level_intpend_w_prior_en[3][2], level_intpend_w_prior_en[3][3]) @[el2_pic_ctl.scala 39:35] + node _T_1697 = mux(_T_1696, level_intpend_w_prior_en[3][3], level_intpend_w_prior_en[3][2]) @[el2_pic_ctl.scala 39:24] + out_priority_32 <= _T_1697 @[el2_pic_ctl.scala 39:18] + level_intpend_id[4][1] <= out_id_32 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[4][1] <= out_priority_32 @[el2_pic_ctl.scala 247:43] + level_intpend_w_prior_en[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] + level_intpend_id[4][3] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] + wire out_id_33 : UInt<8> + out_id_33 <= UInt<1>("h00") + wire out_priority_33 : UInt<4> + out_priority_33 <= UInt<1>("h00") + node _T_1698 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 38:29] + node _T_1699 = mux(_T_1698, level_intpend_id[3][5], level_intpend_id[3][4]) @[el2_pic_ctl.scala 38:18] + out_id_33 <= _T_1699 @[el2_pic_ctl.scala 38:12] + node _T_1700 = lt(level_intpend_w_prior_en[3][4], level_intpend_w_prior_en[3][5]) @[el2_pic_ctl.scala 39:35] + node _T_1701 = mux(_T_1700, level_intpend_w_prior_en[3][5], level_intpend_w_prior_en[3][4]) @[el2_pic_ctl.scala 39:24] + out_priority_33 <= _T_1701 @[el2_pic_ctl.scala 39:18] + level_intpend_id[4][2] <= out_id_33 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[4][2] <= out_priority_33 @[el2_pic_ctl.scala 247:43] + wire out_id_34 : UInt<8> + out_id_34 <= UInt<1>("h00") + wire out_priority_34 : UInt<4> + out_priority_34 <= UInt<1>("h00") + node _T_1702 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 38:29] + node _T_1703 = mux(_T_1702, level_intpend_id[4][1], level_intpend_id[4][0]) @[el2_pic_ctl.scala 38:18] + out_id_34 <= _T_1703 @[el2_pic_ctl.scala 38:12] + node _T_1704 = lt(level_intpend_w_prior_en[4][0], level_intpend_w_prior_en[4][1]) @[el2_pic_ctl.scala 39:35] + node _T_1705 = mux(_T_1704, level_intpend_w_prior_en[4][1], level_intpend_w_prior_en[4][0]) @[el2_pic_ctl.scala 39:24] + out_priority_34 <= _T_1705 @[el2_pic_ctl.scala 39:18] + level_intpend_id[5][0] <= out_id_34 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[5][0] <= out_priority_34 @[el2_pic_ctl.scala 247:43] + level_intpend_w_prior_en[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 242:46] + level_intpend_id[5][2] <= UInt<1>("h00") @[el2_pic_ctl.scala 243:46] + wire out_id_35 : UInt<8> + out_id_35 <= UInt<1>("h00") + wire out_priority_35 : UInt<4> + out_priority_35 <= UInt<1>("h00") + node _T_1706 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 38:29] + node _T_1707 = mux(_T_1706, level_intpend_id[4][3], level_intpend_id[4][2]) @[el2_pic_ctl.scala 38:18] + out_id_35 <= _T_1707 @[el2_pic_ctl.scala 38:12] + node _T_1708 = lt(level_intpend_w_prior_en[4][2], level_intpend_w_prior_en[4][3]) @[el2_pic_ctl.scala 39:35] + node _T_1709 = mux(_T_1708, level_intpend_w_prior_en[4][3], level_intpend_w_prior_en[4][2]) @[el2_pic_ctl.scala 39:24] + out_priority_35 <= _T_1709 @[el2_pic_ctl.scala 39:18] + level_intpend_id[5][1] <= out_id_35 @[el2_pic_ctl.scala 246:43] + level_intpend_w_prior_en[5][1] <= out_priority_35 @[el2_pic_ctl.scala 247:43] + claimid_in <= level_intpend_id[5][0] @[el2_pic_ctl.scala 250:29] + selected_int_priority <= level_intpend_w_prior_en[5][0] @[el2_pic_ctl.scala 251:29] + node config_reg_we = and(waddr_config_pic_match, picm_wren_ff) @[el2_pic_ctl.scala 263:47] + node config_reg_re = and(raddr_config_pic_match, picm_rden_ff) @[el2_pic_ctl.scala 264:47] + node config_reg_in = bits(picm_wr_data_ff, 0, 0) @[el2_pic_ctl.scala 265:39] + node _T_1710 = bits(config_reg_we, 0, 0) @[el2_pic_ctl.scala 266:82] + reg _T_1711 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_1710 : @[Reg.scala 28:19] + _T_1711 <= config_reg_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + config_reg <= _T_1711 @[el2_pic_ctl.scala 266:37] + intpriord <= config_reg @[el2_pic_ctl.scala 267:14] + node _T_1712 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 275:31] + node _T_1713 = not(selected_int_priority) @[el2_pic_ctl.scala 275:38] + node pl_in_q = mux(_T_1712, _T_1713, selected_int_priority) @[el2_pic_ctl.scala 275:20] + reg _T_1714 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 276:47] + _T_1714 <= claimid_in @[el2_pic_ctl.scala 276:47] + io.claimid <= _T_1714 @[el2_pic_ctl.scala 276:37] + reg _T_1715 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 277:42] + _T_1715 <= pl_in_q @[el2_pic_ctl.scala 277:42] + io.pl <= _T_1715 @[el2_pic_ctl.scala 277:32] + node _T_1716 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 278:33] + node _T_1717 = not(io.meipt) @[el2_pic_ctl.scala 278:40] + node meipt_inv = mux(_T_1716, _T_1717, io.meipt) @[el2_pic_ctl.scala 278:22] + node _T_1718 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 279:36] + node _T_1719 = not(io.meicurpl) @[el2_pic_ctl.scala 279:43] + node meicurpl_inv = mux(_T_1718, _T_1719, io.meicurpl) @[el2_pic_ctl.scala 279:25] + node _T_1720 = gt(selected_int_priority, meipt_inv) @[el2_pic_ctl.scala 280:47] + node _T_1721 = gt(selected_int_priority, meicurpl_inv) @[el2_pic_ctl.scala 280:86] + node mexintpend_in = and(_T_1720, _T_1721) @[el2_pic_ctl.scala 280:60] + reg _T_1722 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 281:50] + _T_1722 <= mexintpend_in @[el2_pic_ctl.scala 281:50] + io.mexintpend <= _T_1722 @[el2_pic_ctl.scala 281:17] + node _T_1723 = bits(intpriord, 0, 0) @[el2_pic_ctl.scala 282:30] + node maxint = mux(_T_1723, UInt<1>("h00"), UInt<4>("h0f")) @[el2_pic_ctl.scala 282:19] + node mhwakeup_in = eq(pl_in_q, maxint) @[el2_pic_ctl.scala 283:29] + reg _T_1724 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_pic_ctl.scala 284:48] + _T_1724 <= mhwakeup_in @[el2_pic_ctl.scala 284:48] + io.mhwakeup <= _T_1724 @[el2_pic_ctl.scala 284:15] + node intpend_reg_read = and(addr_intpend_base_match, picm_rden_ff) @[el2_pic_ctl.scala 290:60] + node intpriority_reg_read = and(raddr_intpriority_base_match, picm_rden_ff) @[el2_pic_ctl.scala 291:60] + node intenable_reg_read = and(raddr_intenable_base_match, picm_rden_ff) @[el2_pic_ctl.scala 292:60] + node gw_config_reg_read = and(raddr_config_gw_base_match, picm_rden_ff) @[el2_pic_ctl.scala 293:60] + node _T_1725 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1726 = cat(extintsrc_req_gw_31, extintsrc_req_gw_30) @[Cat.scala 29:58] + node _T_1727 = cat(_T_1726, extintsrc_req_gw_29) @[Cat.scala 29:58] + node _T_1728 = cat(_T_1727, extintsrc_req_gw_28) @[Cat.scala 29:58] + node _T_1729 = cat(_T_1728, extintsrc_req_gw_27) @[Cat.scala 29:58] + node _T_1730 = cat(_T_1729, extintsrc_req_gw_26) @[Cat.scala 29:58] + node _T_1731 = cat(_T_1730, extintsrc_req_gw_25) @[Cat.scala 29:58] + node _T_1732 = cat(_T_1731, extintsrc_req_gw_24) @[Cat.scala 29:58] + node _T_1733 = cat(_T_1732, extintsrc_req_gw_23) @[Cat.scala 29:58] + node _T_1734 = cat(_T_1733, extintsrc_req_gw_22) @[Cat.scala 29:58] + node _T_1735 = cat(_T_1734, extintsrc_req_gw_21) @[Cat.scala 29:58] + node _T_1736 = cat(_T_1735, extintsrc_req_gw_20) @[Cat.scala 29:58] + node _T_1737 = cat(_T_1736, extintsrc_req_gw_19) @[Cat.scala 29:58] + node _T_1738 = cat(_T_1737, extintsrc_req_gw_18) @[Cat.scala 29:58] + node _T_1739 = cat(_T_1738, extintsrc_req_gw_17) @[Cat.scala 29:58] + node _T_1740 = cat(_T_1739, extintsrc_req_gw_16) @[Cat.scala 29:58] + node _T_1741 = cat(_T_1740, extintsrc_req_gw_15) @[Cat.scala 29:58] + node _T_1742 = cat(_T_1741, extintsrc_req_gw_14) @[Cat.scala 29:58] + node _T_1743 = cat(_T_1742, extintsrc_req_gw_13) @[Cat.scala 29:58] + node _T_1744 = cat(_T_1743, extintsrc_req_gw_12) @[Cat.scala 29:58] + node _T_1745 = cat(_T_1744, extintsrc_req_gw_11) @[Cat.scala 29:58] + node _T_1746 = cat(_T_1745, extintsrc_req_gw_10) @[Cat.scala 29:58] + node _T_1747 = cat(_T_1746, extintsrc_req_gw_9) @[Cat.scala 29:58] + node _T_1748 = cat(_T_1747, extintsrc_req_gw_8) @[Cat.scala 29:58] + node _T_1749 = cat(_T_1748, extintsrc_req_gw_7) @[Cat.scala 29:58] + node _T_1750 = cat(_T_1749, extintsrc_req_gw_6) @[Cat.scala 29:58] + node _T_1751 = cat(_T_1750, extintsrc_req_gw_5) @[Cat.scala 29:58] + node _T_1752 = cat(_T_1751, extintsrc_req_gw_4) @[Cat.scala 29:58] + node _T_1753 = cat(_T_1752, extintsrc_req_gw_3) @[Cat.scala 29:58] + node _T_1754 = cat(_T_1753, extintsrc_req_gw_2) @[Cat.scala 29:58] + node _T_1755 = cat(_T_1754, extintsrc_req_gw_1) @[Cat.scala 29:58] + node _T_1756 = cat(_T_1755, UInt<1>("h00")) @[Cat.scala 29:58] + node _T_1757 = cat(_T_1725, _T_1756) @[Cat.scala 29:58] + intpend_reg_extended <= _T_1757 @[el2_pic_ctl.scala 295:25] + wire intpend_rd_part_out : UInt<32>[2] @[el2_pic_ctl.scala 297:33] + node _T_1758 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98] + node _T_1759 = and(intpend_reg_read, _T_1758) @[el2_pic_ctl.scala 298:83] + node _T_1760 = eq(_T_1759, UInt<1>("h00")) @[el2_pic_ctl.scala 298:105] + node _T_1761 = bits(_T_1760, 0, 0) @[Bitwise.scala 72:15] + node _T_1762 = mux(_T_1761, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1763 = bits(intpend_reg_extended, 31, 0) @[el2_pic_ctl.scala 298:141] + node _T_1764 = and(_T_1762, _T_1763) @[el2_pic_ctl.scala 298:119] + intpend_rd_part_out[0] <= _T_1764 @[el2_pic_ctl.scala 298:54] + node _T_1765 = bits(picm_raddr_ff, 5, 2) @[el2_pic_ctl.scala 298:98] + node _T_1766 = and(intpend_reg_read, _T_1765) @[el2_pic_ctl.scala 298:83] + node _T_1767 = eq(_T_1766, UInt<1>("h01")) @[el2_pic_ctl.scala 298:105] + node _T_1768 = bits(_T_1767, 0, 0) @[Bitwise.scala 72:15] + node _T_1769 = mux(_T_1768, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1770 = bits(intpend_reg_extended, 63, 32) @[el2_pic_ctl.scala 298:141] + node _T_1771 = and(_T_1769, _T_1770) @[el2_pic_ctl.scala 298:119] + intpend_rd_part_out[1] <= _T_1771 @[el2_pic_ctl.scala 298:54] + node _T_1772 = or(intpend_rd_part_out[0], intpend_rd_part_out[1]) @[el2_pic_ctl.scala 299:89] + intpend_rd_out <= _T_1772 @[el2_pic_ctl.scala 299:26] + when UInt<1>("h00") : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[0] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1773 = bits(intenable_reg_re_1, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1773 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[1] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1774 = bits(intenable_reg_re_2, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1774 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[2] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1775 = bits(intenable_reg_re_3, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1775 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[3] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1776 = bits(intenable_reg_re_4, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1776 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[4] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1777 = bits(intenable_reg_re_5, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1777 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[5] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1778 = bits(intenable_reg_re_6, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1778 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[6] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1779 = bits(intenable_reg_re_7, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1779 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[7] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1780 = bits(intenable_reg_re_8, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1780 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[8] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1781 = bits(intenable_reg_re_9, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1781 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[9] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1782 = bits(intenable_reg_re_10, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1782 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[10] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1783 = bits(intenable_reg_re_11, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1783 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[11] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1784 = bits(intenable_reg_re_12, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1784 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[12] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1785 = bits(intenable_reg_re_13, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1785 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[13] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1786 = bits(intenable_reg_re_14, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1786 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[14] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1787 = bits(intenable_reg_re_15, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1787 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[15] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1788 = bits(intenable_reg_re_16, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1788 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[16] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1789 = bits(intenable_reg_re_17, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1789 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[17] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1790 = bits(intenable_reg_re_18, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1790 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[18] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1791 = bits(intenable_reg_re_19, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1791 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[19] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1792 = bits(intenable_reg_re_20, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1792 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[20] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1793 = bits(intenable_reg_re_21, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1793 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[21] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1794 = bits(intenable_reg_re_22, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1794 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[22] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1795 = bits(intenable_reg_re_23, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1795 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[23] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1796 = bits(intenable_reg_re_24, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1796 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[24] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1797 = bits(intenable_reg_re_25, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1797 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[25] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1798 = bits(intenable_reg_re_26, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1798 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[26] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1799 = bits(intenable_reg_re_27, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1799 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[27] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1800 = bits(intenable_reg_re_28, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1800 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[28] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1801 = bits(intenable_reg_re_29, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1801 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[29] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1802 = bits(intenable_reg_re_30, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1802 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[30] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1803 = bits(intenable_reg_re_31, 0, 0) @[el2_pic_ctl.scala 300:69] + when _T_1803 : @[el2_pic_ctl.scala 300:76] + intenable_rd_out <= intenable_reg[31] @[el2_pic_ctl.scala 300:95] + skip @[el2_pic_ctl.scala 300:76] + else : @[el2_pic_ctl.scala 300:126] + intenable_rd_out <= UInt<1>("h00") @[el2_pic_ctl.scala 300:144] + skip @[el2_pic_ctl.scala 300:126] + node _T_1804 = bits(intpriority_reg_re_1, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1805 = bits(intpriority_reg_re_2, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1806 = bits(intpriority_reg_re_3, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1807 = bits(intpriority_reg_re_4, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1808 = bits(intpriority_reg_re_5, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1809 = bits(intpriority_reg_re_6, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1810 = bits(intpriority_reg_re_7, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1811 = bits(intpriority_reg_re_8, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1812 = bits(intpriority_reg_re_9, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1813 = bits(intpriority_reg_re_10, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1814 = bits(intpriority_reg_re_11, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1815 = bits(intpriority_reg_re_12, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1816 = bits(intpriority_reg_re_13, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1817 = bits(intpriority_reg_re_14, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1818 = bits(intpriority_reg_re_15, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1819 = bits(intpriority_reg_re_16, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1820 = bits(intpriority_reg_re_17, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1821 = bits(intpriority_reg_re_18, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1822 = bits(intpriority_reg_re_19, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1823 = bits(intpriority_reg_re_20, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1824 = bits(intpriority_reg_re_21, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1825 = bits(intpriority_reg_re_22, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1826 = bits(intpriority_reg_re_23, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1827 = bits(intpriority_reg_re_24, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1828 = bits(intpriority_reg_re_25, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1829 = bits(intpriority_reg_re_26, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1830 = bits(intpriority_reg_re_27, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1831 = bits(intpriority_reg_re_28, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1832 = bits(intpriority_reg_re_29, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1833 = bits(intpriority_reg_re_30, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1834 = bits(intpriority_reg_re_31, 0, 0) @[el2_pic_ctl.scala 302:102] + node _T_1835 = mux(_T_1834, intpriority_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1836 = mux(_T_1833, intpriority_reg[30], _T_1835) @[Mux.scala 98:16] + node _T_1837 = mux(_T_1832, intpriority_reg[29], _T_1836) @[Mux.scala 98:16] + node _T_1838 = mux(_T_1831, intpriority_reg[28], _T_1837) @[Mux.scala 98:16] + node _T_1839 = mux(_T_1830, intpriority_reg[27], _T_1838) @[Mux.scala 98:16] + node _T_1840 = mux(_T_1829, intpriority_reg[26], _T_1839) @[Mux.scala 98:16] + node _T_1841 = mux(_T_1828, intpriority_reg[25], _T_1840) @[Mux.scala 98:16] + node _T_1842 = mux(_T_1827, intpriority_reg[24], _T_1841) @[Mux.scala 98:16] + node _T_1843 = mux(_T_1826, intpriority_reg[23], _T_1842) @[Mux.scala 98:16] + node _T_1844 = mux(_T_1825, intpriority_reg[22], _T_1843) @[Mux.scala 98:16] + node _T_1845 = mux(_T_1824, intpriority_reg[21], _T_1844) @[Mux.scala 98:16] + node _T_1846 = mux(_T_1823, intpriority_reg[20], _T_1845) @[Mux.scala 98:16] + node _T_1847 = mux(_T_1822, intpriority_reg[19], _T_1846) @[Mux.scala 98:16] + node _T_1848 = mux(_T_1821, intpriority_reg[18], _T_1847) @[Mux.scala 98:16] + node _T_1849 = mux(_T_1820, intpriority_reg[17], _T_1848) @[Mux.scala 98:16] + node _T_1850 = mux(_T_1819, intpriority_reg[16], _T_1849) @[Mux.scala 98:16] + node _T_1851 = mux(_T_1818, intpriority_reg[15], _T_1850) @[Mux.scala 98:16] + node _T_1852 = mux(_T_1817, intpriority_reg[14], _T_1851) @[Mux.scala 98:16] + node _T_1853 = mux(_T_1816, intpriority_reg[13], _T_1852) @[Mux.scala 98:16] + node _T_1854 = mux(_T_1815, intpriority_reg[12], _T_1853) @[Mux.scala 98:16] + node _T_1855 = mux(_T_1814, intpriority_reg[11], _T_1854) @[Mux.scala 98:16] + node _T_1856 = mux(_T_1813, intpriority_reg[10], _T_1855) @[Mux.scala 98:16] + node _T_1857 = mux(_T_1812, intpriority_reg[9], _T_1856) @[Mux.scala 98:16] + node _T_1858 = mux(_T_1811, intpriority_reg[8], _T_1857) @[Mux.scala 98:16] + node _T_1859 = mux(_T_1810, intpriority_reg[7], _T_1858) @[Mux.scala 98:16] + node _T_1860 = mux(_T_1809, intpriority_reg[6], _T_1859) @[Mux.scala 98:16] + node _T_1861 = mux(_T_1808, intpriority_reg[5], _T_1860) @[Mux.scala 98:16] + node _T_1862 = mux(_T_1807, intpriority_reg[4], _T_1861) @[Mux.scala 98:16] + node _T_1863 = mux(_T_1806, intpriority_reg[3], _T_1862) @[Mux.scala 98:16] + node _T_1864 = mux(_T_1805, intpriority_reg[2], _T_1863) @[Mux.scala 98:16] + node _T_1865 = mux(_T_1804, intpriority_reg[1], _T_1864) @[Mux.scala 98:16] + node intpriority_rd_out = mux(UInt<1>("h00"), intpriority_reg[0], _T_1865) @[Mux.scala 98:16] + node _T_1866 = bits(gw_config_reg_re_1, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1867 = bits(gw_config_reg_re_2, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1868 = bits(gw_config_reg_re_3, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1869 = bits(gw_config_reg_re_4, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1870 = bits(gw_config_reg_re_5, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1871 = bits(gw_config_reg_re_6, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1872 = bits(gw_config_reg_re_7, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1873 = bits(gw_config_reg_re_8, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1874 = bits(gw_config_reg_re_9, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1875 = bits(gw_config_reg_re_10, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1876 = bits(gw_config_reg_re_11, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1877 = bits(gw_config_reg_re_12, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1878 = bits(gw_config_reg_re_13, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1879 = bits(gw_config_reg_re_14, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1880 = bits(gw_config_reg_re_15, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1881 = bits(gw_config_reg_re_16, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1882 = bits(gw_config_reg_re_17, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1883 = bits(gw_config_reg_re_18, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1884 = bits(gw_config_reg_re_19, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1885 = bits(gw_config_reg_re_20, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1886 = bits(gw_config_reg_re_21, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1887 = bits(gw_config_reg_re_22, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1888 = bits(gw_config_reg_re_23, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1889 = bits(gw_config_reg_re_24, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1890 = bits(gw_config_reg_re_25, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1891 = bits(gw_config_reg_re_26, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1892 = bits(gw_config_reg_re_27, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1893 = bits(gw_config_reg_re_28, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1894 = bits(gw_config_reg_re_29, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1895 = bits(gw_config_reg_re_30, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1896 = bits(gw_config_reg_re_31, 0, 0) @[el2_pic_ctl.scala 303:100] + node _T_1897 = mux(_T_1896, gw_config_reg[31], UInt<1>("h00")) @[Mux.scala 98:16] + node _T_1898 = mux(_T_1895, gw_config_reg[30], _T_1897) @[Mux.scala 98:16] + node _T_1899 = mux(_T_1894, gw_config_reg[29], _T_1898) @[Mux.scala 98:16] + node _T_1900 = mux(_T_1893, gw_config_reg[28], _T_1899) @[Mux.scala 98:16] + node _T_1901 = mux(_T_1892, gw_config_reg[27], _T_1900) @[Mux.scala 98:16] + node _T_1902 = mux(_T_1891, gw_config_reg[26], _T_1901) @[Mux.scala 98:16] + node _T_1903 = mux(_T_1890, gw_config_reg[25], _T_1902) @[Mux.scala 98:16] + node _T_1904 = mux(_T_1889, gw_config_reg[24], _T_1903) @[Mux.scala 98:16] + node _T_1905 = mux(_T_1888, gw_config_reg[23], _T_1904) @[Mux.scala 98:16] + node _T_1906 = mux(_T_1887, gw_config_reg[22], _T_1905) @[Mux.scala 98:16] + node _T_1907 = mux(_T_1886, gw_config_reg[21], _T_1906) @[Mux.scala 98:16] + node _T_1908 = mux(_T_1885, gw_config_reg[20], _T_1907) @[Mux.scala 98:16] + node _T_1909 = mux(_T_1884, gw_config_reg[19], _T_1908) @[Mux.scala 98:16] + node _T_1910 = mux(_T_1883, gw_config_reg[18], _T_1909) @[Mux.scala 98:16] + node _T_1911 = mux(_T_1882, gw_config_reg[17], _T_1910) @[Mux.scala 98:16] + node _T_1912 = mux(_T_1881, gw_config_reg[16], _T_1911) @[Mux.scala 98:16] + node _T_1913 = mux(_T_1880, gw_config_reg[15], _T_1912) @[Mux.scala 98:16] + node _T_1914 = mux(_T_1879, gw_config_reg[14], _T_1913) @[Mux.scala 98:16] + node _T_1915 = mux(_T_1878, gw_config_reg[13], _T_1914) @[Mux.scala 98:16] + node _T_1916 = mux(_T_1877, gw_config_reg[12], _T_1915) @[Mux.scala 98:16] + node _T_1917 = mux(_T_1876, gw_config_reg[11], _T_1916) @[Mux.scala 98:16] + node _T_1918 = mux(_T_1875, gw_config_reg[10], _T_1917) @[Mux.scala 98:16] + node _T_1919 = mux(_T_1874, gw_config_reg[9], _T_1918) @[Mux.scala 98:16] + node _T_1920 = mux(_T_1873, gw_config_reg[8], _T_1919) @[Mux.scala 98:16] + node _T_1921 = mux(_T_1872, gw_config_reg[7], _T_1920) @[Mux.scala 98:16] + node _T_1922 = mux(_T_1871, gw_config_reg[6], _T_1921) @[Mux.scala 98:16] + node _T_1923 = mux(_T_1870, gw_config_reg[5], _T_1922) @[Mux.scala 98:16] + node _T_1924 = mux(_T_1869, gw_config_reg[4], _T_1923) @[Mux.scala 98:16] + node _T_1925 = mux(_T_1868, gw_config_reg[3], _T_1924) @[Mux.scala 98:16] + node _T_1926 = mux(_T_1867, gw_config_reg[2], _T_1925) @[Mux.scala 98:16] + node _T_1927 = mux(_T_1866, gw_config_reg[1], _T_1926) @[Mux.scala 98:16] + node gw_config_rd_out = mux(UInt<1>("h00"), gw_config_reg[0], _T_1927) @[Mux.scala 98:16] + wire picm_rd_data_in : UInt<32> + picm_rd_data_in <= UInt<1>("h00") + node _T_1928 = bits(intpend_reg_read, 0, 0) @[el2_pic_ctl.scala 308:22] + node _T_1929 = bits(intpriority_reg_read, 0, 0) @[el2_pic_ctl.scala 309:26] + node _T_1930 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_1931 = cat(_T_1930, intpriority_rd_out) @[Cat.scala 29:58] + node _T_1932 = bits(intenable_reg_read, 0, 0) @[el2_pic_ctl.scala 310:24] + node _T_1933 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1934 = cat(_T_1933, intenable_rd_out) @[Cat.scala 29:58] + node _T_1935 = bits(gw_config_reg_read, 0, 0) @[el2_pic_ctl.scala 311:24] + node _T_1936 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] + node _T_1937 = cat(_T_1936, gw_config_rd_out) @[Cat.scala 29:58] + node _T_1938 = bits(config_reg_re, 0, 0) @[el2_pic_ctl.scala 312:19] + node _T_1939 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1940 = cat(_T_1939, config_reg) @[Cat.scala 29:58] + node _T_1941 = bits(mask, 3, 3) @[el2_pic_ctl.scala 313:25] + node _T_1942 = and(picm_mken_ff, _T_1941) @[el2_pic_ctl.scala 313:19] + node _T_1943 = bits(_T_1942, 0, 0) @[el2_pic_ctl.scala 313:30] + node _T_1944 = mux(UInt<1>("h00"), UInt<30>("h03fffffff"), UInt<30>("h00")) @[Bitwise.scala 72:12] + node _T_1945 = cat(_T_1944, UInt<2>("h03")) @[Cat.scala 29:58] + node _T_1946 = bits(mask, 2, 2) @[el2_pic_ctl.scala 314:25] + node _T_1947 = and(picm_mken_ff, _T_1946) @[el2_pic_ctl.scala 314:19] + node _T_1948 = bits(_T_1947, 0, 0) @[el2_pic_ctl.scala 314:30] + node _T_1949 = mux(UInt<1>("h00"), UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12] + node _T_1950 = cat(_T_1949, UInt<1>("h01")) @[Cat.scala 29:58] + node _T_1951 = bits(mask, 1, 1) @[el2_pic_ctl.scala 315:25] + node _T_1952 = and(picm_mken_ff, _T_1951) @[el2_pic_ctl.scala 315:19] + node _T_1953 = bits(_T_1952, 0, 0) @[el2_pic_ctl.scala 315:30] + node _T_1954 = mux(UInt<1>("h00"), UInt<28>("h0fffffff"), UInt<28>("h00")) @[Bitwise.scala 72:12] + node _T_1955 = cat(_T_1954, UInt<4>("h0f")) @[Cat.scala 29:58] + node _T_1956 = bits(mask, 0, 0) @[el2_pic_ctl.scala 316:25] + node _T_1957 = and(picm_mken_ff, _T_1956) @[el2_pic_ctl.scala 316:19] + node _T_1958 = bits(_T_1957, 0, 0) @[el2_pic_ctl.scala 316:30] + node _T_1959 = mux(UInt<1>("h00"), UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12] + node _T_1960 = mux(_T_1928, intpend_rd_out, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1961 = mux(_T_1929, _T_1931, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1962 = mux(_T_1932, _T_1934, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1963 = mux(_T_1935, _T_1937, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1964 = mux(_T_1938, _T_1940, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1965 = mux(_T_1943, _T_1945, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1966 = mux(_T_1948, _T_1950, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1967 = mux(_T_1953, _T_1955, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1968 = mux(_T_1958, _T_1959, UInt<1>("h00")) @[Mux.scala 27:72] + node _T_1969 = or(_T_1960, _T_1961) @[Mux.scala 27:72] + node _T_1970 = or(_T_1969, _T_1962) @[Mux.scala 27:72] + node _T_1971 = or(_T_1970, _T_1963) @[Mux.scala 27:72] + node _T_1972 = or(_T_1971, _T_1964) @[Mux.scala 27:72] + node _T_1973 = or(_T_1972, _T_1965) @[Mux.scala 27:72] + node _T_1974 = or(_T_1973, _T_1966) @[Mux.scala 27:72] + node _T_1975 = or(_T_1974, _T_1967) @[Mux.scala 27:72] + node _T_1976 = or(_T_1975, _T_1968) @[Mux.scala 27:72] + wire _T_1977 : UInt<32> @[Mux.scala 27:72] + _T_1977 <= _T_1976 @[Mux.scala 27:72] + picm_rd_data_in <= _T_1977 @[el2_pic_ctl.scala 307:19] + node _T_1978 = bits(picm_bypass_ff, 0, 0) @[el2_pic_ctl.scala 319:41] + node _T_1979 = mux(_T_1978, picm_wr_data_ff, picm_rd_data_in) @[el2_pic_ctl.scala 319:25] + io.picm_rd_data <= _T_1979 @[el2_pic_ctl.scala 319:19] + node address = bits(picm_raddr_ff, 14, 0) @[el2_pic_ctl.scala 320:30] + mask <= UInt<4>("h01") @[el2_pic_ctl.scala 322:8] + node _T_1980 = eq(UInt<15>("h03000"), address) @[Conditional.scala 37:30] + when _T_1980 : @[Conditional.scala 40:58] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 324:44] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_1981 = eq(UInt<15>("h04004"), address) @[Conditional.scala 37:30] + when _T_1981 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 325:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1982 = eq(UInt<15>("h04008"), address) @[Conditional.scala 37:30] + when _T_1982 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 326:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1983 = eq(UInt<15>("h0400c"), address) @[Conditional.scala 37:30] + when _T_1983 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 327:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1984 = eq(UInt<15>("h04010"), address) @[Conditional.scala 37:30] + when _T_1984 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 328:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1985 = eq(UInt<15>("h04014"), address) @[Conditional.scala 37:30] + when _T_1985 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 329:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1986 = eq(UInt<15>("h04018"), address) @[Conditional.scala 37:30] + when _T_1986 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 330:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1987 = eq(UInt<15>("h0401c"), address) @[Conditional.scala 37:30] + when _T_1987 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 331:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1988 = eq(UInt<15>("h04020"), address) @[Conditional.scala 37:30] + when _T_1988 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 332:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1989 = eq(UInt<15>("h04024"), address) @[Conditional.scala 37:30] + when _T_1989 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 333:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1990 = eq(UInt<15>("h04028"), address) @[Conditional.scala 37:30] + when _T_1990 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 334:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1991 = eq(UInt<15>("h0402c"), address) @[Conditional.scala 37:30] + when _T_1991 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 335:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1992 = eq(UInt<15>("h04030"), address) @[Conditional.scala 37:30] + when _T_1992 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 336:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1993 = eq(UInt<15>("h04034"), address) @[Conditional.scala 37:30] + when _T_1993 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 337:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1994 = eq(UInt<15>("h04038"), address) @[Conditional.scala 37:30] + when _T_1994 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 338:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1995 = eq(UInt<15>("h0403c"), address) @[Conditional.scala 37:30] + when _T_1995 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 339:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1996 = eq(UInt<15>("h04040"), address) @[Conditional.scala 37:30] + when _T_1996 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 340:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1997 = eq(UInt<15>("h04044"), address) @[Conditional.scala 37:30] + when _T_1997 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 341:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1998 = eq(UInt<15>("h04048"), address) @[Conditional.scala 37:30] + when _T_1998 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 342:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_1999 = eq(UInt<15>("h0404c"), address) @[Conditional.scala 37:30] + when _T_1999 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 343:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2000 = eq(UInt<15>("h04050"), address) @[Conditional.scala 37:30] + when _T_2000 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 344:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2001 = eq(UInt<15>("h04054"), address) @[Conditional.scala 37:30] + when _T_2001 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 345:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2002 = eq(UInt<15>("h04058"), address) @[Conditional.scala 37:30] + when _T_2002 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 346:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2003 = eq(UInt<15>("h0405c"), address) @[Conditional.scala 37:30] + when _T_2003 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 347:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2004 = eq(UInt<15>("h04060"), address) @[Conditional.scala 37:30] + when _T_2004 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 348:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2005 = eq(UInt<15>("h04064"), address) @[Conditional.scala 37:30] + when _T_2005 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 349:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2006 = eq(UInt<15>("h04068"), address) @[Conditional.scala 37:30] + when _T_2006 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 350:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2007 = eq(UInt<15>("h0406c"), address) @[Conditional.scala 37:30] + when _T_2007 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 351:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2008 = eq(UInt<15>("h04070"), address) @[Conditional.scala 37:30] + when _T_2008 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 352:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2009 = eq(UInt<15>("h04074"), address) @[Conditional.scala 37:30] + when _T_2009 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 353:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2010 = eq(UInt<15>("h04078"), address) @[Conditional.scala 37:30] + when _T_2010 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 354:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2011 = eq(UInt<15>("h0407c"), address) @[Conditional.scala 37:30] + when _T_2011 : @[Conditional.scala 39:67] + mask <= UInt<4>("h08") @[el2_pic_ctl.scala 355:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2012 = eq(UInt<15>("h02004"), address) @[Conditional.scala 37:30] + when _T_2012 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 356:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2013 = eq(UInt<15>("h02008"), address) @[Conditional.scala 37:30] + when _T_2013 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 357:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2014 = eq(UInt<15>("h0200c"), address) @[Conditional.scala 37:30] + when _T_2014 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 358:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2015 = eq(UInt<15>("h02010"), address) @[Conditional.scala 37:30] + when _T_2015 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 359:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2016 = eq(UInt<15>("h02014"), address) @[Conditional.scala 37:30] + when _T_2016 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 360:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2017 = eq(UInt<15>("h02018"), address) @[Conditional.scala 37:30] + when _T_2017 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 361:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2018 = eq(UInt<15>("h0201c"), address) @[Conditional.scala 37:30] + when _T_2018 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 362:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2019 = eq(UInt<15>("h02020"), address) @[Conditional.scala 37:30] + when _T_2019 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 363:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2020 = eq(UInt<15>("h02024"), address) @[Conditional.scala 37:30] + when _T_2020 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 364:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2021 = eq(UInt<15>("h02028"), address) @[Conditional.scala 37:30] + when _T_2021 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 365:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2022 = eq(UInt<15>("h0202c"), address) @[Conditional.scala 37:30] + when _T_2022 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 366:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2023 = eq(UInt<15>("h02030"), address) @[Conditional.scala 37:30] + when _T_2023 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 367:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2024 = eq(UInt<15>("h02034"), address) @[Conditional.scala 37:30] + when _T_2024 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 368:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2025 = eq(UInt<15>("h02038"), address) @[Conditional.scala 37:30] + when _T_2025 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 369:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2026 = eq(UInt<15>("h0203c"), address) @[Conditional.scala 37:30] + when _T_2026 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 370:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2027 = eq(UInt<15>("h02040"), address) @[Conditional.scala 37:30] + when _T_2027 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 371:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2028 = eq(UInt<15>("h02044"), address) @[Conditional.scala 37:30] + when _T_2028 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 372:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2029 = eq(UInt<15>("h02048"), address) @[Conditional.scala 37:30] + when _T_2029 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 373:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2030 = eq(UInt<15>("h0204c"), address) @[Conditional.scala 37:30] + when _T_2030 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 374:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2031 = eq(UInt<15>("h02050"), address) @[Conditional.scala 37:30] + when _T_2031 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 375:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2032 = eq(UInt<15>("h02054"), address) @[Conditional.scala 37:30] + when _T_2032 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 376:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2033 = eq(UInt<15>("h02058"), address) @[Conditional.scala 37:30] + when _T_2033 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 377:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2034 = eq(UInt<15>("h0205c"), address) @[Conditional.scala 37:30] + when _T_2034 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 378:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2035 = eq(UInt<15>("h02060"), address) @[Conditional.scala 37:30] + when _T_2035 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 379:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2036 = eq(UInt<15>("h02064"), address) @[Conditional.scala 37:30] + when _T_2036 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 380:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2037 = eq(UInt<15>("h02068"), address) @[Conditional.scala 37:30] + when _T_2037 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 381:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2038 = eq(UInt<15>("h0206c"), address) @[Conditional.scala 37:30] + when _T_2038 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 382:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2039 = eq(UInt<15>("h02070"), address) @[Conditional.scala 37:30] + when _T_2039 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 383:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2040 = eq(UInt<15>("h02074"), address) @[Conditional.scala 37:30] + when _T_2040 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 384:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2041 = eq(UInt<15>("h02078"), address) @[Conditional.scala 37:30] + when _T_2041 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 385:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2042 = eq(UInt<15>("h0207c"), address) @[Conditional.scala 37:30] + when _T_2042 : @[Conditional.scala 39:67] + mask <= UInt<4>("h04") @[el2_pic_ctl.scala 386:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2043 = eq(UInt<15>("h04"), address) @[Conditional.scala 37:30] + when _T_2043 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 387:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2044 = eq(UInt<15>("h08"), address) @[Conditional.scala 37:30] + when _T_2044 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 388:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2045 = eq(UInt<15>("h0c"), address) @[Conditional.scala 37:30] + when _T_2045 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 389:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2046 = eq(UInt<15>("h010"), address) @[Conditional.scala 37:30] + when _T_2046 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 390:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2047 = eq(UInt<15>("h014"), address) @[Conditional.scala 37:30] + when _T_2047 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 391:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2048 = eq(UInt<15>("h018"), address) @[Conditional.scala 37:30] + when _T_2048 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 392:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2049 = eq(UInt<15>("h01c"), address) @[Conditional.scala 37:30] + when _T_2049 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 393:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2050 = eq(UInt<15>("h020"), address) @[Conditional.scala 37:30] + when _T_2050 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 394:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2051 = eq(UInt<15>("h024"), address) @[Conditional.scala 37:30] + when _T_2051 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 395:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2052 = eq(UInt<15>("h028"), address) @[Conditional.scala 37:30] + when _T_2052 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 396:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2053 = eq(UInt<15>("h02c"), address) @[Conditional.scala 37:30] + when _T_2053 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 397:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2054 = eq(UInt<15>("h030"), address) @[Conditional.scala 37:30] + when _T_2054 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 398:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2055 = eq(UInt<15>("h034"), address) @[Conditional.scala 37:30] + when _T_2055 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 399:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2056 = eq(UInt<15>("h038"), address) @[Conditional.scala 37:30] + when _T_2056 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 400:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2057 = eq(UInt<15>("h03c"), address) @[Conditional.scala 37:30] + when _T_2057 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 401:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2058 = eq(UInt<15>("h040"), address) @[Conditional.scala 37:30] + when _T_2058 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 402:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2059 = eq(UInt<15>("h044"), address) @[Conditional.scala 37:30] + when _T_2059 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 403:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2060 = eq(UInt<15>("h048"), address) @[Conditional.scala 37:30] + when _T_2060 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 404:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2061 = eq(UInt<15>("h04c"), address) @[Conditional.scala 37:30] + when _T_2061 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 405:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2062 = eq(UInt<15>("h050"), address) @[Conditional.scala 37:30] + when _T_2062 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 406:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2063 = eq(UInt<15>("h054"), address) @[Conditional.scala 37:30] + when _T_2063 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 407:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2064 = eq(UInt<15>("h058"), address) @[Conditional.scala 37:30] + when _T_2064 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 408:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2065 = eq(UInt<15>("h05c"), address) @[Conditional.scala 37:30] + when _T_2065 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 409:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2066 = eq(UInt<15>("h060"), address) @[Conditional.scala 37:30] + when _T_2066 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 410:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2067 = eq(UInt<15>("h064"), address) @[Conditional.scala 37:30] + when _T_2067 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 411:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2068 = eq(UInt<15>("h068"), address) @[Conditional.scala 37:30] + when _T_2068 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 412:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2069 = eq(UInt<15>("h06c"), address) @[Conditional.scala 37:30] + when _T_2069 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 413:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2070 = eq(UInt<15>("h070"), address) @[Conditional.scala 37:30] + when _T_2070 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 414:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2071 = eq(UInt<15>("h074"), address) @[Conditional.scala 37:30] + when _T_2071 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 415:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2072 = eq(UInt<15>("h078"), address) @[Conditional.scala 37:30] + when _T_2072 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 416:44] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_2073 = eq(UInt<15>("h07c"), address) @[Conditional.scala 37:30] + when _T_2073 : @[Conditional.scala 39:67] + mask <= UInt<4>("h02") @[el2_pic_ctl.scala 417:44] + skip @[Conditional.scala 39:67] diff --git a/el2_pic_ctrl.v b/el2_pic_ctrl.v index 9fc02173..cc7309ed 100644 --- a/el2_pic_ctrl.v +++ b/el2_pic_ctrl.v @@ -4,100 +4,20 @@ module rvclkhdr( input io_en, input io_scan_mode ); - wire clkhdr_Q; // @[beh_lib.scala 331:24] - wire clkhdr_CK; // @[beh_lib.scala 331:24] - wire clkhdr_EN; // @[beh_lib.scala 331:24] - wire clkhdr_SE; // @[beh_lib.scala 331:24] - TEC_RV_ICG clkhdr ( // @[beh_lib.scala 331:24] + wire clkhdr_Q; // @[el2_lib.scala 474:26] + wire clkhdr_CK; // @[el2_lib.scala 474:26] + wire clkhdr_EN; // @[el2_lib.scala 474:26] + wire clkhdr_SE; // @[el2_lib.scala 474:26] + gated_latch clkhdr ( // @[el2_lib.scala 474:26] .Q(clkhdr_Q), .CK(clkhdr_CK), .EN(clkhdr_EN), .SE(clkhdr_SE) ); - assign io_l1clk = clkhdr_Q; // @[beh_lib.scala 332:12] - assign clkhdr_CK = io_clk; // @[beh_lib.scala 333:16] - assign clkhdr_EN = io_en; // @[beh_lib.scala 334:16] - assign clkhdr_SE = io_scan_mode; // @[beh_lib.scala 335:16] -endmodule -module rvsyncss( - input reset, - input [30:0] io_din, - output [30:0] io_dout, - input io_clk -); -`ifdef RANDOMIZE_REG_INIT - reg [31:0] _RAND_0; - reg [31:0] _RAND_1; -`endif // RANDOMIZE_REG_INIT - reg [30:0] sync_ff1; // @[beh_lib.scala 32:43] - reg [30:0] sync_ff2; // @[beh_lib.scala 33:43] - assign io_dout = sync_ff2; // @[beh_lib.scala 37:12] -`ifdef RANDOMIZE_GARBAGE_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_INVALID_ASSIGN -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_REG_INIT -`define RANDOMIZE -`endif -`ifdef RANDOMIZE_MEM_INIT -`define RANDOMIZE -`endif -`ifndef RANDOM -`define RANDOM $random -`endif -`ifdef RANDOMIZE_MEM_INIT - integer initvar; -`endif -`ifndef SYNTHESIS -`ifdef FIRRTL_BEFORE_INITIAL -`FIRRTL_BEFORE_INITIAL -`endif -initial begin - `ifdef RANDOMIZE - `ifdef INIT_RANDOM - `INIT_RANDOM - `endif - `ifndef VERILATOR - `ifdef RANDOMIZE_DELAY - #`RANDOMIZE_DELAY begin end - `else - #0.002 begin end - `endif - `endif -`ifdef RANDOMIZE_REG_INIT - _RAND_0 = {1{`RANDOM}}; - sync_ff1 = _RAND_0[30:0]; - _RAND_1 = {1{`RANDOM}}; - sync_ff2 = _RAND_1[30:0]; -`endif // RANDOMIZE_REG_INIT - if (reset) begin - sync_ff1 = 31'h0; - end - if (reset) begin - sync_ff2 = 31'h0; - end - `endif // RANDOMIZE -end // initial -`ifdef FIRRTL_AFTER_INITIAL -`FIRRTL_AFTER_INITIAL -`endif -`endif // SYNTHESIS - always @(posedge io_clk or posedge reset) begin - if (reset) begin - sync_ff1 <= 31'h0; - end else begin - sync_ff1 <= io_din; - end - end - always @(posedge io_clk or posedge reset) begin - if (reset) begin - sync_ff2 <= 31'h0; - end else begin - sync_ff2 <= sync_ff1; - end - end + assign io_l1clk = clkhdr_Q; // @[el2_lib.scala 475:14] + assign clkhdr_CK = io_clk; // @[el2_lib.scala 476:18] + assign clkhdr_EN = io_en; // @[el2_lib.scala 477:18] + assign clkhdr_SE = io_scan_mode; // @[el2_lib.scala 478:18] endmodule module el2_pic_ctrl( input clock, @@ -119,8 +39,7 @@ module el2_pic_ctrl( output [7:0] io_claimid, output [3:0] io_pl, output [31:0] io_picm_rd_data, - output io_mhwakeup, - output [31:0] io_test + output io_mhwakeup ); `ifdef RANDOMIZE_REG_INIT reg [31:0] _RAND_0; @@ -131,120 +50,1854 @@ module el2_pic_ctrl( reg [31:0] _RAND_5; reg [31:0] _RAND_6; reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [31:0] _RAND_17; + reg [31:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; + reg [31:0] _RAND_26; + reg [31:0] _RAND_27; + reg [31:0] _RAND_28; + reg [31:0] _RAND_29; + reg [31:0] _RAND_30; + reg [31:0] _RAND_31; + reg [31:0] _RAND_32; + reg [31:0] _RAND_33; + reg [31:0] _RAND_34; + reg [31:0] _RAND_35; + reg [31:0] _RAND_36; + reg [31:0] _RAND_37; + reg [31:0] _RAND_38; + reg [31:0] _RAND_39; + reg [31:0] _RAND_40; + reg [31:0] _RAND_41; + reg [31:0] _RAND_42; + reg [31:0] _RAND_43; + reg [31:0] _RAND_44; + reg [31:0] _RAND_45; + reg [31:0] _RAND_46; + reg [31:0] _RAND_47; + reg [31:0] _RAND_48; + reg [31:0] _RAND_49; + reg [31:0] _RAND_50; + reg [31:0] _RAND_51; + reg [31:0] _RAND_52; + reg [31:0] _RAND_53; + reg [31:0] _RAND_54; + reg [31:0] _RAND_55; + reg [31:0] _RAND_56; + reg [31:0] _RAND_57; + reg [31:0] _RAND_58; + reg [31:0] _RAND_59; + reg [31:0] _RAND_60; + reg [31:0] _RAND_61; + reg [31:0] _RAND_62; + reg [31:0] _RAND_63; + reg [31:0] _RAND_64; + reg [31:0] _RAND_65; + reg [31:0] _RAND_66; + reg [31:0] _RAND_67; + reg [31:0] _RAND_68; + reg [31:0] _RAND_69; + reg [31:0] _RAND_70; + reg [31:0] _RAND_71; + reg [31:0] _RAND_72; + reg [31:0] _RAND_73; + reg [31:0] _RAND_74; + reg [31:0] _RAND_75; + reg [31:0] _RAND_76; + reg [31:0] _RAND_77; + reg [31:0] _RAND_78; + reg [31:0] _RAND_79; + reg [31:0] _RAND_80; + reg [31:0] _RAND_81; + reg [31:0] _RAND_82; + reg [31:0] _RAND_83; + reg [31:0] _RAND_84; + reg [31:0] _RAND_85; + reg [31:0] _RAND_86; + reg [31:0] _RAND_87; + reg [31:0] _RAND_88; + reg [31:0] _RAND_89; + reg [31:0] _RAND_90; + reg [31:0] _RAND_91; + reg [31:0] _RAND_92; + reg [31:0] _RAND_93; + reg [31:0] _RAND_94; + reg [31:0] _RAND_95; + reg [31:0] _RAND_96; + reg [31:0] _RAND_97; + reg [31:0] _RAND_98; + reg [31:0] _RAND_99; + reg [31:0] _RAND_100; + reg [31:0] _RAND_101; + reg [31:0] _RAND_102; + reg [31:0] _RAND_103; + reg [31:0] _RAND_104; + reg [31:0] _RAND_105; + reg [31:0] _RAND_106; + reg [31:0] _RAND_107; + reg [31:0] _RAND_108; + reg [31:0] _RAND_109; + reg [31:0] _RAND_110; + reg [31:0] _RAND_111; + reg [31:0] _RAND_112; + reg [31:0] _RAND_113; + reg [31:0] _RAND_114; + reg [31:0] _RAND_115; + reg [31:0] _RAND_116; + reg [31:0] _RAND_117; + reg [31:0] _RAND_118; + reg [31:0] _RAND_119; + reg [31:0] _RAND_120; + reg [31:0] _RAND_121; + reg [31:0] _RAND_122; + reg [31:0] _RAND_123; + reg [31:0] _RAND_124; + reg [31:0] _RAND_125; + reg [31:0] _RAND_126; + reg [31:0] _RAND_127; + reg [31:0] _RAND_128; + reg [31:0] _RAND_129; + reg [31:0] _RAND_130; + reg [31:0] _RAND_131; + reg [31:0] _RAND_132; + reg [31:0] _RAND_133; + reg [31:0] _RAND_134; + reg [31:0] _RAND_135; + reg [31:0] _RAND_136; `endif // RANDOMIZE_REG_INIT - wire pic_addr_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 162:32] - wire pic_addr_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 162:32] - wire pic_addr_c1_cgc_io_en; // @[el2_pic_ctrl.scala 162:32] - wire pic_addr_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 162:32] - wire pic_data_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 166:32] - wire pic_data_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 166:32] - wire pic_data_c1_cgc_io_en; // @[el2_pic_ctrl.scala 166:32] - wire pic_data_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 166:32] - wire pic_pri_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 170:31] - wire pic_pri_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 170:31] - wire pic_pri_c1_cgc_io_en; // @[el2_pic_ctrl.scala 170:31] - wire pic_pri_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 170:31] - wire pic_int_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 174:32] - wire pic_int_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 174:32] - wire pic_int_c1_cgc_io_en; // @[el2_pic_ctrl.scala 174:32] - wire pic_int_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 174:32] - wire gw_config_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 178:33] - wire gw_config_c1_cgc_io_clk; // @[el2_pic_ctrl.scala 178:33] - wire gw_config_c1_cgc_io_en; // @[el2_pic_ctrl.scala 178:33] - wire gw_config_c1_cgc_io_scan_mode; // @[el2_pic_ctrl.scala 178:33] - wire sync_inst_reset; // @[el2_pic_ctrl.scala 185:26] - wire [30:0] sync_inst_io_din; // @[el2_pic_ctrl.scala 185:26] - wire [30:0] sync_inst_io_dout; // @[el2_pic_ctrl.scala 185:26] - wire sync_inst_io_clk; // @[el2_pic_ctrl.scala 185:26] - wire pic_raddr_c1_clk = pic_addr_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 127:42 el2_pic_ctrl.scala 163:89] - reg [31:0] picm_raddr_ff; // @[el2_pic_ctrl.scala 133:56] - wire pic_data_c1_clk = pic_data_c1_cgc_io_l1clk; // @[el2_pic_ctrl.scala 128:42 el2_pic_ctrl.scala 167:89] - reg [31:0] picm_waddr_ff; // @[el2_pic_ctrl.scala 134:57] - reg picm_wren_ff; // @[el2_pic_ctrl.scala 135:55] - reg picm_rden_ff; // @[el2_pic_ctrl.scala 136:55] - reg [31:0] picm_wr_data_ff; // @[el2_pic_ctrl.scala 138:58] - wire raddr_intenable_base_match = picm_raddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctrl.scala 140:71] - wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctrl.scala 141:71] - wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctrl.scala 142:71] - wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctrl.scala 146:71] - wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctrl.scala 148:71] - wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctrl.scala 150:71] - wire _T_18 = io_picm_mken | io_picm_rden; // @[el2_pic_ctrl.scala 155:42] - wire _T_19 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctrl.scala 157:59] - wire _T_20 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 157:108] - wire _T_21 = _T_19 | _T_20; // @[el2_pic_ctrl.scala 157:76] - wire _T_23 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 158:106] - wire _T_24 = _T_19 | _T_23; // @[el2_pic_ctrl.scala 158:76] - wire _T_25 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctrl.scala 159:59] - wire _T_26 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctrl.scala 159:108] - wire _T_27 = _T_25 | _T_26; // @[el2_pic_ctrl.scala 159:76] - wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctrl.scala 195:47] - wire config_reg_in = picm_wr_data_ff[0]; // @[el2_pic_ctrl.scala 197:39] + wire rvclkhdr_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_1_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_2_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_3_io_scan_mode; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_l1clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_clk; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_en; // @[el2_lib.scala 483:22] + wire rvclkhdr_4_io_scan_mode; // @[el2_lib.scala 483:22] + wire pic_raddr_c1_clk = rvclkhdr_io_l1clk; // @[el2_pic_ctl.scala 109:42 el2_pic_ctl.scala 146:21] + reg [31:0] picm_raddr_ff; // @[el2_pic_ctl.scala 115:56] + wire pic_data_c1_clk = rvclkhdr_1_io_l1clk; // @[el2_pic_ctl.scala 110:42 el2_pic_ctl.scala 147:21] + reg [31:0] picm_waddr_ff; // @[el2_pic_ctl.scala 116:57] + reg picm_wren_ff; // @[el2_pic_ctl.scala 117:55] + reg picm_rden_ff; // @[el2_pic_ctl.scala 118:55] + reg picm_mken_ff; // @[el2_pic_ctl.scala 119:55] + reg [31:0] picm_wr_data_ff; // @[el2_pic_ctl.scala 120:58] + wire [31:0] _T_6 = picm_raddr_ff ^ 32'hf00c2000; // @[el2_pic_ctl.scala 122:59] + wire [31:0] temp_raddr_intenable_base_match = ~_T_6; // @[el2_pic_ctl.scala 122:43] + wire raddr_intenable_base_match = &temp_raddr_intenable_base_match[31:7]; // @[el2_pic_ctl.scala 123:89] + wire raddr_intpriority_base_match = picm_raddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 125:71] + wire raddr_config_gw_base_match = picm_raddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 126:71] + wire raddr_config_pic_match = picm_raddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 127:71] + wire addr_intpend_base_match = picm_raddr_ff[31:6] == 26'h3c03040; // @[el2_pic_ctl.scala 128:71] + wire waddr_config_pic_match = picm_waddr_ff == 32'hf00c3000; // @[el2_pic_ctl.scala 130:71] + wire addr_clear_gw_base_match = picm_waddr_ff[31:7] == 25'h1e018a0; // @[el2_pic_ctl.scala 131:71] + wire waddr_intpriority_base_match = picm_waddr_ff[31:7] == 25'h1e01800; // @[el2_pic_ctl.scala 132:71] + wire waddr_intenable_base_match = picm_waddr_ff[31:7] == 25'h1e01840; // @[el2_pic_ctl.scala 133:71] + wire waddr_config_gw_base_match = picm_waddr_ff[31:7] == 25'h1e01880; // @[el2_pic_ctl.scala 134:71] + wire _T_17 = picm_rden_ff & picm_wren_ff; // @[el2_pic_ctl.scala 135:53] + wire _T_18 = picm_raddr_ff == picm_waddr_ff; // @[el2_pic_ctl.scala 135:86] + wire picm_bypass_ff = _T_17 & _T_18; // @[el2_pic_ctl.scala 135:68] + wire _T_19 = io_picm_mken | io_picm_rden; // @[el2_pic_ctl.scala 139:42] + wire _T_20 = waddr_intpriority_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 141:59] + wire _T_21 = raddr_intpriority_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 141:108] + wire _T_22 = _T_20 | _T_21; // @[el2_pic_ctl.scala 141:76] + wire _T_23 = waddr_intenable_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 142:57] + wire _T_24 = raddr_intenable_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 142:104] + wire _T_25 = _T_23 | _T_24; // @[el2_pic_ctl.scala 142:74] + wire _T_26 = waddr_config_gw_base_match & picm_wren_ff; // @[el2_pic_ctl.scala 143:59] + wire _T_27 = raddr_config_gw_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 143:108] + wire _T_28 = _T_26 | _T_27; // @[el2_pic_ctl.scala 143:76] + reg [30:0] _T_33; // @[el2_lib.scala 176:81] + reg [30:0] _T_34; // @[el2_lib.scala 176:58] + wire [31:0] extintsrc_req_sync = {_T_34,io_extintsrc_req[0]}; // @[Cat.scala 29:58] + wire _T_37 = picm_waddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 155:139] + wire _T_38 = waddr_intpriority_base_match & _T_37; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_1 = _T_38 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_40 = picm_waddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 155:139] + wire _T_41 = waddr_intpriority_base_match & _T_40; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_2 = _T_41 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_43 = picm_waddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 155:139] + wire _T_44 = waddr_intpriority_base_match & _T_43; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_3 = _T_44 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_46 = picm_waddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 155:139] + wire _T_47 = waddr_intpriority_base_match & _T_46; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_4 = _T_47 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_49 = picm_waddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 155:139] + wire _T_50 = waddr_intpriority_base_match & _T_49; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_5 = _T_50 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_52 = picm_waddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 155:139] + wire _T_53 = waddr_intpriority_base_match & _T_52; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_6 = _T_53 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_55 = picm_waddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 155:139] + wire _T_56 = waddr_intpriority_base_match & _T_55; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_7 = _T_56 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_58 = picm_waddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 155:139] + wire _T_59 = waddr_intpriority_base_match & _T_58; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_8 = _T_59 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_61 = picm_waddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 155:139] + wire _T_62 = waddr_intpriority_base_match & _T_61; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_9 = _T_62 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_64 = picm_waddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 155:139] + wire _T_65 = waddr_intpriority_base_match & _T_64; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_10 = _T_65 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_67 = picm_waddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 155:139] + wire _T_68 = waddr_intpriority_base_match & _T_67; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_11 = _T_68 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_70 = picm_waddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 155:139] + wire _T_71 = waddr_intpriority_base_match & _T_70; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_12 = _T_71 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_73 = picm_waddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 155:139] + wire _T_74 = waddr_intpriority_base_match & _T_73; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_13 = _T_74 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_76 = picm_waddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 155:139] + wire _T_77 = waddr_intpriority_base_match & _T_76; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_14 = _T_77 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_79 = picm_waddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 155:139] + wire _T_80 = waddr_intpriority_base_match & _T_79; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_15 = _T_80 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_82 = picm_waddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 155:139] + wire _T_83 = waddr_intpriority_base_match & _T_82; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_16 = _T_83 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_85 = picm_waddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 155:139] + wire _T_86 = waddr_intpriority_base_match & _T_85; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_17 = _T_86 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_88 = picm_waddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 155:139] + wire _T_89 = waddr_intpriority_base_match & _T_88; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_18 = _T_89 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_91 = picm_waddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 155:139] + wire _T_92 = waddr_intpriority_base_match & _T_91; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_19 = _T_92 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_94 = picm_waddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 155:139] + wire _T_95 = waddr_intpriority_base_match & _T_94; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_20 = _T_95 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_97 = picm_waddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 155:139] + wire _T_98 = waddr_intpriority_base_match & _T_97; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_21 = _T_98 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_100 = picm_waddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 155:139] + wire _T_101 = waddr_intpriority_base_match & _T_100; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_22 = _T_101 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_103 = picm_waddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 155:139] + wire _T_104 = waddr_intpriority_base_match & _T_103; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_23 = _T_104 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_106 = picm_waddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 155:139] + wire _T_107 = waddr_intpriority_base_match & _T_106; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_24 = _T_107 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_109 = picm_waddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 155:139] + wire _T_110 = waddr_intpriority_base_match & _T_109; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_25 = _T_110 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_112 = picm_waddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 155:139] + wire _T_113 = waddr_intpriority_base_match & _T_112; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_26 = _T_113 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_115 = picm_waddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 155:139] + wire _T_116 = waddr_intpriority_base_match & _T_115; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_27 = _T_116 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_118 = picm_waddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 155:139] + wire _T_119 = waddr_intpriority_base_match & _T_118; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_28 = _T_119 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_121 = picm_waddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 155:139] + wire _T_122 = waddr_intpriority_base_match & _T_121; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_29 = _T_122 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_124 = picm_waddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 155:139] + wire _T_125 = waddr_intpriority_base_match & _T_124; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_30 = _T_125 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_127 = picm_waddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 155:139] + wire _T_128 = waddr_intpriority_base_match & _T_127; // @[el2_pic_ctl.scala 155:106] + wire intpriority_reg_we_31 = _T_128 & picm_wren_ff; // @[el2_pic_ctl.scala 155:153] + wire _T_130 = picm_raddr_ff[6:2] == 5'h1; // @[el2_pic_ctl.scala 156:139] + wire _T_131 = raddr_intpriority_base_match & _T_130; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_1 = _T_131 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_133 = picm_raddr_ff[6:2] == 5'h2; // @[el2_pic_ctl.scala 156:139] + wire _T_134 = raddr_intpriority_base_match & _T_133; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_2 = _T_134 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_136 = picm_raddr_ff[6:2] == 5'h3; // @[el2_pic_ctl.scala 156:139] + wire _T_137 = raddr_intpriority_base_match & _T_136; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_3 = _T_137 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_139 = picm_raddr_ff[6:2] == 5'h4; // @[el2_pic_ctl.scala 156:139] + wire _T_140 = raddr_intpriority_base_match & _T_139; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_4 = _T_140 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_142 = picm_raddr_ff[6:2] == 5'h5; // @[el2_pic_ctl.scala 156:139] + wire _T_143 = raddr_intpriority_base_match & _T_142; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_5 = _T_143 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_145 = picm_raddr_ff[6:2] == 5'h6; // @[el2_pic_ctl.scala 156:139] + wire _T_146 = raddr_intpriority_base_match & _T_145; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_6 = _T_146 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_148 = picm_raddr_ff[6:2] == 5'h7; // @[el2_pic_ctl.scala 156:139] + wire _T_149 = raddr_intpriority_base_match & _T_148; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_7 = _T_149 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_151 = picm_raddr_ff[6:2] == 5'h8; // @[el2_pic_ctl.scala 156:139] + wire _T_152 = raddr_intpriority_base_match & _T_151; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_8 = _T_152 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_154 = picm_raddr_ff[6:2] == 5'h9; // @[el2_pic_ctl.scala 156:139] + wire _T_155 = raddr_intpriority_base_match & _T_154; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_9 = _T_155 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_157 = picm_raddr_ff[6:2] == 5'ha; // @[el2_pic_ctl.scala 156:139] + wire _T_158 = raddr_intpriority_base_match & _T_157; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_10 = _T_158 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_160 = picm_raddr_ff[6:2] == 5'hb; // @[el2_pic_ctl.scala 156:139] + wire _T_161 = raddr_intpriority_base_match & _T_160; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_11 = _T_161 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_163 = picm_raddr_ff[6:2] == 5'hc; // @[el2_pic_ctl.scala 156:139] + wire _T_164 = raddr_intpriority_base_match & _T_163; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_12 = _T_164 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_166 = picm_raddr_ff[6:2] == 5'hd; // @[el2_pic_ctl.scala 156:139] + wire _T_167 = raddr_intpriority_base_match & _T_166; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_13 = _T_167 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_169 = picm_raddr_ff[6:2] == 5'he; // @[el2_pic_ctl.scala 156:139] + wire _T_170 = raddr_intpriority_base_match & _T_169; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_14 = _T_170 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_172 = picm_raddr_ff[6:2] == 5'hf; // @[el2_pic_ctl.scala 156:139] + wire _T_173 = raddr_intpriority_base_match & _T_172; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_15 = _T_173 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_175 = picm_raddr_ff[6:2] == 5'h10; // @[el2_pic_ctl.scala 156:139] + wire _T_176 = raddr_intpriority_base_match & _T_175; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_16 = _T_176 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_178 = picm_raddr_ff[6:2] == 5'h11; // @[el2_pic_ctl.scala 156:139] + wire _T_179 = raddr_intpriority_base_match & _T_178; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_17 = _T_179 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_181 = picm_raddr_ff[6:2] == 5'h12; // @[el2_pic_ctl.scala 156:139] + wire _T_182 = raddr_intpriority_base_match & _T_181; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_18 = _T_182 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_184 = picm_raddr_ff[6:2] == 5'h13; // @[el2_pic_ctl.scala 156:139] + wire _T_185 = raddr_intpriority_base_match & _T_184; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_19 = _T_185 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_187 = picm_raddr_ff[6:2] == 5'h14; // @[el2_pic_ctl.scala 156:139] + wire _T_188 = raddr_intpriority_base_match & _T_187; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_20 = _T_188 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_190 = picm_raddr_ff[6:2] == 5'h15; // @[el2_pic_ctl.scala 156:139] + wire _T_191 = raddr_intpriority_base_match & _T_190; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_21 = _T_191 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_193 = picm_raddr_ff[6:2] == 5'h16; // @[el2_pic_ctl.scala 156:139] + wire _T_194 = raddr_intpriority_base_match & _T_193; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_22 = _T_194 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_196 = picm_raddr_ff[6:2] == 5'h17; // @[el2_pic_ctl.scala 156:139] + wire _T_197 = raddr_intpriority_base_match & _T_196; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_23 = _T_197 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_199 = picm_raddr_ff[6:2] == 5'h18; // @[el2_pic_ctl.scala 156:139] + wire _T_200 = raddr_intpriority_base_match & _T_199; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_24 = _T_200 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_202 = picm_raddr_ff[6:2] == 5'h19; // @[el2_pic_ctl.scala 156:139] + wire _T_203 = raddr_intpriority_base_match & _T_202; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_25 = _T_203 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_205 = picm_raddr_ff[6:2] == 5'h1a; // @[el2_pic_ctl.scala 156:139] + wire _T_206 = raddr_intpriority_base_match & _T_205; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_26 = _T_206 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_208 = picm_raddr_ff[6:2] == 5'h1b; // @[el2_pic_ctl.scala 156:139] + wire _T_209 = raddr_intpriority_base_match & _T_208; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_27 = _T_209 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_211 = picm_raddr_ff[6:2] == 5'h1c; // @[el2_pic_ctl.scala 156:139] + wire _T_212 = raddr_intpriority_base_match & _T_211; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_28 = _T_212 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_214 = picm_raddr_ff[6:2] == 5'h1d; // @[el2_pic_ctl.scala 156:139] + wire _T_215 = raddr_intpriority_base_match & _T_214; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_29 = _T_215 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_217 = picm_raddr_ff[6:2] == 5'h1e; // @[el2_pic_ctl.scala 156:139] + wire _T_218 = raddr_intpriority_base_match & _T_217; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_30 = _T_218 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_220 = picm_raddr_ff[6:2] == 5'h1f; // @[el2_pic_ctl.scala 156:139] + wire _T_221 = raddr_intpriority_base_match & _T_220; // @[el2_pic_ctl.scala 156:106] + wire intpriority_reg_re_31 = _T_221 & picm_rden_ff; // @[el2_pic_ctl.scala 156:153] + wire _T_224 = waddr_intenable_base_match & _T_37; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_1 = _T_224 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_227 = waddr_intenable_base_match & _T_40; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_2 = _T_227 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_230 = waddr_intenable_base_match & _T_43; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_3 = _T_230 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_233 = waddr_intenable_base_match & _T_46; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_4 = _T_233 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_236 = waddr_intenable_base_match & _T_49; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_5 = _T_236 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_239 = waddr_intenable_base_match & _T_52; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_6 = _T_239 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_242 = waddr_intenable_base_match & _T_55; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_7 = _T_242 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_245 = waddr_intenable_base_match & _T_58; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_8 = _T_245 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_248 = waddr_intenable_base_match & _T_61; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_9 = _T_248 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_251 = waddr_intenable_base_match & _T_64; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_10 = _T_251 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_254 = waddr_intenable_base_match & _T_67; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_11 = _T_254 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_257 = waddr_intenable_base_match & _T_70; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_12 = _T_257 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_260 = waddr_intenable_base_match & _T_73; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_13 = _T_260 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_263 = waddr_intenable_base_match & _T_76; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_14 = _T_263 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_266 = waddr_intenable_base_match & _T_79; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_15 = _T_266 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_269 = waddr_intenable_base_match & _T_82; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_16 = _T_269 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_272 = waddr_intenable_base_match & _T_85; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_17 = _T_272 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_275 = waddr_intenable_base_match & _T_88; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_18 = _T_275 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_278 = waddr_intenable_base_match & _T_91; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_19 = _T_278 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_281 = waddr_intenable_base_match & _T_94; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_20 = _T_281 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_284 = waddr_intenable_base_match & _T_97; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_21 = _T_284 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_287 = waddr_intenable_base_match & _T_100; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_22 = _T_287 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_290 = waddr_intenable_base_match & _T_103; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_23 = _T_290 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_293 = waddr_intenable_base_match & _T_106; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_24 = _T_293 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_296 = waddr_intenable_base_match & _T_109; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_25 = _T_296 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_299 = waddr_intenable_base_match & _T_112; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_26 = _T_299 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_302 = waddr_intenable_base_match & _T_115; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_27 = _T_302 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_305 = waddr_intenable_base_match & _T_118; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_28 = _T_305 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_308 = waddr_intenable_base_match & _T_121; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_29 = _T_308 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_311 = waddr_intenable_base_match & _T_124; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_30 = _T_311 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_314 = waddr_intenable_base_match & _T_127; // @[el2_pic_ctl.scala 157:106] + wire intenable_reg_we_31 = _T_314 & picm_wren_ff; // @[el2_pic_ctl.scala 157:153] + wire _T_407 = raddr_intenable_base_match & _T_220; // @[el2_pic_ctl.scala 158:106] + wire intenable_reg_re_31 = _T_407 & picm_rden_ff; // @[el2_pic_ctl.scala 158:153] + wire _T_410 = waddr_config_gw_base_match & _T_37; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_1 = _T_410 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_413 = waddr_config_gw_base_match & _T_40; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_2 = _T_413 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_416 = waddr_config_gw_base_match & _T_43; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_3 = _T_416 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_419 = waddr_config_gw_base_match & _T_46; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_4 = _T_419 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_422 = waddr_config_gw_base_match & _T_49; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_5 = _T_422 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_425 = waddr_config_gw_base_match & _T_52; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_6 = _T_425 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_428 = waddr_config_gw_base_match & _T_55; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_7 = _T_428 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_431 = waddr_config_gw_base_match & _T_58; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_8 = _T_431 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_434 = waddr_config_gw_base_match & _T_61; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_9 = _T_434 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_437 = waddr_config_gw_base_match & _T_64; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_10 = _T_437 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_440 = waddr_config_gw_base_match & _T_67; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_11 = _T_440 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_443 = waddr_config_gw_base_match & _T_70; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_12 = _T_443 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_446 = waddr_config_gw_base_match & _T_73; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_13 = _T_446 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_449 = waddr_config_gw_base_match & _T_76; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_14 = _T_449 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_452 = waddr_config_gw_base_match & _T_79; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_15 = _T_452 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_455 = waddr_config_gw_base_match & _T_82; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_16 = _T_455 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_458 = waddr_config_gw_base_match & _T_85; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_17 = _T_458 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_461 = waddr_config_gw_base_match & _T_88; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_18 = _T_461 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_464 = waddr_config_gw_base_match & _T_91; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_19 = _T_464 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_467 = waddr_config_gw_base_match & _T_94; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_20 = _T_467 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_470 = waddr_config_gw_base_match & _T_97; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_21 = _T_470 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_473 = waddr_config_gw_base_match & _T_100; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_22 = _T_473 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_476 = waddr_config_gw_base_match & _T_103; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_23 = _T_476 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_479 = waddr_config_gw_base_match & _T_106; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_24 = _T_479 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_482 = waddr_config_gw_base_match & _T_109; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_25 = _T_482 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_485 = waddr_config_gw_base_match & _T_112; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_26 = _T_485 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_488 = waddr_config_gw_base_match & _T_115; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_27 = _T_488 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_491 = waddr_config_gw_base_match & _T_118; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_28 = _T_491 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_494 = waddr_config_gw_base_match & _T_121; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_29 = _T_494 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_497 = waddr_config_gw_base_match & _T_124; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_30 = _T_497 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_500 = waddr_config_gw_base_match & _T_127; // @[el2_pic_ctl.scala 159:106] + wire gw_config_reg_we_31 = _T_500 & picm_wren_ff; // @[el2_pic_ctl.scala 159:153] + wire _T_503 = raddr_config_gw_base_match & _T_130; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_1 = _T_503 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_506 = raddr_config_gw_base_match & _T_133; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_2 = _T_506 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_509 = raddr_config_gw_base_match & _T_136; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_3 = _T_509 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_512 = raddr_config_gw_base_match & _T_139; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_4 = _T_512 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_515 = raddr_config_gw_base_match & _T_142; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_5 = _T_515 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_518 = raddr_config_gw_base_match & _T_145; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_6 = _T_518 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_521 = raddr_config_gw_base_match & _T_148; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_7 = _T_521 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_524 = raddr_config_gw_base_match & _T_151; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_8 = _T_524 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_527 = raddr_config_gw_base_match & _T_154; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_9 = _T_527 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_530 = raddr_config_gw_base_match & _T_157; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_10 = _T_530 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_533 = raddr_config_gw_base_match & _T_160; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_11 = _T_533 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_536 = raddr_config_gw_base_match & _T_163; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_12 = _T_536 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_539 = raddr_config_gw_base_match & _T_166; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_13 = _T_539 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_542 = raddr_config_gw_base_match & _T_169; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_14 = _T_542 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_545 = raddr_config_gw_base_match & _T_172; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_15 = _T_545 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_548 = raddr_config_gw_base_match & _T_175; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_16 = _T_548 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_551 = raddr_config_gw_base_match & _T_178; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_17 = _T_551 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_554 = raddr_config_gw_base_match & _T_181; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_18 = _T_554 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_557 = raddr_config_gw_base_match & _T_184; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_19 = _T_557 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_560 = raddr_config_gw_base_match & _T_187; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_20 = _T_560 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_563 = raddr_config_gw_base_match & _T_190; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_21 = _T_563 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_566 = raddr_config_gw_base_match & _T_193; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_22 = _T_566 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_569 = raddr_config_gw_base_match & _T_196; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_23 = _T_569 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_572 = raddr_config_gw_base_match & _T_199; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_24 = _T_572 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_575 = raddr_config_gw_base_match & _T_202; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_25 = _T_575 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_578 = raddr_config_gw_base_match & _T_205; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_26 = _T_578 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_581 = raddr_config_gw_base_match & _T_208; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_27 = _T_581 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_584 = raddr_config_gw_base_match & _T_211; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_28 = _T_584 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_587 = raddr_config_gw_base_match & _T_214; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_29 = _T_587 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_590 = raddr_config_gw_base_match & _T_217; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_30 = _T_590 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_593 = raddr_config_gw_base_match & _T_220; // @[el2_pic_ctl.scala 160:106] + wire gw_config_reg_re_31 = _T_593 & picm_rden_ff; // @[el2_pic_ctl.scala 160:153] + wire _T_596 = addr_clear_gw_base_match & _T_37; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_1 = _T_596 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_599 = addr_clear_gw_base_match & _T_40; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_2 = _T_599 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_602 = addr_clear_gw_base_match & _T_43; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_3 = _T_602 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_605 = addr_clear_gw_base_match & _T_46; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_4 = _T_605 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_608 = addr_clear_gw_base_match & _T_49; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_5 = _T_608 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_611 = addr_clear_gw_base_match & _T_52; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_6 = _T_611 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_614 = addr_clear_gw_base_match & _T_55; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_7 = _T_614 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_617 = addr_clear_gw_base_match & _T_58; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_8 = _T_617 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_620 = addr_clear_gw_base_match & _T_61; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_9 = _T_620 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_623 = addr_clear_gw_base_match & _T_64; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_10 = _T_623 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_626 = addr_clear_gw_base_match & _T_67; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_11 = _T_626 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_629 = addr_clear_gw_base_match & _T_70; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_12 = _T_629 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_632 = addr_clear_gw_base_match & _T_73; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_13 = _T_632 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_635 = addr_clear_gw_base_match & _T_76; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_14 = _T_635 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_638 = addr_clear_gw_base_match & _T_79; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_15 = _T_638 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_641 = addr_clear_gw_base_match & _T_82; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_16 = _T_641 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_644 = addr_clear_gw_base_match & _T_85; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_17 = _T_644 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_647 = addr_clear_gw_base_match & _T_88; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_18 = _T_647 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_650 = addr_clear_gw_base_match & _T_91; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_19 = _T_650 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_653 = addr_clear_gw_base_match & _T_94; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_20 = _T_653 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_656 = addr_clear_gw_base_match & _T_97; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_21 = _T_656 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_659 = addr_clear_gw_base_match & _T_100; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_22 = _T_659 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_662 = addr_clear_gw_base_match & _T_103; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_23 = _T_662 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_665 = addr_clear_gw_base_match & _T_106; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_24 = _T_665 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_668 = addr_clear_gw_base_match & _T_109; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_25 = _T_668 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_671 = addr_clear_gw_base_match & _T_112; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_26 = _T_671 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_674 = addr_clear_gw_base_match & _T_115; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_27 = _T_674 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_677 = addr_clear_gw_base_match & _T_118; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_28 = _T_677 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_680 = addr_clear_gw_base_match & _T_121; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_29 = _T_680 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_683 = addr_clear_gw_base_match & _T_124; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_30 = _T_683 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire _T_686 = addr_clear_gw_base_match & _T_127; // @[el2_pic_ctl.scala 161:106] + wire gw_clear_reg_we_31 = _T_686 & picm_wren_ff; // @[el2_pic_ctl.scala 161:153] + wire pic_pri_c1_clk = rvclkhdr_2_io_l1clk; // @[el2_pic_ctl.scala 111:42 el2_pic_ctl.scala 148:21] + reg [3:0] intpriority_reg_1; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_2; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_3; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_4; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_5; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_6; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_7; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_8; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_9; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_10; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_11; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_12; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_13; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_14; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_15; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_16; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_17; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_18; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_19; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_20; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_21; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_22; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_23; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_24; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_25; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_26; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_27; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_28; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_29; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_30; // @[Reg.scala 27:20] + reg [3:0] intpriority_reg_31; // @[Reg.scala 27:20] + wire pic_int_c1_clk = rvclkhdr_3_io_l1clk; // @[el2_pic_ctl.scala 112:42 el2_pic_ctl.scala 149:21] + reg intenable_reg_1; // @[Reg.scala 27:20] + reg intenable_reg_2; // @[Reg.scala 27:20] + reg intenable_reg_3; // @[Reg.scala 27:20] + reg intenable_reg_4; // @[Reg.scala 27:20] + reg intenable_reg_5; // @[Reg.scala 27:20] + reg intenable_reg_6; // @[Reg.scala 27:20] + reg intenable_reg_7; // @[Reg.scala 27:20] + reg intenable_reg_8; // @[Reg.scala 27:20] + reg intenable_reg_9; // @[Reg.scala 27:20] + reg intenable_reg_10; // @[Reg.scala 27:20] + reg intenable_reg_11; // @[Reg.scala 27:20] + reg intenable_reg_12; // @[Reg.scala 27:20] + reg intenable_reg_13; // @[Reg.scala 27:20] + reg intenable_reg_14; // @[Reg.scala 27:20] + reg intenable_reg_15; // @[Reg.scala 27:20] + reg intenable_reg_16; // @[Reg.scala 27:20] + reg intenable_reg_17; // @[Reg.scala 27:20] + reg intenable_reg_18; // @[Reg.scala 27:20] + reg intenable_reg_19; // @[Reg.scala 27:20] + reg intenable_reg_20; // @[Reg.scala 27:20] + reg intenable_reg_21; // @[Reg.scala 27:20] + reg intenable_reg_22; // @[Reg.scala 27:20] + reg intenable_reg_23; // @[Reg.scala 27:20] + reg intenable_reg_24; // @[Reg.scala 27:20] + reg intenable_reg_25; // @[Reg.scala 27:20] + reg intenable_reg_26; // @[Reg.scala 27:20] + reg intenable_reg_27; // @[Reg.scala 27:20] + reg intenable_reg_28; // @[Reg.scala 27:20] + reg intenable_reg_29; // @[Reg.scala 27:20] + reg intenable_reg_30; // @[Reg.scala 27:20] + reg intenable_reg_31; // @[Reg.scala 27:20] + wire gw_config_c1_clk = rvclkhdr_4_io_l1clk; // @[el2_pic_ctl.scala 113:42 el2_pic_ctl.scala 150:21] + reg [1:0] gw_config_reg_1; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_2; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_3; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_4; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_5; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_6; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_7; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_8; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_9; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_10; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_11; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_12; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_13; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_14; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_15; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_16; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_17; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_18; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_19; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_20; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_21; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_22; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_23; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_24; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_25; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_26; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_27; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_28; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_29; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_30; // @[Reg.scala 27:20] + reg [1:0] gw_config_reg_31; // @[Reg.scala 27:20] + wire _T_970 = extintsrc_req_sync[1] ^ gw_config_reg_1[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_971 = ~gw_clear_reg_we_1; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending; // @[el2_pic_ctl.scala 46:30] + wire _T_972 = gw_int_pending & _T_971; // @[el2_pic_ctl.scala 45:90] + wire _T_976 = _T_970 | gw_int_pending; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_1 = gw_config_reg_1[1] ? _T_976 : _T_970; // @[el2_pic_ctl.scala 47:8] + wire _T_982 = extintsrc_req_sync[2] ^ gw_config_reg_2[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_983 = ~gw_clear_reg_we_2; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_1; // @[el2_pic_ctl.scala 46:30] + wire _T_984 = gw_int_pending_1 & _T_983; // @[el2_pic_ctl.scala 45:90] + wire _T_988 = _T_982 | gw_int_pending_1; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_2 = gw_config_reg_2[1] ? _T_988 : _T_982; // @[el2_pic_ctl.scala 47:8] + wire _T_994 = extintsrc_req_sync[3] ^ gw_config_reg_3[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_995 = ~gw_clear_reg_we_3; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_2; // @[el2_pic_ctl.scala 46:30] + wire _T_996 = gw_int_pending_2 & _T_995; // @[el2_pic_ctl.scala 45:90] + wire _T_1000 = _T_994 | gw_int_pending_2; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_3 = gw_config_reg_3[1] ? _T_1000 : _T_994; // @[el2_pic_ctl.scala 47:8] + wire _T_1006 = extintsrc_req_sync[4] ^ gw_config_reg_4[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1007 = ~gw_clear_reg_we_4; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_3; // @[el2_pic_ctl.scala 46:30] + wire _T_1008 = gw_int_pending_3 & _T_1007; // @[el2_pic_ctl.scala 45:90] + wire _T_1012 = _T_1006 | gw_int_pending_3; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_4 = gw_config_reg_4[1] ? _T_1012 : _T_1006; // @[el2_pic_ctl.scala 47:8] + wire _T_1018 = extintsrc_req_sync[5] ^ gw_config_reg_5[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1019 = ~gw_clear_reg_we_5; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_4; // @[el2_pic_ctl.scala 46:30] + wire _T_1020 = gw_int_pending_4 & _T_1019; // @[el2_pic_ctl.scala 45:90] + wire _T_1024 = _T_1018 | gw_int_pending_4; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_5 = gw_config_reg_5[1] ? _T_1024 : _T_1018; // @[el2_pic_ctl.scala 47:8] + wire _T_1030 = extintsrc_req_sync[6] ^ gw_config_reg_6[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1031 = ~gw_clear_reg_we_6; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_5; // @[el2_pic_ctl.scala 46:30] + wire _T_1032 = gw_int_pending_5 & _T_1031; // @[el2_pic_ctl.scala 45:90] + wire _T_1036 = _T_1030 | gw_int_pending_5; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_6 = gw_config_reg_6[1] ? _T_1036 : _T_1030; // @[el2_pic_ctl.scala 47:8] + wire _T_1042 = extintsrc_req_sync[7] ^ gw_config_reg_7[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1043 = ~gw_clear_reg_we_7; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_6; // @[el2_pic_ctl.scala 46:30] + wire _T_1044 = gw_int_pending_6 & _T_1043; // @[el2_pic_ctl.scala 45:90] + wire _T_1048 = _T_1042 | gw_int_pending_6; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_7 = gw_config_reg_7[1] ? _T_1048 : _T_1042; // @[el2_pic_ctl.scala 47:8] + wire _T_1054 = extintsrc_req_sync[8] ^ gw_config_reg_8[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1055 = ~gw_clear_reg_we_8; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_7; // @[el2_pic_ctl.scala 46:30] + wire _T_1056 = gw_int_pending_7 & _T_1055; // @[el2_pic_ctl.scala 45:90] + wire _T_1060 = _T_1054 | gw_int_pending_7; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_8 = gw_config_reg_8[1] ? _T_1060 : _T_1054; // @[el2_pic_ctl.scala 47:8] + wire _T_1066 = extintsrc_req_sync[9] ^ gw_config_reg_9[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1067 = ~gw_clear_reg_we_9; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_8; // @[el2_pic_ctl.scala 46:30] + wire _T_1068 = gw_int_pending_8 & _T_1067; // @[el2_pic_ctl.scala 45:90] + wire _T_1072 = _T_1066 | gw_int_pending_8; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_9 = gw_config_reg_9[1] ? _T_1072 : _T_1066; // @[el2_pic_ctl.scala 47:8] + wire _T_1078 = extintsrc_req_sync[10] ^ gw_config_reg_10[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1079 = ~gw_clear_reg_we_10; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_9; // @[el2_pic_ctl.scala 46:30] + wire _T_1080 = gw_int_pending_9 & _T_1079; // @[el2_pic_ctl.scala 45:90] + wire _T_1084 = _T_1078 | gw_int_pending_9; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_10 = gw_config_reg_10[1] ? _T_1084 : _T_1078; // @[el2_pic_ctl.scala 47:8] + wire _T_1090 = extintsrc_req_sync[11] ^ gw_config_reg_11[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1091 = ~gw_clear_reg_we_11; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_10; // @[el2_pic_ctl.scala 46:30] + wire _T_1092 = gw_int_pending_10 & _T_1091; // @[el2_pic_ctl.scala 45:90] + wire _T_1096 = _T_1090 | gw_int_pending_10; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_11 = gw_config_reg_11[1] ? _T_1096 : _T_1090; // @[el2_pic_ctl.scala 47:8] + wire _T_1102 = extintsrc_req_sync[12] ^ gw_config_reg_12[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1103 = ~gw_clear_reg_we_12; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_11; // @[el2_pic_ctl.scala 46:30] + wire _T_1104 = gw_int_pending_11 & _T_1103; // @[el2_pic_ctl.scala 45:90] + wire _T_1108 = _T_1102 | gw_int_pending_11; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_12 = gw_config_reg_12[1] ? _T_1108 : _T_1102; // @[el2_pic_ctl.scala 47:8] + wire _T_1114 = extintsrc_req_sync[13] ^ gw_config_reg_13[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1115 = ~gw_clear_reg_we_13; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_12; // @[el2_pic_ctl.scala 46:30] + wire _T_1116 = gw_int_pending_12 & _T_1115; // @[el2_pic_ctl.scala 45:90] + wire _T_1120 = _T_1114 | gw_int_pending_12; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_13 = gw_config_reg_13[1] ? _T_1120 : _T_1114; // @[el2_pic_ctl.scala 47:8] + wire _T_1126 = extintsrc_req_sync[14] ^ gw_config_reg_14[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1127 = ~gw_clear_reg_we_14; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_13; // @[el2_pic_ctl.scala 46:30] + wire _T_1128 = gw_int_pending_13 & _T_1127; // @[el2_pic_ctl.scala 45:90] + wire _T_1132 = _T_1126 | gw_int_pending_13; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_14 = gw_config_reg_14[1] ? _T_1132 : _T_1126; // @[el2_pic_ctl.scala 47:8] + wire _T_1138 = extintsrc_req_sync[15] ^ gw_config_reg_15[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1139 = ~gw_clear_reg_we_15; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_14; // @[el2_pic_ctl.scala 46:30] + wire _T_1140 = gw_int_pending_14 & _T_1139; // @[el2_pic_ctl.scala 45:90] + wire _T_1144 = _T_1138 | gw_int_pending_14; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_15 = gw_config_reg_15[1] ? _T_1144 : _T_1138; // @[el2_pic_ctl.scala 47:8] + wire _T_1150 = extintsrc_req_sync[16] ^ gw_config_reg_16[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1151 = ~gw_clear_reg_we_16; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_15; // @[el2_pic_ctl.scala 46:30] + wire _T_1152 = gw_int_pending_15 & _T_1151; // @[el2_pic_ctl.scala 45:90] + wire _T_1156 = _T_1150 | gw_int_pending_15; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_16 = gw_config_reg_16[1] ? _T_1156 : _T_1150; // @[el2_pic_ctl.scala 47:8] + wire _T_1162 = extintsrc_req_sync[17] ^ gw_config_reg_17[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1163 = ~gw_clear_reg_we_17; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_16; // @[el2_pic_ctl.scala 46:30] + wire _T_1164 = gw_int_pending_16 & _T_1163; // @[el2_pic_ctl.scala 45:90] + wire _T_1168 = _T_1162 | gw_int_pending_16; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_17 = gw_config_reg_17[1] ? _T_1168 : _T_1162; // @[el2_pic_ctl.scala 47:8] + wire _T_1174 = extintsrc_req_sync[18] ^ gw_config_reg_18[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1175 = ~gw_clear_reg_we_18; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_17; // @[el2_pic_ctl.scala 46:30] + wire _T_1176 = gw_int_pending_17 & _T_1175; // @[el2_pic_ctl.scala 45:90] + wire _T_1180 = _T_1174 | gw_int_pending_17; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_18 = gw_config_reg_18[1] ? _T_1180 : _T_1174; // @[el2_pic_ctl.scala 47:8] + wire _T_1186 = extintsrc_req_sync[19] ^ gw_config_reg_19[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1187 = ~gw_clear_reg_we_19; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_18; // @[el2_pic_ctl.scala 46:30] + wire _T_1188 = gw_int_pending_18 & _T_1187; // @[el2_pic_ctl.scala 45:90] + wire _T_1192 = _T_1186 | gw_int_pending_18; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_19 = gw_config_reg_19[1] ? _T_1192 : _T_1186; // @[el2_pic_ctl.scala 47:8] + wire _T_1198 = extintsrc_req_sync[20] ^ gw_config_reg_20[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1199 = ~gw_clear_reg_we_20; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_19; // @[el2_pic_ctl.scala 46:30] + wire _T_1200 = gw_int_pending_19 & _T_1199; // @[el2_pic_ctl.scala 45:90] + wire _T_1204 = _T_1198 | gw_int_pending_19; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_20 = gw_config_reg_20[1] ? _T_1204 : _T_1198; // @[el2_pic_ctl.scala 47:8] + wire _T_1210 = extintsrc_req_sync[21] ^ gw_config_reg_21[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1211 = ~gw_clear_reg_we_21; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_20; // @[el2_pic_ctl.scala 46:30] + wire _T_1212 = gw_int_pending_20 & _T_1211; // @[el2_pic_ctl.scala 45:90] + wire _T_1216 = _T_1210 | gw_int_pending_20; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_21 = gw_config_reg_21[1] ? _T_1216 : _T_1210; // @[el2_pic_ctl.scala 47:8] + wire _T_1222 = extintsrc_req_sync[22] ^ gw_config_reg_22[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1223 = ~gw_clear_reg_we_22; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_21; // @[el2_pic_ctl.scala 46:30] + wire _T_1224 = gw_int_pending_21 & _T_1223; // @[el2_pic_ctl.scala 45:90] + wire _T_1228 = _T_1222 | gw_int_pending_21; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_22 = gw_config_reg_22[1] ? _T_1228 : _T_1222; // @[el2_pic_ctl.scala 47:8] + wire _T_1234 = extintsrc_req_sync[23] ^ gw_config_reg_23[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1235 = ~gw_clear_reg_we_23; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_22; // @[el2_pic_ctl.scala 46:30] + wire _T_1236 = gw_int_pending_22 & _T_1235; // @[el2_pic_ctl.scala 45:90] + wire _T_1240 = _T_1234 | gw_int_pending_22; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_23 = gw_config_reg_23[1] ? _T_1240 : _T_1234; // @[el2_pic_ctl.scala 47:8] + wire _T_1246 = extintsrc_req_sync[24] ^ gw_config_reg_24[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1247 = ~gw_clear_reg_we_24; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_23; // @[el2_pic_ctl.scala 46:30] + wire _T_1248 = gw_int_pending_23 & _T_1247; // @[el2_pic_ctl.scala 45:90] + wire _T_1252 = _T_1246 | gw_int_pending_23; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_24 = gw_config_reg_24[1] ? _T_1252 : _T_1246; // @[el2_pic_ctl.scala 47:8] + wire _T_1258 = extintsrc_req_sync[25] ^ gw_config_reg_25[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1259 = ~gw_clear_reg_we_25; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_24; // @[el2_pic_ctl.scala 46:30] + wire _T_1260 = gw_int_pending_24 & _T_1259; // @[el2_pic_ctl.scala 45:90] + wire _T_1264 = _T_1258 | gw_int_pending_24; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_25 = gw_config_reg_25[1] ? _T_1264 : _T_1258; // @[el2_pic_ctl.scala 47:8] + wire _T_1270 = extintsrc_req_sync[26] ^ gw_config_reg_26[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1271 = ~gw_clear_reg_we_26; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_25; // @[el2_pic_ctl.scala 46:30] + wire _T_1272 = gw_int_pending_25 & _T_1271; // @[el2_pic_ctl.scala 45:90] + wire _T_1276 = _T_1270 | gw_int_pending_25; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_26 = gw_config_reg_26[1] ? _T_1276 : _T_1270; // @[el2_pic_ctl.scala 47:8] + wire _T_1282 = extintsrc_req_sync[27] ^ gw_config_reg_27[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1283 = ~gw_clear_reg_we_27; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_26; // @[el2_pic_ctl.scala 46:30] + wire _T_1284 = gw_int_pending_26 & _T_1283; // @[el2_pic_ctl.scala 45:90] + wire _T_1288 = _T_1282 | gw_int_pending_26; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_27 = gw_config_reg_27[1] ? _T_1288 : _T_1282; // @[el2_pic_ctl.scala 47:8] + wire _T_1294 = extintsrc_req_sync[28] ^ gw_config_reg_28[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1295 = ~gw_clear_reg_we_28; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_27; // @[el2_pic_ctl.scala 46:30] + wire _T_1296 = gw_int_pending_27 & _T_1295; // @[el2_pic_ctl.scala 45:90] + wire _T_1300 = _T_1294 | gw_int_pending_27; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_28 = gw_config_reg_28[1] ? _T_1300 : _T_1294; // @[el2_pic_ctl.scala 47:8] + wire _T_1306 = extintsrc_req_sync[29] ^ gw_config_reg_29[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1307 = ~gw_clear_reg_we_29; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_28; // @[el2_pic_ctl.scala 46:30] + wire _T_1308 = gw_int_pending_28 & _T_1307; // @[el2_pic_ctl.scala 45:90] + wire _T_1312 = _T_1306 | gw_int_pending_28; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_29 = gw_config_reg_29[1] ? _T_1312 : _T_1306; // @[el2_pic_ctl.scala 47:8] + wire _T_1318 = extintsrc_req_sync[30] ^ gw_config_reg_30[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1319 = ~gw_clear_reg_we_30; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_29; // @[el2_pic_ctl.scala 46:30] + wire _T_1320 = gw_int_pending_29 & _T_1319; // @[el2_pic_ctl.scala 45:90] + wire _T_1324 = _T_1318 | gw_int_pending_29; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_30 = gw_config_reg_30[1] ? _T_1324 : _T_1318; // @[el2_pic_ctl.scala 47:8] + wire _T_1330 = extintsrc_req_sync[31] ^ gw_config_reg_31[0]; // @[el2_pic_ctl.scala 45:50] + wire _T_1331 = ~gw_clear_reg_we_31; // @[el2_pic_ctl.scala 45:92] + reg gw_int_pending_30; // @[el2_pic_ctl.scala 46:30] + wire _T_1332 = gw_int_pending_30 & _T_1331; // @[el2_pic_ctl.scala 45:90] + wire _T_1336 = _T_1330 | gw_int_pending_30; // @[el2_pic_ctl.scala 47:78] + wire extintsrc_req_gw_31 = gw_config_reg_31[1] ? _T_1336 : _T_1330; // @[el2_pic_ctl.scala 47:8] reg config_reg; // @[Reg.scala 27:20] - wire [3:0] pl_in_q = config_reg ? 4'hf : 4'h0; // @[el2_pic_ctrl.scala 204:20] - reg [3:0] _T_36; // @[el2_pic_ctrl.scala 206:42] - wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctrl.scala 211:19] - reg _T_45; // @[el2_pic_ctrl.scala 213:48] - rvclkhdr pic_addr_c1_cgc ( // @[el2_pic_ctrl.scala 162:32] - .io_l1clk(pic_addr_c1_cgc_io_l1clk), - .io_clk(pic_addr_c1_cgc_io_clk), - .io_en(pic_addr_c1_cgc_io_en), - .io_scan_mode(pic_addr_c1_cgc_io_scan_mode) + wire [3:0] intpriority_reg_0 = 4'h0; // @[el2_pic_ctl.scala 162:32 el2_pic_ctl.scala 163:208] + wire [3:0] _T_1342 = ~intpriority_reg_1; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_1 = config_reg ? _T_1342 : intpriority_reg_1; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1345 = ~intpriority_reg_2; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_2 = config_reg ? _T_1345 : intpriority_reg_2; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1348 = ~intpriority_reg_3; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_3 = config_reg ? _T_1348 : intpriority_reg_3; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1351 = ~intpriority_reg_4; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_4 = config_reg ? _T_1351 : intpriority_reg_4; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1354 = ~intpriority_reg_5; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_5 = config_reg ? _T_1354 : intpriority_reg_5; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1357 = ~intpriority_reg_6; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_6 = config_reg ? _T_1357 : intpriority_reg_6; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1360 = ~intpriority_reg_7; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_7 = config_reg ? _T_1360 : intpriority_reg_7; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1363 = ~intpriority_reg_8; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_8 = config_reg ? _T_1363 : intpriority_reg_8; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1366 = ~intpriority_reg_9; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_9 = config_reg ? _T_1366 : intpriority_reg_9; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1369 = ~intpriority_reg_10; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_10 = config_reg ? _T_1369 : intpriority_reg_10; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1372 = ~intpriority_reg_11; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_11 = config_reg ? _T_1372 : intpriority_reg_11; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1375 = ~intpriority_reg_12; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_12 = config_reg ? _T_1375 : intpriority_reg_12; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1378 = ~intpriority_reg_13; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_13 = config_reg ? _T_1378 : intpriority_reg_13; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1381 = ~intpriority_reg_14; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_14 = config_reg ? _T_1381 : intpriority_reg_14; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1384 = ~intpriority_reg_15; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_15 = config_reg ? _T_1384 : intpriority_reg_15; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1387 = ~intpriority_reg_16; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_16 = config_reg ? _T_1387 : intpriority_reg_16; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1390 = ~intpriority_reg_17; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_17 = config_reg ? _T_1390 : intpriority_reg_17; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1393 = ~intpriority_reg_18; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_18 = config_reg ? _T_1393 : intpriority_reg_18; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1396 = ~intpriority_reg_19; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_19 = config_reg ? _T_1396 : intpriority_reg_19; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1399 = ~intpriority_reg_20; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_20 = config_reg ? _T_1399 : intpriority_reg_20; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1402 = ~intpriority_reg_21; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_21 = config_reg ? _T_1402 : intpriority_reg_21; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1405 = ~intpriority_reg_22; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_22 = config_reg ? _T_1405 : intpriority_reg_22; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1408 = ~intpriority_reg_23; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_23 = config_reg ? _T_1408 : intpriority_reg_23; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1411 = ~intpriority_reg_24; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_24 = config_reg ? _T_1411 : intpriority_reg_24; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1414 = ~intpriority_reg_25; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_25 = config_reg ? _T_1414 : intpriority_reg_25; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1417 = ~intpriority_reg_26; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_26 = config_reg ? _T_1417 : intpriority_reg_26; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1420 = ~intpriority_reg_27; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_27 = config_reg ? _T_1420 : intpriority_reg_27; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1423 = ~intpriority_reg_28; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_28 = config_reg ? _T_1423 : intpriority_reg_28; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1426 = ~intpriority_reg_29; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_29 = config_reg ? _T_1426 : intpriority_reg_29; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1429 = ~intpriority_reg_30; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_30 = config_reg ? _T_1429 : intpriority_reg_30; // @[el2_pic_ctl.scala 174:70] + wire [3:0] _T_1432 = ~intpriority_reg_31; // @[el2_pic_ctl.scala 174:89] + wire [3:0] intpriority_reg_inv_31 = config_reg ? _T_1432 : intpriority_reg_31; // @[el2_pic_ctl.scala 174:70] + wire _T_1438 = extintsrc_req_gw_1 & intenable_reg_1; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1440 = _T_1438 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_1 = _T_1440 & intpriority_reg_inv_1; // @[el2_pic_ctl.scala 175:129] + wire _T_1442 = extintsrc_req_gw_2 & intenable_reg_2; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1444 = _T_1442 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_2 = _T_1444 & intpriority_reg_inv_2; // @[el2_pic_ctl.scala 175:129] + wire _T_1446 = extintsrc_req_gw_3 & intenable_reg_3; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1448 = _T_1446 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_3 = _T_1448 & intpriority_reg_inv_3; // @[el2_pic_ctl.scala 175:129] + wire _T_1450 = extintsrc_req_gw_4 & intenable_reg_4; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1452 = _T_1450 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_4 = _T_1452 & intpriority_reg_inv_4; // @[el2_pic_ctl.scala 175:129] + wire _T_1454 = extintsrc_req_gw_5 & intenable_reg_5; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1456 = _T_1454 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_5 = _T_1456 & intpriority_reg_inv_5; // @[el2_pic_ctl.scala 175:129] + wire _T_1458 = extintsrc_req_gw_6 & intenable_reg_6; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1460 = _T_1458 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_6 = _T_1460 & intpriority_reg_inv_6; // @[el2_pic_ctl.scala 175:129] + wire _T_1462 = extintsrc_req_gw_7 & intenable_reg_7; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1464 = _T_1462 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_7 = _T_1464 & intpriority_reg_inv_7; // @[el2_pic_ctl.scala 175:129] + wire _T_1466 = extintsrc_req_gw_8 & intenable_reg_8; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1468 = _T_1466 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_8 = _T_1468 & intpriority_reg_inv_8; // @[el2_pic_ctl.scala 175:129] + wire _T_1470 = extintsrc_req_gw_9 & intenable_reg_9; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1472 = _T_1470 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_9 = _T_1472 & intpriority_reg_inv_9; // @[el2_pic_ctl.scala 175:129] + wire _T_1474 = extintsrc_req_gw_10 & intenable_reg_10; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1476 = _T_1474 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_10 = _T_1476 & intpriority_reg_inv_10; // @[el2_pic_ctl.scala 175:129] + wire _T_1478 = extintsrc_req_gw_11 & intenable_reg_11; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1480 = _T_1478 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_11 = _T_1480 & intpriority_reg_inv_11; // @[el2_pic_ctl.scala 175:129] + wire _T_1482 = extintsrc_req_gw_12 & intenable_reg_12; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1484 = _T_1482 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_12 = _T_1484 & intpriority_reg_inv_12; // @[el2_pic_ctl.scala 175:129] + wire _T_1486 = extintsrc_req_gw_13 & intenable_reg_13; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1488 = _T_1486 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_13 = _T_1488 & intpriority_reg_inv_13; // @[el2_pic_ctl.scala 175:129] + wire _T_1490 = extintsrc_req_gw_14 & intenable_reg_14; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1492 = _T_1490 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_14 = _T_1492 & intpriority_reg_inv_14; // @[el2_pic_ctl.scala 175:129] + wire _T_1494 = extintsrc_req_gw_15 & intenable_reg_15; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1496 = _T_1494 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_15 = _T_1496 & intpriority_reg_inv_15; // @[el2_pic_ctl.scala 175:129] + wire _T_1498 = extintsrc_req_gw_16 & intenable_reg_16; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1500 = _T_1498 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_16 = _T_1500 & intpriority_reg_inv_16; // @[el2_pic_ctl.scala 175:129] + wire _T_1502 = extintsrc_req_gw_17 & intenable_reg_17; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1504 = _T_1502 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_17 = _T_1504 & intpriority_reg_inv_17; // @[el2_pic_ctl.scala 175:129] + wire _T_1506 = extintsrc_req_gw_18 & intenable_reg_18; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1508 = _T_1506 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_18 = _T_1508 & intpriority_reg_inv_18; // @[el2_pic_ctl.scala 175:129] + wire _T_1510 = extintsrc_req_gw_19 & intenable_reg_19; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1512 = _T_1510 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_19 = _T_1512 & intpriority_reg_inv_19; // @[el2_pic_ctl.scala 175:129] + wire _T_1514 = extintsrc_req_gw_20 & intenable_reg_20; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1516 = _T_1514 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_20 = _T_1516 & intpriority_reg_inv_20; // @[el2_pic_ctl.scala 175:129] + wire _T_1518 = extintsrc_req_gw_21 & intenable_reg_21; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1520 = _T_1518 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_21 = _T_1520 & intpriority_reg_inv_21; // @[el2_pic_ctl.scala 175:129] + wire _T_1522 = extintsrc_req_gw_22 & intenable_reg_22; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1524 = _T_1522 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_22 = _T_1524 & intpriority_reg_inv_22; // @[el2_pic_ctl.scala 175:129] + wire _T_1526 = extintsrc_req_gw_23 & intenable_reg_23; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1528 = _T_1526 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_23 = _T_1528 & intpriority_reg_inv_23; // @[el2_pic_ctl.scala 175:129] + wire _T_1530 = extintsrc_req_gw_24 & intenable_reg_24; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1532 = _T_1530 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_24 = _T_1532 & intpriority_reg_inv_24; // @[el2_pic_ctl.scala 175:129] + wire _T_1534 = extintsrc_req_gw_25 & intenable_reg_25; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1536 = _T_1534 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_25 = _T_1536 & intpriority_reg_inv_25; // @[el2_pic_ctl.scala 175:129] + wire _T_1538 = extintsrc_req_gw_26 & intenable_reg_26; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1540 = _T_1538 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_26 = _T_1540 & intpriority_reg_inv_26; // @[el2_pic_ctl.scala 175:129] + wire _T_1542 = extintsrc_req_gw_27 & intenable_reg_27; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1544 = _T_1542 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_27 = _T_1544 & intpriority_reg_inv_27; // @[el2_pic_ctl.scala 175:129] + wire _T_1546 = extintsrc_req_gw_28 & intenable_reg_28; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1548 = _T_1546 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_28 = _T_1548 & intpriority_reg_inv_28; // @[el2_pic_ctl.scala 175:129] + wire _T_1550 = extintsrc_req_gw_29 & intenable_reg_29; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1552 = _T_1550 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_29 = _T_1552 & intpriority_reg_inv_29; // @[el2_pic_ctl.scala 175:129] + wire _T_1554 = extintsrc_req_gw_30 & intenable_reg_30; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1556 = _T_1554 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_30 = _T_1556 & intpriority_reg_inv_30; // @[el2_pic_ctl.scala 175:129] + wire _T_1558 = extintsrc_req_gw_31 & intenable_reg_31; // @[el2_pic_ctl.scala 175:109] + wire [3:0] _T_1560 = _T_1558 ? 4'hf : 4'h0; // @[Bitwise.scala 72:12] + wire [3:0] intpend_w_prior_en_31 = _T_1560 & intpriority_reg_inv_31; // @[el2_pic_ctl.scala 175:129] + wire [7:0] _T_1564 = 8'hff; // @[Bitwise.scala 72:12] + wire [3:0] level_intpend_w_prior_en_0_0 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1441 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_1 = intpend_w_prior_en_1; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1566 = intpriority_reg_0 < _T_1441; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_1 = 8'h1; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_1 = 8'h1; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_0 = 8'h0; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_0 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id = _T_1566 ? intpend_id_1 : intpend_id_0; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority = _T_1566 ? _T_1441 : intpriority_reg_0; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1445 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_2 = intpend_w_prior_en_2; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1449 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_3 = intpend_w_prior_en_3; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1570 = _T_1445 < _T_1449; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_3 = 8'h3; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_3 = 8'h3; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_2 = 8'h2; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_2 = 8'h2; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_1 = _T_1570 ? intpend_id_3 : intpend_id_2; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_1 = _T_1570 ? _T_1449 : _T_1445; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1453 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_4 = intpend_w_prior_en_4; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1457 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_5 = intpend_w_prior_en_5; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1574 = _T_1453 < _T_1457; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_5 = 8'h5; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_5 = 8'h5; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_4 = 8'h4; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_4 = 8'h4; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_2 = _T_1574 ? intpend_id_5 : intpend_id_4; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_2 = _T_1574 ? _T_1457 : _T_1453; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1461 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_6 = intpend_w_prior_en_6; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1465 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_7 = intpend_w_prior_en_7; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1578 = _T_1461 < _T_1465; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_7 = 8'h7; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_7 = 8'h7; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_6 = 8'h6; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_6 = 8'h6; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_3 = _T_1578 ? intpend_id_7 : intpend_id_6; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_3 = _T_1578 ? _T_1465 : _T_1461; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1469 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_8 = intpend_w_prior_en_8; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1473 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_9 = intpend_w_prior_en_9; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1582 = _T_1469 < _T_1473; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_9 = 8'h9; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_9 = 8'h9; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_8 = 8'h8; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_8 = 8'h8; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_4 = _T_1582 ? intpend_id_9 : intpend_id_8; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_4 = _T_1582 ? _T_1473 : _T_1469; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1477 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_10 = intpend_w_prior_en_10; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1481 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_11 = intpend_w_prior_en_11; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1586 = _T_1477 < _T_1481; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_11 = 8'hb; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_11 = 8'hb; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_10 = 8'ha; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_10 = 8'ha; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_5 = _T_1586 ? intpend_id_11 : intpend_id_10; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_5 = _T_1586 ? _T_1481 : _T_1477; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1485 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_12 = intpend_w_prior_en_12; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1489 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_13 = intpend_w_prior_en_13; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1590 = _T_1485 < _T_1489; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_13 = 8'hd; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_13 = 8'hd; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_12 = 8'hc; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_12 = 8'hc; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_6 = _T_1590 ? intpend_id_13 : intpend_id_12; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_6 = _T_1590 ? _T_1489 : _T_1485; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1493 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_14 = intpend_w_prior_en_14; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1497 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_15 = intpend_w_prior_en_15; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1594 = _T_1493 < _T_1497; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_15 = 8'hf; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_15 = 8'hf; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_14 = 8'he; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_14 = 8'he; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_7 = _T_1594 ? intpend_id_15 : intpend_id_14; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_7 = _T_1594 ? _T_1497 : _T_1493; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1501 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_16 = intpend_w_prior_en_16; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1505 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_17 = intpend_w_prior_en_17; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1598 = _T_1501 < _T_1505; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_17 = 8'h11; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_17 = 8'h11; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_16 = 8'h10; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_16 = 8'h10; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_8 = _T_1598 ? intpend_id_17 : intpend_id_16; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_8 = _T_1598 ? _T_1505 : _T_1501; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1509 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_18 = intpend_w_prior_en_18; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1513 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_19 = intpend_w_prior_en_19; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1602 = _T_1509 < _T_1513; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_19 = 8'h13; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_19 = 8'h13; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_18 = 8'h12; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_18 = 8'h12; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_9 = _T_1602 ? intpend_id_19 : intpend_id_18; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_9 = _T_1602 ? _T_1513 : _T_1509; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1517 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_20 = intpend_w_prior_en_20; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1521 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_21 = intpend_w_prior_en_21; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1606 = _T_1517 < _T_1521; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_21 = 8'h15; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_21 = 8'h15; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_20 = 8'h14; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_20 = 8'h14; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_10 = _T_1606 ? intpend_id_21 : intpend_id_20; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_10 = _T_1606 ? _T_1521 : _T_1517; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1525 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_22 = intpend_w_prior_en_22; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1529 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_23 = intpend_w_prior_en_23; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1610 = _T_1525 < _T_1529; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_23 = 8'h17; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_23 = 8'h17; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_22 = 8'h16; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_22 = 8'h16; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_11 = _T_1610 ? intpend_id_23 : intpend_id_22; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_11 = _T_1610 ? _T_1529 : _T_1525; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1533 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_24 = intpend_w_prior_en_24; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1537 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_25 = intpend_w_prior_en_25; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1614 = _T_1533 < _T_1537; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_25 = 8'h19; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_25 = 8'h19; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_24 = 8'h18; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_24 = 8'h18; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_12 = _T_1614 ? intpend_id_25 : intpend_id_24; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_12 = _T_1614 ? _T_1537 : _T_1533; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1541 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_26 = intpend_w_prior_en_26; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1545 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_27 = intpend_w_prior_en_27; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1618 = _T_1541 < _T_1545; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_27 = 8'h1b; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_27 = 8'h1b; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_26 = 8'h1a; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_26 = 8'h1a; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_13 = _T_1618 ? intpend_id_27 : intpend_id_26; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_13 = _T_1618 ? _T_1545 : _T_1541; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1549 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_28 = intpend_w_prior_en_28; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1553 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_29 = intpend_w_prior_en_29; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1622 = _T_1549 < _T_1553; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_29 = 8'h1d; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_29 = 8'h1d; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_28 = 8'h1c; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_28 = 8'h1c; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_14 = _T_1622 ? intpend_id_29 : intpend_id_28; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_14 = _T_1622 ? _T_1553 : _T_1549; // @[el2_pic_ctl.scala 39:24] + wire [3:0] _T_1557 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_30 = intpend_w_prior_en_30; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] _T_1561 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 84:42 el2_pic_ctl.scala 175:63] + wire [3:0] level_intpend_w_prior_en_0_31 = intpend_w_prior_en_31; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1626 = _T_1557 < _T_1561; // @[el2_pic_ctl.scala 38:29] + wire [7:0] intpend_id_31 = 8'h1f; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_31 = 8'h1f; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] intpend_id_30 = 8'h1e; // @[el2_pic_ctl.scala 85:42 el2_pic_ctl.scala 176:55] + wire [7:0] level_intpend_id_0_30 = 8'h1e; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_15 = _T_1626 ? intpend_id_31 : intpend_id_30; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_15 = _T_1626 ? _T_1561 : _T_1557; // @[el2_pic_ctl.scala 39:24] + wire [3:0] level_intpend_w_prior_en_0_32 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire [3:0] level_intpend_w_prior_en_0_33 = 4'h0; // @[el2_pic_ctl.scala 227:40 el2_pic_ctl.scala 231:38 el2_pic_ctl.scala 234:33] + wire _T_1630 = intpriority_reg_0 < intpriority_reg_0; // @[el2_pic_ctl.scala 38:29] + wire [7:0] level_intpend_id_0_33 = 8'hff; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] level_intpend_id_0_32 = 8'hff; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 235:33] + wire [7:0] out_id_16 = _T_1630 ? _T_1564 : _T_1564; // @[el2_pic_ctl.scala 38:18] + wire _T_1634 = out_priority < out_priority_1; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1571 = out_id_1; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_1 = out_id_1; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1567 = out_id; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_0 = out_id; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_17 = _T_1634 ? _T_1571 : _T_1567; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_17 = _T_1634 ? out_priority_1 : out_priority; // @[el2_pic_ctl.scala 39:24] + wire _T_1638 = out_priority_2 < out_priority_3; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1579 = out_id_3; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_3 = out_id_3; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1575 = out_id_2; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_2 = out_id_2; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_18 = _T_1638 ? _T_1579 : _T_1575; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_18 = _T_1638 ? out_priority_3 : out_priority_2; // @[el2_pic_ctl.scala 39:24] + wire _T_1642 = out_priority_4 < out_priority_5; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1587 = out_id_5; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_5 = out_id_5; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1583 = out_id_4; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_4 = out_id_4; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_19 = _T_1642 ? _T_1587 : _T_1583; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_19 = _T_1642 ? out_priority_5 : out_priority_4; // @[el2_pic_ctl.scala 39:24] + wire _T_1646 = out_priority_6 < out_priority_7; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1595 = out_id_7; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_7 = out_id_7; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1591 = out_id_6; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_6 = out_id_6; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_20 = _T_1646 ? _T_1595 : _T_1591; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_20 = _T_1646 ? out_priority_7 : out_priority_6; // @[el2_pic_ctl.scala 39:24] + wire _T_1650 = out_priority_8 < out_priority_9; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1603 = out_id_9; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_9 = out_id_9; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1599 = out_id_8; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_8 = out_id_8; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_21 = _T_1650 ? _T_1603 : _T_1599; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_21 = _T_1650 ? out_priority_9 : out_priority_8; // @[el2_pic_ctl.scala 39:24] + wire _T_1654 = out_priority_10 < out_priority_11; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1611 = out_id_11; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_11 = out_id_11; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1607 = out_id_10; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_10 = out_id_10; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_22 = _T_1654 ? _T_1611 : _T_1607; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_22 = _T_1654 ? out_priority_11 : out_priority_10; // @[el2_pic_ctl.scala 39:24] + wire _T_1658 = out_priority_12 < out_priority_13; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1619 = out_id_13; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_13 = out_id_13; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1615 = out_id_12; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_12 = out_id_12; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_23 = _T_1658 ? _T_1619 : _T_1615; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_23 = _T_1658 ? out_priority_13 : out_priority_12; // @[el2_pic_ctl.scala 39:24] + wire _T_1662 = out_priority_14 < out_priority_15; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1627 = out_id_15; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_15 = out_id_15; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1623 = out_id_14; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_14 = out_id_14; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_24 = _T_1662 ? _T_1627 : _T_1623; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_24 = _T_1662 ? out_priority_15 : out_priority_14; // @[el2_pic_ctl.scala 39:24] + wire [7:0] level_intpend_id_1_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] + wire [7:0] _T_1631 = out_id_16; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_1_16 = out_id_16; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1667 = _T_1631; // @[el2_pic_ctl.scala 38:18] + wire _T_1670 = out_priority_17 < out_priority_18; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1639 = out_id_18; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_1 = out_id_18; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1635 = out_id_17; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_0 = out_id_17; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_26 = _T_1670 ? _T_1639 : _T_1635; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_26 = _T_1670 ? out_priority_18 : out_priority_17; // @[el2_pic_ctl.scala 39:24] + wire _T_1674 = out_priority_19 < out_priority_20; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1647 = out_id_20; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_3 = out_id_20; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1643 = out_id_19; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_2 = out_id_19; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_27 = _T_1674 ? _T_1647 : _T_1643; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_27 = _T_1674 ? out_priority_20 : out_priority_19; // @[el2_pic_ctl.scala 39:24] + wire _T_1678 = out_priority_21 < out_priority_22; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1655 = out_id_22; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_5 = out_id_22; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1651 = out_id_21; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_4 = out_id_21; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_28 = _T_1678 ? _T_1655 : _T_1651; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_28 = _T_1678 ? out_priority_22 : out_priority_21; // @[el2_pic_ctl.scala 39:24] + wire _T_1682 = out_priority_23 < out_priority_24; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1663 = out_id_24; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_7 = out_id_24; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1659 = out_id_23; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_2_6 = out_id_23; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_29 = _T_1682 ? _T_1663 : _T_1659; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_29 = _T_1682 ? out_priority_24 : out_priority_23; // @[el2_pic_ctl.scala 39:24] + wire [7:0] level_intpend_id_2_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] + wire [7:0] level_intpend_id_2_8 = _T_1631; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1687 = _T_1667; // @[el2_pic_ctl.scala 38:18] + wire _T_1690 = out_priority_26 < out_priority_27; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1675 = out_id_27; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_3_1 = out_id_27; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1671 = out_id_26; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_3_0 = out_id_26; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_31 = _T_1690 ? _T_1675 : _T_1671; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_31 = _T_1690 ? out_priority_27 : out_priority_26; // @[el2_pic_ctl.scala 39:24] + wire _T_1694 = out_priority_28 < out_priority_29; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1683 = out_id_29; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_3_3 = out_id_29; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1679 = out_id_28; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_3_2 = out_id_28; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_32 = _T_1694 ? _T_1683 : _T_1679; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_32 = _T_1694 ? out_priority_29 : out_priority_28; // @[el2_pic_ctl.scala 39:24] + wire [7:0] level_intpend_id_3_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] + wire [7:0] level_intpend_id_3_4 = _T_1667; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1699 = _T_1687; // @[el2_pic_ctl.scala 38:18] + wire _T_1702 = out_priority_31 < out_priority_32; // @[el2_pic_ctl.scala 38:29] + wire [7:0] _T_1695 = out_id_32; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_4_1 = out_id_32; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] _T_1691 = out_id_31; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_4_0 = out_id_31; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] out_id_34 = _T_1702 ? _T_1695 : _T_1691; // @[el2_pic_ctl.scala 38:18] + wire [3:0] out_priority_34 = _T_1702 ? out_priority_32 : out_priority_31; // @[el2_pic_ctl.scala 39:24] + wire [7:0] level_intpend_id_4_3 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] + wire [7:0] level_intpend_id_4_2 = _T_1687; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire config_reg_we = waddr_config_pic_match & picm_wren_ff; // @[el2_pic_ctl.scala 263:47] + wire config_reg_re = raddr_config_pic_match & picm_rden_ff; // @[el2_pic_ctl.scala 264:47] + wire [3:0] _T_1705 = out_priority_34; // @[el2_pic_ctl.scala 39:18] + wire [3:0] selected_int_priority = out_priority_34; // @[el2_pic_ctl.scala 251:29] + wire [3:0] _T_1713 = ~_T_1705; // @[el2_pic_ctl.scala 275:38] + wire [3:0] pl_in_q = config_reg ? _T_1713 : _T_1705; // @[el2_pic_ctl.scala 275:20] + reg [7:0] _T_1714; // @[el2_pic_ctl.scala 276:47] + reg [3:0] _T_1715; // @[el2_pic_ctl.scala 277:42] + wire [3:0] _T_1717 = ~io_meipt; // @[el2_pic_ctl.scala 278:40] + wire [3:0] meipt_inv = config_reg ? _T_1717 : io_meipt; // @[el2_pic_ctl.scala 278:22] + wire [3:0] _T_1719 = ~io_meicurpl; // @[el2_pic_ctl.scala 279:43] + wire [3:0] meicurpl_inv = config_reg ? _T_1719 : io_meicurpl; // @[el2_pic_ctl.scala 279:25] + wire _T_1720 = _T_1705 > meipt_inv; // @[el2_pic_ctl.scala 280:47] + wire _T_1721 = _T_1705 > meicurpl_inv; // @[el2_pic_ctl.scala 280:86] + reg _T_1722; // @[el2_pic_ctl.scala 281:50] + wire [3:0] maxint = config_reg ? 4'h0 : 4'hf; // @[el2_pic_ctl.scala 282:19] + reg _T_1724; // @[el2_pic_ctl.scala 284:48] + wire intpend_reg_read = addr_intpend_base_match & picm_rden_ff; // @[el2_pic_ctl.scala 290:60] + wire [9:0] _T_1734 = {extintsrc_req_gw_31,extintsrc_req_gw_30,extintsrc_req_gw_29,extintsrc_req_gw_28,extintsrc_req_gw_27,extintsrc_req_gw_26,extintsrc_req_gw_25,extintsrc_req_gw_24,extintsrc_req_gw_23,extintsrc_req_gw_22}; // @[Cat.scala 29:58] + wire [18:0] _T_1743 = {_T_1734,extintsrc_req_gw_21,extintsrc_req_gw_20,extintsrc_req_gw_19,extintsrc_req_gw_18,extintsrc_req_gw_17,extintsrc_req_gw_16,extintsrc_req_gw_15,extintsrc_req_gw_14,extintsrc_req_gw_13}; // @[Cat.scala 29:58] + wire [27:0] _T_1752 = {_T_1743,extintsrc_req_gw_12,extintsrc_req_gw_11,extintsrc_req_gw_10,extintsrc_req_gw_9,extintsrc_req_gw_8,extintsrc_req_gw_7,extintsrc_req_gw_6,extintsrc_req_gw_5,extintsrc_req_gw_4}; // @[Cat.scala 29:58] + wire [63:0] intpend_reg_extended = {32'h0,_T_1752,extintsrc_req_gw_3,extintsrc_req_gw_2,extintsrc_req_gw_1,1'h0}; // @[Cat.scala 29:58] + wire [3:0] _GEN_220 = {{3'd0}, intpend_reg_read}; // @[el2_pic_ctl.scala 298:83] + wire [3:0] _T_1759 = _GEN_220 & picm_raddr_ff[5:2]; // @[el2_pic_ctl.scala 298:83] + wire _T_1760 = _T_1759 == 4'h0; // @[el2_pic_ctl.scala 298:105] + wire [31:0] _T_1762 = _T_1760 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] intpend_rd_part_out_0 = _T_1762 & intpend_reg_extended[31:0]; // @[el2_pic_ctl.scala 298:119] + wire _T_1767 = _T_1759 == 4'h1; // @[el2_pic_ctl.scala 298:105] + wire [31:0] _T_1769 = _T_1767 ? 32'hffffffff : 32'h0; // @[Bitwise.scala 72:12] + wire [31:0] intpend_rd_part_out_1 = _T_1769 & intpend_reg_extended[63:32]; // @[el2_pic_ctl.scala 298:119] + wire [31:0] intpend_rd_out = intpend_rd_part_out_0 | intpend_rd_part_out_1; // @[el2_pic_ctl.scala 299:89] + wire intenable_rd_out = intenable_reg_re_31 & intenable_reg_31; // @[el2_pic_ctl.scala 300:76] + wire [3:0] _T_1835 = intpriority_reg_re_31 ? intpriority_reg_31 : 4'h0; // @[Mux.scala 98:16] + wire [3:0] _T_1836 = intpriority_reg_re_30 ? intpriority_reg_30 : _T_1835; // @[Mux.scala 98:16] + wire [3:0] _T_1837 = intpriority_reg_re_29 ? intpriority_reg_29 : _T_1836; // @[Mux.scala 98:16] + wire [3:0] _T_1838 = intpriority_reg_re_28 ? intpriority_reg_28 : _T_1837; // @[Mux.scala 98:16] + wire [3:0] _T_1839 = intpriority_reg_re_27 ? intpriority_reg_27 : _T_1838; // @[Mux.scala 98:16] + wire [3:0] _T_1840 = intpriority_reg_re_26 ? intpriority_reg_26 : _T_1839; // @[Mux.scala 98:16] + wire [3:0] _T_1841 = intpriority_reg_re_25 ? intpriority_reg_25 : _T_1840; // @[Mux.scala 98:16] + wire [3:0] _T_1842 = intpriority_reg_re_24 ? intpriority_reg_24 : _T_1841; // @[Mux.scala 98:16] + wire [3:0] _T_1843 = intpriority_reg_re_23 ? intpriority_reg_23 : _T_1842; // @[Mux.scala 98:16] + wire [3:0] _T_1844 = intpriority_reg_re_22 ? intpriority_reg_22 : _T_1843; // @[Mux.scala 98:16] + wire [3:0] _T_1845 = intpriority_reg_re_21 ? intpriority_reg_21 : _T_1844; // @[Mux.scala 98:16] + wire [3:0] _T_1846 = intpriority_reg_re_20 ? intpriority_reg_20 : _T_1845; // @[Mux.scala 98:16] + wire [3:0] _T_1847 = intpriority_reg_re_19 ? intpriority_reg_19 : _T_1846; // @[Mux.scala 98:16] + wire [3:0] _T_1848 = intpriority_reg_re_18 ? intpriority_reg_18 : _T_1847; // @[Mux.scala 98:16] + wire [3:0] _T_1849 = intpriority_reg_re_17 ? intpriority_reg_17 : _T_1848; // @[Mux.scala 98:16] + wire [3:0] _T_1850 = intpriority_reg_re_16 ? intpriority_reg_16 : _T_1849; // @[Mux.scala 98:16] + wire [3:0] _T_1851 = intpriority_reg_re_15 ? intpriority_reg_15 : _T_1850; // @[Mux.scala 98:16] + wire [3:0] _T_1852 = intpriority_reg_re_14 ? intpriority_reg_14 : _T_1851; // @[Mux.scala 98:16] + wire [3:0] _T_1853 = intpriority_reg_re_13 ? intpriority_reg_13 : _T_1852; // @[Mux.scala 98:16] + wire [3:0] _T_1854 = intpriority_reg_re_12 ? intpriority_reg_12 : _T_1853; // @[Mux.scala 98:16] + wire [3:0] _T_1855 = intpriority_reg_re_11 ? intpriority_reg_11 : _T_1854; // @[Mux.scala 98:16] + wire [3:0] _T_1856 = intpriority_reg_re_10 ? intpriority_reg_10 : _T_1855; // @[Mux.scala 98:16] + wire [3:0] _T_1857 = intpriority_reg_re_9 ? intpriority_reg_9 : _T_1856; // @[Mux.scala 98:16] + wire [3:0] _T_1858 = intpriority_reg_re_8 ? intpriority_reg_8 : _T_1857; // @[Mux.scala 98:16] + wire [3:0] _T_1859 = intpriority_reg_re_7 ? intpriority_reg_7 : _T_1858; // @[Mux.scala 98:16] + wire [3:0] _T_1860 = intpriority_reg_re_6 ? intpriority_reg_6 : _T_1859; // @[Mux.scala 98:16] + wire [3:0] _T_1861 = intpriority_reg_re_5 ? intpriority_reg_5 : _T_1860; // @[Mux.scala 98:16] + wire [3:0] _T_1862 = intpriority_reg_re_4 ? intpriority_reg_4 : _T_1861; // @[Mux.scala 98:16] + wire [3:0] _T_1863 = intpriority_reg_re_3 ? intpriority_reg_3 : _T_1862; // @[Mux.scala 98:16] + wire [3:0] _T_1864 = intpriority_reg_re_2 ? intpriority_reg_2 : _T_1863; // @[Mux.scala 98:16] + wire [3:0] intpriority_rd_out = intpriority_reg_re_1 ? intpriority_reg_1 : _T_1864; // @[Mux.scala 98:16] + wire [1:0] _T_1897 = gw_config_reg_re_31 ? gw_config_reg_31 : 2'h0; // @[Mux.scala 98:16] + wire [1:0] _T_1898 = gw_config_reg_re_30 ? gw_config_reg_30 : _T_1897; // @[Mux.scala 98:16] + wire [1:0] _T_1899 = gw_config_reg_re_29 ? gw_config_reg_29 : _T_1898; // @[Mux.scala 98:16] + wire [1:0] _T_1900 = gw_config_reg_re_28 ? gw_config_reg_28 : _T_1899; // @[Mux.scala 98:16] + wire [1:0] _T_1901 = gw_config_reg_re_27 ? gw_config_reg_27 : _T_1900; // @[Mux.scala 98:16] + wire [1:0] _T_1902 = gw_config_reg_re_26 ? gw_config_reg_26 : _T_1901; // @[Mux.scala 98:16] + wire [1:0] _T_1903 = gw_config_reg_re_25 ? gw_config_reg_25 : _T_1902; // @[Mux.scala 98:16] + wire [1:0] _T_1904 = gw_config_reg_re_24 ? gw_config_reg_24 : _T_1903; // @[Mux.scala 98:16] + wire [1:0] _T_1905 = gw_config_reg_re_23 ? gw_config_reg_23 : _T_1904; // @[Mux.scala 98:16] + wire [1:0] _T_1906 = gw_config_reg_re_22 ? gw_config_reg_22 : _T_1905; // @[Mux.scala 98:16] + wire [1:0] _T_1907 = gw_config_reg_re_21 ? gw_config_reg_21 : _T_1906; // @[Mux.scala 98:16] + wire [1:0] _T_1908 = gw_config_reg_re_20 ? gw_config_reg_20 : _T_1907; // @[Mux.scala 98:16] + wire [1:0] _T_1909 = gw_config_reg_re_19 ? gw_config_reg_19 : _T_1908; // @[Mux.scala 98:16] + wire [1:0] _T_1910 = gw_config_reg_re_18 ? gw_config_reg_18 : _T_1909; // @[Mux.scala 98:16] + wire [1:0] _T_1911 = gw_config_reg_re_17 ? gw_config_reg_17 : _T_1910; // @[Mux.scala 98:16] + wire [1:0] _T_1912 = gw_config_reg_re_16 ? gw_config_reg_16 : _T_1911; // @[Mux.scala 98:16] + wire [1:0] _T_1913 = gw_config_reg_re_15 ? gw_config_reg_15 : _T_1912; // @[Mux.scala 98:16] + wire [1:0] _T_1914 = gw_config_reg_re_14 ? gw_config_reg_14 : _T_1913; // @[Mux.scala 98:16] + wire [1:0] _T_1915 = gw_config_reg_re_13 ? gw_config_reg_13 : _T_1914; // @[Mux.scala 98:16] + wire [1:0] _T_1916 = gw_config_reg_re_12 ? gw_config_reg_12 : _T_1915; // @[Mux.scala 98:16] + wire [1:0] _T_1917 = gw_config_reg_re_11 ? gw_config_reg_11 : _T_1916; // @[Mux.scala 98:16] + wire [1:0] _T_1918 = gw_config_reg_re_10 ? gw_config_reg_10 : _T_1917; // @[Mux.scala 98:16] + wire [1:0] _T_1919 = gw_config_reg_re_9 ? gw_config_reg_9 : _T_1918; // @[Mux.scala 98:16] + wire [1:0] _T_1920 = gw_config_reg_re_8 ? gw_config_reg_8 : _T_1919; // @[Mux.scala 98:16] + wire [1:0] _T_1921 = gw_config_reg_re_7 ? gw_config_reg_7 : _T_1920; // @[Mux.scala 98:16] + wire [1:0] _T_1922 = gw_config_reg_re_6 ? gw_config_reg_6 : _T_1921; // @[Mux.scala 98:16] + wire [1:0] _T_1923 = gw_config_reg_re_5 ? gw_config_reg_5 : _T_1922; // @[Mux.scala 98:16] + wire [1:0] _T_1924 = gw_config_reg_re_4 ? gw_config_reg_4 : _T_1923; // @[Mux.scala 98:16] + wire [1:0] _T_1925 = gw_config_reg_re_3 ? gw_config_reg_3 : _T_1924; // @[Mux.scala 98:16] + wire [1:0] _T_1926 = gw_config_reg_re_2 ? gw_config_reg_2 : _T_1925; // @[Mux.scala 98:16] + wire [1:0] gw_config_rd_out = gw_config_reg_re_1 ? gw_config_reg_1 : _T_1926; // @[Mux.scala 98:16] + wire [31:0] _T_1931 = {28'h0,intpriority_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1934 = {31'h0,intenable_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1937 = {30'h0,gw_config_rd_out}; // @[Cat.scala 29:58] + wire [31:0] _T_1940 = {31'h0,config_reg}; // @[Cat.scala 29:58] + wire [14:0] address = picm_raddr_ff[14:0]; // @[el2_pic_ctl.scala 320:30] + wire _T_1980 = 15'h3000 == address; // @[Conditional.scala 37:30] + wire _T_1981 = 15'h4004 == address; // @[Conditional.scala 37:30] + wire _T_1982 = 15'h4008 == address; // @[Conditional.scala 37:30] + wire _T_1983 = 15'h400c == address; // @[Conditional.scala 37:30] + wire _T_1984 = 15'h4010 == address; // @[Conditional.scala 37:30] + wire _T_1985 = 15'h4014 == address; // @[Conditional.scala 37:30] + wire _T_1986 = 15'h4018 == address; // @[Conditional.scala 37:30] + wire _T_1987 = 15'h401c == address; // @[Conditional.scala 37:30] + wire _T_1988 = 15'h4020 == address; // @[Conditional.scala 37:30] + wire _T_1989 = 15'h4024 == address; // @[Conditional.scala 37:30] + wire _T_1990 = 15'h4028 == address; // @[Conditional.scala 37:30] + wire _T_1991 = 15'h402c == address; // @[Conditional.scala 37:30] + wire _T_1992 = 15'h4030 == address; // @[Conditional.scala 37:30] + wire _T_1993 = 15'h4034 == address; // @[Conditional.scala 37:30] + wire _T_1994 = 15'h4038 == address; // @[Conditional.scala 37:30] + wire _T_1995 = 15'h403c == address; // @[Conditional.scala 37:30] + wire _T_1996 = 15'h4040 == address; // @[Conditional.scala 37:30] + wire _T_1997 = 15'h4044 == address; // @[Conditional.scala 37:30] + wire _T_1998 = 15'h4048 == address; // @[Conditional.scala 37:30] + wire _T_1999 = 15'h404c == address; // @[Conditional.scala 37:30] + wire _T_2000 = 15'h4050 == address; // @[Conditional.scala 37:30] + wire _T_2001 = 15'h4054 == address; // @[Conditional.scala 37:30] + wire _T_2002 = 15'h4058 == address; // @[Conditional.scala 37:30] + wire _T_2003 = 15'h405c == address; // @[Conditional.scala 37:30] + wire _T_2004 = 15'h4060 == address; // @[Conditional.scala 37:30] + wire _T_2005 = 15'h4064 == address; // @[Conditional.scala 37:30] + wire _T_2006 = 15'h4068 == address; // @[Conditional.scala 37:30] + wire _T_2007 = 15'h406c == address; // @[Conditional.scala 37:30] + wire _T_2008 = 15'h4070 == address; // @[Conditional.scala 37:30] + wire _T_2009 = 15'h4074 == address; // @[Conditional.scala 37:30] + wire _T_2010 = 15'h4078 == address; // @[Conditional.scala 37:30] + wire _T_2011 = 15'h407c == address; // @[Conditional.scala 37:30] + wire _T_2012 = 15'h2004 == address; // @[Conditional.scala 37:30] + wire _T_2013 = 15'h2008 == address; // @[Conditional.scala 37:30] + wire _T_2014 = 15'h200c == address; // @[Conditional.scala 37:30] + wire _T_2015 = 15'h2010 == address; // @[Conditional.scala 37:30] + wire _T_2016 = 15'h2014 == address; // @[Conditional.scala 37:30] + wire _T_2017 = 15'h2018 == address; // @[Conditional.scala 37:30] + wire _T_2018 = 15'h201c == address; // @[Conditional.scala 37:30] + wire _T_2019 = 15'h2020 == address; // @[Conditional.scala 37:30] + wire _T_2020 = 15'h2024 == address; // @[Conditional.scala 37:30] + wire _T_2021 = 15'h2028 == address; // @[Conditional.scala 37:30] + wire _T_2022 = 15'h202c == address; // @[Conditional.scala 37:30] + wire _T_2023 = 15'h2030 == address; // @[Conditional.scala 37:30] + wire _T_2024 = 15'h2034 == address; // @[Conditional.scala 37:30] + wire _T_2025 = 15'h2038 == address; // @[Conditional.scala 37:30] + wire _T_2026 = 15'h203c == address; // @[Conditional.scala 37:30] + wire _T_2027 = 15'h2040 == address; // @[Conditional.scala 37:30] + wire _T_2028 = 15'h2044 == address; // @[Conditional.scala 37:30] + wire _T_2029 = 15'h2048 == address; // @[Conditional.scala 37:30] + wire _T_2030 = 15'h204c == address; // @[Conditional.scala 37:30] + wire _T_2031 = 15'h2050 == address; // @[Conditional.scala 37:30] + wire _T_2032 = 15'h2054 == address; // @[Conditional.scala 37:30] + wire _T_2033 = 15'h2058 == address; // @[Conditional.scala 37:30] + wire _T_2034 = 15'h205c == address; // @[Conditional.scala 37:30] + wire _T_2035 = 15'h2060 == address; // @[Conditional.scala 37:30] + wire _T_2036 = 15'h2064 == address; // @[Conditional.scala 37:30] + wire _T_2037 = 15'h2068 == address; // @[Conditional.scala 37:30] + wire _T_2038 = 15'h206c == address; // @[Conditional.scala 37:30] + wire _T_2039 = 15'h2070 == address; // @[Conditional.scala 37:30] + wire _T_2040 = 15'h2074 == address; // @[Conditional.scala 37:30] + wire _T_2041 = 15'h2078 == address; // @[Conditional.scala 37:30] + wire _T_2042 = 15'h207c == address; // @[Conditional.scala 37:30] + wire _T_2043 = 15'h4 == address; // @[Conditional.scala 37:30] + wire _T_2044 = 15'h8 == address; // @[Conditional.scala 37:30] + wire _T_2045 = 15'hc == address; // @[Conditional.scala 37:30] + wire _T_2046 = 15'h10 == address; // @[Conditional.scala 37:30] + wire _T_2047 = 15'h14 == address; // @[Conditional.scala 37:30] + wire _T_2048 = 15'h18 == address; // @[Conditional.scala 37:30] + wire _T_2049 = 15'h1c == address; // @[Conditional.scala 37:30] + wire _T_2050 = 15'h20 == address; // @[Conditional.scala 37:30] + wire _T_2051 = 15'h24 == address; // @[Conditional.scala 37:30] + wire _T_2052 = 15'h28 == address; // @[Conditional.scala 37:30] + wire _T_2053 = 15'h2c == address; // @[Conditional.scala 37:30] + wire _T_2054 = 15'h30 == address; // @[Conditional.scala 37:30] + wire _T_2055 = 15'h34 == address; // @[Conditional.scala 37:30] + wire _T_2056 = 15'h38 == address; // @[Conditional.scala 37:30] + wire _T_2057 = 15'h3c == address; // @[Conditional.scala 37:30] + wire _T_2058 = 15'h40 == address; // @[Conditional.scala 37:30] + wire _T_2059 = 15'h44 == address; // @[Conditional.scala 37:30] + wire _T_2060 = 15'h48 == address; // @[Conditional.scala 37:30] + wire _T_2061 = 15'h4c == address; // @[Conditional.scala 37:30] + wire _T_2062 = 15'h50 == address; // @[Conditional.scala 37:30] + wire _T_2063 = 15'h54 == address; // @[Conditional.scala 37:30] + wire _T_2064 = 15'h58 == address; // @[Conditional.scala 37:30] + wire _T_2065 = 15'h5c == address; // @[Conditional.scala 37:30] + wire _T_2066 = 15'h60 == address; // @[Conditional.scala 37:30] + wire _T_2067 = 15'h64 == address; // @[Conditional.scala 37:30] + wire _T_2068 = 15'h68 == address; // @[Conditional.scala 37:30] + wire _T_2069 = 15'h6c == address; // @[Conditional.scala 37:30] + wire _T_2070 = 15'h70 == address; // @[Conditional.scala 37:30] + wire _T_2071 = 15'h74 == address; // @[Conditional.scala 37:30] + wire _T_2072 = 15'h78 == address; // @[Conditional.scala 37:30] + wire _T_2073 = 15'h7c == address; // @[Conditional.scala 37:30] + wire [3:0] _GEN_126 = _T_2073 ? 4'h2 : 4'h1; // @[Conditional.scala 39:67] + wire [3:0] _GEN_127 = _T_2072 ? 4'h2 : _GEN_126; // @[Conditional.scala 39:67] + wire [3:0] _GEN_128 = _T_2071 ? 4'h2 : _GEN_127; // @[Conditional.scala 39:67] + wire [3:0] _GEN_129 = _T_2070 ? 4'h2 : _GEN_128; // @[Conditional.scala 39:67] + wire [3:0] _GEN_130 = _T_2069 ? 4'h2 : _GEN_129; // @[Conditional.scala 39:67] + wire [3:0] _GEN_131 = _T_2068 ? 4'h2 : _GEN_130; // @[Conditional.scala 39:67] + wire [3:0] _GEN_132 = _T_2067 ? 4'h2 : _GEN_131; // @[Conditional.scala 39:67] + wire [3:0] _GEN_133 = _T_2066 ? 4'h2 : _GEN_132; // @[Conditional.scala 39:67] + wire [3:0] _GEN_134 = _T_2065 ? 4'h2 : _GEN_133; // @[Conditional.scala 39:67] + wire [3:0] _GEN_135 = _T_2064 ? 4'h2 : _GEN_134; // @[Conditional.scala 39:67] + wire [3:0] _GEN_136 = _T_2063 ? 4'h2 : _GEN_135; // @[Conditional.scala 39:67] + wire [3:0] _GEN_137 = _T_2062 ? 4'h2 : _GEN_136; // @[Conditional.scala 39:67] + wire [3:0] _GEN_138 = _T_2061 ? 4'h2 : _GEN_137; // @[Conditional.scala 39:67] + wire [3:0] _GEN_139 = _T_2060 ? 4'h2 : _GEN_138; // @[Conditional.scala 39:67] + wire [3:0] _GEN_140 = _T_2059 ? 4'h2 : _GEN_139; // @[Conditional.scala 39:67] + wire [3:0] _GEN_141 = _T_2058 ? 4'h2 : _GEN_140; // @[Conditional.scala 39:67] + wire [3:0] _GEN_142 = _T_2057 ? 4'h2 : _GEN_141; // @[Conditional.scala 39:67] + wire [3:0] _GEN_143 = _T_2056 ? 4'h2 : _GEN_142; // @[Conditional.scala 39:67] + wire [3:0] _GEN_144 = _T_2055 ? 4'h2 : _GEN_143; // @[Conditional.scala 39:67] + wire [3:0] _GEN_145 = _T_2054 ? 4'h2 : _GEN_144; // @[Conditional.scala 39:67] + wire [3:0] _GEN_146 = _T_2053 ? 4'h2 : _GEN_145; // @[Conditional.scala 39:67] + wire [3:0] _GEN_147 = _T_2052 ? 4'h2 : _GEN_146; // @[Conditional.scala 39:67] + wire [3:0] _GEN_148 = _T_2051 ? 4'h2 : _GEN_147; // @[Conditional.scala 39:67] + wire [3:0] _GEN_149 = _T_2050 ? 4'h2 : _GEN_148; // @[Conditional.scala 39:67] + wire [3:0] _GEN_150 = _T_2049 ? 4'h2 : _GEN_149; // @[Conditional.scala 39:67] + wire [3:0] _GEN_151 = _T_2048 ? 4'h2 : _GEN_150; // @[Conditional.scala 39:67] + wire [3:0] _GEN_152 = _T_2047 ? 4'h2 : _GEN_151; // @[Conditional.scala 39:67] + wire [3:0] _GEN_153 = _T_2046 ? 4'h2 : _GEN_152; // @[Conditional.scala 39:67] + wire [3:0] _GEN_154 = _T_2045 ? 4'h2 : _GEN_153; // @[Conditional.scala 39:67] + wire [3:0] _GEN_155 = _T_2044 ? 4'h2 : _GEN_154; // @[Conditional.scala 39:67] + wire [3:0] _GEN_156 = _T_2043 ? 4'h2 : _GEN_155; // @[Conditional.scala 39:67] + wire [3:0] _GEN_157 = _T_2042 ? 4'h4 : _GEN_156; // @[Conditional.scala 39:67] + wire [3:0] _GEN_158 = _T_2041 ? 4'h4 : _GEN_157; // @[Conditional.scala 39:67] + wire [3:0] _GEN_159 = _T_2040 ? 4'h4 : _GEN_158; // @[Conditional.scala 39:67] + wire [3:0] _GEN_160 = _T_2039 ? 4'h4 : _GEN_159; // @[Conditional.scala 39:67] + wire [3:0] _GEN_161 = _T_2038 ? 4'h4 : _GEN_160; // @[Conditional.scala 39:67] + wire [3:0] _GEN_162 = _T_2037 ? 4'h4 : _GEN_161; // @[Conditional.scala 39:67] + wire [3:0] _GEN_163 = _T_2036 ? 4'h4 : _GEN_162; // @[Conditional.scala 39:67] + wire [3:0] _GEN_164 = _T_2035 ? 4'h4 : _GEN_163; // @[Conditional.scala 39:67] + wire [3:0] _GEN_165 = _T_2034 ? 4'h4 : _GEN_164; // @[Conditional.scala 39:67] + wire [3:0] _GEN_166 = _T_2033 ? 4'h4 : _GEN_165; // @[Conditional.scala 39:67] + wire [3:0] _GEN_167 = _T_2032 ? 4'h4 : _GEN_166; // @[Conditional.scala 39:67] + wire [3:0] _GEN_168 = _T_2031 ? 4'h4 : _GEN_167; // @[Conditional.scala 39:67] + wire [3:0] _GEN_169 = _T_2030 ? 4'h4 : _GEN_168; // @[Conditional.scala 39:67] + wire [3:0] _GEN_170 = _T_2029 ? 4'h4 : _GEN_169; // @[Conditional.scala 39:67] + wire [3:0] _GEN_171 = _T_2028 ? 4'h4 : _GEN_170; // @[Conditional.scala 39:67] + wire [3:0] _GEN_172 = _T_2027 ? 4'h4 : _GEN_171; // @[Conditional.scala 39:67] + wire [3:0] _GEN_173 = _T_2026 ? 4'h4 : _GEN_172; // @[Conditional.scala 39:67] + wire [3:0] _GEN_174 = _T_2025 ? 4'h4 : _GEN_173; // @[Conditional.scala 39:67] + wire [3:0] _GEN_175 = _T_2024 ? 4'h4 : _GEN_174; // @[Conditional.scala 39:67] + wire [3:0] _GEN_176 = _T_2023 ? 4'h4 : _GEN_175; // @[Conditional.scala 39:67] + wire [3:0] _GEN_177 = _T_2022 ? 4'h4 : _GEN_176; // @[Conditional.scala 39:67] + wire [3:0] _GEN_178 = _T_2021 ? 4'h4 : _GEN_177; // @[Conditional.scala 39:67] + wire [3:0] _GEN_179 = _T_2020 ? 4'h4 : _GEN_178; // @[Conditional.scala 39:67] + wire [3:0] _GEN_180 = _T_2019 ? 4'h4 : _GEN_179; // @[Conditional.scala 39:67] + wire [3:0] _GEN_181 = _T_2018 ? 4'h4 : _GEN_180; // @[Conditional.scala 39:67] + wire [3:0] _GEN_182 = _T_2017 ? 4'h4 : _GEN_181; // @[Conditional.scala 39:67] + wire [3:0] _GEN_183 = _T_2016 ? 4'h4 : _GEN_182; // @[Conditional.scala 39:67] + wire [3:0] _GEN_184 = _T_2015 ? 4'h4 : _GEN_183; // @[Conditional.scala 39:67] + wire [3:0] _GEN_185 = _T_2014 ? 4'h4 : _GEN_184; // @[Conditional.scala 39:67] + wire [3:0] _GEN_186 = _T_2013 ? 4'h4 : _GEN_185; // @[Conditional.scala 39:67] + wire [3:0] _GEN_187 = _T_2012 ? 4'h4 : _GEN_186; // @[Conditional.scala 39:67] + wire [3:0] _GEN_188 = _T_2011 ? 4'h8 : _GEN_187; // @[Conditional.scala 39:67] + wire [3:0] _GEN_189 = _T_2010 ? 4'h8 : _GEN_188; // @[Conditional.scala 39:67] + wire [3:0] _GEN_190 = _T_2009 ? 4'h8 : _GEN_189; // @[Conditional.scala 39:67] + wire [3:0] _GEN_191 = _T_2008 ? 4'h8 : _GEN_190; // @[Conditional.scala 39:67] + wire [3:0] _GEN_192 = _T_2007 ? 4'h8 : _GEN_191; // @[Conditional.scala 39:67] + wire [3:0] _GEN_193 = _T_2006 ? 4'h8 : _GEN_192; // @[Conditional.scala 39:67] + wire [3:0] _GEN_194 = _T_2005 ? 4'h8 : _GEN_193; // @[Conditional.scala 39:67] + wire [3:0] _GEN_195 = _T_2004 ? 4'h8 : _GEN_194; // @[Conditional.scala 39:67] + wire [3:0] _GEN_196 = _T_2003 ? 4'h8 : _GEN_195; // @[Conditional.scala 39:67] + wire [3:0] _GEN_197 = _T_2002 ? 4'h8 : _GEN_196; // @[Conditional.scala 39:67] + wire [3:0] _GEN_198 = _T_2001 ? 4'h8 : _GEN_197; // @[Conditional.scala 39:67] + wire [3:0] _GEN_199 = _T_2000 ? 4'h8 : _GEN_198; // @[Conditional.scala 39:67] + wire [3:0] _GEN_200 = _T_1999 ? 4'h8 : _GEN_199; // @[Conditional.scala 39:67] + wire [3:0] _GEN_201 = _T_1998 ? 4'h8 : _GEN_200; // @[Conditional.scala 39:67] + wire [3:0] _GEN_202 = _T_1997 ? 4'h8 : _GEN_201; // @[Conditional.scala 39:67] + wire [3:0] _GEN_203 = _T_1996 ? 4'h8 : _GEN_202; // @[Conditional.scala 39:67] + wire [3:0] _GEN_204 = _T_1995 ? 4'h8 : _GEN_203; // @[Conditional.scala 39:67] + wire [3:0] _GEN_205 = _T_1994 ? 4'h8 : _GEN_204; // @[Conditional.scala 39:67] + wire [3:0] _GEN_206 = _T_1993 ? 4'h8 : _GEN_205; // @[Conditional.scala 39:67] + wire [3:0] _GEN_207 = _T_1992 ? 4'h8 : _GEN_206; // @[Conditional.scala 39:67] + wire [3:0] _GEN_208 = _T_1991 ? 4'h8 : _GEN_207; // @[Conditional.scala 39:67] + wire [3:0] _GEN_209 = _T_1990 ? 4'h8 : _GEN_208; // @[Conditional.scala 39:67] + wire [3:0] _GEN_210 = _T_1989 ? 4'h8 : _GEN_209; // @[Conditional.scala 39:67] + wire [3:0] _GEN_211 = _T_1988 ? 4'h8 : _GEN_210; // @[Conditional.scala 39:67] + wire [3:0] _GEN_212 = _T_1987 ? 4'h8 : _GEN_211; // @[Conditional.scala 39:67] + wire [3:0] _GEN_213 = _T_1986 ? 4'h8 : _GEN_212; // @[Conditional.scala 39:67] + wire [3:0] _GEN_214 = _T_1985 ? 4'h8 : _GEN_213; // @[Conditional.scala 39:67] + wire [3:0] _GEN_215 = _T_1984 ? 4'h8 : _GEN_214; // @[Conditional.scala 39:67] + wire [3:0] _GEN_216 = _T_1983 ? 4'h8 : _GEN_215; // @[Conditional.scala 39:67] + wire [3:0] _GEN_217 = _T_1982 ? 4'h8 : _GEN_216; // @[Conditional.scala 39:67] + wire [3:0] _GEN_218 = _T_1981 ? 4'h8 : _GEN_217; // @[Conditional.scala 39:67] + wire [3:0] mask = _T_1980 ? 4'h4 : _GEN_218; // @[Conditional.scala 40:58] + wire _T_1942 = picm_mken_ff & mask[3]; // @[el2_pic_ctl.scala 313:19] + wire _T_1947 = picm_mken_ff & mask[2]; // @[el2_pic_ctl.scala 314:19] + wire _T_1952 = picm_mken_ff & mask[1]; // @[el2_pic_ctl.scala 315:19] + wire [31:0] _T_1960 = intpend_reg_read ? intpend_rd_out : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1961 = _T_21 ? _T_1931 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1962 = _T_24 ? _T_1934 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1963 = _T_27 ? _T_1937 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1964 = config_reg_re ? _T_1940 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1965 = _T_1942 ? 32'h3 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1966 = _T_1947 ? 32'h1 : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1967 = _T_1952 ? 32'hf : 32'h0; // @[Mux.scala 27:72] + wire [31:0] _T_1969 = _T_1960 | _T_1961; // @[Mux.scala 27:72] + wire [31:0] _T_1970 = _T_1969 | _T_1962; // @[Mux.scala 27:72] + wire [31:0] _T_1971 = _T_1970 | _T_1963; // @[Mux.scala 27:72] + wire [31:0] _T_1972 = _T_1971 | _T_1964; // @[Mux.scala 27:72] + wire [31:0] _T_1973 = _T_1972 | _T_1965; // @[Mux.scala 27:72] + wire [31:0] _T_1974 = _T_1973 | _T_1966; // @[Mux.scala 27:72] + wire [31:0] picm_rd_data_in = _T_1974 | _T_1967; // @[Mux.scala 27:72] + wire [7:0] _T_1703 = out_id_34; // @[el2_pic_ctl.scala 38:12] + wire [7:0] level_intpend_id_5_0 = out_id_34; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] level_intpend_id_1_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_1_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_2_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_3_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_4 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_4_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_1 = _T_1699; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 246:43] + wire [7:0] level_intpend_id_5_2 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30 el2_pic_ctl.scala 243:46] + wire [7:0] level_intpend_id_5_3 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_4 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_5 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_6 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_7 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_8 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_9 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_10 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_11 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_12 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_13 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_14 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_15 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_16 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_17 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_18 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_19 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_20 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_21 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_22 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_23 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_24 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_25 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_26 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_27 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_28 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_29 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_30 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_31 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_32 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + wire [7:0] level_intpend_id_5_33 = 8'h0; // @[el2_pic_ctl.scala 228:32 el2_pic_ctl.scala 232:30] + rvclkhdr rvclkhdr ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) ); - rvclkhdr pic_data_c1_cgc ( // @[el2_pic_ctrl.scala 166:32] - .io_l1clk(pic_data_c1_cgc_io_l1clk), - .io_clk(pic_data_c1_cgc_io_clk), - .io_en(pic_data_c1_cgc_io_en), - .io_scan_mode(pic_data_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_1 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - rvclkhdr pic_pri_c1_cgc ( // @[el2_pic_ctrl.scala 170:31] - .io_l1clk(pic_pri_c1_cgc_io_l1clk), - .io_clk(pic_pri_c1_cgc_io_clk), - .io_en(pic_pri_c1_cgc_io_en), - .io_scan_mode(pic_pri_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_2 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) ); - rvclkhdr pic_int_c1_cgc ( // @[el2_pic_ctrl.scala 174:32] - .io_l1clk(pic_int_c1_cgc_io_l1clk), - .io_clk(pic_int_c1_cgc_io_clk), - .io_en(pic_int_c1_cgc_io_en), - .io_scan_mode(pic_int_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_3 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) ); - rvclkhdr gw_config_c1_cgc ( // @[el2_pic_ctrl.scala 178:33] - .io_l1clk(gw_config_c1_cgc_io_l1clk), - .io_clk(gw_config_c1_cgc_io_clk), - .io_en(gw_config_c1_cgc_io_en), - .io_scan_mode(gw_config_c1_cgc_io_scan_mode) + rvclkhdr rvclkhdr_4 ( // @[el2_lib.scala 483:22] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) ); - rvsyncss sync_inst ( // @[el2_pic_ctrl.scala 185:26] - .reset(sync_inst_reset), - .io_din(sync_inst_io_din), - .io_dout(sync_inst_io_dout), - .io_clk(sync_inst_io_clk) - ); - assign io_mexintpend = 1'h0; // @[el2_pic_ctrl.scala 31:20 el2_pic_ctrl.scala 210:40] - assign io_claimid = 8'h0; // @[el2_pic_ctrl.scala 32:20 el2_pic_ctrl.scala 205:37] - assign io_pl = _T_36; // @[el2_pic_ctrl.scala 33:20 el2_pic_ctrl.scala 206:32] - assign io_picm_rd_data = 32'h0; // @[el2_pic_ctrl.scala 34:20] - assign io_mhwakeup = _T_45; // @[el2_pic_ctrl.scala 35:20 el2_pic_ctrl.scala 213:38] - assign io_test = {sync_inst_io_dout,io_extintsrc_req[0]}; // @[el2_pic_ctrl.scala 190:11] - assign pic_addr_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 164:34] - assign pic_addr_c1_cgc_io_en = _T_18 | io_clk_override; // @[el2_pic_ctrl.scala 163:34] - assign pic_addr_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 164:89] - assign pic_data_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 168:34] - assign pic_data_c1_cgc_io_en = io_picm_wren | io_clk_override; // @[el2_pic_ctrl.scala 167:34] - assign pic_data_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 168:89] - assign pic_pri_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 172:33] - assign pic_pri_c1_cgc_io_en = _T_21 | io_clk_override; // @[el2_pic_ctrl.scala 171:33] - assign pic_pri_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 172:87] - assign pic_int_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 176:33] - assign pic_int_c1_cgc_io_en = _T_24 | io_clk_override; // @[el2_pic_ctrl.scala 175:33] - assign pic_int_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 176:87] - assign gw_config_c1_cgc_io_clk = clock; // @[el2_pic_ctrl.scala 180:35] - assign gw_config_c1_cgc_io_en = _T_27 | io_clk_override; // @[el2_pic_ctrl.scala 179:35] - assign gw_config_c1_cgc_io_scan_mode = io_scan_mode; // @[el2_pic_ctrl.scala 180:91] - assign sync_inst_reset = reset; - assign sync_inst_io_din = io_extintsrc_req[31:1]; // @[el2_pic_ctrl.scala 186:29] - assign sync_inst_io_clk = io_free_clk; // @[el2_pic_ctrl.scala 188:29] + assign io_mexintpend = _T_1722; // @[el2_pic_ctl.scala 281:17] + assign io_claimid = _T_1714; // @[el2_pic_ctl.scala 276:37] + assign io_pl = _T_1715; // @[el2_pic_ctl.scala 277:32] + assign io_picm_rd_data = picm_bypass_ff ? picm_wr_data_ff : picm_rd_data_in; // @[el2_pic_ctl.scala 319:19] + assign io_mhwakeup = _T_1724; // @[el2_pic_ctl.scala 284:15] + assign rvclkhdr_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_io_en = _T_19 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_1_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_1_io_en = io_picm_wren | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_2_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_2_io_en = _T_22 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_3_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_3_io_en = _T_25 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] + assign rvclkhdr_4_io_clk = clock; // @[el2_lib.scala 484:17] + assign rvclkhdr_4_io_en = _T_28 | io_clk_override; // @[el2_lib.scala 485:16] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[el2_lib.scala 486:23] `ifdef RANDOMIZE_GARBAGE_ASSIGN `define RANDOMIZE `endif @@ -289,13 +1942,271 @@ initial begin _RAND_3 = {1{`RANDOM}}; picm_rden_ff = _RAND_3[0:0]; _RAND_4 = {1{`RANDOM}}; - picm_wr_data_ff = _RAND_4[31:0]; + picm_mken_ff = _RAND_4[0:0]; _RAND_5 = {1{`RANDOM}}; - config_reg = _RAND_5[0:0]; + picm_wr_data_ff = _RAND_5[31:0]; _RAND_6 = {1{`RANDOM}}; - _T_36 = _RAND_6[3:0]; + _T_33 = _RAND_6[30:0]; _RAND_7 = {1{`RANDOM}}; - _T_45 = _RAND_7[0:0]; + _T_34 = _RAND_7[30:0]; + _RAND_8 = {1{`RANDOM}}; + intpriority_reg_1 = _RAND_8[3:0]; + _RAND_9 = {1{`RANDOM}}; + intpriority_reg_2 = _RAND_9[3:0]; + _RAND_10 = {1{`RANDOM}}; + intpriority_reg_3 = _RAND_10[3:0]; + _RAND_11 = {1{`RANDOM}}; + intpriority_reg_4 = _RAND_11[3:0]; + _RAND_12 = {1{`RANDOM}}; + intpriority_reg_5 = _RAND_12[3:0]; + _RAND_13 = {1{`RANDOM}}; + intpriority_reg_6 = _RAND_13[3:0]; + _RAND_14 = {1{`RANDOM}}; + intpriority_reg_7 = _RAND_14[3:0]; + _RAND_15 = {1{`RANDOM}}; + intpriority_reg_8 = _RAND_15[3:0]; + _RAND_16 = {1{`RANDOM}}; + intpriority_reg_9 = _RAND_16[3:0]; + _RAND_17 = {1{`RANDOM}}; + intpriority_reg_10 = _RAND_17[3:0]; + _RAND_18 = {1{`RANDOM}}; + intpriority_reg_11 = _RAND_18[3:0]; + _RAND_19 = {1{`RANDOM}}; + intpriority_reg_12 = _RAND_19[3:0]; + _RAND_20 = {1{`RANDOM}}; + intpriority_reg_13 = _RAND_20[3:0]; + _RAND_21 = {1{`RANDOM}}; + intpriority_reg_14 = _RAND_21[3:0]; + _RAND_22 = {1{`RANDOM}}; + intpriority_reg_15 = _RAND_22[3:0]; + _RAND_23 = {1{`RANDOM}}; + intpriority_reg_16 = _RAND_23[3:0]; + _RAND_24 = {1{`RANDOM}}; + intpriority_reg_17 = _RAND_24[3:0]; + _RAND_25 = {1{`RANDOM}}; + intpriority_reg_18 = _RAND_25[3:0]; + _RAND_26 = {1{`RANDOM}}; + intpriority_reg_19 = _RAND_26[3:0]; + _RAND_27 = {1{`RANDOM}}; + intpriority_reg_20 = _RAND_27[3:0]; + _RAND_28 = {1{`RANDOM}}; + intpriority_reg_21 = _RAND_28[3:0]; + _RAND_29 = {1{`RANDOM}}; + intpriority_reg_22 = _RAND_29[3:0]; + _RAND_30 = {1{`RANDOM}}; + intpriority_reg_23 = _RAND_30[3:0]; + _RAND_31 = {1{`RANDOM}}; + intpriority_reg_24 = _RAND_31[3:0]; + _RAND_32 = {1{`RANDOM}}; + intpriority_reg_25 = _RAND_32[3:0]; + _RAND_33 = {1{`RANDOM}}; + intpriority_reg_26 = _RAND_33[3:0]; + _RAND_34 = {1{`RANDOM}}; + intpriority_reg_27 = _RAND_34[3:0]; + _RAND_35 = {1{`RANDOM}}; + intpriority_reg_28 = _RAND_35[3:0]; + _RAND_36 = {1{`RANDOM}}; + intpriority_reg_29 = _RAND_36[3:0]; + _RAND_37 = {1{`RANDOM}}; + intpriority_reg_30 = _RAND_37[3:0]; + _RAND_38 = {1{`RANDOM}}; + intpriority_reg_31 = _RAND_38[3:0]; + _RAND_39 = {1{`RANDOM}}; + intenable_reg_1 = _RAND_39[0:0]; + _RAND_40 = {1{`RANDOM}}; + intenable_reg_2 = _RAND_40[0:0]; + _RAND_41 = {1{`RANDOM}}; + intenable_reg_3 = _RAND_41[0:0]; + _RAND_42 = {1{`RANDOM}}; + intenable_reg_4 = _RAND_42[0:0]; + _RAND_43 = {1{`RANDOM}}; + intenable_reg_5 = _RAND_43[0:0]; + _RAND_44 = {1{`RANDOM}}; + intenable_reg_6 = _RAND_44[0:0]; + _RAND_45 = {1{`RANDOM}}; + intenable_reg_7 = _RAND_45[0:0]; + _RAND_46 = {1{`RANDOM}}; + intenable_reg_8 = _RAND_46[0:0]; + _RAND_47 = {1{`RANDOM}}; + intenable_reg_9 = _RAND_47[0:0]; + _RAND_48 = {1{`RANDOM}}; + intenable_reg_10 = _RAND_48[0:0]; + _RAND_49 = {1{`RANDOM}}; + intenable_reg_11 = _RAND_49[0:0]; + _RAND_50 = {1{`RANDOM}}; + intenable_reg_12 = _RAND_50[0:0]; + _RAND_51 = {1{`RANDOM}}; + intenable_reg_13 = _RAND_51[0:0]; + _RAND_52 = {1{`RANDOM}}; + intenable_reg_14 = _RAND_52[0:0]; + _RAND_53 = {1{`RANDOM}}; + intenable_reg_15 = _RAND_53[0:0]; + _RAND_54 = {1{`RANDOM}}; + intenable_reg_16 = _RAND_54[0:0]; + _RAND_55 = {1{`RANDOM}}; + intenable_reg_17 = _RAND_55[0:0]; + _RAND_56 = {1{`RANDOM}}; + intenable_reg_18 = _RAND_56[0:0]; + _RAND_57 = {1{`RANDOM}}; + intenable_reg_19 = _RAND_57[0:0]; + _RAND_58 = {1{`RANDOM}}; + intenable_reg_20 = _RAND_58[0:0]; + _RAND_59 = {1{`RANDOM}}; + intenable_reg_21 = _RAND_59[0:0]; + _RAND_60 = {1{`RANDOM}}; + intenable_reg_22 = _RAND_60[0:0]; + _RAND_61 = {1{`RANDOM}}; + intenable_reg_23 = _RAND_61[0:0]; + _RAND_62 = {1{`RANDOM}}; + intenable_reg_24 = _RAND_62[0:0]; + _RAND_63 = {1{`RANDOM}}; + intenable_reg_25 = _RAND_63[0:0]; + _RAND_64 = {1{`RANDOM}}; + intenable_reg_26 = _RAND_64[0:0]; + _RAND_65 = {1{`RANDOM}}; + intenable_reg_27 = _RAND_65[0:0]; + _RAND_66 = {1{`RANDOM}}; + intenable_reg_28 = _RAND_66[0:0]; + _RAND_67 = {1{`RANDOM}}; + intenable_reg_29 = _RAND_67[0:0]; + _RAND_68 = {1{`RANDOM}}; + intenable_reg_30 = _RAND_68[0:0]; + _RAND_69 = {1{`RANDOM}}; + intenable_reg_31 = _RAND_69[0:0]; + _RAND_70 = {1{`RANDOM}}; + gw_config_reg_1 = _RAND_70[1:0]; + _RAND_71 = {1{`RANDOM}}; + gw_config_reg_2 = _RAND_71[1:0]; + _RAND_72 = {1{`RANDOM}}; + gw_config_reg_3 = _RAND_72[1:0]; + _RAND_73 = {1{`RANDOM}}; + gw_config_reg_4 = _RAND_73[1:0]; + _RAND_74 = {1{`RANDOM}}; + gw_config_reg_5 = _RAND_74[1:0]; + _RAND_75 = {1{`RANDOM}}; + gw_config_reg_6 = _RAND_75[1:0]; + _RAND_76 = {1{`RANDOM}}; + gw_config_reg_7 = _RAND_76[1:0]; + _RAND_77 = {1{`RANDOM}}; + gw_config_reg_8 = _RAND_77[1:0]; + _RAND_78 = {1{`RANDOM}}; + gw_config_reg_9 = _RAND_78[1:0]; + _RAND_79 = {1{`RANDOM}}; + gw_config_reg_10 = _RAND_79[1:0]; + _RAND_80 = {1{`RANDOM}}; + gw_config_reg_11 = _RAND_80[1:0]; + _RAND_81 = {1{`RANDOM}}; + gw_config_reg_12 = _RAND_81[1:0]; + _RAND_82 = {1{`RANDOM}}; + gw_config_reg_13 = _RAND_82[1:0]; + _RAND_83 = {1{`RANDOM}}; + gw_config_reg_14 = _RAND_83[1:0]; + _RAND_84 = {1{`RANDOM}}; + gw_config_reg_15 = _RAND_84[1:0]; + _RAND_85 = {1{`RANDOM}}; + gw_config_reg_16 = _RAND_85[1:0]; + _RAND_86 = {1{`RANDOM}}; + gw_config_reg_17 = _RAND_86[1:0]; + _RAND_87 = {1{`RANDOM}}; + gw_config_reg_18 = _RAND_87[1:0]; + _RAND_88 = {1{`RANDOM}}; + gw_config_reg_19 = _RAND_88[1:0]; + _RAND_89 = {1{`RANDOM}}; + gw_config_reg_20 = _RAND_89[1:0]; + _RAND_90 = {1{`RANDOM}}; + gw_config_reg_21 = _RAND_90[1:0]; + _RAND_91 = {1{`RANDOM}}; + gw_config_reg_22 = _RAND_91[1:0]; + _RAND_92 = {1{`RANDOM}}; + gw_config_reg_23 = _RAND_92[1:0]; + _RAND_93 = {1{`RANDOM}}; + gw_config_reg_24 = _RAND_93[1:0]; + _RAND_94 = {1{`RANDOM}}; + gw_config_reg_25 = _RAND_94[1:0]; + _RAND_95 = {1{`RANDOM}}; + gw_config_reg_26 = _RAND_95[1:0]; + _RAND_96 = {1{`RANDOM}}; + gw_config_reg_27 = _RAND_96[1:0]; + _RAND_97 = {1{`RANDOM}}; + gw_config_reg_28 = _RAND_97[1:0]; + _RAND_98 = {1{`RANDOM}}; + gw_config_reg_29 = _RAND_98[1:0]; + _RAND_99 = {1{`RANDOM}}; + gw_config_reg_30 = _RAND_99[1:0]; + _RAND_100 = {1{`RANDOM}}; + gw_config_reg_31 = _RAND_100[1:0]; + _RAND_101 = {1{`RANDOM}}; + gw_int_pending = _RAND_101[0:0]; + _RAND_102 = {1{`RANDOM}}; + gw_int_pending_1 = _RAND_102[0:0]; + _RAND_103 = {1{`RANDOM}}; + gw_int_pending_2 = _RAND_103[0:0]; + _RAND_104 = {1{`RANDOM}}; + gw_int_pending_3 = _RAND_104[0:0]; + _RAND_105 = {1{`RANDOM}}; + gw_int_pending_4 = _RAND_105[0:0]; + _RAND_106 = {1{`RANDOM}}; + gw_int_pending_5 = _RAND_106[0:0]; + _RAND_107 = {1{`RANDOM}}; + gw_int_pending_6 = _RAND_107[0:0]; + _RAND_108 = {1{`RANDOM}}; + gw_int_pending_7 = _RAND_108[0:0]; + _RAND_109 = {1{`RANDOM}}; + gw_int_pending_8 = _RAND_109[0:0]; + _RAND_110 = {1{`RANDOM}}; + gw_int_pending_9 = _RAND_110[0:0]; + _RAND_111 = {1{`RANDOM}}; + gw_int_pending_10 = _RAND_111[0:0]; + _RAND_112 = {1{`RANDOM}}; + gw_int_pending_11 = _RAND_112[0:0]; + _RAND_113 = {1{`RANDOM}}; + gw_int_pending_12 = _RAND_113[0:0]; + _RAND_114 = {1{`RANDOM}}; + gw_int_pending_13 = _RAND_114[0:0]; + _RAND_115 = {1{`RANDOM}}; + gw_int_pending_14 = _RAND_115[0:0]; + _RAND_116 = {1{`RANDOM}}; + gw_int_pending_15 = _RAND_116[0:0]; + _RAND_117 = {1{`RANDOM}}; + gw_int_pending_16 = _RAND_117[0:0]; + _RAND_118 = {1{`RANDOM}}; + gw_int_pending_17 = _RAND_118[0:0]; + _RAND_119 = {1{`RANDOM}}; + gw_int_pending_18 = _RAND_119[0:0]; + _RAND_120 = {1{`RANDOM}}; + gw_int_pending_19 = _RAND_120[0:0]; + _RAND_121 = {1{`RANDOM}}; + gw_int_pending_20 = _RAND_121[0:0]; + _RAND_122 = {1{`RANDOM}}; + gw_int_pending_21 = _RAND_122[0:0]; + _RAND_123 = {1{`RANDOM}}; + gw_int_pending_22 = _RAND_123[0:0]; + _RAND_124 = {1{`RANDOM}}; + gw_int_pending_23 = _RAND_124[0:0]; + _RAND_125 = {1{`RANDOM}}; + gw_int_pending_24 = _RAND_125[0:0]; + _RAND_126 = {1{`RANDOM}}; + gw_int_pending_25 = _RAND_126[0:0]; + _RAND_127 = {1{`RANDOM}}; + gw_int_pending_26 = _RAND_127[0:0]; + _RAND_128 = {1{`RANDOM}}; + gw_int_pending_27 = _RAND_128[0:0]; + _RAND_129 = {1{`RANDOM}}; + gw_int_pending_28 = _RAND_129[0:0]; + _RAND_130 = {1{`RANDOM}}; + gw_int_pending_29 = _RAND_130[0:0]; + _RAND_131 = {1{`RANDOM}}; + gw_int_pending_30 = _RAND_131[0:0]; + _RAND_132 = {1{`RANDOM}}; + config_reg = _RAND_132[0:0]; + _RAND_133 = {1{`RANDOM}}; + _T_1714 = _RAND_133[7:0]; + _RAND_134 = {1{`RANDOM}}; + _T_1715 = _RAND_134[3:0]; + _RAND_135 = {1{`RANDOM}}; + _T_1722 = _RAND_135[0:0]; + _RAND_136 = {1{`RANDOM}}; + _T_1724 = _RAND_136[0:0]; `endif // RANDOMIZE_REG_INIT if (reset) begin picm_raddr_ff = 32'h0; @@ -309,17 +2220,404 @@ initial begin if (reset) begin picm_rden_ff = 1'h0; end + if (reset) begin + picm_mken_ff = 1'h0; + end if (reset) begin picm_wr_data_ff = 32'h0; end + if (reset) begin + _T_33 = 31'h0; + end + if (reset) begin + _T_34 = 31'h0; + end + if (reset) begin + intpriority_reg_1 = 4'h0; + end + if (reset) begin + intpriority_reg_2 = 4'h0; + end + if (reset) begin + intpriority_reg_3 = 4'h0; + end + if (reset) begin + intpriority_reg_4 = 4'h0; + end + if (reset) begin + intpriority_reg_5 = 4'h0; + end + if (reset) begin + intpriority_reg_6 = 4'h0; + end + if (reset) begin + intpriority_reg_7 = 4'h0; + end + if (reset) begin + intpriority_reg_8 = 4'h0; + end + if (reset) begin + intpriority_reg_9 = 4'h0; + end + if (reset) begin + intpriority_reg_10 = 4'h0; + end + if (reset) begin + intpriority_reg_11 = 4'h0; + end + if (reset) begin + intpriority_reg_12 = 4'h0; + end + if (reset) begin + intpriority_reg_13 = 4'h0; + end + if (reset) begin + intpriority_reg_14 = 4'h0; + end + if (reset) begin + intpriority_reg_15 = 4'h0; + end + if (reset) begin + intpriority_reg_16 = 4'h0; + end + if (reset) begin + intpriority_reg_17 = 4'h0; + end + if (reset) begin + intpriority_reg_18 = 4'h0; + end + if (reset) begin + intpriority_reg_19 = 4'h0; + end + if (reset) begin + intpriority_reg_20 = 4'h0; + end + if (reset) begin + intpriority_reg_21 = 4'h0; + end + if (reset) begin + intpriority_reg_22 = 4'h0; + end + if (reset) begin + intpriority_reg_23 = 4'h0; + end + if (reset) begin + intpriority_reg_24 = 4'h0; + end + if (reset) begin + intpriority_reg_25 = 4'h0; + end + if (reset) begin + intpriority_reg_26 = 4'h0; + end + if (reset) begin + intpriority_reg_27 = 4'h0; + end + if (reset) begin + intpriority_reg_28 = 4'h0; + end + if (reset) begin + intpriority_reg_29 = 4'h0; + end + if (reset) begin + intpriority_reg_30 = 4'h0; + end + if (reset) begin + intpriority_reg_31 = 4'h0; + end + if (reset) begin + intenable_reg_1 = 1'h0; + end + if (reset) begin + intenable_reg_2 = 1'h0; + end + if (reset) begin + intenable_reg_3 = 1'h0; + end + if (reset) begin + intenable_reg_4 = 1'h0; + end + if (reset) begin + intenable_reg_5 = 1'h0; + end + if (reset) begin + intenable_reg_6 = 1'h0; + end + if (reset) begin + intenable_reg_7 = 1'h0; + end + if (reset) begin + intenable_reg_8 = 1'h0; + end + if (reset) begin + intenable_reg_9 = 1'h0; + end + if (reset) begin + intenable_reg_10 = 1'h0; + end + if (reset) begin + intenable_reg_11 = 1'h0; + end + if (reset) begin + intenable_reg_12 = 1'h0; + end + if (reset) begin + intenable_reg_13 = 1'h0; + end + if (reset) begin + intenable_reg_14 = 1'h0; + end + if (reset) begin + intenable_reg_15 = 1'h0; + end + if (reset) begin + intenable_reg_16 = 1'h0; + end + if (reset) begin + intenable_reg_17 = 1'h0; + end + if (reset) begin + intenable_reg_18 = 1'h0; + end + if (reset) begin + intenable_reg_19 = 1'h0; + end + if (reset) begin + intenable_reg_20 = 1'h0; + end + if (reset) begin + intenable_reg_21 = 1'h0; + end + if (reset) begin + intenable_reg_22 = 1'h0; + end + if (reset) begin + intenable_reg_23 = 1'h0; + end + if (reset) begin + intenable_reg_24 = 1'h0; + end + if (reset) begin + intenable_reg_25 = 1'h0; + end + if (reset) begin + intenable_reg_26 = 1'h0; + end + if (reset) begin + intenable_reg_27 = 1'h0; + end + if (reset) begin + intenable_reg_28 = 1'h0; + end + if (reset) begin + intenable_reg_29 = 1'h0; + end + if (reset) begin + intenable_reg_30 = 1'h0; + end + if (reset) begin + intenable_reg_31 = 1'h0; + end + if (reset) begin + gw_config_reg_1 = 2'h0; + end + if (reset) begin + gw_config_reg_2 = 2'h0; + end + if (reset) begin + gw_config_reg_3 = 2'h0; + end + if (reset) begin + gw_config_reg_4 = 2'h0; + end + if (reset) begin + gw_config_reg_5 = 2'h0; + end + if (reset) begin + gw_config_reg_6 = 2'h0; + end + if (reset) begin + gw_config_reg_7 = 2'h0; + end + if (reset) begin + gw_config_reg_8 = 2'h0; + end + if (reset) begin + gw_config_reg_9 = 2'h0; + end + if (reset) begin + gw_config_reg_10 = 2'h0; + end + if (reset) begin + gw_config_reg_11 = 2'h0; + end + if (reset) begin + gw_config_reg_12 = 2'h0; + end + if (reset) begin + gw_config_reg_13 = 2'h0; + end + if (reset) begin + gw_config_reg_14 = 2'h0; + end + if (reset) begin + gw_config_reg_15 = 2'h0; + end + if (reset) begin + gw_config_reg_16 = 2'h0; + end + if (reset) begin + gw_config_reg_17 = 2'h0; + end + if (reset) begin + gw_config_reg_18 = 2'h0; + end + if (reset) begin + gw_config_reg_19 = 2'h0; + end + if (reset) begin + gw_config_reg_20 = 2'h0; + end + if (reset) begin + gw_config_reg_21 = 2'h0; + end + if (reset) begin + gw_config_reg_22 = 2'h0; + end + if (reset) begin + gw_config_reg_23 = 2'h0; + end + if (reset) begin + gw_config_reg_24 = 2'h0; + end + if (reset) begin + gw_config_reg_25 = 2'h0; + end + if (reset) begin + gw_config_reg_26 = 2'h0; + end + if (reset) begin + gw_config_reg_27 = 2'h0; + end + if (reset) begin + gw_config_reg_28 = 2'h0; + end + if (reset) begin + gw_config_reg_29 = 2'h0; + end + if (reset) begin + gw_config_reg_30 = 2'h0; + end + if (reset) begin + gw_config_reg_31 = 2'h0; + end + if (reset) begin + gw_int_pending = 1'h0; + end + if (reset) begin + gw_int_pending_1 = 1'h0; + end + if (reset) begin + gw_int_pending_2 = 1'h0; + end + if (reset) begin + gw_int_pending_3 = 1'h0; + end + if (reset) begin + gw_int_pending_4 = 1'h0; + end + if (reset) begin + gw_int_pending_5 = 1'h0; + end + if (reset) begin + gw_int_pending_6 = 1'h0; + end + if (reset) begin + gw_int_pending_7 = 1'h0; + end + if (reset) begin + gw_int_pending_8 = 1'h0; + end + if (reset) begin + gw_int_pending_9 = 1'h0; + end + if (reset) begin + gw_int_pending_10 = 1'h0; + end + if (reset) begin + gw_int_pending_11 = 1'h0; + end + if (reset) begin + gw_int_pending_12 = 1'h0; + end + if (reset) begin + gw_int_pending_13 = 1'h0; + end + if (reset) begin + gw_int_pending_14 = 1'h0; + end + if (reset) begin + gw_int_pending_15 = 1'h0; + end + if (reset) begin + gw_int_pending_16 = 1'h0; + end + if (reset) begin + gw_int_pending_17 = 1'h0; + end + if (reset) begin + gw_int_pending_18 = 1'h0; + end + if (reset) begin + gw_int_pending_19 = 1'h0; + end + if (reset) begin + gw_int_pending_20 = 1'h0; + end + if (reset) begin + gw_int_pending_21 = 1'h0; + end + if (reset) begin + gw_int_pending_22 = 1'h0; + end + if (reset) begin + gw_int_pending_23 = 1'h0; + end + if (reset) begin + gw_int_pending_24 = 1'h0; + end + if (reset) begin + gw_int_pending_25 = 1'h0; + end + if (reset) begin + gw_int_pending_26 = 1'h0; + end + if (reset) begin + gw_int_pending_27 = 1'h0; + end + if (reset) begin + gw_int_pending_28 = 1'h0; + end + if (reset) begin + gw_int_pending_29 = 1'h0; + end + if (reset) begin + gw_int_pending_30 = 1'h0; + end if (reset) begin config_reg = 1'h0; end if (reset) begin - _T_36 = 4'h0; + _T_1714 = 8'h0; end if (reset) begin - _T_45 = 1'h0; + _T_1715 = 4'h0; + end + if (reset) begin + _T_1722 = 1'h0; + end + if (reset) begin + _T_1724 = 1'h0; end `endif // RANDOMIZE end // initial @@ -355,6 +2653,13 @@ end // initial picm_rden_ff <= io_picm_rden; end end + always @(posedge io_active_clk or posedge reset) begin + if (reset) begin + picm_mken_ff <= 1'h0; + end else begin + picm_mken_ff <= io_picm_mken; + end + end always @(posedge pic_data_c1_clk or posedge reset) begin if (reset) begin picm_wr_data_ff <= 32'h0; @@ -362,27 +2667,923 @@ end // initial picm_wr_data_ff <= io_picm_wr_data; end end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_33 <= 31'h0; + end else begin + _T_33 <= io_extintsrc_req[31:1]; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_34 <= 31'h0; + end else begin + _T_34 <= _T_33; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_1 <= 4'h0; + end else if (intpriority_reg_we_1) begin + intpriority_reg_1 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_2 <= 4'h0; + end else if (intpriority_reg_we_2) begin + intpriority_reg_2 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_3 <= 4'h0; + end else if (intpriority_reg_we_3) begin + intpriority_reg_3 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_4 <= 4'h0; + end else if (intpriority_reg_we_4) begin + intpriority_reg_4 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_5 <= 4'h0; + end else if (intpriority_reg_we_5) begin + intpriority_reg_5 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_6 <= 4'h0; + end else if (intpriority_reg_we_6) begin + intpriority_reg_6 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_7 <= 4'h0; + end else if (intpriority_reg_we_7) begin + intpriority_reg_7 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_8 <= 4'h0; + end else if (intpriority_reg_we_8) begin + intpriority_reg_8 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_9 <= 4'h0; + end else if (intpriority_reg_we_9) begin + intpriority_reg_9 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_10 <= 4'h0; + end else if (intpriority_reg_we_10) begin + intpriority_reg_10 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_11 <= 4'h0; + end else if (intpriority_reg_we_11) begin + intpriority_reg_11 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_12 <= 4'h0; + end else if (intpriority_reg_we_12) begin + intpriority_reg_12 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_13 <= 4'h0; + end else if (intpriority_reg_we_13) begin + intpriority_reg_13 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_14 <= 4'h0; + end else if (intpriority_reg_we_14) begin + intpriority_reg_14 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_15 <= 4'h0; + end else if (intpriority_reg_we_15) begin + intpriority_reg_15 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_16 <= 4'h0; + end else if (intpriority_reg_we_16) begin + intpriority_reg_16 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_17 <= 4'h0; + end else if (intpriority_reg_we_17) begin + intpriority_reg_17 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_18 <= 4'h0; + end else if (intpriority_reg_we_18) begin + intpriority_reg_18 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_19 <= 4'h0; + end else if (intpriority_reg_we_19) begin + intpriority_reg_19 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_20 <= 4'h0; + end else if (intpriority_reg_we_20) begin + intpriority_reg_20 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_21 <= 4'h0; + end else if (intpriority_reg_we_21) begin + intpriority_reg_21 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_22 <= 4'h0; + end else if (intpriority_reg_we_22) begin + intpriority_reg_22 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_23 <= 4'h0; + end else if (intpriority_reg_we_23) begin + intpriority_reg_23 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_24 <= 4'h0; + end else if (intpriority_reg_we_24) begin + intpriority_reg_24 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_25 <= 4'h0; + end else if (intpriority_reg_we_25) begin + intpriority_reg_25 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_26 <= 4'h0; + end else if (intpriority_reg_we_26) begin + intpriority_reg_26 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_27 <= 4'h0; + end else if (intpriority_reg_we_27) begin + intpriority_reg_27 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_28 <= 4'h0; + end else if (intpriority_reg_we_28) begin + intpriority_reg_28 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_29 <= 4'h0; + end else if (intpriority_reg_we_29) begin + intpriority_reg_29 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_30 <= 4'h0; + end else if (intpriority_reg_we_30) begin + intpriority_reg_30 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_pri_c1_clk or posedge reset) begin + if (reset) begin + intpriority_reg_31 <= 4'h0; + end else if (intpriority_reg_we_31) begin + intpriority_reg_31 <= picm_wr_data_ff[3:0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_1 <= 1'h0; + end else if (intenable_reg_we_1) begin + intenable_reg_1 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_2 <= 1'h0; + end else if (intenable_reg_we_2) begin + intenable_reg_2 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_3 <= 1'h0; + end else if (intenable_reg_we_3) begin + intenable_reg_3 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_4 <= 1'h0; + end else if (intenable_reg_we_4) begin + intenable_reg_4 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_5 <= 1'h0; + end else if (intenable_reg_we_5) begin + intenable_reg_5 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_6 <= 1'h0; + end else if (intenable_reg_we_6) begin + intenable_reg_6 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_7 <= 1'h0; + end else if (intenable_reg_we_7) begin + intenable_reg_7 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_8 <= 1'h0; + end else if (intenable_reg_we_8) begin + intenable_reg_8 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_9 <= 1'h0; + end else if (intenable_reg_we_9) begin + intenable_reg_9 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_10 <= 1'h0; + end else if (intenable_reg_we_10) begin + intenable_reg_10 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_11 <= 1'h0; + end else if (intenable_reg_we_11) begin + intenable_reg_11 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_12 <= 1'h0; + end else if (intenable_reg_we_12) begin + intenable_reg_12 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_13 <= 1'h0; + end else if (intenable_reg_we_13) begin + intenable_reg_13 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_14 <= 1'h0; + end else if (intenable_reg_we_14) begin + intenable_reg_14 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_15 <= 1'h0; + end else if (intenable_reg_we_15) begin + intenable_reg_15 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_16 <= 1'h0; + end else if (intenable_reg_we_16) begin + intenable_reg_16 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_17 <= 1'h0; + end else if (intenable_reg_we_17) begin + intenable_reg_17 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_18 <= 1'h0; + end else if (intenable_reg_we_18) begin + intenable_reg_18 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_19 <= 1'h0; + end else if (intenable_reg_we_19) begin + intenable_reg_19 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_20 <= 1'h0; + end else if (intenable_reg_we_20) begin + intenable_reg_20 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_21 <= 1'h0; + end else if (intenable_reg_we_21) begin + intenable_reg_21 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_22 <= 1'h0; + end else if (intenable_reg_we_22) begin + intenable_reg_22 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_23 <= 1'h0; + end else if (intenable_reg_we_23) begin + intenable_reg_23 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_24 <= 1'h0; + end else if (intenable_reg_we_24) begin + intenable_reg_24 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_25 <= 1'h0; + end else if (intenable_reg_we_25) begin + intenable_reg_25 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_26 <= 1'h0; + end else if (intenable_reg_we_26) begin + intenable_reg_26 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_27 <= 1'h0; + end else if (intenable_reg_we_27) begin + intenable_reg_27 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_28 <= 1'h0; + end else if (intenable_reg_we_28) begin + intenable_reg_28 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_29 <= 1'h0; + end else if (intenable_reg_we_29) begin + intenable_reg_29 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_30 <= 1'h0; + end else if (intenable_reg_we_30) begin + intenable_reg_30 <= picm_wr_data_ff[0]; + end + end + always @(posedge pic_int_c1_clk or posedge reset) begin + if (reset) begin + intenable_reg_31 <= 1'h0; + end else if (intenable_reg_we_31) begin + intenable_reg_31 <= picm_wr_data_ff[0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_1 <= 2'h0; + end else if (gw_config_reg_we_1) begin + gw_config_reg_1 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_2 <= 2'h0; + end else if (gw_config_reg_we_2) begin + gw_config_reg_2 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_3 <= 2'h0; + end else if (gw_config_reg_we_3) begin + gw_config_reg_3 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_4 <= 2'h0; + end else if (gw_config_reg_we_4) begin + gw_config_reg_4 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_5 <= 2'h0; + end else if (gw_config_reg_we_5) begin + gw_config_reg_5 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_6 <= 2'h0; + end else if (gw_config_reg_we_6) begin + gw_config_reg_6 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_7 <= 2'h0; + end else if (gw_config_reg_we_7) begin + gw_config_reg_7 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_8 <= 2'h0; + end else if (gw_config_reg_we_8) begin + gw_config_reg_8 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_9 <= 2'h0; + end else if (gw_config_reg_we_9) begin + gw_config_reg_9 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_10 <= 2'h0; + end else if (gw_config_reg_we_10) begin + gw_config_reg_10 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_11 <= 2'h0; + end else if (gw_config_reg_we_11) begin + gw_config_reg_11 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_12 <= 2'h0; + end else if (gw_config_reg_we_12) begin + gw_config_reg_12 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_13 <= 2'h0; + end else if (gw_config_reg_we_13) begin + gw_config_reg_13 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_14 <= 2'h0; + end else if (gw_config_reg_we_14) begin + gw_config_reg_14 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_15 <= 2'h0; + end else if (gw_config_reg_we_15) begin + gw_config_reg_15 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_16 <= 2'h0; + end else if (gw_config_reg_we_16) begin + gw_config_reg_16 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_17 <= 2'h0; + end else if (gw_config_reg_we_17) begin + gw_config_reg_17 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_18 <= 2'h0; + end else if (gw_config_reg_we_18) begin + gw_config_reg_18 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_19 <= 2'h0; + end else if (gw_config_reg_we_19) begin + gw_config_reg_19 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_20 <= 2'h0; + end else if (gw_config_reg_we_20) begin + gw_config_reg_20 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_21 <= 2'h0; + end else if (gw_config_reg_we_21) begin + gw_config_reg_21 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_22 <= 2'h0; + end else if (gw_config_reg_we_22) begin + gw_config_reg_22 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_23 <= 2'h0; + end else if (gw_config_reg_we_23) begin + gw_config_reg_23 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_24 <= 2'h0; + end else if (gw_config_reg_we_24) begin + gw_config_reg_24 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_25 <= 2'h0; + end else if (gw_config_reg_we_25) begin + gw_config_reg_25 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_26 <= 2'h0; + end else if (gw_config_reg_we_26) begin + gw_config_reg_26 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_27 <= 2'h0; + end else if (gw_config_reg_we_27) begin + gw_config_reg_27 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_28 <= 2'h0; + end else if (gw_config_reg_we_28) begin + gw_config_reg_28 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_29 <= 2'h0; + end else if (gw_config_reg_we_29) begin + gw_config_reg_29 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_30 <= 2'h0; + end else if (gw_config_reg_we_30) begin + gw_config_reg_30 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge gw_config_c1_clk or posedge reset) begin + if (reset) begin + gw_config_reg_31 <= 2'h0; + end else if (gw_config_reg_we_31) begin + gw_config_reg_31 <= picm_wr_data_ff[1:0]; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending <= 1'h0; + end else begin + gw_int_pending <= _T_970 | _T_972; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_1 <= 1'h0; + end else begin + gw_int_pending_1 <= _T_982 | _T_984; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_2 <= 1'h0; + end else begin + gw_int_pending_2 <= _T_994 | _T_996; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_3 <= 1'h0; + end else begin + gw_int_pending_3 <= _T_1006 | _T_1008; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_4 <= 1'h0; + end else begin + gw_int_pending_4 <= _T_1018 | _T_1020; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_5 <= 1'h0; + end else begin + gw_int_pending_5 <= _T_1030 | _T_1032; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_6 <= 1'h0; + end else begin + gw_int_pending_6 <= _T_1042 | _T_1044; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_7 <= 1'h0; + end else begin + gw_int_pending_7 <= _T_1054 | _T_1056; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_8 <= 1'h0; + end else begin + gw_int_pending_8 <= _T_1066 | _T_1068; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_9 <= 1'h0; + end else begin + gw_int_pending_9 <= _T_1078 | _T_1080; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_10 <= 1'h0; + end else begin + gw_int_pending_10 <= _T_1090 | _T_1092; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_11 <= 1'h0; + end else begin + gw_int_pending_11 <= _T_1102 | _T_1104; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_12 <= 1'h0; + end else begin + gw_int_pending_12 <= _T_1114 | _T_1116; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_13 <= 1'h0; + end else begin + gw_int_pending_13 <= _T_1126 | _T_1128; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_14 <= 1'h0; + end else begin + gw_int_pending_14 <= _T_1138 | _T_1140; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_15 <= 1'h0; + end else begin + gw_int_pending_15 <= _T_1150 | _T_1152; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_16 <= 1'h0; + end else begin + gw_int_pending_16 <= _T_1162 | _T_1164; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_17 <= 1'h0; + end else begin + gw_int_pending_17 <= _T_1174 | _T_1176; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_18 <= 1'h0; + end else begin + gw_int_pending_18 <= _T_1186 | _T_1188; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_19 <= 1'h0; + end else begin + gw_int_pending_19 <= _T_1198 | _T_1200; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_20 <= 1'h0; + end else begin + gw_int_pending_20 <= _T_1210 | _T_1212; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_21 <= 1'h0; + end else begin + gw_int_pending_21 <= _T_1222 | _T_1224; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_22 <= 1'h0; + end else begin + gw_int_pending_22 <= _T_1234 | _T_1236; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_23 <= 1'h0; + end else begin + gw_int_pending_23 <= _T_1246 | _T_1248; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_24 <= 1'h0; + end else begin + gw_int_pending_24 <= _T_1258 | _T_1260; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_25 <= 1'h0; + end else begin + gw_int_pending_25 <= _T_1270 | _T_1272; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_26 <= 1'h0; + end else begin + gw_int_pending_26 <= _T_1282 | _T_1284; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_27 <= 1'h0; + end else begin + gw_int_pending_27 <= _T_1294 | _T_1296; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_28 <= 1'h0; + end else begin + gw_int_pending_28 <= _T_1306 | _T_1308; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_29 <= 1'h0; + end else begin + gw_int_pending_29 <= _T_1318 | _T_1320; + end + end + always @(posedge clock or posedge reset) begin + if (reset) begin + gw_int_pending_30 <= 1'h0; + end else begin + gw_int_pending_30 <= _T_1330 | _T_1332; + end + end always @(posedge io_free_clk or posedge reset) begin if (reset) begin config_reg <= 1'h0; end else if (config_reg_we) begin - config_reg <= config_reg_in; + config_reg <= picm_wr_data_ff[0]; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_36 <= 4'h0; + _T_1714 <= 8'h0; + end else begin + _T_1714 <= _T_1703; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_1715 <= 4'h0; end else if (config_reg) begin - _T_36 <= 4'hf; + _T_1715 <= _T_1713; end else begin - _T_36 <= 4'h0; + _T_1715 <= _T_1705; end end always @(posedge io_free_clk or posedge reset) begin if (reset) begin - _T_45 <= 1'h0; + _T_1722 <= 1'h0; end else begin - _T_45 <= pl_in_q == maxint; + _T_1722 <= _T_1720 & _T_1721; + end + end + always @(posedge io_free_clk or posedge reset) begin + if (reset) begin + _T_1724 <= 1'h0; + end else begin + _T_1724 <= pl_in_q == maxint; end end endmodule diff --git a/firrtl_black_box_resource_files.f b/firrtl_black_box_resource_files.f index 1fa1aa16..4ec29fe7 100644 --- a/firrtl_black_box_resource_files.f +++ b/firrtl_black_box_resource_files.f @@ -1 +1 @@ -/home/laraibkhan/Desktop/SweRV-Chislified/TEC_RV_ICG.v \ No newline at end of file +/home/laraibkhan/Desktop/SweRV-Chislified/gated_latch.v \ No newline at end of file diff --git a/src/main/resources/vsrc/TEC_RV_ICG.v b/gated_latch.v similarity index 91% rename from src/main/resources/vsrc/TEC_RV_ICG.v rename to gated_latch.v index aebabbef..51b96c9d 100644 --- a/src/main/resources/vsrc/TEC_RV_ICG.v +++ b/gated_latch.v @@ -1,5 +1,4 @@ - -module TEC_RV_ICG( +module gated_latch ( input logic SE, EN, CK, output Q diff --git a/project/target/config-classes/$d88dffe9bb5470e5935e$.class b/project/target/config-classes/$11be0cb76372ba3ee9f6$.class similarity index 94% rename from project/target/config-classes/$d88dffe9bb5470e5935e$.class rename to project/target/config-classes/$11be0cb76372ba3ee9f6$.class index 97a2b6726e4a05ee00ec8ce1529346517c5b2868..e7a102b5048107f975bf0aadd1575e2e68267559 100644 GIT binary patch delta 124 zcmeyZ`dd}$)W2Q(7#J8#7?~Lv#8eColTr0jZ;%C)66z1EoTzJCb9W0 tQy{0IQL=HWk%gs+Ws+fO55<9X(=0RZ$eBIf`A delta 124 zcmeyZ`dd}$)W2Q(7#J8#7?~Lv#8gr&EK<_aQZ18`Oij!UQcW$5O;a~2EoTzJCb9W0 tQy{0IsY$AdrHPTTfu*6Dxrwnwih+r-3OmCoMg|EV6>O55<9X(=0RZA2A(sFE diff --git a/project/target/config-classes/$1a77b77dbd21409628b4.cache b/project/target/config-classes/$11be0cb76372ba3ee9f6.cache similarity index 100% rename from project/target/config-classes/$1a77b77dbd21409628b4.cache rename to project/target/config-classes/$11be0cb76372ba3ee9f6.cache diff --git a/project/target/config-classes/$1a77b77dbd21409628b4.class b/project/target/config-classes/$11be0cb76372ba3ee9f6.class similarity index 54% rename from project/target/config-classes/$1a77b77dbd21409628b4.class rename to project/target/config-classes/$11be0cb76372ba3ee9f6.class index 3ed91e07a18d648a3f3036bd46bbab32fe18fa5d..39c98bc0f3942f24c174b6e4143ba34e1cbe0c65 100644 GIT binary patch delta 157 zcmZo;ZDUnB^>5cc1_lNb2609PQ58eOq*R0CBy%%kbEBk0EplqzxOHA+es)e-lQl9|lQIM)h`Q7Y^V a+>8wDzWy$uKCUW^3=%$AZJhjsaS;I7S1D}( delta 157 zcmZo;ZDUnB^>5cc1_lNb2609PQ5C~PbMqu~^OU3%BSRAdOEV*jB$J6si$#<2V};7o z`HYi2y|`T1ePzv46NTI--jWq#wJC9rl(F#SQc+jul{PGn6k_p^l%CAXIM)h`Q7Y^V a+>8wDzWy$uKCUW^3=%$AZJhjsaS;GtXeT%T diff --git a/project/target/config-classes/$78dad6b7a8f577faa340$.class b/project/target/config-classes/$1754e38fcce51e8851c0$.class similarity index 94% rename from project/target/config-classes/$78dad6b7a8f577faa340$.class rename to project/target/config-classes/$1754e38fcce51e8851c0$.class index 13fdb9785aa21d12057621a9fd3afd37fd901204..eafbb9222fa06b1c9f2b32267eecc75882ea162a 100644 GIT binary patch delta 67 zcmdlixmi;2)W2Q(7#J8#7&b66h^ZKwo0_B=Tcjl?r5cc1_lNb2609PQ58dTQPQIM)h`Sq3WX b4BU(i?7sdkp+2rEj0_S!*sPrVm~k-xK#M1o delta 157 zcmZo;ZDUnD^>5cc1_lNb2609PQ59oD^Q1I0V?z@&GovI+b5lzT(}{|U#iWe#IZe{j zeI-qEBZX9S{bkIG6SY_--jWeZcePUSm69<@4m3(}=QXm*5A|Zv;G4|DIM)h`Sq3WX b4BU(i?7sdkp+2rEj0_S!*sPrVm~k-x5m+WG diff --git a/project/target/config-classes/$54e4942309167438d043$.class b/project/target/config-classes/$2c3e28949b1f44e2665a$.class similarity index 94% rename from project/target/config-classes/$54e4942309167438d043$.class rename to project/target/config-classes/$2c3e28949b1f44e2665a$.class index f6d20b071e85e2b11275f83d8fa5c9bfb6867d3f..f8af9b25832bdff898823a7a01c7d1cef1f1849b 100644 GIT binary patch delta 67 zcmcaBbyrI1)W2Q(7#J8#7^X8ah^ZJQ8>bpsSejTS8K#+-q#Bu-nI=wDDi*;ezH#Li F9ss^K6d3>j delta 67 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\ No newline at end of file diff --git a/target/scala-2.12/classes/vsrc/TEC_RV_ICG.v b/src/main/resources/vsrc/gated_latch.v similarity index 91% rename from target/scala-2.12/classes/vsrc/TEC_RV_ICG.v rename to src/main/resources/vsrc/gated_latch.v index aebabbef..51b96c9d 100644 --- a/target/scala-2.12/classes/vsrc/TEC_RV_ICG.v +++ b/src/main/resources/vsrc/gated_latch.v @@ -1,5 +1,4 @@ - -module TEC_RV_ICG( +module gated_latch ( input logic SE, EN, CK, output Q diff --git a/src/main/scala/dbg/el2_dbg.scala b/src/main/scala/dbg/el2_dbg.scala new file mode 100644 index 00000000..f6d0e100 --- /dev/null +++ b/src/main/scala/dbg/el2_dbg.scala @@ -0,0 +1,480 @@ +package dbg + +import chisel3._ +import chisel3.util._ +import lib._ + +object state_t { + val idle = 0.U(3.W) + val halting = 1.U(3.W) + val halted = 2.U(3.W) + val cmd_start = 3.U(3.W) + val cmd_wait = 4.U(3.W) + val cmd_done = 5.U(3.W) + val resuming = 6.U(3.W) +} + +object sb_state_t { + val sbidle = 0.U(4.W) + val wait_rd = 1.U(4.W) + val wait_wr = 2.U(4.W) + val cmd_rd = 3.U(4.W) + val cmd_wr = 4.U(4.W) + val cmd_wr_addr = 5.U(4.W) + val cmd_wr_data = 6.U(4.W) + val rsp_rd = 7.U(4.W) + val rsp_wr = 8.U(4.W) + val done = 9.U(4.W) +} + +class el2_dbg extends Module with el2_lib with RequireAsyncReset { + val io = IO(new Bundle { + val dbg_cmd_addr = Output(UInt(32.W)) + val dbg_cmd_wrdata = Output(UInt(32.W)) + val dbg_cmd_valid = Output(Bool()) + val dbg_cmd_write = Output(Bool()) + val dbg_cmd_type = Output(UInt(2.W)) + val dbg_cmd_size = Output(UInt(2.W)) + val dbg_core_rst_l = Output(Bool()) + val core_dbg_rddata = Input(UInt(32.W)) + val core_dbg_cmd_done = Input(Bool()) + val core_dbg_cmd_fail = Input(Bool()) + val dbg_dma_bubble = Output(Bool()) + val dma_dbg_ready = Input(Bool()) + val dbg_halt_req = Output(Bool()) + val dbg_resume_req = Output(Bool()) + val dec_tlu_debug_mode = Input(Bool()) + val dec_tlu_dbg_halted = Input(Bool()) + val dec_tlu_mpc_halted_only = Input(Bool()) + val dec_tlu_resume_ack = Input(Bool()) + val dmi_reg_en = Input(Bool()) + val dmi_reg_addr = Input(UInt(7.W)) + val dmi_reg_wr_en = Input(Bool()) + val dmi_reg_wdata = Input(UInt(32.W)) + val dmi_reg_rdata = Output(UInt(32.W)) + val sb_axi_awvalid = Output(Bool()) + val sb_axi_awready = Input(Bool()) + val sb_axi_awid = Output(UInt(SB_BUS_TAG.W)) + val sb_axi_awaddr = Output(UInt(32.W)) + val sb_axi_awregion = Output(UInt(4.W)) + val sb_axi_awlen = Output(UInt(8.W)) + val sb_axi_awsize = Output(UInt(3.W)) + val sb_axi_awburst = Output(UInt(2.W)) + val sb_axi_awlock = Output(Bool()) + val sb_axi_awcache = Output(UInt(4.W)) + val sb_axi_awprot = Output(UInt(3.W)) + val sb_axi_awqos = Output(UInt(4.W)) + val sb_axi_wvalid = Output(Bool()) + val sb_axi_wready = Input(Bool()) + val sb_axi_wdata = Output(UInt(64.W)) + val sb_axi_wstrb = Output(UInt(8.W)) + val sb_axi_wlast = Output(Bool()) + val sb_axi_bvalid = Input(Bool()) + val sb_axi_bready = Output(Bool()) + val sb_axi_bresp = Input(UInt(2.W)) + val sb_axi_arvalid = Output(Bool()) + val sb_axi_arready = Input(Bool()) + val sb_axi_arid = Output(UInt(SB_BUS_TAG.W)) + val sb_axi_araddr = Output(UInt(32.W)) + val sb_axi_arregion = Output(UInt(4.W)) + val sb_axi_arlen = Output(UInt(8.W)) + val sb_axi_arsize = Output(UInt(3.W)) + val sb_axi_arburst = Output(UInt(2.W)) + val sb_axi_arlock = Output(Bool()) + val sb_axi_arcache = Output(UInt(4.W)) + val sb_axi_arprot = Output(UInt(3.W)) + val sb_axi_arqos = Output(UInt(4.W)) + val sb_axi_rvalid = Input(Bool()) + val sb_axi_rready = Output(Bool()) + val sb_axi_rdata = Input(UInt(64.W)) + val sb_axi_rresp = Input(UInt(2.W)) + val dbg_bus_clk_en = Input(Bool()) + val dbg_rst_l = Input(Bool()) + val clk_override = Input(Bool()) + val scan_mode = Input(Bool()) + }) + + val dbg_state = WireInit(state_t.idle) + val dbg_state_en = WireInit(false.B) + val sb_state = WireInit(sb_state_t.sbidle) + val sb_state_en = WireInit(Bool(), false.B) + val dmcontrol_reg = WireInit(0.U(32.W)) + val sbaddress0_reg = WireInit(0.U(32.W)) + val sbcs_sbbusy_wren = WireInit(false.B) + val sbcs_sberror_wren = WireInit(false.B) + val sb_bus_rdata = WireInit(0.U(64.W)) + val sbaddress0_reg_wren1 = WireInit(false.B) + val dmstatus_reg = WireInit(0.U(32.W)) + val dmstatus_havereset = WireInit(false.B) + val dmstatus_resumeack = WireInit(false.B) + val dmstatus_unavail = WireInit(false.B) + val dmstatus_running = WireInit(false.B) + val dmstatus_halted = WireInit(false.B) + val abstractcs_busy_wren = WireInit(false.B) + val abstractcs_busy_din = WireInit(false.B) + val sb_bus_cmd_read = WireInit(false.B) + val sb_bus_cmd_write_addr = WireInit(false.B) + val sb_bus_cmd_write_data = WireInit(false.B) + val sb_bus_rsp_read = WireInit(false.B) + val sb_bus_rsp_error = WireInit(false.B) + val sb_bus_rsp_write = WireInit(false.B) + val sbcs_sbbusy_din = WireInit(false.B) + val sbcs_sberror_din = WireInit(0.U(3.W)) + val data1_reg = WireInit(0.U(32.W)) + val sbcs_reg = WireInit(0.U(32.W)) + + val dbg_free_clken = io.dmi_reg_en | (dbg_state =/= state_t.idle) | dbg_state_en | io.dec_tlu_dbg_halted | io.clk_override + val sb_free_clken = io.dmi_reg_en | sb_state_en | (sb_state =/= sb_state_t.sbidle) | io.clk_override; + val dbg_free_clk = rvclkhdr(clock, dbg_free_clken, io.scan_mode) // dbg_free_cgc + val sb_free_clk = rvclkhdr(clock, sb_free_clken, io.scan_mode) // sb_free_cgc + val dbg_dm_rst_l = io.dbg_rst_l.asBool() & (dmcontrol_reg(0) | io.scan_mode) + io.dbg_core_rst_l := (!dmcontrol_reg(1)).asBool() + val sbcs_wren = (io.dmi_reg_addr === "h38".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (sb_state === sb_state_t.sbidle) + val sbcs_sbbusyerror_wren = (sbcs_wren & io.dmi_reg_wdata(22)) | ((sb_state =/= sb_state_t.sbidle) & io.dmi_reg_en & + ((io.dmi_reg_addr === "h39".U) | (io.dmi_reg_addr === "h3c".U) | (io.dmi_reg_addr === "h3d".U))) + + val sbcs_sbbusyerror_din = (~(sbcs_wren & io.dmi_reg_wdata(22))).asUInt() + val temp_sbcs_22 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(sbcs_sbbusyerror_din, 0.U, sbcs_sbbusyerror_wren) + } // sbcs_sbbusyerror_reg + + val temp_sbcs_21 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(sbcs_sbbusy_din, 0.U, sbcs_sbbusy_wren) + } // sbcs_sbbusy_reg + + val temp_sbcs_20 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(io.dmi_reg_wdata(20), 0.U, sbcs_wren) + } // sbcs_sbreadonaddr_reg + + val temp_sbcs_19_15 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(io.dmi_reg_wdata(19, 15), 0.U, sbcs_wren) + } // sbcs_misc_reg + + val temp_sbcs_14_12 = withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(sbcs_sberror_din(2, 0), 0.U, sbcs_sberror_wren) + } // sbcs_error_reg + sbcs_reg := Cat(1.U(3.W), 0.U(6.W), temp_sbcs_22, temp_sbcs_21, temp_sbcs_20, temp_sbcs_19_15, temp_sbcs_14_12, "h20".U(7.W), "b01111".U(5.W)) + + val sbcs_unaligned = (sbcs_reg(19, 17) === "b001".U) & sbaddress0_reg(0) | + (sbcs_reg(19, 17) === "b010".U) & sbaddress0_reg(1, 0).orR | + (sbcs_reg(19, 17) === "b011".U) & sbaddress0_reg(2, 0).orR + + val sbcs_illegal_size = sbcs_reg(19) + val sbaddress0_incr = Fill(4, (sbcs_reg(19, 17) === "h0".U)) & "b0001".U | Fill(4, (sbcs_reg(19, 17) === "h1".U)) & "b0010".U | + Fill(4, (sbcs_reg(19, 17) === "h2".U)) & "b0100".U | Fill(4, (sbcs_reg(19, 17) === "h3".U)) & "b1000".U + + val sbdata0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) + val sbdata0_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren + val sbdata0_reg_wren = sbdata0_reg_wren0 | sbdata0_reg_wren1 + val sbdata1_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3d".U) + val sbdata1_reg_wren1 = (sb_state === sb_state_t.rsp_rd) & sb_state_en & !sbcs_sberror_wren + val sbdata1_reg_wren = sbdata1_reg_wren0 | sbdata1_reg_wren1 + val sbdata0_din = Fill(32, sbdata0_reg_wren0) & io.dmi_reg_wdata | + Fill(32, sbdata0_reg_wren1) & sb_bus_rdata(31, 0) + + val sbdata1_din = Fill(32, sbdata1_reg_wren0) & io.dmi_reg_wdata | + Fill(32, sbdata1_reg_wren1) & sb_bus_rdata(63, 32) + + val sbdata0_reg = withReset(!dbg_dm_rst_l) { + rvdffe(sbdata0_din, sbdata0_reg_wren, clock, io.scan_mode) + } // dbg_sbdata0_reg + + val sbdata1_reg = withReset(!dbg_dm_rst_l) { + rvdffe(sbdata1_din, sbdata1_reg_wren, clock, io.scan_mode) + } // dbg_sbdata1_reg + + val sbaddress0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U) + val sbaddress0_reg_wren = sbaddress0_reg_wren0 | sbaddress0_reg_wren1 + val sbaddress0_reg_din = Fill(32, sbaddress0_reg_wren0) & io.dmi_reg_wdata | + Fill(32, sbaddress0_reg_wren1) & (sbaddress0_reg + Cat(0.U(28.W), sbaddress0_incr)) + sbaddress0_reg := withReset(!dbg_dm_rst_l) { + rvdffe(sbaddress0_reg_din, sbaddress0_reg_wren, clock, io.scan_mode) + } // dbg_sbaddress0_reg + + val sbreadonaddr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h39".U) & sbcs_reg(20) + val sbreadondata_access = io.dmi_reg_en & !io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) & sbcs_reg(15) + val sbdata0wr_access = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h3c".U) + val dmcontrol_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_en & io.dmi_reg_wr_en + val dm_temp = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegEnable( + Cat(io.dmi_reg_wdata(31, 30), io.dmi_reg_wdata(28), io.dmi_reg_wdata(1)), + 0.U, dmcontrol_wren) + } // dmcontrolff + + val dm_temp_0 = withClockAndReset(dbg_free_clk, io.dbg_rst_l) { + RegEnable(io.dmi_reg_wdata(0), 0.U, dmcontrol_wren) + } // dmcontrol_dmactive_ff + + val temp = Cat(dm_temp(3, 2), 0.U, dm_temp(1), 0.U(26.W), dm_temp(0), dm_temp_0) + dmcontrol_reg := temp + + val dmcontrol_wren_Q = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegNext(dmcontrol_wren, 0.U) + } // dmcontrol_wrenff + + dmstatus_reg := Cat(0.U(12.W), Fill(2, dmstatus_havereset), Fill(2, dmstatus_resumeack), 0.U(2.W), Fill(2, dmstatus_unavail), Fill(2, dmstatus_running), Fill(2, dmstatus_halted), 1.U(1.W), 0.U(3.W), 2.U(4.W)) + + val dmstatus_resumeack_wren = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack | dmstatus_resumeack & !dmcontrol_reg(30) + val dmstatus_resumeack_din = (dbg_state === state_t.resuming) & io.dec_tlu_resume_ack + val dmstatus_havereset_wren = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_wdata(1) & io.dmi_reg_en & io.dmi_reg_wr_en + val dmstatus_havereset_rst = (io.dmi_reg_addr === "h10".U) & io.dmi_reg_wdata(28) & io.dmi_reg_en & io.dmi_reg_wr_en; + val temp_rst = reset.asBool() + dmstatus_unavail := (dmcontrol_reg(1) | !(temp_rst)).asBool() + dmstatus_running := ~(dmstatus_unavail | dmstatus_halted) + dmstatus_resumeack := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegEnable(dmstatus_resumeack_din, 0.U, dmstatus_resumeack_wren) + } // dmstatus_resumeack_reg + + dmstatus_halted := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegNext(io.dec_tlu_dbg_halted & !io.dec_tlu_mpc_halted_only, 0.U) + } // dmstatus_halted_reg + + dmstatus_havereset := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegEnable(~dmstatus_havereset_rst, 0.U, dmstatus_havereset_wren) + } // dmstatus_havereset_reg + + val haltsum0_reg = Cat(0.U(31.W), dmstatus_halted) + val abstractcs_reg = WireInit(2.U(32.W)) + + val abstractcs_error_sel0 = abstractcs_reg(12) & io.dmi_reg_en & (io.dmi_reg_wr_en & ((io.dmi_reg_addr === "h16".U) | (io.dmi_reg_addr === "h17".U)) | (io.dmi_reg_addr === "h4".U)) + val abstractcs_error_sel1 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !((io.dmi_reg_wdata(31, 24) === 0.U) | (io.dmi_reg_wdata(31, 24) === "h2".U)) + val abstractcs_error_sel2 = io.core_dbg_cmd_done & io.core_dbg_cmd_fail + val abstractcs_error_sel3 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h17".U) & !dmstatus_reg(9); + val abstractcs_error_sel4 = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & + ((io.dmi_reg_wdata(22, 20) =/= "b010".U) | ((io.dmi_reg_wdata(31, 24) === "h2".U) && data1_reg(1, 0).orR)) + + val abstractcs_error_sel5 = (io.dmi_reg_addr === "h16".U) & io.dmi_reg_en & io.dmi_reg_wr_en + val abstractcs_error_selor = abstractcs_error_sel0 | abstractcs_error_sel1 | abstractcs_error_sel2 | abstractcs_error_sel3 | abstractcs_error_sel4 | abstractcs_error_sel5 + val abstractcs_error_din = (Fill(3, abstractcs_error_sel0) & "b001".U) | + (Fill(3, abstractcs_error_sel1) & "b010".U) | + (Fill(3, abstractcs_error_sel2) & "b011".U) | + (Fill(3, abstractcs_error_sel3) & "b100".U) | + (Fill(3, abstractcs_error_sel4) & "b111".U) | + (Fill(3, abstractcs_error_sel5) & (~io.dmi_reg_wdata(10, 8)).asUInt() & abstractcs_reg(10, 8)) | + (Fill(3, (~abstractcs_error_selor).asUInt()) & abstractcs_reg(10, 8)) + + val abs_temp_12 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegEnable(abstractcs_busy_din, 0.U, abstractcs_busy_wren) + } // dmabstractcs_busy_reg + + val abs_temp_10_8 = withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegNext(abstractcs_error_din(2, 0), 0.U) + } // dmabstractcs_error_reg + + abstractcs_reg := Cat(0.U(19.W), abs_temp_12, 0.U(1.W), abs_temp_10_8, 2.U(8.W)) + + val command_wren = (io.dmi_reg_addr === "h17".U) & io.dmi_reg_en & io.dmi_reg_wr_en & (dbg_state === state_t.halted) + val command_din = Cat(io.dmi_reg_wdata(31, 24), 0.U(1.W), io.dmi_reg_wdata(22, 20), 0.U(3.W), io.dmi_reg_wdata(16, 0)) + val command_reg = withReset(!dbg_dm_rst_l) { + RegEnable(command_din, 0.U, command_wren) + } // dmcommand_reg + + val data0_reg_wren0 = io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h4".U) & (dbg_state === state_t.halted) + val data0_reg_wren1 = io.core_dbg_cmd_done & (dbg_state === state_t.cmd_wait) & !command_reg(16) + + val data0_reg_wren = data0_reg_wren0 | data0_reg_wren1 + val data0_din = Fill(32, data0_reg_wren0) & io.dmi_reg_wdata | Fill(32, data0_reg_wren1) & io.core_dbg_rddata + val data0_reg = withReset(!dbg_dm_rst_l) { + RegEnable(data0_din, 0.U, data0_reg_wren) + } // dbg_data0_reg + + val data1_reg_wren = (io.dmi_reg_en & io.dmi_reg_wr_en & (io.dmi_reg_addr === "h5".U) & (dbg_state === state_t.halted)) + val data1_din = Fill(32, data1_reg_wren) & io.dmi_reg_wdata + data1_reg := withReset(!dbg_dm_rst_l) { + rvdffe(data1_din, data1_reg_wren, clock, io.scan_mode) + } // dbg_data1_reg + + val dbg_nxtstate = WireInit(state_t.idle) + dbg_nxtstate := state_t.idle + dbg_state_en := false.B + abstractcs_busy_wren := false.B + abstractcs_busy_din := false.B + io.dbg_halt_req := false.B + io.dbg_resume_req := false.B + switch(dbg_state) { + is(state_t.idle) { + dbg_nxtstate := Mux(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only, state_t.halted, state_t.halting) + dbg_state_en := ((dmcontrol_reg(31) & !io.dec_tlu_debug_mode) | dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) & !dmcontrol_reg(1) + io.dbg_halt_req := (dmcontrol_reg(31) & !dmcontrol_reg(1)).asBool() + } + is(state_t.halting) { + dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.halted) + dbg_state_en := dmstatus_reg(9) | dmcontrol_reg(1) + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + } + is(state_t.halted) { + dbg_nxtstate := Mux(dmstatus_reg(9) & !dmcontrol_reg(1), + Mux(dmcontrol_reg(30) & !dmcontrol_reg(3), state_t.resuming, state_t.cmd_start), + Mux(dmcontrol_reg(31), state_t.halting, state_t.idle)) + dbg_state_en := dmstatus_reg(9) & dmcontrol_reg(30) & !dmcontrol_reg(31) & dmcontrol_wren_Q | command_wren | + dmcontrol_reg(1) | !(dmstatus_reg(9) | io.dec_tlu_mpc_halted_only) + abstractcs_busy_wren := dbg_state_en & (dbg_nxtstate === state_t.cmd_start) + abstractcs_busy_din := "b1".U + io.dbg_resume_req := (dbg_state_en & (dbg_nxtstate === state_t.resuming)).asBool() + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + } + is(state_t.cmd_start) { + dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, Mux(abstractcs_reg(10, 8).orR, state_t.cmd_done, state_t.cmd_wait)) + dbg_state_en := io.dbg_cmd_valid | abstractcs_reg(10, 8).orR | dmcontrol_reg(1) + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + } + is(state_t.cmd_wait) { + dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.cmd_done) + dbg_state_en := io.core_dbg_cmd_done | dmcontrol_reg(1) + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + } + is(state_t.cmd_done) { + dbg_nxtstate := Mux(dmcontrol_reg(1), state_t.idle, state_t.halted) + dbg_state_en := true.B + abstractcs_busy_wren := dbg_state_en + abstractcs_busy_din := "b0".U + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + } + is(state_t.resuming) { + dbg_nxtstate := state_t.idle; + dbg_state_en := dmstatus_reg(17) | dmcontrol_reg(1) + io.dbg_halt_req := (dmcontrol_wren_Q & dmcontrol_reg(31) & (~dmcontrol_reg(1)).asUInt()).asBool() + }} + + val dmi_reg_rdata_din = Fill(32, io.dmi_reg_addr === "h4".U).asUInt & data0_reg | Fill(32, io.dmi_reg_addr === "h5".U) & data1_reg | + Fill(32, io.dmi_reg_addr === "h10".U) & dmcontrol_reg | Fill(32, io.dmi_reg_addr === "h11".U) & dmstatus_reg | + Fill(32, io.dmi_reg_addr === "h16".U) & abstractcs_reg | Fill(32, io.dmi_reg_addr === "h17".U) & command_reg | + Fill(32, io.dmi_reg_addr === "h40".U) & haltsum0_reg | Fill(32, io.dmi_reg_addr === "h38".U) & sbcs_reg | + Fill(32, io.dmi_reg_addr === "h39".U) & sbaddress0_reg | Fill(32, io.dmi_reg_addr === "h3c".U) & sbdata0_reg | + Fill(32, io.dmi_reg_addr === "h3d".U) & sbdata1_reg + + dbg_state := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l & temp_rst) { + RegEnable(dbg_nxtstate, 0.U, dbg_state_en) + } // dbg_state_reg + + + io.dmi_reg_rdata := withClockAndReset(dbg_free_clk, !dbg_dm_rst_l) { + RegEnable(dmi_reg_rdata_din, 0.U, io.dmi_reg_en) + } // dmi_rddata_reg + + io.dbg_cmd_addr := Mux((command_reg(31, 24) === "h2".U), Cat(data1_reg(31, 2), "b00".U), Cat(0.U(20.W), command_reg(11, 0))) + io.dbg_cmd_wrdata := data0_reg(31, 0) + io.dbg_cmd_valid := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) & io.dma_dbg_ready).asBool() + io.dbg_cmd_write := command_reg(16).asBool() + io.dbg_cmd_type := Mux((command_reg(31, 24) === "h2".U), "b10".U, Cat("b0".U, (command_reg(15, 12) === "b0".U))) + io.dbg_cmd_size := command_reg(21, 20) + io.dbg_dma_bubble := ((dbg_state === state_t.cmd_start) & !(abstractcs_reg(10, 8).orR) | (dbg_state === state_t.cmd_wait)).asBool() + + val sb_nxtstate = WireInit(sb_state_t.sbidle) + sb_nxtstate := sb_state_t.sbidle + //sb_state_en := true.B + sbcs_sbbusy_wren := false.B + sbcs_sbbusy_din := false.B + sbcs_sberror_wren := false.B + sbcs_sberror_din := 0.U(3.W) + sbaddress0_reg_wren1 := false.B + switch(sb_state) { + is(sb_state_t.sbidle) { + sb_nxtstate := Mux(sbdata0wr_access, sb_state_t.wait_wr, sb_state_t.wait_rd) + sb_state_en := sbdata0wr_access | sbreadondata_access | sbreadonaddr_access + sbcs_sbbusy_wren := sb_state_en + sbcs_sbbusy_din := true.B + sbcs_sberror_wren := sbcs_wren & io.dmi_reg_wdata(14, 12).orR + sbcs_sberror_din := !io.dmi_reg_wdata(14, 12) & sbcs_reg(14, 12) + } + is(sb_state_t.wait_rd) { + sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_rd) + sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size + sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + } + is(sb_state_t.wait_wr) { + sb_nxtstate := Mux(sbcs_unaligned | sbcs_illegal_size, sb_state_t.done, sb_state_t.cmd_wr) + sb_state_en := io.dbg_bus_clk_en | sbcs_unaligned | sbcs_illegal_size + sbcs_sberror_wren := sbcs_unaligned | sbcs_illegal_size; + sbcs_sberror_din := Mux(sbcs_unaligned, "b011".U, "b100".U) + } + is(sb_state_t.cmd_rd) { + sb_nxtstate := sb_state_t.rsp_rd + sb_state_en := sb_bus_cmd_read & io.dbg_bus_clk_en + } + is(sb_state_t.cmd_wr) { + sb_nxtstate := Mux(sb_bus_cmd_write_addr & sb_bus_cmd_write_data, sb_state_t.rsp_wr, Mux(sb_bus_cmd_write_data, sb_state_t.cmd_wr_addr, sb_state_t.cmd_wr_data)) + sb_state_en := (sb_bus_cmd_write_addr | sb_bus_cmd_write_data) & io.dbg_bus_clk_en + } + is(sb_state_t.cmd_wr_addr) { + sb_nxtstate := sb_state_t.rsp_wr + sb_state_en := sb_bus_cmd_write_addr & io.dbg_bus_clk_en + } + is(sb_state_t.cmd_wr_data) { + sb_nxtstate := sb_state_t.rsp_wr + sb_state_en := sb_bus_cmd_write_data & io.dbg_bus_clk_en + } + is(sb_state_t.rsp_rd) { + sb_nxtstate := sb_state_t.done + sb_state_en := sb_bus_rsp_read & io.dbg_bus_clk_en + sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error + sbcs_sberror_din := "b010".U + } + is(sb_state_t.rsp_wr) { + sb_nxtstate := sb_state_t.done; + sb_state_en := sb_bus_rsp_write & io.dbg_bus_clk_en + sbcs_sberror_wren := sb_state_en & sb_bus_rsp_error + sbcs_sberror_din := "b010".U + } + is(sb_state_t.done) { + sb_nxtstate := sb_state_t.sbidle; + sb_state_en := true.B + sbcs_sbbusy_wren := true.B + sbcs_sbbusy_din := false.B + sbaddress0_reg_wren1 := sbcs_reg(16) + }} + + sb_state := withClockAndReset(sb_free_clk, !dbg_dm_rst_l) { + RegEnable(sb_nxtstate, 0.U, sb_state_en) + } // sb_state_reg + + sb_bus_cmd_read := io.sb_axi_arvalid & io.sb_axi_arready + sb_bus_cmd_write_addr := io.sb_axi_awvalid & io.sb_axi_awready + sb_bus_cmd_write_data := io.sb_axi_wvalid & io.sb_axi_wready + sb_bus_rsp_read := io.sb_axi_rvalid & io.sb_axi_rready + sb_bus_rsp_write := io.sb_axi_bvalid & io.sb_axi_bready + sb_bus_rsp_error := sb_bus_rsp_read & io.sb_axi_rresp(1, 0).orR | sb_bus_rsp_write & io.sb_axi_bresp(1, 0).orR + io.sb_axi_awvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_addr)).asBool() + io.sb_axi_awaddr := sbaddress0_reg + io.sb_axi_awid := 0.U + io.sb_axi_awsize := sbcs_reg(19, 17) + io.sb_axi_awprot := 0.U + io.sb_axi_awcache := "b1111".U + io.sb_axi_awregion := sbaddress0_reg(31, 28) + io.sb_axi_awlen := 0.U + io.sb_axi_awburst := "b01".U + io.sb_axi_awqos := 0.U + io.sb_axi_awlock := false.B + io.sb_axi_wvalid := ((sb_state === sb_state_t.cmd_wr) | (sb_state === sb_state_t.cmd_wr_data)).asBool() + io.sb_axi_wdata := Fill(64, (sbcs_reg(19, 17) === 0.U)) & Fill(8, (sbdata0_reg(7, 0))) | Fill(64, (sbcs_reg(19, 17) === "h1".U)) & Fill(4, sbdata0_reg(15, 0)) | + Fill(64, (sbcs_reg(19, 17) === "h2".U)) & Fill(2, (sbdata0_reg(31, 0))) | Fill(64, (sbcs_reg(19, 17) === "h3".U)) & Cat(sbdata1_reg(31, 0), sbdata0_reg(31, 0)) + + io.sb_axi_wstrb := Fill(8, (sbcs_reg(19, 17) === "h0".U)) & ("h1".U(8.W) << sbaddress0_reg(2, 0)) | + Fill(8, (sbcs_reg(19, 17) === "h1".U)) & ("h3".U(8.W) << Cat(sbaddress0_reg(2, 1), "b0".U)) | + Fill(8, (sbcs_reg(19, 17) === "h2".U)) & ("hf".U(8.W) << Cat(sbaddress0_reg(2), "b00".U)) | + Fill(8, (sbcs_reg(19, 17) === "h3".U)) & "hff".U + + io.sb_axi_wlast := true.B + io.sb_axi_arvalid := (sb_state === sb_state_t.cmd_rd).asBool() + io.sb_axi_araddr := sbaddress0_reg + io.sb_axi_arid := 0.U + io.sb_axi_arsize := sbcs_reg(19, 17) + io.sb_axi_arprot := 0.U + io.sb_axi_arcache := 0.U + io.sb_axi_arregion := sbaddress0_reg(31, 28) + io.sb_axi_arlen := 0.U + io.sb_axi_arburst := "b01".U + io.sb_axi_arqos := 0.U + io.sb_axi_arlock := false.B + io.sb_axi_bready := true.B + io.sb_axi_rready := true.B + sb_bus_rdata := Fill(64, (sbcs_reg(19, 17) === "h0".U)) & ((io.sb_axi_rdata(63, 0) >> 8.U * sbaddress0_reg(2, 0)) & "hff".U(64.W)) | + Fill(64, (sbcs_reg(19, 17) === "h1".U)) & ((io.sb_axi_rdata(63, 0) >> 16.U * sbaddress0_reg(2, 1)) & "hffff".U(64.W)) | + Fill(64, (sbcs_reg(19, 17) === "h2".U)) & ((io.sb_axi_rdata(63, 0) >> 32.U * sbaddress0_reg(2)) & "hffff_ffff".U(64.W)) | + Fill(64, (sbcs_reg(19, 17) === "h3".U)) & io.sb_axi_rdata(63, 0) +} + +object debug extends App { + chisel3.Driver.emitVerilog(new el2_dbg) +} \ No newline at end of file diff --git a/src/main/scala/dec/el2_dec.scala b/src/main/scala/dec/el2_dec.scala new file mode 100644 index 00000000..58be6550 --- /dev/null +++ b/src/main/scala/dec/el2_dec.scala @@ -0,0 +1,721 @@ +package dec +import chisel3._ +import chisel3.util._ +import include._ +import lib._ + +class el2_dec_IO extends Bundle with el2_lib { + //val clk = Input(Clock()) + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + + val lsu_fastint_stall_any = Input(Bool()) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + val dec_extint_stall = Output(Bool()) + + val dec_i0_decode_d = Output(Bool()) + val dec_pause_state_cg = Output(Bool()) // to top for active state clock gating + + // val rst_l = Input(Bool()) // reset, active low + val rst_vec = Input(UInt(32.W)) // [31:1] reset vector, from core pins + + val nmi_int = Input(Bool()) // NMI pin + val nmi_vec = Input(UInt(32.W)) // [31:1] NMI vector, from pins + + val i_cpu_halt_req = Input(Bool()) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(Bool()) // Asynchronous Restart request to CPU + + val o_cpu_halt_status = Output(Bool()) // Halt status of core (pmu/fw) + val o_cpu_halt_ack = Output(Bool()) // Halt request ack + val o_cpu_run_ack = Output(Bool()) // Run request ack + val o_debug_mode_status = Output(Bool()) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + val core_id = Input(UInt(32.W)) // [31:4] CORE ID + + // external MPC halt/run interface + val mpc_debug_halt_req = Input(Bool()) // Async halt request + val mpc_debug_run_req = Input(Bool()) // Async run request + val mpc_reset_run_req = Input(Bool()) // Run/halt after reset + val mpc_debug_halt_ack = Output(Bool()) // Halt ack + val mpc_debug_run_ack = Output(Bool()) // Run ack + val debug_brkpt_status = Output(Bool()) // debug breakpoint + + val exu_pmu_i0_br_misp = Input(Bool()) // slot 0 branch misp + val exu_pmu_i0_br_ataken = Input(Bool()) // slot 0 branch actual taken + val exu_pmu_i0_pc4 = Input(Bool()) // slot 0 4 byte branch + + + val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m + val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r + val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back + val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error + val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data + + val lsu_pmu_bus_trxn = Input(Bool()) // D side bus transaction + val lsu_pmu_bus_misaligned = Input(Bool()) // D side bus misaligned + val lsu_pmu_bus_error = Input(Bool()) // D side bus error + val lsu_pmu_bus_busy = Input(Bool()) // D side bus busy + val lsu_pmu_misaligned_m = Input(Bool()) // D side load or store misaligned + val lsu_pmu_load_external_m = Input(Bool()) // D side bus load + val lsu_pmu_store_external_m = Input(Bool()) // D side bus store + val dma_pmu_dccm_read = Input(Bool()) // DMA DCCM read + val dma_pmu_dccm_write = Input(Bool()) // DMA DCCM write + val dma_pmu_any_read = Input(Bool()) // DMA read + val dma_pmu_any_write = Input(Bool()) // DMA write + + val lsu_fir_addr = Input(UInt(32.W)) //[31:1] Fast int address + val lsu_fir_error = Input(UInt(2.W)) //[1:0] Fast int lookup error + + val ifu_pmu_instr_aligned = Input(Bool()) // aligned instructions + val ifu_pmu_fetch_stall = Input(Bool()) // fetch unit stalled + val ifu_pmu_ic_miss = Input(Bool()) // icache miss + val ifu_pmu_ic_hit = Input(Bool()) // icache hit + val ifu_pmu_bus_error = Input(Bool()) // Instruction side bus error + val ifu_pmu_bus_busy = Input(Bool()) // Instruction side bus busy + val ifu_pmu_bus_trxn = Input(Bool()) // Instruction side bus transaction + + val ifu_ic_error_start = Input(Bool()) // IC single bit error + val ifu_iccm_rd_ecc_single_err = Input(Bool()) // ICCM single bit error + + val lsu_trigger_match_m = Input(UInt(4.W)) + val dbg_cmd_valid = Input(Bool()) // debugger abstract command valid + val dbg_cmd_write = Input(Bool()) // command is a write + val dbg_cmd_type = Input(UInt(2.W)) // command type + val dbg_cmd_addr = Input(UInt(32.W)) // command address + val dbg_cmd_wrdata = Input(UInt(2.W)) // command write data, for fence/fence_i + + + val ifu_i0_icaf = Input(Bool()) // icache access fault + val ifu_i0_icaf_type = Input(UInt(2.W)) + + val ifu_i0_icaf_f1 = Input(Bool()) // i0 has access fault on second fetch group + val ifu_i0_dbecc = Input(Bool()) // icache/iccm double-bit error + + val lsu_idle_any = Input(Bool()) // lsu idle for halting + + val i0_brp = Input(new el2_br_pkt_t) // branch packet + val ifu_i0_bp_index = Input(UInt(BTB_ADDR_HI.W)) // BP index + val ifu_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val ifu_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) // LSU exception/error packet + val lsu_single_ecc_error_incr = Input(Bool())// LSU inc SB error counter + + val lsu_imprecise_error_load_any = Input(Bool()) // LSU imprecise load bus error + val lsu_imprecise_error_store_any = Input(Bool()) // LSU imprecise store bus error + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // LSU imprecise bus error address + + val exu_div_result = Input(UInt(32.W)) // final div result + val exu_div_wren = Input(UInt(1.W)) // Divide write enable to GPR + val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instruction + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected load data + + val lsu_load_stall_any = Input(Bool()) // This is for blocking loads + val lsu_store_stall_any = Input(Bool()) // This is for blocking stores + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode, pmu event + val dma_iccm_stall_any = Input(Bool()) // iccm stalled, pmu event + + val iccm_dma_sb_error = Input(Bool()) // ICCM DMA single bit error + + val exu_flush_final = Input(Bool()) // slot0 flush + + val exu_npc_r = Input(UInt(32.W)) // next PC + + val exu_i0_result_x = Input(UInt(32.W)) // alu result x + + + val ifu_i0_valid = Input(Bool()) // fetch valids to instruction buffer + val ifu_i0_instr = Input(UInt(32.W)) // fetch inst's to instruction buffer + val ifu_i0_pc = Input(UInt(32.W)) // pc's for instruction buffer + val ifu_i0_pc4 = Input(Bool()) // indication of 4B or 2B for corresponding inst + val exu_i0_pc_x = Input(UInt(32.W)) // pc's for e1 from the alu's + + val mexintpend = Input(Bool()) // External interrupt pending + val timer_int = Input(Bool()) // Timer interrupt pending (from pin) + val soft_int = Input(Bool()) // Software interrupt pending (from pin) + + val pic_claimid = Input(UInt(8.W)) // PIC claimid + val pic_pl = Input(UInt(4.W)) // PIC priv level + val mhwakeup = Input(Bool()) // High priority wakeup + + val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC, Current priv level + val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + + val ifu_ic_debug_rd_data = Input(UInt(70.W)) // diagnostic icache read data + val ifu_ic_debug_rd_data_valid = Input(Bool()) // diagnostic icache read data valid + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + + + // Debug start + val dbg_halt_req = Input(Bool()) // DM requests a halt + val dbg_resume_req = Input(Bool()) // DM requests a resume + val ifu_miss_state_idle = Input(Bool()) // I-side miss buffer empty + + val dec_tlu_dbg_halted = Output(Bool()) // Core is halted and ready for debug command + val dec_tlu_debug_mode = Output(Bool()) // Core is in debug mode + val dec_tlu_resume_ack = Output(Bool()) // Resume acknowledge + val dec_tlu_flush_noredir_r = Output(Bool()) // Tell fetch to idle on this flush + val dec_tlu_mpc_halted_only = Output(Bool()) // Core is halted only due to MPC + val dec_tlu_flush_leak_one_r = Output(Bool()) // single step + val dec_tlu_flush_err_r = Output(Bool()) // iside perr/ecc rfpc + val dec_tlu_meihap = Output(UInt(32.W)) // Fast ext int base + + val dec_debug_wdata_rs1_d = Output(Bool()) // insert debug write data into rs1 at decode + + val dec_dbg_rddata = Output(UInt(32.W)) // debug command read data + + val dec_dbg_cmd_done = Output(Bool()) // abstract command is done + val dec_dbg_cmd_fail = Output(Bool()) // abstract command failed (illegal reg address) + + val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t)) // info needed by debug trigger blocks + + val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced + // Debug end + // branch info from pipe0 for errors or counter updates + val exu_i0_br_hist_r = Input(UInt(2.W)) // history + val exu_i0_br_error_r = Input(Bool()) // error + val exu_i0_br_start_error_r = Input(Bool()) // start error + val exu_i0_br_valid_r = Input(Bool()) // valid + val exu_i0_br_mp_r = Input(Bool()) // mispredict + val exu_i0_br_middle_r = Input(Bool()) // middle of bank + + val exu_i0_br_way_r = Input(Bool()) // way hit or repl + + val dec_i0_rs1_en_d = Output(Bool()) // Qualify GPR RS1 data + val dec_i0_rs2_en_d = Output(Bool()) // Qualify GPR RS2 data + val gpr_i0_rs1_d = Output(UInt(32.W)) // gpr rs1 data + val gpr_i0_rs2_d = Output(UInt(32.W)) // gpr rs2 data + + val dec_i0_immed_d = Output(UInt(32.W)) // immediate data + val dec_i0_br_immed_d = Output(UInt(13.W)) // br immediate data + + val i0_ap = Output(new el2_alu_pkt_t)// alu packet + + val dec_i0_alu_decode_d = Output(Bool()) // schedule on D-stage alu + + val dec_i0_select_pc_d = Output(Bool()) // select pc onto rs1 for jal's + + val dec_i0_pc_d = Output(UInt(32.W)) // pc's at decode + val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // rs1 bypass enable + val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // rs2 bypass enable + + val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // rs1 bypass data + val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // rs2 bypass data + + val lsu_p = Output(new el2_lsu_pkt_t) // lsu packet + val mul_p = Output(new el2_mul_pkt_t) // mul packet + val div_p = Output(new el2_div_pkt_t) // div packet + val dec_div_cancel = Output(Bool()) // cancel divide operation + + val dec_lsu_offset_d = Output(UInt(12.W)) // 12b offset for load/store addresses + + val dec_csr_ren_d = Output(Bool()) // csr read enable + + + val dec_tlu_flush_lower_r = Output(Bool()) // tlu flush due to late mp, exception, rfpc, or int + val dec_tlu_flush_path_r = Output(UInt(32.W)) // tlu flush target + val dec_tlu_i0_kill_writeb_r = Output(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_fence_i_r = Output(Bool()) // flush is a fence_i rfnpc, flush icache + + val pred_correct_npc_x = Output(UInt(32.W)) // npc if prediction is correct at e2 stage + + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // slot 0 branch predictor update packet + + val dec_tlu_perfcnt0 = Output(Bool()) // toggles when slot0 perf counter 0 has an event inc + val dec_tlu_perfcnt1 = Output(Bool()) // toggles when slot0 perf counter 1 has an event inc + val dec_tlu_perfcnt2 = Output(Bool()) // toggles when slot0 perf counter 2 has an event inc + val dec_tlu_perfcnt3 = Output(Bool()) // toggles when slot0 perf counter 3 has an event inc + + val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // prediction packet to alus + val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // DEC predict fghr + val i0_predict_index_d = Output(UInt(BHT_ADDR_HI.W)) // DEC predict index + val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // DEC predict branch tag + + val dec_lsu_valid_raw_d = Output(Bool()) + + val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control + + val dec_data_en = Output(UInt(2.W)) // clock-gate control logic + val dec_ctl_en = Output(UInt(2.W)) + + val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction + + val rv_trace_pkt = Output(new el2_trace_pkt_t) // trace packet + + // feature disable from mfdc + val dec_tlu_external_ldfwd_disable = Output(Bool()) // disable external load forwarding + val dec_tlu_sideeffect_posted_disable = Output(Bool()) // disable posted stores to side-effect address + val dec_tlu_core_ecc_disable = Output(Bool()) // disable core ECC + val dec_tlu_bpred_disable = Output(Bool()) // disable branch prediction + val dec_tlu_wb_coalescing_disable = Output(Bool()) // disable writebuffer coalescing + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + val dec_tlu_misc_clk_override = Output(Bool()) // override misc clock domain gating + val dec_tlu_ifu_clk_override = Output(Bool()) // override fetch clock domain gating + val dec_tlu_lsu_clk_override = Output(Bool()) // override load/store clock domain gating + val dec_tlu_bus_clk_override = Output(Bool()) // override bus clock domain gating + val dec_tlu_pic_clk_override = Output(Bool()) // override PIC clock domain gating + val dec_tlu_dccm_clk_override = Output(Bool()) // override DCCM clock domain gating + val dec_tlu_icm_clk_override = Output(Bool()) // override ICCM clock domain gating + + val dec_tlu_i0_commit_cmt = Output(Bool()) // committed i0 instruction + val scan_mode = Input(Bool()) + +} + +class el2_dec extends Module with param with RequireAsyncReset{ + val io = IO(new el2_dec_IO) + io.dec_i0_pc_d := 0.U + + + + // val dec_ib0_valid_d = WireInit(Bool(),0.B) + // + // val dec_pmu_instr_decoded = WireInit(Bool(),0.B) + // val dec_pmu_decode_stall = WireInit(Bool(),0.B) + // val dec_pmu_presync_stall = WireInit(Bool(),0.B) + // val dec_pmu_postsync_stall = WireInit(Bool(),0.B) + // + // val dec_tlu_wr_pause_r = WireInit(UInt(1.W),0.U) // CSR write to pause reg is at R. + // + // val dec_i0_rs1_d = WireInit(UInt(5.W),0.U) + // val dec_i0_rs2_d = WireInit(UInt(5.W),0.U) + // + // val dec_i0_instr_d = WireInit(UInt(32.W),0.U) + // + // val dec_tlu_pipelining_disable = WireInit(UInt(1.W),0.U) + // val dec_i0_waddr_r = WireInit(UInt(5.W),0.U) + // val dec_i0_wen_r = WireInit(UInt(5.W),0.U) + // val dec_i0_wdata_r = WireInit(UInt(32.W),0.U) + // val dec_csr_wen_r = WireInit(UInt(1.W),0.U) // csr write enable at wb + // val dec_csr_wraddr_r = WireInit(UInt(12.W),0.U) // write address for csryes + // val dec_csr_wrdata_r = WireInit(UInt(32.W),0.U) // csr write data at wb + // + // val dec_csr_rdaddr_d = WireInit(UInt(12.W),0.U) // read address for csr + // val dec_csr_rddata_d = WireInit(UInt(32.W),0.U) // csr read data at wb + // val dec_csr_legal_d = WireInit(Bool(),0.B) // csr indicates legal operation + // + // val dec_csr_wen_unq_d = WireInit(Bool(),0.B) // valid csr with write - for csr legal + // val dec_csr_any_unq_d = WireInit(Bool(),0.B) // valid csr - for csr legal + // val dec_csr_stall_int_ff = WireInit(Bool(),0.B) // csr is mie/mstatus + // + // val dec_tlu_packet_r = Wire(new el2_trap_pkt_t) + // + // val dec_i0_pc4_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_presync_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_postsync_d = WireInit(UInt(1.W),0.U) + // val dec_tlu_debug_stall = WireInit(UInt(1.W),0.U) + // val dec_illegal_inst = WireInit(UInt(32.W),0.U) + // val dec_i0_icaf_d = WireInit(UInt(1.W),0.U) + // val dec_i0_dbecc_d = WireInit(UInt(1.W),0.U) + // val dec_i0_icaf_f1_d = WireInit(UInt(1.W),0.U) + // val dec_i0_trigger_match_d = WireInit(UInt(4.W),0.U) + // val dec_debug_fence_d = WireInit(UInt(1.W),0.U) + // val dec_nonblock_load_wen = WireInit(UInt(1.W),0.U) + // val dec_nonblock_load_waddr = WireInit(UInt(5.W),0.U) + // val dec_tlu_flush_pause_r = WireInit(UInt(1.W),0.U) + // val dec_i0_brp = Wire(new el2_br_pkt_t) + // val dec_i0_bp_index = WireInit(UInt(BTB_ADDR_HI.W),0.U) + // val dec_i0_bp_fghr = WireInit(UInt(BHT_GHR_SIZE.W),0.U) + // val dec_i0_bp_btag = WireInit(UInt(BTB_BTAG_SIZE.W),0.U) + // + // val dec_tlu_i0_pc_r = WireInit(UInt(32.W),0.U) + // val dec_tlu_i0_kill_writeb_wb = WireInit(Bool(),0.B) + // val dec_tlu_flush_lower_wb = WireInit(Bool(),0.B) + // val dec_tlu_i0_valid_r = WireInit(Bool(),0.B) + // + // val dec_pause_state = WireInit(Bool(),0.B) + // + // val dec_i0_icaf_type_d = WireInit(UInt(2.W),0.U) // i0 instruction access fault type + // + // val dec_tlu_flush_extint = WireInit(Bool(),0.B)// Fast ext int started + // + val dec_i0_inst_wb1 = WireInit(UInt(32.W),0.U) + val dec_i0_pc_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_valid_wb1 = WireInit(UInt(1.W),0.U) + val dec_tlu_int_valid_wb1 = WireInit(UInt(1.W),0.U) + + val dec_tlu_exc_cause_wb1 = WireInit(UInt(5.W),0.U) + val dec_tlu_mtval_wb1 = WireInit(UInt(32.W),0.U) + val dec_tlu_i0_exc_valid_wb1 = WireInit(Bool(),0.B) + // + // val div_waddr_wb = WireInit(UInt(5.W),0.U) + // + // val dec_div_active = WireInit(Bool(),0.B) + + + //--------------------------------------------------------------------------// + val instbuff = Module(new el2_dec_ib_ctl) + val decode = Module(new el2_dec_decode_ctl) + val gpr = Module(new el2_dec_gpr_ctl) + val tlu = Module(new el2_dec_tlu_ctl) + val dec_trigger = Module(new el2_dec_trigger) + + //instbuff.io <> io // error "Connection between left (el2_dec_ib_ctl_IO(IO io in el2_dec_ib_ctl)) and source (el2_dec_IO(" + //--------------------------------------------------------------------------// + + //connections for el2_dec_Ib + //inputs + instbuff.io.dbg_cmd_valid := io.dbg_cmd_valid + instbuff.io.dbg_cmd_write := io.dbg_cmd_write + instbuff.io.dbg_cmd_type := io.dbg_cmd_type + instbuff.io.dbg_cmd_addr := io.dbg_cmd_addr + instbuff.io.i0_brp := io.i0_brp + instbuff.io.ifu_i0_bp_index := io.ifu_i0_bp_index + instbuff.io.ifu_i0_bp_fghr := io.ifu_i0_bp_fghr + instbuff.io.ifu_i0_bp_btag := io.ifu_i0_bp_btag + instbuff.io.ifu_i0_pc4 := io.ifu_i0_pc4 + instbuff.io.ifu_i0_valid := io.ifu_i0_valid + instbuff.io.ifu_i0_icaf := io.ifu_i0_icaf + instbuff.io.ifu_i0_icaf_type := io.ifu_i0_icaf_type + instbuff.io.ifu_i0_icaf_f1 := io.ifu_i0_icaf_f1 + instbuff.io.ifu_i0_dbecc := io.ifu_i0_dbecc + instbuff.io.ifu_i0_instr := io.ifu_i0_instr + instbuff.io.ifu_i0_pc := io.ifu_i0_pc + //outputs + decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d + decode.io.dec_i0_icaf_type_d :=instbuff.io.dec_i0_icaf_type_d + decode.io.dec_i0_instr_d :=instbuff.io.dec_i0_instr_d + decode.io.dec_i0_pc_d :=instbuff.io.dec_i0_pc_d + decode.io.dec_i0_pc4_d :=instbuff.io.dec_i0_pc4_d + decode.io.dec_i0_brp :=instbuff.io.dec_i0_brp + decode.io.dec_i0_bp_index :=instbuff.io.dec_i0_bp_index + decode.io.dec_i0_bp_fghr :=instbuff.io.dec_i0_bp_fghr + decode.io.dec_i0_bp_btag :=instbuff.io.dec_i0_bp_btag + decode.io.dec_i0_icaf_d :=instbuff.io.dec_i0_icaf_d + decode.io.dec_i0_icaf_f1_d :=instbuff.io.dec_i0_icaf_f1_d + decode.io.dec_i0_dbecc_d :=instbuff.io.dec_i0_dbecc_d + io.dec_debug_wdata_rs1_d := instbuff.io.dec_debug_wdata_rs1_d + decode.io.dec_debug_fence_d :=instbuff.io.dec_debug_fence_d + //--------------------------------------------------------------------------// + + //connections for dec_trigger + //dec_trigger.io <> io + //inputs + dec_trigger.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d + dec_trigger.io.trigger_pkt_any := tlu.io.trigger_pkt_any + //output + val dec_i0_trigger_match_d = dec_trigger.io.dec_i0_trigger_match_d + dontTouch(dec_i0_trigger_match_d) + //--------------------------------------------------------------------------// + + //connections for el2_dec_decode + // decode.io <> io + //inputs + decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint + decode.io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt + decode.io.ifu_i0_cinst := io.ifu_i0_cinst + decode.io.lsu_nonblock_load_valid_m := io.lsu_nonblock_load_valid_m + decode.io.lsu_nonblock_load_tag_m := io.lsu_nonblock_load_tag_m + decode.io.lsu_nonblock_load_inv_r := io.lsu_nonblock_load_inv_r + decode.io.lsu_nonblock_load_inv_tag_r := io.lsu_nonblock_load_inv_tag_r + decode.io.lsu_nonblock_load_data_valid := io.lsu_nonblock_load_data_valid + decode.io.lsu_nonblock_load_data_error := io.lsu_nonblock_load_data_error + decode.io.lsu_nonblock_load_data_tag := io.lsu_nonblock_load_data_tag + decode.io.lsu_nonblock_load_data := io.lsu_nonblock_load_data + decode.io.dec_i0_trigger_match_d := dec_i0_trigger_match_d + decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r + decode.io.dec_tlu_pipelining_disable := tlu.io.dec_tlu_pipelining_disable + decode.io.lsu_trigger_match_m := io.lsu_trigger_match_m + decode.io.lsu_pmu_misaligned_m := io.lsu_pmu_bus_misaligned + decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall + decode.io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r + decode.io.dec_debug_fence_d := instbuff.io.dec_debug_fence_d + decode.io.dbg_cmd_wrdata := io.dbg_cmd_wrdata + decode.io.dec_i0_icaf_d := instbuff.io.dec_i0_icaf_d + decode.io.dec_i0_icaf_f1_d := instbuff.io.dec_i0_icaf_f1_d + decode.io.dec_i0_icaf_type_d := instbuff.io.dec_i0_icaf_type_d + decode.io.dec_i0_dbecc_d := instbuff.io.dec_i0_dbecc_d + decode.io.dec_i0_brp := instbuff.io.dec_i0_brp + decode.io.dec_i0_bp_index := instbuff.io.dec_i0_bp_index + decode.io.dec_i0_bp_fghr := instbuff.io.dec_i0_bp_fghr + decode.io.dec_i0_bp_btag := instbuff.io.dec_i0_bp_btag + decode.io.dec_i0_pc_d := instbuff.io.dec_i0_pc_d + decode.io.lsu_idle_any := io.lsu_idle_any + decode.io.lsu_load_stall_any := io.lsu_load_stall_any + decode.io.lsu_store_stall_any := io.lsu_store_stall_any + decode.io.dma_dccm_stall_any := io.dma_dccm_stall_any + decode.io.exu_div_wren := io.exu_div_wren + decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + decode.io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + decode.io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r + decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r + decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d + decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d + decode.io.dec_i0_pc4_d := instbuff.io.dec_i0_pc_d + decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d + decode.io.exu_csr_rs1_x := io.exu_csr_rs1_x + decode.io.lsu_result_m := io.lsu_result_m + decode.io.lsu_result_corr_r := io.lsu_result_corr_r + decode.io.exu_flush_final := io.exu_flush_final + decode.io.exu_i0_pc_x := io.exu_i0_pc_x + decode.io.dec_i0_instr_d := instbuff.io.dec_i0_instr_d + decode.io.dec_ib0_valid_d := instbuff.io.dec_ib0_valid_d + decode.io.exu_i0_result_x := io.exu_i0_result_x + //decode.io.clk := io.clk + decode.io.free_clk := io.free_clk + decode.io.active_clk := io.active_clk + decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override + // decode.io.rst_l := io.rst_l + decode.io.scan_mode := io.scan_mode + //outputs + io.dec_extint_stall := decode.io.dec_extint_stall + dec_i0_inst_wb1 := decode.io.dec_i0_inst_wb1 //for tracer + dec_i0_pc_wb1 := decode.io.dec_i0_pc_wb1 //for tracer + io.dec_i0_rs1_en_d := decode.io.dec_i0_rs1_en_d + io.dec_i0_rs2_en_d := decode.io.dec_i0_rs2_en_d + gpr.io.raddr0 := decode.io.dec_i0_rs1_d + gpr.io.raddr1 := decode.io.dec_i0_rs2_d + io.dec_i0_immed_d := decode.io.dec_i0_immed_d + io.dec_i0_br_immed_d := decode.io.dec_i0_br_immed_d + io.i0_ap := decode.io.i0_ap + io.dec_i0_decode_d := decode.io.dec_i0_decode_d + io.dec_i0_alu_decode_d := decode.io.dec_i0_alu_decode_d + io.dec_i0_rs1_bypass_data_d := decode.io.dec_i0_rs1_bypass_data_d + io.dec_i0_rs2_bypass_data_d := decode.io.dec_i0_rs2_bypass_data_d + gpr.io.waddr0 := decode.io.dec_i0_waddr_r + gpr.io.wen0 := decode.io.dec_i0_wen_r + gpr.io.wd0 := decode.io.dec_i0_wdata_r + io.dec_i0_select_pc_d := decode.io.dec_i0_select_pc_d + io.dec_i0_rs1_bypass_en_d := decode.io.dec_i0_rs1_bypass_en_d + io.dec_i0_rs2_bypass_en_d := decode.io.dec_i0_rs2_bypass_en_d + io.lsu_p := decode.io.lsu_p + io.mul_p := decode.io.mul_p + io.div_p := decode.io.div_p + gpr.io.waddr2 := decode.io.div_waddr_wb + io.dec_div_cancel := decode.io.dec_div_cancel + io.dec_lsu_valid_raw_d := decode.io.dec_lsu_valid_raw_d + io.dec_lsu_offset_d := decode.io.dec_lsu_offset_d + io.dec_csr_ren_d := decode.io.dec_csr_ren_d + tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d + tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d + tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d + tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r + tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r + tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r + tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff + tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r + tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r + tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r + tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst + io.pred_correct_npc_x := decode.io.pred_correct_npc_x + io.dec_i0_predict_p_d := decode.io.dec_i0_predict_p_d + io.i0_predict_fghr_d := decode.io.i0_predict_fghr_d + io.i0_predict_index_d := decode.io.i0_predict_index_d + io.i0_predict_btag_d := decode.io.i0_predict_btag_d + io.dec_data_en := decode.io.dec_data_en + io.dec_ctl_en := decode.io.dec_ctl_en + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_instr_decoded + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_decode_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_presync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_wen + tlu.io.dec_pmu_postsync_stall := decode.io.dec_nonblock_load_waddr + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pause_state + io.dec_pause_state_cg := decode.io.dec_pause_state_cg + tlu.io.dec_div_active := decode.io.dec_div_active + //--------------------------------------------------------------------------// + + + //connections for gprfile + // gpr.io <> io + //inputs + gpr.io.raddr0 := decode.io.dec_i0_rs1_d + gpr.io.raddr1 := decode.io.dec_i0_rs2_d + gpr.io.wen0 := decode.io.dec_i0_wen_r + gpr.io.waddr0 := decode.io.dec_i0_waddr_r + gpr.io.wd0 := decode.io.dec_i0_wdata_r + gpr.io.wen1 := decode.io.dec_nonblock_load_wen + gpr.io.waddr1 := decode.io.dec_nonblock_load_waddr + gpr.io.wd1 := io.lsu_nonblock_load_data + gpr.io.wen2 := io.exu_div_wren + gpr.io.waddr2 := decode.io.div_waddr_wb + gpr.io.wd2 := io.exu_div_result + //gpr.io.clk := io.clk + //gpr.io.rst_l := io.rst_l + gpr.io.scan_mode := io.scan_mode + // outputs + io.gpr_i0_rs1_d := gpr.io.rd0 + io.gpr_i0_rs2_d := gpr.io.rd1 + //--------------------------------------------------------------------------// + + + + //connection for dec_tlu + // tlu.io <> io + //inputs + //tlu.io.clk := io.clk + tlu.io.active_clk := io.active_clk + tlu.io.free_clk := io.free_clk + // tlu.io.rst_l := io.rst_l + tlu.io.scan_mode := io.scan_mode + tlu.io.rst_vec := io.rst_vec + tlu.io.nmi_int := io.nmi_int + tlu.io.nmi_vec := io.nmi_vec + tlu.io.i_cpu_halt_req := io.i_cpu_halt_req + tlu.io.i_cpu_run_req := io.i_cpu_run_req + tlu.io.lsu_fastint_stall_any := io.lsu_fastint_stall_any + tlu.io.ifu_pmu_instr_aligned := io.ifu_pmu_instr_aligned + tlu.io.ifu_pmu_fetch_stall := io.ifu_pmu_fetch_stall + tlu.io.ifu_pmu_ic_miss := io.ifu_pmu_ic_miss + tlu.io.ifu_pmu_ic_hit := io.ifu_pmu_ic_hit + tlu.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error + tlu.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy + tlu.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn + tlu.io.dec_pmu_instr_decoded := decode.io.dec_pmu_instr_decoded + tlu.io.dec_pmu_decode_stall := decode.io.dec_pmu_decode_stall + tlu.io.dec_pmu_presync_stall := decode.io.dec_pmu_presync_stall + tlu.io.dec_pmu_postsync_stall := decode.io.dec_pmu_postsync_stall + tlu.io.lsu_store_stall_any := io.lsu_store_stall_any + tlu.io.dma_dccm_stall_any := io.dma_dccm_stall_any + tlu.io.dma_iccm_stall_any := io.dma_iccm_stall_any + tlu.io.exu_pmu_i0_br_misp := io.exu_pmu_i0_br_misp + tlu.io.exu_pmu_i0_br_ataken := io.exu_pmu_i0_br_ataken + tlu.io.exu_pmu_i0_pc4 := io.exu_pmu_i0_pc4 + tlu.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn + tlu.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned + tlu.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error + tlu.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy + tlu.io.lsu_pmu_load_external_m := io.lsu_pmu_load_external_m + tlu.io.lsu_pmu_store_external_m := io.lsu_pmu_store_external_m + tlu.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read + tlu.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write + tlu.io.dma_pmu_any_read := io.dma_pmu_any_read + tlu.io.dma_pmu_any_write := io.dma_pmu_any_write + tlu.io.lsu_fir_addr := io.lsu_fir_addr + tlu.io.lsu_fir_error := io.lsu_fir_error + tlu.io.iccm_dma_sb_error := io.iccm_dma_sb_error + tlu.io.lsu_error_pkt_r := io.lsu_error_pkt_r + tlu.io.lsu_single_ecc_error_incr := io.lsu_single_ecc_error_incr + tlu.io.dec_pause_state := decode.io.dec_pause_state + tlu.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any + tlu.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any + tlu.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any + tlu.io.dec_csr_wen_unq_d := decode.io.dec_csr_wen_unq_d + tlu.io.dec_csr_any_unq_d := decode.io.dec_csr_any_unq_d + tlu.io.dec_csr_rdaddr_d := decode.io.dec_csr_rdaddr_d + tlu.io.dec_csr_wen_r := decode.io.dec_csr_wen_r + tlu.io.dec_csr_wraddr_r := decode.io.dec_csr_wraddr_r + tlu.io.dec_csr_wrdata_r := decode.io.dec_csr_wrdata_r + tlu.io.dec_csr_stall_int_ff := decode.io.dec_csr_stall_int_ff + tlu.io.dec_tlu_i0_valid_r := decode.io.dec_tlu_i0_valid_r + tlu.io.exu_npc_r := io.exu_npc_r + tlu.io.dec_tlu_i0_pc_r := decode.io.dec_tlu_i0_pc_r + tlu.io.dec_tlu_packet_r := decode.io.dec_tlu_packet_r + tlu.io.dec_illegal_inst := decode.io.dec_illegal_inst + tlu.io.dec_i0_decode_d := decode.io.dec_i0_decode_d + tlu.io.exu_i0_br_hist_r := io.exu_i0_br_hist_r + tlu.io.exu_i0_br_error_r := io.exu_i0_br_error_r + tlu.io.exu_i0_br_start_error_r := io.exu_i0_br_start_error_r + tlu.io.exu_i0_br_valid_r := io.exu_i0_br_valid_r + tlu.io.exu_i0_br_mp_r := io.exu_i0_br_mp_r + tlu.io.exu_i0_br_middle_r := io.exu_i0_br_middle_r + tlu.io.exu_i0_br_way_r := io.exu_i0_br_way_r + tlu.io.dbg_halt_req := io.dbg_halt_req + tlu.io.dbg_resume_req := io.dbg_resume_req + tlu.io.ifu_miss_state_idle := io.ifu_miss_state_idle + tlu.io.lsu_idle_any := io.lsu_idle_any + tlu.io.dec_div_active := decode.io.dec_div_active + tlu.io.ifu_ic_error_start := io.ifu_ic_error_start + tlu.io.ifu_iccm_rd_ecc_single_err := io.ifu_iccm_rd_ecc_single_err + tlu.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data + tlu.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid + tlu.io.pic_claimid := io.pic_claimid + tlu.io.pic_pl := io.pic_pl + tlu.io.mhwakeup := io.mhwakeup + tlu.io.mexintpend := io.mexintpend + tlu.io.timer_int := io.timer_int + tlu.io.soft_int := io.soft_int + tlu.io.core_id := io.core_id + tlu.io.mpc_debug_halt_req := io.mpc_debug_halt_req + tlu.io.mpc_debug_run_req := io.mpc_debug_run_req + tlu.io.mpc_reset_run_req := io.mpc_reset_run_req + //outputs + io.dec_dbg_cmd_done := tlu.io.dec_dbg_cmd_done + io.dec_dbg_cmd_fail := tlu.io.dec_dbg_cmd_fail + io.dec_tlu_dbg_halted := tlu.io.dec_tlu_dbg_halted + io.dec_tlu_debug_mode := tlu.io.dec_tlu_debug_mode + io.dec_tlu_resume_ack := tlu.io.dec_tlu_resume_ack + decode.io.dec_tlu_debug_stall := tlu.io.dec_tlu_debug_stall + io.dec_tlu_flush_noredir_r := tlu.io.dec_tlu_flush_noredir_r + io.dec_tlu_mpc_halted_only := tlu.io.dec_tlu_mpc_halted_only + io.dec_tlu_flush_leak_one_r := tlu.io.dec_tlu_flush_leak_one_r + io.dec_tlu_flush_err_r := tlu.io.dec_tlu_flush_err_r + decode.io.dec_tlu_flush_extint := tlu.io.dec_tlu_flush_extint + io.dec_tlu_meihap := tlu.io.dec_tlu_meihap + io.trigger_pkt_any := tlu.io.trigger_pkt_any + io.dec_tlu_ic_diag_pkt := tlu.io.dec_tlu_ic_diag_pkt + io.o_cpu_halt_status := tlu.io.o_cpu_halt_status + io.o_cpu_halt_ack := tlu.io.o_cpu_halt_ack + io.o_cpu_run_ack := tlu.io.o_cpu_run_ack + io.o_debug_mode_status := tlu.io.o_debug_mode_status + io.mpc_debug_halt_ack := tlu.io.mpc_debug_halt_ack + io.mpc_debug_run_ack := tlu.io.mpc_debug_run_ack + io.debug_brkpt_status := tlu.io.debug_brkpt_status + io.dec_tlu_meicurpl := tlu.io.dec_tlu_meicurpl + io.dec_tlu_meipt := tlu.io.dec_tlu_meipt + decode.io.dec_csr_rddata_d := tlu.io.dec_csr_rddata_d + decode.io.dec_csr_legal_d := tlu.io.dec_csr_legal_d + io.dec_tlu_br0_r_pkt := tlu.io.dec_tlu_br0_r_pkt + decode.io.dec_tlu_i0_kill_writeb_wb := tlu.io.dec_tlu_i0_kill_writeb_wb + decode.io.dec_tlu_flush_lower_wb := tlu.io.dec_tlu_flush_lower_wb + io.dec_tlu_i0_commit_cmt := tlu.io.dec_tlu_i0_commit_cmt + io.dec_tlu_i0_kill_writeb_r := tlu.io.dec_tlu_i0_kill_writeb_r + io.dec_tlu_flush_lower_r := tlu.io.dec_tlu_flush_lower_r + io.dec_tlu_flush_path_r := tlu.io.dec_tlu_flush_path_r + io.dec_tlu_fence_i_r := tlu.io.dec_tlu_fence_i_r + decode.io.dec_tlu_wr_pause_r := tlu.io.dec_tlu_wr_pause_r + decode.io.dec_tlu_flush_pause_r := tlu.io.dec_tlu_flush_pause_r + decode.io.dec_tlu_presync_d := tlu.io.dec_tlu_presync_d + decode.io.dec_tlu_postsync_d := tlu.io.dec_tlu_postsync_d + io.dec_tlu_mrac_ff := tlu.io.dec_tlu_mrac_ff + io.dec_tlu_force_halt := tlu.io.dec_tlu_force_halt + io.dec_tlu_perfcnt0 := tlu.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := tlu.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := tlu.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := tlu.io.dec_tlu_perfcnt3 + dec_tlu_i0_exc_valid_wb1 := tlu.io.dec_tlu_i0_exc_valid_wb1 + dec_tlu_i0_valid_wb1 := tlu.io.dec_tlu_i0_valid_wb1 + dec_tlu_int_valid_wb1 := tlu.io.dec_tlu_int_valid_wb1 + dec_tlu_exc_cause_wb1 := tlu.io.dec_tlu_exc_cause_wb1 + dec_tlu_mtval_wb1 := tlu.io.dec_tlu_mtval_wb1 + io.dec_tlu_external_ldfwd_disable := tlu.io.dec_tlu_external_ldfwd_disable + io.dec_tlu_sideeffect_posted_disable := tlu.io.dec_tlu_sideeffect_posted_disable + io.dec_tlu_core_ecc_disable := tlu.io.dec_tlu_core_ecc_disable + io.dec_tlu_bpred_disable := tlu.io.dec_tlu_bpred_disable + io.dec_tlu_wb_coalescing_disable := tlu.io.dec_tlu_wb_coalescing_disable + // := tlu.io.dec_tlu_pipelining_disable + io.dec_tlu_dma_qos_prty := tlu.io.dec_tlu_dma_qos_prty + io.dec_tlu_misc_clk_override := tlu.io.dec_tlu_misc_clk_override + //decode.io.clk_override := tlu.io.dec_tlu_dec_clk_override + io.dec_tlu_ifu_clk_override := tlu.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := tlu.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := tlu.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := tlu.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := tlu.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := tlu.io.dec_tlu_icm_clk_override + + //--------------------------------------------------------------------------// + + io.rv_trace_pkt.rv_i_insn_ip := decode.io.dec_i0_inst_wb1 + io.rv_trace_pkt.rv_i_address_ip := Cat(decode.io.dec_i0_pc_wb1, 0.U) + io.rv_trace_pkt.rv_i_valid_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_valid_wb1 | tlu.io.dec_tlu_i0_exc_valid_wb1) + io.rv_trace_pkt.rv_i_exception_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, tlu.io.dec_tlu_i0_exc_valid_wb1) + io.rv_trace_pkt.rv_i_ecause_ip := tlu.io.dec_tlu_exc_cause_wb1(4,0) + io.rv_trace_pkt.rv_i_interrupt_ip := Cat(tlu.io.dec_tlu_int_valid_wb1, 0.U) + io.rv_trace_pkt.rv_i_tval_ip := tlu.io.dec_tlu_mtval_wb1 + + + // debug command read data + io.dec_dbg_rddata := decode.io.dec_i0_wdata_r +} +object dec_main extends App { + println((new chisel3.stage.ChiselStage).emitVerilog( new el2_dec())) +} diff --git a/src/main/scala/dec/el2_dec_dec_ctl.scala b/src/main/scala/dec/el2_dec_dec_ctl.scala new file mode 100644 index 00000000..0a0d95f4 --- /dev/null +++ b/src/main/scala/dec/el2_dec_dec_ctl.scala @@ -0,0 +1,173 @@ +package dec +import chisel3._ +import chisel3.util._ + +class el2_dec_pkt_t extends Bundle{ + val alu = Bool() + val rs1 = Bool() + val rs2 = Bool() + val imm12 = Bool() + val rd = Bool() + val shimm5 = Bool() + val imm20 = Bool() + val pc = Bool() + val load = Bool() + val store = Bool() + val lsu = Bool() + val add = Bool() + val sub = Bool() + val land = Bool() + val lor = Bool() + val lxor = Bool() + val sll = Bool() + val sra = Bool() + val srl = Bool() + val slt = Bool() + val unsign = Bool() + val condbr = Bool() + val beq = Bool() + val bne = Bool() + val bge = Bool() + val blt = Bool() + val jal = Bool() + val by = Bool() + val half = Bool() + val word = Bool() + val csr_read = Bool() + val csr_clr = Bool() + val csr_set = Bool() + val csr_write = Bool() + val csr_imm = Bool() + val presync = Bool() + val postsync = Bool() + val ebreak = Bool() + val ecall = Bool() + val mret = Bool() + val mul = Bool() + val rs1_sign = Bool() + val rs2_sign = Bool() + val low = Bool() + val div = Bool() + val rem = Bool() + val fence = Bool() + val fence_i = Bool() + val pm_alu = Bool() + val legal = Bool() +} + +class el2_dec_dec_ctl extends Module{ + val io = IO (new Bundle{ + val ins = Input(UInt(32.W)) + val out = Output(new el2_dec_pkt_t) + }) + + def pattern(y : List[Int]) : Array[UInt] = { + val pat : Array[UInt] = new Array[UInt](y.size) + for (i <- 0 until y.size){ + pat(i) = if(y(i)>0) io.ins(y(i)) else !io.ins(y(i).abs) + } + pat + } + + io.out.alu := io.ins(2) | io.ins(6) | (!io.ins(25)&io.ins(4)) | (!io.ins(5)&io.ins(4)) + io.out.rs1 := pattern(List(-14,-13,-2)).reduce(_&_) | pattern(List(-13,11,-2)).reduce(_&_) | + pattern(List(19,13,-2)).reduce(_&_) | pattern(List(-13,10,-2)).reduce(_&_) | + pattern(List(-18,13,-2)).reduce(_&_) | pattern(List(-13,9,-2)).reduce(_&_) | + pattern(List(17,13,-2)).reduce(_&_) | pattern(List(-13,8,-2)).reduce(_&_) | + pattern(List(16,13,-2)).reduce(_&_) | pattern(List(-13,7,-2)).reduce(_&_) | + pattern(List(15,13,-2)).reduce(_&_) |pattern(List(-4,-3)).reduce(_&_) | pattern(List(-6,-2)).reduce(_&_) + io.out.rs2 := pattern(List(5,-4,-2)).reduce(_&_) | pattern(List(-6,5,-2)).reduce(_&_) + io.out.imm12 := pattern(List(-4,-3,2)).reduce(_&_) | pattern(List(13,-5,4,-2)).reduce(_&_) | + pattern(List(-13,-12,6,4)).reduce(_&_) | pattern(List(-12,-5,4,-2)).reduce(_&_) + io.out.rd := (!io.ins(5) & !io.ins(2)) | (io.ins(5) & io.ins(2)) | io.ins(4) + io.out.shimm5 := pattern(List(-13,12,-5,4,-2)).reduce(_&_) + io.out.imm20 := (io.ins(5)&io.ins(3)) | (io.ins(4)&io.ins(2)) + io.out.pc := (!io.ins(5) & !io.ins(3) & io.ins(2)) | (io.ins(5) & io.ins(3)) + io.out.load := pattern(List(-5,-4,-2)).reduce(_&_) + io.out.store := pattern(List(-6,5,-4)).reduce(_&_) + io.out.lsu := pattern(List(-6,-4,-2)).reduce(_&_) + io.out.add := pattern(List(-14,-13,-12,-5,4)).reduce(_&_) | pattern(List(-5,-3,2)).reduce(_&_) | + pattern(List(-30,-25,-14,-13,-12,-6,4,-2)).reduce(_&_) + io.out.sub := pattern(List(30,-12,-6,5,4,-2)).reduce(_&_) | pattern(List(-25,-14,13,-6,4,-2)).reduce(_&_) | + pattern(List(-14,13,-5,4,-2)).reduce(_&_) | pattern(List(6,-4,-2)).reduce(_&_) + io.out.land := pattern(List(14,13,12,-5,-2)).reduce(_&_) | pattern(List(-25,14,13,12,-6,-2)).reduce(_&_) + io.out.lor := pattern(List(-6,3)).reduce(_&_) | pattern(List(-25,14,13,-12,-6,-2)).reduce(_&_) | + pattern(List(5,4,2)).reduce(_&_) | pattern(List(-13,-12,6,4)).reduce(_&_) | + pattern(List(14,13,-12,-5,-2)).reduce(_&_) + io.out.lxor := pattern(List(-25,14,-13,-12,4,-2)).reduce(_&_) | pattern(List(14,-13,-12,-5,4,-2)).reduce(_&_) + io.out.sll := pattern(List(-25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.sra := pattern(List(30,-13,12,-6,4,-2)).reduce(_&_) + io.out.srl := pattern(List(-30,-25,14,-13,12,-6,4,-2)).reduce(_&_) + io.out.slt := pattern(List(-25,-14,13,12,-6,4,-2)).reduce(_&_) | pattern(List(-14,13,-5,4,-2)).reduce(_&_) + io.out.unsign := pattern(List(-14,13,12,-5,-2)).reduce(_&_) | pattern(List(13,6,-4,-2)).reduce(_&_) | + pattern(List(14,-5,-4)).reduce(_&_) | pattern(List(-25,-14,13,12,-6,-2)).reduce(_&_) | + pattern(List(25,14,12,-6,5,-2)).reduce(_&_) + io.out.condbr := pattern(List(6,-4,-2)).reduce(_&_) + io.out.beq := pattern(List(-14,-12,6,-4,-2)).reduce(_&_) + io.out.bne := pattern(List(-14,12,6,-4,-2)).reduce(_&_) + io.out.bge := pattern(List(14,12,5,-4,-2)).reduce(_&_) + io.out.blt := pattern(List(14,-12,5,-4,-2)).reduce(_&_) + io.out.jal := pattern(List(6,2)).reduce(_&_) + io.out.by := pattern(List(-13,-12,-6,-4,-2)).reduce(_&_) + io.out.half := pattern(List(12,-6,-4,-2)).reduce(_&_) + io.out.word := pattern(List(13,-6,-4)).reduce(_&_) + io.out.csr_read := pattern(List(13,6,4)).reduce(_&_) | pattern(List(7,6,4)).reduce(_&_) | + pattern(List(8,6,4)).reduce(_&_) | pattern(List(9,6,4)).reduce(_&_) | pattern(List(10,6,4)).reduce(_&_) | + pattern(List(11,6,4)).reduce(_&_) + io.out.csr_clr := pattern(List(15,13,12,6,4)).reduce(_&_) | pattern(List(16,13,12,6,4)).reduce(_&_) | + pattern(List(17,13,12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | + pattern(List(19,-12,6,4)).reduce(_&_) + io.out.csr_write := pattern(List(-13,12,6,4)).reduce(_&_) + io.out.csr_imm := pattern(List(14,-13,6,4)).reduce(_&_) | pattern(List(15,14,6,4)).reduce(_&_) | + pattern(List(16,14,6,4)).reduce(_&_) | pattern(List(17,14,6,4)).reduce(_&_) | + pattern(List(18,14,6,4)).reduce(_&_) | pattern(List(19,14,6,4)).reduce(_&_) + io.out.csr_set := pattern(List(15,-12,6,4)).reduce(_&_) | pattern(List(16,-12,6,4)).reduce(_&_) | + pattern(List(17,-12,6,4)).reduce(_&_) | pattern(List(18,-12,6,4)).reduce(_&_) | + pattern(List(19,-12,6,4)).reduce(_&_) + io.out.ebreak := pattern(List(-22,20,-13,-12,6,4)).reduce(_&_) + io.out.ecall := pattern(List(-21,-20,-13,-12,6,4)).reduce(_&_) + io.out.mret := pattern(List(29,-13,-12,6,4)).reduce(_&_) + io.out.mul := pattern(List(25,-14,-6,5,4,-2)).reduce(_&_) + io.out.rs1_sign := pattern(List(25,-14,13,-12,-6,5,4,-2)).reduce(_&_) | + pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.rs2_sign := pattern(List(25,-14,-13,12,-6,4,-2)).reduce(_&_) + io.out.low := pattern(List(25,-14,-13,-12,5,4,-2)).reduce(_&_) + io.out.div := pattern(List(25,14,-6,5,-2)).reduce(_&_) + io.out.rem := pattern(List(25,14,13,-6,5,-2)).reduce(_&_) + io.out.fence := pattern(List(-5,3)).reduce(_&_) + io.out.fence_i := pattern(List(12,-5,3)).reduce(_&_) + io.out.pm_alu := pattern(List(28,22,-13,-12,4)).reduce(_&_) | pattern(List(4,2)).reduce(_&_) | + pattern(List(-25,-6,4)).reduce(_&_) | pattern(List(-5,4)).reduce(_&_) + io.out.presync := pattern(List(-5,3)).reduce(_&_) | pattern(List(-13,7,6,4)).reduce(_&_) | + pattern(List(-13,8,6,4)).reduce(_&_) | pattern(List(-13,9,6,4)).reduce(_&_) | + pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | + pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | + pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | + pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) + io.out.postsync := pattern(List(12,-5,3)).reduce(_&_) | pattern(List(-22,-13,-12,6,4)).reduce(_&_) | + pattern(List(-13,7,6,4)).reduce(_&_) | pattern(List(-13,8,6,4)).reduce(_&_) | + pattern(List(-13,9,6,4)).reduce(_&_) | pattern(List(-13,10,6,4)).reduce(_&_) | + pattern(List(-13,11,6,4)).reduce(_&_) | pattern(List(15,13,6,4)).reduce(_&_) | + pattern(List(16,13,6,4)).reduce(_&_) | pattern(List(17,13,6,4)).reduce(_&_) | + pattern(List(18,13,6,4)).reduce(_&_) | pattern(List(19,13,6,4)).reduce(_&_) + io.out.legal := pattern(List(-31,-30,29,28,-27,-26,-25,-24,-23,-22,21,-20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,28,-27,-26,-25,-24,-23,22,-21,20,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-19,-18,-17,-16,-15,-14,-11,-10,-9,-8,-7,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-6,4,-3,1,0)).reduce(_&_) | + pattern(List(-31,-29,-28,-27,-26,-25,-14,-13,-12,-6,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-29,-28,-27,-26,-25,14,-13,12,-6,4,-3,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-6,5,4,-3,1,0)).reduce(_&_) | + pattern(List(-14,-13,-12,6,5,-4,-3,1,0)).reduce(_&_) | + pattern(List(14,6,5,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-12,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-13,5,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(12,6,5,4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-27,-26,-25,-24,-23,-22,-21,-20,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(-31,-30,-29,-28,-19,-18,-17,-16,-15,-14,-13,-12,-11,-10,-9,-8,-7,-6,-5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(-13,-6,-5,-4,-3,-2,1,0)).reduce(_&_) | pattern(List(6,5,-4,3,2,1,0)).reduce(_&_) | + pattern(List(13,-6,-5,4,-3,1,0)).reduce(_&_) | pattern(List(-14,-12,-6,-4,-3,-2,1,0)).reduce(_&_) | + pattern(List(-6,4,-3,-2,1,0)).reduce(_&_) +} + +//object dec extends App { +// println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_dec_ctl())) +//} diff --git a/src/main/scala/dec/el2_dec_decode_ctl.scala b/src/main/scala/dec/el2_dec_decode_ctl.scala new file mode 100644 index 00000000..c23ddb0e --- /dev/null +++ b/src/main/scala/dec/el2_dec_decode_ctl.scala @@ -0,0 +1,829 @@ +package dec +import chisel3._ +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ + +class el2_dec_decode_ctl extends Module with el2_lib with RequireAsyncReset{ + val io = IO(new Bundle{ + + val dec_tlu_flush_extint = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) // invalidate nonblock load cam on a force halt event + val dec_extint_stall = Output(Bool()) + val ifu_i0_cinst = Input(UInt(16.W)) // 16b compressed instruction + val dec_i0_inst_wb1 = Output(UInt(32.W)) // 32b instruction at wb+1 for trace encoder + val dec_i0_pc_wb1 = Output(UInt(31.W)) // 31b pc at wb+1 for trace encoder + val lsu_nonblock_load_valid_m = Input(Bool()) // valid nonblock load at m + val lsu_nonblock_load_tag_m = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_inv_r = Input(Bool()) // invalidate request for nonblock load r + val lsu_nonblock_load_inv_tag_r = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data_valid = Input(Bool()) // valid nonblock load data back + val lsu_nonblock_load_data_error = Input(Bool()) // nonblock load bus error + val lsu_nonblock_load_data_tag = Input(UInt(LSU_NUM_NBLOAD_WIDTH.W)) // -> corresponding tag + val lsu_nonblock_load_data = Input(UInt(32.W)) // nonblock load data + val dec_i0_trigger_match_d = Input(UInt(4.W)) // i0 decode trigger matches + val dec_tlu_wr_pause_r = Input(Bool()) // pause instruction at r + val dec_tlu_pipelining_disable = Input(Bool()) // pipeline disable - presync, i0 decode only + val lsu_trigger_match_m = Input(UInt(4.W)) // lsu trigger matches + val lsu_pmu_misaligned_m = Input(Bool()) // perf mon: load/store misalign + val dec_tlu_debug_stall = Input(Bool()) // debug stall decode + val dec_tlu_flush_leak_one_r = Input(Bool()) // leak1 instruction + val dec_debug_fence_d = Input(Bool()) // debug fence instruction + val dbg_cmd_wrdata = Input(UInt(2.W)) // disambiguate fence, fence_i + val dec_i0_icaf_d = Input(Bool()) // icache access fault + val dec_i0_icaf_f1_d = Input(Bool()) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_icaf_type_d = Input(UInt(2.W)) // i0 instruction access fault type + val dec_i0_dbecc_d = Input(Bool()) // icache/iccm double-bit error + val dec_i0_brp = Input(new el2_br_pkt_t) // branch packet + val dec_i0_bp_index = Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr = Input(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag = Input(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_pc_d = Input(UInt(31.W)) // pc + val lsu_idle_any = Input(Bool()) // lsu idle: if fence instr & !!!!!!!!!!!!!!!!!!!!!!!!!lsu_idle then stall decode + val lsu_load_stall_any = Input(Bool()) // stall any load at decode + val lsu_store_stall_any = Input(Bool()) // stall any store at decode6 + val dma_dccm_stall_any = Input(Bool()) // stall any load/store at decode + val exu_div_wren = Input(Bool()) // nonblocking divide write enable to GPR. + val dec_tlu_i0_kill_writeb_wb = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Input(Bool()) // trap lower flush + val dec_tlu_i0_kill_writeb_r = Input(Bool()) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Input(Bool()) // trap lower flush + val dec_tlu_flush_pause_r = Input(Bool()) // don't clear pause state on initial lower flush + val dec_tlu_presync_d = Input(Bool()) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Input(Bool()) // CSR ops that need to be postsync'd + val dec_i0_pc4_d = Input(Bool()) // inst is 4B inst else 2B + val dec_csr_rddata_d = Input(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Input(Bool()) // csr indicates legal operation + val exu_csr_rs1_x = Input(UInt(32.W)) // rs1 for csr instr + val lsu_result_m = Input(UInt(32.W)) // load result + val lsu_result_corr_r = Input(UInt(32.W)) // load result - corrected data for writing gpr's, not for bypassing + val exu_flush_final = Input(Bool()) // lower flush or i0 flush at X or D + val exu_i0_pc_x = Input(UInt(31.W)) // pcs at e1 + val dec_i0_instr_d = Input(UInt(32.W)) // inst at decode + val dec_ib0_valid_d = Input(Bool()) // inst valid at decode + val exu_i0_result_x = Input(UInt(32.W)) // from primary alu's + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) // clk except for halt / pause + val clk_override = Input(Bool()) // test stuff + + val dec_i0_rs1_en_d = Output(Bool()) // rs1 enable at decode + val dec_i0_rs2_en_d = Output(Bool()) + val dec_i0_rs1_d = Output(UInt(5.W)) // rs1 logical source + val dec_i0_rs2_d = Output(UInt(5.W)) + val dec_i0_immed_d = Output(UInt(32.W)) // 32b immediate data decode + val dec_i0_br_immed_d = Output(UInt(12.W)) // 12b branch immediate + val i0_ap = Output(new el2_alu_pkt_t) // alu packets + val dec_i0_decode_d = Output(Bool()) // i0 decode + val dec_i0_alu_decode_d = Output(Bool()) // decode to D-stage alu + val dec_i0_rs1_bypass_data_d = Output(UInt(32.W)) // i0 rs1 bypass data + val dec_i0_rs2_bypass_data_d = Output(UInt(32.W)) // i0 rs2 bypass data + val dec_i0_waddr_r = Output(UInt(5.W)) // i0 logical source to write to gpr's + val dec_i0_wen_r = Output(Bool()) // i0 write enable + val dec_i0_wdata_r = Output(UInt(32.W)) // i0 write data + val dec_i0_select_pc_d = Output(Bool()) // i0 select pc for rs1 - branches + val dec_i0_rs1_bypass_en_d = Output(UInt(2.W)) // i0 rs1 bypass enable + val dec_i0_rs2_bypass_en_d = Output(UInt(2.W)) // i0 rs2 bypass enable + val lsu_p = Output(new el2_lsu_pkt_t) // load/store packet + val mul_p = Output(new el2_mul_pkt_t) // multiply packet + val div_p = Output(new el2_div_pkt_t) // divide packet + val div_waddr_wb = Output(UInt(5.W)) // DIV write address to GPR + val dec_div_cancel = Output(Bool()) // cancel the divide operation + val dec_lsu_valid_raw_d = Output(Bool()) + val dec_lsu_offset_d = Output(UInt(12.W)) + val dec_csr_ren_d = Output(Bool()) // valid csr decode + val dec_csr_wen_unq_d = Output(Bool()) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Output(Bool()) // valid csr - for csr legal + val dec_csr_rdaddr_d = Output(UInt(12.W)) // read address for csr + val dec_csr_wen_r = Output(Bool()) // csr write enable at r + val dec_csr_wraddr_r = Output(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Output(UInt(32.W)) // csr write data at r + val dec_csr_stall_int_ff = Output(Bool()) // csr is mie/mstatus + val dec_tlu_i0_valid_r = Output(Bool()) // i0 valid inst at c + val dec_tlu_packet_r = Output(new el2_trap_pkt_t) // trap packet + val dec_tlu_i0_pc_r = Output(UInt(31.W)) // i0 trap pc + val dec_illegal_inst = Output(UInt(32.W)) // illegal inst + val pred_correct_npc_x = Output(UInt(31.W)) // npc e2 if the prediction is correct + val dec_i0_predict_p_d = Output(new el2_predict_pkt_t) // i0 predict packet decode + val i0_predict_fghr_d = Output(UInt(BHT_GHR_SIZE.W)) // i0 predict fghr + val i0_predict_index_d = Output(UInt(((BHT_ADDR_HI-BHT_ADDR_LO)+1).W)) // i0 predict index + val i0_predict_btag_d = Output(UInt(BTB_BTAG_SIZE.W)) // i0_predict branch tag + val dec_data_en = Output(UInt(2.W)) // clock-gating logic + val dec_ctl_en = Output(UInt(2.W)) + val dec_pmu_instr_decoded = Output(Bool()) // number of instructions decode this cycle encoded + val dec_pmu_decode_stall = Output(Bool()) // decode is stalled + val dec_pmu_presync_stall = Output(Bool()) // decode has presync stall + val dec_pmu_postsync_stall = Output(Bool()) // decode has postsync stall + val dec_nonblock_load_wen = Output(Bool()) // write enable for nonblock load + val dec_nonblock_load_waddr = Output(UInt(5.W)) // logical write addr for nonblock load + val dec_pause_state = Output(Bool()) // core in pause state + val dec_pause_state_cg = Output(Bool()) // pause state for clock-gating + val dec_div_active = Output(Bool()) // non-block divide is active + val scan_mode = Input(Bool()) + }) + ///////////////////////////////////////////////////////////////////////////////////////// + // //packets zero initialization + io.mul_p := 0.U.asTypeOf(io.mul_p) + // Vals defined + val leak1_i1_stall_in = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall_in = WireInit(UInt(1.W), 0.U) + val i0r = Wire(new el2_reg_pkt_t) + val d_t = Wire(new el2_trap_pkt_t) + val x_t = Wire(new el2_trap_pkt_t) + val x_t_in = Wire(new el2_trap_pkt_t) + val r_t = Wire(new el2_trap_pkt_t) + val r_t_in = Wire(new el2_trap_pkt_t) + val d_d = Wire(new el2_dest_pkt_t) + val x_d = Wire(new el2_dest_pkt_t) + val r_d = Wire(new el2_dest_pkt_t) + val r_d_in = Wire(new el2_dest_pkt_t) + val wbd = Wire(new el2_dest_pkt_t) + val i0_d_c = Wire(new el2_class_pkt_t) + val i0_rs1_class_d = Wire(new el2_class_pkt_t) + val i0_rs2_class_d = Wire(new el2_class_pkt_t) + val i0_rs1_depth_d = WireInit(UInt(2.W),0.U) + val i0_rs2_depth_d = WireInit(UInt(2.W),0.U) + val cam_wen=WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val cam = Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + val cam_write=WireInit(UInt(1.W), 0.U) + val cam_inv_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_data_reset_val=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val nonblock_load_write=Wire(Vec(LSU_NUM_NBLOAD,UInt(1.W))) + val cam_raw =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + val cam_in =Wire(Vec(LSU_NUM_NBLOAD,new el2_load_cam_pkt_t)) + //val i0_temp = Wire(new el2_inst_pkt_t) + val i0_dp= Wire(new el2_dec_pkt_t) + val i0_dp_raw= Wire(new el2_dec_pkt_t) + val i0_rs1bypass = WireInit(UInt(3.W), 0.U) + val i0_rs2bypass = WireInit(UInt(3.W), 0.U) + val illegal_lockout = WireInit(UInt(1.W), 0.U) + val postsync_stall = WireInit(UInt(1.W), 0.U) + val ps_stall_in = WireInit(UInt(1.W), 0.U) + val i0_pipe_en = WireInit(UInt(4.W), 0.U) + val i0_load_block_d = WireInit(UInt(1.W), 0.U) + val load_ldst_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_d = WireInit(UInt(1.W), 0.U) + val store_data_bypass_m = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r1 = WireInit(UInt(1.W), 0.U) + val tlu_wr_pause_r2 = WireInit(UInt(1.W), 0.U) + val leak1_i1_stall = WireInit(UInt(1.W), 0.U) + val leak1_i0_stall = WireInit(UInt(1.W), 0.U) + val pause_state = WireInit(Bool(), 0.B) + val flush_final_r = WireInit(UInt(1.W), 0.U) + val illegal_lockout_in = WireInit(UInt(1.W), 0.U) + val lsu_idle = WireInit(Bool(), 0.B) + val pause_state_in = WireInit(Bool(), 0.B) + val leak1_mode = WireInit(UInt(1.W), 0.U) + val i0_pcall = WireInit(UInt(1.W), 0.U) + val i0_pja = WireInit(UInt(1.W), 0.U) + val i0_pret = WireInit(UInt(1.W), 0.U) + val i0_legal_decode_d = WireInit(UInt(1.W), 0.U) + val i0_pcall_raw = WireInit(UInt(1.W), 0.U) + val i0_pja_raw = WireInit(UInt(1.W), 0.U) + val i0_pret_raw = WireInit(UInt(1.W), 0.U) + val i0_br_offset = WireInit(UInt(12.W), 0.U) + val i0_csr_write_only_d = WireInit(UInt(1.W), 0.U) + val i0_jal = WireInit(UInt(1.W), 0.U) + val i0_wen_r = WireInit(UInt(1.W), 0.U) + val i0_x_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_r_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_wb_ctl_en = WireInit(UInt(1.W), 0.U) + val i0_x_data_en = WireInit(UInt(1.W), 0.U) + val i0_r_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb_data_en = WireInit(UInt(1.W), 0.U) + val i0_wb1_data_en = WireInit(UInt(1.W), 0.U) + val i0_nonblock_load_stall = WireInit(UInt(1.W), 0.U) + val csr_ren_qual_d = WireInit(Bool(), 0.B) + val lsu_decode_d = WireInit(UInt(1.W), 0.U) + val mul_decode_d = WireInit(UInt(1.W), 0.U) + val div_decode_d = WireInit(UInt(1.W), 0.U) + val write_csr_data = WireInit(UInt(32.W),0.U) + val i0_result_corr_r = WireInit(UInt(32.W),0.U) + val presync_stall = WireInit(UInt(1.W), 0.U) + val i0_nonblock_div_stall = WireInit(UInt(1.W), 0.U) + val debug_fence = WireInit(Bool(), 0.B) + val i0_immed_d = WireInit(UInt(32.W), 0.U) + val i0_result_x = WireInit(UInt(32.W), 0.U) + val i0_result_r = WireInit(UInt(32.W), 0.U) + ////////////////////////////////////////////////////////////////////// + // Start - Data gating {{ + + val data_gate_en = (io.dec_tlu_wr_pause_r ^ tlu_wr_pause_r1 ) | // replaces free_clk + (tlu_wr_pause_r1 ^ tlu_wr_pause_r2 ) | // replaces free_clk + (io.dec_tlu_flush_extint ^ io.dec_extint_stall) | + (leak1_i1_stall_in ^ leak1_i1_stall ) | // replaces free_clk + (leak1_i0_stall_in ^ leak1_i0_stall ) | // replaces free_clk + (pause_state_in ^ pause_state ) | // replaces free_clk + (ps_stall_in ^ postsync_stall ) | // replaces free_clk + (io.exu_flush_final ^ flush_final_r ) | // replaces free_clk + (illegal_lockout_in ^ illegal_lockout ) // replaces active_clk + + + val data_gated_cgc= Module(new rvclkhdr) + data_gated_cgc.io.en := data_gate_en + data_gated_cgc.io.scan_mode :=io.scan_mode + data_gated_cgc.io.clk :=clock + val data_gate_clk =data_gated_cgc.io.l1clk + + // End - Data gating }} + + val i0_brp_valid = io.dec_i0_brp.valid & !leak1_mode + io.dec_i0_predict_p_d.misp :=0.U + io.dec_i0_predict_p_d.ataken :=0.U + io.dec_i0_predict_p_d.boffset :=0.U + io.dec_i0_predict_p_d.pcall := i0_pcall // don't mark as pcall if branch error + io.dec_i0_predict_p_d.pja := i0_pja + io.dec_i0_predict_p_d.pret := i0_pret + io.dec_i0_predict_p_d.prett := io.dec_i0_brp.prett + io.dec_i0_predict_p_d.pc4 := io.dec_i0_pc4_d + io.dec_i0_predict_p_d.hist := io.dec_i0_brp.hist + io.dec_i0_predict_p_d.valid := i0_brp_valid & i0_legal_decode_d + val i0_notbr_error = i0_brp_valid & !(i0_dp_raw.condbr | i0_pcall_raw | i0_pja_raw | i0_pret_raw) + + // no toffset error for a pret + val i0_br_toffset_error = i0_brp_valid & io.dec_i0_brp.hist(1) & (io.dec_i0_brp.toffset =/= i0_br_offset) & !i0_pret_raw + val i0_ret_error = i0_brp_valid & io.dec_i0_brp.ret & !i0_pret_raw; + val i0_br_error = io.dec_i0_brp.br_error | i0_notbr_error | i0_br_toffset_error | i0_ret_error + io.dec_i0_predict_p_d.br_error := i0_br_error & i0_legal_decode_d & !leak1_mode + io.dec_i0_predict_p_d.br_start_error := io.dec_i0_brp.br_start_error & i0_legal_decode_d & !leak1_mode + io.i0_predict_index_d := io.dec_i0_bp_index + io.i0_predict_btag_d := io.dec_i0_bp_btag + val i0_br_error_all = (i0_br_error | io.dec_i0_brp.br_start_error) & !leak1_mode + io.dec_i0_predict_p_d.toffset := i0_br_offset + io.i0_predict_fghr_d := io.dec_i0_bp_fghr + io.dec_i0_predict_p_d.way := io.dec_i0_brp.way + // end + + // on br error turn anything into a nop + // on i0 instruction fetch access fault turn anything into a nop + // nop => alu rs1 imm12 rd lor + val i0_icaf_d = io.dec_i0_icaf_d | io.dec_i0_dbecc_d + + val i0_instr_error = i0_icaf_d; + i0_dp := i0_dp_raw + when((i0_br_error_all | i0_instr_error).asBool){ + i0_dp := 0.U.asTypeOf(i0_dp) + i0_dp.alu := 1.B + i0_dp.rs1 := 1.B + i0_dp.rs2 := 1.B + i0_dp.lor := 1.B + i0_dp.legal := 1.B + i0_dp.postsync := 1.B + } + + val i0 = io.dec_i0_instr_d + io.dec_i0_select_pc_d := i0_dp.pc; + + // branches that can be predicted + val i0_predict_br = i0_dp.condbr | i0_pcall | i0_pja | i0_pret; + + val i0_predict_nt = !(io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br + val i0_predict_t = (io.dec_i0_brp.hist(1) & i0_brp_valid) & i0_predict_br + val i0_ap_pc2 = !io.dec_i0_pc4_d + val i0_ap_pc4 = io.dec_i0_pc4_d + io.i0_ap.predict_nt := i0_predict_nt + io.i0_ap.predict_t := i0_predict_t + + io.i0_ap.add := i0_dp.add + io.i0_ap.sub := i0_dp.sub + io.i0_ap.land := i0_dp.land + io.i0_ap.lor := i0_dp.lor + io.i0_ap.lxor := i0_dp.lxor + io.i0_ap.sll := i0_dp.sll + io.i0_ap.srl := i0_dp.srl + io.i0_ap.sra := i0_dp.sra + io.i0_ap.slt := i0_dp.slt + io.i0_ap.unsign := i0_dp.unsign + io.i0_ap.beq := i0_dp.beq + io.i0_ap.bne := i0_dp.bne + io.i0_ap.blt := i0_dp.blt + io.i0_ap.bge := i0_dp.bge + io.i0_ap.csr_write := i0_csr_write_only_d + io.i0_ap.csr_imm := i0_dp.csr_imm + io.i0_ap.jal := i0_jal + + // non block load cam logic + // val found=Wire(UInt(1.W)) + cam_wen := Mux1H((0 until LSU_NUM_NBLOAD).map(i=>(0 to i).map(j=> if(i==j) !cam(j).valid else cam(j).valid).reduce(_.asBool&_.asBool).asBool -> (cam_write << i))) + + cam_write := io.lsu_nonblock_load_valid_m + val cam_write_tag = io.lsu_nonblock_load_tag_m(LSU_NUM_NBLOAD_WIDTH-1,0) + + val cam_inv_reset = io.lsu_nonblock_load_inv_r + val cam_inv_reset_tag = io.lsu_nonblock_load_inv_tag_r(LSU_NUM_NBLOAD_WIDTH-1,0) + + val cam_data_reset = io.lsu_nonblock_load_data_valid | io.lsu_nonblock_load_data_error + val cam_data_reset_tag = io.lsu_nonblock_load_data_tag(LSU_NUM_NBLOAD_WIDTH-1,0) + + val nonblock_load_rd = Mux(x_d.i0load.asBool, x_d.i0rd, 0.U(5.W)) // rd data + val load_data_tag = io.lsu_nonblock_load_data_tag + // case of multiple loads to same dest ie. x1 ... you have to invalidate the older one + // don't writeback a nonblock load + val nonblock_load_valid_m_delay=withClock(io.active_clk){RegEnable(io.lsu_nonblock_load_valid_m,0.U, i0_r_ctl_en.asBool)} + val i0_load_kill_wen_r = nonblock_load_valid_m_delay & r_d.i0load + for(i <- 0 until LSU_NUM_NBLOAD){ + cam_inv_reset_val(i) := cam_inv_reset & (cam_inv_reset_tag === cam(i).tag) & cam(i).valid + cam_data_reset_val(i) := cam_data_reset & (cam_data_reset_tag === cam(i).tag) & cam_raw(i).valid + cam_in(i):=0.U.asTypeOf(cam(0)) + cam(i):=cam_raw(i) + + when(cam_data_reset_val(i).asBool){ + cam(i).valid := 0.U(1.W) + } + when(cam_wen(i).asBool){ + cam_in(i).valid := 1.U(1.W) + cam_in(i).wb := 0.U(1.W) + cam_in(i).tag := cam_write_tag + cam_in(i).rd := nonblock_load_rd + }.elsewhen(cam_inv_reset_val(i).asBool || (i0_wen_r.asBool && (r_d_in.i0rd === cam(i).rd) && cam(i).wb.asBool)){ + cam_in(i).valid := 0.U + }.otherwise{ + cam_in(i) := cam(i) + } + when(nonblock_load_valid_m_delay===1.U && (io.lsu_nonblock_load_inv_tag_r === cam(i).tag) && cam(i).valid===1.U){ + cam_in(i).wb := 1.U + } + // force debug halt forces cam valids to 0; highest priority + when(io.dec_tlu_force_halt){ + cam_in(i).valid := 0.U + } + + cam_raw(i):=withClock(io.free_clk){RegNext(cam_in(i),0.U.asTypeOf(cam(0)))} + nonblock_load_write(i) := (load_data_tag === cam_raw(i).tag) & cam_raw(i).valid + } + + io.dec_nonblock_load_waddr:=0.U(5.W) + // cancel if any younger inst (including another nonblock) committing this cycle + val nonblock_load_cancel = ((r_d_in.i0rd === io.dec_nonblock_load_waddr) & i0_wen_r) + io.dec_nonblock_load_wen := (io.lsu_nonblock_load_data_valid && nonblock_load_write.reduce(_|_).asBool && !nonblock_load_cancel) + val i0_nonblock_boundary_stall = ((nonblock_load_rd===i0r.rs1) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs1_en_d)|((nonblock_load_rd===i0r.rs2) & io.lsu_nonblock_load_valid_m & io.dec_i0_rs2_en_d) + + i0_nonblock_load_stall := i0_nonblock_boundary_stall + + val cal_temp= for(i <-0 until LSU_NUM_NBLOAD) yield ((Fill(5,nonblock_load_write(i)) & cam(i).rd), io.dec_i0_rs1_en_d & cam(i).valid & (cam(i).rd === i0r.rs1), io.dec_i0_rs2_en_d & cam(i).valid & (cam(i).rd === i0r.rs2)) + val (waddr, ld_stall_1, ld_stall_2) = (cal_temp.map(_._1).reduce(_|_) , cal_temp.map(_._2).reduce(_|_), cal_temp.map(_._3).reduce(_|_) ) + io.dec_nonblock_load_waddr:=waddr + i0_nonblock_load_stall:=ld_stall_1 | ld_stall_2 | i0_nonblock_boundary_stall + //i0_nonblock_load_stall:=ld_stall_2 + + // end non block load cam logic + + // pmu start + + val csr_read = csr_ren_qual_d + val csr_write = io.dec_csr_wen_unq_d + val i0_br_unpred = i0_dp.jal & !i0_predict_br + + // the classes must be mutually exclusive with one another + import el2_inst_pkt_t._ + d_t.pmu_i0_itype :=Fill(4,i0_legal_decode_d) & MuxCase(NULL ,Array( + i0_dp.jal -> JAL, + i0_dp.condbr -> CONDBR, + i0_dp.mret -> MRET, + i0_dp.fence_i -> FENCEI, + i0_dp.fence -> FENCE, + i0_dp.ecall -> ECALL, + i0_dp.ebreak -> EBREAK, + ( csr_read & csr_write).asBool -> CSRRW, + (!csr_read & csr_write).asBool -> CSRWRITE, + ( csr_read & !csr_write).asBool -> CSRREAD, + i0_dp.pm_alu -> ALU, + i0_dp.store -> STORE, + i0_dp.load -> LOAD, + i0_dp.mul -> MUL)) + // end pmu + + val i0_dec =Module(new el2_dec_dec_ctl) + i0_dec.io.ins:= i0 + i0_dp_raw:=i0_dec.io.out + + lsu_idle:=withClock(io.active_clk){RegNext(io.lsu_idle_any,0.U)} + + // can't make this clock active_clock + leak1_i1_stall_in := (io.dec_tlu_flush_leak_one_r | (leak1_i1_stall & !io.dec_tlu_flush_lower_r)) + leak1_i1_stall := withClock(data_gate_clk){RegNext(leak1_i1_stall_in,0.U)} + leak1_mode := leak1_i1_stall + leak1_i0_stall_in := ((io.dec_i0_decode_d & leak1_i1_stall) | (leak1_i0_stall & !io.dec_tlu_flush_lower_r)) + leak1_i0_stall := withClock(data_gate_clk){RegNext(leak1_i0_stall_in,0.U)} + + // 12b jal's can be predicted - these are calls + + val i0_pcall_imm = Cat(i0(31),i0(19,12),i0(20),i0(30,21),0.U(1.W)) + val i0_pcall_12b_offset = Mux(i0_pcall_imm(12).asBool, i0_pcall_imm(20,13) === 0xff.U , i0_pcall_imm(20,13) === 0.U(8.W)) + val i0_pcall_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & (i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + val i0_pja_case = i0_pcall_12b_offset & i0_dp_raw.imm20 & !(i0r.rd === 1.U(5.W) | i0r.rd === 5.U(5.W)) + i0_pcall_raw := i0_dp_raw.jal & i0_pcall_case // this includes ja + i0_pcall := i0_dp.jal & i0_pcall_case + i0_pja_raw := i0_dp_raw.jal & i0_pja_case + i0_pja := i0_dp.jal & i0_pja_case + i0_br_offset := Mux((i0_pcall_raw | i0_pja_raw).asBool, i0_pcall_imm(12,1) , Cat(i0(31),i0(7),i0(30,25),i0(11,8))) + // jalr with rd==0, rs1==1 or rs1==5 is a ret + val i0_pret_case = (i0_dp_raw.jal & i0_dp_raw.imm12 & (i0r.rd === 0.U(5.W)) & (i0r.rs1===1.U(5.W) | i0r.rs1 === 5.U(5.W))) + i0_pret_raw := i0_dp_raw.jal & i0_pret_case + i0_pret := i0_dp.jal & i0_pret_case + i0_jal := i0_dp.jal & !i0_pcall_case & !i0_pja_case & !i0_pret_case + /////////////////////////////////////////////////////////////////////////////////////////////////////////// + + io.div_p.valid := div_decode_d + io.div_p.unsign := i0_dp.unsign + io.div_p.rem := i0_dp.rem + + io.mul_p.valid := mul_decode_d + io.mul_p.rs1_sign := i0_dp.rs1_sign + io.mul_p.rs2_sign := i0_dp.rs2_sign + io.mul_p.low := i0_dp.low + + io.dec_extint_stall := withClock(data_gate_clk){RegNext(io.dec_tlu_flush_extint,0.U)} + + io.lsu_p := 0.U.asTypeOf(io.lsu_p) + when (io.dec_extint_stall){ + io.lsu_p.load := 1.U(1.W) + io.lsu_p.word := 1.U(1.W) + io.lsu_p.fast_int := 1.U(1.W) + io.lsu_p.valid := 1.U(1.W) + }.otherwise { + io.lsu_p.valid := lsu_decode_d + io.lsu_p.load := i0_dp.load + io.lsu_p.store := i0_dp.store + io.lsu_p.by := i0_dp.by + io.lsu_p.half := i0_dp.half + io.lsu_p.word := i0_dp.word + io.lsu_p.load_ldst_bypass_d := load_ldst_bypass_d + io.lsu_p.store_data_bypass_d := store_data_bypass_d + io.lsu_p.store_data_bypass_m := store_data_bypass_m + io.lsu_p.unsign := i0_dp.unsign + } + + ////////////////////////////////////// + io.dec_csr_ren_d := i0_dp.csr_read //H: assigning csr read enable signal decoded from decode_ctl going as input to EXU + csr_ren_qual_d := i0_dp.csr_read & i0_legal_decode_d.asBool //csr_ren_qual_d assigned as csr_read above + + val i0_csr_write = i0_dp.csr_write & !io.dec_debug_fence_d + val csr_clr_d = i0_dp.csr_clr & i0_legal_decode_d.asBool + val csr_set_d = i0_dp.csr_set & i0_legal_decode_d.asBool + val csr_write_d = i0_csr_write & i0_legal_decode_d.asBool + + i0_csr_write_only_d := i0_csr_write & !i0_dp.csr_read + io.dec_csr_wen_unq_d := (i0_dp.csr_clr | i0_dp.csr_set | i0_csr_write) // for csr legal, can't write read-only csr + //dec_csr_wen_unq_d assigned as csr_write above + + io.dec_csr_rdaddr_d := i0(31,20) + io.dec_csr_wraddr_r := r_d.csrwaddr //r_d is a el2_dest_pkt + + // make sure csr doesn't write same cycle as dec_tlu_flush_lower_wb + // also use valid so it's flushable + io.dec_csr_wen_r := r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_r; + + // If we are writing MIE or MSTATUS, hold off the external interrupt for a cycle on the write. + io.dec_csr_stall_int_ff := ((r_d.csrwaddr === "h300".U) | (r_d.csrwaddr === "h304".U)) & r_d.csrwen & r_d.i0valid & !io.dec_tlu_i0_kill_writeb_wb; + + val csr_read_x = withClock(io.active_clk){RegNext(csr_ren_qual_d,init=0.B)} + val csr_clr_x = withClock(io.active_clk){RegNext(csr_clr_d, init=0.B)} + val csr_set_x = withClock(io.active_clk){RegNext(csr_set_d, init=0.B)} + val csr_write_x = withClock(io.active_clk){RegNext(csr_write_d, init=0.B)} + val csr_imm_x = withClock(io.active_clk){RegNext(i0_dp.csr_imm, init=0.U)} + + // perform the update operation if any + val csrimm_x = rvdffe(i0(19,15),i0_x_data_en.asBool,clock,io.scan_mode) + val csr_rddata_x = rvdffe(io.dec_csr_rddata_d,i0_x_data_en.asBool,clock,io.scan_mode) + + val csr_mask_x = Mux1H(Seq( + csr_imm_x.asBool -> Cat(repl(27,0.U),csrimm_x(4,0)), + !csr_imm_x.asBool -> io.exu_csr_rs1_x)) + + val write_csr_data_x = Mux1H(Seq( + csr_clr_x -> (csr_rddata_x & (~csr_mask_x).asUInt), + csr_set_x -> (csr_rddata_x | csr_mask_x), + csr_write_x -> ( csr_mask_x))) + // pause instruction + val clear_pause = (io.dec_tlu_flush_lower_r & !io.dec_tlu_flush_pause_r) | (pause_state & (write_csr_data === 0.U(31.W))) // if 0 or 1 then exit pause state - 1 cycle pause + pause_state_in := (io.dec_tlu_wr_pause_r | pause_state) & !clear_pause + pause_state := withClock(data_gate_clk){RegNext(pause_state_in, 0.U)} + io.dec_pause_state := pause_state + tlu_wr_pause_r1 := RegNext(io.dec_tlu_wr_pause_r, 0.U) + tlu_wr_pause_r2 := RegNext(tlu_wr_pause_r1, 0.U) + //pause for clock gating + io.dec_pause_state_cg := (pause_state & (!tlu_wr_pause_r1 && !tlu_wr_pause_r2)) + // end pause + + val write_csr_data_in = Mux(pause_state,(write_csr_data - 1.U(32.W)), + Mux(io.dec_tlu_wr_pause_r,io.dec_csr_wrdata_r,write_csr_data_x)) + val csr_data_wen = ((csr_clr_x | csr_set_x | csr_write_x) & csr_read_x) | io.dec_tlu_wr_pause_r | pause_state + write_csr_data := rvdffe(write_csr_data_in,csr_data_wen,clock,io.scan_mode) + + // will hold until write-back at which time the CSR will be updated while GPR is possibly written with prior CSR + val pause_stall = pause_state + + // for csr write only data is produced by the alu + io.dec_csr_wrdata_r := Mux(r_d.csrwonly.asBool,i0_result_corr_r,write_csr_data) + + val prior_csr_write = x_d.csrwonly | r_d.csrwonly | wbd.csrwonly; + + val debug_fence_i = io.dec_debug_fence_d & io.dbg_cmd_wrdata(0) + val debug_fence_raw = io.dec_debug_fence_d & io.dbg_cmd_wrdata(1) + debug_fence := debug_fence_raw | debug_fence_i + + // some CSR reads need to be presync'd + val i0_presync = i0_dp.presync | io.dec_tlu_presync_d | debug_fence_i | debug_fence_raw | io.dec_tlu_pipelining_disable // both fence's presync + + // some CSR writes need to be postsync'd + val i0_postsync = i0_dp.postsync | io.dec_tlu_postsync_d | debug_fence_i | (i0_csr_write_only_d & (i0(31,20) === "h7c2".U)) + + val any_csr_d = i0_dp.csr_read | i0_csr_write + io.dec_csr_any_unq_d := any_csr_d + val i0_legal = i0_dp.legal & (!any_csr_d | io.dec_csr_legal_d) + val i0_inst_d = Mux(io.dec_i0_pc4_d,i0,Cat(repl(16,0.U), io.ifu_i0_cinst)) + // illegal inst handling + + val shift_illegal = io.dec_i0_decode_d & !i0_legal//lm: valid but not legal + val illegal_inst_en = shift_illegal & !illegal_lockout + io.dec_illegal_inst := rvdffe(i0_inst_d,illegal_inst_en,clock,io.scan_mode) + illegal_lockout_in := (shift_illegal | illegal_lockout) & !flush_final_r + illegal_lockout := withClock(data_gate_clk){RegNext(illegal_lockout_in, 0.U)} + val i0_div_prior_div_stall = i0_dp.div & io.dec_div_active + //stalls signals + val i0_block_raw_d = (i0_dp.csr_read & prior_csr_write) | io.dec_extint_stall | pause_stall | + leak1_i0_stall | io.dec_tlu_debug_stall | postsync_stall | presync_stall | + ((i0_dp.fence | debug_fence) & !lsu_idle) | i0_nonblock_load_stall | + i0_load_block_d | i0_nonblock_div_stall | i0_div_prior_div_stall + + val i0_store_stall_d = i0_dp.store & (io.lsu_store_stall_any | io.dma_dccm_stall_any) + val i0_load_stall_d = i0_dp.load & (io.lsu_load_stall_any | io.dma_dccm_stall_any) + val i0_block_d = i0_block_raw_d | i0_store_stall_d | i0_load_stall_d + val i0_exublock_d = i0_block_raw_d + + //decode valid + io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exudecode_d = io.dec_ib0_valid_d & !i0_exublock_d & !io.dec_tlu_flush_lower_r & !flush_final_r + val i0_exulegal_decode_d = i0_exudecode_d & i0_legal + + // performance monitor signals + io.dec_pmu_instr_decoded := io.dec_i0_decode_d + io.dec_pmu_decode_stall := io.dec_ib0_valid_d & !io.dec_i0_decode_d + io.dec_pmu_postsync_stall := postsync_stall.asBool + io.dec_pmu_presync_stall := presync_stall.asBool + + val prior_inflight_x = x_d.i0valid + val prior_inflight_wb = r_d.i0valid + val prior_inflight = prior_inflight_x | prior_inflight_wb + val prior_inflight_eff = Mux(i0_dp.div,prior_inflight_x,prior_inflight) + + presync_stall := (i0_presync & prior_inflight_eff) + postsync_stall := withClock(data_gate_clk){RegNext(ps_stall_in, 0.U)} + // illegals will postsync + ps_stall_in := (io.dec_i0_decode_d & (i0_postsync | !i0_legal) ) | ( postsync_stall & prior_inflight_x) + + io.dec_i0_alu_decode_d := i0_exulegal_decode_d & i0_dp.alu + + lsu_decode_d := i0_legal_decode_d & i0_dp.lsu + mul_decode_d := i0_exulegal_decode_d & i0_dp.mul + div_decode_d := i0_exulegal_decode_d & i0_dp.div + + io.dec_tlu_i0_valid_r := r_d.i0valid & !io.dec_tlu_flush_lower_wb + + //traps for TLU (tlu stuff) + d_t.legal := i0_legal_decode_d + d_t.icaf := i0_icaf_d & i0_legal_decode_d // dbecc is icaf exception + d_t.icaf_f1 := io.dec_i0_icaf_f1_d & i0_legal_decode_d // this includes icaf and dbecc + d_t.icaf_type := io.dec_i0_icaf_type_d + + d_t.fence_i := (i0_dp.fence_i | debug_fence_i) & i0_legal_decode_d + + // put pmu info into the trap packet + d_t.pmu_i0_br_unpred := i0_br_unpred + d_t.pmu_divide := 0.U(1.W) + d_t.pmu_lsu_misaligned := 0.U(1.W) + + d_t.i0trigger := io.dec_i0_trigger_match_d & repl(4,io.dec_i0_decode_d) + + + x_t := rvdffe(d_t,i0_x_ctl_en.asBool,clock,io.scan_mode) + + x_t_in := x_t + x_t_in.i0trigger := x_t.i0trigger & ~(repl(4,io.dec_tlu_flush_lower_wb)) + + r_t := rvdffe(x_t_in,i0_x_ctl_en.asBool,clock,io.scan_mode) + val lsu_trigger_match_r = RegNext(io.lsu_trigger_match_m, 0.U) + val lsu_pmu_misaligned_r = RegNext(io.lsu_pmu_misaligned_m, 0.U) + + r_t_in := r_t + + r_t_in.i0trigger := (repl(4,(r_d.i0load | r_d.i0store)) & lsu_trigger_match_r) | r_t.i0trigger + r_t_in.pmu_lsu_misaligned := lsu_pmu_misaligned_r // only valid if a load/store is valid in DC3 stage + + when (io.dec_tlu_flush_lower_wb.asBool) {r_t_in := 0.U.asTypeOf(r_t_in) } + + io.dec_tlu_packet_r := r_t_in + io.dec_tlu_packet_r.pmu_divide := r_d.i0div & r_d.i0valid + // end tlu stuff + + flush_final_r := withClock(data_gate_clk){RegNext(io.exu_flush_final, 0.U)} + + io.dec_i0_decode_d := io.dec_ib0_valid_d & !i0_block_d & !io.dec_tlu_flush_lower_r & !flush_final_r + + i0r.rs1 := i0(19,15) //H: assigning reg packets the instructions bits + i0r.rs2 := i0(24,20) + i0r.rd := i0(11,7) + + io.dec_i0_rs1_en_d := i0_dp.rs1 & (i0r.rs1 =/= 0.U(5.W)) // if rs1_en=0 then read will be all 0's + io.dec_i0_rs2_en_d := i0_dp.rs2 & (i0r.rs2 =/= 0.U(5.W)) + val i0_rd_en_d = i0_dp.rd & (i0r.rd =/= 0.U(5.W)) + io.dec_i0_rs1_d := i0r.rs1//H:assiging packets to output signals leading to gprfile + io.dec_i0_rs2_d := i0r.rs2 + + val i0_jalimm20 = i0_dp.jal & i0_dp.imm20 // H:jal (used at line 915) + val i0_uiimm20 = !i0_dp.jal & i0_dp.imm20 + + io.dec_i0_immed_d := Mux1H(Seq( + i0_dp.csr_read -> io.dec_csr_rddata_d, + !i0_dp.csr_read -> i0_immed_d)) + + i0_immed_d := Mux1H(Seq( + i0_dp.imm12 -> Cat(repl(20,i0(31)),i0(31,20)), // jalr + i0_dp.shimm5 -> Cat(repl(27,0.U),i0(24,20)), + i0_jalimm20 -> Cat(repl(12,i0(31)),i0(19,12),i0(20),i0(30,21),0.U), + i0_uiimm20 -> Cat(i0(31,12),repl(12,0.U)), + (i0_csr_write_only_d & i0_dp.csr_imm).asBool -> Cat(repl(27,0.U),i0(19,15)))) // for csr's that only write + + i0_legal_decode_d := io.dec_i0_decode_d & i0_legal + + i0_d_c.mul := i0_dp.mul & i0_legal_decode_d + i0_d_c.load := i0_dp.load & i0_legal_decode_d + i0_d_c.alu := i0_dp.alu & i0_legal_decode_d + + val i0_x_c = withClock(io.active_clk){RegEnable(i0_d_c, i0_x_ctl_en.asBool)} + val i0_r_c = withClock(io.active_clk){RegEnable(i0_x_c, i0_r_ctl_en.asBool)} + i0_pipe_en := Cat(io.dec_i0_decode_d,withClock(io.active_clk){RegNext(i0_pipe_en(3,1), init=0.U)}) + + i0_x_ctl_en := (i0_pipe_en(3,2).orR | io.clk_override) + i0_r_ctl_en := (i0_pipe_en(2,1).orR | io.clk_override) + i0_wb_ctl_en := (i0_pipe_en(1,0).orR | io.clk_override) + i0_x_data_en := ( i0_pipe_en(3) | io.clk_override) + i0_r_data_en := ( i0_pipe_en(2) | io.clk_override) + i0_wb_data_en := ( i0_pipe_en(1) | io.clk_override) + i0_wb1_data_en := ( i0_pipe_en(0) | io.clk_override) + + io.dec_data_en := Cat(i0_x_data_en, i0_r_data_en) + io.dec_ctl_en := Cat(i0_x_ctl_en, i0_r_ctl_en) + + d_d.i0rd := i0r.rd + d_d.i0v := i0_rd_en_d & i0_legal_decode_d + d_d.i0valid := io.dec_i0_decode_d // has flush_final_r + + d_d.i0load := i0_dp.load & i0_legal_decode_d + d_d.i0store := i0_dp.store & i0_legal_decode_d + d_d.i0div := i0_dp.div & i0_legal_decode_d + + d_d.csrwen := io.dec_csr_wen_unq_d & i0_legal_decode_d + d_d.csrwonly := i0_csr_write_only_d & io.dec_i0_decode_d + d_d.csrwaddr := i0(31,20) + + x_d := rvdffe(d_d, i0_x_ctl_en.asBool,clock,io.scan_mode) + val x_d_in = Wire(new el2_dest_pkt_t) + x_d_in := x_d + x_d_in.i0v := x_d.i0v & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + x_d_in.i0valid := x_d.i0valid & !io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_lower_r + + r_d := rvdffe(x_d_in,i0_r_ctl_en.asBool,clock,io.scan_mode) + r_d_in := r_d + r_d_in.i0rd := r_d.i0rd + + r_d_in.i0v := (r_d.i0v & !io.dec_tlu_flush_lower_wb) + r_d_in.i0valid := (r_d.i0valid & !io.dec_tlu_flush_lower_wb) + r_d_in.i0load := r_d.i0load & !io.dec_tlu_flush_lower_wb + r_d_in.i0store := r_d.i0store & !io.dec_tlu_flush_lower_wb + + wbd := rvdffe(r_d_in,i0_wb_ctl_en.asBool,clock,io.scan_mode) + + io.dec_i0_waddr_r := r_d_in.i0rd + i0_wen_r := r_d_in.i0v & !io.dec_tlu_i0_kill_writeb_r + io.dec_i0_wen_r := i0_wen_r & !r_d_in.i0div & !i0_load_kill_wen_r // don't write a nonblock load 1st time down the pipe + io.dec_i0_wdata_r := i0_result_corr_r + + val i0_result_r_raw = rvdffe(i0_result_x,i0_r_data_en.asBool,clock,io.scan_mode) + if ( LOAD_TO_USE_PLUS1 == 1 ) { + i0_result_x := io.exu_i0_result_x + i0_result_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_m, i0_result_r_raw) + } + else { + i0_result_x := Mux((x_d.i0v & x_d.i0load).asBool,io.lsu_result_m,io.exu_i0_result_x) + i0_result_r := i0_result_r_raw + } + + // correct lsu load data - don't use for bypass, do pass down the pipe + i0_result_corr_r := Mux((r_d.i0v & r_d.i0load).asBool,io.lsu_result_corr_r,i0_result_r_raw) + io.dec_i0_br_immed_d := Mux((io.i0_ap.predict_nt & !i0_dp.jal).asBool,i0_br_offset,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2)) + val last_br_immed_d = WireInit(UInt(12.W),0.U) + last_br_immed_d := Mux((io.i0_ap.predict_nt).asBool,Cat(repl(10,0.U),i0_ap_pc4,i0_ap_pc2),i0_br_offset) + val last_br_immed_x = WireInit(UInt(12.W),0.U) + last_br_immed_x := rvdffe(last_br_immed_d,i0_x_data_en.asBool,clock,io.scan_mode) + + // divide stuff + + val div_e1_to_r = (x_d.i0div & x_d.i0valid) | (r_d.i0div & r_d.i0valid) + + val div_flush = (x_d.i0div & x_d.i0valid & (x_d.i0rd === 0.U(5.W))) | + (x_d.i0div & x_d.i0valid & io.dec_tlu_flush_lower_r ) | + (r_d.i0div & r_d.i0valid & io.dec_tlu_flush_lower_r & io.dec_tlu_i0_kill_writeb_r) + + // cancel if any younger inst committing this cycle to same dest as nonblock divide + + val nonblock_div_cancel = (io.dec_div_active & div_flush) | + (io.dec_div_active & !div_e1_to_r & (r_d.i0rd === io.div_waddr_wb) & i0_wen_r) + + io.dec_div_cancel := nonblock_div_cancel.asBool + val i0_div_decode_d = i0_legal_decode_d & i0_dp.div + + val div_active_in = i0_div_decode_d | (io.dec_div_active & !io.exu_div_wren & !nonblock_div_cancel) + + io.dec_div_active := withClock(io.free_clk){RegNext(div_active_in, 0.U)} + + // nonblocking div scheme + i0_nonblock_div_stall := (io.dec_i0_rs1_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs1)) | + (io.dec_i0_rs2_en_d & io.dec_div_active & (io.div_waddr_wb === i0r.rs2)) + + io.div_waddr_wb := RegEnable(i0r.rd,0.U,i0_div_decode_d.asBool) + ///div end + + //for tracing instruction + val i0_wb_en = i0_wb_data_en + val i0_wb1_en = i0_wb1_data_en + + val div_inst = rvdffe(i0_inst_d(24,7),i0_div_decode_d.asBool,clock,io.scan_mode) + val i0_inst_x = rvdffe(i0_inst_d,i0_x_data_en.asBool,clock,io.scan_mode) + val i0_inst_r = rvdffe(i0_inst_x,i0_r_data_en.asBool,clock,io.scan_mode) + val i0_inst_wb_in = i0_inst_r + val i0_inst_wb = rvdffe(i0_inst_wb_in,i0_wb_en.asBool,clock,io.scan_mode) + io.dec_i0_inst_wb1 := rvdffe(i0_inst_wb,i0_wb1_en.asBool,clock,io.scan_mode) + val i0_pc_wb = rvdffe(io.dec_tlu_i0_pc_r,i0_wb_en.asBool,clock,io.scan_mode) + + io.dec_i0_pc_wb1 := rvdffe(i0_pc_wb,i0_wb1_en.asBool,clock,io.scan_mode) + val dec_i0_pc_r = rvdffe(io.exu_i0_pc_x,i0_r_data_en.asBool,clock,io.scan_mode) + + io.dec_tlu_i0_pc_r := dec_i0_pc_r + + //end tracing + + val temp_pred_correct_npc_x = rvbradder(Cat(io.exu_i0_pc_x,0.U),Cat(last_br_immed_x,0.U)) + io.pred_correct_npc_x := temp_pred_correct_npc_x(31,1) + + // scheduling logic for primary alu's + + val i0_rs1_depend_i0_x = io.dec_i0_rs1_en_d & x_d.i0v & (x_d.i0rd === i0r.rs1) + val i0_rs1_depend_i0_r = io.dec_i0_rs1_en_d & r_d.i0v & (r_d.i0rd === i0r.rs1) + + val i0_rs2_depend_i0_x = io.dec_i0_rs2_en_d & x_d.i0v & (x_d.i0rd === i0r.rs2) + val i0_rs2_depend_i0_r = io.dec_i0_rs2_en_d & r_d.i0v & (r_d.i0rd === i0r.rs2) + // order the producers as follows: , i0_x, i0_r, i0_wb + i0_rs1_class_d := Mux(i0_rs1_depend_i0_x.asBool,i0_x_c,Mux(i0_rs1_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs1_class_d))) + i0_rs1_depth_d := Mux(i0_rs1_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs1_depend_i0_r.asBool, 2.U(2.W), 0.U)) + i0_rs2_class_d := Mux(i0_rs2_depend_i0_x.asBool,i0_x_c,Mux(i0_rs2_depend_i0_r.asBool, i0_r_c, 0.U.asTypeOf(i0_rs2_class_d))) + i0_rs2_depth_d := Mux(i0_rs2_depend_i0_x.asBool,1.U(2.W),Mux(i0_rs2_depend_i0_r.asBool, 2.U(2.W), 0.U)) + + // stores will bypass load data in the lsu pipe + if (LOAD_TO_USE_PLUS1 == 1) { + i0_load_block_d := (i0_rs1_class_d.load & i0_rs1_depth_d) | (i0_rs2_class_d.load & i0_rs2_depth_d(0) & !i0_dp.store) + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(1) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & (i0_rs2_depth_d(1) & i0_rs2_class_d.load) + store_data_bypass_m := i0_dp.store & (i0_rs2_depth_d(0) & i0_rs2_class_d.load) + } + else { + i0_load_block_d := 0.B + load_ldst_bypass_d := (i0_dp.load | i0_dp.store) & i0_rs1_depth_d(0) & i0_rs1_class_d.load + store_data_bypass_d := i0_dp.store & i0_rs2_depth_d(0) & i0_rs2_class_d.load + store_data_bypass_m := 0.B + } + // add nonblock load rs1/rs2 bypass cases + + val i0_rs1_nonblock_load_bypass_en_d = io.dec_i0_rs1_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs1) + + val i0_rs2_nonblock_load_bypass_en_d = io.dec_i0_rs2_en_d & io.dec_nonblock_load_wen & (io.dec_nonblock_load_waddr === i0r.rs2) + + // bit 2 is priority match, bit 0 lowest priority , i0_x, i0_r + i0_rs1bypass := Cat((i0_rs1_depth_d(0) &(i0_rs1_class_d.alu | i0_rs1_class_d.mul)),(i0_rs1_depth_d(0) & (i0_rs1_class_d.load)), (i0_rs1_depth_d(1) & (i0_rs1_class_d.alu | i0_rs1_class_d.mul | i0_rs1_class_d.load))) + + i0_rs2bypass := Cat((i0_rs2_depth_d(0) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul)),(i0_rs2_depth_d(0) & (i0_rs2_class_d.load)),(i0_rs2_depth_d(1) & (i0_rs2_class_d.alu | i0_rs2_class_d.mul | i0_rs2_class_d.load))) + + io.dec_i0_rs1_bypass_en_d := Cat(i0_rs1bypass(2),(i0_rs1bypass(1) | i0_rs1bypass(0) | (!i0_rs1bypass(2) & i0_rs1_nonblock_load_bypass_en_d))) + io.dec_i0_rs2_bypass_en_d := Cat(i0_rs2bypass(2),(i0_rs2bypass(1) | i0_rs2bypass(0) | (!i0_rs2bypass(2) & i0_rs2_nonblock_load_bypass_en_d))) + + io.dec_i0_rs1_bypass_data_d := Mux1H(Seq( + i0_rs1bypass(1).asBool -> io.lsu_result_m, + i0_rs1bypass(0).asBool -> i0_result_r, + (!i0_rs1bypass(1) & !i0_rs1bypass(0) & i0_rs1_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, + )) + io.dec_i0_rs2_bypass_data_d := Mux1H(Seq( + i0_rs2bypass(1).asBool -> io.lsu_result_m, + i0_rs2bypass(0).asBool -> i0_result_r, + (!i0_rs2bypass(1) & !i0_rs2bypass(0) & i0_rs2_nonblock_load_bypass_en_d).asBool -> io.lsu_nonblock_load_data, + )) + io.dec_lsu_valid_raw_d := ((io.dec_ib0_valid_d & (i0_dp_raw.load | i0_dp_raw.store) & !io.dma_dccm_stall_any & !i0_block_raw_d) | io.dec_extint_stall) + io.dec_lsu_offset_d := Mux1H(Seq( + (!io.dec_extint_stall & i0_dp.lsu & i0_dp.load).asBool -> i0(31,20), + (!io.dec_extint_stall & i0_dp.lsu & i0_dp.store).asBool -> Cat(i0(31,25),i0(11,7)))) +} + +object dec_decode extends App{ + println("Generating Verilog...") + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_dec_decode_ctl())) +} diff --git a/src/main/scala/dec/el2_dec_gpr_ctl.scala b/src/main/scala/dec/el2_dec_gpr_ctl.scala new file mode 100644 index 00000000..b37f7f0e --- /dev/null +++ b/src/main/scala/dec/el2_dec_gpr_ctl.scala @@ -0,0 +1,58 @@ +package dec +import chisel3._ +import scala.collection._ +import chisel3.util._ +import include._ +import lib._ + +class el2_dec_gpr_ctl extends Module with RequireAsyncReset with el2_lib { + val io =IO(new el2_dec_gpr_ctl_IO) + val w0v =Wire(Vec(32,UInt(1.W))) + val w1v =Wire(Vec(32,UInt(1.W))) + val w2v =Wire(Vec(32,UInt(1.W))) + val gpr_in =Wire(Vec(32,UInt(32.W))) + val gpr_out =Wire(Vec(32,UInt(32.W))) + val gpr_wr_en =Wire(UInt(32.W)) + w0v(0):=0.U + w1v(0):=0.U + w2v(0):=0.U + gpr_out(0):=0.U + gpr_in(0):=0.U + io.rd0:=0.U + io.rd1:=0.U + gpr_wr_en:= (w0v.reverse).reduceRight(Cat(_,_)) | (w1v.reverse).reduceRight(Cat(_,_)) | (w2v.reverse).reduceRight(Cat(_,_)) + // GPR Write logic + for (j <-1 until 32){ + w0v(j) := io.wen0 & (io.waddr0===j.asUInt) + w1v(j) := io.wen1 & (io.waddr1===j.asUInt) + w2v(j) := io.wen2 & (io.waddr2===j.asUInt) + gpr_in(j) := (Fill(32,w0v(j)) & io.wd0) | (Fill(32,w1v(j)) & io.wd1) | (Fill(32,w2v(j)) & io.wd2) + } + // GPR Write Enables for power savings + for (j <-1 until 32){ + gpr_out(j):=rvdffe(gpr_in(j),gpr_wr_en(j),clock,io.scan_mode) + } + // GPR Read logic + io.rd0:=Mux1H((1 until 32).map(i => (io.raddr0===i.U).asBool -> gpr_out(i))) + io.rd1:=Mux1H((1 until 32).map(i => (io.raddr1===i.U).asBool -> gpr_out(i))) +} + +class el2_dec_gpr_ctl_IO extends Bundle{ + val raddr0=Input(UInt(5.W)) // logical read addresses + val raddr1=Input(UInt(5.W)) + val wen0=Input(UInt(1.W)) // write enable + val waddr0=Input(UInt(5.W)) // write address + val wd0=Input(UInt(32.W)) // write data + val wen1=Input(UInt(1.W)) // write enable + val waddr1=Input(UInt(5.W)) // write address + val wd1=Input(UInt(32.W)) // write data + val wen2=Input(UInt(1.W)) // write enable + val waddr2=Input(UInt(5.W)) // write address + val wd2=Input(UInt(32.W)) // write data + val rd0=Output(UInt(32.W)) // read data + val rd1=Output(UInt(32.W)) + val scan_mode=Input(Bool()) +} +object gpr_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_gpr_ctl))) +} diff --git a/src/main/scala/dec/el2_dec_ib_ctl.scala b/src/main/scala/dec/el2_dec_ib_ctl.scala new file mode 100644 index 00000000..9cdd876d --- /dev/null +++ b/src/main/scala/dec/el2_dec_ib_ctl.scala @@ -0,0 +1,99 @@ +package dec +import include._ +import chisel3._ +import chisel3.util._ +import lib._ + +class el2_dec_ib_ctl_IO extends Bundle with param{ + val dbg_cmd_valid =Input(UInt(1.W)) // valid dbg cmd + val dbg_cmd_write =Input(UInt(1.W)) // dbg cmd is write + val dbg_cmd_type =Input(UInt(2.W)) // dbg type + val dbg_cmd_addr =Input(UInt(32.W)) // expand to 31:0 + val i0_brp =Input(new el2_br_pkt_t) // i0 branch packet from aligner + val ifu_i0_bp_index =Input(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // BP index(Changed size) + val ifu_i0_bp_fghr =Input(UInt((BHT_GHR_SIZE).W)) // BP FGHR + val ifu_i0_bp_btag =Input(UInt((BTB_BTAG_SIZE).W)) // BP tag + val ifu_i0_pc4 =Input(UInt(1.W)) // i0 is 4B inst else 2B + val ifu_i0_valid =Input(UInt(1.W)) // i0 valid from ifu + val ifu_i0_icaf =Input(UInt(1.W)) // i0 instruction access fault + val ifu_i0_icaf_type =Input(UInt(2.W)) // i0 instruction access fault type + val ifu_i0_icaf_f1 =Input(UInt(1.W)) // i0 has access fault on second fetch group + val ifu_i0_dbecc =Input(UInt(1.W)) // i0 double-bit error + val ifu_i0_instr =Input(UInt(32.W)) // i0 instruction from the aligner + val ifu_i0_pc =Input(UInt(31.W)) // i0 pc from the aligner + + val dec_ib0_valid_d =Output(UInt(1.W)) // ib0 valid + val dec_i0_icaf_type_d =Output(UInt(2.W)) // i0 instruction access fault type + val dec_i0_instr_d =Output(UInt(32.W)) // i0 inst at decode + val dec_i0_pc_d =Output(UInt(31.W)) // i0 pc at decode + val dec_i0_pc4_d =Output(UInt(1.W)) // i0 is 4B inst else 2B + val dec_i0_brp =Output(new el2_br_pkt_t) // i0 branch packet at decode + val dec_i0_bp_index =Output(UInt(((BTB_ADDR_HI-BTB_ADDR_LO)+1).W)) // i0 branch index + val dec_i0_bp_fghr =Output(UInt(BHT_GHR_SIZE.W)) // BP FGHR + val dec_i0_bp_btag =Output(UInt(BTB_BTAG_SIZE.W)) // BP tag + val dec_i0_icaf_d =Output(UInt(1.W)) // i0 instruction access fault at decode + val dec_i0_icaf_f1_d =Output(UInt(1.W)) // i0 instruction access fault at decode for f1 fetch group + val dec_i0_dbecc_d =Output(UInt(1.W)) // i0 double-bit error at decode + val dec_debug_wdata_rs1_d =Output(UInt(1.W)) // put debug write data onto rs1 source: machine is halted + val dec_debug_fence_d =Output(UInt(1.W)) // debug fence inst +} + +class el2_dec_ib_ctl extends Module with param{ + val io=IO(new el2_dec_ib_ctl_IO) + io.dec_i0_icaf_f1_d :=io.ifu_i0_icaf_f1 + io.dec_i0_dbecc_d :=io.ifu_i0_dbecc + io.dec_i0_icaf_d :=io.ifu_i0_icaf + io.dec_i0_pc_d :=io.ifu_i0_pc + io.dec_i0_pc4_d :=io.ifu_i0_pc4 + io.dec_i0_icaf_type_d :=io.ifu_i0_icaf_type + io.dec_i0_brp :=io.i0_brp + io.dec_i0_bp_index :=io.ifu_i0_bp_index + io.dec_i0_bp_fghr :=io.ifu_i0_bp_fghr + io.dec_i0_bp_btag :=io.ifu_i0_bp_btag + + // GPR accesses + // put reg to read on rs1 + // read -> or %x0, %reg,%x0 {000000000000,reg[4:0],110000000110011} + // put write date on rs1 + // write -> or %reg, %x0, %x0 {00000000000000000110,reg[4:0],0110011} + // CSR accesses + // csr is of form rd, csr, rs1 + // read -> csrrs %x0, %csr, %x0 {csr[11:0],00000010000001110011} + // put write data on rs1 + // write -> csrrw %x0, %csr, %x0 {csr[11:0],00000001000001110011} + + + val debug_valid =io.dbg_cmd_valid & (io.dbg_cmd_type =/= 2.U) + val debug_read =debug_valid & !io.dbg_cmd_write + val debug_write =debug_valid & io.dbg_cmd_write + + val debug_read_gpr = debug_read & (io.dbg_cmd_type===0.U) + val debug_write_gpr = debug_write & (io.dbg_cmd_type===0.U) + val debug_read_csr = debug_read & (io.dbg_cmd_type===1.U) + val debug_write_csr = debug_write & (io.dbg_cmd_type===1.U) + + val dreg = io.dbg_cmd_addr(4,0) + val dcsr = io.dbg_cmd_addr(11,0) + + val ib0_debug_in =Mux1H(Seq( + debug_read_gpr.asBool -> Cat(Fill(12,0.U(1.W)),dreg,"b110000000110011".U), + debug_write_gpr.asBool -> Cat("b00000000000000000110".U(20.W),dreg,"b0110011".U(7.W)), + debug_read_csr.asBool -> Cat(dcsr,"b00000010000001110011".U(20.W)), + debug_write_csr.asBool -> Cat(dcsr,"b00000001000001110011".U(20.W)) + )) + + // machine is in halted state, pipe empty, write will always happen next cycle + io.dec_debug_wdata_rs1_d := debug_write_gpr | debug_write_csr + + // special fence csr for use only in debug mode + io.dec_debug_fence_d := debug_write_csr & (dcsr === 0x7C4.U) + + io.dec_ib0_valid_d := io.ifu_i0_valid | debug_valid + io.dec_i0_instr_d := Mux(debug_valid.asBool,ib0_debug_in,io.ifu_i0_instr) + + +} + +object ib_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_ib_ctl))) +} diff --git a/src/main/scala/dec/el2_dec_tlu_ctl.scala b/src/main/scala/dec/el2_dec_tlu_ctl.scala new file mode 100644 index 00000000..6b64dc16 --- /dev/null +++ b/src/main/scala/dec/el2_dec_tlu_ctl.scala @@ -0,0 +1,2872 @@ +package dec +import chisel3._ +import chisel3.util._ +import lib._ +import include._ +import el2_inst_pkt_t._ +//import lib.beh_ib_func._ +trait CSR_VAL { + + val MSTATUS_MIE =0 + val MIP_MCEIP =5 + val MIP_MITIP0 =4 + val MIP_MITIP1 =3 + val MIP_MEIP =2 + val MIP_MTIP =1 + val MIP_MSIP =0 + + val MIE_MCEIE =5 + val MIE_MITIE0 =4 + val MIE_MITIE1 =3 + val MIE_MEIE =2 + val MIE_MTIE =1 + val MIE_MSIE =0 + + val DCSR_EBREAKM =15 + val DCSR_STEPIE =11 + val DCSR_STOPC =10 + val DCSR_STEP =2 + + val MTDATA1_DMODE =9 + val MTDATA1_SEL =7 + val MTDATA1_ACTION =6 + val MTDATA1_CHAIN =5 + val MTDATA1_MATCH =4 + val MTDATA1_M_ENABLED =3 + val MTDATA1_EXE =2 + val MTDATA1_ST =1 + val MTDATA1_LD =0 + + +} +class el2_dec_tlu_ctl_IO extends Bundle with el2_lib { + + val active_clk = Input(Clock()) + val free_clk = Input(Clock()) + //val rst_l = Input(Bool()) + val scan_mode = Input(Bool()) + + val rst_vec = Input(UInt(31.W)) // reset vector, from core pins + val nmi_int = Input(UInt(1.W)) // nmi pin + val nmi_vec = Input(UInt(31.W)) // nmi vector + val i_cpu_halt_req = Input(UInt(1.W)) // Asynchronous Halt request to CPU + val i_cpu_run_req = Input(UInt(1.W)) // Asynchronous Restart request to CPU + + val lsu_fastint_stall_any = Input(UInt(1.W)) // needed by lsu for 2nd pass of dma with ecc correction, stall next cycle + + + // perf counter inputs + val ifu_pmu_instr_aligned = Input(UInt(1.W))// aligned instructions + val ifu_pmu_fetch_stall = Input(UInt(1.W))// fetch unit stalled + val ifu_pmu_ic_miss = Input(UInt(1.W))// icache miss + val ifu_pmu_ic_hit = Input(UInt(1.W))// icache hit + val ifu_pmu_bus_error = Input(UInt(1.W))// Instruction side bus error + val ifu_pmu_bus_busy = Input(UInt(1.W))// Instruction side bus busy + val ifu_pmu_bus_trxn = Input(UInt(1.W))// Instruction side bus transaction + val dec_pmu_instr_decoded = Input(UInt(1.W))// decoded instructions + val dec_pmu_decode_stall = Input(UInt(1.W))// decode stall + val dec_pmu_presync_stall = Input(UInt(1.W))// decode stall due to presync'd inst + val dec_pmu_postsync_stall = Input(UInt(1.W))// decode stall due to postsync'd inst + val lsu_store_stall_any = Input(UInt(1.W))// SB or WB is full, stall decode + val dma_dccm_stall_any = Input(UInt(1.W))// DMA stall of lsu + val dma_iccm_stall_any = Input(UInt(1.W))// DMA stall of ifu + val exu_pmu_i0_br_misp = Input(UInt(1.W))// pipe 0 branch misp + val exu_pmu_i0_br_ataken = Input(UInt(1.W))// pipe 0 branch actual taken + val exu_pmu_i0_pc4 = Input(UInt(1.W))// pipe 0 4 byte branch + val lsu_pmu_bus_trxn = Input(UInt(1.W))// D side bus transaction + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) // D side bus misaligned + val lsu_pmu_bus_error = Input(UInt(1.W)) // D side bus error + val lsu_pmu_bus_busy = Input(UInt(1.W)) // D side bus busy + val lsu_pmu_load_external_m = Input(UInt(1.W)) // D side bus load + val lsu_pmu_store_external_m= Input(UInt(1.W)) // D side bus store + val dma_pmu_dccm_read = Input(UInt(1.W)) // DMA DCCM read + val dma_pmu_dccm_write = Input(UInt(1.W)) // DMA DCCM write + val dma_pmu_any_read = Input(UInt(1.W)) // DMA read + val dma_pmu_any_write = Input(UInt(1.W)) // DMA write + + val lsu_fir_addr = Input(UInt(31.W)) // Fast int address + val lsu_fir_error = Input(UInt(2.W)) // Fast int lookup error + + val iccm_dma_sb_error = Input(UInt(1.W)) // I side dma single bit error + + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t)// lsu precise exception/error packet + val lsu_single_ecc_error_incr = Input(UInt(1.W)) // LSU inc SB error counter + + val dec_pause_state = Input(UInt(1.W)) // Pause counter not zero + val lsu_imprecise_error_store_any = Input(UInt(1.W)) // store bus error + val lsu_imprecise_error_load_any = Input(UInt(1.W)) // store bus error + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) // store bus error address + + val dec_csr_wen_unq_d = Input(UInt(1.W)) // valid csr with write - for csr legal + val dec_csr_any_unq_d = Input(UInt(1.W)) // valid csr - for csr legal + val dec_csr_rdaddr_d = Input(UInt(12.W)) // read address for csr + + val dec_csr_wen_r = Input(UInt(1.W)) // csr write enable at wb + val dec_csr_wraddr_r = Input(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r = Input(UInt(32.W)) // csr write data at wb + + val dec_csr_stall_int_ff = Input(UInt(1.W)) // csr is mie/mstatus + + val dec_tlu_i0_valid_r = Input(UInt(1.W)) // pipe 0 op at e4 is valid + + val exu_npc_r = Input(UInt(31.W)) // for NPC tracking + + val dec_tlu_i0_pc_r = Input(UInt(31.W)) // for PC/NPC tracking + + val dec_tlu_packet_r = Input(new el2_trap_pkt_t) // exceptions known at decode + + val dec_illegal_inst = Input(UInt(32.W)) // For mtval + val dec_i0_decode_d = Input(UInt(1.W)) // decode valid, used for clean icache diagnostics + + // branch info from pipe0 for errors or counter updates + val exu_i0_br_hist_r = Input(UInt(2.W)) // history + val exu_i0_br_error_r = Input(UInt(1.W)) // error + val exu_i0_br_start_error_r = Input(UInt(1.W)) // start error + val exu_i0_br_valid_r = Input(UInt(1.W)) // valid + val exu_i0_br_mp_r = Input(UInt(1.W)) // mispredict + val exu_i0_br_middle_r = Input(UInt(1.W)) // middle of bank + + // branch info from pipe1 for errors or counter updates + + val exu_i0_br_way_r = Input(UInt(1.W))// way hit or repl + + // Debug start + val dec_dbg_cmd_done = Output(UInt(1.W)) // abstract command done + val dec_dbg_cmd_fail = Output(UInt(1.W)) // abstract command failed + val dec_tlu_dbg_halted = Output(UInt(1.W)) // Core is halted and ready for debug command + val dec_tlu_debug_mode = Output(UInt(1.W)) // Core is in debug mode + val dec_tlu_resume_ack = Output(UInt(1.W)) // Resume acknowledge + val dec_tlu_debug_stall = Output(UInt(1.W)) // stall decode while waiting on core to empty + + val dec_tlu_flush_noredir_r = Output(UInt(1.W)) // Tell fetch to idle on this flush + val dec_tlu_mpc_halted_only = Output(UInt(1.W)) // Core is halted only due to MPC + val dec_tlu_flush_leak_one_r = Output(UInt(1.W)) // single step + val dec_tlu_flush_err_r = Output(UInt(1.W)) // iside perr/ecc rfpc. This is the D stage of the error + + val dec_tlu_flush_extint = Output(UInt(1.W)) // fast ext int started + val dec_tlu_meihap = Output(UInt(30.W)) // meihap for fast int + + val dbg_halt_req = Input(UInt(1.W)) // DM requests a halt + val dbg_resume_req = Input(UInt(1.W)) // DM requests a resume + val ifu_miss_state_idle = Input(UInt(1.W)) // I-side miss buffer empty + val lsu_idle_any = Input(UInt(1.W)) // lsu is idle + val dec_div_active = Input(UInt(1.W)) // oop div is active + val trigger_pkt_any = Output(Vec(4,new el2_trigger_pkt_t))// trigger info for trigger blocks + + val ifu_ic_error_start = Input(UInt(1.W)) // IC single bit error + val ifu_iccm_rd_ecc_single_err = Input(UInt(1.W)) // ICCM single bit error + + + val ifu_ic_debug_rd_data = Input(UInt(71.W)) // diagnostic icache read data + val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) // diagnostic icache read data valid + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics + // Debug end + + val pic_claimid = Input(UInt(8.W)) // pic claimid for csr + val pic_pl = Input(UInt(4.W)) // pic priv level for csr + val mhwakeup = Input(UInt(1.W)) // high priority external int, wakeup if halted + + val mexintpend= Input(UInt(1.W)) // external interrupt pending + val timer_int= Input(UInt(1.W)) // timer interrupt pending + val soft_int= Input(UInt(1.W)) // software interrupt pending + + val o_cpu_halt_status = Output(UInt(1.W)) // PMU interface, halted + val o_cpu_halt_ack = Output(UInt(1.W)) // halt req ack + val o_cpu_run_ack = Output(UInt(1.W)) // run req ack + val o_debug_mode_status = Output(UInt(1.W)) // Core to the PMU that core is in debug mode. When core is in debug mode, the PMU should refrain from sendng a halt or run request + + val core_id = Input(UInt(28.W)) // Core ID + + // external MPC halt/run interface + val mpc_debug_halt_req = Input(UInt(1.W)) // Async halt request + val mpc_debug_run_req = Input(UInt(1.W)) // Async run request + val mpc_reset_run_req = Input(UInt(1.W)) // Run/halt after reset + val mpc_debug_halt_ack = Output(UInt(1.W)) // Halt ack + val mpc_debug_run_ack = Output(UInt(1.W)) // Run ack + val debug_brkpt_status = Output(UInt(1.W)) // debug breakpoint + val dec_tlu_meicurpl = Output(UInt(4.W)) // to PIC + val dec_tlu_meipt = Output(UInt(4.W)) // to PIC + val dec_csr_rddata_d = Output(UInt(32.W)) // csr read data at wb + val dec_csr_legal_d = Output(UInt(1.W)) // csr indicates legal operation + val dec_tlu_br0_r_pkt = Output(new el2_br_tlu_pkt_t) // branch pkt to bp + val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_wb = Output(UInt(1.W)) // commit has a flush (exception, int, mispredict at e4) + val dec_tlu_i0_commit_cmt = Output(UInt(1.W)) // committed an instruction + val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) // I0 is flushed, don't writeback any results to arch state + val dec_tlu_flush_lower_r = Output(UInt(1.W)) // commit has a flush (exception, int) + val dec_tlu_flush_path_r = Output(UInt(31.W)) // flush pc + val dec_tlu_fence_i_r = Output(UInt(1.W)) // flush is a fence_i rfnpc, flush icache + val dec_tlu_wr_pause_r = Output(UInt(1.W)) // CSR write to pause reg is at R. + val dec_tlu_flush_pause_r = Output(UInt(1.W)) // Flush is due to pause + val dec_tlu_presync_d = Output(UInt(1.W)) // CSR read needs to be presync'd + val dec_tlu_postsync_d = Output(UInt(1.W)) // CSR needs to be presync'd + val dec_tlu_mrac_ff = Output(UInt(32.W)) // CSR for memory region control + val dec_tlu_force_halt = Output(UInt(1.W)) // halt has been forced + val dec_tlu_perfcnt0 = Output(UInt(1.W)) // toggles when pipe0 perf counter 0 has an event inc + val dec_tlu_perfcnt1 = Output(UInt(1.W)) // toggles when pipe0 perf counter 1 has an event inc + val dec_tlu_perfcnt2 = Output(UInt(1.W)) // toggles when pipe0 perf counter 2 has an event inc + val dec_tlu_perfcnt3 = Output(UInt(1.W)) // toggles when pipe0 perf counter 3 has an event inc + val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) // pipe 0 exception valid + val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) // pipe 0 valid + val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) // pipe 2 int valid + val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) // exception or int cause + val dec_tlu_mtval_wb1 = Output(UInt(32.W)) // MTVAL value + + // feature disable from mfdc + val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) // disable external load forwarding + val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) // disable posted stores to side-effect address + val dec_tlu_core_ecc_disable = Output(UInt(1.W)) // disable core ECC + val dec_tlu_bpred_disable = Output(UInt(1.W)) // disable branch prediction + val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) // disable writebuffer coalescing + val dec_tlu_pipelining_disable = Output(UInt(1.W)) // disable pipelining + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) // DMA QoS priority coming from MFDC [18:16] + + // clock gating overrides from mcgc + val dec_tlu_misc_clk_override = Output(UInt(1.W)) // override misc clock domain gating + val dec_tlu_dec_clk_override = Output(UInt(1.W)) // override decode clock domain gating + val dec_tlu_ifu_clk_override = Output(UInt(1.W)) // override fetch clock domain gating + val dec_tlu_lsu_clk_override = Output(UInt(1.W)) // override load/store clock domain gating + val dec_tlu_bus_clk_override = Output(UInt(1.W)) // override bus clock domain gating + val dec_tlu_pic_clk_override = Output(UInt(1.W)) // override PIC clock domain gating + val dec_tlu_dccm_clk_override = Output(UInt(1.W)) // override DCCM clock domain gating + val dec_tlu_icm_clk_override = Output(UInt(1.W)) // override ICCM clock domain gating +} +class el2_dec_tlu_ctl extends Module with el2_lib with RequireAsyncReset with CSR_VAL{ + val io = IO(new el2_dec_tlu_ctl_IO) + val mtdata1_t = Wire(Vec(4,UInt(10.W))) + val pause_expired_wb =Wire(UInt(1.W)) + val take_nmi_r_d1 =Wire(UInt(1.W)) + val exc_or_int_valid_r_d1 =Wire(UInt(1.W)) + val interrupt_valid_r_d1 =Wire(UInt(1.W)) + val tlu_flush_lower_r =Wire(UInt(1.W)) + val synchronous_flush_r =Wire(UInt(1.W)) + val interrupt_valid_r =Wire(UInt(1.W)) + val take_nmi =Wire(UInt(1.W)) + val take_reset =Wire(UInt(1.W)) + val take_int_timer1_int =Wire(UInt(1.W)) + val take_int_timer0_int =Wire(UInt(1.W)) + val take_timer_int =Wire(UInt(1.W)) + val take_soft_int =Wire(UInt(1.W)) + val take_ce_int =Wire(UInt(1.W)) + val take_ext_int_start =Wire(UInt(1.W)) + val ext_int_freeze =Wire(UInt(1.W)) + val ext_int_freeze_d1 =Wire(UInt(1.W)) + val take_ext_int_start_d1 =Wire(UInt(1.W)) + val take_ext_int_start_d2 =Wire(UInt(1.W)) + val take_ext_int_start_d3 =Wire(UInt(1.W)) + val fast_int_meicpct =Wire(UInt(1.W)) + val ignore_ext_int_due_to_lsu_stall =Wire(UInt(1.W)) + val take_ext_int =Wire(UInt(1.W)) + val internal_dbg_halt_timers =Wire(UInt(1.W)) + val int_timer1_int_hold =Wire(UInt(1.W)) + val int_timer0_int_hold =Wire(UInt(1.W)) + val mhwakeup_ready =Wire(UInt(1.W)) + val ext_int_ready =Wire(UInt(1.W)) + val ce_int_ready =Wire(UInt(1.W)) + val soft_int_ready =Wire(UInt(1.W)) + val timer_int_ready =Wire(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 =Wire(UInt(1.W)) + val ebreak_to_debug_mode_r =Wire(UInt(1.W)) + val inst_acc_r =Wire(UInt(1.W)) + val inst_acc_r_raw =Wire(UInt(1.W)) + val iccm_sbecc_r =Wire(UInt(1.W)) + val ic_perr_r =Wire(UInt(1.W)) + val fence_i_r =Wire(UInt(1.W)) + val ebreak_r =Wire(UInt(1.W)) + val ecall_r =Wire(UInt(1.W)) + val illegal_r =Wire(UInt(1.W)) + val mret_r =Wire(UInt(1.W)) + val iccm_repair_state_ns =Wire(UInt(1.W)) + val rfpc_i0_r =Wire(UInt(1.W)) + val tlu_i0_kill_writeb_r =Wire(UInt(1.W)) + val lsu_exc_valid_r_d1 =Wire(UInt(1.W)) + val lsu_i0_exc_r_raw =Wire(UInt(1.W)) + val mdseac_locked_f =Wire(UInt(1.W)) + val i_cpu_run_req_d1 =Wire(UInt(1.W)) + val cpu_run_ack =Wire(UInt(1.W)) + val cpu_halt_status =Wire(UInt(1.W)) + val cpu_halt_ack =Wire(UInt(1.W)) + val pmu_fw_tlu_halted =Wire(UInt(1.W)) + val internal_pmu_fw_halt_mode =Wire(UInt(1.W)) + val pmu_fw_halt_req_ns =Wire(UInt(1.W)) + val pmu_fw_halt_req_f =Wire(UInt(1.W)) + val pmu_fw_tlu_halted_f =Wire(UInt(1.W)) + val int_timer0_int_hold_f =Wire(UInt(1.W)) + val int_timer1_int_hold_f =Wire(UInt(1.W)) + val trigger_hit_dmode_r =Wire(UInt(1.W)) + val i0_trigger_hit_r =Wire(UInt(1.W)) + val pause_expired_r =Wire(UInt(1.W)) + val dec_tlu_pmu_fw_halted =Wire(UInt(1.W)) + val dec_tlu_flush_noredir_r_d1 =Wire(UInt(1.W)) + val halt_taken_f =Wire(UInt(1.W)) + val lsu_idle_any_f =Wire(UInt(1.W)) + val ifu_miss_state_idle_f =Wire(UInt(1.W)) + val dbg_tlu_halted_f =Wire(UInt(1.W)) + val debug_halt_req_f =Wire(UInt(1.W)) + val debug_resume_req_f =Wire(UInt(1.W)) + val trigger_hit_dmode_r_d1 =Wire(UInt(1.W)) + val dcsr_single_step_done_f =Wire(UInt(1.W)) + val debug_halt_req_d1 =Wire(UInt(1.W)) + val request_debug_mode_r_d1 =Wire(UInt(1.W)) + val request_debug_mode_done_f =Wire(UInt(1.W)) + val dcsr_single_step_running_f =Wire(UInt(1.W)) + val dec_tlu_flush_pause_r_d1 =Wire(UInt(1.W)) + val dbg_halt_req_held =Wire(UInt(1.W)) + val debug_halt_req_ns =Wire(UInt(1.W)) + val internal_dbg_halt_mode =Wire(UInt(1.W)) + val core_empty =Wire(UInt(1.W)) + val dbg_halt_req_final =Wire(UInt(1.W)) + val debug_brkpt_status_ns =Wire(UInt(1.W)) + val mpc_debug_halt_ack_ns =Wire(UInt(1.W)) + val mpc_debug_run_ack_ns =Wire(UInt(1.W)) + val mpc_halt_state_ns =Wire(UInt(1.W)) + val mpc_run_state_ns =Wire(UInt(1.W)) + val dbg_halt_state_ns =Wire(UInt(1.W)) + val dbg_run_state_ns =Wire(UInt(1.W)) + val dbg_halt_state_f =Wire(UInt(1.W)) + val mpc_halt_state_f =Wire(UInt(1.W)) + val nmi_int_detected =Wire(UInt(1.W)) + val nmi_lsu_load_type =Wire(UInt(1.W)) + val nmi_lsu_store_type =Wire(UInt(1.W)) + val reset_delayed =Wire(UInt(1.W)) + val internal_dbg_halt_mode_f =Wire(UInt(1.W)) + val e5_valid =Wire(UInt(1.W)) + val ic_perr_r_d1 =Wire(UInt(1.W)) + val iccm_sbecc_r_d1 =Wire(UInt(1.W)) + + val npc_r = Wire(UInt(31.W)) + val npc_r_d1 = Wire(UInt(31.W)) + val mie_ns = Wire(UInt(6.W)) + val mepc = Wire(UInt(31.W)) + val mdseac_locked_ns = Wire(UInt(1.W)) + val force_halt = Wire(UInt(1.W)) + val dpc = Wire(UInt(31.W)) + val mstatus_mie_ns = Wire(UInt(1.W)) + val dec_csr_wen_r_mod = Wire(UInt(1.W)) + val fw_halt_req = Wire(UInt(1.W)) + val mstatus = Wire(UInt(2.W)) + val dcsr = Wire(UInt(16.W)) + val mtvec = Wire(UInt(31.W)) + val mip = Wire(UInt(6.W)) + val csr_pkt = Wire(new el2_dec_tlu_csr_pkt) + val dec_tlu_mpc_halted_only_ns = Wire(UInt(1.W)) + // tell dbg we are only MPC halted + dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f + val int_timers=Module(new el2_dec_timer_ctl) + int_timers.io.free_clk :=io.free_clk + int_timers.io.scan_mode :=io.scan_mode + int_timers.io.dec_csr_wen_r_mod :=dec_csr_wen_r_mod + int_timers.io.dec_csr_rdaddr_d :=io.dec_csr_rdaddr_d + int_timers.io.dec_csr_wraddr_r :=io.dec_csr_wraddr_r + int_timers.io.dec_csr_wrdata_r :=io.dec_csr_wrdata_r + int_timers.io.csr_mitctl0 :=csr_pkt.csr_mitctl0 + int_timers.io.csr_mitctl1 :=csr_pkt.csr_mitctl1 + int_timers.io.csr_mitb0 :=csr_pkt.csr_mitb0 + int_timers.io.csr_mitb1 :=csr_pkt.csr_mitb1 + int_timers.io.csr_mitcnt0 :=csr_pkt.csr_mitcnt0 + int_timers.io.csr_mitcnt1 :=csr_pkt.csr_mitcnt1 + int_timers.io.dec_pause_state :=io.dec_pause_state + int_timers.io.dec_tlu_pmu_fw_halted :=dec_tlu_pmu_fw_halted + int_timers.io.internal_dbg_halt_timers:=internal_dbg_halt_timers + + val dec_timer_rddata_d =int_timers.io.dec_timer_rddata_d + val dec_timer_read_d =int_timers.io.dec_timer_read_d + val dec_timer_t0_pulse =int_timers.io.dec_timer_t0_pulse + val dec_timer_t1_pulse =int_timers.io.dec_timer_t1_pulse + + val clk_override = io.dec_tlu_dec_clk_override + + // Async inputs to the core have to be sync'd to the core clock. + + val syncro_ff=rvsyncss(Cat(io.nmi_int, io.timer_int, io.soft_int, io.i_cpu_halt_req, io.i_cpu_run_req, io.mpc_debug_halt_req, io.mpc_debug_run_req),io.free_clk) + val nmi_int_sync =syncro_ff(6) + val timer_int_sync =syncro_ff(5) + val soft_int_sync =syncro_ff(4) + val i_cpu_halt_req_sync =syncro_ff(3) + val i_cpu_run_req_sync =syncro_ff(2) + val mpc_debug_halt_req_sync_raw =syncro_ff(1) + val mpc_debug_run_req_sync =syncro_ff(0) + + // for CSRs that have inpipe writes only + val csr_wr_clk=rvclkhdr(clock,(dec_csr_wen_r_mod | clk_override).asBool,io.scan_mode) + val lsu_r_wb_clk=rvclkhdr(clock,(io.lsu_error_pkt_r.exc_valid | lsu_exc_valid_r_d1 | clk_override).asBool,io.scan_mode) + + val e4_valid = io.dec_tlu_i0_valid_r + val e4e5_valid = e4_valid | e5_valid + val flush_clkvalid = internal_dbg_halt_mode_f | i_cpu_run_req_d1 | interrupt_valid_r | interrupt_valid_r_d1 | reset_delayed | pause_expired_r | pause_expired_wb | ic_perr_r | ic_perr_r_d1 | iccm_sbecc_r | iccm_sbecc_r_d1 | clk_override + + val e4e5_clk=rvclkhdr(clock,(e4e5_valid | clk_override).asBool,io.scan_mode) + val e4e5_int_clk=rvclkhdr(clock,(e4e5_valid | flush_clkvalid).asBool,io.scan_mode) + + val iccm_repair_state_d1 =withClock(io.free_clk){RegNext(iccm_repair_state_ns,0.U)} + ic_perr_r_d1 :=withClock(io.free_clk){RegNext(ic_perr_r,0.U)} + iccm_sbecc_r_d1 :=withClock(io.free_clk){RegNext(iccm_sbecc_r,0.U)} + e5_valid :=withClock(io.free_clk){RegNext(e4_valid,0.U)} + internal_dbg_halt_mode_f :=withClock(io.free_clk){RegNext(internal_dbg_halt_mode,0.U)} + val lsu_pmu_load_external_r =withClock(io.free_clk){RegNext(io.lsu_pmu_load_external_m,0.U)} + val lsu_pmu_store_external_r =withClock(io.free_clk){RegNext(io.lsu_pmu_store_external_m,0.U)} + val tlu_flush_lower_r_d1 =withClock(io.free_clk){RegNext(tlu_flush_lower_r,0.U)} + io.dec_tlu_i0_kill_writeb_wb :=withClock(io.free_clk){RegNext(tlu_i0_kill_writeb_r,0.U)} + val internal_dbg_halt_mode_f2 =withClock(io.free_clk){RegNext(internal_dbg_halt_mode_f,0.U)} + io.dec_tlu_force_halt :=withClock(io.free_clk){RegNext(force_halt,0.U)} + + + + io.dec_tlu_i0_kill_writeb_r :=tlu_i0_kill_writeb_r + val reset_detect =withClock(io.free_clk){RegNext(1.U(1.W),0.U)} + val reset_detected =withClock(io.free_clk){RegNext(reset_detect,0.U)} + reset_delayed :=reset_detect ^ reset_detected + + val nmi_int_delayed =withClock(io.free_clk){RegNext(nmi_int_sync,0.U)} + val nmi_int_detected_f =withClock(io.free_clk){RegNext(nmi_int_detected,0.U)} + val nmi_lsu_load_type_f =withClock(io.free_clk){RegNext(nmi_lsu_load_type,0.U)} + val nmi_lsu_store_type_f =withClock(io.free_clk){RegNext(nmi_lsu_store_type,0.U)} + + + // Filter subsequent bus errors after the first, until the lock on MDSEAC is cleared + val nmi_lsu_detected = ~mdseac_locked_f & (io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any) + + nmi_int_detected := (nmi_int_sync & ~nmi_int_delayed) | nmi_lsu_detected | (nmi_int_detected_f & ~take_nmi_r_d1) |(take_ext_int_start_d3 & io.lsu_fir_error.orR) + // if the first nmi is a lsu type, note it. If there's already an nmi pending, ignore + nmi_lsu_load_type := (nmi_lsu_detected & io.lsu_imprecise_error_load_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_load_type_f & ~take_nmi_r_d1) + nmi_lsu_store_type := (nmi_lsu_detected & io.lsu_imprecise_error_store_any & ~(nmi_int_detected_f & ~take_nmi_r_d1)) | (nmi_lsu_store_type_f & ~take_nmi_r_d1) + + // ---------------------------------------------------------------------- + // MPC halt + // - can interact with debugger halt and v-v + + // fast ints in progress have priority + val mpc_debug_halt_req_sync = mpc_debug_halt_req_sync_raw & ~ext_int_freeze_d1 + val mpc_debug_halt_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_halt_req_sync,0.U)} + val mpc_debug_run_req_sync_f =withClock(io.free_clk){RegNext(mpc_debug_run_req_sync,0.U)} + mpc_halt_state_f :=withClock(io.free_clk){RegNext(mpc_halt_state_ns,0.U)} + val mpc_run_state_f =withClock(io.free_clk){RegNext(mpc_run_state_ns,0.U)} + val debug_brkpt_status_f =withClock(io.free_clk){RegNext(debug_brkpt_status_ns,0.U)} + val mpc_debug_halt_ack_f =withClock(io.free_clk){RegNext(mpc_debug_halt_ack_ns,0.U)} + val mpc_debug_run_ack_f =withClock(io.free_clk){RegNext(mpc_debug_run_ack_ns,0.U)} + dbg_halt_state_f :=withClock(io.free_clk){RegNext(dbg_halt_state_ns,0.U)} + val dbg_run_state_f =withClock(io.free_clk){RegNext(dbg_run_state_ns,0.U)} + io.dec_tlu_mpc_halted_only :=withClock(io.free_clk){RegNext(dec_tlu_mpc_halted_only_ns,0.U)} + + + // turn level sensitive requests into pulses + val mpc_debug_halt_req_sync_pulse = mpc_debug_halt_req_sync & ~mpc_debug_halt_req_sync_f + val mpc_debug_run_req_sync_pulse = mpc_debug_run_req_sync & ~mpc_debug_run_req_sync_f + // states + mpc_halt_state_ns := (mpc_halt_state_f | mpc_debug_halt_req_sync_pulse | (reset_delayed & ~io.mpc_reset_run_req)) & ~mpc_debug_run_req_sync + mpc_run_state_ns := (mpc_run_state_f | (mpc_debug_run_req_sync_pulse & ~mpc_debug_run_ack_f)) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) + + dbg_halt_state_ns := (dbg_halt_state_f | (dbg_halt_req_final | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1)) & ~io.dbg_resume_req + dbg_run_state_ns := (dbg_run_state_f | io.dbg_resume_req) & (internal_dbg_halt_mode_f & ~dcsr_single_step_running_f) + + // tell dbg we are only MPC halted + dec_tlu_mpc_halted_only_ns := ~dbg_halt_state_f & mpc_halt_state_f + + // this asserts from detection of bkpt until after we leave debug mode + val debug_brkpt_valid = ebreak_to_debug_mode_r_d1 | trigger_hit_dmode_r_d1 + debug_brkpt_status_ns := (debug_brkpt_valid | debug_brkpt_status_f) & (internal_dbg_halt_mode & ~dcsr_single_step_running_f) + + // acks back to interface + mpc_debug_halt_ack_ns := mpc_halt_state_f & internal_dbg_halt_mode_f & mpc_debug_halt_req_sync & core_empty + mpc_debug_run_ack_ns := (mpc_debug_run_req_sync & ~dbg_halt_state_ns & ~mpc_debug_halt_req_sync) | (mpc_debug_run_ack_f & mpc_debug_run_req_sync) + + // Pins + io.mpc_debug_halt_ack := mpc_debug_halt_ack_f + io.mpc_debug_run_ack := mpc_debug_run_ack_f + io.debug_brkpt_status := debug_brkpt_status_f + + // DBG halt req is a pulse, fast ext int in progress has priority + val dbg_halt_req_held_ns = (io.dbg_halt_req | dbg_halt_req_held) & ext_int_freeze_d1 + dbg_halt_req_final := (io.dbg_halt_req | dbg_halt_req_held) & ~ext_int_freeze_d1 + + // combine MPC and DBG halt requests + val debug_halt_req = (dbg_halt_req_final | mpc_debug_halt_req_sync | (reset_delayed & ~io.mpc_reset_run_req)) & ~internal_dbg_halt_mode_f & ~ext_int_freeze_d1 + + val debug_resume_req = ~debug_resume_req_f & ((mpc_run_state_ns & ~dbg_halt_state_ns) | (dbg_run_state_ns & ~mpc_halt_state_ns)) + + + // HALT + // dbg/pmu/fw requests halt, service as soon as lsu is not blocking interrupts + val take_halt = (debug_halt_req_f | pmu_fw_halt_req_f) & ~synchronous_flush_r & ~mret_r & ~halt_taken_f & ~dec_tlu_flush_noredir_r_d1 & ~take_reset + + // hold after we take a halt, so we don't keep taking halts + val halt_taken = (dec_tlu_flush_noredir_r_d1 & ~dec_tlu_flush_pause_r_d1 & ~take_ext_int_start_d1) | (halt_taken_f & ~dbg_tlu_halted_f & ~pmu_fw_tlu_halted_f & ~interrupt_valid_r_d1) + + // After doing halt flush (RFNPC) wait until core is idle before asserting a particular halt mode + // It takes a cycle for mb_empty to assert after a fetch, take_halt covers that cycle + core_empty := force_halt | (io.lsu_idle_any & lsu_idle_any_f & io.ifu_miss_state_idle & ifu_miss_state_idle_f & ~debug_halt_req & ~debug_halt_req_d1 & ~io.dec_div_active) + + //-------------------------------------------------------------------------------- + // Debug start + // + + val enter_debug_halt_req = (~internal_dbg_halt_mode_f & debug_halt_req) | dcsr_single_step_done_f | trigger_hit_dmode_r_d1 | ebreak_to_debug_mode_r_d1 + + // dbg halt state active from request until non-step resume + internal_dbg_halt_mode := debug_halt_req_ns | (internal_dbg_halt_mode_f & ~(debug_resume_req_f & ~dcsr(DCSR_STEP))) + // dbg halt can access csrs as long as we are not stepping + val allow_dbg_halt_csr_write = internal_dbg_halt_mode_f & ~dcsr_single_step_running_f + + + // hold debug_halt_req_ns high until we enter debug halt + + val dbg_tlu_halted = (debug_halt_req_f & core_empty & halt_taken) | (dbg_tlu_halted_f & ~debug_resume_req_f) + debug_halt_req_ns := enter_debug_halt_req | (debug_halt_req_f & ~dbg_tlu_halted) + val resume_ack_ns = (debug_resume_req_f & dbg_tlu_halted_f & dbg_run_state_ns) + + val dcsr_single_step_done = io.dec_tlu_i0_valid_r & ~io.dec_tlu_dbg_halted & dcsr(DCSR_STEP) & ~rfpc_i0_r + + val dcsr_single_step_running = (debug_resume_req_f & dcsr(DCSR_STEP)) | (dcsr_single_step_running_f & ~dcsr_single_step_done_f) + + val dbg_cmd_done_ns = io.dec_tlu_i0_valid_r & io.dec_tlu_dbg_halted + + // used to hold off commits after an in-pipe debug mode request (triggers, DCSR) + val request_debug_mode_r = (trigger_hit_dmode_r | ebreak_to_debug_mode_r) | (request_debug_mode_r_d1 & ~io.dec_tlu_flush_lower_wb) + + val request_debug_mode_done = (request_debug_mode_r_d1 | request_debug_mode_done_f) & ~dbg_tlu_halted_f + + + dec_tlu_flush_noredir_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_noredir_r,0.U)} + halt_taken_f :=withClock(io.free_clk){RegNext(halt_taken,0.U)} + lsu_idle_any_f :=withClock(io.free_clk){RegNext(io.lsu_idle_any,0.U)} + ifu_miss_state_idle_f :=withClock(io.free_clk){RegNext(io.ifu_miss_state_idle,0.U)} + dbg_tlu_halted_f :=withClock(io.free_clk){RegNext(dbg_tlu_halted,0.U)} + io.dec_tlu_resume_ack :=withClock(io.free_clk){RegNext(resume_ack_ns,0.U)} + debug_halt_req_f :=withClock(io.free_clk){RegNext(debug_halt_req_ns,0.U)} + debug_resume_req_f :=withClock(io.free_clk){RegNext(debug_resume_req,0.U)} + trigger_hit_dmode_r_d1 :=withClock(io.free_clk){RegNext(trigger_hit_dmode_r,0.U)} + dcsr_single_step_done_f :=withClock(io.free_clk){RegNext(dcsr_single_step_done,0.U)} + debug_halt_req_d1 :=withClock(io.free_clk){RegNext(debug_halt_req,0.U)} + val dec_tlu_wr_pause_r_d1 =withClock(io.free_clk){RegNext(io.dec_tlu_wr_pause_r,0.U)} + val dec_pause_state_f =withClock(io.free_clk){RegNext(io.dec_pause_state,0.U)} + request_debug_mode_r_d1 :=withClock(io.free_clk){RegNext(request_debug_mode_r,0.U)} + request_debug_mode_done_f :=withClock(io.free_clk){RegNext(request_debug_mode_done,0.U)} + dcsr_single_step_running_f :=withClock(io.free_clk){RegNext(dcsr_single_step_running,0.U)} + dec_tlu_flush_pause_r_d1 :=withClock(io.free_clk){RegNext(io.dec_tlu_flush_pause_r,0.U)} + dbg_halt_req_held :=withClock(io.free_clk){RegNext(dbg_halt_req_held_ns,0.U)} + + + io.dec_tlu_debug_stall := debug_halt_req_f + io.dec_tlu_dbg_halted := dbg_tlu_halted_f + io.dec_tlu_debug_mode := internal_dbg_halt_mode_f + dec_tlu_pmu_fw_halted := pmu_fw_tlu_halted_f + + // kill fetch redirection on flush if going to halt, or if there's a fence during db-halt + io.dec_tlu_flush_noredir_r := take_halt | (fence_i_r & internal_dbg_halt_mode) | io.dec_tlu_flush_pause_r | (i0_trigger_hit_r & trigger_hit_dmode_r) | take_ext_int_start + + io.dec_tlu_flush_extint := take_ext_int_start + + // 1 cycle after writing the PAUSE counter, flush with noredir to idle F1-D. + io.dec_tlu_flush_pause_r := dec_tlu_wr_pause_r_d1 & ~interrupt_valid_r & ~take_ext_int_start + // detect end of pause counter and rfpc + pause_expired_r := ~io.dec_pause_state & dec_pause_state_f & ~(ext_int_ready | ce_int_ready | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | nmi_int_detected | ext_int_freeze_d1) & ~interrupt_valid_r_d1 & ~debug_halt_req_f & ~pmu_fw_halt_req_f & ~halt_taken_f + + io.dec_tlu_flush_leak_one_r := io.dec_tlu_flush_lower_r & dcsr(DCSR_STEP) & (io.dec_tlu_resume_ack | dcsr_single_step_running) & ~io.dec_tlu_flush_noredir_r + io.dec_tlu_flush_err_r := io.dec_tlu_flush_lower_r & (ic_perr_r_d1 | iccm_sbecc_r_d1) + + // If DM attempts to access an illegal CSR, send cmd_fail back + io.dec_dbg_cmd_done := dbg_cmd_done_ns + io.dec_dbg_cmd_fail := illegal_r & io.dec_dbg_cmd_done + + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + // Triggers + // + + // Prioritize trigger hits with other exceptions. + // + // Trigger should have highest priority except: + // - trigger is an execute-data and there is an inst_access exception (lsu triggers won't fire, inst. is nop'd by decode) + // - trigger is a store-data and there is a lsu_acc_exc or lsu_ma_exc. + val trigger_execute = Cat(mtdata1_t(3)(MTDATA1_EXE), mtdata1_t(2)(MTDATA1_EXE), mtdata1_t(1)(MTDATA1_EXE), mtdata1_t(0)(MTDATA1_EXE)) + val trigger_data = Cat(mtdata1_t(3)(MTDATA1_SEL), mtdata1_t(2)(MTDATA1_SEL), mtdata1_t(1)(MTDATA1_SEL), mtdata1_t(0)(MTDATA1_SEL)) + val trigger_store = Cat(mtdata1_t(3)(MTDATA1_ST), mtdata1_t(2)(MTDATA1_ST), mtdata1_t(1)(MTDATA1_ST), mtdata1_t(0)(MTDATA1_ST)) + + // MSTATUS[MIE] needs to be on to take triggers unless the action is trigger to debug mode. + val trigger_enabled = Cat((mtdata1_t(3)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(3)(MTDATA1_M_ENABLED),(mtdata1_t(2)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(2)(MTDATA1_M_ENABLED), (mtdata1_t(1)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(1)(MTDATA1_M_ENABLED), (mtdata1_t(0)(MTDATA1_ACTION) | mstatus(MSTATUS_MIE)) & mtdata1_t(0)(MTDATA1_M_ENABLED)) + + // iside exceptions are always in i0 + val i0_iside_trigger_has_pri_r = ~((trigger_execute & trigger_data & Fill(4,inst_acc_r_raw)) | (Fill(4,io.exu_i0_br_error_r | io.exu_i0_br_start_error_r))) + + // lsu excs have to line up with their respective triggers since the lsu op can be i0 + val i0_lsu_trigger_has_pri_r = ~(trigger_store & trigger_data & Fill(4,lsu_i0_exc_r_raw)) + + // trigger hits have to be eval'd to cancel side effect lsu ops even though the pipe is already frozen + val i0_trigger_eval_r = io.dec_tlu_i0_valid_r + + val i0trigger_qual_r = Fill(4,i0_trigger_eval_r) & io.dec_tlu_packet_r.i0trigger(3,0) & i0_iside_trigger_has_pri_r & i0_lsu_trigger_has_pri_r & trigger_enabled + // Qual trigger hits + val i0_trigger_r = ~(Fill(4,io.dec_tlu_flush_lower_wb | io.dec_tlu_dbg_halted)) & i0trigger_qual_r + + // chaining can mask raw trigger info + val i0_trigger_chain_masked_r = Cat(i0_trigger_r(3) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(2)), i0_trigger_r(2) & (~mtdata1_t(2)(MTDATA1_CHAIN) | i0_trigger_r(3)), i0_trigger_r(1) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(0)), i0_trigger_r(0) & (~mtdata1_t(0)(MTDATA1_CHAIN) | i0_trigger_r(1))) + + // This is the highest priority by this point. + val i0_trigger_hit_raw_r = i0_trigger_chain_masked_r.orR + + i0_trigger_hit_r := i0_trigger_hit_raw_r + + // Actions include breakpoint, or dmode. Dmode is only possible if the DMODE bit is set. + // Otherwise, take a breakpoint. + val trigger_action = Cat(mtdata1_t(3)(MTDATA1_ACTION) & mtdata1_t(3)(MTDATA1_DMODE), mtdata1_t(2)(MTDATA1_ACTION) & mtdata1_t(2)(MTDATA1_DMODE), mtdata1_t(1)(MTDATA1_ACTION) & mtdata1_t(1)(MTDATA1_DMODE), mtdata1_t(0)(MTDATA1_ACTION) & mtdata1_t(0)(MTDATA1_DMODE)) + + // this is needed to set the HIT bit in the triggers + val update_hit_bit_r = (Fill(4,i0_trigger_hit_r) & i0_trigger_chain_masked_r) + + // action, 1 means dmode. Simultaneous triggers with at least 1 set for dmode force entire action to dmode. + val i0_trigger_action_r = (i0_trigger_chain_masked_r & trigger_action).orR + + trigger_hit_dmode_r := (i0_trigger_hit_r & i0_trigger_action_r) + + val mepc_trigger_hit_sel_pc_r = i0_trigger_hit_r & ~trigger_hit_dmode_r + + // + // Debug end + + + //---------------------------------------------------------------------- + // + // Commit + // + //---------------------------------------------------------------------- + + + + //-------------------------------------------------------------------------------- + // External halt (not debug halt) + // - Fully interlocked handshake + // i_cpu_halt_req ____|--------------|_______________ + // core_empty ---------------|___________ + // o_cpu_halt_ack _________________|----|__________ + // o_cpu_halt_status _______________|---------------------|_________ + // i_cpu_run_req ______|----------|____ + // o_cpu_run_ack ____________|------|________ + // + + + // debug mode has priority, ignore PMU/FW halt/run while in debug mode + val i_cpu_halt_req_sync_qual = i_cpu_halt_req_sync & ~io.dec_tlu_debug_mode & ~ext_int_freeze_d1 + val i_cpu_run_req_sync_qual = i_cpu_run_req_sync & ~io.dec_tlu_debug_mode & pmu_fw_tlu_halted_f & ~ext_int_freeze_d1 + + val i_cpu_halt_req_d1 =withClock(io.free_clk){RegNext(i_cpu_halt_req_sync_qual,0.U)} + val i_cpu_run_req_d1_raw =withClock(io.free_clk){RegNext(i_cpu_run_req_sync_qual,0.U)} + io.o_cpu_halt_status :=withClock(io.free_clk){RegNext(cpu_halt_status,0.U)} + io.o_cpu_halt_ack :=withClock(io.free_clk){RegNext(cpu_halt_ack,0.U)} + io.o_cpu_run_ack :=withClock(io.free_clk){RegNext(cpu_run_ack,0.U)} + val internal_pmu_fw_halt_mode_f=withClock(io.free_clk){RegNext(internal_pmu_fw_halt_mode,0.U)} + pmu_fw_halt_req_f :=withClock(io.free_clk){RegNext(pmu_fw_halt_req_ns,0.U)} + pmu_fw_tlu_halted_f :=withClock(io.free_clk){RegNext(pmu_fw_tlu_halted,0.U)} + int_timer0_int_hold_f :=withClock(io.free_clk){RegNext(int_timer0_int_hold,0.U)} + int_timer1_int_hold_f :=withClock(io.free_clk){RegNext(int_timer1_int_hold,0.U)} + + + // only happens if we aren't in dgb_halt + val ext_halt_pulse = i_cpu_halt_req_sync_qual & ~i_cpu_halt_req_d1 + val enter_pmu_fw_halt_req = ext_halt_pulse | fw_halt_req + pmu_fw_halt_req_ns := (enter_pmu_fw_halt_req | (pmu_fw_halt_req_f & ~pmu_fw_tlu_halted)) & ~debug_halt_req_f + internal_pmu_fw_halt_mode := pmu_fw_halt_req_ns | (internal_pmu_fw_halt_mode_f & ~i_cpu_run_req_d1 & ~debug_halt_req_f) + + // debug halt has priority + pmu_fw_tlu_halted := ((pmu_fw_halt_req_f & core_empty & halt_taken & ~enter_debug_halt_req) | (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1)) & ~debug_halt_req_f + + cpu_halt_ack := i_cpu_halt_req_d1 & pmu_fw_tlu_halted_f + cpu_halt_status := (pmu_fw_tlu_halted_f & ~i_cpu_run_req_d1) | (io.o_cpu_halt_status & ~i_cpu_run_req_d1 & ~internal_dbg_halt_mode_f) + cpu_run_ack := (io.o_cpu_halt_status & i_cpu_run_req_sync_qual) | (io.o_cpu_run_ack & i_cpu_run_req_sync_qual) + val debug_mode_status = internal_dbg_halt_mode_f + io.o_debug_mode_status := debug_mode_status + + // high priority interrupts can wakeup from external halt, so can unmasked timer interrupts + i_cpu_run_req_d1 := i_cpu_run_req_d1_raw | ((nmi_int_detected | timer_int_ready | soft_int_ready | int_timer0_int_hold_f | int_timer1_int_hold_f | (io.mhwakeup & mhwakeup_ready)) & io.o_cpu_halt_status & ~i_cpu_halt_req_d1) + + //-------------------------------------------------------------------------------- + //-------------------------------------------------------------------------------- + + val lsu_single_ecc_error_r =io.lsu_single_ecc_error_incr + mdseac_locked_f :=withClock(io.free_clk){RegNext(mdseac_locked_ns,0.U)} + val lsu_single_ecc_error_r_d1 =withClock(io.free_clk){RegNext(lsu_single_ecc_error_r,0.U)} + val lsu_error_pkt_addr_r =io.lsu_error_pkt_r.addr + val lsu_exc_valid_r_raw = io.lsu_error_pkt_r.exc_valid & ~io.dec_tlu_flush_lower_wb + lsu_i0_exc_r_raw := io.lsu_error_pkt_r.exc_valid + val lsu_i0_exc_r = lsu_i0_exc_r_raw & lsu_exc_valid_r_raw & ~i0_trigger_hit_r & ~rfpc_i0_r + val lsu_exc_valid_r = lsu_i0_exc_r + lsu_exc_valid_r_d1 :=withClock(lsu_r_wb_clk){RegNext(lsu_exc_valid_r,0.U)} + val lsu_i0_exc_r_d1 =withClock(lsu_r_wb_clk){RegNext(lsu_i0_exc_r,0.U)} + val lsu_exc_ma_r = lsu_i0_exc_r & ~io.lsu_error_pkt_r.exc_type + val lsu_exc_acc_r = lsu_i0_exc_r & io.lsu_error_pkt_r.exc_type + val lsu_exc_st_r = lsu_i0_exc_r & io.lsu_error_pkt_r.inst_type + + // Single bit ECC errors on loads are RFNPC corrected, with the corrected data written to the GPR. + // LSU turns the load into a store and patches the data in the DCCM + val lsu_i0_rfnpc_r = io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & (~io.lsu_error_pkt_r.inst_type & io.lsu_error_pkt_r.single_ecc_error) + + // Final commit valids + val tlu_i0_commit_cmt = io.dec_tlu_i0_valid_r & ~rfpc_i0_r & ~lsu_i0_exc_r & ~inst_acc_r & ~io.dec_tlu_dbg_halted & ~request_debug_mode_r_d1 & ~i0_trigger_hit_r + + // unified place to manage the killing of arch state writebacks + tlu_i0_kill_writeb_r := rfpc_i0_r | lsu_i0_exc_r | inst_acc_r | (illegal_r & io.dec_tlu_dbg_halted) | i0_trigger_hit_r + io.dec_tlu_i0_commit_cmt := tlu_i0_commit_cmt + + + // refetch PC, microarch flush + // ic errors only in pipe0 + rfpc_i0_r := ((io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (io.exu_i0_br_error_r | io.exu_i0_br_start_error_r)) | ((ic_perr_r_d1 | iccm_sbecc_r_d1) & ~ext_int_freeze_d1)) & ~i0_trigger_hit_r & ~lsu_i0_rfnpc_r + + // From the indication of a iccm single bit error until the first commit or flush, maintain a repair state. In the repair state, rfnpc i0 commits. + iccm_repair_state_ns := iccm_sbecc_r_d1 | (iccm_repair_state_d1 & ~io.dec_tlu_flush_lower_r) + + + val MCPC =0x7c2.U(12.W) + + // this is a flush of last resort, meaning only assert it if there is no other flush happening. + val iccm_repair_state_rfnpc = tlu_i0_commit_cmt & iccm_repair_state_d1 & ~(ebreak_r | ecall_r | mret_r | take_reset | illegal_r | (dec_csr_wen_r_mod & (io.dec_csr_wraddr_r ===MCPC))) + + // go ahead and repair the branch error on other flushes, doesn't have to be the rfpc flush + val dec_tlu_br0_error_r = io.exu_i0_br_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + val dec_tlu_br0_start_error_r = io.exu_i0_br_start_error_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 + val dec_tlu_br0_v_r = io.exu_i0_br_valid_r & io.dec_tlu_i0_valid_r & ~tlu_flush_lower_r_d1 & (~io.exu_i0_br_mp_r | ~io.exu_pmu_i0_br_ataken) + + + io.dec_tlu_br0_r_pkt.hist := io.exu_i0_br_hist_r + io.dec_tlu_br0_r_pkt.br_error := dec_tlu_br0_error_r + io.dec_tlu_br0_r_pkt.br_start_error := dec_tlu_br0_start_error_r + io.dec_tlu_br0_r_pkt.valid := dec_tlu_br0_v_r + io.dec_tlu_br0_r_pkt.way := io.exu_i0_br_way_r + io.dec_tlu_br0_r_pkt.middle := io.exu_i0_br_middle_r + + + ebreak_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + ecall_r := (io.dec_tlu_packet_r.pmu_i0_itype === ECALL) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + illegal_r := ~io.dec_tlu_packet_r.legal & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + mret_r := (io.dec_tlu_packet_r.pmu_i0_itype === MRET) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & ~rfpc_i0_r + // fence_i includes debug only fence_i's + fence_i_r := (io.dec_tlu_packet_r.fence_i & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r) & ~rfpc_i0_r + ic_perr_r := io.ifu_ic_error_start & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + iccm_sbecc_r := io.ifu_iccm_rd_ecc_single_err & ~ext_int_freeze_d1 & (~internal_dbg_halt_mode_f | dcsr_single_step_running) & ~internal_pmu_fw_halt_mode_f + inst_acc_r_raw := io.dec_tlu_packet_r.icaf & io.dec_tlu_i0_valid_r + inst_acc_r := inst_acc_r_raw & ~rfpc_i0_r & ~i0_trigger_hit_r + val inst_acc_second_r = io.dec_tlu_packet_r.icaf_f1 + + ebreak_to_debug_mode_r := (io.dec_tlu_packet_r.pmu_i0_itype === EBREAK) & io.dec_tlu_i0_valid_r & ~i0_trigger_hit_r & dcsr(DCSR_EBREAKM) & ~rfpc_i0_r + + ebreak_to_debug_mode_r_d1:= withClock(e4e5_clk){RegNext(ebreak_to_debug_mode_r,0.U)} + io.dec_tlu_fence_i_r := fence_i_r + + // + // Exceptions + // + // - MEPC <- PC + // - PC <- MTVEC, assert flush_lower + // - MCAUSE <- cause + // - MSCAUSE <- secondary cause + // - MTVAL <- + // - MPIE <- MIE + // - MIE <- 0 + // + val i0_exception_valid_r = (ebreak_r | ecall_r | illegal_r | inst_acc_r) & ~rfpc_i0_r & ~io.dec_tlu_dbg_halted + + // Cause: + // + // 0x2 : illegal + // 0x3 : breakpoint + // 0xb : Environment call M-mode + + val exc_cause_r = Mux1H(Seq( + (take_ext_int & ~take_nmi).asBool -> 0x0b.U(5.W), + (take_timer_int & ~take_nmi).asBool -> 0x07.U(5.W), + (take_soft_int & ~take_nmi).asBool -> 0x03.U(5.W), + (take_int_timer0_int & ~take_nmi).asBool -> 0x1d.U(5.W), + (take_int_timer1_int & ~take_nmi).asBool -> 0x1c.U(5.W), + (take_ce_int & ~take_nmi).asBool -> 0x1e.U(5.W), + (illegal_r & ~take_nmi).asBool -> 0x02.U(5.W), + (ecall_r & ~take_nmi).asBool -> 0x0b.U(5.W), + (inst_acc_r & ~take_nmi).asBool -> 0x01.U(5.W), + ((ebreak_r | i0_trigger_hit_r) & ~take_nmi).asBool -> 0x03.U(5.W), + (lsu_exc_ma_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x04.U(5.W), + (lsu_exc_acc_r & ~lsu_exc_st_r & ~take_nmi).asBool -> 0x05.U(5.W), + (lsu_exc_ma_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x06.U(5.W), + (lsu_exc_acc_r & lsu_exc_st_r & ~take_nmi).asBool -> 0x07.U(5.W) + )) + // + // Interrupts + // + // exceptions that are committed have already happened and will cause an int at E4 to wait a cycle + // or more if MSTATUS[MIE] is cleared. + // + // -in priority order, highest to lowest + // -single cycle window where a csr write to MIE/MSTATUS is at E4 when the other conditions for externals are met. + // Hold off externals for a cycle to make sure we are consistent with what was just written + mhwakeup_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) + ext_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MEIP) & mie_ns(MIE_MEIE) & ~ignore_ext_int_due_to_lsu_stall + ce_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MCEIP) & mie_ns(MIE_MCEIE) + soft_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MSIP) & mie_ns(MIE_MSIE) + timer_int_ready := ~io.dec_csr_stall_int_ff & mstatus_mie_ns & mip(MIP_MTIP) & mie_ns(MIE_MTIE) + + // MIP for internal timers pulses for 1 clock, resets the timer counter. Mip won't hold past the various stall conditions. + val int_timer0_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE0) + val int_timer0_int_ready = mip(MIP_MITIP0) & int_timer0_int_possible + val int_timer1_int_possible = mstatus_mie_ns & mie_ns(MIE_MITIE1) + val int_timer1_int_ready = mip(MIP_MITIP1) & int_timer1_int_possible + + // Internal timers pulse and reset. If core is PMU/FW halted, the pulse will cause an exit from halt, but won't stick around + // Make it sticky, also for 1 cycle stall conditions. + val int_timer_stalled = io.dec_csr_stall_int_ff | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r + + int_timer0_int_hold := (int_timer0_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer0_int_possible & int_timer0_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) + int_timer1_int_hold := (int_timer1_int_ready & (pmu_fw_tlu_halted_f | int_timer_stalled)) | (int_timer1_int_possible & int_timer1_int_hold_f & ~interrupt_valid_r & ~take_ext_int_start & ~internal_dbg_halt_mode_f) + + internal_dbg_halt_timers := internal_dbg_halt_mode_f & ~dcsr_single_step_running; + + val block_interrupts = ((internal_dbg_halt_mode & (~dcsr_single_step_running | io.dec_tlu_i0_valid_r)) | internal_pmu_fw_halt_mode | i_cpu_halt_req_d1 | take_nmi | ebreak_to_debug_mode_r | synchronous_flush_r | exc_or_int_valid_r_d1 | mret_r | ext_int_freeze_d1) + + + if(FAST_INTERRUPT_REDIRECT==1) { + take_ext_int_start_d1:=withClock(io.free_clk){RegNext(take_ext_int_start,0.U)} + take_ext_int_start_d2:=withClock(io.free_clk){RegNext(take_ext_int_start_d1,0.U)} + take_ext_int_start_d3:=withClock(io.free_clk){RegNext(take_ext_int_start_d2,0.U)} + ext_int_freeze_d1 :=withClock(io.free_clk){RegNext(ext_int_freeze,0.U)} + take_ext_int_start := ext_int_ready & ~block_interrupts; + + ext_int_freeze := take_ext_int_start | take_ext_int_start_d1 | take_ext_int_start_d2 | take_ext_int_start_d3 + take_ext_int := take_ext_int_start_d3 & ~io.lsu_fir_error.orR + fast_int_meicpct := csr_pkt.csr_meicpct & io.dec_csr_any_unq_d // MEICPCT becomes illegal if fast ints are enabled + ignore_ext_int_due_to_lsu_stall := io.lsu_fastint_stall_any + }else{ + take_ext_int_start := 0.U(1.W) + ext_int_freeze := 0.U(1.W) + ext_int_freeze_d1 := 0.U(1.W) + take_ext_int_start_d1 := 0.U(1.W) + take_ext_int_start_d2 := 0.U(1.W) + take_ext_int_start_d3 := 0.U(1.W) + fast_int_meicpct := 0.U(1.W) + ignore_ext_int_due_to_lsu_stall := 0.U(1.W) + take_ext_int := ext_int_ready & ~block_interrupts + } + + take_ce_int := ce_int_ready & ~ext_int_ready & ~block_interrupts + take_soft_int := soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_timer_int := timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_int_timer0_int := (int_timer0_int_ready | int_timer0_int_hold_f) & int_timer0_int_possible & ~io.dec_csr_stall_int_ff & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_int_timer1_int := (int_timer1_int_ready | int_timer1_int_hold_f) & int_timer1_int_possible & ~io.dec_csr_stall_int_ff & ~(int_timer0_int_ready | int_timer0_int_hold_f) & ~timer_int_ready & ~soft_int_ready & ~ext_int_ready & ~ce_int_ready & ~block_interrupts + take_reset := reset_delayed & io.mpc_reset_run_req + take_nmi := nmi_int_detected & ~internal_pmu_fw_halt_mode & (~internal_dbg_halt_mode | (dcsr_single_step_running_f & dcsr(DCSR_STEPIE) & ~io.dec_tlu_i0_valid_r & ~dcsr_single_step_done_f)) & ~synchronous_flush_r & ~mret_r & ~take_reset & ~ebreak_to_debug_mode_r & (~ext_int_freeze_d1 | (take_ext_int_start_d3 & io.lsu_fir_error.orR)) + + + interrupt_valid_r := take_ext_int | take_timer_int | take_soft_int | take_nmi | take_ce_int | take_int_timer0_int | take_int_timer1_int + + + // Compute interrupt path: + // If vectored async is set in mtvec, flush path for interrupts is MTVEC + (4 * CAUSE); + val vectored_path = Cat(mtvec(30,1),0.U(1.W)) + Cat(0.U(25.W),exc_cause_r, 0.U(1.W)) ///After Combining Code revisit this + val interrupt_path = Mux(take_nmi.asBool, io.nmi_vec, Mux(mtvec(0) === 1.U, vectored_path, Cat(mtvec(30,1),0.U(1.W))))///After Combining Code revisit this + val sel_npc_r = lsu_i0_rfnpc_r | fence_i_r | iccm_repair_state_rfnpc | (i_cpu_run_req_d1 & ~interrupt_valid_r) | (rfpc_i0_r & ~io.dec_tlu_i0_valid_r) + val sel_npc_resume = (i_cpu_run_req_d1 & pmu_fw_tlu_halted_f) | pause_expired_r + val sel_fir_addr = take_ext_int_start_d3 & ~io.lsu_fir_error.orR + synchronous_flush_r := i0_exception_valid_r | rfpc_i0_r | lsu_exc_valid_r | fence_i_r | lsu_i0_rfnpc_r | iccm_repair_state_rfnpc | debug_resume_req_f | sel_npc_resume | dec_tlu_wr_pause_r_d1 | i0_trigger_hit_r + tlu_flush_lower_r := interrupt_valid_r | mret_r | synchronous_flush_r | take_halt | take_reset | take_ext_int_start + ///After Combining Code revisit this + val tlu_flush_path_r = Mux(take_reset.asBool, io.rst_vec,Mux1H(Seq( + (sel_fir_addr).asBool -> io.lsu_fir_addr, + (take_nmi===0.U & sel_npc_r===1.U) -> npc_r, + (take_nmi===0.U & rfpc_i0_r===1.U & io.dec_tlu_i0_valid_r===1.U & sel_npc_r===0.U) -> io.dec_tlu_i0_pc_r, + (interrupt_valid_r===1.U & sel_fir_addr===0.U) -> interrupt_path, + ((i0_exception_valid_r | lsu_exc_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r)) & ~interrupt_valid_r & ~sel_fir_addr).asBool -> Cat(mtvec(30,1),0.U(1.W)), + (~take_nmi & mret_r).asBool -> mepc, + (~take_nmi & debug_resume_req_f).asBool -> dpc, + (~take_nmi & sel_npc_resume).asBool -> npc_r_d1 + ))) + + val tlu_flush_path_r_d1=withClock(e4e5_int_clk){RegNext(tlu_flush_path_r,0.U)} ///After Combining Code revisit this + + io.dec_tlu_flush_lower_wb := tlu_flush_lower_r_d1 + io.dec_tlu_flush_lower_r := tlu_flush_lower_r + io.dec_tlu_flush_path_r := tlu_flush_path_r ///After Combining Code revisit this + + // this is used to capture mepc, etc. + val exc_or_int_valid_r = lsu_exc_valid_r | i0_exception_valid_r | interrupt_valid_r | (i0_trigger_hit_r & ~trigger_hit_dmode_r) + + interrupt_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(interrupt_valid_r,0.U)} + val i0_exception_valid_r_d1 =withClock(e4e5_int_clk){RegNext(i0_exception_valid_r,0.U)} + exc_or_int_valid_r_d1 :=withClock(e4e5_int_clk){RegNext(exc_or_int_valid_r,0.U)} + val exc_cause_wb =withClock(e4e5_int_clk){RegNext(exc_cause_r,0.U)} + val i0_valid_wb =withClock(e4e5_int_clk){RegNext((tlu_i0_commit_cmt & ~illegal_r),0.U)} + val trigger_hit_r_d1 =withClock(e4e5_int_clk){RegNext(i0_trigger_hit_r,0.U)} + take_nmi_r_d1 :=withClock(e4e5_int_clk){RegNext(take_nmi,0.U)} + pause_expired_wb :=withClock(e4e5_int_clk){RegNext(pause_expired_r,0.U)} + + val csr=Module(new csr_tlu) + csr.io.free_clk := io.free_clk + csr.io.active_clk := io.active_clk + csr.io.scan_mode := io.scan_mode + csr.io.dec_csr_wrdata_r := io.dec_csr_wrdata_r + csr.io.dec_csr_wraddr_r := io.dec_csr_wraddr_r + csr.io.dec_csr_rdaddr_d := io.dec_csr_rdaddr_d + csr.io.dec_csr_wen_unq_d := io.dec_csr_wen_unq_d + csr.io.dec_i0_decode_d := io.dec_i0_decode_d + csr.io.ifu_ic_debug_rd_data_valid := io.ifu_ic_debug_rd_data_valid + csr.io.ifu_pmu_bus_trxn := io.ifu_pmu_bus_trxn + csr.io.dma_iccm_stall_any :=io.dma_iccm_stall_any + csr.io.dma_dccm_stall_any :=io.dma_dccm_stall_any + csr.io.lsu_store_stall_any :=io.lsu_store_stall_any + csr.io.dec_pmu_presync_stall :=io.dec_pmu_presync_stall + csr.io.dec_pmu_postsync_stall :=io.dec_pmu_postsync_stall + csr.io.dec_pmu_decode_stall :=io.dec_pmu_decode_stall + csr.io.ifu_pmu_fetch_stall :=io.ifu_pmu_fetch_stall + csr.io.dec_tlu_packet_r :=io.dec_tlu_packet_r + csr.io.exu_pmu_i0_br_ataken :=io.exu_pmu_i0_br_ataken + csr.io.exu_pmu_i0_br_misp :=io.exu_pmu_i0_br_misp + csr.io.dec_pmu_instr_decoded :=io.dec_pmu_instr_decoded + csr.io.ifu_pmu_instr_aligned :=io.ifu_pmu_instr_aligned + csr.io.exu_pmu_i0_pc4 :=io.exu_pmu_i0_pc4 + csr.io.ifu_pmu_ic_miss :=io.ifu_pmu_ic_miss + csr.io.ifu_pmu_ic_hit :=io.ifu_pmu_ic_hit + csr.io.dec_csr_wen_r := io.dec_csr_wen_r + csr.io.dec_tlu_dbg_halted := io.dec_tlu_dbg_halted + csr.io.dma_pmu_dccm_write := io.dma_pmu_dccm_write + csr.io.dma_pmu_dccm_read := io.dma_pmu_dccm_read + csr.io.dma_pmu_any_write := io.dma_pmu_any_write + csr.io.dma_pmu_any_read := io.dma_pmu_any_read + csr.io.lsu_pmu_bus_busy := io.lsu_pmu_bus_busy + csr.io.dec_tlu_i0_pc_r := io.dec_tlu_i0_pc_r + csr.io.dec_tlu_i0_valid_r := io.dec_tlu_i0_valid_r + csr.io.dec_csr_stall_int_ff := io.dec_csr_stall_int_ff + csr.io.dec_csr_any_unq_d := io.dec_csr_any_unq_d + csr.io.ifu_pmu_bus_busy := io.ifu_pmu_bus_busy + csr.io.lsu_pmu_bus_error := io.lsu_pmu_bus_error + csr.io.ifu_pmu_bus_error := io.ifu_pmu_bus_error + csr.io.lsu_pmu_bus_misaligned := io.lsu_pmu_bus_misaligned + csr.io.lsu_pmu_bus_trxn := io.lsu_pmu_bus_trxn + csr.io.ifu_ic_debug_rd_data := io.ifu_ic_debug_rd_data + csr.io.pic_pl := io.pic_pl + csr.io.pic_claimid := io.pic_claimid + csr.io.iccm_dma_sb_error := io.iccm_dma_sb_error + csr.io.lsu_imprecise_error_addr_any := io.lsu_imprecise_error_addr_any + csr.io.lsu_imprecise_error_load_any := io.lsu_imprecise_error_load_any + csr.io.lsu_imprecise_error_store_any := io.lsu_imprecise_error_store_any + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.mexintpend + csr.io.exu_npc_r := io.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d + io.dec_tlu_meicurpl := csr.io.dec_tlu_meicurpl + io.dec_tlu_meihap := csr.io.dec_tlu_meihap + io.dec_tlu_meipt := csr.io.dec_tlu_meipt + io.dec_tlu_int_valid_wb1 := csr.io.dec_tlu_int_valid_wb1 + io.dec_tlu_i0_exc_valid_wb1 := csr.io.dec_tlu_i0_exc_valid_wb1 + io.dec_tlu_i0_valid_wb1 := csr.io.dec_tlu_i0_valid_wb1 + io.dec_tlu_ic_diag_pkt := csr.io.dec_tlu_ic_diag_pkt + io.trigger_pkt_any := csr.io.trigger_pkt_any + io.dec_tlu_mtval_wb1 := csr.io.dec_tlu_mtval_wb1 + io.dec_tlu_exc_cause_wb1 := csr.io.dec_tlu_exc_cause_wb1 + io.dec_tlu_perfcnt0 := csr.io.dec_tlu_perfcnt0 + io.dec_tlu_perfcnt1 := csr.io.dec_tlu_perfcnt1 + io.dec_tlu_perfcnt2 := csr.io.dec_tlu_perfcnt2 + io.dec_tlu_perfcnt3 := csr.io.dec_tlu_perfcnt3 + io.dec_tlu_misc_clk_override := csr.io.dec_tlu_misc_clk_override + io.dec_tlu_dec_clk_override := csr.io.dec_tlu_dec_clk_override + io.dec_tlu_ifu_clk_override := csr.io.dec_tlu_ifu_clk_override + io.dec_tlu_lsu_clk_override := csr.io.dec_tlu_lsu_clk_override + io.dec_tlu_bus_clk_override := csr.io.dec_tlu_bus_clk_override + io.dec_tlu_pic_clk_override := csr.io.dec_tlu_pic_clk_override + io.dec_tlu_dccm_clk_override := csr.io.dec_tlu_dccm_clk_override + io.dec_tlu_icm_clk_override := csr.io.dec_tlu_icm_clk_override + io.dec_csr_rddata_d := csr.io.dec_csr_rddata_d + io.dec_tlu_pipelining_disable := csr.io.dec_tlu_pipelining_disable + io.dec_tlu_wr_pause_r := csr.io.dec_tlu_wr_pause_r + io.dec_tlu_mrac_ff := csr.io.dec_tlu_mrac_ff + io.dec_tlu_wb_coalescing_disable := csr.io.dec_tlu_wb_coalescing_disable + io.dec_tlu_bpred_disable := csr.io.dec_tlu_bpred_disable + io.dec_tlu_sideeffect_posted_disable := csr.io.dec_tlu_sideeffect_posted_disable + io.dec_tlu_core_ecc_disable := csr.io.dec_tlu_core_ecc_disable + io.dec_tlu_external_ldfwd_disable := csr.io.dec_tlu_external_ldfwd_disable + io.dec_tlu_dma_qos_prty := csr.io.dec_tlu_dma_qos_prty + csr.io.dec_illegal_inst := io.dec_illegal_inst + csr.io.lsu_error_pkt_r := io.lsu_error_pkt_r + csr.io.mexintpend := io.mexintpend + csr.io.exu_npc_r := io.exu_npc_r + csr.io.mpc_reset_run_req := io.mpc_reset_run_req + csr.io.rst_vec := io.rst_vec + csr.io.core_id := io.core_id + csr.io.dec_timer_rddata_d := dec_timer_rddata_d + csr.io.dec_timer_read_d := dec_timer_read_d + + + csr.io.rfpc_i0_r := rfpc_i0_r + csr.io.i0_trigger_hit_r := i0_trigger_hit_r + csr.io.exc_or_int_valid_r := exc_or_int_valid_r + csr.io.mret_r := mret_r + csr.io.dcsr_single_step_running_f := dcsr_single_step_running_f + csr.io.dec_timer_t0_pulse := dec_timer_t0_pulse + csr.io.dec_timer_t1_pulse := dec_timer_t1_pulse + csr.io.timer_int_sync := timer_int_sync + csr.io.soft_int_sync := soft_int_sync + csr.io.csr_wr_clk := csr_wr_clk + csr.io.ebreak_to_debug_mode_r := ebreak_to_debug_mode_r + csr.io.dec_tlu_pmu_fw_halted := dec_tlu_pmu_fw_halted + csr.io.lsu_fir_error := io.lsu_fir_error + csr.io.tlu_flush_lower_r_d1 := tlu_flush_lower_r_d1 + csr.io.dec_tlu_flush_noredir_r_d1 := dec_tlu_flush_noredir_r_d1 + csr.io.tlu_flush_path_r_d1 := tlu_flush_path_r_d1 + csr.io.reset_delayed := reset_delayed + csr.io.interrupt_valid_r := interrupt_valid_r + csr.io.i0_exception_valid_r := i0_exception_valid_r + csr.io.lsu_exc_valid_r := lsu_exc_valid_r + csr.io.mepc_trigger_hit_sel_pc_r := mepc_trigger_hit_sel_pc_r + csr.io.e4e5_int_clk := e4e5_int_clk + csr.io.lsu_i0_exc_r := lsu_i0_exc_r + csr.io.inst_acc_r := inst_acc_r + csr.io.inst_acc_second_r := inst_acc_second_r + csr.io.take_nmi := take_nmi + csr.io.lsu_error_pkt_addr_r := lsu_error_pkt_addr_r + csr.io.exc_cause_r := exc_cause_r + csr.io.i0_valid_wb := i0_valid_wb + csr.io.exc_or_int_valid_r_d1 := exc_or_int_valid_r_d1 + csr.io.interrupt_valid_r_d1 := interrupt_valid_r_d1 + csr.io.clk_override := clk_override + csr.io.i0_exception_valid_r_d1 := i0_exception_valid_r_d1 + csr.io.lsu_i0_exc_r_d1 := lsu_i0_exc_r_d1 + csr.io.exc_cause_wb := exc_cause_wb + csr.io.nmi_lsu_store_type := nmi_lsu_store_type + csr.io.nmi_lsu_load_type := nmi_lsu_load_type + csr.io.tlu_i0_commit_cmt := tlu_i0_commit_cmt + csr.io.ebreak_r := ebreak_r + csr.io.ecall_r := ecall_r + csr.io.illegal_r := illegal_r + csr.io.mdseac_locked_f := mdseac_locked_f + csr.io.nmi_int_detected_f := nmi_int_detected_f + csr.io.internal_dbg_halt_mode_f2 := internal_dbg_halt_mode_f2 + csr.io.ext_int_freeze_d1 := ext_int_freeze_d1 + csr.io.ic_perr_r_d1 := ic_perr_r_d1 + csr.io.iccm_sbecc_r_d1 := iccm_sbecc_r_d1 + csr.io.lsu_single_ecc_error_r_d1 := lsu_single_ecc_error_r_d1 + csr.io.ifu_miss_state_idle_f := ifu_miss_state_idle_f + csr.io.lsu_idle_any_f := lsu_idle_any_f + csr.io.dbg_tlu_halted_f := dbg_tlu_halted_f + csr.io.dbg_tlu_halted := dbg_tlu_halted + csr.io.debug_halt_req_f := debug_halt_req_f + csr.io.take_ext_int_start := take_ext_int_start + csr.io.trigger_hit_dmode_r_d1 := trigger_hit_dmode_r_d1 + csr.io.trigger_hit_r_d1 := trigger_hit_r_d1 + csr.io.dcsr_single_step_done_f := dcsr_single_step_done_f + csr.io.ebreak_to_debug_mode_r_d1 := ebreak_to_debug_mode_r_d1 + csr.io.debug_halt_req := debug_halt_req + csr.io.allow_dbg_halt_csr_write := allow_dbg_halt_csr_write + csr.io.internal_dbg_halt_mode_f := internal_dbg_halt_mode_f + csr.io.enter_debug_halt_req := enter_debug_halt_req + csr.io.internal_dbg_halt_mode := internal_dbg_halt_mode + csr.io.request_debug_mode_done := request_debug_mode_done + csr.io.request_debug_mode_r := request_debug_mode_r + csr.io.update_hit_bit_r := update_hit_bit_r + csr.io.take_timer_int := take_timer_int + csr.io.take_int_timer0_int := take_int_timer0_int + csr.io.take_int_timer1_int := take_int_timer1_int + csr.io.take_ext_int := take_ext_int + csr.io.tlu_flush_lower_r := tlu_flush_lower_r + csr.io.dec_tlu_br0_error_r := dec_tlu_br0_error_r + csr.io.dec_tlu_br0_start_error_r := dec_tlu_br0_start_error_r + csr.io.lsu_pmu_load_external_r := lsu_pmu_load_external_r + csr.io.lsu_pmu_store_external_r := lsu_pmu_store_external_r + csr.io.csr_pkt := csr_pkt + + npc_r := csr.io.npc_r + npc_r_d1 := csr.io.npc_r_d1 + mie_ns := csr.io.mie_ns + mepc := csr.io.mepc + mdseac_locked_ns := csr.io.mdseac_locked_ns + force_halt := csr.io.force_halt + dpc := csr.io.dpc + mstatus_mie_ns := csr.io.mstatus_mie_ns + dec_csr_wen_r_mod := csr.io.dec_csr_wen_r_mod + fw_halt_req := csr.io.fw_halt_req + mstatus := csr.io.mstatus + dcsr := csr.io.dcsr + mtvec := csr.io.mtvec + mip := csr.io.mip + mtdata1_t :=csr.io.mtdata1_t + val csr_read=Module(new el2_dec_decode_csr_read) + csr_read.io.dec_csr_rdaddr_d:=io.dec_csr_rdaddr_d + csr_pkt:=csr_read.io.csr_pkt + + io.dec_tlu_presync_d := csr_pkt.presync & io.dec_csr_any_unq_d & ~io.dec_csr_wen_unq_d + io.dec_tlu_postsync_d := csr_pkt.postsync & io.dec_csr_any_unq_d + + // allow individual configuration of these features + val conditionally_illegal = (csr_pkt.csr_mitcnt0 | csr_pkt.csr_mitcnt1 | csr_pkt.csr_mitb0 | csr_pkt.csr_mitb1 | csr_pkt.csr_mitctl0 | csr_pkt.csr_mitctl1) & ~TIMER_LEGAL_EN.asUInt + val valid_csr = ( csr_pkt.legal & (~(csr_pkt.csr_dcsr | csr_pkt.csr_dpc | csr_pkt.csr_dmst | csr_pkt.csr_dicawics | csr_pkt.csr_dicad0 | csr_pkt.csr_dicad0h | csr_pkt.csr_dicad1 | csr_pkt.csr_dicago) | dbg_tlu_halted_f) & ~fast_int_meicpct & ~conditionally_illegal) + + io.dec_csr_legal_d := ( io.dec_csr_any_unq_d &valid_csr & ~(io.dec_csr_wen_unq_d & (csr_pkt.csr_mvendorid | csr_pkt.csr_marchid | csr_pkt.csr_mimpid | csr_pkt.csr_mhartid | csr_pkt.csr_mdseac | csr_pkt.csr_meihap)) ) +} + +trait CSRs{ + val MISA = "h301".U(12.W) + val MVENDORID = "hf11".U(12.W) + val MARCHID = "hf12".U(12.W) + val MIMPID = "hf13".U(12.W) + val MHARTID = "hf14".U(12.W) + val MSTATUS = "h300".U(12.W) + val MTVEC = "h305".U(12.W) + val MIP = "h344".U(12.W) + val MIE = "h304".U(12.W) + val MCYCLEL = "hb00".U(12.W) + val MCYCLEH = "hb80".U(12.W) + val MINSTRETL = "hb02".U(12.W) + val MINSTRETH = "hb82".U(12.W) + val MSCRATCH = "h340".U(12.W) + val MEPC = "h341".U(12.W) + val MCAUSE = "h342".U(12.W) + val MSCAUSE = "h7ff".U(12.W) + val MTVAL = "h343".U(12.W) + val MCGC = "h7f8".U(12.W) + val MFDC = "h7f9".U(12.W) + val MCPC = "h7c2".U(12.W) + val MRAC = "h7c0".U(12.W) + val MDEAU = "hbc0".U(12.W) + val MDSEAC = "hfc0".U(12.W) + val MPMC = "h7c6".U(12.W) + val MICECT = "h7f0".U(12.W) + val MICCMECT = "h7f1".U(12.W) + val MDCCMECT = "h7f2".U(12.W) + val MFDHT = "h7ce".U(12.W) + val MFDHS = "h7cf".U(12.W) + val MEIVT = "hbc8".U(12.W) + val MEIHAP = "hfc8".U(12.W) + val MEICURPL = "hbcc".U(12.W) + val MEICIDPL = "hbcb".U(12.W) + val MEICPCT = "hbca".U(12.W) + val MEIPT = "hbc9".U(12.W) + val DCSR = "h7b0".U(12.W) + val DPC = "h7b1".U(12.W) + val DICAWICS = "h7c8".U(12.W) + val DICAD0 = "h7c9".U(12.W) + val DICAD0H = "h7cc".U(12.W) + val DICAD1 = "h7ca".U(12.W) + val DICAGO = "h7cb".U(12.W) + val MTSEL = "h7a0".U(12.W) + val MTDATA1 = "h7a1".U(12.W) + val MTDATA2 = "h7a2".U(12.W) + val MHPMC3 = "hB03".U(12.W) + val MHPMC3H = "hB83".U(12.W) + val MHPMC4 = "hB04".U(12.W) + val MHPMC4H = "hB84".U(12.W) + val MHPMC5 = "hB05".U(12.W) + val MHPMC5H = "hB85".U(12.W) + val MHPMC6 = "hB06".U(12.W) + val MHPMC6H = "hB86".U(12.W) + val MHPME3 = "h323".U(12.W) + val MHPME4 = "h324".U(12.W) + val MHPME5 = "h325".U(12.W) + val MHPME6 = "h326".U(12.W) + val MCOUNTINHIBIT = "h320".U(12.W) + val MSTATUS_MIE = 0.U + val MIP_MCEIP = 5.U + val MIP_MITIP0 = 4.U + val MIP_MITIP1 = 3.U + val MIP_MEIP = 2 + val MIP_MTIP = 1 + val MIP_MSIP = 0 + val MIE_MCEIE = 5 + val MIE_MITIE0 = 4 + val MIE_MITIE1 = 3 + val MIE_MEIE = 2 + val MIE_MTIE = 1 + val MIE_MSIE = 0 + val DCSR_EBREAKM = 15 + val DCSR_STEPIE = 11 + val DCSR_STOPC = 10 + val DCSR_STEP = 2 + val MTDATA1_DMODE = 9 + val MTDATA1_SEL = 7 + val MTDATA1_ACTION = 6 + val MTDATA1_CHAIN = 5 + val MTDATA1_MATCH = 4 + val MTDATA1_M_ENABLED = 3 + val MTDATA1_EXE = 2 + val MTDATA1_ST = 1 + val MTDATA1_LD = 0 + val MHPME_NOEVENT = 0.U + val MHPME_CLK_ACTIVE = 1.U // OOP - out of pipe + val MHPME_ICACHE_HIT = 2.U // OOP + val MHPME_ICACHE_MISS = 3.U // OOP + val MHPME_INST_COMMIT = 4.U + val MHPME_INST_COMMIT_16B = 5.U + val MHPME_INST_COMMIT_32B = 6.U + val MHPME_INST_ALIGNED = 7.U // OOP + val MHPME_INST_DECODED = 8.U // OOP + val MHPME_INST_MUL = 9.U + val MHPME_INST_DIV = 10.U + val MHPME_INST_LOAD = 11.U + val MHPME_INST_STORE = 12.U + val MHPME_INST_MALOAD = 13.U + val MHPME_INST_MASTORE = 14.U + val MHPME_INST_ALU = 15.U + val MHPME_INST_CSRREAD = 16.U + val MHPME_INST_CSRRW = 17.U + val MHPME_INST_CSRWRITE = 18.U + val MHPME_INST_EBREAK = 19.U + val MHPME_INST_ECALL = 20.U + val MHPME_INST_FENCE = 21.U + val MHPME_INST_FENCEI = 22.U + val MHPME_INST_MRET = 23.U + val MHPME_INST_BRANCH = 24.U + val MHPME_BRANCH_MP = 25.U + val MHPME_BRANCH_TAKEN = 26.U + val MHPME_BRANCH_NOTP = 27.U + val MHPME_FETCH_STALL = 28.U // OOP + val MHPME_ALGNR_STALL = 29.U // OOP + val MHPME_DECODE_STALL = 30.U // OOP + val MHPME_POSTSYNC_STALL = 31.U // OOP + val MHPME_PRESYNC_STALL = 32.U // OOP + val MHPME_LSU_SB_WB_STALL = 34.U // OOP + val MHPME_DMA_DCCM_STALL = 35.U // OOP + val MHPME_DMA_ICCM_STALL = 36.U // OOP + val MHPME_EXC_TAKEN = 37.U + val MHPME_TIMER_INT_TAKEN = 38.U + val MHPME_EXT_INT_TAKEN = 39.U + val MHPME_FLUSH_LOWER = 40.U + val MHPME_BR_ERROR = 41.U + val MHPME_IBUS_TRANS = 42.U // OOP + val MHPME_DBUS_TRANS = 43.U // OOP + val MHPME_DBUS_MA_TRANS = 44.U // OOP + val MHPME_IBUS_ERROR = 45.U // OOP + val MHPME_DBUS_ERROR = 46.U // OOP + val MHPME_IBUS_STALL = 47.U // OOP + val MHPME_DBUS_STALL = 48.U // OOP + val MHPME_INT_DISABLED = 49.U // OOP + val MHPME_INT_STALLED = 50.U // OOP + val MHPME_INST_BITMANIP = 54.U + val MHPME_DBUS_LOAD = 55.U + val MHPME_DBUS_STORE = 56.U + // Counts even during sleep state + val MHPME_SLEEP_CYC = 512.U // OOP + val MHPME_DMA_READ_ALL = 513.U // OOP + val MHPME_DMA_WRITE_ALL = 514.U // OOP + val MHPME_DMA_READ_DCCM = 515.U // OOP + val MHPME_DMA_WRITE_DCCM = 516.U // OOP + + +} +class el2_CSR_IO extends Bundle with el2_lib { + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val scan_mode = Input(Bool()) + val dec_csr_wrdata_r = Input(UInt(32.W)) + val dec_csr_wraddr_r = Input(UInt(12.W)) + val dec_csr_rdaddr_d = Input(UInt(12.W)) + val dec_csr_wen_unq_d = Input(UInt(1.W)) + val dec_i0_decode_d = Input(UInt(1.W)) + val dec_tlu_ic_diag_pkt = Output(new el2_cache_debug_pkt_t) + val ifu_ic_debug_rd_data_valid = Input(UInt(1.W)) + val trigger_pkt_any = Output(Vec(4, new el2_trigger_pkt_t)) + val ifu_pmu_bus_trxn = Input(UInt(1.W)) + val dma_iccm_stall_any = Input(UInt(1.W)) + val dma_dccm_stall_any = Input(UInt(1.W)) + val lsu_store_stall_any = Input(UInt(1.W)) + val dec_pmu_presync_stall = Input(UInt(1.W)) + val dec_pmu_postsync_stall = Input(UInt(1.W)) + val dec_pmu_decode_stall = Input(UInt(1.W)) + val ifu_pmu_fetch_stall = Input(UInt(1.W)) + val dec_tlu_packet_r = Input(new el2_trap_pkt_t) + val exu_pmu_i0_br_ataken = Input(UInt(1.W)) + val exu_pmu_i0_br_misp = Input(UInt(1.W)) + val dec_pmu_instr_decoded = Input(UInt(1.W)) + val ifu_pmu_instr_aligned = Input(UInt(1.W)) + val exu_pmu_i0_pc4 = Input(UInt(1.W)) + val ifu_pmu_ic_miss = Input(UInt(1.W)) + val ifu_pmu_ic_hit = Input(UInt(1.W)) + val dec_tlu_int_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_exc_valid_wb1 = Output(UInt(1.W)) + val dec_tlu_i0_valid_wb1 = Output(UInt(1.W)) + val dec_csr_wen_r = Input(UInt(1.W)) + //val dec_tlu_force_halt = Output(UInt(1.W)) + //val dec_tlu_flush_extint = Output(UInt(1.W)) + val dec_tlu_mtval_wb1 = Output(UInt(32.W)) + val dec_tlu_exc_cause_wb1 = Output(UInt(5.W)) + val dec_tlu_perfcnt0 = Output(UInt(1.W)) + val dec_tlu_perfcnt1 = Output(UInt(1.W)) + val dec_tlu_perfcnt2 = Output(UInt(1.W)) + val dec_tlu_perfcnt3 = Output(UInt(1.W)) + val dec_tlu_dbg_halted = Input(UInt(1.W)) + val dma_pmu_dccm_write = Input(UInt(1.W)) + val dma_pmu_dccm_read = Input(UInt(1.W)) + val dma_pmu_any_write = Input(UInt(1.W)) + val dma_pmu_any_read = Input(UInt(1.W)) + val lsu_pmu_bus_busy = Input(UInt(1.W)) + val dec_tlu_i0_pc_r = Input(UInt(31.W)) + val dec_tlu_i0_valid_r = Input(UInt(1.W)) + val dec_csr_stall_int_ff = Input(UInt(1.W)) + val dec_csr_any_unq_d = Input(UInt(1.W)) + val dec_tlu_misc_clk_override = Output(UInt(1.W)) + val dec_tlu_dec_clk_override = Output(UInt(1.W)) + val dec_tlu_ifu_clk_override = Output(UInt(1.W)) + val dec_tlu_lsu_clk_override = Output(UInt(1.W)) + val dec_tlu_bus_clk_override = Output(UInt(1.W)) + val dec_tlu_pic_clk_override = Output(UInt(1.W)) + val dec_tlu_dccm_clk_override = Output(UInt(1.W)) + val dec_tlu_icm_clk_override = Output(UInt(1.W)) + //val dec_csr_legal_d = Output(UInt(1.W)) + val dec_csr_rddata_d = Output(UInt(32.W)) + //val dec_tlu_postsync_d = Output(UInt(1.W)) + //val dec_tlu_presync_d = Output(UInt(1.W)) + //val dec_tlu_flush_pause_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_r = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_r = Output(UInt(1.W)) + //val dec_tlu_flush_lower_wb = Output(UInt(1.W)) + //val dec_tlu_i0_kill_writeb_wb = Output(UInt(1.W)) + // val dec_tlu_flush_leak_one_r = Output(UInt(1.W)) + //val dec_tlu_debug_stall = Output(UInt(1.W)) + val dec_tlu_pipelining_disable = Output(UInt(1.W)) + val dec_tlu_wr_pause_r = Output(UInt(1.W)) + val ifu_pmu_bus_busy = Input(UInt(1.W)) + val lsu_pmu_bus_error = Input(UInt(1.W)) + val ifu_pmu_bus_error = Input(UInt(1.W)) + val lsu_pmu_bus_misaligned = Input(UInt(1.W)) + val lsu_pmu_bus_trxn = Input(UInt(1.W)) + val ifu_ic_debug_rd_data = Input(UInt(71.W)) + val dec_tlu_meipt = Output(UInt(4.W)) + val pic_pl = Input(UInt(4.W)) + val dec_tlu_meicurpl = Output(UInt(4.W)) + val dec_tlu_meihap = Output(UInt(30.W)) + val pic_claimid = Input(UInt(8.W)) + val iccm_dma_sb_error = Input(UInt(1.W)) + val lsu_imprecise_error_addr_any = Input(UInt(32.W)) + val lsu_imprecise_error_load_any = Input(UInt(1.W)) + val lsu_imprecise_error_store_any = Input(UInt(1.W)) + val dec_tlu_mrac_ff = Output(UInt(32.W)) + val dec_tlu_wb_coalescing_disable = Output(UInt(1.W)) + val dec_tlu_bpred_disable = Output(UInt(1.W)) + val dec_tlu_sideeffect_posted_disable = Output(UInt(1.W)) + val dec_tlu_core_ecc_disable = Output(UInt(1.W)) + val dec_tlu_external_ldfwd_disable = Output(UInt(1.W)) + val dec_tlu_dma_qos_prty = Output(UInt(3.W)) + val dec_illegal_inst = Input(UInt(32.W)) + val lsu_error_pkt_r = Input(new el2_lsu_error_pkt_t) + val mexintpend = Input(UInt(1.W)) + val exu_npc_r = Input(UInt(31.W)) + val mpc_reset_run_req = Input(UInt(1.W)) + val rst_vec = Input(UInt(31.W)) + val core_id = Input(UInt(28.W)) + val dec_timer_rddata_d = Input(UInt(32.W)) + val dec_timer_read_d = Input(UInt(1.W)) + + + ////////////////////////////////////////////////// + val dec_csr_wen_r_mod = Output(UInt(1.W)) + val rfpc_i0_r = Input(UInt(1.W)) + val i0_trigger_hit_r = Input(UInt(1.W)) + val fw_halt_req = Output(UInt(1.W)) + val mstatus = Output(UInt(2.W)) + val exc_or_int_valid_r = Input(UInt(1.W)) // remove this after + val mret_r = Input(UInt(1.W)) + val mstatus_mie_ns = Output(UInt(1.W)) + val dcsr_single_step_running_f = Input(UInt(1.W)) + val dcsr = Output(UInt(16.W)) + val mtvec = Output(UInt(31.W)) + val mip = Output(UInt(6.W)) + val dec_timer_t0_pulse = Input(UInt(1.W)) + val dec_timer_t1_pulse = Input(UInt(1.W)) + val timer_int_sync = Input(UInt(1.W)) + val soft_int_sync = Input(UInt(1.W)) + val mie_ns = Output(UInt(6.W)) + val csr_wr_clk: Clock = Input(Clock()) // remove after + val ebreak_to_debug_mode_r = Input(UInt(1.W)) + val dec_tlu_pmu_fw_halted = Input(UInt(1.W)) + val lsu_fir_error = Input(UInt(2.W)) + val npc_r = Output(UInt(31.W)) + val tlu_flush_lower_r_d1 = Input(UInt(1.W)) + val dec_tlu_flush_noredir_r_d1 = Input(UInt(1.W)) + val tlu_flush_path_r_d1 = Input(UInt(31.W)) + val npc_r_d1 = Output(UInt(31.W)) + val reset_delayed = Input(UInt(1.W)) + val mepc = Output(UInt(31.W)) + val interrupt_valid_r = Input(UInt(1.W)) + val i0_exception_valid_r = Input(UInt(1.W)) //delete after + val lsu_exc_valid_r = Input(UInt(1.W)) + val mepc_trigger_hit_sel_pc_r = Input(UInt(1.W)) //delete after + val e4e5_int_clk = Input(Clock()) //delete after + val lsu_i0_exc_r = Input(UInt(1.W)) + val inst_acc_r = Input(UInt(1.W)) + val inst_acc_second_r = Input(UInt(1.W)) + val take_nmi = Input(UInt(1.W)) + val lsu_error_pkt_addr_r = Input(UInt(32.W)) + val exc_cause_r = Input(UInt(5.W)) + val i0_valid_wb = Input(UInt(1.W)) + val exc_or_int_valid_r_d1 = Input(UInt(1.W)) + val interrupt_valid_r_d1 = Input(UInt(1.W)) + val clk_override = Input(UInt(1.W)) + val i0_exception_valid_r_d1 = Input(UInt(1.W)) + val lsu_i0_exc_r_d1 = Input(UInt(1.W)) + val exc_cause_wb = Input(UInt(5.W)) + val nmi_lsu_store_type = Input(UInt(1.W)) + val nmi_lsu_load_type = Input(UInt(1.W)) + val tlu_i0_commit_cmt = Input(UInt(1.W)) + val ebreak_r = Input(UInt(1.W)) + val ecall_r = Input(UInt(1.W)) + val illegal_r = Input(UInt(1.W)) + val mdseac_locked_ns = Output(UInt(1.W)) + val mdseac_locked_f = Input(UInt(1.W)) + val nmi_int_detected_f = Input(UInt(1.W)) + val internal_dbg_halt_mode_f2 = Input(UInt(1.W)) + val ext_int_freeze_d1 = Input(UInt(1.W)) + val ic_perr_r_d1 = Input(UInt(1.W)) + val iccm_sbecc_r_d1 = Input(UInt(1.W)) + val lsu_single_ecc_error_r_d1 = Input(UInt(1.W)) + val ifu_miss_state_idle_f = Input(UInt(1.W)) + val lsu_idle_any_f = Input(UInt(1.W)) + val dbg_tlu_halted_f = Input(UInt(1.W)) + val dbg_tlu_halted = Input(UInt(1.W)) + val debug_halt_req_f = Input(UInt(1.W)) + val force_halt = Output(UInt(1.W)) + val take_ext_int_start = Input(UInt(1.W)) + val trigger_hit_dmode_r_d1 = Input(UInt(1.W)) + val trigger_hit_r_d1 = Input(UInt(1.W)) + val dcsr_single_step_done_f = Input(UInt(1.W)) + val ebreak_to_debug_mode_r_d1 = Input(UInt(1.W)) + val debug_halt_req = Input(UInt(1.W)) + val allow_dbg_halt_csr_write = Input(UInt(1.W)) + val internal_dbg_halt_mode_f = Input(UInt(1.W)) + val enter_debug_halt_req = Input(UInt(1.W)) + val internal_dbg_halt_mode = Input(UInt(1.W)) + val request_debug_mode_done = Input(UInt(1.W)) + val request_debug_mode_r = Input(UInt(1.W)) + val dpc = Output(UInt(31.W)) + val update_hit_bit_r = Input(UInt(4.W)) + val take_timer_int = Input(UInt(1.W)) + val take_int_timer0_int = Input(UInt(1.W)) + val take_int_timer1_int = Input(UInt(1.W)) + val take_ext_int = Input(UInt(1.W)) + val tlu_flush_lower_r = Input(UInt(1.W)) + val dec_tlu_br0_error_r = Input(UInt(1.W)) + val dec_tlu_br0_start_error_r = Input(UInt(1.W)) + val lsu_pmu_load_external_r = Input(UInt(1.W)) + val lsu_pmu_store_external_r = Input(UInt(1.W)) + val csr_pkt = Input(new el2_dec_tlu_csr_pkt) + val mtdata1_t = Output(Vec(4,UInt(10.W))) +} + +class csr_tlu extends Module with el2_lib with CSRs { + val io = IO(new el2_CSR_IO) + + ////////////////////////////////wires/////////////////////////////// + val miccme_ce_req = Wire(UInt(1.W)) + val mice_ce_req = Wire(UInt(1.W)) + val mdccme_ce_req = Wire(UInt(1.W)) + val pc_r_d1 = Wire(UInt(31.W)) + val mpmc_b_ns = Wire(UInt(1.W)) + val mpmc_b = Wire(UInt(1.W)) + val wr_mcycleh_r = WireInit(UInt(1.W), 0.U) + val mcycleh = WireInit(UInt(32.W),0.U) + val minstretl_inc = WireInit(UInt(33.W),0.U) + val wr_minstreth_r = WireInit(UInt(1.W),0.U) + val minstretl = WireInit(UInt(32.W),0.U) + val minstreth_inc = WireInit(UInt(32.W),0.U) + val minstreth = WireInit(UInt(32.W),0.U) + val mfdc_ns = WireInit(UInt(15.W),0.U) + val mfdc_int = WireInit(UInt(15.W),0.U) + val mhpmc6_incr = WireInit(UInt(64.W),0.U) + val mhpmc5_incr = WireInit(UInt(64.W),0.U) + val mhpmc4_incr = WireInit(UInt(64.W),0.U) + val perfcnt_halted = WireInit(UInt(1.W),0.U) + val mhpmc3_incr = WireInit(UInt(64.W),0.U) + val mhpme_vec = Wire(Vec(4,UInt(10.W))) + val mtdata2_t = Wire(Vec(4,UInt(32.W))) + val wr_meicpct_r = WireInit(UInt(1.W),0.U) + val force_halt_ctr_f = WireInit(UInt(32.W),0.U) + val mdccmect_inc = WireInit(UInt(27.W),0.U) + val miccmect_inc = WireInit(UInt(27.W),0.U) + val fw_halted = WireInit(UInt(1.W),0.U) + val micect_inc = WireInit(UInt(27.W),0.U) + val mdseac_en = WireInit(UInt(1.W),0.U) + val mie = WireInit(UInt(6.W),0.U) + val mcyclel = WireInit(UInt(32.W),0.U) + val mscratch = WireInit(UInt(32.W),0.U) + val mcause = WireInit(UInt(32.W),0.U) + val mscause = WireInit(UInt(4.W),0.U) + val mtval = WireInit(UInt(32.W),0.U) + val meicurpl = WireInit(UInt(4.W),0.U) + val meicidpl = WireInit(UInt(4.W),0.U) + val meipt = WireInit(UInt(4.W),0.U) + val mfdc = WireInit(UInt(19.W),0.U) + val mtsel = WireInit(UInt(2.W),0.U) + val micect = WireInit(UInt(32.W),0.U) + val miccmect = WireInit(UInt(32.W),0.U) + val mdccmect = WireInit(UInt(32.W),0.U) + val mhpmc3h = WireInit(UInt(32.W),0.U) + val mhpmc3 = WireInit(UInt(32.W),0.U) + val mhpmc4h = WireInit(UInt(32.W),0.U) + val mhpmc4 = WireInit(UInt(32.W),0.U) + val mhpmc5h = WireInit(UInt(32.W),0.U) + val mhpmc5 = WireInit(UInt(32.W),0.U) + val mhpmc6h = WireInit(UInt(32.W),0.U) + val mhpmc6 = WireInit(UInt(32.W),0.U) + val mhpme3 = WireInit(UInt(10.W),0.U) + val mhpme4 = WireInit(UInt(10.W),0.U) + val mhpme5 = WireInit(UInt(10.W),0.U) + val mhpme6 = WireInit(UInt(10.W),0.U) + val mfdht = WireInit(UInt(6.W),0.U) + val mfdhs = WireInit(UInt(2.W),0.U) + val mcountinhibit = WireInit(UInt(7.W),0.U) + val mpmc = WireInit(UInt(1.W),0.U) + val dicad1 = WireInit(UInt(32.W),0.U) + ///////////////////////////////////////////////////////////////////////// + //---------------------------------------------------------------------- + // + // CSRs + // + //---------------------------------------------------------------------- + + // ---------------------------------------------------------------------- + // MSTATUS (RW) + // [12:11] MPP : Prior priv level, always 2'b11, not flopped + // [7] MPIE : Int enable previous [1] + // [3] MIE : Int enable [0] + + //When executing a MRET instruction, supposing MPP holds the value 3, MIE + //is set to MPIE; the privilege mode is changed to 3; MPIE is set to 1; and MPP is set to 3 + + io.dec_csr_wen_r_mod := io.dec_csr_wen_r & !io.i0_trigger_hit_r & !io.rfpc_i0_r + val wr_mstatus_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSTATUS) + + // set this even if we don't go to fwhalt due to debug halt. We committed the inst, so ... + val set_mie_pmu_fw_halt = !mpmc_b_ns & io.fw_halt_req + + val mstatus_ns = Mux1H(Seq( + (!wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.mstatus(MSTATUS_MIE)), + (wr_mstatus_r & io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(3)), + (io.mret_r & !io.exc_or_int_valid_r).asBool -> Cat(1.U, io.mstatus(1)), + (set_mie_pmu_fw_halt).asBool -> Cat(io.mstatus(1), 1.U), + (wr_mstatus_r & !io.exc_or_int_valid_r).asBool -> Cat(io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), + (!wr_mstatus_r & !io.exc_or_int_valid_r & !io.mret_r & !set_mie_pmu_fw_halt).asBool -> io.mstatus)) + + // gate MIE if we are single stepping and DCSR[STEPIE] is off + io.mstatus_mie_ns := io.mstatus(MSTATUS_MIE) & (~io.dcsr_single_step_running_f | io.dcsr(DCSR_STEPIE)) + io.mstatus := withClock(io.free_clk) { + RegNext(mstatus_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MTVEC (RW) + // [31:2] BASE : Trap vector base address + // [1] - Reserved, not implemented, reads zero + // [0] MODE : 0 = Direct, 1 = Asyncs are vectored to BASE + (4 * CAUSE) + + val wr_mtvec_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVEC) + val mtvec_ns = Cat(io.dec_csr_wrdata_r(31, 2), io.dec_csr_wrdata_r(0)) + io.mtvec := rvdffe(mtvec_ns, wr_mtvec_r.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MIP (RW) + // + // [30] MCEIP : (RO) M-Mode Correctable Error interrupt pending + // [29] MITIP0 : (RO) M-Mode Internal Timer0 interrupt pending + // [28] MITIP1 : (RO) M-Mode Internal Timer1 interrupt pending + // [11] MEIP : (RO) M-Mode external interrupt pending + // [7] MTIP : (RO) M-Mode timer interrupt pending + // [3] MSIP : (RO) M-Mode software interrupt pending + + val ce_int = (mdccme_ce_req | miccme_ce_req | mice_ce_req) + + val mip_ns = Cat(ce_int, io.dec_timer_t0_pulse, io.dec_timer_t1_pulse, io.mexintpend, io.timer_int_sync, io.soft_int_sync) + io.mip := withClock(io.free_clk) { + RegNext(mip_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MIE (RW) + // [30] MCEIE : (RO) M-Mode Correctable Error interrupt enable + // [29] MITIE0 : (RO) M-Mode Internal Timer0 interrupt enable + // [28] MITIE1 : (RO) M-Mode Internal Timer1 interrupt enable + // [11] MEIE : (RW) M-Mode external interrupt enable + // [7] MTIE : (RW) M-Mode timer interrupt enable + // [3] MSIE : (RW) M-Mode software interrupt enable + + val wr_mie_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MIE) + io.mie_ns := Mux(wr_mie_r.asBool, Cat(io.dec_csr_wrdata_r(30, 28), io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(3)), mie) + mie := withClock(io.csr_wr_clk) { + RegNext(io.mie_ns,0.U) + } + + // ---------------------------------------------------------------------- + // MCYCLEL (RW) + // [31:0] : Lower Cycle count + + val kill_ebreak_count_r = io.ebreak_to_debug_mode_r & io.dcsr(DCSR_STOPC) + + val wr_mcyclel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEL) + + val mcyclel_cout_in = ~(kill_ebreak_count_r | (io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted | mcountinhibit(0)) + + + val mcyclel_inc = WireInit(UInt(33.W),0.U) + mcyclel_inc := mcyclel + Cat(0.U(31.W), mcyclel_cout_in) + val mcyclel_ns = Mux(wr_mcyclel_r.asBool, io.dec_csr_wrdata_r, mcyclel_inc) + val mcyclel_cout = mcyclel_inc(32).asBool + mcyclel := rvdffe(mcyclel_ns, (wr_mcyclel_r | mcyclel_cout_in.asUInt).asBool, clock, io.scan_mode) + val mcyclel_cout_f = withClock(io.free_clk) {RegNext((mcyclel_cout & !wr_mcycleh_r),0.U)} + // ---------------------------------------------------------------------- + // MCYCLEH (RW) + // [63:32] : Higher Cycle count + // Chained with mcyclel. Note: mcyclel overflow due to a mcycleh write gets ignored. + + wr_mcycleh_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCYCLEH) + + val mcycleh_inc = mcycleh + Cat(0.U(31.W), mcyclel_cout_f) + val mcycleh_ns = Mux(wr_mcycleh_r.asBool, io.dec_csr_wrdata_r, mcycleh_inc) + + mcycleh := rvdffe(mcycleh_ns, (wr_mcycleh_r | mcyclel_cout_f).asBool, clock, io.scan_mode) + + + // ---------------------------------------------------------------------- + // MINSTRETL (RW) + // [31:0] : Lower Instruction retired count + // From the spec "Some CSRs, such as the instructions retired counter, instret, may be modified as side effects + // of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the + // value prior to the execution of the instruction. If a CSR access instruction writes a CSR, the + // update occurs after the execution of the instruction. In particular, a value written to instret by + // one instruction will be the value read by the following instruction (i.e., the increment of instret + // caused by the first instruction retiring happens before the write of the new value)." + + + val i0_valid_no_ebreak_ecall_r = io.tlu_i0_commit_cmt & ~(io.ebreak_r | io.ecall_r | io.ebreak_to_debug_mode_r | io.illegal_r | mcountinhibit(2)).asBool + + val wr_minstretl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETL) + + minstretl_inc := minstretl + Cat(0.U(31.W),i0_valid_no_ebreak_ecall_r) + val minstretl_cout = minstretl_inc(32) + val minstret_enable = (i0_valid_no_ebreak_ecall_r | wr_minstretl_r).asBool + + val minstretl_ns = Mux(wr_minstretl_r.asBool, io.dec_csr_wrdata_r , minstretl_inc) + minstretl := rvdffe(minstretl_ns,minstret_enable.asBool,clock,io.scan_mode) + val minstret_enable_f = withClock(io.free_clk){RegNext(minstret_enable,0.U)} + val minstretl_cout_f = withClock(io.free_clk){RegNext((minstretl_cout & ~wr_minstreth_r),0.U)} + + val minstretl_read = minstretl + // ---------------------------------------------------------------------- + // MINSTRETH (RW) + // [63:32] : Higher Instret count + // Chained with minstretl. Note: minstretl overflow due to a minstreth write gets ignored. + + wr_minstreth_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MINSTRETH)).asBool + + + minstreth_inc := minstreth + Cat(0.U(31.W), minstretl_cout_f) + val minstreth_ns = Mux(wr_minstreth_r.asBool, io.dec_csr_wrdata_r, minstreth_inc) + + minstreth := rvdffe(minstreth_ns, (minstret_enable_f | wr_minstreth_r).asBool, clock, io.scan_mode) + + val minstreth_read = minstreth_inc + + // ---------------------------------------------------------------------- + // mscratch (RW) + // [31:0] : Scratch register + + val wr_mscratch_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCRATCH) + + mscratch := rvdffe(io.dec_csr_wrdata_r,wr_mscratch_r.asBool,clock,io.scan_mode) + + + // ---------------------------------------------------------------------- + // MEPC (RW) + // [31:1] : Exception PC + + // NPC + + val sel_exu_npc_r = !io.dec_tlu_dbg_halted & !io.tlu_flush_lower_r_d1 & io.dec_tlu_i0_valid_r + val sel_flush_npc_r = !io.dec_tlu_dbg_halted & io.tlu_flush_lower_r_d1 & !io.dec_tlu_flush_noredir_r_d1 + val sel_hold_npc_r = !sel_exu_npc_r & !sel_flush_npc_r + + io.npc_r := Mux1H(Seq( + sel_exu_npc_r.asBool -> io.exu_npc_r, + (!io.mpc_reset_run_req & io.reset_delayed).asBool -> io.rst_vec, // init to reset vector for mpc halt on reset case + sel_flush_npc_r.asBool -> io.tlu_flush_path_r_d1, + sel_hold_npc_r.asBool -> io.npc_r_d1 )) + + io.npc_r_d1 := rvdffe(io.npc_r,(sel_exu_npc_r | sel_flush_npc_r | io.reset_delayed).asBool,clock,io.scan_mode) + // PC has to be captured for exceptions and interrupts. For MRET, we could execute it and then take an + // interrupt before the next instruction. + val pc0_valid_r = (!io.dec_tlu_dbg_halted & io.dec_tlu_i0_valid_r).asBool + + val pc_r = Mux1H( Seq( + pc0_valid_r -> io.dec_tlu_i0_pc_r, + ~pc0_valid_r -> pc_r_d1 )) + + pc_r_d1 := rvdffe(pc_r, pc0_valid_r, clock, io.scan_mode) + + val wr_mepc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEPC) + + val mepc_ns = Mux1H( Seq( + (io.i0_exception_valid_r | io.lsu_exc_valid_r | io.mepc_trigger_hit_sel_pc_r).asBool -> pc_r, + (io.interrupt_valid_r).asBool -> io.npc_r, + (wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(31,1), + (!wr_mepc_r & !io.exc_or_int_valid_r).asBool -> io.mepc) ) + + io.mepc := withClock(io.e4e5_int_clk){RegNext(mepc_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MCAUSE (RW) + // [31:0] : Exception Cause + + val wr_mcause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCAUSE) + val mcause_sel_nmi_store = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_store_type + val mcause_sel_nmi_load = io.exc_or_int_valid_r & io.take_nmi & io.nmi_lsu_load_type + val mcause_sel_nmi_ext = io.exc_or_int_valid_r & io.take_nmi & io.lsu_fir_error.orR + // FIR value decoder + // 0 –no error + // 1 –uncorrectable ecc => f000_1000 + // 2 –dccm region access error => f000_1001 + // 3 –non dccm region access error => f000_1002 + val mcause_fir_error_type = Cat(io.lsu_fir_error.andR, (io.lsu_fir_error(1) & ~io.lsu_fir_error(0))) + + val mcause_ns = Mux1H(Seq( + mcause_sel_nmi_store.asBool -> "hf000_0000".U(32.W), + mcause_sel_nmi_load.asBool -> "hf000_0001".U(32.W), + mcause_sel_nmi_ext.asBool -> Cat("hf000_100".U(28.W), 0.U(2.W), mcause_fir_error_type), + (io.exc_or_int_valid_r & ~io.take_nmi).asBool -> Cat(io.interrupt_valid_r, 0.U(26.W), io.exc_cause_r), + (wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r, + (~wr_mcause_r & ~io.exc_or_int_valid_r).asBool -> mcause) ) + + mcause := withClock(io.e4e5_int_clk){RegNext(mcause_ns,0.U)} + + + // ---------------------------------------------------------------------- + // MSCAUSE (RW) + // [2:0] : Secondary exception Cause + + val wr_mscause_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MSCAUSE) + + val ifu_mscause = Mux((io.dec_tlu_packet_r.icaf_type === 0.U(2.W)), "b1001".U, Cat(0.U(2.W) , io.dec_tlu_packet_r.icaf_type)) + + val mscause_type = Mux1H( Seq( + io.lsu_i0_exc_r.asBool -> io.lsu_error_pkt_r.mscause, + io.i0_trigger_hit_r.asBool -> "b0001".U, + io.ebreak_r.asBool -> "b0010".U, + io.inst_acc_r.asBool -> ifu_mscause )) + + + val mscause_ns = Mux1H( Seq( + (io.exc_or_int_valid_r).asBool -> mscause_type, + (wr_mscause_r & !io.exc_or_int_valid_r).asBool -> io.dec_csr_wrdata_r(3,0), + (!wr_mscause_r & !io.exc_or_int_valid_r).asBool -> mscause)) + + mscause := withClock(io.e4e5_int_clk){RegNext(mscause_ns,0.U)} + + // ---------------------------------------------------------------------- + // MTVAL (RW) + // [31:0] : Exception address if relevant + + + val wr_mtval_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTVAL) + val mtval_capture_pc_r = io.exc_or_int_valid_r & (io.ebreak_r | (io.inst_acc_r & ~io.inst_acc_second_r) | io.mepc_trigger_hit_sel_pc_r) & ~io.take_nmi + val mtval_capture_pc_plus2_r = io.exc_or_int_valid_r & (io.inst_acc_r & io.inst_acc_second_r) & ~io.take_nmi + val mtval_capture_inst_r = io.exc_or_int_valid_r & io.illegal_r & ~io.take_nmi + val mtval_capture_lsu_r = io.exc_or_int_valid_r & io.lsu_exc_valid_r & ~io.take_nmi + val mtval_clear_r = io.exc_or_int_valid_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_capture_lsu_r & ~io.mepc_trigger_hit_sel_pc_r + + + val mtval_ns = Mux1H(Seq( + (mtval_capture_pc_r).asBool -> Cat(pc_r, 0.U(1.W)), + (mtval_capture_pc_plus2_r).asBool -> Cat(pc_r + 1.U(31.W), 0.U(1.W)), + (mtval_capture_inst_r).asBool -> io.dec_illegal_inst, + (mtval_capture_lsu_r).asBool -> io.lsu_error_pkt_addr_r, + (wr_mtval_r & ~io.interrupt_valid_r.asUInt).asBool -> io.dec_csr_wrdata_r, + (~io.take_nmi & ~wr_mtval_r & ~mtval_capture_pc_r & ~mtval_capture_inst_r & ~mtval_clear_r & ~mtval_capture_lsu_r).asBool -> mtval )) + + mtval := withClock(io.e4e5_int_clk){RegNext(mtval_ns,0.U)} + + // ---------------------------------------------------------------------- + // MCGC (RW) Clock gating control + // [31:9] : Reserved, reads 0x0 + // [8] : misc_clk_override + // [7] : dec_clk_override + // [6] : unused + // [5] : ifu_clk_override + // [4] : lsu_clk_override + // [3] : bus_clk_override + // [2] : pic_clk_override + // [1] : dccm_clk_override + // [0] : icm_clk_override + // + val wr_mcgc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCGC) + + val mcgc = rvdffe(io.dec_csr_wrdata_r(8,0),wr_mcgc_r.asBool,clock,io.scan_mode) + + io.dec_tlu_misc_clk_override := mcgc(8) + io.dec_tlu_dec_clk_override := mcgc(7) + io.dec_tlu_ifu_clk_override := mcgc(5) + io.dec_tlu_lsu_clk_override := mcgc(4) + io.dec_tlu_bus_clk_override := mcgc(3) + io.dec_tlu_pic_clk_override := mcgc(2) + io.dec_tlu_dccm_clk_override := mcgc(1) + io.dec_tlu_icm_clk_override := mcgc(0) + + // ---------------------------------------------------------------------- + // MFDC (RW) Feature Disable Control + // [31:19] : Reserved, reads 0x0 + // [18:16] : DMA QoS Prty + // [15:12] : Reserved, reads 0x0 + // [11] : Disable external load forwarding + // [10] : Disable dual issue + // [9] : Disable pic multiple ints + // [8] : Disable core ecc + // [7] : Unused, 0x0 + // [6] : Disable Sideeffect lsu posting + // [5:4] : Unused, 0x0 + // [3] : Disable branch prediction and return stack + // [2] : Disable write buffer coalescing + // [1] : Unused, 0x0 + // [0] : Disable pipelining - Enable single instruction execution + // + val wr_mfdc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDC) + + + + mfdc_int := rvdffe(mfdc_ns,wr_mfdc_r.asBool,clock,io.scan_mode) + // rvdffe #(15) mfdc_ff (.*, .en(wr_mfdc_r), .din({mfdc_ns[14:0]}), .dout(mfdc_int[14:0])); + + if(BUILD_AXI4 == true){ + // flip poweron value of bit 6 for AXI build + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,7), ~io.dec_csr_wrdata_r(6), io.dec_csr_wrdata_r(5,0)) + mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,7), ~mfdc_int(6), mfdc_int(5,0)) + } + else { + mfdc_ns := Cat(~io.dec_csr_wrdata_r(18,16),io.dec_csr_wrdata_r(11,0)) + mfdc := Cat(~mfdc_int(14,12),0.U(4.W), mfdc_int(11,0)) + } + + + io.dec_tlu_dma_qos_prty := mfdc(18,16) + io.dec_tlu_external_ldfwd_disable := mfdc(11) + io.dec_tlu_core_ecc_disable := mfdc(8) + io.dec_tlu_sideeffect_posted_disable := mfdc(6) + io.dec_tlu_bpred_disable := mfdc(3) + io.dec_tlu_wb_coalescing_disable := mfdc(2) + io.dec_tlu_pipelining_disable := mfdc(0) + + + // ---------------------------------------------------------------------- + // MCPC (RW) Pause counter + // [31:0] : Reads 0x0, decs in the wb register in decode_ctl + + + + io.dec_tlu_wr_pause_r := io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCPC) & ~io.interrupt_valid_r & ~io.take_ext_int_start + + + // ---------------------------------------------------------------------- + // MRAC (RW) + // [31:0] : Region Access Control Register, 16 regions, {side_effect, cachable} pairs + + val wr_mrac_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MRAC) + + // prevent pairs of 0x11, side_effect and cacheable + val mrac_in = Cat(io.dec_csr_wrdata_r(31), io.dec_csr_wrdata_r(30) & ~io.dec_csr_wrdata_r(31), + io.dec_csr_wrdata_r(29), io.dec_csr_wrdata_r(28) & ~io.dec_csr_wrdata_r(29), + io.dec_csr_wrdata_r(27), io.dec_csr_wrdata_r(26) & ~io.dec_csr_wrdata_r(27), + io.dec_csr_wrdata_r(25), io.dec_csr_wrdata_r(24) & ~io.dec_csr_wrdata_r(25), + io.dec_csr_wrdata_r(23), io.dec_csr_wrdata_r(22) & ~io.dec_csr_wrdata_r(23), + io.dec_csr_wrdata_r(21), io.dec_csr_wrdata_r(20) & ~io.dec_csr_wrdata_r(21), + io.dec_csr_wrdata_r(19), io.dec_csr_wrdata_r(18) & ~io.dec_csr_wrdata_r(19), + io.dec_csr_wrdata_r(17), io.dec_csr_wrdata_r(16) & ~io.dec_csr_wrdata_r(17), + io.dec_csr_wrdata_r(15), io.dec_csr_wrdata_r(14) & ~io.dec_csr_wrdata_r(15), + io.dec_csr_wrdata_r(13), io.dec_csr_wrdata_r(12) & ~io.dec_csr_wrdata_r(13), + io.dec_csr_wrdata_r(11), io.dec_csr_wrdata_r(10) & ~io.dec_csr_wrdata_r(11), + io.dec_csr_wrdata_r(9), io.dec_csr_wrdata_r(8) & ~io.dec_csr_wrdata_r(9), + io.dec_csr_wrdata_r(7), io.dec_csr_wrdata_r(6) & ~io.dec_csr_wrdata_r(7), + io.dec_csr_wrdata_r(5), io.dec_csr_wrdata_r(4) & ~io.dec_csr_wrdata_r(5), + io.dec_csr_wrdata_r(3), io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(3), + io.dec_csr_wrdata_r(1), io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(1)) + + + val mrac = rvdffe(mrac_in,wr_mrac_r.asBool,clock,io.scan_mode) + // drive to LSU/IFU + io.dec_tlu_mrac_ff := mrac + + + // ---------------------------------------------------------------------- + // MDEAU (WAR0) + // [31:0] : Dbus Error Address Unlock register + // + + val wr_mdeau_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDEAU) + + + // ---------------------------------------------------------------------- + // MDSEAC (R) + // [31:0] : Dbus Store Error Address Capture register + // + + + // only capture error bus if the MDSEAC reg is not locked + io.mdseac_locked_ns := mdseac_en | (io.mdseac_locked_f & ~wr_mdeau_r) + + mdseac_en := (io.lsu_imprecise_error_store_any | io.lsu_imprecise_error_load_any) & ~io.nmi_int_detected_f & ~io.mdseac_locked_f + + val mdseac = rvdffe(io.lsu_imprecise_error_addr_any,mdseac_en.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MPMC (R0W1) + // [0] : FW halt + // [1] : Set MSTATUS[MIE] on halt + + + + val wr_mpmc_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MPMC) + + // allow the cycle of the dbg halt flush that contains the wr_mpmc_r to + // set the io.mstatus bit potentially, use delayed version of internal dbg halt. + io.fw_halt_req := wr_mpmc_r & io.dec_csr_wrdata_r(0) & ~io.internal_dbg_halt_mode_f2 & ~io.ext_int_freeze_d1 + + val fw_halted_ns = (io.fw_halt_req | fw_halted) & ~set_mie_pmu_fw_halt + mpmc_b_ns := Mux(wr_mpmc_r.asBool, ~io.dec_csr_wrdata_r(1), ~mpmc) + + mpmc_b := withClock(io.csr_wr_clk){RegNext(mpmc_b_ns,0.U)} + fw_halted := withClock(io.free_clk){RegNext(fw_halted_ns,0.U)} + + mpmc := ~mpmc_b + + // ---------------------------------------------------------------------- + // MICECT (I-Cache error counter/threshold) + // [31:27] : Icache parity error threshold + // [26:0] : Icache parity error count + + + + val csr_sat = Mux((io.dec_csr_wrdata_r(31,27) > 26.U(5.W)), 26.U(5.W), io.dec_csr_wrdata_r(31,27)) + + val wr_micect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICECT) + micect_inc := micect + Cat(0.U(26.W), io.ic_perr_r_d1) + val micect_ns = Mux(wr_micect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(micect(31,27), micect_inc)) + + micect := rvdffe(micect_ns,(wr_micect_r | io.ic_perr_r_d1).asBool,clock,io.scan_mode) + + mice_ce_req := ("hffffffff".U(32.W) << micect(31,27)).orR & Cat(0.U(5.W), micect(26,0)) + + // ---------------------------------------------------------------------- + // MICCMECT (ICCM error counter/threshold) + // [31:27] : ICCM parity error threshold + // [26:0] : ICCM parity error count + + + + val wr_miccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MICCMECT) + miccmect_inc := miccmect(26,0) + Cat(0.U(26.W), (io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error)) + val miccmect_ns = Mux(wr_miccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(miccmect(31,27), miccmect_inc)) + + miccmect := rvdffe(miccmect_ns,(wr_miccmect_r | io.iccm_sbecc_r_d1 | io.iccm_dma_sb_error).asBool,clock,io.scan_mode) + miccme_ce_req := (("hffffffff".U(32.W) << miccmect(31,27)) & Cat(0.U(5.W), miccmect(26,0))).orR + + // ---------------------------------------------------------------------- + // MDCCMECT (DCCM error counter/threshold) + // [31:27] : DCCM parity error threshold + // [26:0] : DCCM parity error count + + + + val wr_mdccmect_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MDCCMECT) + mdccmect_inc := mdccmect(26,0) + Cat(0.U(26.W), io.lsu_single_ecc_error_r_d1) + val mdccmect_ns = Mux(wr_mdccmect_r.asBool, Cat(csr_sat, io.dec_csr_wrdata_r(26,0)) , Cat(mdccmect(31,27), mdccmect_inc)) + + mdccmect := rvdffe(mdccmect_ns, (wr_mdccmect_r | io.lsu_single_ecc_error_r_d1).asBool, clock, io.scan_mode) + + mdccme_ce_req := (("hffffffff".U(32.W) << mdccmect(31,27)) & Cat(0.U(5.W), mdccmect(26,0))).orR + + + // ---------------------------------------------------------------------- + // MFDHT (Force Debug Halt Threshold) + // [5:1] : Halt timeout threshold (power of 2) + // [0] : Halt timeout enabled + + + + val wr_mfdht_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHT) + + val mfdht_ns = Mux(wr_mfdht_r.asBool, io.dec_csr_wrdata_r(5,0) , mfdht) + + mfdht := withClock(io.active_clk){RegNext(mfdht_ns,0.U)} + + // ---------------------------------------------------------------------- + // MFDHS(RW) + // [1] : LSU operation pending when debug halt threshold reached + // [0] : IFU operation pending when debug halt threshold reached + + + + val wr_mfdhs_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MFDHS) + + val mfdhs_ns = Mux(wr_mfdhs_r.asBool, io.dec_csr_wrdata_r(1,0) , + Mux((io.dbg_tlu_halted & ~io.dbg_tlu_halted_f).asBool, Cat(~io.lsu_idle_any_f, ~io.ifu_miss_state_idle_f) , mfdhs)) + + mfdhs := withClock(io.active_clk){RegEnable(mfdhs_ns,0.U,(wr_mfdhs_r | io.dbg_tlu_halted).asBool)} + + val force_halt_ctr = Mux(io.debug_halt_req_f.asBool, (force_halt_ctr_f + 1.U(32.W)) , + Mux(io.dbg_tlu_halted_f.asBool, 0.U(32.W) , force_halt_ctr_f)) + + force_halt_ctr_f := withClock(io.active_clk){RegEnable(force_halt_ctr,0.U,mfdht(0))} + + io.force_halt := mfdht(0) & (force_halt_ctr_f & ("hffffffff".U(32.W) << mfdht(5,1))).orR + + + // ---------------------------------------------------------------------- + // MEIVT (External Interrupt Vector Table (R/W)) + // [31:10]: Base address (R/W) + // [9:0] : Reserved, reads 0x0 + + val wr_meivt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIVT) + + val meivt = rvdffe(io.dec_csr_wrdata_r(31,10),wr_meivt_r.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MEIHAP (External Interrupt Handler Access Pointer (R)) + // [31:10]: Base address (R/W) + // [9:2] : ClaimID (R) + // [1:0] : Reserved, 0x0 + + + + val wr_meihap_r = wr_meicpct_r + + val meihap = rvdffe(io.pic_claimid,wr_meihap_r.asBool,clock,io.scan_mode) + io.dec_tlu_meihap := Cat(meivt, meihap,0.U(2.W)) + + // ---------------------------------------------------------------------- + // MEICURPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : CURRPRI - Priority level of current interrupt service routine (R/W) + + + + val wr_meicurpl_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICURPL) + val meicurpl_ns = Mux(wr_meicurpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicurpl) + + meicurpl := withClock(io.csr_wr_clk){RegNext(meicurpl_ns,0.U)} + // PIC needs this reg + io.dec_tlu_meicurpl := meicurpl + + + // ---------------------------------------------------------------------- + // MEICIDPL (R/W) + // [31:4] : Reserved (read 0x0) + // [3:0] : External Interrupt Claim ID's Priority Level Register + + + + val wr_meicidpl_r = (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICIDPL)) | io.take_ext_int_start + + val meicidpl_ns = Mux(wr_meicpct_r.asBool, io.pic_pl, + Mux(wr_meicidpl_r.asBool, io.dec_csr_wrdata_r(3,0) , meicidpl)) + + meicidpl := withClock(io.free_clk){RegNext(meicidpl_ns,0.U)} + + // ---------------------------------------------------------------------- + // MEICPCT (Capture CLAIMID in MEIHAP and PL in MEICIDPL + // [31:1] : Reserved (read 0x0) + // [0] : Capture (W1, Read 0) + + wr_meicpct_r := (io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEICPCT)) | io.take_ext_int_start + + // ---------------------------------------------------------------------- + // MEIPT (External Interrupt Priority Threshold) + // [31:4] : Reserved (read 0x0) + // [3:0] : PRITHRESH + + + + val wr_meipt_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MEIPT) + val meipt_ns = Mux(wr_meipt_r.asBool, io.dec_csr_wrdata_r(3,0), meipt) + + meipt := withClock(io.active_clk){RegNext(meipt_ns,0.U)} + // to PIC + io.dec_tlu_meipt := meipt + + // ---------------------------------------------------------------------- + // DCSR (R/W) (Only accessible in debug mode) + // [31:28] : xdebugver (hard coded to 0x4) RO + // [27:16] : 0x0, reserved + // [15] : ebreakm + // [14] : 0x0, reserved + // [13] : ebreaks (0x0 for this core) + // [12] : ebreaku (0x0 for this core) + // [11] : stepie + // [10] : stopcount + // [9] : 0x0 //stoptime + // [8:6] : cause (RO) + // [5:4] : 0x0, reserved + // [3] : nmip + // [2] : step + // [1:0] : prv (0x3 for this core) + // + + // RV has clarified that 'priority 4' in the spec means top priority. + // 4. single step. 3. Debugger request. 2. Ebreak. 1. Trigger. + + // RV debug spec indicates a cause priority change for trigger hits during single step. + + + val trigger_hit_for_dscr_cause_r_d1 = io.trigger_hit_dmode_r_d1 | (io.trigger_hit_r_d1 & io.dcsr_single_step_done_f); + + val dcsr_cause = Mux1H(Seq( + (io.dcsr_single_step_done_f & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1 & ~io.debug_halt_req).asBool -> "b100".U(3.W), + (io.debug_halt_req & ~io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b011".U(3.W), + (io.ebreak_to_debug_mode_r_d1 & ~trigger_hit_for_dscr_cause_r_d1).asBool -> "b001".U(3.W), + (trigger_hit_for_dscr_cause_r_d1).asBool -> "b010".U(3.W) )) + + val wr_dcsr_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DCSR) + + + + // Multiple halt enter requests can happen before we are halted. + // We have to continue to upgrade based on dcsr_cause priority but we can't downgrade. + val dcsr_cause_upgradeable = io.internal_dbg_halt_mode_f & (io.dcsr(8,6) === "b011".U(3.W)) + val enter_debug_halt_req_le = io.enter_debug_halt_req & (~io.dbg_tlu_halted | dcsr_cause_upgradeable) + + val nmi_in_debug_mode = io.nmi_int_detected_f & io.internal_dbg_halt_mode_f + val dcsr_ns = Mux(enter_debug_halt_req_le.asBool, Cat(io.dcsr(15,9), dcsr_cause, io.dcsr(5,2),"b11".U(2.W)) ,//prv 0x3 for this core + Mux(wr_dcsr_r.asBool, Cat(io.dec_csr_wrdata_r(15), 0.U(3.W), io.dec_csr_wrdata_r(11,10), 0.U(1.W), io.dcsr(8,6), 0.U(2.W), nmi_in_debug_mode | io.dcsr(3), io.dec_csr_wrdata_r(2), "b11".U(2.W)) , Cat(io.dcsr(15,4), nmi_in_debug_mode, io.dcsr(2),"b11".U(2.W)))) + + io.dcsr := rvdffe(dcsr_ns, (enter_debug_halt_req_le | wr_dcsr_r | io.internal_dbg_halt_mode | io.take_nmi).asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // DPC (R/W) (Only accessible in debug mode) + // [31:0] : Debug PC + + + + val wr_dpc_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DPC) + val dpc_capture_npc = io.dbg_tlu_halted & ~io.dbg_tlu_halted_f & ~io.request_debug_mode_done + val dpc_capture_pc = io.request_debug_mode_r + + val dpc_ns = Mux1H(Seq( + (~dpc_capture_pc & ~dpc_capture_npc & wr_dpc_r).asBool -> io.dec_csr_wrdata_r(31,1), + (dpc_capture_pc).asBool -> pc_r, + (~dpc_capture_pc & dpc_capture_npc).asBool -> io.npc_r )) + + io.dpc := rvdffe(dpc_ns,(wr_dpc_r | dpc_capture_pc | dpc_capture_npc).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAWICS (R/W) (Only accessible in debug mode) + // [31:25] : Reserved + // [24] : Array select, 0 is data, 1 is tag + // [23:22] : Reserved + // [21:20] : Way select + // [19:17] : Reserved + // [16:3] : Index + // [2:0] : Reserved + + + + val dicawics_ns = Cat(io.dec_csr_wrdata_r(24), io.dec_csr_wrdata_r(21,20), io.dec_csr_wrdata_r(16,3)) + val wr_dicawics_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAWICS) + + val dicawics = rvdffe(dicawics_ns,wr_dicawics_r.asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAD0 (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [31:0] : inst data + // + // If io.dicawics[array] is 1 + // [31:16] : Tag + // [15:7] : Reserved + // [6:4] : LRU + // [3:1] : Reserved + // [0] : Valid + + + val wr_dicad0_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0) + val dicad0_ns = Mux(wr_dicad0_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data) + + val dicad0 = rvdffe(dicad0_ns, (wr_dicad0_r | io.ifu_ic_debug_rd_data_valid).asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // DICAD0H (R/W) (Only accessible in debug mode) + // + // If io.dicawics[array] is 0 + // [63:32] : inst data + // + + + val wr_dicad0h_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD0H) + + val dicad0h_ns = Mux(wr_dicad0h_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(63,32)) + + val dicad0h = rvdffe(dicad0h_ns,(wr_dicad0h_r | io.ifu_ic_debug_rd_data_valid).asBool,clock,io.scan_mode) + + if (ICACHE_ECC == true) { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [6:0] : ECC + + val dicad1_raw = WireInit(UInt(7.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) + + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r, io.ifu_ic_debug_rd_data(70,64)) + + dicad1_raw := withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(25.W), dicad1_raw) + + } + else { + // ---------------------------------------------------------------------- + // DICAD1 (R/W) (Only accessible in debug mode) + // [3:0] : Parity + + + val dicad1_raw = WireInit(UInt(4.W),0.U) + val wr_dicad1_r = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAD1) + + val dicad1_ns = Mux(wr_dicad1_r.asBool, io.dec_csr_wrdata_r(3,0), io.ifu_ic_debug_rd_data(67,64)) + + dicad1_raw :=withClock(io.active_clk){RegEnable(dicad1_ns,0.U,(wr_dicad1_r | io.ifu_ic_debug_rd_data_valid).asBool)} + dicad1 := Cat(0.U(28.W), dicad1_raw) + } + + // ---------------------------------------------------------------------- + // DICAGO (R/W) (Only accessible in debug mode) + // [0] : Go + + if (ICACHE_ECC == true) io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(dicad1(6,0), dicad0h(31,0), dicad0(31,0)) + else io.dec_tlu_ic_diag_pkt.icache_wrdata := Cat(0.U(2.W),dicad1(3,0), dicad0h(31,0), dicad0(31,0)) + + io.dec_tlu_ic_diag_pkt.icache_dicawics := dicawics + + val icache_rd_valid = io.allow_dbg_halt_csr_write & io.dec_csr_any_unq_d & io.dec_i0_decode_d & ~io.dec_csr_wen_unq_d & (io.dec_csr_rdaddr_d(11,0) === DICAGO) + val icache_wr_valid = io.allow_dbg_halt_csr_write & io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === DICAGO) + + val icache_rd_valid_f = withClock(io.active_clk){RegNext(icache_rd_valid,0.U)} + val icache_wr_valid_f = withClock(io.active_clk){RegNext(icache_wr_valid,0.U)} + + io.dec_tlu_ic_diag_pkt.icache_rd_valid := icache_rd_valid_f + io.dec_tlu_ic_diag_pkt.icache_wr_valid := icache_wr_valid_f + + // ---------------------------------------------------------------------- + // MTSEL (R/W) + // [1:0] : Trigger select : 00, 01, 10 are data/address triggers. 11 is inst count + + + + val wr_mtsel_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTSEL) + val mtsel_ns = Mux(wr_mtsel_r.asBool, io.dec_csr_wrdata_r(1,0), mtsel) + + mtsel := withClock(io.csr_wr_clk){RegNext(mtsel_ns,0.U)} + // ---------------------------------------------------------------------- + // MTDATA1 (R/W) + // [31:0] : Trigger Data 1 + // for triggers 0, 1, 2 and 3 aka Match Control + // [31:28] : type, hard coded to 0x2 + // [27] : dmode + // [26:21] : hard coded to 0x1f + // [20] : hit + // [19] : select (0 - address, 1 - data) + // [18] : timing, always 'before', reads 0x0 + // [17:12] : action, bits [17:13] not implemented and reads 0x0 + // [11] : chain + // [10:7] : match, bits [10:8] not implemented and reads 0x0 + // [6] : M + // [5:3] : not implemented, reads 0x0 + // [2] : execute + // [1] : store + // [0] : load + // + // decoder ring + // [27] : => 9 + // [20] : => 8 + // [19] : => 7 + // [12] : => 6 + // [11] : => 5 + // [7] : => 4 + // [6] : => 3 + // [2] : => 2 + // [1] : => 1 + // [0] : => 0 + + + + // don't allow setting load-data. + val tdata_load = io.dec_csr_wrdata_r(0) & ~io.dec_csr_wrdata_r(19) + // don't allow setting execute-data. + val tdata_opcode = io.dec_csr_wrdata_r(2) & ~io.dec_csr_wrdata_r(19) + // don't allow clearing DMODE and action=1 + val tdata_action = (io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f) & io.dec_csr_wrdata_r(12) + + val tdata_wrdata_r = Cat(io.dec_csr_wrdata_r(27) & io.dbg_tlu_halted_f, io.dec_csr_wrdata_r(20,19), tdata_action, io.dec_csr_wrdata_r(11), + io.dec_csr_wrdata_r(7,6), tdata_opcode, io.dec_csr_wrdata_r(1), tdata_load) + + // If the DMODE bit is set, tdata1 can only be updated in debug_mode + val wr_mtdata1_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA1) & (mtsel === 0.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) + val mtdata1_t_ns = VecInit.tabulate(4)(i => Mux(wr_mtdata1_t_r(i).asBool, tdata_wrdata_r, Cat(io.mtdata1_t(i)(9), io.update_hit_bit_r(i) | io.mtdata1_t(i)(8), io.mtdata1_t(i)(7,0)))) + + for(i <- 0 until 4) { io.mtdata1_t(i) := withClock(io.active_clk){RegNext(mtdata1_t_ns(i),0.U)}} + + + val mtdata1_tsel_out = Mux1H((0 until 4).map(i => (mtsel === i.U(2.W)) -> Cat(2.U(4.W), io.mtdata1_t(i)(9), "b011111".U(6.W), io.mtdata1_t(i)(8,7), 0.U(6.W), io.mtdata1_t(i)(6,5), 0.U(3.W), io.mtdata1_t(i)(4,3), 0.U(3.W), io.mtdata1_t(i)(2,0)))) + for(i <- 0 until 4 ){ + io.trigger_pkt_any(i).select := io.mtdata1_t(i)(MTDATA1_SEL) + io.trigger_pkt_any(i).match_ := io.mtdata1_t(i)(MTDATA1_MATCH) + io.trigger_pkt_any(i).store := io.mtdata1_t(i)(MTDATA1_ST) + io.trigger_pkt_any(i).load := io.mtdata1_t(i)(MTDATA1_LD) + io.trigger_pkt_any(i).execute := io.mtdata1_t(i)(MTDATA1_EXE) + io.trigger_pkt_any(i).m := io.mtdata1_t(i)(MTDATA1_M_ENABLED) + } + + // ---------------------------------------------------------------------- + // MTDATA2 (R/W) + // [31:0] : Trigger Data 2 + // If the DMODE bit is set, tdata2 can only be updated in debug_mode + val wr_mtdata2_t_r = VecInit.tabulate(4)(i => io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MTDATA2) & (mtsel === i.U(2.W)) & (~io.mtdata1_t(i)(MTDATA1_DMODE) | io.dbg_tlu_halted_f)) + for(i <- 0 until 4) { mtdata2_t(i) := rvdffe(io.dec_csr_wrdata_r,wr_mtdata2_t_r(i).asBool,clock,io.scan_mode)} + + + + val mtdata2_tsel_out = Mux1H((0 until 4).map(i =>(mtsel === i.U(2.W)) -> mtdata2_t(i))) + for(i <- 0 until 4) {io.trigger_pkt_any(i).tdata2 := mtdata2_t(i)} + + + //---------------------------------------------------------------------- + // Performance Monitor Counters section starts + //---------------------------------------------------------------------- + + + + // Pack the event selects into a vector for genvar + mhpme_vec(0) := mhpme3 + mhpme_vec(1) := mhpme4 + mhpme_vec(2) := mhpme5 + mhpme_vec(3) := mhpme6 + + import el2_inst_pkt_t._ + // only consider committed itypes + + + val pmu_i0_itype_qual = io.dec_tlu_packet_r.pmu_i0_itype & Fill(4,io.tlu_i0_commit_cmt) + val mhpmc_inc_r = Wire(Vec(4,UInt(1.W))) + val mhpmc_inc_r_d1 = Wire(Vec(4,UInt(1.W))) + + // Generate the muxed incs for all counters based on event type + for(i <- 0 until 4) { + mhpmc_inc_r(i) := (~mcountinhibit(i+3) & (Mux1H(Seq( + (mhpme_vec(i) === MHPME_CLK_ACTIVE ).asBool -> 1.U, + (mhpme_vec(i) === MHPME_ICACHE_HIT ).asBool -> io.ifu_pmu_ic_hit, + (mhpme_vec(i) === MHPME_ICACHE_MISS ).asBool -> io.ifu_pmu_ic_miss, + (mhpme_vec(i) === MHPME_INST_COMMIT ).asBool -> (io.tlu_i0_commit_cmt & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_COMMIT_16B ).asBool -> (io.tlu_i0_commit_cmt & ~io.exu_pmu_i0_pc4 & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_COMMIT_32B ).asBool -> (io.tlu_i0_commit_cmt & io.exu_pmu_i0_pc4 & ~io.illegal_r), + (mhpme_vec(i) === MHPME_INST_ALIGNED ).asBool -> io.ifu_pmu_instr_aligned, + (mhpme_vec(i) === MHPME_INST_DECODED ).asBool -> io.dec_pmu_instr_decoded, + (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (mhpme_vec(i) === MHPME_INST_MUL ).asBool -> (pmu_i0_itype_qual === MUL), + (mhpme_vec(i) === MHPME_INST_DIV ).asBool -> (io.dec_tlu_packet_r.pmu_divide & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_INST_LOAD ).asBool -> (pmu_i0_itype_qual === LOAD), + (mhpme_vec(i) === MHPME_INST_STORE ).asBool -> (pmu_i0_itype_qual === STORE), + (mhpme_vec(i) === MHPME_INST_MALOAD ).asBool -> ((pmu_i0_itype_qual === LOAD) & io.dec_tlu_packet_r.pmu_lsu_misaligned + (mhpme_vec(i) === MHPME_INST_MASTORE) & (pmu_i0_itype_qual === STORE) & + io.dec_tlu_packet_r.pmu_lsu_misaligned.asBool), + (mhpme_vec(i) === MHPME_INST_ALU).asBool -> (pmu_i0_itype_qual === ALU), + (mhpme_vec(i) === MHPME_INST_CSRREAD ).asBool -> (pmu_i0_itype_qual === CSRREAD), + (mhpme_vec(i) === MHPME_INST_CSRWRITE).asBool -> (pmu_i0_itype_qual === CSRWRITE), + (mhpme_vec(i) === MHPME_INST_CSRRW ).asBool -> (pmu_i0_itype_qual === CSRRW), + (mhpme_vec(i) === MHPME_INST_EBREAK ).asBool -> (pmu_i0_itype_qual === EBREAK), + (mhpme_vec(i) === MHPME_INST_ECALL ).asBool -> (pmu_i0_itype_qual === ECALL), + (mhpme_vec(i) === MHPME_INST_FENCE ).asBool -> (pmu_i0_itype_qual === FENCE), + (mhpme_vec(i) === MHPME_INST_FENCEI ).asBool -> (pmu_i0_itype_qual === FENCEI), + (mhpme_vec(i) === MHPME_INST_MRET ).asBool -> (pmu_i0_itype_qual === MRET), + (mhpme_vec(i) === MHPME_INST_BRANCH ).asBool -> ((pmu_i0_itype_qual === CONDBR) | (pmu_i0_itype_qual === JAL)), + (mhpme_vec(i) === MHPME_BRANCH_MP ).asBool -> (io.exu_pmu_i0_br_misp & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_BRANCH_TAKEN ).asBool -> (io.exu_pmu_i0_br_ataken & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_BRANCH_NOTP ).asBool -> (io.dec_tlu_packet_r.pmu_i0_br_unpred & io.tlu_i0_commit_cmt), + (mhpme_vec(i) === MHPME_FETCH_STALL ).asBool -> io.ifu_pmu_fetch_stall, + (mhpme_vec(i) === MHPME_DECODE_STALL ).asBool -> io.dec_pmu_decode_stall, + (mhpme_vec(i) === MHPME_POSTSYNC_STALL ).asBool -> io.dec_pmu_postsync_stall, + (mhpme_vec(i) === MHPME_PRESYNC_STALL ).asBool -> io.dec_pmu_presync_stall, + (mhpme_vec(i) === MHPME_LSU_SB_WB_STALL ).asBool -> io.lsu_store_stall_any, + (mhpme_vec(i) === MHPME_DMA_DCCM_STALL ).asBool -> io.dma_dccm_stall_any, + (mhpme_vec(i) === MHPME_DMA_ICCM_STALL ).asBool -> io.dma_iccm_stall_any, + (mhpme_vec(i) === MHPME_EXC_TAKEN ).asBool -> (io.i0_exception_valid_r | io.i0_trigger_hit_r | io.lsu_exc_valid_r), + (mhpme_vec(i) === MHPME_TIMER_INT_TAKEN ).asBool -> (io.take_timer_int | io.take_int_timer0_int | io.take_int_timer1_int), + (mhpme_vec(i) === MHPME_EXT_INT_TAKEN ).asBool -> io.take_ext_int, + (mhpme_vec(i) === MHPME_FLUSH_LOWER ).asBool -> io.tlu_flush_lower_r, + (mhpme_vec(i) === MHPME_BR_ERROR ).asBool -> ((io.dec_tlu_br0_error_r | io.dec_tlu_br0_start_error_r) & io.rfpc_i0_r), + (mhpme_vec(i) === MHPME_IBUS_TRANS ).asBool -> io.ifu_pmu_bus_trxn, + (mhpme_vec(i) === MHPME_DBUS_TRANS ).asBool -> io.lsu_pmu_bus_trxn, + (mhpme_vec(i) === MHPME_DBUS_MA_TRANS ).asBool -> io.lsu_pmu_bus_misaligned, + (mhpme_vec(i) === MHPME_IBUS_ERROR ).asBool -> io.ifu_pmu_bus_error, + (mhpme_vec(i) === MHPME_DBUS_ERROR ).asBool -> io.lsu_pmu_bus_error, + (mhpme_vec(i) === MHPME_IBUS_STALL ).asBool -> io.ifu_pmu_bus_busy, + (mhpme_vec(i) === MHPME_DBUS_STALL ).asBool -> io.lsu_pmu_bus_busy, + (mhpme_vec(i) === MHPME_INT_DISABLED ).asBool -> (~io.mstatus(MSTATUS_MIE)), + (mhpme_vec(i) === MHPME_INT_STALLED ).asBool -> (~io.mstatus(MSTATUS_MIE) & (io.mip(5,0) & mie(5,0))), + (mhpme_vec(i) === MHPME_INST_BITMANIP ).asBool -> (pmu_i0_itype_qual === BITMANIPU), + (mhpme_vec(i) === MHPME_DBUS_LOAD ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_load_external_r), + (mhpme_vec(i) === MHPME_DBUS_STORE ).asBool -> (io.tlu_i0_commit_cmt & io.lsu_pmu_store_external_r), + // These count even during sleep + (mhpme_vec(i) === MHPME_SLEEP_CYC ).asBool -> io.dec_tlu_pmu_fw_halted, + (mhpme_vec(i) === MHPME_DMA_READ_ALL ).asBool -> io.dma_pmu_any_read, + (mhpme_vec(i) === MHPME_DMA_WRITE_ALL ).asBool -> io.dma_pmu_any_write, + (mhpme_vec(i) === MHPME_DMA_READ_DCCM ).asBool -> io.dma_pmu_dccm_read, + (mhpme_vec(i) === MHPME_DMA_WRITE_DCCM ).asBool -> io.dma_pmu_dccm_write )))) + } + + mhpmc_inc_r_d1(0) := withClock(io.free_clk){RegNext(mhpmc_inc_r(0),0.U)} + mhpmc_inc_r_d1(1) := withClock(io.free_clk){RegNext(mhpmc_inc_r(1),0.U)} + mhpmc_inc_r_d1(2) := withClock(io.free_clk){RegNext(mhpmc_inc_r(2),0.U)} + mhpmc_inc_r_d1(3) := withClock(io.free_clk){RegNext(mhpmc_inc_r(3),0.U)} + val perfcnt_halted_d1 = withClock(io.free_clk){RegNext(perfcnt_halted,0.U)} + + + perfcnt_halted := ((io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)) | io.dec_tlu_pmu_fw_halted) + val perfcnt_during_sleep = (Fill(4,~(io.dec_tlu_dbg_halted & io.dcsr(DCSR_STOPC)))) & Cat(mhpme_vec(3)(9),mhpme_vec(2)(9),mhpme_vec(1)(9),mhpme_vec(0)(9)) + + io.dec_tlu_perfcnt0 := mhpmc_inc_r_d1(0) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(0)) + io.dec_tlu_perfcnt1 := mhpmc_inc_r_d1(1) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(1)) + io.dec_tlu_perfcnt2 := mhpmc_inc_r_d1(2) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(2)) + io.dec_tlu_perfcnt3 := mhpmc_inc_r_d1(3) & ~(perfcnt_halted_d1 & ~perfcnt_during_sleep(3)) + + // ---------------------------------------------------------------------- + // MHPMC3H(RW), MHPMC3(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 3 + + val mhpmc3_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3) + val mhpmc3_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(0)) & ((mhpmc_inc_r(0)).orR) + val mhpmc3_wr_en = mhpmc3_wr_en0 | mhpmc3_wr_en1 + + + mhpmc3_incr := Cat(mhpmc3h(31,0),mhpmc3(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(0)) + val mhpmc3_ns = Mux(mhpmc3_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(31,0)) + + mhpmc3 := rvdffe(mhpmc3_ns,mhpmc3_wr_en.asBool,clock,io.scan_mode) + + val mhpmc3h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC3H) + val mhpmc3h_wr_en = mhpmc3h_wr_en0 | mhpmc3_wr_en1 + val mhpmc3h_ns = Mux(mhpmc3h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc3_incr(63,32)) + + mhpmc3h := rvdffe(mhpmc3h_ns, mhpmc3h_wr_en.asBool, clock, io.scan_mode) + // ---------------------------------------------------------------------- + // MHPMC4H(RW), MHPMC4(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 4 + + val mhpmc4_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4) + val mhpmc4_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(1)) & ((mhpmc_inc_r(1)).orR) + val mhpmc4_wr_en = mhpmc4_wr_en0 | mhpmc4_wr_en1 + + + + mhpmc4_incr := Cat(mhpmc4h(31,0),mhpmc4(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(1)) + val mhpmc4_ns = Mux(mhpmc4_wr_en0.asBool, io.dec_csr_wrdata_r(31,0), mhpmc4_incr(31,0)) + mhpmc4 := rvdffe(mhpmc4_ns, mhpmc4_wr_en.asBool, clock, io.scan_mode) + + val mhpmc4h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC4H) + val mhpmc4h_wr_en = mhpmc4h_wr_en0 | mhpmc4_wr_en1 + val mhpmc4h_ns = Mux(mhpmc4h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc4_incr(63,32)) + mhpmc4h := rvdffe(mhpmc4h_ns, mhpmc4h_wr_en.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MHPMC5H(RW), MHPMC5(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 5 + + val mhpmc5_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5) + val mhpmc5_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(2)) & ((mhpmc_inc_r(2)).orR) + val mhpmc5_wr_en = mhpmc5_wr_en0 | mhpmc5_wr_en1 + + mhpmc5_incr := Cat(mhpmc5h(31,0),mhpmc5(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(2)) + val mhpmc5_ns = Mux(mhpmc5_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(31,0)) + + mhpmc5 := rvdffe(mhpmc5_ns, mhpmc5_wr_en.asBool, clock, io.scan_mode) + + val mhpmc5h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC5H) + val mhpmc5h_wr_en = mhpmc5h_wr_en0 | mhpmc5_wr_en1 + val mhpmc5h_ns = Mux(mhpmc5h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc5_incr(63,32)) + + mhpmc5h := rvdffe(mhpmc5h_ns, mhpmc5h_wr_en.asBool, clock, io.scan_mode) + // ---------------------------------------------------------------------- + // MHPMC6H(RW), MHPMC6(RW) + // [63:32][31:0] : Hardware Performance Monitor Counter 6 + + val mhpmc6_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6) + val mhpmc6_wr_en1 = (~perfcnt_halted | perfcnt_during_sleep(3)) & ((mhpmc_inc_r(3)).orR) + val mhpmc6_wr_en = mhpmc6_wr_en0 | mhpmc6_wr_en1 + + mhpmc6_incr := Cat(mhpmc6h(31,0),mhpmc6(31,0)) + Cat(0.U(63.W),mhpmc_inc_r(3)) + val mhpmc6_ns = Mux(mhpmc6_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(31,0)) + + mhpmc6 := rvdffe(mhpmc6_ns, mhpmc6_wr_en.asBool, clock, io.scan_mode) + + val mhpmc6h_wr_en0 = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPMC6H) + val mhpmc6h_wr_en = mhpmc6h_wr_en0 | mhpmc6_wr_en1 + val mhpmc6h_ns = Mux(mhpmc6h_wr_en0.asBool, io.dec_csr_wrdata_r, mhpmc6_incr(63,32)) + + mhpmc6h := rvdffe(mhpmc6h_ns, mhpmc6h_wr_en.asBool, clock, io.scan_mode) + + // ---------------------------------------------------------------------- + // MHPME3(RW) + // [9:0] : Hardware Performance Monitor Event 3 + + // we only have events 0-56, 512-516, HPME* are WARL so saturate otherwise + val event_saturate_r = Mux(((io.dec_csr_wrdata_r(9,0) > 516.U(10.W)) | (io.dec_csr_wrdata_r(31,10)).orR), 516.U(10.W), io.dec_csr_wrdata_r(9,0)) + + val wr_mhpme3_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME3) + + mhpme3 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme3_r.asBool)} + // ---------------------------------------------------------------------- + // MHPME4(RW) + // [9:0] : Hardware Performance Monitor Event 4 + + val wr_mhpme4_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME4) + mhpme4 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme4_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME5(RW) + // [9:0] : Hardware Performance Monitor Event 5 + + val wr_mhpme5_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME5) + mhpme5 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme5_r.asBool)} + + // ---------------------------------------------------------------------- + // MHPME6(RW) + // [9:0] : Hardware Performance Monitor Event 6 + + val wr_mhpme6_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MHPME6) + mhpme6 := withClock(io.active_clk){RegEnable(event_saturate_r,0.U,wr_mhpme6_r.asBool)} + //---------------------------------------------------------------------- + // Performance Monitor Counters section ends + //---------------------------------------------------------------------- + // ---------------------------------------------------------------------- + + // MCOUNTINHIBIT(RW) + // [31:7] : Reserved, read 0x0 + // [6] : HPM6 disable + // [5] : HPM5 disable + // [4] : HPM4 disable + // [3] : HPM3 disable + // [2] : MINSTRET disable + // [1] : reserved, read 0x0 + // [0] : MCYCLE disable + + val wr_mcountinhibit_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r(11,0) === MCOUNTINHIBIT) + + val temp_ncount0 = WireInit(UInt(1.W),mcountinhibit(0)) + val temp_ncount1 = WireInit(UInt(1.W),mcountinhibit(1)) + val temp_ncount6_2 = WireInit(UInt(5.W),mcountinhibit(6,2)) + temp_ncount6_2 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(6,2),0.U,wr_mcountinhibit_r.asBool)} + + temp_ncount0 := withClock(io.active_clk){RegEnable(io.dec_csr_wrdata_r(0),0.U,wr_mcountinhibit_r.asBool)} + mcountinhibit := Cat(temp_ncount6_2, 0.U(1.W),temp_ncount0) + //-------------------------------------------------------------------------------- + // trace + //-------------------------------------------------------------------------------- + + + + val trace_tclk = rvclkhdr(clock, (io.i0_valid_wb | io.exc_or_int_valid_r_d1 | io.interrupt_valid_r_d1 | io.dec_tlu_i0_valid_wb1 | + io.dec_tlu_i0_exc_valid_wb1 | io.dec_tlu_int_valid_wb1 | io.clk_override).asBool, io.scan_mode) + + io.dec_tlu_i0_valid_wb1 := withClock(trace_tclk){RegNext(io.i0_valid_wb,0.U)} + io.dec_tlu_i0_exc_valid_wb1 := withClock(trace_tclk){RegNext((io.i0_exception_valid_r_d1 | io.lsu_i0_exc_r_d1 | (io.trigger_hit_r_d1 & ~io.trigger_hit_dmode_r_d1)),0.U)} + io.dec_tlu_exc_cause_wb1 := withClock(trace_tclk){RegNext(io.exc_cause_wb,0.U)} + io.dec_tlu_int_valid_wb1 := withClock(trace_tclk){RegNext(io.interrupt_valid_r_d1,0.U)} + + io.dec_tlu_mtval_wb1 := mtval + + // end trace + //-------------------------------------------------------------------------------- + // CSR read mux + io.dec_csr_rddata_d:=Mux1H(Seq( + io.csr_pkt.csr_misa.asBool -> 0x40001104.U(32.W), + io.csr_pkt.csr_mvendorid.asBool -> 0x00000045.U(32.W), + io.csr_pkt.csr_marchid.asBool -> 0x00000010.U(32.W), + io.csr_pkt.csr_mimpid.asBool -> 0x2.U(32.W), + io.csr_pkt.csr_mhartid.asBool -> Cat(io.core_id,0.U(4.W)), + io.csr_pkt.csr_mstatus.asBool -> Cat(0.U(19.W), 3.U(2.W), 0.U(3.W), io.mstatus(1), 0.U(3.W), io.mstatus(0), 0.U(3.W)), + io.csr_pkt.csr_mtvec.asBool -> Cat(io.mtvec(30,1), 0.U(1.W), io.mtvec(0)), + io.csr_pkt.csr_mip.asBool -> Cat(0.U(1.W), io.mip(5,3), 0.U(16.W), io.mip(2), 0.U(3.W), io.mip(1), 0.U(3.W), io.mip(0), 0.U(3.W)), + io.csr_pkt.csr_mie.asBool -> Cat(0.U(1.W), mie(5,3), 0.U(16.W), mie(2), 0.U(3.W), mie(1), 0.U(3.W), mie(0), 0.U(3.W)), + io.csr_pkt.csr_mcyclel.asBool -> mcyclel(31,0), + io.csr_pkt.csr_mcycleh.asBool -> mcycleh_inc(31,0), + io.csr_pkt.csr_minstretl.asBool -> minstretl_read(31,0), + io.csr_pkt.csr_minstreth.asBool -> minstreth_read(31,0), + io.csr_pkt.csr_mscratch.asBool -> mscratch(31,0), + io.csr_pkt.csr_mepc.asBool -> Cat(io.mepc,0.U(1.W)), + io.csr_pkt.csr_mcause.asBool -> mcause(31,0), + io.csr_pkt.csr_mscause.asBool -> Cat(0.U(28.W), mscause(3,0)), + io.csr_pkt.csr_mtval.asBool -> mtval(31,0), + io.csr_pkt.csr_mrac.asBool -> mrac(31,0), + io.csr_pkt.csr_mdseac.asBool -> mdseac(31,0), + io.csr_pkt.csr_meivt.asBool -> Cat(meivt, 0.U(10.W)), + io.csr_pkt.csr_meihap.asBool -> Cat(meivt, meihap, 0.U(2.W)), + io.csr_pkt.csr_meicurpl.asBool -> Cat(0.U(28.W), meicurpl(3,0)), + io.csr_pkt.csr_meicidpl.asBool -> Cat(0.U(28.W), meicidpl(3,0)), + io.csr_pkt.csr_meipt.asBool -> Cat(0.U(28.W), meipt(3,0)), + io.csr_pkt.csr_mcgc.asBool -> Cat(0.U(23.W), mcgc(8,0)), + io.csr_pkt.csr_mfdc.asBool -> Cat(0.U(13.W), mfdc(18,0)), + io.csr_pkt.csr_dcsr.asBool -> Cat(0x4000.U(16.W), io.dcsr(15,2), 3.U(2.W)), + io.csr_pkt.csr_dpc.asBool -> Cat(io.dpc, 0.U(1.W)), + io.csr_pkt.csr_dicad0.asBool -> dicad0(31,0), + io.csr_pkt.csr_dicad0h.asBool -> dicad0h(31,0), + io.csr_pkt.csr_dicad1.asBool -> dicad1(31,0), + io.csr_pkt.csr_dicawics.asBool -> Cat(0.U(7.W), dicawics(16), 0.U(2.W), dicawics(15,14), 0.U(3.W), dicawics(13,0), 0.U(3.W)), + io.csr_pkt.csr_mtsel.asBool -> Cat(0.U(30.W), mtsel(1,0)), + io.csr_pkt.csr_mtdata1.asBool -> mtdata1_tsel_out(31,0), + io.csr_pkt.csr_mtdata2.asBool -> mtdata2_tsel_out(31,0), + io.csr_pkt.csr_micect.asBool -> micect(31,0), + io.csr_pkt.csr_miccmect.asBool -> miccmect(31,0), + io.csr_pkt.csr_mdccmect.asBool -> mdccmect(31,0), + io.csr_pkt.csr_mhpmc3.asBool -> mhpmc3(31,0), + io.csr_pkt.csr_mhpmc4.asBool -> mhpmc4(31,0), + io.csr_pkt.csr_mhpmc5.asBool -> mhpmc5(31,0), + io.csr_pkt.csr_mhpmc6.asBool -> mhpmc6(31,0), + io.csr_pkt.csr_mhpmc3h.asBool -> mhpmc3h(31,0), + io.csr_pkt.csr_mhpmc4h.asBool -> mhpmc4h(31,0), + io.csr_pkt.csr_mhpmc5h.asBool -> mhpmc5h(31,0), + io.csr_pkt.csr_mhpmc6h.asBool -> mhpmc6h(31,0), + io.csr_pkt.csr_mfdht.asBool -> Cat(0.U(26.W), mfdht(5,0)), + io.csr_pkt.csr_mfdhs.asBool -> Cat(0.U(30.W), mfdhs(1,0)), + io.csr_pkt.csr_mhpme3.asBool -> Cat(0.U(22.W), mhpme3(9,0)), + io.csr_pkt.csr_mhpme4.asBool -> Cat(0.U(22.W), mhpme4(9,0)), + io.csr_pkt.csr_mhpme5.asBool -> Cat(0.U(22.W),mhpme5(9,0)), + io.csr_pkt.csr_mhpme6.asBool -> Cat(0.U(22.W),mhpme6(9,0)), + io.csr_pkt.csr_mcountinhibit.asBool -> Cat(0.U(25.W), mcountinhibit(6,0)), + io.csr_pkt.csr_mpmc.asBool -> Cat(0.U(30.W), mpmc, 0.U(1.W)), + io.dec_timer_read_d.asBool -> io.dec_timer_rddata_d(31,0) + )) + + + +} + + +class el2_dec_decode_csr_read_IO extends Bundle with el2_lib { + val dec_csr_rdaddr_d=Input(UInt(12.W)) + val csr_pkt=Output(new el2_dec_tlu_csr_pkt) +} + +class el2_dec_decode_csr_read extends Module with el2_lib { + val io=IO(new el2_dec_decode_csr_read_IO) + + def pattern(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0 & y(i)!='z') io.dec_csr_rdaddr_d(y(i)) else if(y(i)<0) !io.dec_csr_rdaddr_d(y(i).abs) else !io.dec_csr_rdaddr_d(0)).reduce(_&_) + // 'z' is used for !io.dec_csr_rdaddr_d(0) + io.csr_pkt.csr_misa :=pattern(List(-11,-6,-5,-2,0)) + io.csr_pkt.csr_mvendorid :=pattern(List(10,-7,-1,0)) + io.csr_pkt.csr_marchid :=pattern(List(10,-7,1,'z')) + io.csr_pkt.csr_mimpid :=pattern(List(10,-6,1,0)) + io.csr_pkt.csr_mhartid :=pattern(List(10,-7,2)) + io.csr_pkt.csr_mstatus :=pattern(List(-11,-6,-5,-2,'z')) + io.csr_pkt.csr_mtvec :=pattern(List(-11,-6,-5,2,0)) + io.csr_pkt.csr_mip :=pattern(List(-7,6,2)) + io.csr_pkt.csr_mie :=pattern(List(-11,-6,-5,2,'z')) + io.csr_pkt.csr_mcyclel :=pattern(List(11,-7,-4,-3,-2,-1)) + io.csr_pkt.csr_mcycleh :=pattern(List(7,-6,-5,-4,-3,-2,-1)) + io.csr_pkt.csr_minstretl :=pattern(List(-7,-6,-4,-3,-2,1,'z')) + io.csr_pkt.csr_minstreth :=pattern(List(-10,7,-4,-3,-2,1,'z')) + io.csr_pkt.csr_mscratch :=pattern(List(-7,6,-2,-1,'z')) + io.csr_pkt.csr_mepc :=pattern(List(-7,6,-1,0)) + io.csr_pkt.csr_mcause :=pattern(List(-7,6,1,'z')) + io.csr_pkt.csr_mscause :=pattern(List(6,5,2)) + io.csr_pkt.csr_mtval :=pattern(List(-7,6,1,0)) + io.csr_pkt.csr_mrac :=pattern(List(-11,7,-5,-3,-2,-1)) + io.csr_pkt.csr_dmst :=pattern(List(10,-4,-3,2,-1)) + io.csr_pkt.csr_mdseac :=pattern(List(11,10,-4,-3)) + io.csr_pkt.csr_meihap :=pattern(List(11,10,3)) + io.csr_pkt.csr_meivt :=pattern(List(-10,6,3,-2,-1,'z')) + io.csr_pkt.csr_meipt :=pattern(List(11,6,-1,0)) + io.csr_pkt.csr_meicurpl :=pattern(List(11,6,2)) + io.csr_pkt.csr_meicidpl :=pattern(List(11,6,1,0)) + io.csr_pkt.csr_dcsr :=pattern(List(10,-6,5,4,'z')) + io.csr_pkt.csr_mcgc :=pattern(List(10,4,3,'z')) + io.csr_pkt.csr_mfdc :=pattern(List(10,4,3,-1,0)) + io.csr_pkt.csr_dpc :=pattern(List(10,-6,5,4,0)) + io.csr_pkt.csr_mtsel :=pattern(List(10,5,-4,-1,'z')) + io.csr_pkt.csr_mtdata1 :=pattern(List(10,-4,-3,0)) + io.csr_pkt.csr_mtdata2 :=pattern(List(10,5,-4,1)) + io.csr_pkt.csr_mhpmc3 :=pattern(List(11,-7,-4,-3,-2,0)) + io.csr_pkt.csr_mhpmc4 :=pattern(List(11,-7,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpmc5 :=pattern(List(11,-7,-4,-3,-1,0)) + io.csr_pkt.csr_mhpmc6 :=pattern(List(-7,-5,-4,-3,2,1,'z')) + io.csr_pkt.csr_mhpmc3h :=pattern(List(7,-4,-3,-2,1,0)) + io.csr_pkt.csr_mhpmc4h :=pattern(List(7,-6,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpmc5h :=pattern(List(7,-4,-3,2,-1,0)) + io.csr_pkt.csr_mhpmc6h :=pattern(List(7,-6,-4,-3,2,1,'z')) + io.csr_pkt.csr_mhpme3 :=pattern(List(-7,5,-4,-3,-2,0)) + io.csr_pkt.csr_mhpme4 :=pattern(List(5,-4,-3,2,-1,'z')) + io.csr_pkt.csr_mhpme5 :=pattern(List(5,-4,-3,2,-1,0)) + io.csr_pkt.csr_mhpme6 :=pattern(List(5,-4,-3,2,1,'z')) + io.csr_pkt.csr_mcountinhibit :=pattern(List(-7,5,-4,-3,-2,'z')) + io.csr_pkt.csr_mitctl0 :=pattern(List(6,-5,4,-1,'z')) + io.csr_pkt.csr_mitctl1 :=pattern(List(6,-3,2,1,0)) + io.csr_pkt.csr_mitb0 :=pattern(List(6,-5,4,-2,0)) + io.csr_pkt.csr_mitb1 :=pattern(List(6,4,2,1,'z')) + io.csr_pkt.csr_mitcnt0 :=pattern(List(6,-5,4,-2,'z')) + io.csr_pkt.csr_mitcnt1 :=pattern(List(6,2,-1,0)) + io.csr_pkt.csr_mpmc :=pattern(List(6,-4,-3,2,1)) + io.csr_pkt.csr_mcpc :=pattern(List(10,6,-4,-3,-2,1)) + io.csr_pkt.csr_meicpct :=pattern(List(11,6,1,'z')) + io.csr_pkt.csr_mdeau :=pattern(List(-10,7,6,-3)) + io.csr_pkt.csr_micect :=pattern(List(6,5,-3,-1,'z')) + io.csr_pkt.csr_miccmect :=pattern(List(6,5,-3,0)) + io.csr_pkt.csr_mdccmect :=pattern(List(6,5,1,'z')) + io.csr_pkt.csr_mfdht :=pattern(List(6,3,2,1,'z')) + io.csr_pkt.csr_mfdhs :=pattern(List(6,-4,2,0)) + io.csr_pkt.csr_dicawics :=pattern(List(-11,-5,3,-2,-1,'z')) + io.csr_pkt.csr_dicad0h :=pattern(List(10,3,2,-1)) + io.csr_pkt.csr_dicad0 :=pattern(List(10,-4,3,-1,0)) + io.csr_pkt.csr_dicad1 :=pattern(List(10,3,-2,1,'z')) + io.csr_pkt.csr_dicago :=pattern(List(10,3,-2,1,0)) + io.csr_pkt.presync := pattern(List(10,4,3,-1,0)) | pattern(List(-7,5,-4,-3,-2,'z')) | pattern(List(-6,-5,-4,-3,-2,1)) | + pattern(List(11,-4,-3,2,-1)) | pattern(List(11,-4,-3,1,'z')) | pattern(List(7,-5,-4,-3,-2,1)) + io.csr_pkt.postsync := pattern(List(10,4,3,-1,0)) | pattern(List(-11,-6,-5,2,0)) | pattern(List(-7,6,-1,0)) | + pattern(List(10,-4,-3,0)) | pattern(List(-11,-7,-6,-4,-3,-2,'z')) | pattern(List(-11,7,6,-4,-3,-1))| + pattern(List(10,-4,-3,-2,1)) + io.csr_pkt.legal := pattern(List(-11,10,9,8,7,6,4,-3,-2,1,'z')) | pattern(List(-11,-10,9,8,-7,-6,-5,-4,-3,-1)) | + pattern(List(-11,-10,9,8,-7,-6,5,-1,'z')) | pattern(List(11,9,8,7,6,-5,-4,-2,-1,'z')) | + pattern(List(11,-10,9,8,-6,-5,'z')) | pattern(List(-11,10,9,8,7,6,5,4,3,2,1,0)) | + pattern(List(-11,10,9,8,7,6,5,4,-2,-1)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,0)) | + pattern(List(-11,10,9,8,7,-6,5,-3,-2,-1)) | pattern(List(-11,-10,9,8,-7,-6,5,2)) | + pattern(List(11,9,8,-7,-6,-5,4,-3,2,-1,'z')) | pattern(List(-11,10,9,8,7,6,-5,-4,3,1)) | + pattern(List(-11,10,9,8,7,6,-5,4,-3,2)) | pattern(List(11,9,8,-7,-6,-5,4,-3,-2,1)) | + pattern(List(-11,-10,9,8,-7,-6,5,1,0)) | pattern(List(11,-10,9,8,7,-5,-4,3,-2)) | + pattern(List(11,-10,9,8,7,-5,-4,3,-1,'z')) | pattern(List(11,-10,9,8,-6,-5,2)) | + pattern(List(-11,10,9,8,7,6,-5 ,4,-3,1)) | pattern(List(-11,10,9,8,7,6 ,-5,-4,'z')) | + pattern(List(-11,10,9,8,7,6 ,-5,-4,3,-2)) | pattern(List(-11,10,9,8,7,-6,5,-4,-3,-2,'z')) | + pattern(List(11,-10,9,8,-6,-5,1)) | pattern(List(-11,-10,9,8,-7,6,-5,-4,-3,-2)) | + pattern(List(-11,-10,9,8,-7,-5,-4,-3,-1,'z')) | pattern(List(-11,-10,9,8,-7,-6,5,3)) | + pattern(List(11,-10,9,8,-6,-5,3)) | pattern(List(-11,-10,9,8,-7,-6,5,4)) | + pattern(List(11,-10,9,8,-6,-5,4)) +} + + +class el2_dec_timer_ctl extends Module with el2_lib { + val io=IO(new el2_dec_timer_ctl_IO) + val MITCTL_ENABLE=0 + val MITCTL_ENABLE_HALTED=1 + val MITCTL_ENABLE_PAUSED=2 + + val mitctl1=Wire(UInt(4.W)) + val mitctl0=Wire(UInt(3.W)) + val mitb1 =Wire(UInt(32.W)) + val mitb0 =Wire(UInt(32.W)) + val mitcnt1=Wire(UInt(32.W)) + val mitcnt0=Wire(UInt(32.W)) + + val mit0_match_ns=(mitcnt0 >= mitb0).asUInt + val mit1_match_ns=(mitcnt1 >= mitb1).asUInt + + io.dec_timer_t0_pulse := mit0_match_ns + io.dec_timer_t1_pulse := mit1_match_ns + // ---------------------------------------------------------------------- + // MITCNT0 (RW) + // [31:0] : Internal Timer Counter 0 + + val MITCNT0 =0x7d2.U(12.W) + + val wr_mitcnt0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT0) + + val mitcnt0_inc_ok = mitctl0(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl0(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl0(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers + val mitcnt0_inc = mitcnt0 + 1.U(32.W) + val mitcnt0_ns =Mux(mit0_match_ns.asBool, 0.U, Mux(wr_mitcnt0_r.asBool, io.dec_csr_wrdata_r, mitcnt0_inc)) + mitcnt0 := rvdffe(mitcnt0_ns,(wr_mitcnt0_r | mitcnt0_inc_ok | mit0_match_ns).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MITCNT1 (RW) + // [31:0] : Internal Timer Counter 0 + + val MITCNT1=0x7d5.U(12.W) + val wr_mitcnt1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCNT1).asUInt + + val mitcnt1_inc_ok = mitctl1(MITCTL_ENABLE) & (~io.dec_pause_state | mitctl1(MITCTL_ENABLE_PAUSED)) & (~io.dec_tlu_pmu_fw_halted | mitctl1(MITCTL_ENABLE_HALTED)) & ~io.internal_dbg_halt_timers + + // only inc MITCNT1 if not cascaded with 0, or if 0 overflows + val mitcnt1_inc = mitcnt1 + Cat(Fill(31,0.U(1.W)),(~mitctl1(3) | mit0_match_ns)) + val mitcnt1_ns = Mux(mit1_match_ns.asBool, 0.U, Mux(wr_mitcnt1_r.asBool, io.dec_csr_wrdata_r,mitcnt1_inc)) + mitcnt1 := rvdffe(mitcnt1_ns,(wr_mitcnt1_r | mitcnt1_inc_ok | mit1_match_ns).asBool,clock,io.scan_mode) + + // ---------------------------------------------------------------------- + // MITB0 (RW) + // [31:0] : Internal Timer Bound 0 + val MITB0 =0x7d3.U(12.W) + + val wr_mitb0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITB0) + val mitb0_b = rvdffe((~io.dec_csr_wrdata_r),wr_mitb0_r.asBool,clock,io.scan_mode) + mitb0 := ~mitb0_b + + // ---------------------------------------------------------------------- + // MITB1 (RW) + // [31:0] : Internal Timer Bound 1 + + val MITB1 =0x7d6.U(12.W) + val wr_mitb1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITB1) + val mitb1_b = rvdffe(~io.dec_csr_wrdata_r,wr_mitb1_r.asBool,clock,io.scan_mode) + mitb1 := ~mitb1_b + + // ---------------------------------------------------------------------- + // MITCTL0 (RW) Internal Timer Ctl 0 + // [31:3] : Reserved, reads 0x0 + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + + val MITCTL0 =0x7d4.U(12.W) + + val wr_mitctl0_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r === MITCTL0) + val mitctl0_ns = Mux(wr_mitctl0_r.asBool, io.dec_csr_wrdata_r(2,0), mitctl0(2,0)) + + val mitctl0_0_b_ns = ~mitctl0_ns(0) + val mitctl0_0_b = withClock(io.free_clk){RegNext(mitctl0_0_b_ns,0.U)} + mitctl0 :=Cat(withClock(io.free_clk){RegNext(mitctl0_ns(2,1),0.U)},~mitctl0_0_b) + + // ---------------------------------------------------------------------- + // MITCTL1 (RW) Internal Timer Ctl 1 + // [31:4] : Reserved, reads 0x0 + // [3] : Cascade + // [2] : Enable while PAUSEd + // [1] : Enable while HALTed + // [0] : Enable (resets to 0x1) + val MITCTL1 =0x7d7.U(12.W) + val wr_mitctl1_r = io.dec_csr_wen_r_mod & (io.dec_csr_wraddr_r=== MITCTL1) + val mitctl1_ns = Mux(wr_mitctl1_r.asBool,io.dec_csr_wrdata_r(3,0), mitctl1(3,0)) + val mitctl1_0_b_ns= ~mitctl1_ns(0) + val mitctl1_0_b=withClock(io.free_clk){RegNext(mitctl1_0_b_ns,0.U)} + mitctl1:=Cat(withClock(io.free_clk){RegNext(mitctl1_ns(3,1),0.U)},~mitctl1_0_b) + + io.dec_timer_read_d := io.csr_mitcnt1 | io.csr_mitcnt0 | io.csr_mitb1 | io.csr_mitb0 | io.csr_mitctl0 | io.csr_mitctl1 + io.dec_timer_rddata_d :=Mux1H(Seq( + io.csr_mitcnt0.asBool -> mitcnt0(31,0), + io.csr_mitcnt1.asBool -> mitcnt1, + io.csr_mitb0.asBool -> mitb0, + io.csr_mitb1.asBool -> mitb1, + io.csr_mitctl0.asBool -> Cat(Fill(29,0.U(1.W)),mitctl0), + io.csr_mitctl1.asBool -> Cat(Fill(28,0.U(1.W)),mitctl1) + )) +} + + +class el2_dec_timer_ctl_IO extends Bundle{ + val free_clk =Input(Clock()) + val scan_mode =Input(Bool()) + val dec_csr_wen_r_mod =Input(UInt(1.W)) // csr write enable at wb + val dec_csr_rdaddr_d =Input(UInt(12.W)) // read address for csr + val dec_csr_wraddr_r =Input(UInt(12.W)) // write address for csr + val dec_csr_wrdata_r =Input(UInt(32.W)) // csr write data at wb + + val csr_mitctl0 =Input(UInt(1.W)) + val csr_mitctl1 =Input(UInt(1.W)) + val csr_mitb0 =Input(UInt(1.W)) + val csr_mitb1 =Input(UInt(1.W)) + val csr_mitcnt0 =Input(UInt(1.W)) + val csr_mitcnt1 =Input(UInt(1.W)) + + + val dec_pause_state =Input(UInt(1.W)) // Paused + val dec_tlu_pmu_fw_halted =Input(UInt(1.W)) // pmu/fw halted + val internal_dbg_halt_timers=Input(UInt(1.W)) // debug halted + + val dec_timer_rddata_d =Output(UInt(32.W)) // timer CSR read data + val dec_timer_read_d =Output(UInt(1.W)) // timer CSR address match + val dec_timer_t0_pulse =Output(UInt(1.W)) // timer0 int + val dec_timer_t1_pulse =Output(UInt(1.W)) // timer1 int +} + +object tlu_gen extends App{ + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_tlu_ctl()))) +} diff --git a/src/main/scala/dec/el2_dec_trigger.scala b/src/main/scala/dec/el2_dec_trigger.scala new file mode 100644 index 00000000..171579e8 --- /dev/null +++ b/src/main/scala/dec/el2_dec_trigger.scala @@ -0,0 +1,20 @@ +package dec + +import chisel3.util._ +import chisel3._ +import include.el2_trigger_pkt_t +import lib._ + +class el2_dec_trigger extends Module with el2_lib { + val io = IO(new Bundle { + val trigger_pkt_any = Input(Vec(4, new el2_trigger_pkt_t)) + val dec_i0_pc_d = Input(UInt(31.W)) + val dec_i0_trigger_match_d = Output(UInt(4.W)) + }) + val dec_i0_match_data = VecInit.tabulate(4)(i => repl(32, (!io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).execute)) & Cat(io.dec_i0_pc_d, io.trigger_pkt_any(i).tdata2(0))) + io.dec_i0_trigger_match_d := (0 until 4).map(j =>io.trigger_pkt_any(j).execute & io.trigger_pkt_any(j).m & rvmaskandmatch(io.trigger_pkt_any(j).tdata2, dec_i0_match_data(j), io.trigger_pkt_any(j).match_.asBool())).reverse.reduce(Cat(_,_)) + +} +object dec_trig extends App { + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_dec_trigger()))) +} diff --git a/src/main/scala/dmi/dmi_jtag_to_core_sync.scala b/src/main/scala/dmi/dmi_jtag_to_core_sync.scala index ae1abb3c..0631df2d 100644 --- a/src/main/scala/dmi/dmi_jtag_to_core_sync.scala +++ b/src/main/scala/dmi/dmi_jtag_to_core_sync.scala @@ -12,11 +12,11 @@ class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset { val wr_en = Input(UInt(1.W))// 1 bit Write enable from JTAG // Processor Signals - // val rst_n = Input(Bool()) // Core reset - // val clk = Input(Bool()) // Core clock - val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor - val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor - }) + // val rst_n = Input(Bool()) // Core reset + // val clk = Input(Bool()) // Core clock + val reg_en = Output(UInt(1.W)) // 1 bit Write interface bit to Processor + val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor + }) val c_rd_en =WireInit(0.U(1.W)) val c_wr_en =WireInit(0.U(1.W)) val rden =WireInit(0.U(3.W)) @@ -25,8 +25,8 @@ class dmi_jtag_to_core_sync extends Module with el2_lib with RequireAsyncReset { // synchronizers rden := RegNext(Cat(rden(1,0),io.rd_en),0.U) wren := RegNext(Cat(wren(1,0),io.wr_en),0.U) - c_rd_en := rden(1) & !rden(2) - c_wr_en := wren(1) & !wren(2) + c_rd_en := rden(1) & !rden(2) + c_wr_en := wren(1) & !wren(2) // Outputs io.reg_en := c_wr_en | c_rd_en io.reg_wr_en := c_wr_en diff --git a/src/main/scala/dmi/dmi_wrapper.scala b/src/main/scala/dmi/dmi_wrapper.scala index b46b6c34..61ea9e78 100644 --- a/src/main/scala/dmi/dmi_wrapper.scala +++ b/src/main/scala/dmi/dmi_wrapper.scala @@ -8,23 +8,23 @@ import lib._ class dmi_wrapper extends Module with el2_lib with RequireAsyncReset { val io = IO(new Bundle{ // JTAG signals - //val trst_n =Input(UInt(1.W)) // JTAG reset - //val tck =Input(UInt(1.W)) // JTAG clock + val trst_n = Input(AsyncReset()) + val tck = Input(Clock()) // JTAG clock val tms =Input(UInt(1.W)) // Test mode select val tdi =Input(UInt(1.W)) // Test Data Input val tdo =Output(UInt(1.W)) // Test Data Output val tdoEnable =Output(UInt(1.W)) // Test Data Output enable // Processor Signals - // val core_rst_n =Input(UInt(1.W)) // Core reset - // val core_clk =Input(UInt(1.W)) // Core clock - val jtag_id = Input(UInt(32.W)) // JTAG ID - val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor - val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor - val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor - val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor - val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor - val dmi_hard_reset = Output(UInt(1.W)) + // val core_rst_n =Input(UInt(1.W)) // Core reset + // val core_clk =Input(UInt(1.W)) // Core clock + val jtag_id = Input(UInt(32.W)) // JTAG ID + val rd_data = Input(UInt(32.W)) // 32 bit Read data from Processor + val reg_wr_data = Output(UInt(32.W)) // 32 bit Write data to Processor + val reg_wr_addr = Output(UInt(7.W)) // 7 bit reg address to Processor + val reg_en = Output(UInt(1.W)) // 1 bit Read enable to Processor + val reg_wr_en = Output(UInt(1.W)) // 1 bit Write enable to Processor + val dmi_hard_reset = Output(UInt(1.W)) }) //Wire Declaration val rd_en = WireInit(0.U(1.W)) @@ -33,8 +33,8 @@ class dmi_wrapper extends Module with el2_lib with RequireAsyncReset { //jtag_tap instantiation val i_jtag_tap = Module(new rvjtag_tap()) - //.trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset - //.tck(tck), // dedicated JTAG TCK pad signal + i_jtag_tap.io.trst := io.trst_n // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + i_jtag_tap.io.tck := io.tck // dedicated JTAG TCK pad signal i_jtag_tap.io.tms := io.tms // dedicated JTAG TMS pad signal i_jtag_tap.io.tdi := io.tdi // dedicated JTAG TDI pad signal io.tdo := i_jtag_tap.io.tdo // dedicated JTAG TDO pad signal @@ -56,7 +56,6 @@ class dmi_wrapper extends Module with el2_lib with RequireAsyncReset { val i_dmi_jtag_to_core_sync = Module(new dmi_jtag_to_core_sync()) i_dmi_jtag_to_core_sync.io.wr_en := wr_en // 1 bit Write enable i_dmi_jtag_to_core_sync.io.rd_en := rd_en // 1 bit Read enable - io.reg_en :=i_dmi_jtag_to_core_sync.io.reg_en // 1 bit Write interface bit io.reg_wr_en := i_dmi_jtag_to_core_sync.io.reg_wr_en // 1 bit Write enable } diff --git a/src/main/scala/dmi/rvjtag_tap.scala b/src/main/scala/dmi/rvjtag_tap.scala index 01197d5f..12b9d7dc 100644 --- a/src/main/scala/dmi/rvjtag_tap.scala +++ b/src/main/scala/dmi/rvjtag_tap.scala @@ -1,23 +1,22 @@ package dmi import chisel3._ -import scala.collection._ import chisel3.util._ import include._ import lib._ class rvjtag_tap extends Module with el2_lib with RequireAsyncReset { val io = IO(new Bundle{ - val trst = Input(Bool()) - val tck = Input(Bool()) + val trst = Input(AsyncReset()) + val tck = Input(Clock()) val tms = Input(Bool()) val tdi = Input(Bool()) - val dmi_reset = Input(Bool()) - val dmi_hard_reset = Input(Bool()) + val dmi_reset = Output(Bool()) + val dmi_hard_reset = Output(Bool()) val rd_status = Input(UInt(2.W)) val dmi_stat = Input(UInt(2.W)) val idle = Input(UInt(3.W)) val version = Input(UInt(4.W)) - val jtag_id = Input(UInt(32.W)) + val jtag_id = Input(UInt(31.W)) val rd_data = Input(UInt(32.W)) val tdo = Output(Bool()) @@ -27,65 +26,97 @@ class rvjtag_tap extends Module with el2_lib with RequireAsyncReset { val wr_data = Output(UInt(32.W)) val wr_addr = Output(UInt(AWIDTH.W)) }) - val AWIDTH = 7.U(6.W) + val AWIDTH = 7 val USER_DR_LENGTH = AWIDTH + 34 - val sr = RegInit(0.U(USER_DR_LENGTH.W)) - val nsr = RegInit(0.U(USER_DR_LENGTH.W)) - val dr = RegInit(0.U(USER_DR_LENGTH.W)) - + val nsr = WireInit(0.U(USER_DR_LENGTH.W)) + val sr = withClockAndReset (io.tck,io.trst) {RegNext(nsr,0.U)} + val dr = WireInit(0.U(USER_DR_LENGTH.W)) /////////////////////////////////////////////////////// // Tap controller /////////////////////////////////////////////////////// - val state = RegInit(test_logic_reset_state) - val nstate = RegInit(test_logic_reset_state) - //logic[3:0] state, nstate; - val ir = WireInit(0.U(5.W)) - val jtag_reset = WireInit(UInt(1.W)) - val shift_dr = WireInit(UInt(1.W)) - val pause_dr = WireInit(UInt(1.W)) - val update_dr = WireInit(UInt(1.W)) - val capture_dr = WireInit(UInt(1.W)) - val shift_ir = WireInit(UInt(1.W)) - val pause_ir = WireInit(UInt(1.W)) - val update_ir = WireInit(UInt(1.W)) - val capture_ir = WireInit(UInt(1.W)) - val dr_en = WireInit(UInt(2.W)) - val devid_sel = WireInit(UInt(1.W)) - val abits = WireInit(UInt(6.W)) - val abits = AWIDTH(5,0) - val test_logic_reset_state :: run_test_idle_state :: select_dr_scan_state :: capture_dr_state :: shift_dr_state :: exit1_dr_state :: pause_dr_state :: exit2_dr_state :: update_dr_state :: select_ir_scan_state :: capture_ir_state :: shift_ir_state :: exit1_ir_state :: pause_ir_state :: exit2_ir_state :: update_ir_state :: Nil = Enum(16) - switch(state){ - is(test_logic_reset_state){ nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state)} - is(run_test_idle_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) } - is(select_dr_scan_state){nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) } - is(capture_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) } - is(shift_dr_state){nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) } - is(exit1_dr_state){nstate := Mux(io.tms,update_dr_state,pause_dr_state) } - is(pause_dr_state){nstate := Mux(io.tms,exit2_dr_state,pause_dr_state) } - is(exit2_dr_state){nstate := Mux(io.tms,update_dr_state,shift_dr_state) } - is(update_dr_state){nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) } - is(select_ir_scan_state){nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) } - is(capture_ir_state){nstate := Mux(io.tms,exit1_ir_state,shift_i``r_state) } - is(shift_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) } - is(exit1_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) } - is(pause_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) } - is(exit2_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) } - is(update_ir_state){nstate := Mux(io.tms,test_logic_reset_state,run_test_idle_state) } - } + val nstate = WireInit(test_logic_reset_state) + val state = withClockAndReset(io.tck,io.trst) {RegNext(nstate,test_logic_reset_state)} + val ir = WireInit(0.U(5.W)) + val jtag_reset = WireInit(Bool(),false.B) + val shift_dr = WireInit(UInt(1.W),init = 0.U) + val pause_dr = WireInit(UInt(1.W),init = 0.U) + val update_dr = WireInit(Bool(),false.B) + val capture_dr = WireInit(UInt(1.W),init = 0.U) + val shift_ir = WireInit(UInt(1.W),init = 0.U) + val pause_ir = WireInit(UInt(1.W),init = 0.U) + val update_ir = WireInit(Bool(),false.B) + val capture_ir = WireInit(UInt(1.W),init = 0.U) + val dr_en = WireInit(UInt(2.W),init = 0.U) + val devid_sel = WireInit(Bool(),false.B) + val abits = AWIDTH.U(6.W) -///////////////////////////////////////////////////////////////////////////////////////////////// + switch (state) { + is(test_logic_reset_state) {nstate := Mux(io.tms, test_logic_reset_state, run_test_idle_state) + jtag_reset := 1.U } + is(run_test_idle_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) } + is(select_dr_scan_state) {nstate := Mux(io.tms,select_ir_scan_state,capture_dr_state) } + is(capture_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) + capture_dr := 1.U } + is(shift_dr_state) {nstate := Mux(io.tms,exit1_dr_state,shift_dr_state) + shift_dr := 1.U } + is(exit1_dr_state) {nstate := Mux(io.tms,update_dr_state,pause_dr_state) } + is(pause_dr_state) {nstate := Mux(io.tms,exit2_dr_state,pause_dr_state) + pause_dr := 1.U } + is(exit2_dr_state) {nstate := Mux(io.tms,update_dr_state,shift_dr_state) } + is(update_dr_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) + update_dr := 1.U } + is(select_ir_scan_state) {nstate := Mux(io.tms,test_logic_reset_state,capture_ir_state) } + is(capture_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state) + capture_ir := 1.U } + is(shift_ir_state) {nstate := Mux(io.tms,exit1_ir_state,shift_ir_state) + shift_ir := 1.U } + is(exit1_ir_state) {nstate := Mux(io.tms,update_ir_state,pause_ir_state) } + is(pause_ir_state) {nstate := Mux(io.tms,exit2_ir_state,pause_ir_state) + pause_ir := 1.U } + is(exit2_ir_state) {nstate := Mux(io.tms,update_ir_state,shift_ir_state) } + is(update_ir_state) {nstate := Mux(io.tms,select_dr_scan_state,run_test_idle_state) + update_ir := 1.U } + } + io.tdoEnable := shift_dr | shift_ir + /////////////////////////////////////////////////////// + // IR register + ////////////////////////////////////////////////////// + ir := withClockAndReset(io.tck,io.trst) {RegNext(Mux(jtag_reset,1.U,Mux(update_ir,Mux((sr(4,0)===0.U).asBool,"h1f".U,sr(4,0)),0.U)),1.U)} + devid_sel := ir==="b00001".U(5.W) + dr_en := Cat(ir===17.U,ir===16.U) + /////////////////////////////////////////////////////// + // Shift register + /////////////////////////////////////////////////////// + when(shift_dr===1.U){ + when(dr_en(1)===true.B){nsr :=Cat(io.tdi, sr(USER_DR_LENGTH-1,1))} + .elsewhen(dr_en(0)===1.U || devid_sel===true.B){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U) , io.tdi, sr(31,1))} + .otherwise{nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),io.tdi)} // bypass + } + .elsewhen(capture_dr ===1.U){ + when(dr_en(0)){nsr := Cat(Fill(USER_DR_LENGTH-15,0.U) ,io.idle, io.dmi_stat,abits,io.version)} + .elsewhen(dr_en(1)){nsr := Cat(Fill(AWIDTH,0.U),io.rd_data,io.rd_status)} + .elsewhen(devid_sel){nsr := Cat(Fill(USER_DR_LENGTH-32,0.U),io.jtag_id,1.U)} + } + .elsewhen(shift_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-5,0.U),io.tdi,sr(4,1))} + .elsewhen(capture_ir===1.U){nsr := Cat(Fill(USER_DR_LENGTH-1,0.U),1.U)} - CAPTURE_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; - SHIFT_IR_STATE: nstate = tms ? EXIT1_IR_STATE : SHIFT_IR_STATE; - EXIT1_IR_STATE: nstate = tms ? UPDATE_IR_STATE : PAUSE_IR_STATE; - PAUSE_IR_STATE: nstate = tms ? EXIT2_IR_STATE : PAUSE_IR_STATE; - EXIT2_IR_STATE: nstate = tms ? UPDATE_IR_STATE : SHIFT_IR_STATE; - UPDATE_IR_STATE: nstate = tms ? SELECT_DR_SCAN_STATE : RUN_TEST_IDLE_STATE; - - - /////////////////////////////////////////////////////////////////////////////////////////////// + // TDO retiming + withClock(io.tck) {io.tdo:=RegNext(sr(0),0.U)} + // DMI CS register + withClockAndReset (io.tck,io.trst) {io.dmi_hard_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(17),0.U),0.U)} + withClockAndReset (io.tck,io.trst) {io.dmi_reset := RegNext(Mux(update_dr & dr_en(0).asBool(),sr(16),0.U),0.U)} + // DR register + withClockAndReset (io.tck,io.trst) {dr := RegNext(Mux(update_dr & dr_en(1).asBool(),sr,Cat(dr(USER_DR_LENGTH-1,2),0.U(2.W))),0.U)} + io.rd_en := dr(0) + io.wr_en := dr(1) + io.wr_data := dr(33,2) + io.wr_addr := dr(40,34) } +object tapmain extends App{ + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new rvjtag_tap())) +} diff --git a/src/main/scala/el2_dma_ctrl.scala b/src/main/scala/el2_dma_ctrl.scala new file mode 100644 index 00000000..cdf31208 --- /dev/null +++ b/src/main/scala/el2_dma_ctrl.scala @@ -0,0 +1,556 @@ +import chisel3._ +import chisel3.util._ +import scala.collection._ +import lib._ + +class el2_dma_ctrl extends Module with el2_lib with RequireAsyncReset { + val io = IO(new Bundle { + val free_clk = Input(Clock()) + val dma_bus_clk_en = Input(Bool()) // slave bus clock enable + val clk_override = Input(Bool()) + val scan_mode = Input(Bool()) + + // Debug signals + val dbg_cmd_addr = Input(UInt(32.W)) + val dbg_cmd_wrdata = Input(UInt(32.W)) + val dbg_cmd_valid = Input(Bool()) + val dbg_cmd_write = Input(Bool()) // 1: write command, 0: read_command + val dbg_cmd_type = Input(UInt(2.W)) // 0:gpr 1:csr 2: memory + val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command + + val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid + val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request + val dma_dbg_cmd_done = Output(Bool()) + val dma_dbg_cmd_fail = Output(Bool()) + val dma_dbg_rddata = Output(UInt(32.W)) + + // Core side signals + val dma_dccm_req = Output(Bool()) // DMA dccm request (only one of dccm/iccm will be set) + val dma_iccm_req = Output(Bool()) // DMA iccm request + val dma_mem_tag = Output(UInt(3.W)) // DMA Buffer entry number + val dma_mem_addr = Output(UInt(32.W))// DMA request address + val dma_mem_sz = Output(UInt(3.W)) // DMA request size + val dma_mem_write = Output(Bool()) // DMA write to dccm/iccm + val dma_mem_wdata = Output(UInt(64.W))// DMA write data + val dccm_dma_rvalid = Input(Bool()) // dccm data valid for DMA read + val dccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read + val dccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req + val dccm_dma_rdata = Input(UInt(64.W)) // dccm data for DMA read + val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read + val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read + val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req + val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read + + val dma_dccm_stall_any = Output(Bool()) // stall dccm pipe (bubble) so that DMA can proceed + val dma_iccm_stall_any = Output(Bool()) // stall iccm pipe (bubble) so that DMA can proceed + val dccm_ready = Input(Bool()) // dccm ready to accept DMA request + val iccm_ready = Input(Bool()) // iccm ready to accept DMA request + val dec_tlu_dma_qos_prty = Input(UInt(3.W)) // DMA QoS priority coming from MFDC [18:15] + + // PMU signals + val dma_pmu_dccm_read = Output(Bool()) + val dma_pmu_dccm_write = Output(Bool()) + val dma_pmu_any_read = Output(Bool()) + val dma_pmu_any_write = Output(Bool()) + + // AXI Write Channels + val dma_axi_awvalid = Input(Bool()) + val dma_axi_awready = Output(Bool()) + val dma_axi_awid = Input(UInt(DMA_BUS_TAG.W)) + val dma_axi_awaddr = Input(UInt(32.W)) + val dma_axi_awsize = Input(UInt(3.W)) + + val dma_axi_wvalid = Input(Bool()) + val dma_axi_wready = Output(Bool()) + val dma_axi_wdata = Input(UInt(64.W)) + val dma_axi_wstrb = Input(UInt(8.W)) + + val dma_axi_bvalid = Output(Bool()) + val dma_axi_bready = Input(Bool()) + val dma_axi_bresp = Output(UInt(2.W)) + val dma_axi_bid = Output(UInt(DMA_BUS_TAG.W)) + + // AXI Read Channels + val dma_axi_arvalid = Input(Bool()) + val dma_axi_arready = Output(Bool()) + val dma_axi_arid = Input(UInt(DMA_BUS_TAG.W)) + + val dma_axi_araddr = Input(UInt(32.W)) + val dma_axi_arsize = Input(UInt(3.W)) + + val dma_axi_rvalid = Output(Bool()) + val dma_axi_rready = Input(Bool()) + val dma_axi_rid = Output(UInt(DMA_BUS_TAG.W)) + val dma_axi_rdata = Output(UInt(64.W)) + val dma_axi_rresp = Output(UInt(2.W)) + val dma_axi_rlast = Output(Bool()) + }) + + + val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH) + + val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W))) + + val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W))) + + val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W))) + + val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W))) + + val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W))) + + val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W))) + + val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W))) + + val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W))) + + val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U) + + val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W))) + + val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W))) + + val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U) + + val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U) + + val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U) + + val fifo_empty = WireInit(UInt(1.W), 0.U) + + val dma_address_error = WireInit(UInt(1.W), 0.U) + + val dma_alignment_error = WireInit(UInt(1.W), 0.U) + + val num_fifo_vld = WireInit(UInt(4.W),0.U) + + val dma_mem_req = WireInit(UInt(1.W), 0.U) + + val dma_mem_addr_int = WireInit(UInt(32.W), 0.U) + + val dma_mem_sz_int = WireInit(UInt(3.W), 0.U) + + val dma_mem_byteen = WireInit(UInt(8.W), 0.U) + + val dma_nack_count = WireInit(UInt(3.W), 0.U) + + val dma_nack_count_csr = WireInit(UInt(3.W), 0.U) + + val bus_rsp_valid = WireInit(UInt(1.W), 0.U) + + val bus_rsp_sent = WireInit(UInt(1.W), 0.U) + + val bus_cmd_valid = WireInit(UInt(1.W), 0.U) + + val bus_cmd_sent = WireInit(UInt(1.W), 0.U) + + val bus_cmd_write = WireInit(UInt(1.W), 0.U) + + val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U) + + val bus_cmd_byteen = WireInit(UInt(8.W), 0.U) + + val bus_cmd_sz = WireInit(UInt(3.W), 0.U) + + val bus_cmd_addr = WireInit(UInt(32.W), 0.U) + + val bus_cmd_wdata = WireInit(UInt(64.W), 0.U) + + val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U) + + val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U) + + val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U) + + val bus_posted_write_done = WireInit(UInt(1.W), 0.U) + + val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U) + + val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U) + + val axi_mstr_priority = WireInit(UInt(1.W), 0.U) + + val axi_mstr_sel = WireInit(UInt(1.W), 0.U) + + val axi_rsp_sent = WireInit(UInt(1.W), 0.U) + + val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U) + + val wrbuf_vld = WireInit(UInt(1.W), 0.U) + + val wrbuf_data_vld = WireInit(UInt(1.W), 0.U) + + val rdbuf_vld = WireInit(UInt(1.W), 0.U) + + val dma_free_clk = Wire(Clock()) + + val dma_bus_clk = Wire(Clock()) + + val dma_buffer_c1_clk = Wire(Clock()) + + val fifo_byteen_in = WireInit(UInt(8.W), 0.U) + + //------------------------LOGIC STARTS HERE--------------------------------- + + + // DCCM Address check + + val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),DCCM_SADR.U,DCCM_SIZE) + + // PIC memory address check + + val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),PIC_BASE_ADDR.U,PIC_SIZE) + + // ICCM Address check + + val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),ICCM_SADR.U,ICCM_SIZE) else (0.U,0.U) + + // FIFO inputs + + val fifo_addr_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_addr(31,0), bus_cmd_addr(31,0)) + + fifo_byteen_in := Mux(io.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_cmd_addr(2)), bus_cmd_byteen(7,0)) + + val fifo_sz_in = Mux(io.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0)) + + val fifo_write_in = Mux(io.dbg_cmd_valid.asBool, io.dbg_cmd_write, bus_cmd_write) + + val fifo_posted_write_in = !io.dbg_cmd_valid & bus_cmd_posted_write + + val fifo_dbg_in = io.dbg_cmd_valid + + + fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_)) + + fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_)) + + fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_)) + + fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_)) + + fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_)) + + fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) | (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_)) + + fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_)) + + fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), Cat(0.U, io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error)))))) + + (0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag), io.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_cmd_valid, Fill(2, io.dbg_cmd_wrdata), bus_cmd_wdata(63,0))))))) + + fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)}) + + fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) + + fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) + + fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) + + fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))}) + + (0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())}) + + fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_)) + + fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_)) + + fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode)) + + (0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))}) + + (0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))}) + + (0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))}) + + // Pointer logic + + NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U) + + NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U) + + NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U) + + val WrPtrEn = fifo_cmd_en.orR + + val RdPtrEn = (io.dma_dccm_req | io.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error)) + + val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) + + WrPtr := withClock(dma_free_clk) { + RegEnable(NxtWrPtr, 0.U, WrPtrEn) + } + + RdPtr := withClock(dma_free_clk) { + RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool) + } + + RspPtr := withClock(dma_free_clk) { + RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool) + } + + // Miscellaneous signal + + val fifo_full = fifo_full_spec_bus; + + val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U) + val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U) + + num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent)) + + num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_) + + num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2 + + val fifo_full_spec = (num_fifo_vld_tmp2 >= DMA_BUF_DEPTH.asUInt()) + + val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus) + + // Error logic + + dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM + dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error & + (((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned + ((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned + ((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned + (dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size + (dma_mem_addr_in_dccm & io.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size + (io.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)), + (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)), + (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)), + (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)))) =/= 15.U)) | // Write byte enables not aligned for word store + (io.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store + + //Dbg outputs + + io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus + io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr)) + io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0)) + io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR + + dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed + + // Block the decode if fifo full + + io.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr) + io.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr); + + // Used to indicate ready to debug + + fifo_empty := ~(fifo_valid.orR) + + // Nack counter, stall the lsu pipe if 7 nacks + + dma_nack_count_csr := io.dec_tlu_dma_qos_prty + val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.dma_dccm_req | io.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.dma_dccm_req | io.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U)) + + dma_nack_count := withClock(dma_free_clk) { + RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool) + } + + // Core outputs + + dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error) + io.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.dccm_ready; + io.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready; + io.dma_mem_tag := RdPtr + dma_mem_addr_int := fifo_addr(RdPtr) + dma_mem_sz_int := fifo_sz(RdPtr) + io.dma_mem_addr := Mux(io.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0)) + io.dma_mem_sz := Mux(io.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0)) + dma_mem_byteen := fifo_byteen(RdPtr) + io.dma_mem_write := fifo_write(RdPtr) + io.dma_mem_wdata := fifo_data(RdPtr) + + // PMU outputs + + io.dma_pmu_dccm_read := io.dma_dccm_req & !io.dma_mem_write; + io.dma_pmu_dccm_write := io.dma_dccm_req & io.dma_mem_write; + io.dma_pmu_any_read := (io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write; + io.dma_pmu_any_write := (io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write; + + // Inputs + + fifo_full_spec_bus := withClock(dma_bus_clk) { + RegNext(fifo_full_spec, 0.U) + } + + dbg_dma_bubble_bus := withClock(dma_bus_clk) { + RegNext(io.dbg_dma_bubble, 0.U) + } + + dma_dbg_cmd_done_q := withClock(io.free_clk) { + RegNext(io.dma_dbg_cmd_done, 0.U) + } + + // Clock Gating logic + + val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_cmd_valid | io.clk_override + val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override) + + val dma_buffer_c1cgc = Module(new rvclkhdr) + dma_buffer_c1cgc.io.en := dma_buffer_c1_clken + dma_buffer_c1cgc.io.scan_mode := io.scan_mode + dma_buffer_c1cgc.io.clk := clock + dma_buffer_c1_clk := dma_buffer_c1cgc.io.l1clk + + val dma_free_cgc = Module(new rvclkhdr) + dma_free_cgc.io.en := dma_free_clken + dma_free_cgc.io.scan_mode := io.scan_mode + dma_free_cgc.io.clk := clock + dma_free_clk := dma_free_cgc.io.l1clk + + val dma_bus_cgc = Module(new rvclkhdr) + dma_bus_cgc.io.en := io.dma_bus_clk_en + dma_bus_cgc.io.scan_mode := io.scan_mode + dma_bus_cgc.io.clk := clock + dma_bus_clk := dma_bus_cgc.io.l1clk + + // Write channel buffer + + val wrbuf_en = io.dma_axi_awvalid & io.dma_axi_awready + val wrbuf_data_en = io.dma_axi_wvalid & io.dma_axi_wready + val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write + val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en + val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en + + wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)} + + wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)} + + val wrbuf_tag = withClock(dma_bus_clk) { + RegEnable(io.dma_axi_awid, 0.U, wrbuf_en) + } + + val wrbuf_sz = withClock(dma_bus_clk) { + RegEnable(io.dma_axi_awsize, 0.U, wrbuf_en) + } + + val wrbuf_addr = rvdffe(io.dma_axi_awaddr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode) + + val wrbuf_data = rvdffe(io.dma_axi_wdata, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode) + + val wrbuf_byteen = withClock(dma_bus_clk) { + RegEnable(io.dma_axi_wstrb, 0.U, wrbuf_data_en) + } + + // Read channel buffer + + val rdbuf_en = io.dma_axi_arvalid & io.dma_axi_arready + val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write + val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en + + rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)} + + val rdbuf_tag = withClock(dma_bus_clk) { + RegEnable(io.dma_axi_arid, 0.U, rdbuf_en) + } + + val rdbuf_sz = withClock(dma_bus_clk) { + RegEnable(io.dma_axi_arsize, 0.U, rdbuf_en) + } + + val rdbuf_addr = rvdffe(io.dma_axi_araddr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode) + + io.dma_axi_awready := ~(wrbuf_vld & !wrbuf_cmd_sent) + io.dma_axi_wready := ~(wrbuf_data_vld & !wrbuf_cmd_sent) + io.dma_axi_arready := ~(rdbuf_vld & !rdbuf_cmd_sent) + + //Generate a single request from read/write channel + + bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld + bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt + bus_cmd_write := axi_mstr_sel + bus_cmd_posted_write := 0.U; + bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr) + bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz) + bus_cmd_wdata := wrbuf_data + bus_cmd_byteen := wrbuf_byteen + bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag) + bus_cmd_mid := 0.U + bus_cmd_prty := 0.U + + // Sel=1 -> write has higher priority + + axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld) + val axi_mstr_prty_in = ~axi_mstr_priority + val axi_mstr_prty_en = bus_cmd_sent + + axi_mstr_priority := withClock(dma_bus_clk) { + RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool) + } + + val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr) + val axi_rsp_rdata = fifo_data(RspPtr) + val axi_rsp_write = fifo_write(RspPtr) + val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U)); + + val axi_rsp_tag = fifo_tag(RspPtr) + + // AXI response channel signals + + io.dma_axi_bvalid := axi_rsp_valid & axi_rsp_write + io.dma_axi_bresp := axi_rsp_error(1,0) + io.dma_axi_bid := axi_rsp_tag + + io.dma_axi_rvalid := axi_rsp_valid & !axi_rsp_write + io.dma_axi_rresp := axi_rsp_error + io.dma_axi_rdata := axi_rsp_rdata(63,0) + io.dma_axi_rlast := 1.U + io.dma_axi_rid := axi_rsp_tag + + bus_posted_write_done := 0.U + bus_rsp_valid := (io.dma_axi_bvalid | io.dma_axi_rvalid) + bus_rsp_sent := ((io.dma_axi_bvalid & io.dma_axi_bready) | (io.dma_axi_rvalid & io.dma_axi_rready)) +} +object dma extends App{ + chisel3.Driver.emitVerilog(new el2_dma_ctrl) +} \ No newline at end of file diff --git a/src/main/scala/el2_pic_ctl.scala b/src/main/scala/el2_pic_ctl.scala new file mode 100644 index 00000000..561d4998 --- /dev/null +++ b/src/main/scala/el2_pic_ctl.scala @@ -0,0 +1,426 @@ +import chisel3._ +import chisel3.util._ +import include._ +import lib._ +import chisel3.experimental.chiselName +@chiselName +class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib { + val io = IO (new Bundle { + val scan_mode = Input(Bool()) + val free_clk = Input(Clock () ) + val active_clk = Input(Clock () ) + val clk_override = Input(Bool () ) + val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) + val picm_rdaddr = Input(UInt(32.W)) + val picm_wraddr = Input(UInt(32.W)) + val picm_wr_data = Input(UInt(32.W)) + val picm_wren = Input(Bool()) + val picm_rden = Input(Bool()) + val picm_mken = Input(Bool()) + val meicurpl = Input(UInt(4.W)) + val meipt = Input(UInt(4.W)) + + val mexintpend = Output(Bool()) + val claimid = Output(UInt(8.W)) + val pl = Output(UInt(4.W)) + val picm_rd_data = Output(UInt(32.W)) + val mhwakeup = Output(Bool()) + //val level_intpend_w_prior_en = Output(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) + + }) + + //def el2_cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) = + // (Mux(a_priority 32 + case x if x < 64 => 64 + case x if x < 128 => 128 + case x if x < 256 => 256 + case x if x < 512 => 512 + case _ => 1024 + + } + + val INT_GRPS = INTPEND_SIZE / 32 + val INTPRIORITY_BITS = 4 + val ID_BITS = 8 + val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U) + + val intpend_rd_out = WireInit(0.U(32.W)) + val intenable_rd_out = WireInit(0.U(1.W)) + val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) + val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W)) + val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W)) + val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))/////////////////// + val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W))) + val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W)))) + for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U + val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W)))) + for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U + val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(INTPRIORITY_BITS.W))) + for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_w_prior_en_ff(i) := 0.U + val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(ID_BITS.W))) + for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_id_ff(i) := 0.U + val config_reg = WireInit(0.U(1.W)) + val intpriord = WireInit(0.U(1.W)) + val prithresh_reg_write = WireInit(0.U(1.W)) + val prithresh_reg_read = WireInit(0.U(1.W)) + val picm_wren_ff = WireInit(0.U(1.W)) + val picm_rden_ff = WireInit(0.U(1.W)) + val picm_raddr_ff = WireInit(0.U(32.W)) + val picm_waddr_ff = WireInit(0.U(32.W)) + val picm_wr_data_ff = WireInit(0.U(32.W)) + val mask = WireInit(0.U(4.W)) + val picm_mken_ff = WireInit(0.U(1.W)) + val claimid_in = WireInit(0.U(ID_BITS.W)) + //val extintsrc_req_gw = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W))) + + // clocks + val pic_raddr_c1_clk = Wire(Clock()) + val pic_data_c1_clk = Wire(Clock()) + val pic_pri_c1_clk = Wire(Clock()) + val pic_int_c1_clk = Wire(Clock()) + val gw_config_c1_clk = Wire(Clock()) + + withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)} + withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)} + withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)} + withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)} + withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)} + withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)} + + val temp_raddr_intenable_base_match = ~(picm_raddr_ff ^ INTENABLE_BASE_ADDR.asUInt) + val raddr_intenable_base_match = temp_raddr_intenable_base_match(31,NUM_LEVELS+2).andR//// (31,NUM_LEVELS+2) + + val raddr_intpriority_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val raddr_config_gw_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val raddr_config_pic_match = picm_raddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0) + val addr_intpend_base_match = picm_raddr_ff(31,6) === (INTPEND_BASE_ADDR>>6).asUInt + + val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0) + val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CLEAR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val waddr_intpriority_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val waddr_config_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) + val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff) + + // ---- Clock gating section ------ + // c1 clock enables + val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override + val pic_data_c1_clken = io.picm_wren | io.clk_override + val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override + val pic_int_c1_clken = (waddr_intenable_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override + val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override + + // C1 - 1 clock pulse for data + pic_raddr_c1_clk := rvclkhdr(clock,pic_raddr_c1_clken,io.scan_mode) + pic_data_c1_clk := rvclkhdr(clock,pic_data_c1_clken,io.scan_mode) + pic_pri_c1_clk := rvclkhdr(clock,pic_pri_c1_clken.asBool,io.scan_mode) + pic_int_c1_clk := rvclkhdr(clock,pic_int_c1_clken.asBool,io.scan_mode) + gw_config_c1_clk := rvclkhdr(clock,gw_config_c1_clken.asBool,io.scan_mode) + + // ------ end clock gating section ------------------------ + val extintsrc_req_sync = Cat(rvsyncss(io.extintsrc_req(PIC_TOTAL_INT_PLUS1-1,1),io.free_clk),io.extintsrc_req(0)) + + val intpriority_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intpriority_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U) + val intpriority_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intpriority_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U) + val intenable_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_intenable_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U) + val intenable_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_intenable_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U) + val gw_config_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){waddr_config_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U) + val gw_config_reg_re = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){raddr_config_gw_base_match & (picm_raddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_rden_ff} else 0.U) + val gw_clear_reg_we = (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){addr_clear_gw_base_match & (picm_waddr_ff(NUM_LEVELS+1,2) === i.asUInt) & picm_wren_ff} else 0.U) + val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) + (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ intpriority_reg(i) := withClock(pic_pri_c1_clk){RegEnable(picm_wr_data_ff(INTPRIORITY_BITS-1,0),0.U,intpriority_reg_we(i).asBool)}} else intpriority_reg(i) := 0.U(INTPRIORITY_BITS.W)) + val intenable_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(1.W))) + (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){intenable_reg(i) := withClock(pic_int_c1_clk){RegEnable(picm_wr_data_ff(0),0.U,intenable_reg_we(i).asBool)}} else intenable_reg(i) := 0.U(1.W)) + val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W))) + (0 until PIC_TOTAL_INT_PLUS1).map (i => if(i>0){ gw_config_reg(i) := withClock(gw_config_c1_clk){RegEnable(picm_wr_data_ff(1,0),0.U,gw_config_reg_we(i).asBool)}} else gw_config_reg(i) := 0.U(2.W)) + + val extintsrc_req_gw = (0 until PIC_TOTAL_INT_PLUS1).map(i=>if(i>0) + el2_configurable_gw(extintsrc_req_sync(i), gw_config_reg(i)(0), gw_config_reg(i)(1), gw_clear_reg_we(i).asBool()) + else 0.U) + + //val intpriord = WireInit(Bool(), false.B) + (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpriority_reg_inv(i) := Mux(intpriord.asBool, ~intpriority_reg(i), intpriority_reg(i))) + (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i) := Fill(INTPRIORITY_BITS, extintsrc_req_gw(i) & intenable_reg(i)) & intpriority_reg_inv(i)) + (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i) := i.U) + + + + + + if (PIC_2CYCLE == 1) { + val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(INTPRIORITY_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there + val level_intpend_id = Wire(Vec((NUM_LEVELS/2)+1, Vec(PIC_TOTAL_INT_PLUS1+3, UInt(ID_BITS.W)))) //PIC_TOTAL_INT_PLUS1+3 should be there + for(i<-0 until (NUM_LEVELS/2)+1; j<-0 until PIC_TOTAL_INT_PLUS1+3){ //PIC_TOTAL_INT_PLUS1+3 should be there + level_intpend_w_prior_en(i)(j) := 0.U + level_intpend_id(i)(j) := 0.U + } + + + level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W)) + level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W)) + + levelx_intpend_w_prior_en(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W)) + levelx_intpend_id(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W)) + + /// Do the prioritization of the interrupts here //////////// + for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) { + + if ( m == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt) { + level_intpend_w_prior_en(l+1)(m+1) := 0.U + level_intpend_id(l+1)(m+1) := 0.U + }else { val a = 0.U} + val (out_id, out_priority) = el2_cmp_and_mux(level_intpend_id(l)(2*m), level_intpend_w_prior_en(l)(2*m), level_intpend_id(l)((2*m)+1), level_intpend_w_prior_en(l)((2*m)+1)) + level_intpend_id(l+1)(m) := out_id + level_intpend_w_prior_en(l+1)(m) := out_priority + } + + (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))}) + (0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))}) + + for (j <-NUM_LEVELS/2 until NUM_LEVELS ; k <- 0 to ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).toInt)) { + + if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) { + levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U + levelx_intpend_id(j + 1)(k + 1) := 0.U + }else { val a = 0.U} + val (out_id1, out_priority1) = el2_cmp_and_mux(level_intpend_id(j)(2*k), level_intpend_w_prior_en(j)(2*k), level_intpend_id(j)(2*k+1), level_intpend_w_prior_en(j)(2*k+1)) + (levelx_intpend_id(j+1)(k)) := out_id1 + (levelx_intpend_w_prior_en(j+1)(k)) := out_priority1 + + } + claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output + selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0) + } + else { + val level_intpend_w_prior_en = Wire(Vec((NUM_LEVELS)+1, Vec(PIC_TOTAL_INT_PLUS1+2, UInt(INTPRIORITY_BITS.W)))) + val level_intpend_id = Wire(Vec((NUM_LEVELS)+1, Vec(PIC_TOTAL_INT_PLUS1+2, UInt(ID_BITS.W)))) + dontTouch(level_intpend_id) + for(i<-0 until (NUM_LEVELS)+1; j<-0 until PIC_TOTAL_INT_PLUS1+2){ + level_intpend_w_prior_en(i)(j) := 0.U + level_intpend_id(i)(j) := 0.U + } + level_intpend_w_prior_en(0) := Range(0,PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(Fill(INTPRIORITY_BITS,0.U),Fill(INTPRIORITY_BITS,0.U)) + level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(Fill(ID_BITS,1.U),Fill(ID_BITS,1.U)) /*Cat((1.U((1*ID_BITS).W)),*///l2_intpend_id_ff//) + dontTouch(level_intpend_w_prior_en(0)) + + /// Do the prioritization of the interrupts here //////////// + for (l <-0 until NUM_LEVELS ) { + for (m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,l+1)).toInt) { + if ( m == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,l+1).toInt) { + level_intpend_w_prior_en(l+1)(m+1) := 0.U + level_intpend_id(l+1)(m+1) := 0.U + }else { val a = 0.U} + val (out_id, out_priority) = el2_cmp_and_mux(level_intpend_id(l)(2*m), level_intpend_w_prior_en(l)(2*m), level_intpend_id(l)(2*m+1), level_intpend_w_prior_en(l)(2*m+1)) + level_intpend_id(l+1)(m) := out_id + level_intpend_w_prior_en(l+1)(m) := out_priority + dontTouch(level_intpend_id(l)(2*m)) + }} + claimid_in := level_intpend_id(NUM_LEVELS)(0) // This is the last level output + selected_int_priority := level_intpend_w_prior_en(NUM_LEVELS)(0) + dontTouch(selected_int_priority) + + } + + // io.level_intpend_w_prior_en := (0 to NUM_LEVELS).map(i=>(0 to PIC_TOTAL_INT_PLUS1+1).map(j=> + // level_intpend_w_prior_en(i)(j)).reverse.reduce(Cat(_,_))).reverse.reduce(Cat(_,_)) + + /////////////////////////////////////////////////////////////////////// + // Config Reg` + /////////////////////////////////////////////////////////////////////// + + val config_reg_we = waddr_config_pic_match & picm_wren_ff + val config_reg_re = raddr_config_pic_match & picm_rden_ff + val config_reg_in = picm_wr_data_ff(0) + withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)} + intpriord := config_reg + + + + val pl_in = selected_int_priority + /////////////////////////////////////////////////////////// + /// ClaimId Reg and Corresponding PL + /////////////////////////////////////////////////////////// + val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt + withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)} + withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)} + val meipt_inv = Mux(intpriord.asBool,~io.meipt,io.meipt) + val meicurpl_inv = Mux(intpriord.asBool,~io.meicurpl,io.meicurpl) + val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv) + io.mexintpend := withClock(io.free_clk){RegNext(mexintpend_in,0.U)} + val maxint = Mux(intpriord.asBool,0.U,15.U) + val mhwakeup_in = pl_in_q === maxint + io.mhwakeup := withClock(io.free_clk){RegNext(mhwakeup_in,0.U)} + + ////////////////////////////////////////////////////////////////////////// + // Reads of register. + // 1- intpending + ////////////////////////////////////////////////////////////////////////// + val intpend_reg_read = addr_intpend_base_match & picm_rden_ff + val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff + val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff + val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff + + intpend_reg_extended := Cat(Fill(INTPEND_SIZE-PIC_TOTAL_INT_PLUS1,0.U),(0 until PIC_TOTAL_INT_PLUS1/*extintsrc_req_gw.size*/).map(i => extintsrc_req_gw(i)).reverse.reduce(Cat(_,_))) + + val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W))) + (0 until INT_GRPS).map (i=> intpend_rd_part_out(i) := Fill(32,(intpend_reg_read & picm_raddr_ff(5,2)) === i.asUInt) & intpend_reg_extended((32*i)+31,32*i))//.reverse.reduce(Cat(_,_)) + intpend_rd_out := (0 until INT_GRPS).map (i=>intpend_rd_part_out(i)).reduce (_|_) + for(i <- 0 until PIC_TOTAL_INT_PLUS1) { when (intenable_reg_re(i).asBool){ intenable_rd_out := intenable_reg(i)}.otherwise {intenable_rd_out :=0.U} } + + val intpriority_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> intpriority_reg_re(i).asBool -> intpriority_reg(i))) + val gw_config_rd_out = MuxCase(0.U,(0 until PIC_TOTAL_INT_PLUS1).map (i=> gw_config_reg_re(i).asBool -> gw_config_reg(i))) + ////////////////////////////////////////////////////////////////////////////////////////////////// + + val picm_rd_data_in = WireInit(UInt(32.W),0.U) + picm_rd_data_in := Mux1H(Seq( + intpend_reg_read.asBool -> intpend_rd_out, + intpriority_reg_read.asBool -> Cat(Fill(32-INTPRIORITY_BITS,0.U),intpriority_rd_out ) , + intenable_reg_read.asBool -> Cat(Fill(31,0.U),intenable_rd_out), + gw_config_reg_read.asBool -> Cat(Fill(30,0.U),gw_config_rd_out) , + config_reg_re.asBool -> Cat(Fill(31,0.U),config_reg) , + (picm_mken_ff & mask(3)).asBool -> Cat(Fill(30,0.U) , "b11".U(2.W)) , + (picm_mken_ff & mask(2)).asBool -> Cat(Fill(31,0.U) , "b1".U(1.W)), + (picm_mken_ff & mask(1)).asBool -> Cat(Fill(28,0.U) , "b1111".U(4.W)) , + (picm_mken_ff & mask(0)).asBool -> Fill(32,0.U) )) + + + io.picm_rd_data := Mux(picm_bypass_ff.asBool, picm_wr_data_ff, picm_rd_data_in) + val address = picm_raddr_ff(14,0) + + mask := 1.U(4.W) + switch (address) { + is ("b011000000000000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b100000000000100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000001000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000001100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000010000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000010100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000011000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000011100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000100000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000100100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000101000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000101100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000110000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000110100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000111000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000000111100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001000000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001000100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001001000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001001100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001010000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001010100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001011000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001011100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001100000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001100100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001101000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001101100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001110000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001110100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001111000".U(15.W)) {mask := "b1000".U(4.W)} + is ("b100000001111100".U(15.W)) {mask := "b1000".U(4.W)} + is ("b010000000000100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000001000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000001100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000010000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000010100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000011000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000011100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000100000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000100100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000101000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000101100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000110000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000110100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000111000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000000111100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001000000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001000100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001001000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001001100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001010000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001010100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001011000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001011100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001100000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001100100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001101000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001101100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001110000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001110100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001111000".U(15.W)) {mask := "b0100".U(4.W)} + is ("b010000001111100".U(15.W)) {mask := "b0100".U(4.W)} + is ("b000000000000100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000001000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000001100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000010000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000010100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000011000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000011100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000100000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000100100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000101000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000101100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000110000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000110100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000111000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000000111100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001000000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001000100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001001000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001001100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001010000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001010100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001011000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001011100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001100000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001100100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001101000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001101100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001110000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001110100".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001111000".U(15.W)) {mask := "b0010".U(4.W)} + is ("b000000001111100".U(15.W)) {mask := "b0010".U(4.W)} + + } + +} + +object pic_main extends App{ + println("Generating Verilog...") + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_pic_ctrl())) +} \ No newline at end of file diff --git a/src/main/scala/el2_pic_ctrl.scala b/src/main/scala/el2_pic_ctrl.scala deleted file mode 100644 index 9565885a..00000000 --- a/src/main/scala/el2_pic_ctrl.scala +++ /dev/null @@ -1,271 +0,0 @@ -//import chisel3._ -//import chisel3.util._ -//import include._ -//import lib._ -//import snapshot._ -// -//class el2_pic_ctrl extends Module with RequireAsyncReset with el2_lib { -// val io = IO (new Bundle { -// val scan_mode = Input(Bool()) -// val free_clk = Input(Clock () ) -// val active_clk = Input(Clock () ) -// val clk_override = Input(Bool () ) -// val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W)) -// val picm_rdaddr = Input(UInt(32.W)) -// val picm_wraddr = Input(UInt(32.W)) -// val picm_wr_data = Input(UInt(32.W)) -// val picm_wren = Input(Bool()) -// val picm_rden = Input(Bool()) -// val picm_mken = Input(Bool()) -// val meicurpl = Input(UInt(4.W)) -// val meipt = Input(UInt(4.W)) -// -// val mexintpend = Output(Bool()) -// val claimid = Output(UInt(8.W)) -// val pl = Output(UInt(4.W)) -// val picm_rd_data = Output(UInt(32.W)) -// val mhwakeup = Output(Bool()) -// val test = Output(UInt()) -// }) -// -// io.mexintpend := 0.U -// io.claimid := 0.U -// io.pl := 0.U -// io.picm_rd_data := 0.U -// io.mhwakeup := 0.U -// -// val NUM_LEVELS = log2Ceil(PIC_TOTAL_INT_PLUS1) -// val INTPRIORITY_BASE_ADDR = PIC_BASE_ADDR -// val INTPEND_BASE_ADDR = PIC_BASE_ADDR + 0x00001000L -// val INTENABLE_BASE_ADDR = PIC_BASE_ADDR + 0x00002000L -// val EXT_INTR_PIC_CONFIG = PIC_BASE_ADDR + 0x00003000L -// val EXT_INTR_GW_CONFIG = PIC_BASE_ADDR + 0x00004000L -// val EXT_INTR_GW_CLEAR = PIC_BASE_ADDR + 0x00005000L -// -// val INTPEND_SIZE = PIC_TOTAL_INT_PLUS1 match { -// case x if x < 32 => 32 -// case x if x < 64 => 64 -// case x if x < 128 => 128 -// case x if x < 256 => 256 -// case x if x < 512 => 512 -// case _ => 1024 -// -// } -// -// val INT_GRPS = INTPEND_SIZE / 32 -// val INTPRIORITY_BITS = 4 -// val ID_BITS = 8 -// val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U) -// -// // val addr_intpend_base_match = WireInit(0.U(1.W)) -// // val raddr_config_pic_match = WireInit(0.U(1.W)) -// // val raddr_intenable_base_match = WireInit(0.U(1.W)) -//// val raddr_intpriority_base_match = WireInit(0.U(1.W)) -// // val raddr_config_gw_base_match = WireInit(0.U(1.W)) -// // val waddr_config_pic_match = WireInit(0.U(1.W)) -// // val waddr_intpriority_base_match = WireInit(0.U(1.W)) -// // val waddr_intenable_base_match = WireInit(0.U(1.W)) -// // val waddr_config_gw_base_match = WireInit(0.U(1.W)) -// // val addr_clear_gw_base_match = WireInit(0.U(1.W)) -//// val mexintpend_in = WireInit(0.U(1.W)) -// // val mhwakeup_in = WireInit(0.U(1.W)) -// // val intpend_reg_read = WireInit(0.U(1.W)) -// val picm_rd_data_in = WireInit(0.U(32.W)) -// val intpend_rd_out = WireInit(0.U(32.W)) -//// val intenable_rd_out = WireInit(0.U(1.W)) -// val intpriority_rd_out = WireInit(0.U (INTPRIORITY_BITS.W)) -// val gw_config_rd_out = WireInit(0.U(2.W)) -// val intpriority_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) -// intpriority_reg := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U) -// // val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) -// // intpriority_reg_inv := (0 until PIC_TOTAL_INT_PLUS1).map(i => 0.U) -// val intpriority_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val intpriority_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val gw_config_reg = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(2.W))) -// val intenable_reg = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val intenable_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val intenable_reg_re = WireInit(Bool(), init = false.B) -// val gw_config_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val gw_config_reg_re = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// val gw_clear_reg_we = WireInit(0.U (PIC_TOTAL_INT_PLUS1.W)) -// // -// val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W)) -//// val maxint = WireInit(0.U (INTPRIORITY_BITS.W)) -// val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W)) -//// val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W))) -//// val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W))) -// //val intpend_rd_part_out = Wire(Vec(INT_GRPS,UInt(32.W))) -// // val levelx_intpend_w_prior_en = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(INTPRIORITY_BITS.W)))) -//// val levelx_intpend_id = Wire(Vec(NUM_LEVELS - NUM_LEVELS/2 ,Vec ((PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int])+1,UInt(ID_BITS.W)))) -//// val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(INTPRIORITY_BITS.W))) -// // val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / math.pow(2,NUM_LEVELS/2).asInstanceOf[Int],UInt(ID_BITS.W))) -// val config_reg = WireInit(0.U(1.W)) -//// val intpriord = WireInit(0.U(1.W)) -//// val config_reg_we = WireInit(0.U(1.W)) -//// val config_reg_re = WireInit(0.U(1.W)) -//// val config_reg_in = WireInit(0.U(1.W)) -// val prithresh_reg_write = WireInit(0.U(1.W)) -// val prithresh_reg_read = WireInit(0.U(1.W)) -// // val intpriority_reg_read = WireInit(0.U(1.W)) -// //val intenable_reg_read = WireInit(0.U(1.W)) -// //val gw_config_reg_read = WireInit(0.U(1.W)) -// val picm_wren_ff = WireInit(0.U(1.W)) -// val picm_rden_ff = WireInit(0.U(1.W)) -// val picm_raddr_ff = WireInit(0.U(32.W)) -// val picm_waddr_ff = WireInit(0.U(32.W)) -// val picm_wr_data_ff = WireInit(0.U(32.W)) -// val mask = WireInit(0.U(4.W)) -// val picm_mken_ff = WireInit(0.U(1.W)) -// val claimid_in = WireInit(0.U(ID_BITS.W)) -// val pl_in = WireInit(0.U(INTPRIORITY_BITS.W)) -// // val pl_in_q = WireInit(0.U(INTPRIORITY_BITS.W)) -// val extintsrc_req_sync = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W)) -// val extintsrc_req_gw = WireInit(0.U(PIC_TOTAL_INT_PLUS1.W)) -// // val picm_bypass_ff = WireInit(0.U(1.W)) -// -// // clocks -// val pic_raddr_c1_clk = Wire(Clock()) -// val pic_data_c1_clk = Wire(Clock()) -// val pic_pri_c1_clk = Wire(Clock()) -// val pic_int_c1_clk = Wire(Clock()) -// val gw_config_c1_clk = Wire(Clock()) -// -// withClock(pic_raddr_c1_clk) {picm_raddr_ff := RegNext(io.picm_rdaddr,0.U)} -// withClock(pic_data_c1_clk) {picm_waddr_ff := RegNext (io.picm_wraddr,0.U)} -// withClock(io.active_clk) {picm_wren_ff := RegNext(io.picm_wren,0.U)} -// withClock(io.active_clk) {picm_rden_ff := RegNext(io.picm_rden,0.U)} -// withClock(io.active_clk) {picm_mken_ff := RegNext(io.picm_mken,0.U)} -// withClock(pic_data_c1_clk) {picm_wr_data_ff := RegNext(io.picm_wr_data,0.U)} -// -// val raddr_intenable_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR >>(NUM_LEVELS+2)).asUInt//// (31,NUM_LEVELS+2) -// val raddr_intpriority_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val raddr_config_gw_base_match = picm_raddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val raddr_config_pic_match = picm_raddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0) -// val addr_intpend_base_match = picm_raddr_ff(31,6) === (INTPEND_BASE_ADDR>>6).asUInt -// -// val waddr_config_pic_match = picm_waddr_ff(31,0) === (EXT_INTR_PIC_CONFIG).asUInt //(31,0) -// val addr_clear_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CLEAR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val waddr_intpriority_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTPRIORITY_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val waddr_intenable_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (INTENABLE_BASE_ADDR>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val waddr_config_gw_base_match = picm_waddr_ff(31,NUM_LEVELS+2) === (EXT_INTR_GW_CONFIG>>NUM_LEVELS+2).asUInt// (31,NUM_LEVELS+2) -// val picm_bypass_ff = picm_rden_ff & picm_wren_ff & ( picm_raddr_ff === picm_waddr_ff) -// -// // ---- Clock gating section ------ -// // c1 clock enables -// val pic_raddr_c1_clken = io.picm_mken | io.picm_rden | io.clk_override -// val pic_data_c1_clken = io.picm_wren | io.clk_override -// val pic_pri_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intpriority_base_match & picm_rden_ff) | io.clk_override -// val pic_int_c1_clken = (waddr_intpriority_base_match & picm_wren_ff) | (raddr_intenable_base_match & picm_rden_ff) | io.clk_override -// val gw_config_c1_clken = (waddr_config_gw_base_match & picm_wren_ff) | (raddr_config_gw_base_match & picm_rden_ff) | io.clk_override -// -// // C1 - 1 clock pulse for data -// val pic_addr_c1_cgc = Module(new rvclkhdr) -// pic_addr_c1_cgc.io.en := pic_raddr_c1_clken ; pic_raddr_c1_clk := pic_addr_c1_cgc.io.l1clk -// pic_addr_c1_cgc.io.clk := clock ; pic_addr_c1_cgc.io.scan_mode := io.scan_mode -// -// val pic_data_c1_cgc = Module(new rvclkhdr) -// pic_data_c1_cgc.io.en := pic_data_c1_clken ; pic_data_c1_clk := pic_data_c1_cgc.io.l1clk -// pic_data_c1_cgc.io.clk := clock ; pic_data_c1_cgc.io.scan_mode := io.scan_mode -// -// val pic_pri_c1_cgc = Module(new rvclkhdr) -// pic_pri_c1_cgc.io.en := pic_pri_c1_clken ; pic_pri_c1_clk := pic_pri_c1_cgc.io.l1clk -// pic_pri_c1_cgc.io.clk := clock ; pic_pri_c1_cgc.io.scan_mode := io.scan_mode -// -// val pic_int_c1_cgc = Module(new rvclkhdr) -// pic_int_c1_cgc.io.en := pic_int_c1_clken ; pic_int_c1_clk := pic_int_c1_cgc.io.l1clk -// pic_int_c1_cgc.io.clk := clock ; pic_int_c1_cgc.io.scan_mode := io.scan_mode -// -// val gw_config_c1_cgc = Module(new rvclkhdr) -// gw_config_c1_cgc.io.en := gw_config_c1_clken ; gw_config_c1_clk := gw_config_c1_cgc.io.l1clk -// gw_config_c1_cgc.io.clk := clock ; gw_config_c1_cgc.io.scan_mode := io.scan_mode -// -// // ------ end clock gating section ------------------------ -// -// -// val sync_inst = Module(new rvsyncss(PIC_TOTAL_INT_PLUS1-1)) -// sync_inst.io.din := io.extintsrc_req>>1 -// extintsrc_req_sync := Cat(sync_inst.io.dout, io.extintsrc_req(0)) -// sync_inst.io.clk := io.free_clk -// -// io.test := extintsrc_req_sync -// /////////////////////////////////////////////////////////////////////// -// // Config Reg` -// /////////////////////////////////////////////////////////////////////// -// -// val config_reg_we = waddr_config_pic_match & picm_wren_ff -// val config_reg_re = raddr_config_pic_match & picm_rden_ff -// val config_reg_in = picm_wr_data_ff(0) -// withClock(io.free_clk){config_reg := RegEnable(config_reg_in,0.U,config_reg_we.asBool)} -// val intpriord = config_reg -// -//// /////////////////////////////////////////////////////////// -//// /// ClaimId Reg and Corresponding PL -//// /////////////////////////////////////////////////////////// -//// val pl_in_q = Mux(intpriord.asBool,~pl_in,pl_in).asUInt -//// withClock(io.free_clk){io.claimid := RegNext(claimid_in,0.U)} -//// withClock(io.free_clk){io.pl := RegNext(pl_in_q,0.U)} -//// val meipt_inv = Mux(intpriord.asBool,!io.meipt,io.meipt) -//// val meicurpl_inv = Mux(intpriord.asBool,!io.meicurpl,io.meicurpl) -//// val mexintpend_in = ( selected_int_priority > meipt_inv) & ( selected_int_priority > meicurpl_inv) -//// withClock(io.free_clk){io.mexintpend := RegNext(mexintpend_in,0.U)} -//// val maxint = Mux(intpriord.asBool,0.U,15.U) -//// val mhwakeup_in = pl_in_q === maxint -//// withClock(io.free_clk){io.mhwakeup := RegNext(mhwakeup_in,0.U)} -//// -//// ////////////////////////////////////////////////////////////////////////// -//// // Reads of register. -//// // 1- intpending -//// ////////////////////////////////////////////////////////////////////////// -//// val intpend_reg_read = addr_intpend_base_match & picm_rden_ff -//// val intpriority_reg_read = raddr_intpriority_base_match & picm_rden_ff -//// val intenable_reg_read = raddr_intenable_base_match & picm_rden_ff -//// val gw_config_reg_read = raddr_config_gw_base_match & picm_rden_ff -//// -////// val intpend_reg_extended = Cat(INTPEND_SIZE - PIC_TOTAL_INT_PLUS1 , extintsrc_req_gw) -////// assign intpend_reg_extended[INTPEND_SIZE-1:0] = {{INTPEND_SIZE-pt.PIC_TOTAL_INT_PLUS1{1'b0}},extintsrc_req_gw[pt.PIC_TOTAL_INT_PLUS1-1:0]} ; -//// -//// val intpend_rd_part_out = (0 until INT_GRPS).map (i=> Fill(32,intpend_reg_read & picm_raddr_ff(5,2) === i.asUInt) & intpend_reg_extended((32*i)+31,32*i)).reverse.reduce(Cat(_,_)) -//// intpend_rd_out := VecInit.tabulate(INT_GRPS)(i=>intpend_rd_part_out(i)).reverse.reduce (_|_) -//// val intenable_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intenable_reg_re(i)) intenable_reg(i) else 0.U) -//// val intpriority_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (intpriority_reg_re(i)) intpriority_reg(i) else 0.U) -//// val gw_config_rd_out = (0 until PIC_TOTAL_INT_PLUS1).map (i=> if (gw_config_reg_re(i)) gw_config_reg(i) else 0.U) -//// ////////////////////////////////////////////////////////////////////////////////////////////////// -//// /* -//// -//// for (int i=0; i io.dec_tlu_br0_r_pkt + bp_ctl_ch.io.exu_i0_br_fghr_r := io.exu_i0_br_fghr_r + bp_ctl_ch.io.exu_i0_br_index_r := io.exu_i0_br_index_r + bp_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb + bp_ctl_ch.io.dec_tlu_flush_leak_one_wb := io.dec_tlu_flush_leak_one_wb + bp_ctl_ch.io.dec_tlu_bpred_disable := io.dec_tlu_bpred_disable + bp_ctl_ch.io.exu_mp_pkt <> io.exu_mp_pkt + bp_ctl_ch.io.exu_mp_eghr := io.exu_mp_eghr + bp_ctl_ch.io.exu_mp_fghr := io.exu_mp_fghr + bp_ctl_ch.io.exu_mp_index := io.exu_mp_index + bp_ctl_ch.io.exu_mp_btag := io.exu_mp_btag + bp_ctl_ch.io.exu_flush_final := io.exu_flush_final + + // mem-ctl wiring + mem_ctl_ch.io.free_clk := io.free_clk + mem_ctl_ch.io.active_clk := io.active_clk + mem_ctl_ch.io.exu_flush_final := io.exu_flush_final + mem_ctl_ch.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb + mem_ctl_ch.io.dec_tlu_flush_err_wb := io.dec_tlu_flush_err_wb + mem_ctl_ch.io.dec_tlu_i0_commit_cmt := io.dec_tlu_i0_commit_cmt + mem_ctl_ch.io.dec_tlu_force_halt := io.dec_tlu_force_halt + mem_ctl_ch.io.ifc_fetch_addr_bf := ifc_ctl_ch.io.ifc_fetch_addr_bf + mem_ctl_ch.io.ifc_fetch_uncacheable_bf := ifc_ctl_ch.io.ifc_fetch_uncacheable_bf + mem_ctl_ch.io.ifc_fetch_req_bf := ifc_ctl_ch.io.ifc_fetch_req_bf + mem_ctl_ch.io.ifc_fetch_req_bf_raw := ifc_ctl_ch.io.ifc_fetch_req_bf_raw + mem_ctl_ch.io.ifc_iccm_access_bf := ifc_ctl_ch.io.ifc_iccm_access_bf + mem_ctl_ch.io.ifc_region_acc_fault_bf := ifc_ctl_ch.io.ifc_region_acc_fault_bf + mem_ctl_ch.io.ifc_dma_access_ok := ifc_ctl_ch.io.ifc_dma_access_ok + mem_ctl_ch.io.dec_tlu_fence_i_wb := io.dec_tlu_fence_i_wb + mem_ctl_ch.io.ifu_bp_hit_taken_f := bp_ctl_ch.io.ifu_bp_hit_taken_f + mem_ctl_ch.io.ifu_bp_inst_mask_f := bp_ctl_ch.io.ifu_bp_inst_mask_f + mem_ctl_ch.io.ifu_axi_arready := io.ifu_axi_arready + mem_ctl_ch.io.ifu_axi_rvalid := io.ifu_axi_rvalid + mem_ctl_ch.io.ifu_axi_rid := io.ifu_axi_rid + mem_ctl_ch.io.ifu_axi_rdata := io.ifu_axi_rdata + mem_ctl_ch.io.ifu_axi_rresp := io.ifu_axi_rresp + mem_ctl_ch.io.ifu_bus_clk_en := io.ifu_bus_clk_en + mem_ctl_ch.io.dma_iccm_req := io.dma_iccm_req + mem_ctl_ch.io.dma_mem_addr := io.dma_mem_addr + mem_ctl_ch.io.dma_mem_sz := io.dma_mem_sz + mem_ctl_ch.io.dma_mem_write := io.dma_mem_write + mem_ctl_ch.io.dma_mem_wdata := io.dma_mem_wdata + mem_ctl_ch.io.dma_mem_tag := io.dma_mem_tag + mem_ctl_ch.io.ic_rd_data := io.ic_rd_data + mem_ctl_ch.io.ic_debug_rd_data := io.ic_debug_rd_data + mem_ctl_ch.io.ictag_debug_rd_data := io.ictag_debug_rd_data + mem_ctl_ch.io.ic_eccerr := io.ic_eccerr + mem_ctl_ch.io.ic_parerr := io.ic_parerr + mem_ctl_ch.io.ic_rd_hit := io.ic_rd_hit + mem_ctl_ch.io.ic_tag_perr := io.ic_tag_perr + mem_ctl_ch.io.iccm_rd_data := io.iccm_rd_data + mem_ctl_ch.io.iccm_rd_data_ecc := io.iccm_rd_data_ecc + mem_ctl_ch.io.ifu_fetch_val := mem_ctl_ch.io.ic_fetch_val_f + mem_ctl_ch.io.dec_tlu_ic_diag_pkt <> io.dec_tlu_ic_diag_pkt + mem_ctl_ch.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable + mem_ctl_ch.io.scan_mode := io.scan_mode + + // Connecting the final outputs + io.ifu_axi_awvalid := mem_ctl_ch.io.ifu_axi_awvalid + io.ifu_axi_awid := mem_ctl_ch.io.ifu_axi_awid + io.ifu_axi_awaddr := mem_ctl_ch.io.ifu_axi_awaddr + io.ifu_axi_awregion := mem_ctl_ch.io.ifu_axi_awregion + io.ifu_axi_awlen := mem_ctl_ch.io.ifu_axi_awlen + io.ifu_axi_awsize := mem_ctl_ch.io.ifu_axi_awsize + io.ifu_axi_awburst := mem_ctl_ch.io.ifu_axi_awburst + io.ifu_axi_awlock := mem_ctl_ch.io.ifu_axi_awlock + io.ifu_axi_awcache := mem_ctl_ch.io.ifu_axi_awcache + io.ifu_axi_awprot := mem_ctl_ch.io.ifu_axi_awprot + io.ifu_axi_awqos := mem_ctl_ch.io.ifu_axi_awqos + io.ifu_axi_wvalid := mem_ctl_ch.io.ifu_axi_wvalid + io.ifu_axi_wdata := mem_ctl_ch.io.ifu_axi_wdata + io.ifu_axi_wstrb := mem_ctl_ch.io.ifu_axi_wstrb + io.ifu_axi_wlast := mem_ctl_ch.io.ifu_axi_wlast + io.ifu_axi_bready := mem_ctl_ch.io.ifu_axi_bready + // AXI Read Channel + io.ifu_axi_arvalid := mem_ctl_ch.io.ifu_axi_arvalid + io.ifu_axi_arid := mem_ctl_ch.io.ifu_axi_arid + io.ifu_axi_araddr := mem_ctl_ch.io.ifu_axi_araddr + io.ifu_axi_arregion := mem_ctl_ch.io.ifu_axi_arregion + io.ifu_axi_arlen := mem_ctl_ch.io.ifu_axi_arlen + io.ifu_axi_arsize := mem_ctl_ch.io.ifu_axi_arsize + io.ifu_axi_arburst := mem_ctl_ch.io.ifu_axi_arburst + io.ifu_axi_arlock := mem_ctl_ch.io.ifu_axi_arlock + io.ifu_axi_arcache := mem_ctl_ch.io.ifu_axi_arcache + io.ifu_axi_arprot := mem_ctl_ch.io.ifu_axi_arprot + io.ifu_axi_arqos := mem_ctl_ch.io.ifu_axi_arqos + io.ifu_axi_rready := mem_ctl_ch.io.ifu_axi_rready + io.iccm_dma_ecc_error := mem_ctl_ch.io.iccm_dma_ecc_error + io.iccm_dma_rvalid := mem_ctl_ch.io.iccm_dma_rvalid + io.iccm_dma_rdata := mem_ctl_ch.io.iccm_dma_rdata + io.iccm_dma_rtag := mem_ctl_ch.io.iccm_dma_rtag + io.iccm_ready := mem_ctl_ch.io.iccm_ready + io.ifu_pmu_instr_aligned := aln_ctl_ch.io.ifu_pmu_instr_aligned + io.ifu_pmu_fetch_stall := ifc_ctl_ch.io.ifu_pmu_fetch_stall + io.ifu_ic_error_start := mem_ctl_ch.io.ic_error_start + // I$ + io.ic_rw_addr := mem_ctl_ch.io.ic_rw_addr + io.ic_wr_en := mem_ctl_ch.io.ic_wr_en + io.ic_rd_en := mem_ctl_ch.io.ic_rd_en + io.ic_wr_data := mem_ctl_ch.io.ic_wr_data + io.ic_debug_wr_data := mem_ctl_ch.io.ic_debug_wr_data + io.ifu_ic_debug_rd_data := mem_ctl_ch.io.ifu_ic_debug_rd_data + io.ic_sel_premux_data := mem_ctl_ch.io.ic_sel_premux_data + io.ic_debug_addr := mem_ctl_ch.io.ic_debug_addr + io.ic_debug_rd_en := mem_ctl_ch.io.ic_debug_rd_en + io.ic_debug_wr_en := mem_ctl_ch.io.ic_debug_wr_en + io.ic_debug_tag_array := mem_ctl_ch.io.ic_debug_tag_array + io.ic_debug_way := mem_ctl_ch.io.ic_debug_way + io.ic_tag_valid := mem_ctl_ch.io.ic_tag_valid + io.iccm_rw_addr := mem_ctl_ch.io.iccm_rw_addr + io.iccm_wren := mem_ctl_ch.io.iccm_wren + io.iccm_rden := mem_ctl_ch.io.iccm_rden + io.iccm_wr_data := mem_ctl_ch.io.iccm_wr_data + io.iccm_wr_size := mem_ctl_ch.io.iccm_wr_size + io.ifu_iccm_rd_ecc_single_err := mem_ctl_ch.io.iccm_rd_ecc_single_err + // Performance counter + io.ifu_pmu_ic_miss := mem_ctl_ch.io.ifu_pmu_ic_miss + io.ifu_pmu_ic_hit := mem_ctl_ch.io.ifu_pmu_ic_hit + io.ifu_pmu_bus_error := mem_ctl_ch.io.ifu_pmu_bus_error + io.ifu_pmu_bus_busy := mem_ctl_ch.io.ifu_pmu_bus_busy + io.ifu_pmu_bus_trxn := mem_ctl_ch.io.ifu_pmu_bus_trxn + // + io.ifu_i0_icaf := aln_ctl_ch.io.ifu_i0_icaf + io.ifu_i0_icaf_type := aln_ctl_ch.io.ifu_i0_icaf_type + io.ifu_i0_valid := aln_ctl_ch.io.ifu_i0_valid + io.ifu_i0_icaf_f1 := aln_ctl_ch.io.ifu_i0_icaf_f1 + io.ifu_i0_dbecc := aln_ctl_ch.io.ifu_i0_dbecc + io.iccm_dma_sb_error := mem_ctl_ch.io.iccm_dma_sb_error + io.ifu_i0_instr := aln_ctl_ch.io.ifu_i0_instr + io.ifu_i0_pc := aln_ctl_ch.io.ifu_i0_pc + io.ifu_i0_pc4 := aln_ctl_ch.io.ifu_i0_pc4 + io.ifu_miss_state_idle := mem_ctl_ch.io.ifu_miss_state_idle + // Aligner branch data + io.i0_brp <> aln_ctl_ch.io.i0_brp + io.ifu_i0_bp_index := aln_ctl_ch.io.ifu_i0_bp_index + io.ifu_i0_bp_fghr := aln_ctl_ch.io.ifu_i0_bp_fghr + io.ifu_i0_bp_btag := aln_ctl_ch.io.ifu_i0_bp_btag + io.ifu_i0_cinst := aln_ctl_ch.io.ifu_i0_cinst + io.ifu_ic_debug_rd_data_valid := mem_ctl_ch.io.ifu_ic_debug_rd_data_valid + io.iccm_buf_correct_ecc := mem_ctl_ch.io.iccm_buf_correct_ecc + io.iccm_correction_state := mem_ctl_ch.io.iccm_correction_state + io.ic_premux_data := mem_ctl_ch.io.ic_premux_data +} + +object ifu_comp extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu())) +} diff --git a/src/main/scala/ifu/el2_ifu_aln_ctl.scala b/src/main/scala/ifu/el2_ifu_aln_ctl.scala new file mode 100644 index 00000000..c3b64aeb --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_aln_ctl.scala @@ -0,0 +1,421 @@ +package ifu +import lib._ +import chisel3._ +import chisel3.util._ +import include._ + +class el2_ifu_aln_ctl extends Module with el2_lib with RequireAsyncReset { + val io = IO(new Bundle{ + val scan_mode = Input(Bool()) + val active_clk = Input(Clock()) + val ifu_async_error_start = Input(Bool()) + val iccm_rd_ecc_double_err = Input(Bool()) + val ic_access_fault_f = Input(Bool()) + val ic_access_fault_type_f = Input(UInt(2.W)) + val ifu_bp_fghr_f = Input(UInt(BHT_GHR_SIZE.W)) + val ifu_bp_btb_target_f = Input(UInt(31.W)) + val ifu_bp_poffset_f = Input(UInt(12.W)) + val ifu_bp_hist0_f = Input(UInt(2.W)) + val ifu_bp_hist1_f = Input(UInt(2.W)) + val ifu_bp_pc4_f = Input(UInt(2.W)) + val ifu_bp_way_f = Input(UInt(2.W)) + val ifu_bp_valid_f = Input(UInt(2.W)) + val ifu_bp_ret_f = Input(UInt(2.W)) + val exu_flush_final = Input(Bool()) + val dec_i0_decode_d = Input(Bool()) + val ifu_fetch_data_f = Input(UInt(32.W)) + val ifu_fetch_val = Input(UInt(2.W)) + val ifu_fetch_pc = Input(UInt(31.W)) + ///////////////////////////////////////////////// + val ifu_i0_valid = Output(Bool()) + val ifu_i0_icaf = Output(Bool()) + val ifu_i0_icaf_type = Output(UInt(2.W)) + val ifu_i0_icaf_f1 = Output(Bool()) + val ifu_i0_dbecc = Output(Bool()) + val ifu_i0_instr = Output(UInt(32.W)) + val ifu_i0_pc = Output(UInt(31.W)) + val ifu_i0_pc4 = Output(Bool()) + val ifu_fb_consume1 = Output(Bool()) + val ifu_fb_consume2 = Output(Bool()) + val ifu_i0_bp_index = Output(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) + val ifu_i0_bp_fghr = Output(UInt(BHT_GHR_SIZE.W)) + val ifu_i0_bp_btag = Output(UInt(BTB_BTAG_SIZE.W)) + val ifu_pmu_instr_aligned = Output(Bool()) + val ifu_i0_cinst = Output(UInt(16.W)) + val i0_brp = Output(new el2_br_pkt_t) + }) + io.ifu_i0_valid := 0.U + io.ifu_i0_icaf := 0.U + io.ifu_i0_icaf_type := 0.U + io.ifu_i0_icaf_f1 := 0.U + io.ifu_i0_dbecc := 0.U + io.ifu_i0_instr := 0.U + io.ifu_i0_pc := 0.U + io.ifu_i0_pc4 := 0.U + io.ifu_fb_consume1 := 0.U + io.ifu_fb_consume2 := 0.U + io.ifu_i0_bp_index := 0.U + io.ifu_i0_bp_fghr := 0.U + io.ifu_i0_bp_btag := 0.U + io.ifu_pmu_instr_aligned := 0.U + io.ifu_i0_cinst := 0.U + val MHI = 46+BHT_GHR_SIZE // 54 + val MSIZE = 47+BHT_GHR_SIZE // 55 + val BRDATA_SIZE = 12 + val error_stall_in = WireInit(Bool(),0.U) + val alignval = WireInit(UInt(2.W), 0.U) + val q0final = WireInit(UInt(32.W), 0.U) + val q1final = WireInit(UInt(16.W), 0.U) + val wrptr_in = WireInit(UInt(2.W), init = 0.U) + val rdptr_in = WireInit(UInt(2.W), init = 0.U) + + val f2val_in = WireInit(UInt(2.W), init = 0.U) + val f1val_in = WireInit(UInt(2.W), init = 0.U) + val f0val_in = WireInit(UInt(2.W), init = 0.U) + + val q2off_in = WireInit(UInt(1.W), init = 0.U) + val q1off_in = WireInit(UInt(1.W), init = 0.U) + val q0off_in = WireInit(UInt(1.W), init = 0.U) + + val sf0_valid = WireInit(Bool(), init = 0.U) + val sf1_valid = WireInit(Bool(), init = 0.U) + + val f2_valid = WireInit(Bool(), init = 0.U) + val ifvalid = WireInit(Bool(), init = 0.U) + val shift_f2_f1 = WireInit(Bool(), init = 0.U) + val shift_f2_f0 = WireInit(Bool(), init = 0.U) + val shift_f1_f0 = WireInit(Bool(), init = 0.U) + + val f0icaf = WireInit(Bool(), init = 0.U) + val f1icaf = WireInit(Bool(), init = 0.U) + + val sf0val = WireInit(UInt(2.W), 0.U) + val sf1val = WireInit(UInt(2.W), 0.U) + + val misc0 = WireInit(UInt((MHI+1).W), 0.U) + val misc1 = WireInit(UInt((MHI+1).W), 0.U) + val misc2 = WireInit(UInt((MHI+1).W), 0.U) + + val brdata1 = WireInit(UInt(12.W), init = 0.U) + val brdata0 = WireInit(UInt(12.W), init = 0.U) + val brdata2 = WireInit(UInt(12.W), init = 0.U) + + val q0 = WireInit(UInt(32.W), init = 0.U) + val q1 = WireInit(UInt(32.W), init = 0.U) + val q2 = WireInit(UInt(32.W), init = 0.U) + + val f1pc_in = WireInit(UInt(31.W), 0.U) + val f0pc_in = WireInit(UInt(31.W), 0.U) + val error_stall = WireInit(Bool(), 0.U) + val f2_wr_en = WireInit(Bool(), 0.U) + val shift_4B = WireInit(Bool(), 0.U) + val f1_shift_wr_en = WireInit(Bool(), 0.U) + val f0_shift_wr_en = WireInit(Bool(), 0.U) + val qwen = WireInit(UInt(3.W), 0.U) + val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U) + val misc_data_in = WireInit(UInt((MHI+1).W), 0.U) + + val fetch_to_f0 = WireInit(Bool(), 0.U) + val fetch_to_f1 = WireInit(Bool(), 0.U) + val fetch_to_f2 = WireInit(Bool(), 0.U) + val f1_shift_2B = WireInit(Bool(), 0.U) + val first4B = WireInit(Bool(), 0.U) + val shift_2B = WireInit(Bool(), 0.U) + val f0_shift_2B = WireInit(Bool(), 0.U) + + error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final + + error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)} + val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)} + val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)} + + val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)} + val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)} + val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)} + + val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)} + val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)} + val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)} + + val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode) + val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode) + val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode) + + brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode) + brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode) + brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode) + + misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode) + misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode) + misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode) + + q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode) + q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode) + q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode) + + f2_wr_en := fetch_to_f2 + f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B + f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B + + val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U) + qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid) + + rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U, + (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U, + (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U, + (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U, + (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U, + (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U, + (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr)) + + wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U, + (qwen(1) & !io.exu_flush_final).asBool -> 2.U, + (qwen(2) & !io.exu_flush_final).asBool -> 0.U, + (!ifvalid & !io.exu_flush_final).asBool->wrptr)) + + q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B), + (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B), + (!qwen(2) & (rdptr===0.U)).asBool->q2off)) + + q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B), + (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B), + (!qwen(1) & (rdptr===2.U)).asBool->q1off)) + + q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B), + (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B), + (!qwen(0) & (rdptr===1.U)).asBool -> q0off)) + + val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off, + (rdptr===1.U)->q1off, + (rdptr===2.U)->q2off)) + + val q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off)) + + val q0sel = Cat(q0ptr, !q0ptr) + + val q1sel = Cat(q1ptr, !q1ptr) + + misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f, + io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f) + + val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0), + qren(1).asBool()->Cat(misc2, misc1), + qren(2).asBool()->Cat(misc0, misc2))) + + val misc1eff = misceff(misceff.getWidth-1,MHI+1) + val misc0eff = misceff(MHI, 0) + + + val f1dbecc = misc1eff(misc1eff.getWidth-1) + f1icaf := misc1eff(misc1eff.getWidth-2) + val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4) + val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35) + val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) + val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0) + + val f0dbecc = misc0eff(misc1eff.getWidth-1) + f0icaf := misc0eff(misc1eff.getWidth-2) + val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4) + val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35) + val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE) + val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0) + + brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1), + io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0), + io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0)) + + val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0), + qren(1).asBool->Cat(brdata2,brdata1), + qren(2).asBool->Cat(brdata0,brdata2))) + + val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12)) + + val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6))) + val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6))) + + val f0ret = Cat(brdata0final(6),brdata0final(0)) + val f0brend = Cat(brdata0final(7),brdata0final(1)) + val f0way = Cat(brdata0final(8),brdata0final(2)) + val f0pc4 = Cat(brdata0final(9),brdata0final(3)) + val f0hist0 = Cat(brdata0final(10),brdata0final(4)) + val f0hist1 = Cat(brdata0final(11),brdata0final(5)) + + val f1ret = Cat(brdata1final(6),brdata1final(0)) + val f1brend = Cat(brdata1final(7),brdata1final(1)) + val f1way = Cat(brdata1final(8),brdata1final(2)) + val f1pc4 = Cat(brdata1final(9),brdata1final(3)) + val f1hist0 = Cat(brdata1final(10),brdata1final(4)) + val f1hist1 = Cat(brdata1final(11),brdata1final(5)) + + + f2_valid := f2val(0) + sf1_valid := sf1val(0) + sf0_valid := sf0val(0) + + val consume_fb0 = !sf0val(0) & f0val(0) + val consume_fb1 = !sf1val(0) & f1val(0) + + io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final + io.ifu_fb_consume2 := consume_fb0 & consume_fb1 & !io.exu_flush_final + + ifvalid := io.ifu_fetch_val(0) + + shift_f1_f0 := !sf0_valid & sf1_valid + shift_f2_f0 := !sf0_valid & !sf1_valid & f2_valid + shift_f2_f1 := !sf0_valid & sf1_valid & f2_valid + + fetch_to_f0 := !sf0_valid & !sf1_valid & !f2_valid & ifvalid + fetch_to_f1 := (!sf0_valid & !sf1_valid & f2_valid & ifvalid) | + (!sf0_valid & sf1_valid & !f2_valid & ifvalid) | + ( sf0_valid & !sf1_valid & !f2_valid & ifvalid) + + fetch_to_f2 := (!sf0_valid & sf1_valid & f2_valid & ifvalid) | + ( sf0_valid & sf1_valid & !f2_valid & ifvalid) + + val f0pc_plus1 = f0pc + 1.U + + val f1pc_plus1 = f1pc + 1.U + + val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc) + + f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc, + shift_f2_f1.asBool->f2pc, + (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc)) + + f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc, + shift_f2_f0.asBool->f2pc, + shift_f1_f0.asBool->sf1pc, + (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1)) + + f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val, + (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val)) + + sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val)) + + f1val_in := Mux1H(Seq(( fetch_to_f1 & !io.exu_flush_final).asBool -> io.ifu_fetch_val, + ( shift_f2_f1 & !io.exu_flush_final).asBool->f2val, + (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val)) + + sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)), + (!shift_2B & !shift_4B).asBool->f0val)) + + f0val_in := Mux1H(Seq((fetch_to_f0 & !io.exu_flush_final).asBool->io.ifu_fetch_val, + ( shift_f2_f0 & !io.exu_flush_final).asBool->f2val, + ( shift_f1_f0 & !io.exu_flush_final).asBool->sf1val, + (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val)) + + val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0), + qren(1).asBool->Cat(q2,q1), + qren(2).asBool->Cat(q0,q2))) + val (q1eff, q0eff) = (qeff(63,32), qeff(31,0)) + + q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16))) + + q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16))) + + val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0)))) + + alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U))) + + val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf))) + + val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc))) + + val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0)))) + + val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0)))) + + val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0)))) + + val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0)))) + + val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0)))) + + val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0)))) + + val alignfromf1 = !f0val(1) & f0val(0) + + val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc)) + + io.ifu_i0_pc := f0pc + + val firstpc = f0pc + + io.ifu_i0_pc4 := first4B + + io.ifu_i0_cinst := aligndata(15,0) + + first4B := aligndata(1,0) === 3.U + + val first2B = ~first4B + + io.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0))) + + io.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0))) + + io.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype) + + val icaf_eff = alignicaf(1) | aligndbecc(1) + + io.ifu_i0_icaf_f1 := first4B & icaf_eff & alignfromf1 + + io.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0))) + + val ifirst = aligndata + + val decompressed = Module(new el2_ifu_compress_ctl()) + + io.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout)) + + val firstpc_hash = el2_btb_addr_hash(f0pc) + + val secondpc_hash = el2_btb_addr_hash(secondpc) + + val firstbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(firstpc) else el2_btb_tag_hash(firstpc) + + val secondbrtag_hash = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(secondpc) else el2_btb_tag_hash(secondpc) + + io.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0)) + + io.i0_brp.ret := (first2B & alignret(0)) | (first4B & alignret(1)) + + val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1)) + + io.i0_brp.way := Mux((first2B | alignbrend(0)).asBool, alignway(0), alignway(1)) + + io.i0_brp.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)), + (first2B & alignhist0(0)) | (first4B & alignhist0(1))) + + val i0_ends_f1 = first4B & alignfromf1 + io.i0_brp.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset) + + io.i0_brp.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett) + + io.i0_brp.br_start_error := (first4B & alignval(1) & alignbrend(0)) + + io.i0_brp.bank := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0)) + + io.i0_brp.br_error := (io.i0_brp.valid & i0_brp_pc4 & first2B) | (io.i0_brp.valid & !i0_brp_pc4 & first4B) + + io.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash) + + io.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr) + + io.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash) + + decompressed.io.din := aligndata + + val i0_shift = io.dec_i0_decode_d & ~error_stall + + io.ifu_pmu_instr_aligned := i0_shift + + shift_2B := i0_shift & first2B + shift_4B := i0_shift & first4B + + f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1)))) + f1_shift_2B := f0val(0) & !f0val(1) & shift_4B + +} +object ifu_aln extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_aln_ctl())) +} \ No newline at end of file diff --git a/src/main/scala/ifu/el2_ifu_bp_ctl.scala b/src/main/scala/ifu/el2_ifu_bp_ctl.scala new file mode 100644 index 00000000..926473f7 --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_bp_ctl.scala @@ -0,0 +1,474 @@ +package ifu +import include._ +import lib._ +import chisel3._ +import chisel3.util._ +import chisel3.experimental.chiselName + +@chiselName +class el2_ifu_bp_ctl extends Module with el2_lib with RequireAsyncReset { + val io = IO (new Bundle { + val active_clk = Input(Clock()) + val ic_hit_f = Input(Bool()) + val ifc_fetch_addr_f = Input(UInt(31.W)) + val ifc_fetch_req_f = Input(Bool()) // Fetch request generated by the IFC + // Decode packet containing information if its a brnach or not + val dec_tlu_br0_r_pkt = Input(new el2_br_tlu_pkt_t) + val exu_i0_br_fghr_r = Input(UInt(BHT_GHR_SIZE.W)) // Updated GHR from the exu + val exu_i0_br_index_r = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Way from where the btb got a hit + val dec_tlu_flush_lower_wb = Input(Bool()) + val dec_tlu_flush_leak_one_wb = Input(Bool()) + val dec_tlu_bpred_disable = Input(Bool()) + // Exu misprediction packet + val exu_mp_pkt = Input(new el2_predict_pkt_t) + val exu_mp_eghr = Input(UInt(BHT_GHR_SIZE.W)) + val exu_mp_fghr = Input(UInt(BHT_GHR_SIZE.W)) + val exu_mp_index = Input(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W)) // Misprediction index + val exu_mp_btag = Input(UInt(BTB_BTAG_SIZE.W)) + val exu_flush_final = Input(Bool()) + // Signals to the IFU containing information about brnach + val ifu_bp_hit_taken_f = Output(Bool()) + val ifu_bp_btb_target_f = Output(UInt(31.W)) + val ifu_bp_inst_mask_f = Output(Bool()) + val ifu_bp_fghr_f = Output(UInt(BHT_GHR_SIZE.W)) + val ifu_bp_way_f = Output(UInt(2.W)) + val ifu_bp_ret_f = Output(UInt(2.W)) + val ifu_bp_hist1_f = Output(UInt(2.W)) + val ifu_bp_hist0_f = Output(UInt(2.W)) + val ifu_bp_pc4_f = Output(UInt(2.W)) + val ifu_bp_valid_f = Output(UInt(2.W)) + val ifu_bp_poffset_f = Output(UInt(12.W)) + val scan_mode = Input(Bool()) + val test = Output(UInt()) + }) + + val TAG_START = 16+BTB_BTAG_SIZE + val PC4 = 4 // Branch = pc + 4 (BTB Index) + val BOFF = 3 // Branch offset (BTB Index) + val CALL = 2 // Branch CALL (BTB Index) + val RET = 1 // Branch RET (BTB Index) + val BV = 0 // Branch Valid (BTB Index) + + val LRU_SIZE = BTB_ARRAY_DEPTH + val NUM_BHT_LOOP = if(BHT_ARRAY_DEPTH > 16) 16 else BHT_ARRAY_DEPTH + val NUM_BHT_LOOP_INNER_HI = if(BHT_ARRAY_DEPTH > 16) BHT_ADDR_LO+3 else BHT_ADDR_HI + val NUM_BHT_LOOP_OUTER_LO = if(BHT_ARRAY_DEPTH > 16) BHT_ADDR_LO+4 else BHT_ADDR_LO + val BHT_NO_ADDR_MATCH = BHT_ARRAY_DEPTH <= 16 + ///////////////////////////////////////////////////////// + val leak_one_f = WireInit(Bool(), 0.U) + val bht_dir_f = WireInit(UInt(2.W), 0.U) + val dec_tlu_error_wb = WireInit(Bool(), 0.U) + val btb_error_addr_wb = WireInit(UInt((BTB_ADDR_HI-BTB_ADDR_LO+1).W), 0.U) + val btb_bank0_rd_data_way0_f = WireInit(UInt((TAG_START+1).W), 0.U) + val btb_bank0_rd_data_way1_f = WireInit(UInt((TAG_START+1).W), 0.U) + val btb_bank0_rd_data_way0_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) + val btb_bank0_rd_data_way1_p1_f = WireInit(UInt((TAG_START+1).W), 0.U) + val eoc_mask = WireInit(Bool(), 0.U) + val btb_lru_b0_f = WireInit(UInt(LRU_SIZE.W), init = 0.U) + io.test := btb_lru_b0_f + val dec_tlu_way_wb = WireInit(Bool(), 0.U) + ///////////////////////////////////////////////////////// + // Misprediction packet + val exu_mp_valid = io.exu_mp_pkt.misp & !leak_one_f + val exu_mp_boffset = io.exu_mp_pkt.boffset + val exu_mp_pc4 = io.exu_mp_pkt.pc4 + val exu_mp_call = io.exu_mp_pkt.pcall + val exu_mp_ret = io.exu_mp_pkt.pret + val exu_mp_ja = io.exu_mp_pkt.pja + val exu_mp_way = io.exu_mp_pkt.way + val exu_mp_hist = io.exu_mp_pkt.hist + val exu_mp_tgt = io.exu_mp_pkt.toffset + val exu_mp_addr = io.exu_mp_index + val exu_mp_ataken = io.exu_mp_pkt.ataken + + // Its a commit or update packet + val dec_tlu_br0_v_wb = io.dec_tlu_br0_r_pkt.valid + val dec_tlu_br0_hist_wb = io.dec_tlu_br0_r_pkt.hist + val dec_tlu_br0_addr_wb = io.exu_i0_br_index_r + val dec_tlu_br0_error_wb = io.dec_tlu_br0_r_pkt.br_error + val dec_tlu_br0_middle_wb = io.dec_tlu_br0_r_pkt.middle + val dec_tlu_br0_way_wb = io.dec_tlu_br0_r_pkt.way + val dec_tlu_br0_start_error_wb = io.dec_tlu_br0_r_pkt.br_start_error + val exu_i0_br_fghr_wb = io.exu_i0_br_fghr_r + + dec_tlu_error_wb := dec_tlu_br0_start_error_wb | dec_tlu_br0_error_wb + btb_error_addr_wb := dec_tlu_br0_addr_wb + dec_tlu_way_wb := dec_tlu_br0_way_wb + + // Hash the first PC + val btb_rd_addr_f = el2_btb_addr_hash(io.ifc_fetch_addr_f) + + // Second pc = pc +4 + val fetch_addr_p1_f = io.ifc_fetch_addr_f(30,1) + 1.U + + // Hash the second pc + val btb_rd_addr_p1_f = el2_btb_addr_hash(Cat(fetch_addr_p1_f,0.U)) + + // TODO + val btb_sel_f = Cat(~bht_dir_f(0),bht_dir_f(0)) + + // Checking of the pc is a multiple of 4, if it is fetch-start will be "01" + val fetch_start_f = Cat(io.ifc_fetch_addr_f(0),~io.ifc_fetch_addr_f(0)) + + // If there is an error write-back from the dec check if the current pc is equal to the write-bcak pc + val branch_error_collision_f = dec_tlu_error_wb & (btb_error_addr_wb === btb_rd_addr_f) + val branch_error_collision_p1_f = dec_tlu_error_wb & (btb_error_addr_wb === btb_rd_addr_p1_f) + + // If there is an error write back but the address are from different bank + val branch_error_bank_conflict_f = branch_error_collision_f & dec_tlu_error_wb + val branch_error_bank_conflict_p1_f = branch_error_collision_p1_f & dec_tlu_error_wb + + // Hashing the PC to generate the index for the btb + val fetch_rd_tag_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(io.ifc_fetch_addr_f) else el2_btb_tag_hash(io.ifc_fetch_addr_f) + val fetch_rd_tag_p1_f = if(BTB_BTAG_FOLD) el2_btb_tag_hash_fold(Cat(fetch_addr_p1_f,0.U)) else el2_btb_tag_hash(Cat(fetch_addr_p1_f,0.U)) + + // There is a misprediction and the exu is writing back + val fetch_mp_collision_f = (io.exu_mp_btag === fetch_rd_tag_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_f) + val fetch_mp_collision_p1_f = (io.exu_mp_btag === fetch_rd_tag_p1_f) & exu_mp_valid & io.ifc_fetch_req_f & (exu_mp_addr === btb_rd_addr_p1_f) + + val leak_one_f_d1 = withClock(io.active_clk) {RegNext(leak_one_f, init = 0.U)} + val dec_tlu_way_wb_f = withClock(io.active_clk) {RegNext(dec_tlu_way_wb, init = 0.U)} + val exu_mp_way_f = withClock(io.active_clk) {RegNext(exu_mp_way, init = 0.U)} + val exu_flush_final_d1 = withClock(io.active_clk) {RegNext(io.exu_flush_final, init = 0.U)} + + // If there is a flush from the lower pipe wait until the flush gets deasserted from the (decode) side + leak_one_f := (io.dec_tlu_flush_leak_one_wb & io.dec_tlu_flush_lower_wb) | (leak_one_f_d1 & io.dec_tlu_flush_lower_wb) + + // For a tag to match the branch should be valid tag should match and a fetch request should be generated + // Also there should be no bank conflict or leak-one + val tag_match_way0_f = btb_bank0_rd_data_way0_f(BV) & (btb_bank0_rd_data_way0_f(TAG_START,17) === fetch_rd_tag_f) & + !(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f + + // Similar to the way-0 -> way-1 + val tag_match_way1_f = btb_bank0_rd_data_way1_f(BV) & (btb_bank0_rd_data_way1_f(TAG_START,17) === fetch_rd_tag_f) & + !(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f + + // Similar to above matches + val tag_match_way0_p1_f = btb_bank0_rd_data_way0_p1_f(BV) & (btb_bank0_rd_data_way0_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) & + !(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f + // Similar to above matches + val tag_match_way1_p1_f = btb_bank0_rd_data_way1_p1_f(BV) & (btb_bank0_rd_data_way1_p1_f(TAG_START,17) === fetch_rd_tag_p1_f) & + !(dec_tlu_way_wb_f & branch_error_bank_conflict_f) & io.ifc_fetch_req_f & !leak_one_f + + // Reordering to avoid multiple hit + val tag_match_way0_expanded_f = Cat(tag_match_way0_f & (btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4)), + tag_match_way0_f & !(btb_bank0_rd_data_way0_f(BOFF) ^ btb_bank0_rd_data_way0_f(PC4))) + + val tag_match_way1_expanded_f = Cat(tag_match_way1_f & (btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4)), + tag_match_way1_f & !(btb_bank0_rd_data_way1_f(BOFF) ^ btb_bank0_rd_data_way1_f(PC4))) + + val tag_match_way0_expanded_p1_f = Cat(tag_match_way0_p1_f & (btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4)), + tag_match_way0_p1_f & !(btb_bank0_rd_data_way0_p1_f(BOFF) ^ btb_bank0_rd_data_way0_p1_f(PC4))) + + val tag_match_way1_expanded_p1_f = Cat(tag_match_way1_p1_f & (btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4)), + tag_match_way1_p1_f & !(btb_bank0_rd_data_way1_p1_f(BOFF) ^ btb_bank0_rd_data_way1_p1_f(PC4))) + + // Final hit calculation + val wayhit_f = tag_match_way0_expanded_f | tag_match_way1_expanded_f + + val wayhit_p1_f = tag_match_way0_expanded_p1_f | tag_match_way1_expanded_p1_f + + // Chopping off the ways that had a hit btb_vbank0_rd_data_f + // e-> Lower half o-> Upper half + val btb_bank0e_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(0).asBool->btb_bank0_rd_data_way0_f, + tag_match_way1_expanded_f(0).asBool->btb_bank0_rd_data_way1_f)) + + val btb_bank0o_rd_data_f = Mux1H(Seq(tag_match_way0_expanded_f(1).asBool->btb_bank0_rd_data_way0_f, + tag_match_way1_expanded_f(1).asBool->btb_bank0_rd_data_way1_f)) + + val btb_bank0e_rd_data_p1_f = Mux1H(Seq(tag_match_way0_expanded_p1_f(0).asBool->btb_bank0_rd_data_way0_p1_f, + tag_match_way1_expanded_p1_f(0).asBool->btb_bank0_rd_data_way1_p1_f)) + + // Making virtual banks, made from pc-bit(1) if it comes from a multiple of 4 we get the lower half of the bank + // and the upper half of the bank-0 in vbank 1 + val btb_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_f, + io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f)) + val btb_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0)->btb_bank0o_rd_data_f, + io.ifc_fetch_addr_f(0)->btb_bank0e_rd_data_p1_f)) + + // Branch prediction info is sent with the 2byte lane associated with the end of the branch. + // Cases + // BANK1 BANK0 + // ------------------------------- + // | : | : | + // ------------------------------- + // <------------> : PC4 branch, offset, should be in B1 (indicated on [2]) + // <------------> : PC4 branch, no offset, indicate PC4, VALID, HIST on [1] + // <------------> : PC4 branch, offset, indicate PC4, VALID, HIST on [0] + // <------> : PC2 branch, offset, indicate VALID, HIST on [1] + // <------> : PC2 branch, no offset, indicate VALID, HIST on [0] + + + // Make an LRU value with execution mis-prediction + val mp_wrindex_dec = 1.U << exu_mp_addr + + // Make an LRU value with current read pc + val fetch_wrindex_dec = 1.U << btb_rd_addr_f + + // Make an LRU value with current read pc + 4 + val fetch_wrindex_p1_dec = 1.U << btb_rd_addr_p1_f + + // Checking if the mis-prediction was valid or not and make a new LRU value + val mp_wrlru_b0 = mp_wrindex_dec & Fill(LRU_SIZE, exu_mp_valid) + + val vwayhit_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->wayhit_f, + io.ifc_fetch_addr_f(0).asBool->Cat(wayhit_p1_f(0), wayhit_f(1)))) & Cat(eoc_mask, 1.U(1.W)) + + // Is the update of the lru valid or not + val lru_update_valid_f = (vwayhit_f(0) | vwayhit_f(1)) & io.ifc_fetch_req_f & !leak_one_f + + val fetch_wrlru_b0 = fetch_wrindex_dec & Fill(LRU_SIZE, lru_update_valid_f) + val fetch_wrlru_p1_b0 = fetch_wrindex_p1_dec & Fill(LRU_SIZE, lru_update_valid_f) + + val btb_lru_b0_hold = ~mp_wrlru_b0 & ~fetch_wrlru_b0 + + // If there is a collision the use the mis-predicted value as output and update accordingly + val use_mp_way = fetch_mp_collision_f + val use_mp_way_p1 = fetch_mp_collision_p1_f + + // Calculate the lru next value and flop it + val btb_lru_b0_ns : UInt = Mux1H(Seq(!exu_mp_way.asBool -> mp_wrlru_b0, + tag_match_way0_f.asBool -> fetch_wrlru_b0, + tag_match_way0_p1_f.asBool -> fetch_wrlru_p1_b0)) | btb_lru_b0_hold & btb_lru_b0_f + + + val btb_lru_rd_f = Mux(use_mp_way.asBool, exu_mp_way_f, (fetch_wrindex_dec & btb_lru_b0_f).orR) + + val btb_lru_rd_p1_f = Mux(use_mp_way_p1.asBool, exu_mp_way_f, (fetch_wrindex_p1_dec & btb_lru_b0_f).orR) + + // Similar to the vbank make vlru + val btb_vlru_rd_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0) -> Cat(btb_lru_rd_f, btb_lru_rd_f), + io.ifc_fetch_addr_f(0).asBool -> Cat(btb_lru_rd_p1_f, btb_lru_rd_f))) + + // virtual way depending on pc value + val tag_match_vway1_expanded_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->tag_match_way1_expanded_f, + io.ifc_fetch_addr_f(0).asBool->Cat(tag_match_way1_expanded_p1_f(0),tag_match_way1_expanded_f(1)))) + + io.ifu_bp_way_f := tag_match_vway1_expanded_f | (~vwayhit_f & btb_vlru_rd_f) + + // update the lru + btb_lru_b0_f := rvdffe(btb_lru_b0_ns, (io.ifc_fetch_req_f|exu_mp_valid).asBool, clock, io.scan_mode) +//io.test := btb_lru_b0_ns + // Checking if the end of line is near + val eoc_near = io.ifc_fetch_addr_f(ICACHE_BEAT_ADDR_HI-1, 2).andR + + // Mask according to eoc-near and make the hit-final + eoc_mask := !eoc_near | (~io.ifc_fetch_addr_f(1,0)).orR() + + val btb_sel_data_f = WireInit(UInt(16.W), init = 0.U) + val hist1_raw = WireInit(UInt(2.W), init = 0.U) + + // Filteing out portion of BTB read after virtual banking + // Entry -> tag[pt.BTB_BTAG_SIZE-1:0], toffset[11:0], pc4, boffset, call, ret, valid + val btb_rd_tgt_f = btb_sel_data_f(15,4) + val btb_rd_pc4_f = btb_sel_data_f(3) + val btb_rd_call_f = btb_sel_data_f(1) + val btb_rd_ret_f = btb_sel_data_f(0) + + // This is 1-index shifted to that of the btb-data-read so we have 1-bit shifted + btb_sel_data_f := Mux1H(Seq(btb_sel_f(1).asBool-> btb_vbank1_rd_data_f(16,1), + btb_sel_f(0).asBool-> btb_vbank0_rd_data_f(16,1))) + + // No lower flush or bp-disabple and a fetch request is generated with virtual way hit + io.ifu_bp_hit_taken_f := (vwayhit_f & hist1_raw).orR & io.ifc_fetch_req_f & !leak_one_f_d1 & !io.dec_tlu_bpred_disable + + // If the prediction is a call or ret btb entry then do not check the bht just force a taken with data from the RAS + val bht_force_taken_f = Cat( btb_vbank1_rd_data_f(CALL) | btb_vbank1_rd_data_f(RET) , + btb_vbank0_rd_data_f(CALL) | btb_vbank0_rd_data_f(RET)) + + val bht_valid_f = vwayhit_f + + val bht_bank1_rd_data_f =WireInit(UInt(2.W), 0.U) + val bht_bank0_rd_data_f =WireInit(UInt(2.W), 0.U) + val bht_bank0_rd_data_p1_f =WireInit(UInt(2.W), 0.U) + + // Depending on pc make the virtual bank as commented above + val bht_vbank0_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_f, + io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f)) + + val bht_vbank1_rd_data_f = Mux1H(Seq(!io.ifc_fetch_addr_f(0).asBool->bht_bank1_rd_data_f, + io.ifc_fetch_addr_f(0).asBool->bht_bank0_rd_data_p1_f)) + + // Direction containing data of both banks direction + bht_dir_f := Cat((bht_force_taken_f(1) | bht_vbank1_rd_data_f(1)) & bht_valid_f(1), + (bht_force_taken_f(0) | bht_vbank0_rd_data_f(1)) & bht_valid_f(0)) + + // If the branch is taken then pass btb sel else 0 + io.ifu_bp_inst_mask_f := (io.ifu_bp_hit_taken_f & btb_sel_f(1)) | !io.ifu_bp_hit_taken_f + + // hist 1 shows both banks direction + hist1_raw := bht_force_taken_f | Cat(bht_vbank1_rd_data_f(1), bht_vbank0_rd_data_f(1)) + + // hist 0 shows the both bank strength + val hist0_raw = Cat(bht_vbank1_rd_data_f(0), bht_vbank0_rd_data_f(0)) + + // pc4: if the branch is pc+4 + val pc4_raw = Cat(vwayhit_f(1) & btb_vbank1_rd_data_f(PC4), + vwayhit_f(0) & btb_vbank0_rd_data_f(PC4)) + + // Its a call call or ret branch + val pret_raw = Cat(vwayhit_f(1) & !btb_vbank1_rd_data_f(CALL) & btb_vbank1_rd_data_f(RET), + vwayhit_f(0) & !btb_vbank0_rd_data_f(CALL) & btb_vbank0_rd_data_f(RET)) + + // count number of 1's in bht_valid + val num_valids = bht_valid_f(1) +& bht_valid_f(0) + + // To calculate a merged ghr meaning the is a overlapping 1 in sel and dir + val final_h = (btb_sel_f & bht_dir_f).orR + + val fghr = WireInit(UInt(BHT_GHR_SIZE.W), 0.U) + + val merged_ghr = Mux1H(Seq((num_valids===2.U).asBool->Cat(fghr(BHT_GHR_SIZE-3,0), 0.U, final_h), + (num_valids===1.U).asBool->Cat(fghr(BHT_GHR_SIZE-2,0), final_h), + (num_valids===0.U).asBool->Cat(fghr(BHT_GHR_SIZE-1,0)))) + + val exu_flush_ghr = io.exu_mp_fghr + val fghr_ns = Wire(UInt(BHT_GHR_SIZE.W)) + + // If there is a exu-flush use its ghr + // If there is a hit and a fetch then use the merged-ghr + // If there is no hit or fetch then hold value + fghr_ns := Mux1H(Seq(exu_flush_final_d1.asBool->exu_flush_ghr, + (!exu_flush_final_d1 & io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1).asBool -> merged_ghr, + (!exu_flush_final_d1 & !(io.ifc_fetch_req_f & io.ic_hit_f & !leak_one_f_d1)).asBool -> fghr)) + + fghr := withClock(io.active_clk) {RegNext(fghr_ns, init = 0.U)} + + io.ifu_bp_fghr_f := fghr + io.ifu_bp_hist1_f := hist1_raw + io.ifu_bp_hist0_f := hist0_raw + io.ifu_bp_pc4_f := pc4_raw + + io.ifu_bp_valid_f := vwayhit_f & ~Fill(2, io.dec_tlu_bpred_disable) + io.ifu_bp_ret_f := pret_raw + + // block fetch to calculate if there is a hit with fetch request and a taken branch then compute the branch offset + val bloc_f = Cat((bht_dir_f(0) & !fetch_start_f(0)) | (!bht_dir_f(0) & fetch_start_f(0)), + (bht_dir_f(0) & fetch_start_f(0)) | (!bht_dir_f(0) & !fetch_start_f(0))) + + val use_fa_plus = !bht_dir_f(0) & io.ifc_fetch_addr_f(0) & !btb_rd_pc4_f + + val btb_fg_crossing_f = fetch_start_f(0) & btb_sel_f(0) & btb_rd_pc4_f + val bp_total_branch_offset_f = bloc_f(1)^btb_rd_pc4_f + + val ifc_fetch_adder_prior = rvdffe(io.ifc_fetch_addr_f(30,1), (io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f).asBool, clock, io.scan_mode) + + io.ifu_bp_poffset_f := btb_rd_tgt_f + + val adder_pc_in_f = Mux1H(Seq(use_fa_plus.asBool -> fetch_addr_p1_f, + btb_fg_crossing_f.asBool -> ifc_fetch_adder_prior, + (!btb_fg_crossing_f & !use_fa_plus).asBool-> io.ifc_fetch_addr_f(30,1))) + + // Calculate the branch target by adding the offset + val bp_btb_target_adder_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(btb_rd_tgt_f,0.U)) + + val rets_out = Wire(Vec(RET_STACK_SIZE, UInt(32.W))) + rets_out := (0 until RET_STACK_SIZE).map(i=>0.U) + + // Final target if its a RET then pop else take the target pc + io.ifu_bp_btb_target_f := Mux((btb_rd_ret_f & !btb_rd_call_f & rets_out(0)(0)).asBool, + rets_out(0)(31,1),bp_btb_target_adder_f(31,1)) + + // Return stack + val bp_rs_call_target_f = rvbradder(Cat(adder_pc_in_f(29,0),bp_total_branch_offset_f, 0.U), Cat(Fill(11, 0.U),~btb_rd_pc4_f, 0.U)) + + val rs_push = btb_rd_call_f & !btb_rd_ret_f & io.ifu_bp_hit_taken_f + val rs_pop = btb_rd_ret_f & !btb_rd_call_f & io.ifu_bp_hit_taken_f + val rs_hold = !rs_push & !rs_pop + + val rsenable = (0 until RET_STACK_SIZE).map(i=> if(i==0) !rs_hold else if(i==RET_STACK_SIZE-1) rs_push else rs_push | rs_pop) + + // Make the input of the RAS + val rets_in = (0 until RET_STACK_SIZE).map(i=> if(i==0) + Mux1H(Seq(rs_push.asBool -> Cat(bp_rs_call_target_f(31,1),1.U), + rs_pop.asBool -> rets_out(1))) + else if(i==RET_STACK_SIZE-1) rets_out(i-1) + else Mux1H(Seq(rs_push.asBool->rets_out(i-1), + rs_pop.asBool ->rets_out(i+1)))) + + // Make flops for poping the data + rets_out := (0 until RET_STACK_SIZE).map(i=>rvdffe(rets_in(i), rsenable(i).asBool, clock, io.scan_mode)) + + val btb_valid = exu_mp_valid & (!dec_tlu_error_wb) + val btb_wr_tag = io.exu_mp_btag + + // Making the data to write into the BTB according the structure discribed above + val btb_wr_data = Cat(btb_wr_tag, exu_mp_tgt, exu_mp_pc4, exu_mp_boffset, exu_mp_call | exu_mp_ja, exu_mp_ret | exu_mp_ja, btb_valid) + val exu_mp_valid_write = exu_mp_valid & exu_mp_ataken + + // Enable for write on each way + val btb_wr_en_way0 = ((!exu_mp_way) & exu_mp_valid_write & (!dec_tlu_error_wb)) | ((!dec_tlu_way_wb) & dec_tlu_error_wb) + val btb_wr_en_way1 = (exu_mp_way & exu_mp_valid_write & (!dec_tlu_error_wb)) | (dec_tlu_way_wb & dec_tlu_error_wb) + + // Writing is always done from dec or exu check if the dec have a valid data + val btb_wr_addr = Mux(dec_tlu_error_wb.asBool , btb_error_addr_wb, exu_mp_addr) + val middle_of_bank = exu_mp_pc4 ^ exu_mp_boffset + + // Enable the clk enable according to the exu misprediction where it is not a RAS + val bht_wr_en0 = Fill(2, exu_mp_valid & !exu_mp_call & !exu_mp_ret & !exu_mp_ja) & Cat(middle_of_bank, ~middle_of_bank) + val bht_wr_en2 = Fill(2, dec_tlu_br0_v_wb) & Cat(dec_tlu_br0_middle_wb, ~dec_tlu_br0_middle_wb) + val bht_wr_data0 = exu_mp_hist + val bht_wr_data2 = dec_tlu_br0_hist_wb + + // Hash each read and write address + val mp_hashed = el2_btb_ghr_hash(Cat(exu_mp_addr,0.U(2.W)), io.exu_mp_eghr) + val br0_hashed_wb = el2_btb_ghr_hash(Cat(dec_tlu_br0_addr_wb,0.U(2.W)), exu_i0_br_fghr_wb) + val bht_rd_addr_hashed_f = el2_btb_ghr_hash(Cat(btb_rd_addr_f,0.U(2.W)), fghr) + val bht_rd_addr_hashed_p1_f = el2_btb_ghr_hash(Cat(btb_rd_addr_p1_f,0.U(2.W)), fghr) + + val bht_wr_addr0 = mp_hashed + val bht_wr_addr2 = br0_hashed_wb + val bht_rd_addr_f = bht_rd_addr_hashed_f + val bht_rd_addr_p1_f = bht_rd_addr_hashed_p1_f + + // BTB + // Entry -> Tag[BTB-BTAG-SIZE], toffset[12], pc4, boffset, call, ret, valid + + val btb_bank0_rd_data_way0_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way0).asBool, clock, io.scan_mode)) + val btb_bank0_rd_data_way1_out = (0 until LRU_SIZE).map(i=>rvdffe(btb_wr_data, ((btb_wr_addr===i.U) & btb_wr_en_way1).asBool, clock, io.scan_mode)) + + btb_bank0_rd_data_way0_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way0_out(i))) + btb_bank0_rd_data_way1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_f===i.U).asBool->btb_bank0_rd_data_way1_out(i))) + + // BTB read muxing + btb_bank0_rd_data_way0_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way0_out(i))) + btb_bank0_rd_data_way1_p1_f := Mux1H((0 until LRU_SIZE).map(i=>(btb_rd_addr_p1_f===i.U).asBool->btb_bank0_rd_data_way1_out(i))) + + val bht_bank_clken = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Bool()))) + val bht_bank_clk = (0 until 2).map(i=>(0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)).map(k=>rvclkhdr(clock, bht_bank_clken(i)(k), io.scan_mode))) + for(i<-0 until 2; k<- 0 until (BHT_ARRAY_DEPTH/NUM_BHT_LOOP)){ + // Checking if there is a write enable with address for the BHT + bht_bank_clken(i)(k) := (bht_wr_en0(i) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) | + (bht_wr_en2(i) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-2)===k.U) | BHT_NO_ADDR_MATCH.B)) + } + + // Writing data into the BHT (DEC-side) or (EXU-side) + val bht_bank_wr_data = (0 until 2).map(i=>(0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP).map(k=>(0 until NUM_BHT_LOOP).map(j=> + Mux((bht_wr_en2(i)&(bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.U)&(bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO,NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.U)|BHT_NO_ADDR_MATCH.B).asBool, bht_wr_data2, bht_wr_data0)))) + + val bht_bank_sel = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH/NUM_BHT_LOOP, Vec(NUM_BHT_LOOP, Bool())))) + + // We have a 2 way bht with BHT_ARRAY_DEPTH/NUM_BHT_LOOP blocks and NUM_BHT_LOOP->offset in each block + // Make enables of each flop according to the address dividing the address in 2-blocks upper block for BHT-Block and + // the lower block for the offset and run this on both of the ways + for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<- 0 until NUM_BHT_LOOP){ + bht_bank_sel(i)(k)(j) := (bht_wr_en0(i) & (bht_wr_addr0(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & ((bht_wr_addr0(BHT_ADDR_HI-BHT_ADDR_LO, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B)) | + (bht_wr_en2(i) & (bht_wr_addr2(NUM_BHT_LOOP_INNER_HI-BHT_ADDR_LO,0)===j.asUInt) & ((bht_wr_addr2(BHT_ADDR_HI-BHT_ADDR_LO, NUM_BHT_LOOP_OUTER_LO-BHT_ADDR_LO)===k.asUInt) | BHT_NO_ADDR_MATCH.B)) + } + + // Reading the BHT with i->way, k->block and the j->offset + val bht_bank_rd_data_out = Wire(Vec(2, Vec(BHT_ARRAY_DEPTH, UInt(2.W)))) + for(i<-0 until 2; k<-0 until BHT_ARRAY_DEPTH/NUM_BHT_LOOP; j<-0 until NUM_BHT_LOOP){ + bht_bank_rd_data_out(i)((16*k)+j) := withClock(bht_bank_clk(i)(k)){RegEnable(bht_bank_wr_data(i)(k)(j), 0.U, bht_bank_sel(i)(k)(j))} + } + + // Make the final read mux + bht_bank0_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) + bht_bank1_rd_data_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_f===i.U).asBool->bht_bank_rd_data_out(1)(i))) + bht_bank0_rd_data_p1_f := Mux1H((0 until BHT_ARRAY_DEPTH).map(i=>(bht_rd_addr_p1_f===i.U).asBool->bht_bank_rd_data_out(0)(i))) +} + +object ifu_bp extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_bp_ctl())) +} + diff --git a/src/main/scala/ifu/el2_ifu_compress_ctl.scala b/src/main/scala/ifu/el2_ifu_compress_ctl.scala new file mode 100644 index 00000000..18c0c38a --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_compress_ctl.scala @@ -0,0 +1,178 @@ +package ifu +import lib._ +import chisel3._ +import chisel3.util._ + +class el2_ifu_compress_ctl extends Module with el2_lib{ + val io = IO(new Bundle{ + val din = Input(UInt(16.W)) + val dout = Output(UInt(32.W)) + }) + + def pat(y : List[Int]) = (0 until y.size).map(i=> if(y(i)>=0) io.din(y(i)) else !io.din(y(i).abs)).reduce(_&_) + + val out = Wire(Vec(32, UInt(1.W))) + out := (0 until 32).map(i=> 0.U.asBool) + + out(30) := pat(List(15, -14, -13, 10, -6, -5, 0)) | pat(List(15, -14, -13, -11, 10, 0)) + + out(20) := pat(List(-14, 12, -11, -10, -9, -8, -7, -6, -5, -4, -3, -2, 1)) + + out(14) := pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | pat(List(15, -14, -13, 6, 0)) | pat(List(15, -14, -13, 5, 0)) + + out(13) := pat(List(15, -14, -13, 11, -10, 0)) | pat(List(15, -14, -13, 11, 6, 0)) | (io.din(14)&(!io.din(0))) + + out(12) := pat(List(15, -14, -13, 6, 5, 0)) | pat(List(15, -14, -13, -11, 0)) | pat(List(15, -14, -13, -10, 0)) | + pat(List(-15, -14, 1)) | pat(List(15, 14, 13)) + + out(6) := (pat(List(15, -14, -6, -5, -4, -3, -2)) & !io.din(0)) | pat(List(-14, 13)) | pat(List(15, 14, 0)) + + out(5) := (io.din(15)&(!io.din(0))) | pat(List(15, 11, 10)) | pat(List(13, -8)) | pat(List(13, 7)) | + pat(List(13, 9)) | pat(List(13, 10)) | pat(List(13, 11)) | pat(List(-14, 13)) | pat(List(15, 14)) + + out(4) := (pat(List(-14, -11, -10, -9, -8, -7))&(!io.din(0))) | (pat(List(-15, -14))&(!io.din(0))) | + (pat(List(-14, 6))&(!io.din(0))) | pat(List(-15, 14, 0)) | (pat(List(-14, 5))&(!io.din(0))) | + (pat(List(-14, 4))&(!io.din(0))) | (pat(List(-14, 3))&(!io.din(0))) | (pat(List(-14, 2))&(!io.din(0))) | + pat(List(-14, -13, 0)) + + out(3) := pat(List(-14, 13)) + + out(2) := pat(List(-14, 12, 11, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 10, -6, -5, -4, -3, -2, 1)) | + pat(List(-14, 12, 9, -6, -5, -4, -3, -2, 1)) | pat(List(-14, 12, 8, -6,-5,-4, -3, -2,1)) | + pat(List(-14, 12, 7, -6, -5, -4, -3, -2,1)) | (pat(List(15, -14,-12, -6, -5, -4, -3, -2))&(!io.din(0))) | + pat(List(-15,13,-8)) | pat(List(-15,13,7)) | pat(List(-15,13,9)) | pat(List(-15,13,10)) | + pat(List(-15,13,11)) | pat(List(-14,13)) + + out(1) := 1.U.asBool + + out(0) := 1.U.asBool + + val rs2d = io.din(6,2) + val rdd = io.din(11,7) + val rdpd = Cat(1.U(2.W), io.din(9,7)) + val rs2pd = Cat(1.U(2.W), io.din(4,2)) + + val rdrd = pat(List(-14,6,1)) | pat(List(-15,14,11,0)) | pat(List(-14,5,1)) | pat(List(-15,14,10,0)) | + pat(List(-14,4,1)) | pat(List(-15,14,9,0)) | pat(List(-14,3,1)) | pat(List(-15,14,-8,0)) | + pat(List(-14,2,1)) | pat(List(-15,14,7,0)) | pat(List(-15,1)) | pat(List(-15,-13,0)) + + val rdrs1 = pat(List(-14,12,11,1)) | pat(List(-14,12,10,1)) | pat(List(-14,12,9,1)) | + pat(List(-14,12,8,1)) | pat(List(-14,12,7,1)) | pat(List(-14,-12,-6,-5,-4,-3,-2,1)) | + pat(List(-14,12,6,1)) | pat(List(-14,12,5,1)) | pat(List(-14,12,4,1)) | pat(List(-14,12,3,1)) | + pat(List(-14,12,2,1)) | pat(List(-15,-14,-13,0)) | pat(List(-15,-14,1)) + + val rs2rs2 = pat(List(15,6,1)) | pat(List(15,5,1)) | pat(List(15,4,1)) | pat(List(15,3,1)) | pat(List(15,2,1)) | pat(List(15,14,1)) + + val rdprd = pat(List(15,-14,-13,0)) + + val rdprs1 = pat(List(15,-13,0)) | pat(List(15,14,0)) | (pat(List(14,-1))&(!io.din(0))) + + val rs2prs2 = pat(List(15,-14,-13,11,10,0)) | (pat(List(15,-1))&(!io.din(0))) + + val rs2prd = pat(List(-15,-1))&(!io.din(0)) + + val uimm9_2 = pat(List(-14,-1))&(!io.din(0)) + + val ulwimm6_2 = pat(List(-15,14,-1))&(!io.din(0)) + + val ulwspimm7_2 = pat(List(-15,14,1)) + + val rdeq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) + + val rdeq1 = pat(List(-14,12,11,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,10,-6,-5,-4,-3,-2,1)) | + pat(List(-14,12,9,-6,-5,-4,-3,-2,1)) | pat(List(-14,12,8,-6,-5,-4,-3,-2,1)) | + pat(List(-14,12,7,-6,-5,-4,-3,-2,1)) | pat(List(-15,-14,13)) + + val rs1eq2 = pat(List(-15,14,13,-11,-10,-9,8,-7)) | pat(List(14,1)) | (pat(List(-14,-1))&(!io.din(0))) + + val sbroffset8_1 = pat(List(15,14,0)) + + val simm9_4 = pat(List(-15,14,13,-11,-10,-9,8,-7)) + + val simm5_0 = pat(List(-14,-13,11,-10,0)) | pat(List(-15,-13,0)) + + val sjaloffset11_1 = pat(List(-14,13)) + + val sluimm17_12 = pat(List(-15,14,13,7)) | pat(List(-15,14,13,-8)) | pat(List(-15,14,13,9)) | pat(List(-15,14,13,10)) | pat(List(-15,14,13,11)) + + val uimm5_0 = pat(List(15,-14,-13,-11,0)) | pat(List(-15,-14,1)) + + val uswimm6_2 = pat(List(15,-1))&(!io.din(0)) + + val uswspimm7_2 = pat(List(15,14,1)) + + val l1_6 = Cat(out(6),out(5),out(4),out(3),out(2),out(1),out(0)).asUInt() + + val l1_11 = Cat(out(11),out(10),out(9),out(8),out(7)).asUInt | Mux1H(Seq(rdrd.asBool->rdd, + rdprd.asBool->rdpd, rs2prd.asBool->rs2pd, rdeq1.asBool->1.U(5.W), rdeq2.asBool->2.U(5.W))) + + val l1_14 = Cat(out(14),out(13),out(12)) + + val l1_19 = Cat(out(19),out(18),out(17),out(16),out(15)).asUInt | Mux1H(Seq(rdrs1.asBool->rdd, + rdprs1.asBool->rdpd, rs1eq2.asBool->2.U(5.W))) + + val l1_24 = Cat(out(24),out(23),out(22),out(21),out(20)).asUInt | Mux1H(Seq(rs2rs2.asBool->rs2d, + rs2prs2.asBool->rs2pd)) + + val l1_31 = Cat(out(31),out(30),out(29),out(28),out(27),out(26),out(25)).asUInt + + val l1 = Cat(l1_31,l1_24,l1_19,l1_14,l1_11,l1_6) + + val simm5d = Cat(io.din(12), io.din(6,2)) + val uimm9d = Cat(io.din(10,7), io.din(12,11), io.din(5), io.din(6)) + val simm9d = Cat(io.din(12), io.din(4,3), io.din(5), io.din(2), io.din(6)) + val ulwimm6d = Cat(io.din(5), io.din(12,10), io.din(6)) + val ulwspimm7d = Cat(io.din(3,2), io.din(12), io.din(6,4)) + val uimm5d = Cat(io.din(12), io.din(6,2)) + val sjald_1 = Cat(io.din(12), io.din(8), io.din(10,9), io.din(6), io.din(7), io.din(2), io.din(11), + io.din(5,4), io.din(3)) + val sjald_12 = repl(9, io.din(12)) + val sjald = Cat(sjald_12,sjald_1) + val sluimmd = Cat(repl(15, io.din(12)), io.din(6,2)) + + val l2_31 = l1(31,20) | + Mux1H(Seq(simm5_0.asBool->Cat(repl(7, simm5d(5)), simm5d(4,0)), + uimm9_2.asBool->Cat(0.U(2.W), uimm9d, 0.U(2.W)), + simm9_4.asBool->Cat(repl(3, simm9d(5)), simm9d(4,0), 0.U(4.W)), + ulwimm6_2.asBool->Cat(0.U(5.W), ulwimm6d, 0.U(2.W)), + ulwspimm7_2.asBool->Cat(0.U(4.W), ulwspimm7d, 0.U(2.W)), + uimm5_0.asBool->Cat(0.U(6.W), uimm5d), + sjaloffset11_1.asBool->Cat(sjald(19), sjald(9,0), sjald(10)), + sluimm17_12.asBool->sluimmd(19,8))) + + val l2_19 = l1(19,12) | Mux1H(Seq(sjaloffset11_1.asBool->sjald(19,12), + sluimm17_12.asBool->sluimmd(7,0))) + val l2 = Cat(l2_31, l2_19, l1(11,0)) + + val sbr8d = Cat(io.din(12),io.din(6),io.din(5),io.din(2),io.din(11),io.din(10),io.din(4),io.din(3),0.U) + val uswimm6d = Cat(io.din(5), io.din(12,10), io.din(6), 0.U(2.W)) + val uswspimm7d = Cat(io.din(8,7),io.din(12,9), 0.U(2.W)) + + val l3_31 = l2(31,25) | Mux1H(Seq(sbroffset8_1.asBool->Cat(repl(4,sbr8d(8)),sbr8d(7,5)), + uswimm6_2.asBool->Cat(0.U(5.W),uswimm6d(6,5)), uswspimm7_2.asBool->Cat(0.U(4.W),uswspimm7d(7,5)))) + + val l3_24 = l2(24,12) + + val l3_11 = l2(11,7) | Mux1H(Seq(sbroffset8_1.asBool->Cat(sbr8d(4,1), sbr8d(8)), + uswimm6_2.asBool->uswimm6d(4,0), + uswspimm7_2.asBool->uswspimm7d(4,0))) + + val l3 = Cat(l3_31, l3_24, l3_11, l2(6,0)) + + val legal = (pat(List(-13,-12,11,1))&(!io.din(0))) | (pat(List(-13,-12,6,1))&(!io.din(0))) | + pat(List(-15,-13,11,-1)) | (pat(List(-13,-12,5,1))&(!io.din(0))) | (pat(List(-13,-12,10,1))&(!io.din(0))) | + pat(List(-15,-13,6,-1)) | pat(List(15,-12,-1,0)) | (pat(List(-13,-12,9,1))&(!io.din(0))) | pat(List(-12,6,-1,0)) | pat(List(-15,-13,5,-1)) | + (pat(List(-13,-12,8,1))&(!io.din(0))) | pat(List(-12,5,-1,0)) | pat(List(-15,-13,10,-1)) | + (pat(List(-13,-12,7,1))&(!io.din(0))) | pat(List(12,11,-10,-1,0)) | pat(List(-15,-13,9,-1)) | + (pat(List(-13,-12,4,1))&(!io.din(0))) | pat(List(13,12,-1,0)) | pat(List(-15,-13,8,-1)) | + (pat(List(-13,-12,3,1))&(!io.din(0))) | pat(List(13,4,-1,0)) | (pat(List(-13,-12,2,1))&(!io.din(0))) | + pat(List(-15,-13,7,-1)) | pat(List(13,3,-1,0)) | pat(List(13,2,-1,0)) | pat(List(14,-13,-1)) | + pat(List(-14,-12,-1,0)) | (pat(List(15,-13,12,1))&(!io.din(0))) | (pat(List(-15,-13,-12,1))&(!io.din(0))) | + pat(List(-15,-13,12,-1)) | (pat(List(14,-13))&(!io.din(0))) + + io.dout:= l3 & repl(32, legal) +} + +object ifu_compress extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_compress_ctl())) +} diff --git a/src/main/scala/ifu/el2_ifu_ic_mem.scala b/src/main/scala/ifu/el2_ifu_ic_mem.scala new file mode 100644 index 00000000..e9457141 --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_ic_mem.scala @@ -0,0 +1,277 @@ +package ifu +import lib._ +import chisel3.{util, _} +import chisel3.util._ + +class el2_ifu_ic_mem extends Module with param{ + val io = IO(new Bundle{ + val scan_mode = Input(Bool()) + val clk_override = Input(Bool()) + val dec_tlu_core_ecc_disable = Input(Bool()) + val ic_rw_addr = Input(UInt(31.W)) + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(Bool()) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W)) + val ic_debug_rd_en = Input(Bool()) + val ic_debug_wr_en = Input(Bool()) + val ic_debug_tag_array = Input(Bool()) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_premux_data = Input(UInt(64.W)) + val ic_sel_premux_data = Input(Bool()) + val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_wr_data = Input(Vec(ICACHE_BANKS_WAY, Input(UInt(71.W)))) + + val ic_rd_data = Output(UInt(64.W)) + val ic_debug_rd_data = Output(UInt(71.W)) + val ictag_debug_rd_data = Output(UInt(26.W)) + val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) + val ic_parerr = Output(UInt(ICACHE_BANKS_WAY.W)) + val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_perr = Output(Bool()) + + }) + io.ic_tag_perr := 0.U + io.ic_rd_hit := 0.U + io.ic_parerr := 0.U + io.ic_eccerr := 0.U + io.ictag_debug_rd_data := 0.U + io.ic_debug_rd_data := 0.U + io.ic_rd_data := 0.U + val ic_tag_inst = Module(new EL2_IC_TAG()) + //ic_tag_inst.io <> io + ic_tag_inst.io.ic_tag_valid := io.ic_tag_valid + ic_tag_inst.io.dec_tlu_core_ecc_disable := io.dec_tlu_core_ecc_disable + ic_tag_inst.io.clk_override := io.clk_override + ic_tag_inst.io.ic_rw_addr := io.ic_rw_addr + ic_tag_inst.io.ic_wr_en := io.ic_wr_en + ic_tag_inst.io.ic_rd_en := io.ic_rd_en + ic_tag_inst.io.ic_debug_addr := io.ic_debug_addr + ic_tag_inst.io.ic_debug_rd_en := io.ic_debug_rd_en + ic_tag_inst.io.ic_debug_wr_en := io.ic_debug_wr_en + ic_tag_inst.io.ic_debug_tag_array := io.ic_debug_tag_array + ic_tag_inst.io.ic_debug_way := io.ic_debug_way + io.ictag_debug_rd_data := ic_tag_inst.io.ictag_debug_rd_data // Output + ic_tag_inst.io.ic_debug_wr_data := io.ic_debug_wr_data + io.ic_rd_hit := ic_tag_inst.io.ic_rd_hit // Output + io.ic_tag_perr := ic_tag_inst.io.ic_tag_perr // Output + ic_tag_inst.io.scan_mode := io.scan_mode + val ic_data_inst = Module(new EL2_IC_DATA()) + ic_data_inst.io.clk_override := io.clk_override + + ic_data_inst.io.ic_rw_addr :=io.ic_rw_addr + ic_data_inst.io.ic_wr_en := io.ic_wr_en + ic_data_inst.io.ic_rd_en := io.ic_rd_en + + ic_data_inst.io.ic_wr_data := io.ic_wr_data + io.ic_rd_data := ic_data_inst.io.ic_rd_data + ic_data_inst.io.ic_debug_wr_data := io.ic_debug_wr_data + io.ic_debug_rd_data := ic_data_inst.io.ic_debug_rd_data + io.ic_parerr := ic_data_inst.io.ic_parerr + io.ic_eccerr := ic_data_inst.io.ic_eccerr + ic_data_inst.io.ic_debug_addr := io.ic_debug_addr + ic_data_inst.io.ic_debug_rd_en := io.ic_debug_rd_en + ic_data_inst.io.ic_debug_wr_en := io.ic_debug_wr_en + ic_data_inst.io.ic_debug_tag_array := io.ic_debug_tag_array + ic_data_inst.io.ic_debug_way := io.ic_debug_way + ic_data_inst.io.ic_premux_data := io.ic_premux_data + ic_data_inst.io.ic_sel_premux_data := io.ic_sel_premux_data + + ic_data_inst.io.ic_rd_hit :=io.ic_rd_hit + ic_data_inst.io.scan_mode := io.scan_mode +} + +/////////// ICACHE TAG +class EL2_IC_TAG extends Module with el2_lib with param { + val io = IO(new Bundle{ + val scan_mode = Input(Bool()) + val clk_override = Input(Bool()) + val dec_tlu_core_ecc_disable = Input(Bool()) + val ic_rw_addr = Input(UInt(29.W)) // 32:3 + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_valid = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(Bool()) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-2).W)) // 12-2 = 10-bit value + val ic_debug_rd_en = Input(Bool()) + val ic_debug_wr_en = Input(Bool()) + val ic_debug_tag_array = Input(Bool()) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ictag_debug_rd_data = Output(UInt(26.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_rd_hit = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_perr = Output(Bool()) + }) + io.ictag_debug_rd_data := 0.U + io.ic_rd_hit := 0.U + io.ic_tag_perr := 0.U + val ic_debug_wr_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ic_debug_rd_way_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + + val ic_tag_wren = io.ic_wr_en & Fill(ICACHE_NUM_WAYS, io.ic_rw_addr(ICACHE_BEAT_ADDR_HI-3,1)=== Fill(ICACHE_NUM_WAYS-1, 1.U)) + val ic_tag_clken = Fill(ICACHE_NUM_WAYS, io.ic_rd_en|io.clk_override) | io.ic_wr_en | ic_debug_wr_way_en | ic_debug_rd_way_en + + val ic_rd_en_ff = RegNext(io.ic_rd_en, 0.U) + val ic_rw_addr_ff = RegNext(io.ic_rw_addr(31-ICACHE_TAG_LO, 0), 0.U) + + val PAD_BITS = 21 - (32 - ICACHE_TAG_LO) + + ic_debug_rd_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & io.ic_debug_tag_array) & io.ic_debug_way + ic_debug_wr_way_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way + + val ic_tag_wren_q = ic_tag_wren | ic_debug_wr_way_en + + val ic_tag_ecc = if(ICACHE_ECC) rvecc_encode(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U + + val ic_tag_parity = if(ICACHE_ECC) rveven_paritygen(Cat(Fill(ICACHE_TAG_LO,0.U),io.ic_rw_addr(31-3, ICACHE_TAG_LO-3))) else 0.U + + val ic_tag_wr_data = if(ICACHE_TAG_LO==1)Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), + Cat(if(ICACHE_ECC) ic_tag_ecc(4,0) else ic_tag_parity, io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) + else Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, Cat(if(ICACHE_ECC) io.ic_debug_wr_data(68,64) else io.ic_debug_wr_data(64), io.ic_debug_wr_data(31,11)), + Cat(if(ICACHE_ECC) Cat(ic_tag_ecc(4,0),Fill(PAD_BITS,0.U)) else Cat(ic_tag_parity,Fill(PAD_BITS,0.U)), io.ic_rw_addr(31-3,ICACHE_TAG_LO-3))) + + val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool,io.ic_debug_addr(ICACHE_INDEX_HI-3,ICACHE_TAG_INDEX_LO-3),io.ic_rw_addr) + + val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) + + val tag_mem = Mem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(Tag_Word.W))) + + val write_vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wren_q(i)&ic_tag_clken(i)) + tag_mem.write(ic_rw_addr_q, VecInit.tabulate(ICACHE_NUM_WAYS)(i=>ic_tag_wr_data), write_vec) + + val read_enable = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(!ic_tag_wren_q(i))&ic_tag_clken(i)) + + val ic_tag_data_raw = (0 until ICACHE_NUM_WAYS).map(i=>Fill(Tag_Word,read_enable(i))&tag_mem.read(ic_rw_addr_q)(i)) + + val w_tout = if(ICACHE_ECC) VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(25,21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) + else VecInit.tabulate(ICACHE_NUM_WAYS)(i=>Cat(ic_tag_data_raw(i)(21), ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0))) + + val ic_tag_corrected_ecc_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(7.W))) + val ic_tag_corrected_data_unc = Wire(Vec(ICACHE_NUM_WAYS, UInt(32.W))) + val ic_tag_single_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) + val ic_tag_double_ecc_error = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) + for(i<- 0 until ICACHE_NUM_WAYS){ + val decoded_ecc = if(ICACHE_ECC) rvecc_decode(~io.dec_tlu_core_ecc_disable & ic_rd_en_ff, Cat(0.U(11.W),ic_tag_data_raw(i)(20,0)), Cat(0.U(2.W),ic_tag_data_raw(i)(25,21)), 1.U) + else (0.U, 0.U, 0.U, 0.U) + ic_tag_corrected_ecc_unc(i) := decoded_ecc._1 + ic_tag_corrected_data_unc(i) := decoded_ecc._2 + ic_tag_single_ecc_error(i):= decoded_ecc._3 + ic_tag_double_ecc_error(i) := decoded_ecc._4 + } + + val ic_tag_way_perr = if(ICACHE_ECC)ic_tag_single_ecc_error.reverse.reduce(Cat(_,_)) | ic_tag_double_ecc_error.reverse.reduce(Cat(_,_)) + else (0 until ICACHE_NUM_WAYS).map(i=>rveven_paritycheck(ic_tag_data_raw(i)(31-ICACHE_TAG_LO,0), ic_tag_data_raw(i)(21))).reverse.reduce(Cat(_,_)) + + io.ictag_debug_rd_data := (0 until ICACHE_NUM_WAYS).map(i=> if(ICACHE_ECC) Fill(26, ic_debug_rd_way_en_ff(i))&ic_tag_data_raw(i) else Cat(0.U(4.W), Fill(22, ic_debug_rd_way_en_ff(i)),ic_tag_data_raw(i)(21,0))).reduce(_|_) + io.ic_rd_hit := (0 until ICACHE_NUM_WAYS).map(i=>((w_tout(i)(31-ICACHE_TAG_LO,0)===ic_rw_addr_ff)&io.ic_tag_valid(i)).asUInt()).reverse.reduce(Cat(_,_)) + io.ic_tag_perr := (ic_tag_way_perr & io.ic_tag_valid).orR() +} + + +//////////////////////////////////////////////// + +class EL2_IC_DATA extends Module with el2_lib { + val io = IO (new Bundle{ + val clk_override = Input(Bool()) + val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W)) + val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Input(Bool()) + val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W))) + val ic_rd_data = Output(UInt(64.W)) + val ic_debug_wr_data = Input(UInt(71.W)) + val ic_debug_rd_data = Output(UInt(71.W)) + val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W)) + val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI-3).W)) + val ic_debug_rd_en = Input(Bool()) + val ic_debug_wr_en = Input(Bool()) + val ic_debug_tag_array = Input(Bool()) + val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_premux_data = Input(UInt(64.W)) + val ic_sel_premux_data = Input(Bool()) + val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) + val scan_mode = Input(UInt(1.W)) + }) + + val ic_debug_rd_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_rd_en & !io.ic_debug_tag_array) & io.ic_debug_way + val ic_debug_wr_way_en = Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & !io.ic_debug_tag_array) & io.ic_debug_way + + val ic_bank_wr_data = Wire(Vec(ICACHE_BANKS_WAY,UInt(71.W))) + val ic_rd_en_with_debug = WireInit(Bool(), 0.U) + + val ic_rw_addr_q = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr,0.U(2.W)), io.ic_rw_addr) + + val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-2,ICACHE_DATA_INDEX_LO-1) + 1.U + val ic_b_sb_wren = (0 until ICACHE_NUM_WAYS).map(i=> + io.ic_wr_en | ic_debug_wr_way_en & Fill(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U)) + val ic_debug_sel_sb = (0 until ICACHE_NUM_WAYS).map(i=> (io.ic_debug_addr(ICACHE_BANK_HI-3,ICACHE_BANK_LO-3)===i.U).asUInt).reverse.reduce(Cat(_,_)) + val ic_sb_wr_data = (0 until ICACHE_NUM_WAYS).map(i=> Mux((ic_debug_sel_sb(i)&io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, ic_bank_wr_data(i))) + val ic_b_rden = (0 until ICACHE_NUM_WAYS).map(i=> + (Mux1H(Seq(!ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 0.U), + (ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U===0.U)), + ic_rw_addr_q(ICACHE_BANK_HI-1).asBool -> (i.U === 1.U), + (!ic_rw_addr_q(ICACHE_BANK_HI-1)).asBool -> ((ic_rw_addr_q(1,0)===3.U)&(i.U === 1.U)))) & ic_rd_en_with_debug).asUInt).reverse.reduce(Cat(_,_)) + val ic_b_sb_rden = (0 until ic_b_rden.getWidth).map(i=>Fill(ICACHE_NUM_WAYS, ic_b_rden(i))) + val ic_bank_way_clken = (0 until ICACHE_BANKS_WAY).map(i=>(0 until ICACHE_NUM_WAYS).map(j=> + (ic_b_sb_rden(i)(j) | io.clk_override | ic_b_sb_wren(i)(j)).asUInt).reduce(Cat(_,_))) + + ic_rd_en_with_debug := io.ic_rd_en | io.ic_debug_rd_en & (!io.ic_wr_en.orR) + + val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI-1) & (ic_rw_addr_q(1,0) === 3.U) & ic_rd_en_with_debug & !(io.ic_wr_en.orR) + + val ic_rw_addr_bank_q = VecInit(Mux((!ic_rw_addr_wrap).asBool,ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1), + Cat(ic_rw_addr_q(ICACHE_INDEX_HI-1, ICACHE_TAG_INDEX_LO-1) , ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-2,ICACHE_DATA_INDEX_LO-1))), + ic_rw_addr_q(ICACHE_INDEX_HI-1,ICACHE_DATA_INDEX_LO-1)) + + val ic_b_rden_ff = RegNext(ic_b_rden, 0.U) + val ic_rw_addr_ff = RegNext(ic_rw_addr_q(ICACHE_TAG_INDEX_LO-2,0), 0.U) + val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, 0.U) + val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, 0.U) + + val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-2,ICACHE_BANK_LO-1) === Fill(ICACHE_TAG_INDEX_LO-ICACHE_BANK_LO, 1.U) + +//////////////////////////////////////////// Memory stated + val (data_mem_word, tag_mem_word, ecc_offset, tag_word) = DATA_MEM_LINE + val wb_dout = Wire(Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) + val data_mem = Mem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W)))) + for(i<-0 until ICACHE_NUM_WAYS; k<-0 until ICACHE_BANKS_WAY){ + wb_dout(i)(k) := 0.U + val WE = if(ICACHE_WAYPACK) ic_b_sb_wren(k).orR else ic_b_sb_wren(k)(i) + val ME = if(ICACHE_WAYPACK) ic_bank_way_clken(k).orR else ic_bank_way_clken(k)(i) + when((ic_b_sb_wren(k)(i) & ic_bank_way_clken(k)(i)).asBool){ + data_mem(ic_rw_addr_bank_q(k))(k)(i) := ic_sb_wr_data(k) + }.elsewhen((!ic_b_sb_wren(k)(i)&ic_bank_way_clken(k)(i)).asBool){ + wb_dout(i)(k) := data_mem(ic_rw_addr_bank_q(k))(k)(i) + } + } + val ic_rd_hit_q = Mux(ic_debug_rd_en_ff.asBool, ic_debug_rd_way_en_ff, io.ic_rd_hit) + ic_bank_wr_data := (0 until ICACHE_BANKS_WAY).map(io.ic_wr_data(_)) + + val wb_dout_way_pre = (0 until ICACHE_BANKS_WAY).map(i=>Cat( + Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===j.U).asBool->wb_dout(i)(j))), + Mux1H((0 until ICACHE_BANKS_WAY).map(j=>(ic_rw_addr_ff(ICACHE_BANK_HI-1, ICACHE_BANK_LO-1)===(j.U-1.U)).asBool->wb_dout(i)(j))))) + + val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>Mux1H(Seq((ic_rw_addr_ff(1,0)===0.U).asBool->wb_dout_way_pre(i)(63,0), + (ic_rw_addr_ff(1,0)===1.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+15,data_mem_word),wb_dout_way_pre(i)(63,16)), + (ic_rw_addr_ff(1,0)===2.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+31,data_mem_word),wb_dout_way_pre(i)(63,32)), + (ic_rw_addr_ff(1,0)===3.U).asBool->Cat(wb_dout_way_pre(i)(data_mem_word+47,data_mem_word),wb_dout_way_pre(i)(63,48))))) + + val wb_dout_way_with_premux = (0 until ICACHE_NUM_WAYS).map(i=>Mux(io.ic_sel_premux_data.asBool,io.ic_premux_data, wb_dout_way(i))) + + io.ic_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>(ic_rd_hit_q(i) | io.ic_sel_premux_data).asBool->wb_dout_way_with_premux(i))) + io.ic_debug_rd_data := Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i)(70,0))) + val wb_dout_ecc = Mux1H((0 until ICACHE_NUM_WAYS).map(i=>ic_rd_hit_q(i).asBool->wb_dout_way_pre(i))) + + val bank_check_en = for(i<-0 until ICACHE_BANKS_WAY) yield io.ic_rd_hit.orR & ((i.U==0.U).asBool | (!ic_cacheline_wrap_ff & (ic_b_rden_ff(ICACHE_BANKS_WAY-1,0) === Fill(ICACHE_BANKS_WAY,1.U)))) + val wb_dout_ecc_bank = (0 until ICACHE_BANKS_WAY).map(i=> wb_dout_ecc((data_mem_word*i)+data_mem_word-1,data_mem_word*i)) + + // TODO: RVECC + io.ic_eccerr := (0 until ICACHE_NUM_WAYS).map(i=>rvecc_decode_64(bank_check_en(i),wb_dout_ecc_bank(i)(63,0),wb_dout_ecc_bank(i)(70,64)).asUInt).reverse.reduce(Cat(_,_)) + val ic_parerr_bank = Wire(Vec(ICACHE_NUM_WAYS, Vec(4, UInt(1.W)))) + for(i<-0 until ICACHE_NUM_WAYS; j<-0 until 4){ic_parerr_bank(i)(j):=rveven_paritycheck(wb_dout_ecc_bank(i)(16*(j+1)-1, 16*j), wb_dout_ecc_bank(i)(64+j))} + + io.ic_parerr := Cat(ic_parerr_bank(0).reduce(_|_) & bank_check_en(0), ic_parerr_bank(1).reduce(_|_) & bank_check_en(1)) +} + +object ifu_ic extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ic_mem())) +} \ No newline at end of file diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala new file mode 100644 index 00000000..14750866 --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -0,0 +1,118 @@ +package ifu +import chisel3._ +import chisel3.util._ +import lib._ +import scala.math.pow + +class el2_ifu_iccm_mem extends Module with el2_lib with RequireAsyncReset { + val io = IO(new Bundle{ + val clk_override = Input(Bool()) + val iccm_wren = Input(Bool()) + val iccm_rden = Input(Bool()) + val iccm_rw_addr = Input(UInt((ICCM_BITS-1).W)) + val iccm_buf_correct_ecc = Input(Bool()) + val iccm_correction_state = Input(Bool()) + val iccm_wr_size = Input(UInt(3.W)) + val iccm_wr_data = Input(UInt(78.W)) + val iccm_rd_data = Output(UInt(64.W)) + val iccm_rd_data_ecc = Output(UInt(78.W)) + val scan_mode = Input(Bool()) + // val iccm_bank_addr = Output(Vec(ICCM_NUM_BANKS, UInt())) + }) + io.iccm_rd_data := 0.U + io.iccm_rd_data_ecc := 0.U + val addr_inc = Mux((io.iccm_wr_size(1,0)===3.U).asBool, 2.U(2.W), 1.U(2.W)) + val addr_bank_inc = io.iccm_rw_addr(ICCM_BITS-2,0) + addr_inc + + val iccm_bank_wr_data_vec = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) + for(i<- 0 until ICCM_NUM_BANKS/2){ + iccm_bank_wr_data_vec(2*i) := io.iccm_wr_data(38,0) + iccm_bank_wr_data_vec((2*i)+1) := io.iccm_wr_data(77,39) + } + + val wren_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_wren&((io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U))) + val iccm_bank_wr_data = iccm_bank_wr_data_vec + val rden_bank = (0 until ICCM_NUM_BANKS).map(i=> io.iccm_rden&(io.iccm_rw_addr(ICCM_BANK_HI-1,1)===i.U)|(addr_bank_inc(ICCM_BANK_HI-1,1)===i.U)) + val iccm_clken = for(i<- 0 until ICCM_NUM_BANKS) yield wren_bank(i) | rden_bank(i) | io.clk_override + + val addr_bank = Wire(Vec(ICCM_NUM_BANKS, UInt((ICCM_BITS-ICCM_BANK_INDEX_LO).W))) + for(i<-0 until ICCM_NUM_BANKS) {addr_bank(i) := Mux(wren_bank(i).asBool, io.iccm_rw_addr(ICCM_BITS-2, ICCM_BANK_INDEX_LO-1), + Mux((addr_bank_inc(ICCM_BANK_HI-1,1)===i.U),addr_bank_inc(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1),io.iccm_rw_addr(ICCM_BITS-2,ICCM_BANK_INDEX_LO-1)))} + + val iccm_mem = new Array[SyncReadMem[UInt]](ICCM_NUM_BANKS) + for(i<-0 until ICCM_NUM_BANKS) iccm_mem(i) = SyncReadMem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W)) + //val iccm_mem = VecInit.tabulate(ICCM_NUM_BANKS)(i=>Mem(pow(2, ICCM_INDEX_BITS).intValue, UInt(39.W)))) + //val iccm_mem = Mem(pow(2, ICCM_INDEX_BITS).intValue, Vec(ICCM_NUM_BANKS, UInt(39.W))) + + val write_vec = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&wren_bank(i)) + val read_enable = VecInit.tabulate(ICCM_NUM_BANKS)(i=>iccm_clken(i)&(!wren_bank(i))) + + val iccm_bank_dout = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) + //val inter = Wire(Vec(ICCM_NUM_BANKS, UInt(39.W))) + + + for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)} + + for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegEnable(iccm_mem(i)(addr_bank(i)),0.U,read_enable(i))} + + + + + val redundant_valid = WireInit(UInt(2.W), init = 0.U) + val redundant_address = Wire(Vec(2, UInt((ICCM_BITS-2).W))) + redundant_address := (0 until 2).map(i=>0.U) + + val sel_red1 = (0 until ICCM_NUM_BANKS).map(i=> (redundant_valid(1) & ((io.iccm_rw_addr(ICCM_BITS-2,1)===redundant_address(1)(ICCM_BITS-3,0)) & (io.iccm_rw_addr(2,1) === i.U)) | + ((addr_bank_inc(ICCM_BITS-2,1)===redundant_address(1)(ICCM_BITS-3,0)) & (addr_bank_inc(2,1) === i.U))).asUInt).reverse.reduce(Cat(_,_)) + val sel_red0 = (0 until ICCM_NUM_BANKS).map(i=> (redundant_valid(0) & ((io.iccm_rw_addr(ICCM_BITS-2,1)===redundant_address(0)(ICCM_BITS-3,0)) & (io.iccm_rw_addr(2,1) === i.U)) | + ((addr_bank_inc(ICCM_BITS-2,1)===redundant_address(0)(ICCM_BITS-3,0)) & (addr_bank_inc(2,1) === i.U))).asUInt).reverse.reduce(Cat(_,_)) + + val sel_red0_q = RegNext(sel_red0, init = 0.U) + val sel_red1_q = RegNext(sel_red1, init = 0.U) + val redundant_data = Wire(Vec(2, UInt(39.W))) + redundant_data := (0 until 2).map(i=>0.U) + val iccm_bank_dout_fn = (0 until ICCM_NUM_BANKS).map(i=> + Mux1H(Seq(sel_red1_q(i).asBool->redundant_data(1), + sel_red0_q(i).asBool->redundant_data(0), + (~sel_red0_q(i) & ~sel_red1_q(i)).asBool -> iccm_bank_dout(i)))) + val redundant_lru = WireInit(Bool(), init = 0.U) + val r0_addr_en = !redundant_lru & io.iccm_buf_correct_ecc + val r1_addr_en = redundant_lru & io.iccm_buf_correct_ecc + val redundant_lru_en = io.iccm_buf_correct_ecc | ((sel_red0.orR | sel_red1.orR) & io.iccm_rden & io.iccm_correction_state) + val redundant_lru_in = Mux(io.iccm_buf_correct_ecc, !redundant_lru, Mux(sel_red0.orR, 1.U, 0.U)) + redundant_lru := RegEnable(redundant_lru_in, 0.U, redundant_lru_en) + redundant_address(0) := RegEnable(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U, r0_addr_en) + redundant_address(1) := RegEnable(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U, r1_addr_en.asBool) + redundant_valid := Cat(RegEnable(1.U, 0.U, r1_addr_en.asBool),RegEnable(1.U, 0.U, r0_addr_en)) + + val redundant_data0_en = ((io.iccm_rw_addr(ICCM_BITS-2,2) === redundant_address(0)(ICCM_BITS-3,1)) & + ((io.iccm_rw_addr(1) & redundant_address(0)(0))| (io.iccm_wr_size(1,0)===3.U)) & redundant_valid(0) & io.iccm_wren) | + (!redundant_lru & io.iccm_buf_correct_ecc) + val redundant_data0_in = Mux(((io.iccm_rw_addr(1)&redundant_address(0)(0)) |(redundant_address(0)(0) & (io.iccm_wr_size(1,0)===3.U))).asBool, + io.iccm_wr_data(77,39), io.iccm_wr_data(38,0)) + redundant_data(0) := RegEnable(redundant_data0_in, 0.U, redundant_data0_en.asBool) + + val redundant_data1_en = ((io.iccm_rw_addr(ICCM_BITS-2,2) === redundant_address(1)(ICCM_BITS-3,1)) & + ((io.iccm_rw_addr(1) & redundant_address(1)(0))| (io.iccm_wr_size(1,0)===3.U)) & redundant_valid(1) & io.iccm_wren) | + (!redundant_lru & io.iccm_buf_correct_ecc) + val redundant_data1_in = Mux(((io.iccm_rw_addr(1)&redundant_address(1)(0)) |(redundant_address(1)(0) & (io.iccm_wr_size(1,0)===3.U))).asBool, + io.iccm_wr_data(77,39), io.iccm_wr_data(38,0)) + redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool) + + val iccm_rd_addr_lo_q = RegNext(RegEnable(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U, 1.U.asBool), 0.U) + val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U) + //val hig_q_vec = (0 until ICCM_NUM_BANKS) + val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1)(31,0))), + Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(31,0)))) + + io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre) + io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))), + Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i)))) + io.iccm_rd_data_ecc := Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1)(38,0))), + Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i)(38,0)))) +} + + +object ifu_iccm extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_iccm_mem())) +} \ No newline at end of file diff --git a/src/main/scala/ifu/el2_ifu_ifc_ctl.scala b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala new file mode 100644 index 00000000..390ff4e8 --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_ifc_ctl.scala @@ -0,0 +1,149 @@ +package ifu +import lib._ +import chisel3._ +import chisel3.util._ + +class el2_ifu_ifc_ctl extends Module with el2_lib with RequireAsyncReset { + val io = IO(new Bundle{ + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val scan_mode = Input(Bool()) + val ic_hit_f = Input(Bool()) + val ifu_ic_mb_empty = Input(Bool()) + val ifu_fb_consume1 = Input(Bool()) + val ifu_fb_consume2 = Input(Bool()) + val dec_tlu_flush_noredir_wb = Input(Bool()) + val exu_flush_final = Input(Bool()) + val exu_flush_path_final = Input(UInt(31.W)) + val ifu_bp_hit_taken_f = Input(Bool()) + val ifu_bp_btb_target_f = Input(UInt(31.W)) + val ic_dma_active = Input(Bool()) + val ic_write_stall = Input(Bool()) + val dma_iccm_stall_any = Input(Bool()) + val dec_tlu_mrac_ff = Input(UInt(32.W)) + + val ifc_fetch_addr_f = Output(UInt(31.W)) + val ifc_fetch_addr_bf = Output(UInt(31.W)) + + val ifc_fetch_req_f = Output(Bool()) + val ifu_pmu_fetch_stall = Output(Bool()) + val ifc_fetch_uncacheable_bf = Output(Bool()) + val ifc_fetch_req_bf = Output(Bool()) + val ifc_fetch_req_bf_raw = Output(Bool()) + val ifc_iccm_access_bf = Output(Bool()) + val ifc_region_acc_fault_bf = Output(Bool()) + val ifc_dma_access_ok = Output(Bool()) + }) + + val fetch_addr_bf = WireInit(UInt(31.W), init = 0.U) + val fetch_addr_next_0 = WireInit(Bool(), 0.U) + val fetch_addr_next = WireInit(UInt(31.W), init = 0.U) + val fb_write_ns = WireInit(UInt(4.W), init = 0.U) + val fb_write_f = WireInit(UInt(4.W), init = 0.U) + val fb_full_f_ns = WireInit(Bool(), init = 0.U) + val fb_right = WireInit(Bool(), init = 0.U) + val fb_right2 = WireInit(Bool(), init = 0.U) + val fb_left = WireInit(Bool(), init = 0.U) + val wfm = WireInit(Bool(), init = 0.U) + val idle = WireInit(Bool(), init = 0.U) + val miss_f = WireInit(Bool(), init = 0.U) + val miss_a = WireInit(Bool(), init = 0.U) + val flush_fb = WireInit(Bool(), init = 0.U) + val mb_empty_mod = WireInit(Bool(), init = 0.U) + val goto_idle = WireInit(Bool(), init = 0.U) + val leave_idle = WireInit(Bool(), init = 0.U) + val fetch_bf_en = WireInit(Bool(), init = 0.U) + val line_wrap = WireInit(Bool(), init = 0.U) + val state = WireInit(UInt(2.W), init = 0.U) + val dma_iccm_stall_any_f = WireInit(Bool(), init = 0.U) + + val idle_E :: fetch_E :: stall_E :: wfm_E :: Nil = Enum(4) + + val dma_stall = io.ic_dma_active | dma_iccm_stall_any_f + dma_iccm_stall_any_f := withClock(io.free_clk) {RegNext(io.dma_iccm_stall_any, init=0.U)} + + miss_a := withClock(io.free_clk) {RegNext(miss_f, init=0.U)} + + val sel_last_addr_bf = !io.exu_flush_final & (!io.ifc_fetch_req_f | !io.ic_hit_f) + val sel_btb_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & io.ifu_bp_hit_taken_f & io.ic_hit_f + val sel_next_addr_bf = !io.exu_flush_final & io.ifc_fetch_req_f & !io.ifu_bp_hit_taken_f & io.ic_hit_f + + // TODO: Make an assertion for the 1H-Mux under here + io.ifc_fetch_addr_bf := Mux1H(Seq(io.exu_flush_final.asBool -> io.exu_flush_path_final, // Replay PC + sel_last_addr_bf.asBool -> io.ifc_fetch_addr_f, // Hold the current PC + sel_btb_addr_bf.asBool -> io.ifu_bp_btb_target_f, // Take the predicted PC + sel_next_addr_bf.asBool -> fetch_addr_next)) // PC+4 + + val address_upper = io.ifc_fetch_addr_f(30,1)+1.U + fetch_addr_next_0 := !(address_upper(ICACHE_TAG_INDEX_LO-2) ^ io.ifc_fetch_addr_f(ICACHE_TAG_INDEX_LO-1)) & io.ifc_fetch_addr_f(0) + + fetch_addr_next := Cat(address_upper, fetch_addr_next_0) + + io.ifc_fetch_req_bf_raw := ~idle + + io.ifc_fetch_req_bf := io.ifc_fetch_req_bf_raw & !(fb_full_f_ns & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) & + !dma_stall & !io.ic_write_stall & !io.dec_tlu_flush_noredir_wb + + fetch_bf_en := io.exu_flush_final | io.ifc_fetch_req_f + + miss_f := io.ifc_fetch_req_f & !io.ic_hit_f & !io.exu_flush_final + + mb_empty_mod := (io.ifu_ic_mb_empty | io.exu_flush_final) & !dma_stall & !miss_f & !miss_a + + goto_idle := io.exu_flush_final & io.dec_tlu_flush_noredir_wb + + leave_idle := io.exu_flush_final & !io.dec_tlu_flush_noredir_wb & idle + + val next_state_1 = (!state(1) & state(0) & miss_f & !goto_idle) | + (state(1) & !mb_empty_mod & !goto_idle) + + val next_state_0 = (!goto_idle & leave_idle) | (state(0) & !goto_idle) + + state := withClock(io.active_clk) {RegNext(Cat(next_state_1, next_state_0), init = 0.U)} + + flush_fb := io.exu_flush_final + + fb_right := ( io.ifu_fb_consume1 & !io.ifu_fb_consume2 & (!io.ifc_fetch_req_f | miss_f)) | + (io.ifu_fb_consume2 & io.ifc_fetch_req_f) + + fb_right2 := (io.ifu_fb_consume2 & (~io.ifc_fetch_req_f | miss_f)) + fb_left := io.ifc_fetch_req_f & !(io.ifu_fb_consume1 | io.ifu_fb_consume2) & !miss_f + + fb_write_ns := Mux1H(Seq(flush_fb.asBool -> 1.U(4.W), + (!flush_fb & fb_right).asBool -> Cat(0.U(1.W), fb_write_f(3,1)), + (!flush_fb & fb_right2).asBool -> Cat(0.U(2.W), fb_write_f(3,2)), + (!flush_fb & fb_left).asBool -> Cat(fb_write_f(2,0), 0.U(1.W)), + (!flush_fb & !fb_right & !fb_right2 & !fb_left).asBool -> fb_write_f(3,0) + )) + + idle := state === 0.U(2.W) + wfm := state === 3.U(2.W) + + fb_full_f_ns := fb_write_ns(3) + val fb_full_f = withClock(io.active_clk) {RegNext(fb_full_f_ns, init = 0.U)} + fb_write_f := withClock(io.active_clk) {RegNext(fb_write_ns, 0.U)} + + io.ifu_pmu_fetch_stall := wfm | (io.ifc_fetch_req_bf_raw & + ((fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1 | io.exu_flush_final)) | dma_stall)) + + val (iccm_acc_in_region_bf, iccm_acc_in_range_bf) = if(ICCM_ENABLE) + rvrangecheck(ICCM_SADR, ICCM_SIZE, Cat(io.ifc_fetch_addr_bf,0.U)) + else (0.U, 0.U) + io.ifc_iccm_access_bf := iccm_acc_in_range_bf + io.ifc_dma_access_ok := ( (!io.ifc_iccm_access_bf | + (fb_full_f & !(io.ifu_fb_consume2 | io.ifu_fb_consume1)) | + (wfm & !io.ifc_fetch_req_bf) | idle ) & !io.exu_flush_final) | dma_iccm_stall_any_f + + io.ifc_region_acc_fault_bf := !iccm_acc_in_range_bf & iccm_acc_in_region_bf + io.ifc_fetch_uncacheable_bf := ~io.dec_tlu_mrac_ff(Cat(io.ifc_fetch_addr_bf(30,27), 0.U)) + + io.ifc_fetch_req_f := withClock(io.active_clk){RegNext(io.ifc_fetch_req_bf, init=0.U)} + + io.ifc_fetch_addr_f := rvdffe(io.ifc_fetch_addr_bf, io.exu_flush_final|io.ifc_fetch_req_f, clock, io.scan_mode) + //rvdffe(io.ifc_fetch_addr_bf,(io.exu_flush_final|io.ifc_fetch_req_f).asBool,clock,io.scan_mode) +} + +object ifu_ifc extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_ifc_ctl())) +} + diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala new file mode 100644 index 00000000..f1c664e1 --- /dev/null +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -0,0 +1,858 @@ +package ifu +import chisel3._ +import chisel3.internal.naming.chiselName +import chisel3.util._ +import lib._ +import include._ + +import scala.math.pow +@chiselName +class mem_ctl_bundle extends Bundle with el2_lib{ + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val exu_flush_final = Input(Bool()) + val dec_tlu_flush_lower_wb = Input(Bool()) + val dec_tlu_flush_err_wb = Input(Bool()) + val dec_tlu_i0_commit_cmt = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) + val ifc_fetch_addr_bf = Input(UInt(31.W)) + val ifc_fetch_uncacheable_bf = Input(Bool()) + val ifc_fetch_req_bf = Input(Bool()) + val ifc_fetch_req_bf_raw = Input(Bool()) + val ifc_iccm_access_bf = Input(Bool()) + val ifc_region_acc_fault_bf = Input(Bool()) + val ifc_dma_access_ok = Input(Bool()) + val dec_tlu_fence_i_wb = Input(Bool()) + val ifu_bp_hit_taken_f = Input(Bool()) + val ifu_bp_inst_mask_f = Input(Bool()) + val ifu_axi_arready = Input(Bool()) + val ifu_axi_rvalid = Input(Bool()) + val ifu_axi_rid = Input(UInt(IFU_BUS_TAG.W)) + val ifu_axi_rdata = Input(UInt(64.W)) + val ifu_axi_rresp = Input(UInt(2.W)) + val ifu_bus_clk_en = Input(Bool()) + val dma_iccm_req = Input(Bool()) + val dma_mem_addr = Input(UInt(32.W)) + val dma_mem_sz = Input(UInt(3.W)) + val dma_mem_write = Input(Bool()) + val dma_mem_wdata = Input(UInt(64.W)) + val dma_mem_tag = Input(UInt(3.W)) + val ic_rd_data = Input(UInt(64.W)) + val ic_debug_rd_data = Input(UInt(71.W)) + val ictag_debug_rd_data = Input(UInt(26.W)) + val ic_eccerr = Input(UInt(ICACHE_BANKS_WAY.W)) + val ic_parerr = Input(UInt(ICACHE_BANKS_WAY.W)) + val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_perr = Input(Bool()) + val iccm_rd_data = Input(UInt(64.W)) + val iccm_rd_data_ecc = Input(UInt(78.W)) + val ifu_fetch_val = Input(UInt(2.W)) + val dec_tlu_ic_diag_pkt = Input(new el2_cache_debug_pkt_t) + + + val ifu_miss_state_idle = Output(Bool()) + val ifu_ic_mb_empty = Output(Bool()) + val ic_dma_active = Output(Bool()) + val ic_write_stall = Output(Bool()) + val ifu_pmu_ic_miss = Output(Bool()) + val ifu_pmu_ic_hit = Output(Bool()) + val ifu_pmu_bus_error = Output(Bool()) + val ifu_pmu_bus_busy = Output(Bool()) + val ifu_pmu_bus_trxn = Output(Bool()) + + + val ifu_axi_awvalid = Output(Bool()) + val ifu_axi_awid = Output(UInt(IFU_BUS_TAG.W)) + val ifu_axi_awaddr = Output(UInt(32.W)) + val ifu_axi_awregion = Output(UInt(4.W)) + val ifu_axi_awlen = Output(UInt(8.W)) + val ifu_axi_awsize = Output(UInt(3.W)) + val ifu_axi_awburst = Output(UInt(2.W)) + val ifu_axi_awlock = Output(Bool()) + val ifu_axi_awcache = Output(UInt(4.W)) + val ifu_axi_awprot = Output(UInt(3.W)) + val ifu_axi_awqos = Output(UInt(4.W)) + val ifu_axi_wvalid = Output(Bool()) + val ifu_axi_wdata = Output(UInt(64.W)) + val ifu_axi_wstrb = Output(UInt(8.W)) + val ifu_axi_wlast = Output(Bool()) + val ifu_axi_bready = Output(Bool()) + val ifu_axi_arvalid = Output(Bool()) + val ifu_axi_arid = Output(UInt(IFU_BUS_TAG.W)) + val ifu_axi_araddr = Output(UInt(32.W)) + val ifu_axi_arregion = Output(UInt(4.W)) + val ifu_axi_arlen = Output(UInt(8.W)) + val ifu_axi_arsize = Output(UInt(3.W)) + val ifu_axi_arburst = Output(UInt(2.W)) + val ifu_axi_arlock = Output(Bool()) + val ifu_axi_arcache = Output(UInt(4.W)) + val ifu_axi_arprot = Output(UInt(3.W)) + val ifu_axi_arqos = Output(UInt(4.W)) + val ifu_axi_rready = Output(Bool()) + val iccm_dma_ecc_error = Output(Bool()) + val iccm_dma_rvalid = Output(Bool()) + val iccm_dma_rdata = Output(UInt(64.W)) + val iccm_dma_rtag = Output(UInt(3.W)) + val iccm_ready = Output(Bool()) + val ic_rw_addr = Output(UInt(31.W)) + val ic_wr_en = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_rd_en = Output(Bool()) + val ic_wr_data = Output(Vec(ICACHE_BANKS_WAY, UInt(71.W))) + val ic_debug_wr_data = Output(UInt(71.W)) + val ifu_ic_debug_rd_data = Output(UInt(71.W)) + val ic_debug_addr = Output(UInt((ICACHE_INDEX_HI-2).W)) + val ic_debug_rd_en = Output(Bool()) + val ic_debug_wr_en = Output(Bool()) + val ic_debug_tag_array = Output(Bool()) + val ic_debug_way = Output(UInt(ICACHE_NUM_WAYS.W)) + val ic_tag_valid = Output(UInt(ICACHE_NUM_WAYS.W)) + val iccm_rw_addr = Output(UInt((ICCM_BITS-1).W)) + val iccm_wren = Output(Bool()) + val iccm_rden = Output(Bool()) + val iccm_wr_data = Output(UInt(78.W)) + val iccm_wr_size = Output(UInt(3.W)) + val ic_hit_f = Output(Bool()) + val ic_access_fault_f = Output(Bool()) + val ic_access_fault_type_f = Output(UInt(2.W)) + val iccm_rd_ecc_single_err = Output(Bool()) + val iccm_rd_ecc_double_err = Output(Bool()) + val ic_error_start = Output(Bool()) + val ifu_async_error_start = Output(Bool()) + val iccm_dma_sb_error = Output(Bool()) + val ic_fetch_val_f = Output(UInt(2.W)) + val ic_data_f = Output(UInt(32.W)) + val ic_premux_data = Output(UInt(64.W)) + val ic_sel_premux_data = Output(Bool()) + val dec_tlu_core_ecc_disable = Input(Bool()) + val ifu_ic_debug_rd_data_valid = Output(Bool()) + val iccm_buf_correct_ecc = Output(Bool()) + val iccm_correction_state = Output(Bool()) + val scan_mode = Input(Bool()) + +} +class el2_ifu_mem_ctl extends Module with el2_lib { + val io = IO(new mem_ctl_bundle) + io.ifu_axi_wvalid := 0.U + io.ifu_axi_wdata := 0.U + io.ifu_axi_awqos := 0.U + io.ifu_axi_awaddr := 0.U + io.ifu_axi_awprot := 0.U + io.ifu_axi_awlen := 0.U + io.ifu_axi_arlock := 0.U + io.ifu_axi_awregion := 0.U + io.ifu_axi_awid := 0.U + io.ifu_axi_awvalid := 0.U + io.ifu_axi_wstrb := 0.U + io.ifu_axi_awcache := 0.U + io.ifu_axi_arqos := 0.U + io.ifu_axi_awlock := 0.U + io.ifu_axi_bready := 0.U + io.ifu_axi_arlen := 0.U + io.ifu_axi_awsize := 0.U + io.ifu_axi_arprot := 0.U + io.ifu_axi_awburst := 0.U + io.ifu_axi_wlast := 0.U + val idle_C :: crit_byp_ok_C :: hit_u_miss_C :: miss_wait_C :: crit_wrd_rdy_C :: scnd_miss_C :: stream_C :: stall_scnd_miss_C :: Nil = Enum(8) + val err_stop_idle_C :: err_fetch1_C :: err_fetch2_C :: err_stop_fetch_C :: Nil = Enum(4) + val err_idle_C :: ic_wff_C :: ecc_wff_C :: ecc_cor_C :: dma_sb_err_C :: Nil = Enum(5) + + val iccm_single_ecc_error = WireInit(UInt(2.W), 0.U) + val ifc_fetch_req_f = WireInit(Bool(), false.B) + val miss_pending = WireInit(Bool(), false.B) + val scnd_miss_req = WireInit(Bool(), false.B) + val dma_iccm_req_f = WireInit(Bool(), false.B) + val iccm_correct_ecc = WireInit(Bool(), false.B) + val perr_state = WireInit(UInt(3.W), 0.U) + val err_stop_state = WireInit(UInt(2.W), 0.U) + val err_stop_fetch = WireInit(Bool(), false.B) + val miss_state = WireInit(UInt(3.W), 0.U) + val miss_nxtstate = WireInit(UInt(3.W), 0.U) + val miss_state_en = WireInit(Bool(), false.B) + val ifu_bus_rsp_valid = WireInit(Bool(), false.B) + val bus_ifu_bus_clk_en = WireInit(Bool(), false.B) + val ifu_bus_rsp_ready = WireInit(Bool(), false.B) + val uncacheable_miss_ff = WireInit(Bool(), false.B) + val ic_act_miss_f = WireInit(Bool(), false.B) + val ic_byp_hit_f = WireInit(Bool(), false.B) + val bus_new_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) + val bus_ifu_wr_en_ff = WireInit(Bool(), false.B) + val last_beat = WireInit(Bool(), false.B) + val last_data_recieved_ff = WireInit(Bool(), false.B) + //val flush_final_f = WireInit(Bool(), 0.U) + val stream_eol_f = WireInit(Bool(), false.B) + val ic_miss_under_miss_f = WireInit(Bool(), false.B) + val ic_ignore_2nd_miss_f = WireInit(Bool(), false.B) + val ic_debug_rd_en_ff = WireInit(Bool(), false.B) + val debug_data_clk = rvclkhdr(clock, ic_debug_rd_en_ff, io.scan_mode) + val flush_final_f = RegNext(io.exu_flush_final, 0.U) + val fetch_bf_f_c1_clken = io.ifc_fetch_req_bf_raw | ifc_fetch_req_f | miss_pending | io.exu_flush_final | scnd_miss_req + val debug_c1_clken = io.ic_debug_rd_en | io.ic_debug_wr_en + val debug_c1_clk = rvclkhdr(clock, debug_c1_clken, io.scan_mode) + val fetch_bf_f_c1_clk = rvclkhdr(clock, fetch_bf_f_c1_clken, io.scan_mode) + io.iccm_dma_sb_error := iccm_single_ecc_error.orR() & dma_iccm_req_f.asBool() + io.ifu_async_error_start := io.iccm_rd_ecc_single_err | io.ic_error_start + io.ic_dma_active := iccm_correct_ecc | (perr_state === dma_sb_err_C) | (err_stop_state === err_stop_fetch_C) | err_stop_fetch | io.dec_tlu_flush_err_wb + + val scnd_miss_req_in = ifu_bus_rsp_valid & bus_ifu_bus_clk_en & ifu_bus_rsp_ready & (bus_new_data_beat_count.andR) & + !uncacheable_miss_ff & ((miss_state === scnd_miss_C)|(miss_nxtstate === scnd_miss_C)) & !io.exu_flush_final + + val ifu_bp_hit_taken_q_f = io.ifu_bp_hit_taken_f & io.ic_hit_f + ///////////////////////////////// MISS FSM ///////////////////////////////// + switch(miss_state){ + is (idle_C){ + miss_nxtstate := Mux((ic_act_miss_f & !io.exu_flush_final).asBool, crit_byp_ok_C, hit_u_miss_C) + miss_state_en := ic_act_miss_f & !io.dec_tlu_force_halt} + + is (crit_byp_ok_C){ + miss_nxtstate := Mux((io.dec_tlu_force_halt | (ic_byp_hit_f & (last_data_recieved_ff | (bus_ifu_wr_en_ff & last_beat)) & uncacheable_miss_ff)).asBool, idle_C, + Mux((ic_byp_hit_f & !last_data_recieved_ff & uncacheable_miss_ff).asBool, miss_wait_C, + Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & uncacheable_miss_ff).asBool, crit_wrd_rdy_C, + Mux(((bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, + Mux((ic_byp_hit_f & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, + Mux((bus_ifu_wr_en_ff & !io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !ifu_bp_hit_taken_q_f & !uncacheable_miss_ff).asBool, stream_C, + Mux((!ic_byp_hit_f & !io.exu_flush_final & (bus_ifu_wr_en_ff & last_beat) & !uncacheable_miss_ff).asBool, idle_C, + Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f) & !(bus_ifu_wr_en_ff & last_beat)).asBool, hit_u_miss_C, idle_C)))))))) + miss_state_en := io.dec_tlu_force_halt | io.exu_flush_final | ic_byp_hit_f | ifu_bp_hit_taken_q_f | (bus_ifu_wr_en_ff & last_beat) | (bus_ifu_wr_en_ff & !uncacheable_miss_ff) + } + is (crit_wrd_rdy_C){ + miss_nxtstate := idle_C + miss_state_en := io.exu_flush_final | flush_final_f | ic_byp_hit_f | io.dec_tlu_force_halt + } + is (stream_C){ + miss_nxtstate := Mux(((io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f)&(!(bus_ifu_wr_en_ff & last_beat)) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) + miss_state_en := io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt + } + is (miss_wait_C){ + miss_nxtstate := Mux((io.exu_flush_final & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, hit_u_miss_C, idle_C) + miss_state_en := io.exu_flush_final | (bus_ifu_wr_en_ff & last_beat) | io.dec_tlu_force_halt + } + is (hit_u_miss_C){ + miss_nxtstate := Mux((ic_miss_under_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, scnd_miss_C, + Mux((ic_ignore_2nd_miss_f & !(bus_ifu_wr_en_ff & last_beat) & !io.dec_tlu_force_halt).asBool, stall_scnd_miss_C, idle_C)) + miss_state_en := (bus_ifu_wr_en_ff & last_beat) | ic_miss_under_miss_f | ic_ignore_2nd_miss_f | io.dec_tlu_force_halt + } + is (scnd_miss_C){ + miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, + Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), crit_byp_ok_C)) + miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt + } + is (stall_scnd_miss_C){ + miss_nxtstate := Mux(io.dec_tlu_force_halt, idle_C, Mux(io.exu_flush_final, + Mux((bus_ifu_wr_en_ff & last_beat).asBool, idle_C, hit_u_miss_C), idle_C)) + miss_state_en := (bus_ifu_wr_en_ff & last_beat) | io.exu_flush_final | io.dec_tlu_force_halt + } + } + miss_state := RegEnable(miss_nxtstate, 0.U, miss_state_en.asBool) + val crit_byp_hit_f = WireInit(Bool(), 0.U) + val way_status_mb_scnd_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val tagv_mb_scnd_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val uncacheable_miss_scnd_ff = WireInit(Bool(), 0.U) + val imb_scnd_ff = WireInit(UInt(31.W), 0.U) + val reset_all_tags = WireInit(Bool(), 0.U) + val bus_rd_addr_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) + val ifu_bus_rid_ff = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) + miss_pending := miss_state =/= idle_C + val crit_wd_byp_ok_ff = (miss_state === crit_byp_ok_C) | ((miss_state === crit_wrd_rdy_C) & !flush_final_f) + val sel_hold_imb = (miss_pending & !(bus_ifu_wr_en_ff & last_beat) & !((miss_state === crit_wrd_rdy_C) & io.exu_flush_final) & + !((miss_state === crit_wrd_rdy_C) & crit_byp_hit_f) ) | ic_act_miss_f | + (miss_pending & (miss_nxtstate === crit_wrd_rdy_C)) + + val sel_hold_imb_scnd = ((miss_state === scnd_miss_C) | ic_miss_under_miss_f) & !flush_final_f + val way_status_mb_scnd_in = Mux(miss_state === scnd_miss_C, way_status_mb_scnd_ff, way_status) + + val tagv_mb_scnd_in = Mux(miss_state === scnd_miss_C, tagv_mb_scnd_ff, Fill(ICACHE_NUM_WAYS, !reset_all_tags) & io.ic_tag_valid) + val uncacheable_miss_scnd_in = Mux(sel_hold_imb_scnd.asBool, uncacheable_miss_scnd_ff, io.ifc_fetch_uncacheable_bf) + uncacheable_miss_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_scnd_in, 0.U)} + val imb_scnd_in = Mux(sel_hold_imb_scnd.asBool, imb_scnd_ff, io.ifc_fetch_addr_bf) + imb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_scnd_in, 0.U)} + way_status_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_scnd_in, 0.U)} + tagv_mb_scnd_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_scnd_in, 0.U)} + + val ic_req_addr_bits_hi_3 = bus_rd_addr_count + val ic_wr_addr_bits_hi_3 = ifu_bus_rid_ff & Fill(ICACHE_BEAT_BITS, bus_ifu_wr_en_ff) + val ifc_iccm_access_f = WireInit(Bool(), 0.U) + val ifc_region_acc_fault_final_f = WireInit(Bool(), 0.U) + val fetch_req_icache_f = ifc_fetch_req_f & !ifc_iccm_access_f & !ifc_region_acc_fault_final_f + val fetch_req_iccm_f = ifc_fetch_req_f & ifc_iccm_access_f + val ic_iccm_hit_f = fetch_req_iccm_f & (!miss_pending | (miss_state === hit_u_miss_C) | (miss_state === stream_C)) + val stream_hit_f = WireInit(Bool(), 0.U) + ic_byp_hit_f := (crit_byp_hit_f | stream_hit_f) & fetch_req_icache_f & miss_pending + val sel_mb_addr_ff = WireInit(Bool(), 0.U) + val imb_ff = WireInit(UInt(31.W), 0.U) + val ifu_fetch_addr_int_f = WireInit(UInt(31.W), 0.U) + val ic_act_hit_f = io.ic_rd_hit.orR & fetch_req_icache_f & !reset_all_tags & (!miss_pending | (miss_state===hit_u_miss_C)) & !sel_mb_addr_ff + ic_act_miss_f := (((!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & !miss_pending) | scnd_miss_req) & !ifc_region_acc_fault_final_f + ic_miss_under_miss_f := (!io.ic_rd_hit | reset_all_tags) & fetch_req_icache_f & (miss_state===hit_u_miss_C) & + (imb_ff(30,ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) & !uncacheable_miss_ff & !sel_mb_addr_ff & !ifc_region_acc_fault_final_f + ic_ignore_2nd_miss_f := (!io.ic_rd_hit.orR | reset_all_tags) & fetch_req_icache_f & (miss_state === hit_u_miss_C) & + ((imb_ff(30,ICACHE_TAG_INDEX_LO-1)===ifu_fetch_addr_int_f(30,ICACHE_TAG_INDEX_LO-1)) | uncacheable_miss_ff) + // Output + io.ic_hit_f := ic_act_hit_f | ic_byp_hit_f | ic_iccm_hit_f | (ifc_region_acc_fault_final_f & ifc_fetch_req_f) + val uncacheable_miss_in = Mux(scnd_miss_req.asBool, uncacheable_miss_scnd_ff, Mux(sel_hold_imb.asBool, uncacheable_miss_ff, io.ifc_fetch_uncacheable_bf)) + val imb_in = Mux(scnd_miss_req.asBool, imb_scnd_ff, Mux(sel_hold_imb.asBool, imb_ff, io.ifc_fetch_addr_bf)) + val ifu_wr_cumulative_err_data = WireInit(Bool(), 0.U) + val scnd_miss_index_match = (imb_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1)===imb_scnd_ff(ICACHE_INDEX_HI-1,ICACHE_TAG_INDEX_LO-1))& scnd_miss_req & !ifu_wr_cumulative_err_data + val way_status_mb_ff = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status_rep_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status_mb_in = Mux((scnd_miss_req & !scnd_miss_index_match).asBool, way_status_mb_scnd_ff, + Mux((scnd_miss_req & scnd_miss_index_match).asBool, way_status_rep_new, + Mux(miss_pending.asBool, way_status_mb_ff, way_status))) + val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, UInt(1.W))) + val tagv_mb_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val tagv_mb_in = Mux(scnd_miss_req.asBool, tagv_mb_scnd_ff | (Fill(ICACHE_NUM_WAYS, scnd_miss_index_match) & replace_way_mb_any.reverse.reduce(Cat(_,_))), + Mux(miss_pending.asBool, tagv_mb_ff, io.ic_tag_valid & Fill(ICACHE_NUM_WAYS, !reset_all_tags))) + val scnd_miss_req_q = WireInit(Bool(), false.B) + val reset_ic_ff = WireInit(Bool(), false.B) + val reset_ic_in = miss_pending & !scnd_miss_req_q & (reset_all_tags | reset_ic_ff) + reset_ic_ff := RegNext(reset_ic_in) + val fetch_uncacheable_ff = RegNext(io.ifc_fetch_uncacheable_bf, 0.U) + ifu_fetch_addr_int_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_fetch_addr_bf, 0.U)} + val vaddr_f = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1, 0) + uncacheable_miss_ff := withClock(fetch_bf_f_c1_clk){RegNext(uncacheable_miss_in, 0.U)} + imb_ff := withClock(fetch_bf_f_c1_clk){RegNext(imb_in)} + val miss_addr = WireInit(UInt((31-ICACHE_BEAT_ADDR_HI).W), 0.U) + val miss_addr_in = Mux(!miss_pending, imb_ff(30, ICACHE_BEAT_ADDR_HI), + Mux(scnd_miss_req_q.asBool, imb_scnd_ff(30, ICACHE_BEAT_ADDR_HI), miss_addr)) + val busclk_reset = rvclkhdr(clock, bus_ifu_bus_clk_en | ic_act_miss_f | io.dec_tlu_force_halt, io.scan_mode) + miss_addr := withClock(busclk_reset) {RegNext(miss_addr_in, 0.U)} + way_status_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(way_status_mb_in, 0.U)} + tagv_mb_ff := withClock(fetch_bf_f_c1_clk){RegNext(tagv_mb_in, 0.U)} + val stream_miss_f = WireInit(Bool(), 0.U) + val ifc_fetch_req_qual_bf = io.ifc_fetch_req_bf & !((miss_state===crit_wrd_rdy_C) & flush_final_f) & !stream_miss_f + val ifc_fetch_req_f_raw = RegNext(ifc_fetch_req_qual_bf, 0.U) + ifc_fetch_req_f := ifc_fetch_req_f_raw & !io.exu_flush_final + ifc_iccm_access_f := withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_iccm_access_bf, 0.U)} + val ifc_region_acc_fault_final_bf = WireInit(Bool(), 0.U) + ifc_region_acc_fault_final_f := withClock(fetch_bf_f_c1_clk){RegNext(ifc_region_acc_fault_final_bf, 0.U)} + val ifc_region_acc_fault_f = withClock(fetch_bf_f_c1_clk){RegNext(io.ifc_region_acc_fault_bf, 0.U)} + val ifu_ic_req_addr_f = Cat(miss_addr, ic_req_addr_bits_hi_3) + io.ifu_ic_mb_empty := (((miss_state===hit_u_miss_C) | (miss_state===stream_C)) & !(bus_ifu_wr_en_ff & last_beat)) | !miss_pending + io.ifu_miss_state_idle := miss_state === idle_C + val write_ic_16_bytes = WireInit(Bool(), false.B) + val reset_tag_valid_for_miss = WireInit(Bool(), false.B) + val sel_mb_addr = (miss_pending & write_ic_16_bytes & !uncacheable_miss_ff) | reset_tag_valid_for_miss + val ifu_ic_rw_int_addr = Mux1H(Seq(sel_mb_addr -> Cat(imb_ff(30,ICACHE_BEAT_ADDR_HI) , ic_wr_addr_bits_hi_3 , imb_ff(1,0)), + !sel_mb_addr -> io.ifc_fetch_addr_bf)) + val bus_ifu_wr_en_ff_q = WireInit(Bool(), false.B) + val sel_mb_status_addr = miss_pending & write_ic_16_bytes & !uncacheable_miss_ff & last_beat & bus_ifu_wr_en_ff_q + val ifu_status_wr_addr = Mux(sel_mb_status_addr, Cat(imb_ff(30, ICACHE_BEAT_ADDR_HI),ic_wr_addr_bits_hi_3, imb_ff(1,0)), ifu_fetch_addr_int_f) + io.ic_rw_addr := ifu_ic_rw_int_addr + sel_mb_addr_ff := withClock(io.free_clk){RegNext(sel_mb_addr, 0.U)} + val ifu_bus_rdata_ff = WireInit(UInt(64.W), 0.U) + val ic_miss_buff_half = WireInit(UInt(64.W), 0.U) + val ic_wr_ecc = rvecc_encode_64(ifu_bus_rdata_ff) + val ic_miss_buff_ecc = rvecc_encode_64(ic_miss_buff_half) + val ic_wr_16bytes_data = WireInit(UInt((ICACHE_BANKS_WAY * (if(ICACHE_ECC) 71 else 68)).W), 0.U) + io.ic_wr_data := (0 until ICACHE_BANKS_WAY).map(i=>ic_wr_16bytes_data((i*(if(ICACHE_ECC) 71 else 68))+(if(ICACHE_ECC) 70 else 67),(if(ICACHE_ECC) 71 else 68)*i)) + io.ic_debug_wr_data := io.dec_tlu_ic_diag_pkt.icache_wrdata + val ic_rd_parity_final_err = WireInit(Bool(), 0.U) + io.ic_error_start := ((if(ICACHE_ECC)io.ic_eccerr.orR()else io.ic_parerr.orR()) & ic_act_hit_f) | ic_rd_parity_final_err + val ic_debug_tag_val_rd_out = WireInit(Bool(), 0.U) + val ic_debug_ict_array_sel_ff = WireInit(Bool(), 0.U) + val ifu_ic_debug_rd_data_in = Mux(ic_debug_ict_array_sel_ff.asBool, if(ICACHE_ECC) Cat(0.U(2.W),io.ictag_debug_rd_data(25,21),0.U(32.W),io.ictag_debug_rd_data(20,0), 0.U(7-ICACHE_STATUS_BITS), way_status, 0.U(3.W),ic_debug_tag_val_rd_out) + else Cat(0.U(6.W),io.ictag_debug_rd_data(21),0.U(32.W),io.ictag_debug_rd_data(20,0),0.U(7-ICACHE_STATUS_BITS),way_status ,0.U(3.W) ,ic_debug_tag_val_rd_out) , + io.ic_debug_rd_data) + io.ifu_ic_debug_rd_data := withClock(debug_data_clk){RegNext(ifu_ic_debug_rd_data_in, 0.U)} + val ic_wr_parity = (0 until 4).map(i=>rveven_paritygen(ifu_bus_rdata_ff((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) + val ic_miss_buff_parity = (0 until 4).map(i=>rveven_paritygen(ic_miss_buff_half((16*i)+15,16*i))).reverse.reduce(Cat(_,_)) + + ic_wr_16bytes_data := Mux(ifu_bus_rid_ff(0).asBool,Cat(if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff, if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half), + Cat(if(ICACHE_ECC)ic_miss_buff_ecc else ic_miss_buff_parity, ic_miss_buff_half, if(ICACHE_ECC)ic_wr_ecc else ic_wr_parity, ifu_bus_rdata_ff)) + + val bus_ifu_wr_data_error_ff = WireInit(Bool(), 0.U) + val ifu_wr_data_comb_err_ff = WireInit(Bool(), 0.U) + val reset_beat_cnt = WireInit(Bool(), 0.U) + val ifu_wr_data_comb_err = bus_ifu_wr_data_error_ff + val ifu_wr_cumulative_err = (ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff) & !reset_beat_cnt + ifu_wr_cumulative_err_data := ifu_wr_data_comb_err | ifu_wr_data_comb_err_ff + ifu_wr_data_comb_err_ff := withClock(io.free_clk) {RegNext(ifu_wr_cumulative_err, 0.U)} + val ic_crit_wd_rdy = WireInit(Bool(), 0.U) + val ifu_byp_data_err_new = WireInit(Bool(), 0.U) + val sel_byp_data = (ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !ifu_byp_data_err_new + val sel_ic_data = !(ic_crit_wd_rdy | (miss_state===stream_C) | (miss_state===crit_byp_ok_C)) & !fetch_req_iccm_f + val sel_iccm_data = fetch_req_iccm_f + + val ic_byp_data_only_new = WireInit(UInt(80.W), 0.U) + val ic_final_data = Mux1H(Seq((sel_byp_data | (if(ICCM_ICACHE) (sel_iccm_data | sel_ic_data) else if(ICACHE_ONLY) sel_ic_data else 0.U)).asBool-> + (if(ICCM_ICACHE) io.ic_rd_data else ic_byp_data_only_new(63,0)))) + val ic_premux_data_temp = if(ICCM_ICACHE) (Fill(64,sel_iccm_data) & io.iccm_rd_data) | (Fill(64, sel_byp_data) & ic_byp_data_only_new) + else if(ICACHE_ONLY) Fill(64, sel_byp_data) & ic_byp_data_only_new else 0.U + val ic_sel_premux_data_temp = if(ICCM_ICACHE) sel_iccm_data | sel_byp_data else if(ICACHE_ONLY) sel_byp_data else 0.U + io.ic_premux_data := ic_premux_data_temp + io.ic_sel_premux_data := ic_sel_premux_data_temp + val ifc_bus_acc_fault_f = ic_byp_hit_f & ifu_byp_data_err_new + io.ic_data_f := ic_final_data + val fetch_req_f_qual = io.ic_hit_f & !io.exu_flush_final + val ifc_region_acc_fault_memory_f = WireInit(Bool(), 0.U) + io.ic_access_fault_f := (ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) & !io.exu_flush_final + io.ic_access_fault_type_f := Mux(io.iccm_rd_ecc_double_err.asBool, 1.U, + Mux(ifc_region_acc_fault_f.asBool, 2.U, + Mux(ifc_region_acc_fault_memory_f.asBool(), 3.U, 0.U))) + io.ic_fetch_val_f := Cat(fetch_req_f_qual & io.ifu_bp_inst_mask_f & !(vaddr_f===Fill(ICACHE_BEAT_ADDR_HI,1.U)) & (err_stop_state=/=err_fetch2_C), fetch_req_f_qual) + val two_byte_instr = io.ic_data_f(1,0) =/= 3.U + //// Creating full buffer + val ifu_bus_rsp_rdata = WireInit(UInt(64.W), 0.U) + val ic_miss_buff_data_in = ifu_bus_rsp_rdata + val ifu_bus_rsp_tag = WireInit(UInt(IFU_BUS_TAG.W), 0.U) + val bus_ifu_wr_en = WireInit(Bool(), false.B) + val write_fill_data = (0 until ICACHE_NUM_BEATS).map(i=>bus_ifu_wr_en & (ifu_bus_rsp_tag===i.U)) + val ic_miss_buff_data = Wire(Vec(2*ICACHE_NUM_BEATS, UInt(32.W))) + for(i<- 0 until ICACHE_NUM_BEATS){ + val wr_data_c1_clk = write_fill_data.map(rvclkhdr(clock, _ , io.scan_mode)) + ic_miss_buff_data(2*i) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(31,0), 0.U)} + ic_miss_buff_data(2*i+1) := withClock(wr_data_c1_clk(i)){RegNext(ic_miss_buff_data_in(63,32), 0.U)}} + val ic_miss_buff_data_valid = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U) + val ic_miss_buff_data_valid_in = (0 until ICACHE_NUM_BEATS).map(i=>write_fill_data(i)|(ic_miss_buff_data_valid(i)&(!ic_act_miss_f))) + ic_miss_buff_data_valid := withClock(io.free_clk){RegNext(ic_miss_buff_data_valid_in.map(i=>i.asUInt()).reverse.reduce(Cat(_,_)), 0.U)} + val bus_ifu_wr_data_error = WireInit(Bool(), 0.U) + val ic_miss_buff_data_error = WireInit(UInt(ICACHE_NUM_BEATS.W), 0.U) + val ic_miss_buff_data_error_in =(0 until ICACHE_NUM_BEATS).map(i=>Mux(write_fill_data(i).asBool,bus_ifu_wr_data_error, + ic_miss_buff_data_error(i) & !ic_act_miss_f)) + ic_miss_buff_data_error := withClock(io.free_clk){RegNext(ic_miss_buff_data_error_in.reverse.reduce(Cat(_,_)), 0.U)} + + // New Bypass ready + val bypass_index = imb_ff(ICACHE_BEAT_ADDR_HI-1, 0) + val bypass_index_5_3_inc = bypass_index(bypass_index.getWidth-1,2) + 1.U + val bypass_valid_value_check = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(bypass_index.getWidth-1,2)===i.U).asBool->ic_miss_buff_data_valid_in(i))) + val bypass_data_ready_in = (bypass_valid_value_check & !bypass_index(1) & !bypass_index(0)) | + (bypass_valid_value_check & !bypass_index(1) & bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & !bypass_index(0)) | + (bypass_valid_value_check & bypass_index(1) & bypass_index(0) & Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index_5_3_inc===i.U).asBool->ic_miss_buff_data_valid_in(i)))) | + (bypass_valid_value_check & bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===Fill(ICACHE_BEAT_ADDR_HI,1.U)) + + + val ic_crit_wd_rdy_new_ff = WireInit(Bool(), 0.U) + val ic_crit_wd_rdy_new_in = (bypass_data_ready_in & crit_wd_byp_ok_ff & uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | + ( crit_wd_byp_ok_ff & !uncacheable_miss_ff & !io.exu_flush_final & !ifu_bp_hit_taken_q_f) | + (ic_crit_wd_rdy_new_ff & crit_wd_byp_ok_ff & !fetch_req_icache_f & !io.exu_flush_final) + ic_crit_wd_rdy_new_ff := withClock(io.free_clk){RegNext(ic_crit_wd_rdy_new_in, 0.U)} + val byp_fetch_index = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,0) + val byp_fetch_index_0 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 0.U) + val byp_fetch_index_1 = Cat(ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2), 1.U) + val byp_fetch_index_inc = ifu_fetch_addr_int_f(ICACHE_BEAT_ADDR_HI-1,2) + 1.U + val byp_fetch_index_inc_0 = Cat(byp_fetch_index_inc, 0.U) + val byp_fetch_index_inc_1 = Cat(byp_fetch_index_inc, 1.U) + val ic_miss_buff_data_error_bypass = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(bypass_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_error(i))) + val ic_miss_buff_data_error_bypass_inc = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_error(i))) + + + when(ifu_fetch_addr_int_f(1)&ifu_fetch_addr_int_f(0)){ + ifu_byp_data_err_new := ic_miss_buff_data_error_bypass + } otherwise{ifu_byp_data_err_new := ic_miss_buff_data_error_bypass | ic_miss_buff_data_error_bypass_inc} + + val ic_byp_data_only_pre_new = Mux(!ifu_fetch_addr_int_f(1).asBool, + Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_0===i.U).asBool->ic_miss_buff_data(i)(31,0)))), + Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_1===i.U).asBool->ic_miss_buff_data(i)(15,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc_0===i.U).asBool->ic_miss_buff_data(i)(31,0))), Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_1===i.U).asBool->ic_miss_buff_data(i)(31,0))))) + + ic_byp_data_only_new := Mux(!ifu_fetch_addr_int_f(0).asBool(),ic_byp_data_only_pre_new,Cat(0.U(16.W),ic_byp_data_only_pre_new(79,16))) + + val miss_wrap_f = imb_ff(ICACHE_TAG_INDEX_LO-1) =/= ifu_fetch_addr_int_f(ICACHE_TAG_INDEX_LO-1) + val ic_miss_buff_data_valid_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2)===i.U).asBool->ic_miss_buff_data_valid(i))) + val ic_miss_buff_data_valid_inc_bypass_index = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(byp_fetch_index_inc===i.U).asBool->ic_miss_buff_data_valid(i))) + val miss_buff_hit_unq_f = (ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & !byp_fetch_index(0)) | + (ic_miss_buff_data_valid_bypass_index & !byp_fetch_index(1) & byp_fetch_index(0)) | + (ic_miss_buff_data_valid_bypass_index & byp_fetch_index(1) & !byp_fetch_index(0)) | + (ic_miss_buff_data_valid_bypass_index & byp_fetch_index(1) & byp_fetch_index(0) & ic_miss_buff_data_valid_inc_bypass_index) | + (ic_miss_buff_data_valid_bypass_index & (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,2) === Fill(ICACHE_BEAT_BITS,1.U))) + + stream_hit_f := (miss_state===stream_C) & (miss_buff_hit_unq_f & !miss_wrap_f) + stream_miss_f := (miss_state===stream_C) & !(miss_buff_hit_unq_f & !miss_wrap_f) & ifc_fetch_req_f + stream_eol_f := (byp_fetch_index(ICACHE_BEAT_ADDR_HI-1,1)===Fill(ICACHE_BEAT_BITS+1, 1.U)) & ifc_fetch_req_f & stream_hit_f + crit_byp_hit_f := miss_buff_hit_unq_f & ((miss_state===crit_wrd_rdy_C) | (miss_state===crit_byp_ok_C)) + + + val other_tag = Cat(ifu_bus_rid_ff(IFU_BUS_TAG-1,1),!ifu_bus_rid_ff(0)) + val second_half_available = Mux1H((0 until ICACHE_NUM_BEATS).map(i=>(other_tag===i.U).asBool->ic_miss_buff_data_valid(i))) + write_ic_16_bytes := second_half_available & bus_ifu_wr_en_ff + ic_miss_buff_half := Cat(Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,1.U)===i.U).asBool->ic_miss_buff_data(i))), + Mux1H((0 until 2*ICACHE_NUM_BEATS).map(i=>(Cat(other_tag,0.U)===i.U).asBool->ic_miss_buff_data(i)))) + + + + ic_rd_parity_final_err := io.ic_tag_perr & sel_ic_data & !(ifc_region_acc_fault_final_f | ifc_bus_acc_fault_f) + val ifu_ic_rw_int_addr_ff = WireInit(UInt((ICACHE_INDEX_HI-ICACHE_TAG_INDEX_LO+1).W), 0.U) + + val perr_sb_write_status = WireInit(Bool(), false.B) + val perr_ic_index_ff = withClock(io.active_clk){RegEnable(ifu_ic_rw_int_addr_ff, 0.U, perr_sb_write_status)} + val perr_sel_invalidate = WireInit(Bool(), false.B) + val perr_err_inv_way = Fill(ICACHE_NUM_WAYS, perr_sel_invalidate) + iccm_correct_ecc := perr_state === ecc_cor_C + val dma_sb_err_state = perr_state === dma_sb_err_C + val dma_sb_err_state_ff = Wire(Bool()) + io.iccm_buf_correct_ecc := iccm_correct_ecc & !dma_sb_err_state_ff + dma_sb_err_state_ff := withClock(io.active_clk){RegNext(dma_sb_err_state, false.B)} + + ///////////////////////////////// ERROR FSM ///////////////////////////////// + val perr_nxtstate = WireInit(UInt(3.W), 0.U) + val perr_state_en = WireInit(Bool(), false.B) + val iccm_error_start = WireInit(Bool(), false.B) + switch(perr_state){ + is(err_idle_C){ + perr_nxtstate := Mux(io.iccm_dma_sb_error, dma_sb_err_C, Mux((io.ic_error_start & !io.exu_flush_final).asBool, ic_wff_C, ecc_wff_C)) + perr_state_en := (((iccm_error_start | io.ic_error_start) & !io.exu_flush_final) | io.iccm_dma_sb_error) & !io.dec_tlu_force_halt + perr_sb_write_status := perr_state_en + } + is(ic_wff_C){ + perr_nxtstate := err_idle_C + perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt + perr_sel_invalidate := io.dec_tlu_flush_lower_wb & io.dec_tlu_force_halt + } + is(ecc_wff_C){ + perr_nxtstate := Mux(((io.dec_tlu_flush_err_wb & io.dec_tlu_flush_lower_wb ) | io.dec_tlu_force_halt).asBool(), err_idle_C, ecc_cor_C) + perr_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_force_halt + } + is(dma_sb_err_C){ + perr_nxtstate := Mux(io.dec_tlu_force_halt, err_idle_C, ecc_cor_C) + perr_state_en := true.B + } + is(ecc_cor_C){ + perr_nxtstate := err_idle_C + perr_state_en := true.B + } + } + perr_state := withClock(io.free_clk){RegEnable(perr_nxtstate, 0.U, perr_state_en)} + ///////////////////////////////// STOP FETCH FSM ///////////////////////////////// + val err_stop_nxtstate = WireInit(UInt(2.W), 0.U) + val err_stop_state_en = WireInit(Bool(), false.B) + io.iccm_correction_state := false.B +// val err_stop_fetch := WireInit(Bool(), false.B) + switch(err_stop_state){ + is(err_stop_idle_C){ + err_stop_nxtstate := err_fetch1_C + err_stop_state_en := io.dec_tlu_flush_err_wb & (perr_state === ecc_wff_C) & !io.dec_tlu_force_halt + } + is(err_fetch1_C){ + err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool(), err_stop_idle_C, + Mux(((io.ifu_fetch_val===3.U)|(io.ifu_fetch_val(0)&two_byte_instr)).asBool(), err_stop_fetch_C, + Mux(io.ifu_fetch_val(0).asBool(), err_fetch2_C, err_fetch1_C))) + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | ifu_bp_hit_taken_q_f | io.dec_tlu_force_halt + err_stop_fetch := ((io.ifu_fetch_val(1,0)===3.U) | (io.ifu_fetch_val(0) & two_byte_instr)) & !(io.exu_flush_final | io.dec_tlu_i0_commit_cmt) + io.iccm_correction_state := true.B + } + is(err_fetch2_C){ + err_stop_nxtstate := Mux((io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool, + err_stop_idle_C, Mux(io.ifu_fetch_val(0).asBool, err_stop_fetch_C, err_fetch2_C)) + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.ifu_fetch_val(0) | io.dec_tlu_force_halt + err_stop_fetch := io.ifu_fetch_val(0) & !io.exu_flush_final & !io.dec_tlu_i0_commit_cmt + io.iccm_correction_state := true.B + } + is(err_stop_fetch_C){ + err_stop_nxtstate := Mux(((io.dec_tlu_flush_lower_wb & !io.dec_tlu_flush_err_wb) | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt).asBool, + err_stop_idle_C, Mux(io.dec_tlu_flush_err_wb.asBool(), err_fetch1_C, err_stop_fetch_C)) + err_stop_state_en := io.dec_tlu_flush_lower_wb | io.dec_tlu_i0_commit_cmt | io.dec_tlu_force_halt + err_stop_fetch := true.B + io.iccm_correction_state := true.B + } + } + err_stop_state := withClock(io.free_clk){RegEnable(err_stop_nxtstate, 0.U, err_stop_state_en)} + bus_ifu_bus_clk_en := io.ifu_bus_clk_en + val busclk = rvclkhdr(clock, bus_ifu_bus_clk_en, io.scan_mode) + val busclk_force = rvclkhdr(clock, bus_ifu_bus_clk_en | io.dec_tlu_force_halt , io.scan_mode) + val bus_ifu_bus_clk_en_ff = withClock(io.free_clk){RegNext(bus_ifu_bus_clk_en, 0.U)} + scnd_miss_req_q := withClock(io.free_clk){RegNext(scnd_miss_req_in, 0.U)} + val scnd_miss_req_ff2 = withClock(io.free_clk){RegNext(scnd_miss_req, 0.U)} + scnd_miss_req := scnd_miss_req_q & (!io.exu_flush_final) + val bus_cmd_req_hold = WireInit(Bool(), false.B) + val ifu_bus_cmd_valid = WireInit(Bool(), false.B) + val bus_cmd_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) + val ifu_bus_cmd_ready = WireInit(Bool(), false.B) + val ifc_bus_ic_req_ff_in = (ic_act_miss_f | bus_cmd_req_hold | ifu_bus_cmd_valid) & !io.dec_tlu_force_halt & !((bus_cmd_beat_count===Fill(ICACHE_BEAT_BITS,1.U)) & ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending) + ifu_bus_cmd_valid := withClock(busclk_force){RegNext(ifc_bus_ic_req_ff_in, 0.U)} + val bus_cmd_sent = WireInit(Bool(), false.B) + val bus_cmd_req_in = (ic_act_miss_f | bus_cmd_req_hold) & !bus_cmd_sent & !io.dec_tlu_force_halt + bus_cmd_sent := withClock(io.free_clk){RegNext(bus_cmd_req_in, false.B)} + // AXI Read-Channel + io.ifu_axi_arvalid := ifu_bus_cmd_valid + io.ifu_axi_arid := bus_rd_addr_count & Fill(IFU_BUS_TAG, ifu_bus_cmd_valid) + io.ifu_axi_araddr := Cat(ifu_ic_req_addr_f, 0.U(3.W)) & Fill(32, ifu_bus_cmd_valid) + io.ifu_axi_arsize := 3.U(3.W) + io.ifu_axi_arcache := 15.U + io.ifu_axi_arregion := ifu_ic_req_addr_f(28,25) + io.ifu_axi_arburst := 1.U + io.ifu_axi_rready := true.B + + val ifu_bus_arready_unq = io.ifu_axi_arready + val ifu_bus_rvalid_unq = io.ifu_axi_rvalid + val ifu_bus_arvalid = io.ifu_axi_arvalid + bus_ifu_bus_clk_en + val ifu_bus_arready_unq_ff = withClock(busclk){RegNext(ifu_bus_arready_unq, false.B)} + val ifu_bus_rvalid_unq_ff = withClock(busclk){RegNext(ifu_bus_rvalid_unq, false.B)} + val ifu_bus_arvalid_ff = withClock(busclk){RegNext(ifu_bus_arvalid, false.B)} + val ifu_bus_rresp_ff = withClock(busclk){RegNext(io.ifu_axi_rresp, 0.U)} + ifu_bus_rdata_ff := withClock(busclk){RegNext(io.ifu_axi_rdata, 0.U)} + ifu_bus_rid_ff := withClock(busclk){RegNext(io.ifu_axi_rid, 0.U)} + ifu_bus_cmd_ready := io.ifu_axi_arready + ifu_bus_rsp_valid := io.ifu_axi_rvalid + ifu_bus_rsp_ready := io.ifu_axi_rready + ifu_bus_rsp_tag := io.ifu_axi_rid + ifu_bus_rsp_rdata := io.ifu_axi_rdata + val ifu_bus_rsp_opc = io.ifu_axi_rresp + val ifu_bus_rvalid = ifu_bus_rsp_valid & bus_ifu_bus_clk_en + val ifu_bus_arready = ifu_bus_arready_unq & bus_ifu_bus_clk_en + val ifu_bus_arready_ff = ifu_bus_arready_unq_ff & bus_ifu_bus_clk_en_ff + val ifu_bus_rvalid_ff = ifu_bus_rvalid_unq_ff & bus_ifu_bus_clk_en_ff + bus_cmd_sent := ifu_bus_arvalid & ifu_bus_arready & miss_pending & !io.dec_tlu_force_halt + val bus_last_data_beat = WireInit(Bool(), false.B) + val bus_inc_data_beat_cnt = bus_ifu_wr_en_ff & !bus_last_data_beat & !io.dec_tlu_force_halt + val bus_reset_data_beat_cnt = ic_act_miss_f | (bus_ifu_wr_en_ff & bus_last_data_beat) | io.dec_tlu_force_halt + val bus_hold_data_beat_cnt = !bus_inc_data_beat_cnt & !bus_reset_data_beat_cnt + val bus_data_beat_count = WireInit(UInt(ICACHE_BEAT_BITS.W), 0.U) + bus_new_data_beat_count := Mux1H(Seq(bus_reset_data_beat_cnt->0.U, bus_inc_data_beat_cnt-> (bus_data_beat_count + 1.U), bus_hold_data_beat_cnt->bus_data_beat_count)) + bus_data_beat_count := withClock(io.free_clk){RegNext(bus_new_data_beat_count, 0.U)} + val last_data_recieved_in = (bus_ifu_wr_en_ff & bus_last_data_beat & !scnd_miss_req) | (last_data_recieved_ff & !ic_act_miss_f) + last_data_recieved_ff := withClock(io.free_clk){RegNext(last_data_recieved_in, 0.U)} + // Request Address Count + val bus_new_rd_addr_count = Mux(!miss_pending, imb_ff(ICACHE_BEAT_ADDR_HI-1, 2), + Mux(scnd_miss_req_q, imb_scnd_ff(ICACHE_BEAT_ADDR_HI-1, 2), + Mux(bus_cmd_sent, bus_rd_addr_count + 1.U, bus_rd_addr_count))) + bus_rd_addr_count := withClock(busclk_reset){RegNext(bus_new_rd_addr_count, 0.U)} + // Command beat Count + val bus_inc_cmd_beat_cnt = ifu_bus_cmd_valid & ifu_bus_cmd_ready & miss_pending & !io.dec_tlu_force_halt + val bus_reset_cmd_beat_cnt_0 = (ic_act_miss_f & !uncacheable_miss_in) | io.dec_tlu_force_halt + val bus_reset_cmd_beat_cnt_secondlast = ic_act_miss_f & uncacheable_miss_in + val bus_hold_cmd_beat_cnt = !bus_inc_cmd_beat_cnt & !(ic_act_miss_f | scnd_miss_req | io.dec_tlu_force_halt) + val bus_cmd_beat_en = bus_inc_cmd_beat_cnt | ic_act_miss_f | io.dec_tlu_force_halt + val bus_new_cmd_beat_count = Mux1H(Seq(bus_reset_cmd_beat_cnt_0->0.U, bus_reset_cmd_beat_cnt_secondlast.asBool->ICACHE_SCND_LAST.U, + bus_inc_cmd_beat_cnt->(bus_cmd_beat_count+1.U), bus_hold_cmd_beat_cnt->bus_cmd_beat_count)) + bus_cmd_beat_count := withClock(busclk_reset){RegEnable(bus_new_cmd_beat_count, 0.U, bus_cmd_beat_en)} + bus_last_data_beat := Mux(uncacheable_miss_ff, bus_data_beat_count===1.U, bus_data_beat_count.andR()) + bus_ifu_wr_en := ifu_bus_rvalid & miss_pending + bus_ifu_wr_en_ff := ifu_bus_rvalid_ff & miss_pending + bus_ifu_wr_en_ff_q := ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff & !(ifu_bus_rresp_ff.orR) & write_ic_16_bytes + val bus_ifu_wr_en_ff_wo_err = ifu_bus_rvalid_ff & miss_pending & !uncacheable_miss_ff + val ic_act_miss_f_delayed = withClock(io.free_clk){RegNext(ic_act_miss_f, false.B)} + reset_tag_valid_for_miss := ic_act_miss_f_delayed & (miss_state===crit_byp_ok_C) & !uncacheable_miss_ff + bus_ifu_wr_data_error := ifu_bus_rsp_opc.orR() & ifu_bus_rvalid & miss_pending + bus_ifu_wr_data_error_ff := ifu_bus_rresp_ff.orR & ifu_bus_rvalid_ff & miss_pending + val ifc_dma_access_ok_d = WireInit(Bool(), false.B) + val ifc_dma_access_ok_prev = withClock(io.free_clk){RegNext(ifc_dma_access_ok_d, false.B)} + ic_crit_wd_rdy := ic_crit_wd_rdy_new_in | ic_crit_wd_rdy_new_ff + last_beat := bus_last_data_beat & bus_ifu_wr_en_ff + reset_beat_cnt := bus_reset_data_beat_cnt + // DMA + ifc_dma_access_ok_d := io.ifc_dma_access_ok & !iccm_correct_ecc & !io.iccm_dma_sb_error + val ifc_dma_access_q_ok = io.ifc_dma_access_ok & !iccm_correct_ecc & ifc_dma_access_ok_prev & (perr_state===err_idle_C) & !io.iccm_dma_sb_error + io.iccm_ready := ifc_dma_access_q_ok + dma_iccm_req_f := withClock(io.free_clk){RegNext(io.dma_iccm_req, false.B)} + io.iccm_wren := (ifc_dma_access_q_ok & io.dma_iccm_req & io.dma_mem_write) | iccm_correct_ecc + io.iccm_rden := (ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write) | (io.ifc_iccm_access_bf & io.ifc_fetch_req_bf) + val iccm_dma_rden = ifc_dma_access_q_ok & io.dma_iccm_req & !io.dma_mem_write + io.iccm_wr_size := Fill(3, io.dma_iccm_req) & io.dma_mem_sz + + val dma_mem_ecc = Cat(rvecc_encode(io.dma_mem_wdata(63,32)), rvecc_encode(io.dma_mem_wdata(31,0))) + val iccm_ecc_corr_data_ff = WireInit(UInt(39.W), 0.U) + io.iccm_wr_data := Mux(iccm_correct_ecc & !(ifc_dma_access_q_ok & io.dma_iccm_req), Fill(2,iccm_ecc_corr_data_ff), + Cat(dma_mem_ecc(13,7),io.dma_mem_wdata(63,32), dma_mem_ecc(6,0), io.dma_mem_wdata(31,0))) + val iccm_corrected_data = Wire(Vec(2, UInt(32.W))) + iccm_corrected_data(0) := 0.U + iccm_corrected_data(1) := 0.U + val dma_mem_addr_ff = WireInit(UInt(2.W), 0.U) + val iccm_dma_rdata_1_muxed = Mux(dma_mem_addr_ff(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1)) + val iccm_double_ecc_error = WireInit(UInt(2.W), 0.U) + val iccm_dma_ecc_error_in = iccm_double_ecc_error.orR + val iccm_dma_rdata_in = Mux(iccm_dma_ecc_error_in, Fill(2, io.dma_mem_addr), Cat(iccm_dma_rdata_1_muxed, iccm_corrected_data(0))) + val dma_mem_tag_ff = withClock(io.free_clk){RegNext(io.dma_mem_tag, 0.U)} + val iccm_dma_rtag_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(dma_mem_tag_ff, 0.U)} else 0.U + io.iccm_dma_rtag := iccm_dma_rtag_temp + + dma_mem_addr_ff := withClock(io.free_clk) {RegNext(io.dma_mem_addr(3,2), 0.U)} + val iccm_dma_rvalid_in = withClock(io.free_clk) {RegNext(iccm_dma_rden, false.B)} + val iccm_dma_rvalid_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rvalid_in, false.B)} else 0.U + io.iccm_dma_rvalid := iccm_dma_rvalid_temp + val iccm_dma_ecc_error = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_ecc_error_in, false.B)} else 0.U + io.iccm_dma_ecc_error := iccm_dma_ecc_error_in + val iccm_dma_rdata_temp = if(ICCM_ENABLE) withClock(io.free_clk){RegNext(iccm_dma_rdata_in, 0.U)} else 0.U + io.iccm_dma_rdata := iccm_dma_rdata_temp + val iccm_ecc_corr_index_ff = WireInit(UInt((ICCM_BITS-2).W), 0.U) + io.iccm_rw_addr := Mux(ifc_dma_access_q_ok & io.dma_iccm_req & !iccm_correct_ecc, io.dma_mem_addr(ICCM_BITS-1,1), + Mux(!(ifc_dma_access_q_ok & io.dma_iccm_req) & iccm_correct_ecc, Cat(iccm_ecc_corr_index_ff, 0.U), io.ifc_fetch_addr_bf(ICCM_BITS-2,0))) + val ic_fetch_val_int_f = Cat(0.U(2.W), io.ic_fetch_val_f) + val ic_fetch_val_shift_right = ic_fetch_val_int_f << ifu_fetch_addr_int_f(0) + val iccm_rdmux_data = io.iccm_rd_data_ecc + + val iccm_ecc_word_enable = (0 until 2).map(i=>((ic_fetch_val_shift_right((2*i+1),(2*i)) & !io.exu_flush_final & sel_iccm_data) | iccm_dma_rvalid_in) & !io.dec_tlu_core_ecc_disable).reverse.reduce(Cat(_,_)) + val ecc_decoded = (0 until 2).map(i=>rvecc_decode(iccm_ecc_word_enable(i), iccm_rdmux_data((39*i+31),(39*i)), iccm_rdmux_data((39*i+38),(39*i+32)), 0.U)) + val iccm_corrected_ecc = Wire(Vec(2, UInt(7.W))) + iccm_corrected_ecc := VecInit(ecc_decoded(0)._1,ecc_decoded(1)._1) + iccm_corrected_data := VecInit(ecc_decoded(0)._2,ecc_decoded(1)._2) + iccm_single_ecc_error := Cat(ecc_decoded(0)._3,ecc_decoded(1)._3) + iccm_double_ecc_error := Cat(ecc_decoded(0)._4,ecc_decoded(1)._4) + io.iccm_rd_ecc_single_err := iccm_single_ecc_error.orR & ifc_iccm_access_f & ifc_fetch_req_f + io.iccm_rd_ecc_double_err := iccm_double_ecc_error.orR & ifc_iccm_access_f + val iccm_corrected_data_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_data(0), iccm_corrected_data(1)) + val iccm_corrected_ecc_f_mux = Mux(iccm_single_ecc_error(0).asBool, iccm_corrected_ecc(0), iccm_corrected_ecc(1)) + val iccm_rd_ecc_single_err_ff = WireInit(Bool(), false.B) + val iccm_ecc_write_status = if(ICCM_ENABLE)((io.iccm_rd_ecc_single_err & !iccm_rd_ecc_single_err_ff) & !io.exu_flush_final) | io.iccm_dma_sb_error else 0.U + val iccm_rd_ecc_single_err_hold_in = (io.iccm_rd_ecc_single_err | iccm_rd_ecc_single_err_ff) & !io.exu_flush_final + iccm_error_start := io.iccm_rd_ecc_single_err + val iccm_rw_addr_f = WireInit(UInt((ICCM_BITS-2).W), 0.U) + val iccm_ecc_corr_index_in = Mux(iccm_single_ecc_error(0).asBool(), iccm_rw_addr_f, iccm_rw_addr_f + 1.U) + iccm_rw_addr_f := withClock(io.free_clk){RegNext(io.iccm_rw_addr(ICCM_BITS-2,1), 0.U)} + iccm_rd_ecc_single_err_ff := withClock(io.free_clk){RegNext(iccm_rd_ecc_single_err_hold_in, false.B)} + iccm_ecc_corr_data_ff := withClock(io.free_clk){RegEnable(Cat(iccm_corrected_ecc_f_mux, iccm_corrected_data_f_mux), 0.U, iccm_ecc_write_status.asBool())} + iccm_ecc_corr_index_ff := withClock(io.free_clk){RegEnable(iccm_ecc_corr_index_in, 0.U, iccm_ecc_write_status.asBool())} + io.ic_rd_en := (io.ifc_fetch_req_bf & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf & + !(((miss_state===stream_C) & !miss_state_en) | + ((miss_state===crit_byp_ok_C) & !miss_state_en) | + ((miss_state===stall_scnd_miss_C) & !miss_state_en) | + ((miss_state===miss_wait_C) & !miss_state_en) | + ((miss_state===crit_wrd_rdy_C) & !miss_state_en) | + ((miss_state===crit_byp_ok_C) & miss_state_en & (miss_nxtstate===miss_wait_C)) )) | + (io.ifc_fetch_req_bf & io.exu_flush_final & !io.ifc_fetch_uncacheable_bf & !io.ifc_iccm_access_bf) + val bus_ic_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + io.ic_wr_en := bus_ic_wr_en & Fill(ICACHE_NUM_WAYS, write_ic_16_bytes) + io.ic_write_stall := write_ic_16_bytes & !((((miss_state===crit_byp_ok_C) | ((miss_state===stream_C) & !(io.exu_flush_final | ifu_bp_hit_taken_q_f | stream_eol_f ))) & !(bus_ifu_wr_en_ff & last_beat & !uncacheable_miss_ff))) + reset_all_tags := withClock(io.active_clk){RegNext(io.dec_tlu_fence_i_wb, false.B)} + + val ic_valid = !ifu_wr_cumulative_err_data & !(reset_ic_in | reset_ic_ff) & !reset_tag_valid_for_miss + val ifu_status_wr_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), + ifu_status_wr_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + val ifu_status_wr_addr_ff = withClock(io.free_clk) { + RegNext(ifu_status_wr_addr_w_debug, 0.U) + } + val way_status_wr_en = WireInit(Bool(), false.B) + val way_status_wr_en_w_debug = way_status_wr_en | (io.ic_debug_wr_en & io.ic_debug_tag_array) + val way_status_wr_en_ff = withClock(io.free_clk) { + RegNext(way_status_wr_en_w_debug, false.B) + } + val way_status_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + val way_status_new_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, + if (ICACHE_STATUS_BITS == 1) io.ic_debug_wr_data(4) else io.ic_debug_wr_data(6, 4), way_status_new) + val way_status_new_ff = withClock(io.free_clk) { + RegNext(way_status_new_w_debug, 0.U) + } + val way_status_clken = (0 until ICACHE_TAG_DEPTH / 8).map(i => ifu_status_wr_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 3) === i.U) + val way_status_clk = way_status_clken.map(rvclkhdr(clock, _, io.scan_mode)) + val way_status_out = Wire(Vec(ICACHE_TAG_DEPTH, UInt(ICACHE_STATUS_BITS.W))) + for (i <- 0 until ICACHE_TAG_DEPTH / 8; j <- 0 until 8) + way_status_out((8 * i) + j) := withClock(way_status_clk(i)){RegEnable(way_status_new_ff, 0.U, (ifu_status_wr_addr_ff(2,0)===j.U) & way_status_wr_en_ff)} + val test_way_status_out = (0 until ICACHE_TAG_DEPTH).map(i=>way_status_out(i).asUInt).reverse.reduce(Cat(_,_)) + // io.test_way_status_out := test_way_status_out + val test_way_status_clken = (0 until ICACHE_TAG_DEPTH/8).map(i=>way_status_clken(i).asUInt()).reverse.reduce(Cat(_,_)) + //io.test_way_status_clken := test_way_status_clken + way_status := Mux1H((0 until ICACHE_TAG_DEPTH).map(i=>(ifu_ic_rw_int_addr_ff === i.U) -> way_status_out(i))) + val ifu_ic_rw_int_addr_w_debug = Mux((io.ic_debug_rd_en | io.ic_debug_wr_en) & io.ic_debug_tag_array, + io.ic_debug_addr(ICACHE_INDEX_HI - 3, ICACHE_TAG_INDEX_LO - 3), ifu_ic_rw_int_addr(ICACHE_INDEX_HI - 1, ICACHE_TAG_INDEX_LO - 1)) + ifu_ic_rw_int_addr_ff := withClock(io.free_clk) { + RegNext(ifu_ic_rw_int_addr_w_debug, 0.U) + } + val ifu_tag_wren = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ic_debug_tag_wr_en = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + val ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en + val ifu_tag_wren_ff = withClock(io.free_clk) { + RegNext(ifu_tag_wren_w_debug, 0.U) + } + val ic_valid_w_debug = Mux(io.ic_debug_wr_en & io.ic_debug_tag_array, io.ic_debug_wr_data(0), ic_valid) + val ic_valid_ff = withClock(io.free_clk) { + RegNext(ic_valid_w_debug, false.B) + } + val tag_valid_clken = (0 until (ICACHE_TAG_DEPTH / 32)).map(i => (0 until ICACHE_NUM_WAYS).map(j => + if (ICACHE_TAG_DEPTH == 32) ifu_tag_wren_ff(j) | perr_err_inv_way(j) | reset_all_tags + else ((ifu_ic_rw_int_addr_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & ifu_tag_wren_ff(j)) | + ((perr_ic_index_ff(ICACHE_INDEX_HI - ICACHE_TAG_INDEX_LO, 5) === i.U) & perr_err_inv_way(j)) | + reset_all_tags).reverse.reduce(Cat(_, _))) + val tag_valid_clk = (0 until ICACHE_TAG_DEPTH / 32).map(i => (0 until ICACHE_NUM_WAYS).map(j => rvclkhdr(clock, tag_valid_clken(i)(j), io.scan_mode))) + val ic_tag_valid_out = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_TAG_DEPTH, Bool()))) + // io.valids := Cat((0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(1)(i).asUInt()).reverse.reduce(Cat(_,_)), + // (0 until ICACHE_TAG_DEPTH).map(i=>ic_tag_valid_out(0)(i).asUInt()).reverse.reduce(Cat(_,_))) + + for (i <- 0 until (ICACHE_TAG_DEPTH / 32); j <- 0 until ICACHE_NUM_WAYS; k <- 0 until 32) + ic_tag_valid_out(j)((32 * i) + k) := withClock(tag_valid_clk(i)(j)){RegEnable(ic_valid_ff & !reset_all_tags.asBool & !perr_sel_invalidate, false.B, + ((((ifu_ic_rw_int_addr_ff === (k + (32 * i)).U) & ifu_tag_wren_ff(j)) | ((perr_ic_index_ff === (k + (32 * i)).U) & perr_err_inv_way(j)) | reset_all_tags)).asBool)} + + val ic_tag_valid_unq = (0 until ICACHE_NUM_WAYS).map(k => (0 until ICACHE_TAG_DEPTH).map(j => + Mux(ifu_ic_rw_int_addr_ff === j.U, ic_tag_valid_out(k)(j), false.B).asUInt).reduce(_|_)).reverse.reduce(Cat(_,_)) + + // Making a sudo LRU + // val replace_way_mb_any = Wire(Vec(ICACHE_NUM_WAYS, Bool())) + val way_status_hit_new = WireInit(UInt(ICACHE_STATUS_BITS.W), 0.U) + if (ICACHE_NUM_WAYS == 4) { + replace_way_mb_any(3) := (way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(3) & tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(2) := (!way_status_mb_ff(2) & way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(2) & tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(1) := (way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | + (!tagv_mb_ff(1) & tagv_mb_ff(0)) + replace_way_mb_any(0) := (!way_status_mb_ff(1) & !way_status_mb_ff(0) & tagv_mb_ff(3, 0).andR) | !tagv_mb_ff(0) + + way_status_hit_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status(2), 3.U), + io.ic_rd_hit(1) -> Cat(way_status(2), 1.U(2.W)), + io.ic_rd_hit(2) -> Cat(1.U, way_status(1), 0.U), + io.ic_rd_hit(3) -> Cat(0.U, way_status(1), 0.U))) + + way_status_rep_new := Mux1H(Seq(io.ic_rd_hit(0) -> Cat(way_status_mb_ff(2), 3.U), + io.ic_rd_hit(1) -> Cat(way_status_mb_ff(2), 1.U(2.W)), + io.ic_rd_hit(2) -> Cat(1.U, way_status_mb_ff(1), 0.U), + io.ic_rd_hit(3) -> Cat(0.U, way_status_mb_ff(1), 0.U))) + } + else { + replace_way_mb_any(0) := (!way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(0) + replace_way_mb_any(1) := (way_status_mb_ff & tagv_mb_ff(0) & tagv_mb_ff(1)) | !tagv_mb_ff(1) & tagv_mb_ff(0) + way_status_hit_new := io.ic_rd_hit(0) + way_status_rep_new := replace_way_mb_any(0) + } + way_status_new := Mux((bus_ifu_wr_en_ff_q & last_beat).asBool, way_status_rep_new, way_status_hit_new) + way_status_wr_en := (bus_ifu_wr_en_ff_q & last_beat) | ic_act_hit_f + val bus_wren = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_q & replace_way_mb_any(i) & miss_pending) + + val bus_wren_last = (0 until ICACHE_NUM_WAYS).map(i => bus_ifu_wr_en_ff_wo_err & replace_way_mb_any(i) & miss_pending & bus_last_data_beat) + val wren_reset_miss = (0 until ICACHE_NUM_WAYS).map(i => replace_way_mb_any(i) & reset_tag_valid_for_miss) + ifu_tag_wren := (0 until ICACHE_NUM_WAYS).map(i => bus_wren_last(i) | wren_reset_miss(i)).reverse.reduce(Cat(_, _)) + + bus_ic_wr_en := bus_wren.reverse.reduce(Cat(_,_)) + if(!ICACHE_ENABLE){ + for(i<- 0 until ICACHE_NUM_WAYS){ + + bus_wren(i) := 0.U + } + ic_tag_valid_unq := 0.U + way_status := 0.U + replace_way_mb_any := 0.U + way_status_hit_new := 0.U + way_status_rep_new := 0.U + way_status_new := 0.U + way_status_wr_en := 0.U + } + io.ic_tag_valid := ic_tag_valid_unq & Fill(ICACHE_NUM_WAYS, !fetch_uncacheable_ff & ifc_fetch_req_f) + + val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) + ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR() + + io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)} + io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)} + io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)} + io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)} + io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)} + + + io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics + io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16) + io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid + io.ic_debug_wr_en := io.dec_tlu_ic_diag_pkt.icache_wr_valid + io.ic_debug_way := Cat(io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===3.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===2.U, + io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===1.U, io.dec_tlu_ic_diag_pkt.icache_dicawics(15,14)===0.U) + ic_debug_tag_wr_en := Fill(ICACHE_NUM_WAYS, io.ic_debug_wr_en & io.ic_debug_tag_array) & io.ic_debug_way + val ic_debug_ict_array_sel_in = io.ic_debug_rd_en & io.ic_debug_tag_array + ic_debug_way_ff := withClock(debug_c1_clk){RegNext(io.ic_debug_way, 0.U)} + ic_debug_ict_array_sel_ff := withClock(debug_c1_clk){RegNext(ic_debug_ict_array_sel_in, 0.U)} + ic_debug_rd_en_ff := withClock(io.free_clk){RegNext(io.ic_debug_rd_en, false.B)} + io.ifu_ic_debug_rd_data_valid := withClock(io.free_clk){RegEnable(ic_debug_rd_en_ff, 0.U, ic_debug_rd_en_ff.asBool)} + val ifc_region_acc_okay = Cat(INST_ACCESS_ENABLE0.U,INST_ACCESS_ENABLE1.U,INST_ACCESS_ENABLE2.U,INST_ACCESS_ENABLE3.U,INST_ACCESS_ENABLE4.U,INST_ACCESS_ENABLE5.U,INST_ACCESS_ENABLE6.U,INST_ACCESS_ENABLE7.U).orR() | + INST_ACCESS_ENABLE0.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK0).U) === (INST_ACCESS_ADDR0.U | aslong(INST_ACCESS_MASK0).U)) | + INST_ACCESS_ENABLE1.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK1).U) === (INST_ACCESS_ADDR1.U | aslong(INST_ACCESS_MASK1).U)) | + INST_ACCESS_ENABLE2.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK2).U) === (INST_ACCESS_ADDR2.U | aslong(INST_ACCESS_MASK2).U)) | + INST_ACCESS_ENABLE3.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK3).U) === (INST_ACCESS_ADDR3.U | aslong(INST_ACCESS_MASK3).U)) | + INST_ACCESS_ENABLE4.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK4).U) === (INST_ACCESS_ADDR4.U | aslong(INST_ACCESS_MASK4).U)) | + INST_ACCESS_ENABLE5.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK5).U) === (INST_ACCESS_ADDR5.U | aslong(INST_ACCESS_MASK5).U)) | + INST_ACCESS_ENABLE6.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK6).U) === (INST_ACCESS_ADDR6.U | aslong(INST_ACCESS_MASK6).U)) | + INST_ACCESS_ENABLE7.U & ((Cat(io.ifc_fetch_addr_bf, 0.U) | aslong(INST_ACCESS_MASK7).U) === (INST_ACCESS_ADDR7.U | aslong(INST_ACCESS_MASK7).U)) + val ifc_region_acc_fault_memory_bf = !io.ifc_iccm_access_bf & !ifc_region_acc_okay & io.ifc_fetch_req_bf + ifc_region_acc_fault_final_bf := io.ifc_region_acc_fault_bf | ifc_region_acc_fault_memory_bf + ifc_region_acc_fault_memory_f := withClock(io.free_clk){RegNext(ifc_region_acc_fault_memory_bf, false.B)} + +} +object ifu_mem extends App { + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_mem_ctl())) +} + diff --git a/src/main/scala/include/el2_bundle.scala b/src/main/scala/include/el2_bundle.scala index c18df382..ce98a498 100644 --- a/src/main/scala/include/el2_bundle.scala +++ b/src/main/scala/include/el2_bundle.scala @@ -1,4 +1,5 @@ package include + import chisel3._ // use this for instance declaration val io = IO(Output(new el2_trace_pkt_t)) @@ -14,6 +15,7 @@ class el2_trace_pkt_t extends Bundle{ + object el2_inst_pkt_t extends Enumeration{ val NULL = "b0000".U(4.W) val MUL = "b0001".U(4.W) @@ -32,8 +34,27 @@ object el2_inst_pkt_t extends Enumeration{ val JAL = "b1110".U(4.W) val BITMANIPU = "b1111".U(4.W) } +/* +class el2_inst_pkt_t extends Bundle{ + val NULL = "b0000".U(4.W) + val MUL = "b0001".U(4.W) + val LOAD = "b0010".U(4.W) + val STORE = "b0011".U(4.W) + val ALU = "b0100".U(4.W) + val CSRREAD = "b0101".U(4.W) + val CSRWRITE = "b0110".U(4.W) + val CSRRW = "b0111".U(4.W) + val EBREAK = "b1000".U(4.W) + val ECALL = "b1001".U(4.W) + val FENCE = "b1010".U(4.W) + val FENCEI = "b1011".U(4.W) + val MRET = "b1100".U(4.W) + val CONDBR = "b1101".U(4.W) + val JAL = "b1110".U(4.W) + val BITMANIPU = "b1111".U(4.W) +} - +*/ class el2_load_cam_pkt_t extends Bundle { val valid = UInt(1.W) val wb = UInt(1.W) @@ -54,7 +75,7 @@ class el2_br_pkt_t extends Bundle { val br_error = UInt(1.W) val br_start_error = UInt(1.W) val bank = UInt(1.W) - val prett = UInt(32.W) // predicted ret target //[31:1] in swerv + val prett = UInt(31.W) // predicted ret target val way = UInt(1.W) val ret = UInt(1.W) } @@ -79,7 +100,7 @@ class el2_predict_pkt_t extends Bundle { val valid = UInt(1.W) val br_error = UInt(1.W) val br_start_error = UInt(1.W) - val prett = UInt(32.W) //[31:1] in swerv + val prett = UInt(31.W) val pcall = UInt(1.W) val pret = UInt(1.W) val pja = UInt(1.W) @@ -94,7 +115,7 @@ class el2_trap_pkt_t extends Bundle { val icaf_type = UInt(2.W) val fence_i = UInt(1.W) val i0trigger = UInt(4.W) - val pmu_i0_itype = el2_inst_pkt_t //pmu-instructiontype + val pmu_i0_itype =UInt(4.W) //new el2_inst_pkt_t //pmu-instructiontype val pmu_i0_br_unpred = UInt(1.W) //pmu val pmu_divide = UInt(1.W) val pmu_lsu_misaligned = UInt(1.W) @@ -148,19 +169,19 @@ class el2_alu_pkt_t extends Bundle { } class el2_lsu_pkt_t extends Bundle { - val fast_int = UInt(1.W) - val by = UInt(1.W) - val half = UInt(1.W) - val word = UInt(1.W) - val dword = UInt(1.W) // for dma - val load = UInt(1.W) - val store = UInt(1.W) - val unsign = UInt(1.W) - val dma = UInt(1.W) // dma pkt - val store_data_bypass_d = UInt(1.W) - val load_ldst_bypass_d = UInt(1.W) - val store_data_bypass_m = UInt(1.W) - val valid = UInt(1.W) + val fast_int = Bool() + val by = Bool() + val half = Bool() + val word = Bool() + val dword = Bool() // for dma + val load = Bool() + val store = Bool() + val unsign = Bool() + val dma = Bool() // dma pkt + val store_data_bypass_d = Bool() + val load_ldst_bypass_d = Bool() + val store_data_bypass_m = Bool() + val valid = Bool() } class el2_lsu_error_pkt_t extends Bundle { @@ -168,8 +189,8 @@ class el2_lsu_error_pkt_t extends Bundle { val single_ecc_error = UInt(1.W) val inst_type = UInt(1.W) //0: Load, 1: Store val exc_type = UInt(1.W) //0: MisAligned, 1: Access Fault - val mscause = UInt(4.W) - val addr = UInt(32.W) + val mscause = UInt(1.W) + val addr = UInt(1.W) } class el2_dec_pkt_t extends Bundle { @@ -225,7 +246,6 @@ class el2_dec_pkt_t extends Bundle { val legal = Bool() } - class el2_mul_pkt_t extends Bundle { val valid = UInt(1.W) val rs1_sign = UInt(1.W) @@ -321,3 +341,74 @@ class el2_cache_debug_pkt_t extends Bundle { val icache_wr_valid = UInt(1.W) } +class el2_dec_tlu_csr_pkt extends Bundle{ + val csr_misa =UInt(1.W) + val csr_mvendorid =UInt(1.W) + val csr_marchid =UInt(1.W) + val csr_mimpid =UInt(1.W) + val csr_mhartid =UInt(1.W) + val csr_mstatus =UInt(1.W) + val csr_mtvec =UInt(1.W) + val csr_mip =UInt(1.W) + val csr_mie =UInt(1.W) + val csr_mcyclel =UInt(1.W) + val csr_mcycleh =UInt(1.W) + val csr_minstretl =UInt(1.W) + val csr_minstreth =UInt(1.W) + val csr_mscratch =UInt(1.W) + val csr_mepc =UInt(1.W) + val csr_mcause =UInt(1.W) + val csr_mscause =UInt(1.W) + val csr_mtval =UInt(1.W) + val csr_mrac =UInt(1.W) + val csr_dmst =UInt(1.W) + val csr_mdseac =UInt(1.W) + val csr_meihap =UInt(1.W) + val csr_meivt =UInt(1.W) + val csr_meipt =UInt(1.W) + val csr_meicurpl =UInt(1.W) + val csr_meicidpl =UInt(1.W) + val csr_dcsr =UInt(1.W) + val csr_mcgc =UInt(1.W) + val csr_mfdc =UInt(1.W) + val csr_dpc =UInt(1.W) + val csr_mtsel =UInt(1.W) + val csr_mtdata1 =UInt(1.W) + val csr_mtdata2 =UInt(1.W) + val csr_mhpmc3 =UInt(1.W) + val csr_mhpmc4 =UInt(1.W) + val csr_mhpmc5 =UInt(1.W) + val csr_mhpmc6 =UInt(1.W) + val csr_mhpmc3h =UInt(1.W) + val csr_mhpmc4h =UInt(1.W) + val csr_mhpmc5h =UInt(1.W) + val csr_mhpmc6h =UInt(1.W) + val csr_mhpme3 =UInt(1.W) + val csr_mhpme4 =UInt(1.W) + val csr_mhpme5 =UInt(1.W) + val csr_mhpme6 =UInt(1.W) + val csr_mcountinhibit =UInt(1.W) + val csr_mitctl0 =UInt(1.W) + val csr_mitctl1 =UInt(1.W) + val csr_mitb0 =UInt(1.W) + val csr_mitb1 =UInt(1.W) + val csr_mitcnt0 =UInt(1.W) + val csr_mitcnt1 =UInt(1.W) + val csr_mpmc =UInt(1.W) + val csr_mcpc =UInt(1.W) + val csr_meicpct =UInt(1.W) + val csr_mdeau =UInt(1.W) + val csr_micect =UInt(1.W) + val csr_miccmect =UInt(1.W) + val csr_mdccmect =UInt(1.W) + val csr_mfdht =UInt(1.W) + val csr_mfdhs =UInt(1.W) + val csr_dicawics =UInt(1.W) + val csr_dicad0h =UInt(1.W) + val csr_dicad0 =UInt(1.W) + val csr_dicad1 =UInt(1.W) + val csr_dicago =UInt(1.W) + val presync =UInt(1.W) + val postsync =UInt(1.W) + val legal =UInt(1.W) +} diff --git a/src/main/scala/lib/RVC.scala b/src/main/scala/lib/RVC.scala new file mode 100644 index 00000000..cfcacf91 --- /dev/null +++ b/src/main/scala/lib/RVC.scala @@ -0,0 +1,232 @@ +// See LICENSE.SiFive for license details. + +//package freechips.rocketchip.rocket +package lib + +import chisel3._ +import chisel3.util._ +import chisel3.util.ImplicitConversions +import chisel3.experimental._ +import Chisel.ImplicitConversions._ + +//import freechips.rocketchip.config.Parameters +//import freechips.rocketchip.tile._ +//import freechips.rocketchip.util._ + +class ExpandedInstruction extends Bundle { + val bits = UInt(32.W) + val rd = UInt(5.W) + val rs1 = UInt(5.W) + val rs2 = UInt(5.W) + val rs3 = UInt(5.W) +} + +class RVCDecoder(x: UInt, xLen: Int) { + def inst(bits: UInt, rd: UInt = x(11,7), rs1: UInt = x(19,15), rs2: UInt = x(24,20), rs3: UInt = x(31,27)) = { + val res = Wire(new ExpandedInstruction) + res.bits := bits + res.rd := rd + res.rs1 := rs1 + res.rs2 := rs2 + res.rs3 := rs3 + res + } + + def rs1p = Cat(1.U(2.W), x(9,7)) + def rs2p = Cat(1.U(2.W), x(4,2)) + def rs2 = x(6,2) + def rd = x(11,7) + def addi4spnImm = Cat(x(10,7), x(12,11), x(5), x(6), 0.U(2.W)) + def lwImm = Cat(x(5), x(12,10), x(6), 0.U(2.W)) + def ldImm = Cat(x(6,5), x(12,10), 0.U(3.W)) + def lwspImm = Cat(x(3,2), x(12), x(6,4), 0.U(2.W)) + def ldspImm = Cat(x(4,2), x(12), x(6,5), 0.U(3.W)) + def swspImm = Cat(x(8,7), x(12,9), 0.U(2.W)) + def sdspImm = Cat(x(9,7), x(12,10), 0.U(3.W)) + def luiImm = Cat(Fill(15, x(12)), x(6,2), 0.U(12.W)) + def addi16spImm = Cat(Fill(3, x(12)), x(4,3), x(5), x(2), x(6), 0.U(4.W)) + def addiImm = Cat(Fill(7, x(12)), x(6,2)) + def jImm = Cat(Fill(10, x(12)), x(8), x(10,9), x(6), x(7), x(2), x(11), x(5,3), 0.U(1.W)) + def bImm = Cat(Fill(5, x(12)), x(6,5), x(2), x(11,10), x(4,3), 0.U(1.W)) + def shamt = Cat(x(12), x(6,2)) + def x0 = 0.U(5.W) + def ra = 1.U(5.W) + def sp = 2.U(5.W) + + def q0 = { + def addi4spn = { + val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) + } + def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + def flw = { + if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + else ld + } + def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + def fsw = { + if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + else sd + } + Seq(addi4spn, fld, lw, flw, unimp, fsd, sw, fsw) + } + + def q1 = { + def addi = inst(Cat(addiImm, rd, 0.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2p) + def addiw = { + val opc = Mux(rd.orR, 0x1B.U(7.W), 0x1F.U(7.W)) + inst(Cat(addiImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) + } + def jal = { + if (xLen == 32) inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), ra, 0x6F.U(7.W)), ra, rd, rs2p) + else addiw + } + def li = inst(Cat(addiImm, x0, 0.U(3.W), rd, 0x13.U(7.W)), rd, x0, rs2p) + def addi16sp = { + val opc = Mux(addiImm.orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi16spImm, rd, 0.U(3.W), rd, opc), rd, rd, rs2p) + } + def lui = { + val opc = Mux(addiImm.orR, 0x37.U(7.W), 0x3F.U(7.W)) + val me = inst(Cat(luiImm(31,12), rd, opc), rd, rd, rs2p) + Mux(rd === x0 || rd === sp, addi16sp, me) + } + def j = inst(Cat(jImm(20), jImm(10,1), jImm(11), jImm(19,12), x0, 0x6F.U(7.W)), x0, rs1p, rs2p) + def beqz = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 0.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), rs1p, rs1p, x0) + def bnez = inst(Cat(bImm(12), bImm(10,5), x0, rs1p, 1.U(3.W), bImm(4,1), bImm(11), 0x63.U(7.W)), x0, rs1p, x0) + def arith = { + def srli = Cat(shamt, rs1p, 5.U(3.W), rs1p, 0x13.U(7.W)) + def srai = srli | (1 << 30).U + def andi = Cat(addiImm, rs1p, 7.U(3.W), rs1p, 0x13.U(7.W)) + def rtype = { + val funct = VecInit(0.U, 4.U, 6.U, 7.U, 0.U, 0.U, 2.U, 3.U)(Cat(x(12), x(6,5))) + val sub = Mux(x(6,5) === 0.U, (1 << 30).U, 0.U) + val opc = Mux(x(12), 0x3B.U(7.W), 0x33.U(7.W)) + Cat(rs2p, rs1p, funct, rs1p, opc) | sub + } + inst(VecInit(srli, srai, andi, rtype)(x(11,10)), rs1p, rs1p, rs2p) + } + Seq(addi, jal, li, lui, arith, j, beqz, bnez) + } + + def q2 = { + val load_opc = Mux(rd.orR, 0x03.U(7.W), 0x1F.U(7.W)) + def slli = inst(Cat(shamt, rd, 1.U(3.W), rd, 0x13.U(7.W)), rd, rd, rs2) + def ldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, load_opc), rd, sp, rs2) + def lwsp = inst(Cat(lwspImm, sp, 2.U(3.W), rd, load_opc), rd, sp, rs2) + def fldsp = inst(Cat(ldspImm, sp, 3.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) + def flwsp = { + if (xLen == 32) inst(Cat(lwspImm, sp, 2.U(3.W), rd, 0x07.U(7.W)), rd, sp, rs2) + else ldsp + } + def sdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) + def swsp = inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x23.U(7.W)), rd, sp, rs2) + def fsdsp = inst(Cat(sdspImm >> 5, rs2, sp, 3.U(3.W), sdspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) + def fswsp = { + if (xLen == 32) inst(Cat(swspImm >> 5, rs2, sp, 2.U(3.W), swspImm(4,0), 0x27.U(7.W)), rd, sp, rs2) + else sdsp + } + def jalr = { + val mv = inst(Cat(rs2, x0, 0.U(3.W), rd, 0x33.U(7.W)), rd, x0, rs2) + val add = inst(Cat(rs2, rd, 0.U(3.W), rd, 0x33.U(7.W)), rd, rd, rs2) + val jr = Cat(rs2, rd, 0.U(3.W), x0, 0x67.U(7.W)) + val reserved = Cat(jr >> 7, 0x1F.U(7.W)) + val jr_reserved = inst(Mux(rd.orR, jr, reserved), x0, rd, rs2) + val jr_mv = Mux(rs2.orR, mv, jr_reserved) + val jalr = Cat(rs2, rd, 0.U(3.W), ra, 0x67.U(7.W)) + val ebreak = Cat(jr >> 7, 0x73.U(7.W)) | (1 << 20).U + val jalr_ebreak = inst(Mux(rd.orR, jalr, ebreak), ra, rd, rs2) + val jalr_add = Mux(rs2.orR, add, jalr_ebreak) + Mux(x(12), jalr_add, jr_mv) + } + Seq(slli, fldsp, lwsp, flwsp, jalr, fsdsp, swsp, fswsp) + } + + def q3 = Seq.fill(8)(passthrough) + + def passthrough = inst(x) + + def decode = { + val s = VecInit(q0 ++ q1 ++ q2 ++ q3) + s(Cat(x(1,0), x(15,13))) + } + + + + def changed_q0 = { + def addi4spn = { + val opc = Mux(x(12,5).orR, 0x13.U(7.W), 0x1F.U(7.W)) + inst(Cat(addi4spnImm, sp, 0.U(3.W), rs2p, opc), rs2p, sp, rs2p) + } + def ld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def lw = inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x03.U(7.W)), rs2p, rs1p, rs2p) + def fld = inst(Cat(ldImm, rs1p, 3.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + def flw = { + if (xLen == 32) inst(Cat(lwImm, rs1p, 2.U(3.W), rs2p, 0x07.U(7.W)), rs2p, rs1p, rs2p) + else ld + } + def unimp = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x3F.U(7.W)), rs2p, rs1p, rs2p) + def sd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def sw = inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x23.U(7.W)), rs2p, rs1p, rs2p) + def fsd = inst(Cat(ldImm >> 5, rs2p, rs1p, 3.U(3.W), ldImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + def fsw = { + if (xLen == 32) inst(Cat(lwImm >> 5, rs2p, rs1p, 2.U(3.W), lwImm(4,0), 0x27.U(7.W)), rs2p, rs1p, rs2p) + else sd + } + addi4spn + } + + def ret_q0 = VecInit(q0) + def ret_q1 = q1 + def ret_q2 = q2 + def ret_q3 = q3 +} + +class RVCExpander( val XLen: Int, val usingCompressed: Boolean) extends Module { + val io = IO(new Bundle { + val in = Input(UInt(32.W)) + val out = Output(new ExpandedInstruction) + val rvc = Output(Bool()) + val legal = Output(Bool()) + val waleed_out = Output(UInt(32.W)) + //val q1_Out = Output(new ExpandedInstruction) + //val q2_Out = Output(new ExpandedInstruction) + //val q3_Out = Output(new ExpandedInstruction) + }) + if (usingCompressed) { + io.rvc := io.in(1,0) =/= 3.U + val inst = new RVCDecoder(io.in, XLen) + io.out := inst.decode + io.legal := (!io.in(13))&(!io.in(12))&(io.in(11))&io.in(1)&(!io.in(0)) | + (!io.in(13))&(!io.in(12))&(io.in(6))&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&io.in(11)(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(5)&io.in(1)&(!io.in(0)) | + (!io.in(13))&(!io.in(12))&io.in(10)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(6)&(!io.in(1)) | io.in(15)&(!io.in(12))&(!io.in(1))&io.in(0) | + (!io.in(13))&(!io.in(12))&io.in(9)&io.in(1)&(!io.in(0)) | + (!io.in(12))&io.in(6)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(5)&(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(8)&io.in(1)&(!io.in(0)) | + (!io.in(12))&io.in(5)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(10)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(7)&io.in(1)&(!io.in(0)) | + io.in(12)&io.in(11)&(!io.in(10))&(!io.in(1))&io.in(0) | (!io.in(15))&(!io.in(13))&io.in(9)&(!io.in(1)) | + (!io.in(13))&(!io.in(12))&io.in(4)&io.in(1)&(!io.in(0)) | io.in(13)&io.in(12)&(!io.in(1))&io.in(0) | + (!io.in(15))&(!io.in(13))&io.in(8)&(!io.in(1)) | (!io.in(13))&(!io.in(12))&io.in(3)&io.in(1)&(!io.in(0)) | + io.in(13)&io.in(4)&(!io.in(1))&io.in(0) | (!io.in(13))&(!io.in(12))&io.in(2)&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&io.in(7)&(!io.in(1)) | io.in(13)&io.in(3)&(!io.in(1))&io.in(0) | + io.in(13)&io.in(2)&(!io.in(1))&io.in(0) | io.in(14)&(!io.in(13))&(!io.in(1)) | + (!io.in(14))&(!io.in(12))&(!io.in(1))&io.in(0) | io.in(15)&(!io.in(13))&io.in(12)&io.in(1)&(!io.in(0)) | + (!io.in(15))&(!io.in(13))&(!io.in(12))&io.in(1)&(!io.in(0)) | (!io.in(15))&(!io.in(13))&io.in(12)&(!io.in(1)) | + io.in(14)&(!io.in(13))&(!io.in(0)) + io.waleed_out := Mux(io.legal,io.out.bits,0.U) + } else { + io.rvc := false.B + io.out := new RVCDecoder(io.in, XLen).passthrough + } +} + diff --git a/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala new file mode 100644 index 00000000..e1da8da5 --- /dev/null +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -0,0 +1,85 @@ +package lib +import chisel3._ +import chisel3.util._ +import chisel3.experimental.chiselName + +@chiselName +class ahb_to_axi4 extends Module with el2_lib with RequireAsyncReset { + val TAG = 1 + val io = IO(new Bundle { + val scan_mode = Input(Bool()) + val bus_clk_en = Input(Bool()) + val clk_override = Input(Bool()) + val axi_awready = Input(Bool()) + val axi_wready = Input(Bool()) + val axi_bvalid = Input(Bool()) + val axi_bresp = Input(UInt(2.W)) + val axi_bid = Input(UInt(TAG.W)) + val axi_arready = Input(Bool()) + val axi_rvalid = Input(Bool()) + val axi_rid = Input(UInt(TAG.W)) + val axi_rdata = Input(UInt(64.W)) + val axi_rresp = Input(UInt(2.W)) + val ahb_haddr = Input(UInt(32.W)) // ahb bus address + val ahb_hburst = Input(UInt(3.W)) // tied to 0 + val ahb_hmastlock = Input(Bool()) // tied to 0 + val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 + val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) + val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) + val ahb_hwrite = Input(Bool()) // ahb bus write + val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data + val ahb_hsel = Input(Bool()) // this slave was selected + val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not + // outputs + val axi_awvalid = Output(Bool()) + val axi_awid = Output(UInt(TAG.W)) + val axi_awaddr = Output(UInt(32.W)) + val axi_awsize = Output(UInt(3.W)) + val axi_awprot = Output(UInt(3.W)) + val axi_awlen = Output(UInt(8.W)) + val axi_awburst = Output(UInt(2.W)) + val axi_wvalid = Output(Bool()) + val axi_wdata = Output(UInt(64.W)) + val axi_wstrb = Output(UInt(8.W)) + val axi_wlast = Output(Bool()) + val axi_bready = Output(Bool()) + val axi_arvalid = Output(Bool()) + val axi_arid = Output(UInt(TAG.W)) + val axi_araddr = Output(UInt(32.W)) + val axi_arsize = Output(UInt(3.W)) + val axi_arprot = Output(UInt(3.W)) + val axi_arlen = Output(UInt(8.W)) + val axi_arburst = Output(UInt(2.W)) + val axi_rready = Output(Bool()) + val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data + val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction + val ahb_hresp = Output(Bool()) // slave response (high indicates erro) + }) + io.axi_awvalid := 0.U + io.axi_awid := 0.U + io.axi_awaddr := 0.U + io.axi_awsize := 0.U + io.axi_awprot := 0.U + io.axi_awlen := 0.U + io.axi_awburst := 0.U + io.axi_wvalid := 0.U + io.axi_wdata := 0.U + io.axi_wstrb := 0.U + io.axi_wlast := 0.U + io.axi_bready := 0.U + io.axi_arvalid := 0.U + io.axi_arid := 0.U + io.axi_araddr := 0.U + io.axi_arsize := 0.U + io.axi_arprot := 0.U + io.axi_arlen := 0.U + io.axi_arburst := 0.U + io.axi_rready := 0.U + io.ahb_hrdata := 0.U + io.ahb_hreadyout := 0.U + io.ahb_hresp := 0.U +} +object AHB_main extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new ahb_to_axi4())) +} \ No newline at end of file diff --git a/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala new file mode 100644 index 00000000..4484873e --- /dev/null +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -0,0 +1,442 @@ +package lib + +import chisel3._ +import chisel3.util._ + +trait Config { + val TAG = 1 +} + +class axi4_to_ahb_IO extends Bundle with Config { + + val scan_mode = Input(Bool()) + val bus_clk_en = Input(Bool()) + val clk_override = Input(Bool()) + val axi_awvalid = Input(Bool()) + val axi_awid = Input(UInt(TAG.W)) // [TAG-1:0] + val axi_awaddr = Input(UInt(32.W)) // [31:0] + val axi_awsize = Input(UInt(3.W)) // [2:0] + val axi_awprot = Input(UInt(3.W)) // [2:0] + val axi_wvalid = Input(Bool()) + val axi_wdata = Input(UInt(64.W)) // [63:0] + val axi_wstrb = Input(UInt(8.W)) // [7:0] + val axi_wlast = Input(Bool()) + val axi_bready = Input(Bool()) + val axi_arvalid = Input(Bool()) + val axi_arid = Input(UInt(TAG.W)) // [TAG-1:0] + val axi_araddr = Input(UInt(32.W)) // [31:0] + val axi_arsize = Input(UInt(3.W)) // [2:0] + val axi_arprot = Input(UInt(3.W)) // [2:0] + val axi_rready = Input(Bool()) + val ahb_hrdata = Input(UInt(64.W)) // [63:0] // ahb bus read data + val ahb_hready = Input(Bool()) // slave ready to accept transaction + val ahb_hresp = Input(Bool()) // slave response (high indicates erro) + //----------------------------outputs--------------------------- + val axi_awready = Output(Bool()) + val axi_wready = Output(Bool()) + val axi_bvalid = Output(Bool()) + val axi_bresp = Output(UInt(2.W)) // [1:0]] + val axi_bid = Output(UInt(TAG.W)) // [TAG-1:0] + // AXI Read Channels + val axi_arready = Output(Bool()) + val axi_rvalid = Output(Bool()) + val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0] + val axi_rdata = Output(UInt(32.W)) // [63:0] + val axi_rresp = Output(UInt(2.W)) // 1:0] + val axi_rlast = Output(Bool()) + // AHB-Lite signals + val ahb_haddr = Output(UInt(32.W)) // [31:0] // ahb bus address + val ahb_hburst = Output(UInt(3.W)) // [2:0] // tied to 0 + val ahb_hmastlock = Output(Bool()) // tied to 0 + val ahb_hprot = Output(UInt(4.W)) // [3:0] // tied to 4'b0011 + val ahb_hsize = Output(UInt(3.W)) // [2:0] // size of bus transaction (possible values 0,1,2,3) + val ahb_htrans = Output(UInt(2.W)) + val ahb_hwrite = Output(Bool()) // ahb bus write + val ahb_hwdata = Output(UInt(64.W)) // [63:0] // ahb bus write data +} + +class axi4_to_ahb extends Module with el2_lib with RequireAsyncReset with Config { + val io = IO(new axi4_to_ahb_IO) + val idle :: cmd_rd :: cmd_wr :: data_rd :: data_wr :: done :: stream_rd :: stream_err_rd :: nil = Enum(8) + val state = RegInit(idle) // typedef enum + val buf_state = RegInit(idle) + val buf_nxtstate = RegInit(idle) + //logic signals + val slave_valid = WireInit(Bool(), init = false.B) + val slave_ready = WireInit(Bool(), init = false.B) + val slave_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] + val slave_rdata = WireInit(0.U(64.W)) // [63:0] + val slave_opc = WireInit(0.U(4.W)) // [3:0] + val wrbuf_en = WireInit(Bool(), init = false.B) + val wrbuf_data_en = WireInit(Bool(), init = false.B) + val wrbuf_cmd_sent = WireInit(Bool(), init = false.B) + val wrbuf_rst = WireInit(Bool(), init = false.B) + val wrbuf_vld = WireInit(Bool(), init = false.B) + val wrbuf_data_vld = WireInit(Bool(), init = false.B) + val wrbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] + val wrbuf_size = WireInit(0.U(3.W)) // [2:0] + val wrbuf_addr = WireInit(0.U(32.W)) // [31:0] + val wrbuf_data = WireInit(0.U(64.W)) // [63:0] + val wrbuf_byteen = WireInit(0.U(8.W)) // [7:0] + + val bus_write_clk_en = WireInit(Bool(), init = false.B) + val bus_clk = Wire(Clock()) + val bus_write_clk = Wire(Clock()) + + val master_valid = WireInit(Bool(), init = false.B) + val master_ready = WireInit(0.U(1.W)) + val master_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] + val master_addr = WireInit(0.U(32.W)) // [31:0] + val master_wdata = WireInit(0.U(64.W)) // [63:0] + val master_size = WireInit(0.U(3.W)) // [2:0] + val master_opc = WireInit(0.U(3.W)) // [2:0] + val master_byteen = WireInit(0.U(8.W)) // [7:0] + // Buffer signals (one entry buffer) + val buf_addr = WireInit(0.U(32.W)) // [31:0] + val buf_size = WireInit(0.U(2.W)) // [1:0] + val buf_write = WireInit(Bool(), init = false.B) + val buf_byteen = WireInit(0.U(8.W)) // [7:0] + val buf_aligned = WireInit(Bool(), init = false.B) + val buf_data = WireInit(0.U(64.W)) // [63:0] + val buf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] + //Miscellaneous signals + val buf_rst = WireInit(Bool(), init = false.B) + val buf_tag_in = WireInit(0.U(TAG.W)) // [TAG-1:0] + val buf_addr_in = WireInit(0.U(32.W)) // [31:0] + val buf_byteen_in = WireInit(0.U(8.W)) // [7:0] + val buf_data_in = WireInit(0.U(64.W)) // [63:0] + val buf_write_in = WireInit(Bool(), init = false.B) + val buf_aligned_in = WireInit(Bool(), init = false.B) + val buf_size_in = WireInit(0.U(3.W)) // [2:0] + + val buf_state_en = WireInit(Bool(), init = false.B) + val buf_wr_en = WireInit(Bool(), init = false.B) + val buf_data_wr_en = WireInit(Bool(), init = false.B) + val slvbuf_error_en = WireInit(Bool(), init = false.B) + val wr_cmd_vld = WireInit(Bool(), init = false.B) + + val cmd_done_rst = WireInit(Bool(), init = false.B) + val cmd_done = WireInit(Bool(), init = false.B) + val cmd_doneQ = WireInit(Bool(), init = false.B) + val trxn_done = WireInit(Bool(), init = false.B) + val buf_cmd_byte_ptr = WireInit(0.U(3.W)) // [2:0] + val buf_cmd_byte_ptrQ = WireInit(0.U(3.W)) // [2:0] + val buf_cmd_nxtbyte_ptr = WireInit(0.U(3.W)) // [2:0] + val buf_cmd_byte_ptr_en = WireInit(Bool(), init = false.B) + val found = WireInit(Bool(), init = false.B) + + val slave_valid_pre = WireInit(Bool(), init = false.B) + val ahb_hready_q = WireInit(Bool(), init = false.B) + val ahb_hresp_q = WireInit(Bool(), init = false.B) + val ahb_htrans_q = WireInit(0.U(2.W)) // [1:0] + val ahb_hwrite_q = WireInit(Bool(), init = false.B) + val ahb_hrdata_q = WireInit(0.U(64.W)) // [63:0] + + val slvbuf_write = WireInit(Bool(), init = false.B) + val slvbuf_error = WireInit(Bool(), init = false.B) + val slvbuf_tag = WireInit(0.U(TAG.W)) // [TAG-1:0] + + val slvbuf_error_in = WireInit(Bool(), init = false.B) + val slvbuf_wr_en = WireInit(Bool(), init = false.B) + val bypass_en = WireInit(Bool(), init = false.B) + val rd_bypass_idle = WireInit(Bool(), init = false.B) + + val last_addr_en = WireInit(Bool(), init = false.B) + val last_bus_addr = WireInit(0.U(32.W)) // [31:0] + // Clocks + val buf_clken = WireInit(Bool(), init = false.B) + val slvbuf_clken = WireInit(Bool(), init = false.B) + val ahbm_addr_clken = WireInit(Bool(), init = false.B) + val ahbm_data_clken = WireInit(Bool(), init = false.B) + val buf_clk = Wire(Clock()) + //val slvbuf_clk = Wire(Clock()) + val ahbm_clk = Wire(Clock()) + val ahbm_addr_clk = Wire(Clock()) + val ahbm_data_clk = Wire(Clock()) + + def get_write_size(byteen: UInt) = { + + val byteen = WireInit(0.U(8.W)) + + val size = ("b11".U & (Fill(2, (byteen(7, 0) === "hff".U))) | + ("b10".U & (Fill(2, (byteen(7, 0) === "hf0".U) | (byteen(7, 0) === "h0f".U)))) | + ("b01".U & (Fill(2, (byteen(7, 0) === "hc0".U) | (byteen(7, 0) === "h30".U) | (byteen(7, 0) === "h0c".U) | (byteen(7, 0) === "h03".U))))) + size + } + + def get_write_addr(byteen_e: UInt) = { + val byteen_e = WireInit(0.U(8.W)) + val addr = ("h0".U & (Fill(3, (byteen_e(7, 0) === "hff".U) | (byteen_e(7, 0) === "h0f".U) | (byteen_e(7, 0) === "h03".U))) | + ("h2".U & (Fill(3, (byteen_e(7, 0) === "h0c".U)))) | + ("h4".U & (Fill(3, ((byteen_e(7, 0) === "hf0".U) | (byteen_e(7, 0) === "h03".U)))) | + ("h6".U & (Fill(3, (byteen_e(7, 0) === "hc0".U)))))) + addr + } + + def get_nxtbyte_ptr(current_byte_ptr: UInt, byteen: UInt, get_next: Bool): UInt = { + val start_ptr = Mux(get_next, current_byte_ptr + 1.U, current_byte_ptr) + val temp = (0 until 8).map(j => (byteen(j) & (j.asUInt() >= start_ptr)) -> j.U) + MuxCase(0.U, temp) + } + + // Write buffer + wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready + wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready + wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) + wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en + + io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready + io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready + io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready + io.axi_rlast := true.B + + wr_cmd_vld := wrbuf_vld & wrbuf_data_vld + master_valid := wr_cmd_vld | io.axi_arvalid + master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi_arid(TAG - 1, 0)) + master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U) + master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi_araddr(31, 0)) + master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi_arsize(2, 0)) + master_byteen := wrbuf_byteen(7, 0) + master_wdata := wrbuf_data(63, 0) + + // AXI response channel signals + io.axi_bvalid := slave_valid & slave_ready & slave_opc(3) + io.axi_bresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) + io.axi_bid := slave_tag(TAG - 1, 0) + + io.axi_rvalid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U) + io.axi_rresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) + io.axi_rid := slave_tag(TAG - 1, 0) + io.axi_rdata := slave_rdata(63, 0) + slave_ready := io.axi_bready & io.axi_rready + + // Clock header logic + bus_write_clk_en := io.bus_clk_en & ((io.axi_awvalid & io.axi_awready) | (io.axi_wvalid & io.axi_wready)) + + bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) + bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode) + + //State machine + io.ahb_htrans := 0.U + master_ready := 0.U + buf_state_en := 0.U + switch(buf_state) { + is(idle) { + master_ready := 1.U + buf_write_in := (master_opc(2, 1) === "b01".U) + buf_nxtstate := Mux(buf_write_in.asBool(), cmd_wr, cmd_rd) + buf_state_en := master_valid & master_ready + buf_wr_en := buf_state_en + buf_data_wr_en := buf_state_en & (buf_nxtstate === cmd_wr) + buf_cmd_byte_ptr_en := buf_state_en + // ---------------------FROM FUNCTION CHECK LATER + buf_cmd_byte_ptr := Mux(buf_write_in.asBool(), (get_nxtbyte_ptr("b0".U, buf_byteen_in(7, 0), false.B)).asInstanceOf[UInt], master_addr(2, 0)) + bypass_en := buf_state_en + rd_bypass_idle := bypass_en & (buf_nxtstate === cmd_rd) + io.ahb_htrans := (Fill(2, bypass_en)) & "b10".U + } + + is(cmd_rd) { + buf_nxtstate := Mux((master_valid & (master_opc(2, 0) === "b000".U)).asBool(), stream_rd, data_rd) + buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q + cmd_done := buf_state_en & !master_valid + slvbuf_wr_en := buf_state_en + master_ready := (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q) & (buf_nxtstate === stream_rd) ////////////TBD//////// + buf_wr_en := master_ready + bypass_en := master_ready & master_valid + buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) + io.ahb_htrans := "b10".U & (Fill(2, (!buf_state_en | bypass_en))) + } + + is(stream_rd) { + master_ready := (ahb_hready_q & !ahb_hresp_q) & !(master_valid & master_opc(2, 1) === "b01".U) + buf_wr_en := (master_valid & master_ready & (master_opc(2, 0) === "b000".U)) // update the fifo if we are streaming the read commands + buf_nxtstate := Mux(ahb_hresp_q.asBool(), stream_err_rd, Mux(buf_wr_en.asBool(), stream_rd, data_rd)) // assuming that the master accpets the slave response right away. + buf_state_en := (ahb_hready_q | ahb_hresp_q) + buf_data_wr_en := buf_state_en + slvbuf_error_in := ahb_hresp_q + slvbuf_error_en := buf_state_en + slave_valid_pre := buf_state_en & !ahb_hresp_q // send a response right away if we are not going through an error response. + cmd_done := buf_state_en & !master_valid // last one of the stream should not send a htrans + bypass_en := master_ready & master_valid & (buf_nxtstate === stream_rd) & buf_state_en + buf_cmd_byte_ptr := Mux(bypass_en.asBool(), master_addr(2, 0), buf_addr(2, 0)) + io.ahb_htrans := "b10".U & Fill(2, (!((buf_nxtstate =/= stream_rd) & buf_state_en))) + slvbuf_wr_en := buf_wr_en // shifting the contents from the buf to slv_buf for streaming cases + } + + is(stream_err_rd) { + buf_nxtstate := data_rd + buf_state_en := ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & !ahb_hwrite_q + slave_valid_pre := buf_state_en + slvbuf_wr_en := buf_state_en // Overwrite slvbuf with buffer + buf_cmd_byte_ptr := buf_addr(2, 0) + io.ahb_htrans := "b10".U(2.W) & Fill(2, !buf_state_en) + } + + is(data_rd) { + buf_nxtstate := done + buf_state_en := (ahb_hready_q | ahb_hresp_q) + buf_data_wr_en := buf_state_en + slvbuf_error_in := ahb_hresp_q + slvbuf_error_en := buf_state_en + slvbuf_wr_en := buf_state_en + } + + is(cmd_wr) { + buf_nxtstate := data_wr + trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U) + buf_state_en := trxn_done + buf_cmd_byte_ptr_en := buf_state_en + slvbuf_wr_en := buf_state_en + buf_cmd_byte_ptr := Mux(trxn_done.asBool(), (get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)).asInstanceOf[UInt], buf_cmd_byte_ptrQ) + cmd_done := trxn_done & (buf_aligned | (buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U)) + io.ahb_htrans := Fill(2, !(cmd_done | cmd_doneQ)) & "b10".U + } + + is(data_wr) { + buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q + master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready //////////TBD///////// // Ready to accept new command if current command done and no error + buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U), cmd_wr, cmd_rd), idle)) + slvbuf_error_in := ahb_hresp_q + slvbuf_error_en := buf_state_en + buf_write_in := (master_opc(2, 1) === "b01".U) + buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd)) + buf_data_wr_en := buf_wr_en + cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen((get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B))) === "b0".U)))) + bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being + io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U + slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) + trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U) + buf_cmd_byte_ptr_en := trxn_done | bypass_en + //val tmp_func = get_nxtbyte_ptr(Fill(3,0.U),buf_byteen_in(7,0),false.B) + //val tmp_func2 = get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B) + buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(Fill(3, 0.U), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) + } + is(done) { + buf_nxtstate := idle + buf_state_en := slave_ready + slvbuf_error_en := true.B + slave_valid_pre := true.B + } + } + + buf_rst := false.B + cmd_done_rst := slave_valid_pre + buf_addr_in := Cat(master_addr, Mux((buf_aligned_in & (master_opc(2, 1) === "b01".U)).asBool(), get_write_addr(master_byteen(7, 0)), master_addr(2, 0))) + buf_tag_in := master_tag(TAG - 1, 0) + buf_byteen_in := wrbuf_byteen(7,0) + buf_data_in := Mux((buf_state === data_rd), ahb_hrdata_q(63, 0), master_wdata(63, 0)) + buf_size_in := Mux((buf_aligned_in & (master_size(1, 0) === "b11".U) & (master_opc(2, 1) === "b01".U)).asBool(), get_write_size(master_byteen(7, 0)), master_size(1, 0)) + buf_aligned_in := (master_opc(2, 0) === "b0".U) | // reads are always aligned since they are either DW or sideeffects + (master_size(1, 0) === "b0".U) | (master_size(1, 0) === "b01".U) | (master_size(1, 0) === "b10".U) | // Always aligned for Byte/HW/Word since they can be only for non-idempotent. IFU/SB are always aligned + ((master_size(1, 0) === "b11".U) & ((master_byteen(7, 0) === "h3".U) | (master_byteen(7, 0) === "hc".U) | (master_byteen(7, 0) === "h30".U) | (master_byteen(7, 0) === "hc0".U) | + (master_byteen(7, 0) === "hf".U) | (master_byteen(7, 0) === "hf0".U) | (master_byteen(7, 0) === "hff".U))) + // Generate the ahb signals + io.ahb_haddr := Mux(bypass_en.asBool(), Cat(master_addr(31, 3), buf_cmd_byte_ptr(2, 0)), Cat(buf_addr(31, 3), buf_cmd_byte_ptr(2, 0))) + io.ahb_hsize := Mux(bypass_en.asBool(), Cat("b0".U, (Fill(2, buf_aligned_in) & buf_size_in(1, 0))), (Cat("b0".U, (Fill(2, buf_aligned) & buf_size(1, 0))))) + + io.ahb_hburst := "b0".U + io.ahb_hmastlock := "b0".U + io.ahb_hprot := Cat("b001".U, ~io.axi_arprot(2)) + io.ahb_hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) + io.ahb_hwdata := buf_data(63, 0) + + slave_valid := slave_valid_pre + slave_opc := Cat(Mux(slvbuf_write.asBool(), "b11".U, "b00".U), Fill(2, slvbuf_error) & "b10".U) + slave_rdata := Mux(slvbuf_error.asBool(), Fill(2, last_bus_addr(31, 0)), Mux((buf_state === done), buf_data(63, 0), ahb_hrdata_q(63, 0))) + slave_tag := slvbuf_tag(TAG - 1, 0) + + last_addr_en := (io.ahb_htrans(1, 0) =/= "b0".U) & io.ahb_hready & io.ahb_hwrite + + //rvdffsc + wrbuf_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_en.asBool())} + wrbuf_data_vld := withClock(bus_clk) {RegEnable("b1".U & Fill("b1".U.getWidth, wrbuf_rst), 0.U, wrbuf_data_en.asBool())} + //rvdffs + wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())} + wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())} + //rvdffe + wrbuf_addr := RegEnable(io.axi_awaddr, 0.U, wrbuf_en.asBool()) + wrbuf_data := RegEnable(io.axi_wdata, 0.U, wrbuf_data_en.asBool()) + //rvdffs + wrbuf_byteen := withClock(bus_clk) { + RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool()) + } + last_bus_addr := withClock(ahbm_clk) { + RegEnable(io.ahb_haddr(31, 0), 0.U, last_addr_en.asBool()) + } + //sc + buf_state := withClock(ahbm_clk) { + RegEnable(buf_nxtstate & Fill(buf_nxtstate.getWidth, buf_rst), 0.U, buf_state_en.asBool()) + } + //s + buf_write := withClock(buf_clk) { + RegEnable(buf_write_in, 0.U, buf_wr_en.asBool()) + } + buf_tag := withClock(buf_clk) { + RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool()) + } + //e + buf_addr := RegEnable(buf_addr_in(31, 0), 0.U, (buf_wr_en & io.bus_clk_en).asBool) + //s + buf_size := withClock(buf_clk) { + RegEnable(buf_size(1, 0), 0.U, buf_wr_en.asBool()) + } + buf_aligned := withClock(buf_clk) { + RegEnable(buf_aligned_in, 0.U, buf_wr_en.asBool()) + } + buf_byteen := withClock(buf_clk) { + RegEnable(buf_byteen(7, 0), 0.U, buf_wr_en.asBool()) + } + //e + buf_data := RegEnable(buf_data_in(63, 0), 0.U, (buf_data_wr_en & io.bus_clk_en).asBool()) + //s + slvbuf_write := withClock(buf_clk) { + RegEnable(buf_write, 0.U, slvbuf_wr_en.asBool()) + } + slvbuf_tag := withClock(buf_clk) { + RegEnable(buf_tag(TAG - 1, 0), 0.U, slvbuf_wr_en.asBool()) + } + slvbuf_error := withClock(ahbm_clk) { + RegEnable(slvbuf_error_in, 0.U, slvbuf_error_en.asBool()) + } + //sc + cmd_doneQ := withClock(ahbm_clk) { + RegEnable("b1".U & Fill("b1".U.getWidth, cmd_done_rst), 0.U, cmd_done.asBool()) + } + //rvdffs + buf_cmd_byte_ptrQ := withClock(ahbm_clk) { + RegEnable(buf_cmd_byte_ptr(2, 0), 0.U, buf_cmd_byte_ptr_en.asBool()) + } + + //rvdff + ahb_hready_q := withClock(ahbm_clk) { + RegNext(io.ahb_hready, 0.U) + } + ahb_htrans_q := withClock(ahbm_clk) { + RegNext(io.ahb_htrans(1, 0), 0.U) + } + ahb_hwrite_q := withClock(ahbm_addr_clk) { + RegNext(io.ahb_hwrite, 0.U) + } + ahb_hresp_q := withClock(ahbm_clk) { + RegNext(io.ahb_hresp, 0.U) + } + ahb_hrdata_q := withClock(ahbm_data_clk) { + RegNext(io.ahb_hrdata(63, 0), 0.U) + } + + buf_clken := io.bus_clk_en & (buf_wr_en | slvbuf_wr_en | io.clk_override) + ahbm_addr_clken := io.bus_clk_en & ((io.ahb_hready & io.ahb_htrans(1)) | io.clk_override) + ahbm_data_clken := io.bus_clk_en & ((buf_state =/= idle) | io.clk_override) + + //Clkhdr + buf_clk := rvclkhdr(clock, buf_clken, io.scan_mode) + ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) + ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) + ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) +} + +object AXImain extends App { + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new axi4_to_ahb())) +} \ No newline at end of file diff --git a/src/main/scala/lib/beh_ib_func.scala b/src/main/scala/lib/beh_ib_func.scala deleted file mode 100644 index f4679842..00000000 --- a/src/main/scala/lib/beh_ib_func.scala +++ /dev/null @@ -1,217 +0,0 @@ -package lib -import chisel3._ -import chisel3.util._ -import chisel3.iotesters.{ChiselFlatSpec, Driver, PeekPokeTester} -import chisel3.experimental._ -import chisel3.util.HasBlackBoxResource -import chisel3.withClock -/* -object beh_ib_func extends RequireAsyncReset { - - def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) - - def rvsyncss(din:UInt,clk:Clock) = withClock(clk){RegNext(RegNext(din,0.U),0.U)} - - def rvlsadder(rs1:UInt,offset:UInt) = { - val w1 = Cat(0.U(1.W),rs1(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[11]=sign - val dout_upper = ((Fill(20, ~(offset(11) ^ w1(12)))) & rs1(31,12)) | - ((Fill(20, ~offset(11) & w1(12))) & (rs1(31,12)+1.U)) | - ((Fill(20, offset(11) & ~w1(12))) & (rs1(31,12)-1.U)) - Cat(dout_upper,w1(11,0)) - } - - def rvbradder(pc:UInt,offset:UInt) = { // lsb is not using in code - val w1 = Cat(0.U(1.W),pc(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[12]=sign - val dout_upper = ((Fill(19, ~(offset(11) ^ w1(12))))& pc(30,12)) | - ((Fill(19, ~offset(11) & w1(12))) & (pc(30,12)+1.U)) | - ((Fill(19, offset(11) & ~w1(12))) & (pc(30,12)-1.U)) - Cat(dout_upper,w1(11,0))} - - def rvtwoscomp(din:UInt) = { //Done for verification and testing - val temp = Wire(Vec(din.getWidth-1,UInt(1.W))) - for(i <- 1 to din.getWidth-1){ - temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i)) - } - Cat(temp.asUInt,din(0)) - } - - - //WIDTH will be inferred - def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing - val matchvec = Wire(Vec(data.getWidth,UInt(1.W))) - val masken_or_fullmask = masken.asBool & (~(mask(data.getWidth-1,0).andR)) - matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt - for(i <- 1 to data.getWidth-1) - {matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)} - matchvec.asUInt.andR - } - - - def rvrangecheck(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = { - val REGION_BITS = 4 - val MASK_BITS = 10 + log2Ceil(CCM_SIZE) - val start_addr = CCM_SADR - val region = start_addr(31,(32-REGION_BITS)) - val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt - val in_range = Wire(UInt(1.W)) - if(CCM_SIZE == 48) - in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt) - else - in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt - (in_range,in_region) - } - - - def rvecc_encode(din:UInt):UInt = { - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) - val w0 = Wire(Vec(18,UInt(1.W))) - val w1 = Wire(Vec(18,UInt(1.W))) - val w2 = Wire(Vec(18,UInt(1.W))) - val w3 = Wire(Vec(15,UInt(1.W))) - val w4 = Wire(Vec(15,UInt(1.W))) - val w5 = Wire(Vec(6, UInt(1.W))) - var j = 0;var k = 0;var m = 0; - var x = 0;var y = 0;var z = 0 - for(i <- 0 to 31) - { - if(mask0(i)==1) {w0(j) := din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := din(i); m = m +1 } - if(mask3(i)==1) {w3(x) := din(i); x = x +1 } - if(mask4(i)==1) {w4(y) := din(i); y = y +1 } - if(mask5(i)==1) {w5(z) := din(i); z = z +1 } - } - val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) - val ecc_out = Cat(din.xorR ^ w6.xorR, w6) - ecc_out - } - - - def rveven_paritygen(data_in:UInt):UInt = data_in.xorR.asUInt - def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in - - def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= { - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) - - val w0 = Wire(Vec(18,UInt(1.W))) - val w1 = Wire(Vec(18,UInt(1.W))) - val w2 = Wire(Vec(18,UInt(1.W))) - val w3 = Wire(Vec(15,UInt(1.W))) - val w4 = Wire(Vec(15,UInt(1.W))) - val w5 = Wire(Vec(6,UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0; - - for(i <- 0 to 31) - { - if(mask0(i)==1) {w0(j) := din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := din(i); y = y +1 } - } - - val ecc_check = Cat((din.xorR ^ ecc_in.xorR) & ~sed_ded ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR)) - val single_ecc_error = en & (ecc_check=/= 0.U) & ecc_check(6) - val double_ecc_error = en & (ecc_check=/= 0.U) & ~ecc_check(6) - val error_mask = Wire(Vec(39,UInt(1.W))) - - for(i <- 1 until 40){ - error_mask(i-1) := ecc_check(5,0) === i.asUInt - } - val din_plus_parity = Cat(ecc_in(6), din(31,26), ecc_in(5), din(25,11), ecc_in(4), din(10,4), ecc_in(3), din(3,1), ecc_in(2), din(0), ecc_in(1,0)) - val dout_plus_parity = Mux(single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity) - - val dout = Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) - val ecc_out = Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) - (ecc_out,dout,single_ecc_error,double_ecc_error) - } - - - def rvecc_encode_64(din:UInt):UInt = { - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) - - - val w0 = Wire(Vec(35,UInt(1.W))) - val w1 = Wire(Vec(35,UInt(1.W))) - val w2 = Wire(Vec(35,UInt(1.W))) - val w3 = Wire(Vec(31,UInt(1.W))) - val w4 = Wire(Vec(31,UInt(1.W))) - val w5 = Wire(Vec(31,UInt(1.W))) - val w6 = Wire(Vec(7, UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0;var z = 0 - - for(i <- 0 to 63) - { - if(mask0(i)==1) {w0(j) := din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := din(i); y = y +1 } - if(mask6(i)==1) {w6(z) := din(i); z = z +1 } - } - val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR)) - ecc_out - } - - - def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = { - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) - val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) - - val w0 = Wire(Vec(35,UInt(1.W))) - val w1 = Wire(Vec(35,UInt(1.W))) - val w2 = Wire(Vec(35,UInt(1.W))) - val w3 = Wire(Vec(31,UInt(1.W))) - val w4 = Wire(Vec(31,UInt(1.W))) - val w5 = Wire(Vec(31,UInt(1.W))) - val w6 = Wire(Vec(7, UInt(1.W))) - - var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0;var z = 0 - - for(i <- 0 to 63) - { - if(mask0(i)==1) {w0(j) := din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := din(i); m = m +1 } - if(mask3(i)==1) {w3(n) := din(i); n = n +1 } - if(mask4(i)==1) {w4(x) := din(i); x = x +1 } - if(mask5(i)==1) {w5(y) := din(i); y = y +1 } - if(mask6(i)==1) {w6(z) := din(i); z = z +1 } - } - - val ecc_check = Cat((ecc_in(6) ^ w6.asUInt.xorR) ,ecc_in(5)^(w5.asUInt.xorR),ecc_in(4)^(w4.asUInt.xorR),ecc_in(3)^(w3.asUInt.xorR),ecc_in(2)^(w2.asUInt.xorR),ecc_in(1)^(w1.asUInt.xorR),ecc_in(0)^(w0.asUInt.xorR)) - val ecc_error = en & (ecc_check(6,0) =/= 0.U) - ecc_error - } -} - -*/ - diff --git a/src/main/scala/lib/beh_lib.scala b/src/main/scala/lib/beh_lib.scala index bd59eb8b..5f8d6419 100644 --- a/src/main/scala/lib/beh_lib.scala +++ b/src/main/scala/lib/beh_lib.scala @@ -2,9 +2,7 @@ package lib import chisel3._ import chisel3.util._ -import include._ -//import lib.beh_ib_func._ class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{ val io = IO(new Bundle{ @@ -19,69 +17,95 @@ class rvdff(WIDTH:Int=1,SHORT:Int=0) extends Module{ else {io.dout := flop} } -//println(getVerilog(new rvdff)) -//rvdff => use regnext. with Asynchronous +class rvdffsc extends Module with el2_lib { + val io = IO(new Bundle{ + val din = Input(UInt(32.W)) + val en = Input(Bool()) + val clear = Input(Bool()) + val out = Output(UInt()) + }) + io.out := RegEnable(io.din & Fill(io.din.getWidth, ~io.clear), 0.U, io.en) +} -class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module{ //Done for verification and testing +class rvdffs extends Module with el2_lib { + val io = IO(new Bundle{ + val din = Input(UInt(32.W)) + val en = Input(Bool()) + val clear = Input(Bool()) + val out = Output(UInt()) + }) + io.out := RegEnable(io.din, 0.U, io.en) +} + +class rvsyncss(WIDTH:Int = 251,SHORT:Int = 0) extends Module with RequireAsyncReset{ //Done for verification and testing val io = IO(new Bundle{ val din = Input(UInt(WIDTH.W)) val dout = Output(UInt(WIDTH.W)) - val clk = Input(Clock()) }) - val sync_ff1 = withClock(io.clk){RegNext(io.din,0.U)} //RegNext(io.in,init) - val sync_ff2 = withClock(io.clk){RegNext(sync_ff1,0.U)} + val sync_ff1 = RegNext(io.din,0.U) //RegNext(io.in,init) + val sync_ff2 = RegNext(sync_ff1,0.U) if(SHORT == 1) - {io.dout := io.din } + { io.dout := io.din } else - {io.dout := sync_ff2 } + { io.dout := sync_ff2 } } - - - class rvlsadder extends Module{ //Done for verification and testing val io = IO(new Bundle{ val rs1 = Input(UInt(32.W)) val offset = Input(UInt(12.W)) val dout = Output(UInt(32.W)) }) - val w1 = Cat(0.U(1.W),io.rs1(11,0)) + Cat(0.U(1.W),io.offset(11,0)) //w1[12] =cout offset[11]=sign + val w1 = Cat("b0".U,io.rs1(11,0)) + Cat("b0".U,io.offset(11,0)) //w1[12] =cout offset[11]=sign val dout_upper = ((Fill(20, ~(io.offset(11) ^ w1(12)))) & io.rs1(31,12)) | - ((Fill(20, ~io.offset(11) & w1(12))) & (io.rs1(31,12)+1.U)) | - ((Fill(20, io.offset(11) & ~w1(12))) & (io.rs1(31,12)-1.U)) + ((Fill(20, ~io.offset(11) ^ w1(12))) & (io.rs1(31,12)+1.U)) | + ((Fill(20, io.offset(11) ^ ~w1(12))) & (io.rs1(31,12)-1.U)) io.dout := Cat(dout_upper,w1(11,0)) } -class rvbradder extends Module{ //Done for verification and testing + + + +class rvbsadder extends Module{ //Done for verification and testing val io = IO(new Bundle{ - val pc = Input(UInt(31.W)) // 31:1 => 30:0 - val offset = Input(UInt(12.W)) // 12:1 => 11:0 - val dout = Output(UInt(31.W)) // 31:1 => 30:0 + val pc = Input(UInt(32.W)) // lsb is not using in code + val offset = Input(UInt(13.W)) // lsb is not using in code + val dout = Output(UInt(31.W)) }) - val w1 = Cat(0.U(1.W),io.pc(11,0)) + Cat(0.U(1.W),io.offset(11,0)) //w1[12] =cout offset[12]=sign - val dout_upper = ((Fill(19, ~(io.offset(11) ^ w1(12))))& io.pc(30,12)) | - ((Fill(19, ~io.offset(11) & w1(12))) & (io.pc(30,12)+1.U)) | - ((Fill(19, io.offset(11) & ~w1(12))) & (io.pc(30,12)-1.U)) + val w1 = Cat("b0".U,io.pc(12,1)) + Cat("b0".U,io.offset(12,1)) //w1[12] =cout offset[12]=sign + + val dout_upper = ((Fill(19, ~(io.offset(12) ^ w1(12))))& io.pc(31,13)) | + ((Fill(19, ~io.offset(12) ^ w1(12))) & (io.pc(31,13)+1.U)) | + ((Fill(19, io.offset(12) ^ ~w1(12))) & (io.pc(31,13)-1.U)) io.dout := Cat(dout_upper,w1(11,0)) } + + class rvtwoscomp(WIDTH:Int=32) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val din = Input(UInt(WIDTH.W)) val dout = Output(UInt(WIDTH.W)) }) + + val temp = Wire(Vec(WIDTH-1,UInt(1.W))) + val i:Int = 1 + for(i <- 1 to WIDTH-1){ - temp(i-1) := Mux(io.din(i-1,0).orR ,~io.din(i),io.din(i))} + val done = io.din(i-1,0).orR + temp(i-1) := Mux(done ,~io.din(i),io.din(i)) + } io.dout := Cat(temp.asUInt,io.din(0)) } + class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val mask = Input(UInt(WIDTH.W)) @@ -91,16 +115,19 @@ class rvmaskandmatch(WIDTH:Int=32) extends Module{ //Done for verification a }) val matchvec = Wire(Vec(WIDTH,UInt(1.W))) - val masken_or_fullmask = io.masken.asBool & (~(io.mask(WIDTH-1,0).andR)) + val masken_or_fullmask = io.masken.asBool & ~io.mask(WIDTH-1,0).andR matchvec(0) := masken_or_fullmask | (io.mask(0) === io.data(0)).asUInt for(i <- 1 to WIDTH-1) {matchvec(i) := Mux(io.mask(i-1,0).andR & masken_or_fullmask,"b1".U,(io.mask(i) === io.data(i)).asUInt)} - io.match_out := matchvec.asUInt.andR -}//ewrfdxgh + io.match_out := matchvec.asUInt +} -class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{ + + + +class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{ val io = IO(new Bundle{ val addr = Input(UInt(32.W)) val in_range = Output(UInt(1.W)) @@ -108,7 +135,9 @@ class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{ }) val REGION_BITS = 4 val MASK_BITS = 10 + log2Ceil(CCM_SIZE) - val start_addr = CCM_SADR + + val start_addr = Wire(UInt(32.W)) + start_addr := CCM_SIZE.U val region = start_addr(31,(32-REGION_BITS)) io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt @@ -118,14 +147,19 @@ class rvrangecheck_ch(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{ io.in_range := (io.addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt } + + +// DONE class rveven_paritygen(WIDTH:Int= 16) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val data_in = Input (UInt(WIDTH.W)) val parity_out = Output(UInt(1.W)) }) io.parity_out := io.data_in.xorR.asUInt -} +} // DONE + +// DONE class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verification and testing val io = IO(new Bundle{ val data_in = Input (UInt(WIDTH.W)) @@ -133,20 +167,21 @@ class rveven_paritycheck(WIDTH:Int= 16) extends Module{ //Done for verificati val parity_err = Output(UInt(1.W)) }) io.parity_err := (io.data_in.xorR.asUInt) ^ io.parity_in -} +} // DONE + + class rvecc_encode extends Module{ //Done for verification and testing val io = IO(new Bundle{ val din = Input(UInt(32.W)) val ecc_out = Output(UInt(7.W)) }) - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) - val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) - val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) - val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) - val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) - + val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1) + val mask1 = Array(1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,1,1,0,1) + val mask2 = Array(1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,0) + val mask3 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,0,0,0,0) + val mask4 = Array(0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0) + val mask5 = Array(1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0) val w0 = Wire(Vec(18,UInt(1.W))) val w1 = Wire(Vec(18,UInt(1.W))) val w2 = Wire(Vec(18,UInt(1.W))) @@ -154,7 +189,7 @@ class rvecc_encode extends Module{ //Done for verification and testing val w4 = Wire(Vec(15,UInt(1.W))) val w5 = Wire(Vec(6, UInt(1.W))) var j = 0;var k = 0;var m = 0; - var x = 0;var y = 0;var z = 0; + var x = 0;var y = 0;var z = 0 for(i <- 0 to 31) { @@ -165,12 +200,12 @@ class rvecc_encode extends Module{ //Done for verification and testing if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 } if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 } } - val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) + val w6 = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR)) io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6) } - +// Make generator and then make it a method class rvecc_decode extends Module{ //Done for verification and testing val io = IO(new Bundle{ val en = Input(UInt(1.W)) @@ -182,7 +217,6 @@ class rvecc_decode extends Module{ //Done for verification and testing val single_ecc_error = Output(UInt(1.W)) val double_ecc_error = Output(UInt(1.W)) }) - val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) @@ -211,10 +245,10 @@ class rvecc_decode extends Module{ //Done for verification and testing } val ecc_check = Cat((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) + io.ecc_out := ecc_check - - io.single_ecc_error := io.en & (ecc_check =/= 0.U(7.W)) & ecc_check(6) - io.double_ecc_error := io.en & (ecc_check =/= 0.U(7.W)) & ~ecc_check(6) + io.single_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) + io.double_ecc_error := io.en & (ecc_check!= 0.U) & ((io.din.xorR ^ io.ecc_in.xorR) & ~io.sed_ded) val error_mask = Wire(Vec(39,UInt(1.W))) for(i <- 1 until 40){ @@ -224,11 +258,14 @@ class rvecc_decode extends Module{ //Done for verification and testing val dout_plus_parity = Mux(io.single_ecc_error.asBool, (error_mask.asUInt ^ din_plus_parity), din_plus_parity) io.dout := Cat(dout_plus_parity(37,32),dout_plus_parity(30,16), dout_plus_parity(14,8), dout_plus_parity(6,4), dout_plus_parity(2)) - io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U(7.W)), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) + io.ecc_out := Cat(dout_plus_parity(38) ^ (ecc_check(6,0) === "b1000000".U), dout_plus_parity(31), dout_plus_parity(15), dout_plus_parity(7), dout_plus_parity(3), dout_plus_parity(1,0)) } + + + class rvecc_encode_64 extends Module{ //Done for verification and testing val io = IO(new Bundle{ val din = Input(UInt(64.W)) @@ -263,9 +300,13 @@ class rvecc_encode_64 extends Module{ //Done for verification and testing if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 } } - io.ecc_out := Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) + io.ecc_out := Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR)) } + + + + class rvecc_decode_64 extends Module{ //Done for verification and testing val io = IO(new Bundle{ val en = Input(UInt(1.W)) @@ -290,7 +331,7 @@ class rvecc_decode_64 extends Module{ //Done for verification and testing val w6 = Wire(Vec(7, UInt(1.W))) var j = 0;var k = 0;var m = 0; var n =0; - var x = 0;var y = 0;var z = 0; + var x = 0;var y = 0;var z = 0 for(i <- 0 to 63) { @@ -303,110 +344,16 @@ class rvecc_decode_64 extends Module{ //Done for verification and testing if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 } } - val ecc_check = Cat((io.ecc_in(6) ^ w6.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) - io.ecc_error := io.en & (ecc_check(6,0) =/= 0.U(7.W)) -} + val ecc_check = Cat((io.ecc_in(6) ^ w5.asUInt.xorR) ,io.ecc_in(5)^(w5.asUInt.xorR),io.ecc_in(4)^(w4.asUInt.xorR),io.ecc_in(3)^(w3.asUInt.xorR),io.ecc_in(2)^(w2.asUInt.xorR),io.ecc_in(1)^(w1.asUInt.xorR),io.ecc_in(0)^(w0.asUInt.xorR)) + io.ecc_error := io.en & (ecc_check(6,0) != 0.U) - - - -////////////////////////////TEC_RV_ICG//////////////////////// -class TEC_RV_ICG extends BlackBox with HasBlackBoxResource { - val io = IO(new Bundle { - val Q = Output(Clock()) - val CK = Input(Clock()) - val EN = Input(Bool()) - val SE = Input(Bool()) - }) - addResource("/vsrc/TEC_RV_ICG.v") -} - -class rvclkhdr extends Module { - val io = IO(new Bundle { - val l1clk = Output(Clock()) - val clk = Input(Clock()) - val en = Input(Bool()) - val scan_mode = Input(Bool()) - }) - val clkhdr = { Module(new TEC_RV_ICG) } - io.l1clk := clkhdr.io.Q - clkhdr.io.CK := io.clk - clkhdr.io.EN := io.en - clkhdr.io.SE := io.scan_mode -} - -object rvclkhdr { - def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = { - val cg = Module(new rvclkhdr) - cg.io.clk := clk - cg.io.en := en - cg.io.scan_mode := scan_mode - cg.io.l1clk - } -} - -////rvdffe /////////////////////////////////////////////////////////////////////// -object rvdffe { - def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = { - val obj = Module(new rvclkhdr()) - val l1clk = obj.io.l1clk - obj.io.clk := clk - obj.io.en := en - obj.io.scan_mode := scan_mode - withClock(l1clk) { - RegNext(din, 0.U) - } - } - def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = { - val obj = Module(new rvclkhdr()) - val l1clk = obj.io.l1clk - obj.io.clk := clk - obj.io.en := en - obj.io.scan_mode := scan_mode - withClock(l1clk) { - RegNext(din,0.U.asTypeOf(din.cloneType)) - } - } - def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = { - val obj = Module(new rvclkhdr()) - val l1clk = obj.io.l1clk - obj.io.clk := clk - obj.io.en := en - obj.io.scan_mode := scan_mode - withClock(l1clk) { - RegNext(din, 0.S) - } + object rvsyncss { + def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} } } -/////////////rvdffe ////////////////////////// -/* -class class_rvdffe extends Module with RequireAsyncReset{ - val io = IO(new Bundle { - val lsu_pkt_d = Input(new el2_load_cam_pkt_t) - val lsu_pkt_m = Output(new el2_load_cam_pkt_t) - val clk = Input(Clock()) - val en = Input(Bool()) - val scan_mode = Input(Bool()) - }) - io.lsu_pkt_m := rvdffe(io.lsu_pkt_d,io.en.asBool,io.clk,io.scan_mode.asBool) -} - - -object main extends App{ - println("Generate Verilog") - chisel3.Driver.execute(args, ()=> new class_rvdffe) -}*/ - - - - - - - - diff --git a/src/main/scala/lib/el2_lib.scala b/src/main/scala/lib/el2_lib.scala index d86e077a..083c9549 100644 --- a/src/main/scala/lib/el2_lib.scala +++ b/src/main/scala/lib/el2_lib.scala @@ -1,5 +1,4 @@ package lib - import chisel3._ import chisel3.util._ trait param { @@ -26,30 +25,30 @@ trait param { val BUILD_AXI4 = true val BUILD_AXI_NATIVE = true val BUS_PRTY_DEFAULT = 3 - val DATA_ACCESS_ADDR0 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W) - val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W) - val DATA_ACCESS_ADDR3 = "h80000000".U(32.W) - val DATA_ACCESS_ADDR4 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR5 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR6 = "h00000000".U(32.W) - val DATA_ACCESS_ADDR7 = "h00000000".U(32.W) - val DATA_ACCESS_ENABLE0 = "h1".U(1.W) - val DATA_ACCESS_ENABLE1 = "h1".U(1.W) - val DATA_ACCESS_ENABLE2 = "h1".U(1.W) - val DATA_ACCESS_ENABLE3 = "h1".U(1.W) - val DATA_ACCESS_ENABLE4 = "h0".U(1.W) - val DATA_ACCESS_ENABLE5 = "h0".U(1.W) - val DATA_ACCESS_ENABLE6 = "h0".U(1.W) - val DATA_ACCESS_ENABLE7 = "h0".U(1.W) - val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W) - val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W) - val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W) - val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W) - val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W) - val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W) + val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W) + val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W) + val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W) + val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W) + val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W) + val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W) + val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W) + val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W) + val DATA_ACCESS_ENABLE0 = true //.U(1.W) + val DATA_ACCESS_ENABLE1 = true //.U(1.W) + val DATA_ACCESS_ENABLE2 = true //.U(1.W) + val DATA_ACCESS_ENABLE3 = true //.U(1.W) + val DATA_ACCESS_ENABLE4 = false //.U(1.W) + val DATA_ACCESS_ENABLE5 = false //.U(1.W) + val DATA_ACCESS_ENABLE6 = false //.U(1.W) + val DATA_ACCESS_ENABLE7 = false //.U(1.W) + val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) + val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) + val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) + val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W) + val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W) + val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) + val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) + val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) val DCCM_BANK_BITS = 2 //.U(3.W) val DCCM_BITS = 16 //.U(5.W) val DCCM_BYTE_WIDTH = 4 //.U(3.W) @@ -59,8 +58,8 @@ trait param { val DCCM_FDATA_WIDTH = 0x27 //.U(6.W) val DCCM_INDEX_BITS = 0xC //.U(4.W) val DCCM_NUM_BANKS = 0x04 //.U(5.W) - val DCCM_REGION = 15 - val DCCM_SADR = "hF0040000".U(32.W) + val DCCM_REGION = 15 //.U(4.W) + val DCCM_SADR = 0xF0040000 val DCCM_SIZE = 0x040 val DCCM_WIDTH_BITS = 2 //.U(2.W) val DMA_BUF_DEPTH = 5 //.U(3.W) @@ -102,9 +101,9 @@ trait param { val ICCM_ICACHE = true //.U(1.W) val ICCM_INDEX_BITS = 0xC //.U(4.W) val ICCM_NUM_BANKS = 0x04 //.U(5.W) - val ICCM_ONLY = 0x0 //.U(1.W) - val ICCM_REGION = 0xE //.U(4.W) - val ICCM_SADR = 0xEE000000L //.U(32.W) + val ICCM_ONLY = false //.U(1.W) + val ICCM_REGION = 0xE //.U(4.W) + val ICCM_SADR = 0xEE000000 //.U(32.W) val ICCM_SIZE = 0x040 //.U(10.W) val IFU_BUS_ID = 0x1 //.U(1.W) val IFU_BUS_PRTY = 0x2 //.U(2.W) @@ -142,13 +141,13 @@ trait param { val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W) val LSU_SB_BITS = 0x10 //.U(5.W) val LSU_STBUF_DEPTH = 0x4 //.U(4.W) - val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W) + val NO_ICCM_NO_ICACHE = false //.U(1.W) val PIC_2CYCLE = 0x0 //.U(1.W) - val PIC_BASE_ADDR = "hF00C0000".U(32.W) + val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W) val PIC_BITS = 0x0F //.U(5.W) val PIC_INT_WORDS = 0x1 //.U(4.W) - val PIC_REGION = 0xF - val PIC_SIZE = 0x020//.U(9.W) + val PIC_REGION = 0xF //.U(4.W) + val PIC_SIZE = 0x020 //.U(9.W) val PIC_TOTAL_INT = 0x1F //.U(8.W) val PIC_TOTAL_INT_PLUS1 = 0x020 //.U(9.W) val RET_STACK_SIZE = 0x8 //.U(4.W) @@ -159,37 +158,75 @@ trait param { } trait el2_lib extends param{ - // Configuration Methods - def MEM_CAL : (Int, Int, Int)= + def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) + + def MEM_CAL : (Int, Int, Int, Int)= (ICACHE_WAYPACK, ICACHE_ECC) match{ - case(false,false) => (68,22, 68) - case(false,true) => (71,26, 71) - case(true,false) => (68*ICACHE_NUM_WAYS,22*ICACHE_NUM_WAYS, 68) - case(true,true) => (71*ICACHE_NUM_WAYS,26*ICACHE_NUM_WAYS, 71) + case(false,false) => (68, 22, 68, 22) + case(false,true) => (71, 26, 71, 26) + case(true,false) => (68*ICACHE_NUM_WAYS, 22*ICACHE_NUM_WAYS, 68, 22) + case(true,true) => (71*ICACHE_NUM_WAYS, 26*ICACHE_NUM_WAYS, 71, 26) } val DATA_MEM_LINE = MEM_CAL + val Tag_Word = MEM_CAL._4 + implicit def bool2int(b:Boolean) = if (b) 1 else 0 + implicit def aslong(b:Int) = 0xFFFFFFFFL & b + object rvsyncss { + def apply(din:UInt,clk:Clock) =withClock(clk){RegNext(withClock(clk){RegNext(din,0.U)},0.U)} + } + + + /////////////////////////////////////////////////////////////////// def el2_btb_tag_hash(pc : UInt) = - VecInit.tabulate(3)(i => pc(BTB_ADDR_HI+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE)+1)).reduce(_^_) + VecInit.tabulate(3)(i => pc(BTB_ADDR_HI-1+((i+1)*(BTB_BTAG_SIZE)),BTB_ADDR_HI+(i*BTB_BTAG_SIZE))).reduce(_^_) + /////////////////////////////////////////////////////////////////// def el2_btb_tag_hash_fold(pc : UInt) = pc(BTB_ADDR_HI+(2*BTB_BTAG_SIZE),BTB_ADDR_HI+BTB_BTAG_SIZE+1)^pc(BTB_ADDR_HI+BTB_BTAG_SIZE,BTB_ADDR_HI+1) + /////////////////////////////////////////////////////////////////// def el2_btb_addr_hash(pc : UInt) = - if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO) - else pc(BTB_INDEX1_HI,BTB_INDEX1_LO) ^ pc(BTB_INDEX2_HI,BTB_INDEX2_LO) ^ pc(BTB_INDEX3_HI,BTB_INDEX3_LO) + if(BTB_FOLD2_INDEX_HASH) pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1) + else (pc(BTB_INDEX1_HI-1,BTB_INDEX1_LO-1) ^ pc(BTB_INDEX2_HI-1,BTB_INDEX2_LO-1) ^ pc(BTB_INDEX3_HI-1,BTB_INDEX3_LO-1)) + /////////////////////////////////////////////////////////////////// def el2_btb_ghr_hash(hashin : UInt, ghr :UInt) = if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0)) else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0) - def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_)) + /////////////////////////////////////////////////////////////////// + def rveven_paritycheck(data_in:UInt, parity_in:UInt) : UInt = + (data_in.xorR.asUInt) ^ parity_in - def Mux1H_LM(a:Seq[Bool], b:Seq[UInt]) = (0 until b.size).map(i=> repl(b(i).getWidth,a(i)) & b(i)).reduce(_|_) + /////////////////////////////////////////////////////////////////// + def rveven_paritygen(data_in : UInt) = + data_in.xorR.asUInt + /////////////////////////////////////////////////////////////////// + //rvbradder(Cat(pc, 0.U), Cat(offset, 0.U)) + def rvbradder (pc:UInt, offset:UInt) = { + val dout_lower = pc(12,1) +& offset(12,1) + val pc_inc = pc(31,13)+1.U + val pc_dec = pc(31,13)-1.U + val sign = offset(12) + Cat(Mux1H(Seq(( sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13), + (!sign & dout_lower(dout_lower.getWidth-1)).asBool -> pc_inc, + ( sign & !dout_lower(dout_lower.getWidth-1)).asBool -> pc_dec)), dout_lower(11,0), 0.U) + } - - - def rvsyncss(din:UInt,clk:Clock) = withClock(clk){RegNext(RegNext(din,0.U),0.U)} + /////////////////////////////////////////////////////////////////// + // RV range + def rvrangecheck(CCM_SADR:Long, CCM_SIZE:Int, addr:UInt) = { + val REGION_BITS = 4; + val MASK_BITS = 10 + log2Ceil(CCM_SIZE) + val start_addr = CCM_SADR.U(32.W) + val region = start_addr(31,32-REGION_BITS) + val in_region = addr(31,(32-REGION_BITS)) === region + val in_range = if(CCM_SIZE==48) + (addr(31, MASK_BITS) === start_addr(31,MASK_BITS)) & ~addr(MASK_BITS-1 , MASK_BITS-2).andR + else addr(31,MASK_BITS) === start_addr(31,MASK_BITS) + (in_region, in_range) + } def rvlsadder(rs1:UInt,offset:UInt) = { val w1 = Cat(0.U(1.W),rs1(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[11]=sign @@ -198,73 +235,50 @@ trait el2_lib extends param{ ((Fill(20, offset(11) & ~w1(12))) & (rs1(31,12)-1.U)) Cat(dout_upper,w1(11,0)) } - - def Encoder(dec_value:UInt) = { - val enc_val = Cat(dec_value(4)| dec_value(5) | dec_value(6)|dec_value(7), - dec_value(2)| dec_value(3) | dec_value(6)|dec_value(7), - dec_value(1)| dec_value(3) | dec_value(5)|dec_value(7)) - enc_val } - - - - def rvbradder(pc:UInt,offset:UInt) = { // lsb is not using in code - val w1 = Cat(0.U(1.W),pc(11,0)) + Cat(0.U(1.W),offset(11,0)) //w1[12] =cout offset[12]=sign - val dout_upper = ((Fill(19, ~(offset(11) ^ w1(12))))& pc(30,12)) | - ((Fill(19, ~offset(11) & w1(12))) & (pc(30,12)+1.U)) | - ((Fill(19, offset(11) & ~w1(12))) & (pc(30,12)-1.U)) - Cat(dout_upper,w1(11,0))} - - def rvbradder_32 (pc:UInt, offset:UInt) = { - val dout_lower = pc(12,1) +& offset(12,1) - val pc_inc = pc(31,13)+1.U - val pc_dec = pc(31,13)-1.U - val sign = offset(12) - Cat(Mux1H(Seq((sign ^ !dout_lower(dout_lower.getWidth-1)).asBool -> pc(31,13), - (!sign & dout_lower(dout_lower.getWidth-1)).asBool -> pc_inc, - (sign & !dout_lower(dout_lower.getWidth-1)).asBool -> pc_dec)) , dout_lower(11,0), 0.U) - } - - - def rvtwoscomp(din:UInt) = { //Done for verification and testing - val temp = Wire(Vec(din.getWidth-1,UInt(1.W))) - for(i <- 1 to din.getWidth-1){ - temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i)) - } - Cat(temp.asUInt,din(0)) - } - - - //WIDTH will be inferred - def rvmaskandmatch(mask:UInt,data:UInt,masken:UInt) = { //Done for verification and testing + /////////////////////////////////////////////////////////////////// + def rvmaskandmatch(mask:UInt, data:UInt, masken:Bool):UInt={ val matchvec = Wire(Vec(data.getWidth,UInt(1.W))) - val masken_or_fullmask = masken.asBool & (~(mask(data.getWidth-1,0).andR)) + val masken_or_fullmask = masken & ~mask.andR matchvec(0) := masken_or_fullmask | (mask(0) === data(0)).asUInt for(i <- 1 to data.getWidth-1) - {matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt)} - matchvec.asUInt.andR + matchvec(i) := Mux(mask(i-1,0).andR & masken_or_fullmask,"b1".U,(mask(i) === data(i)).asUInt) + matchvec.asUInt } - - def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = { - val REGION_BITS = 4 - val MASK_BITS = 10 + log2Ceil(CCM_SIZE) - val start_addr = CCM_SADR - val region = start_addr(31,(32-REGION_BITS)) - val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt - val in_range = Wire(UInt(1.W)) - if(CCM_SIZE == 48) - in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt) - else - in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt - (in_range,in_region) + /////////////////////////////////////////////////////////////////// + def el2_configurable_gw(clk : Clock, rst:AsyncReset, extintsrc_req_sync : Bool, meigwctrl_polarity: Bool, meigwctrl_type: Bool, meigwclr: Bool) = { + val din = WireInit(Bool(), 0.U) + val dout = withClockAndReset(clk, rst){RegNext(din, false.B)} + din := (extintsrc_req_sync ^ meigwctrl_polarity) | (dout & !meigwclr) + Mux(meigwctrl_type, (extintsrc_req_sync ^ meigwctrl_polarity) | dout, extintsrc_req_sync ^ meigwctrl_polarity) } + + /////////////////////////////////////////////////////////////////// + // Move rvecc_encode to a proper trait def rvecc_encode(din:UInt):UInt = { + def pat(y : List[Int]) = (0 until y.size).map(i=> din(y(i))).reduce(_^_) + val w0 = pat(List(0, 1, 3, 4, 6, 8, 10, 11, 13, 15, 17, 19, 21, 23, 25, 26, 28, 30)) + val w1 = pat(List(0, 2, 3, 5, 6, 9, 10, 12, 13, 16, 17, 20, 21, 24, 25, 27, 28, 31)) + val w2 = pat(List(1, 2, 3, 7, 8, 9, 10, 14, 15, 16, 17, 22, 23, 24, 25, 29, 30, 31)) + val w3 = pat(List(4, 5, 6, 7, 8, 9, 10, 18, 19, 20, 21, 22, 23, 24, 25)) + val w4 = pat(List(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)) + val w5 = pat(List(26, 27, 28, 29, 30, 31)) + val w6 = Cat(w5,w4,w3,w2,w1,w0) + Cat(din.xorR ^ w6.xorR, w6) + } + + class rvecc_encode extends Module{ //Done for verification and testing + val io = IO(new Bundle{ + val din = Input(UInt(32.W)) + val ecc_out = Output(UInt(7.W)) + }) val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1) val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0) val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0) val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1) + val w0 = Wire(Vec(18,UInt(1.W))) val w1 = Wire(Vec(18,UInt(1.W))) val w2 = Wire(Vec(18,UInt(1.W))) @@ -272,25 +286,22 @@ trait el2_lib extends param{ val w4 = Wire(Vec(15,UInt(1.W))) val w5 = Wire(Vec(6, UInt(1.W))) var j = 0;var k = 0;var m = 0; - var x = 0;var y = 0;var z = 0 + var x = 0;var y = 0;var z = 0; + for(i <- 0 to 31) { - if(mask0(i)==1) {w0(j) := din(i); j = j +1 } - if(mask1(i)==1) {w1(k) := din(i); k = k +1 } - if(mask2(i)==1) {w2(m) := din(i); m = m +1 } - if(mask3(i)==1) {w3(x) := din(i); x = x +1 } - if(mask4(i)==1) {w4(y) := din(i); y = y +1 } - if(mask5(i)==1) {w5(z) := din(i); z = z +1 } + if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } + if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } + if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } + if(mask3(i)==1) {w3(x) := io.din(i); x = x +1 } + if(mask4(i)==1) {w4(y) := io.din(i); y = y +1 } + if(mask5(i)==1) {w5(z) := io.din(i); z = z +1 } } val w6 = Cat((w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) - val ecc_out = Cat(din.xorR ^ w6.xorR, w6) - ecc_out + io.ecc_out := Cat(io.din.xorR ^ w6.xorR, w6) } - def rveven_paritygen(data_in:UInt):UInt = data_in.xorR.asUInt - def rveven_paritycheck(data_in:UInt,parity_in:UInt) = (data_in.xorR.asUInt) ^ parity_in - def rvecc_decode(en:UInt,din:UInt,ecc_in:UInt,sed_ded:UInt)= { val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1) @@ -335,6 +346,42 @@ trait el2_lib extends param{ (ecc_out,dout,single_ecc_error,double_ecc_error) } + class rvecc_encode_64 extends Module{ //Done for verification and testing + val io = IO(new Bundle{ + val din = Input(UInt(64.W)) + val ecc_out = Output(UInt(7.W)) + }) + val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) + val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) + val mask2 = Array(0,1,1,1,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,1,1,1,1) + val mask3 = Array(0,0,0,0,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) + val mask4 = Array(0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) + val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) + val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) + + val w0 = Wire(Vec(35,UInt(1.W))) + val w1 = Wire(Vec(35,UInt(1.W))) + val w2 = Wire(Vec(35,UInt(1.W))) + val w3 = Wire(Vec(31,UInt(1.W))) + val w4 = Wire(Vec(31,UInt(1.W))) + val w5 = Wire(Vec(31,UInt(1.W))) + val w6 = Wire(Vec(7, UInt(1.W))) + + var j = 0;var k = 0;var m = 0; var n =0; + var x = 0;var y = 0;var z = 0 + + for(i <- 0 to 63) + { + if(mask0(i)==1) {w0(j) := io.din(i); j = j +1 } + if(mask1(i)==1) {w1(k) := io.din(i); k = k +1 } + if(mask2(i)==1) {w2(m) := io.din(i); m = m +1 } + if(mask3(i)==1) {w3(n) := io.din(i); n = n +1 } + if(mask4(i)==1) {w4(x) := io.din(i); x = x +1 } + if(mask5(i)==1) {w5(y) := io.din(i); y = y +1 } + if(mask6(i)==1) {w6(z) := io.din(i); z = z +1 } + } + io.ecc_out := Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) + } def rvecc_encode_64(din:UInt):UInt = { val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) @@ -345,7 +392,6 @@ trait el2_lib extends param{ val mask5 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0) val mask6 = Array(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1) - val w0 = Wire(Vec(35,UInt(1.W))) val w1 = Wire(Vec(35,UInt(1.W))) val w2 = Wire(Vec(35,UInt(1.W))) @@ -367,11 +413,9 @@ trait el2_lib extends param{ if(mask5(i)==1) {w5(y) := din(i); y = y +1 } if(mask6(i)==1) {w6(z) := din(i); z = z +1 } } - val ecc_out = Cat((w0.asUInt.xorR),(w1.asUInt.xorR),(w2.asUInt.xorR),(w3.asUInt.xorR),(w4.asUInt.xorR),(w5.asUInt.xorR),(w6.asUInt.xorR)) - ecc_out + Cat((w6.asUInt.xorR),(w5.asUInt.xorR),(w4.asUInt.xorR),(w3.asUInt.xorR),(w2.asUInt.xorR),(w1.asUInt.xorR),(w0.asUInt.xorR)) } - def rvecc_decode_64(en:UInt,din:UInt,ecc_in:UInt) = { val mask0 = Array(1,1,0,1,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1) val mask1 = Array(1,0,1,1,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,0,1,1,0,1,1,0,0,1,1) @@ -408,4 +452,97 @@ trait el2_lib extends param{ ecc_error } -} \ No newline at end of file + + + class gated_latch extends BlackBox with HasBlackBoxResource { + val io = IO(new Bundle { + val Q = Output(Clock()) + val CK = Input(Clock()) + val EN = Input(Bool()) + val SE = Input(Bool()) + }) + addResource("/vsrc/gated_latch.v") + } + + class rvclkhdr extends Module { + val io = IO(new Bundle { + val l1clk = Output(Clock()) + val clk = Input(Clock()) + val en = Input(Bool()) + val scan_mode = Input(Bool()) + }) + val clkhdr = { Module(new gated_latch) } + io.l1clk := clkhdr.io.Q + clkhdr.io.CK := io.clk + clkhdr.io.EN := io.en + clkhdr.io.SE := io.scan_mode + } + + object rvclkhdr { + def apply(clk: Clock, en: Bool, scan_mode: Bool): Clock = { + val cg = Module(new rvclkhdr) + cg.io.clk := clk + cg.io.en := en + cg.io.scan_mode := scan_mode + cg.io.l1clk + } + } + + def rvrangecheck_ch(addr:UInt,CCM_SADR:UInt, CCM_SIZE:Int=128) = { + val REGION_BITS = 4 + val MASK_BITS = 10 + log2Ceil(CCM_SIZE) + val start_addr = CCM_SADR + val region = start_addr(31,(32-REGION_BITS)) + val in_region = (addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt + val in_range = Wire(UInt(1.W)) + if(CCM_SIZE == 48) + in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt & ~(addr(MASK_BITS-1,MASK_BITS-2).andR.asUInt) + else + in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt + (in_range,in_region) + } + + ////rvdffe /////////////////////////////////////////////////////////////////////// + object rvdffe { + def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = { + val obj = Module(new rvclkhdr()) + val l1clk = obj.io.l1clk + obj.io.clk := clk + obj.io.en := en + obj.io.scan_mode := scan_mode + withClock(l1clk) { + RegNext(din, 0.U) + } + } + def apply(din: Bundle, en: Bool, clk: Clock, scan_mode: Bool) = { + val obj = Module(new rvclkhdr()) + val l1clk = obj.io.l1clk + obj.io.clk := clk + obj.io.en := en + obj.io.scan_mode := scan_mode + withClock(l1clk) { + RegNext(din,0.U.asTypeOf(din.cloneType)) + } + } + def apply(din: SInt, en: Bool, clk: Clock, scan_mode: Bool): Bits with Num[_ >: SInt with UInt <: Bits with Num[_ >: SInt with UInt]] = { + val obj = Module(new rvclkhdr()) + val l1clk = obj.io.l1clk + obj.io.clk := clk + obj.io.en := en + obj.io.scan_mode := scan_mode + withClock(l1clk) { + RegNext(din, 0.S) + } + } + } + + ///////////////////////////////////////////////////////// + def rvtwoscomp(din:UInt) = { //Done for verification and testing + val temp = Wire(Vec(din.getWidth-1,UInt(1.W))) + for(i <- 1 to din.getWidth-1){ + temp(i-1) := Mux(din(i-1,0).orR ,~din(i),din(i)) + } + Cat(temp.asUInt,din(0)) + } + +} diff --git a/src/main/scala/lsu/el2_lsu.scala b/src/main/scala/lsu/el2_lsu.scala index b3d298f7..98edea9e 100644 --- a/src/main/scala/lsu/el2_lsu.scala +++ b/src/main/scala/lsu/el2_lsu.scala @@ -27,13 +27,13 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { val dec_tlu_mrac_ff = Input(UInt(32.W)) //Outputs - // val lsu_result_m = Output(UInt(32.W)) - // val lsu_result_corr_r = Output(UInt(32.W)) + val lsu_result_m = Output(UInt(32.W)) + val lsu_result_corr_r = Output(UInt(32.W)) val lsu_load_stall_any = Output(Bool()) val lsu_store_stall_any = Output(Bool()) val lsu_fastint_stall_any = Output(Bool()) val lsu_idle_any = Output(Bool()) - val lsu_fir_addr = Output(UInt(32.W)) + val lsu_fir_addr = Output(UInt(31.W)) val lsu_fir_error = Output(UInt(2.W)) val lsu_single_ecc_error_incr = Output(Bool()) val lsu_error_pkt_r = Output(new el2_lsu_error_pkt_t) @@ -147,11 +147,13 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { val dma_dccm_wdata = WireInit(0.U(64.W)) val dma_dccm_wdata_lo = WireInit(0.U(32.W)) val dma_dccm_wdata_hi = WireInit(0.U(32.W)) - val dma_mem_tag_m = WireInit(0.U(32.W)) + val dma_mem_tag_m = WireInit(0.U(3.W)) val lsu_raw_fwd_lo_r = WireInit(0.U(1.W)) val lsu_raw_fwd_hi_r = WireInit(0.U(1.W)) val lsu_lsc_ctl = Module(new el2_lsu_lsc_ctl ) + io.lsu_result_m := lsu_lsc_ctl.io.lsu_result_m + io.lsu_result_corr_r := lsu_lsc_ctl.io.lsu_result_corr_r val dccm_ctl = Module(new el2_lsu_dccm_ctl ) val stbuf = Module(new el2_lsu_stbuf ) val ecc = Module(new el2_lsu_ecc ) @@ -421,7 +423,9 @@ class el2_lsu extends Module with RequireAsyncReset with param with el2_lib { bus_intf.io.end_addr_d := lsu_lsc_ctl.io.end_addr_d bus_intf.io.end_addr_m := lsu_lsc_ctl.io.end_addr_m bus_intf.io.end_addr_r := lsu_lsc_ctl.io.end_addr_r -// bus_intf.io.store_data_m := lsu_lsc_ctl.io.store_data_m + bus_intf.io.store_data_r := dccm_ctl.io.store_data_r + bus_intf.io.lsu_pkt_m <> lsu_lsc_ctl.io.lsu_pkt_m + bus_intf.io.lsu_pkt_r <> lsu_lsc_ctl.io.lsu_pkt_r bus_intf.io.dec_tlu_force_halt := io.dec_tlu_force_halt bus_intf.io.lsu_commit_r := lsu_lsc_ctl.io.lsu_commit_r bus_intf.io.is_sideeffects_m := lsu_lsc_ctl.io.is_sideeffects_m diff --git a/src/main/scala/lsu/el2_lsu_addrcheck.scala b/src/main/scala/lsu/el2_lsu_addrcheck.scala index 515faa79..42ee4b51 100644 --- a/src/main/scala/lsu/el2_lsu_addrcheck.scala +++ b/src/main/scala/lsu/el2_lsu_addrcheck.scala @@ -33,9 +33,9 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib //DCCM check // Start address check // Gen_dccm_enable - val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U) - // End address check - val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d,DCCM_SADR,DCCM_SIZE) else (0.U,0.U) + val (start_addr_in_dccm_d,start_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.start_addr_d ,aslong(DCCM_SADR).U ,DCCM_SIZE) else (0.U,0.U) + // End address check + val (end_addr_in_dccm_d ,end_addr_in_dccm_region_d) = if(DCCM_ENABLE) rvrangecheck_ch(io.end_addr_d ,aslong(DCCM_SADR).U ,DCCM_SIZE) else (0.U,0.U) val addr_in_iccm = WireInit(0.U(1.W)) if(ICCM_ENABLE ){ //check_iccm @@ -47,9 +47,9 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib //PIC memory check //start address check - val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE) + val (start_addr_in_pic_d,start_addr_in_pic_region_d) = rvrangecheck_ch(io.start_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE) //End address check - val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0),PIC_BASE_ADDR,PIC_SIZE) + val (end_addr_in_pic_d,end_addr_in_pic_region_d) = rvrangecheck_ch(io.end_addr_d(31,0) ,aslong(PIC_BASE_ADDR).U ,PIC_SIZE) val start_addr_dccm_or_pic = start_addr_in_dccm_region_d | start_addr_in_pic_region_d val base_reg_dccm_or_pic = (io.rs1_region_d(3,0) === DCCM_REGION.U) | (io.rs1_region_d(3,0) === PIC_REGION.U) //base region @@ -62,25 +62,25 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib val is_aligned_d = (io.lsu_pkt_d.word & (io.start_addr_d(1,0) === 0.U)) | (io.lsu_pkt_d.half & (io.start_addr_d(0) === 0.U)) | io.lsu_pkt_d.by - val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0,DATA_ACCESS_ENABLE1,DATA_ACCESS_ENABLE2,DATA_ACCESS_ENABLE3, - DATA_ACCESS_ENABLE4,DATA_ACCESS_ENABLE5,DATA_ACCESS_ENABLE6,DATA_ACCESS_ENABLE7)).orR) | - (((DATA_ACCESS_ENABLE0 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) | //0111 - (DATA_ACCESS_ENABLE1 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) | //1111 - (DATA_ACCESS_ENABLE2 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) | //1011 - (DATA_ACCESS_ENABLE3 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) | //1000 - (DATA_ACCESS_ENABLE4 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) | - (DATA_ACCESS_ENABLE5 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) | - (DATA_ACCESS_ENABLE6 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) | - (DATA_ACCESS_ENABLE7 & ((io.start_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7))) + val non_dccm_access_ok = (!(Cat(DATA_ACCESS_ENABLE0.B ,DATA_ACCESS_ENABLE1.B ,DATA_ACCESS_ENABLE2.B ,DATA_ACCESS_ENABLE3.B , + DATA_ACCESS_ENABLE4.B ,DATA_ACCESS_ENABLE5.B ,DATA_ACCESS_ENABLE6.B ,DATA_ACCESS_ENABLE7.B )).orR) | + (((DATA_ACCESS_ENABLE0.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK0).U)) === (aslong(DATA_ACCESS_ADDR0).U | aslong(DATA_ACCESS_MASK0).U)) | //0111 + (DATA_ACCESS_ENABLE1.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK1).U)) === (aslong(DATA_ACCESS_ADDR1).U | aslong(DATA_ACCESS_MASK1).U)) | //1111 + (DATA_ACCESS_ENABLE2.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK2).U)) === (aslong(DATA_ACCESS_ADDR2).U | aslong(DATA_ACCESS_MASK2).U)) | //1011 + (DATA_ACCESS_ENABLE3.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK3).U)) === (aslong(DATA_ACCESS_ADDR3).U | aslong(DATA_ACCESS_MASK3).U)) | //1000 + (DATA_ACCESS_ENABLE4.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK4).U)) === (aslong(DATA_ACCESS_ADDR4).U | aslong(DATA_ACCESS_MASK4).U)) | + (DATA_ACCESS_ENABLE5.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK5).U)) === (aslong(DATA_ACCESS_ADDR5).U | aslong(DATA_ACCESS_MASK5).U)) | + (DATA_ACCESS_ENABLE6.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK6).U)) === (aslong(DATA_ACCESS_ADDR6).U | aslong(DATA_ACCESS_MASK6).U)) | + (DATA_ACCESS_ENABLE7.B & ((io.start_addr_d(31,0) | aslong(DATA_ACCESS_MASK7).U)) === (aslong(DATA_ACCESS_ADDR7).U | aslong(DATA_ACCESS_MASK7).U))) & - ((DATA_ACCESS_ENABLE0 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK0)) === (DATA_ACCESS_ADDR0 | DATA_ACCESS_MASK0)) | - (DATA_ACCESS_ENABLE1 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK1)) === (DATA_ACCESS_ADDR1 | DATA_ACCESS_MASK1)) | - (DATA_ACCESS_ENABLE2 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK2)) === (DATA_ACCESS_ADDR2 | DATA_ACCESS_MASK2)) | - (DATA_ACCESS_ENABLE3 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK3)) === (DATA_ACCESS_ADDR3 | DATA_ACCESS_MASK3)) | - (DATA_ACCESS_ENABLE4 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK4)) === (DATA_ACCESS_ADDR4 | DATA_ACCESS_MASK4)) | - (DATA_ACCESS_ENABLE5 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK5)) === (DATA_ACCESS_ADDR5 | DATA_ACCESS_MASK5)) | - (DATA_ACCESS_ENABLE6 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK6)) === (DATA_ACCESS_ADDR6 | DATA_ACCESS_MASK6)) | - (DATA_ACCESS_ENABLE7 & ((io.end_addr_d(31,0) | DATA_ACCESS_MASK7)) === (DATA_ACCESS_ADDR7 | DATA_ACCESS_MASK7)))) + ((DATA_ACCESS_ENABLE0.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK0).U)) === (aslong(DATA_ACCESS_ADDR0).U | aslong(DATA_ACCESS_MASK0).U)) | + (DATA_ACCESS_ENABLE1.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK1).U)) === (aslong(DATA_ACCESS_ADDR1).U | aslong(DATA_ACCESS_MASK1).U)) | + (DATA_ACCESS_ENABLE2.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK2).U)) === (aslong(DATA_ACCESS_ADDR2).U | aslong(DATA_ACCESS_MASK2).U)) | + (DATA_ACCESS_ENABLE3.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK3).U)) === (aslong(DATA_ACCESS_ADDR3).U | aslong(DATA_ACCESS_MASK3).U)) | + (DATA_ACCESS_ENABLE4.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK4).U)) === (aslong(DATA_ACCESS_ADDR4).U | aslong(DATA_ACCESS_MASK4).U)) | + (DATA_ACCESS_ENABLE5.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK5).U)) === (aslong(DATA_ACCESS_ADDR5).U | aslong(DATA_ACCESS_MASK5).U)) | + (DATA_ACCESS_ENABLE6.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK6).U)) === (aslong(DATA_ACCESS_ADDR6).U | aslong(DATA_ACCESS_MASK6).U)) | + (DATA_ACCESS_ENABLE7.B & ((io.end_addr_d(31,0) | aslong(DATA_ACCESS_MASK7).U)) === (aslong(DATA_ACCESS_ADDR7).U | aslong(DATA_ACCESS_MASK7).U)))) val regpred_access_fault_d = (start_addr_dccm_or_pic ^ base_reg_dccm_or_pic) val picm_access_fault_d = (io.addr_in_pic_d & ((io.start_addr_d(1,0) =/= 0.U(2.W)) | !io.lsu_pkt_d.word)) @@ -123,4 +123,4 @@ class el2_lsu_addrcheck extends Module with RequireAsyncReset with el2_lib object address_checker extends App{ println("Generate Verilog") println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_addrcheck())) -} \ No newline at end of file +} diff --git a/src/main/scala/lsu/el2_lsu_bus_buffer.scala b/src/main/scala/lsu/el2_lsu_bus_buffer.scala index 15bacca1..b0807048 100644 --- a/src/main/scala/lsu/el2_lsu_bus_buffer.scala +++ b/src/main/scala/lsu/el2_lsu_bus_buffer.scala @@ -1,828 +1,677 @@ - package lsu import chisel3._ import chisel3.util._ import lib._ import include._ -import snapshot._ import chisel3.experimental.{ChiselEnum, chiselName} import chisel3.util.ImplicitConversions.intToUInt -//object el2_lsu_bus_buffer { -// object State extends ChiselEnum { -// val IDLE, WAIT, CMD, RESP, DONE_PARTIAL, DONE_WAIT, DONE = Value -// } -//} - @chiselName -class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib -{ -// import el2_lsu_bus_buffer.State -// import el2_lsu_bus_buffer.State._ +class el2_lsu_bus_buffer extends Module with RequireAsyncReset with el2_lib { + val io = IO(new Bundle { + val scan_mode = Input(Bool()) + val dec_tlu_external_ldfwd_disable = Input(Bool()) + val dec_tlu_wb_coalescing_disable = Input(Bool()) + val dec_tlu_sideeffect_posted_disable = Input(Bool()) + val dec_tlu_force_halt = Input(Bool()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_pkt_r = Input(new el2_lsu_pkt_t) + val lsu_addr_m = Input(UInt(32.W)) + val end_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + val store_data_r = Input(UInt(32.W)) + val no_word_merge_r = Input(Bool()) + val no_dword_merge_r = Input(Bool()) + val lsu_busreq_m = Input(Bool()) + val ld_full_hit_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + val lsu_commit_r = Input(Bool()) + val is_sideeffects_r = Input(Bool()) + val ldst_dual_d = Input(Bool()) + val ldst_dual_m = Input(Bool()) + val ldst_dual_r = Input(Bool()) + val ldst_byteen_ext_m = Input(UInt(8.W)) + val lsu_axi_wready = Input(Bool()) + val lsu_axi_bvalid = Input(Bool()) + val lsu_axi_bresp = Input(UInt(2.W)) + val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W)) + val lsu_axi_arready = Input(Bool()) + val lsu_axi_rvalid = Input(Bool()) + val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W)) + val lsu_axi_rdata = Input(UInt(64.W)) + val lsu_axi_rresp = Input(UInt(2.W)) + val lsu_bus_clk_en = Input(Bool()) + val lsu_bus_clk_en_q = Input(Bool()) - val io = IO (new Bundle { - //val clk = Input(Clock()) //implicit - //val rst_l = Input(1.W) //implicit reset - val scan_mode = Input(Bool()) - val dec_tlu_external_ldfwd_disable = Input(Bool()) - val dec_tlu_wb_coalescing_disable = Input(Bool()) - val dec_tlu_sideeffect_posted_disable = Input(Bool()) - val dec_tlu_force_halt = Input(Bool()) - val lsu_c2_r_clk = Input(Clock()) - val lsu_bus_ibuf_c1_clk = Input(Clock()) - val lsu_bus_obuf_c1_clk = Input(Clock()) - val lsu_bus_buf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val lsu_busm_clk = Input(Clock()) - val dec_lsu_valid_raw_d = Input(Bool()) - val lsu_pkt_m = Input(new el2_lsu_pkt_t) - val lsu_pkt_r = Input(new el2_lsu_pkt_t) - val lsu_addr_m = Input(UInt(32.W)) - val end_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) - val store_data_r = Input(UInt(32.W)) - val no_word_merge_r = Input(Bool()) - val no_dword_merge_r = Input(Bool()) - val lsu_busreq_m = Input(Bool()) - val ld_full_hit_m = Input(Bool()) - val flush_m_up = Input(Bool()) - val flush_r = Input(Bool()) - val lsu_commit_r = Input(Bool()) - val is_sideeffects_r = Input(Bool()) - val ldst_dual_d = Input(Bool()) - val ldst_dual_m = Input(Bool()) - val ldst_dual_r = Input(Bool()) - val ldst_byteen_ext_m = Input(UInt(8.W)) - val lsu_axi_awready = Input(Bool()) - val lsu_axi_wready = Input(Bool()) - val lsu_axi_bvalid = Input(Bool()) - val lsu_axi_bresp = Input(UInt(2.W)) - val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_arready = Input(Bool()) - val lsu_axi_rvalid = Input(Bool()) - val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_rdata = Input(UInt(64.W)) - val lsu_axi_rresp = Input(UInt(2.W)) - val lsu_bus_clk_en = Input(Bool()) - val lsu_bus_clk_en_q = Input(Bool()) + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + val lsu_bus_idle_any = Output(Bool()) + val ld_byte_hit_buf_lo = Output((UInt(4.W))) + val ld_byte_hit_buf_hi = Output((UInt(4.W))) + val ld_fwddata_buf_lo = Output((UInt(32.W))) + val ld_fwddata_buf_hi = Output((UInt(32.W))) + val lsu_imprecise_error_load_any = Output(Bool()) + val lsu_imprecise_error_store_any = Output(Bool()) + val lsu_imprecise_error_addr_any = Output(UInt(32.W)) + val lsu_nonblock_load_valid_m = Output(Bool()) + val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_inv_r = Output(Bool()) + val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_data_valid = Output(Bool()) + val lsu_nonblock_load_data_error = Output(Bool()) + val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_data = Output(UInt(32.W)) + val lsu_pmu_bus_trxn = Output(Bool()) + val lsu_pmu_bus_misaligned = Output(Bool()) + val lsu_pmu_bus_error = Output(Bool()) + val lsu_pmu_bus_busy = Output(Bool()) - val lsu_busreq_r = Output(Bool()) - val lsu_bus_buffer_pend_any = Output(Bool()) - val lsu_bus_buffer_full_any = Output(Bool()) - val lsu_bus_buffer_empty_any = Output(Bool()) - val lsu_bus_idle_any = Output(Bool()) - val ld_byte_hit_buf_lo = Output((UInt(4.W))) - val ld_byte_hit_buf_hi = Output((UInt(4.W))) - val ld_fwddata_buf_lo = Output((UInt(32.W))) - val ld_fwddata_buf_hi = Output((UInt(32.W))) - val lsu_imprecise_error_load_any = Output(Bool()) - val lsu_imprecise_error_store_any = Output(Bool()) - val lsu_imprecise_error_addr_any = Output(UInt(32.W)) - val lsu_nonblock_load_valid_m = Output(Bool()) - val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_inv_r = Output(Bool()) - val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_data_valid = Output(Bool()) - val lsu_nonblock_load_data_error = Output(Bool()) - val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_data = Output(UInt(32.W)) - val lsu_pmu_bus_trxn = Output(Bool()) - val lsu_pmu_bus_misaligned = Output(Bool()) - val lsu_pmu_bus_error = Output(Bool()) - val lsu_pmu_bus_busy = Output(Bool()) - val lsu_axi_awvalid = Output(Bool()) - val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_awaddr = Output(UInt(32.W)) - val lsu_axi_awregion = Output(UInt(4.W)) - val lsu_axi_awlen = Output(UInt(8.W)) - val lsu_axi_awsize = Output(UInt(3.W)) - val lsu_axi_awburst = Output(UInt(2.W)) - val lsu_axi_awlock = Output(Bool()) - val lsu_axi_awcache = Output(UInt(4.W)) - val lsu_axi_awprot = Output(UInt(3.W)) - val lsu_axi_awqos = Output(UInt(4.W)) - val lsu_axi_wvalid = Output(Bool()) - val lsu_axi_wdata = Output(UInt(64.W)) - val lsu_axi_wstrb = Output(UInt(8.W)) - val lsu_axi_wlast = Output(Bool()) - val lsu_axi_bready = Output(Bool()) - val lsu_axi_arvalid = Output(Bool()) - val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_araddr = Output(UInt(32.W)) - val lsu_axi_arregion = Output(UInt(4.W)) - val lsu_axi_arlen = Output(UInt(8.W)) - val lsu_axi_arsize = Output(UInt(3.W)) - val lsu_axi_arburst = Output(UInt(2.W)) - val lsu_axi_arlock = Output(Bool()) - val lsu_axi_arcache = Output(UInt(4.W)) - val lsu_axi_arprot = Output(UInt(3.W)) - val lsu_axi_arqos = Output(UInt(4.W)) - val lsu_axi_rready = Output(Bool()) + // AXI Signals + val lsu_axi_awvalid = Output(Bool()) + val lsu_axi_awready = Input(Bool()) + val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_awaddr = Output(UInt(32.W)) + val lsu_axi_awregion = Output(UInt(4.W)) + val lsu_axi_awlen = Output(UInt(8.W)) + val lsu_axi_awsize = Output(UInt(3.W)) + val lsu_axi_awburst = Output(UInt(2.W)) + val lsu_axi_awlock = Output(Bool()) + val lsu_axi_awcache = Output(UInt(4.W)) + val lsu_axi_awprot = Output(UInt(3.W)) + val lsu_axi_awqos = Output(UInt(4.W)) + val lsu_axi_wvalid = Output(Bool()) + val lsu_axi_wdata = Output(UInt(64.W)) + val lsu_axi_wstrb = Output(UInt(8.W)) + val lsu_axi_wlast = Output(Bool()) + val lsu_axi_bready = Output(Bool()) + val lsu_axi_arvalid = Output(Bool()) + val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_araddr = Output(UInt(32.W)) + val lsu_axi_arregion = Output(UInt(4.W)) + val lsu_axi_arlen = Output(UInt(8.W)) + val lsu_axi_arsize = Output(UInt(3.W)) + val lsu_axi_arburst = Output(UInt(2.W)) + val lsu_axi_arlock = Output(Bool()) + val lsu_axi_arcache = Output(UInt(4.W)) + val lsu_axi_arprot = Output(UInt(3.W)) + val lsu_axi_arqos = Output(UInt(4.W)) + val lsu_axi_rready = Output(Bool()) + }) + def indexing(in : UInt, index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) + def indexing(in : Vec[UInt], index : UInt) = Mux1H((0 until math.pow(2, index.getWidth).asInstanceOf[Int]).map(i=>(index===i.U)->in(i))) - }) + val DEPTH = LSU_NUM_NBLOAD + val DEPTH_LOG2 = LSU_NUM_NBLOAD_WIDTH + val TIMER = 8 + val TIMER_MAX = TIMER - 1 + val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) - val DEPTH = pt1.LSU_NUM_NBLOAD - val DEPTH_LOG2 = pt1.LSU_NUM_NBLOAD_WIDTH - val TIMER = 8 - val TIMER_MAX = TIMER - 1 - val TIMER_LOG2 = if (TIMER < 2) 1 else log2Ceil(TIMER) + val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) + val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) + val buf_state = Wire(Vec(DEPTH, UInt(3.W))) + val buf_write = WireInit(UInt(DEPTH.W), 0.U) + val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), 0.U) - val idle_C :: wait_C :: cmd_C :: resp_C :: done_partial_C :: done_wait_C :: done_C :: Nil = Enum(7) - val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) - val ld_addr_hitvec_lo = WireInit(UInt(4.W), init = 0.U) - val ld_addr_hitvec_hi = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_hi_m = io.ldst_byteen_ext_m(7, 4) + val ldst_byteen_lo_m = io.ldst_byteen_ext_m(3, 0) - val ld_byte_hitvec_lo = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_hitvec_hi = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) - val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) + val ld_addr_hitvec_lo = (0 until DEPTH).map(i => (io.lsu_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_addr_hitvec_hi = (0 until DEPTH).map(i => (io.end_addr_m(31, 2) === buf_addr(i)(31, 2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m) + val ld_byte_hitvecfn_lo = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), 0.U) + val ld_byte_hitvecfn_hi = Wire(Vec(4, UInt(DEPTH.W))) + val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), 0.U) + val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) + buf_byteen := buf_byteen.map(i=>0.U) + val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) + buf_nxtstate := buf_nxtstate.map(i=>0.U) + val buf_wr_en = Wire(Vec(DEPTH, Bool())) + buf_wr_en := buf_wr_en.map(i=> false.B) + val buf_data_en = Wire(Vec(DEPTH, Bool())) + buf_data_en := buf_data_en.map(i=> false.B) + val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_state_bus_en := buf_state_bus_en.map(i=> false.B) + val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_in := buf_ldfwd_in.map(i=> false.B) + val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) + buf_ldfwd_en := buf_ldfwd_en.map(i=> false.B) + val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_data_in := buf_data_in.map(i=> 0.U) + val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag_in := buf_ldfwdtag_in.map(i=> 0.U) + val buf_error_en = Wire(Vec(DEPTH, Bool())) + buf_error_en := buf_error_en.map(i=> false.B) + val bus_rsp_read_error = WireInit(Bool(), false.B) + val bus_rsp_rdata = WireInit(UInt(64.W), 0.U) + val bus_rsp_write_error = WireInit(Bool(), false.B) + val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag := buf_dualtag.map(i=> 0.U) + val buf_ldfwd = WireInit(UInt(DEPTH.W), 0.U) + val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_resp_state_bus_en := buf_resp_state_bus_en.map(i=> false.B) + val any_done_wait_state = WireInit(Bool(), false.B) + val bus_rsp_write = WireInit(Bool(), false.B) + val bus_rsp_write_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_ldfwdtag := buf_ldfwdtag.map(i=> 0.U) + val buf_rst = Wire(Vec(DEPTH, Bool())) + buf_rst := buf_rst.map(i=> false.B) + val ibuf_drainvec_vld = WireInit(UInt(DEPTH.W), 0.U) + val buf_byteen_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_byteen_in := buf_byteen_in.map(i=> 0.U) + val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) + buf_addr_in := buf_addr_in.map(i=> 0.U) + val buf_dual_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_samedw_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_nomerge_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualhi_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) + buf_dualtag_in := buf_dualtag_in.map(i=> 0.U) + val buf_sideeffect_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz_in := buf_sz_in.map(i=> 0.U) + val buf_write_in = WireInit(UInt(DEPTH.W), 0.U) + val buf_unsign = WireInit(UInt(DEPTH.W), 0.U) + val buf_error = WireInit(UInt(DEPTH.W), 0.U) - val ld_addr_ibuf_hit_lo = WireInit(Bool(), init = false.B) - val ld_addr_ibuf_hit_hi = WireInit(Bool(), init = false.B) - val ld_byte_ibuf_hit_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_ibuf_hit_hi = WireInit(UInt(4.W), init = 0.U) + val ibuf_data = WireInit(UInt(32.W), 0.U) + io.ld_byte_hit_buf_lo := (0 until 4).map(i => (ld_byte_hitvecfn_lo(i).orR | ld_byte_ibuf_hit_lo(i)).asUInt).reverse.reduce(Cat(_, _)) + io.ld_byte_hit_buf_hi := (0 until 4).map(i => (ld_byte_hitvecfn_hi(i).orR | ld_byte_ibuf_hit_hi(i)).asUInt).reverse.reduce(Cat(_, _)) - val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) - val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) - val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) - val is_aligned_r = WireInit(Bool(), init = false.B) - val ldst_samedw_r = WireInit(Bool(), init = false.B) - val lsu_nonblock_load_valid_r = WireInit(Bool(), init = false.B) - val lsu_nonblock_load_data_hi = WireInit(UInt(32.W), init = 0.U) - val lsu_nonblock_load_data_lo = WireInit(UInt(32.W), init = 0.U) - val lsu_nonblock_data_unalgn = WireInit(UInt(32.W), init = 0.U) - val lsu_nonblock_addr_offset = WireInit(UInt(2.W), init = 0.U) - val lsu_nonblock_sz = WireInit(UInt(2.W), init = 0.U) - val lsu_nonblock_unsign = WireInit(Bool(), init = false.B) - val lsu_nonblock_dual = WireInit(Bool(), init = false.B) - val lsu_nonblock_load_data_ready = WireInit(Bool(), init = false.B) + val ld_byte_hitvec_lo = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_, _))) + val ld_byte_hitvec_hi = (0 until 4).map(j => (0 until DEPTH).map(i => (ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_, _))) - val CmdPtr0Dec = Wire(Vec(DEPTH, Bool())) - val CmdPtr1Dec = Wire(Vec(DEPTH, Bool())) - val RspPtrDec = Wire(Vec(DEPTH, Bool())) - val CmdPtr0 = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val RspPtr = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val found_cmdptr0 = WireInit(Bool(), init = false.B) - val found_cmdptr1 = WireInit(Bool(), init = false.B) - val buf_numvld_any = WireInit(UInt(4.W), init = 0.U) - val buf_numvld_wrcmd_any = WireInit(UInt(4.W), init = 0.U) - val buf_numvld_cmd_any = WireInit(UInt(4.W), init = 0.U) - val buf_numvld_pend_any = WireInit(UInt(4.W), init = 0.U) - val any_done_wait_state = WireInit(Bool(), init = false.B) - val bus_sideeffect_pend = WireInit(Bool(), init = false.B) - val bus_pend_trxn = WireInit(UInt(8.W), init = 0.U) - val bus_pend_trxnQ = WireInit(UInt(8.W), init = 0.U) - val bus_pend_trxn_ns = WireInit(UInt(8.W), init = 0.U) - val lsu_bus_cntr_overflow = WireInit(Bool(), init = false.B) - val bus_coalescing_disable = WireInit(Bool(), init = false.B) - val mdbhd_en = WireInit(Bool(), init = false.B) + val buf_age_younger = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age_younger := buf_age_younger.map(i=> 0.U) + ld_byte_hitvecfn_lo := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_lo(j)(i) & !(ld_byte_hitvec_lo(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_, _))) + ld_byte_hitvecfn_hi := (0 until 4).map(j => (0 until DEPTH).map(i => (ld_byte_hitvec_hi(j)(i) & !(ld_byte_hitvec_hi(j) & buf_age_younger(i)).orR & !ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_, _))) - val bus_addr_match_pending = WireInit(Bool(), init = false.B) - val bus_cmd_sent = WireInit(Bool(), init = false.B) - val bus_cmd_ready = WireInit(Bool(), init = false.B) - val bus_wcmd_sent = WireInit(Bool(), init = false.B) - val bus_wdata_sent = WireInit(Bool(), init = false.B) - val bus_rsp_read = WireInit(Bool(), init = false.B) - val bus_rsp_write = WireInit(Bool(), init = false.B) - val bus_rsp_read_tag = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val bus_rsp_write_tag = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val bus_rsp_read_error = WireInit(Bool(), init = false.B) - val bus_rsp_write_error = WireInit(Bool(), init = false.B) - val bus_rsp_rdata = WireInit(UInt(64.W), init = 0.U) + val ibuf_addr = WireInit(UInt(32.W), 0.U) + val ibuf_write = WireInit(Bool(), false.B) + val ibuf_valid = WireInit(Bool(), false.B) + val ld_addr_ibuf_hit_lo = (io.lsu_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m + val ld_addr_ibuf_hit_hi = (io.end_addr_m(31, 2) === ibuf_addr(31, 2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m - // Bus buffer signals - val buf_state = Wire(Vec(DEPTH, UInt(3.W))) - val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) - val buf_addr = Wire(Vec(DEPTH, UInt(32.W))) - val buf_byteen = Wire(Vec(DEPTH, UInt(4.W))) - val buf_sideeffect = Wire(Vec(DEPTH, Bool())) - val buf_write = Wire(Vec(DEPTH, Bool())) - val buf_unsign = Wire(Vec(DEPTH, Bool())) - val buf_dual = Wire(Vec(DEPTH, Bool())) - val buf_samedw = Wire(Vec(DEPTH, Bool())) - val buf_nomerge = Wire(Vec(DEPTH, Bool())) - val buf_dualhi = Wire(Vec(DEPTH, Bool())) - val buf_dualtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - val buf_ldfwd = Wire(Vec(DEPTH, Bool())) - val buf_ldfwdtag = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - val buf_error = Wire(Vec(DEPTH, Bool())) - val buf_data = Wire(Vec(DEPTH, UInt(32.W))) - val buf_age = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_age_younger = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_rspage = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_rsp_pickage = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) + val ibuf_byteen = WireInit(UInt(4.W), 0.U) - val buf_nxtstate = Wire(Vec(DEPTH, UInt(3.W))) - val buf_rst = Wire(Vec(DEPTH, Bool())) - val buf_state_en = Wire(Vec(DEPTH, Bool())) - val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) - val buf_resp_state_bus_en = Wire(Vec(DEPTH, Bool())) - val buf_state_bus_en = Wire(Vec(DEPTH, Bool())) - val buf_dual_in = Wire(Vec(DEPTH, Bool())) - val buf_samedw_in = Wire(Vec(DEPTH, Bool())) - val buf_nomerge_in = Wire(Vec(DEPTH, Bool())) - val buf_sideeffect_in = Wire(Vec(DEPTH, Bool())) - val buf_unsign_in = Wire(Vec(DEPTH, Bool())) - val buf_sz_in = Wire(Vec(DEPTH, UInt(2.W))) - val buf_write_in = Wire(Vec(DEPTH, Bool())) - val buf_wr_en = Wire(Vec(DEPTH, Bool())) - val buf_dualhi_in = Wire(Vec(DEPTH, Bool())) - val buf_dualtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - val buf_ldfwd_en = Wire(Vec(DEPTH, Bool())) - val buf_ldfwd_in = Wire(Vec(DEPTH, Bool())) - val buf_ldfwdtag_in = Wire(Vec(DEPTH, UInt(DEPTH_LOG2.W))) - val buf_byteen_in = Wire(Vec(DEPTH, UInt(4.W))) - val buf_addr_in = Wire(Vec(DEPTH, UInt(32.W))) - val buf_data_in = Wire(Vec(DEPTH, UInt(32.W))) - val buf_error_en = Wire(Vec(DEPTH, Bool())) - val buf_data_en = Wire(Vec(DEPTH, Bool())) - val buf_age_in = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_ageQ = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_rspage_set = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_rspage_in = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) - val buf_rspageQ = Wire(Vec(DEPTH, Vec(DEPTH, Bool()))) + ld_byte_ibuf_hit_lo := Fill(4, ld_addr_ibuf_hit_lo) & ibuf_byteen & ldst_byteen_lo_m + ld_byte_ibuf_hit_hi := Fill(4, ld_addr_ibuf_hit_hi) & ibuf_byteen & ldst_byteen_hi_m - // Input buffer signals - val ibuf_valid = WireInit(Bool(), init = false.B) - val ibuf_dual = WireInit(Bool(), init = false.B) - val ibuf_samedw = WireInit(Bool(), init = false.B) - val ibuf_nomerge = WireInit(Bool(), init = false.B) - val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val ibuf_dualtag = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val ibuf_sideeffect = WireInit(Bool(), init = false.B) - val ibuf_unsign = WireInit(Bool(), init = false.B) - val ibuf_write = WireInit(Bool(), init = false.B) - val ibuf_sz = WireInit(UInt(2.W), init = 0.U) - val ibuf_byteen = WireInit(UInt(4.W), init = 0.U) - val ibuf_addr = WireInit(UInt(32.W), init = 0.U) - val ibuf_data = WireInit(UInt(32.W), init = 0.U) - val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), init = 0.U) - val ibuf_byp = WireInit(Bool(), init = false.B) - val ibuf_wr_en = WireInit(Bool(), init = false.B) - val ibuf_rst = WireInit(Bool(), init = false.B) - val ibuf_force_drain = WireInit(Bool(), init = false.B) - val ibuf_drain_vld = WireInit(Bool(), init = false.B) - val ibuf_drainvec_vld = Wire(Vec(DEPTH, Bool())) - val ibuf_tag_in = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val ibuf_dualtag_in = WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val ibuf_sz_in = WireInit(UInt(2.W), init = 0.U) - val ibuf_addr_in = WireInit(UInt(32.W), init = 0.U) - val ibuf_byteen_in = WireInit(UInt(4.W), init = 0.U) - val ibuf_data_in = WireInit(UInt(32.W), init = 0.U) - val ibuf_timer_in = WireInit(UInt(TIMER_LOG2.W), init = 0.U) - val ibuf_byteen_out = WireInit(UInt(4.W), init = 0.U) - val ibuf_data_out = WireInit(UInt(32.W), init = 0.U) - val ibuf_merge_en = WireInit(Bool(), init = false.B) - val ibuf_merge_in = WireInit(Bool(), init = false.B) + val buf_data = Wire(Vec(DEPTH, UInt(32.W))) + buf_data := buf_data.map(i=> 0.U) + val fwd_data = WireInit(UInt(32.W), 0.U) + val ld_fwddata_buf_lo_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_lo(i))).reverse.reduce(Cat(_,_)) + val ld_fwddata_buf_hi_initial = (0 until 4).map(i=>Fill(8, ld_byte_ibuf_hit_hi(i))).reverse.reduce(Cat(_,_)) + io.ld_fwddata_buf_lo := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_lo(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_lo_initial & ibuf_data) - // Output buffer signals - val obuf_valid = WireInit(Bool(), init = false.B) - val obuf_write = WireInit(Bool(), init = false.B) - val obuf_nosend = WireInit(Bool(), init = false.B) - val obuf_rdrsp_pend = WireInit(Bool(), init = false.B) - val obuf_sideeffect = WireInit(Bool(), init = false.B) - val obuf_addr = WireInit(UInt(32.W), init = 0.U) - val obuf_data = WireInit(UInt(64.W), init = 0.U) - val obuf_sz = WireInit(UInt(2.W), init = 0.U) - val obuf_byteen = WireInit(UInt(8.W), init = 0.U) - val obuf_merge = WireInit(Bool(), init = false.B) - val obuf_cmd_done = WireInit(Bool(), init = false.B) - val obuf_data_done = WireInit(Bool(), init = false.B) - val obuf_tag0 = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val obuf_tag1 = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val obuf_rdrsp_tag = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) + io.ld_fwddata_buf_hi := Cat((0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(3)(i)) & buf_data(i)(31, 24)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(2)(i)) & buf_data(i)(23, 16)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(1)(i)) & buf_data(i)(15, 8)).reduce(_ | _), + (0 until DEPTH).map(i => Fill(8, ld_byte_hitvecfn_hi(0)(i)) & buf_data(i)(7 , 0)).reduce(_ | _)) | + (ld_fwddata_buf_hi_initial & ibuf_data) - val ibuf_buf_byp = WireInit(Bool(), init = false.B) - val obuf_force_wr_en = WireInit(Bool(), init = false.B) - val obuf_wr_wait = WireInit(Bool(), init = false.B) - val obuf_wr_en = WireInit(Bool(), init = false.B) - val obuf_wr_enQ = WireInit(Bool(), init = false.B) - val obuf_rst = WireInit(Bool(), init = false.B) - val obuf_write_in = WireInit(Bool(), init = false.B) - val obuf_nosend_in = WireInit(Bool(), init = false.B) - val obuf_rdrsp_pend_in = WireInit(Bool(), init = false.B) - val obuf_sideeffect_in = WireInit(Bool(), init = false.B) - val obuf_aligned_in = WireInit(Bool(), init = false.B) - val obuf_addr_in = WireInit(UInt(64.W), init = 0.U) - val obuf_data_in = WireInit(UInt(64.W), init = 0.U) - val obuf_sz_in = WireInit(UInt(2.W), init = 0.U) - val obuf_byteen_in = WireInit(UInt(8.W), init = 0.U) - val obuf_merge_in = WireInit(Bool(), init = false.B) - val obuf_cmd_done_in = WireInit(Bool(), init = false.B) - val obuf_data_done_in = WireInit(Bool(), init = false.B) - val obuf_tag0_in = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val obuf_tag1_in = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val obuf_rdrsp_tag_in = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) + val bus_coalescing_disable = io.dec_tlu_wb_coalescing_disable | BUILD_AHB_LITE.B + val ldst_byteen_r = Mux1H(Seq(io.lsu_pkt_r.by -> 1.U(4.W), + io.lsu_pkt_r.half -> 3.U(4.W), + io.lsu_pkt_r.word -> 15.U(4.W))) - val obuf_merge_en = WireInit(Bool(), init = false.B) - val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), init = 0.U) - val obuf_wr_timer_in = WireInit(UInt(TIMER_LOG2.W), init = 0.U) - val obuf_byteen0_in = WireInit(UInt(8.W), init = 0.U) - val obuf_byteen1_in = WireInit(UInt(8.W), init = 0.U) - val obuf_data0_in = WireInit(UInt(64.W), init = 0.U) - val obuf_data1_in = WireInit(UInt(64.W), init = 0.U) + val ldst_byteen_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(4.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(3.W), ldst_byteen_r(3)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(2.W), ldst_byteen_r(3,2)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(1.W), ldst_byteen_r(3,1)))) + val ldst_byteen_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->ldst_byteen_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(ldst_byteen_r(2,0), 0.U), + (io.lsu_addr_r(1,0)===2.U)->Cat(ldst_byteen_r(1,0), 0.U(2.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(ldst_byteen_r(0) , 0.U(3.W)))) - val lsu_axi_awvalid_q = WireInit(Bool(), init = false.B) - val lsu_axi_awready_q = WireInit(Bool(), init = false.B) - val lsu_axi_wvalid_q = WireInit(Bool(), init = false.B) - val lsu_axi_wready_q = WireInit(Bool(), init = false.B) - val lsu_axi_arvalid_q = WireInit(Bool(), init = false.B) - val lsu_axi_arready_q = WireInit(Bool(), init = false.B) - val lsu_axi_bvalid_q = WireInit(Bool(), init = false.B) - val lsu_axi_bready_q = WireInit(Bool(), init = false.B) - val lsu_axi_rvalid_q = WireInit(Bool(), init = false.B) - val lsu_axi_rready_q = WireInit(Bool(), init = false.B) - val lsu_axi_bid_q = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val lsu_axi_rid_q = WireInit(UInt(pt1.LSU_BUS_TAG.W), init = 0.U) - val lsu_axi_bresp_q = WireInit(UInt(2.W), init = 0.U) - val lsu_axi_rresp_q = WireInit(UInt(2.W), init = 0.U) - val lsu_imprecise_error_store_tag= WireInit(UInt(DEPTH_LOG2.W), init = 0.U) - val lsu_axi_rdata_q = WireInit(UInt(64.W), init = 0.U) + val store_data_hi_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->0.U(32.W), + (io.lsu_addr_r(1,0)===1.U)->Cat(0.U(24.W) , io.store_data_r(31,24)), + (io.lsu_addr_r(1,0)===2.U)->Cat(0.U(16.W), io.store_data_r(31,16)), + (io.lsu_addr_r(1,0)===3.U)->Cat(0.U(8.W), io.store_data_r(31,8)))) -///////////// Initialization of vectors////////////////// - for (i <- 0 until DEPTH) { - CmdPtr0Dec (i) := 0.U - CmdPtr1Dec (i) := 0.U - RspPtrDec(i) := 0.U - buf_state(i) := idle_C - buf_sz(i) := 0.U - buf_addr(i) := 0.U - buf_byteen(i) := 0.U - buf_sideeffect(i) := 0.U - buf_write(i) := 0.U - buf_unsign(i) := 0.U - buf_dual(i) := 0.U - buf_samedw(i) := 0.U - buf_nomerge(i) := 0.U - buf_dualhi(i) := 0.U - buf_dualtag(i) := 0.U - buf_ldfwd(i) := 0.U - buf_ldfwdtag(i) := 0.U - buf_error(i) := 0.U - buf_data(i) := 0.U - buf_age(i) := (0 until DEPTH).map(j =>false.B) - buf_age_younger(i) := (0 until DEPTH).map(j =>false.B) - buf_rspage(i) := (0 until DEPTH).map(j =>false.B) - buf_rsp_pickage(i) := (0 until DEPTH).map(j =>false.B) + val store_data_lo_r = Mux1H(Seq((io.lsu_addr_r(1,0)===0.U)->io.store_data_r, + (io.lsu_addr_r(1,0)===1.U)->Cat(io.store_data_r(23,0), 0.U(8.W)), + (io.lsu_addr_r(1,0)===2.U)->Cat(io.store_data_r(15,0), 0.U(16.W)), + (io.lsu_addr_r(1,0)===3.U)->Cat(io.store_data_r(7 ,0) , 0.U(24.W)))) - buf_dual_in(i) := 0.U - buf_samedw_in(i) := 0.U - buf_nomerge_in(i) := 0.U - buf_sideeffect_in(i) := 0.U - buf_unsign_in(i) := 0.U - buf_sz_in(i) := 0.U - buf_write_in(i) := 0.U - buf_dualhi_in(i) := 0.U - buf_dualtag_in(i) := 0.U - buf_byteen_in(i) := 0.U - buf_addr_in(i) := 0.U - buf_age_in(i) := (0 until DEPTH).map(j =>false.B) - buf_ageQ(i) := (0 until DEPTH).map(j =>false.B) - buf_rspage_set(i) := (0 until DEPTH).map(j =>false.B) - buf_rspage_in(i) := (0 until DEPTH).map(j =>false.B) - buf_rspageQ(i) := (0 until DEPTH).map(j =>false.B) - ibuf_drainvec_vld(i) := 0.U - } -//////////////////////////////////////////////// + val ldst_samedw_r = io.lsu_addr_r(3) === io.end_addr_r(3) + val is_aligned_r = Mux1H(Seq(io.lsu_pkt_r.word -> (io.lsu_addr_r(1, 0) === 0.U), + io.lsu_pkt_r.half -> !io.lsu_addr_r(0), + io.lsu_pkt_r.by -> 1.U)) + val ibuf_byp = io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid + val ibuf_wr_en = io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp + val ibuf_drain_vld = WireInit(Bool(), false.B) + val ibuf_rst = (ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt + val ibuf_force_drain = io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31, 2) =/= io.lsu_addr_m(31, 2))) + val ibuf_sideeffect = WireInit(Bool(), false.B) + val ibuf_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val ibuf_merge_en = WireInit(Bool(), false.B) + val ibuf_merge_in = WireInit(Bool(), false.B) + ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === TIMER_MAX.U)) & !(ibuf_merge_en & ibuf_merge_in)) + | ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) + val ibuf_tag = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr1_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val WrPtr0_r = WireInit(UInt(DEPTH_LOG2.W), 0.U) -//////////////////////Buffer Hit Logic for load forwarding/////////////////// - ldst_byteen_hi_m := io.ldst_byteen_ext_m(7,4) - ldst_byteen_lo_m := io.ldst_byteen_ext_m(3,0) + val ibuf_tag_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_tag, Mux(io.ldst_dual_r, WrPtr1_r, WrPtr0_r)) + val ibuf_dualtag_in = WrPtr0_r + val ibuf_sz_in = Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half) + val ibuf_addr_in = Mux(io.ldst_dual_r, io.end_addr_r, io.lsu_addr_r) + val ibuf_byteen_in = Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3, 0) | ldst_byteen_lo_r(3, 0), + Mux(io.ldst_dual_r, ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) - ld_addr_ibuf_hit_lo := (io.lsu_addr_m(31,2) === ibuf_addr(31,2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m - ld_addr_ibuf_hit_hi := (io.end_addr_m(31,2) === ibuf_addr(31,2)) & ibuf_write & ibuf_valid & io.lsu_busreq_m - ld_byte_ibuf_hit_lo := (0 until 4).map(i =>(ld_addr_ibuf_hit_lo & ibuf_byteen(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_ibuf_hit_hi := (0 until 4).map(i =>(ld_addr_ibuf_hit_hi & ibuf_byteen(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + val ibuf_data_in = (0 until 4).map(i => Mux(ibuf_merge_en & ibuf_merge_in, + Mux(ldst_byteen_lo_r(i), store_data_lo_r((8 * i) + 7, 8 * i), ibuf_data((8 * i) + 7, 8 * i)), + Mux(io.ldst_dual_r, store_data_hi_r((8 * i) + 7, 8 * i), store_data_lo_r((8 * i) + 7, 8 * i)))).reverse.reduce(Cat(_, _)) + val ibuf_timer_in = Mux(ibuf_wr_en, 0.U, Mux((ibuf_timer((io.lsu_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_)) - ld_addr_hitvec_hi := (0 until DEPTH).map(i =>((io.end_addr_m(31,2) === buf_addr(i)(31,2)) & buf_write(i) & (buf_state(i) =/= idle_C) & io.lsu_busreq_m).asUInt).reverse.reduce(Cat(_,_)) + ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & (io.lsu_addr_r(31,2) === ibuf_addr(31,2)) & !io.is_sideeffects_r & !bus_coalescing_disable + ibuf_merge_in := !io.ldst_dual_r + val ibuf_byteen_out = (0 until 4).map(i=>(Mux(ibuf_merge_en & !ibuf_merge_in, ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) + val ibuf_data_out = (0 until 4).map(i=>Mux(ibuf_merge_en & !ibuf_merge_in, Mux(ldst_byteen_lo_r(i), store_data_lo_r((8*i)+7, 8*i), ibuf_data((8*i)+7, 8*i)), ibuf_data((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) - io.ld_byte_hit_buf_lo := (0 until 4).map(i =>(ld_byte_ibuf_hit_lo(i) | ld_byte_hitvecfn_lo(i).orR).asUInt).reverse.reduce(Cat(_,_)) - io.ld_byte_hit_buf_hi := (0 until 4).map(i =>(ld_byte_ibuf_hit_lo(i) | ld_byte_hitvecfn_lo(i).orR).asUInt).reverse.reduce(Cat(_,_)) + ibuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(ibuf_wr_en, true.B, ibuf_valid) & !ibuf_rst, false.B)} + ibuf_tag := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_tag_in, 0.U, ibuf_wr_en)} + val ibuf_dualtag = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_dualtag_in, 0.U, ibuf_wr_en)} + val ibuf_dual = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.ldst_dual_r, 0.U, ibuf_wr_en)} + val ibuf_samedw = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ldst_samedw_r, 0.U, ibuf_wr_en)} + val ibuf_nomerge = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.no_dword_merge_r, 0.U, ibuf_wr_en)} + ibuf_sideeffect := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.is_sideeffects_r, 0.U, ibuf_wr_en)} + val ibuf_unsign = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.unsign, 0.U, ibuf_wr_en)} + ibuf_write := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(io.lsu_pkt_r.store, 0.U, ibuf_wr_en)} + val ibuf_sz = withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_sz_in, 0.U, ibuf_wr_en)} + ibuf_addr := rvdffe(ibuf_addr_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_byteen := withClock(io.lsu_bus_ibuf_c1_clk) {RegEnable(ibuf_byteen_in, 0.U, ibuf_wr_en)} + ibuf_data := rvdffe(ibuf_data_in, ibuf_wr_en, clock, io.scan_mode) + ibuf_timer := withClock(io.lsu_free_c2_clk) {RegNext(ibuf_timer_in, 0.U)} + val buf_numvld_wrcmd_any = WireInit(UInt(4.W), 0.U) + val buf_numvld_cmd_any = WireInit(UInt(4.W), 0.U) + val obuf_wr_timer = WireInit(UInt(TIMER_LOG2.W), 0.U) + val buf_nomerge = Wire(Vec(DEPTH, Bool())) + buf_nomerge := buf_nomerge.map(i=> false.B) - ld_byte_hitvec_lo := (0 until 4).map(j =>(0 until DEPTH).map(i =>(ld_addr_hitvec_lo(i) & buf_byteen(i)(j) & ldst_byteen_lo_m(j)).asUInt).reverse.reduce(Cat(_,_))) - ld_byte_hitvec_hi := (0 until 4).map(j =>(0 until DEPTH).map(i =>(ld_addr_hitvec_hi(i) & buf_byteen(i)(j) & ldst_byteen_hi_m(j)).asUInt).reverse.reduce(Cat(_,_))) + val buf_sideeffect = WireInit(UInt(LSU_NUM_NBLOAD.W), 0.U) + val obuf_force_wr_en = WireInit(Bool(), false.B) + val obuf_wr_en = WireInit(Bool(), false.B) + val obuf_wr_wait = (buf_numvld_wrcmd_any===1.U) & (buf_numvld_cmd_any===1.U) & (obuf_wr_timer =/= TIMER_MAX.U) & + !bus_coalescing_disable & !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_nomerge(i))) & + !Mux1H((0 until math.pow(2,LSU_NUM_NBLOAD_WIDTH).asInstanceOf[Int]).map(i=>(CmdPtr0===i.U)->buf_sideeffect(i))) & !obuf_force_wr_en + val obuf_wr_timer_in = Mux(obuf_wr_en, 0.U(3.W), Mux(buf_numvld_cmd_any.orR & (obuf_wr_timer(CmdPtr0===i.U)->buf_addr(i)(31,2)))) + val buf_numvld_pend_any = WireInit(UInt(4.W), 0.U) + val ibuf_buf_byp = ibuf_byp & (buf_numvld_pend_any===0.U) & (!io.lsu_pkt_r.store | io.no_dword_merge_r) + val bus_sideeffect_pend = WireInit(Bool(), false.B) + val found_cmdptr0 = WireInit(Bool(), false.B) + val buf_cmd_state_bus_en = Wire(Vec(DEPTH, Bool())) + buf_cmd_state_bus_en := buf_cmd_state_bus_en.map(i=> false.B) + val buf_dual = Wire(Vec(DEPTH, Bool())) + buf_dual := buf_dual.map(i=> false.B) + val buf_samedw = Wire(Vec(DEPTH, Bool())) + buf_samedw := buf_samedw.map(i=> false.B) + val found_cmdptr1 = WireInit(Bool(), false.B) + val bus_cmd_ready = WireInit(Bool(), false.B) + val obuf_valid = WireInit(Bool(), false.B) + val obuf_nosend = WireInit(Bool(), false.B) + val lsu_bus_cntr_overflow = WireInit(Bool(), false.B) + val bus_addr_match_pending = WireInit(Bool(), false.B) + obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & !(io.is_sideeffects_r & bus_sideeffect_pend)) | + ((indexing(buf_state, CmdPtr0) === cmd_C) & + found_cmdptr0 & !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !(indexing(buf_sideeffect, CmdPtr0) & bus_sideeffect_pend) & + (!(indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_write, CmdPtr0)) | found_cmdptr1 | indexing(buf_nomerge.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) | + obuf_force_wr_en))) & (bus_cmd_ready | !obuf_valid | obuf_nosend) & !obuf_wr_wait & !lsu_bus_cntr_overflow & !bus_addr_match_pending & io.lsu_bus_clk_en + val bus_cmd_sent = WireInit(Bool(), false.B) + val obuf_rst = ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & !obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + val obuf_write_in = Mux(ibuf_buf_byp, io.lsu_pkt_r.store, indexing(buf_write, CmdPtr0)) + val obuf_sideeffect_in = Mux(ibuf_buf_byp, io.is_sideeffects_r, indexing(buf_sideeffect, CmdPtr0)) + val obuf_addr_in = Mux(ibuf_buf_byp, io.lsu_addr_r, indexing(buf_addr, CmdPtr0)) + val buf_sz = Wire(Vec(DEPTH, UInt(2.W))) + buf_sz := buf_sz.map(i=> 0.U) + val obuf_sz_in = Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half), indexing(buf_sz, CmdPtr0)) + val obuf_merge_en = WireInit(Bool(), false.B) + val obuf_merge_in = obuf_merge_en + val obuf_tag0_in = Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) + val Cmdptr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) - ld_byte_hitvecfn_lo := (0 until 4).map(j =>(0 until DEPTH).map(i =>(ld_byte_hitvec_lo(j)(i) & ~((ld_byte_hitvec_lo(j) & buf_age_younger(i).asUInt).orR) & ~ld_byte_ibuf_hit_lo(j)).asUInt).reverse.reduce(Cat(_,_))) - ld_byte_hitvecfn_hi := (0 until 4).map(j =>(0 until DEPTH).map(i =>(ld_byte_hitvec_hi(j)(i) & ~((ld_byte_hitvec_hi(j) & buf_age_younger(i).asUInt).orR) & ~ld_byte_ibuf_hit_hi(j)).asUInt).reverse.reduce(Cat(_,_))) + val obuf_tag1_in = Mux(ibuf_buf_byp, WrPtr1_r, Cmdptr1) + val obuf_cmd_done = WireInit(Bool(), false.B) + val bus_wcmd_sent = WireInit(Bool(), false.B) + val obuf_cmd_done_in = !(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent) + val obuf_data_done = WireInit(Bool(), false.B) + val bus_wdata_sent = WireInit(Bool(), false.B) + val obuf_data_done_in = !(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) + val obuf_aligned_in = Mux(ibuf_buf_byp, is_aligned_r, obuf_sz_in(1,0)===0.U | (obuf_sz_in(0) & !obuf_addr_in(0)) | (obuf_sz_in(1)&(!obuf_addr_in(1,0).orR))) - //Forwarding MUX - io.ld_fwddata_buf_lo := (0 until 4).map(i =>(Mux(ld_byte_ibuf_hit_lo(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_lo(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_)) - io.ld_fwddata_buf_hi := (0 until 4).map(i =>(Mux(ld_byte_ibuf_hit_hi(i),ibuf_data(i*8+7,i*8),Mux1H((0 until DEPTH).map(j =>(ld_byte_hitvecfn_hi(i)(j)) -> buf_data(j)(i*8+7,i*8)))))).reverse.reduce(Cat(_,_)) + val obuf_nosend_in = WireInit(Bool(), false.B) + val obuf_rdrsp_pend = WireInit(Bool(), false.B) + val bus_rsp_read = WireInit(Bool(), false.B) + val bus_rsp_read_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_write = WireInit(Bool(), false.B) + val obuf_rdrsp_pend_in = (!(obuf_wr_en & !obuf_nosend_in) & obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | + ((bus_cmd_sent & !obuf_write) & !io.dec_tlu_force_halt) + val obuf_tag0 = WireInit(UInt(LSU_BUS_TAG.W), 0.U) + val obuf_rdrsp_tag_in = Mux(bus_cmd_sent & !obuf_write, obuf_tag0, obuf_rdrsp_tag) + val obuf_addr = WireInit(UInt(32.W), 0.U) + val obuf_sideeffect = WireInit(Bool(), false.B) + obuf_nosend_in := (obuf_addr_in(31,3)===obuf_addr(31,3)) & obuf_aligned_in & !obuf_sideeffect & !obuf_write & !obuf_write_in & !io.dec_tlu_external_ldfwd_disable & + ((obuf_valid & !obuf_nosend) | (obuf_rdrsp_pend & !(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) + val obuf_byteen0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_byteen, CmdPtr0), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, CmdPtr0)))) + val obuf_byteen1_in = Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r, 0.U(4.W)), Cat(0.U(4.W), ldst_byteen_hi_r)), + Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_byteen, Cmdptr1), 0.U(4.W)), Cat(0.U(4.W),indexing(buf_byteen, Cmdptr1)))) -///////////////////////////////////////////////////////////////////////////// - bus_coalescing_disable := io.dec_tlu_wb_coalescing_disable | pt.BUILD_AHB_LITE - ldst_byteen_r := Mux1H(Seq( - io.lsu_pkt_r.word.asBool -> 15.U(4.W), - io.lsu_pkt_r.half.asBool -> 3.U(4.W), - io.lsu_pkt_r.by.asBool -> 1.U(4.W) - )) - val ldst_byteen_extended_r = Cat(Fill(4,0.U),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0) - val store_data_extended_r = Cat(Fill(32,0.U),io.store_data_r(31,0)) << (8.U*io.lsu_addr_r(1,0)) - ldst_byteen_hi_r := ldst_byteen_extended_r(7,4) - ldst_byteen_lo_r := ldst_byteen_extended_r(3,0) - store_data_hi_r := store_data_extended_r(63,32) - store_data_lo_r := store_data_extended_r(31, 0) - ldst_samedw_r := io.lsu_addr_r(3) === io.end_addr_r(3) - is_aligned_r := Mux1H(Seq( - io.lsu_pkt_r.by.asBool -> true.B, - io.lsu_pkt_r.half.asBool -> (io.lsu_addr_r(0).asUInt === 0.U), - io.lsu_pkt_r.word.asBool -> (io.lsu_addr_r(1,0).asUInt === 0.U) - )) -//////////////////////////////////////////////////////////////////////////// - ibuf_byp := (io.lsu_busreq_r & (io.lsu_pkt_r.load | io.no_word_merge_r) & !ibuf_valid).asBool - ibuf_wr_en := (io.lsu_busreq_r & io.lsu_commit_r & !ibuf_byp).asBool - ibuf_rst := ((ibuf_drain_vld & !ibuf_wr_en) | io.dec_tlu_force_halt).asBool - ibuf_force_drain := (io.lsu_busreq_m & !io.lsu_busreq_r & ibuf_valid & (io.lsu_pkt_m.load | (ibuf_addr(31,2) =/= io.lsu_addr_m(31,2)))).asBool - ibuf_drain_vld := ibuf_valid & (((ibuf_wr_en | (ibuf_timer === (TIMER_MAX.asUInt(TIMER_LOG2.W)))) & !(ibuf_merge_en & ibuf_merge_in)) | - ibuf_byp | ibuf_force_drain | ibuf_sideeffect | !ibuf_write | bus_coalescing_disable) - ibuf_tag_in := Mux((ibuf_merge_en & ibuf_merge_in), ibuf_tag(DEPTH_LOG2-1,0),Mux(io.ldst_dual_r,WrPtr1_r,WrPtr0_r)) - ibuf_dualtag_in := WrPtr0_r(DEPTH_LOG2-1,0) - ibuf_sz_in := Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half) - ibuf_addr_in := Mux(io.ldst_dual_r,io.end_addr_r,io.lsu_addr_r) - ibuf_byteen_in := Mux(ibuf_merge_en & ibuf_merge_in, ibuf_byteen(3,0) | ldst_byteen_lo_r(3,0), Mux(io.ldst_dual_r, ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0))) - ibuf_data_in := (0 until 4).map(i =>(Mux((ibuf_merge_en & ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),Mux(io.ldst_dual_r, store_data_hi_r((8*i)+7,(8*i)), store_data_lo_r((8*i)+7,(8*i)))))).reverse.reduce(Cat(_,_)) - ibuf_timer_in := Mux(ibuf_wr_en, 0.U, Mux(ibuf_timer < (TIMER_MAX.asUInt(TIMER_LOG2.W)), ibuf_timer+1.U, ibuf_timer)) - ibuf_byteen_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),ibuf_byteen(i) | ldst_byteen_lo_r(i), ibuf_byteen(i))).asUInt).reverse.reduce(Cat(_,_)) - ibuf_data_out := (0 until 4).map(i =>(Mux((ibuf_merge_en & ~ibuf_merge_in),Mux(ldst_byteen_lo_r(i),store_data_lo_r((8*i)+7,(8*i)) , ibuf_data((8*i)+7,(8*i))),ibuf_data(i*8+7,i*8)))).reverse.reduce(Cat(_,_)) - ibuf_merge_en := io.lsu_busreq_r & io.lsu_commit_r & io.lsu_pkt_r.store & ibuf_valid & ibuf_write & io.lsu_addr_r(31,2)===ibuf_addr(31,2) & ~io.is_sideeffects_r & ~bus_coalescing_disable - ibuf_merge_in := ~io.ldst_dual_r.asUInt() + val obuf_data0_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r, 0.U(32.W)), Cat(0.U(32.W), store_data_lo_r)), + Mux(indexing(buf_addr, CmdPtr0)(2).asBool(), Cat(indexing(buf_data, CmdPtr0), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, CmdPtr0)))) + val obuf_data1_in = Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r, 0.U(32.W)), Cat(0.U(32.W), store_data_hi_r)), + Mux(indexing(buf_addr, Cmdptr1)(2).asBool(), Cat(indexing(buf_data, Cmdptr1), 0.U(32.W)), Cat(0.U(32.W),indexing(buf_data, Cmdptr1)))) + val obuf_byteen_in = (0 until 8).map(i=>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) + val obuf_data_in = (0 until 8).map(i=>Mux(obuf_merge_en & obuf_byteen1_in(i), obuf_data1_in((8*i)+7, 8*i), obuf_data0_in((8*i)+7, 8*i))).reverse.reduce(Cat(_,_)) - withClock(io.lsu_free_c2_clk){ - ibuf_valid := RegNext(Mux(ibuf_wr_en.asBool(),1.U ,ibuf_valid) & !ibuf_rst, false.B) - ibuf_timer := RegNext(ibuf_timer_in ,init = 0.U) - } - withClock(io.lsu_bus_ibuf_c1_clk) { - ibuf_dual := RegEnable(io.ldst_dual_r ,init = 0.U, ibuf_wr_en) - ibuf_samedw := RegEnable(ldst_samedw_r ,init = 0.U, ibuf_wr_en) - ibuf_nomerge := RegEnable(io.no_dword_merge_r ,init = 0.U, ibuf_wr_en) - ibuf_sideeffect := RegEnable(io.is_sideeffects_r ,init = 0.U, ibuf_wr_en) - ibuf_unsign := RegEnable(io.lsu_pkt_r.unsign ,init = 0.U, ibuf_wr_en) - ibuf_write := RegEnable(io.lsu_pkt_r.store ,init = 0.U, ibuf_wr_en) - ibuf_sz := RegEnable(ibuf_sz_in(1, 0) ,init = 0.U, ibuf_wr_en) - ibuf_byteen := RegEnable(ibuf_byteen_in ,init = 0.U, ibuf_wr_en) - ibuf_addr := RegEnable(ibuf_addr_in(31, 0) ,init = 0.U, ibuf_wr_en) - ibuf_data := RegEnable(ibuf_data_in(31, 0) ,init = 0.U, ibuf_wr_en) - ibuf_tag := RegEnable(ibuf_tag_in ,init = 0.U, ibuf_wr_en) - ibuf_dualtag := RegEnable(ibuf_dualtag_in ,init = 0.U, ibuf_wr_en) - } -/////////////////////////////////////////////////////////////////////////////////////// + val buf_dualhi = Wire(Vec(DEPTH, Bool())) + buf_dualhi := buf_dualhi.map(i=> false.B) + obuf_merge_en := ((CmdPtr0 =/= Cmdptr1) & found_cmdptr0 & found_cmdptr1 & (indexing(buf_state, CmdPtr0) === cmd_C) & (indexing(buf_state, Cmdptr1) === cmd_C) & + !indexing(buf_cmd_state_bus_en.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_sideeffect, CmdPtr0) & + ((indexing(buf_write, CmdPtr0) & indexing(buf_write, Cmdptr1) & + (indexing(buf_addr, CmdPtr0)(31,3)===indexing(buf_addr, Cmdptr1)(31,3)) & !bus_coalescing_disable & !BUILD_AXI_NATIVE.B) | + (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0)))) | + (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) - ibuf_buf_byp := (ibuf_byp & (buf_numvld_pend_any(3,0) === 0.U) & (~io.lsu_pkt_r.store | io.no_dword_merge_r)) - obuf_force_wr_en := io.lsu_busreq_m & ~io.lsu_busreq_r & ~ibuf_valid & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (io.lsu_addr_m(31,2) =/= buf_addr(CmdPtr0)(31,2)) - obuf_wr_wait := (buf_numvld_wrcmd_any(3,0) === 1.U(4.W)) & (buf_numvld_cmd_any(3,0) === 1.U(4.W)) & (obuf_wr_timer =/= (TIMER_MAX.asUInt(TIMER_LOG2.W))) & - ~bus_coalescing_disable & ~buf_nomerge(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & ~obuf_force_wr_en - obuf_wr_en := ((ibuf_buf_byp & io.lsu_commit_r & ~(io.is_sideeffects_r & bus_sideeffect_pend)) | - ((buf_state(CmdPtr0) === cmd_C) & found_cmdptr0 & ~buf_cmd_state_bus_en(CmdPtr0) & ~(buf_sideeffect(CmdPtr0) & bus_sideeffect_pend) & - (~(buf_dual(CmdPtr0) & buf_samedw(CmdPtr0) & ~buf_write(CmdPtr0)) | found_cmdptr1 | buf_nomerge(CmdPtr0) | obuf_force_wr_en))) & - (bus_cmd_ready | ~obuf_valid | obuf_nosend) & ~obuf_wr_wait & ~lsu_bus_cntr_overflow & ~bus_addr_match_pending & io.lsu_bus_clk_en - obuf_rst := ((bus_cmd_sent | (obuf_valid & obuf_nosend)) & ~obuf_wr_en & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - obuf_write_in := Mux(ibuf_buf_byp, io.lsu_pkt_r.store, buf_write(CmdPtr0)) - obuf_nosend_in := (obuf_addr_in(31,3) === obuf_addr(31,3)) & obuf_aligned_in & ~obuf_sideeffect & ~obuf_write & ~obuf_write_in & ~io.dec_tlu_external_ldfwd_disable & - ((obuf_valid & ~obuf_nosend) | (obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)))) - obuf_rdrsp_pend_in := (~(obuf_wr_en & ~obuf_nosend_in) & obuf_rdrsp_pend & ~(bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag))) | ((bus_cmd_sent & ~obuf_write) & ~io.dec_tlu_force_halt) - obuf_sideeffect_in := Mux(ibuf_buf_byp, io.is_sideeffects_r, buf_sideeffect(CmdPtr0)) - obuf_aligned_in := Mux(ibuf_buf_byp, is_aligned_r, (obuf_sz_in(1,0) === 0.U(2.W) | (obuf_sz_in(0) & ~obuf_addr_in(0)) | (obuf_sz_in(1) & ~(obuf_addr_in(1,0).orR)))) - obuf_addr_in := Mux(ibuf_buf_byp, io.lsu_addr_r, buf_addr(CmdPtr0)) - obuf_data_in := (0 until 8).map(i =>(Mux((obuf_merge_en & obuf_byteen1_in(i)),obuf_data1_in((8*i)+7,(8*i)), obuf_data0_in((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) - obuf_sz_in := Mux(ibuf_buf_byp, Cat(io.lsu_pkt_r.word,io.lsu_pkt_r.half), buf_sz(CmdPtr0)) - obuf_byteen_in := (0 until 8).map(i =>(obuf_byteen0_in(i) | (obuf_merge_en & obuf_byteen1_in(i))).asUInt).reverse.reduce(Cat(_,_)) - obuf_merge_in := obuf_merge_en - obuf_cmd_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_cmd_done | bus_wcmd_sent ) - obuf_data_done_in := ~(obuf_wr_en | obuf_rst) & (obuf_data_done | bus_wdata_sent) - obuf_tag0_in := Mux(ibuf_buf_byp, WrPtr0_r, CmdPtr0) - obuf_tag1_in := Mux(ibuf_buf_byp, WrPtr1_r, CmdPtr0) - obuf_rdrsp_tag_in := Mux((bus_cmd_sent & ~obuf_write), obuf_tag0(pt1.LSU_BUS_TAG-1,0), obuf_rdrsp_tag(pt1.LSU_BUS_TAG-1,0)) + val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)} + obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)} + obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)} + obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)} + obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)} + obuf_rdrsp_pend := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_pend_in, false.B)} + obuf_rdrsp_tag := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_tag_in, 0.U)} + obuf_tag0 := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_tag0_in, 0.U, obuf_wr_en)} + val obuf_tag1 = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_tag1_in, 0.U, obuf_wr_en)} + val obuf_merge = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_merge_in, false.B, obuf_wr_en)} + obuf_write := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_write_in, false.B, obuf_wr_en)} + obuf_sideeffect := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_sideeffect_in, false.B, obuf_wr_en)} + val obuf_sz = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_sz_in, 0.U, obuf_wr_en)} + obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode) + val obuf_byteen = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_byteen_in, 0.U, obuf_wr_en)} + val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode) + obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)} + val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) - obuf_merge_en := ((CmdPtr0 =/= CmdPtr1) & found_cmdptr0 & found_cmdptr1 & (buf_state(CmdPtr0) === cmd_C) & (buf_state(CmdPtr1) === cmd_C) & - ~buf_cmd_state_bus_en(CmdPtr0) & ~buf_sideeffect(CmdPtr0) & - ((buf_write(CmdPtr0) & buf_write(CmdPtr1) & (buf_addr(CmdPtr0)(31,3) === buf_addr(CmdPtr1)(31,3)) & ~bus_coalescing_disable & ~pt.BUILD_AXI_NATIVE) | - (~buf_write(CmdPtr0) & buf_dual(CmdPtr0) & ~buf_dualhi(CmdPtr0) & buf_samedw(CmdPtr0)))) | - (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r) - obuf_wr_timer_in := Mux(obuf_wr_en, 0.U, Mux(((buf_numvld_cmd_any > 0.U(4.W)) & (obuf_wr_timer < TIMER_MAX.asUInt(TIMER_LOG2.W))), (obuf_wr_timer + 1.U), obuf_wr_timer)) - obuf_byteen0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(ldst_byteen_lo_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_lo_r(3,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_byteen(CmdPtr0),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr0)))) - obuf_byteen1_in := Mux(ibuf_buf_byp, Mux(io.end_addr_r(2), Cat(ldst_byteen_hi_r(3,0),0.U(4.W)), Cat(0.U(4.W),ldst_byteen_hi_r(3,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_byteen(CmdPtr1),0.U(4.W)), Cat(0.U(4.W),buf_byteen(CmdPtr1)))) - obuf_data0_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_lo_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_lo_r(31,0))), Mux(buf_addr(CmdPtr0)(2), Cat(buf_data(CmdPtr0), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr0)))) - obuf_data1_in := Mux(ibuf_buf_byp, Mux(io.lsu_addr_r(2), Cat(store_data_hi_r(31,0),0.U(32.W)), Cat(0.U(32.W),store_data_hi_r(31,0))), Mux(buf_addr(CmdPtr1)(2), Cat(buf_data(CmdPtr1), 0.U(32.W)), Cat(0.U(32.W), buf_data(CmdPtr1)))) + WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & + !((ibuf_valid & (ibuf_tag===i.U)) | (io.lsu_busreq_r & + ((WrPtr0_r === i.U) | (io.ldst_dual_r & (WrPtr1_r === i.U)))))) -> i.U)) - obuf_addr := RegEnable(obuf_addr_in , init = 0.U, obuf_wr_en) - obuf_data := RegEnable(obuf_data_in , init = 0.U, obuf_wr_en) - withClock(io.lsu_busm_clk){ - obuf_rdrsp_pend := RegNext(obuf_rdrsp_pend_in , init = 0.U) - obuf_rdrsp_tag := RegNext(obuf_rdrsp_tag_in , init = 0.U) - obuf_cmd_done := RegNext(obuf_cmd_done_in , init = 0.U) - obuf_data_done := RegNext(obuf_data_done_in , init = 0.U) - obuf_wr_timer := RegNext(obuf_wr_timer_in , init = 0.U) - obuf_wr_enQ := RegNext(obuf_wr_en , init = 0.U) - } - withClock(io.lsu_free_c2_clk){ - obuf_valid := RegNext(Mux(obuf_wr_en.asBool(),1.U ,obuf_valid) & !obuf_rst, false.B) - obuf_nosend := RegEnable(obuf_nosend_in , init = 0.U, obuf_wr_en) - } - withClock(io.lsu_bus_obuf_c1_clk){ - obuf_write := RegEnable(obuf_write_in , init = 0.U, obuf_wr_en) - obuf_sideeffect := RegEnable(obuf_sideeffect_in , init = 0.U, obuf_wr_en) - obuf_sz := RegEnable(obuf_sz_in , init = 0.U, obuf_wr_en) - obuf_byteen := RegEnable(obuf_byteen_in , init = 0.U, obuf_wr_en) - obuf_merge := RegEnable(obuf_merge_in , init = 0.U, obuf_wr_en) - obuf_tag0 := RegEnable(obuf_tag0_in , init = 0.U, obuf_wr_en) - obuf_tag1 := RegEnable(obuf_tag1_in , init = 0.U, obuf_wr_en) - } -//////////////////////////////////////////////////////////////////////////////////// - // WrPtr0_m := PriorityMux((0 until DEPTH).map(i =>(((buf_state(i)===IDLE.U) & !((ibuf_valid & (ibuf_tag====i.U)) | (io.lsu_busreq_r & ((WrPtr0_r === i) | (io.ldst_dual_r & (WrPtr1_r === i)))))).asBool -> i.asUInt(DEPTH_LOG2.W)))) - val test_seq = (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & ibuf_tag===i.U) | - (io.lsu_busreq_r & ((WrPtr0_r===i.U) | (io.ldst_dual_r & (WrPtr1_r===i.U)))))).asBool() -> i.U) - WrPtr0_m := MuxCase(0.U, test_seq) - val test_seq2 = (0 until DEPTH).map(i=>((buf_state(i) === idle_C) & !((ibuf_valid & (ibuf_tag === i.U)) | - (io.lsu_busreq_m & (WrPtr0_m === i.U)) | (io.lsu_busreq_r & (WrPtr0_r === i.U) | - (io.ldst_dual_r & (WrPtr1_r === i.U))))).asBool -> i.U) - WrPtr1_m := MuxCase(0.U, test_seq2) + val WrPtr1_m = WireInit(UInt(DEPTH_LOG2.W), 0.U) + WrPtr1_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) & !((ibuf_valid & (ibuf_tag===i.U)) | + (io.lsu_busreq_m & (WrPtr0_m===i.U)) | + (io.lsu_busreq_r & (((WrPtr0_r === i.U)) | + (io.ldst_dual_r & (WrPtr1_r===i.U)))))) -> i.U)) - for { - i <- 0 until DEPTH - j <- 0 until DEPTH - }{ - CmdPtr0Dec(i) := ~(buf_age(i).asUInt.orR()) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) - CmdPtr1Dec(i) := ~((buf_age(i).asUInt & ~CmdPtr0Dec.asUInt).orR()) & ~CmdPtr0Dec(i) & (buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) - RspPtrDec(i) := ~(buf_rsp_pickage(i).asUInt.orR()) & (buf_state(i) === done_wait_C) + val buf_age = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_age := buf_age.map(i=> 0.U) - buf_age_in(i)(j) := (((buf_state(i) === idle_C) & buf_state_en(i)) & - (((buf_state(j) === wait_C) | ((buf_state(j) === cmd_C) & ~buf_cmd_state_bus_en(j))) | - (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) | - (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r)))) | buf_age(i)(j) + val CmdPtr0Dec = (0 until DEPTH).map(i=> (!(buf_age(i).orR) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val CmdPtr1Dec = (0 until DEPTH).map(i=> (!((buf_age(i) & (~CmdPtr0Dec)).orR) & !CmdPtr0Dec(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(Cat(_,_)) + val buf_rsp_pickage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rsp_pickage := buf_rsp_pickage.map(i=> 0.U) + val RspPtrDec = (0 until DEPTH).map(i=> (!(buf_rsp_pickage(i).orR) & (buf_state(i)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_)) + found_cmdptr0 := CmdPtr0Dec.orR + found_cmdptr1 := CmdPtr1Dec.orR - buf_age(i)(j) := buf_ageQ(i)(j) & ~((buf_state(j) === cmd_C) & buf_cmd_state_bus_en(j)) - buf_age_younger(i)(j) := Mux(i.asUInt(DEPTH_LOG2.W) === j.asUInt(DEPTH_LOG2.W), 0.U, (~buf_age(i)(j) & (buf_state(j) =/= idle_C))) + def Enc8x3(in: UInt) : UInt = Cat(in(4)|in(5)|in(6)|in(7), in(2)|in(3)|in(6)|in(7), in(1)|in(3)|in(5)|in(7)) - buf_rspage_set(i)(j) := ((buf_state(i) === idle_C) & buf_state_en(i)) & (~((buf_state(j) === idle_C) | (buf_state(j) === done_C)) | - (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (i === WrPtr0_r) & (j === ibuf_tag)) | - (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (i === WrPtr1_r) & (j === WrPtr0_r))) - buf_rspage_in(i)(j) := buf_rspage_set(i)(j) | buf_rspage(i)(j) - buf_rspage(i)(j) := buf_rspageQ(i)(j) & ~((buf_state(j) === done_C) | (buf_state(j) === idle_C)) - buf_rsp_pickage(i)(j) := buf_rspageQ(i)(j) & (buf_state(j) === done_wait_C) + + val CmdPtr1 = WireInit(UInt(DEPTH_LOG2.W), 0.U) + val RspPtr = WireInit(UInt(DEPTH_LOG2.W), 0.U) + CmdPtr0 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr0Dec)) + + CmdPtr1 := Enc8x3(Cat(Fill(8-DEPTH, 0.U),CmdPtr1Dec)) + RspPtr := Enc8x3(Cat(Fill(8-DEPTH, 0.U),RspPtrDec)) + val buf_state_en = Wire(Vec(DEPTH, Bool())) + buf_state_en := buf_state_en.map(i=> false.B) + val buf_rspageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspageQ := buf_rspageQ.map(i=> 0.U) + val buf_rspage_set = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_set := buf_rspage_set.map(i=> 0.U) + val buf_rspage_in = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage_in := buf_rspage_in.map(i=> 0.U) + val buf_rspage = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_rspage := buf_rspage.map(i=> 0.U) + + val buf_age_in = (0 until DEPTH).map(i=>(0 until DEPTH).map(j=> ((((buf_state(i)===idle_C) & buf_state_en(i)) & + (((buf_state(j)===wait_C) | ((buf_state(j)===cmd_C) & !buf_cmd_state_bus_en(j))) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r === i.U) & (ibuf_tag === j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r === i.U) & (WrPtr0_r === j.U)))) | buf_age(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + val buf_ageQ = Wire(Vec(DEPTH, UInt(DEPTH.W))) + buf_ageQ := buf_ageQ.map(i=> 0.U) + buf_age := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_ageQ(i)(j) & !((buf_state(j)===cmd_C) & buf_cmd_state_bus_en(j))).asUInt).reverse.reduce(Cat(_,_))) + buf_age_younger := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(Mux(i.U===j.U, 0.U, !buf_age(i)(j) & (buf_state(j)=/=idle_C))).asUInt).reverse.reduce(Cat(_,_))) + buf_rsp_pickage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & (buf_state(j)===done_wait_C)).asUInt).reverse.reduce(Cat(_,_))) + + buf_rspage_set := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(((buf_state(i)===idle_C) & buf_state_en(i)) & + (!((buf_state(j)===idle_C) | (buf_state(j)===done_C)) | + (ibuf_drain_vld & io.lsu_busreq_r & (ibuf_byp | io.ldst_dual_r) & (WrPtr0_r===i.U) & (ibuf_tag===j.U)) | + (ibuf_byp & io.lsu_busreq_r & io.ldst_dual_r & (WrPtr1_r===i.U) & (WrPtr0_r===j.U)))).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage_in := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspage_set(i)(j) | buf_rspage(i)(j)).asUInt).reverse.reduce(Cat(_,_))) + buf_rspage := (0 until DEPTH).map(i=>(0 until DEPTH).map(j=>(buf_rspageQ(i)(j) & !((buf_state(j)===done_C) | (buf_state(j)===idle_C))).asUInt).reverse.reduce(Cat(_,_))) + + + + + ibuf_drainvec_vld := (0 until DEPTH).map(i=>(ibuf_drain_vld & (ibuf_tag === i.U)).asUInt).reverse.reduce(Cat(_,_)) + buf_byteen_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), + Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), ldst_byteen_hi_r(3,0), ldst_byteen_lo_r(3,0)))) + buf_addr_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_addr, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), io.end_addr_r, io.lsu_addr_r))) + buf_dual_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_samedw_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_nomerge_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_nomerge | ibuf_force_drain, io.no_dword_merge_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_dualhi_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_dual ,ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U))).asUInt).reverse.reduce(Cat(_,_)) + buf_dualtag_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux(ibuf_byp & io.ldst_dual_r & (WrPtr1_r===i.U), WrPtr0_r, WrPtr1_r))) + buf_sideeffect_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r)).asUInt).reverse.reduce(Cat(_,_)) + buf_unsign_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign)).asUInt).reverse.reduce(Cat(_,_)) + buf_sz_in := (0 until DEPTH).map(i=>Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half))) + buf_write_in := (0 until DEPTH).map(i=>(Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store)).asUInt).reverse.reduce(Cat(_,_)) + + for(i<- 0 until DEPTH) { + switch(buf_state(i)) { + is(idle_C) { + buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) + buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) + buf_wr_en(i) := buf_state_en(i) + buf_data_en(i) := buf_state_en(i) + buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) + } + is(wait_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) + buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt + } + is(cmd_C) { + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) + buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ + buf_state_bus_en(i) := buf_cmd_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_ldfwd_in(i) := true.B + buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt + buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(LSU_BUS_TAG - 2, 0)).asUInt + buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error + buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31, 0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) + } + is(resp_C) { + buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & !(BUILD_AXI_NATIVE.B & bus_rsp_write_error))).asBool(), idle_C, + Mux((buf_dual(i) & !buf_samedw(i) & !buf_write(i) & (buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, + Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & !buf_samedw(i) & !buf_write(i) & indexing(buf_ldfwd,buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) + buf_resp_state_bus_en(i) := (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W))) | + (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | + (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) + buf_state_bus_en(i) := buf_resp_state_bus_en(i) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en + buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(LSU_BUS_TAG.W)))) | + (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | + (bus_rsp_write_error & BUILD_AXI_NATIVE.B & (bus_rsp_write_tag === i.asUInt(LSU_BUS_TAG.W)))) + buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) + } + is(done_partial_C) { // Other part of dual load hasn't returned + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) + buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | + (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) + buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt + } + is(done_wait_C) { // WAIT state if there are multiple outstanding nb returns + buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) + buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) | (buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt + } + is(done_C) { + buf_nxtstate(i) := idle_C + buf_rst(i) := 1.U + buf_state_en(i) := 1.U + buf_ldfwd_in(i) := false.B + buf_ldfwd_en(i) := buf_state_en(i) + } + } + buf_state(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nxtstate(i), 0.U, buf_state_en(i).asBool())} + buf_ageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_age_in(i), 0.U)} + buf_rspageQ(i) := withClock(io.lsu_bus_buf_c1_clk){RegNext(buf_rspage_in(i), 0.U)} + buf_dualtag(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualtag_in(i), 0.U, buf_wr_en(i).asBool())} + buf_dual(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dual_in(i), false.B, buf_wr_en(i).asBool())} + buf_samedw(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_samedw_in(i), false.B, buf_wr_en(i).asBool())} + buf_nomerge(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_nomerge_in(i), false.B, buf_wr_en(i).asBool())} + buf_dualhi(i) := withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_dualhi_in(i), false.B, buf_wr_en(i).asBool())} } - CmdPtr0 := PriorityEncoderOH(CmdPtr0Dec.asUInt) - CmdPtr1 := PriorityEncoderOH(CmdPtr1Dec.asUInt) - RspPtr := PriorityEncoderOH(RspPtrDec.asUInt) - found_cmdptr0 := CmdPtr0Dec.reduce(_|_) - found_cmdptr1 := CmdPtr1Dec.reduce(_|_) - -////////////////////////// FSM /////////////////////////////////////// - for (i <- 0 until DEPTH){ - buf_nxtstate(i) := idle_C - buf_state_en(i) := 0.U - buf_cmd_state_bus_en(i) := 0.U - buf_resp_state_bus_en(i) := 0.U - buf_state_bus_en(i) := 0.U - buf_wr_en(i) := 0.U - buf_data_in(i) := 0.U - buf_data_en(i) := 0.U - buf_error_en(i) := 0.U - buf_rst(i) := 0.U - buf_ldfwd_en(i) := 0.U - buf_ldfwd_in(i) := 0.U - buf_ldfwdtag_in(i) := 0.U - - ibuf_drainvec_vld(i) := (ibuf_drain_vld & (i === ibuf_tag)) - buf_byteen_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_byteen_out(3,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), ldst_byteen_hi_r(3, 0), ldst_byteen_lo_r(3, 0))) - buf_addr_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_addr(31,0), Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), io.end_addr_r(31, 0), io.lsu_addr_r(31, 0))) - buf_dual_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, io.ldst_dual_r) - buf_samedw_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_samedw, ldst_samedw_r) - buf_nomerge_in(i) := Mux(ibuf_drainvec_vld(i), (ibuf_nomerge | ibuf_force_drain), io.no_dword_merge_r) - buf_dualhi_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dual, (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r))) - buf_dualtag_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_dualtag, Mux((ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)).asBool(), WrPtr0_r, WrPtr1_r)) - buf_sideeffect_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sideeffect, io.is_sideeffects_r) - buf_unsign_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_unsign, io.lsu_pkt_r.unsign) - buf_sz_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_sz, Cat(io.lsu_pkt_r.word, io.lsu_pkt_r.half)) - buf_write_in(i) := Mux(ibuf_drainvec_vld(i), ibuf_write, io.lsu_pkt_r.store) - - // Buffer entry state machine - switch (buf_state(i)){ - is (idle_C) { - buf_nxtstate(i) := Mux(io.lsu_bus_clk_en.asBool(), cmd_C, wait_C) - buf_state_en(i) := (io.lsu_busreq_r & io.lsu_commit_r & (((ibuf_byp | io.ldst_dual_r) & !ibuf_merge_en & (i === WrPtr0_r)) | (ibuf_byp & io.ldst_dual_r & (i === WrPtr1_r)))) | (ibuf_drain_vld & (i === ibuf_tag)) - buf_wr_en(i) := buf_state_en(i) - buf_data_en(i) := buf_state_en(i) - buf_data_in(i) := Mux((ibuf_drain_vld & (i === ibuf_tag)).asBool(), ibuf_data_out(31, 0), store_data_lo_r(31, 0)) - } - is (wait_C) { - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, cmd_C) - buf_state_en(i) := io.lsu_bus_clk_en | io.dec_tlu_force_halt - } - is (cmd_C) { - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((obuf_nosend & bus_rsp_read & (bus_rsp_read_tag === obuf_rdrsp_tag)), done_wait_C, resp_C)) - buf_cmd_state_bus_en(i) := ((obuf_tag0 === i.asUInt(pt1.LSU_BUS_TAG.W)) | (obuf_merge & (obuf_tag1 === i.asUInt(pt1.LSU_BUS_TAG.W)))) & obuf_valid & obuf_wr_enQ - buf_state_bus_en(i) := buf_cmd_state_bus_en(i) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - buf_ldfwd_in(i) := 1.U(1.W) - buf_ldfwd_en(i) := buf_state_en(i) & !buf_write(i) & obuf_nosend & !io.dec_tlu_force_halt - buf_ldfwdtag_in(i) := (obuf_rdrsp_tag(pt1.LSU_BUS_TAG - 2,0)).asUInt - buf_data_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read - buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & obuf_nosend & bus_rsp_read_error - buf_data_in(i) := Mux(buf_error_en(i), bus_rsp_rdata(31,0), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0))) - } - is (resp_C){ - buf_nxtstate(i) := Mux((io.dec_tlu_force_halt | (buf_write(i) & ~(pt.BUILD_AXI_NATIVE & bus_rsp_write_error))).asBool(), idle_C, - Mux((buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) &(buf_state(buf_dualtag(i)) =/= done_partial_C)), done_partial_C, - Mux((buf_ldfwd(i) | any_done_wait_state | (buf_dual(i) & ~ buf_samedw(i) & ~ buf_write(i) & buf_ldfwd(buf_dualtag(i)) & (buf_state(buf_dualtag(i)) === done_partial_C) & any_done_wait_state)), done_wait_C, done_C))) - buf_resp_state_bus_en(i):= (bus_rsp_write & (bus_rsp_write_tag === (i.asUInt(pt1.LSU_BUS_TAG.W)))) | - (bus_rsp_read & ((bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) | - (buf_ldfwd(i) & (bus_rsp_read_tag === (buf_ldfwdtag(i)))) | - (buf_dual(i) & buf_dualhi(i) & ~buf_write(i) & buf_samedw(i) & (bus_rsp_read_tag === (buf_dualtag(i)))))) - buf_state_bus_en(i) := buf_resp_state_bus_en(i) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - buf_data_en(i) := buf_state_bus_en(i) & bus_rsp_read & io.lsu_bus_clk_en - buf_error_en(i) := buf_state_bus_en(i) & io.lsu_bus_clk_en & ((bus_rsp_read_error & (bus_rsp_read_tag === (i.asUInt(pt1.LSU_BUS_TAG.W))) ) | - (bus_rsp_read_error & buf_ldfwd(i) & (bus_rsp_read_tag === buf_ldfwdtag(i))) | - (bus_rsp_write_error & pt.BUILD_AXI_NATIVE & (bus_rsp_write_tag === i.asUInt(pt1.LSU_BUS_TAG.W)))) - buf_data_in(i) := Mux((buf_state_en(i) & !buf_error_en(i)), Mux(buf_addr(i)(2), bus_rsp_rdata(63, 32), bus_rsp_rdata(31, 0)), bus_rsp_rdata(31, 0)) - } - is (done_partial_C){ // Other part of dual load hasn't returned - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, Mux((buf_ldfwd(i) | buf_ldfwd(buf_dualtag(i)) | any_done_wait_state), done_wait_C, done_C)) - buf_state_bus_en(i) := bus_rsp_read & ((bus_rsp_read_tag === buf_dualtag(i).asUInt()) | - (buf_ldfwd(buf_dualtag(i)) & (bus_rsp_read_tag === buf_ldfwdtag(buf_dualtag(i)).asUInt()))) - buf_state_en(i) := (buf_state_bus_en(i) & io.lsu_bus_clk_en) | io.dec_tlu_force_halt - } - is (done_wait_C) { // WAIT state if there are multiple outstanding nb returns - buf_nxtstate(i) := Mux(io.dec_tlu_force_halt.asBool(), idle_C, done_C) - buf_state_en(i) := ((RspPtr === i.asUInt(DEPTH_LOG2.W)) |(buf_dual(i) & (buf_dualtag(i) === RspPtr))) | io.dec_tlu_force_halt - } - is (done_C) { - buf_nxtstate(i) := idle_C - buf_rst(i) := 1.U - buf_state_en(i) := 1.U - buf_ldfwd_in(i) := 0.U - buf_ldfwd_en(i) := buf_state_en(i) - } - } - - buf_byteen(i) := RegEnable(buf_byteen_in(i) , init = 0.U ,buf_wr_en(i)) - buf_data(i) := RegEnable(buf_data_in(i) , init = 0.U ,buf_data_en(i)) - withClock(io.lsu_bus_buf_c1_clk){ - buf_state(i) := RegEnable(buf_nxtstate(i) , init = idle_C ,buf_state_en(i)) - buf_dualtag(i) := RegEnable(buf_dualtag_in(i) , init = 0.U ,buf_wr_en(i)) - buf_dual(i) := RegEnable(buf_dual_in(i) , init = 0.U ,buf_wr_en(i)) - buf_samedw(i) := RegEnable(buf_samedw_in(i) , init = 0.U ,buf_wr_en(i)) - buf_nomerge(i) := RegEnable(buf_nomerge_in(i) , init = 0.U ,buf_wr_en(i)) - buf_dualhi(i) := RegEnable(buf_dualhi_in(i) , init = 0.U ,buf_wr_en(i)) - buf_sideeffect(i) := RegEnable(buf_sideeffect_in(i) , init = 0.U ,buf_wr_en(i)) - buf_unsign(i) := RegEnable(buf_unsign_in(i) , init = 0.U ,buf_wr_en(i)) - buf_write(i) := RegEnable(buf_write_in(i) , init = 0.U ,buf_wr_en(i)) - buf_sz(i) := RegEnable(buf_sz_in(i) , init = 0.U ,buf_wr_en(i)) - buf_addr(i) := RegEnable(buf_addr_in(i) , init = 0.U ,buf_wr_en(i)) - buf_ldfwd(i) := RegEnable(buf_ldfwd_in(i) , init = 0.U ,buf_ldfwd_en(i)) - buf_ldfwdtag(i) := RegEnable(buf_ldfwdtag_in(i) , init = 0.U ,buf_ldfwd_en(i)) - buf_error(i) := RegEnable(~buf_rst(i) , init = 0.U ,(buf_error_en(i)|buf_rst(i)).asBool) - buf_ageQ(i) := RegNext(buf_age_in(i) , init = VecInit((0 until 4).map(i=>false.B))) - buf_rspageQ(i) := RegNext(buf_rspage_in(i) , init = VecInit((0 until 4).map(i=>false.B))) - } - } - -////////////////////////////////////////////////////////////////////////////////// - buf_numvld_any := (io.lsu_busreq_m << io.ldst_dual_m) + (io.lsu_busreq_r << io.ldst_dual_r) + ibuf_valid + - {for(i <- 0 until DEPTH) yield ( buf_state(i) =/= idle_C).asUInt }.reduce(_+_) - buf_numvld_wrcmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i) & buf_write(i)).asUInt }.reduce(_+_) - buf_numvld_cmd_any := {for(i <- 0 until DEPTH) yield (( buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)).asUInt }.reduce(_+_) - buf_numvld_pend_any := {for(i <- 0 until DEPTH) yield (((buf_state(i) === cmd_C) & ~buf_cmd_state_bus_en(i)) | (buf_state(i) === wait_C)).asUInt }.reduce(_+_) - any_done_wait_state := {for(i <- 0 until DEPTH) yield buf_state(i) === done_wait_C }.reduce(_|_) - - io.lsu_bus_buffer_pend_any := buf_numvld_pend_any =/= 0.U - io.lsu_bus_buffer_full_any := Mux((io.ldst_dual_d & io.dec_lsu_valid_raw_d),buf_numvld_any(3,0) >= (DEPTH-1).asUInt(4.W), buf_numvld_any(3,0) === DEPTH.asUInt(4.W)) - io.lsu_bus_buffer_empty_any := ~((0 until DEPTH).map(i =>(buf_state(i)).asUInt).reduce(_|_)) & ~ibuf_valid & ~obuf_valid - - io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & ~io.flush_m_up & ~ io.ld_full_hit_m - io.lsu_nonblock_load_tag_m := WrPtr0_m(DEPTH_LOG2-1,0) - io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & ~io.lsu_commit_r - io.lsu_nonblock_load_inv_tag_r := WrPtr0_r(DEPTH_LOG2-1,0) - - lsu_nonblock_load_data_ready := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C) -> ~(pt.BUILD_AXI_NATIVE & buf_write(i)))) - io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i)) -> (buf_error(i)))) - io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & (~buf_dual(i) | ~buf_dualhi(i)) & ~buf_write(i)) -> intToUInt(i))) - lsu_nonblock_load_data_lo := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & (~buf_dual(i) | ~buf_dualhi(i))) -> buf_data(i))) - lsu_nonblock_load_data_hi := Mux1H((0 until DEPTH).map(i =>(buf_state(i) === done_C & ~buf_write(i) & ( buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) - - lsu_nonblock_addr_offset := buf_addr(io.lsu_nonblock_load_data_tag)(1,0) - lsu_nonblock_sz := buf_sz(io.lsu_nonblock_load_data_tag)(1,0) - lsu_nonblock_unsign := buf_unsign(io.lsu_nonblock_load_data_tag) - lsu_nonblock_dual := buf_dual(io.lsu_nonblock_load_data_tag) - lsu_nonblock_data_unalgn := (Cat(lsu_nonblock_load_data_hi(31,0), lsu_nonblock_load_data_lo(31,0)) >> 8*lsu_nonblock_addr_offset(1,0))(31,0) - io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & ~io.lsu_nonblock_load_data_error - io.lsu_nonblock_load_data := Mux1H(Seq( - (lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,0.U(1.W)),lsu_nonblock_data_unalgn(7,0)), - (lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,0.U(1.W)),lsu_nonblock_data_unalgn(15,0)), - (~lsu_nonblock_unsign & lsu_nonblock_sz === 0.U) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)),lsu_nonblock_data_unalgn(7,0)), - (~lsu_nonblock_unsign & lsu_nonblock_sz === 1.U) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)),lsu_nonblock_data_unalgn(15,0)), - (lsu_nonblock_unsign & lsu_nonblock_sz === 2.U) -> lsu_nonblock_data_unalgn(31,0) - )) - bus_sideeffect_pend := Mux(obuf_valid,obuf_sideeffect & io.dec_tlu_sideeffect_posted_disable,Mux1H((0 until DEPTH).map(i =>(buf_state(i) === resp_C) -> (buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable)))) - bus_addr_match_pending := Mux1H((0 until DEPTH).map(i =>(pt.BUILD_AXI_NATIVE & obuf_valid & (obuf_addr(31,3) === buf_addr(i)(31,3))).asBool -> ((buf_state(i) === resp_C) & ~((obuf_tag0 === intToUInt(i)) | (obuf_merge & (obuf_tag1 === intToUInt(i))))))) - - bus_cmd_ready := Mux(obuf_write, Mux((obuf_cmd_done | obuf_data_done), Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), (io.lsu_axi_awready & io.lsu_axi_wready)), io.lsu_axi_arready) - bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready - bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready - bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready) - - bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready - bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready - bus_rsp_read_tag := io.lsu_axi_rid(pt1.LSU_BUS_TAG-1,0) - bus_rsp_write_tag := io.lsu_axi_bid(pt1.LSU_BUS_TAG-1,0) - bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp(1,0) =/= 0.U(2.W)) - bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_rresp(1,0) =/= 0.U(2.W)) - bus_rsp_rdata := io.lsu_axi_rdata(63,0) -////////////////////////////////////////////////////////////////////////////////// - lsu_axi_rdata_q := RegEnable(io.lsu_axi_rdata, init = 0.U, io.lsu_axi_rvalid&io.lsu_bus_clk_en) - withClock(io.lsu_c2_r_clk){ - io.lsu_busreq_r := RegNext((io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m), 0.U) - WrPtr0_r := RegNext(WrPtr0_m, init = 0.U) - WrPtr1_r := RegNext(WrPtr1_m, init = 0.U) - lsu_nonblock_load_valid_r := RegNext(io.lsu_nonblock_load_valid_m, init = 0.U) - } - withClock(io.lsu_busm_clk){ - lsu_axi_awvalid_q := RegNext(io.lsu_axi_awvalid, init = 0.U) - lsu_axi_awready_q := RegNext(io.lsu_axi_awready, init = 0.U) - lsu_axi_wvalid_q := RegNext(io.lsu_axi_wvalid, init = 0.U) - lsu_axi_wready_q := RegNext(io.lsu_axi_wready, init = 0.U) - lsu_axi_arvalid_q := RegNext(io.lsu_axi_arvalid, init = 0.U) - lsu_axi_arready_q := RegNext(io.lsu_axi_arready, init = 0.U) - lsu_axi_bvalid_q := RegNext(io.lsu_axi_bvalid, init = 0.U) - lsu_axi_bready_q := RegNext(io.lsu_axi_bready, init = 0.U) - lsu_axi_rvalid_q := RegNext(io.lsu_axi_rvalid, init = 0.U) - lsu_axi_rready_q := RegNext(io.lsu_axi_rready, init = 0.U) - lsu_axi_bid_q := RegNext(io.lsu_axi_bid, init = 0.U) - lsu_axi_rid_q := RegNext(io.lsu_axi_rid, init = 0.U) - lsu_axi_bresp_q := RegNext(io.lsu_axi_bresp, init = 0.U) - lsu_axi_rresp_q := RegNext(io.lsu_axi_rresp, init = 0.U) - } -/////////////////////////////////////////////////////////////////////////////////// - - io.ld_fwddata_buf_lo := 0.U - io.ld_fwddata_buf_hi := 0.U - - lsu_imprecise_error_store_tag := Mux1H((0 until DEPTH).map(i =>(((buf_state(i) === done_C) & buf_error(i) & buf_write(i)) -> intToUInt(i)))) - io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & ~io.lsu_imprecise_error_store_any - io.lsu_imprecise_error_store_any := {for(i <- 0 until DEPTH) yield io.lsu_bus_clk_en_q & (buf_state(i) === done_C) & buf_error(i) & buf_write(i)}.reduce(_|_) - io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag)) - - bus_pend_trxnQ := 0.U(8.W) - bus_pend_trxn := 0.U(8.W) - bus_pend_trxn_ns := 0.U(8.W) - lsu_bus_cntr_overflow := 0.U(1.W) - io.lsu_bus_idle_any := true.B - - io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready) - io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r - io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any - io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & ~io.lsu_axi_awready | (io.lsu_axi_wvalid & ~io.lsu_axi_wready) | (io.lsu_axi_arvalid & ~io.lsu_axi_arready)) - - io.lsu_axi_awvalid := obuf_valid & obuf_write & ~obuf_cmd_done & ~bus_addr_match_pending - io.lsu_axi_awid := obuf_tag0.asUInt - io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr,Cat(obuf_addr(31,3),0.U(3.W))) - io.lsu_axi_awregion := obuf_addr(31,28) - io.lsu_axi_awlen := 0.U(8.W) - io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(false.B,obuf_sz),3.U(3.W)) - io.lsu_axi_awburst := 1.U(2.W) - io.lsu_axi_awlock := 0.U - io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U(4.W),15.U(4.W)) - io.lsu_axi_awprot := 0.U(3.W) - io.lsu_axi_awqos := 0.U(4.W) - - io.lsu_axi_wvalid := obuf_valid & obuf_write & ~obuf_data_done & ~bus_addr_match_pending - io.lsu_axi_wdata := obuf_data - io.lsu_axi_wstrb := obuf_byteen & Fill(8,obuf_write) - io.lsu_axi_wlast := 1.U - - io.lsu_axi_arvalid := obuf_valid & ~obuf_write & ~obuf_nosend & ~bus_addr_match_pending - io.lsu_axi_arid := obuf_tag0.asUInt - io.lsu_axi_araddr := io.lsu_axi_awaddr - io.lsu_axi_arregion := obuf_addr(31,28) - io.lsu_axi_arlen := 0.U(8.W) - io.lsu_axi_arsize := io.lsu_axi_awsize - io.lsu_axi_arburst := 1.U(2.W) - io.lsu_axi_arlock := 0.U - io.lsu_axi_arcache := io.lsu_axi_awcache - io.lsu_axi_arprot := 0.U - io.lsu_axi_arqos := 0.U - - io.lsu_axi_bready := 1.U - io.lsu_axi_rready := 1.U + buf_ldfwd := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwd_in(i), false.B, buf_ldfwd_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_ldfwdtag := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_ldfwdtag_in(i), 0.U, buf_ldfwd_en(i).asBool())}) + buf_sideeffect := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sideeffect_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_unsign := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_unsign_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_write := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_write_in(i), false.B, buf_wr_en(i).asBool())}).asUInt()).reverse.reduce(Cat(_,_)) + buf_sz := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_sz_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_addr := (0 until DEPTH).map(i=>rvdffe(buf_addr_in(i), buf_wr_en(i).asBool(), clock, io.scan_mode)) + buf_byteen := (0 until DEPTH).map(i=>withClock(io.lsu_bus_buf_c1_clk){RegEnable(buf_byteen_in(i), 0.U, buf_wr_en(i).asBool())}) + buf_data := (0 until DEPTH).map(i=>rvdffe(buf_data_in(i), buf_data_en(i), clock, io.scan_mode)) + buf_error := (0 until DEPTH).map(i=>(withClock(io.lsu_bus_buf_c1_clk){RegNext(Mux(buf_error_en(i), true.B, buf_error(i)) & !buf_rst(i), false.B)}).asUInt()).reverse.reduce(Cat(_,_)) + val buf_numvld_any = (Mux(io.ldst_dual_m, Cat(io.lsu_busreq_m, 0.U),io.lsu_busreq_m) +& Mux(io.ldst_dual_r, Cat(io.lsu_busreq_r, 0.U),io.lsu_busreq_r) +& ibuf_valid) + buf_state.map(i=>(i=/=idle_C).asUInt).reduce(_+&_) + buf_numvld_wrcmd_any := (0 until DEPTH).map(i=>(buf_write(i) & (buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_cmd_any := (0 until DEPTH).map(i=>((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i)).asUInt).reverse.reduce(_ +& _) + buf_numvld_pend_any := (0 until DEPTH).map(i=>((buf_state(i)===wait_C) | ((buf_state(i)===cmd_C) & !buf_cmd_state_bus_en(i))).asUInt).reverse.reduce(_ +& _) + any_done_wait_state := (0 until DEPTH).map(i=>buf_state(i)===done_wait_C).reverse.reduce(_|_) + io.lsu_bus_buffer_pend_any := buf_numvld_pend_any.orR + io.lsu_bus_buffer_full_any := Mux(io.ldst_dual_d & io.dec_lsu_valid_raw_d, buf_numvld_any>=(DEPTH-1).U, buf_numvld_any===DEPTH.U) + io.lsu_bus_buffer_empty_any := !(buf_state.map(_.orR).reduce(_|_)) & !ibuf_valid & !obuf_valid + + io.lsu_nonblock_load_valid_m := io.lsu_busreq_m & io.lsu_pkt_m.valid & io.lsu_pkt_m.load & !io.flush_m_up & !io.ld_full_hit_m + io.lsu_nonblock_load_tag_m := WrPtr0_m + val lsu_nonblock_load_valid_r = WireInit(Bool(), false.B) + io.lsu_nonblock_load_inv_r := lsu_nonblock_load_valid_r & !io.lsu_commit_r + io.lsu_nonblock_load_inv_tag_r := WrPtr0_r + val lsu_nonblock_load_data_ready = Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (!(BUILD_AXI_NATIVE.B & buf_write(i))))) + io.lsu_nonblock_load_data_error := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C) -> (buf_error(i) & !buf_write(i)))) + io.lsu_nonblock_load_data_tag := Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> i.U)) + val lsu_nonblock_load_data_lo = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (!buf_dual(i) | !buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_load_data_hi = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & !buf_write(i) & (buf_dual(i) & buf_dualhi(i))) -> buf_data(i))) + val lsu_nonblock_addr_offset = indexing(buf_addr, io.lsu_nonblock_load_data_tag)(1,0) + val lsu_nonblock_sz = indexing(buf_sz, io.lsu_nonblock_load_data_tag) + val lsu_nonblock_unsign = indexing(buf_unsign, io.lsu_nonblock_load_data_tag) + val lsu_nonblock_dual = indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), io.lsu_nonblock_load_data_tag) + val lsu_nonblock_data_unalgn = Cat(lsu_nonblock_load_data_hi, lsu_nonblock_load_data_lo) >> (lsu_nonblock_addr_offset * 8.U) + + io.lsu_nonblock_load_data_valid := lsu_nonblock_load_data_ready & !io.lsu_nonblock_load_data_error + io.lsu_nonblock_load_data := Mux1H(Seq((lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(0.U(24.W),lsu_nonblock_data_unalgn(7,0)), + (lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(0.U(16.W),lsu_nonblock_data_unalgn(15,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===0.U)) -> Cat(Fill(24,lsu_nonblock_data_unalgn(7)), lsu_nonblock_data_unalgn(7,0)), + (!lsu_nonblock_unsign & (lsu_nonblock_sz===1.U)) -> Cat(Fill(16,lsu_nonblock_data_unalgn(15)), lsu_nonblock_data_unalgn(15,0)), + (lsu_nonblock_sz===2.U) -> lsu_nonblock_data_unalgn)) + bus_sideeffect_pend := (0 until DEPTH).map(i=>(buf_state(i)===resp_C) & buf_sideeffect(i) & io.dec_tlu_sideeffect_posted_disable).reduce(_|_) + bus_addr_match_pending := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===resp_C)-> + (BUILD_AXI_NATIVE.B & obuf_valid & (obuf_addr(31,3)===buf_addr(i)(31,3)) & !((obuf_tag0===i.U) | (obuf_merge & (obuf_tag1===i.U)))))) + + bus_cmd_ready := Mux(obuf_write, Mux(obuf_cmd_done | obuf_data_done, Mux(obuf_cmd_done, io.lsu_axi_wready, io.lsu_axi_awready), io.lsu_axi_awready & io.lsu_axi_awready), io.lsu_axi_arready) + bus_wcmd_sent := io.lsu_axi_awvalid & io.lsu_axi_awready + bus_wdata_sent := io.lsu_axi_wvalid & io.lsu_axi_wready + bus_cmd_sent := ((obuf_cmd_done | bus_wcmd_sent) & (obuf_data_done | bus_wdata_sent)) | (io.lsu_axi_arvalid & io.lsu_axi_arready) + bus_rsp_read := io.lsu_axi_rvalid & io.lsu_axi_rready + bus_rsp_write := io.lsu_axi_bvalid & io.lsu_axi_bready + bus_rsp_read_tag := io.lsu_axi_rid + bus_rsp_write_tag := io.lsu_axi_bid + bus_rsp_write_error := bus_rsp_write & (io.lsu_axi_bresp =/= 0.U) + bus_rsp_read_error := bus_rsp_read & (io.lsu_axi_bresp =/= 0.U) + bus_rsp_rdata := io.lsu_axi_rdata + + // AXI Command signals + io.lsu_axi_awvalid := obuf_valid & obuf_write & !obuf_cmd_done & !bus_addr_match_pending + io.lsu_axi_awid := obuf_tag0 + io.lsu_axi_awaddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3), 0.U(3.W))) + io.lsu_axi_awsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi_awprot := 0.U + io.lsu_axi_awcache := Mux(obuf_sideeffect, 0.U, 15.U) + io.lsu_axi_awregion := obuf_addr(31,28) + io.lsu_axi_awlen := 0.U + io.lsu_axi_awburst := 1.U(2.W) + io.lsu_axi_awqos := 0.U + io.lsu_axi_awlock := 0.U + + io.lsu_axi_wvalid := obuf_valid & obuf_write & !obuf_data_done & !bus_addr_match_pending + io.lsu_axi_wstrb := obuf_byteen & Fill(8, obuf_write) + io.lsu_axi_wdata := obuf_data + io.lsu_axi_wlast := 1.U + + io.lsu_axi_arvalid := obuf_valid & !obuf_write & !obuf_nosend & !bus_addr_match_pending + io.lsu_axi_arid := obuf_tag0 + io.lsu_axi_araddr := Mux(obuf_sideeffect, obuf_addr, Cat(obuf_addr(31,3),0.U(3.W))) + io.lsu_axi_arsize := Mux(obuf_sideeffect, Cat(0.U, obuf_sz), 3.U(3.W)) + io.lsu_axi_arprot := 0.U + io.lsu_axi_arcache := Mux(obuf_sideeffect, 0.U(4.W), 15.U) + io.lsu_axi_arregion := obuf_addr(31,28) + io.lsu_axi_arlen := 0.U + io.lsu_axi_arburst := 1.U(2.W) + io.lsu_axi_arqos := 0.U + io.lsu_axi_arlock := 0.U + io.lsu_axi_bready := 1.U + io.lsu_axi_rready := 1.U + io.lsu_imprecise_error_store_any := Mux1H((0 until DEPTH).map(i=>(buf_state(i)===done_C)->(io.lsu_bus_clk_en_q & buf_error(i) & buf_write(i)))) + val lsu_imprecise_error_store_tag = Mux1H((0 until DEPTH).map(i=>((buf_state(i)===done_C) & buf_error(i) & buf_write(i))->i.U)) + + io.lsu_imprecise_error_load_any := io.lsu_nonblock_load_data_error & !io.lsu_imprecise_error_store_any + io.lsu_imprecise_error_addr_any := Mux(io.lsu_imprecise_error_store_any, buf_addr(lsu_imprecise_error_store_tag), buf_addr(io.lsu_nonblock_load_data_tag)) + lsu_bus_cntr_overflow := 0.U + + io.lsu_bus_idle_any := 1.U + + // PMU signals + io.lsu_pmu_bus_trxn := (io.lsu_axi_awvalid & io.lsu_axi_awready) | (io.lsu_axi_wvalid & io.lsu_axi_wready) | (io.lsu_axi_arvalid & io.lsu_axi_arready) + io.lsu_pmu_bus_misaligned := io.lsu_busreq_r & io.ldst_dual_r & io.lsu_commit_r + io.lsu_pmu_bus_error := io.lsu_imprecise_error_load_any | io.lsu_imprecise_error_store_any + + io.lsu_pmu_bus_busy := (io.lsu_axi_awvalid & !io.lsu_axi_awready) | (io.lsu_axi_wvalid & !io.lsu_axi_wready) | (io.lsu_axi_arvalid & !io.lsu_axi_arready) + + WrPtr0_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr0_m, 0.U)} + WrPtr1_r := withClock(io.lsu_c2_r_clk){RegNext(WrPtr1_m, 0.U)} + io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)} + lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_nonblock_load_valid_m, false.B)} } + object BusBufmain extends App{ - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer()))) + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog((new el2_lsu_bus_buffer()))) } diff --git a/src/main/scala/lsu/el2_lsu_bus_intf.scala b/src/main/scala/lsu/el2_lsu_bus_intf.scala index f72a16ed..c5892e38 100644 --- a/src/main/scala/lsu/el2_lsu_bus_intf.scala +++ b/src/main/scala/lsu/el2_lsu_bus_intf.scala @@ -5,295 +5,329 @@ import chisel3.util._ import lib._ import include._ import snapshot._ -class el2_lsu_bus_intf extends Module with RequireAsyncReset{ - val io = IO (new Bundle { -// val clk = Input(Clock()) //implicit -// val rst_l = Input(1.W) //implicit - val scan_mode = Input(Bool()) - val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals - val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing - val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus - val lsu_c1_m_clk = Input(Clock()) - val lsu_c1_r_clk = Input(Clock()) - val lsu_c2_r_clk = Input(Clock()) - val lsu_bus_ibuf_c1_clk = Input(Clock()) - val lsu_bus_obuf_c1_clk = Input(Clock()) - val lsu_bus_buf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val free_clk = Input(Clock()) - val lsu_busm_clk = Input(Clock()) - val dec_lsu_valid_raw_d = Input(Bool()) - val lsu_busreq_m = Input(Bool()) - val lsu_pkt_m = Input(new el2_lsu_pkt_t) - val lsu_pkt_r = Input(new el2_lsu_pkt_t) - val lsu_addr_d = Input(UInt(32.W)) - val lsu_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - val end_addr_d = Input(UInt(32.W)) - val end_addr_m = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) - val store_data_r = Input(UInt(32.W)) - val dec_tlu_force_halt = Input(Bool()) - val lsu_commit_r = Input(Bool()) - val is_sideeffects_m = Input(Bool()) - val flush_m_up = Input(Bool()) - val flush_r = Input(Bool()) - val lsu_axi_awready = Input(Bool()) - val lsu_axi_wready = Input(Bool()) - val lsu_axi_bvalid = Input(Bool()) - val lsu_axi_bresp = Input(UInt(2.W)) - val lsu_axi_bid = Input(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_arready = Input(Bool()) - val lsu_axi_rvalid = Input(Bool()) - val lsu_axi_rid = Input(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_rdata = Input(UInt(64.W)) - val lsu_axi_rresp = Input(UInt(2.W)) - val lsu_axi_rlast = Input(Bool()) - val lsu_bus_clk_en = Input(Bool()) - val lsu_busreq_r = Output(Bool()) - val lsu_bus_buffer_pend_any = Output(Bool()) - val lsu_bus_buffer_full_any = Output(Bool()) - val lsu_bus_buffer_empty_any = Output(Bool()) - val lsu_bus_idle_any = Output(Bool()) - val bus_read_data_m = Output(UInt(32.W)) - val lsu_imprecise_error_load_any = Output(Bool()) - val lsu_imprecise_error_store_any = Output(Bool()) - val lsu_imprecise_error_addr_any = Output(UInt(32.W)) - val lsu_nonblock_load_valid_m = Output(Bool()) - val lsu_nonblock_load_tag_m = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_inv_r = Output(Bool()) - val lsu_nonblock_load_inv_tag_r = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_data_valid = Output(Bool()) - val lsu_nonblock_load_data_error = Output(Bool()) - val lsu_nonblock_load_data_tag = Output(UInt(pt1.LSU_NUM_NBLOAD_WIDTH.W)) - val lsu_nonblock_load_data = Output(UInt(32.W)) - val lsu_pmu_bus_trxn = Output(Bool()) - val lsu_pmu_bus_misaligned = Output(Bool()) - val lsu_pmu_bus_error = Output(Bool()) - val lsu_pmu_bus_busy = Output(Bool()) - val lsu_axi_awvalid = Output(Bool()) - val lsu_axi_awid = Output(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_awaddr = Output(UInt(32.W)) - val lsu_axi_awregion = Output(UInt(4.W)) - val lsu_axi_awlen = Output(UInt(8.W)) - val lsu_axi_awsize = Output(UInt(3.W)) - val lsu_axi_awburst = Output(UInt(2.W)) - val lsu_axi_awlock = Output(Bool()) - val lsu_axi_awcache = Output(UInt(4.W)) - val lsu_axi_awprot = Output(UInt(3.W)) - val lsu_axi_awqos = Output(UInt(4.W)) - val lsu_axi_wvalid = Output(Bool()) - val lsu_axi_wdata = Output(UInt(64.W)) - val lsu_axi_wstrb = Output(UInt(8.W)) - val lsu_axi_wlast = Output(Bool()) - val lsu_axi_bready = Output(Bool()) - val lsu_axi_arvalid = Output(Bool()) - val lsu_axi_arid = Output(UInt(pt1.LSU_BUS_TAG.W)) - val lsu_axi_araddr = Output(UInt(32.W)) - val lsu_axi_arregion = Output(UInt(4.W)) - val lsu_axi_arlen = Output(UInt(8.W)) - val lsu_axi_arsize = Output(UInt(3.W)) - val lsu_axi_arburst = Output(UInt(2.W)) - val lsu_axi_arlock = Output(Bool()) - val lsu_axi_arcache = Output(UInt(4.W)) - val lsu_axi_arprot = Output(UInt(3.W)) - val lsu_axi_arqos = Output(UInt(4.W)) - val lsu_axi_rready = Output(Bool()) - }) +class el2_lsu_bus_intf extends Module with RequireAsyncReset with el2_lib { + val io = IO (new Bundle { + val scan_mode = Input(Bool()) + val dec_tlu_external_ldfwd_disable = Input(Bool()) // disable load to load forwarding for externals + val dec_tlu_wb_coalescing_disable = Input(Bool()) // disable write buffer coalescing + val dec_tlu_sideeffect_posted_disable = Input(Bool()) // disable the posted sideeffect load store to the bus + val lsu_c1_m_clk = Input(Clock()) + val lsu_c1_r_clk = Input(Clock()) + val lsu_c2_r_clk = Input(Clock()) + val lsu_bus_ibuf_c1_clk = Input(Clock()) + val lsu_bus_obuf_c1_clk = Input(Clock()) + val lsu_bus_buf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val free_clk = Input(Clock()) + val lsu_busm_clk = Input(Clock()) - val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) - val ldst_dual_d = WireInit(Bool(), init = false.B) - val ldst_dual_m = WireInit(Bool(), init = false.B) - val ldst_dual_r = WireInit(Bool(), init = false.B) - val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) - val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) - val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) - val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) - val is_sideeffects_r = WireInit(Bool(), init = false.B) - val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) - val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) - val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) - val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) - val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) - val no_word_merge_r = WireInit(Bool(), init = false.B) - val no_dword_merge_r = WireInit(Bool(), init = false.B) - val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) - val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) - val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) - val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) - val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) - val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) - val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) - val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) - val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) - val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) - val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) - val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) - val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) - val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) - val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) - val ld_full_hit_m = WireInit(Bool(), init = false.B) - val bus_buffer = Module(new el2_lsu_bus_buffer) - bus_buffer.io.scan_mode := io.scan_mode - bus_buffer.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable - bus_buffer.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable - bus_buffer.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable - bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt - bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk - bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk - bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk - bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk - bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk - bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk - bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d - bus_buffer.io.lsu_pkt_m := io.lsu_pkt_m - bus_buffer.io.lsu_pkt_r := io.lsu_pkt_r - bus_buffer.io.lsu_addr_m := io.lsu_addr_m - bus_buffer.io.end_addr_m := io.end_addr_m - bus_buffer.io.lsu_addr_r := io.lsu_addr_r - bus_buffer.io.end_addr_r := io.end_addr_r - bus_buffer.io.store_data_r := io.store_data_r - bus_buffer.io.no_word_merge_r := no_word_merge_r - bus_buffer.io.no_dword_merge_r := no_dword_merge_r - bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m - bus_buffer.io.ld_full_hit_m := ld_full_hit_m - bus_buffer.io.flush_m_up := io.flush_m_up - bus_buffer.io.flush_r := io.flush_r - bus_buffer.io.lsu_commit_r := io.lsu_commit_r - bus_buffer.io.is_sideeffects_r := is_sideeffects_r - bus_buffer.io.ldst_dual_d := ldst_dual_d - bus_buffer.io.ldst_dual_m := ldst_dual_m - bus_buffer.io.ldst_dual_r := ldst_dual_r - bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m - bus_buffer.io.lsu_axi_awready := io.lsu_axi_awready - bus_buffer.io.lsu_axi_wready := io.lsu_axi_wready - bus_buffer.io.lsu_axi_bvalid := io.lsu_axi_bvalid - bus_buffer.io.lsu_axi_bresp := io.lsu_axi_bresp - bus_buffer.io.lsu_axi_bid := io.lsu_axi_bid - bus_buffer.io.lsu_axi_arready := io.lsu_axi_arready - bus_buffer.io.lsu_axi_rvalid := io.lsu_axi_rvalid - bus_buffer.io.lsu_axi_rid := io.lsu_axi_rid - bus_buffer.io.lsu_axi_rdata := io.lsu_axi_rdata - bus_buffer.io.lsu_axi_rresp := io.lsu_axi_rresp - bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en - bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q + val dec_lsu_valid_raw_d = Input(Bool()) + val lsu_busreq_m = Input(Bool()) - io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r - io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any - io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any - io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any - io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any - ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo - ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi - ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo - ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi - io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any - io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any - io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any - io.lsu_nonblock_load_valid_m := bus_buffer.io.lsu_nonblock_load_valid_m - io.lsu_nonblock_load_tag_m := bus_buffer.io.lsu_nonblock_load_tag_m - io.lsu_nonblock_load_inv_r := bus_buffer.io.lsu_nonblock_load_inv_r - io.lsu_nonblock_load_inv_tag_r := bus_buffer.io.lsu_nonblock_load_inv_tag_r - io.lsu_nonblock_load_data_valid := bus_buffer.io.lsu_nonblock_load_data_valid - io.lsu_nonblock_load_data_error := bus_buffer.io.lsu_nonblock_load_data_error - io.lsu_nonblock_load_data_tag := bus_buffer.io.lsu_nonblock_load_data_tag - io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data - io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn - io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned - io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error - io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy - io.lsu_axi_awvalid := bus_buffer.io.lsu_axi_awvalid - io.lsu_axi_awid := bus_buffer.io.lsu_axi_awid - io.lsu_axi_awaddr := bus_buffer.io.lsu_axi_awaddr - io.lsu_axi_awregion := bus_buffer.io.lsu_axi_awregion - io.lsu_axi_awlen := bus_buffer.io.lsu_axi_awlen - io.lsu_axi_awsize := bus_buffer.io.lsu_axi_awsize - io.lsu_axi_awburst := bus_buffer.io.lsu_axi_awburst - io.lsu_axi_awlock := bus_buffer.io.lsu_axi_awlock - io.lsu_axi_awcache := bus_buffer.io.lsu_axi_awcache - io.lsu_axi_awprot := bus_buffer.io.lsu_axi_awprot - io.lsu_axi_awqos := bus_buffer.io.lsu_axi_awqos - io.lsu_axi_wvalid := bus_buffer.io.lsu_axi_wvalid - io.lsu_axi_wdata := bus_buffer.io.lsu_axi_wdata - io.lsu_axi_wstrb := bus_buffer.io.lsu_axi_wstrb - io.lsu_axi_wlast := bus_buffer.io.lsu_axi_wlast - io.lsu_axi_bready := bus_buffer.io.lsu_axi_bready - io.lsu_axi_arvalid := bus_buffer.io.lsu_axi_arvalid - io.lsu_axi_arid := bus_buffer.io.lsu_axi_arid - io.lsu_axi_araddr := bus_buffer.io.lsu_axi_araddr - io.lsu_axi_arregion := bus_buffer.io.lsu_axi_arregion - io.lsu_axi_arlen := bus_buffer.io.lsu_axi_arlen - io.lsu_axi_arsize := bus_buffer.io.lsu_axi_arsize - io.lsu_axi_arburst := bus_buffer.io.lsu_axi_arburst - io.lsu_axi_arlock := bus_buffer.io.lsu_axi_arlock - io.lsu_axi_arcache := bus_buffer.io.lsu_axi_arcache - io.lsu_axi_arprot := bus_buffer.io.lsu_axi_arprot - io.lsu_axi_arqos := bus_buffer.io.lsu_axi_arqos - io.lsu_axi_rready := bus_buffer.io.lsu_axi_rready + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_pkt_r = Input(new el2_lsu_pkt_t) - ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_r.word.asBool -> 15.U(4.W), io.lsu_pkt_r.half.asBool -> 3.U(4.W), io.lsu_pkt_r.by.asBool -> 1.U(4.W))) - ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2) - addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) - addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) - no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_word_lo_r_m) - no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_dw_lo_r_m) - ldst_byteen_ext_m := Cat(0.U(4.W),ldst_byteen_m(3,0)) << io.lsu_addr_m(1,0) - ldst_byteen_ext_r := Cat(0.U(4.W),ldst_byteen_r(3,0)) << io.lsu_addr_r(1,0) - store_data_ext_r := Cat(0.U(32.W),io.store_data_r(31,0)) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) - ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) - ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) - ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) - ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) - store_data_hi_r := store_data_ext_r(63,32) - store_data_lo_r := store_data_ext_r(31,0) - ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m - ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m - ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m - ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m - ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) - ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) - ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) - ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) - ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & !io.is_sideeffects_m - ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) - io.bus_read_data_m := ld_fwddata_m(31,0) + val lsu_addr_d = Input(UInt(32.W)) + val lsu_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) - withClock(io.free_clk) { - lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) - } - withClock(io.lsu_c1_m_clk) { - ldst_dual_m := RegNext(io.lsu_bus_clk_en, init = 0.U) - } - withClock(io.lsu_c1_r_clk) { - ldst_dual_r := RegNext(io.lsu_bus_clk_en, init = 0.U) - is_sideeffects_r := RegNext(io.lsu_bus_clk_en, init = 0.U) - ldst_byteen_r := RegNext(io.lsu_bus_clk_en, init = 0.U(4.W)) - } + val end_addr_d = Input(UInt(32.W)) + val end_addr_m = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) + + val store_data_r = Input(UInt(32.W)) + val dec_tlu_force_halt = Input(Bool()) + + val lsu_commit_r = Input(Bool()) + val is_sideeffects_m = Input(Bool()) + val flush_m_up = Input(Bool()) + val flush_r = Input(Bool()) + + + + + + val lsu_busreq_r = Output(Bool()) + val lsu_bus_buffer_pend_any = Output(Bool()) + val lsu_bus_buffer_full_any = Output(Bool()) + val lsu_bus_buffer_empty_any = Output(Bool()) + val lsu_bus_idle_any = Output(Bool()) + val bus_read_data_m = Output(UInt(32.W)) + + val lsu_imprecise_error_load_any = Output(Bool()) + val lsu_imprecise_error_store_any = Output(Bool()) + val lsu_imprecise_error_addr_any = Output(UInt(32.W)) + + val lsu_nonblock_load_valid_m = Output(Bool()) + val lsu_nonblock_load_tag_m = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_inv_r = Output(Bool()) + val lsu_nonblock_load_inv_tag_r = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_data_valid = Output(Bool()) + val lsu_nonblock_load_data_error = Output(Bool()) + val lsu_nonblock_load_data_tag = Output(UInt(LSU_NUM_NBLOAD_WIDTH.W)) + val lsu_nonblock_load_data = Output(UInt(32.W)) + + val lsu_pmu_bus_trxn = Output(Bool()) + val lsu_pmu_bus_misaligned = Output(Bool()) + val lsu_pmu_bus_error = Output(Bool()) + val lsu_pmu_bus_busy = Output(Bool()) + + val lsu_axi_awvalid = Output(Bool()) + val lsu_axi_awready = Input(Bool()) + val lsu_axi_awid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_awaddr = Output(UInt(32.W)) + val lsu_axi_awregion = Output(UInt(4.W)) + val lsu_axi_awlen = Output(UInt(8.W)) + val lsu_axi_awsize = Output(UInt(3.W)) + val lsu_axi_awburst = Output(UInt(2.W)) + val lsu_axi_awlock = Output(Bool()) + val lsu_axi_awcache = Output(UInt(4.W)) + val lsu_axi_awprot = Output(UInt(3.W)) + val lsu_axi_awqos = Output(UInt(4.W)) + + val lsu_axi_wvalid = Output(Bool()) + val lsu_axi_wready = Input(Bool()) + val lsu_axi_wdata = Output(UInt(64.W)) + val lsu_axi_wstrb = Output(UInt(8.W)) + val lsu_axi_wlast = Output(Bool()) + + val lsu_axi_bvalid = Input(Bool()) + val lsu_axi_bready = Output(Bool()) + val lsu_axi_bresp = Input(UInt(2.W)) + val lsu_axi_bid = Input(UInt(LSU_BUS_TAG.W)) + + val lsu_axi_arvalid = Output(Bool()) + val lsu_axi_arready = Input(Bool()) + val lsu_axi_arid = Output(UInt(LSU_BUS_TAG.W)) + val lsu_axi_araddr = Output(UInt(32.W)) + val lsu_axi_arregion = Output(UInt(4.W)) + val lsu_axi_arlen = Output(UInt(8.W)) + val lsu_axi_arsize = Output(UInt(3.W)) + val lsu_axi_arburst = Output(UInt(2.W)) + val lsu_axi_arlock = Output(Bool()) + val lsu_axi_arcache = Output(UInt(4.W)) + val lsu_axi_arprot = Output(UInt(3.W)) + val lsu_axi_arqos = Output(UInt(4.W)) + + val lsu_axi_rvalid = Input(Bool()) + val lsu_axi_rready = Output(Bool()) + val lsu_axi_rid = Input(UInt(LSU_BUS_TAG.W)) + val lsu_axi_rdata = Input(UInt(64.W)) + val lsu_axi_rresp = Input(UInt(2.W)) + val lsu_axi_rlast = Input(Bool()) + + val lsu_bus_clk_en = Input(Bool()) + }) + + val lsu_bus_clk_en_q = WireInit(Bool(), init = false.B) + val ldst_dual_d = WireInit(Bool(), init = false.B) + val ldst_dual_m = WireInit(Bool(), init = false.B) + val ldst_dual_r = WireInit(Bool(), init = false.B) + val ldst_byteen_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_ext_m = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_ext_r = WireInit(UInt(8.W), init = 0.U) + val ldst_byteen_hi_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_hi_r = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_m = WireInit(UInt(4.W), init = 0.U) + val ldst_byteen_lo_r = WireInit(UInt(4.W), init = 0.U) + val is_sideeffects_r = WireInit(Bool(), init = false.B) + val store_data_ext_r = WireInit(UInt(64.W), init = 0.U) + val store_data_hi_r = WireInit(UInt(32.W), init = 0.U) + val store_data_lo_r = WireInit(UInt(32.W), init = 0.U) + val addr_match_dw_lo_r_m = WireInit(Bool(), init = false.B) + val addr_match_word_lo_r_m = WireInit(Bool(), init = false.B) + val no_word_merge_r = WireInit(Bool(), init = false.B) + val no_dword_merge_r = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_lo = WireInit(Bool(), init = false.B) + val ld_addr_rhit_lo_hi = WireInit(Bool(), init = false.B) + val ld_addr_rhit_hi_hi = WireInit(Bool(), init = false.B) + val ld_byte_rhit_lo_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_byte_rhit_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_rpipe_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_rpipe_hi = WireInit(UInt(32.W), init = 0.U) + val ld_byte_hit_buf_lo = WireInit(UInt(4.W), init = 0.U) + val ld_byte_hit_buf_hi = WireInit(UInt(4.W), init = 0.U) + val ld_fwddata_buf_lo = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_buf_hi = WireInit(UInt(32.W), init = 0.U) + val ld_fwddata_lo = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_hi = WireInit(UInt(64.W), init = 0.U) + val ld_fwddata_m = WireInit(UInt(64.W), init = 0.U) + val ld_full_hit_hi_m = WireInit(Bool(), init = true.B) + val ld_full_hit_lo_m = WireInit(Bool(), init = true.B) + val ld_full_hit_m = WireInit(Bool(), init = false.B) + + val bus_buffer = Module(new el2_lsu_bus_buffer) + + bus_buffer.io.scan_mode := io.scan_mode + + bus_buffer.io.dec_tlu_external_ldfwd_disable := io.dec_tlu_external_ldfwd_disable + bus_buffer.io.dec_tlu_wb_coalescing_disable := io.dec_tlu_wb_coalescing_disable + bus_buffer.io.dec_tlu_sideeffect_posted_disable := io.dec_tlu_sideeffect_posted_disable + bus_buffer.io.dec_tlu_force_halt := io.dec_tlu_force_halt + bus_buffer.io.lsu_c2_r_clk := io.lsu_c2_r_clk + bus_buffer.io.lsu_bus_ibuf_c1_clk := io.lsu_bus_ibuf_c1_clk + bus_buffer.io.lsu_bus_obuf_c1_clk := io.lsu_bus_obuf_c1_clk + bus_buffer.io.lsu_bus_buf_c1_clk := io.lsu_bus_buf_c1_clk + bus_buffer.io.lsu_free_c2_clk := io.lsu_free_c2_clk + bus_buffer.io.lsu_busm_clk := io.lsu_busm_clk + bus_buffer.io.dec_lsu_valid_raw_d := io.dec_lsu_valid_raw_d + + // + bus_buffer.io.lsu_pkt_m <> io.lsu_pkt_m + bus_buffer.io.lsu_pkt_r <> io.lsu_pkt_r + // + + bus_buffer.io.lsu_addr_m := io.lsu_addr_m + bus_buffer.io.end_addr_m := io.end_addr_m + bus_buffer.io.lsu_addr_r := io.lsu_addr_r + bus_buffer.io.end_addr_r := io.end_addr_r + bus_buffer.io.store_data_r := io.store_data_r + + bus_buffer.io.lsu_busreq_m := io.lsu_busreq_m + bus_buffer.io.flush_m_up := io.flush_m_up + bus_buffer.io.flush_r := io.flush_r + bus_buffer.io.lsu_commit_r := io.lsu_commit_r + bus_buffer.io.lsu_axi_awready := io.lsu_axi_awready + bus_buffer.io.lsu_axi_wready := io.lsu_axi_wready + bus_buffer.io.lsu_axi_bvalid := io.lsu_axi_bvalid + bus_buffer.io.lsu_axi_bresp := io.lsu_axi_bresp + bus_buffer.io.lsu_axi_bid := io.lsu_axi_bid + bus_buffer.io.lsu_axi_arready := io.lsu_axi_arready + bus_buffer.io.lsu_axi_rvalid := io.lsu_axi_rvalid + bus_buffer.io.lsu_axi_rid := io.lsu_axi_rid + bus_buffer.io.lsu_axi_rdata := io.lsu_axi_rdata + bus_buffer.io.lsu_axi_rresp := io.lsu_axi_rresp + bus_buffer.io.lsu_bus_clk_en := io.lsu_bus_clk_en + + io.lsu_busreq_r := bus_buffer.io.lsu_busreq_r + io.lsu_bus_buffer_pend_any := bus_buffer.io.lsu_bus_buffer_pend_any + io.lsu_bus_buffer_full_any := bus_buffer.io.lsu_bus_buffer_full_any + io.lsu_bus_buffer_empty_any := bus_buffer.io.lsu_bus_buffer_empty_any + io.lsu_bus_idle_any := bus_buffer.io.lsu_bus_idle_any + ld_byte_hit_buf_lo := bus_buffer.io.ld_byte_hit_buf_lo + ld_byte_hit_buf_hi := bus_buffer.io.ld_byte_hit_buf_hi + ld_fwddata_buf_lo := bus_buffer.io.ld_fwddata_buf_lo + ld_fwddata_buf_hi := bus_buffer.io.ld_fwddata_buf_hi + io.lsu_imprecise_error_load_any := bus_buffer.io.lsu_imprecise_error_load_any + io.lsu_imprecise_error_store_any := bus_buffer.io.lsu_imprecise_error_store_any + io.lsu_imprecise_error_addr_any := bus_buffer.io.lsu_imprecise_error_addr_any + io.lsu_nonblock_load_valid_m := bus_buffer.io.lsu_nonblock_load_valid_m + io.lsu_nonblock_load_tag_m := bus_buffer.io.lsu_nonblock_load_tag_m + io.lsu_nonblock_load_inv_r := bus_buffer.io.lsu_nonblock_load_inv_r + io.lsu_nonblock_load_inv_tag_r := bus_buffer.io.lsu_nonblock_load_inv_tag_r + io.lsu_nonblock_load_data_valid := bus_buffer.io.lsu_nonblock_load_data_valid + io.lsu_nonblock_load_data_error := bus_buffer.io.lsu_nonblock_load_data_error + io.lsu_nonblock_load_data_tag := bus_buffer.io.lsu_nonblock_load_data_tag + io.lsu_nonblock_load_data := bus_buffer.io.lsu_nonblock_load_data + io.lsu_pmu_bus_trxn := bus_buffer.io.lsu_pmu_bus_trxn + io.lsu_pmu_bus_misaligned := bus_buffer.io.lsu_pmu_bus_misaligned + io.lsu_pmu_bus_error := bus_buffer.io.lsu_pmu_bus_error + io.lsu_pmu_bus_busy := bus_buffer.io.lsu_pmu_bus_busy + io.lsu_axi_awvalid := bus_buffer.io.lsu_axi_awvalid + io.lsu_axi_awid := bus_buffer.io.lsu_axi_awid + io.lsu_axi_awaddr := bus_buffer.io.lsu_axi_awaddr + io.lsu_axi_awregion := bus_buffer.io.lsu_axi_awregion + io.lsu_axi_awlen := bus_buffer.io.lsu_axi_awlen + io.lsu_axi_awsize := bus_buffer.io.lsu_axi_awsize + io.lsu_axi_awburst := bus_buffer.io.lsu_axi_awburst + io.lsu_axi_awlock := bus_buffer.io.lsu_axi_awlock + io.lsu_axi_awcache := bus_buffer.io.lsu_axi_awcache + io.lsu_axi_awprot := bus_buffer.io.lsu_axi_awprot + io.lsu_axi_awqos := bus_buffer.io.lsu_axi_awqos + io.lsu_axi_wvalid := bus_buffer.io.lsu_axi_wvalid + io.lsu_axi_wdata := bus_buffer.io.lsu_axi_wdata + io.lsu_axi_wstrb := bus_buffer.io.lsu_axi_wstrb + io.lsu_axi_wlast := bus_buffer.io.lsu_axi_wlast + io.lsu_axi_bready := bus_buffer.io.lsu_axi_bready + io.lsu_axi_arvalid := bus_buffer.io.lsu_axi_arvalid + io.lsu_axi_arid := bus_buffer.io.lsu_axi_arid + io.lsu_axi_araddr := bus_buffer.io.lsu_axi_araddr + io.lsu_axi_arregion := bus_buffer.io.lsu_axi_arregion + io.lsu_axi_arlen := bus_buffer.io.lsu_axi_arlen + io.lsu_axi_arsize := bus_buffer.io.lsu_axi_arsize + io.lsu_axi_arburst := bus_buffer.io.lsu_axi_arburst + io.lsu_axi_arlock := bus_buffer.io.lsu_axi_arlock + io.lsu_axi_arcache := bus_buffer.io.lsu_axi_arcache + io.lsu_axi_arprot := bus_buffer.io.lsu_axi_arprot + io.lsu_axi_arqos := bus_buffer.io.lsu_axi_arqos + io.lsu_axi_rready := bus_buffer.io.lsu_axi_rready + + bus_buffer.io.no_word_merge_r := no_word_merge_r + bus_buffer.io.no_dword_merge_r := no_dword_merge_r + bus_buffer.io.is_sideeffects_r := is_sideeffects_r + bus_buffer.io.ldst_dual_d := ldst_dual_d + bus_buffer.io.ldst_dual_m := ldst_dual_m + bus_buffer.io.ldst_dual_r := ldst_dual_r + bus_buffer.io.ldst_byteen_ext_m := ldst_byteen_ext_m + bus_buffer.io.ld_full_hit_m := ld_full_hit_m + bus_buffer.io.lsu_bus_clk_en_q := lsu_bus_clk_en_q + + + + + ldst_byteen_m := Mux1H(Seq(io.lsu_pkt_m.word.asBool -> 15.U(4.W), io.lsu_pkt_m.half.asBool -> 3.U(4.W), io.lsu_pkt_m.by.asBool -> 1.U(4.W))) + ldst_dual_d := io.lsu_addr_d(2) =/= io.end_addr_d(2) + addr_match_dw_lo_r_m := (io.lsu_addr_r(31,3) === io.lsu_addr_m(31,3)) + addr_match_word_lo_r_m := addr_match_dw_lo_r_m & !(io.lsu_addr_r(2)^io.lsu_addr_m(2)) + no_word_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_word_lo_r_m) + no_dword_merge_r := io.lsu_busreq_r & !ldst_dual_r & io.lsu_busreq_m & (io.lsu_pkt_m.load | !addr_match_dw_lo_r_m) + + ldst_byteen_ext_m := ldst_byteen_m(3,0) << io.lsu_addr_m(1,0) + ldst_byteen_ext_r := ldst_byteen_r(3,0) << io.lsu_addr_r(1,0) + store_data_ext_r := io.store_data_r(31,0) << Cat(io.lsu_addr_r(1,0),0.U(3.W)) + ldst_byteen_hi_m := ldst_byteen_ext_m(7,4) + ldst_byteen_lo_m := ldst_byteen_ext_m(3,0) + ldst_byteen_hi_r := ldst_byteen_ext_r(7,4) + ldst_byteen_lo_r := ldst_byteen_ext_r(3,0) + + store_data_hi_r := store_data_ext_r(63,32) + store_data_lo_r := store_data_ext_r(31,0) + ld_addr_rhit_lo_lo := (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m + ld_addr_rhit_lo_hi := (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m + ld_addr_rhit_hi_lo := (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m + ld_addr_rhit_hi_hi := (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.lsu_busreq_m + + ld_byte_rhit_lo_lo := (0 until 4).map(i =>(ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo_hi := (0 until 4).map(i =>(ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_lo := (0 until 4).map(i =>(ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i) & ldst_byteen_lo_m(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_hi := (0 until 4).map(i =>(ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i) & ldst_byteen_hi_m(i)).asUInt).reverse.reduce(Cat(_,_)) + + ld_byte_hit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) | ld_byte_hit_buf_lo(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_hit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) | ld_byte_hit_buf_hi(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo := (0 until 4).map(i =>(ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi := (0 until 4).map(i =>(ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i) ).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_lo := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_lo(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_lo(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_rpipe_hi := (0 until 4).map(i =>(Mux1H(Seq(ld_byte_rhit_lo_hi(i) -> store_data_lo_r((8*i)+7,(8*i)), ld_byte_rhit_hi_hi(i) -> store_data_hi_r((8*i)+7,(8*i))))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_lo := (0 until 4).map(i =>(Mux(ld_byte_rhit_lo(i), ld_fwddata_rpipe_lo((8*i)+7,(8*i)), ld_fwddata_buf_lo((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_fwddata_hi := (0 until 4).map(i =>(Mux(ld_byte_rhit_hi(i), ld_fwddata_rpipe_hi((8*i)+7,(8*i)), ld_fwddata_buf_hi((8*i)+7,(8*i)))).asUInt).reverse.reduce(Cat(_,_)) + ld_full_hit_lo_m := (0 until 4).map(i =>((ld_byte_hit_lo(i) | !ldst_byteen_lo_m(i))).asUInt).reduce(_&_) + ld_full_hit_hi_m := (0 until 4).map(i =>((ld_byte_hit_hi(i) | !ldst_byteen_hi_m(i))).asUInt).reduce(_&_) + ld_full_hit_m := ld_full_hit_lo_m & ld_full_hit_hi_m & io.lsu_busreq_m & io.lsu_pkt_m.load & !io.is_sideeffects_m + ld_fwddata_m := Cat(ld_fwddata_hi(31,0), ld_fwddata_lo(31,0)) >> (8.U*io.lsu_addr_m(1,0)) + io.bus_read_data_m := ld_fwddata_m(31,0) + + withClock(io.free_clk) { + lsu_bus_clk_en_q := RegNext(io.lsu_bus_clk_en, init = 0.U) + } + withClock(io.lsu_c1_m_clk) { + ldst_dual_m := RegNext(ldst_dual_d, init = 0.U) + } + withClock(io.lsu_c1_r_clk) { + ldst_dual_r := RegNext(ldst_dual_m, init = 0.U) + is_sideeffects_r := RegNext(io.is_sideeffects_m, init = 0.U) + ldst_byteen_r := RegNext(ldst_byteen_m, init = 0.U(4.W)) + } } object BusIntfMain extends App{ - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_bus_intf())) -} \ No newline at end of file + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_bus_intf())) +} diff --git a/src/main/scala/lsu/el2_lsu_clkdomain.scala b/src/main/scala/lsu/el2_lsu_clkdomain.scala index de51e50d..7896ba2b 100644 --- a/src/main/scala/lsu/el2_lsu_clkdomain.scala +++ b/src/main/scala/lsu/el2_lsu_clkdomain.scala @@ -8,96 +8,96 @@ import snapshot._ @chiselName class el2_lsu_clkdomain extends Module with RequireAsyncReset with el2_lib{ - val io = IO (new Bundle { + val io = IO (new Bundle { - val free_clk = Input(Clock()) // clock - // Inputs - val clk_override = Input(Bool()) // chciken bit to turn off clock gating - val addr_in_dccm_m = Input(Bool()) // address in dccm - val dma_dccm_req = Input(Bool()) // dma is active - val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue + val free_clk = Input(Clock()) // clock + // Inputs + val clk_override = Input(Bool()) // chciken bit to turn off clock gating + val addr_in_dccm_m = Input(Bool()) // address in dccm + val dma_dccm_req = Input(Bool()) // dma is active + val ldst_stbuf_reqvld_r = Input(Bool()) // allocating in to the store queue - val stbuf_reqvld_any = Input(Bool()) // stbuf is draining - val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed - val lsu_busreq_r = Input(Bool()) // busreq in r - val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry - val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty - val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty + val stbuf_reqvld_any = Input(Bool()) // stbuf is draining + val stbuf_reqvld_flushed_any = Input(Bool()) // instruction going to stbuf is flushed + val lsu_busreq_r = Input(Bool()) // busreq in r + val lsu_bus_buffer_pend_any = Input(Bool()) // bus buffer has a pending bus entry + val lsu_bus_buffer_empty_any = Input(Bool()) // external bus buffer is empty + val lsu_stbuf_empty_any = Input(Bool()) // stbuf is empty - val lsu_bus_clk_en = Input(Bool()) // bus clock enable + val lsu_bus_clk_en = Input(Bool()) // bus clock enable - val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode - val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d - val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m - val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r + val lsu_p = Input(new el2_lsu_pkt_t) // lsu packet in decode + val lsu_pkt_d = Input(new el2_lsu_pkt_t) // lsu packet in d + val lsu_pkt_m = Input(new el2_lsu_pkt_t) // lsu packet in m + val lsu_pkt_r = Input(new el2_lsu_pkt_t) // lsu packet in r - // Outputs - val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock - val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock + // Outputs + val lsu_c1_m_clk = Output(Clock()) // m pipe single pulse clock + val lsu_c1_r_clk = Output(Clock()) // r pipe single pulse clock - val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock - val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock + val lsu_c2_m_clk = Output(Clock()) // m pipe double pulse clock + val lsu_c2_r_clk = Output(Clock()) // r pipe double pulse clock - val lsu_store_c1_m_clk = Output(Clock()) // store in m - val lsu_store_c1_r_clk = Output(Clock()) // store in r + val lsu_store_c1_m_clk = Output(Clock()) // store in m + val lsu_store_c1_r_clk = Output(Clock()) // store in r - val lsu_stbuf_c1_clk = Output(Clock()) - val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock - val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock - val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock - val lsu_busm_clk = Output(Clock()) // bus clock + val lsu_stbuf_c1_clk = Output(Clock()) + val lsu_bus_obuf_c1_clk = Output(Clock()) // ibuf clock + val lsu_bus_ibuf_c1_clk = Output(Clock()) // ibuf clock + val lsu_bus_buf_c1_clk = Output(Clock()) // ibuf clock + val lsu_busm_clk = Output(Clock()) // bus clock - val lsu_free_c2_clk = Output(Clock()) + val lsu_free_c2_clk = Output(Clock()) - val scan_mode = Input(Bool()) - }) + val scan_mode = Input(Bool()) + }) - //------------------------------------------------------------------------------------------- - // Clock Enable Logic - //------------------------------------------------------------------------------------------- - val lsu_c1_d_clken_q = Wire(Bool()) - val lsu_c1_m_clken_q = Wire(Bool()) - val lsu_c1_r_clken_q = Wire(Bool()) - val lsu_free_c1_clken_q = Wire(Bool()) + //------------------------------------------------------------------------------------------- + // Clock Enable Logic + //------------------------------------------------------------------------------------------- + val lsu_c1_d_clken_q = Wire(Bool()) + val lsu_c1_m_clken_q = Wire(Bool()) + val lsu_c1_r_clken_q = Wire(Bool()) + val lsu_free_c1_clken_q = Wire(Bool()) - val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override - val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override - val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override + val lsu_c1_d_clken = io.lsu_p.valid | io.dma_dccm_req | io.clk_override + val lsu_c1_m_clken = io.lsu_pkt_d.valid | lsu_c1_d_clken_q | io.clk_override + val lsu_c1_r_clken = io.lsu_pkt_m.valid | lsu_c1_m_clken_q | io.clk_override - val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override - val lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override + val lsu_c2_m_clken = lsu_c1_m_clken | lsu_c1_m_clken_q | io.clk_override + val lsu_c2_r_clken = lsu_c1_r_clken | lsu_c1_r_clken_q | io.clk_override - val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.store) | io.clk_override) - val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.store) | io.clk_override) - val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override - val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override - val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en - val lsu_bus_buf_c1_clken = (!io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override).asBool + val lsu_store_c1_m_clken = ((lsu_c1_m_clken & io.lsu_pkt_d.store) | io.clk_override) + val lsu_store_c1_r_clken = ((lsu_c1_r_clken & io.lsu_pkt_m.store) | io.clk_override) + val lsu_stbuf_c1_clken = io.ldst_stbuf_reqvld_r | io.stbuf_reqvld_any | io.stbuf_reqvld_flushed_any | io.clk_override + val lsu_bus_ibuf_c1_clken = io.lsu_busreq_r | io.clk_override + val lsu_bus_obuf_c1_clken = (io.lsu_bus_buffer_pend_any | io.lsu_busreq_r | io.clk_override) & io.lsu_bus_clk_en + val lsu_bus_buf_c1_clken = !io.lsu_bus_buffer_empty_any | io.lsu_busreq_r | io.clk_override - val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | !io.lsu_bus_buffer_empty_any | !io.lsu_stbuf_empty_any | io.clk_override - val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override + val lsu_free_c1_clken = (io.lsu_p.valid | io.lsu_pkt_d.valid | io.lsu_pkt_m.valid | io.lsu_pkt_r.valid) | !io.lsu_bus_buffer_empty_any | !io.lsu_stbuf_empty_any | io.clk_override + val lsu_free_c2_clken = lsu_free_c1_clken | lsu_free_c1_clken_q | io.clk_override - lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)} - lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)} - lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)} - lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)} + lsu_free_c1_clken_q := withClock(io.free_clk) {RegNext(lsu_free_c1_clken,0.U)} + lsu_c1_d_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_d_clken, 0.U)} + lsu_c1_m_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_m_clken, 0.U)} + lsu_c1_r_clken_q := withClock(io.lsu_free_c2_clk) {RegNext(lsu_c1_r_clken, 0.U)} - io.lsu_c1_m_clk := rvclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode) - io.lsu_c1_r_clk := rvclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode) - io.lsu_c2_m_clk := rvclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode) - io.lsu_c2_r_clk := rvclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode) - io.lsu_store_c1_m_clk := rvclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode) - io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode) - io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode) - io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode) - io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,lsu_bus_obuf_c1_clken.asBool,io.scan_mode) - io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode) - io.lsu_busm_clk := rvclkhdr(clock,io.lsu_bus_clk_en.asBool,io.scan_mode) - io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode) + io.lsu_c1_m_clk := rvclkhdr(clock,lsu_c1_m_clken.asBool,io.scan_mode) + io.lsu_c1_r_clk := rvclkhdr(clock,lsu_c1_r_clken.asBool,io.scan_mode) + io.lsu_c2_m_clk := rvclkhdr(clock,lsu_c2_m_clken.asBool,io.scan_mode) + io.lsu_c2_r_clk := rvclkhdr(clock,lsu_c2_r_clken.asBool,io.scan_mode) + io.lsu_store_c1_m_clk := rvclkhdr(clock,lsu_store_c1_m_clken.asBool,io.scan_mode) + io.lsu_store_c1_r_clk := rvclkhdr(clock,lsu_store_c1_r_clken.asBool,io.scan_mode) + io.lsu_stbuf_c1_clk := rvclkhdr(clock,lsu_stbuf_c1_clken.asBool,io.scan_mode) + io.lsu_bus_ibuf_c1_clk := rvclkhdr(clock,lsu_bus_ibuf_c1_clken.asBool,io.scan_mode) + io.lsu_bus_obuf_c1_clk := rvclkhdr(clock,lsu_bus_obuf_c1_clken.asBool,io.scan_mode) + io.lsu_bus_buf_c1_clk := rvclkhdr(clock,lsu_bus_buf_c1_clken.asBool,io.scan_mode) + io.lsu_busm_clk := rvclkhdr(clock,io.lsu_bus_clk_en.asBool,io.scan_mode) + io.lsu_free_c2_clk := rvclkhdr(clock,lsu_free_c2_clken.asBool,io.scan_mode) } object cgcmain extends App{ - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_clkdomain())) + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_clkdomain())) } diff --git a/src/main/scala/lsu/el2_lsu_dccm_ctl.scala b/src/main/scala/lsu/el2_lsu_dccm_ctl.scala index 00af3b92..7a7f3b0e 100644 --- a/src/main/scala/lsu/el2_lsu_dccm_ctl.scala +++ b/src/main/scala/lsu/el2_lsu_dccm_ctl.scala @@ -17,7 +17,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib val lsu_free_c2_clk = Input(Clock()) //tbd val lsu_c1_r_clk = Input(Clock()) val lsu_store_c1_r_clk = Input(Clock()) - // val clk = Input(Clock()) //tbd + // val clk = Input(Clock()) //tbd val lsu_pkt_d = Input(new el2_lsu_pkt_t()) val lsu_pkt_m = Input(new el2_lsu_pkt_t()) @@ -219,13 +219,13 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib io.dccm_rd_addr_hi := io.end_addr_d(DCCM_BITS-1,0) io.dccm_wr_data_lo := Mux(io.ld_single_ecc_error_r_ff.asBool, - Mux(ld_single_ecc_error_lo_r_ff===0.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) , + Mux(ld_single_ecc_error_lo_r_ff===1.U,Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0)) , Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0))) , Mux(io.dma_dccm_wen.asBool,Cat(io.dma_dccm_wdata_ecc_lo(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_lo(DCCM_DATA_WIDTH-1,0)), Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0)))) io.dccm_wr_data_hi := Mux(io.ld_single_ecc_error_r_ff.asBool, - Mux(ld_single_ecc_error_hi_r_ff===0.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)), + Mux(ld_single_ecc_error_hi_r_ff===1.U, Cat(io.sec_data_ecc_hi_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_hi_r_ff(DCCM_DATA_WIDTH-1,0)), Cat(io.sec_data_ecc_lo_r_ff(DCCM_ECC_WIDTH-1,0),io.sec_data_lo_r_ff(DCCM_DATA_WIDTH-1,0))), Mux(io.dma_dccm_wen.asBool, Cat(io.dma_dccm_wdata_ecc_hi(DCCM_ECC_WIDTH-1,0),io.dma_dccm_wdata_hi(DCCM_DATA_WIDTH-1,0)), Cat(io.stbuf_ecc_any(DCCM_ECC_WIDTH-1,0),io.stbuf_data_any(DCCM_DATA_WIDTH-1,0)))) @@ -239,9 +239,9 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib (Fill(4,io.lsu_pkt_r.half) & 3.U(4.W)) | (Fill(4,io.lsu_pkt_r.word) & 15.U(4.W))) val store_byteen_ext_m = WireInit(UInt(8.W),0.U) - store_byteen_ext_m := store_byteen_m(3,0) << io.lsu_addr_m(1,0) // The packet in m + store_byteen_ext_m := store_byteen_m(3,0) << io.lsu_addr_m(1,0) // The packet in m val store_byteen_ext_r = WireInit(UInt(8.W),0.U) - store_byteen_ext_r := store_byteen_r(3,0) << io.lsu_addr_r(1,0) + store_byteen_ext_r := store_byteen_r(3,0) << io.lsu_addr_r(1,0) //LM: If store buffer addr matches with the address in the m-stage then there will be bypassed val dccm_wr_bypass_d_m_lo = (io.stbuf_addr_any(DCCM_BITS-1,2) === io.lsu_addr_m(DCCM_BITS-1,2)) & io.addr_in_dccm_m @@ -283,7 +283,7 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib io.store_data_lo_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i).asBool, store_data_lo_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_lo).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_lo_m((8*i)+7,8*i))))))),0.U)} io.store_data_hi_r := withClock(io.lsu_store_c1_r_clk){RegNext(Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux(store_byteen_ext_m(i+4).asBool,store_data_hi_m((8*i)+7,8*i), Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_m_hi).asBool, io.stbuf_data_any((8*i)+7,8*i),io.sec_data_hi_m((8*i)+7,8*i))))))),0.U)} io.store_datafn_lo_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_lo_r((8*i)+7,8*i)))))) - io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_lo & !store_byteen_ext_r(i)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i)))))) + io.store_datafn_hi_r := Reverse(Cat(VecInit.tabulate(4)(i=> Reverse(Mux((io.lsu_stbuf_commit_any & dccm_wr_bypass_d_r_hi & !store_byteen_ext_r(i+4)).asBool,io.stbuf_data_any((8*i)+7,8*i),io.store_data_hi_r((8*i)+7,8*i)))))) io.store_data_r := (Cat(io.store_data_hi_r(31,0),io.store_data_lo_r(31,0)) >> 8.U*io.lsu_addr_r(1,0)) & Reverse(Cat(VecInit.tabulate(4)(i=> Fill(8,store_byteen_r(i))))) } io.dccm_rdata_lo_m := io.dccm_rd_data_lo(DCCM_DATA_WIDTH-1,0) //4 lines @@ -294,8 +294,8 @@ class el2_lsu_dccm_ctl extends Module with RequireAsyncReset with el2_lib io.picm_wren := (io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_pic_r & io.lsu_commit_r) | io.dma_pic_wen io.picm_rden := io.lsu_pkt_d.valid & io.lsu_pkt_d.load & io.addr_in_pic_d io.picm_mken := io.lsu_pkt_d.valid & io.lsu_pkt_d.store & io.addr_in_pic_d - io.picm_rdaddr := PIC_BASE_ADDR | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0)) - io.picm_wraddr := PIC_BASE_ADDR | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0))) + io.picm_rdaddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),io.lsu_addr_d(PIC_BITS-1,0)) + io.picm_wraddr := aslong(PIC_BASE_ADDR).U | Cat(Fill(32-PIC_BITS,0.U),Mux(io.dma_pic_wen.asBool,io.dma_mem_addr(PIC_BITS-1,0),io.lsu_addr_r(PIC_BITS-1,0))) io.picm_mask_data_m := picm_rd_data_m(31,0) io.picm_wr_data := Mux(io.dma_pic_wen.asBool,io.dma_mem_wdata(31,0),io.store_datafn_lo_r(31,0)) diff --git a/src/main/scala/lsu/el2_lsu_dccm_mem.scala b/src/main/scala/lsu/el2_lsu_dccm_mem.scala deleted file mode 100644 index 93b40fb2..00000000 --- a/src/main/scala/lsu/el2_lsu_dccm_mem.scala +++ /dev/null @@ -1,99 +0,0 @@ -package lsu -import include._ -import lib._ -import snapshot._ -import scala.math._ -import chisel3._ -import chisel3.util._ -class el2_lsu_dccm_mem extends Module { - val io = IO(new Bundle{ - //implicit clk and rst_l - val clk_override = Input(UInt(1.W)) - val scan_mode = Input(UInt(1.W)) - val dccm_wren = Input(UInt(1.W)) - val dccm_rden = Input(UInt(1.W)) - val dccm_wr_addr_lo = Input(UInt(pt1.DCCM_BITS.W)) - val dccm_wr_addr_hi = Input(UInt(pt1.DCCM_BITS.W)) - val dccm_rd_addr_lo = Input(UInt(pt1.DCCM_BITS.W)) - val dccm_rd_addr_hi = Input(UInt(pt1.DCCM_BITS.W)) - val dccm_wr_data_lo = Input(UInt(pt1.DCCM_FDATA_WIDTH.W)) - val dccm_wr_data_hi = Input(UInt(pt1.DCCM_FDATA_WIDTH.W)) - val dccm_rd_data_lo = Output(UInt(pt1.DCCM_FDATA_WIDTH.W)) - val dccm_rd_data_hi = Output(UInt(pt1.DCCM_FDATA_WIDTH.W)) - }) - //DCCM_BYTE_WIDTH = 4 - //DCCM_WIDTH_BITS = 2 - - //DCCM_NUM_BANKS = 4 - //DCCM_BANK_BITS = 2 - - //DCCM_BITS = 16 - //DCCM_FDATA_WIDTH = 39 - - //DCCM_SIZE = 64 - - //DCCM_INDEX_BITS = 12 - //DCCM_INDEX_DEPTH = 4K - - - val DCCM_WIDTH_BITS = log2Ceil(pt1.DCCM_BYTE_WIDTH) - val DCCM_INDEX_BITS = pt1.DCCM_BITS - pt1.DCCM_BANK_BITS - pt1.DCCM_WIDTH_BITS - val DCCM_INDEX_DEPTH = (pt1.DCCM_SIZE*1024)/(pt1.DCCM_BYTE_WIDTH*pt1.DCCM_NUM_BANKS) - - val addr_bank = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt((pt1.DCCM_BITS-pt1.DCCM_BANK_BITS+2).W))) //[15:4] => [11:0] 12 bits per bank => - - //val rd_addr_even = Wire(UInt((pt1.DCCM_BITS-(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)).W)) //[15:4] - //val rd_addr_odd = Wire(UInt((pt1.DCCM_BITS-(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)).W)) //[15:4] - - // val dccm_bank_dout = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt(pt1.DCCM_FDATA_WIDTH.W))) // 3:0, 38:0 - val wr_data_bank = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt(pt1.DCCM_FDATA_WIDTH.W))) // 3:0, 38:0 - - val dccm_rd_addr_lo_q = RegNext(io.dccm_rd_addr_lo(DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,DCCM_WIDTH_BITS),0.U) //[3:2] => [1:0] - val dccm_rd_addr_hi_q = RegNext(io.dccm_rd_addr_hi(DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,DCCM_WIDTH_BITS),0.U) - - - //2+2:2 => 4:2rd_unaligned - val rd_unaligned = io.dccm_rd_addr_lo(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) =/= io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) - val wr_unaligned = io.dccm_wr_addr_lo(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) =/= io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) - - - - val wren_bank = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> io.dccm_wren & ((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) | (io.dccm_wr_addr_lo(pt1.DCCM_BANK_BITS+1,2) === i.U)).asUInt))) - val rden_bank = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> io.dccm_rden & ((io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) | (io.dccm_rd_addr_lo(pt1.DCCM_BANK_BITS+1,2) === i.U)).asUInt))) - val dccm_clken = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> wren_bank(i) | rden_bank(i) | io.clk_override))) - - - //[15:4] => [11:0] 12 bits per bank - addr_bank := VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> Mux(wren_bank(i).asBool, - Mux(((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & wr_unaligned), - io.dccm_wr_addr_hi(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS), - io.dccm_wr_addr_lo(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)), - - Mux(((io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & rd_unaligned), - io.dccm_rd_addr_hi(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS), - io.dccm_rd_addr_lo(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)))) - - wr_data_bank := VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> - Mux(((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & wr_unaligned), - io.dccm_wr_data_hi(pt1.DCCM_FDATA_WIDTH-1,0), - io.dccm_wr_data_lo(pt1.DCCM_FDATA_WIDTH-1,0))) - - - - - val mem =SyncReadMem(DCCM_INDEX_DEPTH, Vec(pt1.DCCM_NUM_BANKS, UInt(39.W))) - // Create one write port and one read port - (0 to pt1.DCCM_NUM_BANKS-1).foreach(i => - when(wren_bank(i)& dccm_clken(i)){ - mem.write(addr_bank(i), wr_data_bank)}) - - val dccm_bank_dout = VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i => mem.read(addr_bank(i), ~wren_bank(i)& dccm_clken(i)))//ME && ~WE - - io.dccm_rd_data_lo := dccm_bank_dout(dccm_rd_addr_lo_q).asUInt - io.dccm_rd_data_hi := dccm_bank_dout(dccm_rd_addr_hi_q).asUInt -} - -object DCCM extends App{ - println("Generate Verilog") - chisel3.Driver.execute(args, ()=> new el2_lsu_dccm_mem) -} diff --git a/src/main/scala/lsu/el2_lsu_ecc.scala b/src/main/scala/lsu/el2_lsu_ecc.scala index c71fade3..1e24c902 100644 --- a/src/main/scala/lsu/el2_lsu_ecc.scala +++ b/src/main/scala/lsu/el2_lsu_ecc.scala @@ -71,7 +71,7 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset { val dccm_wdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) val dccm_rdata_hi_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) val dccm_rdata_lo_any = WireInit(0.U(DCCM_DATA_WIDTH.W)) - // val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) + // val dccm_wdata_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) //val dccm_wdata_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) val dccm_data_ecc_hi_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) val dccm_data_ecc_lo_any = WireInit(0.U(DCCM_ECC_WIDTH.W)) @@ -92,34 +92,34 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset { io.lsu_single_ecc_error_m :=0.U io.lsu_double_ecc_error_m :=0.U -//////////////////////////////CODE STARTS HERE/////////////////////// + //////////////////////////////CODE STARTS HERE/////////////////////// val (ecc_out_hi_nc, sec_data_hi_any, single_ecc_error_hi_any, double_ecc_error_hi_any) = if(DCCM_ENABLE) rvecc_decode(is_ldst_hi_any, dccm_rdata_hi_any, dccm_data_ecc_hi_any, 0.U) else (0.U, 0.U, 0.U, 0.U) val ( ecc_out_lo_nc, sec_data_lo_any, single_ecc_error_lo_any, double_ecc_error_lo_any) = if(DCCM_ENABLE) rvecc_decode(is_ldst_lo_any, dccm_rdata_lo_any, dccm_data_ecc_lo_any, 0.U) else (0.U, 0.U, 0.U, 0.U) - val dccm_wdata_ecc_lo_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_lo_any) else (0.U) - val dccm_wdata_ecc_hi_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_hi_any) else (0.U) + val dccm_wdata_ecc_lo_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_lo_any) else (0.U) + val dccm_wdata_ecc_hi_any = if(DCCM_ENABLE) rvecc_encode(dccm_wdata_hi_any) else (0.U) - when (LOAD_TO_USE_PLUS1.B) { - ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2) - is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.load | io.lsu_pkt_r.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r - is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable - is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.dma) & !io.dec_tlu_core_ecc_disable - is_ldst_hi_any := is_ldst_hi_r - dccm_rdata_hi_any := io.dccm_rdata_hi_r - dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r - is_ldst_lo_any := is_ldst_lo_r - dccm_rdata_lo_any := io.dccm_rdata_lo_r - dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_r - io.sec_data_hi_r := sec_data_hi_any; - io.single_ecc_error_hi_r := single_ecc_error_hi_any - double_ecc_error_hi_r := double_ecc_error_hi_any - io.sec_data_lo_r := sec_data_lo_any - io.single_ecc_error_lo_r := single_ecc_error_lo_any - double_ecc_error_lo_r := double_ecc_error_lo_any - io.lsu_single_ecc_error_r := io.single_ecc_error_hi_r | io.single_ecc_error_lo_r; - io.lsu_double_ecc_error_r := double_ecc_error_hi_r | double_ecc_error_lo_r - } + when (LOAD_TO_USE_PLUS1.B) { + ldst_dual_r := io.lsu_addr_r(2) =/= io.end_addr_r(2) + is_ldst_r := io.lsu_pkt_r.valid & (io.lsu_pkt_r.load | io.lsu_pkt_r.store) & io.addr_in_dccm_r & io.lsu_dccm_rden_r + is_ldst_lo_r := is_ldst_r & !io.dec_tlu_core_ecc_disable + is_ldst_hi_r := is_ldst_r & (ldst_dual_r | io.lsu_pkt_r.dma) & !io.dec_tlu_core_ecc_disable + is_ldst_hi_any := is_ldst_hi_r + dccm_rdata_hi_any := io.dccm_rdata_hi_r + dccm_data_ecc_hi_any := io.dccm_data_ecc_hi_r + is_ldst_lo_any := is_ldst_lo_r + dccm_rdata_lo_any := io.dccm_rdata_lo_r + dccm_data_ecc_lo_any := io.dccm_data_ecc_lo_r + io.sec_data_hi_r := sec_data_hi_any; + io.single_ecc_error_hi_r := single_ecc_error_hi_any + double_ecc_error_hi_r := double_ecc_error_hi_any + io.sec_data_lo_r := sec_data_lo_any + io.single_ecc_error_lo_r := single_ecc_error_lo_any + double_ecc_error_lo_r := double_ecc_error_lo_any + io.lsu_single_ecc_error_r := io.single_ecc_error_hi_r | io.single_ecc_error_lo_r; + io.lsu_double_ecc_error_r := double_ecc_error_hi_r | double_ecc_error_lo_r + } .otherwise { ldst_dual_m := io.lsu_addr_m(2) =/= io.end_addr_m(2) is_ldst_m := io.lsu_pkt_m.valid & (io.lsu_pkt_m.load | io.lsu_pkt_m.store) & io.addr_in_dccm_m & io.lsu_dccm_rden_m @@ -146,13 +146,13 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset { withClock(io.lsu_c2_r_clk) {io.sec_data_lo_r := RegNext(io.sec_data_lo_m,0.U)} } // Logic for ECC generation during write - dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any)) - dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, io.stbuf_data_any)) - io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any - io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any - io.stbuf_ecc_any := dccm_wdata_ecc_lo_any - io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any - io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any + dccm_wdata_lo_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_lo_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_lo, io.stbuf_data_any)) + dccm_wdata_hi_any := Mux(io.ld_single_ecc_error_r_ff.asBool, io.sec_data_hi_r_ff,Mux(io.dma_dccm_wen.asBool, io.dma_dccm_wdata_hi, io.stbuf_data_any)) + io.sec_data_ecc_hi_r_ff := dccm_wdata_ecc_hi_any + io.sec_data_ecc_lo_r_ff := dccm_wdata_ecc_lo_any + io.stbuf_ecc_any := dccm_wdata_ecc_lo_any + io.dma_dccm_wdata_ecc_hi := dccm_wdata_ecc_hi_any + io.dma_dccm_wdata_ecc_lo := dccm_wdata_ecc_lo_any io.sec_data_hi_r_ff := rvdffe(io.sec_data_hi_r, io.ld_single_ecc_error_r,clock,io.scan_mode) io.sec_data_lo_r_ff := rvdffe(io.sec_data_lo_r, io.ld_single_ecc_error_r,clock,io.scan_mode) diff --git a/src/main/scala/lsu/el2_lsu_lsc_ctl.scala b/src/main/scala/lsu/el2_lsu_lsc_ctl.scala index 61303c33..5504b972 100644 --- a/src/main/scala/lsu/el2_lsu_lsc_ctl.scala +++ b/src/main/scala/lsu/el2_lsu_lsc_ctl.scala @@ -222,15 +222,15 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib val store_data_m_in = Mux(io.lsu_pkt_d.store_data_bypass_d.asBool,io.lsu_result_m(31,0),store_data_d(31,0)) val store_data_pre_m = withClock(io.lsu_store_c1_m_clk){RegNext(store_data_m_in,0.U)} - io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} - io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} - io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)} - io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)} - io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} - io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)} - io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)} - io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)} - io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)} + io.lsu_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.lsu_addr_d,0.U)} + io.lsu_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.lsu_addr_m,0.U)} + io.end_addr_m := withClock(io.lsu_c1_m_clk){RegNext(io.end_addr_d,0.U)} + io.end_addr_r := withClock(io.lsu_c1_r_clk){RegNext(io.end_addr_m,0.U)} + io.addr_in_dccm_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_dccm_d,0.U)} + io.addr_in_dccm_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_dccm_m,0.U)} + io.addr_in_pic_m := withClock(io.lsu_c1_m_clk){RegNext(io.addr_in_pic_d,0.U)} + io.addr_in_pic_r := withClock(io.lsu_c1_r_clk){RegNext(io.addr_in_pic_m,0.U)} + io.addr_external_m := withClock(io.lsu_c1_m_clk){RegNext(addr_external_d,0.U)} val addr_external_r = withClock(io.lsu_c1_r_clk){RegNext(io.addr_external_m,0.U)} val bus_read_data_r = withClock(io.lsu_c1_r_clk){RegNext(io.bus_read_data_m,0.U)} // Fast interrupt address @@ -278,4 +278,4 @@ class el2_lsu_lsc_ctl extends Module with RequireAsyncReset with el2_lib object lsu_lsc_ctl extends App{ println("Generate Verilog") println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_lsc_ctl())) -} \ No newline at end of file +} diff --git a/src/main/scala/lsu/el2_lsu_stbuf.scala b/src/main/scala/lsu/el2_lsu_stbuf.scala index a677e939..bb3710ab 100644 --- a/src/main/scala/lsu/el2_lsu_stbuf.scala +++ b/src/main/scala/lsu/el2_lsu_stbuf.scala @@ -6,275 +6,275 @@ import chisel3.util._ import include._ @chiselName -class el2_lsu_stbuf extends Module with param with RequireAsyncReset { - val io = IO (new Bundle { - val lsu_c1_m_clk = Input(Clock()) - val lsu_c1_r_clk = Input(Clock()) - val lsu_stbuf_c1_clk = Input(Clock()) - val lsu_free_c2_clk = Input(Clock()) - val lsu_pkt_m = Input(new el2_lsu_pkt_t) - val lsu_pkt_r = Input(new el2_lsu_pkt_t) - val store_stbuf_reqvld_r = Input(Bool()) - val lsu_commit_r = Input(Bool()) - val dec_lsu_valid_raw_d = Input(Bool()) - val store_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W)) - val store_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W)) - val store_datafn_hi_r = Input(UInt(DCCM_DATA_WIDTH.W)) - val store_datafn_lo_r = Input(UInt(DCCM_DATA_WIDTH.W)) - val lsu_stbuf_commit_any = Input(Bool()) - val lsu_addr_d = Input(UInt(LSU_SB_BITS.W)) - val lsu_addr_m = Input(UInt(32.W)) - val lsu_addr_r = Input(UInt(32.W)) - val end_addr_d = Input(UInt(LSU_SB_BITS.W)) - val end_addr_m = Input(UInt(32.W)) - val end_addr_r = Input(UInt(32.W)) +class el2_lsu_stbuf extends Module with el2_lib with RequireAsyncReset { + val io = IO (new Bundle { + val lsu_c1_m_clk = Input(Clock()) + val lsu_c1_r_clk = Input(Clock()) + val lsu_stbuf_c1_clk = Input(Clock()) + val lsu_free_c2_clk = Input(Clock()) + val lsu_pkt_m = Input(new el2_lsu_pkt_t) + val lsu_pkt_r = Input(new el2_lsu_pkt_t) + val store_stbuf_reqvld_r = Input(Bool()) + val lsu_commit_r = Input(Bool()) + val dec_lsu_valid_raw_d = Input(Bool()) + val store_data_hi_r = Input(UInt(DCCM_DATA_WIDTH.W)) + val store_data_lo_r = Input(UInt(DCCM_DATA_WIDTH.W)) + val store_datafn_hi_r = Input(UInt(DCCM_DATA_WIDTH.W)) + val store_datafn_lo_r = Input(UInt(DCCM_DATA_WIDTH.W)) + val lsu_stbuf_commit_any = Input(Bool()) + val lsu_addr_d = Input(UInt(LSU_SB_BITS.W)) + val lsu_addr_m = Input(UInt(32.W)) + val lsu_addr_r = Input(UInt(32.W)) + val end_addr_d = Input(UInt(LSU_SB_BITS.W)) + val end_addr_m = Input(UInt(32.W)) + val end_addr_r = Input(UInt(32.W)) - val addr_in_dccm_m = Input(Bool()) - val addr_in_dccm_r = Input(Bool()) - val lsu_cmpen_m = Input(Bool()) - val scan_mode = Input(Bool()) + val addr_in_dccm_m = Input(Bool()) + val addr_in_dccm_r = Input(Bool()) + val lsu_cmpen_m = Input(Bool()) + val scan_mode = Input(Bool()) - //Outputs - val stbuf_reqvld_any = Output(Bool()) - val stbuf_reqvld_flushed_any = Output(Bool()) - val stbuf_addr_any = Output(UInt(LSU_SB_BITS.W)) - val stbuf_data_any = Output(UInt(DCCM_DATA_WIDTH.W)) - val lsu_stbuf_full_any = Output(Bool()) - val lsu_stbuf_empty_any = Output(Bool()) - val ldst_stbuf_reqvld_r = Output(Bool()) - val stbuf_fwddata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W)) - val stbuf_fwddata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W)) - val stbuf_fwdbyteen_hi_m = Output(UInt(DCCM_BYTE_WIDTH.W)) - val stbuf_fwdbyteen_lo_m = Output(UInt(DCCM_BYTE_WIDTH.W)) - // val testout = Output(Vec(LSU_STBUF_DEPTH, UInt(8.W))) - }) + //Outputs + val stbuf_reqvld_any = Output(Bool()) + val stbuf_reqvld_flushed_any = Output(Bool()) + val stbuf_addr_any = Output(UInt(LSU_SB_BITS.W)) + val stbuf_data_any = Output(UInt(DCCM_DATA_WIDTH.W)) + val lsu_stbuf_full_any = Output(Bool()) + val lsu_stbuf_empty_any = Output(Bool()) + val ldst_stbuf_reqvld_r = Output(Bool()) + val stbuf_fwddata_hi_m = Output(UInt(DCCM_DATA_WIDTH.W)) + val stbuf_fwddata_lo_m = Output(UInt(DCCM_DATA_WIDTH.W)) + val stbuf_fwdbyteen_hi_m = Output(UInt(DCCM_BYTE_WIDTH.W)) + val stbuf_fwdbyteen_lo_m = Output(UInt(DCCM_BYTE_WIDTH.W)) + // val testout = Output(Vec(LSU_STBUF_DEPTH, UInt(8.W))) + }) - io.stbuf_reqvld_any := 0.U - io.stbuf_reqvld_flushed_any := 0.U - io.stbuf_addr_any := 0.U - io.stbuf_data_any := 0.U - io.lsu_stbuf_full_any := 0.U - io.lsu_stbuf_empty_any := 0.U - io.ldst_stbuf_reqvld_r := 0.U - io.stbuf_fwddata_hi_m := 0.U - io.stbuf_fwddata_lo_m := 0.U - io.stbuf_fwdbyteen_hi_m := 0.U - io.stbuf_fwdbyteen_lo_m := 0.U + io.stbuf_reqvld_any := 0.U + io.stbuf_reqvld_flushed_any := 0.U + io.stbuf_addr_any := 0.U + io.stbuf_data_any := 0.U + io.lsu_stbuf_full_any := 0.U + io.lsu_stbuf_empty_any := 0.U + io.ldst_stbuf_reqvld_r := 0.U + io.stbuf_fwddata_hi_m := 0.U + io.stbuf_fwddata_lo_m := 0.U + io.stbuf_fwdbyteen_hi_m := 0.U + io.stbuf_fwdbyteen_lo_m := 0.U - val stbuf_vld = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) + val stbuf_vld = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) val stbuf_wr_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) - val stbuf_dma_kill_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) - val stbuf_dma_kill = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) - val stbuf_reset = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) - val store_byteen_ext_r = WireInit(UInt(8.W), init= 0.U) + val stbuf_dma_kill_en = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) + val stbuf_dma_kill = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) + val stbuf_reset = WireInit(UInt(LSU_STBUF_DEPTH.W), init = 0.U) + val store_byteen_ext_r = WireInit(UInt(8.W), init= 0.U) val stbuf_addr = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W))) stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i => 0.U) - val stbuf_byteen = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W))) - stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i => 0.U) - val stbuf_data = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W))) - stbuf_data := (0 until LSU_STBUF_DEPTH).map(i => 0.U) + val stbuf_byteen = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W))) + stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i => 0.U) + val stbuf_data = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W))) + stbuf_data := (0 until LSU_STBUF_DEPTH).map(i => 0.U) val stbuf_addrin = Wire(Vec(LSU_STBUF_DEPTH,UInt(LSU_SB_BITS.W))) stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i => 0.U) - val stbuf_datain = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W))) - stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => 0.U) - val stbuf_byteenin = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W))) - stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U) - val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) - val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) - val ldst_dual_m = WireInit(Bool(),init = 0.U) - val ldst_dual_r = WireInit(Bool(),init = 0.U) - val cmpaddr_hi_m = WireInit(0.U(16.W)) - val stbuf_specvld_m = WireInit(0.U(2.W)) - val stbuf_specvld_r = WireInit(0.U(2.W)) - val cmpaddr_lo_m = WireInit(0.U(16.W)) - val stbuf_fwdata_hi_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U) - val stbuf_fwdata_lo_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U) - val ld_byte_rhit_lo_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_rhit_hi_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_rhit_lo_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_rhit_hi_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_hit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_rhit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_hit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ld_byte_rhit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) - val ldst_byteen_ext_r = WireInit(UInt(8.W),init = 0.U) - val ld_fwddata_rpipe_lo = WireInit(UInt(32.W),init = 0.U) - val ld_fwddata_rpipe_hi = WireInit(UInt(32.W),init = 0.U) + val stbuf_datain = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_DATA_WIDTH.W))) + stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i => 0.U) + val stbuf_byteenin = Wire(Vec(LSU_STBUF_DEPTH,UInt(DCCM_BYTE_WIDTH.W))) + stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i => 0.U) + val WrPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) + val RdPtr = WireInit(UInt(log2Ceil(LSU_STBUF_DEPTH).W),init = 0.U) + val ldst_dual_m = WireInit(Bool(),init = 0.U) + val ldst_dual_r = WireInit(Bool(),init = 0.U) + val cmpaddr_hi_m = WireInit(0.U(16.W)) + val stbuf_specvld_m = WireInit(0.U(2.W)) + val stbuf_specvld_r = WireInit(0.U(2.W)) + val cmpaddr_lo_m = WireInit(0.U(16.W)) + val stbuf_fwdata_hi_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U) + val stbuf_fwdata_lo_pre_m = WireInit(UInt(DCCM_DATA_WIDTH.W),init = 0.U) + val ld_byte_rhit_lo_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_rhit_hi_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_rhit_lo_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_rhit_hi_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_hit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_rhit_lo = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_hit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ld_byte_rhit_hi = WireInit(UInt(DCCM_BYTE_WIDTH.W),init = 0.U) + val ldst_byteen_ext_r = WireInit(UInt(8.W),init = 0.U) + val ld_fwddata_rpipe_lo = WireInit(UInt(32.W),init = 0.U) + val ld_fwddata_rpipe_hi = WireInit(UInt(32.W),init = 0.U) - // - val datain1 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) - val datain2 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) - val datain3 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) - val datain4 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) + // + val datain1 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) + val datain2 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) + val datain3 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) + val datain4 = Wire(Vec(LSU_STBUF_DEPTH,UInt(8.W))) - //////////////////////////////////////Code Start here/////////////////////////////// - val ldst_byteen_r = Mux1H(Seq( - io.lsu_pkt_r.by.asBool -> "b00000001".U, - io.lsu_pkt_r.half.asBool ->"b00000011".U, - io.lsu_pkt_r.word.asBool -> "b00001111".U, - io.lsu_pkt_r.dword.asBool -> "b11111111".U - )) - val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2) - val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r + //////////////////////////////////////Code Start here/////////////////////////////// + val ldst_byteen_r = Mux1H(Seq( + io.lsu_pkt_r.by.asBool -> "b00000001".U, + io.lsu_pkt_r.half.asBool ->"b00000011".U, + io.lsu_pkt_r.word.asBool -> "b00001111".U, + io.lsu_pkt_r.dword.asBool -> "b11111111".U + )) + val ldst_dual_d = io.lsu_addr_d (2) =/= io.end_addr_d(2) + val dual_stbuf_write_r = ldst_dual_r & io.store_stbuf_reqvld_r - store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0) + store_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0) val store_byteen_hi_r = store_byteen_ext_r (7,4) & Fill(4, io.lsu_pkt_r.store) val store_byteen_lo_r = store_byteen_ext_r (3,0) & Fill(4, io.lsu_pkt_r.store) - val RdPtrPlus1 = RdPtr + "b01".U - val WrPtrPlus1 = WrPtr + "b01".U - val WrPtrPlus2 = WrPtr + "b10".U + val RdPtrPlus1 = RdPtr + "b01".U + val WrPtrPlus1 = WrPtr + "b01".U + val WrPtrPlus2 = WrPtr + "b10".U - io.ldst_stbuf_reqvld_r := io.lsu_commit_r & io.store_stbuf_reqvld_r + io.ldst_stbuf_reqvld_r := io.lsu_commit_r & io.store_stbuf_reqvld_r val store_matchvec_lo_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.lsu_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_)) val store_matchvec_hi_r = (0 until LSU_STBUF_DEPTH).map(i=> (stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === io.end_addr_r(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) & stbuf_vld(i) & !stbuf_dma_kill(i) & dual_stbuf_write_r & !stbuf_reset(i)).asUInt).reverse.reduce(Cat(_,_)) - val store_coalesce_lo_r = store_matchvec_lo_r.orR - val store_coalesce_hi_r = store_matchvec_hi_r.orR + val store_coalesce_lo_r = store_matchvec_lo_r.orR + val store_coalesce_hi_r = store_matchvec_hi_r.orR - stbuf_wr_en := (0 until LSU_STBUF_DEPTH).map(i=> (io.ldst_stbuf_reqvld_r & ( - ((i.asUInt === WrPtr) & !store_coalesce_lo_r) | - ((i.asUInt === WrPtr) & dual_stbuf_write_r & !store_coalesce_hi_r) | - ((i.asUInt === WrPtrPlus1) & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) | - store_matchvec_lo_r(i) | store_matchvec_hi_r(i))).asUInt).reverse.reduce(Cat(_,_)) + stbuf_wr_en := (0 until LSU_STBUF_DEPTH).map(i=> (io.ldst_stbuf_reqvld_r & ( + ((i.asUInt === WrPtr) & !store_coalesce_lo_r) | + ((i.asUInt === WrPtr) & dual_stbuf_write_r & !store_coalesce_hi_r) | + ((i.asUInt === WrPtrPlus1) & dual_stbuf_write_r & !(store_coalesce_lo_r | store_coalesce_hi_r)) | + store_matchvec_lo_r(i) | store_matchvec_hi_r(i))).asUInt).reverse.reduce(Cat(_,_)) stbuf_reset := (0 until LSU_STBUF_DEPTH).map(i=> ((io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any) & (i.asUInt === RdPtr).asBool).asUInt).reverse.reduce(Cat(_,_)) val sel_lo = (0 until LSU_STBUF_DEPTH).map(i=> (((!ldst_dual_r | io.store_stbuf_reqvld_r) & (i.asUInt === WrPtr).asBool & !store_coalesce_lo_r) | store_matchvec_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) - stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), io.lsu_addr_r(LSU_SB_BITS-1,0), io.end_addr_r(LSU_SB_BITS-1,0))) - stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt) + stbuf_addrin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), io.lsu_addr_r(LSU_SB_BITS-1,0), io.end_addr_r(LSU_SB_BITS-1,0))) + stbuf_byteenin := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), stbuf_byteen(i) | store_byteen_lo_r, stbuf_byteen(i) | store_byteen_hi_r).asUInt) - datain1 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(0) | store_byteen_lo_r(0), io.store_datafn_lo_r(7, 0), stbuf_data(i)(7, 0)), - Mux(!stbuf_byteen(i)(0) | store_byteen_hi_r(0), io.store_datafn_hi_r(7, 0), stbuf_data(i)(7, 0))).asUInt) + datain1 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(0) | store_byteen_lo_r(0), io.store_datafn_lo_r(7, 0), stbuf_data(i)(7, 0)), + Mux(!stbuf_byteen(i)(0) | store_byteen_hi_r(0), io.store_datafn_hi_r(7, 0), stbuf_data(i)(7, 0))).asUInt) - datain2 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(1) | store_byteen_lo_r(1), io.store_datafn_lo_r(15, 8), stbuf_data(i)(15, 8)), - Mux(!stbuf_byteen(i)(1) | store_byteen_hi_r(1), io.store_datafn_hi_r(15, 8), stbuf_data(i)(15, 8))).asUInt) + datain2 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(1) | store_byteen_lo_r(1), io.store_datafn_lo_r(15, 8), stbuf_data(i)(15, 8)), + Mux(!stbuf_byteen(i)(1) | store_byteen_hi_r(1), io.store_datafn_hi_r(15, 8), stbuf_data(i)(15, 8))).asUInt) - datain3 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(2) | store_byteen_lo_r(2), io.store_datafn_lo_r(23, 16), stbuf_data(i)(23, 16)), - Mux(!stbuf_byteen(i)(2) | store_byteen_hi_r(2), io.store_datafn_hi_r(23, 16), stbuf_data(i)(23, 16))).asUInt) + datain3 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(2) | store_byteen_lo_r(2), io.store_datafn_lo_r(23, 16), stbuf_data(i)(23, 16)), + Mux(!stbuf_byteen(i)(2) | store_byteen_hi_r(2), io.store_datafn_hi_r(23, 16), stbuf_data(i)(23, 16))).asUInt) - datain4 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(3) | store_byteen_lo_r(3), io.store_datafn_lo_r(31, 24), stbuf_data(i)(31, 24)), - Mux(!stbuf_byteen(i)(3) | store_byteen_hi_r(3), io.store_datafn_hi_r(31, 24), stbuf_data(i)(31, 24))).asUInt) + datain4 := (0 until LSU_STBUF_DEPTH).map(i=> Mux(sel_lo(i), Mux(!stbuf_byteen(i)(3) | store_byteen_lo_r(3), io.store_datafn_lo_r(31, 24), stbuf_data(i)(31, 24)), + Mux(!stbuf_byteen(i)(3) | store_byteen_hi_r(3), io.store_datafn_hi_r(31, 24), stbuf_data(i)(31, 24))).asUInt) - stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i=>Cat(datain4(i), datain3(i), datain2(i), datain1(i))) - // io.testout := datain3 + stbuf_datain := (0 until LSU_STBUF_DEPTH).map(i=>Cat(datain4(i), datain3(i), datain2(i), datain1(i))) + // io.testout := datain3 -// for (i<- 0 until LSU_STBUF_DEPTH) { + // for (i<- 0 until LSU_STBUF_DEPTH) { stbuf_vld := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),1.U ,stbuf_vld(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) -// stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_addrin(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_)) - stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i=> RegNext(Mux(stbuf_dma_kill_en(i).asBool,1.U ,stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)).reverse.reduce(Cat(_,_)) + // stbuf_addr := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_addrin(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_)) + stbuf_dma_kill := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_free_c2_clk){RegNext(Mux(stbuf_dma_kill_en(i).asBool,1.U ,stbuf_dma_kill(i)) & !stbuf_reset(i), 0.U)}).reverse.reduce(Cat(_,_)) stbuf_byteen := (0 until LSU_STBUF_DEPTH).map(i=> withClock(io.lsu_stbuf_c1_clk){ RegNext(Mux(stbuf_wr_en(i).asBool(),stbuf_byteenin(i) , stbuf_byteen(i)) & Fill(stbuf_byteenin(i).getWidth , !stbuf_reset(i)), 0.U)}) //stbuf_data := (0 until LSU_STBUF_DEPTH).map(i=> RegEnable(stbuf_datain(i), 0.U, stbuf_wr_en(i).asBool())).reverse.reduce(Cat(_,_)) for (i<- 0 until LSU_STBUF_DEPTH) { // withClock(io.lsu_free_c2_clk){ stbuf_dma_kill(i) := RegEnable(1.U & !stbuf_reset(i), 0.U, stbuf_dma_kill_en(i).asBool)} - stbuf_addr(i) := rvdffe(stbuf_addrin(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode) + stbuf_addr(i) := rvdffe(stbuf_addrin(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode) // withClock(io.lsu_stbuf_c1_clk){ stbuf_byteen(i) := RegNext( stbuf_byteenin(i) & Fill(stbuf_byteenin(i).getWidth, !stbuf_reset(i)), 0.U, stbuf_wr_en(i).asBool())} - stbuf_data(i) := rvdffe(stbuf_datain(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode) - } - withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)} - withClock(io.lsu_c1_r_clk){ldst_dual_r := RegNext(ldst_dual_m,0.U)} + stbuf_data(i) := rvdffe(stbuf_datain(i),stbuf_wr_en(i).asBool(),clock,io.scan_mode) + } + withClock(io.lsu_c1_m_clk){ldst_dual_m := RegNext(ldst_dual_d,0.U)} + withClock(io.lsu_c1_r_clk){ldst_dual_r := RegNext(ldst_dual_m,0.U)} - // Store Buffer drain logic - io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr) - io.stbuf_reqvld_any := stbuf_vld(RdPtr) & !stbuf_dma_kill(RdPtr) & !(stbuf_dma_kill_en.orR) - io.stbuf_addr_any := stbuf_addr(RdPtr) - io.stbuf_data_any := stbuf_data(RdPtr) + // Store Buffer drain logic + io.stbuf_reqvld_flushed_any := stbuf_vld(RdPtr) & stbuf_dma_kill(RdPtr) + io.stbuf_reqvld_any := stbuf_vld(RdPtr) & !stbuf_dma_kill(RdPtr) & !(stbuf_dma_kill_en.orR) + io.stbuf_addr_any := stbuf_addr(RdPtr) + io.stbuf_data_any := stbuf_data(RdPtr) val WrPtrEn = ((io.ldst_stbuf_reqvld_r & !dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)) | - (io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r & store_coalesce_lo_r))).asBool - val NxtWrPtr = Mux((io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)).asBool, WrPtrPlus2, WrPtrPlus1) - val RdPtrEn = io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any - val NxtRdPtr = RdPtrPlus1 + (io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r & store_coalesce_lo_r))).asBool + val NxtWrPtr = Mux((io.ldst_stbuf_reqvld_r & dual_stbuf_write_r & !(store_coalesce_hi_r | store_coalesce_lo_r)).asBool, WrPtrPlus2, WrPtrPlus1) + val RdPtrEn = io.lsu_stbuf_commit_any | io.stbuf_reqvld_flushed_any + val NxtRdPtr = RdPtrPlus1 withClock(io.lsu_stbuf_c1_clk){ WrPtr := RegEnable(NxtWrPtr, 0.U, WrPtrEn)} withClock(io.lsu_stbuf_c1_clk){ RdPtr := RegEnable(NxtRdPtr, 0.U, RdPtrEn)} - val stbuf_numvld_any = VecInit.tabulate(LSU_STBUF_DEPTH)(i=>Cat(0.U(3.W), stbuf_vld(i))).reduce (_+_) - val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.addr_in_dccm_m & !io.lsu_pkt_m.dma - val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_dccm_r & !io.lsu_pkt_r.dma + val stbuf_numvld_any = VecInit.tabulate(LSU_STBUF_DEPTH)(i=>Cat(0.U(3.W), stbuf_vld(i))).reduce (_+_) + val isdccmst_m = io.lsu_pkt_m.valid & io.lsu_pkt_m.store & io.addr_in_dccm_m & !io.lsu_pkt_m.dma + val isdccmst_r = io.lsu_pkt_r.valid & io.lsu_pkt_r.store & io.addr_in_dccm_r & !io.lsu_pkt_r.dma - stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m) - stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r) - val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r) + stbuf_specvld_m := Cat(0.U(1.W),isdccmst_m) << (isdccmst_m & ldst_dual_m) + stbuf_specvld_r := Cat(0.U(1.W),isdccmst_r) << (isdccmst_r & ldst_dual_r) + val stbuf_specvld_any = stbuf_numvld_any + Cat(0.U(2.W), stbuf_specvld_m) + Cat(0.U(2.W), stbuf_specvld_r) - io.lsu_stbuf_full_any := Mux((!ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,(stbuf_specvld_any >= LSU_STBUF_DEPTH.U),(stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U)) - io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U + io.lsu_stbuf_full_any := Mux((!ldst_dual_d & io.dec_lsu_valid_raw_d).asBool,(stbuf_specvld_any >= LSU_STBUF_DEPTH.U),(stbuf_specvld_any >= (LSU_STBUF_DEPTH-1).U)) + io.lsu_stbuf_empty_any := stbuf_numvld_any === 0.U - val cmpen_hi_m = io.lsu_cmpen_m & ldst_dual_m - cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) + val cmpen_hi_m = io.lsu_cmpen_m & ldst_dual_m + cmpaddr_hi_m := io.end_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) - val cmpen_lo_m = io.lsu_cmpen_m - cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) + val cmpen_lo_m = io.lsu_cmpen_m + cmpaddr_lo_m := io.lsu_addr_m(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) - val stbuf_match_hi = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_hi_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_)) - val stbuf_match_lo = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_lo_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_)) - stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.dma & io.lsu_pkt_m.store).asUInt).reverse.reduce(Cat(_,_)) + val stbuf_match_hi = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_hi_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_)) + val stbuf_match_lo = (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_addr(i)(LSU_SB_BITS-1,log2Ceil(DCCM_BYTE_WIDTH)) === cmpaddr_lo_m(13,0)) & stbuf_vld(i) & !stbuf_dma_kill(i) & io.addr_in_dccm_m).asUInt).reverse.reduce(Cat(_,_)) + stbuf_dma_kill_en := (0 until LSU_STBUF_DEPTH).map(i=> ((stbuf_match_hi(i) | stbuf_match_lo(i)) & io.lsu_pkt_m.valid & io.lsu_pkt_m.dma & io.lsu_pkt_m.store).asUInt).reverse.reduce(Cat(_,_)) - val stbuf_fwdbyteenvec_hi = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_hi(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt())) - val stbuf_fwdbyteenvec_lo = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_lo(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt())) - val stbuf_fwdbyteen_hi_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_hi(i)(j).asUInt()).reduce(_|_)) - val stbuf_fwdbyteen_lo_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_lo(i)(j).asUInt()).reduce(_|_)) + val stbuf_fwdbyteenvec_hi = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_hi(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt())) + val stbuf_fwdbyteenvec_lo = (0 until LSU_STBUF_DEPTH).map(i=>(0 until DCCM_BYTE_WIDTH).map(j=> stbuf_match_lo(i) & stbuf_byteen(i)(j) & stbuf_vld(i).asUInt())) + val stbuf_fwdbyteen_hi_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_hi(i)(j).asUInt()).reduce(_|_)) + val stbuf_fwdbyteen_lo_pre_m = (0 until LSU_STBUF_DEPTH).map(j=>(0 until DCCM_BYTE_WIDTH).map(i=> stbuf_fwdbyteenvec_lo(i)(j).asUInt()).reduce(_|_)) - val stbuf_fwddata_hi_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_hi(i)) & stbuf_data(i)).reverse.reduce(_|_) - val stbuf_fwddata_lo_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_lo(i)) & stbuf_data(i)).reverse.reduce(_|_) + val stbuf_fwddata_hi_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_hi(i)) & stbuf_data(i)).reverse.reduce(_|_) + val stbuf_fwddata_lo_pre_m = VecInit.tabulate(LSU_STBUF_DEPTH)(i=> Fill(32,stbuf_match_lo(i)) & stbuf_data(i)).reverse.reduce(_|_) - ldst_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0) - val ldst_byteen_hi_r = ldst_byteen_ext_r(7,4) - val ldst_byteen_lo_r = ldst_byteen_ext_r(3,0) + ldst_byteen_ext_r := ldst_byteen_r << io.lsu_addr_r(1,0) + val ldst_byteen_hi_r = ldst_byteen_ext_r(7,4) + val ldst_byteen_lo_r = ldst_byteen_ext_r(3,0) - val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma - val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma - val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r - val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r + val ld_addr_rhit_lo_lo = (io.lsu_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma + val ld_addr_rhit_lo_hi = (io.end_addr_m(31,2) === io.lsu_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma + val ld_addr_rhit_hi_lo = (io.lsu_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r + val ld_addr_rhit_hi_hi = (io.end_addr_m(31,2) === io.end_addr_r(31,2)) & io.lsu_pkt_r.valid & io.lsu_pkt_r.store & !io.lsu_pkt_r.dma & dual_stbuf_write_r - ld_byte_rhit_lo_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_lo & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_lo_hi & ldst_byteen_lo_r(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_lo & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_addr_rhit_hi_hi & ldst_byteen_hi_r(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_)) - ld_byte_rhit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_)) + ld_byte_rhit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_)) - val fwdpipe1_lo = (Fill(8, ld_byte_rhit_lo_lo(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_lo(0)) & io.store_data_hi_r(7,0)) - val fwdpipe2_lo = (Fill(8, ld_byte_rhit_lo_lo(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_lo(1)) & io.store_data_hi_r(15,8)) - val fwdpipe3_lo = (Fill(8, ld_byte_rhit_lo_lo(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_lo(2)) & io.store_data_hi_r(23,16)) - val fwdpipe4_lo = (Fill(8, ld_byte_rhit_lo_lo(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_lo(3)) & io.store_data_hi_r(31,8)) - ld_fwddata_rpipe_lo := Cat(fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo) + val fwdpipe1_lo = (Fill(8, ld_byte_rhit_lo_lo(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_lo(0)) & io.store_data_hi_r(7,0)) + val fwdpipe2_lo = (Fill(8, ld_byte_rhit_lo_lo(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_lo(1)) & io.store_data_hi_r(15,8)) + val fwdpipe3_lo = (Fill(8, ld_byte_rhit_lo_lo(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_lo(2)) & io.store_data_hi_r(23,16)) + val fwdpipe4_lo = (Fill(8, ld_byte_rhit_lo_lo(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_lo(3)) & io.store_data_hi_r(31,24)) + ld_fwddata_rpipe_lo := Cat(fwdpipe4_lo,fwdpipe3_lo,fwdpipe2_lo,fwdpipe1_lo) - val fwdpipe1_hi = (Fill(8, ld_byte_rhit_lo_hi(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_hi(0)) & io.store_data_hi_r(7,0)) - val fwdpipe2_hi = (Fill(8, ld_byte_rhit_lo_hi(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_hi(1)) & io.store_data_hi_r(15,8)) - val fwdpipe3_hi = (Fill(8, ld_byte_rhit_lo_hi(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_hi(2)) & io.store_data_hi_r(23,16)) - val fwdpipe4_hi = (Fill(8, ld_byte_rhit_lo_hi(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_hi(3)) & io.store_data_hi_r(31,8)) - ld_fwddata_rpipe_hi := Cat(fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi) + val fwdpipe1_hi = (Fill(8, ld_byte_rhit_lo_hi(0)) & io.store_data_lo_r(7,0)) | (Fill(8, ld_byte_rhit_hi_hi(0)) & io.store_data_hi_r(7,0)) + val fwdpipe2_hi = (Fill(8, ld_byte_rhit_lo_hi(1)) & io.store_data_lo_r(15,8)) | (Fill(8, ld_byte_rhit_hi_hi(1)) & io.store_data_hi_r(15,8)) + val fwdpipe3_hi = (Fill(8, ld_byte_rhit_lo_hi(2)) & io.store_data_lo_r(23,16)) | (Fill(8, ld_byte_rhit_hi_hi(2)) & io.store_data_hi_r(23,16)) + val fwdpipe4_hi = (Fill(8, ld_byte_rhit_lo_hi(3)) & io.store_data_lo_r(31,24)) | (Fill(8, ld_byte_rhit_hi_hi(3)) & io.store_data_hi_r(31,24)) + ld_fwddata_rpipe_hi := Cat(fwdpipe4_hi,fwdpipe3_hi,fwdpipe2_hi,fwdpipe1_hi) ld_byte_hit_lo := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_lo(i) | ld_byte_rhit_hi_lo(i)).asUInt).reverse.reduce(Cat(_,_)) ld_byte_hit_hi := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_rhit_lo_hi(i) | ld_byte_rhit_hi_hi(i)).asUInt).reverse.reduce(Cat(_,_)) - io.stbuf_fwdbyteen_hi_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_hi(i) | stbuf_fwdbyteen_hi_pre_m(i)).asUInt).reverse.reduce(Cat(_,_)) - io.stbuf_fwdbyteen_lo_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_lo(i) | stbuf_fwdbyteen_lo_pre_m(i)).asUInt).reverse.reduce(Cat(_,_)) + io.stbuf_fwdbyteen_hi_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_hi(i) | stbuf_fwdbyteen_hi_pre_m(i)).asUInt).reverse.reduce(Cat(_,_)) + io.stbuf_fwdbyteen_lo_m := (0 until DCCM_BYTE_WIDTH).map(i=> (ld_byte_hit_lo(i) | stbuf_fwdbyteen_lo_pre_m(i)).asUInt).reverse.reduce(Cat(_,_)) - // Pipe vs Store Queue priority - val stbuf_fwdpipe1_lo = Mux(ld_byte_rhit_lo(0),ld_fwddata_rpipe_lo(7,0),stbuf_fwddata_lo_pre_m(7,0)) - val stbuf_fwdpipe2_lo = Mux(ld_byte_rhit_lo(1),ld_fwddata_rpipe_lo(15,8),stbuf_fwddata_lo_pre_m(15,8)) - val stbuf_fwdpipe3_lo = Mux(ld_byte_rhit_lo(2),ld_fwddata_rpipe_lo(23,16),stbuf_fwddata_lo_pre_m(23,16)) - val stbuf_fwdpipe4_lo = Mux(ld_byte_rhit_lo(3),ld_fwddata_rpipe_lo(31,24),stbuf_fwddata_lo_pre_m(31,24)) - io.stbuf_fwddata_lo_m := Cat(stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo,stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo) - // Pipe vs Store Queue priority - val stbuf_fwdpipe1_hi = Mux(ld_byte_rhit_hi(0),ld_fwddata_rpipe_hi(7,0),stbuf_fwddata_hi_pre_m(7,0)) - val stbuf_fwdpipe2_hi = Mux(ld_byte_rhit_hi(1),ld_fwddata_rpipe_hi(15,8),stbuf_fwddata_hi_pre_m(15,8)) - val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16)) - val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24)) - io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi) + // Pipe vs Store Queue priority + val stbuf_fwdpipe1_lo = Mux(ld_byte_rhit_lo(0),ld_fwddata_rpipe_lo(7,0),stbuf_fwddata_lo_pre_m(7,0)) + val stbuf_fwdpipe2_lo = Mux(ld_byte_rhit_lo(1),ld_fwddata_rpipe_lo(15,8),stbuf_fwddata_lo_pre_m(15,8)) + val stbuf_fwdpipe3_lo = Mux(ld_byte_rhit_lo(2),ld_fwddata_rpipe_lo(23,16),stbuf_fwddata_lo_pre_m(23,16)) + val stbuf_fwdpipe4_lo = Mux(ld_byte_rhit_lo(3),ld_fwddata_rpipe_lo(31,24),stbuf_fwddata_lo_pre_m(31,24)) + io.stbuf_fwddata_lo_m := Cat(stbuf_fwdpipe4_lo,stbuf_fwdpipe3_lo,stbuf_fwdpipe2_lo,stbuf_fwdpipe1_lo) + // Pipe vs Store Queue priority + val stbuf_fwdpipe1_hi = Mux(ld_byte_rhit_hi(0),ld_fwddata_rpipe_hi(7,0),stbuf_fwddata_hi_pre_m(7,0)) + val stbuf_fwdpipe2_hi = Mux(ld_byte_rhit_hi(1),ld_fwddata_rpipe_hi(15,8),stbuf_fwddata_hi_pre_m(15,8)) + val stbuf_fwdpipe3_hi = Mux(ld_byte_rhit_hi(2),ld_fwddata_rpipe_hi(23,16),stbuf_fwddata_hi_pre_m(23,16)) + val stbuf_fwdpipe4_hi = Mux(ld_byte_rhit_hi(3),ld_fwddata_rpipe_hi(31,24),stbuf_fwddata_hi_pre_m(31,24)) + io.stbuf_fwddata_hi_m := Cat(stbuf_fwdpipe4_hi,stbuf_fwdpipe3_hi,stbuf_fwdpipe2_hi,stbuf_fwdpipe1_hi) } object stbmain extends App{ - println("Generate Verilog") - println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_stbuf())) + println("Generate Verilog") + println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_stbuf())) } diff --git a/src/main/scala/lsu/el2_lsu_trigger.scala b/src/main/scala/lsu/el2_lsu_trigger.scala index e02b36c8..cf93b830 100644 --- a/src/main/scala/lsu/el2_lsu_trigger.scala +++ b/src/main/scala/lsu/el2_lsu_trigger.scala @@ -17,12 +17,11 @@ class el2_lsu_trigger extends Module with RequireAsyncReset with el2_lib { val lsu_match_data = (0 until 4).map(i=>Mux1H(Seq(!io.trigger_pkt_any(i).select.asBool->io.lsu_addr_m, (io.trigger_pkt_any(i).select & io.trigger_pkt_any(i).store).asBool->store_data_trigger_m))) io.lsu_trigger_match_m := (0 until 4).map(i =>io.lsu_pkt_m.valid & !io.lsu_pkt_m.dma & ((io.trigger_pkt_any(i).store & io.lsu_pkt_m.store)| (io.trigger_pkt_any(i).load & io.lsu_pkt_m.load & !io.trigger_pkt_any(i).select) )& - rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_)) + rvmaskandmatch(io.trigger_pkt_any(i).tdata2, lsu_match_data(i), io.trigger_pkt_any(i).match_.asBool())).reverse.reduce(Cat(_,_)) } object main_trigger extends App{ println("Generate Verilog") println((new chisel3.stage.ChiselStage).emitVerilog(new el2_lsu_trigger())) -} - +} \ No newline at end of file diff --git a/src/main/scala/snapshot/el2_param.scala b/src/main/scala/snapshot/el2_param.scala index 84e6bdec..40978129 100644 --- a/src/main/scala/snapshot/el2_param.scala +++ b/src/main/scala/snapshot/el2_param.scala @@ -1,12 +1,12 @@ package snapshot import chisel3._ -object pt{ //chisel +object pt{ val BHT_ADDR_HI = "h9".U(4.W) val BHT_ADDR_LO = "h2".U(2.W) val BHT_ARRAY_DEPTH = "h100".U(11.W) val BHT_GHR_HASH_1 = "h0".U(1.W) - val BHT_GHR_SIZE = "h8".U(4.W) + val BHT_GHR_SIZE = "8h".U(4.W) val BHT_SIZE = "h200".U(12.W) val BTB_ADDR_HI = "h09".U(5.W) val BTB_ADDR_LO = "h2".U(2.W) @@ -156,162 +156,3 @@ object pt{ //chisel val SB_BUS_TAG = "h1".U(4.W) val TIMER_LEGAL_EN = "h1".U(1.W) } - - - - -object pt1{ //scala - val BHT_ADDR_HI = 0x9 //.U(4.W) - val BHT_ADDR_LO = 0x2 //.U(2.W) - val BHT_ARRAY_DEPTH = 0x100 //.U(11.W) - val BHT_GHR_HASH_1 = 0x0 //.U(1.W) - val BHT_GHR_SIZE = 0x8 //.U(4.W) - val BHT_SIZE = 0x200 //.U(12.W) - val BTB_ADDR_HI = 0x09 //.U(5.W) - val BTB_ADDR_LO = 0x2 //.U(2.W) - val BTB_ARRAY_DEPTH = 0x100 //.U(9.W) - val BTB_BTAG_FOLD = 0x0 //.U(1.W) - val BTB_BTAG_SIZE = 0x5 //.U(4.W) - val BTB_FOLD2_INDEX_HASH = 0x0 //.U(1.W) - val BTB_INDEX1_HI = 0x09 //.U(5.W) - val BTB_INDEX1_LO = 0x02 //.U(5.W) - val BTB_INDEX2_HI = 0x11 //.U(5.W) - val BTB_INDEX2_LO = 0x0A //.U(5.W) - val BTB_INDEX3_HI = 0x19 //.U(5.W) - val BTB_INDEX3_LO = 0x12 //.U(5.W) - val BTB_SIZE = 0x200 //.U(10.W) - val BUILD_AHB_LITE = 0x0 //.U(1.W) - val BUILD_AXI4 = 0x1 //.U(1.W) - val BUILD_AXI_NATIVE = 0x1 //.U(1.W) - val BUS_PRTY_DEFAULT = 0x3 //.U(2.W) - val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W) - val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W) - val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W) - val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W) - val DATA_ACCESS_ENABLE0 = 0x1 //.U(1.W) - val DATA_ACCESS_ENABLE1 = 0x1 //.U(1.W) - val DATA_ACCESS_ENABLE2 = 0x1 //.U(1.W) - val DATA_ACCESS_ENABLE3 = 0x1 //.U(1.W) - val DATA_ACCESS_ENABLE4 = 0x0 //.U(1.W) - val DATA_ACCESS_ENABLE5 = 0x0 //.U(1.W) - val DATA_ACCESS_ENABLE6 = 0x0 //.U(1.W) - val DATA_ACCESS_ENABLE7 = 0x0 //.U(1.W) - val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W) - val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) - val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) - val DCCM_BANK_BITS = 0x2 //.U(3.W) - val DCCM_BITS = 0x10 //.U(5.W) - val DCCM_BYTE_WIDTH = 0x4 //.U(3.W) - val DCCM_DATA_WIDTH = 0x20 //.U(6.W) - val DCCM_ECC_WIDTH = 0x7 //.U(3.W) - val DCCM_ENABLE = 0x1 //.U(1.W) - val DCCM_FDATA_WIDTH = 0x27 //.U(6.W) - val DCCM_INDEX_BITS = 0xC //.U(4.W) - val DCCM_NUM_BANKS = 0x04 //.U(5.W) - val DCCM_REGION = 0xF //.U(4.W) - val DCCM_SADR = 0xF0040000 - val DCCM_SIZE = 0x040 - val DCCM_WIDTH_BITS = 0x2 //.U(2.W) - val DMA_BUF_DEPTH = 0x5 //.U(3.W) - val DMA_BUS_ID = 0x1 //.U(1.W) - val DMA_BUS_PRTY = 0x2 //.U(2.W) - val DMA_BUS_TAG = 0x1 //.U(4.W) - val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W) - val ICACHE_2BANKS = 0x1 //.U(1.W) - val ICACHE_BANK_BITS = 0x1 //.U(3.W) - val ICACHE_BANK_HI = 0x3 //.U(3.W) - val ICACHE_BANK_LO = 0x3 //.U(2.W) - val ICACHE_BANK_WIDTH = 0x8 //.U(4.W) - val ICACHE_BANKS_WAY = 0x2 //.U(3.W) - val ICACHE_BEAT_ADDR_HI = 0x5 //.U(4.W) - val ICACHE_BEAT_BITS = 0x3 //.U(4.W) - val ICACHE_DATA_DEPTH = 0x0200 //.U(14.W) - val ICACHE_DATA_INDEX_LO = 0x4 //.U(3.W) - val ICACHE_DATA_WIDTH = 0x40 //.U(7.W) - val ICACHE_ECC = 0x1 //.U(1.W) - val ICACHE_ENABLE = 0x1 //.U(1.W) - val ICACHE_FDATA_WIDTH = 0x47 //.U(7.W) - val ICACHE_INDEX_HI = 0x0C //.U(5.W) - val ICACHE_LN_SZ = 0x40 //.U(7.W) - val ICACHE_NUM_BEATS = 0x8 //.U(4.W) - val ICACHE_NUM_WAYS = 0x2 //.U(3.W) - val ICACHE_ONLY = 0x0 //.U(1.W) - val ICACHE_SCND_LAST = 0x6 //.U(4.W) - val ICACHE_SIZE = 0x010 //.U(9.W) - val ICACHE_STATUS_BITS = 0x1 //.U(3.W) - val ICACHE_TAG_DEPTH = 0x0080 //.U(13.W) - val ICACHE_TAG_INDEX_LO = 0x6 //.U(3.W) - val ICACHE_TAG_LO = 0x0D //.U(5.W) - val ICACHE_WAYPACK = 0x0 //.U(1.W) - val ICCM_BANK_BITS = 0x2 //.U(3.W) - val ICCM_BANK_HI = 0x03 //.U(5.W) - val ICCM_BANK_INDEX_LO = 0x04 //.U(5.W) - val ICCM_BITS = 0x10 //.U(5.W) - val ICCM_ENABLE = 0x1 //.U(1.W) - val ICCM_ICACHE = 0x1 //.U(1.W) - val ICCM_INDEX_BITS = 0xC //.U(4.W) - val ICCM_NUM_BANKS = 0x04 //.U(5.W) - val ICCM_ONLY = 0x0 //.U(1.W) - val ICCM_REGION = 0xE //.U(4.W) - val ICCM_SADR = 0xEE000000 //.U(32.W) - val ICCM_SIZE = 0x040 //.U(10.W) - val IFU_BUS_ID = 0x1 //.U(1.W) - val IFU_BUS_PRTY = 0x2 //.U(2.W) - val IFU_BUS_TAG = 0x3 //.U(4.W) - val INST_ACCESS_ADDR0 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR1 = 0xC0000000 //.U(32.W) - val INST_ACCESS_ADDR2 = 0xA0000000 //.U(32.W) - val INST_ACCESS_ADDR3 = 0x80000000 //.U(32.W) - val INST_ACCESS_ADDR4 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR5 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR6 = 0x00000000 //.U(32.W) - val INST_ACCESS_ADDR7 = 0x00000000 //.U(32.W) - val INST_ACCESS_ENABLE0 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE1 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE2 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE3 = 0x1 //.U(1.W) - val INST_ACCESS_ENABLE4 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE5 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE6 = 0x0 //.U(1.W) - val INST_ACCESS_ENABLE7 = 0x0 //.U(1.W) - val INST_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W) - val INST_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W) - val INST_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W) - val INST_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W) - val INST_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W) - val INST_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W) - val LOAD_TO_USE_PLUS1 = 0x0 //.U(1.W) - val LSU2DMA = 0x0 //.U(1.W) - val LSU_BUS_ID = 0x1 //.U(1.W) - val LSU_BUS_PRTY = 0x2 //.U(2.W) - val LSU_BUS_TAG = 0x3 //.U(4.W) - val LSU_NUM_NBLOAD = 0x04 //.U(5.W) - val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W) - val LSU_SB_BITS = 0x10 //.U(5.W) - val LSU_STBUF_DEPTH = 0x4 //.U(4.W) - val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W) - val PIC_2CYCLE = 0x0 //.U(1.W) - val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W) - val PIC_BITS = 0x0F //.U(5.W) - val PIC_INT_WORDS = 0x1 //.U(4.W) - val PIC_REGION = 0xF //.U(4.W) - val PIC_SIZE = 0x020 //.U(9.W) - val PIC_TOTAL_INT = 0x1F //.U(8.W) - val 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b/target/scala-2.12/classes/vsrc/gated_latch.v new file mode 100644 index 00000000..51b96c9d --- /dev/null +++ b/target/scala-2.12/classes/vsrc/gated_latch.v @@ -0,0 +1,14 @@ +module gated_latch + ( + input logic SE, EN, CK, + output Q + ); + logic en_ff; + logic enable; + assign enable = EN | SE; + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end + assign Q = CK & en_ff; +endmodule

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