diff --git a/ifu_aln_ctl.anno.json b/ifu_aln_ctl.anno.json
new file mode 100644
index 00000000..348840a4
--- /dev/null
+++ b/ifu_aln_ctl.anno.json
@@ -0,0 +1,53 @@
+[
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_ifu_pmu_instr_aligned",
+    "sources":[
+      "~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_bits_br_error",
+    "sources":[
+      "~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_valid"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume1",
+    "sources":[
+      "~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
+      "~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.transforms.CombinationalPath",
+    "sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume2",
+    "sources":[
+      "~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
+      "~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
+    ]
+  },
+  {
+    "class":"firrtl.EmitCircuitAnnotation",
+    "emitter":"firrtl.VerilogEmitter"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxResourceAnno",
+    "target":"ifu_aln_ctl.gated_latch",
+    "resourceId":"/vsrc/gated_latch.sv"
+  },
+  {
+    "class":"firrtl.options.TargetDirAnnotation",
+    "directory":"."
+  },
+  {
+    "class":"firrtl.options.OutputAnnotationFileAnnotation",
+    "file":"ifu_aln_ctl"
+  },
+  {
+    "class":"firrtl.transforms.BlackBoxTargetDirAnno",
+    "targetDir":"."
+  }
+]
\ No newline at end of file
diff --git a/ifu_aln_ctl.fir b/ifu_aln_ctl.fir
new file mode 100644
index 00000000..0ce0a013
--- /dev/null
+++ b/ifu_aln_ctl.fir
@@ -0,0 +1,3502 @@
+;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
+circuit ifu_aln_ctl : 
+  extmodule gated_latch : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_1 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_1 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_1 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_2 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_2 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_2 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_3 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_3 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_3 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_4 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_4 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_4 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_5 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_5 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_5 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_6 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_6 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_6 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_7 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_7 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_7 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_8 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_8 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_8 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_9 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_9 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_9 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_10 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_10 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_10 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  extmodule gated_latch_11 : 
+    output Q : Clock
+    input CK : Clock
+    input EN : UInt<1>
+    input SE : UInt<1>
+    
+    defname = gated_latch
+    
+    
+  module rvclkhdr_11 : 
+    input clock : Clock
+    input reset : Reset
+    output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
+    
+    inst clkhdr of gated_latch_11 @[lib.scala 334:26]
+    clkhdr.SE is invalid
+    clkhdr.EN is invalid
+    clkhdr.CK is invalid
+    clkhdr.Q is invalid
+    io.l1clk <= clkhdr.Q @[lib.scala 335:14]
+    clkhdr.CK <= io.clk @[lib.scala 336:18]
+    clkhdr.EN <= io.en @[lib.scala 337:18]
+    clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
+    
+  module ifu_compress_ctl : 
+    input clock : Clock
+    input reset : Reset
+    output io : {flip din : UInt<16>, dout : UInt<32>}
+    
+    wire out : UInt<1>[32] @[ifu_compress_ctl.scala 14:17]
+    out[0] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[1] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[2] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[3] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[4] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[5] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[6] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[7] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[8] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[9] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[10] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[11] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[12] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[13] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[14] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[15] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[16] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[17] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[18] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[19] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[20] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[21] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[22] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[23] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[24] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[25] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[26] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[27] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[28] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[29] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[30] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    out[31] <= UInt<1>("h00") @[ifu_compress_ctl.scala 15:7]
+    node _T = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_2 = eq(_T_1, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_3 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_4 = eq(_T_3, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_5 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_6 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_7 = eq(_T_6, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_8 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_9 = eq(_T_8, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_10 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_11 = and(_T, _T_2) @[ifu_compress_ctl.scala 12:110]
+    node _T_12 = and(_T_11, _T_4) @[ifu_compress_ctl.scala 12:110]
+    node _T_13 = and(_T_12, _T_5) @[ifu_compress_ctl.scala 12:110]
+    node _T_14 = and(_T_13, _T_7) @[ifu_compress_ctl.scala 12:110]
+    node _T_15 = and(_T_14, _T_9) @[ifu_compress_ctl.scala 12:110]
+    node _T_16 = and(_T_15, _T_10) @[ifu_compress_ctl.scala 12:110]
+    node _T_17 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_18 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_19 = eq(_T_18, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_20 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_21 = eq(_T_20, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_22 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_23 = eq(_T_22, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_24 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_25 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_26 = and(_T_17, _T_19) @[ifu_compress_ctl.scala 12:110]
+    node _T_27 = and(_T_26, _T_21) @[ifu_compress_ctl.scala 12:110]
+    node _T_28 = and(_T_27, _T_23) @[ifu_compress_ctl.scala 12:110]
+    node _T_29 = and(_T_28, _T_24) @[ifu_compress_ctl.scala 12:110]
+    node _T_30 = and(_T_29, _T_25) @[ifu_compress_ctl.scala 12:110]
+    node _T_31 = or(_T_16, _T_30) @[ifu_compress_ctl.scala 17:53]
+    out[30] <= _T_31 @[ifu_compress_ctl.scala 17:11]
+    node _T_32 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_33 = eq(_T_32, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_34 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_35 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_36 = eq(_T_35, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_37 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_38 = eq(_T_37, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_39 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:90]
+    node _T_40 = eq(_T_39, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_41 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_42 = eq(_T_41, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_43 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:90]
+    node _T_44 = eq(_T_43, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_45 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_46 = eq(_T_45, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_47 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_48 = eq(_T_47, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_49 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_50 = eq(_T_49, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_51 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_52 = eq(_T_51, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_53 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_54 = eq(_T_53, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_55 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_56 = and(_T_33, _T_34) @[ifu_compress_ctl.scala 12:110]
+    node _T_57 = and(_T_56, _T_36) @[ifu_compress_ctl.scala 12:110]
+    node _T_58 = and(_T_57, _T_38) @[ifu_compress_ctl.scala 12:110]
+    node _T_59 = and(_T_58, _T_40) @[ifu_compress_ctl.scala 12:110]
+    node _T_60 = and(_T_59, _T_42) @[ifu_compress_ctl.scala 12:110]
+    node _T_61 = and(_T_60, _T_44) @[ifu_compress_ctl.scala 12:110]
+    node _T_62 = and(_T_61, _T_46) @[ifu_compress_ctl.scala 12:110]
+    node _T_63 = and(_T_62, _T_48) @[ifu_compress_ctl.scala 12:110]
+    node _T_64 = and(_T_63, _T_50) @[ifu_compress_ctl.scala 12:110]
+    node _T_65 = and(_T_64, _T_52) @[ifu_compress_ctl.scala 12:110]
+    node _T_66 = and(_T_65, _T_54) @[ifu_compress_ctl.scala 12:110]
+    node _T_67 = and(_T_66, _T_55) @[ifu_compress_ctl.scala 12:110]
+    out[20] <= _T_67 @[ifu_compress_ctl.scala 19:11]
+    node _T_68 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_69 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_70 = eq(_T_69, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_71 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_72 = eq(_T_71, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_73 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_74 = eq(_T_73, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_75 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_76 = and(_T_68, _T_70) @[ifu_compress_ctl.scala 12:110]
+    node _T_77 = and(_T_76, _T_72) @[ifu_compress_ctl.scala 12:110]
+    node _T_78 = and(_T_77, _T_74) @[ifu_compress_ctl.scala 12:110]
+    node _T_79 = and(_T_78, _T_75) @[ifu_compress_ctl.scala 12:110]
+    node _T_80 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_81 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_82 = eq(_T_81, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_83 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_84 = eq(_T_83, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_85 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_86 = eq(_T_85, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_87 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_88 = and(_T_80, _T_82) @[ifu_compress_ctl.scala 12:110]
+    node _T_89 = and(_T_88, _T_84) @[ifu_compress_ctl.scala 12:110]
+    node _T_90 = and(_T_89, _T_86) @[ifu_compress_ctl.scala 12:110]
+    node _T_91 = and(_T_90, _T_87) @[ifu_compress_ctl.scala 12:110]
+    node _T_92 = or(_T_79, _T_91) @[ifu_compress_ctl.scala 21:46]
+    node _T_93 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_94 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_95 = eq(_T_94, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_96 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_97 = eq(_T_96, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_98 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_99 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_100 = and(_T_93, _T_95) @[ifu_compress_ctl.scala 12:110]
+    node _T_101 = and(_T_100, _T_97) @[ifu_compress_ctl.scala 12:110]
+    node _T_102 = and(_T_101, _T_98) @[ifu_compress_ctl.scala 12:110]
+    node _T_103 = and(_T_102, _T_99) @[ifu_compress_ctl.scala 12:110]
+    node _T_104 = or(_T_92, _T_103) @[ifu_compress_ctl.scala 21:80]
+    node _T_105 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_106 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_107 = eq(_T_106, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_108 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_109 = eq(_T_108, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_110 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_111 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_112 = and(_T_105, _T_107) @[ifu_compress_ctl.scala 12:110]
+    node _T_113 = and(_T_112, _T_109) @[ifu_compress_ctl.scala 12:110]
+    node _T_114 = and(_T_113, _T_110) @[ifu_compress_ctl.scala 12:110]
+    node _T_115 = and(_T_114, _T_111) @[ifu_compress_ctl.scala 12:110]
+    node _T_116 = or(_T_104, _T_115) @[ifu_compress_ctl.scala 21:113]
+    out[14] <= _T_116 @[ifu_compress_ctl.scala 21:11]
+    node _T_117 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_118 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_119 = eq(_T_118, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_120 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_121 = eq(_T_120, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_122 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_123 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_124 = eq(_T_123, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_125 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_126 = and(_T_117, _T_119) @[ifu_compress_ctl.scala 12:110]
+    node _T_127 = and(_T_126, _T_121) @[ifu_compress_ctl.scala 12:110]
+    node _T_128 = and(_T_127, _T_122) @[ifu_compress_ctl.scala 12:110]
+    node _T_129 = and(_T_128, _T_124) @[ifu_compress_ctl.scala 12:110]
+    node _T_130 = and(_T_129, _T_125) @[ifu_compress_ctl.scala 12:110]
+    node _T_131 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_132 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_133 = eq(_T_132, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_134 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_135 = eq(_T_134, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_136 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_137 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_138 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_139 = and(_T_131, _T_133) @[ifu_compress_ctl.scala 12:110]
+    node _T_140 = and(_T_139, _T_135) @[ifu_compress_ctl.scala 12:110]
+    node _T_141 = and(_T_140, _T_136) @[ifu_compress_ctl.scala 12:110]
+    node _T_142 = and(_T_141, _T_137) @[ifu_compress_ctl.scala 12:110]
+    node _T_143 = and(_T_142, _T_138) @[ifu_compress_ctl.scala 12:110]
+    node _T_144 = or(_T_130, _T_143) @[ifu_compress_ctl.scala 23:50]
+    node _T_145 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 23:95]
+    node _T_146 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 23:108]
+    node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_compress_ctl.scala 23:101]
+    node _T_148 = and(_T_145, _T_147) @[ifu_compress_ctl.scala 23:99]
+    node _T_149 = or(_T_144, _T_148) @[ifu_compress_ctl.scala 23:86]
+    out[13] <= _T_149 @[ifu_compress_ctl.scala 23:11]
+    node _T_150 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_151 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_152 = eq(_T_151, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_153 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_154 = eq(_T_153, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_155 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_156 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_157 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_158 = and(_T_150, _T_152) @[ifu_compress_ctl.scala 12:110]
+    node _T_159 = and(_T_158, _T_154) @[ifu_compress_ctl.scala 12:110]
+    node _T_160 = and(_T_159, _T_155) @[ifu_compress_ctl.scala 12:110]
+    node _T_161 = and(_T_160, _T_156) @[ifu_compress_ctl.scala 12:110]
+    node _T_162 = and(_T_161, _T_157) @[ifu_compress_ctl.scala 12:110]
+    node _T_163 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_164 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_165 = eq(_T_164, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_166 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_167 = eq(_T_166, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_168 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_169 = eq(_T_168, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_170 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_171 = and(_T_163, _T_165) @[ifu_compress_ctl.scala 12:110]
+    node _T_172 = and(_T_171, _T_167) @[ifu_compress_ctl.scala 12:110]
+    node _T_173 = and(_T_172, _T_169) @[ifu_compress_ctl.scala 12:110]
+    node _T_174 = and(_T_173, _T_170) @[ifu_compress_ctl.scala 12:110]
+    node _T_175 = or(_T_162, _T_174) @[ifu_compress_ctl.scala 25:47]
+    node _T_176 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_177 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_178 = eq(_T_177, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_179 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_180 = eq(_T_179, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_181 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_182 = eq(_T_181, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_183 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_184 = and(_T_176, _T_178) @[ifu_compress_ctl.scala 12:110]
+    node _T_185 = and(_T_184, _T_180) @[ifu_compress_ctl.scala 12:110]
+    node _T_186 = and(_T_185, _T_182) @[ifu_compress_ctl.scala 12:110]
+    node _T_187 = and(_T_186, _T_183) @[ifu_compress_ctl.scala 12:110]
+    node _T_188 = or(_T_175, _T_187) @[ifu_compress_ctl.scala 25:81]
+    node _T_189 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_190 = eq(_T_189, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_191 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_192 = eq(_T_191, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_193 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_194 = and(_T_190, _T_192) @[ifu_compress_ctl.scala 12:110]
+    node _T_195 = and(_T_194, _T_193) @[ifu_compress_ctl.scala 12:110]
+    node _T_196 = or(_T_188, _T_195) @[ifu_compress_ctl.scala 25:115]
+    node _T_197 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_198 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_199 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_200 = and(_T_197, _T_198) @[ifu_compress_ctl.scala 12:110]
+    node _T_201 = and(_T_200, _T_199) @[ifu_compress_ctl.scala 12:110]
+    node _T_202 = or(_T_196, _T_201) @[ifu_compress_ctl.scala 26:26]
+    out[12] <= _T_202 @[ifu_compress_ctl.scala 25:11]
+    node _T_203 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_204 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_205 = eq(_T_204, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_206 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_207 = eq(_T_206, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_208 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_209 = eq(_T_208, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_210 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_211 = eq(_T_210, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_212 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_213 = eq(_T_212, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_214 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_215 = eq(_T_214, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_216 = and(_T_203, _T_205) @[ifu_compress_ctl.scala 12:110]
+    node _T_217 = and(_T_216, _T_207) @[ifu_compress_ctl.scala 12:110]
+    node _T_218 = and(_T_217, _T_209) @[ifu_compress_ctl.scala 12:110]
+    node _T_219 = and(_T_218, _T_211) @[ifu_compress_ctl.scala 12:110]
+    node _T_220 = and(_T_219, _T_213) @[ifu_compress_ctl.scala 12:110]
+    node _T_221 = and(_T_220, _T_215) @[ifu_compress_ctl.scala 12:110]
+    node _T_222 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 28:62]
+    node _T_223 = eq(_T_222, UInt<1>("h00")) @[ifu_compress_ctl.scala 28:55]
+    node _T_224 = and(_T_221, _T_223) @[ifu_compress_ctl.scala 28:53]
+    node _T_225 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_226 = eq(_T_225, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_227 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_228 = and(_T_226, _T_227) @[ifu_compress_ctl.scala 12:110]
+    node _T_229 = or(_T_224, _T_228) @[ifu_compress_ctl.scala 28:67]
+    node _T_230 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_231 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_232 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_233 = and(_T_230, _T_231) @[ifu_compress_ctl.scala 12:110]
+    node _T_234 = and(_T_233, _T_232) @[ifu_compress_ctl.scala 12:110]
+    node _T_235 = or(_T_229, _T_234) @[ifu_compress_ctl.scala 28:88]
+    out[6] <= _T_235 @[ifu_compress_ctl.scala 28:10]
+    node _T_236 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 30:20]
+    node _T_237 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 30:33]
+    node _T_238 = eq(_T_237, UInt<1>("h00")) @[ifu_compress_ctl.scala 30:26]
+    node _T_239 = and(_T_236, _T_238) @[ifu_compress_ctl.scala 30:24]
+    node _T_240 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_241 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_242 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_243 = and(_T_240, _T_241) @[ifu_compress_ctl.scala 12:110]
+    node _T_244 = and(_T_243, _T_242) @[ifu_compress_ctl.scala 12:110]
+    node _T_245 = or(_T_239, _T_244) @[ifu_compress_ctl.scala 30:39]
+    node _T_246 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_247 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_248 = eq(_T_247, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_249 = and(_T_246, _T_248) @[ifu_compress_ctl.scala 12:110]
+    node _T_250 = or(_T_245, _T_249) @[ifu_compress_ctl.scala 30:63]
+    node _T_251 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_252 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_253 = and(_T_251, _T_252) @[ifu_compress_ctl.scala 12:110]
+    node _T_254 = or(_T_250, _T_253) @[ifu_compress_ctl.scala 30:83]
+    node _T_255 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_256 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_257 = and(_T_255, _T_256) @[ifu_compress_ctl.scala 12:110]
+    node _T_258 = or(_T_254, _T_257) @[ifu_compress_ctl.scala 30:102]
+    node _T_259 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_260 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_261 = and(_T_259, _T_260) @[ifu_compress_ctl.scala 12:110]
+    node _T_262 = or(_T_258, _T_261) @[ifu_compress_ctl.scala 31:22]
+    node _T_263 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_264 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_265 = and(_T_263, _T_264) @[ifu_compress_ctl.scala 12:110]
+    node _T_266 = or(_T_262, _T_265) @[ifu_compress_ctl.scala 31:42]
+    node _T_267 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_268 = eq(_T_267, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_269 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_270 = and(_T_268, _T_269) @[ifu_compress_ctl.scala 12:110]
+    node _T_271 = or(_T_266, _T_270) @[ifu_compress_ctl.scala 31:62]
+    node _T_272 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_273 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_274 = and(_T_272, _T_273) @[ifu_compress_ctl.scala 12:110]
+    node _T_275 = or(_T_271, _T_274) @[ifu_compress_ctl.scala 31:83]
+    out[5] <= _T_275 @[ifu_compress_ctl.scala 30:10]
+    node _T_276 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_277 = eq(_T_276, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_278 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_279 = eq(_T_278, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_280 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_281 = eq(_T_280, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_282 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:90]
+    node _T_283 = eq(_T_282, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_284 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_285 = eq(_T_284, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_286 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:90]
+    node _T_287 = eq(_T_286, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_288 = and(_T_277, _T_279) @[ifu_compress_ctl.scala 12:110]
+    node _T_289 = and(_T_288, _T_281) @[ifu_compress_ctl.scala 12:110]
+    node _T_290 = and(_T_289, _T_283) @[ifu_compress_ctl.scala 12:110]
+    node _T_291 = and(_T_290, _T_285) @[ifu_compress_ctl.scala 12:110]
+    node _T_292 = and(_T_291, _T_287) @[ifu_compress_ctl.scala 12:110]
+    node _T_293 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 33:59]
+    node _T_294 = eq(_T_293, UInt<1>("h00")) @[ifu_compress_ctl.scala 33:52]
+    node _T_295 = and(_T_292, _T_294) @[ifu_compress_ctl.scala 33:50]
+    node _T_296 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_297 = eq(_T_296, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_298 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_299 = eq(_T_298, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_300 = and(_T_297, _T_299) @[ifu_compress_ctl.scala 12:110]
+    node _T_301 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 33:96]
+    node _T_302 = eq(_T_301, UInt<1>("h00")) @[ifu_compress_ctl.scala 33:89]
+    node _T_303 = and(_T_300, _T_302) @[ifu_compress_ctl.scala 33:87]
+    node _T_304 = or(_T_295, _T_303) @[ifu_compress_ctl.scala 33:65]
+    node _T_305 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_306 = eq(_T_305, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_307 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_308 = and(_T_306, _T_307) @[ifu_compress_ctl.scala 12:110]
+    node _T_309 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 34:32]
+    node _T_310 = eq(_T_309, UInt<1>("h00")) @[ifu_compress_ctl.scala 34:25]
+    node _T_311 = and(_T_308, _T_310) @[ifu_compress_ctl.scala 34:23]
+    node _T_312 = or(_T_304, _T_311) @[ifu_compress_ctl.scala 33:102]
+    node _T_313 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_314 = eq(_T_313, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_315 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_316 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_317 = and(_T_314, _T_315) @[ifu_compress_ctl.scala 12:110]
+    node _T_318 = and(_T_317, _T_316) @[ifu_compress_ctl.scala 12:110]
+    node _T_319 = or(_T_312, _T_318) @[ifu_compress_ctl.scala 34:38]
+    node _T_320 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_321 = eq(_T_320, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_322 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_323 = and(_T_321, _T_322) @[ifu_compress_ctl.scala 12:110]
+    node _T_324 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 34:91]
+    node _T_325 = eq(_T_324, UInt<1>("h00")) @[ifu_compress_ctl.scala 34:84]
+    node _T_326 = and(_T_323, _T_325) @[ifu_compress_ctl.scala 34:82]
+    node _T_327 = or(_T_319, _T_326) @[ifu_compress_ctl.scala 34:62]
+    node _T_328 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_329 = eq(_T_328, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_330 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_331 = and(_T_329, _T_330) @[ifu_compress_ctl.scala 12:110]
+    node _T_332 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 35:32]
+    node _T_333 = eq(_T_332, UInt<1>("h00")) @[ifu_compress_ctl.scala 35:25]
+    node _T_334 = and(_T_331, _T_333) @[ifu_compress_ctl.scala 35:23]
+    node _T_335 = or(_T_327, _T_334) @[ifu_compress_ctl.scala 34:97]
+    node _T_336 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_337 = eq(_T_336, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_338 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_339 = and(_T_337, _T_338) @[ifu_compress_ctl.scala 12:110]
+    node _T_340 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 35:67]
+    node _T_341 = eq(_T_340, UInt<1>("h00")) @[ifu_compress_ctl.scala 35:60]
+    node _T_342 = and(_T_339, _T_341) @[ifu_compress_ctl.scala 35:58]
+    node _T_343 = or(_T_335, _T_342) @[ifu_compress_ctl.scala 35:38]
+    node _T_344 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_345 = eq(_T_344, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_346 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_347 = and(_T_345, _T_346) @[ifu_compress_ctl.scala 12:110]
+    node _T_348 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 35:102]
+    node _T_349 = eq(_T_348, UInt<1>("h00")) @[ifu_compress_ctl.scala 35:95]
+    node _T_350 = and(_T_347, _T_349) @[ifu_compress_ctl.scala 35:93]
+    node _T_351 = or(_T_343, _T_350) @[ifu_compress_ctl.scala 35:73]
+    node _T_352 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_353 = eq(_T_352, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_354 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_355 = eq(_T_354, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_356 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_357 = and(_T_353, _T_355) @[ifu_compress_ctl.scala 12:110]
+    node _T_358 = and(_T_357, _T_356) @[ifu_compress_ctl.scala 12:110]
+    node _T_359 = or(_T_351, _T_358) @[ifu_compress_ctl.scala 35:108]
+    out[4] <= _T_359 @[ifu_compress_ctl.scala 33:10]
+    node _T_360 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_361 = eq(_T_360, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_362 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_363 = and(_T_361, _T_362) @[ifu_compress_ctl.scala 12:110]
+    out[3] <= _T_363 @[ifu_compress_ctl.scala 38:10]
+    node _T_364 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_365 = eq(_T_364, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_366 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_367 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_368 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_369 = eq(_T_368, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_370 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_371 = eq(_T_370, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_372 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_373 = eq(_T_372, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_374 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_375 = eq(_T_374, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_376 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_377 = eq(_T_376, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_378 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_379 = and(_T_365, _T_366) @[ifu_compress_ctl.scala 12:110]
+    node _T_380 = and(_T_379, _T_367) @[ifu_compress_ctl.scala 12:110]
+    node _T_381 = and(_T_380, _T_369) @[ifu_compress_ctl.scala 12:110]
+    node _T_382 = and(_T_381, _T_371) @[ifu_compress_ctl.scala 12:110]
+    node _T_383 = and(_T_382, _T_373) @[ifu_compress_ctl.scala 12:110]
+    node _T_384 = and(_T_383, _T_375) @[ifu_compress_ctl.scala 12:110]
+    node _T_385 = and(_T_384, _T_377) @[ifu_compress_ctl.scala 12:110]
+    node _T_386 = and(_T_385, _T_378) @[ifu_compress_ctl.scala 12:110]
+    node _T_387 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_388 = eq(_T_387, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_389 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_390 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_391 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_392 = eq(_T_391, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_393 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_394 = eq(_T_393, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_395 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_396 = eq(_T_395, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_397 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_398 = eq(_T_397, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_399 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_400 = eq(_T_399, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_401 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_402 = and(_T_388, _T_389) @[ifu_compress_ctl.scala 12:110]
+    node _T_403 = and(_T_402, _T_390) @[ifu_compress_ctl.scala 12:110]
+    node _T_404 = and(_T_403, _T_392) @[ifu_compress_ctl.scala 12:110]
+    node _T_405 = and(_T_404, _T_394) @[ifu_compress_ctl.scala 12:110]
+    node _T_406 = and(_T_405, _T_396) @[ifu_compress_ctl.scala 12:110]
+    node _T_407 = and(_T_406, _T_398) @[ifu_compress_ctl.scala 12:110]
+    node _T_408 = and(_T_407, _T_400) @[ifu_compress_ctl.scala 12:110]
+    node _T_409 = and(_T_408, _T_401) @[ifu_compress_ctl.scala 12:110]
+    node _T_410 = or(_T_386, _T_409) @[ifu_compress_ctl.scala 40:59]
+    node _T_411 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_412 = eq(_T_411, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_413 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_414 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_415 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_416 = eq(_T_415, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_417 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_418 = eq(_T_417, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_419 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_420 = eq(_T_419, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_421 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_422 = eq(_T_421, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_423 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_424 = eq(_T_423, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_425 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_426 = and(_T_412, _T_413) @[ifu_compress_ctl.scala 12:110]
+    node _T_427 = and(_T_426, _T_414) @[ifu_compress_ctl.scala 12:110]
+    node _T_428 = and(_T_427, _T_416) @[ifu_compress_ctl.scala 12:110]
+    node _T_429 = and(_T_428, _T_418) @[ifu_compress_ctl.scala 12:110]
+    node _T_430 = and(_T_429, _T_420) @[ifu_compress_ctl.scala 12:110]
+    node _T_431 = and(_T_430, _T_422) @[ifu_compress_ctl.scala 12:110]
+    node _T_432 = and(_T_431, _T_424) @[ifu_compress_ctl.scala 12:110]
+    node _T_433 = and(_T_432, _T_425) @[ifu_compress_ctl.scala 12:110]
+    node _T_434 = or(_T_410, _T_433) @[ifu_compress_ctl.scala 40:107]
+    node _T_435 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_436 = eq(_T_435, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_437 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_438 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_439 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_440 = eq(_T_439, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_441 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_442 = eq(_T_441, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_443 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_444 = eq(_T_443, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_445 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_446 = eq(_T_445, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_447 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_448 = eq(_T_447, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_449 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_450 = and(_T_436, _T_437) @[ifu_compress_ctl.scala 12:110]
+    node _T_451 = and(_T_450, _T_438) @[ifu_compress_ctl.scala 12:110]
+    node _T_452 = and(_T_451, _T_440) @[ifu_compress_ctl.scala 12:110]
+    node _T_453 = and(_T_452, _T_442) @[ifu_compress_ctl.scala 12:110]
+    node _T_454 = and(_T_453, _T_444) @[ifu_compress_ctl.scala 12:110]
+    node _T_455 = and(_T_454, _T_446) @[ifu_compress_ctl.scala 12:110]
+    node _T_456 = and(_T_455, _T_448) @[ifu_compress_ctl.scala 12:110]
+    node _T_457 = and(_T_456, _T_449) @[ifu_compress_ctl.scala 12:110]
+    node _T_458 = or(_T_434, _T_457) @[ifu_compress_ctl.scala 41:50]
+    node _T_459 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_460 = eq(_T_459, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_461 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_462 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_463 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_464 = eq(_T_463, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_465 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_466 = eq(_T_465, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_467 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_468 = eq(_T_467, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_469 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_470 = eq(_T_469, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_471 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_472 = eq(_T_471, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_473 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_474 = and(_T_460, _T_461) @[ifu_compress_ctl.scala 12:110]
+    node _T_475 = and(_T_474, _T_462) @[ifu_compress_ctl.scala 12:110]
+    node _T_476 = and(_T_475, _T_464) @[ifu_compress_ctl.scala 12:110]
+    node _T_477 = and(_T_476, _T_466) @[ifu_compress_ctl.scala 12:110]
+    node _T_478 = and(_T_477, _T_468) @[ifu_compress_ctl.scala 12:110]
+    node _T_479 = and(_T_478, _T_470) @[ifu_compress_ctl.scala 12:110]
+    node _T_480 = and(_T_479, _T_472) @[ifu_compress_ctl.scala 12:110]
+    node _T_481 = and(_T_480, _T_473) @[ifu_compress_ctl.scala 12:110]
+    node _T_482 = or(_T_458, _T_481) @[ifu_compress_ctl.scala 41:94]
+    node _T_483 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_484 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_485 = eq(_T_484, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_486 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_487 = eq(_T_486, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_488 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_489 = eq(_T_488, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_490 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_491 = eq(_T_490, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_492 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_493 = eq(_T_492, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_494 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_495 = eq(_T_494, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_496 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_497 = eq(_T_496, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_498 = and(_T_483, _T_485) @[ifu_compress_ctl.scala 12:110]
+    node _T_499 = and(_T_498, _T_487) @[ifu_compress_ctl.scala 12:110]
+    node _T_500 = and(_T_499, _T_489) @[ifu_compress_ctl.scala 12:110]
+    node _T_501 = and(_T_500, _T_491) @[ifu_compress_ctl.scala 12:110]
+    node _T_502 = and(_T_501, _T_493) @[ifu_compress_ctl.scala 12:110]
+    node _T_503 = and(_T_502, _T_495) @[ifu_compress_ctl.scala 12:110]
+    node _T_504 = and(_T_503, _T_497) @[ifu_compress_ctl.scala 12:110]
+    node _T_505 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 42:103]
+    node _T_506 = eq(_T_505, UInt<1>("h00")) @[ifu_compress_ctl.scala 42:96]
+    node _T_507 = and(_T_504, _T_506) @[ifu_compress_ctl.scala 42:94]
+    node _T_508 = or(_T_482, _T_507) @[ifu_compress_ctl.scala 42:49]
+    node _T_509 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_510 = eq(_T_509, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_511 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_512 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_513 = eq(_T_512, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_514 = and(_T_510, _T_511) @[ifu_compress_ctl.scala 12:110]
+    node _T_515 = and(_T_514, _T_513) @[ifu_compress_ctl.scala 12:110]
+    node _T_516 = or(_T_508, _T_515) @[ifu_compress_ctl.scala 42:109]
+    node _T_517 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_518 = eq(_T_517, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_519 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_520 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_521 = and(_T_518, _T_519) @[ifu_compress_ctl.scala 12:110]
+    node _T_522 = and(_T_521, _T_520) @[ifu_compress_ctl.scala 12:110]
+    node _T_523 = or(_T_516, _T_522) @[ifu_compress_ctl.scala 43:26]
+    node _T_524 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_525 = eq(_T_524, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_526 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_527 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_528 = and(_T_525, _T_526) @[ifu_compress_ctl.scala 12:110]
+    node _T_529 = and(_T_528, _T_527) @[ifu_compress_ctl.scala 12:110]
+    node _T_530 = or(_T_523, _T_529) @[ifu_compress_ctl.scala 43:48]
+    node _T_531 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_532 = eq(_T_531, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_533 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_534 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_535 = and(_T_532, _T_533) @[ifu_compress_ctl.scala 12:110]
+    node _T_536 = and(_T_535, _T_534) @[ifu_compress_ctl.scala 12:110]
+    node _T_537 = or(_T_530, _T_536) @[ifu_compress_ctl.scala 43:70]
+    node _T_538 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_539 = eq(_T_538, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_540 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_541 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_542 = and(_T_539, _T_540) @[ifu_compress_ctl.scala 12:110]
+    node _T_543 = and(_T_542, _T_541) @[ifu_compress_ctl.scala 12:110]
+    node _T_544 = or(_T_537, _T_543) @[ifu_compress_ctl.scala 43:93]
+    node _T_545 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_546 = eq(_T_545, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_547 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_548 = and(_T_546, _T_547) @[ifu_compress_ctl.scala 12:110]
+    node _T_549 = or(_T_544, _T_548) @[ifu_compress_ctl.scala 44:26]
+    out[2] <= _T_549 @[ifu_compress_ctl.scala 40:10]
+    out[1] <= UInt<1>("h01") @[ifu_compress_ctl.scala 46:10]
+    out[0] <= UInt<1>("h01") @[ifu_compress_ctl.scala 48:10]
+    node rs2d = bits(io.din, 6, 2) @[ifu_compress_ctl.scala 50:20]
+    node rdd = bits(io.din, 11, 7) @[ifu_compress_ctl.scala 51:19]
+    node _T_550 = bits(io.din, 9, 7) @[ifu_compress_ctl.scala 52:34]
+    node rdpd = cat(UInt<2>("h01"), _T_550) @[Cat.scala 29:58]
+    node _T_551 = bits(io.din, 4, 2) @[ifu_compress_ctl.scala 53:35]
+    node rs2pd = cat(UInt<2>("h01"), _T_551) @[Cat.scala 29:58]
+    node _T_552 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_553 = eq(_T_552, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_554 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_555 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_556 = and(_T_553, _T_554) @[ifu_compress_ctl.scala 12:110]
+    node _T_557 = and(_T_556, _T_555) @[ifu_compress_ctl.scala 12:110]
+    node _T_558 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_559 = eq(_T_558, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_560 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_561 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_562 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_563 = and(_T_559, _T_560) @[ifu_compress_ctl.scala 12:110]
+    node _T_564 = and(_T_563, _T_561) @[ifu_compress_ctl.scala 12:110]
+    node _T_565 = and(_T_564, _T_562) @[ifu_compress_ctl.scala 12:110]
+    node _T_566 = or(_T_557, _T_565) @[ifu_compress_ctl.scala 55:33]
+    node _T_567 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_568 = eq(_T_567, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_569 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_570 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_571 = and(_T_568, _T_569) @[ifu_compress_ctl.scala 12:110]
+    node _T_572 = and(_T_571, _T_570) @[ifu_compress_ctl.scala 12:110]
+    node _T_573 = or(_T_566, _T_572) @[ifu_compress_ctl.scala 55:58]
+    node _T_574 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_575 = eq(_T_574, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_576 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_577 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_578 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_579 = and(_T_575, _T_576) @[ifu_compress_ctl.scala 12:110]
+    node _T_580 = and(_T_579, _T_577) @[ifu_compress_ctl.scala 12:110]
+    node _T_581 = and(_T_580, _T_578) @[ifu_compress_ctl.scala 12:110]
+    node _T_582 = or(_T_573, _T_581) @[ifu_compress_ctl.scala 55:79]
+    node _T_583 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_584 = eq(_T_583, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_585 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_586 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_587 = and(_T_584, _T_585) @[ifu_compress_ctl.scala 12:110]
+    node _T_588 = and(_T_587, _T_586) @[ifu_compress_ctl.scala 12:110]
+    node _T_589 = or(_T_582, _T_588) @[ifu_compress_ctl.scala 55:104]
+    node _T_590 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_591 = eq(_T_590, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_592 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_593 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_594 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_595 = and(_T_591, _T_592) @[ifu_compress_ctl.scala 12:110]
+    node _T_596 = and(_T_595, _T_593) @[ifu_compress_ctl.scala 12:110]
+    node _T_597 = and(_T_596, _T_594) @[ifu_compress_ctl.scala 12:110]
+    node _T_598 = or(_T_589, _T_597) @[ifu_compress_ctl.scala 56:24]
+    node _T_599 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_600 = eq(_T_599, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_601 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_602 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_603 = and(_T_600, _T_601) @[ifu_compress_ctl.scala 12:110]
+    node _T_604 = and(_T_603, _T_602) @[ifu_compress_ctl.scala 12:110]
+    node _T_605 = or(_T_598, _T_604) @[ifu_compress_ctl.scala 56:48]
+    node _T_606 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_607 = eq(_T_606, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_608 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_609 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_610 = eq(_T_609, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_611 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_612 = and(_T_607, _T_608) @[ifu_compress_ctl.scala 12:110]
+    node _T_613 = and(_T_612, _T_610) @[ifu_compress_ctl.scala 12:110]
+    node _T_614 = and(_T_613, _T_611) @[ifu_compress_ctl.scala 12:110]
+    node _T_615 = or(_T_605, _T_614) @[ifu_compress_ctl.scala 56:69]
+    node _T_616 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_617 = eq(_T_616, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_618 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_619 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_620 = and(_T_617, _T_618) @[ifu_compress_ctl.scala 12:110]
+    node _T_621 = and(_T_620, _T_619) @[ifu_compress_ctl.scala 12:110]
+    node _T_622 = or(_T_615, _T_621) @[ifu_compress_ctl.scala 56:94]
+    node _T_623 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_624 = eq(_T_623, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_625 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_626 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_627 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_628 = and(_T_624, _T_625) @[ifu_compress_ctl.scala 12:110]
+    node _T_629 = and(_T_628, _T_626) @[ifu_compress_ctl.scala 12:110]
+    node _T_630 = and(_T_629, _T_627) @[ifu_compress_ctl.scala 12:110]
+    node _T_631 = or(_T_622, _T_630) @[ifu_compress_ctl.scala 57:22]
+    node _T_632 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_633 = eq(_T_632, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_634 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_635 = and(_T_633, _T_634) @[ifu_compress_ctl.scala 12:110]
+    node _T_636 = or(_T_631, _T_635) @[ifu_compress_ctl.scala 57:46]
+    node _T_637 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_638 = eq(_T_637, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_639 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_640 = eq(_T_639, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_641 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_642 = and(_T_638, _T_640) @[ifu_compress_ctl.scala 12:110]
+    node _T_643 = and(_T_642, _T_641) @[ifu_compress_ctl.scala 12:110]
+    node rdrd = or(_T_636, _T_643) @[ifu_compress_ctl.scala 57:65]
+    node _T_644 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_645 = eq(_T_644, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_646 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_647 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_648 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_649 = and(_T_645, _T_646) @[ifu_compress_ctl.scala 12:110]
+    node _T_650 = and(_T_649, _T_647) @[ifu_compress_ctl.scala 12:110]
+    node _T_651 = and(_T_650, _T_648) @[ifu_compress_ctl.scala 12:110]
+    node _T_652 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_653 = eq(_T_652, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_654 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_655 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_656 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_657 = and(_T_653, _T_654) @[ifu_compress_ctl.scala 12:110]
+    node _T_658 = and(_T_657, _T_655) @[ifu_compress_ctl.scala 12:110]
+    node _T_659 = and(_T_658, _T_656) @[ifu_compress_ctl.scala 12:110]
+    node _T_660 = or(_T_651, _T_659) @[ifu_compress_ctl.scala 59:38]
+    node _T_661 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_662 = eq(_T_661, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_663 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_664 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_665 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_666 = and(_T_662, _T_663) @[ifu_compress_ctl.scala 12:110]
+    node _T_667 = and(_T_666, _T_664) @[ifu_compress_ctl.scala 12:110]
+    node _T_668 = and(_T_667, _T_665) @[ifu_compress_ctl.scala 12:110]
+    node _T_669 = or(_T_660, _T_668) @[ifu_compress_ctl.scala 59:63]
+    node _T_670 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_671 = eq(_T_670, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_672 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_673 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_674 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_675 = and(_T_671, _T_672) @[ifu_compress_ctl.scala 12:110]
+    node _T_676 = and(_T_675, _T_673) @[ifu_compress_ctl.scala 12:110]
+    node _T_677 = and(_T_676, _T_674) @[ifu_compress_ctl.scala 12:110]
+    node _T_678 = or(_T_669, _T_677) @[ifu_compress_ctl.scala 59:87]
+    node _T_679 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_680 = eq(_T_679, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_681 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_682 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_683 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_684 = and(_T_680, _T_681) @[ifu_compress_ctl.scala 12:110]
+    node _T_685 = and(_T_684, _T_682) @[ifu_compress_ctl.scala 12:110]
+    node _T_686 = and(_T_685, _T_683) @[ifu_compress_ctl.scala 12:110]
+    node _T_687 = or(_T_678, _T_686) @[ifu_compress_ctl.scala 60:27]
+    node _T_688 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_689 = eq(_T_688, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_690 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_691 = eq(_T_690, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_692 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_693 = eq(_T_692, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_694 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_695 = eq(_T_694, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_696 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_697 = eq(_T_696, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_698 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_699 = eq(_T_698, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_700 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_701 = eq(_T_700, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_702 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_703 = and(_T_689, _T_691) @[ifu_compress_ctl.scala 12:110]
+    node _T_704 = and(_T_703, _T_693) @[ifu_compress_ctl.scala 12:110]
+    node _T_705 = and(_T_704, _T_695) @[ifu_compress_ctl.scala 12:110]
+    node _T_706 = and(_T_705, _T_697) @[ifu_compress_ctl.scala 12:110]
+    node _T_707 = and(_T_706, _T_699) @[ifu_compress_ctl.scala 12:110]
+    node _T_708 = and(_T_707, _T_701) @[ifu_compress_ctl.scala 12:110]
+    node _T_709 = and(_T_708, _T_702) @[ifu_compress_ctl.scala 12:110]
+    node _T_710 = or(_T_687, _T_709) @[ifu_compress_ctl.scala 60:51]
+    node _T_711 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_712 = eq(_T_711, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_713 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_714 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_715 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_716 = and(_T_712, _T_713) @[ifu_compress_ctl.scala 12:110]
+    node _T_717 = and(_T_716, _T_714) @[ifu_compress_ctl.scala 12:110]
+    node _T_718 = and(_T_717, _T_715) @[ifu_compress_ctl.scala 12:110]
+    node _T_719 = or(_T_710, _T_718) @[ifu_compress_ctl.scala 60:89]
+    node _T_720 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_721 = eq(_T_720, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_722 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_723 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_724 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_725 = and(_T_721, _T_722) @[ifu_compress_ctl.scala 12:110]
+    node _T_726 = and(_T_725, _T_723) @[ifu_compress_ctl.scala 12:110]
+    node _T_727 = and(_T_726, _T_724) @[ifu_compress_ctl.scala 12:110]
+    node _T_728 = or(_T_719, _T_727) @[ifu_compress_ctl.scala 61:27]
+    node _T_729 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_730 = eq(_T_729, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_731 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_732 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_733 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_734 = and(_T_730, _T_731) @[ifu_compress_ctl.scala 12:110]
+    node _T_735 = and(_T_734, _T_732) @[ifu_compress_ctl.scala 12:110]
+    node _T_736 = and(_T_735, _T_733) @[ifu_compress_ctl.scala 12:110]
+    node _T_737 = or(_T_728, _T_736) @[ifu_compress_ctl.scala 61:51]
+    node _T_738 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_739 = eq(_T_738, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_740 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_741 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_742 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_743 = and(_T_739, _T_740) @[ifu_compress_ctl.scala 12:110]
+    node _T_744 = and(_T_743, _T_741) @[ifu_compress_ctl.scala 12:110]
+    node _T_745 = and(_T_744, _T_742) @[ifu_compress_ctl.scala 12:110]
+    node _T_746 = or(_T_737, _T_745) @[ifu_compress_ctl.scala 61:75]
+    node _T_747 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_748 = eq(_T_747, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_749 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_750 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_751 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_752 = and(_T_748, _T_749) @[ifu_compress_ctl.scala 12:110]
+    node _T_753 = and(_T_752, _T_750) @[ifu_compress_ctl.scala 12:110]
+    node _T_754 = and(_T_753, _T_751) @[ifu_compress_ctl.scala 12:110]
+    node _T_755 = or(_T_746, _T_754) @[ifu_compress_ctl.scala 61:99]
+    node _T_756 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_757 = eq(_T_756, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_758 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_759 = eq(_T_758, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_760 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_761 = eq(_T_760, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_762 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_763 = and(_T_757, _T_759) @[ifu_compress_ctl.scala 12:110]
+    node _T_764 = and(_T_763, _T_761) @[ifu_compress_ctl.scala 12:110]
+    node _T_765 = and(_T_764, _T_762) @[ifu_compress_ctl.scala 12:110]
+    node _T_766 = or(_T_755, _T_765) @[ifu_compress_ctl.scala 62:27]
+    node _T_767 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_768 = eq(_T_767, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_769 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_770 = eq(_T_769, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_771 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_772 = and(_T_768, _T_770) @[ifu_compress_ctl.scala 12:110]
+    node _T_773 = and(_T_772, _T_771) @[ifu_compress_ctl.scala 12:110]
+    node rdrs1 = or(_T_766, _T_773) @[ifu_compress_ctl.scala 62:54]
+    node _T_774 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_775 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_776 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_777 = and(_T_774, _T_775) @[ifu_compress_ctl.scala 12:110]
+    node _T_778 = and(_T_777, _T_776) @[ifu_compress_ctl.scala 12:110]
+    node _T_779 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_780 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_781 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_782 = and(_T_779, _T_780) @[ifu_compress_ctl.scala 12:110]
+    node _T_783 = and(_T_782, _T_781) @[ifu_compress_ctl.scala 12:110]
+    node _T_784 = or(_T_778, _T_783) @[ifu_compress_ctl.scala 64:34]
+    node _T_785 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_786 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_787 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_788 = and(_T_785, _T_786) @[ifu_compress_ctl.scala 12:110]
+    node _T_789 = and(_T_788, _T_787) @[ifu_compress_ctl.scala 12:110]
+    node _T_790 = or(_T_784, _T_789) @[ifu_compress_ctl.scala 64:54]
+    node _T_791 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_792 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_793 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_794 = and(_T_791, _T_792) @[ifu_compress_ctl.scala 12:110]
+    node _T_795 = and(_T_794, _T_793) @[ifu_compress_ctl.scala 12:110]
+    node _T_796 = or(_T_790, _T_795) @[ifu_compress_ctl.scala 64:74]
+    node _T_797 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_798 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_799 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_800 = and(_T_797, _T_798) @[ifu_compress_ctl.scala 12:110]
+    node _T_801 = and(_T_800, _T_799) @[ifu_compress_ctl.scala 12:110]
+    node _T_802 = or(_T_796, _T_801) @[ifu_compress_ctl.scala 64:94]
+    node _T_803 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_804 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_805 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_806 = and(_T_803, _T_804) @[ifu_compress_ctl.scala 12:110]
+    node _T_807 = and(_T_806, _T_805) @[ifu_compress_ctl.scala 12:110]
+    node rs2rs2 = or(_T_802, _T_807) @[ifu_compress_ctl.scala 64:114]
+    node _T_808 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_809 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_810 = eq(_T_809, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_811 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_812 = eq(_T_811, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_813 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_814 = and(_T_808, _T_810) @[ifu_compress_ctl.scala 12:110]
+    node _T_815 = and(_T_814, _T_812) @[ifu_compress_ctl.scala 12:110]
+    node rdprd = and(_T_815, _T_813) @[ifu_compress_ctl.scala 12:110]
+    node _T_816 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_817 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_818 = eq(_T_817, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_819 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_820 = and(_T_816, _T_818) @[ifu_compress_ctl.scala 12:110]
+    node _T_821 = and(_T_820, _T_819) @[ifu_compress_ctl.scala 12:110]
+    node _T_822 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_823 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_824 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_825 = and(_T_822, _T_823) @[ifu_compress_ctl.scala 12:110]
+    node _T_826 = and(_T_825, _T_824) @[ifu_compress_ctl.scala 12:110]
+    node _T_827 = or(_T_821, _T_826) @[ifu_compress_ctl.scala 68:36]
+    node _T_828 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_829 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_830 = eq(_T_829, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_831 = and(_T_828, _T_830) @[ifu_compress_ctl.scala 12:110]
+    node _T_832 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 68:85]
+    node _T_833 = eq(_T_832, UInt<1>("h00")) @[ifu_compress_ctl.scala 68:78]
+    node _T_834 = and(_T_831, _T_833) @[ifu_compress_ctl.scala 68:76]
+    node rdprs1 = or(_T_827, _T_834) @[ifu_compress_ctl.scala 68:57]
+    node _T_835 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_836 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_837 = eq(_T_836, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_838 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_839 = eq(_T_838, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_840 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_841 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_842 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_843 = and(_T_835, _T_837) @[ifu_compress_ctl.scala 12:110]
+    node _T_844 = and(_T_843, _T_839) @[ifu_compress_ctl.scala 12:110]
+    node _T_845 = and(_T_844, _T_840) @[ifu_compress_ctl.scala 12:110]
+    node _T_846 = and(_T_845, _T_841) @[ifu_compress_ctl.scala 12:110]
+    node _T_847 = and(_T_846, _T_842) @[ifu_compress_ctl.scala 12:110]
+    node _T_848 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_849 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_850 = eq(_T_849, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_851 = and(_T_848, _T_850) @[ifu_compress_ctl.scala 12:110]
+    node _T_852 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 70:75]
+    node _T_853 = eq(_T_852, UInt<1>("h00")) @[ifu_compress_ctl.scala 70:68]
+    node _T_854 = and(_T_851, _T_853) @[ifu_compress_ctl.scala 70:66]
+    node rs2prs2 = or(_T_847, _T_854) @[ifu_compress_ctl.scala 70:47]
+    node _T_855 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_856 = eq(_T_855, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_857 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_858 = eq(_T_857, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_859 = and(_T_856, _T_858) @[ifu_compress_ctl.scala 12:110]
+    node _T_860 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 72:42]
+    node _T_861 = eq(_T_860, UInt<1>("h00")) @[ifu_compress_ctl.scala 72:35]
+    node rs2prd = and(_T_859, _T_861) @[ifu_compress_ctl.scala 72:33]
+    node _T_862 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_863 = eq(_T_862, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_864 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_865 = eq(_T_864, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_866 = and(_T_863, _T_865) @[ifu_compress_ctl.scala 12:110]
+    node _T_867 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 74:43]
+    node _T_868 = eq(_T_867, UInt<1>("h00")) @[ifu_compress_ctl.scala 74:36]
+    node uimm9_2 = and(_T_866, _T_868) @[ifu_compress_ctl.scala 74:34]
+    node _T_869 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_870 = eq(_T_869, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_871 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_872 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_873 = eq(_T_872, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_874 = and(_T_870, _T_871) @[ifu_compress_ctl.scala 12:110]
+    node _T_875 = and(_T_874, _T_873) @[ifu_compress_ctl.scala 12:110]
+    node _T_876 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 76:48]
+    node _T_877 = eq(_T_876, UInt<1>("h00")) @[ifu_compress_ctl.scala 76:41]
+    node ulwimm6_2 = and(_T_875, _T_877) @[ifu_compress_ctl.scala 76:39]
+    node _T_878 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_879 = eq(_T_878, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_880 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_881 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_882 = and(_T_879, _T_880) @[ifu_compress_ctl.scala 12:110]
+    node ulwspimm7_2 = and(_T_882, _T_881) @[ifu_compress_ctl.scala 12:110]
+    node _T_883 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_884 = eq(_T_883, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_885 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_886 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_887 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_888 = eq(_T_887, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_889 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_890 = eq(_T_889, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_891 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:90]
+    node _T_892 = eq(_T_891, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_893 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_894 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:90]
+    node _T_895 = eq(_T_894, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_896 = and(_T_884, _T_885) @[ifu_compress_ctl.scala 12:110]
+    node _T_897 = and(_T_896, _T_886) @[ifu_compress_ctl.scala 12:110]
+    node _T_898 = and(_T_897, _T_888) @[ifu_compress_ctl.scala 12:110]
+    node _T_899 = and(_T_898, _T_890) @[ifu_compress_ctl.scala 12:110]
+    node _T_900 = and(_T_899, _T_892) @[ifu_compress_ctl.scala 12:110]
+    node _T_901 = and(_T_900, _T_893) @[ifu_compress_ctl.scala 12:110]
+    node rdeq2 = and(_T_901, _T_895) @[ifu_compress_ctl.scala 12:110]
+    node _T_902 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_903 = eq(_T_902, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_904 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_905 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_906 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_907 = eq(_T_906, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_908 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_909 = eq(_T_908, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_910 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_911 = eq(_T_910, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_912 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_913 = eq(_T_912, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_914 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_915 = eq(_T_914, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_916 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_917 = and(_T_903, _T_904) @[ifu_compress_ctl.scala 12:110]
+    node _T_918 = and(_T_917, _T_905) @[ifu_compress_ctl.scala 12:110]
+    node _T_919 = and(_T_918, _T_907) @[ifu_compress_ctl.scala 12:110]
+    node _T_920 = and(_T_919, _T_909) @[ifu_compress_ctl.scala 12:110]
+    node _T_921 = and(_T_920, _T_911) @[ifu_compress_ctl.scala 12:110]
+    node _T_922 = and(_T_921, _T_913) @[ifu_compress_ctl.scala 12:110]
+    node _T_923 = and(_T_922, _T_915) @[ifu_compress_ctl.scala 12:110]
+    node _T_924 = and(_T_923, _T_916) @[ifu_compress_ctl.scala 12:110]
+    node _T_925 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_926 = eq(_T_925, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_927 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_928 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_929 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_930 = eq(_T_929, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_931 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_932 = eq(_T_931, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_933 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_934 = eq(_T_933, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_935 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_936 = eq(_T_935, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_937 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_938 = eq(_T_937, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_939 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_940 = and(_T_926, _T_927) @[ifu_compress_ctl.scala 12:110]
+    node _T_941 = and(_T_940, _T_928) @[ifu_compress_ctl.scala 12:110]
+    node _T_942 = and(_T_941, _T_930) @[ifu_compress_ctl.scala 12:110]
+    node _T_943 = and(_T_942, _T_932) @[ifu_compress_ctl.scala 12:110]
+    node _T_944 = and(_T_943, _T_934) @[ifu_compress_ctl.scala 12:110]
+    node _T_945 = and(_T_944, _T_936) @[ifu_compress_ctl.scala 12:110]
+    node _T_946 = and(_T_945, _T_938) @[ifu_compress_ctl.scala 12:110]
+    node _T_947 = and(_T_946, _T_939) @[ifu_compress_ctl.scala 12:110]
+    node _T_948 = or(_T_924, _T_947) @[ifu_compress_ctl.scala 82:53]
+    node _T_949 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_950 = eq(_T_949, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_951 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_952 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_953 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_954 = eq(_T_953, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_955 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_956 = eq(_T_955, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_957 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_958 = eq(_T_957, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_959 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_960 = eq(_T_959, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_961 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_962 = eq(_T_961, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_963 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_964 = and(_T_950, _T_951) @[ifu_compress_ctl.scala 12:110]
+    node _T_965 = and(_T_964, _T_952) @[ifu_compress_ctl.scala 12:110]
+    node _T_966 = and(_T_965, _T_954) @[ifu_compress_ctl.scala 12:110]
+    node _T_967 = and(_T_966, _T_956) @[ifu_compress_ctl.scala 12:110]
+    node _T_968 = and(_T_967, _T_958) @[ifu_compress_ctl.scala 12:110]
+    node _T_969 = and(_T_968, _T_960) @[ifu_compress_ctl.scala 12:110]
+    node _T_970 = and(_T_969, _T_962) @[ifu_compress_ctl.scala 12:110]
+    node _T_971 = and(_T_970, _T_963) @[ifu_compress_ctl.scala 12:110]
+    node _T_972 = or(_T_948, _T_971) @[ifu_compress_ctl.scala 82:93]
+    node _T_973 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_974 = eq(_T_973, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_975 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_976 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_977 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_978 = eq(_T_977, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_979 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_980 = eq(_T_979, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_981 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_982 = eq(_T_981, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_983 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_984 = eq(_T_983, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_985 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_986 = eq(_T_985, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_987 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_988 = and(_T_974, _T_975) @[ifu_compress_ctl.scala 12:110]
+    node _T_989 = and(_T_988, _T_976) @[ifu_compress_ctl.scala 12:110]
+    node _T_990 = and(_T_989, _T_978) @[ifu_compress_ctl.scala 12:110]
+    node _T_991 = and(_T_990, _T_980) @[ifu_compress_ctl.scala 12:110]
+    node _T_992 = and(_T_991, _T_982) @[ifu_compress_ctl.scala 12:110]
+    node _T_993 = and(_T_992, _T_984) @[ifu_compress_ctl.scala 12:110]
+    node _T_994 = and(_T_993, _T_986) @[ifu_compress_ctl.scala 12:110]
+    node _T_995 = and(_T_994, _T_987) @[ifu_compress_ctl.scala 12:110]
+    node _T_996 = or(_T_972, _T_995) @[ifu_compress_ctl.scala 83:42]
+    node _T_997 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_998 = eq(_T_997, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_999 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_1000 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_1001 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:90]
+    node _T_1002 = eq(_T_1001, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1003 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:90]
+    node _T_1004 = eq(_T_1003, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1005 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:90]
+    node _T_1006 = eq(_T_1005, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1007 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:90]
+    node _T_1008 = eq(_T_1007, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1009 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:90]
+    node _T_1010 = eq(_T_1009, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1011 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1012 = and(_T_998, _T_999) @[ifu_compress_ctl.scala 12:110]
+    node _T_1013 = and(_T_1012, _T_1000) @[ifu_compress_ctl.scala 12:110]
+    node _T_1014 = and(_T_1013, _T_1002) @[ifu_compress_ctl.scala 12:110]
+    node _T_1015 = and(_T_1014, _T_1004) @[ifu_compress_ctl.scala 12:110]
+    node _T_1016 = and(_T_1015, _T_1006) @[ifu_compress_ctl.scala 12:110]
+    node _T_1017 = and(_T_1016, _T_1008) @[ifu_compress_ctl.scala 12:110]
+    node _T_1018 = and(_T_1017, _T_1010) @[ifu_compress_ctl.scala 12:110]
+    node _T_1019 = and(_T_1018, _T_1011) @[ifu_compress_ctl.scala 12:110]
+    node _T_1020 = or(_T_996, _T_1019) @[ifu_compress_ctl.scala 83:81]
+    node _T_1021 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1022 = eq(_T_1021, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1023 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1024 = eq(_T_1023, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1025 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1026 = and(_T_1022, _T_1024) @[ifu_compress_ctl.scala 12:110]
+    node _T_1027 = and(_T_1026, _T_1025) @[ifu_compress_ctl.scala 12:110]
+    node rdeq1 = or(_T_1020, _T_1027) @[ifu_compress_ctl.scala 84:42]
+    node _T_1028 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1029 = eq(_T_1028, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1030 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1031 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1032 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_1033 = eq(_T_1032, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1034 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_1035 = eq(_T_1034, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1036 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:90]
+    node _T_1037 = eq(_T_1036, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1038 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_1039 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:90]
+    node _T_1040 = eq(_T_1039, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1041 = and(_T_1029, _T_1030) @[ifu_compress_ctl.scala 12:110]
+    node _T_1042 = and(_T_1041, _T_1031) @[ifu_compress_ctl.scala 12:110]
+    node _T_1043 = and(_T_1042, _T_1033) @[ifu_compress_ctl.scala 12:110]
+    node _T_1044 = and(_T_1043, _T_1035) @[ifu_compress_ctl.scala 12:110]
+    node _T_1045 = and(_T_1044, _T_1037) @[ifu_compress_ctl.scala 12:110]
+    node _T_1046 = and(_T_1045, _T_1038) @[ifu_compress_ctl.scala 12:110]
+    node _T_1047 = and(_T_1046, _T_1040) @[ifu_compress_ctl.scala 12:110]
+    node _T_1048 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1049 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1050 = and(_T_1048, _T_1049) @[ifu_compress_ctl.scala 12:110]
+    node _T_1051 = or(_T_1047, _T_1050) @[ifu_compress_ctl.scala 86:53]
+    node _T_1052 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1053 = eq(_T_1052, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1054 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1055 = eq(_T_1054, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1056 = and(_T_1053, _T_1055) @[ifu_compress_ctl.scala 12:110]
+    node _T_1057 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 86:100]
+    node _T_1058 = eq(_T_1057, UInt<1>("h00")) @[ifu_compress_ctl.scala 86:93]
+    node _T_1059 = and(_T_1056, _T_1058) @[ifu_compress_ctl.scala 86:91]
+    node rs1eq2 = or(_T_1051, _T_1059) @[ifu_compress_ctl.scala 86:71]
+    node _T_1060 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1061 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1062 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1063 = and(_T_1060, _T_1061) @[ifu_compress_ctl.scala 12:110]
+    node sbroffset8_1 = and(_T_1063, _T_1062) @[ifu_compress_ctl.scala 12:110]
+    node _T_1064 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1065 = eq(_T_1064, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1066 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1067 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1068 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_1069 = eq(_T_1068, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1070 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_1071 = eq(_T_1070, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1072 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:90]
+    node _T_1073 = eq(_T_1072, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1074 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_1075 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:90]
+    node _T_1076 = eq(_T_1075, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1077 = and(_T_1065, _T_1066) @[ifu_compress_ctl.scala 12:110]
+    node _T_1078 = and(_T_1077, _T_1067) @[ifu_compress_ctl.scala 12:110]
+    node _T_1079 = and(_T_1078, _T_1069) @[ifu_compress_ctl.scala 12:110]
+    node _T_1080 = and(_T_1079, _T_1071) @[ifu_compress_ctl.scala 12:110]
+    node _T_1081 = and(_T_1080, _T_1073) @[ifu_compress_ctl.scala 12:110]
+    node _T_1082 = and(_T_1081, _T_1074) @[ifu_compress_ctl.scala 12:110]
+    node simm9_4 = and(_T_1082, _T_1076) @[ifu_compress_ctl.scala 12:110]
+    node _T_1083 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1084 = eq(_T_1083, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1085 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1086 = eq(_T_1085, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1087 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_1088 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_1089 = eq(_T_1088, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1090 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1091 = and(_T_1084, _T_1086) @[ifu_compress_ctl.scala 12:110]
+    node _T_1092 = and(_T_1091, _T_1087) @[ifu_compress_ctl.scala 12:110]
+    node _T_1093 = and(_T_1092, _T_1089) @[ifu_compress_ctl.scala 12:110]
+    node _T_1094 = and(_T_1093, _T_1090) @[ifu_compress_ctl.scala 12:110]
+    node _T_1095 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1096 = eq(_T_1095, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1097 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1098 = eq(_T_1097, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1099 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1100 = and(_T_1096, _T_1098) @[ifu_compress_ctl.scala 12:110]
+    node _T_1101 = and(_T_1100, _T_1099) @[ifu_compress_ctl.scala 12:110]
+    node simm5_0 = or(_T_1094, _T_1101) @[ifu_compress_ctl.scala 92:45]
+    node _T_1102 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1103 = eq(_T_1102, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1104 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node sjaloffset11_1 = and(_T_1103, _T_1104) @[ifu_compress_ctl.scala 12:110]
+    node _T_1105 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1106 = eq(_T_1105, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1107 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1108 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1109 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_1110 = and(_T_1106, _T_1107) @[ifu_compress_ctl.scala 12:110]
+    node _T_1111 = and(_T_1110, _T_1108) @[ifu_compress_ctl.scala 12:110]
+    node _T_1112 = and(_T_1111, _T_1109) @[ifu_compress_ctl.scala 12:110]
+    node _T_1113 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1114 = eq(_T_1113, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1115 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1116 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1117 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:90]
+    node _T_1118 = eq(_T_1117, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1119 = and(_T_1114, _T_1115) @[ifu_compress_ctl.scala 12:110]
+    node _T_1120 = and(_T_1119, _T_1116) @[ifu_compress_ctl.scala 12:110]
+    node _T_1121 = and(_T_1120, _T_1118) @[ifu_compress_ctl.scala 12:110]
+    node _T_1122 = or(_T_1112, _T_1121) @[ifu_compress_ctl.scala 96:44]
+    node _T_1123 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1124 = eq(_T_1123, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1125 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1126 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1127 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_1128 = and(_T_1124, _T_1125) @[ifu_compress_ctl.scala 12:110]
+    node _T_1129 = and(_T_1128, _T_1126) @[ifu_compress_ctl.scala 12:110]
+    node _T_1130 = and(_T_1129, _T_1127) @[ifu_compress_ctl.scala 12:110]
+    node _T_1131 = or(_T_1122, _T_1130) @[ifu_compress_ctl.scala 96:70]
+    node _T_1132 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1133 = eq(_T_1132, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1134 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1135 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1136 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_1137 = and(_T_1133, _T_1134) @[ifu_compress_ctl.scala 12:110]
+    node _T_1138 = and(_T_1137, _T_1135) @[ifu_compress_ctl.scala 12:110]
+    node _T_1139 = and(_T_1138, _T_1136) @[ifu_compress_ctl.scala 12:110]
+    node _T_1140 = or(_T_1131, _T_1139) @[ifu_compress_ctl.scala 96:95]
+    node _T_1141 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1142 = eq(_T_1141, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1143 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1144 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1145 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_1146 = and(_T_1142, _T_1143) @[ifu_compress_ctl.scala 12:110]
+    node _T_1147 = and(_T_1146, _T_1144) @[ifu_compress_ctl.scala 12:110]
+    node _T_1148 = and(_T_1147, _T_1145) @[ifu_compress_ctl.scala 12:110]
+    node sluimm17_12 = or(_T_1140, _T_1148) @[ifu_compress_ctl.scala 96:121]
+    node _T_1149 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1150 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1151 = eq(_T_1150, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1152 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1153 = eq(_T_1152, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1154 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:90]
+    node _T_1155 = eq(_T_1154, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1156 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1157 = and(_T_1149, _T_1151) @[ifu_compress_ctl.scala 12:110]
+    node _T_1158 = and(_T_1157, _T_1153) @[ifu_compress_ctl.scala 12:110]
+    node _T_1159 = and(_T_1158, _T_1155) @[ifu_compress_ctl.scala 12:110]
+    node _T_1160 = and(_T_1159, _T_1156) @[ifu_compress_ctl.scala 12:110]
+    node _T_1161 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1162 = eq(_T_1161, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1163 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1164 = eq(_T_1163, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1165 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1166 = and(_T_1162, _T_1164) @[ifu_compress_ctl.scala 12:110]
+    node _T_1167 = and(_T_1166, _T_1165) @[ifu_compress_ctl.scala 12:110]
+    node uimm5_0 = or(_T_1160, _T_1167) @[ifu_compress_ctl.scala 98:45]
+    node _T_1168 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1169 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1170 = eq(_T_1169, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1171 = and(_T_1168, _T_1170) @[ifu_compress_ctl.scala 12:110]
+    node _T_1172 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 100:44]
+    node _T_1173 = eq(_T_1172, UInt<1>("h00")) @[ifu_compress_ctl.scala 100:37]
+    node uswimm6_2 = and(_T_1171, _T_1173) @[ifu_compress_ctl.scala 100:35]
+    node _T_1174 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1175 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1176 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1177 = and(_T_1174, _T_1175) @[ifu_compress_ctl.scala 12:110]
+    node uswspimm7_2 = and(_T_1177, _T_1176) @[ifu_compress_ctl.scala 12:110]
+    node _T_1178 = cat(out[2], out[1]) @[Cat.scala 29:58]
+    node _T_1179 = cat(_T_1178, out[0]) @[Cat.scala 29:58]
+    node _T_1180 = cat(out[4], out[3]) @[Cat.scala 29:58]
+    node _T_1181 = cat(out[6], out[5]) @[Cat.scala 29:58]
+    node _T_1182 = cat(_T_1181, _T_1180) @[Cat.scala 29:58]
+    node l1_6 = cat(_T_1182, _T_1179) @[Cat.scala 29:58]
+    node _T_1183 = cat(out[8], out[7]) @[Cat.scala 29:58]
+    node _T_1184 = cat(out[11], out[10]) @[Cat.scala 29:58]
+    node _T_1185 = cat(_T_1184, out[9]) @[Cat.scala 29:58]
+    node _T_1186 = cat(_T_1185, _T_1183) @[Cat.scala 29:58]
+    node _T_1187 = bits(rdrd, 0, 0) @[ifu_compress_ctl.scala 106:81]
+    node _T_1188 = bits(rdprd, 0, 0) @[ifu_compress_ctl.scala 107:9]
+    node _T_1189 = bits(rs2prd, 0, 0) @[ifu_compress_ctl.scala 107:30]
+    node _T_1190 = bits(rdeq1, 0, 0) @[ifu_compress_ctl.scala 107:51]
+    node _T_1191 = bits(rdeq2, 0, 0) @[ifu_compress_ctl.scala 107:75]
+    node _T_1192 = mux(_T_1187, rdd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1193 = mux(_T_1188, rdpd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1194 = mux(_T_1189, rs2pd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1195 = mux(_T_1190, UInt<5>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1196 = mux(_T_1191, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1197 = or(_T_1192, _T_1193) @[Mux.scala 27:72]
+    node _T_1198 = or(_T_1197, _T_1194) @[Mux.scala 27:72]
+    node _T_1199 = or(_T_1198, _T_1195) @[Mux.scala 27:72]
+    node _T_1200 = or(_T_1199, _T_1196) @[Mux.scala 27:72]
+    wire _T_1201 : UInt<5> @[Mux.scala 27:72]
+    _T_1201 <= _T_1200 @[Mux.scala 27:72]
+    node l1_11 = or(_T_1186, _T_1201) @[ifu_compress_ctl.scala 106:64]
+    node _T_1202 = cat(out[14], out[13]) @[Cat.scala 29:58]
+    node l1_14 = cat(_T_1202, out[12]) @[Cat.scala 29:58]
+    node _T_1203 = cat(out[16], out[15]) @[Cat.scala 29:58]
+    node _T_1204 = cat(out[19], out[18]) @[Cat.scala 29:58]
+    node _T_1205 = cat(_T_1204, out[17]) @[Cat.scala 29:58]
+    node _T_1206 = cat(_T_1205, _T_1203) @[Cat.scala 29:58]
+    node _T_1207 = bits(rdrs1, 0, 0) @[ifu_compress_ctl.scala 111:85]
+    node _T_1208 = bits(rdprs1, 0, 0) @[ifu_compress_ctl.scala 112:12]
+    node _T_1209 = bits(rs1eq2, 0, 0) @[ifu_compress_ctl.scala 112:33]
+    node _T_1210 = mux(_T_1207, rdd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1211 = mux(_T_1208, rdpd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1212 = mux(_T_1209, UInt<5>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1213 = or(_T_1210, _T_1211) @[Mux.scala 27:72]
+    node _T_1214 = or(_T_1213, _T_1212) @[Mux.scala 27:72]
+    wire _T_1215 : UInt<5> @[Mux.scala 27:72]
+    _T_1215 <= _T_1214 @[Mux.scala 27:72]
+    node l1_19 = or(_T_1206, _T_1215) @[ifu_compress_ctl.scala 111:67]
+    node _T_1216 = cat(out[21], out[20]) @[Cat.scala 29:58]
+    node _T_1217 = cat(out[24], out[23]) @[Cat.scala 29:58]
+    node _T_1218 = cat(_T_1217, out[22]) @[Cat.scala 29:58]
+    node _T_1219 = cat(_T_1218, _T_1216) @[Cat.scala 29:58]
+    node _T_1220 = bits(rs2rs2, 0, 0) @[ifu_compress_ctl.scala 114:86]
+    node _T_1221 = bits(rs2prs2, 0, 0) @[ifu_compress_ctl.scala 115:13]
+    node _T_1222 = mux(_T_1220, rs2d, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1223 = mux(_T_1221, rs2pd, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1224 = or(_T_1222, _T_1223) @[Mux.scala 27:72]
+    wire _T_1225 : UInt<5> @[Mux.scala 27:72]
+    _T_1225 <= _T_1224 @[Mux.scala 27:72]
+    node l1_24 = or(_T_1219, _T_1225) @[ifu_compress_ctl.scala 114:67]
+    node _T_1226 = cat(out[27], out[26]) @[Cat.scala 29:58]
+    node _T_1227 = cat(_T_1226, out[25]) @[Cat.scala 29:58]
+    node _T_1228 = cat(out[29], out[28]) @[Cat.scala 29:58]
+    node _T_1229 = cat(out[31], out[30]) @[Cat.scala 29:58]
+    node _T_1230 = cat(_T_1229, _T_1228) @[Cat.scala 29:58]
+    node l1_31 = cat(_T_1230, _T_1227) @[Cat.scala 29:58]
+    node _T_1231 = cat(l1_14, l1_11) @[Cat.scala 29:58]
+    node _T_1232 = cat(_T_1231, l1_6) @[Cat.scala 29:58]
+    node _T_1233 = cat(l1_31, l1_24) @[Cat.scala 29:58]
+    node _T_1234 = cat(_T_1233, l1_19) @[Cat.scala 29:58]
+    node l1 = cat(_T_1234, _T_1232) @[Cat.scala 29:58]
+    node _T_1235 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 121:26]
+    node _T_1236 = bits(io.din, 6, 2) @[ifu_compress_ctl.scala 121:38]
+    node simm5d = cat(_T_1235, _T_1236) @[Cat.scala 29:58]
+    node _T_1237 = bits(io.din, 10, 7) @[ifu_compress_ctl.scala 122:26]
+    node _T_1238 = bits(io.din, 12, 11) @[ifu_compress_ctl.scala 122:40]
+    node _T_1239 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 122:55]
+    node _T_1240 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 122:66]
+    node _T_1241 = cat(_T_1239, _T_1240) @[Cat.scala 29:58]
+    node _T_1242 = cat(_T_1237, _T_1238) @[Cat.scala 29:58]
+    node uimm9d = cat(_T_1242, _T_1241) @[Cat.scala 29:58]
+    node _T_1243 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 123:26]
+    node _T_1244 = bits(io.din, 4, 3) @[ifu_compress_ctl.scala 123:38]
+    node _T_1245 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 123:51]
+    node _T_1246 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 123:62]
+    node _T_1247 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 123:73]
+    node _T_1248 = cat(_T_1246, _T_1247) @[Cat.scala 29:58]
+    node _T_1249 = cat(_T_1243, _T_1244) @[Cat.scala 29:58]
+    node _T_1250 = cat(_T_1249, _T_1245) @[Cat.scala 29:58]
+    node simm9d = cat(_T_1250, _T_1248) @[Cat.scala 29:58]
+    node _T_1251 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 124:28]
+    node _T_1252 = bits(io.din, 12, 10) @[ifu_compress_ctl.scala 124:39]
+    node _T_1253 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 124:54]
+    node _T_1254 = cat(_T_1251, _T_1252) @[Cat.scala 29:58]
+    node ulwimm6d = cat(_T_1254, _T_1253) @[Cat.scala 29:58]
+    node _T_1255 = bits(io.din, 3, 2) @[ifu_compress_ctl.scala 125:30]
+    node _T_1256 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 125:43]
+    node _T_1257 = bits(io.din, 6, 4) @[ifu_compress_ctl.scala 125:55]
+    node _T_1258 = cat(_T_1255, _T_1256) @[Cat.scala 29:58]
+    node ulwspimm7d = cat(_T_1258, _T_1257) @[Cat.scala 29:58]
+    node _T_1259 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 126:26]
+    node _T_1260 = bits(io.din, 6, 2) @[ifu_compress_ctl.scala 126:38]
+    node uimm5d = cat(_T_1259, _T_1260) @[Cat.scala 29:58]
+    node _T_1261 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 127:27]
+    node _T_1262 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 127:39]
+    node _T_1263 = bits(io.din, 10, 9) @[ifu_compress_ctl.scala 127:50]
+    node _T_1264 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 127:64]
+    node _T_1265 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 127:75]
+    node _T_1266 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 127:86]
+    node _T_1267 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 127:97]
+    node _T_1268 = bits(io.din, 5, 4) @[ifu_compress_ctl.scala 128:11]
+    node _T_1269 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 128:24]
+    node _T_1270 = cat(_T_1268, _T_1269) @[Cat.scala 29:58]
+    node _T_1271 = cat(_T_1266, _T_1267) @[Cat.scala 29:58]
+    node _T_1272 = cat(_T_1271, _T_1270) @[Cat.scala 29:58]
+    node _T_1273 = cat(_T_1264, _T_1265) @[Cat.scala 29:58]
+    node _T_1274 = cat(_T_1261, _T_1262) @[Cat.scala 29:58]
+    node _T_1275 = cat(_T_1274, _T_1263) @[Cat.scala 29:58]
+    node _T_1276 = cat(_T_1275, _T_1273) @[Cat.scala 29:58]
+    node sjald_1 = cat(_T_1276, _T_1272) @[Cat.scala 29:58]
+    node _T_1277 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 129:32]
+    wire _T_1278 : UInt<1>[9] @[lib.scala 12:48]
+    _T_1278[0] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[1] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[2] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[3] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[4] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[5] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[6] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[7] <= _T_1277 @[lib.scala 12:48]
+    _T_1278[8] <= _T_1277 @[lib.scala 12:48]
+    node _T_1279 = cat(_T_1278[0], _T_1278[1]) @[Cat.scala 29:58]
+    node _T_1280 = cat(_T_1279, _T_1278[2]) @[Cat.scala 29:58]
+    node _T_1281 = cat(_T_1280, _T_1278[3]) @[Cat.scala 29:58]
+    node _T_1282 = cat(_T_1281, _T_1278[4]) @[Cat.scala 29:58]
+    node _T_1283 = cat(_T_1282, _T_1278[5]) @[Cat.scala 29:58]
+    node _T_1284 = cat(_T_1283, _T_1278[6]) @[Cat.scala 29:58]
+    node _T_1285 = cat(_T_1284, _T_1278[7]) @[Cat.scala 29:58]
+    node sjald_12 = cat(_T_1285, _T_1278[8]) @[Cat.scala 29:58]
+    node sjald = cat(sjald_12, sjald_1) @[Cat.scala 29:58]
+    node _T_1286 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 131:36]
+    wire _T_1287 : UInt<1>[15] @[lib.scala 12:48]
+    _T_1287[0] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[1] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[2] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[3] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[4] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[5] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[6] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[7] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[8] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[9] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[10] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[11] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[12] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[13] <= _T_1286 @[lib.scala 12:48]
+    _T_1287[14] <= _T_1286 @[lib.scala 12:48]
+    node _T_1288 = cat(_T_1287[0], _T_1287[1]) @[Cat.scala 29:58]
+    node _T_1289 = cat(_T_1288, _T_1287[2]) @[Cat.scala 29:58]
+    node _T_1290 = cat(_T_1289, _T_1287[3]) @[Cat.scala 29:58]
+    node _T_1291 = cat(_T_1290, _T_1287[4]) @[Cat.scala 29:58]
+    node _T_1292 = cat(_T_1291, _T_1287[5]) @[Cat.scala 29:58]
+    node _T_1293 = cat(_T_1292, _T_1287[6]) @[Cat.scala 29:58]
+    node _T_1294 = cat(_T_1293, _T_1287[7]) @[Cat.scala 29:58]
+    node _T_1295 = cat(_T_1294, _T_1287[8]) @[Cat.scala 29:58]
+    node _T_1296 = cat(_T_1295, _T_1287[9]) @[Cat.scala 29:58]
+    node _T_1297 = cat(_T_1296, _T_1287[10]) @[Cat.scala 29:58]
+    node _T_1298 = cat(_T_1297, _T_1287[11]) @[Cat.scala 29:58]
+    node _T_1299 = cat(_T_1298, _T_1287[12]) @[Cat.scala 29:58]
+    node _T_1300 = cat(_T_1299, _T_1287[13]) @[Cat.scala 29:58]
+    node _T_1301 = cat(_T_1300, _T_1287[14]) @[Cat.scala 29:58]
+    node _T_1302 = bits(io.din, 6, 2) @[ifu_compress_ctl.scala 131:49]
+    node sluimmd = cat(_T_1301, _T_1302) @[Cat.scala 29:58]
+    node _T_1303 = bits(l1, 31, 20) @[ifu_compress_ctl.scala 133:17]
+    node _T_1304 = bits(simm5_0, 0, 0) @[ifu_compress_ctl.scala 134:23]
+    node _T_1305 = bits(simm5d, 5, 5) @[ifu_compress_ctl.scala 134:49]
+    wire _T_1306 : UInt<1>[7] @[lib.scala 12:48]
+    _T_1306[0] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[1] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[2] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[3] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[4] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[5] <= _T_1305 @[lib.scala 12:48]
+    _T_1306[6] <= _T_1305 @[lib.scala 12:48]
+    node _T_1307 = cat(_T_1306[0], _T_1306[1]) @[Cat.scala 29:58]
+    node _T_1308 = cat(_T_1307, _T_1306[2]) @[Cat.scala 29:58]
+    node _T_1309 = cat(_T_1308, _T_1306[3]) @[Cat.scala 29:58]
+    node _T_1310 = cat(_T_1309, _T_1306[4]) @[Cat.scala 29:58]
+    node _T_1311 = cat(_T_1310, _T_1306[5]) @[Cat.scala 29:58]
+    node _T_1312 = cat(_T_1311, _T_1306[6]) @[Cat.scala 29:58]
+    node _T_1313 = bits(simm5d, 4, 0) @[ifu_compress_ctl.scala 134:61]
+    node _T_1314 = cat(_T_1312, _T_1313) @[Cat.scala 29:58]
+    node _T_1315 = bits(uimm9_2, 0, 0) @[ifu_compress_ctl.scala 135:23]
+    node _T_1316 = cat(UInt<2>("h00"), uimm9d) @[Cat.scala 29:58]
+    node _T_1317 = cat(_T_1316, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_1318 = bits(simm9_4, 0, 0) @[ifu_compress_ctl.scala 136:23]
+    node _T_1319 = bits(simm9d, 5, 5) @[ifu_compress_ctl.scala 136:49]
+    wire _T_1320 : UInt<1>[3] @[lib.scala 12:48]
+    _T_1320[0] <= _T_1319 @[lib.scala 12:48]
+    _T_1320[1] <= _T_1319 @[lib.scala 12:48]
+    _T_1320[2] <= _T_1319 @[lib.scala 12:48]
+    node _T_1321 = cat(_T_1320[0], _T_1320[1]) @[Cat.scala 29:58]
+    node _T_1322 = cat(_T_1321, _T_1320[2]) @[Cat.scala 29:58]
+    node _T_1323 = bits(simm9d, 4, 0) @[ifu_compress_ctl.scala 136:61]
+    node _T_1324 = cat(_T_1322, _T_1323) @[Cat.scala 29:58]
+    node _T_1325 = cat(_T_1324, UInt<4>("h00")) @[Cat.scala 29:58]
+    node _T_1326 = bits(ulwimm6_2, 0, 0) @[ifu_compress_ctl.scala 137:25]
+    node _T_1327 = cat(UInt<5>("h00"), ulwimm6d) @[Cat.scala 29:58]
+    node _T_1328 = cat(_T_1327, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_1329 = bits(ulwspimm7_2, 0, 0) @[ifu_compress_ctl.scala 138:27]
+    node _T_1330 = cat(UInt<4>("h00"), ulwspimm7d) @[Cat.scala 29:58]
+    node _T_1331 = cat(_T_1330, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_1332 = bits(uimm5_0, 0, 0) @[ifu_compress_ctl.scala 139:23]
+    node _T_1333 = cat(UInt<6>("h00"), uimm5d) @[Cat.scala 29:58]
+    node _T_1334 = bits(sjaloffset11_1, 0, 0) @[ifu_compress_ctl.scala 140:30]
+    node _T_1335 = bits(sjald, 19, 19) @[ifu_compress_ctl.scala 140:47]
+    node _T_1336 = bits(sjald, 9, 0) @[ifu_compress_ctl.scala 140:58]
+    node _T_1337 = bits(sjald, 10, 10) @[ifu_compress_ctl.scala 140:70]
+    node _T_1338 = cat(_T_1335, _T_1336) @[Cat.scala 29:58]
+    node _T_1339 = cat(_T_1338, _T_1337) @[Cat.scala 29:58]
+    node _T_1340 = bits(sluimm17_12, 0, 0) @[ifu_compress_ctl.scala 141:27]
+    node _T_1341 = bits(sluimmd, 19, 8) @[ifu_compress_ctl.scala 141:42]
+    node _T_1342 = mux(_T_1304, _T_1314, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1343 = mux(_T_1315, _T_1317, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1344 = mux(_T_1318, _T_1325, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1345 = mux(_T_1326, _T_1328, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1346 = mux(_T_1329, _T_1331, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1347 = mux(_T_1332, _T_1333, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1348 = mux(_T_1334, _T_1339, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1349 = mux(_T_1340, _T_1341, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1350 = or(_T_1342, _T_1343) @[Mux.scala 27:72]
+    node _T_1351 = or(_T_1350, _T_1344) @[Mux.scala 27:72]
+    node _T_1352 = or(_T_1351, _T_1345) @[Mux.scala 27:72]
+    node _T_1353 = or(_T_1352, _T_1346) @[Mux.scala 27:72]
+    node _T_1354 = or(_T_1353, _T_1347) @[Mux.scala 27:72]
+    node _T_1355 = or(_T_1354, _T_1348) @[Mux.scala 27:72]
+    node _T_1356 = or(_T_1355, _T_1349) @[Mux.scala 27:72]
+    wire _T_1357 : UInt<12> @[Mux.scala 27:72]
+    _T_1357 <= _T_1356 @[Mux.scala 27:72]
+    node l2_31 = or(_T_1303, _T_1357) @[ifu_compress_ctl.scala 133:25]
+    node _T_1358 = bits(l1, 19, 12) @[ifu_compress_ctl.scala 143:17]
+    node _T_1359 = bits(sjaloffset11_1, 0, 0) @[ifu_compress_ctl.scala 143:52]
+    node _T_1360 = bits(sjald, 19, 12) @[ifu_compress_ctl.scala 143:65]
+    node _T_1361 = bits(sluimm17_12, 0, 0) @[ifu_compress_ctl.scala 144:49]
+    node _T_1362 = bits(sluimmd, 7, 0) @[ifu_compress_ctl.scala 144:64]
+    node _T_1363 = mux(_T_1359, _T_1360, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1364 = mux(_T_1361, _T_1362, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1365 = or(_T_1363, _T_1364) @[Mux.scala 27:72]
+    wire _T_1366 : UInt<8> @[Mux.scala 27:72]
+    _T_1366 <= _T_1365 @[Mux.scala 27:72]
+    node l2_19 = or(_T_1358, _T_1366) @[ifu_compress_ctl.scala 143:25]
+    node _T_1367 = bits(l1, 11, 0) @[ifu_compress_ctl.scala 145:32]
+    node _T_1368 = cat(l2_31, l2_19) @[Cat.scala 29:58]
+    node l2 = cat(_T_1368, _T_1367) @[Cat.scala 29:58]
+    node _T_1369 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 147:25]
+    node _T_1370 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 147:36]
+    node _T_1371 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 147:46]
+    node _T_1372 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 147:56]
+    node _T_1373 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 147:66]
+    node _T_1374 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 147:77]
+    node _T_1375 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 147:88]
+    node _T_1376 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 147:98]
+    node _T_1377 = cat(_T_1376, UInt<1>("h00")) @[Cat.scala 29:58]
+    node _T_1378 = cat(_T_1374, _T_1375) @[Cat.scala 29:58]
+    node _T_1379 = cat(_T_1378, _T_1377) @[Cat.scala 29:58]
+    node _T_1380 = cat(_T_1372, _T_1373) @[Cat.scala 29:58]
+    node _T_1381 = cat(_T_1369, _T_1370) @[Cat.scala 29:58]
+    node _T_1382 = cat(_T_1381, _T_1371) @[Cat.scala 29:58]
+    node _T_1383 = cat(_T_1382, _T_1380) @[Cat.scala 29:58]
+    node sbr8d = cat(_T_1383, _T_1379) @[Cat.scala 29:58]
+    node _T_1384 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 148:28]
+    node _T_1385 = bits(io.din, 12, 10) @[ifu_compress_ctl.scala 148:39]
+    node _T_1386 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 148:54]
+    node _T_1387 = cat(_T_1386, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_1388 = cat(_T_1384, _T_1385) @[Cat.scala 29:58]
+    node uswimm6d = cat(_T_1388, _T_1387) @[Cat.scala 29:58]
+    node _T_1389 = bits(io.din, 8, 7) @[ifu_compress_ctl.scala 149:30]
+    node _T_1390 = bits(io.din, 12, 9) @[ifu_compress_ctl.scala 149:42]
+    node _T_1391 = cat(_T_1389, _T_1390) @[Cat.scala 29:58]
+    node uswspimm7d = cat(_T_1391, UInt<2>("h00")) @[Cat.scala 29:58]
+    node _T_1392 = bits(l2, 31, 25) @[ifu_compress_ctl.scala 151:17]
+    node _T_1393 = bits(sbroffset8_1, 0, 0) @[ifu_compress_ctl.scala 151:50]
+    node _T_1394 = bits(sbr8d, 8, 8) @[ifu_compress_ctl.scala 151:74]
+    wire _T_1395 : UInt<1>[4] @[lib.scala 12:48]
+    _T_1395[0] <= _T_1394 @[lib.scala 12:48]
+    _T_1395[1] <= _T_1394 @[lib.scala 12:48]
+    _T_1395[2] <= _T_1394 @[lib.scala 12:48]
+    _T_1395[3] <= _T_1394 @[lib.scala 12:48]
+    node _T_1396 = cat(_T_1395[0], _T_1395[1]) @[Cat.scala 29:58]
+    node _T_1397 = cat(_T_1396, _T_1395[2]) @[Cat.scala 29:58]
+    node _T_1398 = cat(_T_1397, _T_1395[3]) @[Cat.scala 29:58]
+    node _T_1399 = bits(sbr8d, 7, 5) @[ifu_compress_ctl.scala 151:84]
+    node _T_1400 = cat(_T_1398, _T_1399) @[Cat.scala 29:58]
+    node _T_1401 = bits(uswimm6_2, 0, 0) @[ifu_compress_ctl.scala 152:15]
+    node _T_1402 = bits(uswimm6d, 6, 5) @[ifu_compress_ctl.scala 152:44]
+    node _T_1403 = cat(UInt<5>("h00"), _T_1402) @[Cat.scala 29:58]
+    node _T_1404 = bits(uswspimm7_2, 0, 0) @[ifu_compress_ctl.scala 152:64]
+    node _T_1405 = bits(uswspimm7d, 7, 5) @[ifu_compress_ctl.scala 152:95]
+    node _T_1406 = cat(UInt<4>("h00"), _T_1405) @[Cat.scala 29:58]
+    node _T_1407 = mux(_T_1393, _T_1400, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1408 = mux(_T_1401, _T_1403, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1409 = mux(_T_1404, _T_1406, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1410 = or(_T_1407, _T_1408) @[Mux.scala 27:72]
+    node _T_1411 = or(_T_1410, _T_1409) @[Mux.scala 27:72]
+    wire _T_1412 : UInt<7> @[Mux.scala 27:72]
+    _T_1412 <= _T_1411 @[Mux.scala 27:72]
+    node l3_31 = or(_T_1392, _T_1412) @[ifu_compress_ctl.scala 151:25]
+    node l3_24 = bits(l2, 24, 12) @[ifu_compress_ctl.scala 154:17]
+    node _T_1413 = bits(l2, 11, 7) @[ifu_compress_ctl.scala 156:17]
+    node _T_1414 = bits(sbroffset8_1, 0, 0) @[ifu_compress_ctl.scala 156:49]
+    node _T_1415 = bits(sbr8d, 4, 1) @[ifu_compress_ctl.scala 156:66]
+    node _T_1416 = bits(sbr8d, 8, 8) @[ifu_compress_ctl.scala 156:78]
+    node _T_1417 = cat(_T_1415, _T_1416) @[Cat.scala 29:58]
+    node _T_1418 = bits(uswimm6_2, 0, 0) @[ifu_compress_ctl.scala 157:15]
+    node _T_1419 = bits(uswimm6d, 4, 0) @[ifu_compress_ctl.scala 157:31]
+    node _T_1420 = bits(uswspimm7_2, 0, 0) @[ifu_compress_ctl.scala 158:17]
+    node _T_1421 = bits(uswspimm7d, 4, 0) @[ifu_compress_ctl.scala 158:35]
+    node _T_1422 = mux(_T_1414, _T_1417, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1423 = mux(_T_1418, _T_1419, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1424 = mux(_T_1420, _T_1421, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_1425 = or(_T_1422, _T_1423) @[Mux.scala 27:72]
+    node _T_1426 = or(_T_1425, _T_1424) @[Mux.scala 27:72]
+    wire _T_1427 : UInt<5> @[Mux.scala 27:72]
+    _T_1427 <= _T_1426 @[Mux.scala 27:72]
+    node l3_11 = or(_T_1413, _T_1427) @[ifu_compress_ctl.scala 156:24]
+    node _T_1428 = bits(l2, 6, 0) @[ifu_compress_ctl.scala 160:39]
+    node _T_1429 = cat(l3_11, _T_1428) @[Cat.scala 29:58]
+    node _T_1430 = cat(l3_31, l3_24) @[Cat.scala 29:58]
+    node l3 = cat(_T_1430, _T_1429) @[Cat.scala 29:58]
+    node _T_1431 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1432 = eq(_T_1431, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1433 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1434 = eq(_T_1433, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1435 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_1436 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1437 = and(_T_1432, _T_1434) @[ifu_compress_ctl.scala 12:110]
+    node _T_1438 = and(_T_1437, _T_1435) @[ifu_compress_ctl.scala 12:110]
+    node _T_1439 = and(_T_1438, _T_1436) @[ifu_compress_ctl.scala 12:110]
+    node _T_1440 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 162:48]
+    node _T_1441 = eq(_T_1440, UInt<1>("h00")) @[ifu_compress_ctl.scala 162:41]
+    node _T_1442 = and(_T_1439, _T_1441) @[ifu_compress_ctl.scala 162:39]
+    node _T_1443 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1444 = eq(_T_1443, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1445 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1446 = eq(_T_1445, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1447 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_1448 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1449 = and(_T_1444, _T_1446) @[ifu_compress_ctl.scala 12:110]
+    node _T_1450 = and(_T_1449, _T_1447) @[ifu_compress_ctl.scala 12:110]
+    node _T_1451 = and(_T_1450, _T_1448) @[ifu_compress_ctl.scala 12:110]
+    node _T_1452 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 162:88]
+    node _T_1453 = eq(_T_1452, UInt<1>("h00")) @[ifu_compress_ctl.scala 162:81]
+    node _T_1454 = and(_T_1451, _T_1453) @[ifu_compress_ctl.scala 162:79]
+    node _T_1455 = or(_T_1442, _T_1454) @[ifu_compress_ctl.scala 162:54]
+    node _T_1456 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1457 = eq(_T_1456, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1458 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1459 = eq(_T_1458, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1460 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_1461 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1462 = eq(_T_1461, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1463 = and(_T_1457, _T_1459) @[ifu_compress_ctl.scala 12:110]
+    node _T_1464 = and(_T_1463, _T_1460) @[ifu_compress_ctl.scala 12:110]
+    node _T_1465 = and(_T_1464, _T_1462) @[ifu_compress_ctl.scala 12:110]
+    node _T_1466 = or(_T_1455, _T_1465) @[ifu_compress_ctl.scala 162:94]
+    node _T_1467 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1468 = eq(_T_1467, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1469 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1470 = eq(_T_1469, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1471 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_1472 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1473 = and(_T_1468, _T_1470) @[ifu_compress_ctl.scala 12:110]
+    node _T_1474 = and(_T_1473, _T_1471) @[ifu_compress_ctl.scala 12:110]
+    node _T_1475 = and(_T_1474, _T_1472) @[ifu_compress_ctl.scala 12:110]
+    node _T_1476 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 163:64]
+    node _T_1477 = eq(_T_1476, UInt<1>("h00")) @[ifu_compress_ctl.scala 163:57]
+    node _T_1478 = and(_T_1475, _T_1477) @[ifu_compress_ctl.scala 163:55]
+    node _T_1479 = or(_T_1466, _T_1478) @[ifu_compress_ctl.scala 163:30]
+    node _T_1480 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1481 = eq(_T_1480, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1482 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1483 = eq(_T_1482, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1484 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_1485 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1486 = and(_T_1481, _T_1483) @[ifu_compress_ctl.scala 12:110]
+    node _T_1487 = and(_T_1486, _T_1484) @[ifu_compress_ctl.scala 12:110]
+    node _T_1488 = and(_T_1487, _T_1485) @[ifu_compress_ctl.scala 12:110]
+    node _T_1489 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 163:105]
+    node _T_1490 = eq(_T_1489, UInt<1>("h00")) @[ifu_compress_ctl.scala 163:98]
+    node _T_1491 = and(_T_1488, _T_1490) @[ifu_compress_ctl.scala 163:96]
+    node _T_1492 = or(_T_1479, _T_1491) @[ifu_compress_ctl.scala 163:70]
+    node _T_1493 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1494 = eq(_T_1493, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1495 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1496 = eq(_T_1495, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1497 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_1498 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1499 = eq(_T_1498, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1500 = and(_T_1494, _T_1496) @[ifu_compress_ctl.scala 12:110]
+    node _T_1501 = and(_T_1500, _T_1497) @[ifu_compress_ctl.scala 12:110]
+    node _T_1502 = and(_T_1501, _T_1499) @[ifu_compress_ctl.scala 12:110]
+    node _T_1503 = or(_T_1492, _T_1502) @[ifu_compress_ctl.scala 163:111]
+    node _T_1504 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1505 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1506 = eq(_T_1505, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1507 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1508 = eq(_T_1507, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1509 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1510 = and(_T_1504, _T_1506) @[ifu_compress_ctl.scala 12:110]
+    node _T_1511 = and(_T_1510, _T_1508) @[ifu_compress_ctl.scala 12:110]
+    node _T_1512 = and(_T_1511, _T_1509) @[ifu_compress_ctl.scala 12:110]
+    node _T_1513 = or(_T_1503, _T_1512) @[ifu_compress_ctl.scala 164:29]
+    node _T_1514 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1515 = eq(_T_1514, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1516 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1517 = eq(_T_1516, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1518 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_1519 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1520 = and(_T_1515, _T_1517) @[ifu_compress_ctl.scala 12:110]
+    node _T_1521 = and(_T_1520, _T_1518) @[ifu_compress_ctl.scala 12:110]
+    node _T_1522 = and(_T_1521, _T_1519) @[ifu_compress_ctl.scala 12:110]
+    node _T_1523 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 164:88]
+    node _T_1524 = eq(_T_1523, UInt<1>("h00")) @[ifu_compress_ctl.scala 164:81]
+    node _T_1525 = and(_T_1522, _T_1524) @[ifu_compress_ctl.scala 164:79]
+    node _T_1526 = or(_T_1513, _T_1525) @[ifu_compress_ctl.scala 164:54]
+    node _T_1527 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1528 = eq(_T_1527, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1529 = bits(io.din, 6, 6) @[ifu_compress_ctl.scala 12:71]
+    node _T_1530 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1531 = eq(_T_1530, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1532 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1533 = and(_T_1528, _T_1529) @[ifu_compress_ctl.scala 12:110]
+    node _T_1534 = and(_T_1533, _T_1531) @[ifu_compress_ctl.scala 12:110]
+    node _T_1535 = and(_T_1534, _T_1532) @[ifu_compress_ctl.scala 12:110]
+    node _T_1536 = or(_T_1526, _T_1535) @[ifu_compress_ctl.scala 164:94]
+    node _T_1537 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1538 = eq(_T_1537, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1539 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1540 = eq(_T_1539, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1541 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_1542 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1543 = eq(_T_1542, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1544 = and(_T_1538, _T_1540) @[ifu_compress_ctl.scala 12:110]
+    node _T_1545 = and(_T_1544, _T_1541) @[ifu_compress_ctl.scala 12:110]
+    node _T_1546 = and(_T_1545, _T_1543) @[ifu_compress_ctl.scala 12:110]
+    node _T_1547 = or(_T_1536, _T_1546) @[ifu_compress_ctl.scala 164:118]
+    node _T_1548 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1549 = eq(_T_1548, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1550 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1551 = eq(_T_1550, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1552 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_1553 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1554 = and(_T_1549, _T_1551) @[ifu_compress_ctl.scala 12:110]
+    node _T_1555 = and(_T_1554, _T_1552) @[ifu_compress_ctl.scala 12:110]
+    node _T_1556 = and(_T_1555, _T_1553) @[ifu_compress_ctl.scala 12:110]
+    node _T_1557 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 165:37]
+    node _T_1558 = eq(_T_1557, UInt<1>("h00")) @[ifu_compress_ctl.scala 165:30]
+    node _T_1559 = and(_T_1556, _T_1558) @[ifu_compress_ctl.scala 165:28]
+    node _T_1560 = or(_T_1547, _T_1559) @[ifu_compress_ctl.scala 164:144]
+    node _T_1561 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1562 = eq(_T_1561, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1563 = bits(io.din, 5, 5) @[ifu_compress_ctl.scala 12:71]
+    node _T_1564 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1565 = eq(_T_1564, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1566 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1567 = and(_T_1562, _T_1563) @[ifu_compress_ctl.scala 12:110]
+    node _T_1568 = and(_T_1567, _T_1565) @[ifu_compress_ctl.scala 12:110]
+    node _T_1569 = and(_T_1568, _T_1566) @[ifu_compress_ctl.scala 12:110]
+    node _T_1570 = or(_T_1560, _T_1569) @[ifu_compress_ctl.scala 165:43]
+    node _T_1571 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1572 = eq(_T_1571, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1573 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1574 = eq(_T_1573, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1575 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:71]
+    node _T_1576 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1577 = eq(_T_1576, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1578 = and(_T_1572, _T_1574) @[ifu_compress_ctl.scala 12:110]
+    node _T_1579 = and(_T_1578, _T_1575) @[ifu_compress_ctl.scala 12:110]
+    node _T_1580 = and(_T_1579, _T_1577) @[ifu_compress_ctl.scala 12:110]
+    node _T_1581 = or(_T_1570, _T_1580) @[ifu_compress_ctl.scala 165:67]
+    node _T_1582 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1583 = eq(_T_1582, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1584 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1585 = eq(_T_1584, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1586 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_1587 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1588 = and(_T_1583, _T_1585) @[ifu_compress_ctl.scala 12:110]
+    node _T_1589 = and(_T_1588, _T_1586) @[ifu_compress_ctl.scala 12:110]
+    node _T_1590 = and(_T_1589, _T_1587) @[ifu_compress_ctl.scala 12:110]
+    node _T_1591 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 166:37]
+    node _T_1592 = eq(_T_1591, UInt<1>("h00")) @[ifu_compress_ctl.scala 166:30]
+    node _T_1593 = and(_T_1590, _T_1592) @[ifu_compress_ctl.scala 166:28]
+    node _T_1594 = or(_T_1581, _T_1593) @[ifu_compress_ctl.scala 165:94]
+    node _T_1595 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_1596 = bits(io.din, 11, 11) @[ifu_compress_ctl.scala 12:71]
+    node _T_1597 = bits(io.din, 10, 10) @[ifu_compress_ctl.scala 12:90]
+    node _T_1598 = eq(_T_1597, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1599 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1600 = eq(_T_1599, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1601 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1602 = and(_T_1595, _T_1596) @[ifu_compress_ctl.scala 12:110]
+    node _T_1603 = and(_T_1602, _T_1598) @[ifu_compress_ctl.scala 12:110]
+    node _T_1604 = and(_T_1603, _T_1600) @[ifu_compress_ctl.scala 12:110]
+    node _T_1605 = and(_T_1604, _T_1601) @[ifu_compress_ctl.scala 12:110]
+    node _T_1606 = or(_T_1594, _T_1605) @[ifu_compress_ctl.scala 166:43]
+    node _T_1607 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1608 = eq(_T_1607, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1609 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1610 = eq(_T_1609, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1611 = bits(io.din, 9, 9) @[ifu_compress_ctl.scala 12:71]
+    node _T_1612 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1613 = eq(_T_1612, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1614 = and(_T_1608, _T_1610) @[ifu_compress_ctl.scala 12:110]
+    node _T_1615 = and(_T_1614, _T_1611) @[ifu_compress_ctl.scala 12:110]
+    node _T_1616 = and(_T_1615, _T_1613) @[ifu_compress_ctl.scala 12:110]
+    node _T_1617 = or(_T_1606, _T_1616) @[ifu_compress_ctl.scala 166:71]
+    node _T_1618 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1619 = eq(_T_1618, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1620 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1621 = eq(_T_1620, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1622 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_1623 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1624 = and(_T_1619, _T_1621) @[ifu_compress_ctl.scala 12:110]
+    node _T_1625 = and(_T_1624, _T_1622) @[ifu_compress_ctl.scala 12:110]
+    node _T_1626 = and(_T_1625, _T_1623) @[ifu_compress_ctl.scala 12:110]
+    node _T_1627 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 167:37]
+    node _T_1628 = eq(_T_1627, UInt<1>("h00")) @[ifu_compress_ctl.scala 167:30]
+    node _T_1629 = and(_T_1626, _T_1628) @[ifu_compress_ctl.scala 167:28]
+    node _T_1630 = or(_T_1617, _T_1629) @[ifu_compress_ctl.scala 166:97]
+    node _T_1631 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1632 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_1633 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1634 = eq(_T_1633, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1635 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1636 = and(_T_1631, _T_1632) @[ifu_compress_ctl.scala 12:110]
+    node _T_1637 = and(_T_1636, _T_1634) @[ifu_compress_ctl.scala 12:110]
+    node _T_1638 = and(_T_1637, _T_1635) @[ifu_compress_ctl.scala 12:110]
+    node _T_1639 = or(_T_1630, _T_1638) @[ifu_compress_ctl.scala 167:43]
+    node _T_1640 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1641 = eq(_T_1640, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1642 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1643 = eq(_T_1642, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1644 = bits(io.din, 8, 8) @[ifu_compress_ctl.scala 12:71]
+    node _T_1645 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1646 = eq(_T_1645, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1647 = and(_T_1641, _T_1643) @[ifu_compress_ctl.scala 12:110]
+    node _T_1648 = and(_T_1647, _T_1644) @[ifu_compress_ctl.scala 12:110]
+    node _T_1649 = and(_T_1648, _T_1646) @[ifu_compress_ctl.scala 12:110]
+    node _T_1650 = or(_T_1639, _T_1649) @[ifu_compress_ctl.scala 167:67]
+    node _T_1651 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1652 = eq(_T_1651, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1653 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1654 = eq(_T_1653, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1655 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_1656 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1657 = and(_T_1652, _T_1654) @[ifu_compress_ctl.scala 12:110]
+    node _T_1658 = and(_T_1657, _T_1655) @[ifu_compress_ctl.scala 12:110]
+    node _T_1659 = and(_T_1658, _T_1656) @[ifu_compress_ctl.scala 12:110]
+    node _T_1660 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 168:37]
+    node _T_1661 = eq(_T_1660, UInt<1>("h00")) @[ifu_compress_ctl.scala 168:30]
+    node _T_1662 = and(_T_1659, _T_1661) @[ifu_compress_ctl.scala 168:28]
+    node _T_1663 = or(_T_1650, _T_1662) @[ifu_compress_ctl.scala 167:93]
+    node _T_1664 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1665 = bits(io.din, 4, 4) @[ifu_compress_ctl.scala 12:71]
+    node _T_1666 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1667 = eq(_T_1666, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1668 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1669 = and(_T_1664, _T_1665) @[ifu_compress_ctl.scala 12:110]
+    node _T_1670 = and(_T_1669, _T_1667) @[ifu_compress_ctl.scala 12:110]
+    node _T_1671 = and(_T_1670, _T_1668) @[ifu_compress_ctl.scala 12:110]
+    node _T_1672 = or(_T_1663, _T_1671) @[ifu_compress_ctl.scala 168:43]
+    node _T_1673 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1674 = eq(_T_1673, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1675 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1676 = eq(_T_1675, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1677 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_1678 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1679 = and(_T_1674, _T_1676) @[ifu_compress_ctl.scala 12:110]
+    node _T_1680 = and(_T_1679, _T_1677) @[ifu_compress_ctl.scala 12:110]
+    node _T_1681 = and(_T_1680, _T_1678) @[ifu_compress_ctl.scala 12:110]
+    node _T_1682 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 168:100]
+    node _T_1683 = eq(_T_1682, UInt<1>("h00")) @[ifu_compress_ctl.scala 168:93]
+    node _T_1684 = and(_T_1681, _T_1683) @[ifu_compress_ctl.scala 168:91]
+    node _T_1685 = or(_T_1672, _T_1684) @[ifu_compress_ctl.scala 168:66]
+    node _T_1686 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1687 = eq(_T_1686, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1688 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1689 = eq(_T_1688, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1690 = bits(io.din, 7, 7) @[ifu_compress_ctl.scala 12:71]
+    node _T_1691 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1692 = eq(_T_1691, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1693 = and(_T_1687, _T_1689) @[ifu_compress_ctl.scala 12:110]
+    node _T_1694 = and(_T_1693, _T_1690) @[ifu_compress_ctl.scala 12:110]
+    node _T_1695 = and(_T_1694, _T_1692) @[ifu_compress_ctl.scala 12:110]
+    node _T_1696 = or(_T_1685, _T_1695) @[ifu_compress_ctl.scala 168:106]
+    node _T_1697 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1698 = bits(io.din, 3, 3) @[ifu_compress_ctl.scala 12:71]
+    node _T_1699 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1700 = eq(_T_1699, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1701 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1702 = and(_T_1697, _T_1698) @[ifu_compress_ctl.scala 12:110]
+    node _T_1703 = and(_T_1702, _T_1700) @[ifu_compress_ctl.scala 12:110]
+    node _T_1704 = and(_T_1703, _T_1701) @[ifu_compress_ctl.scala 12:110]
+    node _T_1705 = or(_T_1696, _T_1704) @[ifu_compress_ctl.scala 169:29]
+    node _T_1706 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:71]
+    node _T_1707 = bits(io.din, 2, 2) @[ifu_compress_ctl.scala 12:71]
+    node _T_1708 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1709 = eq(_T_1708, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1710 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1711 = and(_T_1706, _T_1707) @[ifu_compress_ctl.scala 12:110]
+    node _T_1712 = and(_T_1711, _T_1709) @[ifu_compress_ctl.scala 12:110]
+    node _T_1713 = and(_T_1712, _T_1710) @[ifu_compress_ctl.scala 12:110]
+    node _T_1714 = or(_T_1705, _T_1713) @[ifu_compress_ctl.scala 169:52]
+    node _T_1715 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1716 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1717 = eq(_T_1716, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1718 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1719 = eq(_T_1718, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1720 = and(_T_1715, _T_1717) @[ifu_compress_ctl.scala 12:110]
+    node _T_1721 = and(_T_1720, _T_1719) @[ifu_compress_ctl.scala 12:110]
+    node _T_1722 = or(_T_1714, _T_1721) @[ifu_compress_ctl.scala 169:75]
+    node _T_1723 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:90]
+    node _T_1724 = eq(_T_1723, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1725 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1726 = eq(_T_1725, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1727 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1728 = eq(_T_1727, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1729 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 12:71]
+    node _T_1730 = and(_T_1724, _T_1726) @[ifu_compress_ctl.scala 12:110]
+    node _T_1731 = and(_T_1730, _T_1728) @[ifu_compress_ctl.scala 12:110]
+    node _T_1732 = and(_T_1731, _T_1729) @[ifu_compress_ctl.scala 12:110]
+    node _T_1733 = or(_T_1722, _T_1732) @[ifu_compress_ctl.scala 169:98]
+    node _T_1734 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:71]
+    node _T_1735 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1736 = eq(_T_1735, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1737 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_1738 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1739 = and(_T_1734, _T_1736) @[ifu_compress_ctl.scala 12:110]
+    node _T_1740 = and(_T_1739, _T_1737) @[ifu_compress_ctl.scala 12:110]
+    node _T_1741 = and(_T_1740, _T_1738) @[ifu_compress_ctl.scala 12:110]
+    node _T_1742 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 170:63]
+    node _T_1743 = eq(_T_1742, UInt<1>("h00")) @[ifu_compress_ctl.scala 170:56]
+    node _T_1744 = and(_T_1741, _T_1743) @[ifu_compress_ctl.scala 170:54]
+    node _T_1745 = or(_T_1733, _T_1744) @[ifu_compress_ctl.scala 170:29]
+    node _T_1746 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1747 = eq(_T_1746, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1748 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1749 = eq(_T_1748, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1750 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:90]
+    node _T_1751 = eq(_T_1750, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1752 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:71]
+    node _T_1753 = and(_T_1747, _T_1749) @[ifu_compress_ctl.scala 12:110]
+    node _T_1754 = and(_T_1753, _T_1751) @[ifu_compress_ctl.scala 12:110]
+    node _T_1755 = and(_T_1754, _T_1752) @[ifu_compress_ctl.scala 12:110]
+    node _T_1756 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 170:105]
+    node _T_1757 = eq(_T_1756, UInt<1>("h00")) @[ifu_compress_ctl.scala 170:98]
+    node _T_1758 = and(_T_1755, _T_1757) @[ifu_compress_ctl.scala 170:96]
+    node _T_1759 = or(_T_1745, _T_1758) @[ifu_compress_ctl.scala 170:69]
+    node _T_1760 = bits(io.din, 15, 15) @[ifu_compress_ctl.scala 12:90]
+    node _T_1761 = eq(_T_1760, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1762 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1763 = eq(_T_1762, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1764 = bits(io.din, 12, 12) @[ifu_compress_ctl.scala 12:71]
+    node _T_1765 = bits(io.din, 1, 1) @[ifu_compress_ctl.scala 12:90]
+    node _T_1766 = eq(_T_1765, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1767 = and(_T_1761, _T_1763) @[ifu_compress_ctl.scala 12:110]
+    node _T_1768 = and(_T_1767, _T_1764) @[ifu_compress_ctl.scala 12:110]
+    node _T_1769 = and(_T_1768, _T_1766) @[ifu_compress_ctl.scala 12:110]
+    node _T_1770 = or(_T_1759, _T_1769) @[ifu_compress_ctl.scala 170:111]
+    node _T_1771 = bits(io.din, 14, 14) @[ifu_compress_ctl.scala 12:71]
+    node _T_1772 = bits(io.din, 13, 13) @[ifu_compress_ctl.scala 12:90]
+    node _T_1773 = eq(_T_1772, UInt<1>("h00")) @[ifu_compress_ctl.scala 12:83]
+    node _T_1774 = and(_T_1771, _T_1773) @[ifu_compress_ctl.scala 12:110]
+    node _T_1775 = bits(io.din, 0, 0) @[ifu_compress_ctl.scala 171:59]
+    node _T_1776 = eq(_T_1775, UInt<1>("h00")) @[ifu_compress_ctl.scala 171:52]
+    node _T_1777 = and(_T_1774, _T_1776) @[ifu_compress_ctl.scala 171:50]
+    node legal = or(_T_1770, _T_1777) @[ifu_compress_ctl.scala 171:30]
+    wire _T_1778 : UInt<1>[32] @[lib.scala 12:48]
+    _T_1778[0] <= legal @[lib.scala 12:48]
+    _T_1778[1] <= legal @[lib.scala 12:48]
+    _T_1778[2] <= legal @[lib.scala 12:48]
+    _T_1778[3] <= legal @[lib.scala 12:48]
+    _T_1778[4] <= legal @[lib.scala 12:48]
+    _T_1778[5] <= legal @[lib.scala 12:48]
+    _T_1778[6] <= legal @[lib.scala 12:48]
+    _T_1778[7] <= legal @[lib.scala 12:48]
+    _T_1778[8] <= legal @[lib.scala 12:48]
+    _T_1778[9] <= legal @[lib.scala 12:48]
+    _T_1778[10] <= legal @[lib.scala 12:48]
+    _T_1778[11] <= legal @[lib.scala 12:48]
+    _T_1778[12] <= legal @[lib.scala 12:48]
+    _T_1778[13] <= legal @[lib.scala 12:48]
+    _T_1778[14] <= legal @[lib.scala 12:48]
+    _T_1778[15] <= legal @[lib.scala 12:48]
+    _T_1778[16] <= legal @[lib.scala 12:48]
+    _T_1778[17] <= legal @[lib.scala 12:48]
+    _T_1778[18] <= legal @[lib.scala 12:48]
+    _T_1778[19] <= legal @[lib.scala 12:48]
+    _T_1778[20] <= legal @[lib.scala 12:48]
+    _T_1778[21] <= legal @[lib.scala 12:48]
+    _T_1778[22] <= legal @[lib.scala 12:48]
+    _T_1778[23] <= legal @[lib.scala 12:48]
+    _T_1778[24] <= legal @[lib.scala 12:48]
+    _T_1778[25] <= legal @[lib.scala 12:48]
+    _T_1778[26] <= legal @[lib.scala 12:48]
+    _T_1778[27] <= legal @[lib.scala 12:48]
+    _T_1778[28] <= legal @[lib.scala 12:48]
+    _T_1778[29] <= legal @[lib.scala 12:48]
+    _T_1778[30] <= legal @[lib.scala 12:48]
+    _T_1778[31] <= legal @[lib.scala 12:48]
+    node _T_1779 = cat(_T_1778[0], _T_1778[1]) @[Cat.scala 29:58]
+    node _T_1780 = cat(_T_1779, _T_1778[2]) @[Cat.scala 29:58]
+    node _T_1781 = cat(_T_1780, _T_1778[3]) @[Cat.scala 29:58]
+    node _T_1782 = cat(_T_1781, _T_1778[4]) @[Cat.scala 29:58]
+    node _T_1783 = cat(_T_1782, _T_1778[5]) @[Cat.scala 29:58]
+    node _T_1784 = cat(_T_1783, _T_1778[6]) @[Cat.scala 29:58]
+    node _T_1785 = cat(_T_1784, _T_1778[7]) @[Cat.scala 29:58]
+    node _T_1786 = cat(_T_1785, _T_1778[8]) @[Cat.scala 29:58]
+    node _T_1787 = cat(_T_1786, _T_1778[9]) @[Cat.scala 29:58]
+    node _T_1788 = cat(_T_1787, _T_1778[10]) @[Cat.scala 29:58]
+    node _T_1789 = cat(_T_1788, _T_1778[11]) @[Cat.scala 29:58]
+    node _T_1790 = cat(_T_1789, _T_1778[12]) @[Cat.scala 29:58]
+    node _T_1791 = cat(_T_1790, _T_1778[13]) @[Cat.scala 29:58]
+    node _T_1792 = cat(_T_1791, _T_1778[14]) @[Cat.scala 29:58]
+    node _T_1793 = cat(_T_1792, _T_1778[15]) @[Cat.scala 29:58]
+    node _T_1794 = cat(_T_1793, _T_1778[16]) @[Cat.scala 29:58]
+    node _T_1795 = cat(_T_1794, _T_1778[17]) @[Cat.scala 29:58]
+    node _T_1796 = cat(_T_1795, _T_1778[18]) @[Cat.scala 29:58]
+    node _T_1797 = cat(_T_1796, _T_1778[19]) @[Cat.scala 29:58]
+    node _T_1798 = cat(_T_1797, _T_1778[20]) @[Cat.scala 29:58]
+    node _T_1799 = cat(_T_1798, _T_1778[21]) @[Cat.scala 29:58]
+    node _T_1800 = cat(_T_1799, _T_1778[22]) @[Cat.scala 29:58]
+    node _T_1801 = cat(_T_1800, _T_1778[23]) @[Cat.scala 29:58]
+    node _T_1802 = cat(_T_1801, _T_1778[24]) @[Cat.scala 29:58]
+    node _T_1803 = cat(_T_1802, _T_1778[25]) @[Cat.scala 29:58]
+    node _T_1804 = cat(_T_1803, _T_1778[26]) @[Cat.scala 29:58]
+    node _T_1805 = cat(_T_1804, _T_1778[27]) @[Cat.scala 29:58]
+    node _T_1806 = cat(_T_1805, _T_1778[28]) @[Cat.scala 29:58]
+    node _T_1807 = cat(_T_1806, _T_1778[29]) @[Cat.scala 29:58]
+    node _T_1808 = cat(_T_1807, _T_1778[30]) @[Cat.scala 29:58]
+    node _T_1809 = cat(_T_1808, _T_1778[31]) @[Cat.scala 29:58]
+    node _T_1810 = and(l3, _T_1809) @[ifu_compress_ctl.scala 173:16]
+    io.dout <= _T_1810 @[ifu_compress_ctl.scala 173:10]
+    
+  module ifu_aln_ctl : 
+    input clock : Clock
+    input reset : AsyncReset
+    output io : {flip scan_mode : UInt<1>, flip active_clk : Clock, flip ifu_async_error_start : UInt<1>, flip iccm_rd_ecc_double_err : UInt<1>, flip ic_access_fault_f : UInt<1>, flip ic_access_fault_type_f : UInt<2>, flip ifu_bp_fghr_f : UInt<8>, flip ifu_bp_btb_target_f : UInt<31>, flip ifu_bp_poffset_f : UInt<12>, flip ifu_bp_hist0_f : UInt<2>, flip ifu_bp_hist1_f : UInt<2>, flip ifu_bp_pc4_f : UInt<2>, flip ifu_bp_way_f : UInt<2>, flip ifu_bp_valid_f : UInt<2>, flip ifu_bp_ret_f : UInt<2>, flip exu_flush_final : UInt<1>, flip dec_i0_decode_d : UInt<1>, dec_aln : {aln_dec : {ifu_i0_cinst : UInt<16>}, aln_ib : {ifu_i0_icaf : UInt<1>, ifu_i0_icaf_type : UInt<2>, ifu_i0_icaf_second : UInt<1>, ifu_i0_dbecc : UInt<1>, ifu_i0_bp_index : UInt<8>, ifu_i0_bp_fghr : UInt<8>, ifu_i0_bp_btag : UInt<5>, ifu_i0_valid : UInt<1>, ifu_i0_instr : UInt<32>, ifu_i0_pc : UInt<31>, ifu_i0_pc4 : UInt<1>, i0_brp : {valid : UInt<1>, bits : {toffset : UInt<12>, hist : UInt<2>, br_error : UInt<1>, br_start_error : UInt<1>, bank : UInt<1>, prett : UInt<31>, way : UInt<1>, ret : UInt<1>}}}, ifu_pmu_instr_aligned : UInt<1>}, flip ifu_fetch_data_f : UInt<32>, flip ifu_fetch_val : UInt<2>, flip ifu_fetch_pc : UInt<31>, ifu_fb_consume1 : UInt<1>, ifu_fb_consume2 : UInt<1>}
+    
+    wire error_stall_in : UInt<1>
+    error_stall_in <= UInt<1>("h00")
+    wire alignval : UInt<2>
+    alignval <= UInt<1>("h00")
+    wire q0final : UInt<32>
+    q0final <= UInt<1>("h00")
+    wire q1final : UInt<16>
+    q1final <= UInt<1>("h00")
+    wire wrptr_in : UInt<2>
+    wrptr_in <= UInt<1>("h00")
+    wire rdptr_in : UInt<2>
+    rdptr_in <= UInt<1>("h00")
+    wire f2val_in : UInt<2>
+    f2val_in <= UInt<1>("h00")
+    wire f1val_in : UInt<2>
+    f1val_in <= UInt<1>("h00")
+    wire f0val_in : UInt<2>
+    f0val_in <= UInt<1>("h00")
+    wire q2off_in : UInt<1>
+    q2off_in <= UInt<1>("h00")
+    wire q1off_in : UInt<1>
+    q1off_in <= UInt<1>("h00")
+    wire q0off_in : UInt<1>
+    q0off_in <= UInt<1>("h00")
+    wire sf0_valid : UInt<1>
+    sf0_valid <= UInt<1>("h00")
+    wire sf1_valid : UInt<1>
+    sf1_valid <= UInt<1>("h00")
+    wire f2_valid : UInt<1>
+    f2_valid <= UInt<1>("h00")
+    wire ifvalid : UInt<1>
+    ifvalid <= UInt<1>("h00")
+    wire shift_f2_f1 : UInt<1>
+    shift_f2_f1 <= UInt<1>("h00")
+    wire shift_f2_f0 : UInt<1>
+    shift_f2_f0 <= UInt<1>("h00")
+    wire shift_f1_f0 : UInt<1>
+    shift_f1_f0 <= UInt<1>("h00")
+    wire f0icaf : UInt<1>
+    f0icaf <= UInt<1>("h00")
+    wire f1icaf : UInt<1>
+    f1icaf <= UInt<1>("h00")
+    wire sf0val : UInt<2>
+    sf0val <= UInt<1>("h00")
+    wire sf1val : UInt<2>
+    sf1val <= UInt<1>("h00")
+    wire misc0 : UInt<55>
+    misc0 <= UInt<1>("h00")
+    wire misc1 : UInt<55>
+    misc1 <= UInt<1>("h00")
+    wire misc2 : UInt<55>
+    misc2 <= UInt<1>("h00")
+    wire brdata1 : UInt<12>
+    brdata1 <= UInt<1>("h00")
+    wire brdata0 : UInt<12>
+    brdata0 <= UInt<1>("h00")
+    wire brdata2 : UInt<12>
+    brdata2 <= UInt<1>("h00")
+    wire q0 : UInt<32>
+    q0 <= UInt<1>("h00")
+    wire q1 : UInt<32>
+    q1 <= UInt<1>("h00")
+    wire q2 : UInt<32>
+    q2 <= UInt<1>("h00")
+    wire f1pc_in : UInt<31>
+    f1pc_in <= UInt<1>("h00")
+    wire f0pc_in : UInt<31>
+    f0pc_in <= UInt<1>("h00")
+    wire error_stall : UInt<1>
+    error_stall <= UInt<1>("h00")
+    wire f2_wr_en : UInt<1>
+    f2_wr_en <= UInt<1>("h00")
+    wire shift_4B : UInt<1>
+    shift_4B <= UInt<1>("h00")
+    wire f1_shift_wr_en : UInt<1>
+    f1_shift_wr_en <= UInt<1>("h00")
+    wire f0_shift_wr_en : UInt<1>
+    f0_shift_wr_en <= UInt<1>("h00")
+    wire qwen : UInt<3>
+    qwen <= UInt<1>("h00")
+    wire brdata_in : UInt<12>
+    brdata_in <= UInt<1>("h00")
+    wire misc_data_in : UInt<55>
+    misc_data_in <= UInt<1>("h00")
+    wire fetch_to_f0 : UInt<1>
+    fetch_to_f0 <= UInt<1>("h00")
+    wire fetch_to_f1 : UInt<1>
+    fetch_to_f1 <= UInt<1>("h00")
+    wire fetch_to_f2 : UInt<1>
+    fetch_to_f2 <= UInt<1>("h00")
+    wire f1_shift_2B : UInt<1>
+    f1_shift_2B <= UInt<1>("h00")
+    wire first4B : UInt<1>
+    first4B <= UInt<1>("h00")
+    wire shift_2B : UInt<1>
+    shift_2B <= UInt<1>("h00")
+    wire f0_shift_2B : UInt<1>
+    f0_shift_2B <= UInt<1>("h00")
+    node _T = or(error_stall, io.ifu_async_error_start) @[ifu_aln_ctl.scala 100:34]
+    node _T_1 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 100:64]
+    node _T_2 = and(_T, _T_1) @[ifu_aln_ctl.scala 100:62]
+    error_stall_in <= _T_2 @[ifu_aln_ctl.scala 100:18]
+    reg _T_3 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 103:51]
+    _T_3 <= error_stall_in @[ifu_aln_ctl.scala 103:51]
+    error_stall <= _T_3 @[ifu_aln_ctl.scala 103:15]
+    reg wrptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 105:48]
+    wrptr <= wrptr_in @[ifu_aln_ctl.scala 105:48]
+    reg rdptr : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 107:48]
+    rdptr <= rdptr_in @[ifu_aln_ctl.scala 107:48]
+    reg f2val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 109:48]
+    f2val <= f2val_in @[ifu_aln_ctl.scala 109:48]
+    reg f1val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 110:48]
+    f1val <= f1val_in @[ifu_aln_ctl.scala 110:48]
+    reg f0val : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 111:48]
+    f0val <= f0val_in @[ifu_aln_ctl.scala 111:48]
+    reg q2off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 113:48]
+    q2off <= q2off_in @[ifu_aln_ctl.scala 113:48]
+    reg q1off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 114:48]
+    q1off <= q1off_in @[ifu_aln_ctl.scala 114:48]
+    reg q0off : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[ifu_aln_ctl.scala 115:48]
+    q0off <= q0off_in @[ifu_aln_ctl.scala 115:48]
+    node _T_4 = bits(f2_wr_en, 0, 0) @[ifu_aln_ctl.scala 117:47]
+    inst rvclkhdr of rvclkhdr @[lib.scala 404:23]
+    rvclkhdr.clock <= clock
+    rvclkhdr.reset <= reset
+    rvclkhdr.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr.io.en <= _T_4 @[lib.scala 407:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg f2pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_4 : @[Reg.scala 28:19]
+      f2pc <= io.ifu_fetch_pc @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_5 = bits(f1_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 118:45]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
+    rvclkhdr_1.clock <= clock
+    rvclkhdr_1.reset <= reset
+    rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_1.io.en <= _T_5 @[lib.scala 407:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg f1pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_5 : @[Reg.scala 28:19]
+      f1pc <= f1pc_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_6 = bits(f0_shift_wr_en, 0, 0) @[ifu_aln_ctl.scala 119:45]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_2.io.en <= _T_6 @[lib.scala 407:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg f0pc : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_6 : @[Reg.scala 28:19]
+      f0pc <= f0pc_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    node _T_7 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 121:36]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
+    rvclkhdr_3.clock <= clock
+    rvclkhdr_3.reset <= reset
+    rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_3.io.en <= _T_7 @[lib.scala 407:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_8 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_7 : @[Reg.scala 28:19]
+      _T_8 <= brdata_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    brdata2 <= _T_8 @[ifu_aln_ctl.scala 121:11]
+    node _T_9 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 122:36]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 404:23]
+    rvclkhdr_4.clock <= clock
+    rvclkhdr_4.reset <= reset
+    rvclkhdr_4.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_4.io.en <= _T_9 @[lib.scala 407:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_10 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_9 : @[Reg.scala 28:19]
+      _T_10 <= brdata_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    brdata1 <= _T_10 @[ifu_aln_ctl.scala 122:11]
+    node _T_11 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 123:36]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 404:23]
+    rvclkhdr_5.clock <= clock
+    rvclkhdr_5.reset <= reset
+    rvclkhdr_5.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_5.io.en <= _T_11 @[lib.scala 407:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_12 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_11 : @[Reg.scala 28:19]
+      _T_12 <= brdata_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    brdata0 <= _T_12 @[ifu_aln_ctl.scala 123:11]
+    node _T_13 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 125:37]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 404:23]
+    rvclkhdr_6.clock <= clock
+    rvclkhdr_6.reset <= reset
+    rvclkhdr_6.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_6.io.en <= _T_13 @[lib.scala 407:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_14 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_13 : @[Reg.scala 28:19]
+      _T_14 <= misc_data_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    misc2 <= _T_14 @[ifu_aln_ctl.scala 125:9]
+    node _T_15 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 126:37]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 404:23]
+    rvclkhdr_7.clock <= clock
+    rvclkhdr_7.reset <= reset
+    rvclkhdr_7.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_7.io.en <= _T_15 @[lib.scala 407:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_16 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_15 : @[Reg.scala 28:19]
+      _T_16 <= misc_data_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    misc1 <= _T_16 @[ifu_aln_ctl.scala 126:9]
+    node _T_17 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 127:37]
+    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 404:23]
+    rvclkhdr_8.clock <= clock
+    rvclkhdr_8.reset <= reset
+    rvclkhdr_8.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_8.io.en <= _T_17 @[lib.scala 407:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_18 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_17 : @[Reg.scala 28:19]
+      _T_18 <= misc_data_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    misc0 <= _T_18 @[ifu_aln_ctl.scala 127:9]
+    node _T_19 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 129:41]
+    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 404:23]
+    rvclkhdr_9.clock <= clock
+    rvclkhdr_9.reset <= reset
+    rvclkhdr_9.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_9.io.en <= _T_19 @[lib.scala 407:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_20 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_19 : @[Reg.scala 28:19]
+      _T_20 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    q2 <= _T_20 @[ifu_aln_ctl.scala 129:6]
+    node _T_21 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 130:41]
+    inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 404:23]
+    rvclkhdr_10.clock <= clock
+    rvclkhdr_10.reset <= reset
+    rvclkhdr_10.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_10.io.en <= _T_21 @[lib.scala 407:17]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_22 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_21 : @[Reg.scala 28:19]
+      _T_22 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    q1 <= _T_22 @[ifu_aln_ctl.scala 130:6]
+    node _T_23 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 131:41]
+    inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 404:23]
+    rvclkhdr_11.clock <= clock
+    rvclkhdr_11.reset <= reset
+    rvclkhdr_11.io.clk <= clock @[lib.scala 406:18]
+    rvclkhdr_11.io.en <= _T_23 @[lib.scala 407:17]
+    rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
+    reg _T_24 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when _T_23 : @[Reg.scala 28:19]
+      _T_24 <= io.ifu_fetch_data_f @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    q0 <= _T_24 @[ifu_aln_ctl.scala 131:6]
+    f2_wr_en <= fetch_to_f2 @[ifu_aln_ctl.scala 134:18]
+    node _T_25 = or(fetch_to_f1, shift_f2_f1) @[ifu_aln_ctl.scala 135:33]
+    node _T_26 = or(_T_25, f1_shift_2B) @[ifu_aln_ctl.scala 135:47]
+    f1_shift_wr_en <= _T_26 @[ifu_aln_ctl.scala 135:18]
+    node _T_27 = or(fetch_to_f0, shift_f2_f0) @[ifu_aln_ctl.scala 136:33]
+    node _T_28 = or(_T_27, shift_f1_f0) @[ifu_aln_ctl.scala 136:47]
+    node _T_29 = or(_T_28, shift_2B) @[ifu_aln_ctl.scala 136:61]
+    node _T_30 = or(_T_29, shift_4B) @[ifu_aln_ctl.scala 136:72]
+    f0_shift_wr_en <= _T_30 @[ifu_aln_ctl.scala 136:18]
+    node _T_31 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 138:24]
+    node _T_32 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 138:39]
+    node _T_33 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 138:54]
+    node _T_34 = cat(_T_31, _T_32) @[Cat.scala 29:58]
+    node qren = cat(_T_34, _T_33) @[Cat.scala 29:58]
+    node _T_35 = eq(wrptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 140:21]
+    node _T_36 = and(_T_35, ifvalid) @[ifu_aln_ctl.scala 140:29]
+    node _T_37 = eq(wrptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 140:46]
+    node _T_38 = and(_T_37, ifvalid) @[ifu_aln_ctl.scala 140:54]
+    node _T_39 = eq(wrptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 140:71]
+    node _T_40 = and(_T_39, ifvalid) @[ifu_aln_ctl.scala 140:79]
+    node _T_41 = cat(_T_36, _T_38) @[Cat.scala 29:58]
+    node _T_42 = cat(_T_41, _T_40) @[Cat.scala 29:58]
+    qwen <= _T_42 @[ifu_aln_ctl.scala 140:8]
+    node _T_43 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 144:30]
+    node _T_44 = and(_T_43, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 144:34]
+    node _T_45 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 144:57]
+    node _T_46 = and(_T_44, _T_45) @[ifu_aln_ctl.scala 144:55]
+    node _T_47 = bits(_T_46, 0, 0) @[ifu_aln_ctl.scala 144:78]
+    node _T_48 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 145:10]
+    node _T_49 = and(_T_48, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 145:14]
+    node _T_50 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 145:37]
+    node _T_51 = and(_T_49, _T_50) @[ifu_aln_ctl.scala 145:35]
+    node _T_52 = bits(_T_51, 0, 0) @[ifu_aln_ctl.scala 145:58]
+    node _T_53 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 146:10]
+    node _T_54 = and(_T_53, io.ifu_fb_consume1) @[ifu_aln_ctl.scala 146:14]
+    node _T_55 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 146:37]
+    node _T_56 = and(_T_54, _T_55) @[ifu_aln_ctl.scala 146:35]
+    node _T_57 = bits(_T_56, 0, 0) @[ifu_aln_ctl.scala 146:58]
+    node _T_58 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 147:10]
+    node _T_59 = and(_T_58, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 147:14]
+    node _T_60 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 147:37]
+    node _T_61 = and(_T_59, _T_60) @[ifu_aln_ctl.scala 147:35]
+    node _T_62 = bits(_T_61, 0, 0) @[ifu_aln_ctl.scala 147:58]
+    node _T_63 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 148:10]
+    node _T_64 = and(_T_63, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 148:14]
+    node _T_65 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 148:37]
+    node _T_66 = and(_T_64, _T_65) @[ifu_aln_ctl.scala 148:35]
+    node _T_67 = bits(_T_66, 0, 0) @[ifu_aln_ctl.scala 148:58]
+    node _T_68 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 149:10]
+    node _T_69 = and(_T_68, io.ifu_fb_consume2) @[ifu_aln_ctl.scala 149:14]
+    node _T_70 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 149:37]
+    node _T_71 = and(_T_69, _T_70) @[ifu_aln_ctl.scala 149:35]
+    node _T_72 = bits(_T_71, 0, 0) @[ifu_aln_ctl.scala 149:58]
+    node _T_73 = eq(io.ifu_fb_consume1, UInt<1>("h00")) @[ifu_aln_ctl.scala 150:6]
+    node _T_74 = eq(io.ifu_fb_consume2, UInt<1>("h00")) @[ifu_aln_ctl.scala 150:28]
+    node _T_75 = and(_T_73, _T_74) @[ifu_aln_ctl.scala 150:26]
+    node _T_76 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 150:50]
+    node _T_77 = and(_T_75, _T_76) @[ifu_aln_ctl.scala 150:48]
+    node _T_78 = bits(_T_77, 0, 0) @[ifu_aln_ctl.scala 150:71]
+    node _T_79 = mux(_T_47, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_80 = mux(_T_52, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_81 = mux(_T_57, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_82 = mux(_T_62, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_83 = mux(_T_67, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_84 = mux(_T_72, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_85 = mux(_T_78, rdptr, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_86 = or(_T_79, _T_80) @[Mux.scala 27:72]
+    node _T_87 = or(_T_86, _T_81) @[Mux.scala 27:72]
+    node _T_88 = or(_T_87, _T_82) @[Mux.scala 27:72]
+    node _T_89 = or(_T_88, _T_83) @[Mux.scala 27:72]
+    node _T_90 = or(_T_89, _T_84) @[Mux.scala 27:72]
+    node _T_91 = or(_T_90, _T_85) @[Mux.scala 27:72]
+    wire _T_92 : UInt @[Mux.scala 27:72]
+    _T_92 <= _T_91 @[Mux.scala 27:72]
+    rdptr_in <= _T_92 @[ifu_aln_ctl.scala 144:12]
+    node _T_93 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 153:30]
+    node _T_94 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 153:36]
+    node _T_95 = and(_T_93, _T_94) @[ifu_aln_ctl.scala 153:34]
+    node _T_96 = bits(_T_95, 0, 0) @[ifu_aln_ctl.scala 153:57]
+    node _T_97 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 154:10]
+    node _T_98 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 154:16]
+    node _T_99 = and(_T_97, _T_98) @[ifu_aln_ctl.scala 154:14]
+    node _T_100 = bits(_T_99, 0, 0) @[ifu_aln_ctl.scala 154:37]
+    node _T_101 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 155:10]
+    node _T_102 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 155:16]
+    node _T_103 = and(_T_101, _T_102) @[ifu_aln_ctl.scala 155:14]
+    node _T_104 = bits(_T_103, 0, 0) @[ifu_aln_ctl.scala 155:37]
+    node _T_105 = eq(ifvalid, UInt<1>("h00")) @[ifu_aln_ctl.scala 156:6]
+    node _T_106 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 156:17]
+    node _T_107 = and(_T_105, _T_106) @[ifu_aln_ctl.scala 156:15]
+    node _T_108 = bits(_T_107, 0, 0) @[ifu_aln_ctl.scala 156:38]
+    node _T_109 = mux(_T_96, UInt<1>("h01"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_110 = mux(_T_100, UInt<2>("h02"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_111 = mux(_T_104, UInt<1>("h00"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_112 = mux(_T_108, wrptr, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_113 = or(_T_109, _T_110) @[Mux.scala 27:72]
+    node _T_114 = or(_T_113, _T_111) @[Mux.scala 27:72]
+    node _T_115 = or(_T_114, _T_112) @[Mux.scala 27:72]
+    wire _T_116 : UInt @[Mux.scala 27:72]
+    _T_116 <= _T_115 @[Mux.scala 27:72]
+    wrptr_in <= _T_116 @[ifu_aln_ctl.scala 153:12]
+    node _T_117 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 158:31]
+    node _T_118 = eq(_T_117, UInt<1>("h00")) @[ifu_aln_ctl.scala 158:26]
+    node _T_119 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 158:43]
+    node _T_120 = and(_T_118, _T_119) @[ifu_aln_ctl.scala 158:35]
+    node _T_121 = bits(_T_120, 0, 0) @[ifu_aln_ctl.scala 158:52]
+    node _T_122 = or(q2off, f0_shift_2B) @[ifu_aln_ctl.scala 158:74]
+    node _T_123 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 159:11]
+    node _T_124 = eq(_T_123, UInt<1>("h00")) @[ifu_aln_ctl.scala 159:6]
+    node _T_125 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 159:23]
+    node _T_126 = and(_T_124, _T_125) @[ifu_aln_ctl.scala 159:15]
+    node _T_127 = bits(_T_126, 0, 0) @[ifu_aln_ctl.scala 159:32]
+    node _T_128 = or(q2off, f1_shift_2B) @[ifu_aln_ctl.scala 159:54]
+    node _T_129 = bits(qwen, 2, 2) @[ifu_aln_ctl.scala 160:11]
+    node _T_130 = eq(_T_129, UInt<1>("h00")) @[ifu_aln_ctl.scala 160:6]
+    node _T_131 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 160:23]
+    node _T_132 = and(_T_130, _T_131) @[ifu_aln_ctl.scala 160:15]
+    node _T_133 = bits(_T_132, 0, 0) @[ifu_aln_ctl.scala 160:32]
+    node _T_134 = mux(_T_121, _T_122, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_135 = mux(_T_127, _T_128, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_136 = mux(_T_133, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_137 = or(_T_134, _T_135) @[Mux.scala 27:72]
+    node _T_138 = or(_T_137, _T_136) @[Mux.scala 27:72]
+    wire _T_139 : UInt @[Mux.scala 27:72]
+    _T_139 <= _T_138 @[Mux.scala 27:72]
+    q2off_in <= _T_139 @[ifu_aln_ctl.scala 158:12]
+    node _T_140 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 162:31]
+    node _T_141 = eq(_T_140, UInt<1>("h00")) @[ifu_aln_ctl.scala 162:26]
+    node _T_142 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 162:43]
+    node _T_143 = and(_T_141, _T_142) @[ifu_aln_ctl.scala 162:35]
+    node _T_144 = bits(_T_143, 0, 0) @[ifu_aln_ctl.scala 162:52]
+    node _T_145 = or(q1off, f0_shift_2B) @[ifu_aln_ctl.scala 162:74]
+    node _T_146 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 163:11]
+    node _T_147 = eq(_T_146, UInt<1>("h00")) @[ifu_aln_ctl.scala 163:6]
+    node _T_148 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 163:23]
+    node _T_149 = and(_T_147, _T_148) @[ifu_aln_ctl.scala 163:15]
+    node _T_150 = bits(_T_149, 0, 0) @[ifu_aln_ctl.scala 163:32]
+    node _T_151 = or(q1off, f1_shift_2B) @[ifu_aln_ctl.scala 163:54]
+    node _T_152 = bits(qwen, 1, 1) @[ifu_aln_ctl.scala 164:11]
+    node _T_153 = eq(_T_152, UInt<1>("h00")) @[ifu_aln_ctl.scala 164:6]
+    node _T_154 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 164:23]
+    node _T_155 = and(_T_153, _T_154) @[ifu_aln_ctl.scala 164:15]
+    node _T_156 = bits(_T_155, 0, 0) @[ifu_aln_ctl.scala 164:32]
+    node _T_157 = mux(_T_144, _T_145, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_158 = mux(_T_150, _T_151, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_159 = mux(_T_156, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_160 = or(_T_157, _T_158) @[Mux.scala 27:72]
+    node _T_161 = or(_T_160, _T_159) @[Mux.scala 27:72]
+    wire _T_162 : UInt @[Mux.scala 27:72]
+    _T_162 <= _T_161 @[Mux.scala 27:72]
+    q1off_in <= _T_162 @[ifu_aln_ctl.scala 162:12]
+    node _T_163 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 166:31]
+    node _T_164 = eq(_T_163, UInt<1>("h00")) @[ifu_aln_ctl.scala 166:26]
+    node _T_165 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 166:43]
+    node _T_166 = and(_T_164, _T_165) @[ifu_aln_ctl.scala 166:35]
+    node _T_167 = bits(_T_166, 0, 0) @[ifu_aln_ctl.scala 166:52]
+    node _T_168 = or(q0off, f0_shift_2B) @[ifu_aln_ctl.scala 166:76]
+    node _T_169 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 167:31]
+    node _T_170 = eq(_T_169, UInt<1>("h00")) @[ifu_aln_ctl.scala 167:26]
+    node _T_171 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 167:43]
+    node _T_172 = and(_T_170, _T_171) @[ifu_aln_ctl.scala 167:35]
+    node _T_173 = bits(_T_172, 0, 0) @[ifu_aln_ctl.scala 167:52]
+    node _T_174 = or(q0off, f1_shift_2B) @[ifu_aln_ctl.scala 167:76]
+    node _T_175 = bits(qwen, 0, 0) @[ifu_aln_ctl.scala 168:31]
+    node _T_176 = eq(_T_175, UInt<1>("h00")) @[ifu_aln_ctl.scala 168:26]
+    node _T_177 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 168:43]
+    node _T_178 = and(_T_176, _T_177) @[ifu_aln_ctl.scala 168:35]
+    node _T_179 = bits(_T_178, 0, 0) @[ifu_aln_ctl.scala 168:52]
+    node _T_180 = mux(_T_167, _T_168, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_181 = mux(_T_173, _T_174, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_182 = mux(_T_179, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_183 = or(_T_180, _T_181) @[Mux.scala 27:72]
+    node _T_184 = or(_T_183, _T_182) @[Mux.scala 27:72]
+    wire _T_185 : UInt @[Mux.scala 27:72]
+    _T_185 <= _T_184 @[Mux.scala 27:72]
+    q0off_in <= _T_185 @[ifu_aln_ctl.scala 166:12]
+    node _T_186 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 170:31]
+    node _T_187 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 171:11]
+    node _T_188 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 172:11]
+    node _T_189 = mux(_T_186, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_190 = mux(_T_187, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_191 = mux(_T_188, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_192 = or(_T_189, _T_190) @[Mux.scala 27:72]
+    node _T_193 = or(_T_192, _T_191) @[Mux.scala 27:72]
+    wire q0ptr : UInt @[Mux.scala 27:72]
+    q0ptr <= _T_193 @[Mux.scala 27:72]
+    node _T_194 = eq(rdptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 174:32]
+    node _T_195 = eq(rdptr, UInt<1>("h01")) @[ifu_aln_ctl.scala 174:57]
+    node _T_196 = eq(rdptr, UInt<2>("h02")) @[ifu_aln_ctl.scala 174:83]
+    node _T_197 = mux(_T_194, q1off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_198 = mux(_T_195, q2off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_199 = mux(_T_196, q0off, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_200 = or(_T_197, _T_198) @[Mux.scala 27:72]
+    node _T_201 = or(_T_200, _T_199) @[Mux.scala 27:72]
+    wire q1ptr : UInt @[Mux.scala 27:72]
+    q1ptr <= _T_201 @[Mux.scala 27:72]
+    node _T_202 = eq(q0ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 176:26]
+    node q0sel = cat(q0ptr, _T_202) @[Cat.scala 29:58]
+    node _T_203 = eq(q1ptr, UInt<1>("h00")) @[ifu_aln_ctl.scala 178:26]
+    node q1sel = cat(q1ptr, _T_203) @[Cat.scala 29:58]
+    node _T_204 = cat(io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f) @[Cat.scala 29:58]
+    node _T_205 = cat(_T_204, io.ifu_bp_fghr_f) @[Cat.scala 29:58]
+    node _T_206 = cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f) @[Cat.scala 29:58]
+    node _T_207 = cat(_T_206, io.ic_access_fault_type_f) @[Cat.scala 29:58]
+    node _T_208 = cat(_T_207, _T_205) @[Cat.scala 29:58]
+    misc_data_in <= _T_208 @[ifu_aln_ctl.scala 180:16]
+    node _T_209 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 183:31]
+    node _T_210 = bits(_T_209, 0, 0) @[ifu_aln_ctl.scala 183:41]
+    node _T_211 = cat(misc1, misc0) @[Cat.scala 29:58]
+    node _T_212 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 184:9]
+    node _T_213 = bits(_T_212, 0, 0) @[ifu_aln_ctl.scala 184:19]
+    node _T_214 = cat(misc2, misc1) @[Cat.scala 29:58]
+    node _T_215 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 185:9]
+    node _T_216 = bits(_T_215, 0, 0) @[ifu_aln_ctl.scala 185:19]
+    node _T_217 = cat(misc0, misc2) @[Cat.scala 29:58]
+    node _T_218 = mux(_T_210, _T_211, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_219 = mux(_T_213, _T_214, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_220 = mux(_T_216, _T_217, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_221 = or(_T_218, _T_219) @[Mux.scala 27:72]
+    node _T_222 = or(_T_221, _T_220) @[Mux.scala 27:72]
+    wire misceff : UInt<110> @[Mux.scala 27:72]
+    misceff <= _T_222 @[Mux.scala 27:72]
+    node misc1eff = bits(misceff, 109, 55) @[ifu_aln_ctl.scala 187:25]
+    node misc0eff = bits(misceff, 54, 0) @[ifu_aln_ctl.scala 188:25]
+    node f1dbecc = bits(misc1eff, 54, 54) @[ifu_aln_ctl.scala 191:25]
+    node _T_223 = bits(misc1eff, 53, 53) @[ifu_aln_ctl.scala 192:21]
+    f1icaf <= _T_223 @[ifu_aln_ctl.scala 192:10]
+    node f1ictype = bits(misc1eff, 52, 51) @[ifu_aln_ctl.scala 193:26]
+    node f1prett = bits(misc1eff, 50, 20) @[ifu_aln_ctl.scala 194:25]
+    node f1poffset = bits(misc1eff, 19, 8) @[ifu_aln_ctl.scala 195:27]
+    node f1fghr = bits(misc1eff, 7, 0) @[ifu_aln_ctl.scala 196:24]
+    node f0dbecc = bits(misc0eff, 54, 54) @[ifu_aln_ctl.scala 198:25]
+    node _T_224 = bits(misc0eff, 53, 53) @[ifu_aln_ctl.scala 199:21]
+    f0icaf <= _T_224 @[ifu_aln_ctl.scala 199:10]
+    node f0ictype = bits(misc0eff, 52, 51) @[ifu_aln_ctl.scala 200:26]
+    node f0prett = bits(misc0eff, 50, 20) @[ifu_aln_ctl.scala 201:25]
+    node f0poffset = bits(misc0eff, 19, 8) @[ifu_aln_ctl.scala 202:27]
+    node f0fghr = bits(misc0eff, 7, 0) @[ifu_aln_ctl.scala 203:24]
+    node _T_225 = bits(io.ifu_bp_hist1_f, 1, 1) @[ifu_aln_ctl.scala 206:37]
+    node _T_226 = bits(io.ifu_bp_hist0_f, 1, 1) @[ifu_aln_ctl.scala 206:58]
+    node _T_227 = bits(io.ifu_bp_pc4_f, 1, 1) @[ifu_aln_ctl.scala 206:77]
+    node _T_228 = bits(io.ifu_bp_way_f, 1, 1) @[ifu_aln_ctl.scala 206:96]
+    node _T_229 = bits(io.ifu_bp_valid_f, 1, 1) @[ifu_aln_ctl.scala 206:117]
+    node _T_230 = bits(io.ifu_bp_ret_f, 1, 1) @[ifu_aln_ctl.scala 207:20]
+    node _T_231 = bits(io.ifu_bp_hist1_f, 0, 0) @[ifu_aln_ctl.scala 207:42]
+    node _T_232 = bits(io.ifu_bp_hist0_f, 0, 0) @[ifu_aln_ctl.scala 207:63]
+    node _T_233 = bits(io.ifu_bp_pc4_f, 0, 0) @[ifu_aln_ctl.scala 207:82]
+    node _T_234 = bits(io.ifu_bp_way_f, 0, 0) @[ifu_aln_ctl.scala 207:101]
+    node _T_235 = bits(io.ifu_bp_valid_f, 0, 0) @[ifu_aln_ctl.scala 208:22]
+    node _T_236 = bits(io.ifu_bp_ret_f, 0, 0) @[ifu_aln_ctl.scala 208:41]
+    node _T_237 = cat(_T_234, _T_235) @[Cat.scala 29:58]
+    node _T_238 = cat(_T_237, _T_236) @[Cat.scala 29:58]
+    node _T_239 = cat(_T_231, _T_232) @[Cat.scala 29:58]
+    node _T_240 = cat(_T_239, _T_233) @[Cat.scala 29:58]
+    node _T_241 = cat(_T_240, _T_238) @[Cat.scala 29:58]
+    node _T_242 = cat(_T_228, _T_229) @[Cat.scala 29:58]
+    node _T_243 = cat(_T_242, _T_230) @[Cat.scala 29:58]
+    node _T_244 = cat(_T_225, _T_226) @[Cat.scala 29:58]
+    node _T_245 = cat(_T_244, _T_227) @[Cat.scala 29:58]
+    node _T_246 = cat(_T_245, _T_243) @[Cat.scala 29:58]
+    node _T_247 = cat(_T_246, _T_241) @[Cat.scala 29:58]
+    brdata_in <= _T_247 @[ifu_aln_ctl.scala 206:13]
+    node _T_248 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 210:33]
+    node _T_249 = bits(_T_248, 0, 0) @[ifu_aln_ctl.scala 210:37]
+    node _T_250 = cat(brdata1, brdata0) @[Cat.scala 29:58]
+    node _T_251 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 211:9]
+    node _T_252 = bits(_T_251, 0, 0) @[ifu_aln_ctl.scala 211:13]
+    node _T_253 = cat(brdata2, brdata1) @[Cat.scala 29:58]
+    node _T_254 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 212:9]
+    node _T_255 = bits(_T_254, 0, 0) @[ifu_aln_ctl.scala 212:13]
+    node _T_256 = cat(brdata0, brdata2) @[Cat.scala 29:58]
+    node _T_257 = mux(_T_249, _T_250, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_258 = mux(_T_252, _T_253, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_259 = mux(_T_255, _T_256, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_260 = or(_T_257, _T_258) @[Mux.scala 27:72]
+    node _T_261 = or(_T_260, _T_259) @[Mux.scala 27:72]
+    wire brdataeff : UInt<24> @[Mux.scala 27:72]
+    brdataeff <= _T_261 @[Mux.scala 27:72]
+    node brdata0eff = bits(brdataeff, 11, 0) @[ifu_aln_ctl.scala 214:43]
+    node brdata1eff = bits(brdataeff, 23, 12) @[ifu_aln_ctl.scala 214:61]
+    node _T_262 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 216:37]
+    node _T_263 = bits(_T_262, 0, 0) @[ifu_aln_ctl.scala 216:41]
+    node _T_264 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 216:68]
+    node _T_265 = bits(_T_264, 0, 0) @[ifu_aln_ctl.scala 216:72]
+    node _T_266 = bits(brdata0eff, 11, 6) @[ifu_aln_ctl.scala 216:92]
+    node _T_267 = mux(_T_263, brdata0eff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_268 = mux(_T_265, _T_266, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_269 = or(_T_267, _T_268) @[Mux.scala 27:72]
+    wire brdata0final : UInt<12> @[Mux.scala 27:72]
+    brdata0final <= _T_269 @[Mux.scala 27:72]
+    node _T_270 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 217:37]
+    node _T_271 = bits(_T_270, 0, 0) @[ifu_aln_ctl.scala 217:41]
+    node _T_272 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 217:68]
+    node _T_273 = bits(_T_272, 0, 0) @[ifu_aln_ctl.scala 217:72]
+    node _T_274 = bits(brdata1eff, 11, 6) @[ifu_aln_ctl.scala 217:92]
+    node _T_275 = mux(_T_271, brdata1eff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_276 = mux(_T_273, _T_274, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_277 = or(_T_275, _T_276) @[Mux.scala 27:72]
+    wire brdata1final : UInt<12> @[Mux.scala 27:72]
+    brdata1final <= _T_277 @[Mux.scala 27:72]
+    node _T_278 = bits(brdata0final, 6, 6) @[ifu_aln_ctl.scala 219:31]
+    node _T_279 = bits(brdata0final, 0, 0) @[ifu_aln_ctl.scala 219:47]
+    node f0ret = cat(_T_278, _T_279) @[Cat.scala 29:58]
+    node _T_280 = bits(brdata0final, 7, 7) @[ifu_aln_ctl.scala 220:33]
+    node _T_281 = bits(brdata0final, 1, 1) @[ifu_aln_ctl.scala 220:49]
+    node f0brend = cat(_T_280, _T_281) @[Cat.scala 29:58]
+    node _T_282 = bits(brdata0final, 8, 8) @[ifu_aln_ctl.scala 221:31]
+    node _T_283 = bits(brdata0final, 2, 2) @[ifu_aln_ctl.scala 221:47]
+    node f0way = cat(_T_282, _T_283) @[Cat.scala 29:58]
+    node _T_284 = bits(brdata0final, 9, 9) @[ifu_aln_ctl.scala 222:31]
+    node _T_285 = bits(brdata0final, 3, 3) @[ifu_aln_ctl.scala 222:47]
+    node f0pc4 = cat(_T_284, _T_285) @[Cat.scala 29:58]
+    node _T_286 = bits(brdata0final, 10, 10) @[ifu_aln_ctl.scala 223:33]
+    node _T_287 = bits(brdata0final, 4, 4) @[ifu_aln_ctl.scala 223:50]
+    node f0hist0 = cat(_T_286, _T_287) @[Cat.scala 29:58]
+    node _T_288 = bits(brdata0final, 11, 11) @[ifu_aln_ctl.scala 224:33]
+    node _T_289 = bits(brdata0final, 5, 5) @[ifu_aln_ctl.scala 224:50]
+    node f0hist1 = cat(_T_288, _T_289) @[Cat.scala 29:58]
+    node _T_290 = bits(brdata1final, 6, 6) @[ifu_aln_ctl.scala 226:31]
+    node _T_291 = bits(brdata1final, 0, 0) @[ifu_aln_ctl.scala 226:47]
+    node f1ret = cat(_T_290, _T_291) @[Cat.scala 29:58]
+    node _T_292 = bits(brdata1final, 7, 7) @[ifu_aln_ctl.scala 227:33]
+    node _T_293 = bits(brdata1final, 1, 1) @[ifu_aln_ctl.scala 227:49]
+    node f1brend = cat(_T_292, _T_293) @[Cat.scala 29:58]
+    node _T_294 = bits(brdata1final, 8, 8) @[ifu_aln_ctl.scala 228:31]
+    node _T_295 = bits(brdata1final, 2, 2) @[ifu_aln_ctl.scala 228:47]
+    node f1way = cat(_T_294, _T_295) @[Cat.scala 29:58]
+    node _T_296 = bits(brdata1final, 9, 9) @[ifu_aln_ctl.scala 229:31]
+    node _T_297 = bits(brdata1final, 3, 3) @[ifu_aln_ctl.scala 229:47]
+    node f1pc4 = cat(_T_296, _T_297) @[Cat.scala 29:58]
+    node _T_298 = bits(brdata1final, 10, 10) @[ifu_aln_ctl.scala 230:33]
+    node _T_299 = bits(brdata1final, 4, 4) @[ifu_aln_ctl.scala 230:50]
+    node f1hist0 = cat(_T_298, _T_299) @[Cat.scala 29:58]
+    node _T_300 = bits(brdata1final, 11, 11) @[ifu_aln_ctl.scala 231:33]
+    node _T_301 = bits(brdata1final, 5, 5) @[ifu_aln_ctl.scala 231:50]
+    node f1hist1 = cat(_T_300, _T_301) @[Cat.scala 29:58]
+    node _T_302 = bits(f2val, 0, 0) @[ifu_aln_ctl.scala 234:20]
+    f2_valid <= _T_302 @[ifu_aln_ctl.scala 234:12]
+    node _T_303 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 235:22]
+    sf1_valid <= _T_303 @[ifu_aln_ctl.scala 235:13]
+    node _T_304 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 236:22]
+    sf0_valid <= _T_304 @[ifu_aln_ctl.scala 236:13]
+    node _T_305 = bits(sf0val, 0, 0) @[ifu_aln_ctl.scala 238:28]
+    node _T_306 = eq(_T_305, UInt<1>("h00")) @[ifu_aln_ctl.scala 238:21]
+    node _T_307 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 238:39]
+    node consume_fb0 = and(_T_306, _T_307) @[ifu_aln_ctl.scala 238:32]
+    node _T_308 = bits(sf1val, 0, 0) @[ifu_aln_ctl.scala 239:28]
+    node _T_309 = eq(_T_308, UInt<1>("h00")) @[ifu_aln_ctl.scala 239:21]
+    node _T_310 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 239:39]
+    node consume_fb1 = and(_T_309, _T_310) @[ifu_aln_ctl.scala 239:32]
+    node _T_311 = eq(consume_fb1, UInt<1>("h00")) @[ifu_aln_ctl.scala 242:39]
+    node _T_312 = and(consume_fb0, _T_311) @[ifu_aln_ctl.scala 242:37]
+    node _T_313 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 242:54]
+    node _T_314 = and(_T_312, _T_313) @[ifu_aln_ctl.scala 242:52]
+    io.ifu_fb_consume1 <= _T_314 @[ifu_aln_ctl.scala 242:22]
+    node _T_315 = and(consume_fb0, consume_fb1) @[ifu_aln_ctl.scala 243:37]
+    node _T_316 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 243:54]
+    node _T_317 = and(_T_315, _T_316) @[ifu_aln_ctl.scala 243:52]
+    io.ifu_fb_consume2 <= _T_317 @[ifu_aln_ctl.scala 243:22]
+    node _T_318 = bits(io.ifu_fetch_val, 0, 0) @[ifu_aln_ctl.scala 245:30]
+    ifvalid <= _T_318 @[ifu_aln_ctl.scala 245:11]
+    node _T_319 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 248:18]
+    node _T_320 = and(_T_319, sf1_valid) @[ifu_aln_ctl.scala 248:29]
+    shift_f1_f0 <= _T_320 @[ifu_aln_ctl.scala 248:15]
+    node _T_321 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 249:18]
+    node _T_322 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 249:31]
+    node _T_323 = and(_T_321, _T_322) @[ifu_aln_ctl.scala 249:29]
+    node _T_324 = and(_T_323, f2_valid) @[ifu_aln_ctl.scala 249:42]
+    shift_f2_f0 <= _T_324 @[ifu_aln_ctl.scala 249:15]
+    node _T_325 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 250:18]
+    node _T_326 = and(_T_325, sf1_valid) @[ifu_aln_ctl.scala 250:29]
+    node _T_327 = and(_T_326, f2_valid) @[ifu_aln_ctl.scala 250:42]
+    shift_f2_f1 <= _T_327 @[ifu_aln_ctl.scala 250:15]
+    node _T_328 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 252:26]
+    node _T_329 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 252:39]
+    node _T_330 = and(_T_328, _T_329) @[ifu_aln_ctl.scala 252:37]
+    node _T_331 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 252:52]
+    node _T_332 = and(_T_330, _T_331) @[ifu_aln_ctl.scala 252:50]
+    node _T_333 = and(_T_332, ifvalid) @[ifu_aln_ctl.scala 252:62]
+    fetch_to_f0 <= _T_333 @[ifu_aln_ctl.scala 252:22]
+    node _T_334 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 253:26]
+    node _T_335 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 253:39]
+    node _T_336 = and(_T_334, _T_335) @[ifu_aln_ctl.scala 253:37]
+    node _T_337 = and(_T_336, f2_valid) @[ifu_aln_ctl.scala 253:50]
+    node _T_338 = and(_T_337, ifvalid) @[ifu_aln_ctl.scala 253:62]
+    node _T_339 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 254:26]
+    node _T_340 = and(_T_339, sf1_valid) @[ifu_aln_ctl.scala 254:37]
+    node _T_341 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 254:52]
+    node _T_342 = and(_T_340, _T_341) @[ifu_aln_ctl.scala 254:50]
+    node _T_343 = and(_T_342, ifvalid) @[ifu_aln_ctl.scala 254:62]
+    node _T_344 = or(_T_338, _T_343) @[ifu_aln_ctl.scala 253:74]
+    node _T_345 = eq(sf1_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 255:39]
+    node _T_346 = and(sf0_valid, _T_345) @[ifu_aln_ctl.scala 255:37]
+    node _T_347 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 255:52]
+    node _T_348 = and(_T_346, _T_347) @[ifu_aln_ctl.scala 255:50]
+    node _T_349 = and(_T_348, ifvalid) @[ifu_aln_ctl.scala 255:62]
+    node _T_350 = or(_T_344, _T_349) @[ifu_aln_ctl.scala 254:74]
+    fetch_to_f1 <= _T_350 @[ifu_aln_ctl.scala 253:22]
+    node _T_351 = eq(sf0_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 257:26]
+    node _T_352 = and(_T_351, sf1_valid) @[ifu_aln_ctl.scala 257:37]
+    node _T_353 = and(_T_352, f2_valid) @[ifu_aln_ctl.scala 257:50]
+    node _T_354 = and(_T_353, ifvalid) @[ifu_aln_ctl.scala 257:62]
+    node _T_355 = and(sf0_valid, sf1_valid) @[ifu_aln_ctl.scala 258:37]
+    node _T_356 = eq(f2_valid, UInt<1>("h00")) @[ifu_aln_ctl.scala 258:52]
+    node _T_357 = and(_T_355, _T_356) @[ifu_aln_ctl.scala 258:50]
+    node _T_358 = and(_T_357, ifvalid) @[ifu_aln_ctl.scala 258:62]
+    node _T_359 = or(_T_354, _T_358) @[ifu_aln_ctl.scala 257:74]
+    fetch_to_f2 <= _T_359 @[ifu_aln_ctl.scala 257:22]
+    node _T_360 = add(f0pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 260:25]
+    node f0pc_plus1 = tail(_T_360, 1) @[ifu_aln_ctl.scala 260:25]
+    node _T_361 = add(f1pc, UInt<1>("h01")) @[ifu_aln_ctl.scala 262:25]
+    node f1pc_plus1 = tail(_T_361, 1) @[ifu_aln_ctl.scala 262:25]
+    node _T_362 = bits(f1_shift_2B, 0, 0) @[Bitwise.scala 72:15]
+    node _T_363 = mux(_T_362, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+    node _T_364 = and(_T_363, f1pc_plus1) @[ifu_aln_ctl.scala 264:38]
+    node _T_365 = eq(f1_shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 264:64]
+    node _T_366 = bits(_T_365, 0, 0) @[Bitwise.scala 72:15]
+    node _T_367 = mux(_T_366, UInt<31>("h07fffffff"), UInt<31>("h00")) @[Bitwise.scala 72:12]
+    node _T_368 = and(_T_367, f1pc) @[ifu_aln_ctl.scala 264:78]
+    node sf1pc = or(_T_364, _T_368) @[ifu_aln_ctl.scala 264:52]
+    node _T_369 = bits(fetch_to_f1, 0, 0) @[ifu_aln_ctl.scala 266:36]
+    node _T_370 = bits(shift_f2_f1, 0, 0) @[ifu_aln_ctl.scala 267:17]
+    node _T_371 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 268:6]
+    node _T_372 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 268:21]
+    node _T_373 = and(_T_371, _T_372) @[ifu_aln_ctl.scala 268:19]
+    node _T_374 = bits(_T_373, 0, 0) @[ifu_aln_ctl.scala 268:35]
+    node _T_375 = mux(_T_369, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_376 = mux(_T_370, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_377 = mux(_T_374, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_378 = or(_T_375, _T_376) @[Mux.scala 27:72]
+    node _T_379 = or(_T_378, _T_377) @[Mux.scala 27:72]
+    wire _T_380 : UInt @[Mux.scala 27:72]
+    _T_380 <= _T_379 @[Mux.scala 27:72]
+    f1pc_in <= _T_380 @[ifu_aln_ctl.scala 266:11]
+    node _T_381 = bits(fetch_to_f0, 0, 0) @[ifu_aln_ctl.scala 270:36]
+    node _T_382 = bits(shift_f2_f0, 0, 0) @[ifu_aln_ctl.scala 271:36]
+    node _T_383 = bits(shift_f1_f0, 0, 0) @[ifu_aln_ctl.scala 272:36]
+    node _T_384 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 273:24]
+    node _T_385 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 273:39]
+    node _T_386 = and(_T_384, _T_385) @[ifu_aln_ctl.scala 273:37]
+    node _T_387 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 273:54]
+    node _T_388 = and(_T_386, _T_387) @[ifu_aln_ctl.scala 273:52]
+    node _T_389 = bits(_T_388, 0, 0) @[ifu_aln_ctl.scala 273:68]
+    node _T_390 = mux(_T_381, io.ifu_fetch_pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_391 = mux(_T_382, f2pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_392 = mux(_T_383, sf1pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_393 = mux(_T_389, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_394 = or(_T_390, _T_391) @[Mux.scala 27:72]
+    node _T_395 = or(_T_394, _T_392) @[Mux.scala 27:72]
+    node _T_396 = or(_T_395, _T_393) @[Mux.scala 27:72]
+    wire _T_397 : UInt @[Mux.scala 27:72]
+    _T_397 <= _T_396 @[Mux.scala 27:72]
+    f0pc_in <= _T_397 @[ifu_aln_ctl.scala 270:11]
+    node _T_398 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 275:40]
+    node _T_399 = and(fetch_to_f2, _T_398) @[ifu_aln_ctl.scala 275:38]
+    node _T_400 = bits(_T_399, 0, 0) @[ifu_aln_ctl.scala 275:61]
+    node _T_401 = eq(fetch_to_f2, UInt<1>("h00")) @[ifu_aln_ctl.scala 276:25]
+    node _T_402 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 276:40]
+    node _T_403 = and(_T_401, _T_402) @[ifu_aln_ctl.scala 276:38]
+    node _T_404 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 276:55]
+    node _T_405 = and(_T_403, _T_404) @[ifu_aln_ctl.scala 276:53]
+    node _T_406 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 276:70]
+    node _T_407 = and(_T_405, _T_406) @[ifu_aln_ctl.scala 276:68]
+    node _T_408 = bits(_T_407, 0, 0) @[ifu_aln_ctl.scala 276:91]
+    node _T_409 = mux(_T_400, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_410 = mux(_T_408, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_411 = or(_T_409, _T_410) @[Mux.scala 27:72]
+    wire _T_412 : UInt @[Mux.scala 27:72]
+    _T_412 <= _T_411 @[Mux.scala 27:72]
+    f2val_in <= _T_412 @[ifu_aln_ctl.scala 275:12]
+    node _T_413 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 278:35]
+    node _T_414 = bits(f1val, 1, 1) @[ifu_aln_ctl.scala 278:48]
+    node _T_415 = bits(f1_shift_2B, 0, 0) @[ifu_aln_ctl.scala 278:66]
+    node _T_416 = eq(_T_415, UInt<1>("h00")) @[ifu_aln_ctl.scala 278:53]
+    node _T_417 = mux(_T_413, _T_414, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_418 = mux(_T_416, f1val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_419 = or(_T_417, _T_418) @[Mux.scala 27:72]
+    wire _T_420 : UInt @[Mux.scala 27:72]
+    _T_420 <= _T_419 @[Mux.scala 27:72]
+    sf1val <= _T_420 @[ifu_aln_ctl.scala 278:10]
+    node _T_421 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 280:71]
+    node _T_422 = and(fetch_to_f1, _T_421) @[ifu_aln_ctl.scala 280:39]
+    node _T_423 = bits(_T_422, 0, 0) @[ifu_aln_ctl.scala 280:92]
+    node _T_424 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 281:71]
+    node _T_425 = and(shift_f2_f1, _T_424) @[ifu_aln_ctl.scala 281:54]
+    node _T_426 = bits(_T_425, 0, 0) @[ifu_aln_ctl.scala 281:92]
+    node _T_427 = eq(fetch_to_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 282:26]
+    node _T_428 = eq(shift_f2_f1, UInt<1>("h00")) @[ifu_aln_ctl.scala 282:41]
+    node _T_429 = and(_T_427, _T_428) @[ifu_aln_ctl.scala 282:39]
+    node _T_430 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 282:56]
+    node _T_431 = and(_T_429, _T_430) @[ifu_aln_ctl.scala 282:54]
+    node _T_432 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 282:71]
+    node _T_433 = and(_T_431, _T_432) @[ifu_aln_ctl.scala 282:69]
+    node _T_434 = bits(_T_433, 0, 0) @[ifu_aln_ctl.scala 282:92]
+    node _T_435 = mux(_T_423, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_436 = mux(_T_426, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_437 = mux(_T_434, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_438 = or(_T_435, _T_436) @[Mux.scala 27:72]
+    node _T_439 = or(_T_438, _T_437) @[Mux.scala 27:72]
+    wire _T_440 : UInt @[Mux.scala 27:72]
+    _T_440 <= _T_439 @[Mux.scala 27:72]
+    f1val_in <= _T_440 @[ifu_aln_ctl.scala 280:12]
+    node _T_441 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 284:32]
+    node _T_442 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 284:54]
+    node _T_443 = cat(UInt<1>("h00"), _T_442) @[Cat.scala 29:58]
+    node _T_444 = eq(shift_2B, UInt<1>("h00")) @[ifu_aln_ctl.scala 285:18]
+    node _T_445 = eq(shift_4B, UInt<1>("h00")) @[ifu_aln_ctl.scala 285:30]
+    node _T_446 = and(_T_444, _T_445) @[ifu_aln_ctl.scala 285:28]
+    node _T_447 = bits(_T_446, 0, 0) @[ifu_aln_ctl.scala 285:41]
+    node _T_448 = mux(_T_441, _T_443, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_449 = mux(_T_447, f0val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_450 = or(_T_448, _T_449) @[Mux.scala 27:72]
+    wire _T_451 : UInt @[Mux.scala 27:72]
+    _T_451 <= _T_450 @[Mux.scala 27:72]
+    sf0val <= _T_451 @[ifu_aln_ctl.scala 284:10]
+    node _T_452 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 287:71]
+    node _T_453 = and(fetch_to_f0, _T_452) @[ifu_aln_ctl.scala 287:38]
+    node _T_454 = bits(_T_453, 0, 0) @[ifu_aln_ctl.scala 287:92]
+    node _T_455 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 288:71]
+    node _T_456 = and(shift_f2_f0, _T_455) @[ifu_aln_ctl.scala 288:54]
+    node _T_457 = bits(_T_456, 0, 0) @[ifu_aln_ctl.scala 288:92]
+    node _T_458 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 289:71]
+    node _T_459 = and(shift_f1_f0, _T_458) @[ifu_aln_ctl.scala 289:69]
+    node _T_460 = bits(_T_459, 0, 0) @[ifu_aln_ctl.scala 289:92]
+    node _T_461 = eq(fetch_to_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 290:26]
+    node _T_462 = eq(shift_f2_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 290:41]
+    node _T_463 = and(_T_461, _T_462) @[ifu_aln_ctl.scala 290:39]
+    node _T_464 = eq(shift_f1_f0, UInt<1>("h00")) @[ifu_aln_ctl.scala 290:56]
+    node _T_465 = and(_T_463, _T_464) @[ifu_aln_ctl.scala 290:54]
+    node _T_466 = eq(io.exu_flush_final, UInt<1>("h00")) @[ifu_aln_ctl.scala 290:71]
+    node _T_467 = and(_T_465, _T_466) @[ifu_aln_ctl.scala 290:69]
+    node _T_468 = bits(_T_467, 0, 0) @[ifu_aln_ctl.scala 290:92]
+    node _T_469 = mux(_T_454, io.ifu_fetch_val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_470 = mux(_T_457, f2val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_471 = mux(_T_460, sf1val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_472 = mux(_T_468, sf0val, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_473 = or(_T_469, _T_470) @[Mux.scala 27:72]
+    node _T_474 = or(_T_473, _T_471) @[Mux.scala 27:72]
+    node _T_475 = or(_T_474, _T_472) @[Mux.scala 27:72]
+    wire _T_476 : UInt @[Mux.scala 27:72]
+    _T_476 <= _T_475 @[Mux.scala 27:72]
+    f0val_in <= _T_476 @[ifu_aln_ctl.scala 287:12]
+    node _T_477 = bits(qren, 0, 0) @[ifu_aln_ctl.scala 292:28]
+    node _T_478 = bits(_T_477, 0, 0) @[ifu_aln_ctl.scala 292:32]
+    node _T_479 = cat(q1, q0) @[Cat.scala 29:58]
+    node _T_480 = bits(qren, 1, 1) @[ifu_aln_ctl.scala 293:9]
+    node _T_481 = bits(_T_480, 0, 0) @[ifu_aln_ctl.scala 293:13]
+    node _T_482 = cat(q2, q1) @[Cat.scala 29:58]
+    node _T_483 = bits(qren, 2, 2) @[ifu_aln_ctl.scala 294:9]
+    node _T_484 = bits(_T_483, 0, 0) @[ifu_aln_ctl.scala 294:13]
+    node _T_485 = cat(q0, q2) @[Cat.scala 29:58]
+    node _T_486 = mux(_T_478, _T_479, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_487 = mux(_T_481, _T_482, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_488 = mux(_T_484, _T_485, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_489 = or(_T_486, _T_487) @[Mux.scala 27:72]
+    node _T_490 = or(_T_489, _T_488) @[Mux.scala 27:72]
+    wire qeff : UInt<64> @[Mux.scala 27:72]
+    qeff <= _T_490 @[Mux.scala 27:72]
+    node q1eff = bits(qeff, 63, 32) @[ifu_aln_ctl.scala 295:29]
+    node q0eff = bits(qeff, 31, 0) @[ifu_aln_ctl.scala 295:42]
+    node _T_491 = bits(q0sel, 0, 0) @[ifu_aln_ctl.scala 297:29]
+    node _T_492 = bits(_T_491, 0, 0) @[ifu_aln_ctl.scala 297:33]
+    node _T_493 = bits(q0sel, 1, 1) @[ifu_aln_ctl.scala 297:53]
+    node _T_494 = bits(_T_493, 0, 0) @[ifu_aln_ctl.scala 297:57]
+    node _T_495 = bits(q0eff, 31, 16) @[ifu_aln_ctl.scala 297:70]
+    node _T_496 = mux(_T_492, q0eff, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_497 = mux(_T_494, _T_495, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_498 = or(_T_496, _T_497) @[Mux.scala 27:72]
+    wire _T_499 : UInt<32> @[Mux.scala 27:72]
+    _T_499 <= _T_498 @[Mux.scala 27:72]
+    q0final <= _T_499 @[ifu_aln_ctl.scala 297:11]
+    node _T_500 = bits(q1sel, 0, 0) @[ifu_aln_ctl.scala 299:29]
+    node _T_501 = bits(_T_500, 0, 0) @[ifu_aln_ctl.scala 299:33]
+    node _T_502 = bits(q1eff, 15, 0) @[ifu_aln_ctl.scala 299:46]
+    node _T_503 = bits(q1sel, 1, 1) @[ifu_aln_ctl.scala 299:59]
+    node _T_504 = bits(_T_503, 0, 0) @[ifu_aln_ctl.scala 299:63]
+    node _T_505 = bits(q1eff, 31, 16) @[ifu_aln_ctl.scala 299:76]
+    node _T_506 = mux(_T_501, _T_502, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_507 = mux(_T_504, _T_505, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_508 = or(_T_506, _T_507) @[Mux.scala 27:72]
+    wire _T_509 : UInt<16> @[Mux.scala 27:72]
+    _T_509 <= _T_508 @[Mux.scala 27:72]
+    q1final <= _T_509 @[ifu_aln_ctl.scala 299:11]
+    node _T_510 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 302:34]
+    node _T_511 = bits(_T_510, 0, 0) @[ifu_aln_ctl.scala 302:38]
+    node _T_512 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 302:64]
+    node _T_513 = not(_T_512) @[ifu_aln_ctl.scala 302:58]
+    node _T_514 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 302:75]
+    node _T_515 = and(_T_513, _T_514) @[ifu_aln_ctl.scala 302:68]
+    node _T_516 = bits(_T_515, 0, 0) @[ifu_aln_ctl.scala 302:80]
+    node _T_517 = bits(q1final, 15, 0) @[ifu_aln_ctl.scala 302:101]
+    node _T_518 = bits(q0final, 15, 0) @[ifu_aln_ctl.scala 302:115]
+    node _T_519 = cat(_T_517, _T_518) @[Cat.scala 29:58]
+    node _T_520 = mux(_T_511, q0final, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_521 = mux(_T_516, _T_519, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_522 = or(_T_520, _T_521) @[Mux.scala 27:72]
+    wire aligndata : UInt<32> @[Mux.scala 27:72]
+    aligndata <= _T_522 @[Mux.scala 27:72]
+    node _T_523 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 304:30]
+    node _T_524 = bits(_T_523, 0, 0) @[ifu_aln_ctl.scala 304:34]
+    node _T_525 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 304:54]
+    node _T_526 = eq(_T_525, UInt<1>("h00")) @[ifu_aln_ctl.scala 304:48]
+    node _T_527 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 304:65]
+    node _T_528 = and(_T_526, _T_527) @[ifu_aln_ctl.scala 304:58]
+    node _T_529 = bits(f1val, 0, 0) @[ifu_aln_ctl.scala 304:82]
+    node _T_530 = cat(_T_529, UInt<1>("h01")) @[Cat.scala 29:58]
+    node _T_531 = mux(_T_524, UInt<2>("h03"), UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_532 = mux(_T_528, _T_530, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_533 = or(_T_531, _T_532) @[Mux.scala 27:72]
+    wire _T_534 : UInt<2> @[Mux.scala 27:72]
+    _T_534 <= _T_533 @[Mux.scala 27:72]
+    alignval <= _T_534 @[ifu_aln_ctl.scala 304:12]
+    node _T_535 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 306:34]
+    node _T_536 = bits(_T_535, 0, 0) @[ifu_aln_ctl.scala 306:38]
+    node _T_537 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 306:63]
+    node _T_538 = not(_T_537) @[ifu_aln_ctl.scala 306:57]
+    node _T_539 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 306:74]
+    node _T_540 = and(_T_538, _T_539) @[ifu_aln_ctl.scala 306:67]
+    node _T_541 = bits(_T_540, 0, 0) @[ifu_aln_ctl.scala 306:79]
+    node _T_542 = cat(f1icaf, f0icaf) @[Cat.scala 29:58]
+    node _T_543 = mux(_T_536, f0icaf, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_544 = mux(_T_541, _T_542, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_545 = or(_T_543, _T_544) @[Mux.scala 27:72]
+    wire alignicaf : UInt<2> @[Mux.scala 27:72]
+    alignicaf <= _T_545 @[Mux.scala 27:72]
+    node _T_546 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 308:35]
+    node _T_547 = bits(_T_546, 0, 0) @[ifu_aln_ctl.scala 308:39]
+    node _T_548 = bits(f0dbecc, 0, 0) @[Bitwise.scala 72:15]
+    node _T_549 = mux(_T_548, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12]
+    node _T_550 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 308:73]
+    node _T_551 = eq(_T_550, UInt<1>("h00")) @[ifu_aln_ctl.scala 308:67]
+    node _T_552 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 308:84]
+    node _T_553 = and(_T_551, _T_552) @[ifu_aln_ctl.scala 308:77]
+    node _T_554 = bits(_T_553, 0, 0) @[ifu_aln_ctl.scala 308:89]
+    node _T_555 = cat(f1dbecc, f0dbecc) @[Cat.scala 29:58]
+    node _T_556 = mux(_T_547, _T_549, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_557 = mux(_T_554, _T_555, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_558 = or(_T_556, _T_557) @[Mux.scala 27:72]
+    wire aligndbecc : UInt<2> @[Mux.scala 27:72]
+    aligndbecc <= _T_558 @[Mux.scala 27:72]
+    node _T_559 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 310:35]
+    node _T_560 = bits(_T_559, 0, 0) @[ifu_aln_ctl.scala 310:45]
+    node _T_561 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 310:65]
+    node _T_562 = eq(_T_561, UInt<1>("h00")) @[ifu_aln_ctl.scala 310:59]
+    node _T_563 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 310:76]
+    node _T_564 = and(_T_562, _T_563) @[ifu_aln_ctl.scala 310:69]
+    node _T_565 = bits(_T_564, 0, 0) @[ifu_aln_ctl.scala 310:81]
+    node _T_566 = bits(f1brend, 0, 0) @[ifu_aln_ctl.scala 310:100]
+    node _T_567 = bits(f0brend, 0, 0) @[ifu_aln_ctl.scala 310:111]
+    node _T_568 = cat(_T_566, _T_567) @[Cat.scala 29:58]
+    node _T_569 = mux(_T_560, f0brend, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_570 = mux(_T_565, _T_568, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_571 = or(_T_569, _T_570) @[Mux.scala 27:72]
+    wire alignbrend : UInt<2> @[Mux.scala 27:72]
+    alignbrend <= _T_571 @[Mux.scala 27:72]
+    node _T_572 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 312:33]
+    node _T_573 = bits(_T_572, 0, 0) @[ifu_aln_ctl.scala 312:43]
+    node _T_574 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 312:61]
+    node _T_575 = eq(_T_574, UInt<1>("h00")) @[ifu_aln_ctl.scala 312:55]
+    node _T_576 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 312:72]
+    node _T_577 = and(_T_575, _T_576) @[ifu_aln_ctl.scala 312:65]
+    node _T_578 = bits(_T_577, 0, 0) @[ifu_aln_ctl.scala 312:77]
+    node _T_579 = bits(f1pc4, 0, 0) @[ifu_aln_ctl.scala 312:94]
+    node _T_580 = bits(f0pc4, 0, 0) @[ifu_aln_ctl.scala 312:103]
+    node _T_581 = cat(_T_579, _T_580) @[Cat.scala 29:58]
+    node _T_582 = mux(_T_573, f0pc4, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_583 = mux(_T_578, _T_581, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_584 = or(_T_582, _T_583) @[Mux.scala 27:72]
+    wire alignpc4 : UInt<2> @[Mux.scala 27:72]
+    alignpc4 <= _T_584 @[Mux.scala 27:72]
+    node _T_585 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 314:33]
+    node _T_586 = bits(_T_585, 0, 0) @[ifu_aln_ctl.scala 314:43]
+    node _T_587 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 314:61]
+    node _T_588 = eq(_T_587, UInt<1>("h00")) @[ifu_aln_ctl.scala 314:55]
+    node _T_589 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 314:72]
+    node _T_590 = and(_T_588, _T_589) @[ifu_aln_ctl.scala 314:65]
+    node _T_591 = bits(_T_590, 0, 0) @[ifu_aln_ctl.scala 314:77]
+    node _T_592 = bits(f1ret, 0, 0) @[ifu_aln_ctl.scala 314:94]
+    node _T_593 = bits(f0ret, 0, 0) @[ifu_aln_ctl.scala 314:103]
+    node _T_594 = cat(_T_592, _T_593) @[Cat.scala 29:58]
+    node _T_595 = mux(_T_586, f0ret, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_596 = mux(_T_591, _T_594, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_597 = or(_T_595, _T_596) @[Mux.scala 27:72]
+    wire alignret : UInt<2> @[Mux.scala 27:72]
+    alignret <= _T_597 @[Mux.scala 27:72]
+    node _T_598 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 316:33]
+    node _T_599 = bits(_T_598, 0, 0) @[ifu_aln_ctl.scala 316:43]
+    node _T_600 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 316:61]
+    node _T_601 = eq(_T_600, UInt<1>("h00")) @[ifu_aln_ctl.scala 316:55]
+    node _T_602 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 316:72]
+    node _T_603 = and(_T_601, _T_602) @[ifu_aln_ctl.scala 316:65]
+    node _T_604 = bits(_T_603, 0, 0) @[ifu_aln_ctl.scala 316:77]
+    node _T_605 = bits(f1way, 0, 0) @[ifu_aln_ctl.scala 316:94]
+    node _T_606 = bits(f0way, 0, 0) @[ifu_aln_ctl.scala 316:103]
+    node _T_607 = cat(_T_605, _T_606) @[Cat.scala 29:58]
+    node _T_608 = mux(_T_599, f0way, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_609 = mux(_T_604, _T_607, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_610 = or(_T_608, _T_609) @[Mux.scala 27:72]
+    wire alignway : UInt<2> @[Mux.scala 27:72]
+    alignway <= _T_610 @[Mux.scala 27:72]
+    node _T_611 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 318:35]
+    node _T_612 = bits(_T_611, 0, 0) @[ifu_aln_ctl.scala 318:45]
+    node _T_613 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 318:65]
+    node _T_614 = eq(_T_613, UInt<1>("h00")) @[ifu_aln_ctl.scala 318:59]
+    node _T_615 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 318:76]
+    node _T_616 = and(_T_614, _T_615) @[ifu_aln_ctl.scala 318:69]
+    node _T_617 = bits(_T_616, 0, 0) @[ifu_aln_ctl.scala 318:81]
+    node _T_618 = bits(f1hist1, 0, 0) @[ifu_aln_ctl.scala 318:100]
+    node _T_619 = bits(f0hist1, 0, 0) @[ifu_aln_ctl.scala 318:111]
+    node _T_620 = cat(_T_618, _T_619) @[Cat.scala 29:58]
+    node _T_621 = mux(_T_612, f0hist1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_622 = mux(_T_617, _T_620, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_623 = or(_T_621, _T_622) @[Mux.scala 27:72]
+    wire alignhist1 : UInt<2> @[Mux.scala 27:72]
+    alignhist1 <= _T_623 @[Mux.scala 27:72]
+    node _T_624 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 320:35]
+    node _T_625 = bits(_T_624, 0, 0) @[ifu_aln_ctl.scala 320:45]
+    node _T_626 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 320:65]
+    node _T_627 = eq(_T_626, UInt<1>("h00")) @[ifu_aln_ctl.scala 320:59]
+    node _T_628 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 320:76]
+    node _T_629 = and(_T_627, _T_628) @[ifu_aln_ctl.scala 320:69]
+    node _T_630 = bits(_T_629, 0, 0) @[ifu_aln_ctl.scala 320:81]
+    node _T_631 = bits(f1hist0, 0, 0) @[ifu_aln_ctl.scala 320:100]
+    node _T_632 = bits(f0hist0, 0, 0) @[ifu_aln_ctl.scala 320:111]
+    node _T_633 = cat(_T_631, _T_632) @[Cat.scala 29:58]
+    node _T_634 = mux(_T_625, f0hist0, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_635 = mux(_T_630, _T_633, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_636 = or(_T_634, _T_635) @[Mux.scala 27:72]
+    wire alignhist0 : UInt<2> @[Mux.scala 27:72]
+    alignhist0 <= _T_636 @[Mux.scala 27:72]
+    node _T_637 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 322:27]
+    node _T_638 = eq(_T_637, UInt<1>("h00")) @[ifu_aln_ctl.scala 322:21]
+    node _T_639 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 322:38]
+    node alignfromf1 = and(_T_638, _T_639) @[ifu_aln_ctl.scala 322:31]
+    node _T_640 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 324:33]
+    node _T_641 = bits(_T_640, 0, 0) @[ifu_aln_ctl.scala 324:43]
+    node _T_642 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 324:67]
+    node _T_643 = eq(_T_642, UInt<1>("h00")) @[ifu_aln_ctl.scala 324:61]
+    node _T_644 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 324:78]
+    node _T_645 = and(_T_643, _T_644) @[ifu_aln_ctl.scala 324:71]
+    node _T_646 = bits(_T_645, 0, 0) @[ifu_aln_ctl.scala 324:83]
+    node _T_647 = mux(_T_641, f0pc_plus1, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_648 = mux(_T_646, f1pc, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_649 = or(_T_647, _T_648) @[Mux.scala 27:72]
+    wire secondpc : UInt @[Mux.scala 27:72]
+    secondpc <= _T_649 @[Mux.scala 27:72]
+    io.dec_aln.aln_ib.ifu_i0_pc <= f0pc @[ifu_aln_ctl.scala 326:31]
+    io.dec_aln.aln_ib.ifu_i0_pc4 <= first4B @[ifu_aln_ctl.scala 330:32]
+    node _T_650 = bits(aligndata, 15, 0) @[ifu_aln_ctl.scala 332:47]
+    io.dec_aln.aln_dec.ifu_i0_cinst <= _T_650 @[ifu_aln_ctl.scala 332:35]
+    node _T_651 = bits(aligndata, 1, 0) @[ifu_aln_ctl.scala 335:23]
+    node _T_652 = eq(_T_651, UInt<2>("h03")) @[ifu_aln_ctl.scala 335:29]
+    first4B <= _T_652 @[ifu_aln_ctl.scala 335:11]
+    node first2B = not(first4B) @[ifu_aln_ctl.scala 337:17]
+    node _T_653 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 339:55]
+    node _T_654 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 339:73]
+    node _T_655 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 339:86]
+    node _T_656 = bits(alignval, 0, 0) @[ifu_aln_ctl.scala 339:104]
+    node _T_657 = mux(_T_653, _T_654, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_658 = mux(_T_655, _T_656, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_659 = or(_T_657, _T_658) @[Mux.scala 27:72]
+    wire _T_660 : UInt<1> @[Mux.scala 27:72]
+    _T_660 <= _T_659 @[Mux.scala 27:72]
+    io.dec_aln.aln_ib.ifu_i0_valid <= _T_660 @[ifu_aln_ctl.scala 339:34]
+    node _T_661 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 341:54]
+    node _T_662 = orr(alignicaf) @[ifu_aln_ctl.scala 341:74]
+    node _T_663 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 341:87]
+    node _T_664 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 341:106]
+    node _T_665 = mux(_T_661, _T_662, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_666 = mux(_T_663, _T_664, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_667 = or(_T_665, _T_666) @[Mux.scala 27:72]
+    wire _T_668 : UInt<1> @[Mux.scala 27:72]
+    _T_668 <= _T_667 @[Mux.scala 27:72]
+    io.dec_aln.aln_ib.ifu_i0_icaf <= _T_668 @[ifu_aln_ctl.scala 341:33]
+    node _T_669 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 343:62]
+    node _T_670 = eq(_T_669, UInt<1>("h00")) @[ifu_aln_ctl.scala 343:56]
+    node _T_671 = and(first4B, _T_670) @[ifu_aln_ctl.scala 343:54]
+    node _T_672 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 343:73]
+    node _T_673 = and(_T_671, _T_672) @[ifu_aln_ctl.scala 343:66]
+    node _T_674 = bits(alignicaf, 0, 0) @[ifu_aln_ctl.scala 343:89]
+    node _T_675 = eq(_T_674, UInt<1>("h00")) @[ifu_aln_ctl.scala 343:79]
+    node _T_676 = and(_T_673, _T_675) @[ifu_aln_ctl.scala 343:77]
+    node _T_677 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 343:106]
+    node _T_678 = eq(_T_677, UInt<1>("h00")) @[ifu_aln_ctl.scala 343:95]
+    node _T_679 = and(_T_676, _T_678) @[ifu_aln_ctl.scala 343:93]
+    node _T_680 = bits(_T_679, 0, 0) @[ifu_aln_ctl.scala 343:111]
+    node _T_681 = mux(_T_680, f1ictype, f0ictype) @[ifu_aln_ctl.scala 343:44]
+    io.dec_aln.aln_ib.ifu_i0_icaf_type <= _T_681 @[ifu_aln_ctl.scala 343:38]
+    node _T_682 = bits(alignicaf, 1, 1) @[ifu_aln_ctl.scala 345:27]
+    node _T_683 = bits(aligndbecc, 1, 1) @[ifu_aln_ctl.scala 345:43]
+    node icaf_eff = or(_T_682, _T_683) @[ifu_aln_ctl.scala 345:31]
+    node _T_684 = and(first4B, icaf_eff) @[ifu_aln_ctl.scala 347:51]
+    node _T_685 = and(_T_684, alignfromf1) @[ifu_aln_ctl.scala 347:62]
+    io.dec_aln.aln_ib.ifu_i0_icaf_second <= _T_685 @[ifu_aln_ctl.scala 347:40]
+    node _T_686 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 349:55]
+    node _T_687 = orr(aligndbecc) @[ifu_aln_ctl.scala 349:74]
+    node _T_688 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 349:87]
+    node _T_689 = bits(aligndbecc, 0, 0) @[ifu_aln_ctl.scala 349:105]
+    node _T_690 = mux(_T_686, _T_687, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_691 = mux(_T_688, _T_689, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_692 = or(_T_690, _T_691) @[Mux.scala 27:72]
+    wire _T_693 : UInt<1> @[Mux.scala 27:72]
+    _T_693 <= _T_692 @[Mux.scala 27:72]
+    io.dec_aln.aln_ib.ifu_i0_dbecc <= _T_693 @[ifu_aln_ctl.scala 349:34]
+    inst decompressed of ifu_compress_ctl @[ifu_aln_ctl.scala 353:28]
+    decompressed.clock <= clock
+    decompressed.reset <= reset
+    node _T_694 = bits(first4B, 0, 0) @[ifu_aln_ctl.scala 355:55]
+    node _T_695 = bits(first2B, 0, 0) @[ifu_aln_ctl.scala 355:81]
+    node _T_696 = mux(_T_694, aligndata, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_697 = mux(_T_695, decompressed.io.dout, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_698 = or(_T_696, _T_697) @[Mux.scala 27:72]
+    wire _T_699 : UInt<32> @[Mux.scala 27:72]
+    _T_699 <= _T_698 @[Mux.scala 27:72]
+    io.dec_aln.aln_ib.ifu_i0_instr <= _T_699 @[ifu_aln_ctl.scala 355:34]
+    node _T_700 = bits(f0pc, 8, 1) @[lib.scala 51:13]
+    node _T_701 = bits(f0pc, 16, 9) @[lib.scala 51:51]
+    node _T_702 = xor(_T_700, _T_701) @[lib.scala 51:47]
+    node _T_703 = bits(f0pc, 24, 17) @[lib.scala 51:89]
+    node firstpc_hash = xor(_T_702, _T_703) @[lib.scala 51:85]
+    node _T_704 = bits(secondpc, 8, 1) @[lib.scala 51:13]
+    node _T_705 = bits(secondpc, 16, 9) @[lib.scala 51:51]
+    node _T_706 = xor(_T_704, _T_705) @[lib.scala 51:47]
+    node _T_707 = bits(secondpc, 24, 17) @[lib.scala 51:89]
+    node secondpc_hash = xor(_T_706, _T_707) @[lib.scala 51:85]
+    node _T_708 = bits(f0pc, 13, 9) @[lib.scala 42:32]
+    node _T_709 = bits(f0pc, 18, 14) @[lib.scala 42:32]
+    node _T_710 = bits(f0pc, 23, 19) @[lib.scala 42:32]
+    wire _T_711 : UInt<5>[3] @[lib.scala 42:24]
+    _T_711[0] <= _T_708 @[lib.scala 42:24]
+    _T_711[1] <= _T_709 @[lib.scala 42:24]
+    _T_711[2] <= _T_710 @[lib.scala 42:24]
+    node _T_712 = xor(_T_711[0], _T_711[1]) @[lib.scala 42:111]
+    node firstbrtag_hash = xor(_T_712, _T_711[2]) @[lib.scala 42:111]
+    node _T_713 = bits(secondpc, 13, 9) @[lib.scala 42:32]
+    node _T_714 = bits(secondpc, 18, 14) @[lib.scala 42:32]
+    node _T_715 = bits(secondpc, 23, 19) @[lib.scala 42:32]
+    wire _T_716 : UInt<5>[3] @[lib.scala 42:24]
+    _T_716[0] <= _T_713 @[lib.scala 42:24]
+    _T_716[1] <= _T_714 @[lib.scala 42:24]
+    _T_716[2] <= _T_715 @[lib.scala 42:24]
+    node _T_717 = xor(_T_716[0], _T_716[1]) @[lib.scala 42:111]
+    node secondbrtag_hash = xor(_T_717, _T_716[2]) @[lib.scala 42:111]
+    node _T_718 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 366:57]
+    node _T_719 = and(first2B, _T_718) @[ifu_aln_ctl.scala 366:45]
+    node _T_720 = bits(alignbrend, 1, 1) @[ifu_aln_ctl.scala 366:85]
+    node _T_721 = and(first4B, _T_720) @[ifu_aln_ctl.scala 366:73]
+    node _T_722 = or(_T_719, _T_721) @[ifu_aln_ctl.scala 366:62]
+    node _T_723 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 366:111]
+    node _T_724 = and(first4B, _T_723) @[ifu_aln_ctl.scala 366:101]
+    node _T_725 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 366:127]
+    node _T_726 = and(_T_724, _T_725) @[ifu_aln_ctl.scala 366:115]
+    node _T_727 = or(_T_722, _T_726) @[ifu_aln_ctl.scala 366:90]
+    io.dec_aln.aln_ib.i0_brp.valid <= _T_727 @[ifu_aln_ctl.scala 366:34]
+    node _T_728 = bits(alignret, 0, 0) @[ifu_aln_ctl.scala 368:59]
+    node _T_729 = and(first2B, _T_728) @[ifu_aln_ctl.scala 368:49]
+    node _T_730 = bits(alignret, 1, 1) @[ifu_aln_ctl.scala 368:85]
+    node _T_731 = and(first4B, _T_730) @[ifu_aln_ctl.scala 368:75]
+    node _T_732 = or(_T_729, _T_731) @[ifu_aln_ctl.scala 368:64]
+    io.dec_aln.aln_ib.i0_brp.bits.ret <= _T_732 @[ifu_aln_ctl.scala 368:37]
+    node _T_733 = bits(alignpc4, 0, 0) @[ifu_aln_ctl.scala 370:39]
+    node _T_734 = and(first2B, _T_733) @[ifu_aln_ctl.scala 370:29]
+    node _T_735 = bits(alignpc4, 1, 1) @[ifu_aln_ctl.scala 370:65]
+    node _T_736 = and(first4B, _T_735) @[ifu_aln_ctl.scala 370:55]
+    node i0_brp_pc4 = or(_T_734, _T_736) @[ifu_aln_ctl.scala 370:44]
+    node _T_737 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 372:65]
+    node _T_738 = or(first2B, _T_737) @[ifu_aln_ctl.scala 372:53]
+    node _T_739 = bits(_T_738, 0, 0) @[ifu_aln_ctl.scala 372:70]
+    node _T_740 = bits(alignway, 0, 0) @[ifu_aln_ctl.scala 372:86]
+    node _T_741 = bits(alignway, 1, 1) @[ifu_aln_ctl.scala 372:100]
+    node _T_742 = mux(_T_739, _T_740, _T_741) @[ifu_aln_ctl.scala 372:43]
+    io.dec_aln.aln_ib.i0_brp.bits.way <= _T_742 @[ifu_aln_ctl.scala 372:37]
+    node _T_743 = bits(alignhist1, 0, 0) @[ifu_aln_ctl.scala 374:66]
+    node _T_744 = and(first2B, _T_743) @[ifu_aln_ctl.scala 374:54]
+    node _T_745 = bits(alignhist1, 1, 1) @[ifu_aln_ctl.scala 374:94]
+    node _T_746 = and(first4B, _T_745) @[ifu_aln_ctl.scala 374:82]
+    node _T_747 = or(_T_744, _T_746) @[ifu_aln_ctl.scala 374:71]
+    node _T_748 = bits(alignhist0, 0, 0) @[ifu_aln_ctl.scala 375:26]
+    node _T_749 = and(first2B, _T_748) @[ifu_aln_ctl.scala 375:14]
+    node _T_750 = bits(alignhist0, 1, 1) @[ifu_aln_ctl.scala 375:54]
+    node _T_751 = and(first4B, _T_750) @[ifu_aln_ctl.scala 375:42]
+    node _T_752 = or(_T_749, _T_751) @[ifu_aln_ctl.scala 375:31]
+    node _T_753 = cat(_T_747, _T_752) @[Cat.scala 29:58]
+    io.dec_aln.aln_ib.i0_brp.bits.hist <= _T_753 @[ifu_aln_ctl.scala 374:38]
+    node i0_ends_f1 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 377:28]
+    node _T_754 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 378:59]
+    node _T_755 = mux(_T_754, f1poffset, f0poffset) @[ifu_aln_ctl.scala 378:47]
+    io.dec_aln.aln_ib.i0_brp.bits.toffset <= _T_755 @[ifu_aln_ctl.scala 378:41]
+    node _T_756 = bits(i0_ends_f1, 0, 0) @[ifu_aln_ctl.scala 380:57]
+    node _T_757 = mux(_T_756, f1prett, f0prett) @[ifu_aln_ctl.scala 380:45]
+    io.dec_aln.aln_ib.i0_brp.bits.prett <= _T_757 @[ifu_aln_ctl.scala 380:39]
+    node _T_758 = bits(alignval, 1, 1) @[ifu_aln_ctl.scala 382:71]
+    node _T_759 = and(first4B, _T_758) @[ifu_aln_ctl.scala 382:61]
+    node _T_760 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 382:87]
+    node _T_761 = and(_T_759, _T_760) @[ifu_aln_ctl.scala 382:75]
+    io.dec_aln.aln_ib.i0_brp.bits.br_start_error <= _T_761 @[ifu_aln_ctl.scala 382:49]
+    node _T_762 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 384:77]
+    node _T_763 = or(first2B, _T_762) @[ifu_aln_ctl.scala 384:65]
+    node _T_764 = bits(_T_763, 0, 0) @[ifu_aln_ctl.scala 384:82]
+    node _T_765 = bits(f0pc, 0, 0) @[ifu_aln_ctl.scala 384:97]
+    node _T_766 = bits(secondpc, 0, 0) @[ifu_aln_ctl.scala 384:110]
+    node _T_767 = mux(_T_764, _T_765, _T_766) @[ifu_aln_ctl.scala 384:55]
+    io.dec_aln.aln_ib.i0_brp.bits.bank <= _T_767 @[ifu_aln_ctl.scala 384:49]
+    node _T_768 = and(io.dec_aln.aln_ib.i0_brp.valid, i0_brp_pc4) @[ifu_aln_ctl.scala 386:77]
+    node _T_769 = and(_T_768, first2B) @[ifu_aln_ctl.scala 386:91]
+    node _T_770 = eq(i0_brp_pc4, UInt<1>("h00")) @[ifu_aln_ctl.scala 386:139]
+    node _T_771 = and(io.dec_aln.aln_ib.i0_brp.valid, _T_770) @[ifu_aln_ctl.scala 386:137]
+    node _T_772 = and(_T_771, first4B) @[ifu_aln_ctl.scala 386:151]
+    node _T_773 = or(_T_769, _T_772) @[ifu_aln_ctl.scala 386:103]
+    io.dec_aln.aln_ib.i0_brp.bits.br_error <= _T_773 @[ifu_aln_ctl.scala 386:42]
+    node _T_774 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 388:65]
+    node _T_775 = or(first2B, _T_774) @[ifu_aln_ctl.scala 388:53]
+    node _T_776 = bits(_T_775, 0, 0) @[ifu_aln_ctl.scala 388:70]
+    node _T_777 = mux(_T_776, firstpc_hash, secondpc_hash) @[ifu_aln_ctl.scala 388:43]
+    io.dec_aln.aln_ib.ifu_i0_bp_index <= _T_777 @[ifu_aln_ctl.scala 388:37]
+    node _T_778 = and(first4B, alignfromf1) @[ifu_aln_ctl.scala 390:52]
+    node _T_779 = bits(_T_778, 0, 0) @[ifu_aln_ctl.scala 390:67]
+    node _T_780 = mux(_T_779, f1fghr, f0fghr) @[ifu_aln_ctl.scala 390:42]
+    io.dec_aln.aln_ib.ifu_i0_bp_fghr <= _T_780 @[ifu_aln_ctl.scala 390:36]
+    node _T_781 = bits(alignbrend, 0, 0) @[ifu_aln_ctl.scala 392:64]
+    node _T_782 = or(first2B, _T_781) @[ifu_aln_ctl.scala 392:52]
+    node _T_783 = bits(_T_782, 0, 0) @[ifu_aln_ctl.scala 392:69]
+    node _T_784 = mux(_T_783, firstbrtag_hash, secondbrtag_hash) @[ifu_aln_ctl.scala 392:42]
+    io.dec_aln.aln_ib.ifu_i0_bp_btag <= _T_784 @[ifu_aln_ctl.scala 392:36]
+    decompressed.io.din <= aligndata @[ifu_aln_ctl.scala 394:23]
+    node _T_785 = not(error_stall) @[ifu_aln_ctl.scala 396:39]
+    node i0_shift = and(io.dec_i0_decode_d, _T_785) @[ifu_aln_ctl.scala 396:37]
+    io.dec_aln.ifu_pmu_instr_aligned <= i0_shift @[ifu_aln_ctl.scala 398:36]
+    node _T_786 = and(i0_shift, first2B) @[ifu_aln_ctl.scala 400:24]
+    shift_2B <= _T_786 @[ifu_aln_ctl.scala 400:12]
+    node _T_787 = and(i0_shift, first4B) @[ifu_aln_ctl.scala 401:24]
+    shift_4B <= _T_787 @[ifu_aln_ctl.scala 401:12]
+    node _T_788 = bits(shift_2B, 0, 0) @[ifu_aln_ctl.scala 403:37]
+    node _T_789 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 403:52]
+    node _T_790 = bits(shift_4B, 0, 0) @[ifu_aln_ctl.scala 403:66]
+    node _T_791 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 403:82]
+    node _T_792 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 403:94]
+    node _T_793 = eq(_T_792, UInt<1>("h00")) @[ifu_aln_ctl.scala 403:88]
+    node _T_794 = and(_T_791, _T_793) @[ifu_aln_ctl.scala 403:86]
+    node _T_795 = mux(_T_788, _T_789, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_796 = mux(_T_790, _T_794, UInt<1>("h00")) @[Mux.scala 27:72]
+    node _T_797 = or(_T_795, _T_796) @[Mux.scala 27:72]
+    wire _T_798 : UInt<1> @[Mux.scala 27:72]
+    _T_798 <= _T_797 @[Mux.scala 27:72]
+    f0_shift_2B <= _T_798 @[ifu_aln_ctl.scala 403:15]
+    node _T_799 = bits(f0val, 0, 0) @[ifu_aln_ctl.scala 404:24]
+    node _T_800 = bits(f0val, 1, 1) @[ifu_aln_ctl.scala 404:36]
+    node _T_801 = eq(_T_800, UInt<1>("h00")) @[ifu_aln_ctl.scala 404:30]
+    node _T_802 = and(_T_799, _T_801) @[ifu_aln_ctl.scala 404:28]
+    node _T_803 = and(_T_802, shift_4B) @[ifu_aln_ctl.scala 404:40]
+    f1_shift_2B <= _T_803 @[ifu_aln_ctl.scala 404:15]
+    
diff --git a/ifu_aln_ctl.v b/ifu_aln_ctl.v
new file mode 100644
index 00000000..e3fcbbf2
--- /dev/null
+++ b/ifu_aln_ctl.v
@@ -0,0 +1,1405 @@
+module rvclkhdr(
+  input   io_clk,
+  input   io_en
+);
+  wire  clkhdr_Q; // @[lib.scala 334:26]
+  wire  clkhdr_CK; // @[lib.scala 334:26]
+  wire  clkhdr_EN; // @[lib.scala 334:26]
+  wire  clkhdr_SE; // @[lib.scala 334:26]
+  gated_latch clkhdr ( // @[lib.scala 334:26]
+    .Q(clkhdr_Q),
+    .CK(clkhdr_CK),
+    .EN(clkhdr_EN),
+    .SE(clkhdr_SE)
+  );
+  assign clkhdr_CK = io_clk; // @[lib.scala 336:18]
+  assign clkhdr_EN = io_en; // @[lib.scala 337:18]
+  assign clkhdr_SE = 1'h0; // @[lib.scala 338:18]
+endmodule
+module ifu_compress_ctl(
+  input  [15:0] io_din,
+  output [31:0] io_dout
+);
+  wire  _T_2 = ~io_din[14]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_4 = ~io_din[13]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_7 = ~io_din[6]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_9 = ~io_din[5]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_11 = io_din[15] & _T_2; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_12 = _T_11 & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_13 = _T_12 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_14 = _T_13 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_15 = _T_14 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_16 = _T_15 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_23 = ~io_din[11]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_28 = _T_12 & _T_23; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_29 = _T_28 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_30 = _T_29 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_30 = _T_16 | _T_30; // @[ifu_compress_ctl.scala 17:53]
+  wire  _T_38 = ~io_din[10]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_40 = ~io_din[9]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_42 = ~io_din[8]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_44 = ~io_din[7]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_50 = ~io_din[4]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_52 = ~io_din[3]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_54 = ~io_din[2]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_56 = _T_2 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_57 = _T_56 & _T_23; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_58 = _T_57 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_59 = _T_58 & _T_40; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_60 = _T_59 & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_61 = _T_60 & _T_44; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_62 = _T_61 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_63 = _T_62 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_64 = _T_63 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_65 = _T_64 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_66 = _T_65 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_20 = _T_66 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_79 = _T_28 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_90 = _T_12 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_91 = _T_90 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_92 = _T_79 | _T_91; // @[ifu_compress_ctl.scala 21:46]
+  wire  _T_102 = _T_12 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_103 = _T_102 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_104 = _T_92 | _T_103; // @[ifu_compress_ctl.scala 21:80]
+  wire  _T_114 = _T_12 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_115 = _T_114 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_14 = _T_104 | _T_115; // @[ifu_compress_ctl.scala 21:113]
+  wire  _T_128 = _T_12 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_129 = _T_128 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_130 = _T_129 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_142 = _T_128 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_143 = _T_142 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_144 = _T_130 | _T_143; // @[ifu_compress_ctl.scala 23:50]
+  wire  _T_147 = ~io_din[0]; // @[ifu_compress_ctl.scala 23:101]
+  wire  _T_148 = io_din[14] & _T_147; // @[ifu_compress_ctl.scala 23:99]
+  wire  out_13 = _T_144 | _T_148; // @[ifu_compress_ctl.scala 23:86]
+  wire  _T_161 = _T_102 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_162 = _T_161 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_175 = _T_162 | _T_79; // @[ifu_compress_ctl.scala 25:47]
+  wire  _T_188 = _T_175 | _T_91; // @[ifu_compress_ctl.scala 25:81]
+  wire  _T_190 = ~io_din[15]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_194 = _T_190 & _T_2; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_195 = _T_194 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_196 = _T_188 | _T_195; // @[ifu_compress_ctl.scala 25:115]
+  wire  _T_200 = io_din[15] & io_din[14]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_201 = _T_200 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_12 = _T_196 | _T_201; // @[ifu_compress_ctl.scala 26:26]
+  wire  _T_217 = _T_11 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_218 = _T_217 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_219 = _T_218 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_220 = _T_219 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_221 = _T_220 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_224 = _T_221 & _T_147; // @[ifu_compress_ctl.scala 28:53]
+  wire  _T_228 = _T_2 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_229 = _T_224 | _T_228; // @[ifu_compress_ctl.scala 28:67]
+  wire  _T_234 = _T_200 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_6 = _T_229 | _T_234; // @[ifu_compress_ctl.scala 28:88]
+  wire  _T_239 = io_din[15] & _T_147; // @[ifu_compress_ctl.scala 30:24]
+  wire  _T_243 = io_din[15] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_244 = _T_243 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_245 = _T_239 | _T_244; // @[ifu_compress_ctl.scala 30:39]
+  wire  _T_249 = io_din[13] & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_250 = _T_245 | _T_249; // @[ifu_compress_ctl.scala 30:63]
+  wire  _T_253 = io_din[13] & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_254 = _T_250 | _T_253; // @[ifu_compress_ctl.scala 30:83]
+  wire  _T_257 = io_din[13] & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_258 = _T_254 | _T_257; // @[ifu_compress_ctl.scala 30:102]
+  wire  _T_261 = io_din[13] & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_262 = _T_258 | _T_261; // @[ifu_compress_ctl.scala 31:22]
+  wire  _T_265 = io_din[13] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_266 = _T_262 | _T_265; // @[ifu_compress_ctl.scala 31:42]
+  wire  _T_271 = _T_266 | _T_228; // @[ifu_compress_ctl.scala 31:62]
+  wire  out_5 = _T_271 | _T_200; // @[ifu_compress_ctl.scala 31:83]
+  wire  _T_288 = _T_2 & _T_23; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_289 = _T_288 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_290 = _T_289 & _T_40; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_291 = _T_290 & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_292 = _T_291 & _T_44; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_295 = _T_292 & _T_147; // @[ifu_compress_ctl.scala 33:50]
+  wire  _T_303 = _T_194 & _T_147; // @[ifu_compress_ctl.scala 33:87]
+  wire  _T_304 = _T_295 | _T_303; // @[ifu_compress_ctl.scala 33:65]
+  wire  _T_308 = _T_2 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_311 = _T_308 & _T_147; // @[ifu_compress_ctl.scala 34:23]
+  wire  _T_312 = _T_304 | _T_311; // @[ifu_compress_ctl.scala 33:102]
+  wire  _T_317 = _T_190 & io_din[14]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_318 = _T_317 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_319 = _T_312 | _T_318; // @[ifu_compress_ctl.scala 34:38]
+  wire  _T_323 = _T_2 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_326 = _T_323 & _T_147; // @[ifu_compress_ctl.scala 34:82]
+  wire  _T_327 = _T_319 | _T_326; // @[ifu_compress_ctl.scala 34:62]
+  wire  _T_331 = _T_2 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_334 = _T_331 & _T_147; // @[ifu_compress_ctl.scala 35:23]
+  wire  _T_335 = _T_327 | _T_334; // @[ifu_compress_ctl.scala 34:97]
+  wire  _T_339 = _T_2 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_342 = _T_339 & _T_147; // @[ifu_compress_ctl.scala 35:58]
+  wire  _T_343 = _T_335 | _T_342; // @[ifu_compress_ctl.scala 35:38]
+  wire  _T_347 = _T_2 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_350 = _T_347 & _T_147; // @[ifu_compress_ctl.scala 35:93]
+  wire  _T_351 = _T_343 | _T_350; // @[ifu_compress_ctl.scala 35:73]
+  wire  _T_357 = _T_2 & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_358 = _T_357 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  out_4 = _T_351 | _T_358; // @[ifu_compress_ctl.scala 35:108]
+  wire  _T_380 = _T_56 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_381 = _T_380 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_382 = _T_381 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_383 = _T_382 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_384 = _T_383 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_385 = _T_384 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_386 = _T_385 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_403 = _T_56 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_404 = _T_403 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_405 = _T_404 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_406 = _T_405 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_407 = _T_406 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_408 = _T_407 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_409 = _T_408 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_410 = _T_386 | _T_409; // @[ifu_compress_ctl.scala 40:59]
+  wire  _T_427 = _T_56 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_428 = _T_427 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_429 = _T_428 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_430 = _T_429 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_431 = _T_430 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_432 = _T_431 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_433 = _T_432 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_434 = _T_410 | _T_433; // @[ifu_compress_ctl.scala 40:107]
+  wire  _T_451 = _T_56 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_452 = _T_451 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_453 = _T_452 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_454 = _T_453 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_455 = _T_454 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_456 = _T_455 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_457 = _T_456 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_458 = _T_434 | _T_457; // @[ifu_compress_ctl.scala 41:50]
+  wire  _T_475 = _T_56 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_476 = _T_475 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_477 = _T_476 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_478 = _T_477 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_479 = _T_478 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_480 = _T_479 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_481 = _T_480 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_482 = _T_458 | _T_481; // @[ifu_compress_ctl.scala 41:94]
+  wire  _T_487 = ~io_din[12]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_499 = _T_11 & _T_487; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_500 = _T_499 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_501 = _T_500 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_502 = _T_501 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_503 = _T_502 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_504 = _T_503 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_507 = _T_504 & _T_147; // @[ifu_compress_ctl.scala 42:94]
+  wire  _T_508 = _T_482 | _T_507; // @[ifu_compress_ctl.scala 42:49]
+  wire  _T_514 = _T_190 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_515 = _T_514 & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_516 = _T_508 | _T_515; // @[ifu_compress_ctl.scala 42:109]
+  wire  _T_522 = _T_514 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_523 = _T_516 | _T_522; // @[ifu_compress_ctl.scala 43:26]
+  wire  _T_529 = _T_514 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_530 = _T_523 | _T_529; // @[ifu_compress_ctl.scala 43:48]
+  wire  _T_536 = _T_514 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_537 = _T_530 | _T_536; // @[ifu_compress_ctl.scala 43:70]
+  wire  _T_543 = _T_514 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_544 = _T_537 | _T_543; // @[ifu_compress_ctl.scala 43:93]
+  wire  out_2 = _T_544 | _T_228; // @[ifu_compress_ctl.scala 44:26]
+  wire [4:0] rs2d = io_din[6:2]; // @[ifu_compress_ctl.scala 50:20]
+  wire [4:0] rdd = io_din[11:7]; // @[ifu_compress_ctl.scala 51:19]
+  wire [4:0] rdpd = {2'h1,io_din[9:7]}; // @[Cat.scala 29:58]
+  wire [4:0] rs2pd = {2'h1,io_din[4:2]}; // @[Cat.scala 29:58]
+  wire  _T_557 = _T_308 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_564 = _T_317 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_565 = _T_564 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_566 = _T_557 | _T_565; // @[ifu_compress_ctl.scala 55:33]
+  wire  _T_572 = _T_323 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_573 = _T_566 | _T_572; // @[ifu_compress_ctl.scala 55:58]
+  wire  _T_580 = _T_317 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_581 = _T_580 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_582 = _T_573 | _T_581; // @[ifu_compress_ctl.scala 55:79]
+  wire  _T_588 = _T_331 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_589 = _T_582 | _T_588; // @[ifu_compress_ctl.scala 55:104]
+  wire  _T_596 = _T_317 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_597 = _T_596 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_598 = _T_589 | _T_597; // @[ifu_compress_ctl.scala 56:24]
+  wire  _T_604 = _T_339 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_605 = _T_598 | _T_604; // @[ifu_compress_ctl.scala 56:48]
+  wire  _T_613 = _T_317 & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_614 = _T_613 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_615 = _T_605 | _T_614; // @[ifu_compress_ctl.scala 56:69]
+  wire  _T_621 = _T_347 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_622 = _T_615 | _T_621; // @[ifu_compress_ctl.scala 56:94]
+  wire  _T_629 = _T_317 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_630 = _T_629 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_631 = _T_622 | _T_630; // @[ifu_compress_ctl.scala 57:22]
+  wire  _T_635 = _T_190 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_636 = _T_631 | _T_635; // @[ifu_compress_ctl.scala 57:46]
+  wire  _T_642 = _T_190 & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_643 = _T_642 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  rdrd = _T_636 | _T_643; // @[ifu_compress_ctl.scala 57:65]
+  wire  _T_651 = _T_380 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_659 = _T_403 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_660 = _T_651 | _T_659; // @[ifu_compress_ctl.scala 59:38]
+  wire  _T_668 = _T_427 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_669 = _T_660 | _T_668; // @[ifu_compress_ctl.scala 59:63]
+  wire  _T_677 = _T_451 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_678 = _T_669 | _T_677; // @[ifu_compress_ctl.scala 59:87]
+  wire  _T_686 = _T_475 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_687 = _T_678 | _T_686; // @[ifu_compress_ctl.scala 60:27]
+  wire  _T_703 = _T_2 & _T_487; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_704 = _T_703 & _T_7; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_705 = _T_704 & _T_9; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_706 = _T_705 & _T_50; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_707 = _T_706 & _T_52; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_708 = _T_707 & _T_54; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_709 = _T_708 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_710 = _T_687 | _T_709; // @[ifu_compress_ctl.scala 60:51]
+  wire  _T_717 = _T_56 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_718 = _T_717 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_719 = _T_710 | _T_718; // @[ifu_compress_ctl.scala 60:89]
+  wire  _T_726 = _T_56 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_727 = _T_726 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_728 = _T_719 | _T_727; // @[ifu_compress_ctl.scala 61:27]
+  wire  _T_735 = _T_56 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_736 = _T_735 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_737 = _T_728 | _T_736; // @[ifu_compress_ctl.scala 61:51]
+  wire  _T_744 = _T_56 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_745 = _T_744 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_746 = _T_737 | _T_745; // @[ifu_compress_ctl.scala 61:75]
+  wire  _T_753 = _T_56 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_754 = _T_753 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_755 = _T_746 | _T_754; // @[ifu_compress_ctl.scala 61:99]
+  wire  _T_764 = _T_194 & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_765 = _T_764 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_766 = _T_755 | _T_765; // @[ifu_compress_ctl.scala 62:27]
+  wire  rdrs1 = _T_766 | _T_195; // @[ifu_compress_ctl.scala 62:54]
+  wire  _T_777 = io_din[15] & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_778 = _T_777 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_782 = io_din[15] & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_783 = _T_782 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_784 = _T_778 | _T_783; // @[ifu_compress_ctl.scala 64:34]
+  wire  _T_788 = io_din[15] & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_789 = _T_788 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_790 = _T_784 | _T_789; // @[ifu_compress_ctl.scala 64:54]
+  wire  _T_794 = io_din[15] & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_795 = _T_794 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_796 = _T_790 | _T_795; // @[ifu_compress_ctl.scala 64:74]
+  wire  _T_800 = io_din[15] & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_801 = _T_800 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_802 = _T_796 | _T_801; // @[ifu_compress_ctl.scala 64:94]
+  wire  _T_807 = _T_200 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  rs2rs2 = _T_802 | _T_807; // @[ifu_compress_ctl.scala 64:114]
+  wire  rdprd = _T_12 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_820 = io_din[15] & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_821 = _T_820 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_827 = _T_821 | _T_234; // @[ifu_compress_ctl.scala 68:36]
+  wire  _T_830 = ~io_din[1]; // @[ifu_compress_ctl.scala 12:83]
+  wire  _T_831 = io_din[14] & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_834 = _T_831 & _T_147; // @[ifu_compress_ctl.scala 68:76]
+  wire  rdprs1 = _T_827 | _T_834; // @[ifu_compress_ctl.scala 68:57]
+  wire  _T_846 = _T_128 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_847 = _T_846 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_851 = io_din[15] & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_854 = _T_851 & _T_147; // @[ifu_compress_ctl.scala 70:66]
+  wire  rs2prs2 = _T_847 | _T_854; // @[ifu_compress_ctl.scala 70:47]
+  wire  _T_859 = _T_190 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  rs2prd = _T_859 & _T_147; // @[ifu_compress_ctl.scala 72:33]
+  wire  _T_866 = _T_2 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  uimm9_2 = _T_866 & _T_147; // @[ifu_compress_ctl.scala 74:34]
+  wire  _T_875 = _T_317 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  ulwimm6_2 = _T_875 & _T_147; // @[ifu_compress_ctl.scala 76:39]
+  wire  ulwspimm7_2 = _T_317 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_897 = _T_317 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_898 = _T_897 & _T_23; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_899 = _T_898 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_900 = _T_899 & _T_40; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_901 = _T_900 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
+  wire  rdeq2 = _T_901 & _T_44; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1027 = _T_194 & io_din[13]; // @[ifu_compress_ctl.scala 12:110]
+  wire  rdeq1 = _T_482 | _T_1027; // @[ifu_compress_ctl.scala 84:42]
+  wire  _T_1050 = io_din[14] & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1051 = rdeq2 | _T_1050; // @[ifu_compress_ctl.scala 86:53]
+  wire  rs1eq2 = _T_1051 | uimm9_2; // @[ifu_compress_ctl.scala 86:71]
+  wire  _T_1092 = _T_357 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1093 = _T_1092 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1094 = _T_1093 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  simm5_0 = _T_1094 | _T_643; // @[ifu_compress_ctl.scala 92:45]
+  wire  _T_1112 = _T_897 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1121 = _T_897 & _T_42; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1122 = _T_1112 | _T_1121; // @[ifu_compress_ctl.scala 96:44]
+  wire  _T_1130 = _T_897 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1131 = _T_1122 | _T_1130; // @[ifu_compress_ctl.scala 96:70]
+  wire  _T_1139 = _T_897 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1140 = _T_1131 | _T_1139; // @[ifu_compress_ctl.scala 96:95]
+  wire  _T_1148 = _T_897 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  sluimm17_12 = _T_1140 | _T_1148; // @[ifu_compress_ctl.scala 96:121]
+  wire  uimm5_0 = _T_79 | _T_195; // @[ifu_compress_ctl.scala 98:45]
+  wire [6:0] l1_6 = {out_6,out_5,out_4,_T_228,out_2,1'h1,1'h1}; // @[Cat.scala 29:58]
+  wire [4:0] _T_1192 = rdrd ? rdd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1193 = rdprd ? rdpd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1194 = rs2prd ? rs2pd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1195 = rdeq1 ? 5'h1 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1196 = rdeq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1197 = _T_1192 | _T_1193; // @[Mux.scala 27:72]
+  wire [4:0] _T_1198 = _T_1197 | _T_1194; // @[Mux.scala 27:72]
+  wire [4:0] _T_1199 = _T_1198 | _T_1195; // @[Mux.scala 27:72]
+  wire [4:0] l1_11 = _T_1199 | _T_1196; // @[Mux.scala 27:72]
+  wire [4:0] _T_1210 = rdrs1 ? rdd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1211 = rdprs1 ? rdpd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1212 = rs1eq2 ? 5'h2 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1213 = _T_1210 | _T_1211; // @[Mux.scala 27:72]
+  wire [4:0] l1_19 = _T_1213 | _T_1212; // @[Mux.scala 27:72]
+  wire [4:0] _T_1219 = {3'h0,1'h0,out_20}; // @[Cat.scala 29:58]
+  wire [4:0] _T_1222 = rs2rs2 ? rs2d : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1223 = rs2prs2 ? rs2pd : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1224 = _T_1222 | _T_1223; // @[Mux.scala 27:72]
+  wire [4:0] l1_24 = _T_1219 | _T_1224; // @[ifu_compress_ctl.scala 114:67]
+  wire [14:0] _T_1232 = {out_14,out_13,out_12,l1_11,l1_6}; // @[Cat.scala 29:58]
+  wire [31:0] l1 = {1'h0,out_30,2'h0,3'h0,l1_24,l1_19,_T_1232}; // @[Cat.scala 29:58]
+  wire [5:0] simm5d = {io_din[12],rs2d}; // @[Cat.scala 29:58]
+  wire [5:0] simm9d = {io_din[12],io_din[4:3],io_din[5],io_din[2],io_din[6]}; // @[Cat.scala 29:58]
+  wire [10:0] sjald_1 = {io_din[12],io_din[8],io_din[10:9],io_din[6],io_din[7],io_din[2],io_din[11],io_din[5:4],io_din[3]}; // @[Cat.scala 29:58]
+  wire [19:0] sjald = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],sjald_1}; // @[Cat.scala 29:58]
+  wire [9:0] _T_1296 = {io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],io_din[12]}; // @[Cat.scala 29:58]
+  wire [19:0] sluimmd = {_T_1296,io_din[12],io_din[12],io_din[12],io_din[12],io_din[12],rs2d}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1314 = {simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[5],simm5d[4:0]}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1317 = {2'h0,io_din[10:7],io_din[12:11],io_din[5],io_din[6],2'h0}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1325 = {simm9d[5],simm9d[5],simm9d[5],simm9d[4:0],4'h0}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1328 = {5'h0,io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1331 = {4'h0,io_din[3:2],io_din[12],io_din[6:4],2'h0}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1333 = {6'h0,io_din[12],rs2d}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1339 = {sjald[19],sjald[9:0],sjald[10]}; // @[Cat.scala 29:58]
+  wire [11:0] _T_1342 = simm5_0 ? _T_1314 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1343 = uimm9_2 ? _T_1317 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1344 = rdeq2 ? _T_1325 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1345 = ulwimm6_2 ? _T_1328 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1346 = ulwspimm7_2 ? _T_1331 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1347 = uimm5_0 ? _T_1333 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1348 = _T_228 ? _T_1339 : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1349 = sluimm17_12 ? sluimmd[19:8] : 12'h0; // @[Mux.scala 27:72]
+  wire [11:0] _T_1350 = _T_1342 | _T_1343; // @[Mux.scala 27:72]
+  wire [11:0] _T_1351 = _T_1350 | _T_1344; // @[Mux.scala 27:72]
+  wire [11:0] _T_1352 = _T_1351 | _T_1345; // @[Mux.scala 27:72]
+  wire [11:0] _T_1353 = _T_1352 | _T_1346; // @[Mux.scala 27:72]
+  wire [11:0] _T_1354 = _T_1353 | _T_1347; // @[Mux.scala 27:72]
+  wire [11:0] _T_1355 = _T_1354 | _T_1348; // @[Mux.scala 27:72]
+  wire [11:0] _T_1356 = _T_1355 | _T_1349; // @[Mux.scala 27:72]
+  wire [11:0] l2_31 = l1[31:20] | _T_1356; // @[ifu_compress_ctl.scala 133:25]
+  wire [7:0] _T_1363 = _T_228 ? sjald[19:12] : 8'h0; // @[Mux.scala 27:72]
+  wire [7:0] _T_1364 = sluimm17_12 ? sluimmd[7:0] : 8'h0; // @[Mux.scala 27:72]
+  wire [7:0] _T_1365 = _T_1363 | _T_1364; // @[Mux.scala 27:72]
+  wire [7:0] l2_19 = l1[19:12] | _T_1365; // @[ifu_compress_ctl.scala 143:25]
+  wire [31:0] l2 = {l2_31,l2_19,l1[11:0]}; // @[Cat.scala 29:58]
+  wire [8:0] sbr8d = {io_din[12],io_din[6],io_din[5],io_din[2],io_din[11],io_din[10],io_din[4],io_din[3],1'h0}; // @[Cat.scala 29:58]
+  wire [6:0] uswimm6d = {io_din[5],io_din[12:10],io_din[6],2'h0}; // @[Cat.scala 29:58]
+  wire [7:0] uswspimm7d = {io_din[8:7],io_din[12:9],2'h0}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1400 = {sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[8],sbr8d[7:5]}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1403 = {5'h0,uswimm6d[6:5]}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1406 = {4'h0,uswspimm7d[7:5]}; // @[Cat.scala 29:58]
+  wire [6:0] _T_1407 = _T_234 ? _T_1400 : 7'h0; // @[Mux.scala 27:72]
+  wire [6:0] _T_1408 = _T_854 ? _T_1403 : 7'h0; // @[Mux.scala 27:72]
+  wire [6:0] _T_1409 = _T_807 ? _T_1406 : 7'h0; // @[Mux.scala 27:72]
+  wire [6:0] _T_1410 = _T_1407 | _T_1408; // @[Mux.scala 27:72]
+  wire [6:0] _T_1411 = _T_1410 | _T_1409; // @[Mux.scala 27:72]
+  wire [6:0] l3_31 = l2[31:25] | _T_1411; // @[ifu_compress_ctl.scala 151:25]
+  wire [12:0] l3_24 = l2[24:12]; // @[ifu_compress_ctl.scala 154:17]
+  wire [4:0] _T_1417 = {sbr8d[4:1],sbr8d[8]}; // @[Cat.scala 29:58]
+  wire [4:0] _T_1422 = _T_234 ? _T_1417 : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1423 = _T_854 ? uswimm6d[4:0] : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1424 = _T_807 ? uswspimm7d[4:0] : 5'h0; // @[Mux.scala 27:72]
+  wire [4:0] _T_1425 = _T_1422 | _T_1423; // @[Mux.scala 27:72]
+  wire [4:0] _T_1426 = _T_1425 | _T_1424; // @[Mux.scala 27:72]
+  wire [4:0] l3_11 = l2[11:7] | _T_1426; // @[ifu_compress_ctl.scala 156:24]
+  wire [31:0] l3 = {l3_31,l3_24,l3_11,l2[6:0]}; // @[Cat.scala 29:58]
+  wire  _T_1437 = _T_4 & _T_487; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1438 = _T_1437 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1439 = _T_1438 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1442 = _T_1439 & _T_147; // @[ifu_compress_ctl.scala 162:39]
+  wire  _T_1450 = _T_1437 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1451 = _T_1450 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1454 = _T_1451 & _T_147; // @[ifu_compress_ctl.scala 162:79]
+  wire  _T_1455 = _T_1442 | _T_1454; // @[ifu_compress_ctl.scala 162:54]
+  wire  _T_1464 = _T_642 & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1465 = _T_1464 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1466 = _T_1455 | _T_1465; // @[ifu_compress_ctl.scala 162:94]
+  wire  _T_1474 = _T_1437 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1475 = _T_1474 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1478 = _T_1475 & _T_147; // @[ifu_compress_ctl.scala 163:55]
+  wire  _T_1479 = _T_1466 | _T_1478; // @[ifu_compress_ctl.scala 163:30]
+  wire  _T_1487 = _T_1437 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1488 = _T_1487 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1491 = _T_1488 & _T_147; // @[ifu_compress_ctl.scala 163:96]
+  wire  _T_1492 = _T_1479 | _T_1491; // @[ifu_compress_ctl.scala 163:70]
+  wire  _T_1501 = _T_642 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1502 = _T_1501 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1503 = _T_1492 | _T_1502; // @[ifu_compress_ctl.scala 163:111]
+  wire  _T_1510 = io_din[15] & _T_487; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1511 = _T_1510 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1512 = _T_1511 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1513 = _T_1503 | _T_1512; // @[ifu_compress_ctl.scala 164:29]
+  wire  _T_1521 = _T_1437 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1522 = _T_1521 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1525 = _T_1522 & _T_147; // @[ifu_compress_ctl.scala 164:79]
+  wire  _T_1526 = _T_1513 | _T_1525; // @[ifu_compress_ctl.scala 164:54]
+  wire  _T_1533 = _T_487 & io_din[6]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1534 = _T_1533 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1535 = _T_1534 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1536 = _T_1526 | _T_1535; // @[ifu_compress_ctl.scala 164:94]
+  wire  _T_1545 = _T_642 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1546 = _T_1545 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1547 = _T_1536 | _T_1546; // @[ifu_compress_ctl.scala 164:118]
+  wire  _T_1555 = _T_1437 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1556 = _T_1555 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1559 = _T_1556 & _T_147; // @[ifu_compress_ctl.scala 165:28]
+  wire  _T_1560 = _T_1547 | _T_1559; // @[ifu_compress_ctl.scala 164:144]
+  wire  _T_1567 = _T_487 & io_din[5]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1568 = _T_1567 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1569 = _T_1568 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1570 = _T_1560 | _T_1569; // @[ifu_compress_ctl.scala 165:43]
+  wire  _T_1579 = _T_642 & io_din[10]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1580 = _T_1579 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1581 = _T_1570 | _T_1580; // @[ifu_compress_ctl.scala 165:67]
+  wire  _T_1589 = _T_1437 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1590 = _T_1589 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1593 = _T_1590 & _T_147; // @[ifu_compress_ctl.scala 166:28]
+  wire  _T_1594 = _T_1581 | _T_1593; // @[ifu_compress_ctl.scala 165:94]
+  wire  _T_1602 = io_din[12] & io_din[11]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1603 = _T_1602 & _T_38; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1604 = _T_1603 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1605 = _T_1604 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1606 = _T_1594 | _T_1605; // @[ifu_compress_ctl.scala 166:43]
+  wire  _T_1615 = _T_642 & io_din[9]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1616 = _T_1615 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1617 = _T_1606 | _T_1616; // @[ifu_compress_ctl.scala 166:71]
+  wire  _T_1625 = _T_1437 & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1626 = _T_1625 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1629 = _T_1626 & _T_147; // @[ifu_compress_ctl.scala 167:28]
+  wire  _T_1630 = _T_1617 | _T_1629; // @[ifu_compress_ctl.scala 166:97]
+  wire  _T_1636 = io_din[13] & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1637 = _T_1636 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1638 = _T_1637 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1639 = _T_1630 | _T_1638; // @[ifu_compress_ctl.scala 167:43]
+  wire  _T_1648 = _T_642 & io_din[8]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1649 = _T_1648 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1650 = _T_1639 | _T_1649; // @[ifu_compress_ctl.scala 167:67]
+  wire  _T_1658 = _T_1437 & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1659 = _T_1658 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1662 = _T_1659 & _T_147; // @[ifu_compress_ctl.scala 168:28]
+  wire  _T_1663 = _T_1650 | _T_1662; // @[ifu_compress_ctl.scala 167:93]
+  wire  _T_1669 = io_din[13] & io_din[4]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1670 = _T_1669 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1671 = _T_1670 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1672 = _T_1663 | _T_1671; // @[ifu_compress_ctl.scala 168:43]
+  wire  _T_1680 = _T_1437 & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1681 = _T_1680 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1684 = _T_1681 & _T_147; // @[ifu_compress_ctl.scala 168:91]
+  wire  _T_1685 = _T_1672 | _T_1684; // @[ifu_compress_ctl.scala 168:66]
+  wire  _T_1694 = _T_642 & io_din[7]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1695 = _T_1694 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1696 = _T_1685 | _T_1695; // @[ifu_compress_ctl.scala 168:106]
+  wire  _T_1702 = io_din[13] & io_din[3]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1703 = _T_1702 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1704 = _T_1703 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1705 = _T_1696 | _T_1704; // @[ifu_compress_ctl.scala 169:29]
+  wire  _T_1711 = io_din[13] & io_din[2]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1712 = _T_1711 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1713 = _T_1712 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1714 = _T_1705 | _T_1713; // @[ifu_compress_ctl.scala 169:52]
+  wire  _T_1720 = io_din[14] & _T_4; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1721 = _T_1720 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1722 = _T_1714 | _T_1721; // @[ifu_compress_ctl.scala 169:75]
+  wire  _T_1731 = _T_703 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1732 = _T_1731 & io_din[0]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1733 = _T_1722 | _T_1732; // @[ifu_compress_ctl.scala 169:98]
+  wire  _T_1740 = _T_820 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1741 = _T_1740 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1744 = _T_1741 & _T_147; // @[ifu_compress_ctl.scala 170:54]
+  wire  _T_1745 = _T_1733 | _T_1744; // @[ifu_compress_ctl.scala 170:29]
+  wire  _T_1754 = _T_642 & _T_487; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1755 = _T_1754 & io_din[1]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1758 = _T_1755 & _T_147; // @[ifu_compress_ctl.scala 170:96]
+  wire  _T_1759 = _T_1745 | _T_1758; // @[ifu_compress_ctl.scala 170:69]
+  wire  _T_1768 = _T_642 & io_din[12]; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1769 = _T_1768 & _T_830; // @[ifu_compress_ctl.scala 12:110]
+  wire  _T_1770 = _T_1759 | _T_1769; // @[ifu_compress_ctl.scala 170:111]
+  wire  _T_1777 = _T_1720 & _T_147; // @[ifu_compress_ctl.scala 171:50]
+  wire  legal = _T_1770 | _T_1777; // @[ifu_compress_ctl.scala 171:30]
+  wire [9:0] _T_1787 = {legal,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
+  wire [18:0] _T_1796 = {_T_1787,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
+  wire [27:0] _T_1805 = {_T_1796,legal,legal,legal,legal,legal,legal,legal,legal,legal}; // @[Cat.scala 29:58]
+  wire [31:0] _T_1809 = {_T_1805,legal,legal,legal,legal}; // @[Cat.scala 29:58]
+  assign io_dout = l3 & _T_1809; // @[ifu_compress_ctl.scala 173:10]
+endmodule
+module ifu_aln_ctl(
+  input         clock,
+  input         reset,
+  input         io_scan_mode,
+  input         io_active_clk,
+  input         io_ifu_async_error_start,
+  input         io_iccm_rd_ecc_double_err,
+  input         io_ic_access_fault_f,
+  input  [1:0]  io_ic_access_fault_type_f,
+  input  [7:0]  io_ifu_bp_fghr_f,
+  input  [30:0] io_ifu_bp_btb_target_f,
+  input  [11:0] io_ifu_bp_poffset_f,
+  input  [1:0]  io_ifu_bp_hist0_f,
+  input  [1:0]  io_ifu_bp_hist1_f,
+  input  [1:0]  io_ifu_bp_pc4_f,
+  input  [1:0]  io_ifu_bp_way_f,
+  input  [1:0]  io_ifu_bp_valid_f,
+  input  [1:0]  io_ifu_bp_ret_f,
+  input         io_exu_flush_final,
+  input         io_dec_i0_decode_d,
+  output [15:0] io_dec_aln_aln_dec_ifu_i0_cinst,
+  output        io_dec_aln_aln_ib_ifu_i0_icaf,
+  output [1:0]  io_dec_aln_aln_ib_ifu_i0_icaf_type,
+  output        io_dec_aln_aln_ib_ifu_i0_icaf_second,
+  output        io_dec_aln_aln_ib_ifu_i0_dbecc,
+  output [7:0]  io_dec_aln_aln_ib_ifu_i0_bp_index,
+  output [7:0]  io_dec_aln_aln_ib_ifu_i0_bp_fghr,
+  output [4:0]  io_dec_aln_aln_ib_ifu_i0_bp_btag,
+  output        io_dec_aln_aln_ib_ifu_i0_valid,
+  output [31:0] io_dec_aln_aln_ib_ifu_i0_instr,
+  output [30:0] io_dec_aln_aln_ib_ifu_i0_pc,
+  output        io_dec_aln_aln_ib_ifu_i0_pc4,
+  output        io_dec_aln_aln_ib_i0_brp_valid,
+  output [11:0] io_dec_aln_aln_ib_i0_brp_bits_toffset,
+  output [1:0]  io_dec_aln_aln_ib_i0_brp_bits_hist,
+  output        io_dec_aln_aln_ib_i0_brp_bits_br_error,
+  output        io_dec_aln_aln_ib_i0_brp_bits_br_start_error,
+  output        io_dec_aln_aln_ib_i0_brp_bits_bank,
+  output [30:0] io_dec_aln_aln_ib_i0_brp_bits_prett,
+  output        io_dec_aln_aln_ib_i0_brp_bits_way,
+  output        io_dec_aln_aln_ib_i0_brp_bits_ret,
+  output        io_dec_aln_ifu_pmu_instr_aligned,
+  input  [31:0] io_ifu_fetch_data_f,
+  input  [1:0]  io_ifu_fetch_val,
+  input  [30:0] io_ifu_fetch_pc,
+  output        io_ifu_fb_consume1,
+  output        io_ifu_fb_consume2
+);
+`ifdef RANDOMIZE_REG_INIT
+  reg [31:0] _RAND_0;
+  reg [31:0] _RAND_1;
+  reg [31:0] _RAND_2;
+  reg [31:0] _RAND_3;
+  reg [31:0] _RAND_4;
+  reg [31:0] _RAND_5;
+  reg [31:0] _RAND_6;
+  reg [31:0] _RAND_7;
+  reg [31:0] _RAND_8;
+  reg [31:0] _RAND_9;
+  reg [31:0] _RAND_10;
+  reg [31:0] _RAND_11;
+  reg [31:0] _RAND_12;
+  reg [31:0] _RAND_13;
+  reg [31:0] _RAND_14;
+  reg [31:0] _RAND_15;
+  reg [31:0] _RAND_16;
+  reg [31:0] _RAND_17;
+  reg [63:0] _RAND_18;
+  reg [63:0] _RAND_19;
+  reg [63:0] _RAND_20;
+`endif // RANDOMIZE_REG_INIT
+  wire  rvclkhdr_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_1_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_1_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_2_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_2_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_3_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_3_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_4_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_4_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_5_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_5_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_6_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_6_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_7_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_7_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_8_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_8_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_9_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_9_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_10_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_10_io_en; // @[lib.scala 404:23]
+  wire  rvclkhdr_11_io_clk; // @[lib.scala 404:23]
+  wire  rvclkhdr_11_io_en; // @[lib.scala 404:23]
+  wire [15:0] decompressed_io_din; // @[ifu_aln_ctl.scala 353:28]
+  wire [31:0] decompressed_io_dout; // @[ifu_aln_ctl.scala 353:28]
+  reg  error_stall; // @[ifu_aln_ctl.scala 103:51]
+  wire  _T = error_stall | io_ifu_async_error_start; // @[ifu_aln_ctl.scala 100:34]
+  wire  _T_1 = ~io_exu_flush_final; // @[ifu_aln_ctl.scala 100:64]
+  reg [1:0] wrptr; // @[ifu_aln_ctl.scala 105:48]
+  reg [1:0] rdptr; // @[ifu_aln_ctl.scala 107:48]
+  reg [1:0] f2val; // @[ifu_aln_ctl.scala 109:48]
+  reg [1:0] f1val; // @[ifu_aln_ctl.scala 110:48]
+  reg [1:0] f0val; // @[ifu_aln_ctl.scala 111:48]
+  reg  q2off; // @[ifu_aln_ctl.scala 113:48]
+  reg  q1off; // @[ifu_aln_ctl.scala 114:48]
+  reg  q0off; // @[ifu_aln_ctl.scala 115:48]
+  wire  _T_785 = ~error_stall; // @[ifu_aln_ctl.scala 396:39]
+  wire  i0_shift = io_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 396:37]
+  wire  _T_186 = rdptr == 2'h0; // @[ifu_aln_ctl.scala 170:31]
+  wire  _T_189 = _T_186 & q0off; // @[Mux.scala 27:72]
+  wire  _T_187 = rdptr == 2'h1; // @[ifu_aln_ctl.scala 171:11]
+  wire  _T_190 = _T_187 & q1off; // @[Mux.scala 27:72]
+  wire  _T_192 = _T_189 | _T_190; // @[Mux.scala 27:72]
+  wire  _T_188 = rdptr == 2'h2; // @[ifu_aln_ctl.scala 172:11]
+  wire  _T_191 = _T_188 & q2off; // @[Mux.scala 27:72]
+  wire  q0ptr = _T_192 | _T_191; // @[Mux.scala 27:72]
+  wire  _T_202 = ~q0ptr; // @[ifu_aln_ctl.scala 176:26]
+  wire [1:0] q0sel = {q0ptr,_T_202}; // @[Cat.scala 29:58]
+  wire [2:0] qren = {_T_188,_T_187,_T_186}; // @[Cat.scala 29:58]
+  reg [31:0] q1; // @[Reg.scala 27:20]
+  reg [31:0] q0; // @[Reg.scala 27:20]
+  wire [63:0] _T_479 = {q1,q0}; // @[Cat.scala 29:58]
+  wire [63:0] _T_486 = qren[0] ? _T_479 : 64'h0; // @[Mux.scala 27:72]
+  reg [31:0] q2; // @[Reg.scala 27:20]
+  wire [63:0] _T_482 = {q2,q1}; // @[Cat.scala 29:58]
+  wire [63:0] _T_487 = qren[1] ? _T_482 : 64'h0; // @[Mux.scala 27:72]
+  wire [63:0] _T_489 = _T_486 | _T_487; // @[Mux.scala 27:72]
+  wire [63:0] _T_485 = {q0,q2}; // @[Cat.scala 29:58]
+  wire [63:0] _T_488 = qren[2] ? _T_485 : 64'h0; // @[Mux.scala 27:72]
+  wire [63:0] qeff = _T_489 | _T_488; // @[Mux.scala 27:72]
+  wire [31:0] q0eff = qeff[31:0]; // @[ifu_aln_ctl.scala 295:42]
+  wire [31:0] _T_496 = q0sel[0] ? q0eff : 32'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_497 = q0sel[1] ? q0eff[31:16] : 16'h0; // @[Mux.scala 27:72]
+  wire [31:0] _GEN_12 = {{16'd0}, _T_497}; // @[Mux.scala 27:72]
+  wire [31:0] q0final = _T_496 | _GEN_12; // @[Mux.scala 27:72]
+  wire [31:0] _T_520 = f0val[1] ? q0final : 32'h0; // @[Mux.scala 27:72]
+  wire  _T_513 = ~f0val[1]; // @[ifu_aln_ctl.scala 302:58]
+  wire  _T_515 = _T_513 & f0val[0]; // @[ifu_aln_ctl.scala 302:68]
+  wire  _T_197 = _T_186 & q1off; // @[Mux.scala 27:72]
+  wire  _T_198 = _T_187 & q2off; // @[Mux.scala 27:72]
+  wire  _T_200 = _T_197 | _T_198; // @[Mux.scala 27:72]
+  wire  _T_199 = _T_188 & q0off; // @[Mux.scala 27:72]
+  wire  q1ptr = _T_200 | _T_199; // @[Mux.scala 27:72]
+  wire  _T_203 = ~q1ptr; // @[ifu_aln_ctl.scala 178:26]
+  wire [1:0] q1sel = {q1ptr,_T_203}; // @[Cat.scala 29:58]
+  wire [31:0] q1eff = qeff[63:32]; // @[ifu_aln_ctl.scala 295:29]
+  wire [15:0] _T_506 = q1sel[0] ? q1eff[15:0] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] _T_507 = q1sel[1] ? q1eff[31:16] : 16'h0; // @[Mux.scala 27:72]
+  wire [15:0] q1final = _T_506 | _T_507; // @[Mux.scala 27:72]
+  wire [31:0] _T_519 = {q1final,q0final[15:0]}; // @[Cat.scala 29:58]
+  wire [31:0] _T_521 = _T_515 ? _T_519 : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] aligndata = _T_520 | _T_521; // @[Mux.scala 27:72]
+  wire  first4B = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 335:29]
+  wire  first2B = ~first4B; // @[ifu_aln_ctl.scala 337:17]
+  wire  shift_2B = i0_shift & first2B; // @[ifu_aln_ctl.scala 400:24]
+  wire [1:0] _T_443 = {1'h0,f0val[1]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_448 = shift_2B ? _T_443 : 2'h0; // @[Mux.scala 27:72]
+  wire  _T_444 = ~shift_2B; // @[ifu_aln_ctl.scala 285:18]
+  wire  shift_4B = i0_shift & first4B; // @[ifu_aln_ctl.scala 401:24]
+  wire  _T_445 = ~shift_4B; // @[ifu_aln_ctl.scala 285:30]
+  wire  _T_446 = _T_444 & _T_445; // @[ifu_aln_ctl.scala 285:28]
+  wire [1:0] _T_449 = _T_446 ? f0val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] sf0val = _T_448 | _T_449; // @[Mux.scala 27:72]
+  wire  sf0_valid = sf0val[0]; // @[ifu_aln_ctl.scala 236:22]
+  wire  _T_351 = ~sf0_valid; // @[ifu_aln_ctl.scala 257:26]
+  wire  _T_802 = f0val[0] & _T_513; // @[ifu_aln_ctl.scala 404:28]
+  wire  f1_shift_2B = _T_802 & shift_4B; // @[ifu_aln_ctl.scala 404:40]
+  wire  _T_417 = f1_shift_2B & f1val[1]; // @[Mux.scala 27:72]
+  wire  _T_416 = ~f1_shift_2B; // @[ifu_aln_ctl.scala 278:53]
+  wire [1:0] _T_418 = _T_416 ? f1val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_13 = {{1'd0}, _T_417}; // @[Mux.scala 27:72]
+  wire [1:0] sf1val = _GEN_13 | _T_418; // @[Mux.scala 27:72]
+  wire  sf1_valid = sf1val[0]; // @[ifu_aln_ctl.scala 235:22]
+  wire  _T_352 = _T_351 & sf1_valid; // @[ifu_aln_ctl.scala 257:37]
+  wire  f2_valid = f2val[0]; // @[ifu_aln_ctl.scala 234:20]
+  wire  _T_353 = _T_352 & f2_valid; // @[ifu_aln_ctl.scala 257:50]
+  wire  ifvalid = io_ifu_fetch_val[0]; // @[ifu_aln_ctl.scala 245:30]
+  wire  _T_354 = _T_353 & ifvalid; // @[ifu_aln_ctl.scala 257:62]
+  wire  _T_355 = sf0_valid & sf1_valid; // @[ifu_aln_ctl.scala 258:37]
+  wire  _T_356 = ~f2_valid; // @[ifu_aln_ctl.scala 258:52]
+  wire  _T_357 = _T_355 & _T_356; // @[ifu_aln_ctl.scala 258:50]
+  wire  _T_358 = _T_357 & ifvalid; // @[ifu_aln_ctl.scala 258:62]
+  wire  fetch_to_f2 = _T_354 | _T_358; // @[ifu_aln_ctl.scala 257:74]
+  reg [30:0] f2pc; // @[Reg.scala 27:20]
+  wire  _T_335 = ~sf1_valid; // @[ifu_aln_ctl.scala 253:39]
+  wire  _T_336 = _T_351 & _T_335; // @[ifu_aln_ctl.scala 253:37]
+  wire  _T_337 = _T_336 & f2_valid; // @[ifu_aln_ctl.scala 253:50]
+  wire  _T_338 = _T_337 & ifvalid; // @[ifu_aln_ctl.scala 253:62]
+  wire  _T_342 = _T_352 & _T_356; // @[ifu_aln_ctl.scala 254:50]
+  wire  _T_343 = _T_342 & ifvalid; // @[ifu_aln_ctl.scala 254:62]
+  wire  _T_344 = _T_338 | _T_343; // @[ifu_aln_ctl.scala 253:74]
+  wire  _T_346 = sf0_valid & _T_335; // @[ifu_aln_ctl.scala 255:37]
+  wire  _T_348 = _T_346 & _T_356; // @[ifu_aln_ctl.scala 255:50]
+  wire  _T_349 = _T_348 & ifvalid; // @[ifu_aln_ctl.scala 255:62]
+  wire  fetch_to_f1 = _T_344 | _T_349; // @[ifu_aln_ctl.scala 254:74]
+  wire  _T_25 = fetch_to_f1 | _T_353; // @[ifu_aln_ctl.scala 135:33]
+  wire  f1_shift_wr_en = _T_25 | f1_shift_2B; // @[ifu_aln_ctl.scala 135:47]
+  reg [30:0] f1pc; // @[Reg.scala 27:20]
+  wire [30:0] _T_375 = fetch_to_f1 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_376 = _T_353 ? f2pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_378 = _T_375 | _T_376; // @[Mux.scala 27:72]
+  wire  _T_371 = ~fetch_to_f1; // @[ifu_aln_ctl.scala 268:6]
+  wire  _T_372 = ~_T_353; // @[ifu_aln_ctl.scala 268:21]
+  wire  _T_373 = _T_371 & _T_372; // @[ifu_aln_ctl.scala 268:19]
+  wire [30:0] _T_363 = f1_shift_2B ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
+  wire [30:0] f1pc_plus1 = f1pc + 31'h1; // @[ifu_aln_ctl.scala 262:25]
+  wire [30:0] _T_364 = _T_363 & f1pc_plus1; // @[ifu_aln_ctl.scala 264:38]
+  wire [30:0] _T_367 = _T_416 ? 31'h7fffffff : 31'h0; // @[Bitwise.scala 72:12]
+  wire [30:0] _T_368 = _T_367 & f1pc; // @[ifu_aln_ctl.scala 264:78]
+  wire [30:0] sf1pc = _T_364 | _T_368; // @[ifu_aln_ctl.scala 264:52]
+  wire [30:0] _T_377 = _T_373 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] f1pc_in = _T_378 | _T_377; // @[Mux.scala 27:72]
+  wire  _T_332 = _T_336 & _T_356; // @[ifu_aln_ctl.scala 252:50]
+  wire  fetch_to_f0 = _T_332 & ifvalid; // @[ifu_aln_ctl.scala 252:62]
+  wire  _T_27 = fetch_to_f0 | _T_337; // @[ifu_aln_ctl.scala 136:33]
+  wire  _T_28 = _T_27 | _T_352; // @[ifu_aln_ctl.scala 136:47]
+  wire  _T_29 = _T_28 | shift_2B; // @[ifu_aln_ctl.scala 136:61]
+  wire  f0_shift_wr_en = _T_29 | shift_4B; // @[ifu_aln_ctl.scala 136:72]
+  reg [30:0] f0pc; // @[Reg.scala 27:20]
+  wire [30:0] _T_390 = fetch_to_f0 ? io_ifu_fetch_pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_391 = _T_337 ? f2pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_394 = _T_390 | _T_391; // @[Mux.scala 27:72]
+  wire [30:0] _T_392 = _T_352 ? sf1pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_395 = _T_394 | _T_392; // @[Mux.scala 27:72]
+  wire  _T_384 = ~fetch_to_f0; // @[ifu_aln_ctl.scala 273:24]
+  wire  _T_385 = ~_T_337; // @[ifu_aln_ctl.scala 273:39]
+  wire  _T_386 = _T_384 & _T_385; // @[ifu_aln_ctl.scala 273:37]
+  wire  _T_387 = ~_T_352; // @[ifu_aln_ctl.scala 273:54]
+  wire  _T_388 = _T_386 & _T_387; // @[ifu_aln_ctl.scala 273:52]
+  wire [30:0] f0pc_plus1 = f0pc + 31'h1; // @[ifu_aln_ctl.scala 260:25]
+  wire [30:0] _T_393 = _T_388 ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] f0pc_in = _T_395 | _T_393; // @[Mux.scala 27:72]
+  wire  _T_35 = wrptr == 2'h2; // @[ifu_aln_ctl.scala 140:21]
+  wire  _T_36 = _T_35 & ifvalid; // @[ifu_aln_ctl.scala 140:29]
+  wire  _T_37 = wrptr == 2'h1; // @[ifu_aln_ctl.scala 140:46]
+  wire  _T_38 = _T_37 & ifvalid; // @[ifu_aln_ctl.scala 140:54]
+  wire  _T_39 = wrptr == 2'h0; // @[ifu_aln_ctl.scala 140:71]
+  wire  _T_40 = _T_39 & ifvalid; // @[ifu_aln_ctl.scala 140:79]
+  wire [2:0] qwen = {_T_36,_T_38,_T_40}; // @[Cat.scala 29:58]
+  reg [11:0] brdata2; // @[Reg.scala 27:20]
+  wire [5:0] _T_241 = {io_ifu_bp_hist1_f[0],io_ifu_bp_hist0_f[0],io_ifu_bp_pc4_f[0],io_ifu_bp_way_f[0],io_ifu_bp_valid_f[0],io_ifu_bp_ret_f[0]}; // @[Cat.scala 29:58]
+  wire [11:0] brdata_in = {io_ifu_bp_hist1_f[1],io_ifu_bp_hist0_f[1],io_ifu_bp_pc4_f[1],io_ifu_bp_way_f[1],io_ifu_bp_valid_f[1],io_ifu_bp_ret_f[1],_T_241}; // @[Cat.scala 29:58]
+  reg [11:0] brdata1; // @[Reg.scala 27:20]
+  reg [11:0] brdata0; // @[Reg.scala 27:20]
+  reg [54:0] misc2; // @[Reg.scala 27:20]
+  wire [54:0] misc_data_in = {io_iccm_rd_ecc_double_err,io_ic_access_fault_f,io_ic_access_fault_type_f,io_ifu_bp_btb_target_f,io_ifu_bp_poffset_f,io_ifu_bp_fghr_f}; // @[Cat.scala 29:58]
+  reg [54:0] misc1; // @[Reg.scala 27:20]
+  reg [54:0] misc0; // @[Reg.scala 27:20]
+  wire  _T_44 = qren[0] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 144:34]
+  wire  _T_46 = _T_44 & _T_1; // @[ifu_aln_ctl.scala 144:55]
+  wire  _T_49 = qren[1] & io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 145:14]
+  wire  _T_51 = _T_49 & _T_1; // @[ifu_aln_ctl.scala 145:35]
+  wire  _T_59 = qren[0] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 147:14]
+  wire  _T_61 = _T_59 & _T_1; // @[ifu_aln_ctl.scala 147:35]
+  wire  _T_69 = qren[2] & io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 149:14]
+  wire  _T_71 = _T_69 & _T_1; // @[ifu_aln_ctl.scala 149:35]
+  wire  _T_73 = ~io_ifu_fb_consume1; // @[ifu_aln_ctl.scala 150:6]
+  wire  _T_74 = ~io_ifu_fb_consume2; // @[ifu_aln_ctl.scala 150:28]
+  wire  _T_75 = _T_73 & _T_74; // @[ifu_aln_ctl.scala 150:26]
+  wire  _T_77 = _T_75 & _T_1; // @[ifu_aln_ctl.scala 150:48]
+  wire [1:0] _T_80 = _T_51 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_82 = _T_61 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_85 = _T_77 ? rdptr : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_14 = {{1'd0}, _T_46}; // @[Mux.scala 27:72]
+  wire [1:0] _T_86 = _GEN_14 | _T_80; // @[Mux.scala 27:72]
+  wire [1:0] _T_88 = _T_86 | _T_82; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_15 = {{1'd0}, _T_71}; // @[Mux.scala 27:72]
+  wire [1:0] _T_90 = _T_88 | _GEN_15; // @[Mux.scala 27:72]
+  wire  _T_95 = qwen[0] & _T_1; // @[ifu_aln_ctl.scala 153:34]
+  wire  _T_99 = qwen[1] & _T_1; // @[ifu_aln_ctl.scala 154:14]
+  wire  _T_105 = ~ifvalid; // @[ifu_aln_ctl.scala 156:6]
+  wire  _T_107 = _T_105 & _T_1; // @[ifu_aln_ctl.scala 156:15]
+  wire [1:0] _T_110 = _T_99 ? 2'h2 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_112 = _T_107 ? wrptr : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_16 = {{1'd0}, _T_95}; // @[Mux.scala 27:72]
+  wire [1:0] _T_113 = _GEN_16 | _T_110; // @[Mux.scala 27:72]
+  wire  _T_118 = ~qwen[2]; // @[ifu_aln_ctl.scala 158:26]
+  wire  _T_120 = _T_118 & _T_188; // @[ifu_aln_ctl.scala 158:35]
+  wire  _T_795 = shift_2B & f0val[0]; // @[Mux.scala 27:72]
+  wire  _T_796 = shift_4B & _T_802; // @[Mux.scala 27:72]
+  wire  f0_shift_2B = _T_795 | _T_796; // @[Mux.scala 27:72]
+  wire  _T_122 = q2off | f0_shift_2B; // @[ifu_aln_ctl.scala 158:74]
+  wire  _T_126 = _T_118 & _T_187; // @[ifu_aln_ctl.scala 159:15]
+  wire  _T_128 = q2off | f1_shift_2B; // @[ifu_aln_ctl.scala 159:54]
+  wire  _T_132 = _T_118 & _T_186; // @[ifu_aln_ctl.scala 160:15]
+  wire  _T_134 = _T_120 & _T_122; // @[Mux.scala 27:72]
+  wire  _T_135 = _T_126 & _T_128; // @[Mux.scala 27:72]
+  wire  _T_136 = _T_132 & q2off; // @[Mux.scala 27:72]
+  wire  _T_137 = _T_134 | _T_135; // @[Mux.scala 27:72]
+  wire  _T_141 = ~qwen[1]; // @[ifu_aln_ctl.scala 162:26]
+  wire  _T_143 = _T_141 & _T_187; // @[ifu_aln_ctl.scala 162:35]
+  wire  _T_145 = q1off | f0_shift_2B; // @[ifu_aln_ctl.scala 162:74]
+  wire  _T_149 = _T_141 & _T_186; // @[ifu_aln_ctl.scala 163:15]
+  wire  _T_151 = q1off | f1_shift_2B; // @[ifu_aln_ctl.scala 163:54]
+  wire  _T_155 = _T_141 & _T_188; // @[ifu_aln_ctl.scala 164:15]
+  wire  _T_157 = _T_143 & _T_145; // @[Mux.scala 27:72]
+  wire  _T_158 = _T_149 & _T_151; // @[Mux.scala 27:72]
+  wire  _T_159 = _T_155 & q1off; // @[Mux.scala 27:72]
+  wire  _T_160 = _T_157 | _T_158; // @[Mux.scala 27:72]
+  wire  _T_164 = ~qwen[0]; // @[ifu_aln_ctl.scala 166:26]
+  wire  _T_166 = _T_164 & _T_186; // @[ifu_aln_ctl.scala 166:35]
+  wire  _T_168 = q0off | f0_shift_2B; // @[ifu_aln_ctl.scala 166:76]
+  wire  _T_172 = _T_164 & _T_188; // @[ifu_aln_ctl.scala 167:35]
+  wire  _T_174 = q0off | f1_shift_2B; // @[ifu_aln_ctl.scala 167:76]
+  wire  _T_178 = _T_164 & _T_187; // @[ifu_aln_ctl.scala 168:35]
+  wire  _T_180 = _T_166 & _T_168; // @[Mux.scala 27:72]
+  wire  _T_181 = _T_172 & _T_174; // @[Mux.scala 27:72]
+  wire  _T_182 = _T_178 & q0off; // @[Mux.scala 27:72]
+  wire  _T_183 = _T_180 | _T_181; // @[Mux.scala 27:72]
+  wire [109:0] _T_211 = {misc1,misc0}; // @[Cat.scala 29:58]
+  wire [109:0] _T_214 = {misc2,misc1}; // @[Cat.scala 29:58]
+  wire [109:0] _T_217 = {misc0,misc2}; // @[Cat.scala 29:58]
+  wire [109:0] _T_218 = qren[0] ? _T_211 : 110'h0; // @[Mux.scala 27:72]
+  wire [109:0] _T_219 = qren[1] ? _T_214 : 110'h0; // @[Mux.scala 27:72]
+  wire [109:0] _T_220 = qren[2] ? _T_217 : 110'h0; // @[Mux.scala 27:72]
+  wire [109:0] _T_221 = _T_218 | _T_219; // @[Mux.scala 27:72]
+  wire [109:0] misceff = _T_221 | _T_220; // @[Mux.scala 27:72]
+  wire [54:0] misc1eff = misceff[109:55]; // @[ifu_aln_ctl.scala 187:25]
+  wire [54:0] misc0eff = misceff[54:0]; // @[ifu_aln_ctl.scala 188:25]
+  wire  f1dbecc = misc1eff[54]; // @[ifu_aln_ctl.scala 191:25]
+  wire  f1icaf = misc1eff[53]; // @[ifu_aln_ctl.scala 192:21]
+  wire [1:0] f1ictype = misc1eff[52:51]; // @[ifu_aln_ctl.scala 193:26]
+  wire [30:0] f1prett = misc1eff[50:20]; // @[ifu_aln_ctl.scala 194:25]
+  wire [11:0] f1poffset = misc1eff[19:8]; // @[ifu_aln_ctl.scala 195:27]
+  wire [7:0] f1fghr = misc1eff[7:0]; // @[ifu_aln_ctl.scala 196:24]
+  wire  f0dbecc = misc0eff[54]; // @[ifu_aln_ctl.scala 198:25]
+  wire  f0icaf = misc0eff[53]; // @[ifu_aln_ctl.scala 199:21]
+  wire [1:0] f0ictype = misc0eff[52:51]; // @[ifu_aln_ctl.scala 200:26]
+  wire [30:0] f0prett = misc0eff[50:20]; // @[ifu_aln_ctl.scala 201:25]
+  wire [11:0] f0poffset = misc0eff[19:8]; // @[ifu_aln_ctl.scala 202:27]
+  wire [7:0] f0fghr = misc0eff[7:0]; // @[ifu_aln_ctl.scala 203:24]
+  wire [23:0] _T_250 = {brdata1,brdata0}; // @[Cat.scala 29:58]
+  wire [23:0] _T_253 = {brdata2,brdata1}; // @[Cat.scala 29:58]
+  wire [23:0] _T_256 = {brdata0,brdata2}; // @[Cat.scala 29:58]
+  wire [23:0] _T_257 = qren[0] ? _T_250 : 24'h0; // @[Mux.scala 27:72]
+  wire [23:0] _T_258 = qren[1] ? _T_253 : 24'h0; // @[Mux.scala 27:72]
+  wire [23:0] _T_259 = qren[2] ? _T_256 : 24'h0; // @[Mux.scala 27:72]
+  wire [23:0] _T_260 = _T_257 | _T_258; // @[Mux.scala 27:72]
+  wire [23:0] brdataeff = _T_260 | _T_259; // @[Mux.scala 27:72]
+  wire [11:0] brdata0eff = brdataeff[11:0]; // @[ifu_aln_ctl.scala 214:43]
+  wire [11:0] brdata1eff = brdataeff[23:12]; // @[ifu_aln_ctl.scala 214:61]
+  wire [11:0] _T_267 = q0sel[0] ? brdata0eff : 12'h0; // @[Mux.scala 27:72]
+  wire [5:0] _T_268 = q0sel[1] ? brdata0eff[11:6] : 6'h0; // @[Mux.scala 27:72]
+  wire [11:0] _GEN_17 = {{6'd0}, _T_268}; // @[Mux.scala 27:72]
+  wire [11:0] brdata0final = _T_267 | _GEN_17; // @[Mux.scala 27:72]
+  wire [11:0] _T_275 = q1sel[0] ? brdata1eff : 12'h0; // @[Mux.scala 27:72]
+  wire [5:0] _T_276 = q1sel[1] ? brdata1eff[11:6] : 6'h0; // @[Mux.scala 27:72]
+  wire [11:0] _GEN_18 = {{6'd0}, _T_276}; // @[Mux.scala 27:72]
+  wire [11:0] brdata1final = _T_275 | _GEN_18; // @[Mux.scala 27:72]
+  wire [1:0] f0ret = {brdata0final[6],brdata0final[0]}; // @[Cat.scala 29:58]
+  wire [1:0] f0brend = {brdata0final[7],brdata0final[1]}; // @[Cat.scala 29:58]
+  wire [1:0] f0way = {brdata0final[8],brdata0final[2]}; // @[Cat.scala 29:58]
+  wire [1:0] f0pc4 = {brdata0final[9],brdata0final[3]}; // @[Cat.scala 29:58]
+  wire [1:0] f0hist0 = {brdata0final[10],brdata0final[4]}; // @[Cat.scala 29:58]
+  wire [1:0] f0hist1 = {brdata0final[11],brdata0final[5]}; // @[Cat.scala 29:58]
+  wire [1:0] f1ret = {brdata1final[6],brdata1final[0]}; // @[Cat.scala 29:58]
+  wire [1:0] f1brend = {brdata1final[7],brdata1final[1]}; // @[Cat.scala 29:58]
+  wire [1:0] f1way = {brdata1final[8],brdata1final[2]}; // @[Cat.scala 29:58]
+  wire [1:0] f1pc4 = {brdata1final[9],brdata1final[3]}; // @[Cat.scala 29:58]
+  wire [1:0] f1hist0 = {brdata1final[10],brdata1final[4]}; // @[Cat.scala 29:58]
+  wire [1:0] f1hist1 = {brdata1final[11],brdata1final[5]}; // @[Cat.scala 29:58]
+  wire  consume_fb0 = _T_351 & f0val[0]; // @[ifu_aln_ctl.scala 238:32]
+  wire  consume_fb1 = _T_335 & f1val[0]; // @[ifu_aln_ctl.scala 239:32]
+  wire  _T_311 = ~consume_fb1; // @[ifu_aln_ctl.scala 242:39]
+  wire  _T_312 = consume_fb0 & _T_311; // @[ifu_aln_ctl.scala 242:37]
+  wire  _T_315 = consume_fb0 & consume_fb1; // @[ifu_aln_ctl.scala 243:37]
+  wire  _T_399 = fetch_to_f2 & _T_1; // @[ifu_aln_ctl.scala 275:38]
+  wire  _T_401 = ~fetch_to_f2; // @[ifu_aln_ctl.scala 276:25]
+  wire  _T_403 = _T_401 & _T_372; // @[ifu_aln_ctl.scala 276:38]
+  wire  _T_405 = _T_403 & _T_385; // @[ifu_aln_ctl.scala 276:53]
+  wire  _T_407 = _T_405 & _T_1; // @[ifu_aln_ctl.scala 276:68]
+  wire [1:0] _T_409 = _T_399 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_410 = _T_407 ? f2val : 2'h0; // @[Mux.scala 27:72]
+  wire  _T_422 = fetch_to_f1 & _T_1; // @[ifu_aln_ctl.scala 280:39]
+  wire  _T_425 = _T_353 & _T_1; // @[ifu_aln_ctl.scala 281:54]
+  wire  _T_431 = _T_373 & _T_387; // @[ifu_aln_ctl.scala 282:54]
+  wire  _T_433 = _T_431 & _T_1; // @[ifu_aln_ctl.scala 282:69]
+  wire [1:0] _T_435 = _T_422 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_436 = _T_425 ? f2val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_437 = _T_433 ? sf1val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_438 = _T_435 | _T_436; // @[Mux.scala 27:72]
+  wire  _T_453 = fetch_to_f0 & _T_1; // @[ifu_aln_ctl.scala 287:38]
+  wire  _T_456 = _T_337 & _T_1; // @[ifu_aln_ctl.scala 288:54]
+  wire  _T_459 = _T_352 & _T_1; // @[ifu_aln_ctl.scala 289:69]
+  wire  _T_467 = _T_388 & _T_1; // @[ifu_aln_ctl.scala 290:69]
+  wire [1:0] _T_469 = _T_453 ? io_ifu_fetch_val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_470 = _T_456 ? f2val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_471 = _T_459 ? sf1val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_472 = _T_467 ? sf0val : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_473 = _T_469 | _T_470; // @[Mux.scala 27:72]
+  wire [1:0] _T_474 = _T_473 | _T_471; // @[Mux.scala 27:72]
+  wire [1:0] _T_530 = {f1val[0],1'h1}; // @[Cat.scala 29:58]
+  wire [1:0] _T_531 = f0val[1] ? 2'h3 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_532 = _T_515 ? _T_530 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignval = _T_531 | _T_532; // @[Mux.scala 27:72]
+  wire [1:0] _T_542 = {f1icaf,f0icaf}; // @[Cat.scala 29:58]
+  wire  _T_543 = f0val[1] & f0icaf; // @[Mux.scala 27:72]
+  wire [1:0] _T_544 = _T_515 ? _T_542 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _GEN_19 = {{1'd0}, _T_543}; // @[Mux.scala 27:72]
+  wire [1:0] alignicaf = _GEN_19 | _T_544; // @[Mux.scala 27:72]
+  wire [1:0] _T_549 = f0dbecc ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12]
+  wire [1:0] _T_555 = {f1dbecc,f0dbecc}; // @[Cat.scala 29:58]
+  wire [1:0] _T_556 = f0val[1] ? _T_549 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_557 = _T_515 ? _T_555 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] aligndbecc = _T_556 | _T_557; // @[Mux.scala 27:72]
+  wire [1:0] _T_568 = {f1brend[0],f0brend[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_569 = f0val[1] ? f0brend : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_570 = _T_515 ? _T_568 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignbrend = _T_569 | _T_570; // @[Mux.scala 27:72]
+  wire [1:0] _T_581 = {f1pc4[0],f0pc4[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_582 = f0val[1] ? f0pc4 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_583 = _T_515 ? _T_581 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignpc4 = _T_582 | _T_583; // @[Mux.scala 27:72]
+  wire [1:0] _T_594 = {f1ret[0],f0ret[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_595 = f0val[1] ? f0ret : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_596 = _T_515 ? _T_594 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignret = _T_595 | _T_596; // @[Mux.scala 27:72]
+  wire [1:0] _T_607 = {f1way[0],f0way[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_608 = f0val[1] ? f0way : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_609 = _T_515 ? _T_607 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignway = _T_608 | _T_609; // @[Mux.scala 27:72]
+  wire [1:0] _T_620 = {f1hist1[0],f0hist1[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_621 = f0val[1] ? f0hist1 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_622 = _T_515 ? _T_620 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignhist1 = _T_621 | _T_622; // @[Mux.scala 27:72]
+  wire [1:0] _T_633 = {f1hist0[0],f0hist0[0]}; // @[Cat.scala 29:58]
+  wire [1:0] _T_634 = f0val[1] ? f0hist0 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] _T_635 = _T_515 ? _T_633 : 2'h0; // @[Mux.scala 27:72]
+  wire [1:0] alignhist0 = _T_634 | _T_635; // @[Mux.scala 27:72]
+  wire [30:0] _T_647 = f0val[1] ? f0pc_plus1 : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] _T_648 = _T_515 ? f1pc : 31'h0; // @[Mux.scala 27:72]
+  wire [30:0] secondpc = _T_647 | _T_648; // @[Mux.scala 27:72]
+  wire  _T_657 = first4B & alignval[1]; // @[Mux.scala 27:72]
+  wire  _T_658 = first2B & alignval[0]; // @[Mux.scala 27:72]
+  wire  _T_662 = |alignicaf; // @[ifu_aln_ctl.scala 341:74]
+  wire  _T_665 = first4B & _T_662; // @[Mux.scala 27:72]
+  wire  _T_666 = first2B & alignicaf[0]; // @[Mux.scala 27:72]
+  wire  _T_671 = first4B & _T_513; // @[ifu_aln_ctl.scala 343:54]
+  wire  _T_673 = _T_671 & f0val[0]; // @[ifu_aln_ctl.scala 343:66]
+  wire  _T_675 = ~alignicaf[0]; // @[ifu_aln_ctl.scala 343:79]
+  wire  _T_676 = _T_673 & _T_675; // @[ifu_aln_ctl.scala 343:77]
+  wire  _T_678 = ~aligndbecc[0]; // @[ifu_aln_ctl.scala 343:95]
+  wire  _T_679 = _T_676 & _T_678; // @[ifu_aln_ctl.scala 343:93]
+  wire  icaf_eff = alignicaf[1] | aligndbecc[1]; // @[ifu_aln_ctl.scala 345:31]
+  wire  _T_684 = first4B & icaf_eff; // @[ifu_aln_ctl.scala 347:51]
+  wire  _T_687 = |aligndbecc; // @[ifu_aln_ctl.scala 349:74]
+  wire  _T_690 = first4B & _T_687; // @[Mux.scala 27:72]
+  wire  _T_691 = first2B & aligndbecc[0]; // @[Mux.scala 27:72]
+  wire [31:0] _T_696 = first4B ? aligndata : 32'h0; // @[Mux.scala 27:72]
+  wire [31:0] _T_697 = first2B ? decompressed_io_dout : 32'h0; // @[Mux.scala 27:72]
+  wire [7:0] _T_702 = f0pc[8:1] ^ f0pc[16:9]; // @[lib.scala 51:47]
+  wire [7:0] firstpc_hash = _T_702 ^ f0pc[24:17]; // @[lib.scala 51:85]
+  wire [7:0] _T_706 = secondpc[8:1] ^ secondpc[16:9]; // @[lib.scala 51:47]
+  wire [7:0] secondpc_hash = _T_706 ^ secondpc[24:17]; // @[lib.scala 51:85]
+  wire [4:0] _T_712 = f0pc[13:9] ^ f0pc[18:14]; // @[lib.scala 42:111]
+  wire [4:0] firstbrtag_hash = _T_712 ^ f0pc[23:19]; // @[lib.scala 42:111]
+  wire [4:0] _T_717 = secondpc[13:9] ^ secondpc[18:14]; // @[lib.scala 42:111]
+  wire [4:0] secondbrtag_hash = _T_717 ^ secondpc[23:19]; // @[lib.scala 42:111]
+  wire  _T_719 = first2B & alignbrend[0]; // @[ifu_aln_ctl.scala 366:45]
+  wire  _T_721 = first4B & alignbrend[1]; // @[ifu_aln_ctl.scala 366:73]
+  wire  _T_722 = _T_719 | _T_721; // @[ifu_aln_ctl.scala 366:62]
+  wire  _T_726 = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 366:115]
+  wire  _T_729 = first2B & alignret[0]; // @[ifu_aln_ctl.scala 368:49]
+  wire  _T_731 = first4B & alignret[1]; // @[ifu_aln_ctl.scala 368:75]
+  wire  _T_734 = first2B & alignpc4[0]; // @[ifu_aln_ctl.scala 370:29]
+  wire  _T_736 = first4B & alignpc4[1]; // @[ifu_aln_ctl.scala 370:55]
+  wire  i0_brp_pc4 = _T_734 | _T_736; // @[ifu_aln_ctl.scala 370:44]
+  wire  _T_738 = first2B | alignbrend[0]; // @[ifu_aln_ctl.scala 372:53]
+  wire  _T_744 = first2B & alignhist1[0]; // @[ifu_aln_ctl.scala 374:54]
+  wire  _T_746 = first4B & alignhist1[1]; // @[ifu_aln_ctl.scala 374:82]
+  wire  _T_747 = _T_744 | _T_746; // @[ifu_aln_ctl.scala 374:71]
+  wire  _T_749 = first2B & alignhist0[0]; // @[ifu_aln_ctl.scala 375:14]
+  wire  _T_751 = first4B & alignhist0[1]; // @[ifu_aln_ctl.scala 375:42]
+  wire  _T_752 = _T_749 | _T_751; // @[ifu_aln_ctl.scala 375:31]
+  wire  i0_ends_f1 = first4B & _T_515; // @[ifu_aln_ctl.scala 377:28]
+  wire  _T_768 = io_dec_aln_aln_ib_i0_brp_valid & i0_brp_pc4; // @[ifu_aln_ctl.scala 386:77]
+  wire  _T_769 = _T_768 & first2B; // @[ifu_aln_ctl.scala 386:91]
+  wire  _T_770 = ~i0_brp_pc4; // @[ifu_aln_ctl.scala 386:139]
+  wire  _T_771 = io_dec_aln_aln_ib_i0_brp_valid & _T_770; // @[ifu_aln_ctl.scala 386:137]
+  wire  _T_772 = _T_771 & first4B; // @[ifu_aln_ctl.scala 386:151]
+  rvclkhdr rvclkhdr ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_io_clk),
+    .io_en(rvclkhdr_io_en)
+  );
+  rvclkhdr rvclkhdr_1 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_1_io_clk),
+    .io_en(rvclkhdr_1_io_en)
+  );
+  rvclkhdr rvclkhdr_2 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_2_io_clk),
+    .io_en(rvclkhdr_2_io_en)
+  );
+  rvclkhdr rvclkhdr_3 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_3_io_clk),
+    .io_en(rvclkhdr_3_io_en)
+  );
+  rvclkhdr rvclkhdr_4 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_4_io_clk),
+    .io_en(rvclkhdr_4_io_en)
+  );
+  rvclkhdr rvclkhdr_5 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_5_io_clk),
+    .io_en(rvclkhdr_5_io_en)
+  );
+  rvclkhdr rvclkhdr_6 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_6_io_clk),
+    .io_en(rvclkhdr_6_io_en)
+  );
+  rvclkhdr rvclkhdr_7 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_7_io_clk),
+    .io_en(rvclkhdr_7_io_en)
+  );
+  rvclkhdr rvclkhdr_8 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_8_io_clk),
+    .io_en(rvclkhdr_8_io_en)
+  );
+  rvclkhdr rvclkhdr_9 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_9_io_clk),
+    .io_en(rvclkhdr_9_io_en)
+  );
+  rvclkhdr rvclkhdr_10 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_10_io_clk),
+    .io_en(rvclkhdr_10_io_en)
+  );
+  rvclkhdr rvclkhdr_11 ( // @[lib.scala 404:23]
+    .io_clk(rvclkhdr_11_io_clk),
+    .io_en(rvclkhdr_11_io_en)
+  );
+  ifu_compress_ctl decompressed ( // @[ifu_aln_ctl.scala 353:28]
+    .io_din(decompressed_io_din),
+    .io_dout(decompressed_io_dout)
+  );
+  assign io_dec_aln_aln_dec_ifu_i0_cinst = aligndata[15:0]; // @[ifu_aln_ctl.scala 332:35]
+  assign io_dec_aln_aln_ib_ifu_i0_icaf = _T_665 | _T_666; // @[ifu_aln_ctl.scala 341:33]
+  assign io_dec_aln_aln_ib_ifu_i0_icaf_type = _T_679 ? f1ictype : f0ictype; // @[ifu_aln_ctl.scala 343:38]
+  assign io_dec_aln_aln_ib_ifu_i0_icaf_second = _T_684 & _T_515; // @[ifu_aln_ctl.scala 347:40]
+  assign io_dec_aln_aln_ib_ifu_i0_dbecc = _T_690 | _T_691; // @[ifu_aln_ctl.scala 349:34]
+  assign io_dec_aln_aln_ib_ifu_i0_bp_index = _T_738 ? firstpc_hash : secondpc_hash; // @[ifu_aln_ctl.scala 388:37]
+  assign io_dec_aln_aln_ib_ifu_i0_bp_fghr = i0_ends_f1 ? f1fghr : f0fghr; // @[ifu_aln_ctl.scala 390:36]
+  assign io_dec_aln_aln_ib_ifu_i0_bp_btag = _T_738 ? firstbrtag_hash : secondbrtag_hash; // @[ifu_aln_ctl.scala 392:36]
+  assign io_dec_aln_aln_ib_ifu_i0_valid = _T_657 | _T_658; // @[ifu_aln_ctl.scala 339:34]
+  assign io_dec_aln_aln_ib_ifu_i0_instr = _T_696 | _T_697; // @[ifu_aln_ctl.scala 355:34]
+  assign io_dec_aln_aln_ib_ifu_i0_pc = f0pc; // @[ifu_aln_ctl.scala 326:31]
+  assign io_dec_aln_aln_ib_ifu_i0_pc4 = aligndata[1:0] == 2'h3; // @[ifu_aln_ctl.scala 330:32]
+  assign io_dec_aln_aln_ib_i0_brp_valid = _T_722 | _T_726; // @[ifu_aln_ctl.scala 366:34]
+  assign io_dec_aln_aln_ib_i0_brp_bits_toffset = i0_ends_f1 ? f1poffset : f0poffset; // @[ifu_aln_ctl.scala 378:41]
+  assign io_dec_aln_aln_ib_i0_brp_bits_hist = {_T_747,_T_752}; // @[ifu_aln_ctl.scala 374:38]
+  assign io_dec_aln_aln_ib_i0_brp_bits_br_error = _T_769 | _T_772; // @[ifu_aln_ctl.scala 386:42]
+  assign io_dec_aln_aln_ib_i0_brp_bits_br_start_error = _T_657 & alignbrend[0]; // @[ifu_aln_ctl.scala 382:49]
+  assign io_dec_aln_aln_ib_i0_brp_bits_bank = _T_738 ? f0pc[0] : secondpc[0]; // @[ifu_aln_ctl.scala 384:49]
+  assign io_dec_aln_aln_ib_i0_brp_bits_prett = i0_ends_f1 ? f1prett : f0prett; // @[ifu_aln_ctl.scala 380:39]
+  assign io_dec_aln_aln_ib_i0_brp_bits_way = _T_738 ? alignway[0] : alignway[1]; // @[ifu_aln_ctl.scala 372:37]
+  assign io_dec_aln_aln_ib_i0_brp_bits_ret = _T_729 | _T_731; // @[ifu_aln_ctl.scala 368:37]
+  assign io_dec_aln_ifu_pmu_instr_aligned = io_dec_i0_decode_d & _T_785; // @[ifu_aln_ctl.scala 398:36]
+  assign io_ifu_fb_consume1 = _T_312 & _T_1; // @[ifu_aln_ctl.scala 242:22]
+  assign io_ifu_fb_consume2 = _T_315 & _T_1; // @[ifu_aln_ctl.scala 243:22]
+  assign rvclkhdr_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_io_en = _T_354 | _T_358; // @[lib.scala 407:17]
+  assign rvclkhdr_1_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_1_io_en = _T_25 | f1_shift_2B; // @[lib.scala 407:17]
+  assign rvclkhdr_2_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_2_io_en = _T_29 | shift_4B; // @[lib.scala 407:17]
+  assign rvclkhdr_3_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_3_io_en = qwen[2]; // @[lib.scala 407:17]
+  assign rvclkhdr_4_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_4_io_en = qwen[1]; // @[lib.scala 407:17]
+  assign rvclkhdr_5_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_5_io_en = qwen[0]; // @[lib.scala 407:17]
+  assign rvclkhdr_6_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_6_io_en = qwen[2]; // @[lib.scala 407:17]
+  assign rvclkhdr_7_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_7_io_en = qwen[1]; // @[lib.scala 407:17]
+  assign rvclkhdr_8_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_8_io_en = qwen[0]; // @[lib.scala 407:17]
+  assign rvclkhdr_9_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_9_io_en = qwen[2]; // @[lib.scala 407:17]
+  assign rvclkhdr_10_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_10_io_en = qwen[1]; // @[lib.scala 407:17]
+  assign rvclkhdr_11_io_clk = clock; // @[lib.scala 406:18]
+  assign rvclkhdr_11_io_en = qwen[0]; // @[lib.scala 407:17]
+  assign decompressed_io_din = aligndata[15:0]; // @[ifu_aln_ctl.scala 394:23]
+`ifdef RANDOMIZE_GARBAGE_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_INVALID_ASSIGN
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_REG_INIT
+`define RANDOMIZE
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+`define RANDOMIZE
+`endif
+`ifndef RANDOM
+`define RANDOM $random
+`endif
+`ifdef RANDOMIZE_MEM_INIT
+  integer initvar;
+`endif
+`ifndef SYNTHESIS
+`ifdef FIRRTL_BEFORE_INITIAL
+`FIRRTL_BEFORE_INITIAL
+`endif
+initial begin
+  `ifdef RANDOMIZE
+    `ifdef INIT_RANDOM
+      `INIT_RANDOM
+    `endif
+    `ifndef VERILATOR
+      `ifdef RANDOMIZE_DELAY
+        #`RANDOMIZE_DELAY begin end
+      `else
+        #0.002 begin end
+      `endif
+    `endif
+`ifdef RANDOMIZE_REG_INIT
+  _RAND_0 = {1{`RANDOM}};
+  error_stall = _RAND_0[0:0];
+  _RAND_1 = {1{`RANDOM}};
+  wrptr = _RAND_1[1:0];
+  _RAND_2 = {1{`RANDOM}};
+  rdptr = _RAND_2[1:0];
+  _RAND_3 = {1{`RANDOM}};
+  f2val = _RAND_3[1:0];
+  _RAND_4 = {1{`RANDOM}};
+  f1val = _RAND_4[1:0];
+  _RAND_5 = {1{`RANDOM}};
+  f0val = _RAND_5[1:0];
+  _RAND_6 = {1{`RANDOM}};
+  q2off = _RAND_6[0:0];
+  _RAND_7 = {1{`RANDOM}};
+  q1off = _RAND_7[0:0];
+  _RAND_8 = {1{`RANDOM}};
+  q0off = _RAND_8[0:0];
+  _RAND_9 = {1{`RANDOM}};
+  q1 = _RAND_9[31:0];
+  _RAND_10 = {1{`RANDOM}};
+  q0 = _RAND_10[31:0];
+  _RAND_11 = {1{`RANDOM}};
+  q2 = _RAND_11[31:0];
+  _RAND_12 = {1{`RANDOM}};
+  f2pc = _RAND_12[30:0];
+  _RAND_13 = {1{`RANDOM}};
+  f1pc = _RAND_13[30:0];
+  _RAND_14 = {1{`RANDOM}};
+  f0pc = _RAND_14[30:0];
+  _RAND_15 = {1{`RANDOM}};
+  brdata2 = _RAND_15[11:0];
+  _RAND_16 = {1{`RANDOM}};
+  brdata1 = _RAND_16[11:0];
+  _RAND_17 = {1{`RANDOM}};
+  brdata0 = _RAND_17[11:0];
+  _RAND_18 = {2{`RANDOM}};
+  misc2 = _RAND_18[54:0];
+  _RAND_19 = {2{`RANDOM}};
+  misc1 = _RAND_19[54:0];
+  _RAND_20 = {2{`RANDOM}};
+  misc0 = _RAND_20[54:0];
+`endif // RANDOMIZE_REG_INIT
+  if (reset) begin
+    error_stall = 1'h0;
+  end
+  if (reset) begin
+    wrptr = 2'h0;
+  end
+  if (reset) begin
+    rdptr = 2'h0;
+  end
+  if (reset) begin
+    f2val = 2'h0;
+  end
+  if (reset) begin
+    f1val = 2'h0;
+  end
+  if (reset) begin
+    f0val = 2'h0;
+  end
+  if (reset) begin
+    q2off = 1'h0;
+  end
+  if (reset) begin
+    q1off = 1'h0;
+  end
+  if (reset) begin
+    q0off = 1'h0;
+  end
+  if (reset) begin
+    q1 = 32'h0;
+  end
+  if (reset) begin
+    q0 = 32'h0;
+  end
+  if (reset) begin
+    q2 = 32'h0;
+  end
+  if (reset) begin
+    f2pc = 31'h0;
+  end
+  if (reset) begin
+    f1pc = 31'h0;
+  end
+  if (reset) begin
+    f0pc = 31'h0;
+  end
+  if (reset) begin
+    brdata2 = 12'h0;
+  end
+  if (reset) begin
+    brdata1 = 12'h0;
+  end
+  if (reset) begin
+    brdata0 = 12'h0;
+  end
+  if (reset) begin
+    misc2 = 55'h0;
+  end
+  if (reset) begin
+    misc1 = 55'h0;
+  end
+  if (reset) begin
+    misc0 = 55'h0;
+  end
+  `endif // RANDOMIZE
+end // initial
+`ifdef FIRRTL_AFTER_INITIAL
+`FIRRTL_AFTER_INITIAL
+`endif
+`endif // SYNTHESIS
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      error_stall <= 1'h0;
+    end else begin
+      error_stall <= _T & _T_1;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      wrptr <= 2'h0;
+    end else begin
+      wrptr <= _T_113 | _T_112;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      rdptr <= 2'h0;
+    end else begin
+      rdptr <= _T_90 | _T_85;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      f2val <= 2'h0;
+    end else begin
+      f2val <= _T_409 | _T_410;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      f1val <= 2'h0;
+    end else begin
+      f1val <= _T_438 | _T_437;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      f0val <= 2'h0;
+    end else begin
+      f0val <= _T_474 | _T_472;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      q2off <= 1'h0;
+    end else begin
+      q2off <= _T_137 | _T_136;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      q1off <= 1'h0;
+    end else begin
+      q1off <= _T_160 | _T_159;
+    end
+  end
+  always @(posedge io_active_clk or posedge reset) begin
+    if (reset) begin
+      q0off <= 1'h0;
+    end else begin
+      q0off <= _T_183 | _T_182;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      q1 <= 32'h0;
+    end else if (qwen[1]) begin
+      q1 <= io_ifu_fetch_data_f;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      q0 <= 32'h0;
+    end else if (qwen[0]) begin
+      q0 <= io_ifu_fetch_data_f;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      q2 <= 32'h0;
+    end else if (qwen[2]) begin
+      q2 <= io_ifu_fetch_data_f;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      f2pc <= 31'h0;
+    end else if (fetch_to_f2) begin
+      f2pc <= io_ifu_fetch_pc;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      f1pc <= 31'h0;
+    end else if (f1_shift_wr_en) begin
+      f1pc <= f1pc_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      f0pc <= 31'h0;
+    end else if (f0_shift_wr_en) begin
+      f0pc <= f0pc_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      brdata2 <= 12'h0;
+    end else if (qwen[2]) begin
+      brdata2 <= brdata_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      brdata1 <= 12'h0;
+    end else if (qwen[1]) begin
+      brdata1 <= brdata_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      brdata0 <= 12'h0;
+    end else if (qwen[0]) begin
+      brdata0 <= brdata_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      misc2 <= 55'h0;
+    end else if (qwen[2]) begin
+      misc2 <= misc_data_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      misc1 <= 55'h0;
+    end else if (qwen[1]) begin
+      misc1 <= misc_data_in;
+    end
+  end
+  always @(posedge clock or posedge reset) begin
+    if (reset) begin
+      misc0 <= 55'h0;
+    end else if (qwen[0]) begin
+      misc0 <= misc_data_in;
+    end
+  end
+endmodule
diff --git a/src/main/scala/ifu/ifu_aln_ctl.scala b/src/main/scala/ifu/ifu_aln_ctl.scala
index 7414c781..b7c819cd 100644
--- a/src/main/scala/ifu/ifu_aln_ctl.scala
+++ b/src/main/scala/ifu/ifu_aln_ctl.scala
@@ -1,405 +1,409 @@
-//package ifu
-//import lib._
-//import chisel3._
-//import chisel3.util._
-//import include._
-//
-//class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
-//  val io = IO(new Bundle{
-//    val scan_mode = Input(Bool())
-//    val active_clk              = Input(Clock())
-//    val ifu_async_error_start   = Input(Bool()) // Error coming from mem-ctl
-//    val iccm_rd_ecc_double_err  = Input(Bool()) // ICCM double error coming from mem-ctl
-//    val ic_access_fault_f       = Input(Bool()) // Access fault in I$
-//    val ic_access_fault_type_f  = Input(UInt(2.W)) // Type of access fault occured
-//    val ifu_bp_fghr_f           = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
-//    val ifu_bp_btb_target_f     = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
-//    val ifu_bp_poffset_f        = Input(UInt(12.W)) // Offset to the current PC for branch
-//    val ifu_bp_hist0_f          = Input(UInt(2.W)) // History to EXU
-//    val ifu_bp_hist1_f          = Input(UInt(2.W)) // History to EXU
-//    val ifu_bp_pc4_f            = Input(UInt(2.W)) // PC4
-//    val ifu_bp_way_f            = Input(UInt(2.W)) // Way to help in miss prediction
-//    val ifu_bp_valid_f          = Input(UInt(2.W)) // Valid Branch prediction
-//    val ifu_bp_ret_f            = Input(UInt(2.W)) // BP ret
-//    val exu_flush_final         = Input(Bool()) // Miss prediction
-//    val dec_aln                 = new dec_aln() // Data going to the dec from the ALN
-//    val ifu_fetch_data_f        = Input(UInt(32.W)) // PC of the current instruction in the FP
-//    val ifu_fetch_val           = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
-//    val ifu_fetch_pc            = Input(UInt(31.W)) // Current PC
-//   /////////////////////////////////////////////////
-//    val ifu_fb_consume1         = Output(Bool()) // FP used 1
-//    val ifu_fb_consume2         = Output(Bool()) // FP used 2
-//
-//  })
-//  val MHI = 46+BHT_GHR_SIZE // 54
-//  val MSIZE = 47+BHT_GHR_SIZE // 55
-//  val BRDATA_SIZE = 12
-//  val error_stall_in = WireInit(Bool(),0.U)
-//  val alignval = WireInit(UInt(2.W), 0.U)
-//  val q0final = WireInit(UInt(32.W), 0.U)
-//  val q1final = WireInit(UInt(16.W), 0.U)
-//  val wrptr_in = WireInit(UInt(2.W), init = 0.U)
-//  val rdptr_in = WireInit(UInt(2.W), init = 0.U)
-//
-//  val f2val_in = WireInit(UInt(2.W), init = 0.U)
-//  val f1val_in = WireInit(UInt(2.W), init = 0.U)
-//  val f0val_in = WireInit(UInt(2.W), init = 0.U)
-//
-//  val q2off_in = WireInit(UInt(1.W), init = 0.U)
-//  val q1off_in = WireInit(UInt(1.W), init = 0.U)
-//  val q0off_in = WireInit(UInt(1.W), init = 0.U)
-//
-//  val sf0_valid = WireInit(Bool(), init = 0.U)
-//  val sf1_valid = WireInit(Bool(), init = 0.U)
-//
-//  val f2_valid = WireInit(Bool(), init = 0.U)
-//  val ifvalid = WireInit(Bool(), init = 0.U)
-//  val shift_f2_f1 = WireInit(Bool(), init = 0.U)
-//  val shift_f2_f0 = WireInit(Bool(), init = 0.U)
-//  val shift_f1_f0 = WireInit(Bool(), init = 0.U)
-//
-//  val f0icaf = WireInit(Bool(), init = 0.U)
-//  val f1icaf = WireInit(Bool(), init = 0.U)
-//
-//  val sf0val = WireInit(UInt(2.W), 0.U)
-//  val sf1val = WireInit(UInt(2.W), 0.U)
-//
-//  val misc0 = WireInit(UInt((MHI+1).W), 0.U)
-//  val misc1 = WireInit(UInt((MHI+1).W), 0.U)
-//  val misc2 = WireInit(UInt((MHI+1).W), 0.U)
-//
-//  val brdata1 = WireInit(UInt(12.W), init = 0.U)
-//  val brdata0 = WireInit(UInt(12.W), init = 0.U)
-//  val brdata2 = WireInit(UInt(12.W), init = 0.U)
-//
-//  val q0 = WireInit(UInt(32.W), init = 0.U)
-//  val q1 = WireInit(UInt(32.W), init = 0.U)
-//  val q2 = WireInit(UInt(32.W), init = 0.U)
-//
-//  val f1pc_in = WireInit(UInt(31.W), 0.U)
-//  val f0pc_in = WireInit(UInt(31.W), 0.U)
-//  val error_stall = WireInit(Bool(), 0.U)
-//  val f2_wr_en = WireInit(Bool(), 0.U)
-//  val shift_4B = WireInit(Bool(), 0.U)
-//  val f1_shift_wr_en = WireInit(Bool(), 0.U)
-//  val f0_shift_wr_en = WireInit(Bool(), 0.U)
-//  val qwen = WireInit(UInt(3.W), 0.U)
-//  val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
-//  val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
-//
-//  val fetch_to_f0 = WireInit(Bool(), 0.U)
-//  val fetch_to_f1 = WireInit(Bool(), 0.U)
-//  val fetch_to_f2 = WireInit(Bool(), 0.U)
-//  val f1_shift_2B = WireInit(Bool(), 0.U)
-//  val first4B = WireInit(Bool(), 0.U)
-//  val shift_2B = WireInit(Bool(), 0.U)
-//  val f0_shift_2B = WireInit(Bool(), 0.U)
-//
-//  // Stall if there is an error in the instrucion
-//  error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
-//
-//  // Flop the stall until flush
-//  error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
-//  // Write Ptr of the FP
-//  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
-//  // Read Ptr of the FP
-//  val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
-//  // Fetch Instruction boundary
-//  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
-//  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
-//  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
-//
-//  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
-//  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
-//  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
-//  // Instrution PC to the FP
-//  val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
-//  val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
-//  val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
-//  // Branch data to the FP
-//  brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
-//  brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
-//  brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
-//  // Miscalanious data to the FP including error's
-//  misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
-//  misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
-//  misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
-//  // Instruction in the FP
-//  q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
-//  q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
-//  q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
-//
-//  // Shift FP logic
-//  f2_wr_en       := fetch_to_f2
-//  f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
-//  f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
-//  // FP read enable .. 3-bit for Implemenation of 1HMux
-//  val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
-//  // FP write enable .. 3-bit for Implemenation of 1HMux
-//  qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
-//
-//  // Read Pointer calculation
-//  // Next rdptr = # of consume + current ptr location (Rounding it from 2)
-//  rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
-//    (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
-//    (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
-//    (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
-//    (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
-//    (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
-//    (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
-//
-//  // As there is only 1 enqueue so each time move by 1
-//  wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
-//    (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
-//    (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
-//    (!ifvalid & !io.exu_flush_final).asBool->wrptr))
-//
-//  q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
-//    (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
-//    (!qwen(2) & (rdptr===0.U)).asBool->q2off))
-//
-//  q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
-//    (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
-//    (!qwen(1) & (rdptr===2.U)).asBool->q1off))
-//
-//  q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
-//                        (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
-//                        (!qwen(0) & (rdptr===1.U)).asBool ->  q0off))
-//
-//  val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
-//    (rdptr===1.U)->q1off,
-//    (rdptr===2.U)->q2off))
-//
-//  val  q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
-//
-//  val q0sel = Cat(q0ptr, !q0ptr)
-//
-//  val q1sel = Cat(q1ptr, !q1ptr)
-//  // Misc data error, access-fault, type of fault, target, offset and ghr value
-//  misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
-//    io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
-//
-//  val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
-//    qren(1).asBool()->Cat(misc2, misc1),
-//    qren(2).asBool()->Cat(misc0, misc2)))
-//
-//  val misc1eff = misceff(misceff.getWidth-1,MHI+1)
-//  val misc0eff = misceff(MHI, 0)
-//
-//
-//  val f1dbecc = misc1eff(misc1eff.getWidth-1)
-//  f1icaf := misc1eff(misc1eff.getWidth-2)
-//  val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
-//  val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
-//  val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
-//  val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
-//
-//  val f0dbecc = misc0eff(misc1eff.getWidth-1)
-//  f0icaf := misc0eff(misc1eff.getWidth-2)
-//  val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
-//  val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
-//  val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
-//  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
-//
-//  // Branch information
-//  brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
-//    io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
-//    io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
-//  // Effective branch information
-//  val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
-//    qren(1).asBool->Cat(brdata2,brdata1),
-//    qren(2).asBool->Cat(brdata0,brdata2)))
-//
-//  val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
-//
-//  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
-//  val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
-//
-//  val f0ret = Cat(brdata0final(6),brdata0final(0))
-//  val f0brend = Cat(brdata0final(7),brdata0final(1))
-//  val f0way = Cat(brdata0final(8),brdata0final(2))
-//  val f0pc4 = Cat(brdata0final(9),brdata0final(3))
-//  val f0hist0 = Cat(brdata0final(10),brdata0final(4))
-//  val f0hist1 = Cat(brdata0final(11),brdata0final(5))
-//
-//  val f1ret = Cat(brdata1final(6),brdata1final(0))
-//  val f1brend = Cat(brdata1final(7),brdata1final(1))
-//  val f1way = Cat(brdata1final(8),brdata1final(2))
-//  val f1pc4 = Cat(brdata1final(9),brdata1final(3))
-//  val f1hist0 = Cat(brdata1final(10),brdata1final(4))
-//  val f1hist1 = Cat(brdata1final(11),brdata1final(5))
-//
-//
-//  f2_valid := f2val(0)
-//  sf1_valid := sf1val(0)
-//  sf0_valid := sf0val(0)
-//
-//  val consume_fb0 = !sf0val(0) & f0val(0)
-//  val consume_fb1 = !sf1val(0) & f1val(0)
-//
-//  // Depending on type of instruction and boundary determine how many FP to consume
-//  io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
-//  io.ifu_fb_consume2 := consume_fb0 &  consume_fb1 & !io.exu_flush_final
-//
-//  ifvalid := io.ifu_fetch_val(0)
-//
-//  // Shift logic for each dequeue
-//  shift_f1_f0 := !sf0_valid &  sf1_valid
-//  shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
-//  shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
-//
-//  fetch_to_f0        :=  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
-//  fetch_to_f1        := (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
-//                        (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
-//                        ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
-//
-//  fetch_to_f2        := (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
-//                        ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
-//
-//  val f0pc_plus1 = f0pc + 1.U
-//
-//  val f1pc_plus1 = f1pc + 1.U
-//
-//  val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
-//
-//  f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
-//    shift_f2_f1.asBool->f2pc,
-//    (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
-//
-//  f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
-//                       shift_f2_f0.asBool->f2pc,
-//                       shift_f1_f0.asBool->sf1pc,
-//                      (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
-//
-//  f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
-//                       (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
-//
-//  sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
-//
-//  f1val_in := Mux1H(Seq(( fetch_to_f1 &                               !io.exu_flush_final).asBool -> io.ifu_fetch_val,
-//                        (                shift_f2_f1 &                !io.exu_flush_final).asBool->f2val,
-//                        (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
-//
-//  sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
-//                (!shift_2B & !shift_4B).asBool->f0val))
-//
-//  f0val_in := Mux1H(Seq((fetch_to_f0 &                                !io.exu_flush_final).asBool->io.ifu_fetch_val,
-//                        (                shift_f2_f0 &                !io.exu_flush_final).asBool->f2val,
-//                        (                               shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
-//                        (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
-//
-//  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
-//    qren(1).asBool->Cat(q2,q1),
-//    qren(2).asBool->Cat(q0,q2)))
-//  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
-//
-//  q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
-//
-//  q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
-//
-//  // Alinging the data according to the boundary of PC
-//  val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
-//
-//  alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
-//
-//  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
-//
-//  val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
-//
-//  val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
-//
-//  val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
-//
-//  val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
-//
-//  val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
-//
-//  val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
-//
-//  val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
-//
-//  val alignfromf1 = !f0val(1) & f0val(0)
-//
-//  val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
-//
-//  io.dec_aln.aln_ib.ifu_i0_pc := f0pc
-//
-//  val firstpc = f0pc
-//
-//  io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
-//
-//  io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
-//
-//  // Instruction is compressed or not
-//  first4B := aligndata(1,0) === 3.U
-//
-//  val first2B = ~first4B
-//
-//  io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
-//
-//  io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
-//
-//  io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
-//
-//  val icaf_eff = alignicaf(1) | aligndbecc(1)
-//
-//  io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
-//
-//  io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
-//
-//  val ifirst = aligndata
-//  // Expander from 16-bit to 32-bit
-//  val decompressed = Module(new ifu_compress_ctl())
-//
-//  io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
-//
-//  // Hashing the PC
-//  val firstpc_hash =  btb_addr_hash(f0pc)
-//
-//  val secondpc_hash = btb_addr_hash(secondpc)
-//
-//  val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
-//
-//  val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
-//
-//  io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
-//
-//  val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
-//    (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
-//
-//  val i0_ends_f1 = first4B & alignfromf1
-//  io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.br_start_error  := (first4B & alignval(1) & alignbrend(0))
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
-//
-//  io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 &  first4B)
-//
-//  io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
-//
-//  io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
-//
-//  io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
-//
-//  decompressed.io.din := aligndata
-//
-//  val i0_shift = io.dec_aln.aln_dec.dec_i0_decode_d & ~error_stall
-//
-//  io.dec_aln.ifu_pmu_instr_aligned := i0_shift
-//
-//  shift_2B := i0_shift & first2B
-//  shift_4B := i0_shift & first4B
-//
-//  f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
-//  f1_shift_2B :=  f0val(0) & !f0val(1) & shift_4B
-//
-//}
+package ifu
+import lib._
+import chisel3._
+import chisel3.util._
+import include._
+
+class ifu_aln_ctl extends Module with lib with RequireAsyncReset {
+  val io = IO(new Bundle{
+    val scan_mode = Input(Bool())
+    val active_clk              = Input(Clock())
+    val ifu_async_error_start   = Input(Bool()) // Error coming from mem-ctl
+    val iccm_rd_ecc_double_err  = Input(Bool()) // ICCM double error coming from mem-ctl
+    val ic_access_fault_f       = Input(Bool()) // Access fault in I$
+    val ic_access_fault_type_f  = Input(UInt(2.W)) // Type of access fault occured
+    val ifu_bp_fghr_f           = Input(UInt(BHT_GHR_SIZE.W)) // Data coming from the branch predictor to put in the FP
+    val ifu_bp_btb_target_f     = Input(UInt(31.W)) // Target for the instruction enqueue in the FP
+    val ifu_bp_poffset_f        = Input(UInt(12.W)) // Offset to the current PC for branch
+    val ifu_bp_hist0_f          = Input(UInt(2.W)) // History to EXU
+    val ifu_bp_hist1_f          = Input(UInt(2.W)) // History to EXU
+    val ifu_bp_pc4_f            = Input(UInt(2.W)) // PC4
+    val ifu_bp_way_f            = Input(UInt(2.W)) // Way to help in miss prediction
+    val ifu_bp_valid_f          = Input(UInt(2.W)) // Valid Branch prediction
+    val ifu_bp_ret_f            = Input(UInt(2.W)) // BP ret
+    val exu_flush_final         = Input(Bool()) // Miss prediction
+    val dec_i0_decode_d         = Input(Bool())
+    val dec_aln                 = new dec_aln() // Data going to the dec from the ALN
+    val ifu_fetch_data_f        = Input(UInt(32.W)) // PC of the current instruction in the FP
+    val ifu_fetch_val           = Input(UInt(2.W)) // PC boundary i.e 'x' of 2 or 4
+    val ifu_fetch_pc            = Input(UInt(31.W)) // Current PC
+   /////////////////////////////////////////////////
+    val ifu_fb_consume1         = Output(Bool()) // FP used 1
+    val ifu_fb_consume2         = Output(Bool()) // FP used 2
+
+  })
+  val MHI = 46+BHT_GHR_SIZE // 54
+  val MSIZE = 47+BHT_GHR_SIZE // 55
+  val BRDATA_SIZE = 12
+  val error_stall_in = WireInit(Bool(),0.U)
+  val alignval = WireInit(UInt(2.W), 0.U)
+  val q0final = WireInit(UInt(32.W), 0.U)
+  val q1final = WireInit(UInt(16.W), 0.U)
+  val wrptr_in = WireInit(UInt(2.W), init = 0.U)
+  val rdptr_in = WireInit(UInt(2.W), init = 0.U)
+
+  val f2val_in = WireInit(UInt(2.W), init = 0.U)
+  val f1val_in = WireInit(UInt(2.W), init = 0.U)
+  val f0val_in = WireInit(UInt(2.W), init = 0.U)
+
+  val q2off_in = WireInit(UInt(1.W), init = 0.U)
+  val q1off_in = WireInit(UInt(1.W), init = 0.U)
+  val q0off_in = WireInit(UInt(1.W), init = 0.U)
+
+  val sf0_valid = WireInit(Bool(), init = 0.U)
+  val sf1_valid = WireInit(Bool(), init = 0.U)
+
+  val f2_valid = WireInit(Bool(), init = 0.U)
+  val ifvalid = WireInit(Bool(), init = 0.U)
+  val shift_f2_f1 = WireInit(Bool(), init = 0.U)
+  val shift_f2_f0 = WireInit(Bool(), init = 0.U)
+  val shift_f1_f0 = WireInit(Bool(), init = 0.U)
+
+  val f0icaf = WireInit(Bool(), init = 0.U)
+  val f1icaf = WireInit(Bool(), init = 0.U)
+
+  val sf0val = WireInit(UInt(2.W), 0.U)
+  val sf1val = WireInit(UInt(2.W), 0.U)
+
+  val misc0 = WireInit(UInt((MHI+1).W), 0.U)
+  val misc1 = WireInit(UInt((MHI+1).W), 0.U)
+  val misc2 = WireInit(UInt((MHI+1).W), 0.U)
+
+  val brdata1 = WireInit(UInt(12.W), init = 0.U)
+  val brdata0 = WireInit(UInt(12.W), init = 0.U)
+  val brdata2 = WireInit(UInt(12.W), init = 0.U)
+
+  val q0 = WireInit(UInt(32.W), init = 0.U)
+  val q1 = WireInit(UInt(32.W), init = 0.U)
+  val q2 = WireInit(UInt(32.W), init = 0.U)
+
+  val f1pc_in = WireInit(UInt(31.W), 0.U)
+  val f0pc_in = WireInit(UInt(31.W), 0.U)
+  val error_stall = WireInit(Bool(), 0.U)
+  val f2_wr_en = WireInit(Bool(), 0.U)
+  val shift_4B = WireInit(Bool(), 0.U)
+  val f1_shift_wr_en = WireInit(Bool(), 0.U)
+  val f0_shift_wr_en = WireInit(Bool(), 0.U)
+  val qwen = WireInit(UInt(3.W), 0.U)
+  val brdata_in = WireInit(UInt(BRDATA_SIZE.W), 0.U)
+  val misc_data_in = WireInit(UInt((MHI+1).W), 0.U)
+
+  val fetch_to_f0 = WireInit(Bool(), 0.U)
+  val fetch_to_f1 = WireInit(Bool(), 0.U)
+  val fetch_to_f2 = WireInit(Bool(), 0.U)
+  val f1_shift_2B = WireInit(Bool(), 0.U)
+  val first4B = WireInit(Bool(), 0.U)
+  val shift_2B = WireInit(Bool(), 0.U)
+  val f0_shift_2B = WireInit(Bool(), 0.U)
+
+  // Stall if there is an error in the instrucion
+  error_stall_in := (error_stall | io.ifu_async_error_start) & !io.exu_flush_final
+
+  // Flop the stall until flush
+  error_stall := withClock(io.active_clk) {RegNext(error_stall_in, init = 0.U)}
+  // Write Ptr of the FP
+  val wrptr = withClock(io.active_clk) {RegNext(wrptr_in, init = 0.U)}
+  // Read Ptr of the FP
+  val rdptr = withClock(io.active_clk) {RegNext(rdptr_in, init = 0.U)}
+  // Fetch Instruction boundary
+  val f2val = withClock(io.active_clk) {RegNext(f2val_in, init = 0.U)}
+  val f1val = withClock(io.active_clk) {RegNext(f1val_in, init = 0.U)}
+  val f0val = withClock(io.active_clk) {RegNext(f0val_in, init = 0.U)}
+
+  val q2off = withClock(io.active_clk) {RegNext(q2off_in, init = 0.U)}
+  val q1off = withClock(io.active_clk) {RegNext(q1off_in, init = 0.U)}
+  val q0off = withClock(io.active_clk) {RegNext(q0off_in, init = 0.U)}
+  // Instrution PC to the FP
+  val f2pc = rvdffe(io.ifu_fetch_pc, f2_wr_en.asBool, clock, io.scan_mode)
+  val f1pc = rvdffe(f1pc_in, f1_shift_wr_en.asBool, clock, io.scan_mode)
+  val f0pc = rvdffe(f0pc_in, f0_shift_wr_en.asBool, clock, io.scan_mode)
+  // Branch data to the FP
+  brdata2 := rvdffe(brdata_in, qwen(2), clock, io.scan_mode)
+  brdata1 := rvdffe(brdata_in, qwen(1), clock, io.scan_mode)
+  brdata0 := rvdffe(brdata_in, qwen(0), clock, io.scan_mode)
+  // Miscalanious data to the FP including error's
+  misc2 := rvdffe(misc_data_in, qwen(2), clock, io.scan_mode)
+  misc1 := rvdffe(misc_data_in, qwen(1), clock, io.scan_mode)
+  misc0 := rvdffe(misc_data_in, qwen(0), clock, io.scan_mode)
+  // Instruction in the FP
+  q2 := rvdffe(io.ifu_fetch_data_f, qwen(2), clock, io.scan_mode)
+  q1 := rvdffe(io.ifu_fetch_data_f, qwen(1), clock, io.scan_mode)
+  q0 := rvdffe(io.ifu_fetch_data_f, qwen(0), clock, io.scan_mode)
+
+  // Shift FP logic
+  f2_wr_en       := fetch_to_f2
+  f1_shift_wr_en := fetch_to_f1 | shift_f2_f1 | f1_shift_2B
+  f0_shift_wr_en := fetch_to_f0 | shift_f2_f0 | shift_f1_f0 | shift_2B | shift_4B
+  // FP read enable .. 3-bit for Implemenation of 1HMux
+  val qren = Cat(rdptr === 2.U, rdptr === 1.U, rdptr === 0.U)
+  // FP write enable .. 3-bit for Implemenation of 1HMux
+  qwen := Cat(wrptr === 2.U & ifvalid, wrptr === 1.U & ifvalid, wrptr === 0.U & ifvalid)
+
+  // Read Pointer calculation
+  // Next rdptr = # of consume + current ptr location (Rounding it from 2)
+  rdptr_in := Mux1H(Seq((qren(0) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 1.U,
+    (qren(1) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 2.U,
+    (qren(2) & io.ifu_fb_consume1 & !io.exu_flush_final).asBool -> 0.U,
+    (qren(0) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 2.U,
+    (qren(1) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 0.U,
+    (qren(2) & io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> 1.U,
+    (!io.ifu_fb_consume1 & !io.ifu_fb_consume2 & !io.exu_flush_final).asBool -> rdptr))
+
+  // As there is only 1 enqueue so each time move by 1
+  wrptr_in := Mux1H(Seq((qwen(0) & !io.exu_flush_final).asBool -> 1.U,
+    (qwen(1) & !io.exu_flush_final).asBool -> 2.U,
+    (qwen(2) & !io.exu_flush_final).asBool -> 0.U,
+    (!ifvalid & !io.exu_flush_final).asBool->wrptr))
+
+  q2off_in := Mux1H(Seq((!qwen(2) & (rdptr===2.U)).asBool->(q2off.asUInt | f0_shift_2B),
+    (!qwen(2) & (rdptr===1.U)).asBool->(q2off.asUInt | f1_shift_2B),
+    (!qwen(2) & (rdptr===0.U)).asBool->q2off))
+
+  q1off_in := Mux1H(Seq((!qwen(1) & (rdptr===1.U)).asBool->(q1off.asUInt | f0_shift_2B),
+    (!qwen(1) & (rdptr===0.U)).asBool->(q1off.asUInt | f1_shift_2B),
+    (!qwen(1) & (rdptr===2.U)).asBool->q1off))
+
+  q0off_in := Mux1H(Seq((!qwen(0) & (rdptr===0.U)).asBool -> (q0off.asUInt | f0_shift_2B),
+                        (!qwen(0) & (rdptr===2.U)).asBool -> (q0off.asUInt | f1_shift_2B),
+                        (!qwen(0) & (rdptr===1.U)).asBool ->  q0off))
+
+  val q0ptr = Mux1H(Seq((rdptr===0.U)->q0off,
+    (rdptr===1.U)->q1off,
+    (rdptr===2.U)->q2off))
+
+  val  q1ptr = Mux1H(Seq((rdptr===0.U) -> q1off, (rdptr === 1.U) -> q2off, (rdptr === 2.U) -> q0off))
+
+  val q0sel = Cat(q0ptr, !q0ptr)
+
+  val q1sel = Cat(q1ptr, !q1ptr)
+  // Misc data error, access-fault, type of fault, target, offset and ghr value
+  misc_data_in := Cat(io.iccm_rd_ecc_double_err, io.ic_access_fault_f, io.ic_access_fault_type_f,
+    io.ifu_bp_btb_target_f, io.ifu_bp_poffset_f, io.ifu_bp_fghr_f)
+
+  val misceff = Mux1H(Seq(qren(0).asBool() -> Cat(misc1, misc0),
+    qren(1).asBool()->Cat(misc2, misc1),
+    qren(2).asBool()->Cat(misc0, misc2)))
+
+  val misc1eff = misceff(misceff.getWidth-1,MHI+1)
+  val misc0eff = misceff(MHI, 0)
+
+
+  val f1dbecc = misc1eff(misc1eff.getWidth-1)
+  f1icaf := misc1eff(misc1eff.getWidth-2)
+  val f1ictype = misc1eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
+  val f1prett = misc1eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
+  val f1poffset = misc1eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
+  val f1fghr = misc1eff(BHT_GHR_SIZE-1, 0)
+
+  val f0dbecc = misc0eff(misc1eff.getWidth-1)
+  f0icaf := misc0eff(misc1eff.getWidth-2)
+  val f0ictype = misc0eff(misc1eff.getWidth-3,misc1eff.getWidth-4)
+  val f0prett = misc0eff(misc1eff.getWidth-5,misc1eff.getWidth-35)
+  val f0poffset = misc0eff(BHT_GHR_SIZE+11, BHT_GHR_SIZE)
+  val f0fghr = misc0eff(BHT_GHR_SIZE-1, 0)
+
+  // Branch information
+  brdata_in := Cat(io.ifu_bp_hist1_f(1),io.ifu_bp_hist0_f(1),io.ifu_bp_pc4_f(1),io.ifu_bp_way_f(1),io.ifu_bp_valid_f(1),
+    io.ifu_bp_ret_f(1), io.ifu_bp_hist1_f(0),io.ifu_bp_hist0_f(0),io.ifu_bp_pc4_f(0),io.ifu_bp_way_f(0),
+    io.ifu_bp_valid_f(0),io.ifu_bp_ret_f(0))
+  // Effective branch information
+  val brdataeff = Mux1H(Seq(qren(0).asBool->Cat(brdata1,brdata0),
+    qren(1).asBool->Cat(brdata2,brdata1),
+    qren(2).asBool->Cat(brdata0,brdata2)))
+
+  val (brdata0eff,brdata1eff) = (brdataeff(11,0) , brdataeff(23,12))
+
+  val brdata0final = Mux1H(Seq(q0sel(0).asBool -> brdata0eff, q0sel(1).asBool -> brdata0eff(11,6)))
+  val brdata1final = Mux1H(Seq(q1sel(0).asBool -> brdata1eff, q1sel(1).asBool -> brdata1eff(11,6)))
+
+  val f0ret = Cat(brdata0final(6),brdata0final(0))
+  val f0brend = Cat(brdata0final(7),brdata0final(1))
+  val f0way = Cat(brdata0final(8),brdata0final(2))
+  val f0pc4 = Cat(brdata0final(9),brdata0final(3))
+  val f0hist0 = Cat(brdata0final(10),brdata0final(4))
+  val f0hist1 = Cat(brdata0final(11),brdata0final(5))
+
+  val f1ret = Cat(brdata1final(6),brdata1final(0))
+  val f1brend = Cat(brdata1final(7),brdata1final(1))
+  val f1way = Cat(brdata1final(8),brdata1final(2))
+  val f1pc4 = Cat(brdata1final(9),brdata1final(3))
+  val f1hist0 = Cat(brdata1final(10),brdata1final(4))
+  val f1hist1 = Cat(brdata1final(11),brdata1final(5))
+
+
+  f2_valid := f2val(0)
+  sf1_valid := sf1val(0)
+  sf0_valid := sf0val(0)
+
+  val consume_fb0 = !sf0val(0) & f0val(0)
+  val consume_fb1 = !sf1val(0) & f1val(0)
+
+  // Depending on type of instruction and boundary determine how many FP to consume
+  io.ifu_fb_consume1 := consume_fb0 & !consume_fb1 & !io.exu_flush_final
+  io.ifu_fb_consume2 := consume_fb0 &  consume_fb1 & !io.exu_flush_final
+
+  ifvalid := io.ifu_fetch_val(0)
+
+  // Shift logic for each dequeue
+  shift_f1_f0 := !sf0_valid &  sf1_valid
+  shift_f2_f0 := !sf0_valid & !sf1_valid &  f2_valid
+  shift_f2_f1 := !sf0_valid &  sf1_valid &  f2_valid
+
+  fetch_to_f0        :=  !sf0_valid & !sf1_valid & !f2_valid & ifvalid
+  fetch_to_f1        := (!sf0_valid & !sf1_valid &  f2_valid & ifvalid)  |
+                        (!sf0_valid &  sf1_valid & !f2_valid & ifvalid)  |
+                        ( sf0_valid & !sf1_valid & !f2_valid & ifvalid)
+
+  fetch_to_f2        := (!sf0_valid &  sf1_valid &  f2_valid & ifvalid)  |
+                        ( sf0_valid &  sf1_valid & !f2_valid & ifvalid)
+
+  val f0pc_plus1 = f0pc + 1.U
+
+  val f1pc_plus1 = f1pc + 1.U
+
+  val sf1pc = (Fill(31, f1_shift_2B) & f1pc_plus1) | (Fill(31, !f1_shift_2B) & f1pc)
+
+  f1pc_in := Mux1H(Seq(fetch_to_f1.asBool->io.ifu_fetch_pc,
+    shift_f2_f1.asBool->f2pc,
+    (!fetch_to_f1 & !shift_f2_f1).asBool -> sf1pc))
+
+  f0pc_in := Mux1H(Seq(fetch_to_f0.asBool->io.ifu_fetch_pc,
+                       shift_f2_f0.asBool->f2pc,
+                       shift_f1_f0.asBool->sf1pc,
+                      (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0).asBool->f0pc_plus1))
+
+  f2val_in := Mux1H(Seq((fetch_to_f2 & !io.exu_flush_final).asBool->io.ifu_fetch_val,
+                       (!fetch_to_f2 & !shift_f2_f1 & !shift_f2_f0 & !io.exu_flush_final).asBool->f2val))
+
+  sf1val := Mux1H(Seq(f1_shift_2B.asBool->f1val(1), !f1_shift_2B.asBool->f1val))
+
+  f1val_in := Mux1H(Seq(( fetch_to_f1 &                               !io.exu_flush_final).asBool -> io.ifu_fetch_val,
+                        (                shift_f2_f1 &                !io.exu_flush_final).asBool->f2val,
+                        (!fetch_to_f1 & !shift_f2_f1 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf1val))
+
+  sf0val := Mux1H(Seq(shift_2B.asBool->Cat(0.U, f0val(1)),
+                (!shift_2B & !shift_4B).asBool->f0val))
+
+  f0val_in := Mux1H(Seq((fetch_to_f0 &                                !io.exu_flush_final).asBool->io.ifu_fetch_val,
+                        (                shift_f2_f0 &                !io.exu_flush_final).asBool->f2val,
+                        (                               shift_f1_f0 & !io.exu_flush_final).asBool->sf1val,
+                        (!fetch_to_f0 & !shift_f2_f0 & !shift_f1_f0 & !io.exu_flush_final).asBool->sf0val))
+
+  val qeff = Mux1H(Seq(qren(0).asBool->Cat(q1,q0),
+    qren(1).asBool->Cat(q2,q1),
+    qren(2).asBool->Cat(q0,q2)))
+  val (q1eff, q0eff) = (qeff(63,32), qeff(31,0))
+
+  q0final := Mux1H(Seq(q0sel(0).asBool->q0eff, q0sel(1).asBool->q0eff(31,16)))
+
+  q1final := Mux1H(Seq(q1sel(0).asBool->q1eff(15,0), q1sel(1).asBool->q1eff(31,16)))
+
+  // Alinging the data according to the boundary of PC
+  val aligndata = Mux1H(Seq(f0val(1).asBool -> q0final, (~f0val(1) & f0val(0)).asBool -> Cat(q1final(15,0),q0final(15,0))))
+
+  alignval := Mux1H(Seq(f0val(1).asBool->3.U, (!f0val(1) & f0val(0)) -> Cat(f1val(0),1.U)))
+
+  val alignicaf = Mux1H(Seq(f0val(1).asBool -> f0icaf, (~f0val(1) & f0val(0)).asBool -> Cat(f1icaf,f0icaf)))
+
+  val aligndbecc = Mux1H(Seq(f0val(1).asBool -> Fill(2,f0dbecc), (!f0val(1) & f0val(0)).asBool -> Cat(f1dbecc,f0dbecc)))
+
+  val alignbrend = Mux1H(Seq(f0val(1).asBool()->f0brend, (!f0val(1) & f0val(0)).asBool->Cat(f1brend(0),f0brend(0))))
+
+  val alignpc4 = Mux1H(Seq(f0val(1).asBool()->f0pc4, (!f0val(1) & f0val(0)).asBool->Cat(f1pc4(0),f0pc4(0))))
+
+  val alignret = Mux1H(Seq(f0val(1).asBool()->f0ret, (!f0val(1) & f0val(0)).asBool->Cat(f1ret(0),f0ret(0))))
+
+  val alignway = Mux1H(Seq(f0val(1).asBool()->f0way, (!f0val(1) & f0val(0)).asBool->Cat(f1way(0),f0way(0))))
+
+  val alignhist1 = Mux1H(Seq(f0val(1).asBool()->f0hist1, (!f0val(1) & f0val(0)).asBool->Cat(f1hist1(0),f0hist1(0))))
+
+  val alignhist0 = Mux1H(Seq(f0val(1).asBool()->f0hist0, (!f0val(1) & f0val(0)).asBool->Cat(f1hist0(0),f0hist0(0))))
+
+  val alignfromf1 = !f0val(1) & f0val(0)
+
+  val secondpc = Mux1H(Seq(f0val(1).asBool()->f0pc_plus1 , (!f0val(1) & f0val(0)).asBool->f1pc))
+
+  io.dec_aln.aln_ib.ifu_i0_pc := f0pc
+
+  val firstpc = f0pc
+
+  io.dec_aln.aln_ib.ifu_i0_pc4 := first4B
+
+  io.dec_aln.aln_dec.ifu_i0_cinst := aligndata(15,0)
+
+  // Instruction is compressed or not
+  first4B := aligndata(1,0) === 3.U
+
+  val first2B = ~first4B
+
+  io.dec_aln.aln_ib.ifu_i0_valid := Mux1H(Seq(first4B.asBool -> alignval(1), first2B.asBool -> alignval(0)))
+
+  io.dec_aln.aln_ib.ifu_i0_icaf := Mux1H(Seq(first4B.asBool -> alignicaf.orR, first2B.asBool -> alignicaf(0)))
+
+  io.dec_aln.aln_ib.ifu_i0_icaf_type := Mux((first4B & !f0val(1) & f0val(0) & !alignicaf(0) & !aligndbecc(0)).asBool, f1ictype, f0ictype)
+
+  val icaf_eff = alignicaf(1) | aligndbecc(1)
+
+  io.dec_aln.aln_ib.ifu_i0_icaf_second := first4B & icaf_eff & alignfromf1
+
+  io.dec_aln.aln_ib.ifu_i0_dbecc := Mux1H(Seq(first4B.asBool->aligndbecc.orR, first2B.asBool->aligndbecc(0)))
+
+  val ifirst = aligndata
+  // Expander from 16-bit to 32-bit
+  val decompressed = Module(new ifu_compress_ctl())
+
+  io.dec_aln.aln_ib.ifu_i0_instr := Mux1H(Seq(first4B.asBool -> ifirst, first2B.asBool -> decompressed.io.dout))
+
+  // Hashing the PC
+  val firstpc_hash =  btb_addr_hash(f0pc)
+
+  val secondpc_hash = btb_addr_hash(secondpc)
+
+  val firstbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(firstpc) else btb_tag_hash(firstpc)
+
+  val secondbrtag_hash = if(BTB_BTAG_FOLD) btb_tag_hash_fold(secondpc) else btb_tag_hash(secondpc)
+
+  io.dec_aln.aln_ib.i0_brp.valid :=(first2B & alignbrend(0)) | (first4B & alignbrend(1)) | (first4B & alignval(1) & alignbrend(0))
+
+  io.dec_aln.aln_ib.i0_brp.bits.ret := (first2B & alignret(0)) | (first4B & alignret(1))
+
+  val i0_brp_pc4 = (first2B & alignpc4(0)) | (first4B & alignpc4(1))
+
+  io.dec_aln.aln_ib.i0_brp.bits.way := Mux((first2B | alignbrend(0)).asBool, alignway(0),  alignway(1))
+
+  io.dec_aln.aln_ib.i0_brp.bits.hist := Cat((first2B & alignhist1(0)) | (first4B & alignhist1(1)),
+    (first2B & alignhist0(0)) | (first4B & alignhist0(1)))
+
+  val i0_ends_f1 = first4B & alignfromf1
+  io.dec_aln.aln_ib.i0_brp.bits.toffset := Mux(i0_ends_f1.asBool, f1poffset, f0poffset)
+
+  io.dec_aln.aln_ib.i0_brp.bits.prett := Mux(i0_ends_f1.asBool, f1prett, f0prett)
+
+  io.dec_aln.aln_ib.i0_brp.bits.br_start_error  := (first4B & alignval(1) & alignbrend(0))
+
+  io.dec_aln.aln_ib.i0_brp.bits.bank            := Mux((first2B | alignbrend(0)).asBool, firstpc(0), secondpc(0))
+
+  io.dec_aln.aln_ib.i0_brp.bits.br_error := (io.dec_aln.aln_ib.i0_brp.valid &  i0_brp_pc4 &  first2B) | (io.dec_aln.aln_ib.i0_brp.valid & !i0_brp_pc4 &  first4B)
+
+  io.dec_aln.aln_ib.ifu_i0_bp_index := Mux((first2B | alignbrend(0)).asBool, firstpc_hash, secondpc_hash)
+
+  io.dec_aln.aln_ib.ifu_i0_bp_fghr := Mux((first4B & alignfromf1).asBool, f1fghr, f0fghr)
+
+  io.dec_aln.aln_ib.ifu_i0_bp_btag := Mux((first2B | alignbrend(0)).asBool, firstbrtag_hash, secondbrtag_hash)
+
+  decompressed.io.din := aligndata
+
+  val i0_shift = io.dec_i0_decode_d & ~error_stall
+
+  io.dec_aln.ifu_pmu_instr_aligned := i0_shift
+
+  shift_2B := i0_shift & first2B
+  shift_4B := i0_shift & first4B
+
+  f0_shift_2B := Mux1H(Seq(shift_2B.asBool -> f0val(0), shift_4B.asBool -> (f0val(0) & !f0val(1))))
+  f1_shift_2B :=  f0val(0) & !f0val(1) & shift_4B
+
+}
+object aln_main extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new ifu_aln_ctl()))
+}
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