From 2b59a630d6f03f8b1a1df3d6d74e3d4cff721a5c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=E2=80=8BLaraib=20Khan?= <​laraib.khan@lampromellon.com> Date: Wed, 18 Nov 2020 16:14:53 +0500 Subject: [PATCH] lsu update --- src/main/scala/lsu/el2_lsu_ecc.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/lsu/el2_lsu_ecc.scala b/src/main/scala/lsu/el2_lsu_ecc.scala index 1e24c902..4c21ef4d 100644 --- a/src/main/scala/lsu/el2_lsu_ecc.scala +++ b/src/main/scala/lsu/el2_lsu_ecc.scala @@ -19,7 +19,7 @@ class el2_lsu_ecc extends Module with el2_lib with RequireAsyncReset { val lsu_addr_r = Input(UInt(DCCM_BITS.W)) val end_addr_r = Input(UInt(DCCM_BITS.W)) - val lsu_addr_m = Input(UInt(DCCM_BITS.W)) + val lsu_addr_m = Input(UInt(DCCM_BITS.W))//6fba5e03053441e71b7d54f50a77e3b496d56173 val end_addr_m = Input(UInt(DCCM_BITS.W)) val dccm_rdata_hi_r = Input(UInt(DCCM_DATA_WIDTH.W))