From 2b6bfabc4f408763c88454e287928ee30e76ff74 Mon Sep 17 00:00:00 2001 From: Junaid Ahmed <67728633+junaidahmed-lm@users.noreply.github.com> Date: Wed, 23 Sep 2020 18:51:52 +0500 Subject: [PATCH] Update beh_lib.scala --- src/main/scala/lib/beh_lib.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/lib/beh_lib.scala b/src/main/scala/lib/beh_lib.scala index 38d07cc8..083dae9c 100644 --- a/src/main/scala/lib/beh_lib.scala +++ b/src/main/scala/lib/beh_lib.scala @@ -99,7 +99,7 @@ class rvbsadder extends Module{ //Done for verification and testing io.match_out := matchvec.asUInt.andR } - class rvrangecheck(CCM_SADR:Int=0, CCM_SIZE:Int=128) extends Module{ + class rvrangecheck(CCM_SADR:UInt, CCM_SIZE:Int=128) extends Module{ val io = IO(new Bundle{ val addr = Input(UInt(32.W)) val in_range = Output(UInt(1.W)) @@ -107,9 +107,7 @@ class rvbsadder extends Module{ //Done for verification and testing }) val REGION_BITS = 4 val MASK_BITS = 10 + log2Ceil(CCM_SIZE) - - val start_addr = Wire(UInt(32.W)) - start_addr := CCM_SADR.U + val start_addr = CCM_SADR val region = start_addr(31,(32-REGION_BITS)) io.in_region := (io.addr(31,(32-REGION_BITS)) === region(REGION_BITS-1,0)).asUInt