Hard-coded values
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waleed-lm
parent
185f4fa702
commit
2ba9ceb82e
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@ -593,4 +593,40 @@ circuit el2_ifu_iccm_mem :
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_T_448 <= _T_447 @[Mux.scala 27:72]
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node _T_449 = cat(_T_432, _T_448) @[Cat.scala 29:58]
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io.iccm_rd_data_ecc <= _T_449 @[el2_ifu_iccm_mem.scala 109:23]
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node _T_450 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
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node _T_451 = eq(_T_450, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:104]
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node _T_452 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
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node _T_453 = eq(_T_452, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:104]
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node _T_454 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
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node _T_455 = eq(_T_454, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:104]
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node _T_456 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 111:86]
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node _T_457 = eq(_T_456, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:104]
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node _T_458 = mux(_T_451, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_459 = mux(_T_453, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_460 = mux(_T_455, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_461 = mux(_T_457, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_462 = or(_T_458, _T_459) @[Mux.scala 27:72]
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node _T_463 = or(_T_462, _T_460) @[Mux.scala 27:72]
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node _T_464 = or(_T_463, _T_461) @[Mux.scala 27:72]
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wire _T_465 : UInt<39> @[Mux.scala 27:72]
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_T_465 <= _T_464 @[Mux.scala 27:72]
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node _T_466 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
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node _T_467 = eq(_T_466, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 112:79]
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node _T_468 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
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node _T_469 = eq(_T_468, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 112:79]
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node _T_470 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
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node _T_471 = eq(_T_470, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 112:79]
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node _T_472 = bits(iccm_rd_addr_lo_q, 2, 1) @[el2_ifu_iccm_mem.scala 112:61]
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node _T_473 = eq(_T_472, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 112:79]
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node _T_474 = mux(_T_467, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_475 = mux(_T_469, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_476 = mux(_T_471, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_477 = mux(_T_473, iccm_bank_dout_fn_3, UInt<1>("h00")) @[Mux.scala 27:72]
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node _T_478 = or(_T_474, _T_475) @[Mux.scala 27:72]
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node _T_479 = or(_T_478, _T_476) @[Mux.scala 27:72]
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node _T_480 = or(_T_479, _T_477) @[Mux.scala 27:72]
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wire _T_481 : UInt<39> @[Mux.scala 27:72]
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_T_481 <= _T_480 @[Mux.scala 27:72]
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node _T_482 = cat(_T_465, _T_481) @[Cat.scala 29:58]
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io.iccm_rd_data_ecc <= _T_482 @[el2_ifu_iccm_mem.scala 111:23]
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@ -39,7 +39,6 @@ module el2_ifu_iccm_mem(
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reg [31:0] _RAND_20;
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reg [31:0] _RAND_21;
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reg [31:0] _RAND_22;
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reg [31:0] _RAND_23;
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`endif // RANDOMIZE_REG_INIT
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reg [38:0] _T_85 [0:4095]; // @[el2_ifu_iccm_mem.scala 43:59]
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wire [38:0] _T_85__T_105_data; // @[el2_ifu_iccm_mem.scala 43:59]
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@ -238,7 +237,6 @@ module el2_ifu_iccm_mem(
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wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
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reg [2:0] _T_373; // @[Reg.scala 27:20]
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reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
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reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
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wire _T_376 = iccm_rd_addr_lo_q[2:1] == 2'h0; // @[el2_ifu_iccm_mem.scala 105:104]
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wire _T_379 = iccm_rd_addr_lo_q[2:1] == 2'h1; // @[el2_ifu_iccm_mem.scala 105:104]
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wire _T_382 = iccm_rd_addr_lo_q[2:1] == 2'h2; // @[el2_ifu_iccm_mem.scala 105:104]
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@ -259,28 +257,20 @@ module el2_ifu_iccm_mem(
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wire [31:0] _T_413 = _T_412 | _T_410; // @[Mux.scala 27:72]
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wire [63:0] iccm_rd_data_pre = {_T_393,_T_413}; // @[Cat.scala 29:58]
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wire [63:0] _T_419 = {16'h0,iccm_rd_data_pre[63:16]}; // @[Cat.scala 29:58]
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wire _T_421 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 109:85]
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wire _T_422 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 109:85]
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wire _T_423 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 109:85]
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wire _T_424 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 109:85]
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wire [38:0] _T_425 = _T_421 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_426 = _T_422 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_427 = _T_423 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_428 = _T_424 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_429 = _T_425 | _T_426; // @[Mux.scala 27:72]
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wire [38:0] _T_430 = _T_429 | _T_427; // @[Mux.scala 27:72]
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wire [38:0] _T_431 = _T_430 | _T_428; // @[Mux.scala 27:72]
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wire _T_434 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 110:79]
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wire _T_436 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 110:79]
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wire _T_438 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 110:79]
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wire _T_440 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 110:79]
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wire [38:0] _T_441 = _T_434 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_442 = _T_436 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_443 = _T_438 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_444 = _T_440 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_445 = _T_441 | _T_442; // @[Mux.scala 27:72]
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wire [38:0] _T_446 = _T_445 | _T_443; // @[Mux.scala 27:72]
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wire [38:0] _T_447 = _T_446 | _T_444; // @[Mux.scala 27:72]
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wire [38:0] _T_458 = _T_376 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_459 = _T_379 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_460 = _T_382 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_461 = _T_385 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_462 = _T_458 | _T_459; // @[Mux.scala 27:72]
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wire [38:0] _T_463 = _T_462 | _T_460; // @[Mux.scala 27:72]
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wire [38:0] _T_464 = _T_463 | _T_461; // @[Mux.scala 27:72]
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wire [38:0] _T_474 = _T_376 ? iccm_bank_dout_fn_0 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_475 = _T_379 ? iccm_bank_dout_fn_1 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_476 = _T_382 ? iccm_bank_dout_fn_2 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_477 = _T_385 ? iccm_bank_dout_fn_3 : 39'h0; // @[Mux.scala 27:72]
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wire [38:0] _T_478 = _T_474 | _T_475; // @[Mux.scala 27:72]
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wire [38:0] _T_479 = _T_478 | _T_476; // @[Mux.scala 27:72]
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wire [38:0] _T_480 = _T_479 | _T_477; // @[Mux.scala 27:72]
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assign _T_85__T_105_addr = _T_85__T_105_addr_pipe_0;
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assign _T_85__T_105_data = _T_85[_T_85__T_105_addr]; // @[el2_ifu_iccm_mem.scala 43:59]
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assign _T_85__T_101_data = io_iccm_wr_data[38:0];
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@ -306,7 +296,7 @@ module el2_ifu_iccm_mem(
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assign _T_88__T_104_mask = 1'h1;
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assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
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assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_419 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
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assign io_iccm_rd_data_ecc = {_T_431,_T_447}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
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assign io_iccm_rd_data_ecc = {_T_464,_T_480}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23 el2_ifu_iccm_mem.scala 111:23]
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`ifdef RANDOMIZE_GARBAGE_ASSIGN
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`define RANDOMIZE
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`endif
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@ -394,8 +384,6 @@ initial begin
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_T_373 = _RAND_21[2:0];
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_RAND_22 = {1{`RANDOM}};
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iccm_rd_addr_lo_q = _RAND_22[2:0];
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_RAND_23 = {1{`RANDOM}};
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iccm_rd_addr_hi_q = _RAND_23[1:0];
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`endif // RANDOMIZE_REG_INIT
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`endif // RANDOMIZE
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end // initial
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@ -531,10 +519,5 @@ end // initial
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end else begin
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iccm_rd_addr_lo_q <= _T_373;
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end
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if (reset) begin
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iccm_rd_addr_hi_q <= 2'h0;
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end else begin
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iccm_rd_addr_hi_q <= addr_bank_inc[2:1];
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end
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end
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endmodule
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@ -108,6 +108,8 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
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io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre)
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io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))),
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Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i))))
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io.iccm_rd_data_ecc := Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(if(i==3) 0 else i+1))),
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Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-1,1)===i.U)->iccm_bank_dout_fn(i))))
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}
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