Update and rename el2_lsu_dccm_mem.scala to el2_lsu_dccm_mem.v
This commit is contained in:
laraibkhan-lm
GitHub
parent
abab84bc96
commit
2d67d26e1a
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@ -1,99 +0,0 @@
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package lsu
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import include._
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import lib._
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import snapshot._
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import scala.math._
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import chisel3._
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import chisel3.util._
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class el2_lsu_dccm_mem extends Module {
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val io = IO(new Bundle{
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//implicit clk and rst_l
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val clk_override = Input(UInt(1.W))
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val scan_mode = Input(UInt(1.W))
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val dccm_wren = Input(UInt(1.W))
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val dccm_rden = Input(UInt(1.W))
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val dccm_wr_addr_lo = Input(UInt(pt1.DCCM_BITS.W))
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val dccm_wr_addr_hi = Input(UInt(pt1.DCCM_BITS.W))
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val dccm_rd_addr_lo = Input(UInt(pt1.DCCM_BITS.W))
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val dccm_rd_addr_hi = Input(UInt(pt1.DCCM_BITS.W))
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val dccm_wr_data_lo = Input(UInt(pt1.DCCM_FDATA_WIDTH.W))
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val dccm_wr_data_hi = Input(UInt(pt1.DCCM_FDATA_WIDTH.W))
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val dccm_rd_data_lo = Output(UInt(pt1.DCCM_FDATA_WIDTH.W))
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val dccm_rd_data_hi = Output(UInt(pt1.DCCM_FDATA_WIDTH.W))
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})
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//DCCM_BYTE_WIDTH = 4
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//DCCM_WIDTH_BITS = 2
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//DCCM_NUM_BANKS = 4
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//DCCM_BANK_BITS = 2
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//DCCM_BITS = 16
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//DCCM_FDATA_WIDTH = 39
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//DCCM_SIZE = 64
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//DCCM_INDEX_BITS = 12
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//DCCM_INDEX_DEPTH = 4K
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val DCCM_WIDTH_BITS = log2Ceil(pt1.DCCM_BYTE_WIDTH)
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val DCCM_INDEX_BITS = pt1.DCCM_BITS - pt1.DCCM_BANK_BITS - pt1.DCCM_WIDTH_BITS
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val DCCM_INDEX_DEPTH = (pt1.DCCM_SIZE*1024)/(pt1.DCCM_BYTE_WIDTH*pt1.DCCM_NUM_BANKS)
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val addr_bank = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt((pt1.DCCM_BITS-pt1.DCCM_BANK_BITS+2).W))) //[15:4] => [11:0] 12 bits per bank =>
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//val rd_addr_even = Wire(UInt((pt1.DCCM_BITS-(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)).W)) //[15:4]
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//val rd_addr_odd = Wire(UInt((pt1.DCCM_BITS-(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)).W)) //[15:4]
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// val dccm_bank_dout = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt(pt1.DCCM_FDATA_WIDTH.W))) // 3:0, 38:0
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val wr_data_bank = Wire(Vec(pt1.DCCM_NUM_BANKS,UInt(pt1.DCCM_FDATA_WIDTH.W))) // 3:0, 38:0
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val dccm_rd_addr_lo_q = RegNext(io.dccm_rd_addr_lo(DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,DCCM_WIDTH_BITS),0.U) //[3:2] => [1:0]
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val dccm_rd_addr_hi_q = RegNext(io.dccm_rd_addr_hi(DCCM_WIDTH_BITS+pt1.DCCM_BANK_BITS-1,DCCM_WIDTH_BITS),0.U)
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//2+2:2 => 4:2rd_unaligned
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val rd_unaligned = io.dccm_rd_addr_lo(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) =/= io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS)
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val wr_unaligned = io.dccm_wr_addr_lo(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS) =/= io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1,DCCM_WIDTH_BITS)
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val wren_bank = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> io.dccm_wren & ((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) | (io.dccm_wr_addr_lo(pt1.DCCM_BANK_BITS+1,2) === i.U)).asUInt)))
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val rden_bank = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> io.dccm_rden & ((io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) | (io.dccm_rd_addr_lo(pt1.DCCM_BANK_BITS+1,2) === i.U)).asUInt)))
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val dccm_clken = Reverse(Cat(VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> wren_bank(i) | rden_bank(i) | io.clk_override)))
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//[15:4] => [11:0] 12 bits per bank
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addr_bank := VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=> Mux(wren_bank(i).asBool,
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Mux(((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & wr_unaligned),
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io.dccm_wr_addr_hi(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS),
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io.dccm_wr_addr_lo(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS)),
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Mux(((io.dccm_rd_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & rd_unaligned),
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io.dccm_rd_addr_hi(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS),
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io.dccm_rd_addr_lo(DCCM_INDEX_BITS+pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS-1, pt1.DCCM_BANK_BITS+DCCM_WIDTH_BITS))))
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wr_data_bank := VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i=>
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Mux(((io.dccm_wr_addr_hi(pt1.DCCM_BANK_BITS+1,2) === i.U) & wr_unaligned),
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io.dccm_wr_data_hi(pt1.DCCM_FDATA_WIDTH-1,0),
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io.dccm_wr_data_lo(pt1.DCCM_FDATA_WIDTH-1,0)))
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val mem =SyncReadMem(DCCM_INDEX_DEPTH, Vec(pt1.DCCM_NUM_BANKS, UInt(39.W)))
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// Create one write port and one read port
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(0 to pt1.DCCM_NUM_BANKS-1).foreach(i =>
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when(wren_bank(i)& dccm_clken(i)){
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mem.write(addr_bank(i), wr_data_bank)})
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val dccm_bank_dout = VecInit.tabulate(pt1.DCCM_NUM_BANKS)(i => mem.read(addr_bank(i), ~wren_bank(i)& dccm_clken(i)))//ME && ~WE
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io.dccm_rd_data_lo := dccm_bank_dout(dccm_rd_addr_lo_q).asUInt
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io.dccm_rd_data_hi := dccm_bank_dout(dccm_rd_addr_hi_q).asUInt
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}
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object DCCM extends App{
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println("Generate Verilog")
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chisel3.Driver.execute(args, ()=> new el2_lsu_dccm_mem)
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}
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@ -0,0 +1,235 @@
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// SPDX-License-Identifier: Apache-2.0
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// Copyright 2020 Western Digital Corporation or it's affiliates.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//********************************************************************************
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// $Id$
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//
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//
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// Owner:
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// Function: DCCM for LSU pipe
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// Comments: Single ported memory
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//
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//
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// DC1 -> DC2 -> DC3 -> DC4 (Commit)
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//
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// //********************************************************************************
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module el2_lsu_dccm_mem
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#(
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parameter DCCM_BYTE_WIDTH,
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parameter DCCM_BITS,
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parameter DCCM_NUM_BANKS,
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parameter DCCM_BANK_BITS,
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parameter DCCM_SIZE,
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parameter DCCM_FDATA_WIDTH )(
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input logic clk, // clock
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input logic rst_l,
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input logic clk_override, // clock override
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input logic dccm_wren, // write enable
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input logic dccm_rden, // read enable
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input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, // write address
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input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, // write address
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input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, // read address
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input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, // read address for the upper bank in case of a misaligned access
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, // write data
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input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, // write data
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, // read data from the lo bank
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output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, // read data from the hi bank
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input logic scan_mode
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);
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localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
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localparam DCCM_INDEX_BITS = (DCCM_BITS - DCCM_BANK_BITS - DCCM_WIDTH_BITS);
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localparam DCCM_INDEX_DEPTH = ((DCCM_SIZE)*1024)/((DCCM_BYTE_WIDTH)*(DCCM_NUM_BANKS)); // Depth of memory bank
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logic [DCCM_NUM_BANKS-1:0] wren_bank;
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logic [DCCM_NUM_BANKS-1:0] rden_bank;
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logic [DCCM_NUM_BANKS-1:0] [DCCM_BITS-1:(DCCM_BANK_BITS+2)] addr_bank;
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logic [DCCM_BITS-1:(DCCM_BANK_BITS+DCCM_WIDTH_BITS)] rd_addr_even, rd_addr_odd;
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logic rd_unaligned, wr_unaligned;
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logic [DCCM_NUM_BANKS-1:0] [DCCM_FDATA_WIDTH-1:0] dccm_bank_dout;
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logic [DCCM_FDATA_WIDTH-1:0] wrdata;
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logic [DCCM_NUM_BANKS-1:0][DCCM_FDATA_WIDTH-1:0] wr_data_bank;
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logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_lo_q;
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logic [(DCCM_WIDTH_BITS+DCCM_BANK_BITS-1):DCCM_WIDTH_BITS] dccm_rd_addr_hi_q;
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logic [DCCM_NUM_BANKS-1:0] dccm_clken;
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assign rd_unaligned = (dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
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assign wr_unaligned = (dccm_wr_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS] != dccm_wr_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]);
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// Align the read data
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assign dccm_rd_data_lo[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
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assign dccm_rd_data_hi[DCCM_FDATA_WIDTH-1:0] = dccm_bank_dout[dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]][DCCM_FDATA_WIDTH-1:0];
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// Generate even/odd address
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// 8 Banks, 16KB each (2048 x 72)
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for (genvar i=0; i<32'(DCCM_NUM_BANKS); i++) begin: mem_bank
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assign wren_bank[i] = dccm_wren & ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_wr_addr_lo[2+:DCCM_BANK_BITS] == i));
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assign rden_bank[i] = dccm_rden & ((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) | (dccm_rd_addr_lo[2+:DCCM_BANK_BITS] == i));
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assign addr_bank[i][(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] = wren_bank[i] ? (((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ?
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dccm_wr_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
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dccm_wr_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]) :
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(((dccm_rd_addr_hi[2+:DCCM_BANK_BITS] == i) & rd_unaligned) ?
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dccm_rd_addr_hi[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS] :
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dccm_rd_addr_lo[(DCCM_BANK_BITS+DCCM_WIDTH_BITS)+:DCCM_INDEX_BITS]);
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assign wr_data_bank[i] = ((dccm_wr_addr_hi[2+:DCCM_BANK_BITS] == i) & wr_unaligned) ? dccm_wr_data_hi[DCCM_FDATA_WIDTH-1:0] : dccm_wr_data_lo[DCCM_FDATA_WIDTH-1:0];
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// clock gating section
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assign dccm_clken[i] = (wren_bank[i] | rden_bank[i] | clk_override) ;
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// end clock gating section
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`ifdef VERILATOR
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el2_ram #(DCCM_INDEX_DEPTH,39) ram (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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`else
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if (DCCM_INDEX_DEPTH == 32768) begin : dccm
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ram_32768x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 16384) begin : dccm
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ram_16384x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 8192) begin : dccm
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ram_8192x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 4096) begin : dccm
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ram_4096x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 3072) begin : dccm
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ram_3072x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 2048) begin : dccm
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ram_2048x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 1024) begin : dccm
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ram_1024x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 512) begin : dccm
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ram_512x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
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.*
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);
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end
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else if (DCCM_INDEX_DEPTH == 256) begin : dccm
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ram_256x39 dccm_bank (
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// Primary ports
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.ME(dccm_clken[i]),
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.CLK(clk),
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.WE(wren_bank[i]),
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.ADR(addr_bank[i]),
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.D(wr_data_bank[i][DCCM_FDATA_WIDTH-1:0]),
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.Q(dccm_bank_dout[i][DCCM_FDATA_WIDTH-1:0]),
|
||||
.*
|
||||
);
|
||||
end
|
||||
`endif // VERILATOR
|
||||
end : mem_bank
|
||||
|
||||
// Flops
|
||||
rvdffs #(DCCM_BANK_BITS) rd_addr_lo_ff (.*, .din(dccm_rd_addr_lo[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_lo_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
|
||||
rvdffs #(DCCM_BANK_BITS) rd_addr_hi_ff (.*, .din(dccm_rd_addr_hi[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .dout(dccm_rd_addr_hi_q[DCCM_WIDTH_BITS+:DCCM_BANK_BITS]), .en(1'b1));
|
||||
|
||||
`undef EL2_LOCAL_DCCM_RAM_TEST_PORTS
|
||||
|
||||
endmodule // el2_lsu_dccm_mem
|
||||
|
||||
|
||||
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Reference in New Issue