I$ Almost done
This commit is contained in:
waleed-lm
parent
f36fd18211
commit
2e97626f0a
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@ -1,4 +1,20 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_debug_rd_data",
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"sources":[
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_data",
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"sources":[
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_sel_premux_data",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_premux_data",
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"~EL2_IC_DATA|EL2_IC_DATA>io_ic_rd_hit"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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3061
EL2_IC_DATA.fir
3061
EL2_IC_DATA.fir
File diff suppressed because it is too large
Load Diff
669
EL2_IC_DATA.v
669
EL2_IC_DATA.v
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@ -3,7 +3,7 @@ module EL2_IC_DATA(
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input reset,
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input io_rst_l,
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input io_clk_override,
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input [11:0] io_ic_rw_addr,
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input [12:0] io_ic_rw_addr,
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input [1:0] io_ic_wr_en,
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input io_ic_rd_en,
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input [70:0] io_ic_wr_data_0,
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@ -13,7 +13,7 @@ module EL2_IC_DATA(
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output [70:0] io_ic_debug_rd_data,
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output [1:0] io_ic_parerr,
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output [1:0] io_ic_eccerr,
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input [14:0] io_ic_debug_addr,
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input [12:0] io_ic_debug_addr,
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input io_ic_debug_rd_en,
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input io_ic_debug_wr_en,
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input io_ic_debug_tag_array,
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@ -22,13 +22,662 @@ module EL2_IC_DATA(
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input io_ic_sel_premux_data,
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input [1:0] io_ic_rd_hit,
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input io_scan_mode,
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input io_mask_0_0,
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input io_mask_0_1,
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input io_mask_1_0,
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input io_mask_1_1
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output io_test_port2,
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output [70:0] io_test_port_0_0,
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output [70:0] io_test_port_0_1,
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output [70:0] io_test_port_1_0,
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output [70:0] io_test_port_1_1
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);
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assign io_ic_rd_data = 64'h0; // @[el2_ifu_ic_mem.scala 215:17]
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assign io_ic_debug_rd_data = 71'h0; // @[el2_ifu_ic_mem.scala 214:23]
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assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 217:16]
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assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 216:16]
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`ifdef RANDOMIZE_MEM_INIT
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reg [95:0] _RAND_0;
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reg [95:0] _RAND_5;
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reg [95:0] _RAND_10;
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reg [95:0] _RAND_15;
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`endif // RANDOMIZE_MEM_INIT
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`ifdef RANDOMIZE_REG_INIT
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reg [31:0] _RAND_1;
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reg [31:0] _RAND_2;
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reg [31:0] _RAND_3;
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reg [31:0] _RAND_4;
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reg [31:0] _RAND_6;
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reg [31:0] _RAND_7;
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reg [31:0] _RAND_8;
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reg [31:0] _RAND_9;
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reg [31:0] _RAND_11;
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reg [31:0] _RAND_12;
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reg [31:0] _RAND_13;
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reg [31:0] _RAND_14;
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reg [31:0] _RAND_16;
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reg [31:0] _RAND_17;
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reg [31:0] _RAND_18;
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reg [31:0] _RAND_19;
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reg [31:0] _RAND_20;
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reg [31:0] _RAND_21;
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reg [31:0] _RAND_22;
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`endif // RANDOMIZE_REG_INIT
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reg [70:0] data_mem_0_0 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_0__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_0__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [8:0] data_mem_0_0__T_137_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_144_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_151_addr_pipe_0;
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reg [8:0] data_mem_0_0__T_158_addr_pipe_0;
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reg [70:0] data_mem_0_1 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_0_1__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_0_1__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [8:0] data_mem_0_1__T_137_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_144_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_151_addr_pipe_0;
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reg [8:0] data_mem_0_1__T_158_addr_pipe_0;
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reg [70:0] data_mem_1_0 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_0__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_0__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [8:0] data_mem_1_0__T_137_addr_pipe_0;
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reg [8:0] data_mem_1_0__T_144_addr_pipe_0;
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reg [8:0] data_mem_1_0__T_151_addr_pipe_0;
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reg [8:0] data_mem_1_0__T_158_addr_pipe_0;
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reg [70:0] data_mem_1_1 [0:511]; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_137_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_137_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_144_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_144_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_151_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_151_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_158_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_130_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_130_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_130_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_135_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_135_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_135_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_142_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_142_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_142_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_149_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_149_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_149_en; // @[el2_ifu_ic_mem.scala 245:29]
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wire [70:0] data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
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wire [8:0] data_mem_1_1__T_156_addr; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_156_mask; // @[el2_ifu_ic_mem.scala 245:29]
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wire data_mem_1_1__T_156_en; // @[el2_ifu_ic_mem.scala 245:29]
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reg [8:0] data_mem_1_1__T_137_addr_pipe_0;
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reg [8:0] data_mem_1_1__T_144_addr_pipe_0;
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reg [8:0] data_mem_1_1__T_151_addr_pipe_0;
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reg [8:0] data_mem_1_1__T_158_addr_pipe_0;
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wire _T = ~io_ic_debug_tag_array; // @[el2_ifu_ic_mem.scala 210:70]
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wire _T_1 = io_ic_debug_rd_en & _T; // @[el2_ifu_ic_mem.scala 210:68]
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wire [1:0] _T_3 = {_T_1,_T_1}; // @[Cat.scala 29:58]
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wire [1:0] ic_debug_rd_way_en = _T_3 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 210:94]
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wire _T_5 = io_ic_debug_wr_en & _T; // @[el2_ifu_ic_mem.scala 211:68]
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wire [1:0] _T_7 = {_T_5,_T_5}; // @[Cat.scala 29:58]
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wire [1:0] ic_debug_wr_way_en = _T_7 & io_ic_debug_way; // @[el2_ifu_ic_mem.scala 211:94]
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wire _T_9 = ~io_ic_debug_addr[3]; // @[el2_ifu_ic_mem.scala 213:107]
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wire [1:0] _T_11 = {_T_9,_T_9}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_12 = ic_debug_wr_way_en & _T_11; // @[el2_ifu_ic_mem.scala 213:36]
|
||||
wire [1:0] _T_13 = io_ic_wr_en | _T_12; // @[el2_ifu_ic_mem.scala 213:16]
|
||||
wire [1:0] _T_17 = {io_ic_debug_addr[3],io_ic_debug_addr[3]}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _T_18 = ic_debug_wr_way_en & _T_17; // @[el2_ifu_ic_mem.scala 213:36]
|
||||
wire [1:0] _T_19 = io_ic_wr_en | _T_18; // @[el2_ifu_ic_mem.scala 213:16]
|
||||
wire _T_23 = _T_9 & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 215:66]
|
||||
wire [70:0] _T_25 = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0; // @[el2_ifu_ic_mem.scala 215:8]
|
||||
wire _T_28 = io_ic_debug_addr[3] & io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 215:66]
|
||||
wire [70:0] _T_30 = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1; // @[el2_ifu_ic_mem.scala 215:8]
|
||||
wire _T_32 = io_ic_debug_rd_en | io_ic_debug_wr_en; // @[el2_ifu_ic_mem.scala 216:49]
|
||||
wire [11:0] _T_35 = {io_ic_debug_addr[12:3],2'h0}; // @[Cat.scala 29:58]
|
||||
wire [11:0] _T_37 = _T_32 ? _T_35 : io_ic_rw_addr[12:1]; // @[el2_ifu_ic_mem.scala 216:29]
|
||||
wire [12:0] ic_rw_addr_q = {_T_37,1'h0}; // @[Cat.scala 29:58]
|
||||
wire _T_38 = io_ic_rd_en | io_ic_debug_rd_en; // @[el2_ifu_ic_mem.scala 217:44]
|
||||
wire _T_39 = |io_ic_wr_en; // @[el2_ifu_ic_mem.scala 217:82]
|
||||
wire _T_40 = ~_T_39; // @[el2_ifu_ic_mem.scala 217:68]
|
||||
wire ic_rd_en_with_debug = _T_38 & _T_40; // @[el2_ifu_ic_mem.scala 217:66]
|
||||
wire _T_43 = ~ic_rw_addr_q[3]; // @[el2_ifu_ic_mem.scala 219:15]
|
||||
wire _T_47 = ic_rw_addr_q[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 220:55]
|
||||
wire _T_48 = ic_rw_addr_q[3] & _T_47; // @[el2_ifu_ic_mem.scala 220:36]
|
||||
wire _T_58 = _T_43 & _T_47; // @[el2_ifu_ic_mem.scala 222:37]
|
||||
wire _T_95 = ic_rw_addr_q[3] | _T_58; // @[Mux.scala 27:72]
|
||||
wire ic_b_rden_0 = _T_95 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 222:107]
|
||||
wire [1:0] _T_99 = {ic_b_rden_0,ic_b_rden_0}; // @[Cat.scala 29:58]
|
||||
wire [1:0] _GEN_24 = {{1'd0}, io_clk_override}; // @[el2_ifu_ic_mem.scala 225:62]
|
||||
wire [1:0] _T_100 = _T_99 | _GEN_24; // @[el2_ifu_ic_mem.scala 225:62]
|
||||
wire [1:0] _T_101 = _T_100 | _T_19; // @[el2_ifu_ic_mem.scala 225:80]
|
||||
wire [1:0] _T_105 = _T_100 | _T_13; // @[el2_ifu_ic_mem.scala 227:82]
|
||||
wire [1:0] _T_106 = _T_105 | _T_101; // @[el2_ifu_ic_mem.scala 227:101]
|
||||
wire [8:0] ic_rw_addr_q_inc = ic_rw_addr_q[12:4] + 9'h1; // @[el2_ifu_ic_mem.scala 230:77]
|
||||
wire _T_113 = _T_48 & ic_rd_en_with_debug; // @[el2_ifu_ic_mem.scala 231:82]
|
||||
wire ic_rw_addr_wrap = _T_113 & _T_40; // @[el2_ifu_ic_mem.scala 231:104]
|
||||
reg [12:0] ic_rw_addr_ff; // @[el2_ifu_ic_mem.scala 234:30]
|
||||
reg [1:0] ic_debug_rd_way_en_ff; // @[el2_ifu_ic_mem.scala 236:38]
|
||||
reg ic_debug_rd_en_ff; // @[el2_ifu_ic_mem.scala 237:34]
|
||||
wire _T_122 = ~ic_rw_addr_wrap; // @[el2_ifu_ic_mem.scala 241:31]
|
||||
wire [8:0] _T_126 = {ic_rw_addr_q[12:6],ic_rw_addr_q_inc[5:4]}; // @[Cat.scala 29:58]
|
||||
wire [8:0] _T_127 = _T_122 ? ic_rw_addr_q[12:4] : _T_126; // @[el2_ifu_ic_mem.scala 241:30]
|
||||
wire [12:0] ic_rw_addr_bank_q_0 = {{4'd0}, _T_127}; // @[el2_ifu_ic_mem.scala 240:31 el2_ifu_ic_mem.scala 241:24]
|
||||
wire [12:0] ic_rw_addr_bank_q_1 = {{4'd0}, ic_rw_addr_q[12:4]}; // @[el2_ifu_ic_mem.scala 240:31 el2_ifu_ic_mem.scala 242:24]
|
||||
wire _T_160 = ~ic_rw_addr_ff[3]; // @[el2_ifu_ic_mem.scala 259:71]
|
||||
wire [9:0] _T_170 = {_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_179 = {_T_170,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_188 = {_T_179,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_197 = {_T_188,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_206 = {_T_197,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_215 = {_T_206,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_224 = {_T_215,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_231 = {_T_224,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160,_T_160}; // @[Cat.scala 29:58]
|
||||
wire [70:0] wb_dout_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_232 = _T_231 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [9:0] _T_244 = {ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_253 = {_T_244,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_262 = {_T_253,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_271 = {_T_262,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_280 = {_T_271,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_289 = {_T_280,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_298 = {_T_289,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_305 = {_T_298,ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3],ic_rw_addr_ff[3]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] wb_dout_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_306 = _T_305 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_0 = _T_232 | _T_306; // @[el2_ifu_ic_mem.scala 259:102]
|
||||
wire [70:0] wb_dout_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_380 = _T_231 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 247:21 el2_ifu_ic_mem.scala 250:19 el2_ifu_ic_mem.scala 254:19]
|
||||
wire [70:0] _T_454 = _T_305 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 259:78]
|
||||
wire [70:0] wb_dout_way_pre_lower_1 = _T_380 | _T_454; // @[el2_ifu_ic_mem.scala 259:102]
|
||||
wire _T_457 = 1'h0 - 1'h1; // @[el2_ifu_ic_mem.scala 263:77]
|
||||
wire _T_458 = ic_rw_addr_ff[3] == _T_457; // @[el2_ifu_ic_mem.scala 263:71]
|
||||
wire [9:0] _T_468 = {_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_477 = {_T_468,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_486 = {_T_477,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_495 = {_T_486,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_504 = {_T_495,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_513 = {_T_504,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_522 = {_T_513,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_529 = {_T_522,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458,_T_458}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_530 = _T_529 & wb_dout_0_0; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] _T_606 = _T_231 & wb_dout_0_1; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_0 = _T_530 | _T_606; // @[el2_ifu_ic_mem.scala 263:106]
|
||||
wire [70:0] _T_682 = _T_529 & wb_dout_1_0; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] _T_758 = _T_231 & wb_dout_1_1; // @[el2_ifu_ic_mem.scala 263:82]
|
||||
wire [70:0] wb_dout_way_pre_upper_1 = _T_682 | _T_758; // @[el2_ifu_ic_mem.scala 263:106]
|
||||
wire [141:0] wb_dout_way_pre_0 = {wb_dout_way_pre_upper_0,wb_dout_way_pre_lower_0}; // @[Cat.scala 29:58]
|
||||
wire [141:0] wb_dout_way_pre_1 = {wb_dout_way_pre_upper_1,wb_dout_way_pre_lower_1}; // @[Cat.scala 29:58]
|
||||
wire _T_760 = ic_rw_addr_ff[2:1] == 2'h0; // @[el2_ifu_ic_mem.scala 269:36]
|
||||
wire [9:0] _T_770 = {_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_779 = {_T_770,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_788 = {_T_779,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_797 = {_T_788,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_806 = {_T_797,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_815 = {_T_806,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_824 = {_T_815,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760,_T_760}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_826 = _T_824 & wb_dout_way_pre_0[63:0]; // @[el2_ifu_ic_mem.scala 269:44]
|
||||
wire _T_828 = ic_rw_addr_ff[2:1] == 2'h1; // @[el2_ifu_ic_mem.scala 270:36]
|
||||
wire [9:0] _T_838 = {_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_847 = {_T_838,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_856 = {_T_847,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_865 = {_T_856,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_874 = {_T_865,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_883 = {_T_874,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_892 = {_T_883,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828,_T_828}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_895 = {wb_dout_way_pre_0[86:71],wb_dout_way_pre_0[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_896 = _T_892 & _T_895; // @[el2_ifu_ic_mem.scala 270:44]
|
||||
wire [63:0] _T_897 = _T_826 | _T_896; // @[el2_ifu_ic_mem.scala 269:71]
|
||||
wire _T_899 = ic_rw_addr_ff[2:1] == 2'h2; // @[el2_ifu_ic_mem.scala 271:36]
|
||||
wire [9:0] _T_909 = {_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_918 = {_T_909,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_927 = {_T_918,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_936 = {_T_927,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_945 = {_T_936,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_954 = {_T_945,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_963 = {_T_954,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899,_T_899}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_966 = {wb_dout_way_pre_0[102:71],wb_dout_way_pre_0[63:32]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_967 = _T_963 & _T_966; // @[el2_ifu_ic_mem.scala 271:44]
|
||||
wire [63:0] _T_968 = _T_897 | _T_967; // @[el2_ifu_ic_mem.scala 270:122]
|
||||
wire _T_970 = ic_rw_addr_ff[2:1] == 2'h3; // @[el2_ifu_ic_mem.scala 272:36]
|
||||
wire [9:0] _T_980 = {_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_989 = {_T_980,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_998 = {_T_989,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_1007 = {_T_998,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_1016 = {_T_1007,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1025 = {_T_1016,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1034 = {_T_1025,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970,_T_970}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1037 = {wb_dout_way_pre_0[118:71],wb_dout_way_pre_0[63:48]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1038 = _T_1034 & _T_1037; // @[el2_ifu_ic_mem.scala 272:44]
|
||||
wire [63:0] wb_dout_way_0 = _T_968 | _T_1038; // @[el2_ifu_ic_mem.scala 271:122]
|
||||
wire [63:0] _T_1106 = _T_824 & wb_dout_way_pre_1[63:0]; // @[el2_ifu_ic_mem.scala 269:44]
|
||||
wire [63:0] _T_1175 = {wb_dout_way_pre_1[86:71],wb_dout_way_pre_1[63:16]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1176 = _T_892 & _T_1175; // @[el2_ifu_ic_mem.scala 270:44]
|
||||
wire [63:0] _T_1177 = _T_1106 | _T_1176; // @[el2_ifu_ic_mem.scala 269:71]
|
||||
wire [63:0] _T_1246 = {wb_dout_way_pre_1[102:71],wb_dout_way_pre_1[63:32]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1247 = _T_963 & _T_1246; // @[el2_ifu_ic_mem.scala 271:44]
|
||||
wire [63:0] _T_1248 = _T_1177 | _T_1247; // @[el2_ifu_ic_mem.scala 270:122]
|
||||
wire [63:0] _T_1317 = {wb_dout_way_pre_1[118:71],wb_dout_way_pre_1[63:48]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1318 = _T_1034 & _T_1317; // @[el2_ifu_ic_mem.scala 272:44]
|
||||
wire [63:0] wb_dout_way_1 = _T_1248 | _T_1318; // @[el2_ifu_ic_mem.scala 271:122]
|
||||
wire [1:0] ic_rd_hit_q = ic_debug_rd_en_ff ? ic_debug_rd_way_en_ff : io_ic_rd_hit; // @[el2_ifu_ic_mem.scala 275:24]
|
||||
wire [63:0] wb_dout_way_with_premux_0 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_0; // @[el2_ifu_ic_mem.scala 276:52]
|
||||
wire [63:0] wb_dout_way_with_premux_1 = io_ic_sel_premux_data ? io_ic_premux_data : wb_dout_way_1; // @[el2_ifu_ic_mem.scala 276:52]
|
||||
wire _T_1321 = ic_rd_hit_q[0] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 282:79]
|
||||
wire _T_1323 = ic_rd_hit_q[1] | io_ic_sel_premux_data; // @[el2_ifu_ic_mem.scala 282:79]
|
||||
wire [9:0] _T_1333 = {_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1342 = {_T_1333,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1351 = {_T_1342,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_1360 = {_T_1351,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_1369 = {_T_1360,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1378 = {_T_1369,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1387 = {_T_1378,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321,_T_1321}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1388 = _T_1387 & wb_dout_way_with_premux_0; // @[el2_lib.scala 189:94]
|
||||
wire [9:0] _T_1398 = {_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1407 = {_T_1398,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1416 = {_T_1407,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_1425 = {_T_1416,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_1434 = {_T_1425,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1443 = {_T_1434,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1452 = {_T_1443,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323,_T_1323}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1453 = _T_1452 & wb_dout_way_with_premux_1; // @[el2_lib.scala 189:94]
|
||||
wire [9:0] _T_1468 = {ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1477 = {_T_1468,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1486 = {_T_1477,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_1495 = {_T_1486,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_1504 = {_T_1495,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1513 = {_T_1504,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1522 = {_T_1513,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1529 = {_T_1522,ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0],ic_rd_hit_q[0]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1530 = _T_1529 & wb_dout_way_pre_0[70:0]; // @[el2_lib.scala 189:94]
|
||||
wire [9:0] _T_1540 = {ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [18:0] _T_1549 = {_T_1540,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [27:0] _T_1558 = {_T_1549,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [36:0] _T_1567 = {_T_1558,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [45:0] _T_1576 = {_T_1567,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [54:0] _T_1585 = {_T_1576,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [63:0] _T_1594 = {_T_1585,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1601 = {_T_1594,ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1],ic_rd_hit_q[1]}; // @[Cat.scala 29:58]
|
||||
wire [70:0] _T_1602 = _T_1601 & wb_dout_way_pre_1[70:0]; // @[el2_lib.scala 189:94]
|
||||
assign data_mem_0_0__T_137_addr = data_mem_0_0__T_137_addr_pipe_0;
|
||||
assign data_mem_0_0__T_137_data = data_mem_0_0[data_mem_0_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_144_addr = data_mem_0_0__T_144_addr_pipe_0;
|
||||
assign data_mem_0_0__T_144_data = data_mem_0_0[data_mem_0_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_151_addr = data_mem_0_0__T_151_addr_pipe_0;
|
||||
assign data_mem_0_0__T_151_data = data_mem_0_0[data_mem_0_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_158_addr = data_mem_0_0__T_158_addr_pipe_0;
|
||||
assign data_mem_0_0__T_158_data = data_mem_0_0[data_mem_0_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_0__T_130_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
|
||||
assign data_mem_0_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_0__T_130_mask = 1'h1;
|
||||
assign data_mem_0_0__T_130_en = 1'h1;
|
||||
assign data_mem_0_0__T_135_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
|
||||
assign data_mem_0_0__T_135_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_0__T_135_mask = 1'h1;
|
||||
assign data_mem_0_0__T_135_en = _T_30[0] & _T_101[0];
|
||||
assign data_mem_0_0__T_142_data = 71'h0;
|
||||
assign data_mem_0_0__T_142_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_0_0__T_142_mask = 1'h0;
|
||||
assign data_mem_0_0__T_142_en = _T_30[1] & _T_101[1];
|
||||
assign data_mem_0_0__T_149_data = 71'h0;
|
||||
assign data_mem_0_0__T_149_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_0__T_149_mask = 1'h0;
|
||||
assign data_mem_0_0__T_149_en = _T_25[0] & _T_106[0];
|
||||
assign data_mem_0_0__T_156_data = 71'h0;
|
||||
assign data_mem_0_0__T_156_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_0_0__T_156_mask = 1'h0;
|
||||
assign data_mem_0_0__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_0_1__T_137_addr = data_mem_0_1__T_137_addr_pipe_0;
|
||||
assign data_mem_0_1__T_137_data = data_mem_0_1[data_mem_0_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_144_addr = data_mem_0_1__T_144_addr_pipe_0;
|
||||
assign data_mem_0_1__T_144_data = data_mem_0_1[data_mem_0_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_151_addr = data_mem_0_1__T_151_addr_pipe_0;
|
||||
assign data_mem_0_1__T_151_data = data_mem_0_1[data_mem_0_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_158_addr = data_mem_0_1__T_158_addr_pipe_0;
|
||||
assign data_mem_0_1__T_158_data = data_mem_0_1[data_mem_0_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_0_1__T_130_data = 71'h0;
|
||||
assign data_mem_0_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_1__T_130_mask = 1'h0;
|
||||
assign data_mem_0_1__T_130_en = 1'h1;
|
||||
assign data_mem_0_1__T_135_data = 71'h0;
|
||||
assign data_mem_0_1__T_135_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_1__T_135_mask = 1'h0;
|
||||
assign data_mem_0_1__T_135_en = _T_30[0] & _T_101[0];
|
||||
assign data_mem_0_1__T_142_data = 71'h0;
|
||||
assign data_mem_0_1__T_142_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_0_1__T_142_mask = 1'h0;
|
||||
assign data_mem_0_1__T_142_en = _T_30[1] & _T_101[1];
|
||||
assign data_mem_0_1__T_149_data = _T_28 ? io_ic_debug_wr_data : io_ic_wr_data_1;
|
||||
assign data_mem_0_1__T_149_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_0_1__T_149_mask = 1'h1;
|
||||
assign data_mem_0_1__T_149_en = _T_25[0] & _T_106[0];
|
||||
assign data_mem_0_1__T_156_data = 71'h0;
|
||||
assign data_mem_0_1__T_156_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_0_1__T_156_mask = 1'h0;
|
||||
assign data_mem_0_1__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_1_0__T_137_addr = data_mem_1_0__T_137_addr_pipe_0;
|
||||
assign data_mem_1_0__T_137_data = data_mem_1_0[data_mem_1_0__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_144_addr = data_mem_1_0__T_144_addr_pipe_0;
|
||||
assign data_mem_1_0__T_144_data = data_mem_1_0[data_mem_1_0__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_151_addr = data_mem_1_0__T_151_addr_pipe_0;
|
||||
assign data_mem_1_0__T_151_data = data_mem_1_0[data_mem_1_0__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_158_addr = data_mem_1_0__T_158_addr_pipe_0;
|
||||
assign data_mem_1_0__T_158_data = data_mem_1_0[data_mem_1_0__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_0__T_130_data = 71'h0;
|
||||
assign data_mem_1_0__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_0__T_130_mask = 1'h0;
|
||||
assign data_mem_1_0__T_130_en = 1'h1;
|
||||
assign data_mem_1_0__T_135_data = 71'h0;
|
||||
assign data_mem_1_0__T_135_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_0__T_135_mask = 1'h0;
|
||||
assign data_mem_1_0__T_135_en = _T_30[0] & _T_101[0];
|
||||
assign data_mem_1_0__T_142_data = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0;
|
||||
assign data_mem_1_0__T_142_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_1_0__T_142_mask = 1'h1;
|
||||
assign data_mem_1_0__T_142_en = _T_30[1] & _T_101[1];
|
||||
assign data_mem_1_0__T_149_data = 71'h0;
|
||||
assign data_mem_1_0__T_149_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_0__T_149_mask = 1'h0;
|
||||
assign data_mem_1_0__T_149_en = _T_25[0] & _T_106[0];
|
||||
assign data_mem_1_0__T_156_data = 71'h0;
|
||||
assign data_mem_1_0__T_156_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_1_0__T_156_mask = 1'h0;
|
||||
assign data_mem_1_0__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign data_mem_1_1__T_137_addr = data_mem_1_1__T_137_addr_pipe_0;
|
||||
assign data_mem_1_1__T_137_data = data_mem_1_1[data_mem_1_1__T_137_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_144_addr = data_mem_1_1__T_144_addr_pipe_0;
|
||||
assign data_mem_1_1__T_144_data = data_mem_1_1[data_mem_1_1__T_144_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_151_addr = data_mem_1_1__T_151_addr_pipe_0;
|
||||
assign data_mem_1_1__T_151_data = data_mem_1_1[data_mem_1_1__T_151_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_158_addr = data_mem_1_1__T_158_addr_pipe_0;
|
||||
assign data_mem_1_1__T_158_data = data_mem_1_1[data_mem_1_1__T_158_addr]; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
assign data_mem_1_1__T_130_data = 71'h0;
|
||||
assign data_mem_1_1__T_130_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_1__T_130_mask = 1'h0;
|
||||
assign data_mem_1_1__T_130_en = 1'h1;
|
||||
assign data_mem_1_1__T_135_data = 71'h0;
|
||||
assign data_mem_1_1__T_135_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_1__T_135_mask = 1'h0;
|
||||
assign data_mem_1_1__T_135_en = _T_30[0] & _T_101[0];
|
||||
assign data_mem_1_1__T_142_data = 71'h0;
|
||||
assign data_mem_1_1__T_142_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_1_1__T_142_mask = 1'h0;
|
||||
assign data_mem_1_1__T_142_en = _T_30[1] & _T_101[1];
|
||||
assign data_mem_1_1__T_149_data = 71'h0;
|
||||
assign data_mem_1_1__T_149_addr = ic_rw_addr_bank_q_0[12:4];
|
||||
assign data_mem_1_1__T_149_mask = 1'h0;
|
||||
assign data_mem_1_1__T_149_en = _T_25[0] & _T_106[0];
|
||||
assign data_mem_1_1__T_156_data = _T_23 ? io_ic_debug_wr_data : io_ic_wr_data_0;
|
||||
assign data_mem_1_1__T_156_addr = ic_rw_addr_bank_q_1[12:4];
|
||||
assign data_mem_1_1__T_156_mask = 1'h1;
|
||||
assign data_mem_1_1__T_156_en = _T_25[1] & _T_106[1];
|
||||
assign io_ic_rd_data = _T_1388 | _T_1453; // @[el2_ifu_ic_mem.scala 282:17]
|
||||
assign io_ic_debug_rd_data = _T_1530 | _T_1602; // @[el2_ifu_ic_mem.scala 278:23 el2_ifu_ic_mem.scala 284:23]
|
||||
assign io_ic_parerr = 2'h0; // @[el2_ifu_ic_mem.scala 279:16]
|
||||
assign io_ic_eccerr = 2'h0; // @[el2_ifu_ic_mem.scala 280:16]
|
||||
assign io_test_port2 = 1'h0; // @[el2_ifu_ic_mem.scala 286:17]
|
||||
assign io_test_port_0_0 = data_mem_0_0__T_137_data; // @[el2_ifu_ic_mem.scala 287:16]
|
||||
assign io_test_port_0_1 = data_mem_0_1__T_144_data; // @[el2_ifu_ic_mem.scala 287:16]
|
||||
assign io_test_port_1_0 = data_mem_1_0__T_151_data; // @[el2_ifu_ic_mem.scala 287:16]
|
||||
assign io_test_port_1_1 = data_mem_1_1__T_158_data; // @[el2_ifu_ic_mem.scala 287:16]
|
||||
`ifdef RANDOMIZE_GARBAGE_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_INVALID_ASSIGN
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
`define RANDOMIZE
|
||||
`endif
|
||||
`ifndef RANDOM
|
||||
`define RANDOM $random
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
integer initvar;
|
||||
`endif
|
||||
`ifndef SYNTHESIS
|
||||
`ifdef FIRRTL_BEFORE_INITIAL
|
||||
`FIRRTL_BEFORE_INITIAL
|
||||
`endif
|
||||
initial begin
|
||||
`ifdef RANDOMIZE
|
||||
`ifdef INIT_RANDOM
|
||||
`INIT_RANDOM
|
||||
`endif
|
||||
`ifndef VERILATOR
|
||||
`ifdef RANDOMIZE_DELAY
|
||||
#`RANDOMIZE_DELAY begin end
|
||||
`else
|
||||
#0.002 begin end
|
||||
`endif
|
||||
`endif
|
||||
`ifdef RANDOMIZE_MEM_INIT
|
||||
_RAND_0 = {3{`RANDOM}};
|
||||
for (initvar = 0; initvar < 512; initvar = initvar+1)
|
||||
data_mem_0_0[initvar] = _RAND_0[70:0];
|
||||
_RAND_5 = {3{`RANDOM}};
|
||||
for (initvar = 0; initvar < 512; initvar = initvar+1)
|
||||
data_mem_0_1[initvar] = _RAND_5[70:0];
|
||||
_RAND_10 = {3{`RANDOM}};
|
||||
for (initvar = 0; initvar < 512; initvar = initvar+1)
|
||||
data_mem_1_0[initvar] = _RAND_10[70:0];
|
||||
_RAND_15 = {3{`RANDOM}};
|
||||
for (initvar = 0; initvar < 512; initvar = initvar+1)
|
||||
data_mem_1_1[initvar] = _RAND_15[70:0];
|
||||
`endif // RANDOMIZE_MEM_INIT
|
||||
`ifdef RANDOMIZE_REG_INIT
|
||||
_RAND_1 = {1{`RANDOM}};
|
||||
data_mem_0_0__T_137_addr_pipe_0 = _RAND_1[8:0];
|
||||
_RAND_2 = {1{`RANDOM}};
|
||||
data_mem_0_0__T_144_addr_pipe_0 = _RAND_2[8:0];
|
||||
_RAND_3 = {1{`RANDOM}};
|
||||
data_mem_0_0__T_151_addr_pipe_0 = _RAND_3[8:0];
|
||||
_RAND_4 = {1{`RANDOM}};
|
||||
data_mem_0_0__T_158_addr_pipe_0 = _RAND_4[8:0];
|
||||
_RAND_6 = {1{`RANDOM}};
|
||||
data_mem_0_1__T_137_addr_pipe_0 = _RAND_6[8:0];
|
||||
_RAND_7 = {1{`RANDOM}};
|
||||
data_mem_0_1__T_144_addr_pipe_0 = _RAND_7[8:0];
|
||||
_RAND_8 = {1{`RANDOM}};
|
||||
data_mem_0_1__T_151_addr_pipe_0 = _RAND_8[8:0];
|
||||
_RAND_9 = {1{`RANDOM}};
|
||||
data_mem_0_1__T_158_addr_pipe_0 = _RAND_9[8:0];
|
||||
_RAND_11 = {1{`RANDOM}};
|
||||
data_mem_1_0__T_137_addr_pipe_0 = _RAND_11[8:0];
|
||||
_RAND_12 = {1{`RANDOM}};
|
||||
data_mem_1_0__T_144_addr_pipe_0 = _RAND_12[8:0];
|
||||
_RAND_13 = {1{`RANDOM}};
|
||||
data_mem_1_0__T_151_addr_pipe_0 = _RAND_13[8:0];
|
||||
_RAND_14 = {1{`RANDOM}};
|
||||
data_mem_1_0__T_158_addr_pipe_0 = _RAND_14[8:0];
|
||||
_RAND_16 = {1{`RANDOM}};
|
||||
data_mem_1_1__T_137_addr_pipe_0 = _RAND_16[8:0];
|
||||
_RAND_17 = {1{`RANDOM}};
|
||||
data_mem_1_1__T_144_addr_pipe_0 = _RAND_17[8:0];
|
||||
_RAND_18 = {1{`RANDOM}};
|
||||
data_mem_1_1__T_151_addr_pipe_0 = _RAND_18[8:0];
|
||||
_RAND_19 = {1{`RANDOM}};
|
||||
data_mem_1_1__T_158_addr_pipe_0 = _RAND_19[8:0];
|
||||
_RAND_20 = {1{`RANDOM}};
|
||||
ic_rw_addr_ff = _RAND_20[12:0];
|
||||
_RAND_21 = {1{`RANDOM}};
|
||||
ic_debug_rd_way_en_ff = _RAND_21[1:0];
|
||||
_RAND_22 = {1{`RANDOM}};
|
||||
ic_debug_rd_en_ff = _RAND_22[0:0];
|
||||
`endif // RANDOMIZE_REG_INIT
|
||||
`endif // RANDOMIZE
|
||||
end // initial
|
||||
`ifdef FIRRTL_AFTER_INITIAL
|
||||
`FIRRTL_AFTER_INITIAL
|
||||
`endif
|
||||
`endif // SYNTHESIS
|
||||
always @(posedge clock) begin
|
||||
if(data_mem_0_0__T_130_en & data_mem_0_0__T_130_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_130_addr] <= data_mem_0_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_0__T_135_en & data_mem_0_0__T_135_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_135_addr] <= data_mem_0_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_0__T_142_en & data_mem_0_0__T_142_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_142_addr] <= data_mem_0_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_0__T_149_en & data_mem_0_0__T_149_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_149_addr] <= data_mem_0_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_0__T_156_en & data_mem_0_0__T_156_mask) begin
|
||||
data_mem_0_0[data_mem_0_0__T_156_addr] <= data_mem_0_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
data_mem_0_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_0_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_0_1__T_130_en & data_mem_0_1__T_130_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_130_addr] <= data_mem_0_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_1__T_135_en & data_mem_0_1__T_135_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_135_addr] <= data_mem_0_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_1__T_142_en & data_mem_0_1__T_142_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_142_addr] <= data_mem_0_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_1__T_149_en & data_mem_0_1__T_149_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_149_addr] <= data_mem_0_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_0_1__T_156_en & data_mem_0_1__T_156_mask) begin
|
||||
data_mem_0_1[data_mem_0_1__T_156_addr] <= data_mem_0_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
data_mem_0_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_0_1__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_0_1__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_1_0__T_130_en & data_mem_1_0__T_130_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_130_addr] <= data_mem_1_0__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_0__T_135_en & data_mem_1_0__T_135_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_135_addr] <= data_mem_1_0__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_0__T_142_en & data_mem_1_0__T_142_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_142_addr] <= data_mem_1_0__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_0__T_149_en & data_mem_1_0__T_149_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_149_addr] <= data_mem_1_0__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_0__T_156_en & data_mem_1_0__T_156_mask) begin
|
||||
data_mem_1_0[data_mem_1_0__T_156_addr] <= data_mem_1_0__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
data_mem_1_0__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_0__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_1_0__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_0__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if(data_mem_1_1__T_130_en & data_mem_1_1__T_130_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_130_addr] <= data_mem_1_1__T_130_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_1__T_135_en & data_mem_1_1__T_135_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_135_addr] <= data_mem_1_1__T_135_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_1__T_142_en & data_mem_1_1__T_142_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_142_addr] <= data_mem_1_1__T_142_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_1__T_149_en & data_mem_1_1__T_149_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_149_addr] <= data_mem_1_1__T_149_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
if(data_mem_1_1__T_156_en & data_mem_1_1__T_156_mask) begin
|
||||
data_mem_1_1[data_mem_1_1__T_156_addr] <= data_mem_1_1__T_156_data; // @[el2_ifu_ic_mem.scala 245:29]
|
||||
end
|
||||
data_mem_1_1__T_137_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_1__T_144_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
data_mem_1_1__T_151_addr_pipe_0 <= ic_rw_addr_bank_q_0[12:4];
|
||||
data_mem_1_1__T_158_addr_pipe_0 <= ic_rw_addr_bank_q_1[12:4];
|
||||
if (reset) begin
|
||||
ic_rw_addr_ff <= 13'h0;
|
||||
end else begin
|
||||
ic_rw_addr_ff <= ic_rw_addr_q;
|
||||
end
|
||||
if (reset) begin
|
||||
ic_debug_rd_way_en_ff <= 2'h0;
|
||||
end else begin
|
||||
ic_debug_rd_way_en_ff <= ic_debug_rd_way_en;
|
||||
end
|
||||
if (reset) begin
|
||||
ic_debug_rd_en_ff <= 1'h0;
|
||||
end else begin
|
||||
ic_debug_rd_en_ff <= io_ic_debug_rd_en;
|
||||
end
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
package ifu
|
||||
import lib._
|
||||
import chisel3._
|
||||
import chisel3.{util, _}
|
||||
import chisel3.util._
|
||||
|
||||
class el2_ifu_ic_mem extends Module with param{
|
||||
|
|
@ -174,18 +174,19 @@ class EL2_IC_TAG extends Module with el2_lib with param {
|
|||
}
|
||||
io.ictag_debug_rd_data := temp
|
||||
io.test := w_tout.reduce(_&_)
|
||||
io.ic_tag_perr := (ic_tag_way_perr.reduce(Cat(_,_)) & io.ic_tag_valid).orR
|
||||
io.ic_tag_perr := (ic_tag_way_perr.reverse.reduce(Cat(_,_)) & io.ic_tag_valid).orR
|
||||
val w_tout_Vec = VecInit.tabulate(ICACHE_NUM_WAYS)(i=> w_tout(i))
|
||||
io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reduce(Cat(_,_))
|
||||
io.ic_rd_hit := VecInit.tabulate(ICACHE_NUM_WAYS)(i=>(w_tout_Vec(i)(31,ICACHE_TAG_LO)===ic_rw_addr_ff(31,ICACHE_TAG_LO)).asUInt() & io.ic_tag_valid).reverse.reduce(Cat(_,_))
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////
|
||||
|
||||
class EL2_IC_DATA extends Module with param{
|
||||
class EL2_IC_DATA extends Module with el2_lib {
|
||||
val io = IO (new Bundle{
|
||||
val rst_l = Input(UInt(1.W))
|
||||
val clk_override = Input(UInt(1.W))
|
||||
val ic_rw_addr = Input(UInt(ICACHE_INDEX_HI.W))
|
||||
val ic_rw_addr = Input(UInt((ICACHE_INDEX_HI+1).W))
|
||||
val ic_wr_en = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_rd_en = Input(UInt(1.W))
|
||||
val ic_wr_data = Input(Vec(ICACHE_NUM_WAYS, UInt(71.W)))
|
||||
|
|
@ -194,31 +195,107 @@ class EL2_IC_DATA extends Module with param{
|
|||
val ic_debug_rd_data = Output(UInt(71.W))
|
||||
val ic_parerr = Output(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_eccerr = Output(UInt(ICACHE_BANKS_WAY.W))
|
||||
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+3).W))
|
||||
val ic_debug_addr = Input(UInt((ICACHE_INDEX_HI+1).W))
|
||||
val ic_debug_rd_en = Input(UInt(1.W))
|
||||
val ic_debug_wr_en = Input(UInt(1.W))
|
||||
val ic_debug_tag_array = Input(UInt(1.W))
|
||||
val ic_debug_way = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val ic_premux_data = Input(UInt(64.W))
|
||||
val ic_sel_premux_data = Input(UInt(1.W))
|
||||
val ic_sel_premux_data = Input(Bool())
|
||||
val ic_rd_hit = Input(UInt(ICACHE_NUM_WAYS.W))
|
||||
val scan_mode = Input(UInt(1.W))
|
||||
val mask = Input(Vec(2,Vec(2,Bool())))
|
||||
val test_port2 = Output(UInt())
|
||||
val test_port = Output(Vec(ICACHE_BANKS_WAY, Vec(ICACHE_NUM_WAYS, UInt(71.W))))
|
||||
})
|
||||
val ic_debug_rd_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_rd_en & ~io.ic_debug_tag_array) & io.ic_debug_way
|
||||
val ic_debug_wr_way_en = repl(ICACHE_NUM_WAYS, io.ic_debug_wr_en & ~io.ic_debug_tag_array) & io.ic_debug_way
|
||||
val ic_b_sb_wren = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>
|
||||
io.ic_wr_en|ic_debug_wr_way_en & repl(ICACHE_NUM_WAYS, io.ic_debug_addr(ICACHE_BANK_HI,ICACHE_BANK_LO)===i.U)).reverse
|
||||
val ic_sb_wr_data = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>
|
||||
Mux(((io.ic_debug_addr(ICACHE_BANK_HI,ICACHE_BANK_LO)===i.U) & io.ic_debug_wr_en).asBool, io.ic_debug_wr_data, io.ic_wr_data(i))).reverse
|
||||
val ic_rw_addr_q = Cat(Mux((io.ic_debug_rd_en | io.ic_debug_wr_en).asBool, Cat(io.ic_debug_addr(ICACHE_INDEX_HI,3),0.U(2.W)), io.ic_rw_addr(ICACHE_INDEX_HI,1)), 0.U(1.W))
|
||||
val ic_rd_en_with_debug = (io.ic_rd_en | io.ic_debug_rd_en ) & ~(io.ic_wr_en.orR)
|
||||
val ic_b_rden = (VecInit.tabulate(ICACHE_BANKS_WAY)(i=>
|
||||
Mux1H(Seq(~ic_rw_addr_q(ICACHE_BANK_HI).asBool -> (i.U === 0.U),
|
||||
(ic_rw_addr_q(ICACHE_BANK_HI)&(ic_rw_addr_q(2,1)===3.U)).asBool -> (i.U === 0.U),
|
||||
ic_rw_addr_q(ICACHE_BANK_HI).asBool -> (i.U === 1.U),
|
||||
(~ic_rw_addr_q(ICACHE_BANK_HI)&(ic_rw_addr_q(2,1)===3.U)).asBool -> (i.U === 1.U))))).reverse.map(_ & ic_rd_en_with_debug)
|
||||
//val ic_b_sb_rden = ic_b_rden.map(repl(ICACHE_NUM_WAYS, _))
|
||||
val ic_bank_way_clken = new Array[UInt](ICACHE_NUM_WAYS)
|
||||
ic_bank_way_clken(0) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(0))
|
||||
for(i<-1 until ICACHE_NUM_WAYS){
|
||||
ic_bank_way_clken(i) = (repl(ICACHE_NUM_WAYS,ic_b_rden(0)) | io.clk_override | ic_b_sb_wren(i)) | ic_bank_way_clken(i-1)
|
||||
}
|
||||
// TODO: AS it is being used at only one place replace
|
||||
val ic_rw_addr_q_inc = ic_rw_addr_q(ICACHE_TAG_LO-1,ICACHE_DATA_INDEX_LO) + 1.U
|
||||
val ic_rw_addr_wrap = ic_rw_addr_q(ICACHE_BANK_HI) & (ic_rw_addr_q(2,1)===3.U) & ic_rd_en_with_debug & ~(io.ic_wr_en.orR)
|
||||
// All flops rw-address
|
||||
// rd-enable as it is a sync mem
|
||||
val ic_rw_addr_ff = RegNext(ic_rw_addr_q, init = 0.U)
|
||||
val ic_b_rden_ff = RegNext(ic_b_rden.reverse.reduce(Cat(_,_)), init = 0.U)
|
||||
val ic_debug_rd_way_en_ff = RegNext(ic_debug_rd_way_en, init = 0.U)
|
||||
val ic_debug_rd_en_ff = RegNext(io.ic_debug_rd_en, init = 0.U)
|
||||
val ic_cacheline_wrap_ff = ic_rw_addr_ff(ICACHE_TAG_INDEX_LO-1,ICACHE_BANK_LO) === repl(ICACHE_TAG_INDEX_LO - ICACHE_BANK_LO, 1.U)
|
||||
|
||||
val ic_rw_addr_bank_q = Wire(Vec(ICACHE_BANKS_WAY,UInt((ICACHE_INDEX_HI+1).W)))
|
||||
ic_rw_addr_bank_q(0) := Mux(~ic_rw_addr_wrap.asBool, ic_rw_addr_q(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO), Cat(ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_TAG_INDEX_LO), ic_rw_addr_q_inc(ICACHE_TAG_INDEX_LO-1, ICACHE_DATA_INDEX_LO)))
|
||||
ic_rw_addr_bank_q(1) := ic_rw_addr_q(ICACHE_INDEX_HI, ICACHE_DATA_INDEX_LO)
|
||||
val (data_mem_word, tag_mem_word, ecc_offset) = DATA_MEM_LINE
|
||||
// Making a memory with Location=ICACHE_DATA_DEPTH banks and ways
|
||||
val data_mem = SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_BANKS_WAY,Vec(ICACHE_NUM_WAYS, UInt(data_mem_word.W))))
|
||||
data_mem(ic_rw_addr_bank_q(0)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(0)(0):= ic_sb_wr_data(0)
|
||||
val wb_dout = Wire(Vec(ICACHE_NUM_WAYS, Vec(ICACHE_BANKS_WAY, UInt(data_mem_word.W))))
|
||||
// Initializing the wire
|
||||
wb_dout.indices.foreach { i => wb_dout(i).indices.foreach{ j=>
|
||||
wb_dout(i)(j) := 0.U
|
||||
when(ic_sb_wr_data(i)(j) & ic_bank_way_clken(i)(j)){
|
||||
data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(j)(i) := ic_sb_wr_data(j)
|
||||
}
|
||||
wb_dout(i)(j) := data_mem(ic_rw_addr_bank_q(j)(ICACHE_INDEX_HI,ICACHE_DATA_INDEX_LO))(i)(j)
|
||||
}
|
||||
}
|
||||
val wb_dout_way_pre_lower = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
(0 until ICACHE_BANKS_WAY).map(j=>
|
||||
repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U)&wb_dout(i)(j)).reduce(_|_))
|
||||
|
||||
val wb_dout_way_pre_upper = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
(0 until ICACHE_BANKS_WAY).map(j=>
|
||||
repl(data_mem_word,ic_rw_addr_ff(ICACHE_BANK_HI, ICACHE_BANK_LO)===j.U-1.U)&wb_dout(i)(j)).reduce(_|_))
|
||||
|
||||
val wb_dout_way_pre = (0 until ICACHE_NUM_WAYS).map(i=>Cat(wb_dout_way_pre_upper(i),wb_dout_way_pre_lower(i)))
|
||||
|
||||
// TODO: Put an assertion here
|
||||
val wb_dout_way = (0 until ICACHE_NUM_WAYS).map(i=>
|
||||
repl(64 ,ic_rw_addr_ff(2,1)===0.U) & wb_dout_way_pre(i)(63,0) |
|
||||
repl(64 ,ic_rw_addr_ff(2,1)===1.U) & Cat(wb_dout_way_pre(i)(ecc_offset+15,ecc_offset),wb_dout_way_pre(i)(63,16)) |
|
||||
repl(64 ,ic_rw_addr_ff(2,1)===2.U) & Cat(wb_dout_way_pre(i)(ecc_offset+31,ecc_offset),wb_dout_way_pre(i)(63,32)) |
|
||||
repl(64 ,ic_rw_addr_ff(2,1)===3.U) & Cat(wb_dout_way_pre(i)(ecc_offset+47,ecc_offset),wb_dout_way_pre(i)(63,48))
|
||||
)
|
||||
// ic_rw_addr_ff(ICACHE_BANK_HI,ICACHE_BANK_LO)===1.U -> wb_dout(1)(0)))
|
||||
val ic_rd_hit_q = Mux(ic_debug_rd_en_ff===1.U, ic_debug_rd_way_en_ff, io.ic_rd_hit) ;
|
||||
val wb_dout_way_with_premux = wb_dout_way.map(Mux(io.ic_sel_premux_data, io.ic_premux_data, _))
|
||||
|
||||
// val data_memory = VecInit.tabulate(ICACHE_BANKS_WAY)(i => SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
|
||||
// SyncReadMem(ICACHE_TAG_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(22.W)))
|
||||
val mask = VecInit.tabulate(ICACHE_NUM_WAYS)(i=>1.U)
|
||||
val data_mem = (SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))), SyncReadMem(ICACHE_DATA_DEPTH, Vec(ICACHE_NUM_WAYS, UInt(26.W))))
|
||||
data_mem(0).write(io.ic_rw_addr,io.ic_wr_data,mask)
|
||||
// ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask)
|
||||
io.ic_debug_rd_data := 0.U
|
||||
io.ic_rd_data := 0.U
|
||||
io.ic_eccerr := 0.U
|
||||
io.ic_parerr := 0.U
|
||||
io.ic_eccerr := 0.U
|
||||
|
||||
io.ic_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i) | io.ic_sel_premux_data),
|
||||
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_with_premux(_)))
|
||||
io.ic_debug_rd_data := Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
|
||||
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)(data_mem_word-1,0)))
|
||||
val wb_dout_ecc = Mux1H_LM((0 until ICACHE_NUM_WAYS).map(i => ic_rd_hit_q(i)),
|
||||
(0 until ICACHE_NUM_WAYS).map(wb_dout_way_pre(_)))
|
||||
io.test_port2 := 0.U//inter2//wb_dout_way_pre
|
||||
io.test_port := wb_dout
|
||||
|
||||
//data_mem(ic_rw_addr_bank_q)(ICACHE_BANK_HI,ICACHE_BANK_LO)(ic_debug_rd_way_en)
|
||||
//ic_memory.write(io.ic_rw_addr, io.ic_wr_data, io.mask)
|
||||
//io.ic_debug_rd_data := 0.U
|
||||
//io.ic_rd_data := 0.U
|
||||
//io.ic_eccerr := 0.U
|
||||
//io.ic_parerr := 0.U
|
||||
//val (a,b) = DATA_MEM_LINE
|
||||
//println(s"${DATA_MEM_LINE._2}")
|
||||
}
|
||||
|
||||
object ifu_ic extends App {
|
||||
|
|
|
|||
|
|
@ -156,6 +156,17 @@ trait param {
|
|||
val SB_BUS_TAG = 0x1 //.U(4.W)
|
||||
val TIMER_LEGAL_EN = 0x1 //.U(1.W)
|
||||
|
||||
// Configuration Methods
|
||||
def MEM_CAL : (Int, Int, Int)=
|
||||
(ICACHE_WAYPACK, ICACHE_ECC) match{
|
||||
case(false,false) => (68,22, 68)
|
||||
case(false,true) => (71,26, 71)
|
||||
case(true,false) => (68*ICACHE_NUM_WAYS,22*ICACHE_NUM_WAYS, 68)
|
||||
case(true,true) => (71*ICACHE_NUM_WAYS,26*ICACHE_NUM_WAYS, 71)
|
||||
}
|
||||
|
||||
val DATA_MEM_LINE = MEM_CAL
|
||||
|
||||
}
|
||||
|
||||
trait el2_lib extends param{
|
||||
|
|
@ -173,8 +184,9 @@ trait el2_lib extends param{
|
|||
if(BHT_GHR_HASH_1) Cat(ghr(BHT_GHR_SIZE-1,BTB_INDEX1_HI-1), hashin(BTB_INDEX1_HI,2) ^ ghr(BTB_INDEX1_HI-2,0))
|
||||
else hashin(BHT_GHR_SIZE+1,2) ^ ghr(BHT_GHR_SIZE-1,0)
|
||||
|
||||
def repl(b:Int, a:UInt) : UInt =
|
||||
VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
|
||||
def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
|
||||
|
||||
def Mux1H_LM(a:Seq[Bool], b:Seq[UInt]) = (0 until b.size).map(i=> repl(b(i).getWidth,a(i)) & b(i)).reduce(_|_)
|
||||
|
||||
def rveven_paritycheck(data_in:UInt, parity_in:UInt) : UInt =
|
||||
(data_in.xorR.asUInt) ^ parity_in
|
||||
|
|
@ -182,15 +194,6 @@ trait el2_lib extends param{
|
|||
def rveven_paritygen(data_in : UInt) =
|
||||
data_in.xorR.asUInt
|
||||
|
||||
def memory_cal =
|
||||
(ICACHE_WAYPACK, ICACHE_ECC) match{
|
||||
case(false,false) => 68
|
||||
case(false,true) => 71
|
||||
case(true,false) => 68*ICACHE_NUM_WAYS
|
||||
case(true,true) => 71*ICACHE_NUM_WAYS
|
||||
}
|
||||
|
||||
val data_mem_size : Int = memory_cal
|
||||
// Move rvecc_encode to a proper trait
|
||||
def rvecc_encode(din:UInt) = { //Done for verification and testing
|
||||
val mask0 = Array(0,1,0,1,0,1,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,1,0,1,0,1,0,1,1,0,1,1)
|
||||
|
|
|
|||
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Reference in New Issue