QUASAR added
This commit is contained in:
Laraib Khan
parent
95a4cc20df
commit
2f42344e29
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@ -1,53 +0,0 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_ifu_pmu_instr_aligned",
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"sources":[
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"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_bits_br_error",
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"sources":[
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"~ifu_aln_ctl|ifu_aln_ctl>io_dec_aln_aln_ib_i0_brp_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume1",
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"sources":[
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"~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
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"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_aln_ctl|ifu_aln_ctl>io_ifu_fb_consume2",
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"sources":[
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"~ifu_aln_ctl|ifu_aln_ctl>io_exu_flush_final",
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"~ifu_aln_ctl|ifu_aln_ctl>io_dec_i0_decode_d"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"ifu_aln_ctl.gated_latch",
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"resourceId":"/vsrc/gated_latch.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"ifu_aln_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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3502
ifu_aln_ctl.fir
3502
ifu_aln_ctl.fir
File diff suppressed because it is too large
Load Diff
1405
ifu_aln_ctl.v
1405
ifu_aln_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -1,165 +0,0 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_inst_mask_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist0_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_btb_target_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_pc4_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_valid_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_ret_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_way_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_index",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_btag",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_mp_pkt_bits_misp",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_poffset_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hit_taken_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_bpred_disable",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~ifu_bp_ctl|ifu_bp_ctl>io_ifu_bp_hist1_f",
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"sources":[
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_addr_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_ifc_fetch_req_f",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_flush_leak_one_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_tlu_flush_lower_wb",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_way",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_start_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_dec_bp_dec_tlu_br0_r_pkt_bits_br_error",
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"~ifu_bp_ctl|ifu_bp_ctl>io_exu_bp_exu_i0_br_index_r"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"ifu_bp_ctl.gated_latch",
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"resourceId":"/vsrc/gated_latch.sv"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"ifu_bp_ctl"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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46597
ifu_bp_ctl.fir
46597
ifu_bp_ctl.fir
File diff suppressed because it is too large
Load Diff
28590
ifu_bp_ctl.v
28590
ifu_bp_ctl.v
File diff suppressed because it is too large
Load Diff
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@ -1,183 +0,0 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
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]
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||||
},
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||||
{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
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]
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||||
},
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||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
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||||
"sources":[
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
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||||
]
|
||||
},
|
||||
{
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||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
|
||||
"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
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||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_nonblock_load_data",
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||||
"sources":[
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
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]
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||||
},
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||||
{
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"class":"firrtl.transforms.CombinationalPath",
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||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
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||||
"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
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]
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||||
},
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||||
{
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"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
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||||
"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
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"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
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]
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||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
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||||
"sources":[
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
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||||
"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dec_tlu_force_halt"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
|
||||
"sources":[
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
|
||||
"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu_bus_buffer.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu_bus_buffer"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
6552
lsu_bus_buffer.fir
6552
lsu_bus_buffer.fir
File diff suppressed because it is too large
Load Diff
4633
lsu_bus_buffer.v
4633
lsu_bus_buffer.v
File diff suppressed because it is too large
Load Diff
|
|
@ -1,113 +0,0 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_misaligned",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_bus_read_data_m",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_store_data_r",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_valid_m",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_load",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_flush_m_up",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_valid",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_is_sideeffects_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_dec_tlu_force_halt",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_bits_store",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_pkt_r_valid",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_addr_r",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_end_addr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_busy",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_tag_m",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_lsu_bus_buffer_full_any",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_d",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_busreq_m",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_ldst_dual_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_dctl_busbuff_lsu_nonblock_load_inv_r",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_lsu_commit_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_bus_intf|lsu_bus_intf>io_tlu_busbuff_lsu_pmu_bus_trxn",
|
||||
"sources":[
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_ar_ready",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_aw_ready",
|
||||
"~lsu_bus_intf|lsu_bus_intf>io_axi_w_ready"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu_bus_intf.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu_bus_intf"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
7199
lsu_bus_intf.fir
7199
lsu_bus_intf.fir
File diff suppressed because it is too large
Load Diff
5251
lsu_bus_intf.v
5251
lsu_bus_intf.v
File diff suppressed because it is too large
Load Diff
|
|
@ -1,333 +0,0 @@
|
|||
[
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_fast_int",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_r",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_fir_addr",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_ldst_dual_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_m"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_store_data_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_picm_mask_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_store_data_bypass_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_addr_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dma",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dma",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_stack",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_stack",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_valid",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_dccm_req",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_valid",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_m_up",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_fast_int"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_unsign",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_unsign",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_pic_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_end_addr_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_write"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_incr",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_valid",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_single_ecc_error_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_commit_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_dma",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_double_ecc_error_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_flush_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_store",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_load"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_by",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_store_data_bypass_m",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_store_data_bypass_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_in_dccm_d",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_lsu_result_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_exu_exu_lsu_rs1_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_addr",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_valid_raw_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_load_ldst_bypass_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dec_lsu_offset_d",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_addr_external_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_bus_read_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_m",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_m_bits_unsign",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_d_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_dword",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_p_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_dma_lsc_ctl_dma_mem_sz"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.CombinationalPath",
|
||||
"sink":"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_result_corr_r",
|
||||
"sources":[
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_word",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_ld_data_corr_r",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_half",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_by",
|
||||
"~lsu_lsc_ctl|lsu_lsc_ctl>io_lsu_pkt_r_bits_unsign"
|
||||
]
|
||||
},
|
||||
{
|
||||
"class":"firrtl.EmitCircuitAnnotation",
|
||||
"emitter":"firrtl.VerilogEmitter"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxResourceAnno",
|
||||
"target":"lsu_lsc_ctl.gated_latch",
|
||||
"resourceId":"/vsrc/gated_latch.sv"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.TargetDirAnnotation",
|
||||
"directory":"."
|
||||
},
|
||||
{
|
||||
"class":"firrtl.options.OutputAnnotationFileAnnotation",
|
||||
"file":"lsu_lsc_ctl"
|
||||
},
|
||||
{
|
||||
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
|
||||
"targetDir":"."
|
||||
}
|
||||
]
|
||||
977
lsu_lsc_ctl.fir
977
lsu_lsc_ctl.fir
|
|
@ -1,977 +0,0 @@
|
|||
;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10
|
||||
circuit lsu_lsc_ctl :
|
||||
module lsu_addrcheck :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip lsu_c2_m_clk : Clock, flip start_addr_d : UInt<32>, flip end_addr_d : UInt<32>, flip lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_tlu_mrac_ff : UInt<32>, flip rs1_region_d : UInt<4>, flip rs1_d : UInt<32>, is_sideeffects_m : UInt<1>, addr_in_dccm_d : UInt<1>, addr_in_pic_d : UInt<1>, addr_external_d : UInt<1>, access_fault_d : UInt<1>, misaligned_fault_d : UInt<1>, exc_mscause_d : UInt<4>, fir_dccm_access_error_d : UInt<1>, fir_nondccm_access_error_d : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
node _T = bits(io.start_addr_d, 31, 28) @[lib.scala 370:27]
|
||||
node start_addr_in_dccm_region_d = eq(_T, UInt<4>("h0f")) @[lib.scala 370:49]
|
||||
wire start_addr_in_dccm_d : UInt<1> @[lib.scala 371:26]
|
||||
node _T_1 = bits(io.start_addr_d, 31, 16) @[lib.scala 375:24]
|
||||
node _T_2 = eq(_T_1, UInt<16>("h0f004")) @[lib.scala 375:39]
|
||||
start_addr_in_dccm_d <= _T_2 @[lib.scala 375:16]
|
||||
node _T_3 = bits(io.end_addr_d, 31, 28) @[lib.scala 370:27]
|
||||
node end_addr_in_dccm_region_d = eq(_T_3, UInt<4>("h0f")) @[lib.scala 370:49]
|
||||
wire end_addr_in_dccm_d : UInt<1> @[lib.scala 371:26]
|
||||
node _T_4 = bits(io.end_addr_d, 31, 16) @[lib.scala 375:24]
|
||||
node _T_5 = eq(_T_4, UInt<16>("h0f004")) @[lib.scala 375:39]
|
||||
end_addr_in_dccm_d <= _T_5 @[lib.scala 375:16]
|
||||
wire addr_in_iccm : UInt<1>
|
||||
addr_in_iccm <= UInt<1>("h00")
|
||||
node _T_6 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 42:37]
|
||||
node _T_7 = eq(_T_6, UInt<4>("h0e")) @[lsu_addrcheck.scala 42:45]
|
||||
addr_in_iccm <= _T_7 @[lsu_addrcheck.scala 42:18]
|
||||
node _T_8 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 50:89]
|
||||
node _T_9 = bits(_T_8, 31, 28) @[lib.scala 370:27]
|
||||
node start_addr_in_pic_region_d = eq(_T_9, UInt<4>("h0f")) @[lib.scala 370:49]
|
||||
wire start_addr_in_pic_d : UInt<1> @[lib.scala 371:26]
|
||||
node _T_10 = bits(_T_8, 31, 15) @[lib.scala 375:24]
|
||||
node _T_11 = eq(_T_10, UInt<17>("h01e018")) @[lib.scala 375:39]
|
||||
start_addr_in_pic_d <= _T_11 @[lib.scala 375:16]
|
||||
node _T_12 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 52:83]
|
||||
node _T_13 = bits(_T_12, 31, 28) @[lib.scala 370:27]
|
||||
node end_addr_in_pic_region_d = eq(_T_13, UInt<4>("h0f")) @[lib.scala 370:49]
|
||||
wire end_addr_in_pic_d : UInt<1> @[lib.scala 371:26]
|
||||
node _T_14 = bits(_T_12, 31, 15) @[lib.scala 375:24]
|
||||
node _T_15 = eq(_T_14, UInt<17>("h01e018")) @[lib.scala 375:39]
|
||||
end_addr_in_pic_d <= _T_15 @[lib.scala 375:16]
|
||||
node start_addr_dccm_or_pic = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 54:60]
|
||||
node _T_16 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:49]
|
||||
node _T_17 = eq(_T_16, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:55]
|
||||
node _T_18 = and(_T_17, UInt<1>("h01")) @[lsu_addrcheck.scala 55:74]
|
||||
node _T_19 = bits(io.rs1_region_d, 3, 0) @[lsu_addrcheck.scala 55:109]
|
||||
node _T_20 = eq(_T_19, UInt<4>("h0f")) @[lsu_addrcheck.scala 55:115]
|
||||
node base_reg_dccm_or_pic = or(_T_18, _T_20) @[lsu_addrcheck.scala 55:91]
|
||||
node _T_21 = and(start_addr_in_dccm_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 56:57]
|
||||
io.addr_in_dccm_d <= _T_21 @[lsu_addrcheck.scala 56:32]
|
||||
node _T_22 = and(start_addr_in_pic_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 57:56]
|
||||
io.addr_in_pic_d <= _T_22 @[lsu_addrcheck.scala 57:32]
|
||||
node _T_23 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 59:63]
|
||||
node _T_24 = not(_T_23) @[lsu_addrcheck.scala 59:33]
|
||||
io.addr_external_d <= _T_24 @[lsu_addrcheck.scala 59:30]
|
||||
node _T_25 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 60:51]
|
||||
node csr_idx = cat(_T_25, UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_26 = dshr(io.dec_tlu_mrac_ff, csr_idx) @[lsu_addrcheck.scala 61:50]
|
||||
node _T_27 = bits(_T_26, 0, 0) @[lsu_addrcheck.scala 61:50]
|
||||
node _T_28 = or(start_addr_in_dccm_region_d, start_addr_in_pic_region_d) @[lsu_addrcheck.scala 61:92]
|
||||
node _T_29 = or(_T_28, addr_in_iccm) @[lsu_addrcheck.scala 61:121]
|
||||
node _T_30 = eq(_T_29, UInt<1>("h00")) @[lsu_addrcheck.scala 61:62]
|
||||
node _T_31 = and(_T_27, _T_30) @[lsu_addrcheck.scala 61:60]
|
||||
node _T_32 = and(_T_31, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 61:137]
|
||||
node _T_33 = or(io.lsu_pkt_d.bits.store, io.lsu_pkt_d.bits.load) @[lsu_addrcheck.scala 61:185]
|
||||
node is_sideeffects_d = and(_T_32, _T_33) @[lsu_addrcheck.scala 61:158]
|
||||
node _T_34 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 62:74]
|
||||
node _T_35 = eq(_T_34, UInt<1>("h00")) @[lsu_addrcheck.scala 62:80]
|
||||
node _T_36 = and(io.lsu_pkt_d.bits.word, _T_35) @[lsu_addrcheck.scala 62:56]
|
||||
node _T_37 = bits(io.start_addr_d, 0, 0) @[lsu_addrcheck.scala 62:134]
|
||||
node _T_38 = eq(_T_37, UInt<1>("h00")) @[lsu_addrcheck.scala 62:138]
|
||||
node _T_39 = and(io.lsu_pkt_d.bits.half, _T_38) @[lsu_addrcheck.scala 62:116]
|
||||
node _T_40 = or(_T_36, _T_39) @[lsu_addrcheck.scala 62:90]
|
||||
node is_aligned_d = or(_T_40, io.lsu_pkt_d.bits.by) @[lsu_addrcheck.scala 62:148]
|
||||
node _T_41 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_42 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58]
|
||||
node _T_43 = cat(_T_42, _T_41) @[Cat.scala 29:58]
|
||||
node _T_44 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_45 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58]
|
||||
node _T_46 = cat(_T_45, _T_44) @[Cat.scala 29:58]
|
||||
node _T_47 = cat(_T_46, _T_43) @[Cat.scala 29:58]
|
||||
node _T_48 = orr(_T_47) @[lsu_addrcheck.scala 66:99]
|
||||
node _T_49 = eq(_T_48, UInt<1>("h00")) @[lsu_addrcheck.scala 65:33]
|
||||
node _T_50 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 67:49]
|
||||
node _T_51 = or(_T_50, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:56]
|
||||
node _T_52 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 67:121]
|
||||
node _T_53 = eq(_T_51, _T_52) @[lsu_addrcheck.scala 67:88]
|
||||
node _T_54 = and(UInt<1>("h01"), _T_53) @[lsu_addrcheck.scala 67:30]
|
||||
node _T_55 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 68:49]
|
||||
node _T_56 = or(_T_55, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:56]
|
||||
node _T_57 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 68:121]
|
||||
node _T_58 = eq(_T_56, _T_57) @[lsu_addrcheck.scala 68:88]
|
||||
node _T_59 = and(UInt<1>("h01"), _T_58) @[lsu_addrcheck.scala 68:30]
|
||||
node _T_60 = or(_T_54, _T_59) @[lsu_addrcheck.scala 67:153]
|
||||
node _T_61 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 69:49]
|
||||
node _T_62 = or(_T_61, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:56]
|
||||
node _T_63 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 69:121]
|
||||
node _T_64 = eq(_T_62, _T_63) @[lsu_addrcheck.scala 69:88]
|
||||
node _T_65 = and(UInt<1>("h01"), _T_64) @[lsu_addrcheck.scala 69:30]
|
||||
node _T_66 = or(_T_60, _T_65) @[lsu_addrcheck.scala 68:153]
|
||||
node _T_67 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 70:49]
|
||||
node _T_68 = or(_T_67, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:56]
|
||||
node _T_69 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 70:121]
|
||||
node _T_70 = eq(_T_68, _T_69) @[lsu_addrcheck.scala 70:88]
|
||||
node _T_71 = and(UInt<1>("h01"), _T_70) @[lsu_addrcheck.scala 70:30]
|
||||
node _T_72 = or(_T_66, _T_71) @[lsu_addrcheck.scala 69:153]
|
||||
node _T_73 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 71:49]
|
||||
node _T_74 = or(_T_73, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:56]
|
||||
node _T_75 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 71:121]
|
||||
node _T_76 = eq(_T_74, _T_75) @[lsu_addrcheck.scala 71:88]
|
||||
node _T_77 = and(UInt<1>("h00"), _T_76) @[lsu_addrcheck.scala 71:30]
|
||||
node _T_78 = or(_T_72, _T_77) @[lsu_addrcheck.scala 70:153]
|
||||
node _T_79 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 72:49]
|
||||
node _T_80 = or(_T_79, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:56]
|
||||
node _T_81 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 72:121]
|
||||
node _T_82 = eq(_T_80, _T_81) @[lsu_addrcheck.scala 72:88]
|
||||
node _T_83 = and(UInt<1>("h00"), _T_82) @[lsu_addrcheck.scala 72:30]
|
||||
node _T_84 = or(_T_78, _T_83) @[lsu_addrcheck.scala 71:153]
|
||||
node _T_85 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 73:49]
|
||||
node _T_86 = or(_T_85, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:56]
|
||||
node _T_87 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 73:121]
|
||||
node _T_88 = eq(_T_86, _T_87) @[lsu_addrcheck.scala 73:88]
|
||||
node _T_89 = and(UInt<1>("h00"), _T_88) @[lsu_addrcheck.scala 73:30]
|
||||
node _T_90 = or(_T_84, _T_89) @[lsu_addrcheck.scala 72:153]
|
||||
node _T_91 = bits(io.start_addr_d, 31, 0) @[lsu_addrcheck.scala 74:49]
|
||||
node _T_92 = or(_T_91, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:56]
|
||||
node _T_93 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 74:121]
|
||||
node _T_94 = eq(_T_92, _T_93) @[lsu_addrcheck.scala 74:88]
|
||||
node _T_95 = and(UInt<1>("h00"), _T_94) @[lsu_addrcheck.scala 74:30]
|
||||
node _T_96 = or(_T_90, _T_95) @[lsu_addrcheck.scala 73:153]
|
||||
node _T_97 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 76:48]
|
||||
node _T_98 = or(_T_97, UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:57]
|
||||
node _T_99 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[lsu_addrcheck.scala 76:122]
|
||||
node _T_100 = eq(_T_98, _T_99) @[lsu_addrcheck.scala 76:89]
|
||||
node _T_101 = and(UInt<1>("h01"), _T_100) @[lsu_addrcheck.scala 76:31]
|
||||
node _T_102 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 77:49]
|
||||
node _T_103 = or(_T_102, UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:58]
|
||||
node _T_104 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[lsu_addrcheck.scala 77:123]
|
||||
node _T_105 = eq(_T_103, _T_104) @[lsu_addrcheck.scala 77:90]
|
||||
node _T_106 = and(UInt<1>("h01"), _T_105) @[lsu_addrcheck.scala 77:32]
|
||||
node _T_107 = or(_T_101, _T_106) @[lsu_addrcheck.scala 76:154]
|
||||
node _T_108 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 78:49]
|
||||
node _T_109 = or(_T_108, UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:58]
|
||||
node _T_110 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[lsu_addrcheck.scala 78:123]
|
||||
node _T_111 = eq(_T_109, _T_110) @[lsu_addrcheck.scala 78:90]
|
||||
node _T_112 = and(UInt<1>("h01"), _T_111) @[lsu_addrcheck.scala 78:32]
|
||||
node _T_113 = or(_T_107, _T_112) @[lsu_addrcheck.scala 77:155]
|
||||
node _T_114 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 79:49]
|
||||
node _T_115 = or(_T_114, UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:58]
|
||||
node _T_116 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[lsu_addrcheck.scala 79:123]
|
||||
node _T_117 = eq(_T_115, _T_116) @[lsu_addrcheck.scala 79:90]
|
||||
node _T_118 = and(UInt<1>("h01"), _T_117) @[lsu_addrcheck.scala 79:32]
|
||||
node _T_119 = or(_T_113, _T_118) @[lsu_addrcheck.scala 78:155]
|
||||
node _T_120 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 80:49]
|
||||
node _T_121 = or(_T_120, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:58]
|
||||
node _T_122 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 80:123]
|
||||
node _T_123 = eq(_T_121, _T_122) @[lsu_addrcheck.scala 80:90]
|
||||
node _T_124 = and(UInt<1>("h00"), _T_123) @[lsu_addrcheck.scala 80:32]
|
||||
node _T_125 = or(_T_119, _T_124) @[lsu_addrcheck.scala 79:155]
|
||||
node _T_126 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 81:49]
|
||||
node _T_127 = or(_T_126, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:58]
|
||||
node _T_128 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 81:123]
|
||||
node _T_129 = eq(_T_127, _T_128) @[lsu_addrcheck.scala 81:90]
|
||||
node _T_130 = and(UInt<1>("h00"), _T_129) @[lsu_addrcheck.scala 81:32]
|
||||
node _T_131 = or(_T_125, _T_130) @[lsu_addrcheck.scala 80:155]
|
||||
node _T_132 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 82:49]
|
||||
node _T_133 = or(_T_132, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:58]
|
||||
node _T_134 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 82:123]
|
||||
node _T_135 = eq(_T_133, _T_134) @[lsu_addrcheck.scala 82:90]
|
||||
node _T_136 = and(UInt<1>("h00"), _T_135) @[lsu_addrcheck.scala 82:32]
|
||||
node _T_137 = or(_T_131, _T_136) @[lsu_addrcheck.scala 81:155]
|
||||
node _T_138 = bits(io.end_addr_d, 31, 0) @[lsu_addrcheck.scala 83:49]
|
||||
node _T_139 = or(_T_138, UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:58]
|
||||
node _T_140 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[lsu_addrcheck.scala 83:123]
|
||||
node _T_141 = eq(_T_139, _T_140) @[lsu_addrcheck.scala 83:90]
|
||||
node _T_142 = and(UInt<1>("h00"), _T_141) @[lsu_addrcheck.scala 83:32]
|
||||
node _T_143 = or(_T_137, _T_142) @[lsu_addrcheck.scala 82:155]
|
||||
node _T_144 = and(_T_96, _T_143) @[lsu_addrcheck.scala 75:7]
|
||||
node non_dccm_access_ok = or(_T_49, _T_144) @[lsu_addrcheck.scala 66:104]
|
||||
node regpred_access_fault_d = xor(start_addr_dccm_or_pic, base_reg_dccm_or_pic) @[lsu_addrcheck.scala 85:57]
|
||||
node _T_145 = bits(io.start_addr_d, 1, 0) @[lsu_addrcheck.scala 86:70]
|
||||
node _T_146 = neq(_T_145, UInt<2>("h00")) @[lsu_addrcheck.scala 86:76]
|
||||
node _T_147 = eq(io.lsu_pkt_d.bits.word, UInt<1>("h00")) @[lsu_addrcheck.scala 86:92]
|
||||
node _T_148 = or(_T_146, _T_147) @[lsu_addrcheck.scala 86:90]
|
||||
node picm_access_fault_d = and(io.addr_in_pic_d, _T_148) @[lsu_addrcheck.scala 86:51]
|
||||
wire unmapped_access_fault_d : UInt<1>
|
||||
unmapped_access_fault_d <= UInt<1>("h01")
|
||||
wire mpu_access_fault_d : UInt<1>
|
||||
mpu_access_fault_d <= UInt<1>("h01")
|
||||
node _T_149 = or(start_addr_in_dccm_d, start_addr_in_pic_d) @[lsu_addrcheck.scala 91:87]
|
||||
node _T_150 = eq(_T_149, UInt<1>("h00")) @[lsu_addrcheck.scala 91:64]
|
||||
node _T_151 = and(start_addr_in_dccm_region_d, _T_150) @[lsu_addrcheck.scala 91:62]
|
||||
node _T_152 = or(end_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 93:57]
|
||||
node _T_153 = eq(_T_152, UInt<1>("h00")) @[lsu_addrcheck.scala 93:36]
|
||||
node _T_154 = and(end_addr_in_dccm_region_d, _T_153) @[lsu_addrcheck.scala 93:34]
|
||||
node _T_155 = or(_T_151, _T_154) @[lsu_addrcheck.scala 91:112]
|
||||
node _T_156 = and(start_addr_in_dccm_d, end_addr_in_pic_d) @[lsu_addrcheck.scala 95:29]
|
||||
node _T_157 = or(_T_155, _T_156) @[lsu_addrcheck.scala 93:85]
|
||||
node _T_158 = and(start_addr_in_pic_d, end_addr_in_dccm_d) @[lsu_addrcheck.scala 97:29]
|
||||
node _T_159 = or(_T_157, _T_158) @[lsu_addrcheck.scala 95:85]
|
||||
unmapped_access_fault_d <= _T_159 @[lsu_addrcheck.scala 91:29]
|
||||
node _T_160 = eq(start_addr_in_dccm_region_d, UInt<1>("h00")) @[lsu_addrcheck.scala 99:33]
|
||||
node _T_161 = eq(non_dccm_access_ok, UInt<1>("h00")) @[lsu_addrcheck.scala 99:64]
|
||||
node _T_162 = and(_T_160, _T_161) @[lsu_addrcheck.scala 99:62]
|
||||
mpu_access_fault_d <= _T_162 @[lsu_addrcheck.scala 99:29]
|
||||
node _T_163 = or(unmapped_access_fault_d, mpu_access_fault_d) @[lsu_addrcheck.scala 111:49]
|
||||
node _T_164 = or(_T_163, picm_access_fault_d) @[lsu_addrcheck.scala 111:70]
|
||||
node _T_165 = or(_T_164, regpred_access_fault_d) @[lsu_addrcheck.scala 111:92]
|
||||
node _T_166 = and(_T_165, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 111:118]
|
||||
node _T_167 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 111:141]
|
||||
node _T_168 = and(_T_166, _T_167) @[lsu_addrcheck.scala 111:139]
|
||||
io.access_fault_d <= _T_168 @[lsu_addrcheck.scala 111:21]
|
||||
node _T_169 = bits(unmapped_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:60]
|
||||
node _T_170 = bits(mpu_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:100]
|
||||
node _T_171 = bits(regpred_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:144]
|
||||
node _T_172 = bits(picm_access_fault_d, 0, 0) @[lsu_addrcheck.scala 112:185]
|
||||
node _T_173 = mux(_T_172, UInt<4>("h06"), UInt<4>("h00")) @[lsu_addrcheck.scala 112:164]
|
||||
node _T_174 = mux(_T_171, UInt<4>("h05"), _T_173) @[lsu_addrcheck.scala 112:120]
|
||||
node _T_175 = mux(_T_170, UInt<4>("h03"), _T_174) @[lsu_addrcheck.scala 112:80]
|
||||
node access_fault_mscause_d = mux(_T_169, UInt<4>("h02"), _T_175) @[lsu_addrcheck.scala 112:35]
|
||||
node _T_176 = bits(io.start_addr_d, 31, 28) @[lsu_addrcheck.scala 113:53]
|
||||
node _T_177 = bits(io.end_addr_d, 31, 28) @[lsu_addrcheck.scala 113:78]
|
||||
node regcross_misaligned_fault_d = neq(_T_176, _T_177) @[lsu_addrcheck.scala 113:61]
|
||||
node _T_178 = eq(is_aligned_d, UInt<1>("h00")) @[lsu_addrcheck.scala 114:59]
|
||||
node sideeffect_misaligned_fault_d = and(is_sideeffects_d, _T_178) @[lsu_addrcheck.scala 114:57]
|
||||
node _T_179 = and(sideeffect_misaligned_fault_d, io.addr_external_d) @[lsu_addrcheck.scala 115:90]
|
||||
node _T_180 = or(regcross_misaligned_fault_d, _T_179) @[lsu_addrcheck.scala 115:57]
|
||||
node _T_181 = and(_T_180, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 115:113]
|
||||
node _T_182 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_addrcheck.scala 115:136]
|
||||
node _T_183 = and(_T_181, _T_182) @[lsu_addrcheck.scala 115:134]
|
||||
io.misaligned_fault_d <= _T_183 @[lsu_addrcheck.scala 115:25]
|
||||
node _T_184 = bits(sideeffect_misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 116:111]
|
||||
node _T_185 = mux(_T_184, UInt<4>("h01"), UInt<4>("h00")) @[lsu_addrcheck.scala 116:80]
|
||||
node misaligned_fault_mscause_d = mux(regcross_misaligned_fault_d, UInt<4>("h02"), _T_185) @[lsu_addrcheck.scala 116:39]
|
||||
node _T_186 = bits(io.misaligned_fault_d, 0, 0) @[lsu_addrcheck.scala 117:50]
|
||||
node _T_187 = bits(misaligned_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:84]
|
||||
node _T_188 = bits(access_fault_mscause_d, 3, 0) @[lsu_addrcheck.scala 117:113]
|
||||
node _T_189 = mux(_T_186, _T_187, _T_188) @[lsu_addrcheck.scala 117:27]
|
||||
io.exc_mscause_d <= _T_189 @[lsu_addrcheck.scala 117:21]
|
||||
node _T_190 = eq(start_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:66]
|
||||
node _T_191 = and(start_addr_in_dccm_region_d, _T_190) @[lsu_addrcheck.scala 118:64]
|
||||
node _T_192 = eq(end_addr_in_dccm_d, UInt<1>("h00")) @[lsu_addrcheck.scala 118:120]
|
||||
node _T_193 = and(end_addr_in_dccm_region_d, _T_192) @[lsu_addrcheck.scala 118:118]
|
||||
node _T_194 = or(_T_191, _T_193) @[lsu_addrcheck.scala 118:88]
|
||||
node _T_195 = and(_T_194, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 118:142]
|
||||
node _T_196 = and(_T_195, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 118:163]
|
||||
io.fir_dccm_access_error_d <= _T_196 @[lsu_addrcheck.scala 118:31]
|
||||
node _T_197 = and(start_addr_in_dccm_region_d, end_addr_in_dccm_region_d) @[lsu_addrcheck.scala 119:66]
|
||||
node _T_198 = eq(_T_197, UInt<1>("h00")) @[lsu_addrcheck.scala 119:36]
|
||||
node _T_199 = and(_T_198, io.lsu_pkt_d.valid) @[lsu_addrcheck.scala 119:95]
|
||||
node _T_200 = and(_T_199, io.lsu_pkt_d.bits.fast_int) @[lsu_addrcheck.scala 119:116]
|
||||
io.fir_nondccm_access_error_d <= _T_200 @[lsu_addrcheck.scala 119:33]
|
||||
reg _T_201 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_addrcheck.scala 121:60]
|
||||
_T_201 <= is_sideeffects_d @[lsu_addrcheck.scala 121:60]
|
||||
io.is_sideeffects_m <= _T_201 @[lsu_addrcheck.scala 121:50]
|
||||
|
||||
extmodule gated_latch :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of gated_latch @[lib.scala 334:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||||
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||||
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||||
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||||
|
||||
extmodule gated_latch_1 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr_1 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of gated_latch_1 @[lib.scala 334:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||||
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||||
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||||
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||||
|
||||
extmodule gated_latch_2 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr_2 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of gated_latch_2 @[lib.scala 334:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||||
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||||
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||||
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||||
|
||||
extmodule gated_latch_3 :
|
||||
output Q : Clock
|
||||
input CK : Clock
|
||||
input EN : UInt<1>
|
||||
input SE : UInt<1>
|
||||
|
||||
defname = gated_latch
|
||||
|
||||
|
||||
module rvclkhdr_3 :
|
||||
input clock : Clock
|
||||
input reset : Reset
|
||||
output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>}
|
||||
|
||||
inst clkhdr of gated_latch_3 @[lib.scala 334:26]
|
||||
clkhdr.SE is invalid
|
||||
clkhdr.EN is invalid
|
||||
clkhdr.CK is invalid
|
||||
clkhdr.Q is invalid
|
||||
io.l1clk <= clkhdr.Q @[lib.scala 335:14]
|
||||
clkhdr.CK <= io.clk @[lib.scala 336:18]
|
||||
clkhdr.EN <= io.en @[lib.scala 337:18]
|
||||
clkhdr.SE <= io.scan_mode @[lib.scala 338:18]
|
||||
|
||||
module lsu_lsc_ctl :
|
||||
input clock : Clock
|
||||
input reset : AsyncReset
|
||||
output io : {flip clk_override : UInt<1>, flip lsu_c1_m_clk : Clock, flip lsu_c1_r_clk : Clock, flip lsu_c2_m_clk : Clock, flip lsu_c2_r_clk : Clock, flip lsu_store_c1_m_clk : Clock, flip lsu_ld_data_r : UInt<32>, flip lsu_ld_data_corr_r : UInt<32>, flip lsu_single_ecc_error_r : UInt<1>, flip lsu_double_ecc_error_r : UInt<1>, flip lsu_ld_data_m : UInt<32>, flip lsu_single_ecc_error_m : UInt<1>, flip lsu_double_ecc_error_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, lsu_exu : {flip exu_lsu_rs1_d : UInt<32>, flip exu_lsu_rs2_d : UInt<32>, lsu_result_m : UInt<32>}, flip lsu_p : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip dec_lsu_valid_raw_d : UInt<1>, flip dec_lsu_offset_d : UInt<12>, flip picm_mask_data_m : UInt<32>, flip bus_read_data_m : UInt<32>, lsu_result_corr_r : UInt<32>, lsu_addr_d : UInt<32>, lsu_addr_m : UInt<32>, lsu_addr_r : UInt<32>, end_addr_d : UInt<32>, end_addr_m : UInt<32>, end_addr_r : UInt<32>, store_data_m : UInt<32>, flip dec_tlu_mrac_ff : UInt<32>, lsu_exc_m : UInt<1>, is_sideeffects_m : UInt<1>, lsu_commit_r : UInt<1>, lsu_single_ecc_error_incr : UInt<1>, lsu_error_pkt_r : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, lsu_fir_addr : UInt<31>, lsu_fir_error : UInt<2>, addr_in_dccm_d : UInt<1>, addr_in_dccm_m : UInt<1>, addr_in_dccm_r : UInt<1>, addr_in_pic_d : UInt<1>, addr_in_pic_m : UInt<1>, addr_in_pic_r : UInt<1>, addr_external_m : UInt<1>, dma_lsc_ctl : {flip dma_dccm_req : UInt<1>, flip dma_mem_addr : UInt<32>, flip dma_mem_sz : UInt<3>, flip dma_mem_write : UInt<1>, flip dma_mem_wdata : UInt<64>}, lsu_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip scan_mode : UInt<1>}
|
||||
|
||||
wire end_addr_pre_m : UInt<29>
|
||||
end_addr_pre_m <= UInt<29>("h00")
|
||||
wire end_addr_pre_r : UInt<29>
|
||||
end_addr_pre_r <= UInt<29>("h00")
|
||||
wire dma_pkt_d : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 93:29]
|
||||
wire lsu_pkt_m_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 94:29]
|
||||
wire lsu_pkt_r_in : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 95:29]
|
||||
wire lsu_error_pkt_m : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 96:29]
|
||||
wire _T : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.bits.addr <= UInt<32>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.bits.mscause <= UInt<4>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.bits.exc_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.bits.inst_type <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.bits.single_ecc_error <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
_T.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 97:35]
|
||||
lsu_error_pkt_m.bits.addr <= _T.bits.addr @[lsu_lsc_ctl.scala 97:20]
|
||||
lsu_error_pkt_m.bits.mscause <= _T.bits.mscause @[lsu_lsc_ctl.scala 97:20]
|
||||
lsu_error_pkt_m.bits.exc_type <= _T.bits.exc_type @[lsu_lsc_ctl.scala 97:20]
|
||||
lsu_error_pkt_m.bits.inst_type <= _T.bits.inst_type @[lsu_lsc_ctl.scala 97:20]
|
||||
lsu_error_pkt_m.bits.single_ecc_error <= _T.bits.single_ecc_error @[lsu_lsc_ctl.scala 97:20]
|
||||
lsu_error_pkt_m.valid <= _T.valid @[lsu_lsc_ctl.scala 97:20]
|
||||
node _T_1 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 99:52]
|
||||
node lsu_rs1_d = mux(_T_1, io.lsu_exu.exu_lsu_rs1_d, io.dma_lsc_ctl.dma_mem_addr) @[lsu_lsc_ctl.scala 99:28]
|
||||
node _T_2 = bits(io.dec_lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 100:44]
|
||||
node _T_3 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_4 = mux(_T_3, UInt<12>("h0fff"), UInt<12>("h00")) @[Bitwise.scala 72:12]
|
||||
node lsu_offset_d = and(_T_2, _T_4) @[lsu_lsc_ctl.scala 100:51]
|
||||
node _T_5 = bits(io.lsu_pkt_d.bits.load_ldst_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 103:66]
|
||||
node rs1_d = mux(_T_5, io.lsu_exu.lsu_result_m, lsu_rs1_d) @[lsu_lsc_ctl.scala 103:28]
|
||||
node _T_6 = bits(rs1_d, 11, 0) @[lib.scala 92:31]
|
||||
node _T_7 = cat(UInt<1>("h00"), _T_6) @[Cat.scala 29:58]
|
||||
node _T_8 = bits(lsu_offset_d, 11, 0) @[lib.scala 92:60]
|
||||
node _T_9 = cat(UInt<1>("h00"), _T_8) @[Cat.scala 29:58]
|
||||
node _T_10 = add(_T_7, _T_9) @[lib.scala 92:39]
|
||||
node _T_11 = tail(_T_10, 1) @[lib.scala 92:39]
|
||||
node _T_12 = bits(lsu_offset_d, 11, 11) @[lib.scala 93:41]
|
||||
node _T_13 = bits(_T_11, 12, 12) @[lib.scala 93:50]
|
||||
node _T_14 = xor(_T_12, _T_13) @[lib.scala 93:46]
|
||||
node _T_15 = not(_T_14) @[lib.scala 93:33]
|
||||
node _T_16 = bits(_T_15, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_17 = mux(_T_16, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_18 = bits(rs1_d, 31, 12) @[lib.scala 93:63]
|
||||
node _T_19 = and(_T_17, _T_18) @[lib.scala 93:58]
|
||||
node _T_20 = bits(lsu_offset_d, 11, 11) @[lib.scala 94:25]
|
||||
node _T_21 = not(_T_20) @[lib.scala 94:18]
|
||||
node _T_22 = bits(_T_11, 12, 12) @[lib.scala 94:34]
|
||||
node _T_23 = and(_T_21, _T_22) @[lib.scala 94:30]
|
||||
node _T_24 = bits(_T_23, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_25 = mux(_T_24, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_26 = bits(rs1_d, 31, 12) @[lib.scala 94:47]
|
||||
node _T_27 = add(_T_26, UInt<1>("h01")) @[lib.scala 94:54]
|
||||
node _T_28 = tail(_T_27, 1) @[lib.scala 94:54]
|
||||
node _T_29 = and(_T_25, _T_28) @[lib.scala 94:41]
|
||||
node _T_30 = or(_T_19, _T_29) @[lib.scala 93:72]
|
||||
node _T_31 = bits(lsu_offset_d, 11, 11) @[lib.scala 95:24]
|
||||
node _T_32 = bits(_T_11, 12, 12) @[lib.scala 95:34]
|
||||
node _T_33 = not(_T_32) @[lib.scala 95:31]
|
||||
node _T_34 = and(_T_31, _T_33) @[lib.scala 95:29]
|
||||
node _T_35 = bits(_T_34, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_36 = mux(_T_35, UInt<20>("h0fffff"), UInt<20>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_37 = bits(rs1_d, 31, 12) @[lib.scala 95:47]
|
||||
node _T_38 = sub(_T_37, UInt<1>("h01")) @[lib.scala 95:54]
|
||||
node _T_39 = tail(_T_38, 1) @[lib.scala 95:54]
|
||||
node _T_40 = and(_T_36, _T_39) @[lib.scala 95:41]
|
||||
node _T_41 = or(_T_30, _T_40) @[lib.scala 94:61]
|
||||
node _T_42 = bits(_T_11, 11, 0) @[lib.scala 96:22]
|
||||
node full_addr_d = cat(_T_41, _T_42) @[Cat.scala 29:58]
|
||||
node _T_43 = bits(io.lsu_pkt_d.bits.half, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_44 = mux(_T_43, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_45 = and(_T_44, UInt<3>("h01")) @[lsu_lsc_ctl.scala 108:58]
|
||||
node _T_46 = bits(io.lsu_pkt_d.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_47 = mux(_T_46, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_48 = and(_T_47, UInt<3>("h03")) @[lsu_lsc_ctl.scala 109:40]
|
||||
node _T_49 = or(_T_45, _T_48) @[lsu_lsc_ctl.scala 108:70]
|
||||
node _T_50 = bits(io.lsu_pkt_d.bits.dword, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_51 = mux(_T_50, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_52 = and(_T_51, UInt<3>("h07")) @[lsu_lsc_ctl.scala 110:40]
|
||||
node addr_offset_d = or(_T_49, _T_52) @[lsu_lsc_ctl.scala 109:52]
|
||||
node _T_53 = bits(lsu_offset_d, 11, 11) @[lsu_lsc_ctl.scala 112:39]
|
||||
node _T_54 = bits(lsu_offset_d, 11, 0) @[lsu_lsc_ctl.scala 112:52]
|
||||
node _T_55 = cat(_T_53, _T_54) @[Cat.scala 29:58]
|
||||
node _T_56 = mux(UInt<1>("h00"), UInt<9>("h01ff"), UInt<9>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_57 = bits(addr_offset_d, 2, 0) @[lsu_lsc_ctl.scala 112:91]
|
||||
node _T_58 = cat(_T_56, _T_57) @[Cat.scala 29:58]
|
||||
node _T_59 = add(_T_55, _T_58) @[lsu_lsc_ctl.scala 112:60]
|
||||
node end_addr_offset_d = tail(_T_59, 1) @[lsu_lsc_ctl.scala 112:60]
|
||||
node _T_60 = bits(rs1_d, 31, 0) @[lsu_lsc_ctl.scala 113:32]
|
||||
node _T_61 = bits(end_addr_offset_d, 12, 12) @[lsu_lsc_ctl.scala 113:70]
|
||||
node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_63 = mux(_T_62, UInt<19>("h07ffff"), UInt<19>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_64 = bits(end_addr_offset_d, 12, 0) @[lsu_lsc_ctl.scala 113:93]
|
||||
node _T_65 = cat(_T_63, _T_64) @[Cat.scala 29:58]
|
||||
node _T_66 = add(_T_60, _T_65) @[lsu_lsc_ctl.scala 113:39]
|
||||
node full_end_addr_d = tail(_T_66, 1) @[lsu_lsc_ctl.scala 113:39]
|
||||
io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 114:24]
|
||||
inst addrcheck of lsu_addrcheck @[lsu_lsc_ctl.scala 117:25]
|
||||
addrcheck.clock <= clock
|
||||
addrcheck.reset <= reset
|
||||
addrcheck.io.lsu_c2_m_clk <= io.lsu_c2_m_clk @[lsu_lsc_ctl.scala 119:42]
|
||||
addrcheck.io.start_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 121:42]
|
||||
addrcheck.io.end_addr_d <= full_end_addr_d @[lsu_lsc_ctl.scala 122:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.lsu_pkt_d.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 123:42]
|
||||
addrcheck.io.dec_tlu_mrac_ff <= io.dec_tlu_mrac_ff @[lsu_lsc_ctl.scala 124:42]
|
||||
node _T_67 = bits(rs1_d, 31, 28) @[lsu_lsc_ctl.scala 125:50]
|
||||
addrcheck.io.rs1_region_d <= _T_67 @[lsu_lsc_ctl.scala 125:42]
|
||||
addrcheck.io.rs1_d <= rs1_d @[lsu_lsc_ctl.scala 126:42]
|
||||
io.is_sideeffects_m <= addrcheck.io.is_sideeffects_m @[lsu_lsc_ctl.scala 127:42]
|
||||
io.addr_in_dccm_d <= addrcheck.io.addr_in_dccm_d @[lsu_lsc_ctl.scala 128:42]
|
||||
io.addr_in_pic_d <= addrcheck.io.addr_in_pic_d @[lsu_lsc_ctl.scala 129:42]
|
||||
addrcheck.io.scan_mode <= io.scan_mode @[lsu_lsc_ctl.scala 136:42]
|
||||
wire exc_mscause_r : UInt<4>
|
||||
exc_mscause_r <= UInt<4>("h00")
|
||||
wire fir_dccm_access_error_r : UInt<1>
|
||||
fir_dccm_access_error_r <= UInt<1>("h00")
|
||||
wire fir_nondccm_access_error_r : UInt<1>
|
||||
fir_nondccm_access_error_r <= UInt<1>("h00")
|
||||
wire access_fault_r : UInt<1>
|
||||
access_fault_r <= UInt<1>("h00")
|
||||
wire misaligned_fault_r : UInt<1>
|
||||
misaligned_fault_r <= UInt<1>("h00")
|
||||
wire lsu_fir_error_m : UInt<2>
|
||||
lsu_fir_error_m <= UInt<2>("h00")
|
||||
wire fir_dccm_access_error_m : UInt<1>
|
||||
fir_dccm_access_error_m <= UInt<1>("h00")
|
||||
wire fir_nondccm_access_error_m : UInt<1>
|
||||
fir_nondccm_access_error_m <= UInt<1>("h00")
|
||||
reg access_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 148:75]
|
||||
access_fault_m <= addrcheck.io.access_fault_d @[lsu_lsc_ctl.scala 148:75]
|
||||
reg misaligned_fault_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 149:75]
|
||||
misaligned_fault_m <= addrcheck.io.misaligned_fault_d @[lsu_lsc_ctl.scala 149:75]
|
||||
reg exc_mscause_m : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 150:75]
|
||||
exc_mscause_m <= addrcheck.io.exc_mscause_d @[lsu_lsc_ctl.scala 150:75]
|
||||
reg _T_68 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 151:75]
|
||||
_T_68 <= addrcheck.io.fir_dccm_access_error_d @[lsu_lsc_ctl.scala 151:75]
|
||||
fir_dccm_access_error_m <= _T_68 @[lsu_lsc_ctl.scala 151:38]
|
||||
reg _T_69 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 152:75]
|
||||
_T_69 <= addrcheck.io.fir_nondccm_access_error_d @[lsu_lsc_ctl.scala 152:75]
|
||||
fir_nondccm_access_error_m <= _T_69 @[lsu_lsc_ctl.scala 152:38]
|
||||
node _T_70 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 154:34]
|
||||
io.lsu_exc_m <= _T_70 @[lsu_lsc_ctl.scala 154:16]
|
||||
node _T_71 = eq(io.lsu_double_ecc_error_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 155:64]
|
||||
node _T_72 = and(io.lsu_single_ecc_error_r, _T_71) @[lsu_lsc_ctl.scala 155:62]
|
||||
node _T_73 = or(io.lsu_commit_r, io.lsu_pkt_r.bits.dma) @[lsu_lsc_ctl.scala 155:111]
|
||||
node _T_74 = and(_T_72, _T_73) @[lsu_lsc_ctl.scala 155:92]
|
||||
node _T_75 = and(_T_74, io.lsu_pkt_r.valid) @[lsu_lsc_ctl.scala 155:136]
|
||||
io.lsu_single_ecc_error_incr <= _T_75 @[lsu_lsc_ctl.scala 155:32]
|
||||
node _T_76 = or(access_fault_m, misaligned_fault_m) @[lsu_lsc_ctl.scala 177:46]
|
||||
node _T_77 = or(_T_76, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 177:67]
|
||||
node _T_78 = and(_T_77, io.lsu_pkt_m.valid) @[lsu_lsc_ctl.scala 177:96]
|
||||
node _T_79 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:119]
|
||||
node _T_80 = and(_T_78, _T_79) @[lsu_lsc_ctl.scala 177:117]
|
||||
node _T_81 = eq(io.lsu_pkt_m.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:144]
|
||||
node _T_82 = and(_T_80, _T_81) @[lsu_lsc_ctl.scala 177:142]
|
||||
node _T_83 = eq(io.flush_m_up, UInt<1>("h00")) @[lsu_lsc_ctl.scala 177:174]
|
||||
node _T_84 = and(_T_82, _T_83) @[lsu_lsc_ctl.scala 177:172]
|
||||
lsu_error_pkt_m.valid <= _T_84 @[lsu_lsc_ctl.scala 177:27]
|
||||
node _T_85 = eq(lsu_error_pkt_m.valid, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:75]
|
||||
node _T_86 = and(io.lsu_single_ecc_error_m, _T_85) @[lsu_lsc_ctl.scala 178:73]
|
||||
node _T_87 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 178:101]
|
||||
node _T_88 = and(_T_86, _T_87) @[lsu_lsc_ctl.scala 178:99]
|
||||
lsu_error_pkt_m.bits.single_ecc_error <= _T_88 @[lsu_lsc_ctl.scala 178:43]
|
||||
lsu_error_pkt_m.bits.inst_type <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 179:43]
|
||||
node _T_89 = not(misaligned_fault_m) @[lsu_lsc_ctl.scala 180:46]
|
||||
lsu_error_pkt_m.bits.exc_type <= _T_89 @[lsu_lsc_ctl.scala 180:43]
|
||||
node _T_90 = eq(misaligned_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:80]
|
||||
node _T_91 = and(io.lsu_double_ecc_error_m, _T_90) @[lsu_lsc_ctl.scala 181:78]
|
||||
node _T_92 = eq(access_fault_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 181:102]
|
||||
node _T_93 = and(_T_91, _T_92) @[lsu_lsc_ctl.scala 181:100]
|
||||
node _T_94 = eq(_T_93, UInt<1>("h01")) @[lsu_lsc_ctl.scala 181:118]
|
||||
node _T_95 = bits(exc_mscause_m, 3, 0) @[lsu_lsc_ctl.scala 181:149]
|
||||
node _T_96 = mux(_T_94, UInt<4>("h01"), _T_95) @[lsu_lsc_ctl.scala 181:49]
|
||||
lsu_error_pkt_m.bits.mscause <= _T_96 @[lsu_lsc_ctl.scala 181:43]
|
||||
node _T_97 = bits(io.lsu_addr_m, 31, 0) @[lsu_lsc_ctl.scala 182:59]
|
||||
lsu_error_pkt_m.bits.addr <= _T_97 @[lsu_lsc_ctl.scala 182:43]
|
||||
node _T_98 = bits(fir_nondccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:72]
|
||||
node _T_99 = bits(fir_dccm_access_error_m, 0, 0) @[lsu_lsc_ctl.scala 183:117]
|
||||
node _T_100 = and(io.lsu_pkt_m.bits.fast_int, io.lsu_double_ecc_error_m) @[lsu_lsc_ctl.scala 183:166]
|
||||
node _T_101 = bits(_T_100, 0, 0) @[lsu_lsc_ctl.scala 183:195]
|
||||
node _T_102 = mux(_T_101, UInt<2>("h01"), UInt<2>("h00")) @[lsu_lsc_ctl.scala 183:137]
|
||||
node _T_103 = mux(_T_99, UInt<2>("h02"), _T_102) @[lsu_lsc_ctl.scala 183:92]
|
||||
node _T_104 = mux(_T_98, UInt<2>("h03"), _T_103) @[lsu_lsc_ctl.scala 183:44]
|
||||
lsu_fir_error_m <= _T_104 @[lsu_lsc_ctl.scala 183:38]
|
||||
node _T_105 = or(lsu_error_pkt_m.valid, lsu_error_pkt_m.bits.single_ecc_error) @[lsu_lsc_ctl.scala 184:73]
|
||||
node _T_106 = or(_T_105, io.clk_override) @[lsu_lsc_ctl.scala 184:113]
|
||||
node _T_107 = bits(_T_106, 0, 0) @[lib.scala 8:44]
|
||||
node _T_108 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr of rvclkhdr @[lib.scala 417:23]
|
||||
rvclkhdr.clock <= clock
|
||||
rvclkhdr.reset <= reset
|
||||
rvclkhdr.io.clk <= clock @[lib.scala 419:18]
|
||||
rvclkhdr.io.en <= _T_107 @[lib.scala 420:17]
|
||||
rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 421:24]
|
||||
wire _T_109 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}} @[lib.scala 423:50]
|
||||
_T_109.bits.addr <= UInt<32>("h00") @[lib.scala 423:50]
|
||||
_T_109.bits.mscause <= UInt<4>("h00") @[lib.scala 423:50]
|
||||
_T_109.bits.exc_type <= UInt<1>("h00") @[lib.scala 423:50]
|
||||
_T_109.bits.inst_type <= UInt<1>("h00") @[lib.scala 423:50]
|
||||
_T_109.bits.single_ecc_error <= UInt<1>("h00") @[lib.scala 423:50]
|
||||
_T_109.valid <= UInt<1>("h00") @[lib.scala 423:50]
|
||||
reg _T_110 : {valid : UInt<1>, bits : {single_ecc_error : UInt<1>, inst_type : UInt<1>, exc_type : UInt<1>, mscause : UInt<4>, addr : UInt<32>}}, clock with : (reset => (reset, _T_109)) @[Reg.scala 27:20]
|
||||
when _T_107 : @[Reg.scala 28:19]
|
||||
_T_110.bits.addr <= lsu_error_pkt_m.bits.addr @[Reg.scala 28:23]
|
||||
_T_110.bits.mscause <= lsu_error_pkt_m.bits.mscause @[Reg.scala 28:23]
|
||||
_T_110.bits.exc_type <= lsu_error_pkt_m.bits.exc_type @[Reg.scala 28:23]
|
||||
_T_110.bits.inst_type <= lsu_error_pkt_m.bits.inst_type @[Reg.scala 28:23]
|
||||
_T_110.bits.single_ecc_error <= lsu_error_pkt_m.bits.single_ecc_error @[Reg.scala 28:23]
|
||||
_T_110.valid <= lsu_error_pkt_m.valid @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
io.lsu_error_pkt_r.bits.addr <= _T_110.bits.addr @[lsu_lsc_ctl.scala 184:24]
|
||||
io.lsu_error_pkt_r.bits.mscause <= _T_110.bits.mscause @[lsu_lsc_ctl.scala 184:24]
|
||||
io.lsu_error_pkt_r.bits.exc_type <= _T_110.bits.exc_type @[lsu_lsc_ctl.scala 184:24]
|
||||
io.lsu_error_pkt_r.bits.inst_type <= _T_110.bits.inst_type @[lsu_lsc_ctl.scala 184:24]
|
||||
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_110.bits.single_ecc_error @[lsu_lsc_ctl.scala 184:24]
|
||||
io.lsu_error_pkt_r.valid <= _T_110.valid @[lsu_lsc_ctl.scala 184:24]
|
||||
reg _T_111 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 185:83]
|
||||
_T_111 <= lsu_error_pkt_m.bits.single_ecc_error @[lsu_lsc_ctl.scala 185:83]
|
||||
io.lsu_error_pkt_r.bits.single_ecc_error <= _T_111 @[lsu_lsc_ctl.scala 185:46]
|
||||
reg _T_112 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 186:67]
|
||||
_T_112 <= lsu_error_pkt_m.valid @[lsu_lsc_ctl.scala 186:67]
|
||||
io.lsu_error_pkt_r.valid <= _T_112 @[lsu_lsc_ctl.scala 186:30]
|
||||
reg _T_113 : UInt, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 187:75]
|
||||
_T_113 <= lsu_fir_error_m @[lsu_lsc_ctl.scala 187:75]
|
||||
io.lsu_fir_error <= _T_113 @[lsu_lsc_ctl.scala 187:38]
|
||||
dma_pkt_d.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 189:27]
|
||||
dma_pkt_d.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 190:26]
|
||||
dma_pkt_d.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 191:27]
|
||||
dma_pkt_d.valid <= io.dma_lsc_ctl.dma_dccm_req @[lsu_lsc_ctl.scala 192:22]
|
||||
dma_pkt_d.bits.dma <= UInt<1>("h01") @[lsu_lsc_ctl.scala 193:27]
|
||||
dma_pkt_d.bits.store <= io.dma_lsc_ctl.dma_mem_write @[lsu_lsc_ctl.scala 194:27]
|
||||
node _T_114 = not(io.dma_lsc_ctl.dma_mem_write) @[lsu_lsc_ctl.scala 195:30]
|
||||
dma_pkt_d.bits.load <= _T_114 @[lsu_lsc_ctl.scala 195:27]
|
||||
node _T_115 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 196:56]
|
||||
node _T_116 = eq(_T_115, UInt<3>("h00")) @[lsu_lsc_ctl.scala 196:62]
|
||||
dma_pkt_d.bits.by <= _T_116 @[lsu_lsc_ctl.scala 196:27]
|
||||
node _T_117 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 197:56]
|
||||
node _T_118 = eq(_T_117, UInt<3>("h01")) @[lsu_lsc_ctl.scala 197:62]
|
||||
dma_pkt_d.bits.half <= _T_118 @[lsu_lsc_ctl.scala 197:27]
|
||||
node _T_119 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 198:56]
|
||||
node _T_120 = eq(_T_119, UInt<3>("h02")) @[lsu_lsc_ctl.scala 198:62]
|
||||
dma_pkt_d.bits.word <= _T_120 @[lsu_lsc_ctl.scala 198:27]
|
||||
node _T_121 = bits(io.dma_lsc_ctl.dma_mem_sz, 2, 0) @[lsu_lsc_ctl.scala 199:56]
|
||||
node _T_122 = eq(_T_121, UInt<3>("h03")) @[lsu_lsc_ctl.scala 199:62]
|
||||
dma_pkt_d.bits.dword <= _T_122 @[lsu_lsc_ctl.scala 199:27]
|
||||
dma_pkt_d.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 200:39]
|
||||
dma_pkt_d.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 201:39]
|
||||
dma_pkt_d.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 202:39]
|
||||
wire lsu_ld_datafn_r : UInt<32>
|
||||
lsu_ld_datafn_r <= UInt<32>("h00")
|
||||
wire lsu_ld_datafn_corr_r : UInt<32>
|
||||
lsu_ld_datafn_corr_r <= UInt<32>("h00")
|
||||
wire lsu_ld_datafn_m : UInt<32>
|
||||
lsu_ld_datafn_m <= UInt<32>("h00")
|
||||
node _T_123 = bits(io.dec_lsu_valid_raw_d, 0, 0) @[lsu_lsc_ctl.scala 208:50]
|
||||
node _T_124 = mux(_T_123, io.lsu_p, dma_pkt_d) @[lsu_lsc_ctl.scala 208:26]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_m <= _T_124.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.load_ldst_bypass_d <= _T_124.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.store_data_bypass_d <= _T_124.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.dma <= _T_124.bits.dma @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.unsign <= _T_124.bits.unsign @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.store <= _T_124.bits.store @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.load <= _T_124.bits.load @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.dword <= _T_124.bits.dword @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.word <= _T_124.bits.word @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.half <= _T_124.bits.half @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.by <= _T_124.bits.by @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.stack <= _T_124.bits.stack @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.bits.fast_int <= _T_124.bits.fast_int @[lsu_lsc_ctl.scala 208:20]
|
||||
io.lsu_pkt_d.valid <= _T_124.valid @[lsu_lsc_ctl.scala 208:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_m <= io.lsu_pkt_d.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.load_ldst_bypass_d <= io.lsu_pkt_d.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.store_data_bypass_d <= io.lsu_pkt_d.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.dma <= io.lsu_pkt_d.bits.dma @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.unsign <= io.lsu_pkt_d.bits.unsign @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.store <= io.lsu_pkt_d.bits.store @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.load <= io.lsu_pkt_d.bits.load @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.dword <= io.lsu_pkt_d.bits.dword @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.word <= io.lsu_pkt_d.bits.word @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.half <= io.lsu_pkt_d.bits.half @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.by <= io.lsu_pkt_d.bits.by @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.stack <= io.lsu_pkt_d.bits.stack @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.bits.fast_int <= io.lsu_pkt_d.bits.fast_int @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_m_in.valid <= io.lsu_pkt_d.valid @[lsu_lsc_ctl.scala 209:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_m <= io.lsu_pkt_m.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.load_ldst_bypass_d <= io.lsu_pkt_m.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.store_data_bypass_d <= io.lsu_pkt_m.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.dma <= io.lsu_pkt_m.bits.dma @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.unsign <= io.lsu_pkt_m.bits.unsign @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.store <= io.lsu_pkt_m.bits.store @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.load <= io.lsu_pkt_m.bits.load @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.dword <= io.lsu_pkt_m.bits.dword @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.word <= io.lsu_pkt_m.bits.word @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.half <= io.lsu_pkt_m.bits.half @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.by <= io.lsu_pkt_m.bits.by @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.stack <= io.lsu_pkt_m.bits.stack @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.bits.fast_int <= io.lsu_pkt_m.bits.fast_int @[lsu_lsc_ctl.scala 210:20]
|
||||
lsu_pkt_r_in.valid <= io.lsu_pkt_m.valid @[lsu_lsc_ctl.scala 210:20]
|
||||
node _T_125 = eq(io.lsu_p.bits.fast_int, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:64]
|
||||
node _T_126 = and(io.flush_m_up, _T_125) @[lsu_lsc_ctl.scala 212:61]
|
||||
node _T_127 = eq(_T_126, UInt<1>("h00")) @[lsu_lsc_ctl.scala 212:45]
|
||||
node _T_128 = and(io.lsu_p.valid, _T_127) @[lsu_lsc_ctl.scala 212:43]
|
||||
node _T_129 = or(_T_128, io.dma_lsc_ctl.dma_dccm_req) @[lsu_lsc_ctl.scala 212:90]
|
||||
io.lsu_pkt_d.valid <= _T_129 @[lsu_lsc_ctl.scala 212:24]
|
||||
node _T_130 = eq(io.lsu_pkt_d.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:68]
|
||||
node _T_131 = and(io.flush_m_up, _T_130) @[lsu_lsc_ctl.scala 213:65]
|
||||
node _T_132 = eq(_T_131, UInt<1>("h00")) @[lsu_lsc_ctl.scala 213:49]
|
||||
node _T_133 = and(io.lsu_pkt_d.valid, _T_132) @[lsu_lsc_ctl.scala 213:47]
|
||||
lsu_pkt_m_in.valid <= _T_133 @[lsu_lsc_ctl.scala 213:24]
|
||||
node _T_134 = eq(io.lsu_pkt_m.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:68]
|
||||
node _T_135 = and(io.flush_m_up, _T_134) @[lsu_lsc_ctl.scala 214:65]
|
||||
node _T_136 = eq(_T_135, UInt<1>("h00")) @[lsu_lsc_ctl.scala 214:49]
|
||||
node _T_137 = and(io.lsu_pkt_m.valid, _T_136) @[lsu_lsc_ctl.scala 214:47]
|
||||
lsu_pkt_r_in.valid <= _T_137 @[lsu_lsc_ctl.scala 214:24]
|
||||
wire _T_138 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
_T_138.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 216:91]
|
||||
reg _T_139 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_m_clk with : (reset => (reset, _T_138)) @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.store_data_bypass_m <= lsu_pkt_m_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.load_ldst_bypass_d <= lsu_pkt_m_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.store_data_bypass_d <= lsu_pkt_m_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.dma <= lsu_pkt_m_in.bits.dma @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.unsign <= lsu_pkt_m_in.bits.unsign @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.store <= lsu_pkt_m_in.bits.store @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.load <= lsu_pkt_m_in.bits.load @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.dword <= lsu_pkt_m_in.bits.dword @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.word <= lsu_pkt_m_in.bits.word @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.half <= lsu_pkt_m_in.bits.half @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.by <= lsu_pkt_m_in.bits.by @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.stack <= lsu_pkt_m_in.bits.stack @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.bits.fast_int <= lsu_pkt_m_in.bits.fast_int @[lsu_lsc_ctl.scala 216:65]
|
||||
_T_139.valid <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 216:65]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_m <= _T_139.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.load_ldst_bypass_d <= _T_139.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.store_data_bypass_d <= _T_139.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.dma <= _T_139.bits.dma @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.unsign <= _T_139.bits.unsign @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.store <= _T_139.bits.store @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.load <= _T_139.bits.load @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.dword <= _T_139.bits.dword @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.word <= _T_139.bits.word @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.half <= _T_139.bits.half @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.by <= _T_139.bits.by @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.stack <= _T_139.bits.stack @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.bits.fast_int <= _T_139.bits.fast_int @[lsu_lsc_ctl.scala 216:28]
|
||||
io.lsu_pkt_m.valid <= _T_139.valid @[lsu_lsc_ctl.scala 216:28]
|
||||
wire _T_140 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}} @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.store_data_bypass_m <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.load_ldst_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.store_data_bypass_d <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.dma <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.unsign <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.store <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.load <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.dword <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.word <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.half <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.by <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.stack <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.bits.fast_int <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
_T_140.valid <= UInt<1>("h00") @[lsu_lsc_ctl.scala 217:91]
|
||||
reg _T_141 : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, io.lsu_c1_r_clk with : (reset => (reset, _T_140)) @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.store_data_bypass_m <= lsu_pkt_r_in.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.load_ldst_bypass_d <= lsu_pkt_r_in.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.store_data_bypass_d <= lsu_pkt_r_in.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.dma <= lsu_pkt_r_in.bits.dma @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.unsign <= lsu_pkt_r_in.bits.unsign @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.store <= lsu_pkt_r_in.bits.store @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.load <= lsu_pkt_r_in.bits.load @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.dword <= lsu_pkt_r_in.bits.dword @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.word <= lsu_pkt_r_in.bits.word @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.half <= lsu_pkt_r_in.bits.half @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.by <= lsu_pkt_r_in.bits.by @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.stack <= lsu_pkt_r_in.bits.stack @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.bits.fast_int <= lsu_pkt_r_in.bits.fast_int @[lsu_lsc_ctl.scala 217:65]
|
||||
_T_141.valid <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 217:65]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_m <= _T_141.bits.store_data_bypass_m @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.load_ldst_bypass_d <= _T_141.bits.load_ldst_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.store_data_bypass_d <= _T_141.bits.store_data_bypass_d @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.dma <= _T_141.bits.dma @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.unsign <= _T_141.bits.unsign @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.store <= _T_141.bits.store @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.load <= _T_141.bits.load @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.dword <= _T_141.bits.dword @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.word <= _T_141.bits.word @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.half <= _T_141.bits.half @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.by <= _T_141.bits.by @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.stack <= _T_141.bits.stack @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.bits.fast_int <= _T_141.bits.fast_int @[lsu_lsc_ctl.scala 217:28]
|
||||
io.lsu_pkt_r.valid <= _T_141.valid @[lsu_lsc_ctl.scala 217:28]
|
||||
reg _T_142 : UInt<1>, io.lsu_c2_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 218:65]
|
||||
_T_142 <= lsu_pkt_m_in.valid @[lsu_lsc_ctl.scala 218:65]
|
||||
io.lsu_pkt_m.valid <= _T_142 @[lsu_lsc_ctl.scala 218:28]
|
||||
reg _T_143 : UInt<1>, io.lsu_c2_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 219:65]
|
||||
_T_143 <= lsu_pkt_r_in.valid @[lsu_lsc_ctl.scala 219:65]
|
||||
io.lsu_pkt_r.valid <= _T_143 @[lsu_lsc_ctl.scala 219:28]
|
||||
node _T_144 = bits(io.dma_lsc_ctl.dma_mem_wdata, 63, 0) @[lsu_lsc_ctl.scala 221:59]
|
||||
node _T_145 = bits(io.dma_lsc_ctl.dma_mem_addr, 2, 0) @[lsu_lsc_ctl.scala 221:100]
|
||||
node _T_146 = cat(_T_145, UInt<3>("h00")) @[Cat.scala 29:58]
|
||||
node dma_mem_wdata_shifted = dshr(_T_144, _T_146) @[lsu_lsc_ctl.scala 221:66]
|
||||
node _T_147 = bits(io.dma_lsc_ctl.dma_dccm_req, 0, 0) @[lsu_lsc_ctl.scala 222:63]
|
||||
node _T_148 = bits(dma_mem_wdata_shifted, 31, 0) @[lsu_lsc_ctl.scala 222:91]
|
||||
node _T_149 = bits(io.lsu_exu.exu_lsu_rs2_d, 31, 0) @[lsu_lsc_ctl.scala 222:122]
|
||||
node store_data_d = mux(_T_147, _T_148, _T_149) @[lsu_lsc_ctl.scala 222:34]
|
||||
node _T_150 = bits(io.lsu_pkt_d.bits.store_data_bypass_d, 0, 0) @[lsu_lsc_ctl.scala 223:73]
|
||||
node _T_151 = bits(io.lsu_exu.lsu_result_m, 31, 0) @[lsu_lsc_ctl.scala 223:103]
|
||||
node _T_152 = bits(store_data_d, 31, 0) @[lsu_lsc_ctl.scala 223:122]
|
||||
node store_data_m_in = mux(_T_150, _T_151, _T_152) @[lsu_lsc_ctl.scala 223:34]
|
||||
reg store_data_pre_m : UInt, io.lsu_store_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 225:72]
|
||||
store_data_pre_m <= store_data_m_in @[lsu_lsc_ctl.scala 225:72]
|
||||
reg _T_153 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 226:62]
|
||||
_T_153 <= io.lsu_addr_d @[lsu_lsc_ctl.scala 226:62]
|
||||
io.lsu_addr_m <= _T_153 @[lsu_lsc_ctl.scala 226:24]
|
||||
reg _T_154 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 227:62]
|
||||
_T_154 <= io.lsu_addr_m @[lsu_lsc_ctl.scala 227:62]
|
||||
io.lsu_addr_r <= _T_154 @[lsu_lsc_ctl.scala 227:24]
|
||||
node _T_155 = bits(io.ldst_dual_m, 0, 0) @[lib.scala 8:44]
|
||||
node _T_156 = bits(io.lsu_addr_m, 31, 3) @[lsu_lsc_ctl.scala 228:71]
|
||||
node _T_157 = mux(_T_155, end_addr_pre_m, _T_156) @[lsu_lsc_ctl.scala 228:27]
|
||||
node _T_158 = bits(io.end_addr_d, 2, 0) @[lsu_lsc_ctl.scala 228:128]
|
||||
reg _T_159 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 228:114]
|
||||
_T_159 <= _T_158 @[lsu_lsc_ctl.scala 228:114]
|
||||
node _T_160 = cat(_T_157, _T_159) @[Cat.scala 29:58]
|
||||
io.end_addr_m <= _T_160 @[lsu_lsc_ctl.scala 228:17]
|
||||
node _T_161 = bits(io.ldst_dual_r, 0, 0) @[lib.scala 8:44]
|
||||
node _T_162 = bits(io.lsu_addr_r, 31, 3) @[lsu_lsc_ctl.scala 229:71]
|
||||
node _T_163 = mux(_T_161, end_addr_pre_r, _T_162) @[lsu_lsc_ctl.scala 229:27]
|
||||
node _T_164 = bits(io.end_addr_m, 2, 0) @[lsu_lsc_ctl.scala 229:128]
|
||||
reg _T_165 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 229:114]
|
||||
_T_165 <= _T_164 @[lsu_lsc_ctl.scala 229:114]
|
||||
node _T_166 = cat(_T_163, _T_165) @[Cat.scala 29:58]
|
||||
io.end_addr_r <= _T_166 @[lsu_lsc_ctl.scala 229:17]
|
||||
node _T_167 = bits(io.end_addr_d, 31, 3) @[lsu_lsc_ctl.scala 230:41]
|
||||
node _T_168 = and(io.lsu_pkt_d.valid, io.ldst_dual_d) @[lsu_lsc_ctl.scala 230:69]
|
||||
node _T_169 = or(_T_168, io.clk_override) @[lsu_lsc_ctl.scala 230:87]
|
||||
node _T_170 = bits(_T_169, 0, 0) @[lib.scala 8:44]
|
||||
node _T_171 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 404:23]
|
||||
rvclkhdr_1.clock <= clock
|
||||
rvclkhdr_1.reset <= reset
|
||||
rvclkhdr_1.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_1.io.en <= _T_170 @[lib.scala 407:17]
|
||||
rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg _T_172 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_170 : @[Reg.scala 28:19]
|
||||
_T_172 <= _T_167 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_m <= _T_172 @[lsu_lsc_ctl.scala 230:18]
|
||||
node _T_173 = bits(io.end_addr_m, 31, 3) @[lsu_lsc_ctl.scala 231:41]
|
||||
node _T_174 = and(io.lsu_pkt_m.valid, io.ldst_dual_m) @[lsu_lsc_ctl.scala 231:69]
|
||||
node _T_175 = or(_T_174, io.clk_override) @[lsu_lsc_ctl.scala 231:87]
|
||||
node _T_176 = bits(_T_175, 0, 0) @[lib.scala 8:44]
|
||||
node _T_177 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 404:23]
|
||||
rvclkhdr_2.clock <= clock
|
||||
rvclkhdr_2.reset <= reset
|
||||
rvclkhdr_2.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_2.io.en <= _T_176 @[lib.scala 407:17]
|
||||
rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg _T_178 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_176 : @[Reg.scala 28:19]
|
||||
_T_178 <= _T_173 @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
end_addr_pre_r <= _T_178 @[lsu_lsc_ctl.scala 231:18]
|
||||
reg _T_179 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 232:62]
|
||||
_T_179 <= io.addr_in_dccm_d @[lsu_lsc_ctl.scala 232:62]
|
||||
io.addr_in_dccm_m <= _T_179 @[lsu_lsc_ctl.scala 232:24]
|
||||
reg _T_180 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 233:62]
|
||||
_T_180 <= io.addr_in_dccm_m @[lsu_lsc_ctl.scala 233:62]
|
||||
io.addr_in_dccm_r <= _T_180 @[lsu_lsc_ctl.scala 233:24]
|
||||
reg _T_181 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 234:62]
|
||||
_T_181 <= io.addr_in_pic_d @[lsu_lsc_ctl.scala 234:62]
|
||||
io.addr_in_pic_m <= _T_181 @[lsu_lsc_ctl.scala 234:24]
|
||||
reg _T_182 : UInt, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 235:62]
|
||||
_T_182 <= io.addr_in_pic_m @[lsu_lsc_ctl.scala 235:62]
|
||||
io.addr_in_pic_r <= _T_182 @[lsu_lsc_ctl.scala 235:24]
|
||||
reg _T_183 : UInt, io.lsu_c1_m_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 236:62]
|
||||
_T_183 <= addrcheck.io.addr_external_d @[lsu_lsc_ctl.scala 236:62]
|
||||
io.addr_external_m <= _T_183 @[lsu_lsc_ctl.scala 236:24]
|
||||
reg addr_external_r : UInt<1>, io.lsu_c1_r_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_lsc_ctl.scala 237:66]
|
||||
addr_external_r <= io.addr_external_m @[lsu_lsc_ctl.scala 237:66]
|
||||
node _T_184 = or(io.addr_external_m, io.clk_override) @[lsu_lsc_ctl.scala 238:77]
|
||||
node _T_185 = bits(io.scan_mode, 0, 0) @[lib.scala 8:44]
|
||||
inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 404:23]
|
||||
rvclkhdr_3.clock <= clock
|
||||
rvclkhdr_3.reset <= reset
|
||||
rvclkhdr_3.io.clk <= clock @[lib.scala 406:18]
|
||||
rvclkhdr_3.io.en <= _T_184 @[lib.scala 407:17]
|
||||
rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 408:24]
|
||||
reg bus_read_data_r : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
|
||||
when _T_184 : @[Reg.scala 28:19]
|
||||
bus_read_data_r <= io.bus_read_data_m @[Reg.scala 28:23]
|
||||
skip @[Reg.scala 28:19]
|
||||
node _T_186 = bits(io.lsu_ld_data_corr_r, 31, 1) @[lsu_lsc_ctl.scala 241:52]
|
||||
io.lsu_fir_addr <= _T_186 @[lsu_lsc_ctl.scala 241:28]
|
||||
io.lsu_addr_d <= full_addr_d @[lsu_lsc_ctl.scala 243:28]
|
||||
node _T_187 = or(io.lsu_pkt_r.bits.store, io.lsu_pkt_r.bits.load) @[lsu_lsc_ctl.scala 245:68]
|
||||
node _T_188 = and(io.lsu_pkt_r.valid, _T_187) @[lsu_lsc_ctl.scala 245:41]
|
||||
node _T_189 = eq(io.flush_r, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:96]
|
||||
node _T_190 = and(_T_188, _T_189) @[lsu_lsc_ctl.scala 245:94]
|
||||
node _T_191 = eq(io.lsu_pkt_r.bits.dma, UInt<1>("h00")) @[lsu_lsc_ctl.scala 245:110]
|
||||
node _T_192 = and(_T_190, _T_191) @[lsu_lsc_ctl.scala 245:108]
|
||||
io.lsu_commit_r <= _T_192 @[lsu_lsc_ctl.scala 245:19]
|
||||
node _T_193 = bits(io.picm_mask_data_m, 31, 0) @[lsu_lsc_ctl.scala 246:52]
|
||||
node _T_194 = eq(io.addr_in_pic_m, UInt<1>("h00")) @[lsu_lsc_ctl.scala 246:69]
|
||||
node _T_195 = bits(_T_194, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_196 = mux(_T_195, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_197 = or(_T_193, _T_196) @[lsu_lsc_ctl.scala 246:59]
|
||||
node _T_198 = bits(io.lsu_pkt_m.bits.store_data_bypass_m, 0, 0) @[lsu_lsc_ctl.scala 246:133]
|
||||
node _T_199 = mux(_T_198, io.lsu_exu.lsu_result_m, store_data_pre_m) @[lsu_lsc_ctl.scala 246:94]
|
||||
node _T_200 = and(_T_197, _T_199) @[lsu_lsc_ctl.scala 246:89]
|
||||
io.store_data_m <= _T_200 @[lsu_lsc_ctl.scala 246:29]
|
||||
node _T_201 = mux(io.addr_external_m, io.bus_read_data_m, io.lsu_ld_data_m) @[lsu_lsc_ctl.scala 267:33]
|
||||
lsu_ld_datafn_m <= _T_201 @[lsu_lsc_ctl.scala 267:27]
|
||||
node _T_202 = eq(addr_external_r, UInt<1>("h01")) @[lsu_lsc_ctl.scala 268:49]
|
||||
node _T_203 = mux(_T_202, bus_read_data_r, io.lsu_ld_data_corr_r) @[lsu_lsc_ctl.scala 268:33]
|
||||
lsu_ld_datafn_corr_r <= _T_203 @[lsu_lsc_ctl.scala 268:27]
|
||||
node _T_204 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 269:74]
|
||||
node _T_205 = bits(_T_204, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_206 = mux(_T_205, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_207 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 269:133]
|
||||
node _T_208 = cat(UInt<24>("h00"), _T_207) @[Cat.scala 29:58]
|
||||
node _T_209 = and(_T_206, _T_208) @[lsu_lsc_ctl.scala 269:102]
|
||||
node _T_210 = and(io.lsu_pkt_m.bits.unsign, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 270:43]
|
||||
node _T_211 = bits(_T_210, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_212 = mux(_T_211, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_213 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 270:102]
|
||||
node _T_214 = cat(UInt<16>("h00"), _T_213) @[Cat.scala 29:58]
|
||||
node _T_215 = and(_T_212, _T_214) @[lsu_lsc_ctl.scala 270:71]
|
||||
node _T_216 = or(_T_209, _T_215) @[lsu_lsc_ctl.scala 269:141]
|
||||
node _T_217 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 271:17]
|
||||
node _T_218 = and(_T_217, io.lsu_pkt_m.bits.by) @[lsu_lsc_ctl.scala 271:43]
|
||||
node _T_219 = bits(_T_218, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_220 = mux(_T_219, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_221 = bits(lsu_ld_datafn_m, 7, 7) @[lsu_lsc_ctl.scala 271:102]
|
||||
node _T_222 = bits(_T_221, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_223 = mux(_T_222, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_224 = bits(lsu_ld_datafn_m, 7, 0) @[lsu_lsc_ctl.scala 271:125]
|
||||
node _T_225 = cat(_T_223, _T_224) @[Cat.scala 29:58]
|
||||
node _T_226 = and(_T_220, _T_225) @[lsu_lsc_ctl.scala 271:71]
|
||||
node _T_227 = or(_T_216, _T_226) @[lsu_lsc_ctl.scala 270:114]
|
||||
node _T_228 = eq(io.lsu_pkt_m.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 272:17]
|
||||
node _T_229 = and(_T_228, io.lsu_pkt_m.bits.half) @[lsu_lsc_ctl.scala 272:43]
|
||||
node _T_230 = bits(_T_229, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_231 = mux(_T_230, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_232 = bits(lsu_ld_datafn_m, 15, 15) @[lsu_lsc_ctl.scala 272:101]
|
||||
node _T_233 = bits(_T_232, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_234 = mux(_T_233, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_235 = bits(lsu_ld_datafn_m, 15, 0) @[lsu_lsc_ctl.scala 272:125]
|
||||
node _T_236 = cat(_T_234, _T_235) @[Cat.scala 29:58]
|
||||
node _T_237 = and(_T_231, _T_236) @[lsu_lsc_ctl.scala 272:71]
|
||||
node _T_238 = or(_T_227, _T_237) @[lsu_lsc_ctl.scala 271:134]
|
||||
node _T_239 = bits(io.lsu_pkt_m.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_240 = mux(_T_239, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_241 = bits(lsu_ld_datafn_m, 31, 0) @[lsu_lsc_ctl.scala 273:60]
|
||||
node _T_242 = and(_T_240, _T_241) @[lsu_lsc_ctl.scala 273:43]
|
||||
node _T_243 = or(_T_238, _T_242) @[lsu_lsc_ctl.scala 272:134]
|
||||
io.lsu_exu.lsu_result_m <= _T_243 @[lsu_lsc_ctl.scala 269:35]
|
||||
node _T_244 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 274:66]
|
||||
node _T_245 = bits(_T_244, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_246 = mux(_T_245, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_247 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 274:130]
|
||||
node _T_248 = cat(UInt<24>("h00"), _T_247) @[Cat.scala 29:58]
|
||||
node _T_249 = and(_T_246, _T_248) @[lsu_lsc_ctl.scala 274:94]
|
||||
node _T_250 = and(io.lsu_pkt_r.bits.unsign, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 275:43]
|
||||
node _T_251 = bits(_T_250, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_252 = mux(_T_251, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_253 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 275:107]
|
||||
node _T_254 = cat(UInt<16>("h00"), _T_253) @[Cat.scala 29:58]
|
||||
node _T_255 = and(_T_252, _T_254) @[lsu_lsc_ctl.scala 275:71]
|
||||
node _T_256 = or(_T_249, _T_255) @[lsu_lsc_ctl.scala 274:138]
|
||||
node _T_257 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 276:17]
|
||||
node _T_258 = and(_T_257, io.lsu_pkt_r.bits.by) @[lsu_lsc_ctl.scala 276:43]
|
||||
node _T_259 = bits(_T_258, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_260 = mux(_T_259, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_261 = bits(lsu_ld_datafn_corr_r, 7, 7) @[lsu_lsc_ctl.scala 276:107]
|
||||
node _T_262 = bits(_T_261, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_263 = mux(_T_262, UInt<24>("h0ffffff"), UInt<24>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_264 = bits(lsu_ld_datafn_corr_r, 7, 0) @[lsu_lsc_ctl.scala 276:135]
|
||||
node _T_265 = cat(_T_263, _T_264) @[Cat.scala 29:58]
|
||||
node _T_266 = and(_T_260, _T_265) @[lsu_lsc_ctl.scala 276:71]
|
||||
node _T_267 = or(_T_256, _T_266) @[lsu_lsc_ctl.scala 275:119]
|
||||
node _T_268 = eq(io.lsu_pkt_r.bits.unsign, UInt<1>("h00")) @[lsu_lsc_ctl.scala 277:17]
|
||||
node _T_269 = and(_T_268, io.lsu_pkt_r.bits.half) @[lsu_lsc_ctl.scala 277:43]
|
||||
node _T_270 = bits(_T_269, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_271 = mux(_T_270, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_272 = bits(lsu_ld_datafn_corr_r, 15, 15) @[lsu_lsc_ctl.scala 277:106]
|
||||
node _T_273 = bits(_T_272, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_274 = mux(_T_273, UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_275 = bits(lsu_ld_datafn_corr_r, 15, 0) @[lsu_lsc_ctl.scala 277:135]
|
||||
node _T_276 = cat(_T_274, _T_275) @[Cat.scala 29:58]
|
||||
node _T_277 = and(_T_271, _T_276) @[lsu_lsc_ctl.scala 277:71]
|
||||
node _T_278 = or(_T_267, _T_277) @[lsu_lsc_ctl.scala 276:144]
|
||||
node _T_279 = bits(io.lsu_pkt_r.bits.word, 0, 0) @[Bitwise.scala 72:15]
|
||||
node _T_280 = mux(_T_279, UInt<32>("h0ffffffff"), UInt<32>("h00")) @[Bitwise.scala 72:12]
|
||||
node _T_281 = bits(lsu_ld_datafn_corr_r, 31, 0) @[lsu_lsc_ctl.scala 278:65]
|
||||
node _T_282 = and(_T_280, _T_281) @[lsu_lsc_ctl.scala 278:43]
|
||||
node _T_283 = or(_T_278, _T_282) @[lsu_lsc_ctl.scala 277:144]
|
||||
io.lsu_result_corr_r <= _T_283 @[lsu_lsc_ctl.scala 274:27]
|
||||
|
||||
1442
lsu_lsc_ctl.v
1442
lsu_lsc_ctl.v
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
|
|
@ -1,499 +1,395 @@
|
|||
//
|
||||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import include._
|
||||
//import dbg._
|
||||
//import scala.collection._
|
||||
//import lib._
|
||||
//
|
||||
//class dma_ctrl extends Module with lib with RequireAsyncReset {
|
||||
// val io = IO(new Bundle {
|
||||
// val free_clk = Input(Clock())
|
||||
// val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
||||
// val clk_override = Input(Bool())
|
||||
// val scan_mode = Input(Bool())
|
||||
// val dbg_cmd_size = Input(UInt(2.W)) // size of the abstract mem access debug command
|
||||
// val dma_dbg_rddata = Output(UInt(32.W))
|
||||
// val dma_dbg_cmd_done = Output(Bool())
|
||||
// val dma_dbg_cmd_fail = Output(Bool())
|
||||
// val dbg_dma = new dec_dbg()
|
||||
// val dbg_dma_io = new dbg_dma()
|
||||
// val dec_dma = Flipped(new dec_dma())
|
||||
// val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read
|
||||
// val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read
|
||||
// val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req
|
||||
// val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read
|
||||
// val iccm_ready = Input(Bool()) // iccm ready to accept DMA request
|
||||
// // AXI Write Channels
|
||||
// val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
// val lsu_dma = Flipped(new lsu_dma)
|
||||
// val ifu_dma = Flipped(new ifu_dma)
|
||||
// })
|
||||
//
|
||||
//
|
||||
// val DEPTH_PTR = log2Ceil(DMA_BUF_DEPTH)
|
||||
//
|
||||
// val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
//
|
||||
// val fifo_error_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_addr = Wire(Vec(DMA_BUF_DEPTH, UInt(32.W)))
|
||||
//
|
||||
// val fifo_sz = Wire(Vec(DMA_BUF_DEPTH,UInt(3.W)))
|
||||
//
|
||||
// val fifo_byteen = Wire(Vec(DMA_BUF_DEPTH,UInt(8.W)))
|
||||
//
|
||||
// val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
//
|
||||
// val fifo_tag = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_TAG.W)))
|
||||
//
|
||||
// val fifo_mid = Wire(Vec(DMA_BUF_DEPTH,UInt((DMA_BUS_ID:Int).W)))
|
||||
//
|
||||
// val fifo_prty = Wire(Vec(DMA_BUF_DEPTH,UInt(DMA_BUS_PRTY.W)))
|
||||
//
|
||||
// val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
|
||||
//
|
||||
// val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
//
|
||||
// val fifo_data_in = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))
|
||||
//
|
||||
// val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val WrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val RdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtRspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtWrPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val NxtRdPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
//
|
||||
// val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
|
||||
//
|
||||
// val dma_dbg_cmd_done_q = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_empty = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_address_error = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_alignment_error = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val num_fifo_vld = WireInit(UInt(4.W),0.U)
|
||||
//
|
||||
// val dma_mem_req = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_mem_addr_int = WireInit(UInt(32.W), 0.U)
|
||||
//
|
||||
// val dma_mem_sz_int = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val dma_mem_byteen = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// val dma_nack_count = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val dma_nack_count_csr = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val bus_rsp_valid = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_valid = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_write = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_posted_write = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W), 0.U)
|
||||
//
|
||||
// val bus_cmd_mid = WireInit(UInt((DMA_BUS_ID:Int).W), 0.U)
|
||||
//
|
||||
// val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W), 0.U)
|
||||
//
|
||||
// val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_full_spec_bus = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dbg_dma_bubble_bus = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_mstr_priority = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_mstr_sel = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val axi_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_valid = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_rpend = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_done_bus = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_posted_write = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val fifo_dbg = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
//
|
||||
// val wrbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val wrbuf_data_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val rdbuf_vld = WireInit(UInt(1.W), 0.U)
|
||||
//
|
||||
// val dma_free_clk = Wire(Clock())
|
||||
//
|
||||
// val dma_bus_clk = Wire(Clock())
|
||||
//
|
||||
// val dma_buffer_c1_clk = Wire(Clock())
|
||||
//
|
||||
// val fifo_byteen_in = WireInit(UInt(8.W), 0.U)
|
||||
//
|
||||
// //------------------------LOGIC STARTS HERE---------------------------------
|
||||
//
|
||||
//
|
||||
// // DCCM Address check
|
||||
//
|
||||
// val (dma_mem_addr_in_dccm,dma_mem_addr_in_dccm_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)
|
||||
//
|
||||
// // PIC memory address check
|
||||
//
|
||||
// val (dma_mem_addr_in_pic,dma_mem_addr_in_pic_region_nc) = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)
|
||||
//
|
||||
// // ICCM Address check
|
||||
//
|
||||
// val (dma_mem_addr_in_iccm,dma_mem_addr_in_iccm_region_nc) = if(ICCM_ENABLE) rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE) else (0.U,0.U)
|
||||
//
|
||||
// // FIFO inputs
|
||||
//
|
||||
// val fifo_addr_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_addr(31,0), bus_cmd_addr(31,0))
|
||||
//
|
||||
// fifo_byteen_in := Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, "h0f".U << (4.U * io.dbg_dma.dbg_ib.dbg_cmd_addr(2)), bus_cmd_byteen(7,0))
|
||||
//
|
||||
// val fifo_sz_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, Cat(0.U, io.dbg_cmd_size(1,0)), bus_cmd_sz(2,0))
|
||||
//
|
||||
// val fifo_write_in = Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid.asBool, io.dbg_dma.dbg_ib.dbg_cmd_write, bus_cmd_write)
|
||||
//
|
||||
// val fifo_posted_write_in = !io.dbg_dma.dbg_ib.dbg_cmd_valid & bus_cmd_posted_write
|
||||
//
|
||||
// val fifo_dbg_in = io.dbg_dma.dbg_ib.dbg_cmd_valid
|
||||
//
|
||||
//
|
||||
// fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_dma.dbg_ib.dbg_cmd_valid & io.dbg_dma.dbg_ib.dbg_cmd_type(1) & io.dbg_dma.dbg_ib.dbg_cmd_write)) & (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_data_in(i) := (Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_dma.dbg_ib.dbg_cmd_valid, Fill(2, io.dbg_dma.dbg_dctl.dbg_cmd_wrdata), bus_cmd_wdata(63,0)))))))
|
||||
//
|
||||
// fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
|
||||
//
|
||||
// fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_sz(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_byteen(i) := withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
|
||||
//
|
||||
// fifo_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_posted_write := (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// fifo_dbg := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_tag(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_mid(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// (0 until DMA_BUF_DEPTH).map(i => fifo_prty(i) := withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
|
||||
//
|
||||
// // Pointer logic
|
||||
//
|
||||
// NxtWrPtr := Mux((WrPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, WrPtr + 1.U)
|
||||
//
|
||||
// NxtRdPtr := Mux((RdPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RdPtr + 1.U)
|
||||
//
|
||||
// NxtRspPtr := Mux((RspPtr === (DMA_BUF_DEPTH - 1).U).asBool, 0.U, RspPtr + 1.U)
|
||||
//
|
||||
// val WrPtrEn = fifo_cmd_en.orR
|
||||
//
|
||||
// val RdPtrEn = (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req | (dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error))
|
||||
//
|
||||
// val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
||||
//
|
||||
// WrPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtWrPtr, 0.U, WrPtrEn)
|
||||
// }
|
||||
//
|
||||
// RdPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool)
|
||||
// }
|
||||
//
|
||||
// RspPtr := withClock(dma_free_clk) {
|
||||
// RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool)
|
||||
// }
|
||||
//
|
||||
// // Miscellaneous signal
|
||||
//
|
||||
// val fifo_full = fifo_full_spec_bus;
|
||||
//
|
||||
// val num_fifo_vld_tmp = WireInit(UInt(4.W),0.U)
|
||||
// val num_fifo_vld_tmp2 = WireInit(UInt(4.W),0.U)
|
||||
//
|
||||
// num_fifo_vld_tmp := (Cat(Fill(3, 0.U), bus_cmd_sent)) - (Cat(Fill(3, 0.U), bus_rsp_sent))
|
||||
//
|
||||
// num_fifo_vld_tmp2 := (0 until DMA_BUF_DEPTH).map(i => Cat(Fill(3,0.U), fifo_valid(i))).reduce(_+_)
|
||||
//
|
||||
// num_fifo_vld := num_fifo_vld_tmp + num_fifo_vld_tmp2
|
||||
//
|
||||
// val fifo_full_spec = (num_fifo_vld >= DMA_BUF_DEPTH.asUInt())
|
||||
//
|
||||
// val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
|
||||
//
|
||||
// // Error logic
|
||||
//
|
||||
// dma_address_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)).asUInt // request not for ICCM or DCCM
|
||||
// dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !dma_address_error &
|
||||
// (((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
|
||||
// ((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
||||
// ((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
||||
// (dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
||||
// (dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
||||
// (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
||||
// (dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
||||
// (dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
||||
// (dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)),
|
||||
// (dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)),
|
||||
// (dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)),
|
||||
// (dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)),
|
||||
// (dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store
|
||||
// (io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
||||
//
|
||||
//
|
||||
// //Dbg outputs
|
||||
//
|
||||
// io.dbg_dma_io.dma_dbg_ready := fifo_empty & dbg_dma_bubble_bus
|
||||
// io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
||||
// io.dma_dbg_rddata := Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63, 32), fifo_data(RspPtr)(31,0))
|
||||
// io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
||||
//
|
||||
// dma_dbg_cmd_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & fifo_dbg(RdPtr) & ((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)).asBool() | (dma_mem_sz_int(1, 0) =/= 2.U)) // Only word accesses allowed
|
||||
//
|
||||
// // Block the decode if fifo full
|
||||
//
|
||||
// io.dec_dma.tlu_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
||||
// io.ifu_dma.dma_ifc.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr);
|
||||
// io.dec_dma.tlu_dma.dma_iccm_stall_any := io.ifu_dma.dma_ifc.dma_iccm_stall_any
|
||||
// io.dec_dma.dctl_dma.dma_dccm_stall_any := io.dec_dma.tlu_dma.dma_dccm_stall_any
|
||||
// // Used to indicate ready to debug
|
||||
//
|
||||
// fifo_empty := ~(fifo_valid.orR)
|
||||
//
|
||||
// // Nack counter, stall the lsu pipe if 7 nacks
|
||||
//
|
||||
// dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty
|
||||
// val dma_nack_count_d = Mux(dma_nack_count >= dma_nack_count_csr, (Fill(3, !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)) & dma_nack_count(2,0)), Mux((dma_mem_req.asBool & !(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), dma_nack_count(2,0) + 1.U, 0.U))
|
||||
//
|
||||
// dma_nack_count := withClock(dma_free_clk) {
|
||||
// RegEnable(dma_nack_count_d(2,0), 0.U, dma_mem_req.asBool)
|
||||
// }
|
||||
//
|
||||
// // Core outputs
|
||||
//
|
||||
// dma_mem_req := fifo_valid(RdPtr) & !fifo_rpend(RdPtr) & !fifo_done(RdPtr) & !(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready
|
||||
// io.ifu_dma.dma_mem_ctl.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready;
|
||||
// io.lsu_dma.dma_mem_tag := RdPtr
|
||||
// dma_mem_addr_int := fifo_addr(RdPtr)
|
||||
// dma_mem_sz_int := fifo_sz(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_addr := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_byteen(7,0) === "hf0".U), Cat(dma_mem_addr_int(31, 3), 1.U, dma_mem_addr_int(1, 0)), dma_mem_addr_int(31,0))
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U)), 2.U, dma_mem_sz_int(2,0))
|
||||
// dma_mem_byteen := fifo_byteen(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
|
||||
// io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := fifo_data(RdPtr)
|
||||
//
|
||||
// // PMU outputs
|
||||
//
|
||||
// io.dec_dma.tlu_dma.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.dec_dma.tlu_dma.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
//
|
||||
// // Inputs
|
||||
//
|
||||
// fifo_full_spec_bus := withClock(dma_bus_clk) {
|
||||
// RegNext(fifo_full_spec, 0.U)
|
||||
// }
|
||||
//
|
||||
// dbg_dma_bubble_bus := withClock(dma_bus_clk) {
|
||||
// RegNext(io.dbg_dma_io.dbg_dma_bubble, 0.U)
|
||||
// }
|
||||
//
|
||||
// dma_dbg_cmd_done_q := withClock(io.free_clk) {
|
||||
// RegNext(io.dma_dbg_cmd_done, 0.U)
|
||||
// }
|
||||
//
|
||||
// // Clock Gating logic
|
||||
//
|
||||
// val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||
// val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||
//
|
||||
// dma_buffer_c1_clk := rvclkhdr(clock,dma_buffer_c1_clken.asBool,io.scan_mode)
|
||||
// dma_free_clk := rvclkhdr(clock,dma_free_clken.asBool(),io.scan_mode)
|
||||
// dma_bus_clk := rvclkhdr(clock,io.dma_bus_clk_en,io.scan_mode)
|
||||
//
|
||||
//
|
||||
// // Write channel buffer
|
||||
//
|
||||
// val wrbuf_en = io.dma_axi.aw.valid & io.dma_axi.aw.ready
|
||||
// val wrbuf_data_en = io.dma_axi.w.valid & io.dma_axi.w.ready
|
||||
// val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
||||
// val wrbuf_rst = wrbuf_cmd_sent.asBool & !wrbuf_en
|
||||
// val wrbuf_data_rst = wrbuf_cmd_sent.asBool & !wrbuf_data_en
|
||||
//
|
||||
// wrbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_en, 1.U, wrbuf_vld) & !wrbuf_rst, 0.U)}
|
||||
//
|
||||
// wrbuf_data_vld := withClock(dma_bus_clk) {RegNext(Mux(wrbuf_data_en, 1.U, wrbuf_data_vld) & !wrbuf_data_rst, 0.U)}
|
||||
//
|
||||
// val wrbuf_tag = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.aw.bits.id, 0.U, wrbuf_en)
|
||||
// }
|
||||
//
|
||||
// val wrbuf_sz = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.aw.bits.size, 0.U, wrbuf_en)
|
||||
// }
|
||||
//
|
||||
// val wrbuf_addr = rvdffe(io.dma_axi.aw.bits.addr, wrbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// val wrbuf_data = rvdffe(io.dma_axi.w.bits.data, wrbuf_data_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// val wrbuf_byteen = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.w.bits.strb, 0.U, wrbuf_data_en)
|
||||
// }
|
||||
//
|
||||
// // Read channel buffer
|
||||
//
|
||||
// val rdbuf_en = io.dma_axi.ar.valid & io.dma_axi.ar.ready
|
||||
// val rdbuf_cmd_sent = bus_cmd_sent & !bus_cmd_write
|
||||
// val rdbuf_rst = rdbuf_cmd_sent.asBool & !rdbuf_en
|
||||
//
|
||||
// rdbuf_vld := withClock(dma_bus_clk) {RegNext(Mux(rdbuf_en, 1.U, rdbuf_vld) & !rdbuf_rst, 0.U)}
|
||||
//
|
||||
// val rdbuf_tag = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.ar.bits.id, 0.U, rdbuf_en)
|
||||
// }
|
||||
//
|
||||
// val rdbuf_sz = withClock(dma_bus_clk) {
|
||||
// RegEnable(io.dma_axi.ar.bits.size, 0.U, rdbuf_en)
|
||||
// }
|
||||
//
|
||||
// val rdbuf_addr = rvdffe(io.dma_axi.ar.bits.addr, rdbuf_en & io.dma_bus_clk_en, clock, io.scan_mode)
|
||||
//
|
||||
// io.dma_axi.aw.ready := ~(wrbuf_vld & !wrbuf_cmd_sent)
|
||||
// io.dma_axi.w.ready := ~(wrbuf_data_vld & !wrbuf_cmd_sent)
|
||||
// io.dma_axi.ar.ready := ~(rdbuf_vld & !rdbuf_cmd_sent)
|
||||
//
|
||||
// //Generate a single request from read/write channel
|
||||
//
|
||||
// bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
|
||||
// bus_cmd_sent := bus_cmd_valid & dma_fifo_ready.asUInt
|
||||
// bus_cmd_write := axi_mstr_sel
|
||||
// bus_cmd_posted_write := 0.U;
|
||||
// bus_cmd_addr := Mux(axi_mstr_sel.asBool, wrbuf_addr, rdbuf_addr)
|
||||
// bus_cmd_sz := Mux(axi_mstr_sel.asBool, wrbuf_sz, rdbuf_sz)
|
||||
// bus_cmd_wdata := wrbuf_data
|
||||
// bus_cmd_byteen := wrbuf_byteen
|
||||
// bus_cmd_tag := Mux(axi_mstr_sel.asBool, wrbuf_tag, rdbuf_tag)
|
||||
// bus_cmd_mid := 0.U
|
||||
// bus_cmd_prty := 0.U
|
||||
//
|
||||
// // Sel=1 -> write has higher priority
|
||||
//
|
||||
// axi_mstr_sel := Mux((wrbuf_vld & wrbuf_data_vld & rdbuf_vld) === 1.U, axi_mstr_priority, wrbuf_vld & wrbuf_data_vld)
|
||||
// val axi_mstr_prty_in = ~axi_mstr_priority
|
||||
// val axi_mstr_prty_en = bus_cmd_sent
|
||||
//
|
||||
// axi_mstr_priority := withClock(dma_bus_clk) {
|
||||
// RegEnable(axi_mstr_prty_in, 0.U, axi_mstr_prty_en.asBool)
|
||||
// }
|
||||
//
|
||||
// val axi_rsp_valid = fifo_valid(RspPtr) & !fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
|
||||
// val axi_rsp_rdata = fifo_data(RspPtr)
|
||||
// val axi_rsp_write = fifo_write(RspPtr)
|
||||
// val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U, Mux(fifo_error(RspPtr)(1), 3.U, 0.U));
|
||||
//
|
||||
// val axi_rsp_tag = fifo_tag(RspPtr)
|
||||
//
|
||||
// // AXI response channel signals
|
||||
//
|
||||
// io.dma_axi.b.valid := axi_rsp_valid & axi_rsp_write
|
||||
// io.dma_axi.b.bits.resp := axi_rsp_error(1,0)
|
||||
// io.dma_axi.b.bits.id := axi_rsp_tag
|
||||
//
|
||||
// io.dma_axi.r.valid := axi_rsp_valid & !axi_rsp_write
|
||||
// io.dma_axi.r.bits.resp := axi_rsp_error
|
||||
// io.dma_axi.r.bits.data := axi_rsp_rdata(63,0)
|
||||
// io.dma_axi.r.bits.last := 1.U
|
||||
// io.dma_axi.r.bits.id := axi_rsp_tag
|
||||
//
|
||||
// bus_posted_write_done := 0.U
|
||||
// bus_rsp_valid := (io.dma_axi.b.valid | io.dma_axi.r.valid)
|
||||
// bus_rsp_sent := ((io.dma_axi.b.valid & io.dma_axi.b.ready) | (io.dma_axi.r.valid & io.dma_axi.r.ready))
|
||||
// io.lsu_dma.dma_dccm_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
// io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_sz := io.lsu_dma.dma_lsc_ctl.dma_mem_sz
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_addr := io.lsu_dma.dma_lsc_ctl.dma_mem_addr
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_wdata := io.lsu_dma.dma_lsc_ctl.dma_mem_wdata
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
// io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
//}
|
||||
//
|
||||
//
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import include._
|
||||
import dbg._
|
||||
import scala.collection._
|
||||
import lib._
|
||||
|
||||
class dma_ctrl extends Module with lib with RequireAsyncReset {
|
||||
val io = IO(new Bundle {
|
||||
val free_clk = Input(Clock())
|
||||
val dma_bus_clk_en = Input(Bool()) // slave bus clock enable
|
||||
val clk_override = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
val dbg_cmd_size = Input(UInt(2.W))
|
||||
|
||||
val dma_dbg_cmd_done = Output(Bool())
|
||||
val dma_dbg_cmd_fail = Output(Bool())
|
||||
val dma_dbg_rddata = Output(UInt(32.W))
|
||||
val iccm_dma_rvalid = Input(Bool())
|
||||
val iccm_dma_ecc_error = Input(Bool())
|
||||
val iccm_dma_rtag = Input(UInt(3.W))
|
||||
val iccm_dma_rdata = Input(UInt(64.W))
|
||||
val dma_active = Output(Bool())
|
||||
val iccm_ready = Input(Bool())
|
||||
|
||||
val dbg_dec_dma = new dec_dbg()
|
||||
val dbg_dma = new dbg_dma()
|
||||
val dec_dma = Flipped(new dec_dma())
|
||||
val lsu_dma = Flipped(new lsu_dma)
|
||||
val ifu_dma = Flipped(new ifu_dma)// AXI Write Channel
|
||||
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
|
||||
|
||||
})
|
||||
|
||||
val DEPTH = DMA_BUF_DEPTH
|
||||
|
||||
val DEPTH_PTR = log2Ceil(DEPTH)
|
||||
|
||||
val NACK_COUNT = 7
|
||||
|
||||
val dma_dbg_mem_wrdata = WireInit(UInt(32.W), 0.U)
|
||||
val bus_cmd_addr = WireInit(UInt(32.W), 0.U)
|
||||
val bus_cmd_byteen = WireInit(UInt(8.W), 0.U)
|
||||
val bus_cmd_sz = WireInit(UInt(3.W), 0.U)
|
||||
val bus_cmd_write = WireInit(Bool(), false.B)
|
||||
val bus_cmd_posted_write = WireInit(Bool(), false.B)
|
||||
// Clock Gating logic
|
||||
val bus_cmd_valid = WireInit(Bool(),0.B)
|
||||
val bus_rsp_valid = WireInit(Bool(),0.B)
|
||||
val dma_dbg_cmd_done_q = WireInit(Bool(),0.B)
|
||||
val fifo_valid = WireInit(UInt(DEPTH.W),0.U)
|
||||
val dma_buffer_c1_clken = (bus_cmd_valid & io.dma_bus_clk_en) | io.dbg_dec_dma.dbg_ib.dbg_cmd_valid | io.clk_override
|
||||
val dma_free_clken = (bus_cmd_valid | bus_rsp_valid | io.dbg_dec_dma.dbg_ib.dbg_cmd_valid | io.dma_dbg_cmd_done | dma_dbg_cmd_done_q | (fifo_valid.orR) | io.clk_override)
|
||||
|
||||
val dma_buffer_c1_clk = rvoclkhdr(clock,dma_buffer_c1_clken,io.scan_mode)
|
||||
val dma_free_clk = rvoclkhdr(clock,dma_free_clken,io.scan_mode)
|
||||
|
||||
val fifo_addr_in = Mux(io.dbg_dec_dma.dbg_ib.dbg_cmd_valid, io.dbg_dec_dma.dbg_ib.dbg_cmd_addr, bus_cmd_addr)
|
||||
val fifo_byteen_in = Fill(8,!io.dbg_dec_dma.dbg_ib.dbg_cmd_valid) & bus_cmd_byteen // Byte enable is used only for bus requests//Mux(io.dbg_cmd_valid, 0.U, bus_cmd_byteen)
|
||||
val fifo_sz_in = Mux(io.dbg_dec_dma.dbg_ib.dbg_cmd_valid, Cat(0.U,io.dbg_cmd_size), bus_cmd_sz)
|
||||
val fifo_write_in = Mux(io.dbg_dec_dma.dbg_ib.dbg_cmd_valid, io.dbg_dec_dma.dbg_ib.dbg_cmd_write, bus_cmd_write)
|
||||
val fifo_posted_write_in = !io.dbg_dec_dma.dbg_ib.dbg_cmd_valid & bus_cmd_posted_write
|
||||
val fifo_dbg_in = io.dbg_dec_dma.dbg_ib.dbg_cmd_valid
|
||||
val bus_cmd_sent = WireInit(Bool(), false.B)
|
||||
val WrPtr = WireInit(UInt(DEPTH_PTR.W), 0.U)
|
||||
val RdPtr = WireInit(UInt(DEPTH_PTR.W), 0.U)
|
||||
val dma_address_error = WireInit(Bool(), false.B)
|
||||
val dma_alignment_error = WireInit(Bool(), false.B)
|
||||
|
||||
// val fifo_cmd_en = (0 until DEPTH).map(i=>((bus_cmd_sent & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1))) & (WrPtr === i.U).asUInt()).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// val fifo_data_en = (0 until DEPTH).map(i => ((((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_cmd_valid & io.dbg_cmd_type(1) & io.dbg_cmd_write)) &
|
||||
// (i.U === WrPtr)) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr)) |
|
||||
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) |
|
||||
// (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// val fifo_pend_en = (0 until DEPTH).map(i => ((io.dma_dccm_req | io.dma_iccm_req) & !io.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
//
|
||||
// val dma_dbg_cmd_error = WireInit(Bool(), false.B)
|
||||
//
|
||||
// val fifo_error_en = (0 until DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) &
|
||||
// (i.U === RdPtr)) | ((io.dccm_dma_rvalid & io.dccm_dma_ecc_error) & (i.U === io.dccm_dma_rtag)) |
|
||||
// ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// val fifo_error_in = Wire(Vec(DEPTH, UInt(2.W)))
|
||||
// val fifo_error = Wire(Vec(DEPTH, UInt(2.W)))
|
||||
// val fifo_error_bus_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error_in(i).orR & fifo_error_en(i)) | fifo_error(i).orR) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
// val fifo_done_en = (0 until DMA_BUF_DEPTH).map(i=>(((fifo_error(i).orR | fifo_error_en(i) | ((io.dma_dccm_req | io.dma_iccm_req) & io.dma_mem_write)) & (i.U === RdPtr)) |
|
||||
// (io.dccm_dma_rvalid & (i.U === io.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
// val fifo_done = WireInit(UInt(DEPTH.W), 0.U)
|
||||
// val fifo_done_bus_en = (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
// val bus_rsp_sent = WireInit(Bool(), false.B)
|
||||
// val bus_posted_write_done = WireInit(Bool(), false.B)
|
||||
// val RspPtr = WireInit(UInt(DEPTH_PTR.W), 0.U)
|
||||
// val fifo_reset = (0 until DMA_BUF_DEPTH).map(i=>((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr)).asUInt()).reverse.reduce(Cat(_,_))
|
||||
// fifo_error_in := (0 until DMA_BUF_DEPTH).map(i=>Mux(io.dccm_dma_rvalid & (io.dccm_dma_rtag===i.U), Cat(0.U(1.W),io.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (io.iccm_dma_rtag===i.U), Cat(0.U(1.W),io.iccm_dma_ecc_error), Cat(dma_address_error | dma_alignment_error | dma_dbg_cmd_error, dma_alignment_error))))
|
||||
val fifo_cmd_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_data_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_pend_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_error_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_done_bus_en = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_reset = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
|
||||
val fifo_error_en = WireInit(UInt(DMA_BUF_DEPTH.W),0.U)
|
||||
val dma_dbg_cmd_error = WireInit(UInt(1.W),0.U)
|
||||
val fifo_error_in = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
val RspPtr = WireInit(UInt((log2Ceil(DMA_BUF_DEPTH)).W), 0.U)
|
||||
val bus_posted_write_done = WireInit(UInt(1.W), 0.U)
|
||||
val bus_rsp_sent = WireInit(UInt(1.W), 0.U)
|
||||
val fifo_error = Wire(Vec(DMA_BUF_DEPTH, UInt(2.W)))
|
||||
val fifo_done = WireInit(UInt(DMA_BUF_DEPTH.W), 0.U)
|
||||
fifo_cmd_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent.asBool & io.dma_bus_clk_en) | (io.dbg_dec_dma.dbg_ib.dbg_cmd_valid & io.dbg_dec_dma.dbg_ib.dbg_cmd_type(1).asBool)) & (i.U === WrPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_data_en := (0 until DMA_BUF_DEPTH).map(i => (((bus_cmd_sent & fifo_write_in & io.dma_bus_clk_en) | (io.dbg_dec_dma.dbg_ib.dbg_cmd_valid & io.dbg_dec_dma.dbg_ib.dbg_cmd_type(1) & io.dbg_dec_dma.dbg_ib.dbg_cmd_write)) & (i.U === WrPtr).asUInt()) | ((dma_address_error | dma_alignment_error) & (i.U === RdPtr).asUInt()) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag).asUInt()) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag).asUInt())).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_pend_en := (0 until DMA_BUF_DEPTH).map(i => ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & !io.lsu_dma.dma_lsc_ctl.dma_mem_write & (i.U === RdPtr)).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_error_en := (0 until DMA_BUF_DEPTH).map(i => (((dma_address_error.asBool | dma_alignment_error.asBool | dma_dbg_cmd_error) & (i.U === RdPtr)) | ((io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error) & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | ((io.iccm_dma_rvalid & io.iccm_dma_ecc_error) & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_error_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((((fifo_error_in(i)(1,0).orR) & fifo_error_en(i)) | (fifo_error(i).orR)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done_en := (0 until DMA_BUF_DEPTH).map(i => (((fifo_error(i).orR | fifo_error_en(i) | ((io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write)) & (i.U === RdPtr)) | (io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag)) | (io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag))).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_done_bus_en := (0 until DMA_BUF_DEPTH).map(i => ((fifo_done_en(i) | fifo_done(i)) & io.dma_bus_clk_en).asUInt).reverse.reduce(Cat(_,_))
|
||||
|
||||
fifo_reset := (0 until DMA_BUF_DEPTH).map(i => ((((bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en) | io.dma_dbg_cmd_done) & (i.U === RspPtr))).reverse.reduce(Cat(_,_))
|
||||
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_error_in(i) := (Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), Cat(0.U, io.lsu_dma.dma_dccm_ctl.dccm_dma_ecc_error), Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), (Cat(0.U, io.iccm_dma_ecc_error)), (Cat((dma_address_error | dma_alignment_error | dma_dbg_cmd_error), dma_alignment_error))))))
|
||||
|
||||
val fifo_addr = Wire(Vec(DEPTH,UInt(32.W)))
|
||||
val bus_cmd_wdata = WireInit(UInt(64.W), 0.U)
|
||||
val fifo_data_in = VecInit.tabulate(DMA_BUF_DEPTH)(i =>(Mux(fifo_error_en(i) & (fifo_error_in(i).orR), Cat(Fill(32, 0.U), fifo_addr(i)), Mux(io.lsu_dma.dma_dccm_ctl.dccm_dma_rvalid & (i.U === io.lsu_dma.dma_dccm_ctl.dccm_dma_rtag), io.lsu_dma.dma_dccm_ctl.dccm_dma_rdata, Mux(io.iccm_dma_rvalid & (i.U === io.iccm_dma_rtag), io.iccm_dma_rdata, Mux(io.dbg_dec_dma.dbg_ib.dbg_cmd_valid, Fill(2, dma_dbg_mem_wrdata), bus_cmd_wdata(63,0)))))))
|
||||
|
||||
fifo_valid := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_cmd_en(i), 1.U, fifo_valid(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_error(i) := withClock(dma_free_clk) {RegNext(Mux(fifo_error_en(i).asBool(),fifo_error_in(i) , fifo_error(i)) & Fill(fifo_error_in(i).getWidth , !fifo_reset(i)), 0.U)})
|
||||
val fifo_error_bus = WireInit(UInt(DEPTH.W), 0.U)
|
||||
val fifo_rpend = WireInit(UInt(DEPTH.W), 0.U)
|
||||
fifo_error_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_error_bus_en(i), 1.U, fifo_error_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
fifo_rpend := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_pend_en(i), 1.U, fifo_rpend(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
fifo_done := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_en(i), 1.U, fifo_done(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
val fifo_done_bus = WireInit(UInt(DEPTH.W), 0.U)
|
||||
fifo_done_bus := (0 until DMA_BUF_DEPTH).map(i => withClock(dma_free_clk) {RegNext(Mux(fifo_done_bus_en(i), 1.U, fifo_done_bus(i)) & !fifo_reset(i), 0.U)}).reverse.reduce(Cat(_,_))
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_addr(i) := rvdffe(fifo_addr_in, fifo_cmd_en(i), clock, io.scan_mode))
|
||||
val fifo_sz = VecInit.tabulate(DMA_BUF_DEPTH)(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_sz_in(2,0), 0.U, fifo_cmd_en(i))})
|
||||
val fifo_byteen = VecInit.tabulate(DMA_BUF_DEPTH)(i =>withClock(dma_buffer_c1_clk) {RegEnable(fifo_byteen_in(7,0), 0.U, fifo_cmd_en(i).asBool())})
|
||||
val fifo_write = (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
val fifo_posted_write = (0 until DMA_BUF_DEPTH).map(i => (withClock(dma_buffer_c1_clk) {RegEnable(fifo_posted_write_in, 0.U, fifo_cmd_en(i))})).reverse.reduce(Cat(_,_))
|
||||
val fifo_dbg = (0 until DMA_BUF_DEPTH).map(i => withClock(dma_buffer_c1_clk) {RegEnable(fifo_dbg_in, 0.U, fifo_cmd_en(i))}).reverse.reduce(Cat(_,_))
|
||||
|
||||
val fifo_data = Wire(Vec(DMA_BUF_DEPTH,UInt(64.W)))//VecInit.tabulate(DMA_BUF_DEPTH)(i =>rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
|
||||
(0 until DMA_BUF_DEPTH).map(i => fifo_data(i) := rvdffe(fifo_data_in(i), fifo_data_en(i), clock, io.scan_mode))
|
||||
val bus_cmd_tag = WireInit(UInt(DMA_BUS_TAG.W),0.U)
|
||||
val bus_cmd_mid = WireInit(UInt(DMA_BUS_ID.W),0.U)
|
||||
val bus_cmd_prty = WireInit(UInt(DMA_BUS_PRTY.W),0.U)
|
||||
val fifo_tag = VecInit.tabulate(DMA_BUF_DEPTH)(i =>withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_tag, 0.U, fifo_cmd_en(i))})
|
||||
val fifo_mid = VecInit.tabulate(DMA_BUF_DEPTH)(i =>withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_mid, 0.U, fifo_cmd_en(i))})
|
||||
val fifo_prty = VecInit.tabulate(DMA_BUF_DEPTH)(i =>withClock(dma_buffer_c1_clk) {RegEnable(bus_cmd_prty, 0.U, fifo_cmd_en(i))})
|
||||
|
||||
// Pointer logic
|
||||
|
||||
val NxtWrPtr = Mux((WrPtr === (DEPTH-1).U), 0.U, WrPtr+ 1.U)
|
||||
val NxtRdPtr = Mux((RdPtr === (DEPTH-1).U), 0.U, RdPtr+ 1.U)
|
||||
val NxtRspPtr = Mux((RspPtr === (DEPTH-1).U), 0.U, RspPtr + 1.U)
|
||||
|
||||
val WrPtrEn = fifo_cmd_en.orR
|
||||
val RdPtrEn = io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req | (dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||
val RspPtrEn = (io.dma_dbg_cmd_done | (bus_rsp_sent | bus_posted_write_done) & io.dma_bus_clk_en)
|
||||
|
||||
|
||||
WrPtr := withClock(dma_free_clk) { RegEnable(NxtWrPtr, 0.U, WrPtrEn) }
|
||||
RdPtr := withClock(dma_free_clk) { RegEnable(NxtRdPtr, 0.U, RdPtrEn.asBool) }
|
||||
RspPtr := withClock(dma_free_clk) { RegEnable(NxtRspPtr, 0.U, RspPtrEn.asBool) }
|
||||
// Miscellaneous signals
|
||||
val fifo_full_spec_bus = WireInit(Bool(),0.B)
|
||||
val fifo_full = fifo_full_spec_bus
|
||||
|
||||
val num_fifo_vld = Wire(Vec(DEPTH+1,UInt(4.W)))
|
||||
val dbg_dma_bubble_bus = WireInit(Bool(),0.B)
|
||||
num_fifo_vld(0) := Cat(0.U(3.W),bus_cmd_sent) - Cat(0.U(3.W),bus_rsp_sent)
|
||||
for (i <- 1 to DEPTH) { num_fifo_vld(i):= num_fifo_vld(i-1) + Cat(0.U(3.W),fifo_valid(i-1))}
|
||||
val fifo_full_spec = (num_fifo_vld(DEPTH) >= DEPTH.U)
|
||||
val dma_fifo_ready = ~(fifo_full | dbg_dma_bubble_bus)
|
||||
|
||||
// Error logic
|
||||
val dma_mem_addr_in_dccm = WireInit(Bool(),0.B)
|
||||
val dma_mem_addr_in_iccm = WireInit(Bool(),0.B)
|
||||
val dma_mem_sz_int = WireInit(UInt(3.W),0.U)
|
||||
val dma_mem_addr_int = WireInit(UInt(32.W),0.U)
|
||||
val dma_mem_byteen = WireInit(UInt(8.W),0.U)
|
||||
dma_address_error := fifo_valid(RdPtr) & ~fifo_done(RdPtr) & ~fifo_dbg(RdPtr) & (~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm)) // request not for ICCM or DCCM
|
||||
|
||||
dma_alignment_error := fifo_valid(RdPtr) & !fifo_done(RdPtr) & !fifo_dbg(RdPtr) & !dma_address_error &
|
||||
(((dma_mem_sz_int(2,0) === 1.U) & dma_mem_addr_int(0)) | // HW size but unaligned
|
||||
((dma_mem_sz_int(2,0) === 2.U) & (dma_mem_addr_int(1, 0).orR)) | // W size but unaligned
|
||||
((dma_mem_sz_int(2,0) === 3.U) & (dma_mem_addr_int(2, 0).orR)) | // DW size but unaligned
|
||||
(dma_mem_addr_in_iccm & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt ) | // ICCM access not word size
|
||||
(dma_mem_addr_in_dccm & io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~((dma_mem_sz_int(1, 0) === 2.U) | (dma_mem_sz_int(1, 0) === 3.U)).asUInt) | // DCCM write not word size
|
||||
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 2.U) & (Mux1H(Seq((dma_mem_addr_int(2,0) === 0.U) -> (dma_mem_byteen(3,0)),
|
||||
(dma_mem_addr_int(2,0) === 1.U) -> (dma_mem_byteen(4,1)),
|
||||
(dma_mem_addr_int(2,0) === 2.U) -> (dma_mem_byteen(5,2)),
|
||||
(dma_mem_addr_int(2,0) === 3.U) -> (dma_mem_byteen(6,3)),
|
||||
(dma_mem_addr_int(2,0) === 4.U) -> (dma_mem_byteen(7,4)),
|
||||
(dma_mem_addr_int(2,0) === 5.U) -> (dma_mem_byteen(7,5)),
|
||||
(dma_mem_addr_int(2,0) === 6.U) -> (dma_mem_byteen(7,6)),
|
||||
(dma_mem_addr_int(2,0) === 7.U) -> (dma_mem_byteen(7)))) =/= "hf".U)) | // Write byte enables not aligned for word store
|
||||
(io.lsu_dma.dma_lsc_ctl.dma_mem_write & (dma_mem_sz_int(2, 0) === 3.U) & !((dma_mem_byteen(7,0) === "h0f".U) | (dma_mem_byteen(7,0) === "hf0".U) | (dma_mem_byteen(7,0) === "hff".U)))) // Write byte enables not aligned for dword store
|
||||
// Used to indicate ready to debug
|
||||
val fifo_empty = ~(fifo_valid.orR | bus_cmd_sent)
|
||||
|
||||
//Dbg outputs
|
||||
io.dbg_dma.dma_dbg_ready := fifo_empty & io.dbg_dma.dbg_dma_bubble
|
||||
io.dma_dbg_cmd_done := (fifo_valid(RspPtr) & fifo_dbg(RspPtr) & fifo_done(RspPtr))
|
||||
io.dma_dbg_cmd_fail := fifo_error(RspPtr).orR
|
||||
|
||||
val dma_dbg_sz = fifo_sz(RspPtr)(1,0)
|
||||
val dma_dbg_addr = fifo_addr(RspPtr)(1,0)
|
||||
val dma_dbg_mem_rddata = Mux(fifo_addr(RspPtr)(2), fifo_data(RspPtr)(63,32) , fifo_data(RspPtr)(31,0))
|
||||
io.dma_dbg_rddata := Mux1H(Seq(
|
||||
(dma_dbg_sz(1,0) === "h0".U(2.W)) -> ((dma_dbg_mem_rddata >> ((8.U)*dma_dbg_addr(1,0))) & "hff".U) ,
|
||||
(dma_dbg_sz(1,0) === "h1".U(2.W)) -> ((dma_dbg_mem_rddata >> ((16.U)*dma_dbg_addr(1))) & "hffff".U) ,
|
||||
(dma_dbg_sz(1,0) === "h2".U(2.W)) -> dma_dbg_mem_rddata))
|
||||
|
||||
// PIC memory address check
|
||||
|
||||
val dma_mem_addr_in_pic = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)._1
|
||||
val dma_mem_addr_in_pic_region_nc = rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(PIC_BASE_ADDR).U,PIC_SIZE)._2
|
||||
|
||||
dma_dbg_cmd_error := fifo_valid(RdPtr) & ~fifo_done(RdPtr) & fifo_dbg(RdPtr) &
|
||||
((~(dma_mem_addr_in_dccm | dma_mem_addr_in_iccm | dma_mem_addr_in_pic)) | // Address outside of ICCM/DCCM/PIC
|
||||
((dma_mem_addr_in_iccm | dma_mem_addr_in_pic) & (dma_mem_sz_int(1,0) =/= 2.U))) // Only word accesses allowed for ICCM/PIC
|
||||
|
||||
dma_dbg_mem_wrdata := Mux1H(Seq(
|
||||
(io.dbg_cmd_size(1,0) === "h0".U(2.W)) -> Fill(4,io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata(7,0)) ,
|
||||
(io.dbg_cmd_size(1,0) === "h1".U(2.W)) -> Fill(2,io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata(15,0)),
|
||||
(io.dbg_cmd_size(1,0) === "h2".U(2.W)) -> io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata ))
|
||||
|
||||
// Block the decode if fifo full
|
||||
val dma_mem_req = WireInit(Bool(),0.B)
|
||||
val dma_nack_count = WireInit(UInt(3.W),0.U)
|
||||
val dma_nack_count_csr = WireInit(UInt(3.W),0.U)
|
||||
val dma_nack_count_d = WireInit(UInt(3.W),0.U)
|
||||
io.dec_dma.dctl_dma.dma_dccm_stall_any := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & (dma_nack_count >= dma_nack_count_csr)
|
||||
io.dec_dma.tlu_dma.dma_dccm_stall_any := io.dec_dma.dctl_dma.dma_dccm_stall_any
|
||||
io.dec_dma.tlu_dma.dma_iccm_stall_any := dma_mem_req & dma_mem_addr_in_iccm & (dma_nack_count >= dma_nack_count_csr)
|
||||
io.ifu_dma.dma_ifc.dma_iccm_stall_any := io.dec_dma.tlu_dma.dma_iccm_stall_any
|
||||
// Nack counter, stall the lsu pipe if 7 nacks
|
||||
dma_nack_count_csr := io.dec_dma.tlu_dma.dec_tlu_dma_qos_prty
|
||||
dma_nack_count_d := Mux((dma_nack_count >= dma_nack_count_csr), (Fill(3,(!(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req))) & dma_nack_count),
|
||||
Mux((dma_mem_req & ~(io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req)), (dma_nack_count + 1.U), 0.U(3.W)))
|
||||
dma_nack_count := withClock(dma_free_clk){RegEnable(dma_nack_count_d,0.U,dma_mem_req)}
|
||||
|
||||
|
||||
// Core outputs
|
||||
dma_mem_req := fifo_valid(RdPtr) & ~fifo_rpend(RdPtr) & ~fifo_done(RdPtr) & ~(dma_address_error | dma_alignment_error | dma_dbg_cmd_error)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_dccm_req := dma_mem_req & (dma_mem_addr_in_dccm | dma_mem_addr_in_pic) & io.lsu_dma.dccm_ready
|
||||
io.ifu_dma.dma_mem_ctl.dma_iccm_req := dma_mem_req & dma_mem_addr_in_iccm & io.iccm_ready
|
||||
io.lsu_dma.dma_mem_tag := RdPtr
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_tag := io.lsu_dma.dma_mem_tag
|
||||
dma_mem_addr_int := fifo_addr(RdPtr)
|
||||
dma_mem_sz_int := fifo_sz(RdPtr)
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_addr := Mux((io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~fifo_dbg(RdPtr) & (dma_mem_byteen === "hf0".U(8.W))), Cat(dma_mem_addr_int(31,3),1.U,dma_mem_addr_int(1,0)), dma_mem_addr_int)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_addr := io.lsu_dma.dma_dccm_ctl.dma_mem_addr
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_addr := io.lsu_dma.dma_dccm_ctl.dma_mem_addr
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_sz := Mux(io.lsu_dma.dma_lsc_ctl.dma_mem_write & ~fifo_dbg(RdPtr) & ((dma_mem_byteen === "h0f".U(8.W)) | (dma_mem_byteen === "hf0".U(8.W))), 2.U(3.W), dma_mem_sz_int)
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_sz := io.lsu_dma.dma_lsc_ctl.dma_mem_sz
|
||||
dma_mem_byteen := fifo_byteen(RdPtr)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_write := fifo_write(RdPtr)
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_write := io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.lsu_dma.dma_dccm_ctl.dma_mem_wdata := fifo_data(RdPtr)
|
||||
io.lsu_dma.dma_lsc_ctl.dma_mem_wdata := io.lsu_dma.dma_dccm_ctl.dma_mem_wdata
|
||||
io.ifu_dma.dma_mem_ctl.dma_mem_wdata := io.lsu_dma.dma_dccm_ctl.dma_mem_wdata
|
||||
|
||||
// PMU outputs
|
||||
io.dec_dma.tlu_dma.dma_pmu_dccm_read := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & ~io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_dccm_write := io.lsu_dma.dma_lsc_ctl.dma_dccm_req & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_any_read := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & ~io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
io.dec_dma.tlu_dma.dma_pmu_any_write := (io.lsu_dma.dma_lsc_ctl.dma_dccm_req | io.ifu_dma.dma_mem_ctl.dma_iccm_req) & io.lsu_dma.dma_lsc_ctl.dma_mem_write
|
||||
|
||||
// Address check dccm
|
||||
val dma_mem_addr_in_dccm_region_nc = WireInit(Bool(),0.B)
|
||||
if (DCCM_ENABLE){
|
||||
dma_mem_addr_in_dccm := rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)._1
|
||||
dma_mem_addr_in_dccm_region_nc := rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(DCCM_SADR).U,DCCM_SIZE)._2
|
||||
} else{
|
||||
dma_mem_addr_in_dccm := 0.U
|
||||
dma_mem_addr_in_dccm_region_nc := 0.U
|
||||
}
|
||||
|
||||
|
||||
// Address check iccm
|
||||
val dma_mem_addr_in_iccm_region_nc = WireInit(Bool(),0.B)
|
||||
if (ICCM_ENABLE) {
|
||||
dma_mem_addr_in_iccm := rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE)._1
|
||||
dma_mem_addr_in_iccm_region_nc := rvrangecheck_ch(dma_mem_addr_int(31,0),aslong(ICCM_SADR).U,ICCM_SIZE)._2
|
||||
|
||||
}else {
|
||||
dma_mem_addr_in_iccm := 0.U
|
||||
dma_mem_addr_in_iccm_region_nc := 0.U
|
||||
}
|
||||
|
||||
|
||||
val dma_bus_clk = Wire(Clock())
|
||||
if(RV_FPGA_OPTIMIZE) dma_bus_clk := 0.B.asClock()
|
||||
else dma_bus_clk := rvclkhdr(clock,io.dma_bus_clk_en,io.scan_mode)// dma_bus_cgc (.en(dma_bus_clk_en), .l1clk(dma_bus_clk), .*)
|
||||
|
||||
// Inputs
|
||||
fifo_full_spec_bus := rvdff_fpga(fifo_full_spec,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
dbg_dma_bubble_bus := rvdff_fpga(io.dbg_dma.dbg_dma_bubble,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
dma_dbg_cmd_done_q := withClock(io.free_clk){ RegNext(io.dma_dbg_cmd_done,0.U)}
|
||||
|
||||
// Write channel buffer
|
||||
val wrbuf_en = io.dma_axi.aw.valid & io.dma_axi.aw.ready
|
||||
val wrbuf_data_en = io.dma_axi.w.valid & io.dma_axi.w.ready
|
||||
val wrbuf_cmd_sent = bus_cmd_sent & bus_cmd_write
|
||||
val wrbuf_rst = wrbuf_cmd_sent & ~wrbuf_en
|
||||
val wrbuf_data_rst = wrbuf_cmd_sent & ~wrbuf_data_en
|
||||
|
||||
val wrbuf_vld = rvdffsc_fpga(1.B,wrbuf_en,wrbuf_rst,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val wrbuf_data_vld = rvdffsc_fpga(1.B,wrbuf_data_en,wrbuf_data_rst,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val wrbuf_tag = rvdffs_fpga(io.dma_axi.aw.bits.id,wrbuf_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val wrbuf_sz = rvdffs_fpga(io.dma_axi.aw.bits.size,wrbuf_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val wrbuf_addr = rvdffe(io.dma_axi.aw.bits.addr,wrbuf_en & io.dma_bus_clk_en,clock,io.scan_mode)
|
||||
val wrbuf_data = rvdffe(io.dma_axi.w.bits.data,wrbuf_data_en & io.dma_bus_clk_en,clock,io.scan_mode)
|
||||
val wrbuf_byteen = rvdffs_fpga(io.dma_axi.w.bits.strb,wrbuf_data_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
|
||||
// Read channel buffer
|
||||
val rdbuf_en = io.dma_axi.ar.valid & io.dma_axi.ar.ready
|
||||
val rdbuf_cmd_sent = bus_cmd_sent & ~bus_cmd_write
|
||||
val rdbuf_rst = rdbuf_cmd_sent & ~rdbuf_en
|
||||
|
||||
val rdbuf_vld = rvdffsc_fpga(1.B,rdbuf_en,rdbuf_rst,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val rdbuf_tag = rvdffs_fpga(io.dma_axi.ar.bits.id,rdbuf_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val rdbuf_sz = rvdffs_fpga(io.dma_axi.ar.bits.size,rdbuf_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
val rdbuf_addr = rvdffe(io.dma_axi.ar.bits.addr,rdbuf_en & io.dma_bus_clk_en,clock,io.scan_mode)
|
||||
|
||||
io.dma_axi.aw.ready := ~(wrbuf_vld & ~wrbuf_cmd_sent)
|
||||
io.dma_axi.w.ready := ~(wrbuf_data_vld & ~wrbuf_cmd_sent)
|
||||
io.dma_axi.ar.ready := ~(rdbuf_vld & ~rdbuf_cmd_sent)
|
||||
|
||||
//Generate a single request from read/write channel
|
||||
val axi_mstr_sel = WireInit(Bool(),0.B)
|
||||
bus_cmd_valid := (wrbuf_vld & wrbuf_data_vld) | rdbuf_vld
|
||||
bus_cmd_sent := bus_cmd_valid & dma_fifo_ready
|
||||
bus_cmd_write := axi_mstr_sel
|
||||
bus_cmd_posted_write := 0.U
|
||||
bus_cmd_addr := Mux(axi_mstr_sel, wrbuf_addr, rdbuf_addr)
|
||||
bus_cmd_sz := Mux(axi_mstr_sel, wrbuf_sz, rdbuf_sz)
|
||||
bus_cmd_wdata := wrbuf_data
|
||||
bus_cmd_byteen := wrbuf_byteen
|
||||
bus_cmd_tag := Mux(axi_mstr_sel, wrbuf_tag, rdbuf_tag)
|
||||
bus_cmd_mid := 0.U
|
||||
bus_cmd_prty := 0.U
|
||||
|
||||
// Sel=1 -> write has higher priority
|
||||
val axi_mstr_priority = WireInit(Bool(),0.B)
|
||||
axi_mstr_sel := Mux(((wrbuf_vld & wrbuf_data_vld & rdbuf_vld)===1.U).asBool(), axi_mstr_priority, (wrbuf_vld & wrbuf_data_vld) )
|
||||
val axi_mstr_prty_in = ~axi_mstr_priority
|
||||
val axi_mstr_prty_en = bus_cmd_sent
|
||||
axi_mstr_priority := rvdffs_fpga(axi_mstr_prty_in.asUInt(),axi_mstr_prty_en,dma_bus_clk,io.dma_bus_clk_en,clock)
|
||||
|
||||
val axi_rsp_valid = fifo_valid(RspPtr) & ~fifo_dbg(RspPtr) & fifo_done_bus(RspPtr)
|
||||
val axi_rsp_rdata = fifo_data(RspPtr)
|
||||
val axi_rsp_write = fifo_write(RspPtr)
|
||||
val axi_rsp_error = Mux(fifo_error(RspPtr)(0), 2.U,Mux(fifo_error(RspPtr)(1), 3.U, 0.U))
|
||||
val axi_rsp_tag = fifo_tag(RspPtr)
|
||||
|
||||
// AXI response channel signals
|
||||
io.dma_axi.b.valid := axi_rsp_valid & axi_rsp_write
|
||||
io.dma_axi.b.bits.resp := axi_rsp_error
|
||||
io.dma_axi.b.bits.id := axi_rsp_tag
|
||||
|
||||
io.dma_axi.r.valid := axi_rsp_valid & ~axi_rsp_write
|
||||
io.dma_axi.r.bits.resp := axi_rsp_error
|
||||
io.dma_axi.r.bits.data := axi_rsp_rdata
|
||||
io.dma_axi.r.bits.last := 1.U
|
||||
io.dma_axi.r.bits.id := axi_rsp_tag
|
||||
|
||||
bus_posted_write_done := 0.U
|
||||
bus_rsp_valid := (io.dma_axi.b.valid | io.dma_axi.r.valid)
|
||||
bus_rsp_sent := (io.dma_axi.b.valid & io.dma_axi.b.ready) | (io.dma_axi.r.valid & io.dma_axi.r.ready)
|
||||
|
||||
io.dma_active := wrbuf_vld | rdbuf_vld | (fifo_valid.orR)
|
||||
|
||||
}
|
||||
object DMA extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new dma_ctrl))
|
||||
}
|
||||
|
|
@ -76,21 +76,7 @@ class ifu extends Module with lib with RequireAsyncReset {
|
|||
aln_ctl.io.ifu_bp_ret_f := bp_ctl.io.ifu_bp_ret_f
|
||||
aln_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
aln_ctl.io.dec_aln <> io.ifu_dec.dec_aln
|
||||
// io.ifu_dec.dec_aln.aln_dec.ifu_i0_cinst := aln_ctl.io.ifu_i0_cinst
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf := aln_ctl.io.ifu_i0_icaf
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_type := aln_ctl.io.ifu_i0_icaf_type
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_icaf_second := aln_ctl.io.ifu_i0_icaf_second
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_dbecc := aln_ctl.io.ifu_i0_dbecc
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_index := aln_ctl.io.ifu_i0_bp_index
|
||||
io.ifu_i0_fa_index := aln_ctl.io.ifu_i0_fa_index
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_fghr := aln_ctl.io.ifu_i0_bp_fghr
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_bp_btag := aln_ctl.io.ifu_i0_bp_btag
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_valid := aln_ctl.io.ifu_i0_valid
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_instr := aln_ctl.io.ifu_i0_instr
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc := aln_ctl.io.ifu_i0_pc
|
||||
// io.ifu_dec.dec_aln.aln_ib.ifu_i0_pc4 := aln_ctl.io.ifu_i0_pc4
|
||||
// io.ifu_dec.dec_aln.ifu_pmu_instr_aligned := aln_ctl.io.ifu_pmu_instr_aligned
|
||||
// aln_ctl.io.i0_brp <> io.ifu_dec.dec_aln.aln_ib.i0_brp
|
||||
aln_ctl.io.dec_i0_decode_d := io.dec_i0_decode_d
|
||||
aln_ctl.io.ifu_bp_fa_index_f := bp_ctl.io.ifu_bp_fa_index_f
|
||||
|
||||
|
|
@ -100,7 +86,6 @@ class ifu extends Module with lib with RequireAsyncReset {
|
|||
|
||||
// BP wiring Inputs
|
||||
bp_ctl.io.scan_mode := io.scan_mode
|
||||
bp_ctl.io.active_clk := io.active_clk
|
||||
bp_ctl.io.ic_hit_f := mem_ctl.io.ic_hit_f
|
||||
bp_ctl.io.ifc_fetch_addr_f := ifc_ctl.io.ifc_fetch_addr_f
|
||||
bp_ctl.io.ifc_fetch_req_f := ifc_ctl.io.ifc_fetch_req_f
|
||||
|
|
@ -109,13 +94,6 @@ class ifu extends Module with lib with RequireAsyncReset {
|
|||
bp_ctl.io.exu_flush_final := io.exu_flush_final
|
||||
bp_ctl.io.dec_tlu_flush_lower_wb := io.dec_tlu_flush_lower_wb
|
||||
bp_ctl.io.dec_fa_error_index := io.dec_fa_error_index
|
||||
// bp_ctl.btb_bank0_rd_data_way1_out.suggestName("bp_ctl.btb_bank0_rd_data_way1_out")
|
||||
// for(i <- 0 until BTB_ARRAY_DEPTH) {dontTouch(bp_ctl.btb_bank0_rd_data_way0_out(i))}
|
||||
// dontTouch(bp_ctl.btb_bank0_rd_data_way1_out(0))
|
||||
// dontTouch(bp_ctl.btb_bank0_rd_data_way0_f)
|
||||
// dontTouch(bp_ctl.btb_bank0_rd_data_way1_f)
|
||||
// dontTouch(bp_ctl.btb_bank0_rd_data_way0_p1_f)
|
||||
// dontTouch(bp_ctl.btb_bank0_rd_data_way1_p1_f)
|
||||
|
||||
// mem-ctl Inputs
|
||||
mem_ctl.io.free_l2clk := io.free_l2clk
|
||||
|
|
|
|||
|
|
@ -9,7 +9,6 @@ import chisel3.experimental.chiselName
|
|||
@chiselName
|
||||
class ifu_bp_ctl extends Module with lib with RequireAsyncReset {
|
||||
val io = IO (new Bundle {
|
||||
val active_clk = Input(Clock())
|
||||
val ic_hit_f = Input(Bool())
|
||||
val exu_flush_final = Input(Bool())
|
||||
val ifc_fetch_addr_f = Input(UInt(31.W))
|
||||
|
|
|
|||
|
|
@ -182,6 +182,11 @@ class lsu_dec extends Bundle {
|
|||
val tlu_busbuff = new tlu_busbuff
|
||||
val dctl_busbuff = new dctl_busbuff
|
||||
|
||||
}
|
||||
class dbg_dma extends Bundle {
|
||||
val dbg_dma_bubble = Input(Bool()) // Debug needs a bubble to send a valid
|
||||
val dma_dbg_ready = Output(Bool()) // DMA is ready to accept debug request
|
||||
|
||||
}
|
||||
class tlu_busbuff extends Bundle {
|
||||
val lsu_pmu_bus_trxn = Output(Bool())
|
||||
|
|
|
|||
|
|
@ -3,6 +3,7 @@ import chisel3.util._
|
|||
import include._
|
||||
import lib._
|
||||
import chisel3.experimental.chiselName
|
||||
import chisel3.stage.ChiselStage
|
||||
|
||||
@chiselName
|
||||
class pic_ctrl extends Module with RequireAsyncReset with lib {
|
||||
|
|
@ -14,13 +15,13 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
val extintsrc_req = Input(UInt (PIC_TOTAL_INT_PLUS1.W))
|
||||
val lsu_pic = Flipped(new lsu_pic())
|
||||
val dec_pic = Flipped(new dec_pic)
|
||||
// val dec_tlu_meicurpl = Input(UInt(4.W))
|
||||
// val dec_tlu_meipt = Input(UInt(4.W))
|
||||
//
|
||||
// val mexintpend = Output(Bool())
|
||||
// val pic_claimid = Output(UInt(8.W))
|
||||
// val pic_pl = Output(UInt(4.W))
|
||||
// val mhwakeup = Output(Bool())
|
||||
// val dec_tlu_meicurpl = Input(UInt(4.W))
|
||||
// val dec_tlu_meipt = Input(UInt(4.W))
|
||||
//
|
||||
// val mexintpend = Output(Bool())
|
||||
// val pic_claimid = Output(UInt(8.W))
|
||||
// val pic_pl = Output(UInt(4.W))
|
||||
// val mhwakeup = Output(Bool())
|
||||
})
|
||||
|
||||
def cmp_and_mux (a_id : UInt, a_priority : UInt, b_id : UInt, b_priority : UInt) =
|
||||
|
|
@ -63,20 +64,20 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
val GW_CONFIG = WireInit(UInt(PIC_TOTAL_INT_PLUS1.W), init=0.U)
|
||||
|
||||
val intpend_rd_out = WireInit(0.U(32.W))
|
||||
// val intenable_rd_out = WireInit(0.U(1.W))
|
||||
// val intenable_rd_out = WireInit(0.U(1.W))
|
||||
val intpriority_reg_inv = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))
|
||||
val intpend_reg_extended = WireInit(0.U (INTPEND_SIZE.W))
|
||||
val selected_int_priority = WireInit(0.U (INTPRIORITY_BITS.W))
|
||||
val intpend_w_prior_en = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(INTPRIORITY_BITS.W)))///////////////////
|
||||
val intpend_id = Wire(Vec(PIC_TOTAL_INT_PLUS1,UInt(ID_BITS.W)))
|
||||
val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(INTPRIORITY_BITS.W))))
|
||||
val levelx_intpend_w_prior_en = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+2).toInt,UInt(INTPRIORITY_BITS.W))))
|
||||
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_w_prior_en(i)(j) := 0.U
|
||||
val levelx_intpend_id = Wire(Vec((NUM_LEVELS - NUM_LEVELS/2)+1 ,Vec ((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2,UInt(ID_BITS.W))))
|
||||
for(i<- 0 until (NUM_LEVELS - NUM_LEVELS/2)+1; j<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)+2) levelx_intpend_id(i)(j) := 0.U
|
||||
val l2_intpend_w_prior_en_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(INTPRIORITY_BITS.W)))
|
||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_w_prior_en_ff(i) := 0.U
|
||||
val l2_intpend_id_ff = Wire(Vec(PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt,UInt(ID_BITS.W)))
|
||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt)) l2_intpend_id_ff(i) := 0.U
|
||||
val l2_intpend_w_prior_en_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(INTPRIORITY_BITS.W)))
|
||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_w_prior_en_ff(i) := 0.U
|
||||
val l2_intpend_id_ff = Wire(Vec((PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt,UInt(ID_BITS.W)))
|
||||
for(i<- 0 until (PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2)+1).toInt) l2_intpend_id_ff(i) := 0.U
|
||||
val config_reg = WireInit(0.U(1.W))
|
||||
val intpriord = WireInit(0.U(1.W))
|
||||
val prithresh_reg_write = WireInit(0.U(1.W))
|
||||
|
|
@ -177,8 +178,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
level_intpend_w_prior_en(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_w_prior_en(i)) ++ IndexedSeq(0.U(4.W), 0.U(4.W), 0.U(4.W))
|
||||
level_intpend_id(0) := (0 until PIC_TOTAL_INT_PLUS1).map(i=> intpend_id(i)) ++ IndexedSeq(0.U(8.W), 0.U(8.W), 0.U(8.W))
|
||||
|
||||
levelx_intpend_w_prior_en(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W))
|
||||
levelx_intpend_id(NUM_LEVELS/2) := (0 until (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W))
|
||||
levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_w_prior_en_ff(i)) ++ IndexedSeq(0.U(INTPRIORITY_BITS.W))
|
||||
levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2) := (0 to (PIC_TOTAL_INT_PLUS1/scala.math.pow(2,(NUM_LEVELS/2))).toInt).map(i=> l2_intpend_id_ff(i)) ++ IndexedSeq(1.U(ID_BITS.W))
|
||||
|
||||
/// Do the prioritization of the interrupts here ////////////
|
||||
for (l <-0 until NUM_LEVELS/2 ; m <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(l+1)).toInt)) {
|
||||
|
|
@ -195,7 +196,8 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_w_prior_en_ff(i) := withClock(io.free_clk){RegNext(level_intpend_w_prior_en(NUM_LEVELS/2)(i))})
|
||||
(0 to PIC_TOTAL_INT_PLUS1 / scala.math.pow(2,NUM_LEVELS/2).toInt).map(i => l2_intpend_id_ff(i) := withClock(io.free_clk){RegNext(level_intpend_id(NUM_LEVELS/2)(i))})
|
||||
|
||||
for (j <-NUM_LEVELS/2 until NUM_LEVELS ; k <- 0 to ((PIC_TOTAL_INT_PLUS1)/math.pow(2,(j+1)).toInt)) {
|
||||
for (j <- 0 until (NUM_LEVELS - NUM_LEVELS/2) ) {
|
||||
for(k <- 0 to ((PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1+3)).toInt)) {
|
||||
|
||||
if ( k == (PIC_TOTAL_INT_PLUS1)/scala.math.pow(2,(j+1)).toInt) {
|
||||
levelx_intpend_w_prior_en(j + 1)(k + 1) := 0.U
|
||||
|
|
@ -206,6 +208,7 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
(levelx_intpend_w_prior_en(j+1)(k)) := out_priority1
|
||||
|
||||
}
|
||||
}
|
||||
claimid_in := levelx_intpend_id(NUM_LEVELS - NUM_LEVELS/2)(0) // This is the last level output
|
||||
selected_int_priority := levelx_intpend_w_prior_en(NUM_LEVELS - NUM_LEVELS/2)(0)
|
||||
}
|
||||
|
|
@ -405,4 +408,5 @@ class pic_ctrl extends Module with RequireAsyncReset with lib {
|
|||
}
|
||||
|
||||
}
|
||||
|
||||
object pic extends App {
|
||||
println((new ChiselStage).emitVerilog(new pic_ctrl))}
|
||||
|
|
|
|||
|
|
@ -1,290 +1,328 @@
|
|||
//import chisel3._
|
||||
//import chisel3.util._
|
||||
//import ifu._
|
||||
//import dec._
|
||||
//import exu._
|
||||
//import lsu._
|
||||
//import lib._
|
||||
//import include._
|
||||
//import dbg._
|
||||
//import mem.mem_lsu
|
||||
//class quasar_bundle extends Bundle with lib{
|
||||
// val lsu_axi = new axi_channels(LSU_BUS_TAG)
|
||||
// val ifu_axi = new axi_channels(IFU_BUS_TAG)
|
||||
// val sb_axi = new axi_channels(SB_BUS_TAG)
|
||||
// val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
//
|
||||
// val lsu_ahb = new ahb_channel
|
||||
// val ifu_ahb = new ahb_channel
|
||||
// val sb_ahb = new ahb_channel
|
||||
// val dma_ahb = new Bundle{
|
||||
// val sig = Flipped(new ahb_channel())
|
||||
// val hsel = Input(Bool())
|
||||
// val hreadyin = Input(Bool())}
|
||||
//
|
||||
// val dbg_rst_l = Input(AsyncReset())
|
||||
// val rst_vec = Input(UInt(31.W))
|
||||
// val nmi_int = Input(Bool())
|
||||
// val nmi_vec = Input(UInt(31.W))
|
||||
// val core_rst_l = Output(AsyncReset())
|
||||
// val rv_trace_pkt = new trace_pkt_t()
|
||||
// val dccm_clk_override = Output(Bool())
|
||||
// val icm_clk_override = Output(Bool())
|
||||
// val dec_tlu_core_ecc_disable = Output(Bool())
|
||||
// val i_cpu_halt_req = Input(Bool())
|
||||
// val i_cpu_run_req = Input(Bool())
|
||||
// val o_cpu_halt_ack = Output(Bool())
|
||||
// val o_cpu_halt_status = Output(Bool())
|
||||
// val o_cpu_run_ack = Output(Bool())
|
||||
// val o_debug_mode_status = Output(Bool())
|
||||
// val core_id = Input(UInt(28.W))
|
||||
// val mpc_debug_halt_req = Input(Bool())
|
||||
// val mpc_debug_run_req = Input(Bool())
|
||||
// val mpc_reset_run_req = Input(Bool())
|
||||
// val mpc_debug_halt_ack = Output(Bool())
|
||||
// val mpc_debug_run_ack = Output(Bool())
|
||||
// val debug_brkpt_status = Output(Bool())
|
||||
// val dec_tlu_perfcnt0 = Output(Bool())
|
||||
// val dec_tlu_perfcnt1 = Output(Bool())
|
||||
// val dec_tlu_perfcnt2 = Output(Bool())
|
||||
// val dec_tlu_perfcnt3 = Output(Bool())
|
||||
// val dccm = Flipped(new mem_lsu)
|
||||
// val ic = new ic_mem()
|
||||
// val iccm = new iccm_mem()
|
||||
//
|
||||
// val lsu_bus_clk_en = Input(Bool())
|
||||
// val ifu_bus_clk_en = Input(Bool())
|
||||
// val dbg_bus_clk_en = Input(Bool())
|
||||
// val dma_bus_clk_en = Input(Bool())
|
||||
// val dmi_reg_en = Input(Bool())
|
||||
// val dmi_reg_addr = Input(UInt(7.W))
|
||||
// val dmi_reg_wr_en = Input(Bool())
|
||||
// val dmi_reg_wdata = Input(UInt(32.W))
|
||||
// val dmi_reg_rdata = Output(UInt(32.W))
|
||||
// val dmi_hard_reset = Input(Bool())
|
||||
// val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||
// val timer_int = Input(Bool())
|
||||
// val soft_int = Input(Bool())
|
||||
// val scan_mode = Input(Bool())
|
||||
//}
|
||||
//
|
||||
//class quasar extends Module with RequireAsyncReset with lib {
|
||||
// val io = IO (new quasar_bundle)
|
||||
//
|
||||
// val ifu = Module(new ifu)
|
||||
// val dec = Module(new dec)
|
||||
// val dbg = Module(new dbg)
|
||||
// val exu = Module(new exu)
|
||||
// val lsu = Module(new lsu)
|
||||
// val pic_ctrl_inst = Module(new pic_ctrl)
|
||||
// val dma_ctrl = Module(new dma_ctrl)
|
||||
//
|
||||
// io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
|
||||
// val active_state = (!dec.io.dec_pause_state_cg | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r) | dec.io.dec_tlu_misc_clk_override
|
||||
// val free_clk = rvclkhdr(clock, true.B, io.scan_mode)
|
||||
// val active_clk = rvclkhdr(clock, active_state.asBool, io.scan_mode)
|
||||
//
|
||||
// // Lets start with IFU
|
||||
// ifu.io.ifu_dec <> dec.io.ifu_dec
|
||||
//
|
||||
// ifu.reset := io.core_rst_l
|
||||
// ifu.io.scan_mode := io.scan_mode
|
||||
// ifu.io.free_clk := free_clk
|
||||
// ifu.io.active_clk := active_clk
|
||||
//
|
||||
// ifu.io.exu_flush_final := dec.io.exu_flush_final
|
||||
// ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
|
||||
//
|
||||
// ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
// ifu.io.ifu_dma <> dma_ctrl.io.ifu_dma
|
||||
// ifu.io.ic <> io.ic
|
||||
// ifu.io.iccm <> io.iccm
|
||||
// ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
|
||||
// ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
|
||||
// ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
|
||||
// ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
// ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
||||
//
|
||||
// // Lets start with Dec
|
||||
// dec.reset := io.core_rst_l
|
||||
// dec.io.free_clk := free_clk
|
||||
// dec.io.active_clk := active_clk
|
||||
// dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
|
||||
// dec.io.rst_vec := io.rst_vec
|
||||
// dec.io.nmi_int := io.nmi_int
|
||||
// dec.io.nmi_vec := io.nmi_vec
|
||||
// dec.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
// dec.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
// dec.io.core_id := io.core_id
|
||||
// dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
// dec.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
// dec.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
// dec.io.lsu_dec <> lsu.io.lsu_dec
|
||||
// dec.io.lsu_tlu <> lsu.io.lsu_tlu
|
||||
// dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
|
||||
// dec.io.dec_dma <> dma_ctrl.io.dec_dma
|
||||
//
|
||||
// dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
|
||||
// dec.io.lsu_fir_error := lsu.io.lsu_fir_error
|
||||
// dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
|
||||
// dec.io.dec_dbg <> dbg.io.dbg_dec
|
||||
// dec.io.lsu_idle_any := lsu.io.lsu_idle_any
|
||||
// dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
|
||||
// dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
|
||||
// dec.io.exu_div_result := exu.io.exu_div_result
|
||||
// dec.io.exu_div_wren := exu.io.exu_div_wren
|
||||
// dec.io.lsu_result_m := lsu.io.lsu_result_m
|
||||
// dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
|
||||
// dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
|
||||
// dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
|
||||
// dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
|
||||
// dec.io.exu_flush_final := exu.io.exu_flush_final
|
||||
//
|
||||
// dec.io.soft_int := io.soft_int
|
||||
// dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
||||
// dec.io.dbg_resume_req := dbg.io.dbg_resume_req
|
||||
// dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r
|
||||
// dec.io.timer_int := io.timer_int
|
||||
// dec.io.scan_mode := io.scan_mode
|
||||
//
|
||||
// // EXU lets go
|
||||
// dec.io.dec_exu <> exu.io.dec_exu
|
||||
// exu.reset := io.core_rst_l
|
||||
// exu.io.scan_mode := io.scan_mode
|
||||
// exu.io.dbg_cmd_wrdata := dbg.io.dbg_dec.dbg_dctl.dbg_cmd_wrdata
|
||||
//
|
||||
// // LSU Lets go
|
||||
// lsu.reset := io.core_rst_l
|
||||
// lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
|
||||
// lsu.io.dec_tlu_flush_lower_r := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
// lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
|
||||
// lsu.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
||||
// lsu.io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||
// lsu.io.lsu_exu <> exu.io.lsu_exu
|
||||
// lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
|
||||
// lsu.io.lsu_p <> dec.io.lsu_p
|
||||
// lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
|
||||
// lsu.io.dec_tlu_mrac_ff := dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff
|
||||
// lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
|
||||
//
|
||||
// lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
// lsu.io.lsu_dma <> dma_ctrl.io.lsu_dma
|
||||
// lsu.io.scan_mode := io.scan_mode
|
||||
// lsu.io.free_clk := free_clk
|
||||
//
|
||||
// // Debug lets go
|
||||
// dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
||||
// dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
||||
// dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
||||
// dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
|
||||
// dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
|
||||
// dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
|
||||
// dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
|
||||
// dbg.io.dmi_reg_en := io.dmi_reg_en
|
||||
// dbg.io.dmi_reg_addr := io.dmi_reg_addr
|
||||
// dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
|
||||
// dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
|
||||
// dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||
// dbg.io.dbg_rst_l := io.dbg_rst_l.asBool()
|
||||
// dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||
// dbg.io.scan_mode := io.scan_mode
|
||||
//
|
||||
//
|
||||
// // DMA Lets go
|
||||
// dma_ctrl.reset := io.core_rst_l
|
||||
// dma_ctrl.io.free_clk := free_clk
|
||||
// dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||
// dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||
// dma_ctrl.io.scan_mode := io.scan_mode
|
||||
// dma_ctrl.io.dbg_dma <> dbg.io.dbg_dma
|
||||
// dma_ctrl.io.dbg_dma_io <> dbg.io.dbg_dma_io
|
||||
// dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
|
||||
// dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
|
||||
// dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
|
||||
// dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
|
||||
// dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
|
||||
// dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
|
||||
//
|
||||
// // PIC lets go
|
||||
// pic_ctrl_inst.io.scan_mode := io.scan_mode
|
||||
// pic_ctrl_inst.reset := io.core_rst_l
|
||||
// pic_ctrl_inst.io.free_clk := free_clk
|
||||
// pic_ctrl_inst.io.active_clk := active_clk
|
||||
// pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_pic_clk_override
|
||||
// pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
|
||||
// pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
|
||||
// pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
|
||||
// // Trace Packet
|
||||
// io.rv_trace_pkt := dec.io.rv_trace_pkt
|
||||
//
|
||||
// // Outputs
|
||||
// io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
|
||||
// io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
|
||||
// io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||
// io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
|
||||
// io.o_cpu_halt_status := dec.io.o_cpu_halt_status
|
||||
// io.o_cpu_run_ack := dec.io.o_cpu_run_ack
|
||||
// io.o_debug_mode_status := dec.io.o_debug_mode_status
|
||||
// io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
|
||||
// io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
|
||||
// io.debug_brkpt_status := dec.io.debug_brkpt_status
|
||||
// io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
|
||||
// io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
|
||||
// io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
|
||||
// io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
|
||||
// io.dmi_reg_rdata := dbg.io.dmi_reg_rdata
|
||||
//
|
||||
// // LSU Outputs
|
||||
// io.dccm <> lsu.io.dccm
|
||||
//
|
||||
// if(BUILD_AHB_LITE) {
|
||||
// val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG))
|
||||
// val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG))
|
||||
// val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG))
|
||||
// val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG))
|
||||
//
|
||||
// lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
// lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en
|
||||
// lsu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
// lsu_axi4_to_ahb.io.axi <> lsu.io.axi
|
||||
// lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb
|
||||
//
|
||||
// ifu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
// ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en
|
||||
// ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
// ifu_axi4_to_ahb.io.axi <> ifu.io.ifu
|
||||
// ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb
|
||||
// ifu_axi4_to_ahb.io.axi.b.ready := true.B
|
||||
//
|
||||
// sb_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
// sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en
|
||||
// sb_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
// sb_axi4_to_ahb.io.axi <> dbg.io.sb_axi
|
||||
// sb_axi4_to_ahb.io.ahb <> io.sb_ahb
|
||||
//
|
||||
// dma_ahb_to_axi4.io.scan_mode := io.scan_mode
|
||||
// dma_ahb_to_axi4.io.bus_clk_en := io.dma_bus_clk_en
|
||||
// dma_ahb_to_axi4.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
// dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi
|
||||
// dma_ahb_to_axi4.io.ahb <> io.dma_ahb
|
||||
//
|
||||
// io.dma_axi <> 0.U.asTypeOf(io.dma_axi)
|
||||
// io.sb_axi <> 0.U.asTypeOf(io.sb_axi)
|
||||
// io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi)
|
||||
// io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi)
|
||||
// }
|
||||
// else{
|
||||
// io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb)
|
||||
// io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb)
|
||||
// io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb)
|
||||
// io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb)
|
||||
// dma_ctrl.io.dma_axi <> io.dma_axi
|
||||
// dbg.io.sb_axi <> io.sb_axi
|
||||
// ifu.io.ifu <> io.ifu_axi
|
||||
// lsu.io.axi <> io.lsu_axi
|
||||
// }
|
||||
//
|
||||
//}
|
||||
////object QUASAR extends App {
|
||||
// // println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||
////}
|
||||
import chisel3._
|
||||
import chisel3.util._
|
||||
import ifu._
|
||||
import dec._
|
||||
import exu._
|
||||
import lsu._
|
||||
import lib._
|
||||
import include._
|
||||
import dbg._
|
||||
import mem.mem_lsu
|
||||
class quasar_bundle extends Bundle with lib{
|
||||
val lsu_axi = new axi_channels(LSU_BUS_TAG)
|
||||
val ifu_axi = new axi_channels(IFU_BUS_TAG)
|
||||
val sb_axi = new axi_channels(SB_BUS_TAG)
|
||||
val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG))
|
||||
|
||||
val lsu_ahb = new ahb_channel
|
||||
val ifu_ahb = new ahb_channel
|
||||
val sb_ahb = new ahb_channel
|
||||
val dma_ahb = new Bundle{
|
||||
val sig = Flipped(new ahb_channel())
|
||||
val hsel = Input(Bool())
|
||||
val hreadyin = Input(Bool())}
|
||||
|
||||
val active_l2clk = Output(Clock())
|
||||
val free_l2clk = Output(Clock())
|
||||
val dbg_rst_l = Input(AsyncReset())
|
||||
val rst_vec = Input(UInt(31.W))
|
||||
val nmi_int = Input(Bool())
|
||||
val nmi_vec = Input(UInt(31.W))
|
||||
val core_rst_l = Output(AsyncReset())
|
||||
val rv_trace_pkt = new trace_pkt_t()
|
||||
val dccm_clk_override = Output(Bool())
|
||||
val icm_clk_override = Output(Bool())
|
||||
val dec_tlu_core_ecc_disable = Output(Bool())
|
||||
val i_cpu_halt_req = Input(Bool())
|
||||
val i_cpu_run_req = Input(Bool())
|
||||
val o_cpu_halt_ack = Output(Bool())
|
||||
val o_cpu_halt_status = Output(Bool())
|
||||
val o_cpu_run_ack = Output(Bool())
|
||||
val o_debug_mode_status = Output(Bool())
|
||||
val core_id = Input(UInt(28.W))
|
||||
val mpc_debug_halt_req = Input(Bool())
|
||||
val mpc_debug_run_req = Input(Bool())
|
||||
val mpc_reset_run_req = Input(Bool())
|
||||
val mpc_debug_halt_ack = Output(Bool())
|
||||
val mpc_debug_run_ack = Output(Bool())
|
||||
val debug_brkpt_status = Output(Bool())
|
||||
val dec_tlu_perfcnt0 = Output(Bool())
|
||||
val dec_tlu_perfcnt1 = Output(Bool())
|
||||
val dec_tlu_perfcnt2 = Output(Bool())
|
||||
val dec_tlu_perfcnt3 = Output(Bool())
|
||||
val dccm = Flipped(new mem_lsu)
|
||||
val ic = new ic_mem()
|
||||
val iccm = new iccm_mem()
|
||||
|
||||
val lsu_bus_clk_en = Input(Bool())
|
||||
val ifu_bus_clk_en = Input(Bool())
|
||||
val dbg_bus_clk_en = Input(Bool())
|
||||
val dma_bus_clk_en = Input(Bool())
|
||||
val dmi_reg_en = Input(Bool())
|
||||
val dmi_reg_addr = Input(UInt(7.W))
|
||||
val dmi_reg_wr_en = Input(Bool())
|
||||
val dmi_reg_wdata = Input(UInt(32.W))
|
||||
val dmi_reg_rdata = Output(UInt(32.W))
|
||||
// val dmi_hard_reset = Input(Bool())
|
||||
val extintsrc_req = Input(UInt(PIC_TOTAL_INT.W))
|
||||
val timer_int = Input(Bool())
|
||||
val soft_int = Input(Bool())
|
||||
val scan_mode = Input(Bool())
|
||||
}
|
||||
|
||||
class quasar extends Module with RequireAsyncReset with lib {
|
||||
val io = IO (new quasar_bundle)
|
||||
|
||||
val ifu = Module(new ifu)
|
||||
val dec = Module(new dec)
|
||||
val dbg = Module(new dbg)
|
||||
val exu = Module(new exu)
|
||||
val lsu = Module(new lsu)
|
||||
val pic_ctrl_inst = Module(new pic_ctrl)
|
||||
val dma_ctrl = Module(new dma_ctrl)
|
||||
|
||||
val pause_state = dec.io.dec_pause_state_cg & ~(dma_ctrl.io.dma_active | lsu.io.lsu_active) & dec.io.dec_tlu_core_empty;
|
||||
|
||||
val halt_state = dec.io.o_cpu_halt_status & ~(dma_ctrl.io.dma_active | lsu.io.lsu_active);
|
||||
|
||||
|
||||
io.core_rst_l := (reset.asBool() & (dbg.io.dbg_core_rst_l.asBool() | io.scan_mode)).asAsyncReset()
|
||||
val active_state = (~(halt_state | pause_state) | dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r | dec.io.dec_tlu_flush_lower_wb) | dec.io.dec_tlu_misc_clk_override;
|
||||
|
||||
io.free_l2clk := rvoclkhdr(clock, true.B, io.scan_mode)
|
||||
io.active_l2clk := rvoclkhdr(clock, active_state, io.scan_mode)
|
||||
val free_clk = rvoclkhdr(io.free_l2clk, true.B, io.scan_mode)
|
||||
val active_clk = rvoclkhdr(io.active_l2clk, true.B, io.scan_mode)
|
||||
|
||||
// Lets start with IFU
|
||||
ifu.io.ifu_dec <> dec.io.ifu_dec
|
||||
ifu.io.dec_i0_decode_d := dec.io.dec_i0_decode_d
|
||||
ifu.clock := io.active_l2clk
|
||||
ifu.io.free_l2clk := io.free_l2clk
|
||||
ifu.reset := io.core_rst_l
|
||||
ifu.io.scan_mode := io.scan_mode
|
||||
ifu.io.active_clk := active_clk
|
||||
|
||||
ifu.io.exu_flush_final := dec.io.exu_flush_final
|
||||
ifu.io.exu_flush_path_final := exu.io.exu_flush_path_final
|
||||
ifu.io.dec_fa_error_index := dec.io.dec_fa_error_index
|
||||
ifu.io.ifu_bus_clk_en := io.ifu_bus_clk_en
|
||||
ifu.io.ifu_dma <> dma_ctrl.io.ifu_dma
|
||||
ifu.io.ic <> io.ic
|
||||
ifu.io.iccm <> io.iccm
|
||||
ifu.io.exu_ifu.exu_bp <> exu.io.exu_bp
|
||||
ifu.io.exu_ifu.exu_bp.exu_i0_br_fghr_r := exu.io.exu_bp.exu_i0_br_fghr_r
|
||||
ifu.io.exu_ifu.exu_bp.exu_i0_br_index_r := exu.io.dec_exu.tlu_exu.exu_i0_br_index_r
|
||||
ifu.io.dec_tlu_flush_lower_wb := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
ifu.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt <> dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_ic_diag_pkt
|
||||
|
||||
// Lets start with Dec
|
||||
dec.io.ifu_i0_fa_index := ifu.io.ifu_i0_fa_index
|
||||
dec.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data
|
||||
dec.io.free_l2clk := io.free_l2clk
|
||||
dec.reset := io.core_rst_l
|
||||
dec.clock := io.active_l2clk
|
||||
dec.io.active_clk := active_clk
|
||||
dec.io.free_clk := free_clk
|
||||
dec.io.lsu_fastint_stall_any := lsu.io.lsu_fastint_stall_any
|
||||
dec.io.rst_vec := io.rst_vec
|
||||
dec.io.nmi_int := io.nmi_int
|
||||
dec.io.nmi_vec := io.nmi_vec
|
||||
dec.io.i_cpu_halt_req := io.i_cpu_halt_req
|
||||
dec.io.i_cpu_run_req := io.i_cpu_run_req
|
||||
dec.io.core_id := io.core_id
|
||||
dec.io.mpc_debug_halt_req := io.mpc_debug_halt_req
|
||||
dec.io.mpc_debug_run_req := io.mpc_debug_run_req
|
||||
dec.io.mpc_reset_run_req := io.mpc_reset_run_req
|
||||
dec.io.lsu_dec <> lsu.io.lsu_dec
|
||||
dec.io.lsu_tlu <> lsu.io.lsu_tlu
|
||||
dec.io.lsu_pmu_misaligned_m := lsu.io.lsu_pmu_misaligned_m
|
||||
dec.io.dec_dma <> dma_ctrl.io.dec_dma
|
||||
|
||||
dec.io.lsu_fir_addr := lsu.io.lsu_fir_addr
|
||||
dec.io.lsu_fir_error := lsu.io.lsu_fir_error
|
||||
dec.io.lsu_trigger_match_m := lsu.io.lsu_trigger_match_m
|
||||
dec.io.dec_dbg <> dbg.io.dbg_dec_dma
|
||||
dec.io.lsu_idle_any := lsu.io.lsu_idle_any
|
||||
dec.io.lsu_error_pkt_r <> lsu.io.lsu_error_pkt_r
|
||||
dec.io.lsu_single_ecc_error_incr := lsu.io.lsu_single_ecc_error_incr
|
||||
dec.io.exu_div_result := exu.io.exu_div_result
|
||||
dec.io.exu_div_wren := exu.io.exu_div_wren
|
||||
dec.io.lsu_result_m := lsu.io.lsu_exu.lsu_result_m
|
||||
dec.io.lsu_result_corr_r := lsu.io.lsu_result_corr_r
|
||||
dec.io.lsu_load_stall_any := lsu.io.lsu_load_stall_any
|
||||
dec.io.lsu_store_stall_any := lsu.io.lsu_store_stall_any
|
||||
dec.io.iccm_dma_sb_error := ifu.io.iccm_dma_sb_error
|
||||
dec.io.exu_flush_final := exu.io.exu_flush_final
|
||||
|
||||
dec.io.soft_int := io.soft_int
|
||||
dec.io.dbg_halt_req := dbg.io.dbg_halt_req
|
||||
dec.io.dbg_resume_req := dbg.io.dbg_resume_req
|
||||
dec.io.exu_i0_br_way_r := exu.io.exu_bp.exu_i0_br_way_r
|
||||
dec.io.timer_int := io.timer_int
|
||||
dec.io.scan_mode := io.scan_mode
|
||||
|
||||
// EXU lets go
|
||||
dec.io.dec_exu <> exu.io.dec_exu
|
||||
exu.io.dec_csr_rddata_d := dec.io.dec_csr_rddata_d
|
||||
exu.io.lsu_nonblock_load_data := lsu.io.lsu_nonblock_load_data
|
||||
exu.reset := io.core_rst_l
|
||||
exu.clock := io.active_l2clk
|
||||
exu.io.scan_mode := io.scan_mode
|
||||
exu.io.dbg_cmd_wrdata := dbg.io.dbg_dec_dma.dbg_dctl.dbg_cmd_wrdata
|
||||
|
||||
// LSU Lets go
|
||||
lsu.clock := io.active_l2clk
|
||||
lsu.reset := io.core_rst_l
|
||||
lsu.io.clk_override := dec.io.dec_tlu_lsu_clk_override
|
||||
lsu.io.dec_tlu_flush_lower_r := dec.io.dec_exu.tlu_exu.dec_tlu_flush_lower_r
|
||||
lsu.io.dec_tlu_i0_kill_writeb_r := dec.io.dec_tlu_i0_kill_writeb_r
|
||||
lsu.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
||||
lsu.io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||
lsu.io.lsu_exu <> exu.io.lsu_exu
|
||||
lsu.io.dec_lsu_offset_d := dec.io.dec_lsu_offset_d
|
||||
lsu.io.lsu_p <> dec.io.lsu_p
|
||||
lsu.io.dec_lsu_valid_raw_d := dec.io.dec_lsu_valid_raw_d
|
||||
lsu.io.dec_tlu_mrac_ff := dec.io.ifu_dec.dec_ifc.dec_tlu_mrac_ff
|
||||
lsu.io.trigger_pkt_any <> dec.io.trigger_pkt_any
|
||||
|
||||
lsu.io.lsu_bus_clk_en := io.lsu_bus_clk_en
|
||||
lsu.io.lsu_dma <> dma_ctrl.io.lsu_dma
|
||||
lsu.io.scan_mode := io.scan_mode
|
||||
lsu.io.active_clk := active_clk
|
||||
|
||||
// Debug lets go
|
||||
dbg.io.core_dbg_rddata := Mux(dma_ctrl.io.dma_dbg_cmd_done, dma_ctrl.io.dma_dbg_rddata, dec.io.dec_dbg_rddata)
|
||||
dbg.io.core_dbg_cmd_done := dma_ctrl.io.dma_dbg_cmd_done | dec.io.dec_dbg_cmd_done
|
||||
dbg.io.core_dbg_cmd_fail := dma_ctrl.io.dma_dbg_cmd_fail | dec.io.dec_dbg_cmd_fail
|
||||
dbg.io.dec_tlu_debug_mode := dec.io.dec_tlu_debug_mode
|
||||
dbg.io.dec_tlu_dbg_halted := dec.io.dec_tlu_dbg_halted
|
||||
dbg.io.dec_tlu_mpc_halted_only := dec.io.dec_tlu_mpc_halted_only
|
||||
dbg.io.dec_tlu_resume_ack := dec.io.dec_tlu_resume_ack
|
||||
dbg.io.dmi_reg_en := io.dmi_reg_en
|
||||
dbg.io.dmi_reg_addr := io.dmi_reg_addr
|
||||
dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en
|
||||
dbg.io.dmi_reg_wdata := io.dmi_reg_wdata
|
||||
dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en
|
||||
dbg.io.dbg_rst_l := io.dbg_rst_l
|
||||
dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||
dbg.io.scan_mode := io.scan_mode
|
||||
dbg.clock := io.free_l2clk
|
||||
dbg.reset := io.core_rst_l
|
||||
|
||||
|
||||
// DMA Lets go
|
||||
dma_ctrl.clock := io.free_l2clk
|
||||
dma_ctrl.reset := io.core_rst_l
|
||||
dma_ctrl.io.free_clk := free_clk
|
||||
dma_ctrl.io.dma_bus_clk_en := io.dma_bus_clk_en
|
||||
dma_ctrl.io.clk_override := dec.io.dec_tlu_misc_clk_override
|
||||
dma_ctrl.io.scan_mode := io.scan_mode
|
||||
dma_ctrl.io.dbg_dma <> dbg.io.dbg_dma
|
||||
dma_ctrl.io.dbg_dec_dma <> dbg.io.dbg_dec_dma
|
||||
dma_ctrl.io.dbg_cmd_size := dbg.io.dbg_cmd_size
|
||||
dma_ctrl.io.iccm_dma_rvalid := ifu.io.iccm_dma_rvalid
|
||||
dma_ctrl.io.iccm_dma_rtag := ifu.io.iccm_dma_rtag
|
||||
dma_ctrl.io.iccm_dma_rdata := ifu.io.iccm_dma_rdata
|
||||
dma_ctrl.io.iccm_ready := ifu.io.iccm_ready
|
||||
dma_ctrl.io.iccm_dma_ecc_error := ifu.io.iccm_dma_ecc_error
|
||||
|
||||
// PIC lets go
|
||||
pic_ctrl_inst.io.scan_mode := io.scan_mode
|
||||
pic_ctrl_inst.clock := io.free_l2clk
|
||||
pic_ctrl_inst.reset := io.core_rst_l
|
||||
pic_ctrl_inst.io.free_clk := free_clk
|
||||
pic_ctrl_inst.io.active_clk := active_clk
|
||||
pic_ctrl_inst.io.clk_override := dec.io.dec_tlu_picio_clk_override
|
||||
pic_ctrl_inst.io.extintsrc_req := Cat(io.extintsrc_req,0.U)
|
||||
pic_ctrl_inst.io.lsu_pic <> lsu.io.lsu_pic
|
||||
pic_ctrl_inst.io.dec_pic <> dec.io.dec_pic
|
||||
// Trace Packet
|
||||
io.rv_trace_pkt := dec.io.trace_rv_trace_pkt
|
||||
|
||||
// Outputs
|
||||
io.dccm_clk_override := dec.io.dec_tlu_dccm_clk_override
|
||||
io.icm_clk_override := dec.io.dec_tlu_icm_clk_override
|
||||
io.dec_tlu_core_ecc_disable := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable
|
||||
io.o_cpu_halt_ack := dec.io.o_cpu_halt_ack
|
||||
io.o_cpu_halt_status := dec.io.o_cpu_halt_status
|
||||
io.o_cpu_run_ack := dec.io.o_cpu_run_ack
|
||||
io.o_debug_mode_status := dec.io.o_debug_mode_status
|
||||
io.mpc_debug_halt_ack := dec.io.mpc_debug_halt_ack
|
||||
io.mpc_debug_run_ack := dec.io.mpc_debug_run_ack
|
||||
io.debug_brkpt_status := dec.io.debug_brkpt_status
|
||||
io.dec_tlu_perfcnt0 := dec.io.dec_tlu_perfcnt0
|
||||
io.dec_tlu_perfcnt1 := dec.io.dec_tlu_perfcnt1
|
||||
io.dec_tlu_perfcnt2 := dec.io.dec_tlu_perfcnt2
|
||||
io.dec_tlu_perfcnt3 := dec.io.dec_tlu_perfcnt3
|
||||
io.dmi_reg_rdata := dbg.io.dmi_reg_rdata
|
||||
|
||||
// LSU Outputs
|
||||
io.dccm <> lsu.io.dccm
|
||||
|
||||
if(BUILD_AHB_LITE) {
|
||||
val sb_axi4_to_ahb = Module(new axi4_to_ahb(SB_BUS_TAG))
|
||||
val ifu_axi4_to_ahb = Module(new axi4_to_ahb(IFU_BUS_TAG))
|
||||
val lsu_axi4_to_ahb = Module(new axi4_to_ahb(LSU_BUS_TAG))
|
||||
val dma_ahb_to_axi4 = Module(new ahb_to_axi4(DMA_BUS_TAG))
|
||||
|
||||
lsu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en
|
||||
lsu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
lsu_axi4_to_ahb.io.axi <> lsu.io.axi
|
||||
lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb
|
||||
lsu_axi4_to_ahb.clock := io.free_l2clk
|
||||
lsu_axi4_to_ahb.io.free_clk := free_clk
|
||||
lsu_axi4_to_ahb.reset := io.core_rst_l
|
||||
lsu_axi4_to_ahb.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
||||
|
||||
|
||||
ifu_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en
|
||||
ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
ifu_axi4_to_ahb.io.axi <> ifu.io.ifu
|
||||
ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb
|
||||
ifu_axi4_to_ahb.io.axi.b.ready := true.B
|
||||
ifu_axi4_to_ahb.clock := io.free_l2clk
|
||||
ifu_axi4_to_ahb.io.free_clk := free_clk
|
||||
ifu_axi4_to_ahb.reset := io.core_rst_l
|
||||
ifu_axi4_to_ahb.io.dec_tlu_force_halt := dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_force_halt
|
||||
|
||||
sb_axi4_to_ahb.io.scan_mode := io.scan_mode
|
||||
sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en
|
||||
sb_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
sb_axi4_to_ahb.io.axi <> dbg.io.sb_axi
|
||||
sb_axi4_to_ahb.io.ahb <> io.sb_ahb
|
||||
sb_axi4_to_ahb.clock := io.free_l2clk
|
||||
sb_axi4_to_ahb.io.free_clk := free_clk
|
||||
sb_axi4_to_ahb.reset := io.core_rst_l
|
||||
sb_axi4_to_ahb.io.dec_tlu_force_halt := 0.U
|
||||
|
||||
dma_ahb_to_axi4.io.scan_mode := io.scan_mode
|
||||
dma_ahb_to_axi4.io.bus_clk_en := io.dma_bus_clk_en
|
||||
dma_ahb_to_axi4.io.clk_override := dec.io.dec_tlu_bus_clk_override
|
||||
dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi
|
||||
dma_ahb_to_axi4.io.ahb <> io.dma_ahb
|
||||
dma_ahb_to_axi4.clock := io.free_l2clk
|
||||
dma_ahb_to_axi4.reset := io.core_rst_l
|
||||
|
||||
io.dma_axi <> 0.U.asTypeOf(io.dma_axi)
|
||||
io.sb_axi <> 0.U.asTypeOf(io.sb_axi)
|
||||
io.ifu_axi <> 0.U.asTypeOf(io.ifu_axi)
|
||||
io.lsu_axi <> 0.U.asTypeOf(io.lsu_axi)
|
||||
}
|
||||
else{
|
||||
io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb)
|
||||
io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb)
|
||||
io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb)
|
||||
io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb)
|
||||
dma_ctrl.io.dma_axi <> io.dma_axi
|
||||
dbg.io.sb_axi <> io.sb_axi
|
||||
ifu.io.ifu <> io.ifu_axi
|
||||
lsu.io.axi <> io.lsu_axi
|
||||
}
|
||||
|
||||
}
|
||||
object QUASAR extends App {
|
||||
println((new chisel3.stage.ChiselStage).emitVerilog(new quasar()))
|
||||
}
|
||||
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Reference in New Issue