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RegEnable added

This commit is contained in:
waleed-lm 2020-10-08 18:53:20 +05:00
parent e9c21910d8
commit 2fd89019c6
8 changed files with 392 additions and 442 deletions
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36
el2_ifu_iccm_mem.anno.json
View File

@ -1,40 +1,4 @@
[ [
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_2",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_3",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_1",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_bank_addr_0",
"sources":[
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_rw_addr",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wren",
"~el2_ifu_iccm_mem|el2_ifu_iccm_mem>io_iccm_wr_size"
]
},
{ {
"class":"firrtl.EmitCircuitAnnotation", "class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter" "emitter":"firrtl.VerilogEmitter"

596
el2_ifu_iccm_mem.fir
View File

@ -3,7 +3,7 @@ circuit el2_ifu_iccm_mem :
module el2_ifu_iccm_mem : module el2_ifu_iccm_mem :
input clock : Clock input clock : Clock
input reset : UInt<1> input reset : UInt<1>
output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>, iccm_bank_addr : UInt[4]} output io : {flip clk_override : UInt<1>, flip iccm_wren : UInt<1>, flip iccm_rden : UInt<1>, flip iccm_rw_addr : UInt<15>, flip iccm_buf_correct_ecc : UInt<1>, flip iccm_correction_state : UInt<1>, flip iccm_wr_size : UInt<3>, flip iccm_wr_data : UInt<78>, iccm_rd_data : UInt<64>, iccm_rd_data_ecc : UInt<78>, flip scan_mode : UInt<1>}
io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19] io.iccm_rd_data <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 22:19]
io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23] io.iccm_rd_data_ecc <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 23:23]
@ -183,158 +183,154 @@ circuit el2_ifu_iccm_mem :
_T_112 <= _T_111 @[Reg.scala 28:23] _T_112 <= _T_111 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
iccm_bank_dout[3] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53] iccm_bank_dout[3] <= _T_112 @[el2_ifu_iccm_mem.scala 56:53]
io.iccm_bank_addr[0] <= addr_bank[0] @[el2_ifu_iccm_mem.scala 61:21]
io.iccm_bank_addr[1] <= addr_bank[1] @[el2_ifu_iccm_mem.scala 61:21]
io.iccm_bank_addr[2] <= addr_bank[2] @[el2_ifu_iccm_mem.scala 61:21]
io.iccm_bank_addr[3] <= addr_bank[3] @[el2_ifu_iccm_mem.scala 61:21]
wire redundant_valid : UInt<2> wire redundant_valid : UInt<2>
redundant_valid <= UInt<1>("h00") redundant_valid <= UInt<1>("h00")
wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 67:31] wire redundant_address : UInt<14>[2] @[el2_ifu_iccm_mem.scala 62:31]
redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21] redundant_address[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 68:21] redundant_address[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 63:21]
node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] node _T_113 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] node _T_114 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] node _T_115 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 70:105] node _T_116 = eq(_T_114, _T_115) @[el2_ifu_iccm_mem.scala 65:105]
node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] node _T_117 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 70:169] node _T_118 = eq(_T_117, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 70:145] node _T_119 = and(_T_116, _T_118) @[el2_ifu_iccm_mem.scala 65:145]
node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 70:71] node _T_120 = and(_T_113, _T_119) @[el2_ifu_iccm_mem.scala 65:71]
node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] node _T_121 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] node _T_122 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 71:37] node _T_123 = eq(_T_121, _T_122) @[el2_ifu_iccm_mem.scala 66:37]
node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] node _T_124 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 71:99] node _T_125 = eq(_T_124, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 71:77] node _T_126 = and(_T_123, _T_125) @[el2_ifu_iccm_mem.scala 66:77]
node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 70:179] node _T_127 = or(_T_120, _T_126) @[el2_ifu_iccm_mem.scala 65:179]
node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] node _T_128 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] node _T_129 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] node _T_130 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 70:105] node _T_131 = eq(_T_129, _T_130) @[el2_ifu_iccm_mem.scala 65:105]
node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] node _T_132 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 70:169] node _T_133 = eq(_T_132, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 70:145] node _T_134 = and(_T_131, _T_133) @[el2_ifu_iccm_mem.scala 65:145]
node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 70:71] node _T_135 = and(_T_128, _T_134) @[el2_ifu_iccm_mem.scala 65:71]
node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] node _T_136 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] node _T_137 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 71:37] node _T_138 = eq(_T_136, _T_137) @[el2_ifu_iccm_mem.scala 66:37]
node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] node _T_139 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 71:99] node _T_140 = eq(_T_139, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 71:77] node _T_141 = and(_T_138, _T_140) @[el2_ifu_iccm_mem.scala 66:77]
node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 70:179] node _T_142 = or(_T_135, _T_141) @[el2_ifu_iccm_mem.scala 65:179]
node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] node _T_143 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] node _T_144 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] node _T_145 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 70:105] node _T_146 = eq(_T_144, _T_145) @[el2_ifu_iccm_mem.scala 65:105]
node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] node _T_147 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 70:169] node _T_148 = eq(_T_147, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 70:145] node _T_149 = and(_T_146, _T_148) @[el2_ifu_iccm_mem.scala 65:145]
node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 70:71] node _T_150 = and(_T_143, _T_149) @[el2_ifu_iccm_mem.scala 65:71]
node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] node _T_151 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] node _T_152 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 71:37] node _T_153 = eq(_T_151, _T_152) @[el2_ifu_iccm_mem.scala 66:37]
node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] node _T_154 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 71:99] node _T_155 = eq(_T_154, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 71:77] node _T_156 = and(_T_153, _T_155) @[el2_ifu_iccm_mem.scala 66:77]
node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 70:179] node _T_157 = or(_T_150, _T_156) @[el2_ifu_iccm_mem.scala 65:179]
node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 70:67] node _T_158 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 65:67]
node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 70:90] node _T_159 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 65:90]
node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 70:128] node _T_160 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 65:128]
node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 70:105] node _T_161 = eq(_T_159, _T_160) @[el2_ifu_iccm_mem.scala 65:105]
node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 70:163] node _T_162 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 65:163]
node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 70:169] node _T_163 = eq(_T_162, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 65:169]
node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 70:145] node _T_164 = and(_T_161, _T_163) @[el2_ifu_iccm_mem.scala 65:145]
node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 70:71] node _T_165 = and(_T_158, _T_164) @[el2_ifu_iccm_mem.scala 65:71]
node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 71:22] node _T_166 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 66:22]
node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 71:60] node _T_167 = bits(redundant_address[1], 13, 0) @[el2_ifu_iccm_mem.scala 66:60]
node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 71:37] node _T_168 = eq(_T_166, _T_167) @[el2_ifu_iccm_mem.scala 66:37]
node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 71:93] node _T_169 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 66:93]
node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 71:99] node _T_170 = eq(_T_169, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 66:99]
node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 71:77] node _T_171 = and(_T_168, _T_170) @[el2_ifu_iccm_mem.scala 66:77]
node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 70:179] node _T_172 = or(_T_165, _T_171) @[el2_ifu_iccm_mem.scala 65:179]
node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58] node _T_173 = cat(_T_172, _T_157) @[Cat.scala 29:58]
node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58] node _T_174 = cat(_T_173, _T_142) @[Cat.scala 29:58]
node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58] node sel_red1 = cat(_T_174, _T_127) @[Cat.scala 29:58]
node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] node _T_175 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] node _T_176 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] node _T_177 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 72:105] node _T_178 = eq(_T_176, _T_177) @[el2_ifu_iccm_mem.scala 67:105]
node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] node _T_179 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 72:169] node _T_180 = eq(_T_179, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 72:145] node _T_181 = and(_T_178, _T_180) @[el2_ifu_iccm_mem.scala 67:145]
node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 72:71] node _T_182 = and(_T_175, _T_181) @[el2_ifu_iccm_mem.scala 67:71]
node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] node _T_183 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] node _T_184 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 73:37] node _T_185 = eq(_T_183, _T_184) @[el2_ifu_iccm_mem.scala 68:37]
node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] node _T_186 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 73:99] node _T_187 = eq(_T_186, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 73:77] node _T_188 = and(_T_185, _T_187) @[el2_ifu_iccm_mem.scala 68:77]
node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 72:179] node _T_189 = or(_T_182, _T_188) @[el2_ifu_iccm_mem.scala 67:179]
node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] node _T_190 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] node _T_191 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] node _T_192 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 72:105] node _T_193 = eq(_T_191, _T_192) @[el2_ifu_iccm_mem.scala 67:105]
node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] node _T_194 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 72:169] node _T_195 = eq(_T_194, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 72:145] node _T_196 = and(_T_193, _T_195) @[el2_ifu_iccm_mem.scala 67:145]
node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 72:71] node _T_197 = and(_T_190, _T_196) @[el2_ifu_iccm_mem.scala 67:71]
node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] node _T_198 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] node _T_199 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 73:37] node _T_200 = eq(_T_198, _T_199) @[el2_ifu_iccm_mem.scala 68:37]
node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] node _T_201 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 73:99] node _T_202 = eq(_T_201, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 73:77] node _T_203 = and(_T_200, _T_202) @[el2_ifu_iccm_mem.scala 68:77]
node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 72:179] node _T_204 = or(_T_197, _T_203) @[el2_ifu_iccm_mem.scala 67:179]
node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] node _T_205 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] node _T_206 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] node _T_207 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 72:105] node _T_208 = eq(_T_206, _T_207) @[el2_ifu_iccm_mem.scala 67:105]
node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] node _T_209 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 72:169] node _T_210 = eq(_T_209, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 72:145] node _T_211 = and(_T_208, _T_210) @[el2_ifu_iccm_mem.scala 67:145]
node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 72:71] node _T_212 = and(_T_205, _T_211) @[el2_ifu_iccm_mem.scala 67:71]
node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] node _T_213 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] node _T_214 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 73:37] node _T_215 = eq(_T_213, _T_214) @[el2_ifu_iccm_mem.scala 68:37]
node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] node _T_216 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 73:99] node _T_217 = eq(_T_216, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 73:77] node _T_218 = and(_T_215, _T_217) @[el2_ifu_iccm_mem.scala 68:77]
node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 72:179] node _T_219 = or(_T_212, _T_218) @[el2_ifu_iccm_mem.scala 67:179]
node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 72:67] node _T_220 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 67:67]
node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 72:90] node _T_221 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 67:90]
node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 72:128] node _T_222 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 67:128]
node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 72:105] node _T_223 = eq(_T_221, _T_222) @[el2_ifu_iccm_mem.scala 67:105]
node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 72:163] node _T_224 = bits(io.iccm_rw_addr, 2, 1) @[el2_ifu_iccm_mem.scala 67:163]
node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 72:169] node _T_225 = eq(_T_224, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 67:169]
node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 72:145] node _T_226 = and(_T_223, _T_225) @[el2_ifu_iccm_mem.scala 67:145]
node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 72:71] node _T_227 = and(_T_220, _T_226) @[el2_ifu_iccm_mem.scala 67:71]
node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 73:22] node _T_228 = bits(addr_bank_inc, 14, 1) @[el2_ifu_iccm_mem.scala 68:22]
node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 73:60] node _T_229 = bits(redundant_address[0], 13, 0) @[el2_ifu_iccm_mem.scala 68:60]
node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 73:37] node _T_230 = eq(_T_228, _T_229) @[el2_ifu_iccm_mem.scala 68:37]
node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 73:93] node _T_231 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 68:93]
node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 73:99] node _T_232 = eq(_T_231, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 68:99]
node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 73:77] node _T_233 = and(_T_230, _T_232) @[el2_ifu_iccm_mem.scala 68:77]
node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 72:179] node _T_234 = or(_T_227, _T_233) @[el2_ifu_iccm_mem.scala 67:179]
node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58] node _T_235 = cat(_T_234, _T_219) @[Cat.scala 29:58]
node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58] node _T_236 = cat(_T_235, _T_204) @[Cat.scala 29:58]
node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58] node sel_red0 = cat(_T_236, _T_189) @[Cat.scala 29:58]
reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 75:27] reg sel_red0_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 70:27]
sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 75:27] sel_red0_q <= sel_red0 @[el2_ifu_iccm_mem.scala 70:27]
reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 76:27] reg sel_red1_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 71:27]
sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 76:27] sel_red1_q <= sel_red1 @[el2_ifu_iccm_mem.scala 71:27]
wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 77:28] wire redundant_data : UInt<39>[2] @[el2_ifu_iccm_mem.scala 72:28]
redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18] redundant_data[0] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 78:18] redundant_data[1] <= UInt<1>("h00") @[el2_ifu_iccm_mem.scala 73:18]
node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 80:47] node _T_237 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 75:47]
node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] node _T_238 = bits(_T_237, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 81:47] node _T_239 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 76:47]
node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] node _T_240 = bits(_T_239, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:47] node _T_241 = bits(sel_red0_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:47]
node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 82:36] node _T_242 = not(_T_241) @[el2_ifu_iccm_mem.scala 77:36]
node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 82:64] node _T_243 = bits(sel_red1_q, 0, 0) @[el2_ifu_iccm_mem.scala 77:64]
node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 82:53] node _T_244 = not(_T_243) @[el2_ifu_iccm_mem.scala 77:53]
node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 82:51] node _T_245 = and(_T_242, _T_244) @[el2_ifu_iccm_mem.scala 77:51]
node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] node _T_246 = bits(_T_245, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_247 = mux(_T_238, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_248 = mux(_T_240, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_249 = mux(_T_246, iccm_bank_dout[0], UInt<1>("h00")) @[Mux.scala 27:72]
@ -342,16 +338,16 @@ circuit el2_ifu_iccm_mem :
node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72] node _T_251 = or(_T_250, _T_249) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72] wire iccm_bank_dout_fn_0 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72] iccm_bank_dout_fn_0 <= _T_251 @[Mux.scala 27:72]
node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 80:47] node _T_252 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 75:47]
node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] node _T_253 = bits(_T_252, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 81:47] node _T_254 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 76:47]
node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] node _T_255 = bits(_T_254, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:47] node _T_256 = bits(sel_red0_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:47]
node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 82:36] node _T_257 = not(_T_256) @[el2_ifu_iccm_mem.scala 77:36]
node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 82:64] node _T_258 = bits(sel_red1_q, 1, 1) @[el2_ifu_iccm_mem.scala 77:64]
node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 82:53] node _T_259 = not(_T_258) @[el2_ifu_iccm_mem.scala 77:53]
node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 82:51] node _T_260 = and(_T_257, _T_259) @[el2_ifu_iccm_mem.scala 77:51]
node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] node _T_261 = bits(_T_260, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_262 = mux(_T_253, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_263 = mux(_T_255, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_264 = mux(_T_261, iccm_bank_dout[1], UInt<1>("h00")) @[Mux.scala 27:72]
@ -359,16 +355,16 @@ circuit el2_ifu_iccm_mem :
node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72] node _T_266 = or(_T_265, _T_264) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72] wire iccm_bank_dout_fn_1 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72] iccm_bank_dout_fn_1 <= _T_266 @[Mux.scala 27:72]
node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 80:47] node _T_267 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 75:47]
node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] node _T_268 = bits(_T_267, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 81:47] node _T_269 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 76:47]
node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] node _T_270 = bits(_T_269, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:47] node _T_271 = bits(sel_red0_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:47]
node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 82:36] node _T_272 = not(_T_271) @[el2_ifu_iccm_mem.scala 77:36]
node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 82:64] node _T_273 = bits(sel_red1_q, 2, 2) @[el2_ifu_iccm_mem.scala 77:64]
node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 82:53] node _T_274 = not(_T_273) @[el2_ifu_iccm_mem.scala 77:53]
node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 82:51] node _T_275 = and(_T_272, _T_274) @[el2_ifu_iccm_mem.scala 77:51]
node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] node _T_276 = bits(_T_275, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_277 = mux(_T_268, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_278 = mux(_T_270, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72] node _T_279 = mux(_T_276, iccm_bank_dout[2], UInt<1>("h00")) @[Mux.scala 27:72]
@ -376,16 +372,16 @@ circuit el2_ifu_iccm_mem :
node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72] node _T_281 = or(_T_280, _T_279) @[Mux.scala 27:72]
wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72] wire iccm_bank_dout_fn_2 : UInt<39> @[Mux.scala 27:72]
iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72] iccm_bank_dout_fn_2 <= _T_281 @[Mux.scala 27:72]
node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 80:47] node _T_282 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 75:47]
node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 80:51] node _T_283 = bits(_T_282, 0, 0) @[el2_ifu_iccm_mem.scala 75:51]
node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 81:47] node _T_284 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 76:47]
node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 81:51] node _T_285 = bits(_T_284, 0, 0) @[el2_ifu_iccm_mem.scala 76:51]
node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:47] node _T_286 = bits(sel_red0_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:47]
node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 82:36] node _T_287 = not(_T_286) @[el2_ifu_iccm_mem.scala 77:36]
node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 82:64] node _T_288 = bits(sel_red1_q, 3, 3) @[el2_ifu_iccm_mem.scala 77:64]
node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 82:53] node _T_289 = not(_T_288) @[el2_ifu_iccm_mem.scala 77:53]
node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 82:51] node _T_290 = and(_T_287, _T_289) @[el2_ifu_iccm_mem.scala 77:51]
node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 82:69] node _T_291 = bits(_T_290, 0, 0) @[el2_ifu_iccm_mem.scala 77:69]
node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72] node _T_292 = mux(_T_283, redundant_data[1], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72] node _T_293 = mux(_T_285, redundant_data[0], UInt<1>("h00")) @[Mux.scala 27:72]
node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72] node _T_294 = mux(_T_291, iccm_bank_dout[3], UInt<1>("h00")) @[Mux.scala 27:72]
@ -395,38 +391,38 @@ circuit el2_ifu_iccm_mem :
iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72] iccm_bank_dout_fn_3 <= _T_296 @[Mux.scala 27:72]
wire redundant_lru : UInt<1> wire redundant_lru : UInt<1>
redundant_lru <= UInt<1>("h00") redundant_lru <= UInt<1>("h00")
node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 84:20] node _T_297 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 79:20]
node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 84:35] node r0_addr_en = and(_T_297, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 79:35]
node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 85:35] node r1_addr_en = and(redundant_lru, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 80:35]
node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 86:63] node _T_298 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 81:63]
node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 86:78] node _T_299 = orr(sel_red1) @[el2_ifu_iccm_mem.scala 81:78]
node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 86:67] node _T_300 = or(_T_298, _T_299) @[el2_ifu_iccm_mem.scala 81:67]
node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 86:83] node _T_301 = and(_T_300, io.iccm_rden) @[el2_ifu_iccm_mem.scala 81:83]
node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 86:98] node _T_302 = and(_T_301, io.iccm_correction_state) @[el2_ifu_iccm_mem.scala 81:98]
node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 86:50] node redundant_lru_en = or(io.iccm_buf_correct_ecc, _T_302) @[el2_ifu_iccm_mem.scala 81:50]
node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:55] node _T_303 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:55]
node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 87:84] node _T_304 = orr(sel_red0) @[el2_ifu_iccm_mem.scala 82:84]
node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 87:74] node _T_305 = mux(_T_304, UInt<1>("h01"), UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 82:74]
node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 87:29] node redundant_lru_in = mux(io.iccm_buf_correct_ecc, _T_303, _T_305) @[el2_ifu_iccm_mem.scala 82:29]
reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_306 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when redundant_lru_en : @[Reg.scala 28:19] when redundant_lru_en : @[Reg.scala 28:19]
_T_306 <= redundant_lru_in @[Reg.scala 28:23] _T_306 <= redundant_lru_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 88:17] redundant_lru <= _T_306 @[el2_ifu_iccm_mem.scala 83:17]
node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 89:52] node _T_307 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 84:52]
reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_308 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when r0_addr_en : @[Reg.scala 28:19] when r0_addr_en : @[Reg.scala 28:19]
_T_308 <= _T_307 @[Reg.scala 28:23] _T_308 <= _T_307 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 89:24] redundant_address[0] <= _T_308 @[el2_ifu_iccm_mem.scala 84:24]
node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 90:52] node _T_309 = bits(io.iccm_rw_addr, 14, 1) @[el2_ifu_iccm_mem.scala 85:52]
node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 90:85] node _T_310 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 85:85]
reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_311 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_310 : @[Reg.scala 28:19] when _T_310 : @[Reg.scala 28:19]
_T_311 <= _T_309 @[Reg.scala 28:23] _T_311 <= _T_309 @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 90:24] redundant_address[1] <= _T_311 @[el2_ifu_iccm_mem.scala 85:24]
node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 91:57] node _T_312 = bits(r1_addr_en, 0, 0) @[el2_ifu_iccm_mem.scala 86:57]
reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_313 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_312 : @[Reg.scala 28:19] when _T_312 : @[Reg.scala 28:19]
_T_313 <= UInt<1>("h01") @[Reg.scala 28:23] _T_313 <= UInt<1>("h01") @[Reg.scala 28:23]
@ -436,89 +432,89 @@ circuit el2_ifu_iccm_mem :
_T_314 <= UInt<1>("h01") @[Reg.scala 28:23] _T_314 <= UInt<1>("h01") @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58] node _T_315 = cat(_T_313, _T_314) @[Cat.scala 29:58]
redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 91:19] redundant_valid <= _T_315 @[el2_ifu_iccm_mem.scala 86:19]
node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 93:45] node _T_316 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 88:45]
node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 93:85] node _T_317 = bits(redundant_address[0], 13, 1) @[el2_ifu_iccm_mem.scala 88:85]
node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 93:61] node _T_318 = eq(_T_316, _T_317) @[el2_ifu_iccm_mem.scala 88:61]
node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 94:22] node _T_319 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 89:22]
node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 94:48] node _T_320 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 89:48]
node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 94:26] node _T_321 = and(_T_319, _T_320) @[el2_ifu_iccm_mem.scala 89:26]
node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 94:70] node _T_322 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 89:70]
node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 94:75] node _T_323 = eq(_T_322, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 89:75]
node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 94:52] node _T_324 = or(_T_321, _T_323) @[el2_ifu_iccm_mem.scala 89:52]
node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 93:102] node _T_325 = and(_T_318, _T_324) @[el2_ifu_iccm_mem.scala 88:102]
node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 94:101] node _T_326 = bits(redundant_valid, 0, 0) @[el2_ifu_iccm_mem.scala 89:101]
node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 94:84] node _T_327 = and(_T_325, _T_326) @[el2_ifu_iccm_mem.scala 89:84]
node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 94:105] node _T_328 = and(_T_327, io.iccm_wren) @[el2_ifu_iccm_mem.scala 89:105]
node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 95:6] node _T_329 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 90:6]
node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 95:21] node _T_330 = and(_T_329, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 90:21]
node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 94:121] node redundant_data0_en = or(_T_328, _T_330) @[el2_ifu_iccm_mem.scala 89:121]
node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:49] node _T_331 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 91:49]
node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:73] node _T_332 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:73]
node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 96:52] node _T_333 = and(_T_331, _T_332) @[el2_ifu_iccm_mem.scala 91:52]
node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 96:100] node _T_334 = bits(redundant_address[0], 0, 0) @[el2_ifu_iccm_mem.scala 91:100]
node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:122] node _T_335 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 91:122]
node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:127] node _T_336 = eq(_T_335, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 91:127]
node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 96:104] node _T_337 = and(_T_334, _T_336) @[el2_ifu_iccm_mem.scala 91:104]
node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 96:78] node _T_338 = or(_T_333, _T_337) @[el2_ifu_iccm_mem.scala 91:78]
node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 96:137] node _T_339 = bits(_T_338, 0, 0) @[el2_ifu_iccm_mem.scala 91:137]
node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 97:20] node _T_340 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 92:20]
node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 97:44] node _T_341 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 92:44]
node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 96:31] node redundant_data0_in = mux(_T_339, _T_340, _T_341) @[el2_ifu_iccm_mem.scala 91:31]
node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 98:78] node _T_342 = bits(redundant_data0_en, 0, 0) @[el2_ifu_iccm_mem.scala 93:78]
reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_343 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_342 : @[Reg.scala 28:19] when _T_342 : @[Reg.scala 28:19]
_T_343 <= redundant_data0_in @[Reg.scala 28:23] _T_343 <= redundant_data0_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 98:21] redundant_data[0] <= _T_343 @[el2_ifu_iccm_mem.scala 93:21]
node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 100:45] node _T_344 = bits(io.iccm_rw_addr, 14, 2) @[el2_ifu_iccm_mem.scala 95:45]
node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 100:85] node _T_345 = bits(redundant_address[1], 13, 1) @[el2_ifu_iccm_mem.scala 95:85]
node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 100:61] node _T_346 = eq(_T_344, _T_345) @[el2_ifu_iccm_mem.scala 95:61]
node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 101:22] node _T_347 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 96:22]
node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 101:48] node _T_348 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 96:48]
node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 101:26] node _T_349 = and(_T_347, _T_348) @[el2_ifu_iccm_mem.scala 96:26]
node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 101:70] node _T_350 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 96:70]
node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 101:75] node _T_351 = eq(_T_350, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 96:75]
node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 101:52] node _T_352 = or(_T_349, _T_351) @[el2_ifu_iccm_mem.scala 96:52]
node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 100:102] node _T_353 = and(_T_346, _T_352) @[el2_ifu_iccm_mem.scala 95:102]
node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 101:101] node _T_354 = bits(redundant_valid, 1, 1) @[el2_ifu_iccm_mem.scala 96:101]
node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 101:84] node _T_355 = and(_T_353, _T_354) @[el2_ifu_iccm_mem.scala 96:84]
node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 101:105] node _T_356 = and(_T_355, io.iccm_wren) @[el2_ifu_iccm_mem.scala 96:105]
node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 102:6] node _T_357 = eq(redundant_lru, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 97:6]
node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 102:21] node _T_358 = and(_T_357, io.iccm_buf_correct_ecc) @[el2_ifu_iccm_mem.scala 97:21]
node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 101:121] node redundant_data1_en = or(_T_356, _T_358) @[el2_ifu_iccm_mem.scala 96:121]
node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 103:49] node _T_359 = bits(io.iccm_rw_addr, 1, 1) @[el2_ifu_iccm_mem.scala 98:49]
node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:73] node _T_360 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:73]
node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 103:52] node _T_361 = and(_T_359, _T_360) @[el2_ifu_iccm_mem.scala 98:52]
node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 103:100] node _T_362 = bits(redundant_address[1], 0, 0) @[el2_ifu_iccm_mem.scala 98:100]
node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 103:122] node _T_363 = bits(io.iccm_wr_size, 1, 0) @[el2_ifu_iccm_mem.scala 98:122]
node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 103:127] node _T_364 = eq(_T_363, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 98:127]
node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 103:104] node _T_365 = and(_T_362, _T_364) @[el2_ifu_iccm_mem.scala 98:104]
node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 103:78] node _T_366 = or(_T_361, _T_365) @[el2_ifu_iccm_mem.scala 98:78]
node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 103:137] node _T_367 = bits(_T_366, 0, 0) @[el2_ifu_iccm_mem.scala 98:137]
node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 104:20] node _T_368 = bits(io.iccm_wr_data, 77, 39) @[el2_ifu_iccm_mem.scala 99:20]
node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 104:44] node _T_369 = bits(io.iccm_wr_data, 38, 0) @[el2_ifu_iccm_mem.scala 99:44]
node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 103:31] node redundant_data1_in = mux(_T_367, _T_368, _T_369) @[el2_ifu_iccm_mem.scala 98:31]
node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 105:78] node _T_370 = bits(redundant_data1_en, 0, 0) @[el2_ifu_iccm_mem.scala 100:78]
reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] reg _T_371 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
when _T_370 : @[Reg.scala 28:19] when _T_370 : @[Reg.scala 28:19]
_T_371 <= redundant_data1_in @[Reg.scala 28:23] _T_371 <= redundant_data1_in @[Reg.scala 28:23]
skip @[Reg.scala 28:19] skip @[Reg.scala 28:19]
redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 105:21] redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21]
node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 107:50] node _T_372 = bits(io.iccm_rw_addr, 3, 1) @[el2_ifu_iccm_mem.scala 102:50]
reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 107:34] reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34]
iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 107:34] iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34]
node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 108:48] node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48]
reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 108:34] reg iccm_rd_addr_hi_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 103:34]
iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 108:34] iccm_rd_addr_hi_q <= _T_373 @[el2_ifu_iccm_mem.scala 103:34]
node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:86] node _T_374 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 105:86]
node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] node _T_375 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:86] node _T_376 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 105:86]
node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] node _T_377 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:86] node _T_378 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 105:86]
node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] node _T_379 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:86] node _T_380 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 105:86]
node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 110:115] node _T_381 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 105:115]
node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72] node _T_382 = mux(_T_374, _T_375, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72] node _T_383 = mux(_T_376, _T_377, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72] node _T_384 = mux(_T_378, _T_379, UInt<1>("h00")) @[Mux.scala 27:72]
@ -528,18 +524,18 @@ circuit el2_ifu_iccm_mem :
node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72] node _T_388 = or(_T_387, _T_385) @[Mux.scala 27:72]
wire _T_389 : UInt<32> @[Mux.scala 27:72] wire _T_389 : UInt<32> @[Mux.scala 27:72]
_T_389 <= _T_388 @[Mux.scala 27:72] _T_389 <= _T_388 @[Mux.scala 27:72]
node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] node _T_390 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 111:77] node _T_391 = eq(_T_390, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] node _T_392 = bits(iccm_bank_dout_fn_0, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] node _T_393 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 111:77] node _T_394 = eq(_T_393, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] node _T_395 = bits(iccm_bank_dout_fn_1, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] node _T_396 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 111:77] node _T_397 = eq(_T_396, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] node _T_398 = bits(iccm_bank_dout_fn_2, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 111:59] node _T_399 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 106:59]
node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 111:77] node _T_400 = eq(_T_399, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 106:77]
node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 111:106] node _T_401 = bits(iccm_bank_dout_fn_3, 31, 0) @[el2_ifu_iccm_mem.scala 106:106]
node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72] node _T_402 = mux(_T_391, _T_392, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72] node _T_403 = mux(_T_394, _T_395, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72] node _T_404 = mux(_T_397, _T_398, UInt<1>("h00")) @[Mux.scala 27:72]
@ -550,17 +546,17 @@ circuit el2_ifu_iccm_mem :
wire _T_409 : UInt<32> @[Mux.scala 27:72] wire _T_409 : UInt<32> @[Mux.scala 27:72]
_T_409 <= _T_408 @[Mux.scala 27:72] _T_409 <= _T_408 @[Mux.scala 27:72]
node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58] node iccm_rd_data_pre = cat(_T_389, _T_409) @[Cat.scala 29:58]
node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 112:43] node _T_410 = bits(iccm_rd_addr_lo_q, 0, 0) @[el2_ifu_iccm_mem.scala 108:43]
node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 112:53] node _T_411 = bits(_T_410, 0, 0) @[el2_ifu_iccm_mem.scala 108:53]
node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12] node _T_412 = mux(UInt<1>("h00"), UInt<16>("h0ffff"), UInt<16>("h00")) @[Bitwise.scala 72:12]
node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 112:89] node _T_413 = bits(iccm_rd_data_pre, 63, 16) @[el2_ifu_iccm_mem.scala 108:89]
node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58] node _T_414 = cat(_T_412, _T_413) @[Cat.scala 29:58]
node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 112:25] node _T_415 = mux(_T_411, _T_414, iccm_rd_data_pre) @[el2_ifu_iccm_mem.scala 108:25]
io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 112:19] io.iccm_rd_data <= _T_415 @[el2_ifu_iccm_mem.scala 108:19]
node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 113:85] node _T_416 = eq(iccm_rd_addr_hi_q, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 113:85] node _T_417 = eq(iccm_rd_addr_hi_q, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 113:85] node _T_418 = eq(iccm_rd_addr_hi_q, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 113:85] node _T_419 = eq(iccm_rd_addr_hi_q, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 109:85]
node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_420 = mux(_T_416, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_421 = mux(_T_417, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] node _T_422 = mux(_T_418, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
@ -570,14 +566,14 @@ circuit el2_ifu_iccm_mem :
node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72] node _T_426 = or(_T_425, _T_423) @[Mux.scala 27:72]
wire _T_427 : UInt<39> @[Mux.scala 27:72] wire _T_427 : UInt<39> @[Mux.scala 27:72]
_T_427 <= _T_426 @[Mux.scala 27:72] _T_427 <= _T_426 @[Mux.scala 27:72]
node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] node _T_428 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 114:79] node _T_429 = eq(_T_428, UInt<1>("h00")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] node _T_430 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 114:79] node _T_431 = eq(_T_430, UInt<1>("h01")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] node _T_432 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 114:79] node _T_433 = eq(_T_432, UInt<2>("h02")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 114:61] node _T_434 = bits(iccm_rd_addr_lo_q, 1, 0) @[el2_ifu_iccm_mem.scala 110:61]
node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 114:79] node _T_435 = eq(_T_434, UInt<2>("h03")) @[el2_ifu_iccm_mem.scala 110:79]
node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72] node _T_436 = mux(_T_429, iccm_bank_dout_fn_0, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72] node _T_437 = mux(_T_431, iccm_bank_dout_fn_1, UInt<1>("h00")) @[Mux.scala 27:72]
node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72] node _T_438 = mux(_T_433, iccm_bank_dout_fn_2, UInt<1>("h00")) @[Mux.scala 27:72]
@ -588,5 +584,5 @@ circuit el2_ifu_iccm_mem :
wire _T_443 : UInt<39> @[Mux.scala 27:72] wire _T_443 : UInt<39> @[Mux.scala 27:72]
_T_443 <= _T_442 @[Mux.scala 27:72] _T_443 <= _T_442 @[Mux.scala 27:72]
node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58] node _T_444 = cat(_T_427, _T_443) @[Cat.scala 29:58]
io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 113:23] io.iccm_rd_data_ecc <= _T_444 @[el2_ifu_iccm_mem.scala 109:23]

190
el2_ifu_iccm_mem.v
View File

@ -11,11 +11,7 @@ module el2_ifu_iccm_mem(
input [77:0] io_iccm_wr_data, input [77:0] io_iccm_wr_data,
output [63:0] io_iccm_rd_data, output [63:0] io_iccm_rd_data,
output [77:0] io_iccm_rd_data_ecc, output [77:0] io_iccm_rd_data_ecc,
input io_scan_mode, input io_scan_mode
output [11:0] io_iccm_bank_addr_0,
output [11:0] io_iccm_bank_addr_1,
output [11:0] io_iccm_bank_addr_2,
output [11:0] io_iccm_bank_addr_3
); );
`ifdef RANDOMIZE_MEM_INIT `ifdef RANDOMIZE_MEM_INIT
reg [63:0] _RAND_0; reg [63:0] _RAND_0;
@ -134,50 +130,50 @@ module el2_ifu_iccm_mem(
reg _T_314; // @[Reg.scala 27:20] reg _T_314; // @[Reg.scala 27:20]
wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58] wire [1:0] redundant_valid = {_T_313,_T_314}; // @[Cat.scala 29:58]
reg [13:0] redundant_address_1; // @[Reg.scala 27:20] reg [13:0] redundant_address_1; // @[Reg.scala 27:20]
wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 70:105] wire _T_116 = io_iccm_rw_addr[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 65:105]
wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 70:145] wire _T_119 = _T_116 & _T_10; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 70:71] wire _T_120 = redundant_valid[1] & _T_119; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 71:37] wire _T_123 = addr_bank_inc[14:1] == redundant_address_1; // @[el2_ifu_iccm_mem.scala 66:37]
wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 71:77] wire _T_126 = _T_123 & _T_12; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 70:179] wire _T_127 = _T_120 | _T_126; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 70:145] wire _T_134 = _T_116 & _T_15; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 70:71] wire _T_135 = redundant_valid[1] & _T_134; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 71:77] wire _T_141 = _T_123 & _T_17; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 70:179] wire _T_142 = _T_135 | _T_141; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 70:145] wire _T_149 = _T_116 & _T_20; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 70:71] wire _T_150 = redundant_valid[1] & _T_149; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 71:77] wire _T_156 = _T_123 & _T_22; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 70:179] wire _T_157 = _T_150 | _T_156; // @[el2_ifu_iccm_mem.scala 65:179]
wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 70:145] wire _T_164 = _T_116 & _T_25; // @[el2_ifu_iccm_mem.scala 65:145]
wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 70:71] wire _T_165 = redundant_valid[1] & _T_164; // @[el2_ifu_iccm_mem.scala 65:71]
wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 71:77] wire _T_171 = _T_123 & _T_27; // @[el2_ifu_iccm_mem.scala 66:77]
wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 70:179] wire _T_172 = _T_165 | _T_171; // @[el2_ifu_iccm_mem.scala 65:179]
wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58] wire [3:0] sel_red1 = {_T_172,_T_157,_T_142,_T_127}; // @[Cat.scala 29:58]
reg [13:0] redundant_address_0; // @[Reg.scala 27:20] reg [13:0] redundant_address_0; // @[Reg.scala 27:20]
wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 72:105] wire _T_178 = io_iccm_rw_addr[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 67:105]
wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 72:145] wire _T_181 = _T_178 & _T_10; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 72:71] wire _T_182 = redundant_valid[0] & _T_181; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 73:37] wire _T_185 = addr_bank_inc[14:1] == redundant_address_0; // @[el2_ifu_iccm_mem.scala 68:37]
wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 73:77] wire _T_188 = _T_185 & _T_12; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 72:179] wire _T_189 = _T_182 | _T_188; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 72:145] wire _T_196 = _T_178 & _T_15; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 72:71] wire _T_197 = redundant_valid[0] & _T_196; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 73:77] wire _T_203 = _T_185 & _T_17; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 72:179] wire _T_204 = _T_197 | _T_203; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 72:145] wire _T_211 = _T_178 & _T_20; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 72:71] wire _T_212 = redundant_valid[0] & _T_211; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 73:77] wire _T_218 = _T_185 & _T_22; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 72:179] wire _T_219 = _T_212 | _T_218; // @[el2_ifu_iccm_mem.scala 67:179]
wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 72:145] wire _T_226 = _T_178 & _T_25; // @[el2_ifu_iccm_mem.scala 67:145]
wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 72:71] wire _T_227 = redundant_valid[0] & _T_226; // @[el2_ifu_iccm_mem.scala 67:71]
wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 73:77] wire _T_233 = _T_185 & _T_27; // @[el2_ifu_iccm_mem.scala 68:77]
wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 72:179] wire _T_234 = _T_227 | _T_233; // @[el2_ifu_iccm_mem.scala 67:179]
wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58] wire [3:0] sel_red0 = {_T_234,_T_219,_T_204,_T_189}; // @[Cat.scala 29:58]
reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 75:27] reg [3:0] sel_red0_q; // @[el2_ifu_iccm_mem.scala 70:27]
reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 76:27] reg [3:0] sel_red1_q; // @[el2_ifu_iccm_mem.scala 71:27]
wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 82:36] wire _T_242 = ~sel_red0_q[0]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 82:53] wire _T_244 = ~sel_red1_q[0]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 82:51] wire _T_245 = _T_242 & _T_244; // @[el2_ifu_iccm_mem.scala 77:51]
reg [38:0] redundant_data_1; // @[Reg.scala 27:20] reg [38:0] redundant_data_1; // @[Reg.scala 27:20]
wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_247 = sel_red1_q[0] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
reg [38:0] redundant_data_0; // @[Reg.scala 27:20] reg [38:0] redundant_data_0; // @[Reg.scala 27:20]
@ -185,66 +181,66 @@ module el2_ifu_iccm_mem(
wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_249 = _T_245 ? iccm_bank_dout_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72] wire [38:0] _T_250 = _T_247 | _T_248; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72] wire [38:0] iccm_bank_dout_fn_0 = _T_250 | _T_249; // @[Mux.scala 27:72]
wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 82:36] wire _T_257 = ~sel_red0_q[1]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 82:53] wire _T_259 = ~sel_red1_q[1]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 82:51] wire _T_260 = _T_257 & _T_259; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_262 = sel_red1_q[1] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_263 = sel_red0_q[1] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_264 = _T_260 ? iccm_bank_dout_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72] wire [38:0] _T_265 = _T_262 | _T_263; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72] wire [38:0] iccm_bank_dout_fn_1 = _T_265 | _T_264; // @[Mux.scala 27:72]
wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 82:36] wire _T_272 = ~sel_red0_q[2]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 82:53] wire _T_274 = ~sel_red1_q[2]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 82:51] wire _T_275 = _T_272 & _T_274; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_277 = sel_red1_q[2] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_278 = sel_red0_q[2] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_279 = _T_275 ? iccm_bank_dout_2 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72] wire [38:0] _T_280 = _T_277 | _T_278; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72] wire [38:0] iccm_bank_dout_fn_2 = _T_280 | _T_279; // @[Mux.scala 27:72]
wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 82:36] wire _T_287 = ~sel_red0_q[3]; // @[el2_ifu_iccm_mem.scala 77:36]
wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 82:53] wire _T_289 = ~sel_red1_q[3]; // @[el2_ifu_iccm_mem.scala 77:53]
wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 82:51] wire _T_290 = _T_287 & _T_289; // @[el2_ifu_iccm_mem.scala 77:51]
wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_292 = sel_red1_q[3] ? redundant_data_1 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_293 = sel_red0_q[3] ? redundant_data_0 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72] wire [38:0] _T_294 = _T_290 ? iccm_bank_dout_3 : 39'h0; // @[Mux.scala 27:72]
wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72] wire [38:0] _T_295 = _T_292 | _T_293; // @[Mux.scala 27:72]
wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72] wire [38:0] iccm_bank_dout_fn_3 = _T_295 | _T_294; // @[Mux.scala 27:72]
reg redundant_lru; // @[Reg.scala 27:20] reg redundant_lru; // @[Reg.scala 27:20]
wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 84:20] wire _T_297 = ~redundant_lru; // @[el2_ifu_iccm_mem.scala 79:20]
wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 84:35] wire r0_addr_en = _T_297 & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 79:35]
wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 85:35] wire r1_addr_en = redundant_lru & io_iccm_buf_correct_ecc; // @[el2_ifu_iccm_mem.scala 80:35]
wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 86:63] wire _T_298 = |sel_red0; // @[el2_ifu_iccm_mem.scala 81:63]
wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 86:78] wire _T_299 = |sel_red1; // @[el2_ifu_iccm_mem.scala 81:78]
wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 86:67] wire _T_300 = _T_298 | _T_299; // @[el2_ifu_iccm_mem.scala 81:67]
wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 86:83] wire _T_301 = _T_300 & io_iccm_rden; // @[el2_ifu_iccm_mem.scala 81:83]
wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 86:98] wire _T_302 = _T_301 & io_iccm_correction_state; // @[el2_ifu_iccm_mem.scala 81:98]
wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 86:50] wire redundant_lru_en = io_iccm_buf_correct_ecc | _T_302; // @[el2_ifu_iccm_mem.scala 81:50]
wire _GEN_27 = r1_addr_en | _T_313; // @[Reg.scala 28:19] wire _GEN_27 = r1_addr_en | _T_313; // @[Reg.scala 28:19]
wire _GEN_28 = r0_addr_en | _T_314; // @[Reg.scala 28:19] wire _GEN_28 = r0_addr_en | _T_314; // @[Reg.scala 28:19]
wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 93:61] wire _T_318 = io_iccm_rw_addr[14:2] == redundant_address_0[13:1]; // @[el2_ifu_iccm_mem.scala 88:61]
wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 94:26] wire _T_321 = io_iccm_rw_addr[1] & redundant_address_0[0]; // @[el2_ifu_iccm_mem.scala 89:26]
wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 94:52] wire _T_324 = _T_321 | _T_1; // @[el2_ifu_iccm_mem.scala 89:52]
wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 93:102] wire _T_325 = _T_318 & _T_324; // @[el2_ifu_iccm_mem.scala 88:102]
wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 94:84] wire _T_327 = _T_325 & redundant_valid[0]; // @[el2_ifu_iccm_mem.scala 89:84]
wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 94:105] wire _T_328 = _T_327 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 89:105]
wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 94:121] wire redundant_data0_en = _T_328 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 89:121]
wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 96:104] wire _T_337 = redundant_address_0[0] & _T_1; // @[el2_ifu_iccm_mem.scala 91:104]
wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 96:78] wire _T_338 = _T_321 | _T_337; // @[el2_ifu_iccm_mem.scala 91:78]
wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 100:61] wire _T_346 = io_iccm_rw_addr[14:2] == redundant_address_1[13:1]; // @[el2_ifu_iccm_mem.scala 95:61]
wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 101:26] wire _T_349 = io_iccm_rw_addr[1] & redundant_address_1[0]; // @[el2_ifu_iccm_mem.scala 96:26]
wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 101:52] wire _T_352 = _T_349 | _T_1; // @[el2_ifu_iccm_mem.scala 96:52]
wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 100:102] wire _T_353 = _T_346 & _T_352; // @[el2_ifu_iccm_mem.scala 95:102]
wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 101:84] wire _T_355 = _T_353 & redundant_valid[1]; // @[el2_ifu_iccm_mem.scala 96:84]
wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 101:105] wire _T_356 = _T_355 & io_iccm_wren; // @[el2_ifu_iccm_mem.scala 96:105]
wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 101:121] wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121]
wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 103:104] wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104]
wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 103:78] wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78]
reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 107:34] reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34]
reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 108:34] reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34]
wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 110:86] wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86]
wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 110:86] wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86]
wire _T_378 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 110:86] wire _T_378 = iccm_rd_addr_hi_q == 2'h2; // @[el2_ifu_iccm_mem.scala 105:86]
wire _T_380 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 110:86] wire _T_380 = iccm_rd_addr_hi_q == 2'h3; // @[el2_ifu_iccm_mem.scala 105:86]
wire [31:0] _T_382 = _T_374 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_382 = _T_374 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_383 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_383 = _T_376 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_384 = _T_378 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_384 = _T_378 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
@ -252,10 +248,10 @@ module el2_ifu_iccm_mem(
wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72] wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72]
wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72] wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72]
wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72] wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72]
wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 111:77] wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 111:77] wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 111:77] wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77]
wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 111:77] wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77]
wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72]
wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72]
@ -303,12 +299,8 @@ module el2_ifu_iccm_mem(
assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83; assign _T_88__T_104_addr = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83;
assign _T_88__T_104_mask = 1'h1; assign _T_88__T_104_mask = 1'h1;
assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3; assign _T_88__T_104_en = iccm_clken_3 & wren_bank_3;
assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_414 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 112:19] assign io_iccm_rd_data = iccm_rd_addr_lo_q[0] ? _T_414 : iccm_rd_data_pre; // @[el2_ifu_iccm_mem.scala 22:19 el2_ifu_iccm_mem.scala 108:19]
assign io_iccm_rd_data_ecc = {_T_426,_T_442}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 113:23] assign io_iccm_rd_data_ecc = {_T_426,_T_442}; // @[el2_ifu_iccm_mem.scala 23:23 el2_ifu_iccm_mem.scala 109:23]
assign io_iccm_bank_addr_0 = wren_bank_0 ? io_iccm_rw_addr[14:3] : _T_59; // @[el2_ifu_iccm_mem.scala 61:21]
assign io_iccm_bank_addr_1 = wren_bank_1 ? io_iccm_rw_addr[14:3] : _T_67; // @[el2_ifu_iccm_mem.scala 61:21]
assign io_iccm_bank_addr_2 = wren_bank_2 ? io_iccm_rw_addr[14:3] : _T_75; // @[el2_ifu_iccm_mem.scala 61:21]
assign io_iccm_bank_addr_3 = wren_bank_3 ? io_iccm_rw_addr[14:3] : _T_83; // @[el2_ifu_iccm_mem.scala 61:21]
`ifdef RANDOMIZE_GARBAGE_ASSIGN `ifdef RANDOMIZE_GARBAGE_ASSIGN
`define RANDOMIZE `define RANDOMIZE
`endif `endif
@ -524,7 +516,7 @@ end // initial
if (reset) begin if (reset) begin
iccm_rd_addr_lo_q <= 3'h0; iccm_rd_addr_lo_q <= 3'h0;
end else begin end else begin
iccm_rd_addr_lo_q <= io_iccm_rw_addr[2:0]; iccm_rd_addr_lo_q <= io_iccm_rw_addr[3:1];
end end
if (reset) begin if (reset) begin
iccm_rd_addr_hi_q <= 2'h0; iccm_rd_addr_hi_q <= 2'h0;

12
src/main/scala/ifu/el2_ifu_iccm_mem.scala
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@ -17,7 +17,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
val iccm_rd_data = Output(UInt(64.W)) val iccm_rd_data = Output(UInt(64.W))
val iccm_rd_data_ecc = Output(UInt(78.W)) val iccm_rd_data_ecc = Output(UInt(78.W))
val scan_mode = Input(Bool()) val scan_mode = Input(Bool())
val iccm_bank_addr = Output(Vec(ICCM_NUM_BANKS, UInt())) // val iccm_bank_addr = Output(Vec(ICCM_NUM_BANKS, UInt()))
}) })
io.iccm_rd_data := 0.U io.iccm_rd_data := 0.U
io.iccm_rd_data_ecc := 0.U io.iccm_rd_data_ecc := 0.U
@ -54,11 +54,6 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)} for(i<-0 until ICCM_NUM_BANKS) when(write_vec(i)) {iccm_mem(i)(addr_bank(i)) := iccm_bank_wr_data(i)}
for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegEnable(iccm_mem(i)(addr_bank(i)),0.U,read_enable(i))} for(i<-0 until ICCM_NUM_BANKS) {iccm_bank_dout(i) := RegEnable(iccm_mem(i)(addr_bank(i)),0.U,read_enable(i))}
//(0 until ICCM_NUM_BANKS).map(i=> )
// iccm_bank_dout(i) := RegNext(inter(i))
io.iccm_bank_addr := addr_bank
@ -104,15 +99,18 @@ class el2_ifu_iccm_mem extends Module with el2_lib {
io.iccm_wr_data(77,39), io.iccm_wr_data(38,0)) io.iccm_wr_data(77,39), io.iccm_wr_data(38,0))
redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool) redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool)
val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U) val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI,1), 0.U)
val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U) val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U)
val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))), val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i)(31,0)))) Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i)(31,0))))
io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre) io.iccm_rd_data := Mux(iccm_rd_addr_lo_q(0).asBool(),Cat(Fill(16,0.U),iccm_rd_data_pre(63,16)) ,iccm_rd_data_pre)
io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))), io.iccm_rd_data_ecc :=Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i))),
Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i)))) Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_lo_q(ICCM_BANK_HI-2,0)===i.U)->iccm_bank_dout_fn(i))))
} }
object ifu_iccm extends App { object ifu_iccm extends App {
println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_iccm_mem())) println((new chisel3.stage.ChiselStage).emitVerilog(new el2_ifu_iccm_mem()))
} }

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target/scala-2.12/classes/ifu/el2_ifu_iccm_mem$$anon$1.class
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target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class
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target/scala-2.12/classes/ifu/ifu_iccm$.class
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target/scala-2.12/classes/ifu/ifu_iccm$delayedInit$body.class
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