Update el2_param.scala
This commit is contained in:
Junaid Ahmed
GitHub
parent
fa1a39200a
commit
3062c9343e
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@ -6,7 +6,7 @@ object pt{
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val BHT_ADDR_LO = "h2".U(2.W)
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val BHT_ADDR_LO = "h2".U(2.W)
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val BHT_ARRAY_DEPTH = "h100".U(11.W)
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val BHT_ARRAY_DEPTH = "h100".U(11.W)
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val BHT_GHR_HASH_1 = "h0".U(1.W)
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val BHT_GHR_HASH_1 = "h0".U(1.W)
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val BHT_GHR_SIZE = "8h".U(4.W)
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val BHT_GHR_SIZE = "h8".U(4.W)
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val BHT_SIZE = "h200".U(12.W)
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val BHT_SIZE = "h200".U(12.W)
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val BTB_ADDR_HI = "h09".U(5.W)
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val BTB_ADDR_HI = "h09".U(5.W)
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val BTB_ADDR_LO = "h2".U(2.W)
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val BTB_ADDR_LO = "h2".U(2.W)
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@ -156,3 +156,162 @@ object pt{
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val SB_BUS_TAG = "h1".U(4.W)
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val SB_BUS_TAG = "h1".U(4.W)
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val TIMER_LEGAL_EN = "h1".U(1.W)
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val TIMER_LEGAL_EN = "h1".U(1.W)
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}
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}
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object pt1{
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val BHT_ADDR_HI = 0x9 //.U(4.W)
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val BHT_ADDR_LO = 0x2 //.U(2.W)
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val BHT_ARRAY_DEPTH = 0x100 //.U(11.W)
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val BHT_GHR_HASH_1 = 0x0 //.U(1.W)
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val BHT_GHR_SIZE = 0x4 //.U(4.W)
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val BHT_SIZE = 0x200 //.U(12.W)
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val BTB_ADDR_HI = 0x09 //.U(5.W)
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val BTB_ADDR_LO = 0x2 //.U(2.W)
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val BTB_ARRAY_DEPTH = 0x100 //.U(9.W)
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val BTB_BTAG_FOLD = 0x0 //.U(1.W)
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val BTB_BTAG_SIZE = 0x5 //.U(4.W)
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val BTB_FOLD2_INDEX_HASH = 0x0 //.U(1.W)
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val BTB_INDEX1_HI = 0x09 //.U(5.W)
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val BTB_INDEX1_LO = 0x02 //.U(5.W)
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val BTB_INDEX2_HI = 0x11 //.U(5.W)
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val BTB_INDEX2_LO = 0x0A //.U(5.W)
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val BTB_INDEX3_HI = 0x19 //.U(5.W)
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val BTB_INDEX3_LO = 0x12 //.U(5.W)
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val BTB_SIZE = 0x200 //.U(10.W)
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val BUILD_AHB_LITE = 0x0 //.U(1.W)
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val BUILD_AXI4 = 0x1 //.U(1.W)
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val BUILD_AXI_NATIVE = 0x1 //.U(1.W)
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val BUS_PRTY_DEFAULT = 0x3 //.U(2.W)
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val DATA_ACCESS_ADDR0 = 0x00000000 //.U(32.W)
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val DATA_ACCESS_ADDR1 = 0xC0000000 //.U(32.W)
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val DATA_ACCESS_ADDR2 = 0xA0000000 //.U(32.W)
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val DATA_ACCESS_ADDR3 = 0x80000000 //.U(32.W)
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val DATA_ACCESS_ADDR4 = 0x00000000 //.U(32.W)
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val DATA_ACCESS_ADDR5 = 0x00000000 //.U(32.W)
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val DATA_ACCESS_ADDR6 = 0x00000000 //.U(32.W)
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val DATA_ACCESS_ADDR7 = 0x00000000 //.U(32.W)
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val DATA_ACCESS_ENABLE0 = 0x1 //.U(1.W)
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val DATA_ACCESS_ENABLE1 = 0x1 //.U(1.W)
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val DATA_ACCESS_ENABLE2 = 0x1 //.U(1.W)
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val DATA_ACCESS_ENABLE3 = 0x1 //.U(1.W)
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val DATA_ACCESS_ENABLE4 = 0x0 //.U(1.W)
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val DATA_ACCESS_ENABLE5 = 0x0 //.U(1.W)
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val DATA_ACCESS_ENABLE6 = 0x0 //.U(1.W)
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val DATA_ACCESS_ENABLE7 = 0x0 //.U(1.W)
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val DATA_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W)
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val DATA_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W)
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val DCCM_BANK_BITS = 0x2 //.U(3.W)
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val DCCM_BITS = 0x10 //.U(5.W)
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val DCCM_BYTE_WIDTH = 0x4 //.U(3.W)
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val DCCM_DATA_WIDTH = 0x20 //.U(6.W)
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val DCCM_ECC_WIDTH = 0x7 //.U(3.W)
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val DCCM_ENABLE = 0x1 //.U(1.W)
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val DCCM_FDATA_WIDTH = 0x27 //.U(6.W)
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val DCCM_INDEX_BITS = 0xC //.U(4.W)
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val DCCM_NUM_BANKS = 0x04 //.U(5.W)
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val DCCM_REGION = 0xF //.U(4.W)
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val DCCM_SADR = 0xF0040000
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val DCCM_SIZE = 0x040
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val DCCM_WIDTH_BITS = 0x2 //.U(2.W)
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val DMA_BUF_DEPTH = 0x5 //.U(3.W)
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val DMA_BUS_ID = 0x1 //.U(1.W)
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val DMA_BUS_PRTY = 0x2 //.U(2.W)
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val DMA_BUS_TAG = 0x1 //.U(4.W)
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val FAST_INTERRUPT_REDIRECT= 0x1 //.U(1.W)
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val ICACHE_2BANKS = 0x1 //.U(1.W)
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val ICACHE_BANK_BITS = 0x1 //.U(3.W)
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val ICACHE_BANK_HI = 0x3 //.U(3.W)
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val ICACHE_BANK_LO = 0x3 //.U(2.W)
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val ICACHE_BANK_WIDTH = 0x8 //.U(4.W)
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val ICACHE_BANKS_WAY = 0x2 //.U(3.W)
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val ICACHE_BEAT_ADDR_HI = 0x5 //.U(4.W)
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val ICACHE_BEAT_BITS = 0x3 //.U(4.W)
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val ICACHE_DATA_DEPTH = 0x0200 //.U(14.W)
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val ICACHE_DATA_INDEX_LO = 0x4 //.U(3.W)
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val ICACHE_DATA_WIDTH = 0x40 //.U(7.W)
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val ICACHE_ECC = 0x1 //.U(1.W)
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val ICACHE_ENABLE = 0x1 //.U(1.W)
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val ICACHE_FDATA_WIDTH = 0x47 //.U(7.W)
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val ICACHE_INDEX_HI = 0x0C //.U(5.W)
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val ICACHE_LN_SZ = 0x40 //.U(7.W)
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val ICACHE_NUM_BEATS = 0x8 //.U(4.W)
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val ICACHE_NUM_WAYS = 0x2 //.U(3.W)
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val ICACHE_ONLY = 0x0 //.U(1.W)
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val ICACHE_SCND_LAST = 0x6 //.U(4.W)
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val ICACHE_SIZE = 0x010 //.U(9.W)
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val ICACHE_STATUS_BITS = 0x1 //.U(3.W)
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val ICACHE_TAG_DEPTH = 0x0080 //.U(13.W)
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val ICACHE_TAG_INDEX_LO = 0x6 //.U(3.W)
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val ICACHE_TAG_LO = 0x0D //.U(5.W)
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val ICACHE_WAYPACK = 0x0 //.U(1.W)
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val ICCM_BANK_BITS = 0x2 //.U(3.W)
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val ICCM_BANK_HI = 0x03 //.U(5.W)
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val ICCM_BANK_INDEX_LO = 0x04 //.U(5.W)
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val ICCM_BITS = 0x10 //.U(5.W)
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val ICCM_ENABLE = 0x1 //.U(1.W)
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val ICCM_ICACHE = 0x1 //.U(1.W)
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val ICCM_INDEX_BITS = 0xC //.U(4.W)
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val ICCM_NUM_BANKS = 0x04 //.U(5.W)
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val ICCM_ONLY = 0x0 //.U(1.W)
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val ICCM_REGION = 0xE //.U(4.W)
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val ICCM_SADR = 0xEE000000 //.U(32.W)
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val ICCM_SIZE = 0x040 //.U(10.W)
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val IFU_BUS_ID = 0x1 //.U(1.W)
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val IFU_BUS_PRTY = 0x2 //.U(2.W)
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val IFU_BUS_TAG = 0x3 //.U(4.W)
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val INST_ACCESS_ADDR0 = 0x00000000 //.U(32.W)
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val INST_ACCESS_ADDR1 = 0xC0000000 //.U(32.W)
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val INST_ACCESS_ADDR2 = 0xA0000000 //.U(32.W)
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val INST_ACCESS_ADDR3 = 0x80000000 //.U(32.W)
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val INST_ACCESS_ADDR4 = 0x00000000 //.U(32.W)
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val INST_ACCESS_ADDR5 = 0x00000000 //.U(32.W)
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val INST_ACCESS_ADDR6 = 0x00000000 //.U(32.W)
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val INST_ACCESS_ADDR7 = 0x00000000 //.U(32.W)
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val INST_ACCESS_ENABLE0 = 0x1 //.U(1.W)
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val INST_ACCESS_ENABLE1 = 0x1 //.U(1.W)
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val INST_ACCESS_ENABLE2 = 0x1 //.U(1.W)
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val INST_ACCESS_ENABLE3 = 0x1 //.U(1.W)
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val INST_ACCESS_ENABLE4 = 0x0 //.U(1.W)
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val INST_ACCESS_ENABLE5 = 0x0 //.U(1.W)
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val INST_ACCESS_ENABLE6 = 0x0 //.U(1.W)
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val INST_ACCESS_ENABLE7 = 0x0 //.U(1.W)
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val INST_ACCESS_MASK0 = 0x7FFFFFFF //.U(32.W)
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val INST_ACCESS_MASK1 = 0x3FFFFFFF //.U(32.W)
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val INST_ACCESS_MASK2 = 0x1FFFFFFF //.U(32.W)
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val INST_ACCESS_MASK3 = 0x0FFFFFFF //.U(32.W)
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val INST_ACCESS_MASK4 = 0xFFFFFFFF //.U(32.W)
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val INST_ACCESS_MASK5 = 0xFFFFFFFF //.U(32.W)
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val INST_ACCESS_MASK6 = 0xFFFFFFFF //.U(32.W)
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val INST_ACCESS_MASK7 = 0xFFFFFFFF //.U(32.W)
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val LOAD_TO_USE_PLUS1 = 0x0 //.U(1.W)
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val LSU2DMA = 0x0 //.U(1.W)
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val LSU_BUS_ID = 0x1 //.U(1.W)
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val LSU_BUS_PRTY = 0x2 //.U(2.W)
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val LSU_BUS_TAG = 0x3 //.U(4.W)
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val LSU_NUM_NBLOAD = 0x04 //.U(5.W)
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val LSU_NUM_NBLOAD_WIDTH = 0x2 //.U(3.W)
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val LSU_SB_BITS = 0x10 //.U(5.W)
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val LSU_STBUF_DEPTH = 0x4 //.U(4.W)
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val NO_ICCM_NO_ICACHE = 0x0 //.U(1.W)
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val PIC_2CYCLE = 0x0 //.U(1.W)
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val PIC_BASE_ADDR = 0xF00C0000 //.U(32.W)
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val PIC_BITS = 0x0F //.U(5.W)
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val PIC_INT_WORDS = 0x1 //.U(4.W)
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val PIC_REGION = 0xF //.U(4.W)
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val PIC_SIZE = 0x020 //.U(9.W)
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val PIC_TOTAL_INT = 0x1F //.U(8.W)
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val PIC_TOTAL_INT_PLUS1 = 0x020 //.U(9.W)
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val RET_STACK_SIZE = 0x8 //.U(4.W)
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val SB_BUS_ID = 0x1 //.U(1.W)
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val SB_BUS_PRTY = 0x2 //.U(2.W)
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val SB_BUS_TAG = 0x1 //.U(4.W)
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val TIMER_LEGAL_EN = 0x1 //.U(1.W)
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}
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