bus buffer added

lsu_bus_buffer.fir

@@ -291,7 +291,7 @@ circuit lsu_bus_buffer :
   module lsu_bus_buffer : 
     input clock : Clock
     input reset : AsyncReset
-    output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>}
+    output io : {flip clk_override : UInt<1>, flip scan_mode : UInt<1>, tlu_busbuff : {lsu_pmu_bus_trxn : UInt<1>, lsu_pmu_bus_misaligned : UInt<1>, lsu_pmu_bus_error : UInt<1>, lsu_pmu_bus_busy : UInt<1>, flip dec_tlu_external_ldfwd_disable : UInt<1>, flip dec_tlu_wb_coalescing_disable : UInt<1>, flip dec_tlu_sideeffect_posted_disable : UInt<1>, lsu_imprecise_error_load_any : UInt<1>, lsu_imprecise_error_store_any : UInt<1>, lsu_imprecise_error_addr_any : UInt<32>}, dctl_busbuff : {lsu_nonblock_load_valid_m : UInt<1>, lsu_nonblock_load_tag_m : UInt<2>, lsu_nonblock_load_inv_r : UInt<1>, lsu_nonblock_load_inv_tag_r : UInt<2>, lsu_nonblock_load_data_valid : UInt<1>, lsu_nonblock_load_data_error : UInt<1>, lsu_nonblock_load_data_tag : UInt<2>, lsu_nonblock_load_data : UInt<32>}, flip dec_tlu_force_halt : UInt<1>, flip lsu_bus_obuf_c1_clken : UInt<1>, flip lsu_busm_clken : UInt<1>, flip lsu_c2_r_clk : Clock, flip lsu_bus_ibuf_c1_clk : Clock, flip lsu_bus_obuf_c1_clk : Clock, flip lsu_bus_buf_c1_clk : Clock, flip lsu_free_c2_clk : Clock, flip lsu_busm_clk : Clock, flip dec_lsu_valid_raw_d : UInt<1>, flip lsu_pkt_m : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_pkt_r : {valid : UInt<1>, bits : {fast_int : UInt<1>, stack : UInt<1>, by : UInt<1>, half : UInt<1>, word : UInt<1>, dword : UInt<1>, load : UInt<1>, store : UInt<1>, unsign : UInt<1>, dma : UInt<1>, store_data_bypass_d : UInt<1>, load_ldst_bypass_d : UInt<1>, store_data_bypass_m : UInt<1>}}, flip lsu_addr_m : UInt<32>, flip end_addr_m : UInt<32>, flip lsu_addr_r : UInt<32>, flip end_addr_r : UInt<32>, flip store_data_r : UInt<32>, flip no_word_merge_r : UInt<1>, flip no_dword_merge_r : UInt<1>, flip lsu_busreq_m : UInt<1>, flip ld_full_hit_m : UInt<1>, flip flush_m_up : UInt<1>, flip flush_r : UInt<1>, flip lsu_commit_r : UInt<1>, flip is_sideeffects_r : UInt<1>, flip ldst_dual_d : UInt<1>, flip ldst_dual_m : UInt<1>, flip ldst_dual_r : UInt<1>, flip ldst_byteen_ext_m : UInt<8>, lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip lsu_bus_clk_en : UInt<1>, flip lsu_bus_clk_en_q : UInt<1>, lsu_busreq_r : UInt<1>, lsu_bus_buffer_pend_any : UInt<1>, lsu_bus_buffer_full_any : UInt<1>, lsu_bus_buffer_empty_any : UInt<1>, ld_byte_hit_buf_lo : UInt<4>, ld_byte_hit_buf_hi : UInt<4>, ld_fwddata_buf_lo : UInt<32>, ld_fwddata_buf_hi : UInt<32>}
     
     wire buf_addr : UInt<32>[4] @[lsu_bus_buffer.scala 70:22]
     wire buf_state : UInt<3>[4] @[lsu_bus_buffer.scala 71:23]
@@ -1584,28 +1584,28 @@ circuit lsu_bus_buffer :
     when ibuf_wr_en : @[Reg.scala 28:19]
       ibuf_sz <= ibuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr of rvclkhdr @[lib.scala 368:23]
+    inst rvclkhdr of rvclkhdr @[lib.scala 390:23]
     rvclkhdr.clock <= clock
     rvclkhdr.reset <= reset
-    rvclkhdr.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 371:17]
-    rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1012 <= ibuf_addr_in @[lib.scala 374:16]
+    rvclkhdr.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr.io.en <= ibuf_wr_en @[lib.scala 393:17]
+    rvclkhdr.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1012 : UInt, rvclkhdr.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_1012 <= ibuf_addr_in @[lib.scala 396:16]
     ibuf_addr <= _T_1012 @[lsu_bus_buffer.scala 253:13]
     reg _T_1013 : UInt, io.lsu_bus_ibuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when ibuf_wr_en : @[Reg.scala 28:19]
       _T_1013 <= ibuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     ibuf_byteen <= _T_1013 @[lsu_bus_buffer.scala 254:15]
-    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 368:23]
+    inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 390:23]
     rvclkhdr_1.clock <= clock
     rvclkhdr_1.reset <= reset
-    rvclkhdr_1.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1014 <= ibuf_data_in @[lib.scala 374:16]
+    rvclkhdr_1.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_1.io.en <= ibuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_1.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1014 : UInt, rvclkhdr_1.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_1014 <= ibuf_data_in @[lib.scala 396:16]
     ibuf_data <= _T_1014 @[lsu_bus_buffer.scala 255:13]
     reg _T_1015 : UInt, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 256:55]
     _T_1015 <= ibuf_timer_in @[lsu_bus_buffer.scala 256:55]
@@ -2513,8 +2513,8 @@ circuit lsu_bus_buffer :
     node _T_1769 = and(_T_1768, io.ldst_dual_r) @[lsu_bus_buffer.scala 345:35]
     node _T_1770 = or(_T_1767, _T_1769) @[lsu_bus_buffer.scala 344:250]
     obuf_merge_en <= _T_1770 @[lsu_bus_buffer.scala 342:17]
-    reg obuf_wr_enQ : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 347:55]
-    obuf_wr_enQ <= obuf_wr_en @[lsu_bus_buffer.scala 347:55]
+    reg obuf_wr_enQ : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
+    obuf_wr_enQ <= obuf_wr_en @[lib.scala 377:18]
     node _T_1771 = mux(obuf_wr_en, UInt<1>("h01"), obuf_valid) @[lsu_bus_buffer.scala 348:58]
     node _T_1772 = eq(obuf_rst, UInt<1>("h00")) @[lsu_bus_buffer.scala 348:93]
     node _T_1773 = and(_T_1771, _T_1772) @[lsu_bus_buffer.scala 348:91]
@@ -2526,68 +2526,70 @@ circuit lsu_bus_buffer :
       _T_1775 <= obuf_nosend_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_nosend <= _T_1775 @[lsu_bus_buffer.scala 349:15]
-    reg _T_1776 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 350:54]
-    _T_1776 <= obuf_cmd_done_in @[lsu_bus_buffer.scala 350:54]
-    obuf_cmd_done <= _T_1776 @[lsu_bus_buffer.scala 350:17]
-    reg _T_1777 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 351:55]
-    _T_1777 <= obuf_data_done_in @[lsu_bus_buffer.scala 351:55]
-    obuf_data_done <= _T_1777 @[lsu_bus_buffer.scala 351:18]
-    reg _T_1778 : UInt<1>, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 352:56]
-    _T_1778 <= obuf_rdrsp_pend_in @[lsu_bus_buffer.scala 352:56]
-    obuf_rdrsp_pend <= _T_1778 @[lsu_bus_buffer.scala 352:19]
-    reg _T_1779 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 353:55]
-    _T_1779 <= obuf_rdrsp_tag_in @[lsu_bus_buffer.scala 353:55]
+    reg _T_1776 : UInt<1>, io.lsu_free_c2_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    when obuf_rdrsp_pend_en : @[Reg.scala 28:19]
+      _T_1776 <= obuf_rdrsp_pend_in @[Reg.scala 28:23]
+      skip @[Reg.scala 28:19]
+    obuf_rdrsp_pend <= _T_1776 @[lsu_bus_buffer.scala 350:19]
+    reg _T_1777 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
+    _T_1777 <= obuf_cmd_done_in @[lib.scala 377:18]
+    obuf_cmd_done <= _T_1777 @[lsu_bus_buffer.scala 351:17]
+    reg _T_1778 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
+    _T_1778 <= obuf_data_done_in @[lib.scala 377:18]
+    obuf_data_done <= _T_1778 @[lsu_bus_buffer.scala 352:18]
+    reg _T_1779 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
+    _T_1779 <= obuf_rdrsp_tag_in @[lib.scala 377:18]
     obuf_rdrsp_tag <= _T_1779 @[lsu_bus_buffer.scala 353:18]
-    reg _T_1780 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1780 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1780 <= obuf_tag0_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_tag0 <= _T_1780 @[lsu_bus_buffer.scala 354:13]
-    reg obuf_tag1 : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_tag1 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_tag1 <= obuf_tag1_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg obuf_merge : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_merge : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_merge <= obuf_merge_en @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    reg _T_1781 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1781 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1781 <= obuf_write_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_write <= _T_1781 @[lsu_bus_buffer.scala 357:14]
-    reg _T_1782 : UInt<1>, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg _T_1782 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       _T_1782 <= obuf_sideeffect_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_sideeffect <= _T_1782 @[lsu_bus_buffer.scala 358:19]
-    reg obuf_sz : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_sz : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_sz <= obuf_sz_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23]
-    rvclkhdr_2.clock <= clock
-    rvclkhdr_2.reset <= reset
-    rvclkhdr_2.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_1783 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_1783 <= obuf_addr_in @[lib.scala 374:16]
-    obuf_addr <= _T_1783 @[lsu_bus_buffer.scala 360:13]
-    reg obuf_byteen : UInt, io.lsu_bus_obuf_c1_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
+    reg obuf_byteen : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
     when obuf_wr_en : @[Reg.scala 28:19]
       obuf_byteen <= obuf_byteen_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
-    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23]
+    inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 390:23]
+    rvclkhdr_2.clock <= clock
+    rvclkhdr_2.reset <= reset
+    rvclkhdr_2.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_2.io.en <= obuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_2.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_1783 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_1783 <= obuf_addr_in @[lib.scala 396:16]
+    obuf_addr <= _T_1783 @[lsu_bus_buffer.scala 361:13]
+    inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 390:23]
     rvclkhdr_3.clock <= clock
     rvclkhdr_3.reset <= reset
-    rvclkhdr_3.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 371:17]
-    rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    obuf_data <= obuf_data_in @[lib.scala 374:16]
-    reg _T_1784 : UInt, io.lsu_busm_clk with : (reset => (reset, UInt<1>("h00"))) @[lsu_bus_buffer.scala 363:54]
-    _T_1784 <= obuf_wr_timer_in @[lsu_bus_buffer.scala 363:54]
+    rvclkhdr_3.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_3.io.en <= obuf_wr_en @[lib.scala 393:17]
+    rvclkhdr_3.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg obuf_data : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    obuf_data <= obuf_data_in @[lib.scala 396:16]
+    reg _T_1784 : UInt<1>, clock with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 377:18]
+    _T_1784 <= obuf_data_done_in @[lib.scala 377:18]
     obuf_wr_timer <= _T_1784 @[lsu_bus_buffer.scala 363:17]
     wire WrPtr0_m : UInt<2>
     WrPtr0_m <= UInt<1>("h00")
@@ -5709,41 +5711,41 @@ circuit lsu_bus_buffer :
     buf_sz[2] <= _T_4353 @[lsu_bus_buffer.scala 522:10]
     buf_sz[3] <= _T_4355 @[lsu_bus_buffer.scala 522:10]
     node _T_4356 = bits(buf_wr_en[0], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23]
+    inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 390:23]
     rvclkhdr_4.clock <= clock
     rvclkhdr_4.reset <= reset
-    rvclkhdr_4.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_4.io.en <= _T_4356 @[lib.scala 371:17]
-    rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4357 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4357 <= buf_addr_in[0] @[lib.scala 374:16]
+    rvclkhdr_4.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_4.io.en <= _T_4356 @[lib.scala 393:17]
+    rvclkhdr_4.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4357 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4357 <= buf_addr_in[0] @[lib.scala 396:16]
     node _T_4358 = bits(buf_wr_en[1], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23]
+    inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 390:23]
     rvclkhdr_5.clock <= clock
     rvclkhdr_5.reset <= reset
-    rvclkhdr_5.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_5.io.en <= _T_4358 @[lib.scala 371:17]
-    rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4359 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4359 <= buf_addr_in[1] @[lib.scala 374:16]
+    rvclkhdr_5.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_5.io.en <= _T_4358 @[lib.scala 393:17]
+    rvclkhdr_5.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4359 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4359 <= buf_addr_in[1] @[lib.scala 396:16]
     node _T_4360 = bits(buf_wr_en[2], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 368:23]
+    inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 390:23]
     rvclkhdr_6.clock <= clock
     rvclkhdr_6.reset <= reset
-    rvclkhdr_6.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_6.io.en <= _T_4360 @[lib.scala 371:17]
-    rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4361 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4361 <= buf_addr_in[2] @[lib.scala 374:16]
+    rvclkhdr_6.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_6.io.en <= _T_4360 @[lib.scala 393:17]
+    rvclkhdr_6.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4361 : UInt, rvclkhdr_6.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4361 <= buf_addr_in[2] @[lib.scala 396:16]
     node _T_4362 = bits(buf_wr_en[3], 0, 0) @[lsu_bus_buffer.scala 523:80]
-    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 368:23]
+    inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 390:23]
     rvclkhdr_7.clock <= clock
     rvclkhdr_7.reset <= reset
-    rvclkhdr_7.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_7.io.en <= _T_4362 @[lib.scala 371:17]
-    rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4363 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4363 <= buf_addr_in[3] @[lib.scala 374:16]
+    rvclkhdr_7.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_7.io.en <= _T_4362 @[lib.scala 393:17]
+    rvclkhdr_7.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4363 : UInt, rvclkhdr_7.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4363 <= buf_addr_in[3] @[lib.scala 396:16]
     buf_addr[0] <= _T_4357 @[lsu_bus_buffer.scala 523:12]
     buf_addr[1] <= _T_4359 @[lsu_bus_buffer.scala 523:12]
     buf_addr[2] <= _T_4361 @[lsu_bus_buffer.scala 523:12]
@@ -5772,38 +5774,38 @@ circuit lsu_bus_buffer :
     buf_byteen[1] <= _T_4367 @[lsu_bus_buffer.scala 524:14]
     buf_byteen[2] <= _T_4369 @[lsu_bus_buffer.scala 524:14]
     buf_byteen[3] <= _T_4371 @[lsu_bus_buffer.scala 524:14]
-    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 368:23]
+    inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 390:23]
     rvclkhdr_8.clock <= clock
     rvclkhdr_8.reset <= reset
-    rvclkhdr_8.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 371:17]
-    rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4372 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4372 <= buf_data_in[0] @[lib.scala 374:16]
-    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 368:23]
+    rvclkhdr_8.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_8.io.en <= buf_data_en[0] @[lib.scala 393:17]
+    rvclkhdr_8.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4372 : UInt, rvclkhdr_8.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4372 <= buf_data_in[0] @[lib.scala 396:16]
+    inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 390:23]
     rvclkhdr_9.clock <= clock
     rvclkhdr_9.reset <= reset
-    rvclkhdr_9.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 371:17]
-    rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4373 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4373 <= buf_data_in[1] @[lib.scala 374:16]
-    inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 368:23]
+    rvclkhdr_9.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_9.io.en <= buf_data_en[1] @[lib.scala 393:17]
+    rvclkhdr_9.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4373 : UInt, rvclkhdr_9.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4373 <= buf_data_in[1] @[lib.scala 396:16]
+    inst rvclkhdr_10 of rvclkhdr_10 @[lib.scala 390:23]
     rvclkhdr_10.clock <= clock
     rvclkhdr_10.reset <= reset
-    rvclkhdr_10.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 371:17]
-    rvclkhdr_10.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4374 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4374 <= buf_data_in[2] @[lib.scala 374:16]
-    inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 368:23]
+    rvclkhdr_10.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_10.io.en <= buf_data_en[2] @[lib.scala 393:17]
+    rvclkhdr_10.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4374 : UInt, rvclkhdr_10.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4374 <= buf_data_in[2] @[lib.scala 396:16]
+    inst rvclkhdr_11 of rvclkhdr_11 @[lib.scala 390:23]
     rvclkhdr_11.clock <= clock
     rvclkhdr_11.reset <= reset
-    rvclkhdr_11.io.clk <= clock @[lib.scala 370:18]
-    rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 371:17]
-    rvclkhdr_11.io.scan_mode <= io.scan_mode @[lib.scala 372:24]
-    reg _T_4375 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16]
-    _T_4375 <= buf_data_in[3] @[lib.scala 374:16]
+    rvclkhdr_11.io.clk <= clock @[lib.scala 392:18]
+    rvclkhdr_11.io.en <= buf_data_en[3] @[lib.scala 393:17]
+    rvclkhdr_11.io.scan_mode <= UInt<1>("h00") @[lib.scala 394:24]
+    reg _T_4375 : UInt, rvclkhdr_11.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 396:16]
+    _T_4375 <= buf_data_in[3] @[lib.scala 396:16]
     buf_data[0] <= _T_4372 @[lsu_bus_buffer.scala 525:12]
     buf_data[1] <= _T_4373 @[lsu_bus_buffer.scala 525:12]
     buf_data[2] <= _T_4374 @[lsu_bus_buffer.scala 525:12]

src/main/scala/lib/lib.scala

@@ -370,7 +370,20 @@ trait lib extends param{
       in_range := (addr(31,MASK_BITS) === start_addr(31,MASK_BITS)).asUInt
     (in_range,in_region)
   }
-
+  object rvdff_fpga {
+  def apply(din: UInt, clk: Clock, clken: Bool,rawclk:Clock):UInt = {
+    if (RV_FPGA_OPTIMIZE)
+    withClock (clk) {RegEnable (din, 0.U, clken)}
+    else RegNext (din, 0.U)
+  }
+}
+  object rvdffs_fpga {
+    def apply(din: UInt, en:Bool,clk: Clock, clken: Bool,rawclk:Clock):UInt = {
+      if (RV_FPGA_OPTIMIZE)
+        withClock (clk) {RegEnable (din, 0.U, clken & en)}
+      else RegEnable (din, 0.U,en)
+    }
+  }
   ////rvdffe ///////////////////////////////////////////////////////////////////////
   object rvdffe {
     def apply(din: UInt, en: Bool, clk: Clock, scan_mode: Bool): UInt = {

src/main/scala/lib/param.scala

@@ -155,4 +155,5 @@ trait param {
   val SB_BUS_PRTY            = 	0x2
   val SB_BUS_TAG             = 	0x1
   val TIMER_LEGAL_EN         = 	0x1
+  val RV_FPGA_OPTIMIZE       =  0x0
 }

src/main/scala/lsu/lsu_bus_buffer.scala

@@ -8,7 +8,7 @@ import chisel3.util.ImplicitConversions.intToUInt
 import ifu._
 
 @chiselName
-class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
+class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   val io = IO(new Bundle {
     val clk_override           = Input(Bool())
     val scan_mode           = Input(Bool())
@@ -344,23 +344,23 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
     (!indexing(buf_write, CmdPtr0) & indexing(buf_dual.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & !indexing(buf_dualhi.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0) & indexing(buf_samedw.map(_.asUInt).reverse.reduce(Cat(_,_)), CmdPtr0))) |
     (ibuf_buf_byp & ldst_samedw_r & io.ldst_dual_r)
 
-  val obuf_wr_enQ = withClock(io.lsu_busm_clk){RegNext(obuf_wr_en, false.B)}
+  val obuf_wr_enQ = rvdff_fpga (obuf_wr_en,io.lsu_busm_clk,io.lsu_busm_clken,clock)
   obuf_valid := withClock(io.lsu_free_c2_clk){RegNext(Mux(obuf_wr_en, true.B, obuf_valid) & !obuf_rst, false.B)}
   obuf_nosend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_nosend_in, false.B, obuf_wr_en)}
-  obuf_cmd_done := withClock(io.lsu_busm_clk){RegNext(obuf_cmd_done_in, false.B)}
-  obuf_data_done := withClock(io.lsu_busm_clk){RegNext(obuf_data_done_in, false.B)}
-  obuf_rdrsp_pend := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_pend_in, false.B)}
-  obuf_rdrsp_tag := withClock(io.lsu_busm_clk){RegNext(obuf_rdrsp_tag_in, 0.U)}
-  obuf_tag0 := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_tag0_in, 0.U, obuf_wr_en)}
-  val obuf_tag1 = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_tag1_in, 0.U, obuf_wr_en)}
-  val obuf_merge = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_merge_in, false.B, obuf_wr_en)}
-  obuf_write := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_write_in, false.B, obuf_wr_en)}
-  obuf_sideeffect := withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_sideeffect_in, false.B, obuf_wr_en)}
-  val obuf_sz = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_sz_in, 0.U, obuf_wr_en)}
+  obuf_rdrsp_pend := withClock(io.lsu_free_c2_clk){RegEnable(obuf_rdrsp_pend_in, false.B,obuf_rdrsp_pend_en)}
+  obuf_cmd_done := rvdff_fpga (obuf_cmd_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
+  obuf_data_done := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
+  obuf_rdrsp_tag := rvdff_fpga (obuf_rdrsp_tag_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
+  obuf_tag0 := rvdffs_fpga (obuf_tag0_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  val obuf_tag1 = rvdffs_fpga (obuf_tag1_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  val obuf_merge = rvdffs_fpga (obuf_merge_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  obuf_write := rvdffs_fpga (obuf_write_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  obuf_sideeffect := rvdffs_fpga (obuf_sideeffect_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  val obuf_sz = rvdffs_fpga (obuf_sz_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
+  val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
   obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode)
-  val obuf_byteen = withClock(io.lsu_bus_obuf_c1_clk){RegEnable(obuf_byteen_in, 0.U, obuf_wr_en)}
   val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode)
-  obuf_wr_timer := withClock(io.lsu_busm_clk){RegNext(obuf_wr_timer_in, 0.U)}
+  obuf_wr_timer := rvdff_fpga (obuf_data_done_in,io.lsu_busm_clk,obuf_wr_en,clock)
   val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
 
   WrPtr0_m := MuxCase(3.U, (0 until DEPTH).map(i=>((buf_state(i)===idle_C) &
@@ -624,4 +624,6 @@ class  lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
   lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
 }
-
+object buffer extends App {
+  println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
+}