Core Complete
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14
TEC_RV_ICG.v
14
TEC_RV_ICG.v
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@ -1,14 +0,0 @@
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module TEC_RV_ICG(
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(
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input logic SE, EN, CK,
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output Q
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);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always @(CK, enable) begin
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if(!CK)
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en_ff = enable;
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end
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assign Q = CK & en_ff;
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endmodule
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@ -1,51 +0,0 @@
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
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"sources":[
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"~el2_dbg|el2_dbg>io_dma_dbg_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~el2_dbg|el2_dbg>io_dbg_resume_req",
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"sources":[
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"~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
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"~el2_dbg|el2_dbg>io_dec_tlu_debug_mode",
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"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
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"~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
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"~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
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"~el2_dbg|el2_dbg>io_dmi_reg_en",
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"~el2_dbg|el2_dbg>io_dma_dbg_ready",
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"~el2_dbg|el2_dbg>io_dmi_reg_addr",
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"~el2_dbg|el2_dbg>reset"
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]
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},
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{
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"class":"logger.LogLevelAnnotation",
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"globalLogLevel":{
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}
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"el2_dbg.TEC_RV_ICG",
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"resourceId":"/vsrc/TEC_RV_ICG.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"el2_dbg"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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1235
el2_dbg.fir
1235
el2_dbg.fir
File diff suppressed because it is too large
Load Diff
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@ -6,7 +6,6 @@ import exu._
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import lsu._
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import lib._
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import include._
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import dmi._
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import dbg._
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class el2_swerv extends Module with RequireAsyncReset with el2_lib {
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