Core Complete

This commit is contained in:
waleed-lm 2020-11-11 14:46:44 +05:00
parent e3f5cb5bed
commit 309b51b11f
5 changed files with 0 additions and 2337 deletions

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@ -1,14 +0,0 @@
module TEC_RV_ICG(
(
input logic SE, EN, CK,
output Q
);
logic en_ff;
logic enable;
assign enable = EN | SE;
always @(CK, enable) begin
if(!CK)
en_ff = enable;
end
assign Q = CK & en_ff;
endmodule

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@ -1,51 +0,0 @@
[
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"sources":[
"~el2_dbg|el2_dbg>io_dma_dbg_ready"
]
},
{
"class":"firrtl.transforms.CombinationalPath",
"sink":"~el2_dbg|el2_dbg>io_dbg_resume_req",
"sources":[
"~el2_dbg|el2_dbg>io_dec_tlu_mpc_halted_only",
"~el2_dbg|el2_dbg>io_dec_tlu_debug_mode",
"~el2_dbg|el2_dbg>io_dbg_cmd_valid",
"~el2_dbg|el2_dbg>io_core_dbg_cmd_done",
"~el2_dbg|el2_dbg>io_dmi_reg_wr_en",
"~el2_dbg|el2_dbg>io_dmi_reg_en",
"~el2_dbg|el2_dbg>io_dma_dbg_ready",
"~el2_dbg|el2_dbg>io_dmi_reg_addr",
"~el2_dbg|el2_dbg>reset"
]
},
{
"class":"logger.LogLevelAnnotation",
"globalLogLevel":{
}
},
{
"class":"firrtl.EmitCircuitAnnotation",
"emitter":"firrtl.VerilogEmitter"
},
{
"class":"firrtl.transforms.BlackBoxResourceAnno",
"target":"el2_dbg.TEC_RV_ICG",
"resourceId":"/vsrc/TEC_RV_ICG.v"
},
{
"class":"firrtl.options.TargetDirAnnotation",
"directory":"."
},
{
"class":"firrtl.options.OutputAnnotationFileAnnotation",
"file":"el2_dbg"
},
{
"class":"firrtl.transforms.BlackBoxTargetDirAnno",
"targetDir":"."
}
]

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1036
el2_dbg.v

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@ -6,7 +6,6 @@ import exu._
import lsu._ import lsu._
import lib._ import lib._
import include._ import include._
import dmi._
import dbg._ import dbg._
class el2_swerv extends Module with RequireAsyncReset with el2_lib { class el2_swerv extends Module with RequireAsyncReset with el2_lib {