From 31d996405984d3172f0909f8f412d1fbab041dfb Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Fri, 9 Oct 2020 10:36:09 +0500 Subject: [PATCH] RegEnable added --- el2_ifu_iccm_mem.fir | 2 +- el2_ifu_iccm_mem.v | 16 ++++++++-------- src/main/scala/ifu/el2_ifu_iccm_mem.scala | 2 +- .../classes/ifu/el2_ifu_iccm_mem.class | Bin 92976 -> 92976 bytes 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir index 1768a319..f065aff5 100644 --- a/el2_ifu_iccm_mem.fir +++ b/el2_ifu_iccm_mem.fir @@ -501,7 +501,7 @@ circuit el2_ifu_iccm_mem : _T_371 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21] - node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50] + node _T_372 = bits(io.iccm_rw_addr, 1, 0) @[el2_ifu_iccm_mem.scala 102:50] reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34] iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34] node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48] diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v index ec8556c3..a34ba71a 100644 --- a/el2_ifu_iccm_mem.v +++ b/el2_ifu_iccm_mem.v @@ -235,7 +235,7 @@ module el2_ifu_iccm_mem( wire redundant_data1_en = _T_356 | r0_addr_en; // @[el2_ifu_iccm_mem.scala 96:121] wire _T_365 = redundant_address_1[0] & _T_1; // @[el2_ifu_iccm_mem.scala 98:104] wire _T_366 = _T_349 | _T_365; // @[el2_ifu_iccm_mem.scala 98:78] - reg [2:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34] + reg [1:0] iccm_rd_addr_lo_q; // @[el2_ifu_iccm_mem.scala 102:34] reg [1:0] iccm_rd_addr_hi_q; // @[el2_ifu_iccm_mem.scala 103:34] wire _T_374 = iccm_rd_addr_hi_q == 2'h0; // @[el2_ifu_iccm_mem.scala 105:86] wire _T_376 = iccm_rd_addr_hi_q == 2'h1; // @[el2_ifu_iccm_mem.scala 105:86] @@ -248,10 +248,10 @@ module el2_ifu_iccm_mem( wire [31:0] _T_386 = _T_382 | _T_383; // @[Mux.scala 27:72] wire [31:0] _T_387 = _T_386 | _T_384; // @[Mux.scala 27:72] wire [31:0] _T_388 = _T_387 | _T_385; // @[Mux.scala 27:72] - wire _T_391 = iccm_rd_addr_lo_q[1:0] == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77] - wire _T_394 = iccm_rd_addr_lo_q[1:0] == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77] - wire _T_397 = iccm_rd_addr_lo_q[1:0] == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77] - wire _T_400 = iccm_rd_addr_lo_q[1:0] == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77] + wire _T_391 = iccm_rd_addr_lo_q == 2'h0; // @[el2_ifu_iccm_mem.scala 106:77] + wire _T_394 = iccm_rd_addr_lo_q == 2'h1; // @[el2_ifu_iccm_mem.scala 106:77] + wire _T_397 = iccm_rd_addr_lo_q == 2'h2; // @[el2_ifu_iccm_mem.scala 106:77] + wire _T_400 = iccm_rd_addr_lo_q == 2'h3; // @[el2_ifu_iccm_mem.scala 106:77] wire [31:0] _T_402 = _T_391 ? iccm_bank_dout_fn_0[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_403 = _T_394 ? iccm_bank_dout_fn_1[31:0] : 32'h0; // @[Mux.scala 27:72] wire [31:0] _T_404 = _T_397 ? iccm_bank_dout_fn_2[31:0] : 32'h0; // @[Mux.scala 27:72] @@ -385,7 +385,7 @@ initial begin _RAND_20 = {1{`RANDOM}}; redundant_lru = _RAND_20[0:0]; _RAND_21 = {1{`RANDOM}}; - iccm_rd_addr_lo_q = _RAND_21[2:0]; + iccm_rd_addr_lo_q = _RAND_21[1:0]; _RAND_22 = {1{`RANDOM}}; iccm_rd_addr_hi_q = _RAND_22[1:0]; `endif // RANDOMIZE_REG_INIT @@ -514,9 +514,9 @@ end // initial end end if (reset) begin - iccm_rd_addr_lo_q <= 3'h0; + iccm_rd_addr_lo_q <= 2'h0; end else begin - iccm_rd_addr_lo_q <= io_iccm_rw_addr[2:0]; + iccm_rd_addr_lo_q <= io_iccm_rw_addr[1:0]; end if (reset) begin iccm_rd_addr_hi_q <= 2'h0; diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala index 24199a5a..e72ec762 100644 --- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -99,7 +99,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib { io.iccm_wr_data(77,39), io.iccm_wr_data(38,0)) redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool) - val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U) + val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI-2,0), 0.U) val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U) val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))), diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class index f10d07d73ec53ab293ec604e38597238adcc0cf3..374704a028db878882f5f74f291fe8bd667c7192 100644 GIT binary patch delta 19 bcmdmRjdjB{)`l&Ng?5ar+l%ZN_vrutQ#l7y delta 19 bcmdmRjdjB{)`l&Ng?5ZA+l%ZN_vrutQ!)oq