diff --git a/lsu.fir b/lsu.fir
index d832a54e..fac0a7e0 100644
--- a/lsu.fir
+++ b/lsu.fir
@@ -10798,7 +10798,7 @@ circuit lsu :
       obuf_data <= obuf_data_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     reg _T_1791 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20]
-    when obuf_wr_en : @[Reg.scala 28:19]
+    when io.lsu_busm_clken : @[Reg.scala 28:19]
       _T_1791 <= obuf_wr_timer_in @[Reg.scala 28:23]
       skip @[Reg.scala 28:19]
     obuf_wr_timer <= _T_1791 @[lsu_bus_buffer.scala 367:17]
diff --git a/lsu.v b/lsu.v
index 7c9d4e88..0f9ec944 100644
--- a/lsu.v
+++ b/lsu.v
@@ -8929,7 +8929,7 @@ end // initial
   always @(posedge clock or posedge reset) begin
     if (reset) begin
       obuf_wr_timer <= 3'h0;
-    end else if (obuf_wr_en) begin
+    end else if (io_lsu_busm_clken) begin
       if (obuf_wr_en) begin
         obuf_wr_timer <= 3'h0;
       end else if (_T_1058) begin
diff --git a/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala
index b7665549..9d7ca08d 100644
--- a/src/main/scala/lsu/lsu_bus_buffer.scala
+++ b/src/main/scala/lsu/lsu_bus_buffer.scala
@@ -364,7 +364,7 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
   val obuf_byteen = rvdffs_fpga (obuf_byteen_in,obuf_wr_en,io.lsu_bus_obuf_c1_clk,io.lsu_bus_obuf_c1_clken,clock)
   obuf_addr := rvdffe(obuf_addr_in, obuf_wr_en, clock, io.scan_mode)
   val obuf_data = rvdffe(obuf_data_in, obuf_wr_en, clock, io.scan_mode)
-  obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,obuf_wr_en,clock)
+  obuf_wr_timer := rvdff_fpga (obuf_wr_timer_in,io.lsu_busm_clk,io.lsu_busm_clken,clock)
   val WrPtr0_m = WireInit(UInt(DEPTH_LOG2.W), 0.U)
 
 
diff --git a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class
index afb77a71..bd3f67b5 100644
Binary files a/target/scala-2.12/classes/lsu/lsu_bus_buffer.class and b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class differ