Update beh_ib_func.scala
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@ -7,7 +7,8 @@ import chisel3.util.HasBlackBoxResource
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import chisel3.withClock
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object beh_ib_func {
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// use this for rvdffsc = > io.out := RegEnable(io.din & repl(io.din.getWidth, io.clear), 0.U, io.en)
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// use this for rvdffs = > io.out := RegEnable(io.din, 0.U, io.en)
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def repl(b:Int, a:UInt) = VecInit.tabulate(b)(i => a).reduce(Cat(_,_))
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def rvsyncss(din:UInt) = RegNext(RegNext(din,0.U),0.U)
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