From 33da1ffa7937b7bef1534905741e8c03cfea2bde Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Fri, 23 Oct 2020 12:05:34 +0500 Subject: [PATCH] miss state update --- el2_ifu_mem_ctl.fir | 184 +++++++++--------- el2_ifu_mem_ctl.v | 56 +++--- src/main/scala/ifu/el2_ifu_mem_ctl.scala | 10 +- .../classes/ifu/el2_ifu_mem_ctl.class | Bin 221044 -> 221044 bytes target/scala-2.12/classes/ifu/ifu_mem$.class | Bin 3876 -> 3876 bytes .../ifu/ifu_mem$delayedInit$body.class | Bin 736 -> 736 bytes 6 files changed, 126 insertions(+), 124 deletions(-) diff --git a/el2_ifu_mem_ctl.fir b/el2_ifu_mem_ctl.fir index ff19bd98..dc61ba83 100644 --- a/el2_ifu_mem_ctl.fir +++ b/el2_ifu_mem_ctl.fir @@ -13323,68 +13323,68 @@ circuit el2_ifu_mem_ctl : node _T_10105 = and(ic_tag_valid_unq, _T_10104) @[el2_ifu_mem_ctl.scala 798:48] node _T_10106 = orr(_T_10105) @[el2_ifu_mem_ctl.scala 798:115] ic_debug_tag_val_rd_out <= _T_10106 @[el2_ifu_mem_ctl.scala 798:27] - reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:58] - _T_10107 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:58] - io.ifu_pmu_bus_trxn <= _T_10107 @[el2_ifu_mem_ctl.scala 800:23] - reg _T_10108 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:58] - _T_10108 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:58] - io.ifu_pmu_bus_busy <= _T_10108 @[el2_ifu_mem_ctl.scala 801:23] + reg _T_10107 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 800:57] + _T_10107 <= ic_act_miss_f @[el2_ifu_mem_ctl.scala 800:57] + io.ifu_pmu_ic_miss <= _T_10107 @[el2_ifu_mem_ctl.scala 800:22] + reg _T_10108 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 801:56] + _T_10108 <= ic_act_hit_f @[el2_ifu_mem_ctl.scala 801:56] + io.ifu_pmu_ic_hit <= _T_10108 @[el2_ifu_mem_ctl.scala 801:21] reg _T_10109 : UInt, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 802:59] _T_10109 <= ifc_bus_acc_fault_f @[el2_ifu_mem_ctl.scala 802:59] io.ifu_pmu_bus_error <= _T_10109 @[el2_ifu_mem_ctl.scala 802:24] - node _T_10110 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 803:78] - node _T_10111 = and(ifu_bus_arvalid_ff, _T_10110) @[el2_ifu_mem_ctl.scala 803:76] - node _T_10112 = and(_T_10111, miss_pending) @[el2_ifu_mem_ctl.scala 803:98] - reg _T_10113 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:56] - _T_10113 <= _T_10112 @[el2_ifu_mem_ctl.scala 803:56] - io.ifu_pmu_ic_hit <= _T_10113 @[el2_ifu_mem_ctl.scala 803:21] - reg _T_10114 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:57] - _T_10114 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 804:57] - io.ifu_pmu_ic_miss <= _T_10114 @[el2_ifu_mem_ctl.scala 804:22] - io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 805:20] - node _T_10115 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 806:66] - io.ic_debug_tag_array <= _T_10115 @[el2_ifu_mem_ctl.scala 806:25] - io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 807:21] - io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 808:21] - node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 809:64] - node _T_10117 = eq(_T_10116, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 809:71] - node _T_10118 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 809:117] - node _T_10119 = eq(_T_10118, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 809:124] - node _T_10120 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 810:43] - node _T_10121 = eq(_T_10120, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 810:50] - node _T_10122 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 810:96] - node _T_10123 = eq(_T_10122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 810:103] + reg _T_10110 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 803:58] + _T_10110 <= bus_cmd_sent @[el2_ifu_mem_ctl.scala 803:58] + io.ifu_pmu_bus_busy <= _T_10110 @[el2_ifu_mem_ctl.scala 803:23] + node _T_10111 = eq(ifu_bus_arready_ff, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 804:80] + node _T_10112 = and(ifu_bus_arvalid_ff, _T_10111) @[el2_ifu_mem_ctl.scala 804:78] + node _T_10113 = and(_T_10112, miss_pending) @[el2_ifu_mem_ctl.scala 804:100] + reg _T_10114 : UInt<1>, io.active_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 804:58] + _T_10114 <= _T_10113 @[el2_ifu_mem_ctl.scala 804:58] + io.ifu_pmu_bus_trxn <= _T_10114 @[el2_ifu_mem_ctl.scala 804:23] + io.ic_debug_addr <= io.dec_tlu_ic_diag_pkt.icache_dicawics @[el2_ifu_mem_ctl.scala 807:20] + node _T_10115 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 16, 16) @[el2_ifu_mem_ctl.scala 808:66] + io.ic_debug_tag_array <= _T_10115 @[el2_ifu_mem_ctl.scala 808:25] + io.ic_debug_rd_en <= io.dec_tlu_ic_diag_pkt.icache_rd_valid @[el2_ifu_mem_ctl.scala 809:21] + io.ic_debug_wr_en <= io.dec_tlu_ic_diag_pkt.icache_wr_valid @[el2_ifu_mem_ctl.scala 810:21] + node _T_10116 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:64] + node _T_10117 = eq(_T_10116, UInt<2>("h03")) @[el2_ifu_mem_ctl.scala 811:71] + node _T_10118 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 811:117] + node _T_10119 = eq(_T_10118, UInt<2>("h02")) @[el2_ifu_mem_ctl.scala 811:124] + node _T_10120 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:43] + node _T_10121 = eq(_T_10120, UInt<1>("h01")) @[el2_ifu_mem_ctl.scala 812:50] + node _T_10122 = bits(io.dec_tlu_ic_diag_pkt.icache_dicawics, 15, 14) @[el2_ifu_mem_ctl.scala 812:96] + node _T_10123 = eq(_T_10122, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 812:103] node _T_10124 = cat(_T_10121, _T_10123) @[Cat.scala 29:58] node _T_10125 = cat(_T_10117, _T_10119) @[Cat.scala 29:58] node _T_10126 = cat(_T_10125, _T_10124) @[Cat.scala 29:58] - io.ic_debug_way <= _T_10126 @[el2_ifu_mem_ctl.scala 809:19] - node _T_10127 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 811:65] + io.ic_debug_way <= _T_10126 @[el2_ifu_mem_ctl.scala 811:19] + node _T_10127 = and(io.ic_debug_wr_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 813:65] node _T_10128 = bits(_T_10127, 0, 0) @[Bitwise.scala 72:15] node _T_10129 = mux(_T_10128, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] - node _T_10130 = and(_T_10129, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 811:90] - ic_debug_tag_wr_en <= _T_10130 @[el2_ifu_mem_ctl.scala 811:22] - node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 812:53] - node _T_10131 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 813:72] + node _T_10130 = and(_T_10129, io.ic_debug_way) @[el2_ifu_mem_ctl.scala 813:90] + ic_debug_tag_wr_en <= _T_10130 @[el2_ifu_mem_ctl.scala 813:22] + node ic_debug_ict_array_sel_in = and(io.ic_debug_rd_en, io.ic_debug_tag_array) @[el2_ifu_mem_ctl.scala 814:53] + node _T_10131 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 815:72] reg _T_10132 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10131 : @[Reg.scala 28:19] _T_10132 <= io.ic_debug_way @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_debug_way_ff <= _T_10132 @[el2_ifu_mem_ctl.scala 813:19] - node _T_10133 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 814:92] + ic_debug_way_ff <= _T_10132 @[el2_ifu_mem_ctl.scala 815:19] + node _T_10133 = or(io.ic_debug_rd_en, io.ic_debug_wr_en) @[el2_ifu_mem_ctl.scala 816:92] reg _T_10134 : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10133 : @[Reg.scala 28:19] _T_10134 <= ic_debug_ict_array_sel_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] - ic_debug_ict_array_sel_ff <= _T_10134 @[el2_ifu_mem_ctl.scala 814:29] - reg _T_10135 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 815:54] - _T_10135 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 815:54] - ic_debug_rd_en_ff <= _T_10135 @[el2_ifu_mem_ctl.scala 815:21] - node _T_10136 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 816:111] + ic_debug_ict_array_sel_ff <= _T_10134 @[el2_ifu_mem_ctl.scala 816:29] + reg _T_10135 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 817:54] + _T_10135 <= io.ic_debug_rd_en @[el2_ifu_mem_ctl.scala 817:54] + ic_debug_rd_en_ff <= _T_10135 @[el2_ifu_mem_ctl.scala 817:21] + node _T_10136 = bits(ic_debug_rd_en_ff, 0, 0) @[el2_ifu_mem_ctl.scala 818:111] reg _T_10137 : UInt, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] when _T_10136 : @[Reg.scala 28:19] _T_10137 <= ic_debug_rd_en_ff @[Reg.scala 28:23] skip @[Reg.scala 28:19] - io.ifu_ic_debug_rd_data_valid <= _T_10137 @[el2_ifu_mem_ctl.scala 816:33] + io.ifu_ic_debug_rd_data_valid <= _T_10137 @[el2_ifu_mem_ctl.scala 818:33] node _T_10138 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10139 = cat(UInt<1>("h00"), UInt<1>("h00")) @[Cat.scala 29:58] node _T_10140 = cat(_T_10139, _T_10138) @[Cat.scala 29:58] @@ -13392,62 +13392,62 @@ circuit el2_ifu_mem_ctl : node _T_10142 = cat(UInt<1>("h01"), UInt<1>("h01")) @[Cat.scala 29:58] node _T_10143 = cat(_T_10142, _T_10141) @[Cat.scala 29:58] node _T_10144 = cat(_T_10143, _T_10140) @[Cat.scala 29:58] - node _T_10145 = orr(_T_10144) @[el2_ifu_mem_ctl.scala 817:213] + node _T_10145 = orr(_T_10144) @[el2_ifu_mem_ctl.scala 819:213] node _T_10146 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10147 = or(_T_10146, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 818:62] - node _T_10148 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 818:110] - node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 818:85] - node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 818:27] - node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 817:216] + node _T_10147 = or(_T_10146, UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:62] + node _T_10148 = or(UInt<1>("h00"), UInt<31>("h07fffffff")) @[el2_ifu_mem_ctl.scala 820:110] + node _T_10149 = eq(_T_10147, _T_10148) @[el2_ifu_mem_ctl.scala 820:85] + node _T_10150 = and(UInt<1>("h01"), _T_10149) @[el2_ifu_mem_ctl.scala 820:27] + node _T_10151 = or(_T_10145, _T_10150) @[el2_ifu_mem_ctl.scala 819:216] node _T_10152 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10153 = or(_T_10152, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 819:62] - node _T_10154 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 819:110] - node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 819:85] - node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 819:27] - node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 818:134] + node _T_10153 = or(_T_10152, UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:62] + node _T_10154 = or(UInt<32>("h0c0000000"), UInt<30>("h03fffffff")) @[el2_ifu_mem_ctl.scala 821:110] + node _T_10155 = eq(_T_10153, _T_10154) @[el2_ifu_mem_ctl.scala 821:85] + node _T_10156 = and(UInt<1>("h01"), _T_10155) @[el2_ifu_mem_ctl.scala 821:27] + node _T_10157 = or(_T_10151, _T_10156) @[el2_ifu_mem_ctl.scala 820:134] node _T_10158 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10159 = or(_T_10158, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 820:62] - node _T_10160 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 820:110] - node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 820:85] - node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 820:27] - node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 819:134] + node _T_10159 = or(_T_10158, UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:62] + node _T_10160 = or(UInt<32>("h0a0000000"), UInt<29>("h01fffffff")) @[el2_ifu_mem_ctl.scala 822:110] + node _T_10161 = eq(_T_10159, _T_10160) @[el2_ifu_mem_ctl.scala 822:85] + node _T_10162 = and(UInt<1>("h01"), _T_10161) @[el2_ifu_mem_ctl.scala 822:27] + node _T_10163 = or(_T_10157, _T_10162) @[el2_ifu_mem_ctl.scala 821:134] node _T_10164 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10165 = or(_T_10164, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 821:62] - node _T_10166 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 821:110] - node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 821:85] - node _T_10168 = and(UInt<1>("h01"), _T_10167) @[el2_ifu_mem_ctl.scala 821:27] - node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 820:134] + node _T_10165 = or(_T_10164, UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:62] + node _T_10166 = or(UInt<32>("h080000000"), UInt<28>("h0fffffff")) @[el2_ifu_mem_ctl.scala 823:110] + node _T_10167 = eq(_T_10165, _T_10166) @[el2_ifu_mem_ctl.scala 823:85] + node _T_10168 = and(UInt<1>("h01"), _T_10167) @[el2_ifu_mem_ctl.scala 823:27] + node _T_10169 = or(_T_10163, _T_10168) @[el2_ifu_mem_ctl.scala 822:134] node _T_10170 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 822:62] - node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 822:110] - node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 822:85] - node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 822:27] - node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 821:134] + node _T_10171 = or(_T_10170, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62] + node _T_10172 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110] + node _T_10173 = eq(_T_10171, _T_10172) @[el2_ifu_mem_ctl.scala 824:85] + node _T_10174 = and(UInt<1>("h00"), _T_10173) @[el2_ifu_mem_ctl.scala 824:27] + node _T_10175 = or(_T_10169, _T_10174) @[el2_ifu_mem_ctl.scala 823:134] node _T_10176 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 823:62] - node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 823:110] - node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 823:85] - node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 823:27] - node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 822:134] + node _T_10177 = or(_T_10176, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62] + node _T_10178 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110] + node _T_10179 = eq(_T_10177, _T_10178) @[el2_ifu_mem_ctl.scala 825:85] + node _T_10180 = and(UInt<1>("h00"), _T_10179) @[el2_ifu_mem_ctl.scala 825:27] + node _T_10181 = or(_T_10175, _T_10180) @[el2_ifu_mem_ctl.scala 824:134] node _T_10182 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:62] - node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 824:110] - node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 824:85] - node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 824:27] - node _T_10187 = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 823:134] + node _T_10183 = or(_T_10182, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:62] + node _T_10184 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 826:110] + node _T_10185 = eq(_T_10183, _T_10184) @[el2_ifu_mem_ctl.scala 826:85] + node _T_10186 = and(UInt<1>("h00"), _T_10185) @[el2_ifu_mem_ctl.scala 826:27] + node _T_10187 = or(_T_10181, _T_10186) @[el2_ifu_mem_ctl.scala 825:134] node _T_10188 = cat(io.ifc_fetch_addr_bf, UInt<1>("h00")) @[Cat.scala 29:58] - node _T_10189 = or(_T_10188, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:62] - node _T_10190 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 825:110] - node _T_10191 = eq(_T_10189, _T_10190) @[el2_ifu_mem_ctl.scala 825:85] - node _T_10192 = and(UInt<1>("h00"), _T_10191) @[el2_ifu_mem_ctl.scala 825:27] - node ifc_region_acc_okay = or(_T_10187, _T_10192) @[el2_ifu_mem_ctl.scala 824:134] - node _T_10193 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 826:40] - node _T_10194 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 826:65] - node _T_10195 = and(_T_10193, _T_10194) @[el2_ifu_mem_ctl.scala 826:63] - node ifc_region_acc_fault_memory_bf = and(_T_10195, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 826:86] - node _T_10196 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 827:63] - ifc_region_acc_fault_final_bf <= _T_10196 @[el2_ifu_mem_ctl.scala 827:33] - reg _T_10197 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 828:66] - _T_10197 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 828:66] - ifc_region_acc_fault_memory_f <= _T_10197 @[el2_ifu_mem_ctl.scala 828:33] + node _T_10189 = or(_T_10188, UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:62] + node _T_10190 = or(UInt<1>("h00"), UInt<32>("h0ffffffff")) @[el2_ifu_mem_ctl.scala 827:110] + node _T_10191 = eq(_T_10189, _T_10190) @[el2_ifu_mem_ctl.scala 827:85] + node _T_10192 = and(UInt<1>("h00"), _T_10191) @[el2_ifu_mem_ctl.scala 827:27] + node ifc_region_acc_okay = or(_T_10187, _T_10192) @[el2_ifu_mem_ctl.scala 826:134] + node _T_10193 = eq(io.ifc_iccm_access_bf, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:40] + node _T_10194 = eq(ifc_region_acc_okay, UInt<1>("h00")) @[el2_ifu_mem_ctl.scala 828:65] + node _T_10195 = and(_T_10193, _T_10194) @[el2_ifu_mem_ctl.scala 828:63] + node ifc_region_acc_fault_memory_bf = and(_T_10195, io.ifc_fetch_req_bf) @[el2_ifu_mem_ctl.scala 828:86] + node _T_10196 = or(io.ifc_region_acc_fault_bf, ifc_region_acc_fault_memory_bf) @[el2_ifu_mem_ctl.scala 829:63] + ifc_region_acc_fault_final_bf <= _T_10196 @[el2_ifu_mem_ctl.scala 829:33] + reg _T_10197 : UInt<1>, io.free_clk with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_mem_ctl.scala 830:66] + _T_10197 <= ifc_region_acc_fault_memory_bf @[el2_ifu_mem_ctl.scala 830:66] + ifc_region_acc_fault_memory_f <= _T_10197 @[el2_ifu_mem_ctl.scala 830:33] diff --git a/el2_ifu_mem_ctl.v b/el2_ifu_mem_ctl.v index 7ddc14d2..dbdfcd81 100644 --- a/el2_ifu_mem_ctl.v +++ b/el2_ifu_mem_ctl.v @@ -2974,7 +2974,7 @@ module el2_ifu_mem_ctl( wire _T_9681 = _T_9680 | _T_9554; // @[el2_ifu_mem_ctl.scala 744:91] wire [1:0] ic_tag_valid_unq = {_T_10064,_T_9681}; // @[Cat.scala 29:58] reg [1:0] ic_debug_way_ff; // @[Reg.scala 27:20] - reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 815:54] + reg ic_debug_rd_en_ff; // @[el2_ifu_mem_ctl.scala 817:54] wire [1:0] _T_10103 = ic_debug_rd_en_ff ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] wire [1:0] _T_10104 = ic_debug_way_ff & _T_10103; // @[el2_ifu_mem_ctl.scala 798:67] wire [1:0] _T_10105 = ic_tag_valid_unq & _T_10104; // @[el2_ifu_mem_ctl.scala 798:48] @@ -3750,7 +3750,7 @@ module el2_ifu_mem_ctl( wire _T_10094 = bus_wren_last_0 | wren_reset_miss_0; // @[el2_ifu_mem_ctl.scala 780:73] wire [1:0] ifu_tag_wren = {_T_10095,_T_10094}; // @[Cat.scala 29:58] wire [1:0] _T_10129 = _T_3944 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - wire [1:0] ic_debug_tag_wr_en = _T_10129 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 811:90] + wire [1:0] ic_debug_tag_wr_en = _T_10129 & io_ic_debug_way; // @[el2_ifu_mem_ctl.scala 813:90] wire [1:0] ifu_tag_wren_w_debug = ifu_tag_wren | ic_debug_tag_wr_en; // @[el2_ifu_mem_ctl.scala 724:45] reg [1:0] ifu_tag_wren_ff; // @[el2_ifu_mem_ctl.scala 726:14] reg ic_valid_ff; // @[el2_ifu_mem_ctl.scala 730:14] @@ -4957,30 +4957,30 @@ module el2_ifu_mem_ctl( wire _T_10097 = ~fetch_uncacheable_ff; // @[el2_ifu_mem_ctl.scala 795:63] wire _T_10098 = _T_10097 & ifc_fetch_req_f; // @[el2_ifu_mem_ctl.scala 795:85] wire [1:0] _T_10100 = _T_10098 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] - reg _T_10107; // @[el2_ifu_mem_ctl.scala 800:58] - reg _T_10108; // @[el2_ifu_mem_ctl.scala 801:58] + reg _T_10107; // @[el2_ifu_mem_ctl.scala 800:57] + reg _T_10108; // @[el2_ifu_mem_ctl.scala 801:56] reg _T_10109; // @[el2_ifu_mem_ctl.scala 802:59] - wire _T_10110 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 803:78] - wire _T_10111 = ifu_bus_arvalid_ff & _T_10110; // @[el2_ifu_mem_ctl.scala 803:76] - wire _T_10112 = _T_10111 & miss_pending; // @[el2_ifu_mem_ctl.scala 803:98] - reg _T_10113; // @[el2_ifu_mem_ctl.scala 803:56] - reg _T_10114; // @[el2_ifu_mem_ctl.scala 804:57] - wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 809:71] - wire _T_10119 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 809:124] - wire _T_10121 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 810:50] - wire _T_10123 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 810:103] + reg _T_10110; // @[el2_ifu_mem_ctl.scala 803:58] + wire _T_10111 = ~ifu_bus_arready_ff; // @[el2_ifu_mem_ctl.scala 804:80] + wire _T_10112 = ifu_bus_arvalid_ff & _T_10111; // @[el2_ifu_mem_ctl.scala 804:78] + wire _T_10113 = _T_10112 & miss_pending; // @[el2_ifu_mem_ctl.scala 804:100] + reg _T_10114; // @[el2_ifu_mem_ctl.scala 804:58] + wire _T_10117 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h3; // @[el2_ifu_mem_ctl.scala 811:71] + wire _T_10119 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h2; // @[el2_ifu_mem_ctl.scala 811:124] + wire _T_10121 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h1; // @[el2_ifu_mem_ctl.scala 812:50] + wire _T_10123 = io_dec_tlu_ic_diag_pkt_icache_dicawics[15:14] == 2'h0; // @[el2_ifu_mem_ctl.scala 812:103] wire [3:0] _T_10126 = {_T_10117,_T_10119,_T_10121,_T_10123}; // @[Cat.scala 29:58] - wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 812:53] + wire ic_debug_ict_array_sel_in = io_ic_debug_rd_en & io_ic_debug_tag_array; // @[el2_ifu_mem_ctl.scala 814:53] reg _T_10137; // @[Reg.scala 27:20] assign io_ifu_miss_state_idle = miss_state == 3'h0; // @[el2_ifu_mem_ctl.scala 323:26] assign io_ifu_ic_mb_empty = _T_327 | _T_232; // @[el2_ifu_mem_ctl.scala 322:22] assign io_ic_dma_active = _T_11 | io_dec_tlu_flush_err_wb; // @[el2_ifu_mem_ctl.scala 187:20] assign io_ic_write_stall = write_ic_16_bytes & _T_3932; // @[el2_ifu_mem_ctl.scala 691:21] - assign io_ifu_pmu_ic_miss = _T_10114; // @[el2_ifu_mem_ctl.scala 804:22] - assign io_ifu_pmu_ic_hit = _T_10113; // @[el2_ifu_mem_ctl.scala 803:21] + assign io_ifu_pmu_ic_miss = _T_10107; // @[el2_ifu_mem_ctl.scala 800:22] + assign io_ifu_pmu_ic_hit = _T_10108; // @[el2_ifu_mem_ctl.scala 801:21] assign io_ifu_pmu_bus_error = _T_10109; // @[el2_ifu_mem_ctl.scala 802:24] - assign io_ifu_pmu_bus_busy = _T_10108; // @[el2_ifu_mem_ctl.scala 801:23] - assign io_ifu_pmu_bus_trxn = _T_10107; // @[el2_ifu_mem_ctl.scala 800:23] + assign io_ifu_pmu_bus_busy = _T_10110; // @[el2_ifu_mem_ctl.scala 803:23] + assign io_ifu_pmu_bus_trxn = _T_10114; // @[el2_ifu_mem_ctl.scala 804:23] assign io_ifu_axi_awvalid = 1'h0; // @[el2_ifu_mem_ctl.scala 138:22] assign io_ifu_axi_awid = 3'h0; // @[el2_ifu_mem_ctl.scala 137:19] assign io_ifu_axi_awaddr = 32'h0; // @[el2_ifu_mem_ctl.scala 132:21] @@ -5021,11 +5021,11 @@ module el2_ifu_mem_ctl( assign io_ic_wr_data_1 = ic_wr_16bytes_data[141:71]; // @[el2_ifu_mem_ctl.scala 339:17] assign io_ic_debug_wr_data = io_dec_tlu_ic_diag_pkt_icache_wrdata; // @[el2_ifu_mem_ctl.scala 340:23] assign io_ifu_ic_debug_rd_data = _T_1212; // @[el2_ifu_mem_ctl.scala 348:27] - assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 805:20] - assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 807:21] - assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 808:21] - assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 806:25] - assign io_ic_debug_way = _T_10126[1:0]; // @[el2_ifu_mem_ctl.scala 809:19] + assign io_ic_debug_addr = io_dec_tlu_ic_diag_pkt_icache_dicawics[9:0]; // @[el2_ifu_mem_ctl.scala 807:20] + assign io_ic_debug_rd_en = io_dec_tlu_ic_diag_pkt_icache_rd_valid; // @[el2_ifu_mem_ctl.scala 809:21] + assign io_ic_debug_wr_en = io_dec_tlu_ic_diag_pkt_icache_wr_valid; // @[el2_ifu_mem_ctl.scala 810:21] + assign io_ic_debug_tag_array = io_dec_tlu_ic_diag_pkt_icache_dicawics[16]; // @[el2_ifu_mem_ctl.scala 808:25] + assign io_ic_debug_way = _T_10126[1:0]; // @[el2_ifu_mem_ctl.scala 811:19] assign io_ic_tag_valid = ic_tag_valid_unq & _T_10100; // @[el2_ifu_mem_ctl.scala 795:19] assign io_iccm_rw_addr = _T_3064[14:0]; // @[el2_ifu_mem_ctl.scala 654:19] assign io_iccm_wren = _T_2633 | iccm_correct_ecc; // @[el2_ifu_mem_ctl.scala 625:16] @@ -5044,7 +5044,7 @@ module el2_ifu_mem_ctl( assign io_ic_data_f = io_ic_rd_data[31:0]; // @[el2_ifu_mem_ctl.scala 376:16] assign io_ic_premux_data = ic_premux_data[63:0]; // @[el2_ifu_mem_ctl.scala 373:21] assign io_ic_sel_premux_data = fetch_req_iccm_f | sel_byp_data; // @[el2_ifu_mem_ctl.scala 374:25] - assign io_ifu_ic_debug_rd_data_valid = _T_10137; // @[el2_ifu_mem_ctl.scala 816:33] + assign io_ifu_ic_debug_rd_data_valid = _T_10137; // @[el2_ifu_mem_ctl.scala 818:33] assign io_iccm_buf_correct_ecc = iccm_correct_ecc & _T_2416; // @[el2_ifu_mem_ctl.scala 472:27] assign io_iccm_correction_state = _T_2444 ? 1'h0 : _GEN_59; // @[el2_ifu_mem_ctl.scala 507:28 el2_ifu_mem_ctl.scala 520:32 el2_ifu_mem_ctl.scala 527:32 el2_ifu_mem_ctl.scala 534:32] `ifdef RANDOMIZE_GARBAGE_ASSIGN @@ -6015,7 +6015,7 @@ initial begin _RAND_465 = {1{`RANDOM}}; _T_10109 = _RAND_465[0:0]; _RAND_466 = {1{`RANDOM}}; - _T_10113 = _RAND_466[0:0]; + _T_10110 = _RAND_466[0:0]; _RAND_467 = {1{`RANDOM}}; _T_10114 = _RAND_467[0:0]; _RAND_468 = {1{`RANDOM}}; @@ -8524,14 +8524,14 @@ end // initial _T_10109 <= ifc_bus_acc_fault_f; end if (reset) begin - _T_10113 <= 1'h0; + _T_10110 <= 1'h0; end else begin - _T_10113 <= _T_10112; + _T_10110 <= bus_cmd_sent; end if (reset) begin _T_10114 <= 1'h0; end else begin - _T_10114 <= bus_cmd_sent; + _T_10114 <= _T_10113; end end endmodule diff --git a/src/main/scala/ifu/el2_ifu_mem_ctl.scala b/src/main/scala/ifu/el2_ifu_mem_ctl.scala index d147b2d2..31546706 100644 --- a/src/main/scala/ifu/el2_ifu_mem_ctl.scala +++ b/src/main/scala/ifu/el2_ifu_mem_ctl.scala @@ -797,11 +797,13 @@ class el2_ifu_mem_ctl extends Module with el2_lib { val ic_debug_way_ff = WireInit(UInt(ICACHE_NUM_WAYS.W), 0.U) ic_debug_tag_val_rd_out := (ic_tag_valid_unq & (ic_debug_way_ff & Fill(ICACHE_NUM_WAYS, ic_debug_rd_en_ff))).orR() - io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)} - io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)} + io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(ic_act_miss_f, false.B)} + io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ic_act_hit_f, false.B)} io.ifu_pmu_bus_error := withClock(io.active_clk){RegNext(ifc_bus_acc_fault_f, false.B)} - io.ifu_pmu_ic_hit := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)} - io.ifu_pmu_ic_miss := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)} + io.ifu_pmu_bus_busy := withClock(io.active_clk){RegNext(bus_cmd_sent, false.B)} + io.ifu_pmu_bus_trxn := withClock(io.active_clk){RegNext(ifu_bus_arvalid_ff & !ifu_bus_arready_ff & miss_pending, false.B)} + + io.ic_debug_addr := io.dec_tlu_ic_diag_pkt.icache_dicawics io.ic_debug_tag_array := io.dec_tlu_ic_diag_pkt.icache_dicawics(16) io.ic_debug_rd_en := io.dec_tlu_ic_diag_pkt.icache_rd_valid diff --git a/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class b/target/scala-2.12/classes/ifu/el2_ifu_mem_ctl.class index ab6dd46c5648a4630d86d69b9d5e9035686a06a7..c77b40be4420c63a8986a6e4ae77b06b12612015 100644 GIT binary patch delta 1440 zcmY*ZYitx%6y9^r>~?2&yE98^t1YE1E#2)4+HPCA+XtYM#upSq0tlfgBDFtQ=wn3^ z#V!a{%MXN{V|X1;U2?>qP0 zd*|L6JrO^8BL2v%b6!$5*-WUmgGtM72&@UL3I?(RZ>`HNFLr<}rfqV7rYtjDn{Ad6 z%lTui=YB5GwWd|U`n9Wr^-XWquWo8>-LZHqU331Ae7mV_$46szF8wLDBG_6l&-xv= z#?mK0!?v}&8*n(kk#?3t&Tk#+#$#EJ?{vd7Zcc?nc89^uonc7ehA`woRdj0@*0q3- zzjI?cXHCUAsNlO7VKQ%@io4l81kUHwP&m#{5vwy|b@f;xOA;(m7iH=GSj~eRba2Wg zm{_20jJs+=EnqU422H971doN|ym=AzLwUA@E#3cBXEUT>s-|{4Oa5^dCh^*ps3T=_ zT@)wr=^UI$*-v{lxuuucjfwn;8;hWrd)$~QFzCjGRHCop*?&SR&+}jslyIXaE86VA zX;h=XFg{nPVeJy6MgQ{P*(B(Q_Rhp9D0po)wt?W{7g05E#Y^ZV=-{2TxJc4FwYXc- zXy>cwFyzl(!(D=0Iv3xO^x#~4Y@}b-;bKW~K7vJ1S%is-V9HV)HH)k@j1Sh>fL@o- zyIK&8-h0|G!KgkO#6n4jgLol9@aV@_X5g*e*r-B?=Y4@+LnvxKfR`1)!GkzvHiz;e zw(I<91e2npN3qBlZfZBaoG-(z8OEiOo*Bj;k_ETl$DfQzt$Ko|fLk8Hgf2g2L1Nc( zYJ%jhAE{K{k10nEM{_PF@C=|7@NoMB`2+zVo5bsZJdn%#49Md%KqZu~&*H0VF_qIE zLLyQ=pA3or$OtIB04YQCU`*eJlqA`EyjP`E{vIg}3U)q(3_jk86BH`YOJa(b429r%;l_%@xwD_X*l0o}*B%9Px}pn8sTbDue0VzDy=I zsE||Q-xaE+B7GUpj>wS13OS&N7n-S9&dwIIEWU($%=DGwb(t>my&fs-u+ZyVq{=b; z$3hw0rcwy{xcD-paCaQd<>fY!a;zflv(bM3%}TYr)h^sZRk-tZ;gW5_9d}R`hisI| zPaML{u?u%QUbw?{;R>9>wK{}L(xi6CA+>L4w1+dSWZ}K>R11DCR%r^`os=o@1-q=% z&&}3x2ss6OoN4qu=M-~g%|yGZuT4I$$VdDjw*hl7U|G51b_L;07uk3Xyl{5S0xd zrqbblD*ttm%C1^z#)zHDN6M+m_jZ|@cJNa*Pk?%$?Ro*;J{+sux>egWk WRo^yIO|;)flb(l-(fbSNeaFAZGrTwe delta 1406 zcmZ8gZERCz6z)0aw(D)X_I9%y?t^uV(RQ%0wi|3?22hcxI6krj2!sVh=1ln5m(fIV z14cu}57+|71TX@L#DHOx*(%dzpfM(p3?j%J>*g2?O$>-GPGAtvU87Nd-1|J|dCocS zd*6HBvF^mN?!=A-y-5~jr^SG3lMNioTAl4^-_o06_1l2r&hE4Iy;o;BwVF+hRogZ< zR&8jkuWG1!YfJmeiLCZ(6UptNi3*4PZ@1>vs@H28+D9j{G9CZYHrLeG+w7l7N7E_$ z=Qg$FY|i7moiK}Q)4|1_FnFLO&Nm9@iZCQcKM2EXbx_7%dN7M~a&ejPd)Htpx8>sD z?3h6{fWcrm8%_x3Mbu__c7{!zU8czDWK+~hIsEG-NO!8c{v&EjczF~ux%>-EM9FDt zz;q6H&_y{~$>d6q!*6)dO)Uw->>dQy6g3o1D5Hqk9x*%r={{X6jqj_*gEmh49-iVo z9`wU(?($%^K+J=cRH$v`g}*^MFZE&y6mqpgzNE#A1yrs*8?SE-!(@F@^mi{_N`YO` zp7}Tp1xFTQ0|>5q4pkjDJdZ(wU3_pcu9WcZVmvHiwDo1Q>Gu0e@Q@%ERp6Tvo~*#f zdie1&TqPkcM=%L0E77G0rmev-qu7r1lg+BvW6&w`p*jS8?IR7CtXH3D#C!>d8u3c9 z;F&#GtmB=-Sgk^cmwtqwLMUoHf!7tm*h!o)8bf&z%Prm?!IbFO87$P><#ytWGo{_u zAzUNj#UcDARj_RwztcCh=?Pu{NIl@AB6+W)8gL!>mWsIU5hSr4$OXAv>%(N83zP;k zxak3A@D?D8@V9}yGBC$<@bX2V0Qs~9JiJZ*Yvx06A^G@xv*dT&1cg^1xy5gc`}>em zBzlLBs+7)OBV|I~!H3}HbFG-9P@WcuJ3-PNUQQGgXnG(&^h1(e`8c9WGr9Smj8uX` zDZ*<@WU-znXc4|hA)m~+`xIvKUWJMwpPSao#$pQDh5w?^GgP3h<%JPxIi!#c3b@ip z`WWpt%3&08myteE{7%C)zTYK&Oe)JF<&(at5nI&Qxd3|bF4ItQ!QekS&SVP zFsNOwhcwb8W#1o=!JQgq(L8Y`Pq5Xn!eXJPj?;@fGy0?JuFKu~7g3 diff --git a/target/scala-2.12/classes/ifu/ifu_mem$.class b/target/scala-2.12/classes/ifu/ifu_mem$.class index cb40c30421955f704ee0e17da46715dbf244c5c3..4cac2a579077a27f84ea400735d957381c346062 100644 GIT binary patch delta 99 zcmZ1?w?uBkOD;x-$*;I~gVx delta 19 ZcmaFB`hazVGZUlTWEZ9YAUT!E8vsE61>67t