From 37dda515de807d61f5817210c72681d75833c30b Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Mon, 14 Dec 2020 14:54:59 +0500 Subject: [PATCH] Bridge done --- {design/.idea => .idea}/.gitignore | 0 {design/.idea => .idea}/.name | 0 .../.idea => .idea}/codeStyles/Project.xml | 0 .../codeStyles/codeStyleConfig.xml | 0 {design/.idea => .idea}/compiler.xml | 0 {design/.idea => .idea}/edaphic/defines.xml | 0 .../inspectionProfiles/Project_Default.xml | 0 ...scala_time_nscala_time_2_12_2_22_0_jar.xml | 0 ..._com_github_scopt_scopt_2_12_3_7_1_jar.xml | 0 ...oogle_protobuf_protobuf_java_3_9_0_jar.xml | 0 .../sbt__com_lihaoyi_utest_2_12_0_6_6_jar.xml | 0 ...oughtworks_paranamer_paranamer_2_8_jar.xml | 0 ...edu_berkeley_cs_chisel3_2_12_3_3_1_jar.xml | 0 ...erkeley_cs_chisel3_core_2_12_3_3_1_jar.xml | 0 ...keley_cs_chisel3_macros_2_12_3_3_1_jar.xml | 0 ...ley_cs_chisel_iotesters_2_12_1_4_1_jar.xml | 0 ..._berkeley_cs_chiseltest_2_12_0_2_1_jar.xml | 0 ..._edu_berkeley_cs_firrtl_2_12_1_3_1_jar.xml | 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{design/src => src}/main/scala/dec/dec_tlu_ctl.scala (100%) rename {design/src => src}/main/scala/dec/dec_trigger.scala (100%) rename {design/src => src}/main/scala/dma_ctrl.scala (98%) rename {design/src => src}/main/scala/dmi/dmi_wrapper.scala (100%) rename {design/src => src}/main/scala/exu/exu.scala (100%) rename {design/src => src}/main/scala/exu/exu_alu_ctl.scala (100%) rename {design/src => src}/main/scala/exu/exu_div_ctl.scala (100%) rename {design/src => src}/main/scala/exu/exu_mul_ctl.scala (100%) rename {design/src => src}/main/scala/ifu/ifu.scala (90%) rename {design/src => src}/main/scala/ifu/ifu_aln_ctl.scala (100%) rename {design/src => src}/main/scala/ifu/ifu_bp_ctl.scala (100%) rename {design/src => src}/main/scala/ifu/ifu_compress_ctl.scala (100%) rename {design/src => src}/main/scala/ifu/ifu_ifc_ctl.scala (100%) rename {design/src => src}/main/scala/ifu/ifu_mem_ctl.scala (100%) rename {design/src => src}/main/scala/include/bundle.scala (98%) rename {design/src => src}/main/scala/lib/ahb_to_axi4.scala (69%) rename {design/src => src}/main/scala/lib/axi4_to_ahb.scala (77%) rename {design/src => src}/main/scala/lib/lib.scala (100%) rename {design/src => src}/main/scala/lib/param.scala (100%) rename {design/src => src}/main/scala/lsu/lsu.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_addrcheck.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_bus_buffer.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_bus_intf.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_clkdomain.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_dccm_ctl.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_ecc.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_lsc_ctl.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_stbuf.scala (100%) rename {design/src => src}/main/scala/lsu/lsu_trigger.scala (100%) rename {design/src => src}/main/scala/mem.scala (100%) rename {design/src => src}/main/scala/pic_ctrl.scala (100%) rename {design/src => src}/main/scala/quasar.scala (52%) rename {design/src => src}/main/scala/quasar_wrapper.scala (95%) rename {design/src => src}/test/scala/lib/Tester.scala (100%) rename {design/target => target}/.history (100%) rename {design/target => target}/global-logging/sbt-global-log13192661858450530136.log (100%) rename {design/target => target}/global-logging/sbt-global-log15583694003838645557.log (100%) rename {design/target => target}/global-logging/sbt-global-log3143817455308956308.log (100%) rename {design/target => target}/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar (100%) rename {design/target => target}/scala-2.12/chisel-module-template_2.12-3.3.0.jar (100%) rename {design/target => target}/scala-2.12/classes/.vscode/settings.json (100%) create mode 100644 target/scala-2.12/classes/QUASAR_Wrp$.class rename {design/target => target}/scala-2.12/classes/QUASAR_Wrp$delayedInit$body.class (100%) rename {design/target => target}/scala-2.12/classes/QUASAR_Wrp.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/dbg$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/dbg.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/dbg_dma.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/sb_state_t$.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/sb_state_t.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/state_t$.class (100%) rename {design/target => target}/scala-2.12/classes/dbg/state_t.class (100%) rename {design/target => target}/scala-2.12/classes/dec/CSR_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/CSR_VAL.class (100%) rename {design/target => target}/scala-2.12/classes/dec/CSRs.class (100%) rename {design/target => target}/scala-2.12/classes/dec/csr_tlu.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_dec_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_dec_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_decode_csr_read.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_decode_csr_read_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_decode_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_decode_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_gpr_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_gpr_ctl_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_ib_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_ib_ctl_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_timer_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_timer_ctl_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_tlu_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_tlu_ctl_IO.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_trigger$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dec/dec_trigger.class (100%) rename {design/target => target}/scala-2.12/classes/dma_ctrl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dma_ctrl.class (100%) rename {design/target => target}/scala-2.12/classes/dmi/dmi_wrapper$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/dmi/dmi_wrapper.class (100%) rename {design/target => target}/scala-2.12/classes/dmi/dmi_wrapper_module$$anon$2.class (100%) rename {design/target => target}/scala-2.12/classes/dmi/dmi_wrapper_module.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_alu_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_alu_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_div_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_div_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_mul_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/exu/exu_mul_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_aln_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_aln_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_bp_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_bp_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_compress_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_compress_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_ifc_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_ifc_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/ifu_mem_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/ifu/mem_ctl_io.class (100%) rename {design/target => target}/scala-2.12/classes/include/ahb_channel.class (100%) rename {design/target => target}/scala-2.12/classes/include/ahb_in.class (100%) rename {design/target => target}/scala-2.12/classes/include/ahb_out.class (100%) rename {design/target => target}/scala-2.12/classes/include/ahb_out_dma.class (100%) rename {design/target => target}/scala-2.12/classes/include/aln_dec.class (90%) rename {design/target => target}/scala-2.12/classes/include/aln_ib.class (53%) rename {design/target => target}/scala-2.12/classes/include/alu_pkt_t.class (58%) rename {design/target => target}/scala-2.12/classes/include/axi_channels$.class (85%) rename {design/target => target}/scala-2.12/classes/include/axi_channels.class (100%) rename {design/target => target}/scala-2.12/classes/include/br_pkt_t.class (75%) rename {design/target => target}/scala-2.12/classes/include/br_tlu_pkt_t.class (77%) rename {design/target => target}/scala-2.12/classes/include/cache_debug_pkt_t.class (82%) rename {design/target => target}/scala-2.12/classes/include/ccm_ext_in_pkt_t.class (73%) rename {design/target => target}/scala-2.12/classes/include/class_pkt_t.class (84%) rename {design/target => target}/scala-2.12/classes/include/dbg_dctl.class (90%) rename {design/target => target}/scala-2.12/classes/include/dbg_ib.class (84%) rename {design/target => target}/scala-2.12/classes/include/dccm_ext_in_pkt_t.class (73%) rename {design/target => target}/scala-2.12/classes/include/dctl_busbuff.class (52%) rename {design/target => target}/scala-2.12/classes/include/dctl_dma.class (100%) rename {design/target => target}/scala-2.12/classes/include/dec_aln.class (51%) rename {design/target => target}/scala-2.12/classes/include/dec_alu.class (85%) rename {design/target => target}/scala-2.12/classes/include/dec_bp.class (100%) rename {design/target => target}/scala-2.12/classes/include/dec_dbg.class (85%) rename {design/target => target}/scala-2.12/classes/include/dec_div.class (90%) rename {design/target => target}/scala-2.12/classes/include/dec_dma.class (100%) rename {design/target => target}/scala-2.12/classes/include/dec_exu.class (51%) rename {design/target => target}/scala-2.12/classes/include/dec_ifc.class (100%) rename {design/target => target}/scala-2.12/classes/include/dec_mem_ctrl.class (97%) rename {design/target => target}/scala-2.12/classes/include/dec_pic.class (100%) rename {design/target => target}/scala-2.12/classes/include/dec_pkt_t.class (59%) rename {design/target => target}/scala-2.12/classes/include/dec_tlu_csr_pkt.class (65%) rename {design/target => target}/scala-2.12/classes/include/decode_exu.class (53%) rename {design/target => target}/scala-2.12/classes/include/dest_pkt_t.class (75%) rename {design/target => target}/scala-2.12/classes/include/div_pkt_t.class (85%) rename {design/target => target}/scala-2.12/classes/include/dma_dccm_ctl.class (81%) rename {design/target => target}/scala-2.12/classes/include/dma_ifc.class (90%) rename {design/target => target}/scala-2.12/classes/include/dma_lsc_ctl.class (81%) rename {design/target => target}/scala-2.12/classes/include/dma_mem_ctl.class (81%) rename {design/target => target}/scala-2.12/classes/include/exu_bp.class (53%) rename {design/target => target}/scala-2.12/classes/include/exu_ifu.class (84%) rename {design/target => target}/scala-2.12/classes/include/gpr_exu.class (88%) rename {design/target => target}/scala-2.12/classes/include/ib_exu.class (88%) rename {design/target => target}/scala-2.12/classes/include/ic_data_ext_in_pkt_t.class (73%) rename {design/target => target}/scala-2.12/classes/include/ic_mem.class (53%) rename {design/target => target}/scala-2.12/classes/include/ic_tag_ext_in_pkt_t.class (73%) rename {design/target => target}/scala-2.12/classes/include/iccm_mem.class (52%) rename {design/target => target}/scala-2.12/classes/include/ifu_dec.class (79%) rename {design/target => target}/scala-2.12/classes/include/ifu_dma.class (85%) rename {design/target => target}/scala-2.12/classes/include/inst_pkt_t$.class (62%) rename {design/target => target}/scala-2.12/classes/include/inst_pkt_t.class (100%) rename {design/target => target}/scala-2.12/classes/include/load_cam_pkt_t.class (84%) rename {design/target => target}/scala-2.12/classes/include/lsu_dec.class (85%) rename {design/target => target}/scala-2.12/classes/include/lsu_dma.class (85%) rename {design/target => target}/scala-2.12/classes/include/lsu_error_pkt_t.class (78%) rename {design/target => target}/scala-2.12/classes/include/lsu_exu.class (88%) rename {design/target => target}/scala-2.12/classes/include/lsu_pic.class (78%) rename {design/target => target}/scala-2.12/classes/include/lsu_pkt_t.class (69%) rename {design/target => target}/scala-2.12/classes/include/lsu_tlu.class (85%) rename {design/target => target}/scala-2.12/classes/include/mul_pkt_t.class (70%) rename {design/target => target}/scala-2.12/classes/include/predict_pkt_t.class (74%) create mode 100644 target/scala-2.12/classes/include/read_addr.class create mode 100644 target/scala-2.12/classes/include/read_data.class rename {design/target => target}/scala-2.12/classes/include/reg_pkt_t.class (84%) rename {design/target => target}/scala-2.12/classes/include/rets_pkt_t.class (84%) rename {design/target => target}/scala-2.12/classes/include/tlu_busbuff.class (80%) rename {design/target => target}/scala-2.12/classes/include/tlu_dma.class (100%) rename {design/target => target}/scala-2.12/classes/include/tlu_exu.class (52%) rename {design/target => target}/scala-2.12/classes/include/trace_pkt_t.class (79%) rename {design/target => target}/scala-2.12/classes/include/trap_pkt_t.class (72%) rename {design/target => target}/scala-2.12/classes/include/trigger_pkt_t.class (74%) create mode 100644 target/scala-2.12/classes/include/write_addr.class rename {design/target => target}/scala-2.12/classes/include/write_data.class (100%) create mode 100644 target/scala-2.12/classes/include/write_resp.class rename {design/target => target}/scala-2.12/classes/lib/Config.class (100%) rename {design/target => target}/scala-2.12/classes/lib/ahb_to_axi4$$anon$1$$anon$2.class (79%) create mode 100644 target/scala-2.12/classes/lib/ahb_to_axi4$$anon$1.class create mode 100644 target/scala-2.12/classes/lib/ahb_to_axi4.class create mode 100644 target/scala-2.12/classes/lib/axi4_to_ahb.class create mode 100644 target/scala-2.12/classes/lib/axi4_to_ahb_IO.class rename {design/target => target}/scala-2.12/classes/lib/lib$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$gated_latch.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvclkhdr$.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvclkhdr.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvdffe$.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvecc_encode.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvecc_encode_64.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib$rvsyncss$.class (100%) rename {design/target => target}/scala-2.12/classes/lib/lib.class (100%) rename {design/target => target}/scala-2.12/classes/lib/param.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_addrcheck.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_bus_buffer.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_bus_intf.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_clkdomain.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_dccm_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_ecc.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_lsc_ctl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_lsc_ctl.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_stbuf$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_stbuf.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_trigger$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/lsu/lsu_trigger.class (100%) rename {design/target => target}/scala-2.12/classes/mem/Mem_bundle.class (100%) rename {design/target => target}/scala-2.12/classes/mem/blackbox_mem.class (100%) rename {design/target => target}/scala-2.12/classes/mem/mem_lsu.class (100%) rename {design/target => target}/scala-2.12/classes/mem/quasar$.class (100%) rename {design/target => target}/scala-2.12/classes/mem/quasar$mem.class (100%) rename {design/target => target}/scala-2.12/classes/mem/quasar.class (100%) rename {design/target => target}/scala-2.12/classes/pic_ctrl$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/pic_ctrl.class (100%) create mode 100644 target/scala-2.12/classes/quasar.class rename {design/target => target}/scala-2.12/classes/quasar_bundle$$anon$1.class (91%) rename {design/target => target}/scala-2.12/classes/quasar_bundle.class (99%) rename {design/target => target}/scala-2.12/classes/quasar_wrapper$$anon$1.class (100%) rename {design/target => target}/scala-2.12/classes/quasar_wrapper.class (94%) rename {design/target => target}/scala-2.12/classes/vsrc/beh_lib.sv (100%) rename {design/target => target}/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv (100%) create mode 100644 target/scala-2.12/classes/vsrc/dmi_wrapper.sv rename {design/target => target}/scala-2.12/classes/vsrc/gated_latch.sv (100%) create mode 100644 target/scala-2.12/classes/vsrc/gated_latch.v rename {design/target => target}/scala-2.12/classes/vsrc/ifu_ic_mem.sv (100%) rename {design/target => target}/scala-2.12/classes/vsrc/ifu_iccm_mem.sv (100%) rename {design/target => target}/scala-2.12/classes/vsrc/lsu_dccm_mem.sv (100%) create mode 100644 target/scala-2.12/classes/vsrc/mem.sv rename {design/target => target}/scala-2.12/classes/vsrc/mem_lib.sv (100%) rename {design/target => target}/scala-2.12/classes/vsrc/mem_mod.sv (100%) rename {design/target => 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a/design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml b/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml similarity index 100% rename from design/.idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml rename to .idea/libraries/sbt__org_yaml_snakeyaml_1_26_jar.xml diff --git a/design/.idea/misc.xml b/.idea/misc.xml similarity index 100% rename from design/.idea/misc.xml rename to .idea/misc.xml diff --git a/design/.idea/modules.xml b/.idea/modules.xml similarity index 100% rename from design/.idea/modules.xml rename to .idea/modules.xml diff --git a/design/.idea/modules/chisel-module-template-build.iml b/.idea/modules/chisel-module-template-build.iml similarity index 100% rename from design/.idea/modules/chisel-module-template-build.iml rename to .idea/modules/chisel-module-template-build.iml diff --git a/design/.idea/modules/chisel-module-template.iml b/.idea/modules/chisel-module-template.iml similarity index 100% rename from design/.idea/modules/chisel-module-template.iml rename to .idea/modules/chisel-module-template.iml diff --git a/design/.idea/sbt.xml b/.idea/sbt.xml similarity index 100% rename from design/.idea/sbt.xml rename to .idea/sbt.xml diff --git a/design/.idea/scala_compiler.xml b/.idea/scala_compiler.xml similarity index 100% rename from design/.idea/scala_compiler.xml rename to .idea/scala_compiler.xml diff --git a/design/.idea/vcs.xml b/.idea/vcs.xml similarity index 100% rename from design/.idea/vcs.xml rename to .idea/vcs.xml diff --git a/ahb_to_axi4.anno.json b/ahb_to_axi4.anno.json new file mode 100644 index 00000000..e256d28b --- /dev/null +++ b/ahb_to_axi4.anno.json @@ -0,0 +1,34 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hready", + "sources":[ + "~ahb_to_axi4|ahb_to_axi4>io_ahb_sig_in_hresp", + "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_valid", + "~ahb_to_axi4|ahb_to_axi4>io_axi_aw_ready", + "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_valid", + "~ahb_to_axi4|ahb_to_axi4>io_axi_ar_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"ahb_to_axi4.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"ahb_to_axi4" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/ahb_to_axi4.fir b/ahb_to_axi4.fir new file mode 100644 index 00000000..1ae07a04 --- /dev/null +++ b/ahb_to_axi4.fir @@ -0,0 +1,615 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit ahb_to_axi4 : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module ahb_to_axi4 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} + + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] + _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] + _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] + _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] + _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] + io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] + _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] + _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] + _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] + _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] + io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] + io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] + _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] + _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] + wire master_wstrb : UInt<8> + master_wstrb <= UInt<8>("h00") + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire buf_read_error_in : UInt<1> + buf_read_error_in <= UInt<1>("h00") + wire buf_read_error : UInt<1> + buf_read_error <= UInt<1>("h00") + wire buf_rdata : UInt<64> + buf_rdata <= UInt<64>("h00") + wire ahb_hready : UInt<1> + ahb_hready <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_htrans_in : UInt<2> + ahb_htrans_in <= UInt<2>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hsize_q : UInt<3> + ahb_hsize_q <= UInt<3>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_haddr_q : UInt<32> + ahb_haddr_q <= UInt<32>("h00") + wire ahb_hwdata_q : UInt<64> + ahb_hwdata_q <= UInt<64>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire buf_rdata_en : UInt<1> + buf_rdata_en <= UInt<1>("h00") + wire ahb_bus_addr_clk_en : UInt<1> + ahb_bus_addr_clk_en <= UInt<1>("h00") + wire buf_rdata_clk_en : UInt<1> + buf_rdata_clk_en <= UInt<1>("h00") + wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33] + wire cmdbuf_wr_en : UInt<1> + cmdbuf_wr_en <= UInt<1>("h00") + wire cmdbuf_rst : UInt<1> + cmdbuf_rst <= UInt<1>("h00") + wire cmdbuf_full : UInt<1> + cmdbuf_full <= UInt<1>("h00") + wire cmdbuf_vld : UInt<1> + cmdbuf_vld <= UInt<1>("h00") + wire cmdbuf_write : UInt<1> + cmdbuf_write <= UInt<1>("h00") + wire cmdbuf_size : UInt<2> + cmdbuf_size <= UInt<2>("h00") + wire cmdbuf_wstrb : UInt<8> + cmdbuf_wstrb <= UInt<8>("h00") + wire cmdbuf_addr : UInt<32> + cmdbuf_addr <= UInt<32>("h00") + wire cmdbuf_wdata : UInt<64> + cmdbuf_wdata <= UInt<64>("h00") + wire bus_clk : Clock @[ahb_to_axi4.scala 58:33] + node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] + node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] + node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] + node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] + node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] + wire buf_state : UInt<2> + buf_state <= UInt<2>("h00") + wire buf_nxtstate : UInt<2> + buf_nxtstate <= UInt<2>("h00") + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] + node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_7 : @[Conditional.scala 40:58] + node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26] + buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20] + node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57] + node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34] + node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61] + buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_12 : @[Conditional.scala 39:67] + node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79] + node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48] + node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93] + node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91] + node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107] + node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124] + node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26] + buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20] + node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24] + node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37] + buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20] + node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23] + node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85] + node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92] + node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110] + node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38] + node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36] + cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_30 : @[Conditional.scala 39:67] + node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26] + buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20] + node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24] + node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37] + buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20] + node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23] + node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46] + node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44] + cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_37 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20] + node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40] + node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38] + buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20] + node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61] + node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68] + node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41] + buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25] + skip @[Conditional.scala 39:67] + node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99] + reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_43 : @[Reg.scala 28:19] + _T_44 <= buf_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state <= _T_44 @[ahb_to_axi4.scala 96:31] + node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60] + node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92] + node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78] + node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70] + node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30] + node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] + node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] + node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48] + node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40] + node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109] + node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] + node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48] + node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40] + node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79] + node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30] + node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] + node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40] + node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79] + master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31] + node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80] + node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78] + node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98] + node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124] + node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111] + node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149] + node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168] + node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137] + node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135] + node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181] + node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179] + node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44] + io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38] + node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55] + ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31] + node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] + node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77] + node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54] + ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31] + node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50] + io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38] + node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55] + node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61] + node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83] + node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70] + node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7] + node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46] + node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26] + node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80] + node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86] + node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109] + node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115] + node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66] + node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64] + node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47] + node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] + node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26] + node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48] + node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35] + node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126] + node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] + node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26] + node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49] + node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56] + node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35] + node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55] + node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] + node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26] + node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49] + node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56] + node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35] + node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61] + node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94] + node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63] + node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20] + node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18] + node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20] + io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38] + reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66] + _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66] + buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60] + _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60] + buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] + _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60] + ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31] + reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] + _T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60] + ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31] + reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] + _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60] + ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31] + reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] + _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65] + ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31] + reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] + _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65] + ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31] + reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] + _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65] + ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31] + node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85] + node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62] + node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48] + ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31] + node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48] + buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31] + inst rvclkhdr of rvclkhdr @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 343:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31] + node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53] + node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91] + node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72] + node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113] + node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111] + node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153] + node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151] + node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128] + cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31] + node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67] + node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105] + node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48] + node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46] + cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31] + node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86] + node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66] + node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110] + node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108] + reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61] + _T_160 <= _T_159 @[ahb_to_axi4.scala 140:61] + cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31] + node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53] + reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_161 : @[Reg.scala 28:19] + _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31] + node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52] + reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_163 : @[Reg.scala 28:19] + _T_164 <= ahb_hsize_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31] + node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53] + reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_165 : @[Reg.scala 28:19] + _T_166 <= master_wstrb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31] + node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_168 <= ahb_haddr_q @[lib.scala 374:16] + cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15] + node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] + cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16] + node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42] + io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28] + io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33] + io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33] + node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59] + node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] + io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33] + node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33] + node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33] + io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33] + node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42] + io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28] + io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33] + io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33] + io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33] + io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28] + node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44] + node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42] + io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28] + io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33] + io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33] + node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59] + node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] + io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33] + node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33] + node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33] + io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33] + io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 343:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27] + diff --git a/ahb_to_axi4.v b/ahb_to_axi4.v new file mode 100644 index 00000000..b65746cd --- /dev/null +++ b/ahb_to_axi4.v @@ -0,0 +1,584 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module ahb_to_axi4( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + input io_axi_aw_ready, + output io_axi_aw_valid, + output io_axi_aw_bits_id, + output [31:0] io_axi_aw_bits_addr, + output [3:0] io_axi_aw_bits_region, + output [7:0] io_axi_aw_bits_len, + output [2:0] io_axi_aw_bits_size, + output [1:0] io_axi_aw_bits_burst, + output io_axi_aw_bits_lock, + output [3:0] io_axi_aw_bits_cache, + output [2:0] io_axi_aw_bits_prot, + output [3:0] io_axi_aw_bits_qos, + input io_axi_w_ready, + output io_axi_w_valid, + output [63:0] io_axi_w_bits_data, + output [7:0] io_axi_w_bits_strb, + output io_axi_w_bits_last, + output io_axi_b_ready, + input io_axi_b_valid, + input [1:0] io_axi_b_bits_resp, + input io_axi_b_bits_id, + input io_axi_ar_ready, + output io_axi_ar_valid, + output io_axi_ar_bits_id, + output [31:0] io_axi_ar_bits_addr, + output [3:0] io_axi_ar_bits_region, + output [7:0] io_axi_ar_bits_len, + output [2:0] io_axi_ar_bits_size, + output [1:0] io_axi_ar_bits_burst, + output io_axi_ar_bits_lock, + output [3:0] io_axi_ar_bits_cache, + output [2:0] io_axi_ar_bits_prot, + output [3:0] io_axi_ar_bits_qos, + output io_axi_r_ready, + input io_axi_r_valid, + input io_axi_r_bits_id, + input [63:0] io_axi_r_bits_data, + input [1:0] io_axi_r_bits_resp, + input io_axi_r_bits_last, + output [63:0] io_ahb_sig_in_hrdata, + output io_ahb_sig_in_hready, + output io_ahb_sig_in_hresp, + input [31:0] io_ahb_sig_out_haddr, + input [2:0] io_ahb_sig_out_hburst, + input io_ahb_sig_out_hmastlock, + input [3:0] io_ahb_sig_out_hprot, + input [2:0] io_ahb_sig_out_hsize, + input [1:0] io_ahb_sig_out_htrans, + input io_ahb_sig_out_hwrite, + input [63:0] io_ahb_sig_out_hwdata, + input io_ahb_hsel, + input io_ahb_hreadyin +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [63:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [31:0] _RAND_12; + reg [31:0] _RAND_13; + reg [63:0] _RAND_14; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire ahb_addr_clk = rvclkhdr_1_io_l1clk; // @[ahb_to_axi4.scala 45:33 ahb_to_axi4.scala 134:31] + reg [31:0] ahb_haddr_q; // @[ahb_to_axi4.scala 127:65] + wire ahb_addr_in_dccm = ahb_haddr_q[31:16] == 16'hf004; // @[lib.scala 87:29] + wire ahb_addr_in_iccm = ahb_haddr_q[31:16] == 16'hee00; // @[lib.scala 87:29] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + reg [1:0] buf_state; // @[Reg.scala 27:20] + wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] + wire ahb_hready = io_ahb_sig_in_hready & io_ahb_hreadyin; // @[ahb_to_axi4.scala 105:55] + wire _T_10 = ahb_hready & io_ahb_sig_out_htrans[1]; // @[ahb_to_axi4.scala 77:34] + wire _T_11 = _T_10 & io_ahb_hsel; // @[ahb_to_axi4.scala 77:61] + wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_14 = io_ahb_sig_out_htrans == 2'h0; // @[ahb_to_axi4.scala 80:79] + wire _T_15 = io_ahb_sig_in_hresp | _T_14; // @[ahb_to_axi4.scala 80:48] + wire _T_16 = ~io_ahb_hsel; // @[ahb_to_axi4.scala 80:93] + wire _T_17 = _T_15 | _T_16; // @[ahb_to_axi4.scala 80:91] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] + wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67] + wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] + wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86] + wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] + wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] + wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] + wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37] + wire _T_25 = io_ahb_sig_out_htrans == 2'h1; // @[ahb_to_axi4.scala 82:92] + wire _T_26 = _T_25 & io_ahb_hsel; // @[ahb_to_axi4.scala 82:110] + wire _T_27 = io_ahb_sig_in_hresp | _T_26; // @[ahb_to_axi4.scala 82:60] + wire _T_28 = ~_T_27; // @[ahb_to_axi4.scala 82:38] + wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36] + wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_34 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 87:23] + wire _T_36 = _T_34 & _T_21; // @[ahb_to_axi4.scala 87:44] + wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] + reg cmdbuf_write; // @[Reg.scala 27:20] + wire _T_38 = ~cmdbuf_write; // @[ahb_to_axi4.scala 91:40] + wire _T_39 = io_axi_r_valid & _T_38; // @[ahb_to_axi4.scala 91:38] + wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68] + wire _GEN_1 = _T_37 & _T_39; // @[Conditional.scala 39:67] + wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] + wire buf_state_en = _T_7 ? _T_11 : _GEN_10; // @[Conditional.scala 40:58] + wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41] + wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] + wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] + reg [2:0] ahb_hsize_q; // @[ahb_to_axi4.scala 125:65] + wire _T_46 = ahb_hsize_q == 3'h0; // @[ahb_to_axi4.scala 98:60] + wire [7:0] _T_48 = _T_46 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [7:0] _T_50 = 8'h1 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 98:78] + wire [7:0] _T_51 = _T_48 & _T_50; // @[ahb_to_axi4.scala 98:70] + wire _T_53 = ahb_hsize_q == 3'h1; // @[ahb_to_axi4.scala 99:30] + wire [7:0] _T_55 = _T_53 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [8:0] _T_57 = 9'h3 << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 99:48] + wire [8:0] _GEN_23 = {{1'd0}, _T_55}; // @[ahb_to_axi4.scala 99:40] + wire [8:0] _T_58 = _GEN_23 & _T_57; // @[ahb_to_axi4.scala 99:40] + wire [8:0] _GEN_24 = {{1'd0}, _T_51}; // @[ahb_to_axi4.scala 98:109] + wire [8:0] _T_59 = _GEN_24 | _T_58; // @[ahb_to_axi4.scala 98:109] + wire _T_61 = ahb_hsize_q == 3'h2; // @[ahb_to_axi4.scala 100:30] + wire [7:0] _T_63 = _T_61 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _T_65 = 11'hf << ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 100:48] + wire [10:0] _GEN_25 = {{3'd0}, _T_63}; // @[ahb_to_axi4.scala 100:40] + wire [10:0] _T_66 = _GEN_25 & _T_65; // @[ahb_to_axi4.scala 100:40] + wire [10:0] _GEN_26 = {{2'd0}, _T_59}; // @[ahb_to_axi4.scala 99:79] + wire [10:0] _T_67 = _GEN_26 | _T_66; // @[ahb_to_axi4.scala 99:79] + wire _T_69 = ahb_hsize_q == 3'h3; // @[ahb_to_axi4.scala 101:30] + wire [7:0] _T_71 = _T_69 ? 8'hff : 8'h0; // @[Bitwise.scala 72:12] + wire [10:0] _GEN_27 = {{3'd0}, _T_71}; // @[ahb_to_axi4.scala 100:79] + wire [10:0] _T_73 = _T_67 | _GEN_27; // @[ahb_to_axi4.scala 100:79] + reg ahb_hready_q; // @[ahb_to_axi4.scala 123:60] + wire _T_74 = ~ahb_hready_q; // @[ahb_to_axi4.scala 104:80] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60] + wire _T_75 = ahb_hresp_q & _T_74; // @[ahb_to_axi4.scala 104:78] + wire _T_77 = buf_state == 2'h0; // @[ahb_to_axi4.scala 104:124] + wire _T_78 = _T_21 | _T_77; // @[ahb_to_axi4.scala 104:111] + wire _T_79 = buf_state == 2'h2; // @[ahb_to_axi4.scala 104:149] + wire _T_80 = buf_state == 2'h3; // @[ahb_to_axi4.scala 104:168] + wire _T_81 = _T_79 | _T_80; // @[ahb_to_axi4.scala 104:156] + wire _T_82 = ~_T_81; // @[ahb_to_axi4.scala 104:137] + wire _T_83 = _T_78 & _T_82; // @[ahb_to_axi4.scala 104:135] + reg buf_read_error; // @[ahb_to_axi4.scala 119:60] + wire _T_84 = ~buf_read_error; // @[ahb_to_axi4.scala 104:181] + wire _T_85 = _T_83 & _T_84; // @[ahb_to_axi4.scala 104:179] + wire [1:0] _T_89 = io_ahb_hsel ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire buf_rdata_clk = rvclkhdr_2_io_l1clk; // @[ahb_to_axi4.scala 46:33 ahb_to_axi4.scala 135:31] + reg [63:0] buf_rdata; // @[ahb_to_axi4.scala 118:66] + reg [1:0] ahb_htrans_q; // @[ahb_to_axi4.scala 124:60] + wire _T_94 = ahb_htrans_q != 2'h0; // @[ahb_to_axi4.scala 108:61] + wire _T_95 = buf_state != 2'h0; // @[ahb_to_axi4.scala 108:83] + wire _T_96 = _T_94 & _T_95; // @[ahb_to_axi4.scala 108:70] + wire _T_97 = ahb_addr_in_dccm | ahb_addr_in_iccm; // @[ahb_to_axi4.scala 109:26] + wire _T_98 = ~_T_97; // @[ahb_to_axi4.scala 109:7] + reg ahb_hwrite_q; // @[ahb_to_axi4.scala 126:65] + wire _T_99 = ahb_addr_in_dccm & ahb_hwrite_q; // @[ahb_to_axi4.scala 110:46] + wire _T_100 = ahb_addr_in_iccm | _T_99; // @[ahb_to_axi4.scala 110:26] + wire _T_102 = ahb_hsize_q[1:0] == 2'h2; // @[ahb_to_axi4.scala 110:86] + wire _T_104 = ahb_hsize_q[1:0] == 2'h3; // @[ahb_to_axi4.scala 110:115] + wire _T_105 = _T_102 | _T_104; // @[ahb_to_axi4.scala 110:95] + wire _T_106 = ~_T_105; // @[ahb_to_axi4.scala 110:66] + wire _T_107 = _T_100 & _T_106; // @[ahb_to_axi4.scala 110:64] + wire _T_108 = _T_98 | _T_107; // @[ahb_to_axi4.scala 109:47] + wire _T_112 = _T_53 & ahb_haddr_q[0]; // @[ahb_to_axi4.scala 111:35] + wire _T_113 = _T_108 | _T_112; // @[ahb_to_axi4.scala 110:126] + wire _T_117 = |ahb_haddr_q[1:0]; // @[ahb_to_axi4.scala 112:56] + wire _T_118 = _T_61 & _T_117; // @[ahb_to_axi4.scala 112:35] + wire _T_119 = _T_113 | _T_118; // @[ahb_to_axi4.scala 111:55] + wire _T_123 = |ahb_haddr_q[2:0]; // @[ahb_to_axi4.scala 113:56] + wire _T_124 = _T_69 & _T_123; // @[ahb_to_axi4.scala 113:35] + wire _T_125 = _T_119 | _T_124; // @[ahb_to_axi4.scala 112:61] + wire _T_126 = _T_96 & _T_125; // @[ahb_to_axi4.scala 108:94] + wire _T_127 = _T_126 | buf_read_error; // @[ahb_to_axi4.scala 113:63] + wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113] + wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111] + wire _T_149 = io_ahb_sig_in_hresp & _T_38; // @[ahb_to_axi4.scala 137:151] + wire cmdbuf_rst = _T_147 | _T_149; // @[ahb_to_axi4.scala 137:128] + wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66] + wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110] + reg [2:0] _T_164; // @[Reg.scala 27:20] + reg [7:0] cmdbuf_wstrb; // @[Reg.scala 27:20] + wire [7:0] master_wstrb = _T_73[7:0]; // @[ahb_to_axi4.scala 98:31] + reg [31:0] cmdbuf_addr; // @[lib.scala 374:16] + reg [63:0] cmdbuf_wdata; // @[lib.scala 374:16] + wire [1:0] cmdbuf_size = _T_164[1:0]; // @[ahb_to_axi4.scala 146:31] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_axi_aw_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28] + assign io_axi_aw_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 158:33] + assign io_axi_aw_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 159:33] + assign io_axi_aw_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 162:33] + assign io_axi_aw_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 160:33] + assign io_axi_aw_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 163:33] + assign io_axi_aw_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_aw_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 161:33] + assign io_axi_aw_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_w_valid = cmdbuf_vld & cmdbuf_write; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 165:28] + assign io_axi_w_bits_data = cmdbuf_wdata; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 166:33] + assign io_axi_w_bits_strb = cmdbuf_wstrb; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 167:33] + assign io_axi_w_bits_last = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 168:33] + assign io_axi_b_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 170:28] + assign io_axi_ar_valid = cmdbuf_vld & _T_38; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28] + assign io_axi_ar_bits_id = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 173:33] + assign io_axi_ar_bits_addr = cmdbuf_addr; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 174:33] + assign io_axi_ar_bits_region = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_len = 8'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 177:33] + assign io_axi_ar_bits_size = {1'h0,cmdbuf_size}; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 175:33] + assign io_axi_ar_bits_burst = 2'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 178:33] + assign io_axi_ar_bits_lock = 1'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_cache = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_ar_bits_prot = 3'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 176:33] + assign io_axi_ar_bits_qos = 4'h0; // @[ahb_to_axi4.scala 20:10] + assign io_axi_r_ready = 1'h1; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 180:28] + assign io_ahb_sig_in_hrdata = buf_rdata; // @[ahb_to_axi4.scala 107:38] + assign io_ahb_sig_in_hready = io_ahb_sig_in_hresp ? _T_75 : _T_85; // @[ahb_to_axi4.scala 104:38] + assign io_ahb_sig_in_hresp = _T_127 | _T_75; // @[ahb_to_axi4.scala 108:38] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_10; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + ahb_haddr_q = _RAND_0[31:0]; + _RAND_1 = {1{`RANDOM}}; + buf_state = _RAND_1[1:0]; + _RAND_2 = {1{`RANDOM}}; + cmdbuf_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + cmdbuf_write = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_hsize_q = _RAND_4[2:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hready_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + buf_read_error = _RAND_7[0:0]; + _RAND_8 = {2{`RANDOM}}; + buf_rdata = _RAND_8[63:0]; + _RAND_9 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_9[1:0]; + _RAND_10 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_10[0:0]; + _RAND_11 = {1{`RANDOM}}; + _T_164 = _RAND_11[2:0]; + _RAND_12 = {1{`RANDOM}}; + cmdbuf_wstrb = _RAND_12[7:0]; + _RAND_13 = {1{`RANDOM}}; + cmdbuf_addr = _RAND_13[31:0]; + _RAND_14 = {2{`RANDOM}}; + cmdbuf_wdata = _RAND_14[63:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + ahb_haddr_q = 32'h0; + end + if (reset) begin + buf_state = 2'h0; + end + if (reset) begin + cmdbuf_vld = 1'h0; + end + if (reset) begin + cmdbuf_write = 1'h0; + end + if (reset) begin + ahb_hsize_q = 3'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + buf_read_error = 1'h0; + end + if (reset) begin + buf_rdata = 64'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + _T_164 = 3'h0; + end + if (reset) begin + cmdbuf_wstrb = 8'h0; + end + if (reset) begin + cmdbuf_addr = 32'h0; + end + if (reset) begin + cmdbuf_wdata = 64'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_haddr_q <= 32'h0; + end else begin + ahb_haddr_q <= io_ahb_sig_out_haddr; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_state <= 2'h0; + end else if (buf_state_en) begin + if (_T_7) begin + if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_12) begin + if (_T_17) begin + buf_state <= 2'h0; + end else if (io_ahb_sig_out_hwrite) begin + buf_state <= 2'h1; + end else begin + buf_state <= 2'h2; + end + end else if (_T_30) begin + if (io_ahb_sig_in_hresp) begin + buf_state <= 2'h0; + end else begin + buf_state <= 2'h3; + end + end else begin + buf_state <= 2'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_vld <= 1'h0; + end else begin + cmdbuf_vld <= _T_157 & _T_158; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_write <= 1'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_write <= ahb_hwrite_q; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hsize_q <= 3'h0; + end else begin + ahb_hsize_q <= io_ahb_sig_out_hsize; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_sig_in_hready & io_ahb_hreadyin; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_sig_in_hresp; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_read_error <= 1'h0; + end else if (_T_7) begin + buf_read_error <= 1'h0; + end else if (_T_12) begin + buf_read_error <= 1'h0; + end else if (_T_30) begin + buf_read_error <= 1'h0; + end else begin + buf_read_error <= _GEN_3; + end + end + always @(posedge buf_rdata_clk or posedge reset) begin + if (reset) begin + buf_rdata <= 64'h0; + end else begin + buf_rdata <= io_axi_r_bits_data; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= _T_89 & io_ahb_sig_out_htrans; + end + end + always @(posedge ahb_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_sig_out_hwrite; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + _T_164 <= 3'h0; + end else if (cmdbuf_wr_en) begin + _T_164 <= ahb_hsize_q; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_wstrb <= 8'h0; + end else if (cmdbuf_wr_en) begin + cmdbuf_wstrb <= master_wstrb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_addr <= 32'h0; + end else begin + cmdbuf_addr <= ahb_haddr_q; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + cmdbuf_wdata <= 64'h0; + end else begin + cmdbuf_wdata <= io_ahb_sig_out_hwdata; + end + end +endmodule diff --git a/axi4_to_ahb.anno.json b/axi4_to_ahb.anno.json new file mode 100644 index 00000000..d41890d1 --- /dev/null +++ b/axi4_to_ahb.anno.json @@ -0,0 +1,113 @@ +[ + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_w_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hprot", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_prot" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_aw_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_haddr", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_addr", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_b_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hsize", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_bits_size", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_hwrite", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_ahb_out_htrans", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_r_valid", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid" + ] + }, + { + "class":"firrtl.transforms.CombinationalPath", + "sink":"~axi4_to_ahb|axi4_to_ahb>io_axi_ar_ready", + "sources":[ + "~axi4_to_ahb|axi4_to_ahb>io_axi_ar_valid", + "~axi4_to_ahb|axi4_to_ahb>io_axi_b_ready", + "~axi4_to_ahb|axi4_to_ahb>io_axi_r_ready" + ] + }, + { + "class":"firrtl.EmitCircuitAnnotation", + "emitter":"firrtl.VerilogEmitter" + }, + { + "class":"firrtl.transforms.BlackBoxResourceAnno", + "target":"axi4_to_ahb.gated_latch", + "resourceId":"/vsrc/gated_latch.v" + }, + { + "class":"firrtl.options.TargetDirAnnotation", + "directory":"." + }, + { + "class":"firrtl.options.OutputAnnotationFileAnnotation", + "file":"axi4_to_ahb" + }, + { + "class":"firrtl.transforms.BlackBoxTargetDirAnno", + "targetDir":"." + } +] \ No newline at end of file diff --git a/axi4_to_ahb.fir b/axi4_to_ahb.fir new file mode 100644 index 00000000..6f56dc26 --- /dev/null +++ b/axi4_to_ahb.fir @@ -0,0 +1,1406 @@ +;buildInfoPackage: chisel3, version: 3.3.1, scalaVersion: 2.12.11, sbtVersion: 1.3.10 +circuit axi4_to_ahb : + extmodule gated_latch : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_1 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_1 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_1 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_2 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_2 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_2 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_3 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_3 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_3 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_4 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_4 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_4 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_5 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_5 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_5 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_6 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_6 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_6 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_7 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_7 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_7 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_8 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_8 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_8 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_9 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_9 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_9 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] + master_size <= _T_22 @[axi4_to_ahb.scala 151:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + inst rvclkhdr of rvclkhdr @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + inst rvclkhdr_1 of rvclkhdr_1 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + inst rvclkhdr_2 of rvclkhdr_2 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + inst rvclkhdr_3 of rvclkhdr_3 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + inst rvclkhdr_4 of rvclkhdr_4 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + inst rvclkhdr_5 of rvclkhdr_5 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + inst rvclkhdr_6 of rvclkhdr_6 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + inst rvclkhdr_7 of rvclkhdr_7 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + inst rvclkhdr_8 of rvclkhdr_8 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + inst rvclkhdr_9 of rvclkhdr_9 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + diff --git a/axi4_to_ahb.v b/axi4_to_ahb.v new file mode 100644 index 00000000..2c3bf777 --- /dev/null +++ b/axi4_to_ahb.v @@ -0,0 +1,1139 @@ +module rvclkhdr( + output io_l1clk, + input io_clk, + input io_en, + input io_scan_mode +); + wire clkhdr_Q; // @[lib.scala 334:26] + wire clkhdr_CK; // @[lib.scala 334:26] + wire clkhdr_EN; // @[lib.scala 334:26] + wire clkhdr_SE; // @[lib.scala 334:26] + gated_latch clkhdr ( // @[lib.scala 334:26] + .Q(clkhdr_Q), + .CK(clkhdr_CK), + .EN(clkhdr_EN), + .SE(clkhdr_SE) + ); + assign io_l1clk = clkhdr_Q; // @[lib.scala 335:14] + assign clkhdr_CK = io_clk; // @[lib.scala 336:18] + assign clkhdr_EN = io_en; // @[lib.scala 337:18] + assign clkhdr_SE = io_scan_mode; // @[lib.scala 338:18] +endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + input io_axi_aw_bits_id, + input [31:0] io_axi_aw_bits_addr, + input [3:0] io_axi_aw_bits_region, + input [7:0] io_axi_aw_bits_len, + input [2:0] io_axi_aw_bits_size, + input [1:0] io_axi_aw_bits_burst, + input io_axi_aw_bits_lock, + input [3:0] io_axi_aw_bits_cache, + input [2:0] io_axi_aw_bits_prot, + input [3:0] io_axi_aw_bits_qos, + output io_axi_w_ready, + input io_axi_w_valid, + input [63:0] io_axi_w_bits_data, + input [7:0] io_axi_w_bits_strb, + input io_axi_w_bits_last, + input io_axi_b_ready, + output io_axi_b_valid, + output [1:0] io_axi_b_bits_resp, + output io_axi_b_bits_id, + output io_axi_ar_ready, + input io_axi_ar_valid, + input io_axi_ar_bits_id, + input [31:0] io_axi_ar_bits_addr, + input [3:0] io_axi_ar_bits_region, + input [7:0] io_axi_ar_bits_len, + input [2:0] io_axi_ar_bits_size, + input [1:0] io_axi_ar_bits_burst, + input io_axi_ar_bits_lock, + input [3:0] io_axi_ar_bits_cache, + input [2:0] io_axi_ar_bits_prot, + input [3:0] io_axi_ar_bits_qos, + input io_axi_r_ready, + output io_axi_r_valid, + output io_axi_r_bits_id, + output [63:0] io_axi_r_bits_data, + output [1:0] io_axi_r_bits_resp, + output io_axi_r_bits_last, + input [63:0] io_ahb_in_hrdata, + input io_ahb_in_hready, + input io_ahb_in_hresp, + output [31:0] io_ahb_out_haddr, + output [2:0] io_ahb_out_hburst, + output io_ahb_out_hmastlock, + output [3:0] io_ahb_out_hprot, + output [2:0] io_ahb_out_hsize, + output [1:0] io_ahb_out_htrans, + output io_ahb_out_hwrite, + output [63:0] io_ahb_out_hwdata +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; + reg [31:0] _RAND_4; + reg [31:0] _RAND_5; + reg [31:0] _RAND_6; + reg [31:0] _RAND_7; + reg [31:0] _RAND_8; + reg [31:0] _RAND_9; + reg [31:0] _RAND_10; + reg [31:0] _RAND_11; + reg [63:0] _RAND_12; + reg [31:0] _RAND_13; + reg [31:0] _RAND_14; + reg [31:0] _RAND_15; + reg [31:0] _RAND_16; + reg [63:0] _RAND_17; + reg [63:0] _RAND_18; + reg [31:0] _RAND_19; + reg [31:0] _RAND_20; + reg [31:0] _RAND_21; + reg [31:0] _RAND_22; + reg [31:0] _RAND_23; + reg [31:0] _RAND_24; + reg [31:0] _RAND_25; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hready_q; // @[axi4_to_ahb.scala 328:52] + reg [1:0] ahb_htrans_q; // @[axi4_to_ahb.scala 329:52] + wire _T_108 = ahb_htrans_q != 2'h0; // @[axi4_to_ahb.scala 190:58] + wire _T_109 = ahb_hready_q & _T_108; // @[axi4_to_ahb.scala 190:36] + wire ahbm_addr_clk = rvclkhdr_8_io_l1clk; // @[axi4_to_ahb.scala 32:27 axi4_to_ahb.scala 341:17] + reg ahb_hwrite_q; // @[axi4_to_ahb.scala 330:57] + wire _T_110 = ~ahb_hwrite_q; // @[axi4_to_ahb.scala 190:72] + wire _T_111 = _T_109 & _T_110; // @[axi4_to_ahb.scala 190:70] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + reg ahb_hresp_q; // @[axi4_to_ahb.scala 331:52] + wire _T_156 = ahb_hready_q | ahb_hresp_q; // @[axi4_to_ahb.scala 204:37] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_189 = ahb_hready_q & ahb_hwrite_q; // @[axi4_to_ahb.scala 236:33] + wire _T_192 = _T_189 & _T_108; // @[axi4_to_ahb.scala 236:48] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_15 = _T_281 & _T_192; // @[Conditional.scala 39:67] + wire _GEN_19 = _T_188 ? _T_192 : _GEN_15; // @[Conditional.scala 39:67] + wire _GEN_40 = _T_186 ? 1'h0 : _GEN_19; // @[Conditional.scala 39:67] + wire _GEN_59 = _T_175 ? 1'h0 : _GEN_40; // @[Conditional.scala 39:67] + wire _GEN_79 = _T_136 ? 1'h0 : _GEN_59; // @[Conditional.scala 39:67] + wire _GEN_95 = _T_101 ? 1'h0 : _GEN_79; // @[Conditional.scala 39:67] + wire trxn_done = _T_49 ? 1'h0 : _GEN_95; // @[Conditional.scala 40:58] + reg cmd_doneQ; // @[axi4_to_ahb.scala 326:52] + wire _T_282 = cmd_doneQ & ahb_hready_q; // @[axi4_to_ahb.scala 246:34] + wire _T_283 = _T_282 | ahb_hresp_q; // @[axi4_to_ahb.scala 246:50] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire slave_ready = io_axi_b_ready & io_axi_r_ready; // @[axi4_to_ahb.scala 164:33] + wire _GEN_1 = _T_440 & slave_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_281 ? _T_283 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? trxn_done : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? _T_156 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? _T_111 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? _T_156 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? _T_111 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] + wire _T_124 = _T_106 == 3'h6; // @[axi4_to_ahb.scala 193:174] + wire _T_125 = _T_111 & _T_124; // @[axi4_to_ahb.scala 193:88] + wire _T_137 = ~ahb_hresp_q; // @[axi4_to_ahb.scala 201:39] + wire _T_138 = ahb_hready_q & _T_137; // @[axi4_to_ahb.scala 201:37] + wire _T_141 = master_valid & _T_51; // @[axi4_to_ahb.scala 201:70] + wire _T_142 = ~_T_141; // @[axi4_to_ahb.scala 201:55] + wire _T_143 = _T_138 & _T_142; // @[axi4_to_ahb.scala 201:53] + wire _T_285 = buf_state_en & _T_137; // @[axi4_to_ahb.scala 247:36] + wire _T_286 = _T_285 & slave_ready; // @[axi4_to_ahb.scala 247:51] + wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? _T_143 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? _T_125 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] + wire [2:0] _T_155 = ahb_hresp_q ? 3'h7 : _T_154; // @[axi4_to_ahb.scala 203:26] + wire _T_287 = ~slave_ready; // @[axi4_to_ahb.scala 248:42] + wire _T_288 = ahb_hresp_q | _T_287; // @[axi4_to_ahb.scala 248:40] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] + wire [2:0] _T_295 = _T_288 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_155 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + reg wrbuf_tag; // @[Reg.scala 27:20] + reg [31:0] wrbuf_addr; // @[lib.scala 374:16] + wire [31:0] master_addr = wr_cmd_vld ? wrbuf_addr : io_axi_ar_bits_addr; // @[axi4_to_ahb.scala 150:21] + reg [2:0] wrbuf_size; // @[Reg.scala 27:20] + wire [2:0] master_size = wr_cmd_vld ? wrbuf_size : io_axi_ar_bits_size; // @[axi4_to_ahb.scala 151:21] + reg [7:0] wrbuf_byteen; // @[Reg.scala 27:20] + reg [63:0] wrbuf_data; // @[lib.scala 374:16] + wire _T_358 = buf_nxtstate != 3'h5; // @[axi4_to_ahb.scala 258:55] + wire _T_359 = buf_state_en & _T_358; // @[axi4_to_ahb.scala 258:39] + wire _GEN_14 = _T_281 ? _T_359 : _T_440; // @[Conditional.scala 39:67] + wire _GEN_33 = _T_188 ? 1'h0 : _GEN_14; // @[Conditional.scala 39:67] + wire _GEN_49 = _T_186 ? 1'h0 : _GEN_33; // @[Conditional.scala 39:67] + wire _GEN_52 = _T_175 ? buf_state_en : _GEN_49; // @[Conditional.scala 39:67] + wire _GEN_73 = _T_136 ? _T_285 : _GEN_52; // @[Conditional.scala 39:67] + wire _GEN_94 = _T_101 ? 1'h0 : _GEN_73; // @[Conditional.scala 39:67] + wire slave_valid_pre = _T_49 ? 1'h0 : _GEN_94; // @[Conditional.scala 40:58] + wire _T_25 = slave_valid_pre & slave_ready; // @[axi4_to_ahb.scala 156:33] + wire buf_clk = rvclkhdr_6_io_l1clk; // @[axi4_to_ahb.scala 125:21 axi4_to_ahb.scala 339:12] + reg slvbuf_write; // @[Reg.scala 27:20] + wire [1:0] _T_596 = slvbuf_write ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 292:23] + reg slvbuf_error; // @[Reg.scala 27:20] + wire [1:0] _T_598 = slvbuf_error ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_599 = _T_598 & 2'h2; // @[axi4_to_ahb.scala 292:88] + wire [3:0] slave_opc = {_T_596,_T_599}; // @[Cat.scala 29:58] + wire [1:0] _T_30 = slave_opc[1] ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 157:55] + reg slvbuf_tag; // @[Reg.scala 27:20] + wire _T_35 = slave_opc[3:2] == 2'h0; // @[axi4_to_ahb.scala 160:66] + reg [31:0] last_bus_addr; // @[Reg.scala 27:20] + wire [63:0] _T_603 = {last_bus_addr,last_bus_addr}; // @[Cat.scala 29:58] + wire _T_604 = buf_state == 3'h5; // @[axi4_to_ahb.scala 293:91] + reg [63:0] buf_data; // @[lib.scala 374:16] + wire ahbm_data_clk = rvclkhdr_9_io_l1clk; // @[axi4_to_ahb.scala 33:27 axi4_to_ahb.scala 342:17] + reg [63:0] ahb_hrdata_q; // @[axi4_to_ahb.scala 332:57] + wire [63:0] _T_607 = _T_604 ? buf_data : ahb_hrdata_q; // @[axi4_to_ahb.scala 293:79] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] + wire [2:0] _T_87 = wrbuf_byteen[6] ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_88 = wrbuf_byteen[5] ? 3'h5 : _T_87; // @[Mux.scala 98:16] + wire [2:0] _T_89 = wrbuf_byteen[4] ? 3'h4 : _T_88; // @[Mux.scala 98:16] + wire [2:0] _T_90 = wrbuf_byteen[3] ? 3'h3 : _T_89; // @[Mux.scala 98:16] + wire [2:0] _T_91 = wrbuf_byteen[2] ? 3'h2 : _T_90; // @[Mux.scala 98:16] + wire [2:0] _T_92 = wrbuf_byteen[1] ? 3'h1 : _T_91; // @[Mux.scala 98:16] + wire [2:0] _T_93 = wrbuf_byteen[0] ? 3'h0 : _T_92; // @[Mux.scala 98:16] + wire [2:0] _T_95 = buf_write_in ? _T_93 : master_addr[2:0]; // @[axi4_to_ahb.scala 182:30] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] + wire _T_126 = master_ready & master_valid; // @[axi4_to_ahb.scala 195:33] + wire _T_162 = buf_nxtstate == 3'h6; // @[axi4_to_ahb.scala 210:64] + wire _T_163 = _T_126 & _T_162; // @[axi4_to_ahb.scala 210:48] + wire _T_164 = _T_163 & buf_state_en; // @[axi4_to_ahb.scala 210:79] + wire _T_349 = buf_state_en & buf_write_in; // @[axi4_to_ahb.scala 256:33] + wire _T_351 = _T_349 & _T_55; // @[axi4_to_ahb.scala 256:48] + wire _GEN_12 = _T_281 & _T_351; // @[Conditional.scala 39:67] + wire _GEN_32 = _T_188 ? 1'h0 : _GEN_12; // @[Conditional.scala 39:67] + wire _GEN_48 = _T_186 ? 1'h0 : _GEN_32; // @[Conditional.scala 39:67] + wire _GEN_65 = _T_175 ? 1'h0 : _GEN_48; // @[Conditional.scala 39:67] + wire _GEN_75 = _T_136 ? _T_164 : _GEN_65; // @[Conditional.scala 39:67] + wire _GEN_88 = _T_101 ? _T_126 : _GEN_75; // @[Conditional.scala 39:67] + wire bypass_en = _T_49 ? buf_state_en : _GEN_88; // @[Conditional.scala 40:58] + wire [1:0] _T_99 = bypass_en ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_100 = _T_99 & 2'h2; // @[axi4_to_ahb.scala 185:49] + wire _T_112 = ~master_valid; // @[axi4_to_ahb.scala 191:34] + wire _T_113 = buf_state_en & _T_112; // @[axi4_to_ahb.scala 191:32] + reg [31:0] buf_addr; // @[lib.scala 374:16] + wire [2:0] _T_130 = bypass_en ? master_addr[2:0] : buf_addr[2:0]; // @[axi4_to_ahb.scala 196:30] + wire _T_131 = ~buf_state_en; // @[axi4_to_ahb.scala 197:48] + wire _T_132 = _T_131 | bypass_en; // @[axi4_to_ahb.scala 197:62] + wire [1:0] _T_134 = _T_132 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_135 = 2'h2 & _T_134; // @[axi4_to_ahb.scala 197:36] + wire _T_169 = buf_nxtstate != 3'h6; // @[axi4_to_ahb.scala 212:63] + wire _T_170 = _T_169 & buf_state_en; // @[axi4_to_ahb.scala 212:78] + wire _T_171 = ~_T_170; // @[axi4_to_ahb.scala 212:47] + wire [1:0] _T_173 = _T_171 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_174 = 2'h2 & _T_173; // @[axi4_to_ahb.scala 212:36] + wire [1:0] _T_184 = _T_131 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_185 = 2'h2 & _T_184; // @[axi4_to_ahb.scala 222:41] + reg [2:0] buf_cmd_byte_ptrQ; // @[Reg.scala 27:20] + reg [7:0] buf_byteen; // @[Reg.scala 27:20] + wire [2:0] _T_197 = buf_cmd_byte_ptrQ + 3'h1; // @[axi4_to_ahb.scala 142:52] + wire _T_200 = 3'h0 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_201 = buf_byteen[0] & _T_200; // @[axi4_to_ahb.scala 143:48] + wire _T_203 = 3'h1 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_204 = buf_byteen[1] & _T_203; // @[axi4_to_ahb.scala 143:48] + wire _T_206 = 3'h2 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_207 = buf_byteen[2] & _T_206; // @[axi4_to_ahb.scala 143:48] + wire _T_209 = 3'h3 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_210 = buf_byteen[3] & _T_209; // @[axi4_to_ahb.scala 143:48] + wire _T_212 = 3'h4 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_213 = buf_byteen[4] & _T_212; // @[axi4_to_ahb.scala 143:48] + wire _T_215 = 3'h5 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_216 = buf_byteen[5] & _T_215; // @[axi4_to_ahb.scala 143:48] + wire _T_218 = 3'h6 >= _T_197; // @[axi4_to_ahb.scala 143:62] + wire _T_219 = buf_byteen[6] & _T_218; // @[axi4_to_ahb.scala 143:48] + wire [2:0] _T_224 = _T_219 ? 3'h6 : 3'h7; // @[Mux.scala 98:16] + wire [2:0] _T_225 = _T_216 ? 3'h5 : _T_224; // @[Mux.scala 98:16] + wire [2:0] _T_226 = _T_213 ? 3'h4 : _T_225; // @[Mux.scala 98:16] + wire [2:0] _T_227 = _T_210 ? 3'h3 : _T_226; // @[Mux.scala 98:16] + wire [2:0] _T_228 = _T_207 ? 3'h2 : _T_227; // @[Mux.scala 98:16] + wire [2:0] _T_229 = _T_204 ? 3'h1 : _T_228; // @[Mux.scala 98:16] + wire [2:0] _T_230 = _T_201 ? 3'h0 : _T_229; // @[Mux.scala 98:16] + wire [2:0] _T_231 = trxn_done ? _T_230 : buf_cmd_byte_ptrQ; // @[axi4_to_ahb.scala 240:30] + wire _T_232 = buf_cmd_byte_ptrQ == 3'h7; // @[axi4_to_ahb.scala 241:65] + reg buf_aligned; // @[Reg.scala 27:20] + wire _T_233 = buf_aligned | _T_232; // @[axi4_to_ahb.scala 241:44] + wire [7:0] _T_271 = buf_byteen >> _T_230; // @[axi4_to_ahb.scala 241:92] + wire _T_273 = ~_T_271[0]; // @[axi4_to_ahb.scala 241:163] + wire _T_274 = _T_233 | _T_273; // @[axi4_to_ahb.scala 241:79] + wire _T_275 = trxn_done & _T_274; // @[axi4_to_ahb.scala 241:29] + wire _T_346 = _T_232 | _T_273; // @[axi4_to_ahb.scala 255:38] + wire _T_347 = _T_109 & _T_346; // @[axi4_to_ahb.scala 254:80] + wire _T_348 = ahb_hresp_q | _T_347; // @[axi4_to_ahb.scala 254:34] + wire _GEN_11 = _T_281 & _T_348; // @[Conditional.scala 39:67] + wire _GEN_24 = _T_188 ? _T_275 : _GEN_11; // @[Conditional.scala 39:67] + wire _GEN_43 = _T_186 ? 1'h0 : _GEN_24; // @[Conditional.scala 39:67] + wire _GEN_61 = _T_175 ? 1'h0 : _GEN_43; // @[Conditional.scala 39:67] + wire _GEN_74 = _T_136 ? _T_113 : _GEN_61; // @[Conditional.scala 39:67] + wire _GEN_84 = _T_101 ? _T_113 : _GEN_74; // @[Conditional.scala 39:67] + wire cmd_done = _T_49 ? 1'h0 : _GEN_84; // @[Conditional.scala 40:58] + wire _T_276 = cmd_done | cmd_doneQ; // @[axi4_to_ahb.scala 242:47] + wire _T_277 = ~_T_276; // @[axi4_to_ahb.scala 242:36] + wire [1:0] _T_279 = _T_277 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_280 = _T_279 & 2'h2; // @[axi4_to_ahb.scala 242:61] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] + wire _T_354 = _T_277 | bypass_en; // @[axi4_to_ahb.scala 257:61] + wire [1:0] _T_356 = _T_354 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_357 = _T_356 & 2'h2; // @[axi4_to_ahb.scala 257:75] + wire _T_364 = trxn_done | bypass_en; // @[axi4_to_ahb.scala 260:40] + wire [2:0] _T_439 = bypass_en ? _T_93 : _T_231; // @[axi4_to_ahb.scala 261:30] + wire _GEN_6 = _T_281 & ahb_hresp_q; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_281 ? buf_state_en : _T_440; // @[Conditional.scala 39:67] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire [1:0] _GEN_13 = _T_281 ? _T_357 : 2'h0; // @[Conditional.scala 39:67] + wire _GEN_16 = _T_281 & _T_364; // @[Conditional.scala 39:67] + wire [2:0] _GEN_17 = _T_281 ? _T_439 : 3'h0; // @[Conditional.scala 39:67] + wire _GEN_21 = _T_188 ? buf_state_en : _GEN_16; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire [2:0] _GEN_23 = _T_188 ? _T_231 : _GEN_17; // @[Conditional.scala 39:67] + wire [1:0] _GEN_25 = _T_188 ? _T_280 : _GEN_13; // @[Conditional.scala 39:67] + wire _GEN_28 = _T_188 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_38 = _T_186 ? buf_state_en : _GEN_28; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_41 = _T_186 ? 1'h0 : _GEN_21; // @[Conditional.scala 39:67] + wire [2:0] _GEN_42 = _T_186 ? 3'h0 : _GEN_23; // @[Conditional.scala 39:67] + wire [1:0] _GEN_44 = _T_186 ? 2'h0 : _GEN_25; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire [2:0] _GEN_54 = _T_175 ? buf_addr[2:0] : _GEN_42; // @[Conditional.scala 39:67] + wire [1:0] _GEN_55 = _T_175 ? _T_185 : _GEN_44; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_58 = _T_175 ? 1'h0 : _GEN_38; // @[Conditional.scala 39:67] + wire _GEN_60 = _T_175 ? 1'h0 : _GEN_41; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_72 = _T_136 ? buf_state_en : _GEN_58; // @[Conditional.scala 39:67] + wire [2:0] _GEN_76 = _T_136 ? _T_130 : _GEN_54; // @[Conditional.scala 39:67] + wire [1:0] _GEN_77 = _T_136 ? _T_174 : _GEN_55; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_80 = _T_136 ? 1'h0 : _GEN_60; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire [2:0] _GEN_89 = _T_101 ? _T_130 : _GEN_76; // @[Conditional.scala 39:67] + wire [1:0] _GEN_90 = _T_101 ? _T_135 : _GEN_77; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire _GEN_93 = _T_101 ? 1'h0 : _GEN_72; // @[Conditional.scala 39:67] + wire _GEN_96 = _T_101 ? 1'h0 : _GEN_80; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire buf_cmd_byte_ptr_en = _T_49 ? buf_state_en : _GEN_96; // @[Conditional.scala 40:58] + wire [2:0] buf_cmd_byte_ptr = _T_49 ? _T_95 : _GEN_89; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire slvbuf_error_en = _T_49 ? 1'h0 : _GEN_93; // @[Conditional.scala 40:58] + wire _T_535 = master_size[1:0] == 2'h0; // @[axi4_to_ahb.scala 278:24] + wire _T_536 = _T_103 | _T_535; // @[axi4_to_ahb.scala 277:48] + wire _T_538 = master_size[1:0] == 2'h1; // @[axi4_to_ahb.scala 278:54] + wire _T_539 = _T_536 | _T_538; // @[axi4_to_ahb.scala 278:33] + wire _T_541 = master_size[1:0] == 2'h2; // @[axi4_to_ahb.scala 278:93] + wire _T_542 = _T_539 | _T_541; // @[axi4_to_ahb.scala 278:72] + wire _T_544 = master_size[1:0] == 2'h3; // @[axi4_to_ahb.scala 279:25] + wire _T_546 = wrbuf_byteen == 8'h3; // @[axi4_to_ahb.scala 279:62] + wire _T_548 = wrbuf_byteen == 8'hc; // @[axi4_to_ahb.scala 279:97] + wire _T_549 = _T_546 | _T_548; // @[axi4_to_ahb.scala 279:74] + wire _T_551 = wrbuf_byteen == 8'h30; // @[axi4_to_ahb.scala 279:132] + wire _T_552 = _T_549 | _T_551; // @[axi4_to_ahb.scala 279:109] + wire _T_554 = wrbuf_byteen == 8'hc0; // @[axi4_to_ahb.scala 279:168] + wire _T_555 = _T_552 | _T_554; // @[axi4_to_ahb.scala 279:145] + wire _T_557 = wrbuf_byteen == 8'hf; // @[axi4_to_ahb.scala 280:28] + wire _T_558 = _T_555 | _T_557; // @[axi4_to_ahb.scala 279:181] + wire _T_560 = wrbuf_byteen == 8'hf0; // @[axi4_to_ahb.scala 280:63] + wire _T_561 = _T_558 | _T_560; // @[axi4_to_ahb.scala 280:40] + wire _T_563 = wrbuf_byteen == 8'hff; // @[axi4_to_ahb.scala 280:99] + wire _T_564 = _T_561 | _T_563; // @[axi4_to_ahb.scala 280:76] + wire _T_565 = _T_544 & _T_564; // @[axi4_to_ahb.scala 279:38] + wire buf_aligned_in = _T_542 | _T_565; // @[axi4_to_ahb.scala 278:106] + wire _T_444 = buf_aligned_in & _T_51; // @[axi4_to_ahb.scala 272:60] + wire [2:0] _T_461 = _T_548 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_462 = 3'h2 & _T_461; // @[axi4_to_ahb.scala 135:15] + wire _T_468 = _T_560 | _T_546; // @[axi4_to_ahb.scala 136:56] + wire [2:0] _T_470 = _T_468 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_471 = 3'h4 & _T_470; // @[axi4_to_ahb.scala 136:15] + wire [2:0] _T_472 = _T_462 | _T_471; // @[axi4_to_ahb.scala 135:63] + wire [2:0] _T_476 = _T_554 ? 3'h7 : 3'h0; // @[Bitwise.scala 72:12] + wire [2:0] _T_477 = 3'h6 & _T_476; // @[axi4_to_ahb.scala 137:15] + wire [2:0] _T_478 = _T_472 | _T_477; // @[axi4_to_ahb.scala 136:96] + wire [2:0] _T_485 = _T_444 ? _T_478 : master_addr[2:0]; // @[axi4_to_ahb.scala 272:43] + wire _T_489 = buf_state == 3'h3; // @[axi4_to_ahb.scala 275:33] + wire _T_495 = buf_aligned_in & _T_544; // @[axi4_to_ahb.scala 276:38] + wire _T_498 = _T_495 & _T_51; // @[axi4_to_ahb.scala 276:71] + wire [1:0] _T_504 = _T_563 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire _T_510 = _T_560 | _T_557; // @[axi4_to_ahb.scala 129:55] + wire [1:0] _T_512 = _T_510 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_513 = 2'h2 & _T_512; // @[axi4_to_ahb.scala 129:16] + wire [1:0] _T_514 = _T_504 | _T_513; // @[axi4_to_ahb.scala 128:64] + wire _T_519 = _T_554 | _T_551; // @[axi4_to_ahb.scala 130:60] + wire _T_522 = _T_519 | _T_548; // @[axi4_to_ahb.scala 130:89] + wire _T_525 = _T_522 | _T_546; // @[axi4_to_ahb.scala 130:123] + wire [1:0] _T_527 = _T_525 ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [1:0] _T_528 = 2'h1 & _T_527; // @[axi4_to_ahb.scala 130:21] + wire [1:0] _T_529 = _T_514 | _T_528; // @[axi4_to_ahb.scala 129:93] + wire [1:0] _T_531 = _T_498 ? _T_529 : master_size[1:0]; // @[axi4_to_ahb.scala 276:21] + wire [31:0] _T_570 = {master_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [31:0] _T_573 = {buf_addr[31:3],buf_cmd_byte_ptr}; // @[Cat.scala 29:58] + wire [1:0] _T_577 = buf_aligned_in ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + wire [2:0] buf_size_in = {{1'd0}, _T_531}; // @[axi4_to_ahb.scala 276:15] + wire [1:0] _T_579 = _T_577 & buf_size_in[1:0]; // @[axi4_to_ahb.scala 283:81] + wire [2:0] _T_580 = {1'h0,_T_579}; // @[Cat.scala 29:58] + wire [1:0] _T_582 = buf_aligned ? 2'h3 : 2'h0; // @[Bitwise.scala 72:12] + reg [1:0] buf_size; // @[Reg.scala 27:20] + wire [1:0] _T_584 = _T_582 & buf_size; // @[axi4_to_ahb.scala 283:138] + wire [2:0] _T_585 = {1'h0,_T_584}; // @[Cat.scala 29:58] + wire _T_588 = ~io_axi_ar_bits_prot[2]; // @[axi4_to_ahb.scala 287:37] + wire [1:0] _T_589 = {1'h1,_T_588}; // @[Cat.scala 29:58] + reg buf_write; // @[Reg.scala 27:20] + wire _T_611 = io_ahb_out_htrans != 2'h0; // @[axi4_to_ahb.scala 296:44] + wire _T_612 = _T_611 & io_ahb_in_hready; // @[axi4_to_ahb.scala 296:56] + wire last_addr_en = _T_612 & io_ahb_out_hwrite; // @[axi4_to_ahb.scala 296:75] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] + wire _T_633 = ~wr_cmd_vld; // @[axi4_to_ahb.scala 305:22] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] + reg buf_tag; // @[Reg.scala 27:20] + wire _T_691 = ~slave_valid_pre; // @[axi4_to_ahb.scala 326:92] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] + wire _T_708 = io_ahb_in_hready & io_ahb_out_htrans[1]; // @[axi4_to_ahb.scala 335:57] + wire _T_709 = _T_708 | io_clk_override; // @[axi4_to_ahb.scala 335:81] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] + assign io_axi_b_valid = _T_25 & slave_opc[3]; // @[axi4_to_ahb.scala 156:18] + assign io_axi_b_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 157:22] + assign io_axi_b_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 158:20] + assign io_axi_ar_ready = _T_633 & master_ready; // @[axi4_to_ahb.scala 305:19] + assign io_axi_r_valid = _T_25 & _T_35; // @[axi4_to_ahb.scala 160:18] + assign io_axi_r_bits_id = slvbuf_tag; // @[axi4_to_ahb.scala 162:20] + assign io_axi_r_bits_data = slvbuf_error ? _T_603 : _T_607; // @[axi4_to_ahb.scala 163:22] + assign io_axi_r_bits_resp = slave_opc[0] ? 2'h2 : _T_30; // @[axi4_to_ahb.scala 161:22] + assign io_axi_r_bits_last = 1'h1; // @[axi4_to_ahb.scala 306:22] + assign io_ahb_out_haddr = bypass_en ? _T_570 : _T_573; // @[axi4_to_ahb.scala 282:20] + assign io_ahb_out_hburst = 3'h0; // @[axi4_to_ahb.scala 285:21] + assign io_ahb_out_hmastlock = 1'h0; // @[axi4_to_ahb.scala 286:24] + assign io_ahb_out_hprot = {{2'd0}, _T_589}; // @[axi4_to_ahb.scala 287:20] + assign io_ahb_out_hsize = bypass_en ? _T_580 : _T_585; // @[axi4_to_ahb.scala 283:20] + assign io_ahb_out_htrans = _T_49 ? _T_100 : _GEN_90; // @[axi4_to_ahb.scala 29:21 axi4_to_ahb.scala 185:25 axi4_to_ahb.scala 197:25 axi4_to_ahb.scala 212:25 axi4_to_ahb.scala 222:25 axi4_to_ahb.scala 242:25 axi4_to_ahb.scala 257:25] + assign io_ahb_out_hwrite = bypass_en ? _T_51 : buf_write; // @[axi4_to_ahb.scala 288:21] + assign io_ahb_out_hwdata = buf_data; // @[axi4_to_ahb.scala 289:21] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & _T_709; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + ahb_hready_q = _RAND_3[0:0]; + _RAND_4 = {1{`RANDOM}}; + ahb_htrans_q = _RAND_4[1:0]; + _RAND_5 = {1{`RANDOM}}; + ahb_hwrite_q = _RAND_5[0:0]; + _RAND_6 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_6[0:0]; + _RAND_7 = {1{`RANDOM}}; + cmd_doneQ = _RAND_7[0:0]; + _RAND_8 = {1{`RANDOM}}; + wrbuf_tag = _RAND_8[0:0]; + _RAND_9 = {1{`RANDOM}}; + wrbuf_addr = _RAND_9[31:0]; + _RAND_10 = {1{`RANDOM}}; + wrbuf_size = _RAND_10[2:0]; + _RAND_11 = {1{`RANDOM}}; + wrbuf_byteen = _RAND_11[7:0]; + _RAND_12 = {2{`RANDOM}}; + wrbuf_data = _RAND_12[63:0]; + _RAND_13 = {1{`RANDOM}}; + slvbuf_write = _RAND_13[0:0]; + _RAND_14 = {1{`RANDOM}}; + slvbuf_error = _RAND_14[0:0]; + _RAND_15 = {1{`RANDOM}}; + slvbuf_tag = _RAND_15[0:0]; + _RAND_16 = {1{`RANDOM}}; + last_bus_addr = _RAND_16[31:0]; + _RAND_17 = {2{`RANDOM}}; + buf_data = _RAND_17[63:0]; + _RAND_18 = {2{`RANDOM}}; + ahb_hrdata_q = _RAND_18[63:0]; + _RAND_19 = {1{`RANDOM}}; + buf_addr = _RAND_19[31:0]; + _RAND_20 = {1{`RANDOM}}; + buf_cmd_byte_ptrQ = _RAND_20[2:0]; + _RAND_21 = {1{`RANDOM}}; + buf_byteen = _RAND_21[7:0]; + _RAND_22 = {1{`RANDOM}}; + buf_aligned = _RAND_22[0:0]; + _RAND_23 = {1{`RANDOM}}; + buf_size = _RAND_23[1:0]; + _RAND_24 = {1{`RANDOM}}; + buf_write = _RAND_24[0:0]; + _RAND_25 = {1{`RANDOM}}; + buf_tag = _RAND_25[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + if (reset) begin + ahb_hready_q = 1'h0; + end + if (reset) begin + ahb_htrans_q = 2'h0; + end + if (reset) begin + ahb_hwrite_q = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + cmd_doneQ = 1'h0; + end + if (reset) begin + wrbuf_tag = 1'h0; + end + if (reset) begin + wrbuf_addr = 32'h0; + end + if (reset) begin + wrbuf_size = 3'h0; + end + if (reset) begin + wrbuf_byteen = 8'h0; + end + if (reset) begin + wrbuf_data = 64'h0; + end + if (reset) begin + slvbuf_write = 1'h0; + end + if (reset) begin + slvbuf_error = 1'h0; + end + if (reset) begin + slvbuf_tag = 1'h0; + end + if (reset) begin + last_bus_addr = 32'h0; + end + if (reset) begin + buf_data = 64'h0; + end + if (reset) begin + ahb_hrdata_q = 64'h0; + end + if (reset) begin + buf_addr = 32'h0; + end + if (reset) begin + buf_cmd_byte_ptrQ = 3'h0; + end + if (reset) begin + buf_byteen = 8'h0; + end + if (reset) begin + buf_aligned = 1'h0; + end + if (reset) begin + buf_size = 2'h0; + end + if (reset) begin + buf_write = 1'h0; + end + if (reset) begin + buf_tag = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (ahb_hresp_q) begin + buf_state <= 3'h7; + end else if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (_T_288) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hready_q <= 1'h0; + end else begin + ahb_hready_q <= io_ahb_in_hready; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_htrans_q <= 2'h0; + end else begin + ahb_htrans_q <= io_ahb_out_htrans; + end + end + always @(posedge ahbm_addr_clk or posedge reset) begin + if (reset) begin + ahb_hwrite_q <= 1'h0; + end else begin + ahb_hwrite_q <= io_ahb_out_hwrite; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_in_hresp; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + cmd_doneQ <= 1'h0; + end else begin + cmd_doneQ <= _T_276 & _T_691; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_tag <= 1'h0; + end else if (wrbuf_en) begin + wrbuf_tag <= io_axi_aw_bits_id; + end + end + always @(posedge rvclkhdr_2_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_addr <= 32'h0; + end else begin + wrbuf_addr <= io_axi_aw_bits_addr; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_size <= 3'h0; + end else if (wrbuf_en) begin + wrbuf_size <= io_axi_aw_bits_size; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_byteen <= 8'h0; + end else if (wrbuf_data_en) begin + wrbuf_byteen <= io_axi_w_bits_strb; + end + end + always @(posedge rvclkhdr_3_io_l1clk or posedge reset) begin + if (reset) begin + wrbuf_data <= 64'h0; + end else begin + wrbuf_data <= io_axi_w_bits_data; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_write <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_write <= buf_write; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + slvbuf_error <= 1'h0; + end else if (slvbuf_error_en) begin + if (_T_49) begin + slvbuf_error <= 1'h0; + end else if (_T_101) begin + slvbuf_error <= 1'h0; + end else if (_T_136) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_175) begin + slvbuf_error <= 1'h0; + end else if (_T_186) begin + slvbuf_error <= ahb_hresp_q; + end else if (_T_188) begin + slvbuf_error <= 1'h0; + end else begin + slvbuf_error <= _GEN_6; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + slvbuf_tag <= 1'h0; + end else if (slvbuf_wr_en) begin + slvbuf_tag <= buf_tag; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + last_bus_addr <= 32'h0; + end else if (last_addr_en) begin + last_bus_addr <= io_ahb_out_haddr; + end + end + always @(posedge rvclkhdr_5_io_l1clk or posedge reset) begin + if (reset) begin + buf_data <= 64'h0; + end else if (_T_489) begin + buf_data <= ahb_hrdata_q; + end else begin + buf_data <= wrbuf_data; + end + end + always @(posedge ahbm_data_clk or posedge reset) begin + if (reset) begin + ahb_hrdata_q <= 64'h0; + end else begin + ahb_hrdata_q <= io_ahb_in_hrdata; + end + end + always @(posedge rvclkhdr_4_io_l1clk or posedge reset) begin + if (reset) begin + buf_addr <= 32'h0; + end else begin + buf_addr <= {master_addr[31:3],_T_485}; + end + end + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (buf_cmd_byte_ptr_en) begin + if (_T_49) begin + if (buf_write_in) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end + end else if (_T_101) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_136) begin + if (bypass_en) begin + buf_cmd_byte_ptrQ <= master_addr[2:0]; + end else begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end + end else if (_T_175) begin + buf_cmd_byte_ptrQ <= buf_addr[2:0]; + end else if (_T_186) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_188) begin + if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else if (_T_281) begin + if (bypass_en) begin + if (wrbuf_byteen[0]) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (wrbuf_byteen[1]) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (wrbuf_byteen[2]) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (wrbuf_byteen[3]) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (wrbuf_byteen[4]) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (wrbuf_byteen[5]) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (wrbuf_byteen[6]) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end else if (trxn_done) begin + if (_T_201) begin + buf_cmd_byte_ptrQ <= 3'h0; + end else if (_T_204) begin + buf_cmd_byte_ptrQ <= 3'h1; + end else if (_T_207) begin + buf_cmd_byte_ptrQ <= 3'h2; + end else if (_T_210) begin + buf_cmd_byte_ptrQ <= 3'h3; + end else if (_T_213) begin + buf_cmd_byte_ptrQ <= 3'h4; + end else if (_T_216) begin + buf_cmd_byte_ptrQ <= 3'h5; + end else if (_T_219) begin + buf_cmd_byte_ptrQ <= 3'h6; + end else begin + buf_cmd_byte_ptrQ <= 3'h7; + end + end + end else begin + buf_cmd_byte_ptrQ <= 3'h0; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_byteen <= 8'h0; + end else if (buf_wr_en) begin + buf_byteen <= wrbuf_byteen; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_aligned <= 1'h0; + end else if (buf_wr_en) begin + buf_aligned <= buf_aligned_in; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_size <= 2'h0; + end else if (buf_wr_en) begin + buf_size <= buf_size_in[1:0]; + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_write <= 1'h0; + end else if (buf_wr_en) begin + if (_T_49) begin + buf_write <= _T_51; + end else if (_T_101) begin + buf_write <= 1'h0; + end else if (_T_136) begin + buf_write <= 1'h0; + end else if (_T_175) begin + buf_write <= 1'h0; + end else if (_T_186) begin + buf_write <= 1'h0; + end else if (_T_188) begin + buf_write <= 1'h0; + end else begin + buf_write <= _GEN_8; + end + end + end + always @(posedge buf_clk or posedge reset) begin + if (reset) begin + buf_tag <= 1'h0; + end else if (buf_wr_en) begin + if (wr_cmd_vld) begin + buf_tag <= wrbuf_tag; + end else begin + buf_tag <= io_axi_ar_bits_id; + end + end + end +endmodule diff --git a/design/build.sbt b/build.sbt similarity index 100% rename from design/build.sbt rename to build.sbt diff --git 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b/project/target/streams/compile/copyResources/_global/streams/out similarity index 100% rename from design/project/target/streams/compile/copyResources/_global/streams/out rename to project/target/streams/compile/copyResources/_global/streams/out diff --git a/design/project/target/streams/compile/dependencyClasspath/_global/streams/export b/project/target/streams/compile/dependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/dependencyClasspath/_global/streams/export rename to project/target/streams/compile/dependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/compile/exportedProducts/_global/streams/export b/project/target/streams/compile/exportedProducts/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/exportedProducts/_global/streams/export rename to project/target/streams/compile/exportedProducts/_global/streams/export diff --git a/design/project/target/streams/compile/externalDependencyClasspath/_global/streams/export b/project/target/streams/compile/externalDependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/externalDependencyClasspath/_global/streams/export rename to project/target/streams/compile/externalDependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/compile/incOptions/_global/streams/out b/project/target/streams/compile/incOptions/_global/streams/out similarity index 100% rename from design/project/target/streams/compile/incOptions/_global/streams/out rename to project/target/streams/compile/incOptions/_global/streams/out diff --git a/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/export b/project/target/streams/compile/internalDependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/internalDependencyClasspath/_global/streams/export rename to project/target/streams/compile/internalDependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/compile/internalDependencyClasspath/_global/streams/out b/project/target/streams/compile/internalDependencyClasspath/_global/streams/out similarity index 100% rename from design/project/target/streams/compile/internalDependencyClasspath/_global/streams/out rename to project/target/streams/compile/internalDependencyClasspath/_global/streams/out diff --git a/design/project/target/streams/compile/managedClasspath/_global/streams/export b/project/target/streams/compile/managedClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/managedClasspath/_global/streams/export rename to project/target/streams/compile/managedClasspath/_global/streams/export diff --git a/design/project/target/streams/compile/scalacOptions/_global/streams/out b/project/target/streams/compile/scalacOptions/_global/streams/out similarity index 100% rename from design/project/target/streams/compile/scalacOptions/_global/streams/out rename to project/target/streams/compile/scalacOptions/_global/streams/out diff --git a/design/project/target/streams/compile/unmanagedClasspath/_global/streams/export b/project/target/streams/compile/unmanagedClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/unmanagedClasspath/_global/streams/export rename to project/target/streams/compile/unmanagedClasspath/_global/streams/export diff --git a/design/project/target/streams/compile/unmanagedClasspath/_global/streams/out b/project/target/streams/compile/unmanagedClasspath/_global/streams/out similarity index 100% rename from design/project/target/streams/compile/unmanagedClasspath/_global/streams/out rename to project/target/streams/compile/unmanagedClasspath/_global/streams/out diff --git a/design/project/target/streams/compile/unmanagedJars/_global/streams/export b/project/target/streams/compile/unmanagedJars/_global/streams/export similarity index 100% rename from design/project/target/streams/compile/unmanagedJars/_global/streams/export rename to project/target/streams/compile/unmanagedJars/_global/streams/export diff --git a/design/project/target/streams/runtime/dependencyClasspath/_global/streams/export b/project/target/streams/runtime/dependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/dependencyClasspath/_global/streams/export rename to project/target/streams/runtime/dependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/exportedProducts/_global/streams/export b/project/target/streams/runtime/exportedProducts/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/exportedProducts/_global/streams/export rename to project/target/streams/runtime/exportedProducts/_global/streams/export diff --git a/design/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/externalDependencyClasspath/_global/streams/export rename to project/target/streams/runtime/externalDependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/fullClasspath/_global/streams/export b/project/target/streams/runtime/fullClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/fullClasspath/_global/streams/export rename to project/target/streams/runtime/fullClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/export rename to project/target/streams/runtime/internalDependencyClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out b/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out similarity index 100% rename from design/project/target/streams/runtime/internalDependencyClasspath/_global/streams/out rename to project/target/streams/runtime/internalDependencyClasspath/_global/streams/out diff --git a/design/project/target/streams/runtime/managedClasspath/_global/streams/export b/project/target/streams/runtime/managedClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/managedClasspath/_global/streams/export rename to project/target/streams/runtime/managedClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/export b/project/target/streams/runtime/unmanagedClasspath/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/unmanagedClasspath/_global/streams/export rename to project/target/streams/runtime/unmanagedClasspath/_global/streams/export diff --git a/design/project/target/streams/runtime/unmanagedClasspath/_global/streams/out b/project/target/streams/runtime/unmanagedClasspath/_global/streams/out similarity index 100% rename from design/project/target/streams/runtime/unmanagedClasspath/_global/streams/out rename to project/target/streams/runtime/unmanagedClasspath/_global/streams/out diff --git a/design/project/target/streams/runtime/unmanagedJars/_global/streams/export b/project/target/streams/runtime/unmanagedJars/_global/streams/export similarity index 100% rename from design/project/target/streams/runtime/unmanagedJars/_global/streams/export rename to project/target/streams/runtime/unmanagedJars/_global/streams/export diff --git a/design/quasar_wrapper.anno.json b/quasar_wrapper.anno.json similarity index 100% rename from design/quasar_wrapper.anno.json rename to quasar_wrapper.anno.json diff --git a/design/quasar_wrapper.fir b/quasar_wrapper.fir similarity index 95% rename from design/quasar_wrapper.fir rename to quasar_wrapper.fir index 4a37af3c..e44fa672 100644 --- a/design/quasar_wrapper.fir +++ b/quasar_wrapper.fir @@ -109058,10 +109058,4835 @@ circuit quasar_wrapper : clkhdr.EN <= io.en @[lib.scala 337:18] clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + extmodule gated_latch_849 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_849 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_849 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_850 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_850 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_850 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_851 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_851 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_851 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_852 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_852 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_852 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_853 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_853 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_853 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_854 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_854 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_854 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_855 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_855 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_855 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_856 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_856 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_856 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_857 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_857 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_857 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_858 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_858 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_858 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] + master_size <= _T_22 @[axi4_to_ahb.scala 151:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + inst rvclkhdr of rvclkhdr_849 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + inst rvclkhdr_1 of rvclkhdr_850 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + inst rvclkhdr_2 of rvclkhdr_851 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + inst rvclkhdr_3 of rvclkhdr_852 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + inst rvclkhdr_4 of rvclkhdr_853 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + inst rvclkhdr_5 of rvclkhdr_854 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + inst rvclkhdr_6 of rvclkhdr_855 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + inst rvclkhdr_7 of rvclkhdr_856 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + inst rvclkhdr_8 of rvclkhdr_857 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + inst rvclkhdr_9 of rvclkhdr_858 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + + extmodule gated_latch_859 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_859 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_859 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_860 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_860 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_860 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_861 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_861 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_861 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_862 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_862 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_862 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_863 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_863 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_863 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_864 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_864 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_864 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_865 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_865 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_865 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_866 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_866 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_866 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_867 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_867 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_867 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_868 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_868 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_868 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb_1 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] + master_size <= _T_22 @[axi4_to_ahb.scala 151:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + inst rvclkhdr of rvclkhdr_859 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + inst rvclkhdr_1 of rvclkhdr_860 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + inst rvclkhdr_2 of rvclkhdr_861 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + inst rvclkhdr_3 of rvclkhdr_862 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + inst rvclkhdr_4 of rvclkhdr_863 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + inst rvclkhdr_5 of rvclkhdr_864 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + inst rvclkhdr_6 of rvclkhdr_865 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + inst rvclkhdr_7 of rvclkhdr_866 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + inst rvclkhdr_8 of rvclkhdr_867 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + inst rvclkhdr_9 of rvclkhdr_868 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + + extmodule gated_latch_869 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_869 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_869 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_870 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_870 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_870 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_871 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_871 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_871 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_872 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_872 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_872 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_873 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_873 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_873 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_874 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_874 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_874 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_875 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_875 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_875 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_876 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_876 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_876 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_877 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_877 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_877 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_878 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_878 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_878 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module axi4_to_ahb_2 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, flip axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}} + + wire buf_rst : UInt<1> + buf_rst <= UInt<1>("h00") + buf_rst <= UInt<1>("h00") @[axi4_to_ahb.scala 28:11] + io.ahb.out.htrans <= UInt<1>("h00") @[axi4_to_ahb.scala 29:21] + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire ahbm_clk : Clock @[axi4_to_ahb.scala 31:22] + wire ahbm_addr_clk : Clock @[axi4_to_ahb.scala 32:27] + wire ahbm_data_clk : Clock @[axi4_to_ahb.scala 33:27] + wire buf_state : UInt<3> + buf_state <= UInt<3>("h00") + wire buf_nxtstate : UInt<3> + buf_nxtstate <= UInt<3>("h00") + node _T = bits(buf_state_en, 0, 0) @[axi4_to_ahb.scala 37:70] + node _T_1 = mux(_T, buf_nxtstate, buf_state) @[axi4_to_ahb.scala 37:50] + node _T_2 = eq(buf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 37:108] + node _T_3 = bits(_T_2, 0, 0) @[Bitwise.scala 72:15] + node _T_4 = mux(_T_3, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_5 = and(_T_1, _T_4) @[axi4_to_ahb.scala 37:98] + reg _T_6 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 37:45] + _T_6 <= _T_5 @[axi4_to_ahb.scala 37:45] + buf_state <= _T_6 @[axi4_to_ahb.scala 37:13] + wire slave_valid : UInt<1> + slave_valid <= UInt<1>("h00") + wire slave_ready : UInt<1> + slave_ready <= UInt<1>("h00") + wire slave_tag : UInt<1> + slave_tag <= UInt<1>("h00") + wire slave_rdata : UInt<64> + slave_rdata <= UInt<64>("h00") + wire slave_opc : UInt<4> + slave_opc <= UInt<4>("h00") + wire wrbuf_en : UInt<1> + wrbuf_en <= UInt<1>("h00") + wire wrbuf_data_en : UInt<1> + wrbuf_data_en <= UInt<1>("h00") + wire wrbuf_cmd_sent : UInt<1> + wrbuf_cmd_sent <= UInt<1>("h00") + wire wrbuf_rst : UInt<1> + wrbuf_rst <= UInt<1>("h00") + wire wrbuf_vld : UInt<1> + wrbuf_vld <= UInt<1>("h00") + wire wrbuf_data_vld : UInt<1> + wrbuf_data_vld <= UInt<1>("h00") + wire wrbuf_tag : UInt<1> + wrbuf_tag <= UInt<1>("h00") + wire wrbuf_size : UInt<3> + wrbuf_size <= UInt<3>("h00") + wire wrbuf_addr : UInt<32> + wrbuf_addr <= UInt<32>("h00") + wire wrbuf_data : UInt<64> + wrbuf_data <= UInt<64>("h00") + wire wrbuf_byteen : UInt<8> + wrbuf_byteen <= UInt<8>("h00") + wire bus_write_clk_en : UInt<1> + bus_write_clk_en <= UInt<1>("h00") + wire bus_clk : Clock @[axi4_to_ahb.scala 57:21] + wire bus_write_clk : Clock @[axi4_to_ahb.scala 58:27] + wire master_valid : UInt<1> + master_valid <= UInt<1>("h00") + wire master_ready : UInt<1> + master_ready <= UInt<1>("h00") + wire master_tag : UInt<1> + master_tag <= UInt<1>("h00") + wire master_addr : UInt<32> + master_addr <= UInt<32>("h00") + wire master_wdata : UInt<64> + master_wdata <= UInt<64>("h00") + wire master_size : UInt<3> + master_size <= UInt<3>("h00") + wire master_opc : UInt<3> + master_opc <= UInt<3>("h00") + wire master_byteen : UInt<8> + master_byteen <= UInt<8>("h00") + wire buf_addr : UInt<32> + buf_addr <= UInt<32>("h00") + wire buf_size : UInt<2> + buf_size <= UInt<2>("h00") + wire buf_write : UInt<1> + buf_write <= UInt<1>("h00") + wire buf_byteen : UInt<8> + buf_byteen <= UInt<8>("h00") + wire buf_aligned : UInt<1> + buf_aligned <= UInt<1>("h00") + wire buf_data : UInt<64> + buf_data <= UInt<64>("h00") + wire buf_tag : UInt<1> + buf_tag <= UInt<1>("h00") + wire buf_tag_in : UInt<1> + buf_tag_in <= UInt<1>("h00") + wire buf_addr_in : UInt<32> + buf_addr_in <= UInt<32>("h00") + wire buf_byteen_in : UInt<8> + buf_byteen_in <= UInt<8>("h00") + wire buf_data_in : UInt<64> + buf_data_in <= UInt<64>("h00") + wire buf_write_in : UInt<1> + buf_write_in <= UInt<1>("h00") + wire buf_aligned_in : UInt<1> + buf_aligned_in <= UInt<1>("h00") + wire buf_size_in : UInt<3> + buf_size_in <= UInt<3>("h00") + wire buf_wr_en : UInt<1> + buf_wr_en <= UInt<1>("h00") + wire buf_data_wr_en : UInt<1> + buf_data_wr_en <= UInt<1>("h00") + wire slvbuf_error_en : UInt<1> + slvbuf_error_en <= UInt<1>("h00") + wire wr_cmd_vld : UInt<1> + wr_cmd_vld <= UInt<1>("h00") + wire cmd_done_rst : UInt<1> + cmd_done_rst <= UInt<1>("h00") + wire cmd_done : UInt<1> + cmd_done <= UInt<1>("h00") + wire cmd_doneQ : UInt<1> + cmd_doneQ <= UInt<1>("h00") + wire trxn_done : UInt<1> + trxn_done <= UInt<1>("h00") + wire buf_cmd_byte_ptr : UInt<3> + buf_cmd_byte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptrQ : UInt<3> + buf_cmd_byte_ptrQ <= UInt<3>("h00") + wire buf_cmd_nxtbyte_ptr : UInt<3> + buf_cmd_nxtbyte_ptr <= UInt<3>("h00") + wire buf_cmd_byte_ptr_en : UInt<1> + buf_cmd_byte_ptr_en <= UInt<1>("h00") + wire found : UInt<1> + found <= UInt<1>("h00") + wire slave_valid_pre : UInt<1> + slave_valid_pre <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_hrdata_q : UInt<64> + ahb_hrdata_q <= UInt<64>("h00") + wire slvbuf_write : UInt<1> + slvbuf_write <= UInt<1>("h00") + wire slvbuf_error : UInt<1> + slvbuf_error <= UInt<1>("h00") + wire slvbuf_tag : UInt<1> + slvbuf_tag <= UInt<1>("h00") + wire slvbuf_error_in : UInt<1> + slvbuf_error_in <= UInt<1>("h00") + wire slvbuf_wr_en : UInt<1> + slvbuf_wr_en <= UInt<1>("h00") + wire bypass_en : UInt<1> + bypass_en <= UInt<1>("h00") + wire rd_bypass_idle : UInt<1> + rd_bypass_idle <= UInt<1>("h00") + wire last_addr_en : UInt<1> + last_addr_en <= UInt<1>("h00") + wire last_bus_addr : UInt<32> + last_bus_addr <= UInt<32>("h00") + wire buf_clken : UInt<1> + buf_clken <= UInt<1>("h00") + wire slvbuf_clken : UInt<1> + slvbuf_clken <= UInt<1>("h00") + wire ahbm_addr_clken : UInt<1> + ahbm_addr_clken <= UInt<1>("h00") + wire ahbm_data_clken : UInt<1> + ahbm_data_clken <= UInt<1>("h00") + wire buf_clk : Clock @[axi4_to_ahb.scala 125:21] + node _T_7 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 146:27] + wr_cmd_vld <= _T_7 @[axi4_to_ahb.scala 146:14] + node _T_8 = or(wr_cmd_vld, io.axi.ar.valid) @[axi4_to_ahb.scala 147:30] + master_valid <= _T_8 @[axi4_to_ahb.scala 147:16] + node _T_9 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 148:38] + node _T_10 = bits(wrbuf_tag, 0, 0) @[axi4_to_ahb.scala 148:51] + node _T_11 = bits(io.axi.ar.bits.id, 0, 0) @[axi4_to_ahb.scala 148:82] + node _T_12 = mux(_T_9, _T_10, _T_11) @[axi4_to_ahb.scala 148:20] + master_tag <= _T_12 @[axi4_to_ahb.scala 148:14] + node _T_13 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 149:38] + node _T_14 = mux(_T_13, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 149:20] + master_opc <= _T_14 @[axi4_to_ahb.scala 149:14] + node _T_15 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 150:39] + node _T_16 = bits(wrbuf_addr, 31, 0) @[axi4_to_ahb.scala 150:53] + node _T_17 = bits(io.axi.ar.bits.addr, 31, 0) @[axi4_to_ahb.scala 150:81] + node _T_18 = mux(_T_15, _T_16, _T_17) @[axi4_to_ahb.scala 150:21] + master_addr <= _T_18 @[axi4_to_ahb.scala 150:15] + node _T_19 = bits(wr_cmd_vld, 0, 0) @[axi4_to_ahb.scala 151:39] + node _T_20 = bits(wrbuf_size, 2, 0) @[axi4_to_ahb.scala 151:53] + node _T_21 = bits(io.axi.ar.bits.size, 2, 0) @[axi4_to_ahb.scala 151:80] + node _T_22 = mux(_T_19, _T_20, _T_21) @[axi4_to_ahb.scala 151:21] + master_size <= _T_22 @[axi4_to_ahb.scala 151:15] + node _T_23 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 152:32] + master_byteen <= _T_23 @[axi4_to_ahb.scala 152:17] + node _T_24 = bits(wrbuf_data, 63, 0) @[axi4_to_ahb.scala 153:29] + master_wdata <= _T_24 @[axi4_to_ahb.scala 153:16] + node _T_25 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 156:33] + node _T_26 = bits(slave_opc, 3, 3) @[axi4_to_ahb.scala 156:58] + node _T_27 = and(_T_25, _T_26) @[axi4_to_ahb.scala 156:47] + io.axi.b.valid <= _T_27 @[axi4_to_ahb.scala 156:18] + node _T_28 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 157:38] + node _T_29 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 157:65] + node _T_30 = mux(_T_29, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 157:55] + node _T_31 = mux(_T_28, UInt<2>("h02"), _T_30) @[axi4_to_ahb.scala 157:28] + io.axi.b.bits.resp <= _T_31 @[axi4_to_ahb.scala 157:22] + node _T_32 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 158:32] + io.axi.b.bits.id <= _T_32 @[axi4_to_ahb.scala 158:20] + node _T_33 = and(slave_valid, slave_ready) @[axi4_to_ahb.scala 160:33] + node _T_34 = bits(slave_opc, 3, 2) @[axi4_to_ahb.scala 160:59] + node _T_35 = eq(_T_34, UInt<1>("h00")) @[axi4_to_ahb.scala 160:66] + node _T_36 = and(_T_33, _T_35) @[axi4_to_ahb.scala 160:47] + io.axi.r.valid <= _T_36 @[axi4_to_ahb.scala 160:18] + node _T_37 = bits(slave_opc, 0, 0) @[axi4_to_ahb.scala 161:38] + node _T_38 = bits(slave_opc, 1, 1) @[axi4_to_ahb.scala 161:65] + node _T_39 = mux(_T_38, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 161:55] + node _T_40 = mux(_T_37, UInt<2>("h02"), _T_39) @[axi4_to_ahb.scala 161:28] + io.axi.r.bits.resp <= _T_40 @[axi4_to_ahb.scala 161:22] + node _T_41 = bits(slave_tag, 0, 0) @[axi4_to_ahb.scala 162:32] + io.axi.r.bits.id <= _T_41 @[axi4_to_ahb.scala 162:20] + node _T_42 = bits(slave_rdata, 63, 0) @[axi4_to_ahb.scala 163:36] + io.axi.r.bits.data <= _T_42 @[axi4_to_ahb.scala 163:22] + node _T_43 = and(io.axi.b.ready, io.axi.r.ready) @[axi4_to_ahb.scala 164:33] + slave_ready <= _T_43 @[axi4_to_ahb.scala 164:15] + node _T_44 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 167:57] + node _T_45 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 167:94] + node _T_46 = or(_T_44, _T_45) @[axi4_to_ahb.scala 167:76] + node _T_47 = and(io.bus_clk_en, _T_46) @[axi4_to_ahb.scala 167:37] + bus_write_clk_en <= _T_47 @[axi4_to_ahb.scala 167:20] + inst rvclkhdr of rvclkhdr_869 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr.io.l1clk @[axi4_to_ahb.scala 169:11] + node _T_48 = bits(bus_write_clk_en, 0, 0) @[axi4_to_ahb.scala 170:59] + inst rvclkhdr_1 of rvclkhdr_870 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= _T_48 @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_write_clk <= rvclkhdr_1.io.l1clk @[axi4_to_ahb.scala 170:17] + node _T_49 = eq(UInt<3>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_49 : @[Conditional.scala 40:58] + master_ready <= UInt<1>("h01") @[axi4_to_ahb.scala 174:20] + node _T_50 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 175:34] + node _T_51 = eq(_T_50, UInt<1>("h01")) @[axi4_to_ahb.scala 175:41] + buf_write_in <= _T_51 @[axi4_to_ahb.scala 175:20] + node _T_52 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 176:46] + node _T_53 = mux(_T_52, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 176:26] + buf_nxtstate <= _T_53 @[axi4_to_ahb.scala 176:20] + node _T_54 = and(master_valid, UInt<1>("h01")) @[axi4_to_ahb.scala 177:36] + buf_state_en <= _T_54 @[axi4_to_ahb.scala 177:20] + buf_wr_en <= buf_state_en @[axi4_to_ahb.scala 178:17] + node _T_55 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 179:54] + node _T_56 = and(buf_state_en, _T_55) @[axi4_to_ahb.scala 179:38] + buf_data_wr_en <= _T_56 @[axi4_to_ahb.scala 179:22] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 180:27] + node _T_57 = bits(buf_write_in, 0, 0) @[axi4_to_ahb.scala 182:50] + node _T_58 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 182:94] + node _T_59 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_60 = tail(_T_59, 1) @[axi4_to_ahb.scala 142:52] + node _T_61 = mux(UInt<1>("h00"), _T_60, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_62 = bits(_T_58, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_63 = geq(UInt<1>("h00"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_64 = and(_T_62, _T_63) @[axi4_to_ahb.scala 143:48] + node _T_65 = bits(_T_58, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_66 = geq(UInt<1>("h01"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_67 = and(_T_65, _T_66) @[axi4_to_ahb.scala 143:48] + node _T_68 = bits(_T_58, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_69 = geq(UInt<2>("h02"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_70 = and(_T_68, _T_69) @[axi4_to_ahb.scala 143:48] + node _T_71 = bits(_T_58, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_72 = geq(UInt<2>("h03"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_73 = and(_T_71, _T_72) @[axi4_to_ahb.scala 143:48] + node _T_74 = bits(_T_58, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_75 = geq(UInt<3>("h04"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_76 = and(_T_74, _T_75) @[axi4_to_ahb.scala 143:48] + node _T_77 = bits(_T_58, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_78 = geq(UInt<3>("h05"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_79 = and(_T_77, _T_78) @[axi4_to_ahb.scala 143:48] + node _T_80 = bits(_T_58, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_81 = geq(UInt<3>("h06"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_82 = and(_T_80, _T_81) @[axi4_to_ahb.scala 143:48] + node _T_83 = bits(_T_58, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_84 = geq(UInt<3>("h07"), _T_61) @[axi4_to_ahb.scala 143:62] + node _T_85 = and(_T_83, _T_84) @[axi4_to_ahb.scala 143:48] + node _T_86 = mux(_T_85, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_87 = mux(_T_82, UInt<3>("h06"), _T_86) @[Mux.scala 98:16] + node _T_88 = mux(_T_79, UInt<3>("h05"), _T_87) @[Mux.scala 98:16] + node _T_89 = mux(_T_76, UInt<3>("h04"), _T_88) @[Mux.scala 98:16] + node _T_90 = mux(_T_73, UInt<2>("h03"), _T_89) @[Mux.scala 98:16] + node _T_91 = mux(_T_70, UInt<2>("h02"), _T_90) @[Mux.scala 98:16] + node _T_92 = mux(_T_67, UInt<1>("h01"), _T_91) @[Mux.scala 98:16] + node _T_93 = mux(_T_64, UInt<1>("h00"), _T_92) @[Mux.scala 98:16] + node _T_94 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 182:124] + node _T_95 = mux(_T_57, _T_93, _T_94) @[axi4_to_ahb.scala 182:30] + buf_cmd_byte_ptr <= _T_95 @[axi4_to_ahb.scala 182:24] + bypass_en <= buf_state_en @[axi4_to_ahb.scala 183:17] + node _T_96 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 184:51] + node _T_97 = and(bypass_en, _T_96) @[axi4_to_ahb.scala 184:35] + rd_bypass_idle <= _T_97 @[axi4_to_ahb.scala 184:22] + node _T_98 = bits(bypass_en, 0, 0) @[Bitwise.scala 72:15] + node _T_99 = mux(_T_98, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_100 = and(_T_99, UInt<2>("h02")) @[axi4_to_ahb.scala 185:49] + io.ahb.out.htrans <= _T_100 @[axi4_to_ahb.scala 185:25] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_101 = eq(UInt<3>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_101 : @[Conditional.scala 39:67] + node _T_102 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 189:54] + node _T_103 = eq(_T_102, UInt<1>("h00")) @[axi4_to_ahb.scala 189:61] + node _T_104 = and(master_valid, _T_103) @[axi4_to_ahb.scala 189:41] + node _T_105 = bits(_T_104, 0, 0) @[axi4_to_ahb.scala 189:82] + node _T_106 = mux(_T_105, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 189:26] + buf_nxtstate <= _T_106 @[axi4_to_ahb.scala 189:20] + node _T_107 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 190:51] + node _T_108 = neq(_T_107, UInt<1>("h00")) @[axi4_to_ahb.scala 190:58] + node _T_109 = and(ahb_hready_q, _T_108) @[axi4_to_ahb.scala 190:36] + node _T_110 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 190:72] + node _T_111 = and(_T_109, _T_110) @[axi4_to_ahb.scala 190:70] + buf_state_en <= _T_111 @[axi4_to_ahb.scala 190:20] + node _T_112 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 191:34] + node _T_113 = and(buf_state_en, _T_112) @[axi4_to_ahb.scala 191:32] + cmd_done <= _T_113 @[axi4_to_ahb.scala 191:16] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 192:20] + node _T_114 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 193:52] + node _T_115 = neq(_T_114, UInt<1>("h00")) @[axi4_to_ahb.scala 193:59] + node _T_116 = and(ahb_hready_q, _T_115) @[axi4_to_ahb.scala 193:37] + node _T_117 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 193:73] + node _T_118 = and(_T_116, _T_117) @[axi4_to_ahb.scala 193:71] + node _T_119 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 193:122] + node _T_120 = eq(_T_119, UInt<1>("h00")) @[axi4_to_ahb.scala 193:129] + node _T_121 = and(master_valid, _T_120) @[axi4_to_ahb.scala 193:109] + node _T_122 = bits(_T_121, 0, 0) @[axi4_to_ahb.scala 193:150] + node _T_123 = mux(_T_122, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 193:94] + node _T_124 = eq(_T_123, UInt<3>("h06")) @[axi4_to_ahb.scala 193:174] + node _T_125 = and(_T_118, _T_124) @[axi4_to_ahb.scala 193:88] + master_ready <= _T_125 @[axi4_to_ahb.scala 193:20] + buf_wr_en <= master_ready @[axi4_to_ahb.scala 194:17] + node _T_126 = and(master_ready, master_valid) @[axi4_to_ahb.scala 195:33] + bypass_en <= _T_126 @[axi4_to_ahb.scala 195:17] + node _T_127 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 196:47] + node _T_128 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 196:62] + node _T_129 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 196:78] + node _T_130 = mux(_T_127, _T_128, _T_129) @[axi4_to_ahb.scala 196:30] + buf_cmd_byte_ptr <= _T_130 @[axi4_to_ahb.scala 196:24] + node _T_131 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 197:48] + node _T_132 = or(_T_131, bypass_en) @[axi4_to_ahb.scala 197:62] + node _T_133 = bits(_T_132, 0, 0) @[Bitwise.scala 72:15] + node _T_134 = mux(_T_133, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_135 = and(UInt<2>("h02"), _T_134) @[axi4_to_ahb.scala 197:36] + io.ahb.out.htrans <= _T_135 @[axi4_to_ahb.scala 197:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_136 = eq(UInt<3>("h06"), buf_state) @[Conditional.scala 37:30] + when _T_136 : @[Conditional.scala 39:67] + node _T_137 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 201:39] + node _T_138 = and(ahb_hready_q, _T_137) @[axi4_to_ahb.scala 201:37] + node _T_139 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 201:82] + node _T_140 = eq(_T_139, UInt<1>("h01")) @[axi4_to_ahb.scala 201:89] + node _T_141 = and(master_valid, _T_140) @[axi4_to_ahb.scala 201:70] + node _T_142 = not(_T_141) @[axi4_to_ahb.scala 201:55] + node _T_143 = and(_T_138, _T_142) @[axi4_to_ahb.scala 201:53] + master_ready <= _T_143 @[axi4_to_ahb.scala 201:20] + node _T_144 = and(master_valid, master_ready) @[axi4_to_ahb.scala 202:34] + node _T_145 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 202:62] + node _T_146 = eq(_T_145, UInt<1>("h00")) @[axi4_to_ahb.scala 202:69] + node _T_147 = and(_T_144, _T_146) @[axi4_to_ahb.scala 202:49] + buf_wr_en <= _T_147 @[axi4_to_ahb.scala 202:17] + node _T_148 = bits(ahb_hresp_q, 0, 0) @[axi4_to_ahb.scala 203:45] + node _T_149 = and(master_valid, master_ready) @[axi4_to_ahb.scala 203:82] + node _T_150 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 203:110] + node _T_151 = eq(_T_150, UInt<1>("h00")) @[axi4_to_ahb.scala 203:117] + node _T_152 = and(_T_149, _T_151) @[axi4_to_ahb.scala 203:97] + node _T_153 = bits(_T_152, 0, 0) @[axi4_to_ahb.scala 203:138] + node _T_154 = mux(_T_153, UInt<3>("h06"), UInt<3>("h03")) @[axi4_to_ahb.scala 203:67] + node _T_155 = mux(_T_148, UInt<3>("h07"), _T_154) @[axi4_to_ahb.scala 203:26] + buf_nxtstate <= _T_155 @[axi4_to_ahb.scala 203:20] + node _T_156 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 204:37] + buf_state_en <= _T_156 @[axi4_to_ahb.scala 204:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 205:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 206:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 207:23] + node _T_157 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 208:41] + node _T_158 = and(buf_state_en, _T_157) @[axi4_to_ahb.scala 208:39] + slave_valid_pre <= _T_158 @[axi4_to_ahb.scala 208:23] + node _T_159 = eq(master_valid, UInt<1>("h00")) @[axi4_to_ahb.scala 209:34] + node _T_160 = and(buf_state_en, _T_159) @[axi4_to_ahb.scala 209:32] + cmd_done <= _T_160 @[axi4_to_ahb.scala 209:16] + node _T_161 = and(master_ready, master_valid) @[axi4_to_ahb.scala 210:33] + node _T_162 = eq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 210:64] + node _T_163 = and(_T_161, _T_162) @[axi4_to_ahb.scala 210:48] + node _T_164 = and(_T_163, buf_state_en) @[axi4_to_ahb.scala 210:79] + bypass_en <= _T_164 @[axi4_to_ahb.scala 210:17] + node _T_165 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 211:47] + node _T_166 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 211:62] + node _T_167 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 211:78] + node _T_168 = mux(_T_165, _T_166, _T_167) @[axi4_to_ahb.scala 211:30] + buf_cmd_byte_ptr <= _T_168 @[axi4_to_ahb.scala 211:24] + node _T_169 = neq(buf_nxtstate, UInt<3>("h06")) @[axi4_to_ahb.scala 212:63] + node _T_170 = and(_T_169, buf_state_en) @[axi4_to_ahb.scala 212:78] + node _T_171 = eq(_T_170, UInt<1>("h00")) @[axi4_to_ahb.scala 212:47] + node _T_172 = bits(_T_171, 0, 0) @[Bitwise.scala 72:15] + node _T_173 = mux(_T_172, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_174 = and(UInt<2>("h02"), _T_173) @[axi4_to_ahb.scala 212:36] + io.ahb.out.htrans <= _T_174 @[axi4_to_ahb.scala 212:25] + slvbuf_wr_en <= buf_wr_en @[axi4_to_ahb.scala 213:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_175 = eq(UInt<3>("h07"), buf_state) @[Conditional.scala 37:30] + when _T_175 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h03") @[axi4_to_ahb.scala 217:20] + node _T_176 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 218:51] + node _T_177 = neq(_T_176, UInt<1>("h00")) @[axi4_to_ahb.scala 218:58] + node _T_178 = and(ahb_hready_q, _T_177) @[axi4_to_ahb.scala 218:36] + node _T_179 = eq(ahb_hwrite_q, UInt<1>("h00")) @[axi4_to_ahb.scala 218:72] + node _T_180 = and(_T_178, _T_179) @[axi4_to_ahb.scala 218:70] + buf_state_en <= _T_180 @[axi4_to_ahb.scala 218:20] + slave_valid_pre <= buf_state_en @[axi4_to_ahb.scala 219:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 220:20] + node _T_181 = bits(buf_addr, 2, 0) @[axi4_to_ahb.scala 221:35] + buf_cmd_byte_ptr <= _T_181 @[axi4_to_ahb.scala 221:24] + node _T_182 = eq(buf_state_en, UInt<1>("h00")) @[axi4_to_ahb.scala 222:51] + node _T_183 = bits(_T_182, 0, 0) @[Bitwise.scala 72:15] + node _T_184 = mux(_T_183, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_185 = and(UInt<2>("h02"), _T_184) @[axi4_to_ahb.scala 222:41] + io.ahb.out.htrans <= _T_185 @[axi4_to_ahb.scala 222:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_186 = eq(UInt<3>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_186 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h05") @[axi4_to_ahb.scala 226:20] + node _T_187 = or(ahb_hready_q, ahb_hresp_q) @[axi4_to_ahb.scala 227:37] + buf_state_en <= _T_187 @[axi4_to_ahb.scala 227:20] + buf_data_wr_en <= buf_state_en @[axi4_to_ahb.scala 228:22] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 229:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 230:23] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 231:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_188 = eq(UInt<3>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_188 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h04") @[axi4_to_ahb.scala 235:20] + node _T_189 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 236:33] + node _T_190 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 236:63] + node _T_191 = neq(_T_190, UInt<1>("h00")) @[axi4_to_ahb.scala 236:70] + node _T_192 = and(_T_189, _T_191) @[axi4_to_ahb.scala 236:48] + trxn_done <= _T_192 @[axi4_to_ahb.scala 236:17] + buf_state_en <= trxn_done @[axi4_to_ahb.scala 237:20] + buf_cmd_byte_ptr_en <= buf_state_en @[axi4_to_ahb.scala 238:27] + slvbuf_wr_en <= buf_state_en @[axi4_to_ahb.scala 239:20] + node _T_193 = bits(trxn_done, 0, 0) @[axi4_to_ahb.scala 240:47] + node _T_194 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 240:85] + node _T_195 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 240:103] + node _T_196 = add(_T_194, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_197 = tail(_T_196, 1) @[axi4_to_ahb.scala 142:52] + node _T_198 = mux(UInt<1>("h01"), _T_197, _T_194) @[axi4_to_ahb.scala 142:24] + node _T_199 = bits(_T_195, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_200 = geq(UInt<1>("h00"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_201 = and(_T_199, _T_200) @[axi4_to_ahb.scala 143:48] + node _T_202 = bits(_T_195, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_203 = geq(UInt<1>("h01"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_204 = and(_T_202, _T_203) @[axi4_to_ahb.scala 143:48] + node _T_205 = bits(_T_195, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_206 = geq(UInt<2>("h02"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_207 = and(_T_205, _T_206) @[axi4_to_ahb.scala 143:48] + node _T_208 = bits(_T_195, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_209 = geq(UInt<2>("h03"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_210 = and(_T_208, _T_209) @[axi4_to_ahb.scala 143:48] + node _T_211 = bits(_T_195, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_212 = geq(UInt<3>("h04"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_213 = and(_T_211, _T_212) @[axi4_to_ahb.scala 143:48] + node _T_214 = bits(_T_195, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_215 = geq(UInt<3>("h05"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_216 = and(_T_214, _T_215) @[axi4_to_ahb.scala 143:48] + node _T_217 = bits(_T_195, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_218 = geq(UInt<3>("h06"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_219 = and(_T_217, _T_218) @[axi4_to_ahb.scala 143:48] + node _T_220 = bits(_T_195, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_221 = geq(UInt<3>("h07"), _T_198) @[axi4_to_ahb.scala 143:62] + node _T_222 = and(_T_220, _T_221) @[axi4_to_ahb.scala 143:48] + node _T_223 = mux(_T_222, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_224 = mux(_T_219, UInt<3>("h06"), _T_223) @[Mux.scala 98:16] + node _T_225 = mux(_T_216, UInt<3>("h05"), _T_224) @[Mux.scala 98:16] + node _T_226 = mux(_T_213, UInt<3>("h04"), _T_225) @[Mux.scala 98:16] + node _T_227 = mux(_T_210, UInt<2>("h03"), _T_226) @[Mux.scala 98:16] + node _T_228 = mux(_T_207, UInt<2>("h02"), _T_227) @[Mux.scala 98:16] + node _T_229 = mux(_T_204, UInt<1>("h01"), _T_228) @[Mux.scala 98:16] + node _T_230 = mux(_T_201, UInt<1>("h00"), _T_229) @[Mux.scala 98:16] + node _T_231 = mux(_T_193, _T_230, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 240:30] + buf_cmd_byte_ptr <= _T_231 @[axi4_to_ahb.scala 240:24] + node _T_232 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 241:65] + node _T_233 = or(buf_aligned, _T_232) @[axi4_to_ahb.scala 241:44] + node _T_234 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 241:127] + node _T_235 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 241:145] + node _T_236 = add(_T_234, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_237 = tail(_T_236, 1) @[axi4_to_ahb.scala 142:52] + node _T_238 = mux(UInt<1>("h01"), _T_237, _T_234) @[axi4_to_ahb.scala 142:24] + node _T_239 = bits(_T_235, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_240 = geq(UInt<1>("h00"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_241 = and(_T_239, _T_240) @[axi4_to_ahb.scala 143:48] + node _T_242 = bits(_T_235, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_243 = geq(UInt<1>("h01"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_244 = and(_T_242, _T_243) @[axi4_to_ahb.scala 143:48] + node _T_245 = bits(_T_235, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_246 = geq(UInt<2>("h02"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_247 = and(_T_245, _T_246) @[axi4_to_ahb.scala 143:48] + node _T_248 = bits(_T_235, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_249 = geq(UInt<2>("h03"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_250 = and(_T_248, _T_249) @[axi4_to_ahb.scala 143:48] + node _T_251 = bits(_T_235, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_252 = geq(UInt<3>("h04"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_253 = and(_T_251, _T_252) @[axi4_to_ahb.scala 143:48] + node _T_254 = bits(_T_235, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_255 = geq(UInt<3>("h05"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_256 = and(_T_254, _T_255) @[axi4_to_ahb.scala 143:48] + node _T_257 = bits(_T_235, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_258 = geq(UInt<3>("h06"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_259 = and(_T_257, _T_258) @[axi4_to_ahb.scala 143:48] + node _T_260 = bits(_T_235, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_261 = geq(UInt<3>("h07"), _T_238) @[axi4_to_ahb.scala 143:62] + node _T_262 = and(_T_260, _T_261) @[axi4_to_ahb.scala 143:48] + node _T_263 = mux(_T_262, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_264 = mux(_T_259, UInt<3>("h06"), _T_263) @[Mux.scala 98:16] + node _T_265 = mux(_T_256, UInt<3>("h05"), _T_264) @[Mux.scala 98:16] + node _T_266 = mux(_T_253, UInt<3>("h04"), _T_265) @[Mux.scala 98:16] + node _T_267 = mux(_T_250, UInt<2>("h03"), _T_266) @[Mux.scala 98:16] + node _T_268 = mux(_T_247, UInt<2>("h02"), _T_267) @[Mux.scala 98:16] + node _T_269 = mux(_T_244, UInt<1>("h01"), _T_268) @[Mux.scala 98:16] + node _T_270 = mux(_T_241, UInt<1>("h00"), _T_269) @[Mux.scala 98:16] + node _T_271 = dshr(buf_byteen, _T_270) @[axi4_to_ahb.scala 241:92] + node _T_272 = bits(_T_271, 0, 0) @[axi4_to_ahb.scala 241:92] + node _T_273 = eq(_T_272, UInt<1>("h00")) @[axi4_to_ahb.scala 241:163] + node _T_274 = or(_T_233, _T_273) @[axi4_to_ahb.scala 241:79] + node _T_275 = and(trxn_done, _T_274) @[axi4_to_ahb.scala 241:29] + cmd_done <= _T_275 @[axi4_to_ahb.scala 241:16] + node _T_276 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 242:47] + node _T_277 = eq(_T_276, UInt<1>("h00")) @[axi4_to_ahb.scala 242:36] + node _T_278 = bits(_T_277, 0, 0) @[Bitwise.scala 72:15] + node _T_279 = mux(_T_278, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_280 = and(_T_279, UInt<2>("h02")) @[axi4_to_ahb.scala 242:61] + io.ahb.out.htrans <= _T_280 @[axi4_to_ahb.scala 242:25] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_281 = eq(UInt<3>("h04"), buf_state) @[Conditional.scala 37:30] + when _T_281 : @[Conditional.scala 39:67] + node _T_282 = and(cmd_doneQ, ahb_hready_q) @[axi4_to_ahb.scala 246:34] + node _T_283 = or(_T_282, ahb_hresp_q) @[axi4_to_ahb.scala 246:50] + buf_state_en <= _T_283 @[axi4_to_ahb.scala 246:20] + node _T_284 = eq(ahb_hresp_q, UInt<1>("h00")) @[axi4_to_ahb.scala 247:38] + node _T_285 = and(buf_state_en, _T_284) @[axi4_to_ahb.scala 247:36] + node _T_286 = and(_T_285, slave_ready) @[axi4_to_ahb.scala 247:51] + master_ready <= _T_286 @[axi4_to_ahb.scala 247:20] + node _T_287 = eq(slave_ready, UInt<1>("h00")) @[axi4_to_ahb.scala 248:42] + node _T_288 = or(ahb_hresp_q, _T_287) @[axi4_to_ahb.scala 248:40] + node _T_289 = and(master_valid, master_valid) @[axi4_to_ahb.scala 248:80] + node _T_290 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 248:111] + node _T_291 = eq(_T_290, UInt<1>("h01")) @[axi4_to_ahb.scala 248:117] + node _T_292 = bits(_T_291, 0, 0) @[axi4_to_ahb.scala 248:132] + node _T_293 = mux(_T_292, UInt<3>("h02"), UInt<3>("h01")) @[axi4_to_ahb.scala 248:99] + node _T_294 = mux(_T_289, _T_293, UInt<3>("h00")) @[axi4_to_ahb.scala 248:65] + node _T_295 = mux(_T_288, UInt<3>("h05"), _T_294) @[axi4_to_ahb.scala 248:26] + buf_nxtstate <= _T_295 @[axi4_to_ahb.scala 248:20] + slvbuf_error_in <= ahb_hresp_q @[axi4_to_ahb.scala 249:23] + slvbuf_error_en <= buf_state_en @[axi4_to_ahb.scala 250:23] + node _T_296 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 251:33] + node _T_297 = eq(_T_296, UInt<1>("h01")) @[axi4_to_ahb.scala 251:39] + buf_write_in <= _T_297 @[axi4_to_ahb.scala 251:20] + node _T_298 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 252:50] + node _T_299 = eq(buf_nxtstate, UInt<3>("h01")) @[axi4_to_ahb.scala 252:78] + node _T_300 = or(_T_298, _T_299) @[axi4_to_ahb.scala 252:62] + node _T_301 = and(buf_state_en, _T_300) @[axi4_to_ahb.scala 252:33] + buf_wr_en <= _T_301 @[axi4_to_ahb.scala 252:17] + buf_data_wr_en <= buf_wr_en @[axi4_to_ahb.scala 253:22] + node _T_302 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 254:65] + node _T_303 = neq(_T_302, UInt<1>("h00")) @[axi4_to_ahb.scala 254:71] + node _T_304 = and(ahb_hready_q, _T_303) @[axi4_to_ahb.scala 254:50] + node _T_305 = eq(buf_cmd_byte_ptrQ, UInt<3>("h07")) @[axi4_to_ahb.scala 255:29] + node _T_306 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 255:85] + node _T_307 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 255:101] + node _T_308 = add(_T_306, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_309 = tail(_T_308, 1) @[axi4_to_ahb.scala 142:52] + node _T_310 = mux(UInt<1>("h01"), _T_309, _T_306) @[axi4_to_ahb.scala 142:24] + node _T_311 = bits(_T_307, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_312 = geq(UInt<1>("h00"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_313 = and(_T_311, _T_312) @[axi4_to_ahb.scala 143:48] + node _T_314 = bits(_T_307, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_315 = geq(UInt<1>("h01"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_316 = and(_T_314, _T_315) @[axi4_to_ahb.scala 143:48] + node _T_317 = bits(_T_307, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_318 = geq(UInt<2>("h02"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_319 = and(_T_317, _T_318) @[axi4_to_ahb.scala 143:48] + node _T_320 = bits(_T_307, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_321 = geq(UInt<2>("h03"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_322 = and(_T_320, _T_321) @[axi4_to_ahb.scala 143:48] + node _T_323 = bits(_T_307, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_324 = geq(UInt<3>("h04"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_325 = and(_T_323, _T_324) @[axi4_to_ahb.scala 143:48] + node _T_326 = bits(_T_307, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_327 = geq(UInt<3>("h05"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_328 = and(_T_326, _T_327) @[axi4_to_ahb.scala 143:48] + node _T_329 = bits(_T_307, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_330 = geq(UInt<3>("h06"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_331 = and(_T_329, _T_330) @[axi4_to_ahb.scala 143:48] + node _T_332 = bits(_T_307, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_333 = geq(UInt<3>("h07"), _T_310) @[axi4_to_ahb.scala 143:62] + node _T_334 = and(_T_332, _T_333) @[axi4_to_ahb.scala 143:48] + node _T_335 = mux(_T_334, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_336 = mux(_T_331, UInt<3>("h06"), _T_335) @[Mux.scala 98:16] + node _T_337 = mux(_T_328, UInt<3>("h05"), _T_336) @[Mux.scala 98:16] + node _T_338 = mux(_T_325, UInt<3>("h04"), _T_337) @[Mux.scala 98:16] + node _T_339 = mux(_T_322, UInt<2>("h03"), _T_338) @[Mux.scala 98:16] + node _T_340 = mux(_T_319, UInt<2>("h02"), _T_339) @[Mux.scala 98:16] + node _T_341 = mux(_T_316, UInt<1>("h01"), _T_340) @[Mux.scala 98:16] + node _T_342 = mux(_T_313, UInt<1>("h00"), _T_341) @[Mux.scala 98:16] + node _T_343 = dshr(buf_byteen, _T_342) @[axi4_to_ahb.scala 255:51] + node _T_344 = bits(_T_343, 0, 0) @[axi4_to_ahb.scala 255:51] + node _T_345 = eq(_T_344, UInt<1>("h00")) @[axi4_to_ahb.scala 255:116] + node _T_346 = or(_T_305, _T_345) @[axi4_to_ahb.scala 255:38] + node _T_347 = and(_T_304, _T_346) @[axi4_to_ahb.scala 254:80] + node _T_348 = or(ahb_hresp_q, _T_347) @[axi4_to_ahb.scala 254:34] + cmd_done <= _T_348 @[axi4_to_ahb.scala 254:16] + node _T_349 = and(buf_state_en, buf_write_in) @[axi4_to_ahb.scala 256:33] + node _T_350 = eq(buf_nxtstate, UInt<3>("h02")) @[axi4_to_ahb.scala 256:64] + node _T_351 = and(_T_349, _T_350) @[axi4_to_ahb.scala 256:48] + bypass_en <= _T_351 @[axi4_to_ahb.scala 256:17] + node _T_352 = or(cmd_done, cmd_doneQ) @[axi4_to_ahb.scala 257:48] + node _T_353 = eq(_T_352, UInt<1>("h00")) @[axi4_to_ahb.scala 257:37] + node _T_354 = or(_T_353, bypass_en) @[axi4_to_ahb.scala 257:61] + node _T_355 = bits(_T_354, 0, 0) @[Bitwise.scala 72:15] + node _T_356 = mux(_T_355, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_357 = and(_T_356, UInt<2>("h02")) @[axi4_to_ahb.scala 257:75] + io.ahb.out.htrans <= _T_357 @[axi4_to_ahb.scala 257:25] + node _T_358 = neq(buf_nxtstate, UInt<3>("h05")) @[axi4_to_ahb.scala 258:55] + node _T_359 = and(buf_state_en, _T_358) @[axi4_to_ahb.scala 258:39] + slave_valid_pre <= _T_359 @[axi4_to_ahb.scala 258:23] + node _T_360 = and(ahb_hready_q, ahb_hwrite_q) @[axi4_to_ahb.scala 259:33] + node _T_361 = bits(ahb_htrans_q, 1, 0) @[axi4_to_ahb.scala 259:63] + node _T_362 = neq(_T_361, UInt<1>("h00")) @[axi4_to_ahb.scala 259:69] + node _T_363 = and(_T_360, _T_362) @[axi4_to_ahb.scala 259:48] + trxn_done <= _T_363 @[axi4_to_ahb.scala 259:17] + node _T_364 = or(trxn_done, bypass_en) @[axi4_to_ahb.scala 260:40] + buf_cmd_byte_ptr_en <= _T_364 @[axi4_to_ahb.scala 260:27] + node _T_365 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 261:79] + node _T_366 = add(UInt<3>("h00"), UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_367 = tail(_T_366, 1) @[axi4_to_ahb.scala 142:52] + node _T_368 = mux(UInt<1>("h00"), _T_367, UInt<3>("h00")) @[axi4_to_ahb.scala 142:24] + node _T_369 = bits(_T_365, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_370 = geq(UInt<1>("h00"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_371 = and(_T_369, _T_370) @[axi4_to_ahb.scala 143:48] + node _T_372 = bits(_T_365, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_373 = geq(UInt<1>("h01"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_374 = and(_T_372, _T_373) @[axi4_to_ahb.scala 143:48] + node _T_375 = bits(_T_365, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_376 = geq(UInt<2>("h02"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_377 = and(_T_375, _T_376) @[axi4_to_ahb.scala 143:48] + node _T_378 = bits(_T_365, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_379 = geq(UInt<2>("h03"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_380 = and(_T_378, _T_379) @[axi4_to_ahb.scala 143:48] + node _T_381 = bits(_T_365, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_382 = geq(UInt<3>("h04"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_383 = and(_T_381, _T_382) @[axi4_to_ahb.scala 143:48] + node _T_384 = bits(_T_365, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_385 = geq(UInt<3>("h05"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_386 = and(_T_384, _T_385) @[axi4_to_ahb.scala 143:48] + node _T_387 = bits(_T_365, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_388 = geq(UInt<3>("h06"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_389 = and(_T_387, _T_388) @[axi4_to_ahb.scala 143:48] + node _T_390 = bits(_T_365, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_391 = geq(UInt<3>("h07"), _T_368) @[axi4_to_ahb.scala 143:62] + node _T_392 = and(_T_390, _T_391) @[axi4_to_ahb.scala 143:48] + node _T_393 = mux(_T_392, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_394 = mux(_T_389, UInt<3>("h06"), _T_393) @[Mux.scala 98:16] + node _T_395 = mux(_T_386, UInt<3>("h05"), _T_394) @[Mux.scala 98:16] + node _T_396 = mux(_T_383, UInt<3>("h04"), _T_395) @[Mux.scala 98:16] + node _T_397 = mux(_T_380, UInt<2>("h03"), _T_396) @[Mux.scala 98:16] + node _T_398 = mux(_T_377, UInt<2>("h02"), _T_397) @[Mux.scala 98:16] + node _T_399 = mux(_T_374, UInt<1>("h01"), _T_398) @[Mux.scala 98:16] + node _T_400 = mux(_T_371, UInt<1>("h00"), _T_399) @[Mux.scala 98:16] + node _T_401 = bits(buf_cmd_byte_ptrQ, 2, 0) @[axi4_to_ahb.scala 261:141] + node _T_402 = bits(buf_byteen, 7, 0) @[axi4_to_ahb.scala 261:157] + node _T_403 = add(_T_401, UInt<1>("h01")) @[axi4_to_ahb.scala 142:52] + node _T_404 = tail(_T_403, 1) @[axi4_to_ahb.scala 142:52] + node _T_405 = mux(UInt<1>("h01"), _T_404, _T_401) @[axi4_to_ahb.scala 142:24] + node _T_406 = bits(_T_402, 0, 0) @[axi4_to_ahb.scala 143:44] + node _T_407 = geq(UInt<1>("h00"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_408 = and(_T_406, _T_407) @[axi4_to_ahb.scala 143:48] + node _T_409 = bits(_T_402, 1, 1) @[axi4_to_ahb.scala 143:44] + node _T_410 = geq(UInt<1>("h01"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_411 = and(_T_409, _T_410) @[axi4_to_ahb.scala 143:48] + node _T_412 = bits(_T_402, 2, 2) @[axi4_to_ahb.scala 143:44] + node _T_413 = geq(UInt<2>("h02"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_414 = and(_T_412, _T_413) @[axi4_to_ahb.scala 143:48] + node _T_415 = bits(_T_402, 3, 3) @[axi4_to_ahb.scala 143:44] + node _T_416 = geq(UInt<2>("h03"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_417 = and(_T_415, _T_416) @[axi4_to_ahb.scala 143:48] + node _T_418 = bits(_T_402, 4, 4) @[axi4_to_ahb.scala 143:44] + node _T_419 = geq(UInt<3>("h04"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_420 = and(_T_418, _T_419) @[axi4_to_ahb.scala 143:48] + node _T_421 = bits(_T_402, 5, 5) @[axi4_to_ahb.scala 143:44] + node _T_422 = geq(UInt<3>("h05"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_423 = and(_T_421, _T_422) @[axi4_to_ahb.scala 143:48] + node _T_424 = bits(_T_402, 6, 6) @[axi4_to_ahb.scala 143:44] + node _T_425 = geq(UInt<3>("h06"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_426 = and(_T_424, _T_425) @[axi4_to_ahb.scala 143:48] + node _T_427 = bits(_T_402, 7, 7) @[axi4_to_ahb.scala 143:44] + node _T_428 = geq(UInt<3>("h07"), _T_405) @[axi4_to_ahb.scala 143:62] + node _T_429 = and(_T_427, _T_428) @[axi4_to_ahb.scala 143:48] + node _T_430 = mux(_T_429, UInt<3>("h07"), UInt<3>("h07")) @[Mux.scala 98:16] + node _T_431 = mux(_T_426, UInt<3>("h06"), _T_430) @[Mux.scala 98:16] + node _T_432 = mux(_T_423, UInt<3>("h05"), _T_431) @[Mux.scala 98:16] + node _T_433 = mux(_T_420, UInt<3>("h04"), _T_432) @[Mux.scala 98:16] + node _T_434 = mux(_T_417, UInt<2>("h03"), _T_433) @[Mux.scala 98:16] + node _T_435 = mux(_T_414, UInt<2>("h02"), _T_434) @[Mux.scala 98:16] + node _T_436 = mux(_T_411, UInt<1>("h01"), _T_435) @[Mux.scala 98:16] + node _T_437 = mux(_T_408, UInt<1>("h00"), _T_436) @[Mux.scala 98:16] + node _T_438 = mux(trxn_done, _T_437, buf_cmd_byte_ptrQ) @[axi4_to_ahb.scala 261:97] + node _T_439 = mux(bypass_en, _T_400, _T_438) @[axi4_to_ahb.scala 261:30] + buf_cmd_byte_ptr <= _T_439 @[axi4_to_ahb.scala 261:24] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_440 = eq(UInt<3>("h05"), buf_state) @[Conditional.scala 37:30] + when _T_440 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<3>("h00") @[axi4_to_ahb.scala 264:20] + buf_state_en <= slave_ready @[axi4_to_ahb.scala 265:20] + slvbuf_error_en <= UInt<1>("h01") @[axi4_to_ahb.scala 266:23] + slave_valid_pre <= UInt<1>("h01") @[axi4_to_ahb.scala 267:23] + skip @[Conditional.scala 39:67] + cmd_done_rst <= slave_valid_pre @[axi4_to_ahb.scala 271:16] + node _T_441 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 272:33] + node _T_442 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 272:73] + node _T_443 = eq(_T_442, UInt<1>("h01")) @[axi4_to_ahb.scala 272:80] + node _T_444 = and(buf_aligned_in, _T_443) @[axi4_to_ahb.scala 272:60] + node _T_445 = bits(_T_444, 0, 0) @[axi4_to_ahb.scala 272:100] + node _T_446 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 272:132] + node _T_447 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:50] + node _T_448 = eq(_T_447, UInt<8>("h0ff")) @[axi4_to_ahb.scala 134:57] + node _T_449 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:81] + node _T_450 = eq(_T_449, UInt<8>("h0f")) @[axi4_to_ahb.scala 134:88] + node _T_451 = or(_T_448, _T_450) @[axi4_to_ahb.scala 134:70] + node _T_452 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 134:117] + node _T_453 = eq(_T_452, UInt<8>("h03")) @[axi4_to_ahb.scala 134:124] + node _T_454 = or(_T_451, _T_453) @[axi4_to_ahb.scala 134:106] + node _T_455 = bits(_T_454, 0, 0) @[Bitwise.scala 72:15] + node _T_456 = mux(_T_455, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_457 = and(UInt<3>("h00"), _T_456) @[axi4_to_ahb.scala 134:29] + node _T_458 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 135:35] + node _T_459 = eq(_T_458, UInt<8>("h0c")) @[axi4_to_ahb.scala 135:42] + node _T_460 = bits(_T_459, 0, 0) @[Bitwise.scala 72:15] + node _T_461 = mux(_T_460, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_462 = and(UInt<2>("h02"), _T_461) @[axi4_to_ahb.scala 135:15] + node _T_463 = or(_T_457, _T_462) @[axi4_to_ahb.scala 134:146] + node _T_464 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:36] + node _T_465 = eq(_T_464, UInt<8>("h0f0")) @[axi4_to_ahb.scala 136:43] + node _T_466 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 136:67] + node _T_467 = eq(_T_466, UInt<8>("h03")) @[axi4_to_ahb.scala 136:74] + node _T_468 = or(_T_465, _T_467) @[axi4_to_ahb.scala 136:56] + node _T_469 = bits(_T_468, 0, 0) @[Bitwise.scala 72:15] + node _T_470 = mux(_T_469, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_471 = and(UInt<3>("h04"), _T_470) @[axi4_to_ahb.scala 136:15] + node _T_472 = or(_T_463, _T_471) @[axi4_to_ahb.scala 135:63] + node _T_473 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 137:35] + node _T_474 = eq(_T_473, UInt<8>("h0c0")) @[axi4_to_ahb.scala 137:42] + node _T_475 = bits(_T_474, 0, 0) @[Bitwise.scala 72:15] + node _T_476 = mux(_T_475, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_477 = and(UInt<3>("h06"), _T_476) @[axi4_to_ahb.scala 137:15] + node _T_478 = or(_T_472, _T_477) @[axi4_to_ahb.scala 136:96] + node _T_479 = bits(_T_446, 7, 0) @[axi4_to_ahb.scala 138:33] + node _T_480 = eq(_T_479, UInt<8>("h0c0")) @[axi4_to_ahb.scala 138:40] + node _T_481 = bits(_T_480, 0, 0) @[Bitwise.scala 72:15] + node _T_482 = mux(_T_481, UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + node _T_483 = and(UInt<3>("h06"), _T_482) @[axi4_to_ahb.scala 138:13] + node _T_484 = bits(master_addr, 2, 0) @[axi4_to_ahb.scala 272:152] + node _T_485 = mux(_T_445, _T_478, _T_484) @[axi4_to_ahb.scala 272:43] + node _T_486 = cat(_T_441, _T_485) @[Cat.scala 29:58] + buf_addr_in <= _T_486 @[axi4_to_ahb.scala 272:15] + node _T_487 = bits(master_tag, 0, 0) @[axi4_to_ahb.scala 273:27] + buf_tag_in <= _T_487 @[axi4_to_ahb.scala 273:14] + node _T_488 = bits(wrbuf_byteen, 7, 0) @[axi4_to_ahb.scala 274:32] + buf_byteen_in <= _T_488 @[axi4_to_ahb.scala 274:17] + node _T_489 = eq(buf_state, UInt<3>("h03")) @[axi4_to_ahb.scala 275:33] + node _T_490 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 275:59] + node _T_491 = bits(master_wdata, 63, 0) @[axi4_to_ahb.scala 275:80] + node _T_492 = mux(_T_489, _T_490, _T_491) @[axi4_to_ahb.scala 275:21] + buf_data_in <= _T_492 @[axi4_to_ahb.scala 275:15] + node _T_493 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:52] + node _T_494 = eq(_T_493, UInt<2>("h03")) @[axi4_to_ahb.scala 276:58] + node _T_495 = and(buf_aligned_in, _T_494) @[axi4_to_ahb.scala 276:38] + node _T_496 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 276:84] + node _T_497 = eq(_T_496, UInt<1>("h01")) @[axi4_to_ahb.scala 276:91] + node _T_498 = and(_T_495, _T_497) @[axi4_to_ahb.scala 276:71] + node _T_499 = bits(_T_498, 0, 0) @[axi4_to_ahb.scala 276:111] + node _T_500 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 276:142] + node _T_501 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 128:42] + node _T_502 = eq(_T_501, UInt<8>("h0ff")) @[axi4_to_ahb.scala 128:49] + node _T_503 = bits(_T_502, 0, 0) @[Bitwise.scala 72:15] + node _T_504 = mux(_T_503, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_505 = and(UInt<2>("h03"), _T_504) @[axi4_to_ahb.scala 128:25] + node _T_506 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:35] + node _T_507 = eq(_T_506, UInt<8>("h0f0")) @[axi4_to_ahb.scala 129:42] + node _T_508 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 129:64] + node _T_509 = eq(_T_508, UInt<8>("h0f")) @[axi4_to_ahb.scala 129:71] + node _T_510 = or(_T_507, _T_509) @[axi4_to_ahb.scala 129:55] + node _T_511 = bits(_T_510, 0, 0) @[Bitwise.scala 72:15] + node _T_512 = mux(_T_511, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_513 = and(UInt<2>("h02"), _T_512) @[axi4_to_ahb.scala 129:16] + node _T_514 = or(_T_505, _T_513) @[axi4_to_ahb.scala 128:64] + node _T_515 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:40] + node _T_516 = eq(_T_515, UInt<8>("h0c0")) @[axi4_to_ahb.scala 130:47] + node _T_517 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:69] + node _T_518 = eq(_T_517, UInt<6>("h030")) @[axi4_to_ahb.scala 130:76] + node _T_519 = or(_T_516, _T_518) @[axi4_to_ahb.scala 130:60] + node _T_520 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:98] + node _T_521 = eq(_T_520, UInt<8>("h0c")) @[axi4_to_ahb.scala 130:105] + node _T_522 = or(_T_519, _T_521) @[axi4_to_ahb.scala 130:89] + node _T_523 = bits(_T_500, 7, 0) @[axi4_to_ahb.scala 130:132] + node _T_524 = eq(_T_523, UInt<8>("h03")) @[axi4_to_ahb.scala 130:139] + node _T_525 = or(_T_522, _T_524) @[axi4_to_ahb.scala 130:123] + node _T_526 = bits(_T_525, 0, 0) @[Bitwise.scala 72:15] + node _T_527 = mux(_T_526, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_528 = and(UInt<2>("h01"), _T_527) @[axi4_to_ahb.scala 130:21] + node _T_529 = or(_T_514, _T_528) @[axi4_to_ahb.scala 129:93] + node _T_530 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 276:161] + node _T_531 = mux(_T_499, _T_529, _T_530) @[axi4_to_ahb.scala 276:21] + buf_size_in <= _T_531 @[axi4_to_ahb.scala 276:15] + node _T_532 = bits(master_opc, 2, 0) @[axi4_to_ahb.scala 277:32] + node _T_533 = eq(_T_532, UInt<1>("h00")) @[axi4_to_ahb.scala 277:39] + node _T_534 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:17] + node _T_535 = eq(_T_534, UInt<1>("h00")) @[axi4_to_ahb.scala 278:24] + node _T_536 = or(_T_533, _T_535) @[axi4_to_ahb.scala 277:48] + node _T_537 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:47] + node _T_538 = eq(_T_537, UInt<2>("h01")) @[axi4_to_ahb.scala 278:54] + node _T_539 = or(_T_536, _T_538) @[axi4_to_ahb.scala 278:33] + node _T_540 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 278:86] + node _T_541 = eq(_T_540, UInt<2>("h02")) @[axi4_to_ahb.scala 278:93] + node _T_542 = or(_T_539, _T_541) @[axi4_to_ahb.scala 278:72] + node _T_543 = bits(master_size, 1, 0) @[axi4_to_ahb.scala 279:18] + node _T_544 = eq(_T_543, UInt<2>("h03")) @[axi4_to_ahb.scala 279:25] + node _T_545 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:55] + node _T_546 = eq(_T_545, UInt<2>("h03")) @[axi4_to_ahb.scala 279:62] + node _T_547 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:90] + node _T_548 = eq(_T_547, UInt<4>("h0c")) @[axi4_to_ahb.scala 279:97] + node _T_549 = or(_T_546, _T_548) @[axi4_to_ahb.scala 279:74] + node _T_550 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:125] + node _T_551 = eq(_T_550, UInt<6>("h030")) @[axi4_to_ahb.scala 279:132] + node _T_552 = or(_T_549, _T_551) @[axi4_to_ahb.scala 279:109] + node _T_553 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 279:161] + node _T_554 = eq(_T_553, UInt<8>("h0c0")) @[axi4_to_ahb.scala 279:168] + node _T_555 = or(_T_552, _T_554) @[axi4_to_ahb.scala 279:145] + node _T_556 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:21] + node _T_557 = eq(_T_556, UInt<4>("h0f")) @[axi4_to_ahb.scala 280:28] + node _T_558 = or(_T_555, _T_557) @[axi4_to_ahb.scala 279:181] + node _T_559 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:56] + node _T_560 = eq(_T_559, UInt<8>("h0f0")) @[axi4_to_ahb.scala 280:63] + node _T_561 = or(_T_558, _T_560) @[axi4_to_ahb.scala 280:40] + node _T_562 = bits(master_byteen, 7, 0) @[axi4_to_ahb.scala 280:92] + node _T_563 = eq(_T_562, UInt<8>("h0ff")) @[axi4_to_ahb.scala 280:99] + node _T_564 = or(_T_561, _T_563) @[axi4_to_ahb.scala 280:76] + node _T_565 = and(_T_544, _T_564) @[axi4_to_ahb.scala 279:38] + node _T_566 = or(_T_542, _T_565) @[axi4_to_ahb.scala 278:106] + buf_aligned_in <= _T_566 @[axi4_to_ahb.scala 277:18] + node _T_567 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 282:43] + node _T_568 = bits(master_addr, 31, 3) @[axi4_to_ahb.scala 282:62] + node _T_569 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:87] + node _T_570 = cat(_T_568, _T_569) @[Cat.scala 29:58] + node _T_571 = bits(buf_addr, 31, 3) @[axi4_to_ahb.scala 282:108] + node _T_572 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 282:133] + node _T_573 = cat(_T_571, _T_572) @[Cat.scala 29:58] + node _T_574 = mux(_T_567, _T_570, _T_573) @[axi4_to_ahb.scala 282:26] + io.ahb.out.haddr <= _T_574 @[axi4_to_ahb.scala 282:20] + node _T_575 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 283:43] + node _T_576 = bits(buf_aligned_in, 0, 0) @[Bitwise.scala 72:15] + node _T_577 = mux(_T_576, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_578 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 283:94] + node _T_579 = and(_T_577, _T_578) @[axi4_to_ahb.scala 283:81] + node _T_580 = cat(UInt<1>("h00"), _T_579) @[Cat.scala 29:58] + node _T_581 = bits(buf_aligned, 0, 0) @[Bitwise.scala 72:15] + node _T_582 = mux(_T_581, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_583 = bits(buf_size, 1, 0) @[axi4_to_ahb.scala 283:148] + node _T_584 = and(_T_582, _T_583) @[axi4_to_ahb.scala 283:138] + node _T_585 = cat(UInt<1>("h00"), _T_584) @[Cat.scala 29:58] + node _T_586 = mux(_T_575, _T_580, _T_585) @[axi4_to_ahb.scala 283:26] + io.ahb.out.hsize <= _T_586 @[axi4_to_ahb.scala 283:20] + io.ahb.out.hburst <= UInt<1>("h00") @[axi4_to_ahb.scala 285:21] + io.ahb.out.hmastlock <= UInt<1>("h00") @[axi4_to_ahb.scala 286:24] + node _T_587 = bits(io.axi.ar.bits.prot, 2, 2) @[axi4_to_ahb.scala 287:57] + node _T_588 = eq(_T_587, UInt<1>("h00")) @[axi4_to_ahb.scala 287:37] + node _T_589 = cat(UInt<1>("h01"), _T_588) @[Cat.scala 29:58] + io.ahb.out.hprot <= _T_589 @[axi4_to_ahb.scala 287:20] + node _T_590 = bits(bypass_en, 0, 0) @[axi4_to_ahb.scala 288:44] + node _T_591 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 288:59] + node _T_592 = eq(_T_591, UInt<1>("h01")) @[axi4_to_ahb.scala 288:66] + node _T_593 = mux(_T_590, _T_592, buf_write) @[axi4_to_ahb.scala 288:27] + io.ahb.out.hwrite <= _T_593 @[axi4_to_ahb.scala 288:21] + node _T_594 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 289:32] + io.ahb.out.hwdata <= _T_594 @[axi4_to_ahb.scala 289:21] + slave_valid <= slave_valid_pre @[axi4_to_ahb.scala 291:15] + node _T_595 = bits(slvbuf_write, 0, 0) @[axi4_to_ahb.scala 292:43] + node _T_596 = mux(_T_595, UInt<2>("h03"), UInt<1>("h00")) @[axi4_to_ahb.scala 292:23] + node _T_597 = bits(slvbuf_error, 0, 0) @[Bitwise.scala 72:15] + node _T_598 = mux(_T_597, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_599 = and(_T_598, UInt<2>("h02")) @[axi4_to_ahb.scala 292:88] + node _T_600 = cat(_T_596, _T_599) @[Cat.scala 29:58] + slave_opc <= _T_600 @[axi4_to_ahb.scala 292:13] + node _T_601 = bits(slvbuf_error, 0, 0) @[axi4_to_ahb.scala 293:41] + node _T_602 = bits(last_bus_addr, 31, 0) @[axi4_to_ahb.scala 293:66] + node _T_603 = cat(_T_602, _T_602) @[Cat.scala 29:58] + node _T_604 = eq(buf_state, UInt<3>("h05")) @[axi4_to_ahb.scala 293:91] + node _T_605 = bits(buf_data, 63, 0) @[axi4_to_ahb.scala 293:110] + node _T_606 = bits(ahb_hrdata_q, 63, 0) @[axi4_to_ahb.scala 293:131] + node _T_607 = mux(_T_604, _T_605, _T_606) @[axi4_to_ahb.scala 293:79] + node _T_608 = mux(_T_601, _T_603, _T_607) @[axi4_to_ahb.scala 293:21] + slave_rdata <= _T_608 @[axi4_to_ahb.scala 293:15] + node _T_609 = bits(slvbuf_tag, 0, 0) @[axi4_to_ahb.scala 294:26] + slave_tag <= _T_609 @[axi4_to_ahb.scala 294:13] + node _T_610 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 296:37] + node _T_611 = neq(_T_610, UInt<1>("h00")) @[axi4_to_ahb.scala 296:44] + node _T_612 = and(_T_611, io.ahb.in.hready) @[axi4_to_ahb.scala 296:56] + node _T_613 = and(_T_612, io.ahb.out.hwrite) @[axi4_to_ahb.scala 296:75] + last_addr_en <= _T_613 @[axi4_to_ahb.scala 296:16] + node _T_614 = and(io.axi.aw.valid, io.axi.aw.ready) @[axi4_to_ahb.scala 298:31] + node _T_615 = and(_T_614, master_ready) @[axi4_to_ahb.scala 298:49] + wrbuf_en <= _T_615 @[axi4_to_ahb.scala 298:12] + node _T_616 = and(io.axi.w.valid, io.axi.w.ready) @[axi4_to_ahb.scala 299:35] + node _T_617 = and(_T_616, master_ready) @[axi4_to_ahb.scala 299:52] + wrbuf_data_en <= _T_617 @[axi4_to_ahb.scala 299:17] + node _T_618 = and(master_valid, master_ready) @[axi4_to_ahb.scala 300:34] + node _T_619 = bits(master_opc, 2, 1) @[axi4_to_ahb.scala 300:62] + node _T_620 = eq(_T_619, UInt<1>("h01")) @[axi4_to_ahb.scala 300:69] + node _T_621 = and(_T_618, _T_620) @[axi4_to_ahb.scala 300:49] + wrbuf_cmd_sent <= _T_621 @[axi4_to_ahb.scala 300:18] + node _T_622 = eq(wrbuf_en, UInt<1>("h00")) @[axi4_to_ahb.scala 301:33] + node _T_623 = and(wrbuf_cmd_sent, _T_622) @[axi4_to_ahb.scala 301:31] + wrbuf_rst <= _T_623 @[axi4_to_ahb.scala 301:13] + node _T_624 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 303:36] + node _T_625 = and(wrbuf_vld, _T_624) @[axi4_to_ahb.scala 303:34] + node _T_626 = eq(_T_625, UInt<1>("h00")) @[axi4_to_ahb.scala 303:22] + node _T_627 = and(_T_626, master_ready) @[axi4_to_ahb.scala 303:53] + io.axi.aw.ready <= _T_627 @[axi4_to_ahb.scala 303:19] + node _T_628 = eq(wrbuf_cmd_sent, UInt<1>("h00")) @[axi4_to_ahb.scala 304:40] + node _T_629 = and(wrbuf_data_vld, _T_628) @[axi4_to_ahb.scala 304:38] + node _T_630 = eq(_T_629, UInt<1>("h00")) @[axi4_to_ahb.scala 304:21] + node _T_631 = and(_T_630, master_ready) @[axi4_to_ahb.scala 304:57] + io.axi.w.ready <= _T_631 @[axi4_to_ahb.scala 304:18] + node _T_632 = and(wrbuf_vld, wrbuf_data_vld) @[axi4_to_ahb.scala 305:34] + node _T_633 = eq(_T_632, UInt<1>("h00")) @[axi4_to_ahb.scala 305:22] + node _T_634 = and(_T_633, master_ready) @[axi4_to_ahb.scala 305:52] + io.axi.ar.ready <= _T_634 @[axi4_to_ahb.scala 305:19] + io.axi.r.bits.last <= UInt<1>("h01") @[axi4_to_ahb.scala 306:22] + node _T_635 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 308:71] + node _T_636 = mux(_T_635, UInt<1>("h01"), wrbuf_vld) @[axi4_to_ahb.scala 308:55] + node _T_637 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 308:91] + node _T_638 = and(_T_636, _T_637) @[axi4_to_ahb.scala 308:89] + reg _T_639 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 308:51] + _T_639 <= _T_638 @[axi4_to_ahb.scala 308:51] + wrbuf_vld <= _T_639 @[axi4_to_ahb.scala 308:21] + node _T_640 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 309:76] + node _T_641 = mux(_T_640, UInt<1>("h01"), wrbuf_data_vld) @[axi4_to_ahb.scala 309:55] + node _T_642 = eq(wrbuf_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 309:102] + node _T_643 = and(_T_641, _T_642) @[axi4_to_ahb.scala 309:100] + reg _T_644 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 309:51] + _T_644 <= _T_643 @[axi4_to_ahb.scala 309:51] + wrbuf_data_vld <= _T_644 @[axi4_to_ahb.scala 309:21] + node _T_645 = bits(io.axi.aw.bits.id, 0, 0) @[axi4_to_ahb.scala 310:71] + node _T_646 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 310:105] + reg _T_647 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_646 : @[Reg.scala 28:19] + _T_647 <= _T_645 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_tag <= _T_647 @[axi4_to_ahb.scala 310:21] + node _T_648 = bits(io.axi.aw.bits.size, 2, 0) @[axi4_to_ahb.scala 311:73] + node _T_649 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 311:101] + reg _T_650 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_649 : @[Reg.scala 28:19] + _T_650 <= _T_648 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_size <= _T_650 @[axi4_to_ahb.scala 311:21] + node _T_651 = bits(wrbuf_en, 0, 0) @[axi4_to_ahb.scala 312:61] + inst rvclkhdr_2 of rvclkhdr_871 @[lib.scala 368:23] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_2.io.en <= _T_651 @[lib.scala 371:17] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_652 : UInt, rvclkhdr_2.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_652 <= io.axi.aw.bits.addr @[lib.scala 374:16] + wrbuf_addr <= _T_652 @[axi4_to_ahb.scala 312:21] + node _T_653 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 313:65] + inst rvclkhdr_3 of rvclkhdr_872 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_653 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_654 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_654 <= io.axi.w.bits.data @[lib.scala 374:16] + wrbuf_data <= _T_654 @[axi4_to_ahb.scala 313:21] + node _T_655 = bits(io.axi.w.bits.strb, 7, 0) @[axi4_to_ahb.scala 314:72] + node _T_656 = bits(wrbuf_data_en, 0, 0) @[axi4_to_ahb.scala 314:105] + reg _T_657 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_656 : @[Reg.scala 28:19] + _T_657 <= _T_655 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + wrbuf_byteen <= _T_657 @[axi4_to_ahb.scala 314:21] + node _T_658 = bits(io.ahb.out.haddr, 31, 0) @[axi4_to_ahb.scala 315:71] + node _T_659 = bits(last_addr_en, 0, 0) @[axi4_to_ahb.scala 315:104] + reg _T_660 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_659 : @[Reg.scala 28:19] + _T_660 <= _T_658 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + last_bus_addr <= _T_660 @[axi4_to_ahb.scala 315:21] + node _T_661 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 316:89] + reg _T_662 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_661 : @[Reg.scala 28:19] + _T_662 <= buf_write_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_write <= _T_662 @[axi4_to_ahb.scala 316:21] + node _T_663 = bits(buf_tag_in, 0, 0) @[axi4_to_ahb.scala 317:64] + node _T_664 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 317:99] + reg _T_665 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_664 : @[Reg.scala 28:19] + _T_665 <= _T_663 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_tag <= _T_665 @[axi4_to_ahb.scala 317:21] + node _T_666 = bits(buf_addr_in, 31, 0) @[axi4_to_ahb.scala 318:42] + node _T_667 = and(buf_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 318:61] + node _T_668 = bits(_T_667, 0, 0) @[axi4_to_ahb.scala 318:78] + inst rvclkhdr_4 of rvclkhdr_873 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_668 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_669 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_669 <= _T_666 @[lib.scala 374:16] + buf_addr <= _T_669 @[axi4_to_ahb.scala 318:21] + node _T_670 = bits(buf_size_in, 1, 0) @[axi4_to_ahb.scala 319:65] + node _T_671 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 319:94] + reg _T_672 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_671 : @[Reg.scala 28:19] + _T_672 <= _T_670 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_size <= _T_672 @[axi4_to_ahb.scala 319:21] + node _T_673 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 320:91] + reg _T_674 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_673 : @[Reg.scala 28:19] + _T_674 <= buf_aligned_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_aligned <= _T_674 @[axi4_to_ahb.scala 320:21] + node _T_675 = bits(buf_byteen_in, 7, 0) @[axi4_to_ahb.scala 321:67] + node _T_676 = bits(buf_wr_en, 0, 0) @[axi4_to_ahb.scala 321:96] + reg _T_677 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_676 : @[Reg.scala 28:19] + _T_677 <= _T_675 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_byteen <= _T_677 @[axi4_to_ahb.scala 321:21] + node _T_678 = bits(buf_data_in, 63, 0) @[axi4_to_ahb.scala 322:42] + node _T_679 = and(buf_data_wr_en, io.bus_clk_en) @[axi4_to_ahb.scala 322:66] + node _T_680 = bits(_T_679, 0, 0) @[axi4_to_ahb.scala 322:89] + inst rvclkhdr_5 of rvclkhdr_874 @[lib.scala 368:23] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 370:18] + rvclkhdr_5.io.en <= _T_680 @[lib.scala 371:17] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_681 : UInt, rvclkhdr_5.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_681 <= _T_678 @[lib.scala 374:16] + buf_data <= _T_681 @[axi4_to_ahb.scala 322:21] + node _T_682 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 323:89] + reg _T_683 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_682 : @[Reg.scala 28:19] + _T_683 <= buf_write @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_write <= _T_683 @[axi4_to_ahb.scala 323:21] + node _T_684 = bits(buf_tag, 0, 0) @[axi4_to_ahb.scala 324:61] + node _T_685 = bits(slvbuf_wr_en, 0, 0) @[axi4_to_ahb.scala 324:99] + reg _T_686 : UInt, buf_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_685 : @[Reg.scala 28:19] + _T_686 <= _T_684 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_tag <= _T_686 @[axi4_to_ahb.scala 324:21] + node _T_687 = bits(slvbuf_error_en, 0, 0) @[axi4_to_ahb.scala 325:99] + reg _T_688 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_687 : @[Reg.scala 28:19] + _T_688 <= slvbuf_error_in @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + slvbuf_error <= _T_688 @[axi4_to_ahb.scala 325:21] + node _T_689 = bits(cmd_done, 0, 0) @[axi4_to_ahb.scala 326:72] + node _T_690 = mux(_T_689, UInt<1>("h01"), cmd_doneQ) @[axi4_to_ahb.scala 326:56] + node _T_691 = eq(cmd_done_rst, UInt<1>("h00")) @[axi4_to_ahb.scala 326:92] + node _T_692 = and(_T_690, _T_691) @[axi4_to_ahb.scala 326:90] + reg _T_693 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 326:52] + _T_693 <= _T_692 @[axi4_to_ahb.scala 326:52] + cmd_doneQ <= _T_693 @[axi4_to_ahb.scala 326:21] + node _T_694 = bits(buf_cmd_byte_ptr, 2, 0) @[axi4_to_ahb.scala 327:71] + node _T_695 = bits(buf_cmd_byte_ptr_en, 0, 0) @[axi4_to_ahb.scala 327:110] + reg _T_696 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_695 : @[Reg.scala 28:19] + _T_696 <= _T_694 @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_cmd_byte_ptrQ <= _T_696 @[axi4_to_ahb.scala 327:21] + reg _T_697 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 328:52] + _T_697 <= io.ahb.in.hready @[axi4_to_ahb.scala 328:52] + ahb_hready_q <= _T_697 @[axi4_to_ahb.scala 328:21] + node _T_698 = bits(io.ahb.out.htrans, 1, 0) @[axi4_to_ahb.scala 329:70] + reg _T_699 : UInt, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 329:52] + _T_699 <= _T_698 @[axi4_to_ahb.scala 329:52] + ahb_htrans_q <= _T_699 @[axi4_to_ahb.scala 329:21] + reg _T_700 : UInt<1>, ahbm_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 330:57] + _T_700 <= io.ahb.out.hwrite @[axi4_to_ahb.scala 330:57] + ahb_hwrite_q <= _T_700 @[axi4_to_ahb.scala 330:21] + reg _T_701 : UInt<1>, ahbm_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 331:52] + _T_701 <= io.ahb.in.hresp @[axi4_to_ahb.scala 331:52] + ahb_hresp_q <= _T_701 @[axi4_to_ahb.scala 331:21] + node _T_702 = bits(io.ahb.in.hrdata, 63, 0) @[axi4_to_ahb.scala 332:74] + reg _T_703 : UInt, ahbm_data_clk with : (reset => (reset, UInt<1>("h00"))) @[axi4_to_ahb.scala 332:57] + _T_703 <= _T_702 @[axi4_to_ahb.scala 332:57] + ahb_hrdata_q <= _T_703 @[axi4_to_ahb.scala 332:21] + node _T_704 = or(buf_wr_en, slvbuf_wr_en) @[axi4_to_ahb.scala 334:43] + node _T_705 = or(_T_704, io.clk_override) @[axi4_to_ahb.scala 334:58] + node _T_706 = and(io.bus_clk_en, _T_705) @[axi4_to_ahb.scala 334:30] + buf_clken <= _T_706 @[axi4_to_ahb.scala 334:13] + node _T_707 = bits(io.ahb.out.htrans, 1, 1) @[axi4_to_ahb.scala 335:76] + node _T_708 = and(io.ahb.in.hready, _T_707) @[axi4_to_ahb.scala 335:57] + node _T_709 = or(_T_708, io.clk_override) @[axi4_to_ahb.scala 335:81] + node _T_710 = and(io.bus_clk_en, _T_709) @[axi4_to_ahb.scala 335:36] + ahbm_addr_clken <= _T_710 @[axi4_to_ahb.scala 335:19] + node _T_711 = neq(buf_state, UInt<3>("h00")) @[axi4_to_ahb.scala 336:50] + node _T_712 = or(_T_711, io.clk_override) @[axi4_to_ahb.scala 336:60] + node _T_713 = and(io.bus_clk_en, _T_712) @[axi4_to_ahb.scala 336:36] + ahbm_data_clken <= _T_713 @[axi4_to_ahb.scala 336:19] + inst rvclkhdr_6 of rvclkhdr_875 @[lib.scala 343:22] + rvclkhdr_6.clock <= clock + rvclkhdr_6.reset <= reset + rvclkhdr_6.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_6.io.en <= buf_clken @[lib.scala 345:16] + rvclkhdr_6.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_clk <= rvclkhdr_6.io.l1clk @[axi4_to_ahb.scala 339:12] + inst rvclkhdr_7 of rvclkhdr_876 @[lib.scala 343:22] + rvclkhdr_7.clock <= clock + rvclkhdr_7.reset <= reset + rvclkhdr_7.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_7.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_7.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_clk <= rvclkhdr_7.io.l1clk @[axi4_to_ahb.scala 340:12] + inst rvclkhdr_8 of rvclkhdr_877 @[lib.scala 343:22] + rvclkhdr_8.clock <= clock + rvclkhdr_8.reset <= reset + rvclkhdr_8.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_8.io.en <= ahbm_addr_clken @[lib.scala 345:16] + rvclkhdr_8.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_addr_clk <= rvclkhdr_8.io.l1clk @[axi4_to_ahb.scala 341:17] + inst rvclkhdr_9 of rvclkhdr_878 @[lib.scala 343:22] + rvclkhdr_9.clock <= clock + rvclkhdr_9.reset <= reset + rvclkhdr_9.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_9.io.en <= ahbm_data_clken @[lib.scala 345:16] + rvclkhdr_9.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahbm_data_clk <= rvclkhdr_9.io.l1clk @[axi4_to_ahb.scala 342:17] + + extmodule gated_latch_879 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_879 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_879 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_880 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_880 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_880 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_881 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_881 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_881 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_882 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_882 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_882 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_883 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_883 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_883 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + extmodule gated_latch_884 : + output Q : Clock + input CK : Clock + input EN : UInt<1> + input SE : UInt<1> + + defname = gated_latch + + + module rvclkhdr_884 : + input clock : Clock + input reset : Reset + output io : {l1clk : Clock, flip clk : Clock, flip en : UInt<1>, flip scan_mode : UInt<1>} + + inst clkhdr of gated_latch_884 @[lib.scala 334:26] + clkhdr.SE is invalid + clkhdr.EN is invalid + clkhdr.CK is invalid + clkhdr.Q is invalid + io.l1clk <= clkhdr.Q @[lib.scala 335:14] + clkhdr.CK <= io.clk @[lib.scala 336:18] + clkhdr.EN <= io.en @[lib.scala 337:18] + clkhdr.SE <= io.scan_mode @[lib.scala 338:18] + + module ahb_to_axi4 : + input clock : Clock + input reset : AsyncReset + output io : {flip scan_mode : UInt<1>, flip bus_clk_en : UInt<1>, flip clk_override : UInt<1>, axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}} + + wire _T : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.ar.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.bits.resp <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.b.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.last <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.strb <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.bits.data <= UInt<64>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.w.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.qos <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.prot <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.cache <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.lock <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.burst <= UInt<2>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.size <= UInt<3>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.len <= UInt<8>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.region <= UInt<4>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.addr <= UInt<32>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.valid <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.aw.ready <= UInt<1>("h00") @[ahb_to_axi4.scala 20:25] + _T.r.bits.last <= io.axi.r.bits.last @[ahb_to_axi4.scala 20:10] + _T.r.bits.resp <= io.axi.r.bits.resp @[ahb_to_axi4.scala 20:10] + _T.r.bits.data <= io.axi.r.bits.data @[ahb_to_axi4.scala 20:10] + _T.r.bits.id <= io.axi.r.bits.id @[ahb_to_axi4.scala 20:10] + _T.r.valid <= io.axi.r.valid @[ahb_to_axi4.scala 20:10] + io.axi.r.ready <= _T.r.ready @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.qos <= _T.ar.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.prot <= _T.ar.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.cache <= _T.ar.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.lock <= _T.ar.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.burst <= _T.ar.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.size <= _T.ar.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.len <= _T.ar.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.region <= _T.ar.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.addr <= _T.ar.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.ar.bits.id <= _T.ar.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.ar.valid <= _T.ar.valid @[ahb_to_axi4.scala 20:10] + _T.ar.ready <= io.axi.ar.ready @[ahb_to_axi4.scala 20:10] + _T.b.bits.id <= io.axi.b.bits.id @[ahb_to_axi4.scala 20:10] + _T.b.bits.resp <= io.axi.b.bits.resp @[ahb_to_axi4.scala 20:10] + _T.b.valid <= io.axi.b.valid @[ahb_to_axi4.scala 20:10] + io.axi.b.ready <= _T.b.ready @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.last <= _T.w.bits.last @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.strb <= _T.w.bits.strb @[ahb_to_axi4.scala 20:10] + io.axi.w.bits.data <= _T.w.bits.data @[ahb_to_axi4.scala 20:10] + io.axi.w.valid <= _T.w.valid @[ahb_to_axi4.scala 20:10] + _T.w.ready <= io.axi.w.ready @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.qos <= _T.aw.bits.qos @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.prot <= _T.aw.bits.prot @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.cache <= _T.aw.bits.cache @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.lock <= _T.aw.bits.lock @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.burst <= _T.aw.bits.burst @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.size <= _T.aw.bits.size @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.len <= _T.aw.bits.len @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.region <= _T.aw.bits.region @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.addr <= _T.aw.bits.addr @[ahb_to_axi4.scala 20:10] + io.axi.aw.bits.id <= _T.aw.bits.id @[ahb_to_axi4.scala 20:10] + io.axi.aw.valid <= _T.aw.valid @[ahb_to_axi4.scala 20:10] + _T.aw.ready <= io.axi.aw.ready @[ahb_to_axi4.scala 20:10] + wire master_wstrb : UInt<8> + master_wstrb <= UInt<8>("h00") + wire buf_state_en : UInt<1> + buf_state_en <= UInt<1>("h00") + wire buf_read_error_in : UInt<1> + buf_read_error_in <= UInt<1>("h00") + wire buf_read_error : UInt<1> + buf_read_error <= UInt<1>("h00") + wire buf_rdata : UInt<64> + buf_rdata <= UInt<64>("h00") + wire ahb_hready : UInt<1> + ahb_hready <= UInt<1>("h00") + wire ahb_hready_q : UInt<1> + ahb_hready_q <= UInt<1>("h00") + wire ahb_htrans_in : UInt<2> + ahb_htrans_in <= UInt<2>("h00") + wire ahb_htrans_q : UInt<2> + ahb_htrans_q <= UInt<2>("h00") + wire ahb_hsize_q : UInt<3> + ahb_hsize_q <= UInt<3>("h00") + wire ahb_hwrite_q : UInt<1> + ahb_hwrite_q <= UInt<1>("h00") + wire ahb_haddr_q : UInt<32> + ahb_haddr_q <= UInt<32>("h00") + wire ahb_hwdata_q : UInt<64> + ahb_hwdata_q <= UInt<64>("h00") + wire ahb_hresp_q : UInt<1> + ahb_hresp_q <= UInt<1>("h00") + wire buf_rdata_en : UInt<1> + buf_rdata_en <= UInt<1>("h00") + wire ahb_bus_addr_clk_en : UInt<1> + ahb_bus_addr_clk_en <= UInt<1>("h00") + wire buf_rdata_clk_en : UInt<1> + buf_rdata_clk_en <= UInt<1>("h00") + wire ahb_clk : Clock @[ahb_to_axi4.scala 44:33] + wire ahb_addr_clk : Clock @[ahb_to_axi4.scala 45:33] + wire buf_rdata_clk : Clock @[ahb_to_axi4.scala 46:33] + wire cmdbuf_wr_en : UInt<1> + cmdbuf_wr_en <= UInt<1>("h00") + wire cmdbuf_rst : UInt<1> + cmdbuf_rst <= UInt<1>("h00") + wire cmdbuf_full : UInt<1> + cmdbuf_full <= UInt<1>("h00") + wire cmdbuf_vld : UInt<1> + cmdbuf_vld <= UInt<1>("h00") + wire cmdbuf_write : UInt<1> + cmdbuf_write <= UInt<1>("h00") + wire cmdbuf_size : UInt<2> + cmdbuf_size <= UInt<2>("h00") + wire cmdbuf_wstrb : UInt<8> + cmdbuf_wstrb <= UInt<8>("h00") + wire cmdbuf_addr : UInt<32> + cmdbuf_addr <= UInt<32>("h00") + wire cmdbuf_wdata : UInt<64> + cmdbuf_wdata <= UInt<64>("h00") + wire bus_clk : Clock @[ahb_to_axi4.scala 58:33] + node _T_1 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_dccm_region_nc = eq(_T_1, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_2 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_dccm = eq(_T_2, UInt<16>("h0f004")) @[lib.scala 87:29] + node _T_3 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_iccm_region_nc = eq(_T_3, UInt<4>("h0e")) @[lib.scala 84:47] + node _T_4 = bits(ahb_haddr_q, 31, 16) @[lib.scala 87:14] + node ahb_addr_in_iccm = eq(_T_4, UInt<16>("h0ee00")) @[lib.scala 87:29] + node _T_5 = bits(ahb_haddr_q, 31, 28) @[lib.scala 84:25] + node ahb_addr_in_pic_region_nc = eq(_T_5, UInt<4>("h0f")) @[lib.scala 84:47] + node _T_6 = bits(ahb_haddr_q, 31, 15) @[lib.scala 87:14] + node ahb_addr_in_pic = eq(_T_6, UInt<17>("h01e018")) @[lib.scala 87:29] + wire buf_state : UInt<2> + buf_state <= UInt<2>("h00") + wire buf_nxtstate : UInt<2> + buf_nxtstate <= UInt<2>("h00") + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 68:31] + buf_state_en <= UInt<1>("h00") @[ahb_to_axi4.scala 69:31] + buf_rdata_en <= UInt<1>("h00") @[ahb_to_axi4.scala 70:31] + buf_read_error_in <= UInt<1>("h00") @[ahb_to_axi4.scala 71:31] + cmdbuf_wr_en <= UInt<1>("h00") @[ahb_to_axi4.scala 72:31] + node _T_7 = eq(UInt<2>("h00"), buf_state) @[Conditional.scala 37:30] + when _T_7 : @[Conditional.scala 40:58] + node _T_8 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 76:26] + buf_nxtstate <= _T_8 @[ahb_to_axi4.scala 76:20] + node _T_9 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 77:57] + node _T_10 = and(ahb_hready, _T_9) @[ahb_to_axi4.scala 77:34] + node _T_11 = and(_T_10, io.ahb.hsel) @[ahb_to_axi4.scala 77:61] + buf_state_en <= _T_11 @[ahb_to_axi4.scala 77:20] + skip @[Conditional.scala 40:58] + else : @[Conditional.scala 39:67] + node _T_12 = eq(UInt<2>("h01"), buf_state) @[Conditional.scala 37:30] + when _T_12 : @[Conditional.scala 39:67] + node _T_13 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 80:72] + node _T_14 = eq(_T_13, UInt<1>("h00")) @[ahb_to_axi4.scala 80:79] + node _T_15 = or(io.ahb.sig.in.hresp, _T_14) @[ahb_to_axi4.scala 80:48] + node _T_16 = eq(io.ahb.hsel, UInt<1>("h00")) @[ahb_to_axi4.scala 80:93] + node _T_17 = or(_T_15, _T_16) @[ahb_to_axi4.scala 80:91] + node _T_18 = bits(_T_17, 0, 0) @[ahb_to_axi4.scala 80:107] + node _T_19 = mux(io.ahb.sig.out.hwrite, UInt<2>("h01"), UInt<2>("h02")) @[ahb_to_axi4.scala 80:124] + node _T_20 = mux(_T_18, UInt<2>("h00"), _T_19) @[ahb_to_axi4.scala 80:26] + buf_nxtstate <= _T_20 @[ahb_to_axi4.scala 80:20] + node _T_21 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 81:24] + node _T_22 = or(_T_21, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 81:37] + buf_state_en <= _T_22 @[ahb_to_axi4.scala 81:20] + node _T_23 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 82:23] + node _T_24 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 82:85] + node _T_25 = eq(_T_24, UInt<2>("h01")) @[ahb_to_axi4.scala 82:92] + node _T_26 = and(_T_25, io.ahb.hsel) @[ahb_to_axi4.scala 82:110] + node _T_27 = or(io.ahb.sig.in.hresp, _T_26) @[ahb_to_axi4.scala 82:60] + node _T_28 = eq(_T_27, UInt<1>("h00")) @[ahb_to_axi4.scala 82:38] + node _T_29 = and(_T_23, _T_28) @[ahb_to_axi4.scala 82:36] + cmdbuf_wr_en <= _T_29 @[ahb_to_axi4.scala 82:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_30 = eq(UInt<2>("h02"), buf_state) @[Conditional.scala 37:30] + when _T_30 : @[Conditional.scala 39:67] + node _T_31 = mux(io.ahb.sig.in.hresp, UInt<2>("h00"), UInt<2>("h03")) @[ahb_to_axi4.scala 85:26] + buf_nxtstate <= _T_31 @[ahb_to_axi4.scala 85:20] + node _T_32 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 86:24] + node _T_33 = or(_T_32, io.ahb.sig.in.hresp) @[ahb_to_axi4.scala 86:37] + buf_state_en <= _T_33 @[ahb_to_axi4.scala 86:20] + node _T_34 = eq(io.ahb.sig.in.hresp, UInt<1>("h00")) @[ahb_to_axi4.scala 87:23] + node _T_35 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 87:46] + node _T_36 = and(_T_34, _T_35) @[ahb_to_axi4.scala 87:44] + cmdbuf_wr_en <= _T_36 @[ahb_to_axi4.scala 87:20] + skip @[Conditional.scala 39:67] + else : @[Conditional.scala 39:67] + node _T_37 = eq(UInt<2>("h03"), buf_state) @[Conditional.scala 37:30] + when _T_37 : @[Conditional.scala 39:67] + buf_nxtstate <= UInt<2>("h00") @[ahb_to_axi4.scala 90:20] + node _T_38 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 91:40] + node _T_39 = and(io.axi.r.valid, _T_38) @[ahb_to_axi4.scala 91:38] + buf_state_en <= _T_39 @[ahb_to_axi4.scala 91:20] + buf_rdata_en <= buf_state_en @[ahb_to_axi4.scala 92:20] + node _T_40 = bits(io.axi.r.bits.resp, 1, 0) @[ahb_to_axi4.scala 93:61] + node _T_41 = orr(_T_40) @[ahb_to_axi4.scala 93:68] + node _T_42 = and(buf_state_en, _T_41) @[ahb_to_axi4.scala 93:41] + buf_read_error_in <= _T_42 @[ahb_to_axi4.scala 93:25] + skip @[Conditional.scala 39:67] + node _T_43 = bits(buf_state_en, 0, 0) @[ahb_to_axi4.scala 96:99] + reg _T_44 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_43 : @[Reg.scala 28:19] + _T_44 <= buf_nxtstate @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + buf_state <= _T_44 @[ahb_to_axi4.scala 96:31] + node _T_45 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 98:54] + node _T_46 = eq(_T_45, UInt<1>("h00")) @[ahb_to_axi4.scala 98:60] + node _T_47 = bits(_T_46, 0, 0) @[Bitwise.scala 72:15] + node _T_48 = mux(_T_47, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_49 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 98:92] + node _T_50 = dshl(UInt<1>("h01"), _T_49) @[ahb_to_axi4.scala 98:78] + node _T_51 = and(_T_48, _T_50) @[ahb_to_axi4.scala 98:70] + node _T_52 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 99:24] + node _T_53 = eq(_T_52, UInt<1>("h01")) @[ahb_to_axi4.scala 99:30] + node _T_54 = bits(_T_53, 0, 0) @[Bitwise.scala 72:15] + node _T_55 = mux(_T_54, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_56 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 99:62] + node _T_57 = dshl(UInt<2>("h03"), _T_56) @[ahb_to_axi4.scala 99:48] + node _T_58 = and(_T_55, _T_57) @[ahb_to_axi4.scala 99:40] + node _T_59 = or(_T_51, _T_58) @[ahb_to_axi4.scala 98:109] + node _T_60 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 100:24] + node _T_61 = eq(_T_60, UInt<2>("h02")) @[ahb_to_axi4.scala 100:30] + node _T_62 = bits(_T_61, 0, 0) @[Bitwise.scala 72:15] + node _T_63 = mux(_T_62, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_64 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 100:62] + node _T_65 = dshl(UInt<4>("h0f"), _T_64) @[ahb_to_axi4.scala 100:48] + node _T_66 = and(_T_63, _T_65) @[ahb_to_axi4.scala 100:40] + node _T_67 = or(_T_59, _T_66) @[ahb_to_axi4.scala 99:79] + node _T_68 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 101:24] + node _T_69 = eq(_T_68, UInt<2>("h03")) @[ahb_to_axi4.scala 101:30] + node _T_70 = bits(_T_69, 0, 0) @[Bitwise.scala 72:15] + node _T_71 = mux(_T_70, UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + node _T_72 = and(_T_71, UInt<8>("h0ff")) @[ahb_to_axi4.scala 101:40] + node _T_73 = or(_T_67, _T_72) @[ahb_to_axi4.scala 100:79] + master_wstrb <= _T_73 @[ahb_to_axi4.scala 98:31] + node _T_74 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 104:80] + node _T_75 = and(ahb_hresp_q, _T_74) @[ahb_to_axi4.scala 104:78] + node _T_76 = eq(cmdbuf_full, UInt<1>("h00")) @[ahb_to_axi4.scala 104:98] + node _T_77 = eq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 104:124] + node _T_78 = or(_T_76, _T_77) @[ahb_to_axi4.scala 104:111] + node _T_79 = eq(buf_state, UInt<2>("h02")) @[ahb_to_axi4.scala 104:149] + node _T_80 = eq(buf_state, UInt<2>("h03")) @[ahb_to_axi4.scala 104:168] + node _T_81 = or(_T_79, _T_80) @[ahb_to_axi4.scala 104:156] + node _T_82 = eq(_T_81, UInt<1>("h00")) @[ahb_to_axi4.scala 104:137] + node _T_83 = and(_T_78, _T_82) @[ahb_to_axi4.scala 104:135] + node _T_84 = eq(buf_read_error, UInt<1>("h00")) @[ahb_to_axi4.scala 104:181] + node _T_85 = and(_T_83, _T_84) @[ahb_to_axi4.scala 104:179] + node _T_86 = mux(io.ahb.sig.in.hresp, _T_75, _T_85) @[ahb_to_axi4.scala 104:44] + io.ahb.sig.in.hready <= _T_86 @[ahb_to_axi4.scala 104:38] + node _T_87 = and(io.ahb.sig.in.hready, io.ahb.hreadyin) @[ahb_to_axi4.scala 105:55] + ahb_hready <= _T_87 @[ahb_to_axi4.scala 105:31] + node _T_88 = bits(io.ahb.hsel, 0, 0) @[Bitwise.scala 72:15] + node _T_89 = mux(_T_88, UInt<2>("h03"), UInt<2>("h00")) @[Bitwise.scala 72:12] + node _T_90 = bits(io.ahb.sig.out.htrans, 1, 0) @[ahb_to_axi4.scala 106:77] + node _T_91 = and(_T_89, _T_90) @[ahb_to_axi4.scala 106:54] + ahb_htrans_in <= _T_91 @[ahb_to_axi4.scala 106:31] + node _T_92 = bits(buf_rdata, 63, 0) @[ahb_to_axi4.scala 107:50] + io.ahb.sig.in.hrdata <= _T_92 @[ahb_to_axi4.scala 107:38] + node _T_93 = bits(ahb_htrans_q, 1, 0) @[ahb_to_axi4.scala 108:55] + node _T_94 = neq(_T_93, UInt<1>("h00")) @[ahb_to_axi4.scala 108:61] + node _T_95 = neq(buf_state, UInt<2>("h00")) @[ahb_to_axi4.scala 108:83] + node _T_96 = and(_T_94, _T_95) @[ahb_to_axi4.scala 108:70] + node _T_97 = or(ahb_addr_in_dccm, ahb_addr_in_iccm) @[ahb_to_axi4.scala 109:26] + node _T_98 = eq(_T_97, UInt<1>("h00")) @[ahb_to_axi4.scala 109:7] + node _T_99 = and(ahb_addr_in_dccm, ahb_hwrite_q) @[ahb_to_axi4.scala 110:46] + node _T_100 = or(ahb_addr_in_iccm, _T_99) @[ahb_to_axi4.scala 110:26] + node _T_101 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:80] + node _T_102 = eq(_T_101, UInt<2>("h02")) @[ahb_to_axi4.scala 110:86] + node _T_103 = bits(ahb_hsize_q, 1, 0) @[ahb_to_axi4.scala 110:109] + node _T_104 = eq(_T_103, UInt<2>("h03")) @[ahb_to_axi4.scala 110:115] + node _T_105 = or(_T_102, _T_104) @[ahb_to_axi4.scala 110:95] + node _T_106 = eq(_T_105, UInt<1>("h00")) @[ahb_to_axi4.scala 110:66] + node _T_107 = and(_T_100, _T_106) @[ahb_to_axi4.scala 110:64] + node _T_108 = or(_T_98, _T_107) @[ahb_to_axi4.scala 109:47] + node _T_109 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 111:20] + node _T_110 = eq(_T_109, UInt<1>("h01")) @[ahb_to_axi4.scala 111:26] + node _T_111 = bits(ahb_haddr_q, 0, 0) @[ahb_to_axi4.scala 111:48] + node _T_112 = and(_T_110, _T_111) @[ahb_to_axi4.scala 111:35] + node _T_113 = or(_T_108, _T_112) @[ahb_to_axi4.scala 110:126] + node _T_114 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 112:20] + node _T_115 = eq(_T_114, UInt<2>("h02")) @[ahb_to_axi4.scala 112:26] + node _T_116 = bits(ahb_haddr_q, 1, 0) @[ahb_to_axi4.scala 112:49] + node _T_117 = orr(_T_116) @[ahb_to_axi4.scala 112:56] + node _T_118 = and(_T_115, _T_117) @[ahb_to_axi4.scala 112:35] + node _T_119 = or(_T_113, _T_118) @[ahb_to_axi4.scala 111:55] + node _T_120 = bits(ahb_hsize_q, 2, 0) @[ahb_to_axi4.scala 113:20] + node _T_121 = eq(_T_120, UInt<2>("h03")) @[ahb_to_axi4.scala 113:26] + node _T_122 = bits(ahb_haddr_q, 2, 0) @[ahb_to_axi4.scala 113:49] + node _T_123 = orr(_T_122) @[ahb_to_axi4.scala 113:56] + node _T_124 = and(_T_121, _T_123) @[ahb_to_axi4.scala 113:35] + node _T_125 = or(_T_119, _T_124) @[ahb_to_axi4.scala 112:61] + node _T_126 = and(_T_96, _T_125) @[ahb_to_axi4.scala 108:94] + node _T_127 = or(_T_126, buf_read_error) @[ahb_to_axi4.scala 113:63] + node _T_128 = eq(ahb_hready_q, UInt<1>("h00")) @[ahb_to_axi4.scala 115:20] + node _T_129 = and(ahb_hresp_q, _T_128) @[ahb_to_axi4.scala 115:18] + node _T_130 = or(_T_127, _T_129) @[ahb_to_axi4.scala 114:20] + io.ahb.sig.in.hresp <= _T_130 @[ahb_to_axi4.scala 108:38] + reg _T_131 : UInt, buf_rdata_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 118:66] + _T_131 <= io.axi.r.bits.data @[ahb_to_axi4.scala 118:66] + buf_rdata <= _T_131 @[ahb_to_axi4.scala 118:31] + reg _T_132 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 119:60] + _T_132 <= buf_read_error_in @[ahb_to_axi4.scala 119:60] + buf_read_error <= _T_132 @[ahb_to_axi4.scala 119:31] + reg _T_133 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 122:60] + _T_133 <= io.ahb.sig.in.hresp @[ahb_to_axi4.scala 122:60] + ahb_hresp_q <= _T_133 @[ahb_to_axi4.scala 122:31] + reg _T_134 : UInt<1>, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 123:60] + _T_134 <= ahb_hready @[ahb_to_axi4.scala 123:60] + ahb_hready_q <= _T_134 @[ahb_to_axi4.scala 123:31] + reg _T_135 : UInt, ahb_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 124:60] + _T_135 <= ahb_htrans_in @[ahb_to_axi4.scala 124:60] + ahb_htrans_q <= _T_135 @[ahb_to_axi4.scala 124:31] + reg _T_136 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 125:65] + _T_136 <= io.ahb.sig.out.hsize @[ahb_to_axi4.scala 125:65] + ahb_hsize_q <= _T_136 @[ahb_to_axi4.scala 125:31] + reg _T_137 : UInt<1>, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 126:65] + _T_137 <= io.ahb.sig.out.hwrite @[ahb_to_axi4.scala 126:65] + ahb_hwrite_q <= _T_137 @[ahb_to_axi4.scala 126:31] + reg _T_138 : UInt, ahb_addr_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 127:65] + _T_138 <= io.ahb.sig.out.haddr @[ahb_to_axi4.scala 127:65] + ahb_haddr_q <= _T_138 @[ahb_to_axi4.scala 127:31] + node _T_139 = bits(io.ahb.sig.out.htrans, 1, 1) @[ahb_to_axi4.scala 130:85] + node _T_140 = and(ahb_hready, _T_139) @[ahb_to_axi4.scala 130:62] + node _T_141 = and(io.bus_clk_en, _T_140) @[ahb_to_axi4.scala 130:48] + ahb_bus_addr_clk_en <= _T_141 @[ahb_to_axi4.scala 130:31] + node _T_142 = and(io.bus_clk_en, buf_rdata_en) @[ahb_to_axi4.scala 131:48] + buf_rdata_clk_en <= _T_142 @[ahb_to_axi4.scala 131:31] + inst rvclkhdr of rvclkhdr_879 @[lib.scala 343:22] + rvclkhdr.clock <= clock + rvclkhdr.reset <= reset + rvclkhdr.io.clk <= clock @[lib.scala 344:17] + rvclkhdr.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_clk <= rvclkhdr.io.l1clk @[ahb_to_axi4.scala 133:31] + inst rvclkhdr_1 of rvclkhdr_880 @[lib.scala 343:22] + rvclkhdr_1.clock <= clock + rvclkhdr_1.reset <= reset + rvclkhdr_1.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_1.io.en <= ahb_bus_addr_clk_en @[lib.scala 345:16] + rvclkhdr_1.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + ahb_addr_clk <= rvclkhdr_1.io.l1clk @[ahb_to_axi4.scala 134:31] + inst rvclkhdr_2 of rvclkhdr_881 @[lib.scala 343:22] + rvclkhdr_2.clock <= clock + rvclkhdr_2.reset <= reset + rvclkhdr_2.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_2.io.en <= buf_rdata_clk_en @[lib.scala 345:16] + rvclkhdr_2.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + buf_rdata_clk <= rvclkhdr_2.io.l1clk @[ahb_to_axi4.scala 135:31] + node _T_143 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 137:53] + node _T_144 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 137:91] + node _T_145 = or(_T_143, _T_144) @[ahb_to_axi4.scala 137:72] + node _T_146 = eq(cmdbuf_wr_en, UInt<1>("h00")) @[ahb_to_axi4.scala 137:113] + node _T_147 = and(_T_145, _T_146) @[ahb_to_axi4.scala 137:111] + node _T_148 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 137:153] + node _T_149 = and(io.ahb.sig.in.hresp, _T_148) @[ahb_to_axi4.scala 137:151] + node _T_150 = or(_T_147, _T_149) @[ahb_to_axi4.scala 137:128] + cmdbuf_rst <= _T_150 @[ahb_to_axi4.scala 137:31] + node _T_151 = and(io.axi.aw.valid, io.axi.aw.ready) @[ahb_to_axi4.scala 138:67] + node _T_152 = and(io.axi.ar.valid, io.axi.ar.ready) @[ahb_to_axi4.scala 138:105] + node _T_153 = or(_T_151, _T_152) @[ahb_to_axi4.scala 138:86] + node _T_154 = eq(_T_153, UInt<1>("h00")) @[ahb_to_axi4.scala 138:48] + node _T_155 = and(cmdbuf_vld, _T_154) @[ahb_to_axi4.scala 138:46] + cmdbuf_full <= _T_155 @[ahb_to_axi4.scala 138:31] + node _T_156 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 140:86] + node _T_157 = mux(_T_156, UInt<1>("h01"), cmdbuf_vld) @[ahb_to_axi4.scala 140:66] + node _T_158 = eq(cmdbuf_rst, UInt<1>("h00")) @[ahb_to_axi4.scala 140:110] + node _T_159 = and(_T_157, _T_158) @[ahb_to_axi4.scala 140:108] + reg _T_160 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[ahb_to_axi4.scala 140:61] + _T_160 <= _T_159 @[ahb_to_axi4.scala 140:61] + cmdbuf_vld <= _T_160 @[ahb_to_axi4.scala 140:31] + node _T_161 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 144:53] + reg _T_162 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_161 : @[Reg.scala 28:19] + _T_162 <= ahb_hwrite_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_write <= _T_162 @[ahb_to_axi4.scala 143:31] + node _T_163 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 147:52] + reg _T_164 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_163 : @[Reg.scala 28:19] + _T_164 <= ahb_hsize_q @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_size <= _T_164 @[ahb_to_axi4.scala 146:31] + node _T_165 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 150:53] + reg _T_166 : UInt, bus_clk with : (reset => (reset, UInt<1>("h00"))) @[Reg.scala 27:20] + when _T_165 : @[Reg.scala 28:19] + _T_166 <= master_wstrb @[Reg.scala 28:23] + skip @[Reg.scala 28:19] + cmdbuf_wstrb <= _T_166 @[ahb_to_axi4.scala 149:31] + node _T_167 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 153:57] + inst rvclkhdr_3 of rvclkhdr_882 @[lib.scala 368:23] + rvclkhdr_3.clock <= clock + rvclkhdr_3.reset <= reset + rvclkhdr_3.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_3.io.en <= _T_167 @[lib.scala 371:17] + rvclkhdr_3.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_168 : UInt, rvclkhdr_3.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_168 <= ahb_haddr_q @[lib.scala 374:16] + cmdbuf_addr <= _T_168 @[ahb_to_axi4.scala 153:15] + node _T_169 = bits(cmdbuf_wr_en, 0, 0) @[ahb_to_axi4.scala 154:68] + inst rvclkhdr_4 of rvclkhdr_883 @[lib.scala 368:23] + rvclkhdr_4.clock <= clock + rvclkhdr_4.reset <= reset + rvclkhdr_4.io.clk <= bus_clk @[lib.scala 370:18] + rvclkhdr_4.io.en <= _T_169 @[lib.scala 371:17] + rvclkhdr_4.io.scan_mode <= io.scan_mode @[lib.scala 372:24] + reg _T_170 : UInt, rvclkhdr_4.io.l1clk with : (reset => (reset, UInt<1>("h00"))) @[lib.scala 374:16] + _T_170 <= io.ahb.sig.out.hwdata @[lib.scala 374:16] + cmdbuf_wdata <= _T_170 @[ahb_to_axi4.scala 154:16] + node _T_171 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 157:42] + io.axi.aw.valid <= _T_171 @[ahb_to_axi4.scala 157:28] + io.axi.aw.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 158:33] + io.axi.aw.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 159:33] + node _T_172 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 160:59] + node _T_173 = cat(UInt<1>("h00"), _T_172) @[Cat.scala 29:58] + io.axi.aw.bits.size <= _T_173 @[ahb_to_axi4.scala 160:33] + node _T_174 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.prot <= _T_174 @[ahb_to_axi4.scala 161:33] + node _T_175 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.aw.bits.len <= _T_175 @[ahb_to_axi4.scala 162:33] + io.axi.aw.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 163:33] + node _T_176 = and(cmdbuf_vld, cmdbuf_write) @[ahb_to_axi4.scala 165:42] + io.axi.w.valid <= _T_176 @[ahb_to_axi4.scala 165:28] + io.axi.w.bits.data <= cmdbuf_wdata @[ahb_to_axi4.scala 166:33] + io.axi.w.bits.strb <= cmdbuf_wstrb @[ahb_to_axi4.scala 167:33] + io.axi.w.bits.last <= UInt<1>("h01") @[ahb_to_axi4.scala 168:33] + io.axi.b.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 170:28] + node _T_177 = eq(cmdbuf_write, UInt<1>("h00")) @[ahb_to_axi4.scala 172:44] + node _T_178 = and(cmdbuf_vld, _T_177) @[ahb_to_axi4.scala 172:42] + io.axi.ar.valid <= _T_178 @[ahb_to_axi4.scala 172:28] + io.axi.ar.bits.id <= UInt<1>("h00") @[ahb_to_axi4.scala 173:33] + io.axi.ar.bits.addr <= cmdbuf_addr @[ahb_to_axi4.scala 174:33] + node _T_179 = bits(cmdbuf_size, 1, 0) @[ahb_to_axi4.scala 175:59] + node _T_180 = cat(UInt<1>("h00"), _T_179) @[Cat.scala 29:58] + io.axi.ar.bits.size <= _T_180 @[ahb_to_axi4.scala 175:33] + node _T_181 = mux(UInt<1>("h00"), UInt<3>("h07"), UInt<3>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.prot <= _T_181 @[ahb_to_axi4.scala 176:33] + node _T_182 = mux(UInt<1>("h00"), UInt<8>("h0ff"), UInt<8>("h00")) @[Bitwise.scala 72:12] + io.axi.ar.bits.len <= _T_182 @[ahb_to_axi4.scala 177:33] + io.axi.ar.bits.burst <= UInt<1>("h01") @[ahb_to_axi4.scala 178:33] + io.axi.r.ready <= UInt<1>("h01") @[ahb_to_axi4.scala 180:28] + inst rvclkhdr_5 of rvclkhdr_884 @[lib.scala 343:22] + rvclkhdr_5.clock <= clock + rvclkhdr_5.reset <= reset + rvclkhdr_5.io.clk <= clock @[lib.scala 344:17] + rvclkhdr_5.io.en <= io.bus_clk_en @[lib.scala 345:16] + rvclkhdr_5.io.scan_mode <= io.scan_mode @[lib.scala 346:23] + bus_clk <= rvclkhdr_5.io.l1clk @[ahb_to_axi4.scala 181:27] + module quasar : input clock : Clock input reset : AsyncReset - output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, lsu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma : {flip ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} + output io : {lsu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, ifu_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<3>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<3>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, sb_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, flip dma_axi : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}}, lsu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, ifu_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, sb_ahb : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, dma_ahb : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>}, flip dbg_rst_l : AsyncReset, flip rst_vec : UInt<31>, flip nmi_int : UInt<1>, flip nmi_vec : UInt<31>, core_rst_l : AsyncReset, rv_trace_pkt : {rv_i_valid_ip : UInt<2>, rv_i_insn_ip : UInt<32>, rv_i_address_ip : UInt<32>, rv_i_exception_ip : UInt<2>, rv_i_ecause_ip : UInt<5>, rv_i_interrupt_ip : UInt<2>, rv_i_tval_ip : UInt<32>}, dccm_clk_override : UInt<1>, icm_clk_override : UInt<1>, dec_tlu_core_ecc_disable : UInt<1>, flip i_cpu_halt_req : UInt<1>, flip i_cpu_run_req : UInt<1>, o_cpu_halt_ack : UInt<1>, o_cpu_halt_status : UInt<1>, o_cpu_run_ack : UInt<1>, o_debug_mode_status : UInt<1>, flip core_id : UInt<28>, flip mpc_debug_halt_req : UInt<1>, flip mpc_debug_run_req : UInt<1>, flip mpc_reset_run_req : UInt<1>, mpc_debug_halt_ack : UInt<1>, mpc_debug_run_ack : UInt<1>, debug_brkpt_status : UInt<1>, dec_tlu_perfcnt0 : UInt<1>, dec_tlu_perfcnt1 : UInt<1>, dec_tlu_perfcnt2 : UInt<1>, dec_tlu_perfcnt3 : UInt<1>, flip dccm : {flip wren : UInt<1>, flip rden : UInt<1>, flip wr_addr_lo : UInt<16>, flip wr_addr_hi : UInt<16>, flip rd_addr_lo : UInt<16>, flip rd_addr_hi : UInt<16>, flip wr_data_lo : UInt<39>, flip wr_data_hi : UInt<39>, rd_data_lo : UInt<39>, rd_data_hi : UInt<39>}, ic : {rw_addr : UInt<31>, tag_valid : UInt<2>, wr_en : UInt<2>, rd_en : UInt<1>, wr_data : UInt<71>[2], debug_wr_data : UInt<71>, debug_addr : UInt<10>, flip rd_data : UInt<64>, flip debug_rd_data : UInt<71>, flip tag_debug_rd_data : UInt<26>, flip eccerr : UInt<2>, flip parerr : UInt<2>, flip rd_hit : UInt<2>, flip tag_perr : UInt<1>, debug_rd_en : UInt<1>, debug_wr_en : UInt<1>, debug_tag_array : UInt<1>, debug_way : UInt<2>, premux_data : UInt<64>, sel_premux_data : UInt<1>}, iccm : {rw_addr : UInt<15>, buf_correct_ecc : UInt<1>, correction_state : UInt<1>, wren : UInt<1>, rden : UInt<1>, wr_size : UInt<3>, wr_data : UInt<78>, flip rd_data : UInt<64>, flip rd_data_ecc : UInt<78>}, flip lsu_bus_clk_en : UInt<1>, flip ifu_bus_clk_en : UInt<1>, flip dbg_bus_clk_en : UInt<1>, flip dma_bus_clk_en : UInt<1>, flip dmi_reg_en : UInt<1>, flip dmi_reg_addr : UInt<7>, flip dmi_reg_wr_en : UInt<1>, flip dmi_reg_wdata : UInt<32>, dmi_reg_rdata : UInt<32>, flip dmi_hard_reset : UInt<1>, flip extintsrc_req : UInt<31>, flip timer_int : UInt<1>, flip soft_int : UInt<1>, flip scan_mode : UInt<1>} inst ifu of ifu @[quasar.scala 72:19] ifu.clock <= clock @@ -109487,294 +114312,878 @@ circuit quasar_wrapper : dbg.io.dmi_reg_addr <= io.dmi_reg_addr @[quasar.scala 186:23] dbg.io.dmi_reg_wr_en <= io.dmi_reg_wr_en @[quasar.scala 187:24] dbg.io.dmi_reg_wdata <= io.dmi_reg_wdata @[quasar.scala 188:24] - dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 189:17] - dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 189:17] - dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 189:17] - dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 189:17] - dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 189:17] - io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 189:17] - io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 189:17] - io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 189:17] - io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 189:17] - io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 189:17] - io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 189:17] - io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 189:17] - io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 189:17] - io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 189:17] - io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 189:17] - io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 189:17] - io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 189:17] - dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 189:17] - dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 189:17] - dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 189:17] - dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 189:17] - io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 189:17] - io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 189:17] - io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 189:17] - io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 189:17] - io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 189:17] - dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 189:17] - io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 189:17] - io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 189:17] - io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 189:17] - io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 189:17] - io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 189:17] - io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 189:17] - io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 189:17] - io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 189:17] - io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 189:17] - io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 189:17] - io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 189:17] - dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 189:17] - dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 190:25] - node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 191:42] - dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 191:20] - dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 192:23] - dbg.io.scan_mode <= io.scan_mode @[quasar.scala 193:20] - dma_ctrl.reset <= io.core_rst_l @[quasar.scala 197:18] - dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 198:24] - dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 199:30] - dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 200:28] - dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 201:25] - dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 202:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 202:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 202:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 202:23] - dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 202:23] - dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 203:26] - dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 203:26] - dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 204:28] - dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 205:31] - dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 206:29] - dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 207:30] - dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 208:26] - dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 209:34] - pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 212:30] - pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 213:23] - pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 214:29] - pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 215:31] - pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 216:33] - pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 217:34] - lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 218:28] - pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 218:28] - dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 219:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 219:28] - pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 219:28] - dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 219:28] - dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 219:28] - dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 219:28] - io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 221:19] - io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 221:19] - io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 224:24] - io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 225:23] - io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 226:31] - io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 227:21] - io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 228:24] - io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 229:20] - io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 230:26] - io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 231:25] - io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 232:24] - io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 233:25] - io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 234:23] - io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 235:23] - io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 236:23] - io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 237:23] - lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 239:11] - lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 239:11] - io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 239:11] - io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 239:11] - io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 239:11] - io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 239:11] - io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 239:11] - io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 239:11] - io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 239:11] - io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 239:11] - lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 242:14] - lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 242:14] - lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 242:14] - lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 242:14] - lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 242:14] - io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 242:14] - io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 242:14] - io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 242:14] - io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 242:14] - io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 242:14] - io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 242:14] - io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 242:14] - io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 242:14] - io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 242:14] - io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 242:14] - io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 242:14] - io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 242:14] - lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 242:14] - lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 242:14] - lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 242:14] - lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 242:14] - io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 242:14] - io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 242:14] - io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 242:14] - io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 242:14] - io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 242:14] - lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 242:14] - io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 242:14] - io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 242:14] - io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 242:14] - io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 242:14] - io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 242:14] - io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 242:14] - io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 242:14] - io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 242:14] - io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 242:14] - io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 242:14] - io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 242:14] - lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 242:14] - ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 245:14] - ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 245:14] - ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 245:14] - ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 245:14] - ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 245:14] - io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 245:14] - io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 245:14] - io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 245:14] - io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 245:14] - io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 245:14] - io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 245:14] - io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 245:14] - io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 245:14] - io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 245:14] - io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 245:14] - io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 245:14] - io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 245:14] - ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 245:14] - ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 245:14] - ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 245:14] - ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 245:14] - io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 245:14] - io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 245:14] - io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 245:14] - io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 245:14] - io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 245:14] - ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 245:14] - io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 245:14] - io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 245:14] - io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 245:14] - io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 245:14] - io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 245:14] - io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 245:14] - io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 245:14] - io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 245:14] - io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 245:14] - io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 245:14] - io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 245:14] - ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 245:14] - io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 246:14] - io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 246:14] - io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 246:14] - io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 246:14] - io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 246:14] - io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 246:14] - io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 246:14] - io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 246:14] - io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 246:14] - io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 246:14] - dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 246:14] - io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 246:14] - wire _T_12 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 424:29] - _T_12.hwdata <= UInt<64>("h00") @[quasar.scala 424:29] - _T_12.hwrite <= UInt<1>("h00") @[quasar.scala 424:29] - _T_12.htrans <= UInt<2>("h00") @[quasar.scala 424:29] - _T_12.hsize <= UInt<3>("h00") @[quasar.scala 424:29] - _T_12.hprot <= UInt<4>("h00") @[quasar.scala 424:29] - _T_12.hmastlock <= UInt<1>("h00") @[quasar.scala 424:29] - _T_12.hburst <= UInt<3>("h00") @[quasar.scala 424:29] - _T_12.haddr <= UInt<32>("h00") @[quasar.scala 424:29] - io.ahb.out.hwdata <= _T_12.hwdata @[quasar.scala 424:14] - io.ahb.out.hwrite <= _T_12.hwrite @[quasar.scala 424:14] - io.ahb.out.htrans <= _T_12.htrans @[quasar.scala 424:14] - io.ahb.out.hsize <= _T_12.hsize @[quasar.scala 424:14] - io.ahb.out.hprot <= _T_12.hprot @[quasar.scala 424:14] - io.ahb.out.hmastlock <= _T_12.hmastlock @[quasar.scala 424:14] - io.ahb.out.hburst <= _T_12.hburst @[quasar.scala 424:14] - io.ahb.out.haddr <= _T_12.haddr @[quasar.scala 424:14] - wire _T_13 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 425:33] - _T_13.hwdata <= UInt<64>("h00") @[quasar.scala 425:33] - _T_13.hwrite <= UInt<1>("h00") @[quasar.scala 425:33] - _T_13.htrans <= UInt<2>("h00") @[quasar.scala 425:33] - _T_13.hsize <= UInt<3>("h00") @[quasar.scala 425:33] - _T_13.hprot <= UInt<4>("h00") @[quasar.scala 425:33] - _T_13.hmastlock <= UInt<1>("h00") @[quasar.scala 425:33] - _T_13.hburst <= UInt<3>("h00") @[quasar.scala 425:33] - _T_13.haddr <= UInt<32>("h00") @[quasar.scala 425:33] - io.lsu_ahb.out.hwdata <= _T_13.hwdata @[quasar.scala 425:18] - io.lsu_ahb.out.hwrite <= _T_13.hwrite @[quasar.scala 425:18] - io.lsu_ahb.out.htrans <= _T_13.htrans @[quasar.scala 425:18] - io.lsu_ahb.out.hsize <= _T_13.hsize @[quasar.scala 425:18] - io.lsu_ahb.out.hprot <= _T_13.hprot @[quasar.scala 425:18] - io.lsu_ahb.out.hmastlock <= _T_13.hmastlock @[quasar.scala 425:18] - io.lsu_ahb.out.hburst <= _T_13.hburst @[quasar.scala 425:18] - io.lsu_ahb.out.haddr <= _T_13.haddr @[quasar.scala 425:18] - wire _T_14 : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>} @[quasar.scala 426:32] - _T_14.hwdata <= UInt<64>("h00") @[quasar.scala 426:32] - _T_14.hwrite <= UInt<1>("h00") @[quasar.scala 426:32] - _T_14.htrans <= UInt<2>("h00") @[quasar.scala 426:32] - _T_14.hsize <= UInt<3>("h00") @[quasar.scala 426:32] - _T_14.hprot <= UInt<4>("h00") @[quasar.scala 426:32] - _T_14.hmastlock <= UInt<1>("h00") @[quasar.scala 426:32] - _T_14.hburst <= UInt<3>("h00") @[quasar.scala 426:32] - _T_14.haddr <= UInt<32>("h00") @[quasar.scala 426:32] - io.sb_ahb.out.hwdata <= _T_14.hwdata @[quasar.scala 426:17] - io.sb_ahb.out.hwrite <= _T_14.hwrite @[quasar.scala 426:17] - io.sb_ahb.out.htrans <= _T_14.htrans @[quasar.scala 426:17] - io.sb_ahb.out.hsize <= _T_14.hsize @[quasar.scala 426:17] - io.sb_ahb.out.hprot <= _T_14.hprot @[quasar.scala 426:17] - io.sb_ahb.out.hmastlock <= _T_14.hmastlock @[quasar.scala 426:17] - io.sb_ahb.out.hburst <= _T_14.hburst @[quasar.scala 426:17] - io.sb_ahb.out.haddr <= _T_14.haddr @[quasar.scala 426:17] - wire _T_15 : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>} @[quasar.scala 427:32] - _T_15.hresp <= UInt<1>("h00") @[quasar.scala 427:32] - _T_15.hready <= UInt<1>("h00") @[quasar.scala 427:32] - _T_15.hrdata <= UInt<64>("h00") @[quasar.scala 427:32] - io.dma.ahb.in.hresp <= _T_15.hresp @[quasar.scala 427:17] - io.dma.ahb.in.hready <= _T_15.hready @[quasar.scala 427:17] - io.dma.ahb.in.hrdata <= _T_15.hrdata @[quasar.scala 427:17] - io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 428:20] + dbg.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 189:25] + node _T_11 = asUInt(io.dbg_rst_l) @[quasar.scala 190:42] + dbg.io.dbg_rst_l <= _T_11 @[quasar.scala 190:20] + dbg.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 191:23] + dbg.io.scan_mode <= io.scan_mode @[quasar.scala 192:20] + dma_ctrl.reset <= io.core_rst_l @[quasar.scala 196:18] + dma_ctrl.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 197:24] + dma_ctrl.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 198:30] + dma_ctrl.io.clk_override <= dec.io.dec_tlu_misc_clk_override @[quasar.scala 199:28] + dma_ctrl.io.scan_mode <= io.scan_mode @[quasar.scala 200:25] + dma_ctrl.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata <= dbg.io.dbg_dma.dbg_dctl.dbg_cmd_wrdata @[quasar.scala 201:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_addr <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_addr @[quasar.scala 201:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_type <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_type @[quasar.scala 201:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_write <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_write @[quasar.scala 201:23] + dma_ctrl.io.dbg_dma.dbg_ib.dbg_cmd_valid <= dbg.io.dbg_dma.dbg_ib.dbg_cmd_valid @[quasar.scala 201:23] + dbg.io.dbg_dma_io.dma_dbg_ready <= dma_ctrl.io.dbg_dma_io.dma_dbg_ready @[quasar.scala 202:26] + dma_ctrl.io.dbg_dma_io.dbg_dma_bubble <= dbg.io.dbg_dma_io.dbg_dma_bubble @[quasar.scala 202:26] + dma_ctrl.io.dbg_cmd_size <= dbg.io.dbg_cmd_size @[quasar.scala 203:28] + dma_ctrl.io.iccm_dma_rvalid <= ifu.io.iccm_dma_rvalid @[quasar.scala 204:31] + dma_ctrl.io.iccm_dma_rtag <= ifu.io.iccm_dma_rtag @[quasar.scala 205:29] + dma_ctrl.io.iccm_dma_rdata <= ifu.io.iccm_dma_rdata @[quasar.scala 206:30] + dma_ctrl.io.iccm_ready <= ifu.io.iccm_ready @[quasar.scala 207:26] + dma_ctrl.io.iccm_dma_ecc_error <= ifu.io.iccm_dma_ecc_error @[quasar.scala 208:34] + pic_ctrl_inst.io.scan_mode <= io.scan_mode @[quasar.scala 211:30] + pic_ctrl_inst.reset <= io.core_rst_l @[quasar.scala 212:23] + pic_ctrl_inst.io.free_clk <= rvclkhdr.io.l1clk @[quasar.scala 213:29] + pic_ctrl_inst.io.active_clk <= rvclkhdr_1.io.l1clk @[quasar.scala 214:31] + pic_ctrl_inst.io.clk_override <= dec.io.dec_tlu_pic_clk_override @[quasar.scala 215:33] + pic_ctrl_inst.io.extintsrc_req <= io.extintsrc_req @[quasar.scala 216:34] + lsu.io.lsu_pic.picm_rd_data <= pic_ctrl_inst.io.lsu_pic.picm_rd_data @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_wr_data <= lsu.io.lsu_pic.picm_wr_data @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_wraddr <= lsu.io.lsu_pic.picm_wraddr @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_rdaddr <= lsu.io.lsu_pic.picm_rdaddr @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_mken <= lsu.io.lsu_pic.picm_mken @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_rden <= lsu.io.lsu_pic.picm_rden @[quasar.scala 217:28] + pic_ctrl_inst.io.lsu_pic.picm_wren <= lsu.io.lsu_pic.picm_wren @[quasar.scala 217:28] + dec.io.dec_pic.mexintpend <= pic_ctrl_inst.io.dec_pic.mexintpend @[quasar.scala 218:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meipt <= dec.io.dec_pic.dec_tlu_meipt @[quasar.scala 218:28] + pic_ctrl_inst.io.dec_pic.dec_tlu_meicurpl <= dec.io.dec_pic.dec_tlu_meicurpl @[quasar.scala 218:28] + dec.io.dec_pic.mhwakeup <= pic_ctrl_inst.io.dec_pic.mhwakeup @[quasar.scala 218:28] + dec.io.dec_pic.pic_pl <= pic_ctrl_inst.io.dec_pic.pic_pl @[quasar.scala 218:28] + dec.io.dec_pic.pic_claimid <= pic_ctrl_inst.io.dec_pic.pic_claimid @[quasar.scala 218:28] + io.rv_trace_pkt.rv_i_tval_ip <= dec.io.rv_trace_pkt.rv_i_tval_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= dec.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_ecause_ip <= dec.io.rv_trace_pkt.rv_i_ecause_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_exception_ip <= dec.io.rv_trace_pkt.rv_i_exception_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_address_ip <= dec.io.rv_trace_pkt.rv_i_address_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_insn_ip <= dec.io.rv_trace_pkt.rv_i_insn_ip @[quasar.scala 220:19] + io.rv_trace_pkt.rv_i_valid_ip <= dec.io.rv_trace_pkt.rv_i_valid_ip @[quasar.scala 220:19] + io.dccm_clk_override <= dec.io.dec_tlu_dccm_clk_override @[quasar.scala 223:24] + io.icm_clk_override <= dec.io.dec_tlu_icm_clk_override @[quasar.scala 224:23] + io.dec_tlu_core_ecc_disable <= dec.io.ifu_dec.dec_mem_ctrl.dec_tlu_core_ecc_disable @[quasar.scala 225:31] + io.o_cpu_halt_ack <= dec.io.o_cpu_halt_ack @[quasar.scala 226:21] + io.o_cpu_halt_status <= dec.io.o_cpu_halt_status @[quasar.scala 227:24] + io.o_cpu_run_ack <= dec.io.o_cpu_run_ack @[quasar.scala 228:20] + io.o_debug_mode_status <= dec.io.o_debug_mode_status @[quasar.scala 229:26] + io.mpc_debug_halt_ack <= dec.io.mpc_debug_halt_ack @[quasar.scala 230:25] + io.mpc_debug_run_ack <= dec.io.mpc_debug_run_ack @[quasar.scala 231:24] + io.debug_brkpt_status <= dec.io.debug_brkpt_status @[quasar.scala 232:25] + io.dec_tlu_perfcnt0 <= dec.io.dec_tlu_perfcnt0 @[quasar.scala 233:23] + io.dec_tlu_perfcnt1 <= dec.io.dec_tlu_perfcnt1 @[quasar.scala 234:23] + io.dec_tlu_perfcnt2 <= dec.io.dec_tlu_perfcnt2 @[quasar.scala 235:23] + io.dec_tlu_perfcnt3 <= dec.io.dec_tlu_perfcnt3 @[quasar.scala 236:23] + lsu.io.dccm.rd_data_hi <= io.dccm.rd_data_hi @[quasar.scala 238:11] + lsu.io.dccm.rd_data_lo <= io.dccm.rd_data_lo @[quasar.scala 238:11] + io.dccm.wr_data_hi <= lsu.io.dccm.wr_data_hi @[quasar.scala 238:11] + io.dccm.wr_data_lo <= lsu.io.dccm.wr_data_lo @[quasar.scala 238:11] + io.dccm.rd_addr_hi <= lsu.io.dccm.rd_addr_hi @[quasar.scala 238:11] + io.dccm.rd_addr_lo <= lsu.io.dccm.rd_addr_lo @[quasar.scala 238:11] + io.dccm.wr_addr_hi <= lsu.io.dccm.wr_addr_hi @[quasar.scala 238:11] + io.dccm.wr_addr_lo <= lsu.io.dccm.wr_addr_lo @[quasar.scala 238:11] + io.dccm.rden <= lsu.io.dccm.rden @[quasar.scala 238:11] + io.dccm.wren <= lsu.io.dccm.wren @[quasar.scala 238:11] + when UInt<1>("h00") : @[quasar.scala 241:26] + inst axi4_to_ahb of axi4_to_ahb @[quasar.scala 242:32] + axi4_to_ahb.clock <= clock + axi4_to_ahb.reset <= reset + inst axi4_to_ahb_1 of axi4_to_ahb_1 @[quasar.scala 243:33] + axi4_to_ahb_1.clock <= clock + axi4_to_ahb_1.reset <= reset + inst axi4_to_ahb_2 of axi4_to_ahb_2 @[quasar.scala 244:33] + axi4_to_ahb_2.clock <= clock + axi4_to_ahb_2.reset <= reset + inst ahb_to_axi4 of ahb_to_axi4 @[quasar.scala 245:33] + ahb_to_axi4.clock <= clock + ahb_to_axi4.reset <= reset + axi4_to_ahb_2.io.scan_mode <= io.scan_mode @[quasar.scala 247:34] + axi4_to_ahb_2.io.bus_clk_en <= io.lsu_bus_clk_en @[quasar.scala 248:35] + axi4_to_ahb_2.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 249:37] + lsu.io.axi.r.bits.last <= axi4_to_ahb_2.io.axi.r.bits.last @[quasar.scala 250:28] + lsu.io.axi.r.bits.resp <= axi4_to_ahb_2.io.axi.r.bits.resp @[quasar.scala 250:28] + lsu.io.axi.r.bits.data <= axi4_to_ahb_2.io.axi.r.bits.data @[quasar.scala 250:28] + lsu.io.axi.r.bits.id <= axi4_to_ahb_2.io.axi.r.bits.id @[quasar.scala 250:28] + lsu.io.axi.r.valid <= axi4_to_ahb_2.io.axi.r.valid @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 250:28] + lsu.io.axi.ar.ready <= axi4_to_ahb_2.io.axi.ar.ready @[quasar.scala 250:28] + lsu.io.axi.b.bits.id <= axi4_to_ahb_2.io.axi.b.bits.id @[quasar.scala 250:28] + lsu.io.axi.b.bits.resp <= axi4_to_ahb_2.io.axi.b.bits.resp @[quasar.scala 250:28] + lsu.io.axi.b.valid <= axi4_to_ahb_2.io.axi.b.valid @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 250:28] + lsu.io.axi.w.ready <= axi4_to_ahb_2.io.axi.w.ready @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 250:28] + axi4_to_ahb_2.io.axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 250:28] + lsu.io.axi.aw.ready <= axi4_to_ahb_2.io.axi.aw.ready @[quasar.scala 250:28] + io.lsu_ahb.out.hwdata <= axi4_to_ahb_2.io.ahb.out.hwdata @[quasar.scala 251:28] + io.lsu_ahb.out.hwrite <= axi4_to_ahb_2.io.ahb.out.hwrite @[quasar.scala 251:28] + io.lsu_ahb.out.htrans <= axi4_to_ahb_2.io.ahb.out.htrans @[quasar.scala 251:28] + io.lsu_ahb.out.hsize <= axi4_to_ahb_2.io.ahb.out.hsize @[quasar.scala 251:28] + io.lsu_ahb.out.hprot <= axi4_to_ahb_2.io.ahb.out.hprot @[quasar.scala 251:28] + io.lsu_ahb.out.hmastlock <= axi4_to_ahb_2.io.ahb.out.hmastlock @[quasar.scala 251:28] + io.lsu_ahb.out.hburst <= axi4_to_ahb_2.io.ahb.out.hburst @[quasar.scala 251:28] + io.lsu_ahb.out.haddr <= axi4_to_ahb_2.io.ahb.out.haddr @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 251:28] + axi4_to_ahb_2.io.ahb.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 251:28] + axi4_to_ahb_1.io.scan_mode <= io.scan_mode @[quasar.scala 254:34] + axi4_to_ahb_1.io.bus_clk_en <= io.ifu_bus_clk_en @[quasar.scala 255:35] + axi4_to_ahb_1.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 256:37] + ifu.io.ifu.r.bits.last <= axi4_to_ahb_1.io.axi.r.bits.last @[quasar.scala 257:28] + ifu.io.ifu.r.bits.resp <= axi4_to_ahb_1.io.axi.r.bits.resp @[quasar.scala 257:28] + ifu.io.ifu.r.bits.data <= axi4_to_ahb_1.io.axi.r.bits.data @[quasar.scala 257:28] + ifu.io.ifu.r.bits.id <= axi4_to_ahb_1.io.axi.r.bits.id @[quasar.scala 257:28] + ifu.io.ifu.r.valid <= axi4_to_ahb_1.io.axi.r.valid @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 257:28] + ifu.io.ifu.ar.ready <= axi4_to_ahb_1.io.axi.ar.ready @[quasar.scala 257:28] + ifu.io.ifu.b.bits.id <= axi4_to_ahb_1.io.axi.b.bits.id @[quasar.scala 257:28] + ifu.io.ifu.b.bits.resp <= axi4_to_ahb_1.io.axi.b.bits.resp @[quasar.scala 257:28] + ifu.io.ifu.b.valid <= axi4_to_ahb_1.io.axi.b.valid @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 257:28] + ifu.io.ifu.w.ready <= axi4_to_ahb_1.io.axi.w.ready @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 257:28] + axi4_to_ahb_1.io.axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 257:28] + ifu.io.ifu.aw.ready <= axi4_to_ahb_1.io.axi.aw.ready @[quasar.scala 257:28] + io.ifu_ahb.out.hwdata <= axi4_to_ahb_1.io.ahb.out.hwdata @[quasar.scala 258:28] + io.ifu_ahb.out.hwrite <= axi4_to_ahb_1.io.ahb.out.hwrite @[quasar.scala 258:28] + io.ifu_ahb.out.htrans <= axi4_to_ahb_1.io.ahb.out.htrans @[quasar.scala 258:28] + io.ifu_ahb.out.hsize <= axi4_to_ahb_1.io.ahb.out.hsize @[quasar.scala 258:28] + io.ifu_ahb.out.hprot <= axi4_to_ahb_1.io.ahb.out.hprot @[quasar.scala 258:28] + io.ifu_ahb.out.hmastlock <= axi4_to_ahb_1.io.ahb.out.hmastlock @[quasar.scala 258:28] + io.ifu_ahb.out.hburst <= axi4_to_ahb_1.io.ahb.out.hburst @[quasar.scala 258:28] + io.ifu_ahb.out.haddr <= axi4_to_ahb_1.io.ahb.out.haddr @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 258:28] + axi4_to_ahb_1.io.ahb.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 258:28] + axi4_to_ahb.io.scan_mode <= io.scan_mode @[quasar.scala 260:33] + axi4_to_ahb.io.bus_clk_en <= io.dbg_bus_clk_en @[quasar.scala 261:34] + axi4_to_ahb.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 262:36] + dbg.io.sb_axi.r.bits.last <= axi4_to_ahb.io.axi.r.bits.last @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.resp <= axi4_to_ahb.io.axi.r.bits.resp @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.data <= axi4_to_ahb.io.axi.r.bits.data @[quasar.scala 263:27] + dbg.io.sb_axi.r.bits.id <= axi4_to_ahb.io.axi.r.bits.id @[quasar.scala 263:27] + dbg.io.sb_axi.r.valid <= axi4_to_ahb.io.axi.r.valid @[quasar.scala 263:27] + axi4_to_ahb.io.axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 263:27] + axi4_to_ahb.io.axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 263:27] + dbg.io.sb_axi.ar.ready <= axi4_to_ahb.io.axi.ar.ready @[quasar.scala 263:27] + dbg.io.sb_axi.b.bits.id <= axi4_to_ahb.io.axi.b.bits.id @[quasar.scala 263:27] + dbg.io.sb_axi.b.bits.resp <= axi4_to_ahb.io.axi.b.bits.resp @[quasar.scala 263:27] + dbg.io.sb_axi.b.valid <= axi4_to_ahb.io.axi.b.valid @[quasar.scala 263:27] + axi4_to_ahb.io.axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 263:27] + axi4_to_ahb.io.axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 263:27] + dbg.io.sb_axi.w.ready <= axi4_to_ahb.io.axi.w.ready @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 263:27] + axi4_to_ahb.io.axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 263:27] + dbg.io.sb_axi.aw.ready <= axi4_to_ahb.io.axi.aw.ready @[quasar.scala 263:27] + io.sb_ahb.out.hwdata <= axi4_to_ahb.io.ahb.out.hwdata @[quasar.scala 264:27] + io.sb_ahb.out.hwrite <= axi4_to_ahb.io.ahb.out.hwrite @[quasar.scala 264:27] + io.sb_ahb.out.htrans <= axi4_to_ahb.io.ahb.out.htrans @[quasar.scala 264:27] + io.sb_ahb.out.hsize <= axi4_to_ahb.io.ahb.out.hsize @[quasar.scala 264:27] + io.sb_ahb.out.hprot <= axi4_to_ahb.io.ahb.out.hprot @[quasar.scala 264:27] + io.sb_ahb.out.hmastlock <= axi4_to_ahb.io.ahb.out.hmastlock @[quasar.scala 264:27] + io.sb_ahb.out.hburst <= axi4_to_ahb.io.ahb.out.hburst @[quasar.scala 264:27] + io.sb_ahb.out.haddr <= axi4_to_ahb.io.ahb.out.haddr @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hready <= io.sb_ahb.in.hready @[quasar.scala 264:27] + axi4_to_ahb.io.ahb.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 264:27] + ahb_to_axi4.io.scan_mode <= io.scan_mode @[quasar.scala 266:34] + ahb_to_axi4.io.bus_clk_en <= io.dma_bus_clk_en @[quasar.scala 267:35] + ahb_to_axi4.io.clk_override <= dec.io.dec_tlu_bus_clk_override @[quasar.scala 268:37] + ahb_to_axi4.io.axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 269:28] + ahb_to_axi4.io.axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.r.ready <= ahb_to_axi4.io.axi.r.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.qos <= ahb_to_axi4.io.axi.ar.bits.qos @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.prot <= ahb_to_axi4.io.axi.ar.bits.prot @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.cache <= ahb_to_axi4.io.axi.ar.bits.cache @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.lock <= ahb_to_axi4.io.axi.ar.bits.lock @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.burst <= ahb_to_axi4.io.axi.ar.bits.burst @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.size <= ahb_to_axi4.io.axi.ar.bits.size @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.len <= ahb_to_axi4.io.axi.ar.bits.len @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.region <= ahb_to_axi4.io.axi.ar.bits.region @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.addr <= ahb_to_axi4.io.axi.ar.bits.addr @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.bits.id <= ahb_to_axi4.io.axi.ar.bits.id @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.ar.valid <= ahb_to_axi4.io.axi.ar.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 269:28] + ahb_to_axi4.io.axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.b.ready <= ahb_to_axi4.io.axi.b.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.last <= ahb_to_axi4.io.axi.w.bits.last @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.strb <= ahb_to_axi4.io.axi.w.bits.strb @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.bits.data <= ahb_to_axi4.io.axi.w.bits.data @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.w.valid <= ahb_to_axi4.io.axi.w.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.qos <= ahb_to_axi4.io.axi.aw.bits.qos @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.prot <= ahb_to_axi4.io.axi.aw.bits.prot @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.cache <= ahb_to_axi4.io.axi.aw.bits.cache @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.lock <= ahb_to_axi4.io.axi.aw.bits.lock @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.burst <= ahb_to_axi4.io.axi.aw.bits.burst @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.size <= ahb_to_axi4.io.axi.aw.bits.size @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.len <= ahb_to_axi4.io.axi.aw.bits.len @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.region <= ahb_to_axi4.io.axi.aw.bits.region @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.addr <= ahb_to_axi4.io.axi.aw.bits.addr @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.bits.id <= ahb_to_axi4.io.axi.aw.bits.id @[quasar.scala 269:28] + dma_ctrl.io.dma_axi.aw.valid <= ahb_to_axi4.io.axi.aw.valid @[quasar.scala 269:28] + ahb_to_axi4.io.axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 269:28] + ahb_to_axi4.io.ahb.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.hsel <= io.dma_ahb.hsel @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 270:28] + ahb_to_axi4.io.ahb.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 270:28] + io.dma_ahb.sig.in.hresp <= ahb_to_axi4.io.ahb.sig.in.hresp @[quasar.scala 270:28] + io.dma_ahb.sig.in.hready <= ahb_to_axi4.io.ahb.sig.in.hready @[quasar.scala 270:28] + io.dma_ahb.sig.in.hrdata <= ahb_to_axi4.io.ahb.sig.in.hrdata @[quasar.scala 270:28] + wire _T_12 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 272:31] + _T_12.r.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.r.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] + _T_12.r.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.r.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] + _T_12.ar.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.ar.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.bits.resp <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.b.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.b.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.bits.last <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.bits.strb <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.w.bits.data <= UInt<64>("h00") @[quasar.scala 272:31] + _T_12.w.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.w.ready <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.size <= UInt<3>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.len <= UInt<8>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.region <= UInt<4>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 272:31] + _T_12.aw.bits.id <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.valid <= UInt<1>("h00") @[quasar.scala 272:31] + _T_12.aw.ready <= UInt<1>("h00") @[quasar.scala 272:31] + io.dma_axi.r.bits.last <= _T_12.r.bits.last @[quasar.scala 272:16] + io.dma_axi.r.bits.resp <= _T_12.r.bits.resp @[quasar.scala 272:16] + io.dma_axi.r.bits.data <= _T_12.r.bits.data @[quasar.scala 272:16] + io.dma_axi.r.bits.id <= _T_12.r.bits.id @[quasar.scala 272:16] + io.dma_axi.r.valid <= _T_12.r.valid @[quasar.scala 272:16] + _T_12.r.ready <= io.dma_axi.r.ready @[quasar.scala 272:16] + _T_12.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 272:16] + _T_12.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 272:16] + _T_12.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 272:16] + _T_12.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 272:16] + _T_12.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 272:16] + _T_12.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 272:16] + _T_12.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 272:16] + _T_12.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 272:16] + _T_12.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 272:16] + _T_12.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 272:16] + _T_12.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 272:16] + io.dma_axi.ar.ready <= _T_12.ar.ready @[quasar.scala 272:16] + io.dma_axi.b.bits.id <= _T_12.b.bits.id @[quasar.scala 272:16] + io.dma_axi.b.bits.resp <= _T_12.b.bits.resp @[quasar.scala 272:16] + io.dma_axi.b.valid <= _T_12.b.valid @[quasar.scala 272:16] + _T_12.b.ready <= io.dma_axi.b.ready @[quasar.scala 272:16] + _T_12.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 272:16] + _T_12.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 272:16] + _T_12.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 272:16] + _T_12.w.valid <= io.dma_axi.w.valid @[quasar.scala 272:16] + io.dma_axi.w.ready <= _T_12.w.ready @[quasar.scala 272:16] + _T_12.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 272:16] + _T_12.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 272:16] + _T_12.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 272:16] + _T_12.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 272:16] + _T_12.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 272:16] + _T_12.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 272:16] + _T_12.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 272:16] + _T_12.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 272:16] + _T_12.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 272:16] + _T_12.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 272:16] + _T_12.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 272:16] + io.dma_axi.aw.ready <= _T_12.aw.ready @[quasar.scala 272:16] + wire _T_13 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 273:36] + _T_13.r.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.r.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_13.r.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_13.ar.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.ar.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.bits.resp <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.b.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.b.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.bits.last <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.bits.strb <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.w.bits.data <= UInt<64>("h00") @[quasar.scala 273:36] + _T_13.w.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.w.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.size <= UInt<3>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.len <= UInt<8>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.region <= UInt<4>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 273:36] + _T_13.aw.bits.id <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.valid <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.aw.ready <= UInt<1>("h00") @[quasar.scala 273:36] + _T_13.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 273:21] + _T_13.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 273:21] + _T_13.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 273:21] + _T_13.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 273:21] + _T_13.r.valid <= io.sb_axi.r.valid @[quasar.scala 273:21] + io.sb_axi.r.ready <= _T_13.r.ready @[quasar.scala 273:21] + io.sb_axi.ar.bits.qos <= _T_13.ar.bits.qos @[quasar.scala 273:21] + io.sb_axi.ar.bits.prot <= _T_13.ar.bits.prot @[quasar.scala 273:21] + io.sb_axi.ar.bits.cache <= _T_13.ar.bits.cache @[quasar.scala 273:21] + io.sb_axi.ar.bits.lock <= _T_13.ar.bits.lock @[quasar.scala 273:21] + io.sb_axi.ar.bits.burst <= _T_13.ar.bits.burst @[quasar.scala 273:21] + io.sb_axi.ar.bits.size <= _T_13.ar.bits.size @[quasar.scala 273:21] + io.sb_axi.ar.bits.len <= _T_13.ar.bits.len @[quasar.scala 273:21] + io.sb_axi.ar.bits.region <= _T_13.ar.bits.region @[quasar.scala 273:21] + io.sb_axi.ar.bits.addr <= _T_13.ar.bits.addr @[quasar.scala 273:21] + io.sb_axi.ar.bits.id <= _T_13.ar.bits.id @[quasar.scala 273:21] + io.sb_axi.ar.valid <= _T_13.ar.valid @[quasar.scala 273:21] + _T_13.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 273:21] + _T_13.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 273:21] + _T_13.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 273:21] + _T_13.b.valid <= io.sb_axi.b.valid @[quasar.scala 273:21] + io.sb_axi.b.ready <= _T_13.b.ready @[quasar.scala 273:21] + io.sb_axi.w.bits.last <= _T_13.w.bits.last @[quasar.scala 273:21] + io.sb_axi.w.bits.strb <= _T_13.w.bits.strb @[quasar.scala 273:21] + io.sb_axi.w.bits.data <= _T_13.w.bits.data @[quasar.scala 273:21] + io.sb_axi.w.valid <= _T_13.w.valid @[quasar.scala 273:21] + _T_13.w.ready <= io.sb_axi.w.ready @[quasar.scala 273:21] + io.sb_axi.aw.bits.qos <= _T_13.aw.bits.qos @[quasar.scala 273:21] + io.sb_axi.aw.bits.prot <= _T_13.aw.bits.prot @[quasar.scala 273:21] + io.sb_axi.aw.bits.cache <= _T_13.aw.bits.cache @[quasar.scala 273:21] + io.sb_axi.aw.bits.lock <= _T_13.aw.bits.lock @[quasar.scala 273:21] + io.sb_axi.aw.bits.burst <= _T_13.aw.bits.burst @[quasar.scala 273:21] + io.sb_axi.aw.bits.size <= _T_13.aw.bits.size @[quasar.scala 273:21] + io.sb_axi.aw.bits.len <= _T_13.aw.bits.len @[quasar.scala 273:21] + io.sb_axi.aw.bits.region <= _T_13.aw.bits.region @[quasar.scala 273:21] + io.sb_axi.aw.bits.addr <= _T_13.aw.bits.addr @[quasar.scala 273:21] + io.sb_axi.aw.bits.id <= _T_13.aw.bits.id @[quasar.scala 273:21] + io.sb_axi.aw.valid <= _T_13.aw.valid @[quasar.scala 273:21] + _T_13.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 273:21] + wire _T_14 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 274:40] + _T_14.r.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.r.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] + _T_14.r.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] + _T_14.ar.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.ar.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.bits.resp <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.b.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.b.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.bits.last <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.bits.strb <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.w.bits.data <= UInt<64>("h00") @[quasar.scala 274:40] + _T_14.w.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.w.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.size <= UInt<3>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.len <= UInt<8>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.region <= UInt<4>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 274:40] + _T_14.aw.bits.id <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.valid <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.aw.ready <= UInt<1>("h00") @[quasar.scala 274:40] + _T_14.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 274:25] + _T_14.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 274:25] + _T_14.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 274:25] + _T_14.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 274:25] + _T_14.r.valid <= io.ifu_axi.r.valid @[quasar.scala 274:25] + io.ifu_axi.r.ready <= _T_14.r.ready @[quasar.scala 274:25] + io.ifu_axi.ar.bits.qos <= _T_14.ar.bits.qos @[quasar.scala 274:25] + io.ifu_axi.ar.bits.prot <= _T_14.ar.bits.prot @[quasar.scala 274:25] + io.ifu_axi.ar.bits.cache <= _T_14.ar.bits.cache @[quasar.scala 274:25] + io.ifu_axi.ar.bits.lock <= _T_14.ar.bits.lock @[quasar.scala 274:25] + io.ifu_axi.ar.bits.burst <= _T_14.ar.bits.burst @[quasar.scala 274:25] + io.ifu_axi.ar.bits.size <= _T_14.ar.bits.size @[quasar.scala 274:25] + io.ifu_axi.ar.bits.len <= _T_14.ar.bits.len @[quasar.scala 274:25] + io.ifu_axi.ar.bits.region <= _T_14.ar.bits.region @[quasar.scala 274:25] + io.ifu_axi.ar.bits.addr <= _T_14.ar.bits.addr @[quasar.scala 274:25] + io.ifu_axi.ar.bits.id <= _T_14.ar.bits.id @[quasar.scala 274:25] + io.ifu_axi.ar.valid <= _T_14.ar.valid @[quasar.scala 274:25] + _T_14.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 274:25] + _T_14.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 274:25] + _T_14.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 274:25] + _T_14.b.valid <= io.ifu_axi.b.valid @[quasar.scala 274:25] + io.ifu_axi.b.ready <= _T_14.b.ready @[quasar.scala 274:25] + io.ifu_axi.w.bits.last <= _T_14.w.bits.last @[quasar.scala 274:25] + io.ifu_axi.w.bits.strb <= _T_14.w.bits.strb @[quasar.scala 274:25] + io.ifu_axi.w.bits.data <= _T_14.w.bits.data @[quasar.scala 274:25] + io.ifu_axi.w.valid <= _T_14.w.valid @[quasar.scala 274:25] + _T_14.w.ready <= io.ifu_axi.w.ready @[quasar.scala 274:25] + io.ifu_axi.aw.bits.qos <= _T_14.aw.bits.qos @[quasar.scala 274:25] + io.ifu_axi.aw.bits.prot <= _T_14.aw.bits.prot @[quasar.scala 274:25] + io.ifu_axi.aw.bits.cache <= _T_14.aw.bits.cache @[quasar.scala 274:25] + io.ifu_axi.aw.bits.lock <= _T_14.aw.bits.lock @[quasar.scala 274:25] + io.ifu_axi.aw.bits.burst <= _T_14.aw.bits.burst @[quasar.scala 274:25] + io.ifu_axi.aw.bits.size <= _T_14.aw.bits.size @[quasar.scala 274:25] + io.ifu_axi.aw.bits.len <= _T_14.aw.bits.len @[quasar.scala 274:25] + io.ifu_axi.aw.bits.region <= _T_14.aw.bits.region @[quasar.scala 274:25] + io.ifu_axi.aw.bits.addr <= _T_14.aw.bits.addr @[quasar.scala 274:25] + io.ifu_axi.aw.bits.id <= _T_14.aw.bits.id @[quasar.scala 274:25] + io.ifu_axi.aw.valid <= _T_14.aw.valid @[quasar.scala 274:25] + _T_14.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 274:25] + wire _T_15 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, strb : UInt<8>, last : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, addr : UInt<32>, region : UInt<4>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {id : UInt<1>, data : UInt<64>, resp : UInt<2>, last : UInt<1>}}} @[quasar.scala 275:40] + _T_15.r.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.r.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] + _T_15.r.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] + _T_15.ar.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.ar.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.bits.resp <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.b.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.b.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.bits.last <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.bits.strb <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.w.bits.data <= UInt<64>("h00") @[quasar.scala 275:40] + _T_15.w.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.w.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.qos <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.prot <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.cache <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.lock <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.burst <= UInt<2>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.size <= UInt<3>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.len <= UInt<8>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.region <= UInt<4>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.addr <= UInt<32>("h00") @[quasar.scala 275:40] + _T_15.aw.bits.id <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.valid <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.aw.ready <= UInt<1>("h00") @[quasar.scala 275:40] + _T_15.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 275:25] + _T_15.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 275:25] + _T_15.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 275:25] + _T_15.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 275:25] + _T_15.r.valid <= io.lsu_axi.r.valid @[quasar.scala 275:25] + io.lsu_axi.r.ready <= _T_15.r.ready @[quasar.scala 275:25] + io.lsu_axi.ar.bits.qos <= _T_15.ar.bits.qos @[quasar.scala 275:25] + io.lsu_axi.ar.bits.prot <= _T_15.ar.bits.prot @[quasar.scala 275:25] + io.lsu_axi.ar.bits.cache <= _T_15.ar.bits.cache @[quasar.scala 275:25] + io.lsu_axi.ar.bits.lock <= _T_15.ar.bits.lock @[quasar.scala 275:25] + io.lsu_axi.ar.bits.burst <= _T_15.ar.bits.burst @[quasar.scala 275:25] + io.lsu_axi.ar.bits.size <= _T_15.ar.bits.size @[quasar.scala 275:25] + io.lsu_axi.ar.bits.len <= _T_15.ar.bits.len @[quasar.scala 275:25] + io.lsu_axi.ar.bits.region <= _T_15.ar.bits.region @[quasar.scala 275:25] + io.lsu_axi.ar.bits.addr <= _T_15.ar.bits.addr @[quasar.scala 275:25] + io.lsu_axi.ar.bits.id <= _T_15.ar.bits.id @[quasar.scala 275:25] + io.lsu_axi.ar.valid <= _T_15.ar.valid @[quasar.scala 275:25] + _T_15.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 275:25] + _T_15.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 275:25] + _T_15.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 275:25] + _T_15.b.valid <= io.lsu_axi.b.valid @[quasar.scala 275:25] + io.lsu_axi.b.ready <= _T_15.b.ready @[quasar.scala 275:25] + io.lsu_axi.w.bits.last <= _T_15.w.bits.last @[quasar.scala 275:25] + io.lsu_axi.w.bits.strb <= _T_15.w.bits.strb @[quasar.scala 275:25] + io.lsu_axi.w.bits.data <= _T_15.w.bits.data @[quasar.scala 275:25] + io.lsu_axi.w.valid <= _T_15.w.valid @[quasar.scala 275:25] + _T_15.w.ready <= io.lsu_axi.w.ready @[quasar.scala 275:25] + io.lsu_axi.aw.bits.qos <= _T_15.aw.bits.qos @[quasar.scala 275:25] + io.lsu_axi.aw.bits.prot <= _T_15.aw.bits.prot @[quasar.scala 275:25] + io.lsu_axi.aw.bits.cache <= _T_15.aw.bits.cache @[quasar.scala 275:25] + io.lsu_axi.aw.bits.lock <= _T_15.aw.bits.lock @[quasar.scala 275:25] + io.lsu_axi.aw.bits.burst <= _T_15.aw.bits.burst @[quasar.scala 275:25] + io.lsu_axi.aw.bits.size <= _T_15.aw.bits.size @[quasar.scala 275:25] + io.lsu_axi.aw.bits.len <= _T_15.aw.bits.len @[quasar.scala 275:25] + io.lsu_axi.aw.bits.region <= _T_15.aw.bits.region @[quasar.scala 275:25] + io.lsu_axi.aw.bits.addr <= _T_15.aw.bits.addr @[quasar.scala 275:25] + io.lsu_axi.aw.bits.id <= _T_15.aw.bits.id @[quasar.scala 275:25] + io.lsu_axi.aw.valid <= _T_15.aw.valid @[quasar.scala 275:25] + _T_15.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 275:25] + skip @[quasar.scala 241:26] + else : @[quasar.scala 277:15] + wire _T_16 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 278:33] + _T_16.out.hwdata <= UInt<64>("h00") @[quasar.scala 278:33] + _T_16.out.hwrite <= UInt<1>("h00") @[quasar.scala 278:33] + _T_16.out.htrans <= UInt<2>("h00") @[quasar.scala 278:33] + _T_16.out.hsize <= UInt<3>("h00") @[quasar.scala 278:33] + _T_16.out.hprot <= UInt<4>("h00") @[quasar.scala 278:33] + _T_16.out.hmastlock <= UInt<1>("h00") @[quasar.scala 278:33] + _T_16.out.hburst <= UInt<3>("h00") @[quasar.scala 278:33] + _T_16.out.haddr <= UInt<32>("h00") @[quasar.scala 278:33] + _T_16.in.hresp <= UInt<1>("h00") @[quasar.scala 278:33] + _T_16.in.hready <= UInt<1>("h00") @[quasar.scala 278:33] + _T_16.in.hrdata <= UInt<64>("h00") @[quasar.scala 278:33] + io.lsu_ahb.out.hwdata <= _T_16.out.hwdata @[quasar.scala 278:18] + io.lsu_ahb.out.hwrite <= _T_16.out.hwrite @[quasar.scala 278:18] + io.lsu_ahb.out.htrans <= _T_16.out.htrans @[quasar.scala 278:18] + io.lsu_ahb.out.hsize <= _T_16.out.hsize @[quasar.scala 278:18] + io.lsu_ahb.out.hprot <= _T_16.out.hprot @[quasar.scala 278:18] + io.lsu_ahb.out.hmastlock <= _T_16.out.hmastlock @[quasar.scala 278:18] + io.lsu_ahb.out.hburst <= _T_16.out.hburst @[quasar.scala 278:18] + io.lsu_ahb.out.haddr <= _T_16.out.haddr @[quasar.scala 278:18] + _T_16.in.hresp <= io.lsu_ahb.in.hresp @[quasar.scala 278:18] + _T_16.in.hready <= io.lsu_ahb.in.hready @[quasar.scala 278:18] + _T_16.in.hrdata <= io.lsu_ahb.in.hrdata @[quasar.scala 278:18] + wire _T_17 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 279:33] + _T_17.out.hwdata <= UInt<64>("h00") @[quasar.scala 279:33] + _T_17.out.hwrite <= UInt<1>("h00") @[quasar.scala 279:33] + _T_17.out.htrans <= UInt<2>("h00") @[quasar.scala 279:33] + _T_17.out.hsize <= UInt<3>("h00") @[quasar.scala 279:33] + _T_17.out.hprot <= UInt<4>("h00") @[quasar.scala 279:33] + _T_17.out.hmastlock <= UInt<1>("h00") @[quasar.scala 279:33] + _T_17.out.hburst <= UInt<3>("h00") @[quasar.scala 279:33] + _T_17.out.haddr <= UInt<32>("h00") @[quasar.scala 279:33] + _T_17.in.hresp <= UInt<1>("h00") @[quasar.scala 279:33] + _T_17.in.hready <= UInt<1>("h00") @[quasar.scala 279:33] + _T_17.in.hrdata <= UInt<64>("h00") @[quasar.scala 279:33] + io.ifu_ahb.out.hwdata <= _T_17.out.hwdata @[quasar.scala 279:18] + io.ifu_ahb.out.hwrite <= _T_17.out.hwrite @[quasar.scala 279:18] + io.ifu_ahb.out.htrans <= _T_17.out.htrans @[quasar.scala 279:18] + io.ifu_ahb.out.hsize <= _T_17.out.hsize @[quasar.scala 279:18] + io.ifu_ahb.out.hprot <= _T_17.out.hprot @[quasar.scala 279:18] + io.ifu_ahb.out.hmastlock <= _T_17.out.hmastlock @[quasar.scala 279:18] + io.ifu_ahb.out.hburst <= _T_17.out.hburst @[quasar.scala 279:18] + io.ifu_ahb.out.haddr <= _T_17.out.haddr @[quasar.scala 279:18] + _T_17.in.hresp <= io.ifu_ahb.in.hresp @[quasar.scala 279:18] + _T_17.in.hready <= io.ifu_ahb.in.hready @[quasar.scala 279:18] + _T_17.in.hrdata <= io.ifu_ahb.in.hrdata @[quasar.scala 279:18] + wire _T_18 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar.scala 280:32] + _T_18.out.hwdata <= UInt<64>("h00") @[quasar.scala 280:32] + _T_18.out.hwrite <= UInt<1>("h00") @[quasar.scala 280:32] + _T_18.out.htrans <= UInt<2>("h00") @[quasar.scala 280:32] + _T_18.out.hsize <= UInt<3>("h00") @[quasar.scala 280:32] + _T_18.out.hprot <= UInt<4>("h00") @[quasar.scala 280:32] + _T_18.out.hmastlock <= UInt<1>("h00") @[quasar.scala 280:32] + _T_18.out.hburst <= UInt<3>("h00") @[quasar.scala 280:32] + _T_18.out.haddr <= UInt<32>("h00") @[quasar.scala 280:32] + _T_18.in.hresp <= UInt<1>("h00") @[quasar.scala 280:32] + _T_18.in.hready <= UInt<1>("h00") @[quasar.scala 280:32] + _T_18.in.hrdata <= UInt<64>("h00") @[quasar.scala 280:32] + io.sb_ahb.out.hwdata <= _T_18.out.hwdata @[quasar.scala 280:17] + io.sb_ahb.out.hwrite <= _T_18.out.hwrite @[quasar.scala 280:17] + io.sb_ahb.out.htrans <= _T_18.out.htrans @[quasar.scala 280:17] + io.sb_ahb.out.hsize <= _T_18.out.hsize @[quasar.scala 280:17] + io.sb_ahb.out.hprot <= _T_18.out.hprot @[quasar.scala 280:17] + io.sb_ahb.out.hmastlock <= _T_18.out.hmastlock @[quasar.scala 280:17] + io.sb_ahb.out.hburst <= _T_18.out.hburst @[quasar.scala 280:17] + io.sb_ahb.out.haddr <= _T_18.out.haddr @[quasar.scala 280:17] + _T_18.in.hresp <= io.sb_ahb.in.hresp @[quasar.scala 280:17] + _T_18.in.hready <= io.sb_ahb.in.hready @[quasar.scala 280:17] + _T_18.in.hrdata <= io.sb_ahb.in.hrdata @[quasar.scala 280:17] + wire _T_19 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar.scala 281:33] + _T_19.hreadyin <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.hsel <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hwdata <= UInt<64>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hwrite <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.sig.out.htrans <= UInt<2>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hsize <= UInt<3>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hprot <= UInt<4>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hmastlock <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.sig.out.hburst <= UInt<3>("h00") @[quasar.scala 281:33] + _T_19.sig.out.haddr <= UInt<32>("h00") @[quasar.scala 281:33] + _T_19.sig.in.hresp <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.sig.in.hready <= UInt<1>("h00") @[quasar.scala 281:33] + _T_19.sig.in.hrdata <= UInt<64>("h00") @[quasar.scala 281:33] + _T_19.hreadyin <= io.dma_ahb.hreadyin @[quasar.scala 281:18] + _T_19.hsel <= io.dma_ahb.hsel @[quasar.scala 281:18] + _T_19.sig.out.hwdata <= io.dma_ahb.sig.out.hwdata @[quasar.scala 281:18] + _T_19.sig.out.hwrite <= io.dma_ahb.sig.out.hwrite @[quasar.scala 281:18] + _T_19.sig.out.htrans <= io.dma_ahb.sig.out.htrans @[quasar.scala 281:18] + _T_19.sig.out.hsize <= io.dma_ahb.sig.out.hsize @[quasar.scala 281:18] + _T_19.sig.out.hprot <= io.dma_ahb.sig.out.hprot @[quasar.scala 281:18] + _T_19.sig.out.hmastlock <= io.dma_ahb.sig.out.hmastlock @[quasar.scala 281:18] + _T_19.sig.out.hburst <= io.dma_ahb.sig.out.hburst @[quasar.scala 281:18] + _T_19.sig.out.haddr <= io.dma_ahb.sig.out.haddr @[quasar.scala 281:18] + io.dma_ahb.sig.in.hresp <= _T_19.sig.in.hresp @[quasar.scala 281:18] + io.dma_ahb.sig.in.hready <= _T_19.sig.in.hready @[quasar.scala 281:18] + io.dma_ahb.sig.in.hrdata <= _T_19.sig.in.hrdata @[quasar.scala 281:18] + io.dma_axi.r.bits.last <= dma_ctrl.io.dma_axi.r.bits.last @[quasar.scala 282:27] + io.dma_axi.r.bits.resp <= dma_ctrl.io.dma_axi.r.bits.resp @[quasar.scala 282:27] + io.dma_axi.r.bits.data <= dma_ctrl.io.dma_axi.r.bits.data @[quasar.scala 282:27] + io.dma_axi.r.bits.id <= dma_ctrl.io.dma_axi.r.bits.id @[quasar.scala 282:27] + io.dma_axi.r.valid <= dma_ctrl.io.dma_axi.r.valid @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.r.ready <= io.dma_axi.r.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.qos <= io.dma_axi.ar.bits.qos @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.prot <= io.dma_axi.ar.bits.prot @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.cache <= io.dma_axi.ar.bits.cache @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.lock <= io.dma_axi.ar.bits.lock @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.burst <= io.dma_axi.ar.bits.burst @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.size <= io.dma_axi.ar.bits.size @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.len <= io.dma_axi.ar.bits.len @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.region <= io.dma_axi.ar.bits.region @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.addr <= io.dma_axi.ar.bits.addr @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.bits.id <= io.dma_axi.ar.bits.id @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.ar.valid <= io.dma_axi.ar.valid @[quasar.scala 282:27] + io.dma_axi.ar.ready <= dma_ctrl.io.dma_axi.ar.ready @[quasar.scala 282:27] + io.dma_axi.b.bits.id <= dma_ctrl.io.dma_axi.b.bits.id @[quasar.scala 282:27] + io.dma_axi.b.bits.resp <= dma_ctrl.io.dma_axi.b.bits.resp @[quasar.scala 282:27] + io.dma_axi.b.valid <= dma_ctrl.io.dma_axi.b.valid @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.b.ready <= io.dma_axi.b.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.last <= io.dma_axi.w.bits.last @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.strb <= io.dma_axi.w.bits.strb @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.bits.data <= io.dma_axi.w.bits.data @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.w.valid <= io.dma_axi.w.valid @[quasar.scala 282:27] + io.dma_axi.w.ready <= dma_ctrl.io.dma_axi.w.ready @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.qos <= io.dma_axi.aw.bits.qos @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.prot <= io.dma_axi.aw.bits.prot @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.cache <= io.dma_axi.aw.bits.cache @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.lock <= io.dma_axi.aw.bits.lock @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.burst <= io.dma_axi.aw.bits.burst @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.size <= io.dma_axi.aw.bits.size @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.len <= io.dma_axi.aw.bits.len @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.region <= io.dma_axi.aw.bits.region @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.addr <= io.dma_axi.aw.bits.addr @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.bits.id <= io.dma_axi.aw.bits.id @[quasar.scala 282:27] + dma_ctrl.io.dma_axi.aw.valid <= io.dma_axi.aw.valid @[quasar.scala 282:27] + io.dma_axi.aw.ready <= dma_ctrl.io.dma_axi.aw.ready @[quasar.scala 282:27] + dbg.io.sb_axi.r.bits.last <= io.sb_axi.r.bits.last @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.resp <= io.sb_axi.r.bits.resp @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.data <= io.sb_axi.r.bits.data @[quasar.scala 283:27] + dbg.io.sb_axi.r.bits.id <= io.sb_axi.r.bits.id @[quasar.scala 283:27] + dbg.io.sb_axi.r.valid <= io.sb_axi.r.valid @[quasar.scala 283:27] + io.sb_axi.r.ready <= dbg.io.sb_axi.r.ready @[quasar.scala 283:27] + io.sb_axi.ar.bits.qos <= dbg.io.sb_axi.ar.bits.qos @[quasar.scala 283:27] + io.sb_axi.ar.bits.prot <= dbg.io.sb_axi.ar.bits.prot @[quasar.scala 283:27] + io.sb_axi.ar.bits.cache <= dbg.io.sb_axi.ar.bits.cache @[quasar.scala 283:27] + io.sb_axi.ar.bits.lock <= dbg.io.sb_axi.ar.bits.lock @[quasar.scala 283:27] + io.sb_axi.ar.bits.burst <= dbg.io.sb_axi.ar.bits.burst @[quasar.scala 283:27] + io.sb_axi.ar.bits.size <= dbg.io.sb_axi.ar.bits.size @[quasar.scala 283:27] + io.sb_axi.ar.bits.len <= dbg.io.sb_axi.ar.bits.len @[quasar.scala 283:27] + io.sb_axi.ar.bits.region <= dbg.io.sb_axi.ar.bits.region @[quasar.scala 283:27] + io.sb_axi.ar.bits.addr <= dbg.io.sb_axi.ar.bits.addr @[quasar.scala 283:27] + io.sb_axi.ar.bits.id <= dbg.io.sb_axi.ar.bits.id @[quasar.scala 283:27] + io.sb_axi.ar.valid <= dbg.io.sb_axi.ar.valid @[quasar.scala 283:27] + dbg.io.sb_axi.ar.ready <= io.sb_axi.ar.ready @[quasar.scala 283:27] + dbg.io.sb_axi.b.bits.id <= io.sb_axi.b.bits.id @[quasar.scala 283:27] + dbg.io.sb_axi.b.bits.resp <= io.sb_axi.b.bits.resp @[quasar.scala 283:27] + dbg.io.sb_axi.b.valid <= io.sb_axi.b.valid @[quasar.scala 283:27] + io.sb_axi.b.ready <= dbg.io.sb_axi.b.ready @[quasar.scala 283:27] + io.sb_axi.w.bits.last <= dbg.io.sb_axi.w.bits.last @[quasar.scala 283:27] + io.sb_axi.w.bits.strb <= dbg.io.sb_axi.w.bits.strb @[quasar.scala 283:27] + io.sb_axi.w.bits.data <= dbg.io.sb_axi.w.bits.data @[quasar.scala 283:27] + io.sb_axi.w.valid <= dbg.io.sb_axi.w.valid @[quasar.scala 283:27] + dbg.io.sb_axi.w.ready <= io.sb_axi.w.ready @[quasar.scala 283:27] + io.sb_axi.aw.bits.qos <= dbg.io.sb_axi.aw.bits.qos @[quasar.scala 283:27] + io.sb_axi.aw.bits.prot <= dbg.io.sb_axi.aw.bits.prot @[quasar.scala 283:27] + io.sb_axi.aw.bits.cache <= dbg.io.sb_axi.aw.bits.cache @[quasar.scala 283:27] + io.sb_axi.aw.bits.lock <= dbg.io.sb_axi.aw.bits.lock @[quasar.scala 283:27] + io.sb_axi.aw.bits.burst <= dbg.io.sb_axi.aw.bits.burst @[quasar.scala 283:27] + io.sb_axi.aw.bits.size <= dbg.io.sb_axi.aw.bits.size @[quasar.scala 283:27] + io.sb_axi.aw.bits.len <= dbg.io.sb_axi.aw.bits.len @[quasar.scala 283:27] + io.sb_axi.aw.bits.region <= dbg.io.sb_axi.aw.bits.region @[quasar.scala 283:27] + io.sb_axi.aw.bits.addr <= dbg.io.sb_axi.aw.bits.addr @[quasar.scala 283:27] + io.sb_axi.aw.bits.id <= dbg.io.sb_axi.aw.bits.id @[quasar.scala 283:27] + io.sb_axi.aw.valid <= dbg.io.sb_axi.aw.valid @[quasar.scala 283:27] + dbg.io.sb_axi.aw.ready <= io.sb_axi.aw.ready @[quasar.scala 283:27] + ifu.io.ifu.r.bits.last <= io.ifu_axi.r.bits.last @[quasar.scala 284:27] + ifu.io.ifu.r.bits.resp <= io.ifu_axi.r.bits.resp @[quasar.scala 284:27] + ifu.io.ifu.r.bits.data <= io.ifu_axi.r.bits.data @[quasar.scala 284:27] + ifu.io.ifu.r.bits.id <= io.ifu_axi.r.bits.id @[quasar.scala 284:27] + ifu.io.ifu.r.valid <= io.ifu_axi.r.valid @[quasar.scala 284:27] + io.ifu_axi.r.ready <= ifu.io.ifu.r.ready @[quasar.scala 284:27] + io.ifu_axi.ar.bits.qos <= ifu.io.ifu.ar.bits.qos @[quasar.scala 284:27] + io.ifu_axi.ar.bits.prot <= ifu.io.ifu.ar.bits.prot @[quasar.scala 284:27] + io.ifu_axi.ar.bits.cache <= ifu.io.ifu.ar.bits.cache @[quasar.scala 284:27] + io.ifu_axi.ar.bits.lock <= ifu.io.ifu.ar.bits.lock @[quasar.scala 284:27] + io.ifu_axi.ar.bits.burst <= ifu.io.ifu.ar.bits.burst @[quasar.scala 284:27] + io.ifu_axi.ar.bits.size <= ifu.io.ifu.ar.bits.size @[quasar.scala 284:27] + io.ifu_axi.ar.bits.len <= ifu.io.ifu.ar.bits.len @[quasar.scala 284:27] + io.ifu_axi.ar.bits.region <= ifu.io.ifu.ar.bits.region @[quasar.scala 284:27] + io.ifu_axi.ar.bits.addr <= ifu.io.ifu.ar.bits.addr @[quasar.scala 284:27] + io.ifu_axi.ar.bits.id <= ifu.io.ifu.ar.bits.id @[quasar.scala 284:27] + io.ifu_axi.ar.valid <= ifu.io.ifu.ar.valid @[quasar.scala 284:27] + ifu.io.ifu.ar.ready <= io.ifu_axi.ar.ready @[quasar.scala 284:27] + ifu.io.ifu.b.bits.id <= io.ifu_axi.b.bits.id @[quasar.scala 284:27] + ifu.io.ifu.b.bits.resp <= io.ifu_axi.b.bits.resp @[quasar.scala 284:27] + ifu.io.ifu.b.valid <= io.ifu_axi.b.valid @[quasar.scala 284:27] + io.ifu_axi.b.ready <= ifu.io.ifu.b.ready @[quasar.scala 284:27] + io.ifu_axi.w.bits.last <= ifu.io.ifu.w.bits.last @[quasar.scala 284:27] + io.ifu_axi.w.bits.strb <= ifu.io.ifu.w.bits.strb @[quasar.scala 284:27] + io.ifu_axi.w.bits.data <= ifu.io.ifu.w.bits.data @[quasar.scala 284:27] + io.ifu_axi.w.valid <= ifu.io.ifu.w.valid @[quasar.scala 284:27] + ifu.io.ifu.w.ready <= io.ifu_axi.w.ready @[quasar.scala 284:27] + io.ifu_axi.aw.bits.qos <= ifu.io.ifu.aw.bits.qos @[quasar.scala 284:27] + io.ifu_axi.aw.bits.prot <= ifu.io.ifu.aw.bits.prot @[quasar.scala 284:27] + io.ifu_axi.aw.bits.cache <= ifu.io.ifu.aw.bits.cache @[quasar.scala 284:27] + io.ifu_axi.aw.bits.lock <= ifu.io.ifu.aw.bits.lock @[quasar.scala 284:27] + io.ifu_axi.aw.bits.burst <= ifu.io.ifu.aw.bits.burst @[quasar.scala 284:27] + io.ifu_axi.aw.bits.size <= ifu.io.ifu.aw.bits.size @[quasar.scala 284:27] + io.ifu_axi.aw.bits.len <= ifu.io.ifu.aw.bits.len @[quasar.scala 284:27] + io.ifu_axi.aw.bits.region <= ifu.io.ifu.aw.bits.region @[quasar.scala 284:27] + io.ifu_axi.aw.bits.addr <= ifu.io.ifu.aw.bits.addr @[quasar.scala 284:27] + io.ifu_axi.aw.bits.id <= ifu.io.ifu.aw.bits.id @[quasar.scala 284:27] + io.ifu_axi.aw.valid <= ifu.io.ifu.aw.valid @[quasar.scala 284:27] + ifu.io.ifu.aw.ready <= io.ifu_axi.aw.ready @[quasar.scala 284:27] + lsu.io.axi.r.bits.last <= io.lsu_axi.r.bits.last @[quasar.scala 285:27] + lsu.io.axi.r.bits.resp <= io.lsu_axi.r.bits.resp @[quasar.scala 285:27] + lsu.io.axi.r.bits.data <= io.lsu_axi.r.bits.data @[quasar.scala 285:27] + lsu.io.axi.r.bits.id <= io.lsu_axi.r.bits.id @[quasar.scala 285:27] + lsu.io.axi.r.valid <= io.lsu_axi.r.valid @[quasar.scala 285:27] + io.lsu_axi.r.ready <= lsu.io.axi.r.ready @[quasar.scala 285:27] + io.lsu_axi.ar.bits.qos <= lsu.io.axi.ar.bits.qos @[quasar.scala 285:27] + io.lsu_axi.ar.bits.prot <= lsu.io.axi.ar.bits.prot @[quasar.scala 285:27] + io.lsu_axi.ar.bits.cache <= lsu.io.axi.ar.bits.cache @[quasar.scala 285:27] + io.lsu_axi.ar.bits.lock <= lsu.io.axi.ar.bits.lock @[quasar.scala 285:27] + io.lsu_axi.ar.bits.burst <= lsu.io.axi.ar.bits.burst @[quasar.scala 285:27] + io.lsu_axi.ar.bits.size <= lsu.io.axi.ar.bits.size @[quasar.scala 285:27] + io.lsu_axi.ar.bits.len <= lsu.io.axi.ar.bits.len @[quasar.scala 285:27] + io.lsu_axi.ar.bits.region <= lsu.io.axi.ar.bits.region @[quasar.scala 285:27] + io.lsu_axi.ar.bits.addr <= lsu.io.axi.ar.bits.addr @[quasar.scala 285:27] + io.lsu_axi.ar.bits.id <= lsu.io.axi.ar.bits.id @[quasar.scala 285:27] + io.lsu_axi.ar.valid <= lsu.io.axi.ar.valid @[quasar.scala 285:27] + lsu.io.axi.ar.ready <= io.lsu_axi.ar.ready @[quasar.scala 285:27] + lsu.io.axi.b.bits.id <= io.lsu_axi.b.bits.id @[quasar.scala 285:27] + lsu.io.axi.b.bits.resp <= io.lsu_axi.b.bits.resp @[quasar.scala 285:27] + lsu.io.axi.b.valid <= io.lsu_axi.b.valid @[quasar.scala 285:27] + io.lsu_axi.b.ready <= lsu.io.axi.b.ready @[quasar.scala 285:27] + io.lsu_axi.w.bits.last <= lsu.io.axi.w.bits.last @[quasar.scala 285:27] + io.lsu_axi.w.bits.strb <= lsu.io.axi.w.bits.strb @[quasar.scala 285:27] + io.lsu_axi.w.bits.data <= lsu.io.axi.w.bits.data @[quasar.scala 285:27] + io.lsu_axi.w.valid <= lsu.io.axi.w.valid @[quasar.scala 285:27] + lsu.io.axi.w.ready <= io.lsu_axi.w.ready @[quasar.scala 285:27] + io.lsu_axi.aw.bits.qos <= lsu.io.axi.aw.bits.qos @[quasar.scala 285:27] + io.lsu_axi.aw.bits.prot <= lsu.io.axi.aw.bits.prot @[quasar.scala 285:27] + io.lsu_axi.aw.bits.cache <= lsu.io.axi.aw.bits.cache @[quasar.scala 285:27] + io.lsu_axi.aw.bits.lock <= lsu.io.axi.aw.bits.lock @[quasar.scala 285:27] + io.lsu_axi.aw.bits.burst <= lsu.io.axi.aw.bits.burst @[quasar.scala 285:27] + io.lsu_axi.aw.bits.size <= lsu.io.axi.aw.bits.size @[quasar.scala 285:27] + io.lsu_axi.aw.bits.len <= lsu.io.axi.aw.bits.len @[quasar.scala 285:27] + io.lsu_axi.aw.bits.region <= lsu.io.axi.aw.bits.region @[quasar.scala 285:27] + io.lsu_axi.aw.bits.addr <= lsu.io.axi.aw.bits.addr @[quasar.scala 285:27] + io.lsu_axi.aw.bits.id <= lsu.io.axi.aw.bits.id @[quasar.scala 285:27] + io.lsu_axi.aw.valid <= lsu.io.axi.aw.valid @[quasar.scala 285:27] + lsu.io.axi.aw.ready <= io.lsu_axi.aw.ready @[quasar.scala 285:27] + skip @[quasar.scala 277:15] + io.dmi_reg_rdata <= UInt<1>("h00") @[quasar.scala 287:20] module quasar_wrapper : input clock : Clock @@ -109872,289 +115281,291 @@ circuit quasar_wrapper : mem.iccm.correction_state <= core.io.iccm.correction_state @[quasar_wrapper.scala 95:16] mem.iccm.buf_correct_ecc <= core.io.iccm.buf_correct_ecc @[quasar_wrapper.scala 95:16] mem.iccm.rw_addr <= core.io.iccm.rw_addr @[quasar_wrapper.scala 95:16] - wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 97:30] - _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 97:30] - _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 97:30] - _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 97:30] - _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 97:30] - _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 97:30] - _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 97:30] - _T.out.hwdata <= core.io.ahb.out.hwdata @[quasar_wrapper.scala 97:15] - _T.out.hwrite <= core.io.ahb.out.hwrite @[quasar_wrapper.scala 97:15] - _T.out.htrans <= core.io.ahb.out.htrans @[quasar_wrapper.scala 97:15] - _T.out.hsize <= core.io.ahb.out.hsize @[quasar_wrapper.scala 97:15] - _T.out.hprot <= core.io.ahb.out.hprot @[quasar_wrapper.scala 97:15] - _T.out.hmastlock <= core.io.ahb.out.hmastlock @[quasar_wrapper.scala 97:15] - _T.out.hburst <= core.io.ahb.out.hburst @[quasar_wrapper.scala 97:15] - _T.out.haddr <= core.io.ahb.out.haddr @[quasar_wrapper.scala 97:15] - core.io.ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 97:15] - core.io.ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 97:15] - core.io.ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 97:15] - wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 98:34] - _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 98:34] - _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 98:34] - _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 98:34] - _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 98:34] - _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 98:19] - _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 98:19] - _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 98:19] - _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 98:19] - _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 98:19] - _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 98:19] - _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 98:19] - _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 98:19] - core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 98:19] - core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 98:19] - core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 98:19] - wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:33] - _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:33] - _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:33] - _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:33] - _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:33] - _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 99:18] - _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 99:18] - _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 99:18] - _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 99:18] - _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 99:18] - _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 99:18] - _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 99:18] - _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 99:18] - core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 99:18] - core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 99:18] - core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 99:18] - wire _T_3 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:34] - _T_3.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:34] - _T_3.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:34] - _T_3.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:34] - _T_3.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:34] - _T_3.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:34] - core.io.dma.ahb.out.hwdata <= _T_3.out.hwdata @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.hwrite <= _T_3.out.hwrite @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.htrans <= _T_3.out.htrans @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.hsize <= _T_3.out.hsize @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.hprot <= _T_3.out.hprot @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.hmastlock <= _T_3.out.hmastlock @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.hburst <= _T_3.out.hburst @[quasar_wrapper.scala 100:19] - core.io.dma.ahb.out.haddr <= _T_3.out.haddr @[quasar_wrapper.scala 100:19] - _T_3.in.hresp <= core.io.dma.ahb.in.hresp @[quasar_wrapper.scala 100:19] - _T_3.in.hready <= core.io.dma.ahb.in.hready @[quasar_wrapper.scala 100:19] - _T_3.in.hrdata <= core.io.dma.ahb.in.hrdata @[quasar_wrapper.scala 100:19] - core.io.dma.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 101:20] - core.io.dma.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 102:24] - core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 103:19] - io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 103:19] - io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 103:19] - io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 103:19] - io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 103:19] - io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 103:19] - io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 103:19] - io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 103:19] - io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 103:19] - core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 103:19] - core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 104:19] - io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 104:19] - io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 104:19] - io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 104:19] - io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 104:19] - io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 104:19] - io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 104:19] - io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 104:19] - io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 104:19] - core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 104:19] - core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 105:18] - core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 105:18] - core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 105:18] - core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 105:18] - core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 105:18] - io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 105:18] - io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 105:18] - core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 105:18] - core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 105:18] - core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 105:18] - core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 105:18] - io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 105:18] - io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 105:18] - io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 105:18] - io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 105:18] - io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 105:18] - core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 105:18] - io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 105:18] - core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 105:18] - io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 106:19] - io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 106:19] - io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 106:19] - io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 106:19] - io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 106:19] - core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 106:19] - core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 106:19] - io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 106:19] - io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 106:19] - io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 106:19] - io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 106:19] - core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 106:19] - core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 106:19] - core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 106:19] - core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 106:19] - core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 106:19] - io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 106:19] - core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 106:19] - io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 106:19] - core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 123:21] - core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 124:19] - core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 125:19] - core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 126:19] - core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 129:26] - core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 130:25] - core.io.core_id <= io.core_id @[quasar_wrapper.scala 131:19] - core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 134:30] - core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 135:29] - core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 136:29] - core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 138:26] - core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 139:26] - core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 140:26] - core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 141:26] - core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 143:21] - core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 144:20] - core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 145:25] - io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 149:19] - io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 149:19] - io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 152:21] - io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 153:24] - io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 154:20] - io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 155:26] - io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 157:25] - io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 158:24] - io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 159:25] - io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 161:23] - io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 162:23] - io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 163:23] - io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 164:23] + wire _T : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 99:36] + _T.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 99:36] + _T.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 99:36] + _T.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 99:36] + _T.out.hwdata <= core.io.ifu_ahb.out.hwdata @[quasar_wrapper.scala 99:21] + _T.out.hwrite <= core.io.ifu_ahb.out.hwrite @[quasar_wrapper.scala 99:21] + _T.out.htrans <= core.io.ifu_ahb.out.htrans @[quasar_wrapper.scala 99:21] + _T.out.hsize <= core.io.ifu_ahb.out.hsize @[quasar_wrapper.scala 99:21] + _T.out.hprot <= core.io.ifu_ahb.out.hprot @[quasar_wrapper.scala 99:21] + _T.out.hmastlock <= core.io.ifu_ahb.out.hmastlock @[quasar_wrapper.scala 99:21] + _T.out.hburst <= core.io.ifu_ahb.out.hburst @[quasar_wrapper.scala 99:21] + _T.out.haddr <= core.io.ifu_ahb.out.haddr @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hresp <= _T.in.hresp @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hready <= _T.in.hready @[quasar_wrapper.scala 99:21] + core.io.ifu_ahb.in.hrdata <= _T.in.hrdata @[quasar_wrapper.scala 99:21] + wire _T_1 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 100:36] + _T_1.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 100:36] + _T_1.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 100:36] + _T_1.out.hwdata <= core.io.lsu_ahb.out.hwdata @[quasar_wrapper.scala 100:21] + _T_1.out.hwrite <= core.io.lsu_ahb.out.hwrite @[quasar_wrapper.scala 100:21] + _T_1.out.htrans <= core.io.lsu_ahb.out.htrans @[quasar_wrapper.scala 100:21] + _T_1.out.hsize <= core.io.lsu_ahb.out.hsize @[quasar_wrapper.scala 100:21] + _T_1.out.hprot <= core.io.lsu_ahb.out.hprot @[quasar_wrapper.scala 100:21] + _T_1.out.hmastlock <= core.io.lsu_ahb.out.hmastlock @[quasar_wrapper.scala 100:21] + _T_1.out.hburst <= core.io.lsu_ahb.out.hburst @[quasar_wrapper.scala 100:21] + _T_1.out.haddr <= core.io.lsu_ahb.out.haddr @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hresp <= _T_1.in.hresp @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hready <= _T_1.in.hready @[quasar_wrapper.scala 100:21] + core.io.lsu_ahb.in.hrdata <= _T_1.in.hrdata @[quasar_wrapper.scala 100:21] + wire _T_2 : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}} @[quasar_wrapper.scala 101:36] + _T_2.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 101:36] + _T_2.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 101:36] + _T_2.out.hwdata <= core.io.sb_ahb.out.hwdata @[quasar_wrapper.scala 101:21] + _T_2.out.hwrite <= core.io.sb_ahb.out.hwrite @[quasar_wrapper.scala 101:21] + _T_2.out.htrans <= core.io.sb_ahb.out.htrans @[quasar_wrapper.scala 101:21] + _T_2.out.hsize <= core.io.sb_ahb.out.hsize @[quasar_wrapper.scala 101:21] + _T_2.out.hprot <= core.io.sb_ahb.out.hprot @[quasar_wrapper.scala 101:21] + _T_2.out.hmastlock <= core.io.sb_ahb.out.hmastlock @[quasar_wrapper.scala 101:21] + _T_2.out.hburst <= core.io.sb_ahb.out.hburst @[quasar_wrapper.scala 101:21] + _T_2.out.haddr <= core.io.sb_ahb.out.haddr @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hresp <= _T_2.in.hresp @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hready <= _T_2.in.hready @[quasar_wrapper.scala 101:21] + core.io.sb_ahb.in.hrdata <= _T_2.in.hrdata @[quasar_wrapper.scala 101:21] + wire _T_3 : {flip sig : {in : {flip hrdata : UInt<64>, flip hready : UInt<1>, flip hresp : UInt<1>}, out : {haddr : UInt<32>, hburst : UInt<3>, hmastlock : UInt<1>, hprot : UInt<4>, hsize : UInt<3>, htrans : UInt<2>, hwrite : UInt<1>, hwdata : UInt<64>}}, flip hsel : UInt<1>, flip hreadyin : UInt<1>} @[quasar_wrapper.scala 102:36] + _T_3.hreadyin <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.hsel <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hwdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hwrite <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.htrans <= UInt<2>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hsize <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hprot <= UInt<4>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hmastlock <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.hburst <= UInt<3>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.out.haddr <= UInt<32>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hresp <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hready <= UInt<1>("h00") @[quasar_wrapper.scala 102:36] + _T_3.sig.in.hrdata <= UInt<64>("h00") @[quasar_wrapper.scala 102:36] + core.io.dma_ahb.hreadyin <= _T_3.hreadyin @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.hsel <= _T_3.hsel @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hwdata <= _T_3.sig.out.hwdata @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hwrite <= _T_3.sig.out.hwrite @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.htrans <= _T_3.sig.out.htrans @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hsize <= _T_3.sig.out.hsize @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hprot <= _T_3.sig.out.hprot @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hmastlock <= _T_3.sig.out.hmastlock @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.hburst <= _T_3.sig.out.hburst @[quasar_wrapper.scala 102:21] + core.io.dma_ahb.sig.out.haddr <= _T_3.sig.out.haddr @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hresp <= core.io.dma_ahb.sig.in.hresp @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hready <= core.io.dma_ahb.sig.in.hready @[quasar_wrapper.scala 102:21] + _T_3.sig.in.hrdata <= core.io.dma_ahb.sig.in.hrdata @[quasar_wrapper.scala 102:21] + core.io.lsu_axi.r.bits.last <= io.lsu_brg.r.bits.last @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.resp <= io.lsu_brg.r.bits.resp @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.data <= io.lsu_brg.r.bits.data @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.bits.id <= io.lsu_brg.r.bits.id @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.r.valid <= io.lsu_brg.r.valid @[quasar_wrapper.scala 104:21] + io.lsu_brg.r.ready <= core.io.lsu_axi.r.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.qos <= core.io.lsu_axi.ar.bits.qos @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.prot <= core.io.lsu_axi.ar.bits.prot @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.cache <= core.io.lsu_axi.ar.bits.cache @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.lock <= core.io.lsu_axi.ar.bits.lock @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.burst <= core.io.lsu_axi.ar.bits.burst @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.size <= core.io.lsu_axi.ar.bits.size @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.len <= core.io.lsu_axi.ar.bits.len @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.region <= core.io.lsu_axi.ar.bits.region @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.addr <= core.io.lsu_axi.ar.bits.addr @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.bits.id <= core.io.lsu_axi.ar.bits.id @[quasar_wrapper.scala 104:21] + io.lsu_brg.ar.valid <= core.io.lsu_axi.ar.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.ar.ready <= io.lsu_brg.ar.ready @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.bits.id <= io.lsu_brg.b.bits.id @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.bits.resp <= io.lsu_brg.b.bits.resp @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.b.valid <= io.lsu_brg.b.valid @[quasar_wrapper.scala 104:21] + io.lsu_brg.b.ready <= core.io.lsu_axi.b.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.last <= core.io.lsu_axi.w.bits.last @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.strb <= core.io.lsu_axi.w.bits.strb @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.bits.data <= core.io.lsu_axi.w.bits.data @[quasar_wrapper.scala 104:21] + io.lsu_brg.w.valid <= core.io.lsu_axi.w.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.w.ready <= io.lsu_brg.w.ready @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.qos <= core.io.lsu_axi.aw.bits.qos @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.prot <= core.io.lsu_axi.aw.bits.prot @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.cache <= core.io.lsu_axi.aw.bits.cache @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.lock <= core.io.lsu_axi.aw.bits.lock @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.burst <= core.io.lsu_axi.aw.bits.burst @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.size <= core.io.lsu_axi.aw.bits.size @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.len <= core.io.lsu_axi.aw.bits.len @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.region <= core.io.lsu_axi.aw.bits.region @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.addr <= core.io.lsu_axi.aw.bits.addr @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.bits.id <= core.io.lsu_axi.aw.bits.id @[quasar_wrapper.scala 104:21] + io.lsu_brg.aw.valid <= core.io.lsu_axi.aw.valid @[quasar_wrapper.scala 104:21] + core.io.lsu_axi.aw.ready <= io.lsu_brg.aw.ready @[quasar_wrapper.scala 104:21] + core.io.ifu_axi.r.bits.last <= io.ifu_brg.r.bits.last @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.resp <= io.ifu_brg.r.bits.resp @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.data <= io.ifu_brg.r.bits.data @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.bits.id <= io.ifu_brg.r.bits.id @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.r.valid <= io.ifu_brg.r.valid @[quasar_wrapper.scala 105:21] + io.ifu_brg.r.ready <= core.io.ifu_axi.r.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.qos <= core.io.ifu_axi.ar.bits.qos @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.prot <= core.io.ifu_axi.ar.bits.prot @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.cache <= core.io.ifu_axi.ar.bits.cache @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.lock <= core.io.ifu_axi.ar.bits.lock @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.burst <= core.io.ifu_axi.ar.bits.burst @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.size <= core.io.ifu_axi.ar.bits.size @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.len <= core.io.ifu_axi.ar.bits.len @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.region <= core.io.ifu_axi.ar.bits.region @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.addr <= core.io.ifu_axi.ar.bits.addr @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.bits.id <= core.io.ifu_axi.ar.bits.id @[quasar_wrapper.scala 105:21] + io.ifu_brg.ar.valid <= core.io.ifu_axi.ar.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.ar.ready <= io.ifu_brg.ar.ready @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.bits.id <= io.ifu_brg.b.bits.id @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.bits.resp <= io.ifu_brg.b.bits.resp @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.b.valid <= io.ifu_brg.b.valid @[quasar_wrapper.scala 105:21] + io.ifu_brg.b.ready <= core.io.ifu_axi.b.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.last <= core.io.ifu_axi.w.bits.last @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.strb <= core.io.ifu_axi.w.bits.strb @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.bits.data <= core.io.ifu_axi.w.bits.data @[quasar_wrapper.scala 105:21] + io.ifu_brg.w.valid <= core.io.ifu_axi.w.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.w.ready <= io.ifu_brg.w.ready @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.qos <= core.io.ifu_axi.aw.bits.qos @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.prot <= core.io.ifu_axi.aw.bits.prot @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.cache <= core.io.ifu_axi.aw.bits.cache @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.lock <= core.io.ifu_axi.aw.bits.lock @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.burst <= core.io.ifu_axi.aw.bits.burst @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.size <= core.io.ifu_axi.aw.bits.size @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.len <= core.io.ifu_axi.aw.bits.len @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.region <= core.io.ifu_axi.aw.bits.region @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.addr <= core.io.ifu_axi.aw.bits.addr @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.bits.id <= core.io.ifu_axi.aw.bits.id @[quasar_wrapper.scala 105:21] + io.ifu_brg.aw.valid <= core.io.ifu_axi.aw.valid @[quasar_wrapper.scala 105:21] + core.io.ifu_axi.aw.ready <= io.ifu_brg.aw.ready @[quasar_wrapper.scala 105:21] + core.io.sb_axi.r.bits.last <= io.sb_brg.r.bits.last @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.resp <= io.sb_brg.r.bits.resp @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.data <= io.sb_brg.r.bits.data @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.bits.id <= io.sb_brg.r.bits.id @[quasar_wrapper.scala 106:21] + core.io.sb_axi.r.valid <= io.sb_brg.r.valid @[quasar_wrapper.scala 106:21] + io.sb_brg.r.ready <= core.io.sb_axi.r.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.qos <= core.io.sb_axi.ar.bits.qos @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.prot <= core.io.sb_axi.ar.bits.prot @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.cache <= core.io.sb_axi.ar.bits.cache @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.lock <= core.io.sb_axi.ar.bits.lock @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.burst <= core.io.sb_axi.ar.bits.burst @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.size <= core.io.sb_axi.ar.bits.size @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.len <= core.io.sb_axi.ar.bits.len @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.region <= core.io.sb_axi.ar.bits.region @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.addr <= core.io.sb_axi.ar.bits.addr @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.bits.id <= core.io.sb_axi.ar.bits.id @[quasar_wrapper.scala 106:21] + io.sb_brg.ar.valid <= core.io.sb_axi.ar.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.ar.ready <= io.sb_brg.ar.ready @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.bits.id <= io.sb_brg.b.bits.id @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.bits.resp <= io.sb_brg.b.bits.resp @[quasar_wrapper.scala 106:21] + core.io.sb_axi.b.valid <= io.sb_brg.b.valid @[quasar_wrapper.scala 106:21] + io.sb_brg.b.ready <= core.io.sb_axi.b.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.last <= core.io.sb_axi.w.bits.last @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.strb <= core.io.sb_axi.w.bits.strb @[quasar_wrapper.scala 106:21] + io.sb_brg.w.bits.data <= core.io.sb_axi.w.bits.data @[quasar_wrapper.scala 106:21] + io.sb_brg.w.valid <= core.io.sb_axi.w.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.w.ready <= io.sb_brg.w.ready @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.qos <= core.io.sb_axi.aw.bits.qos @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.prot <= core.io.sb_axi.aw.bits.prot @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.cache <= core.io.sb_axi.aw.bits.cache @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.lock <= core.io.sb_axi.aw.bits.lock @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.burst <= core.io.sb_axi.aw.bits.burst @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.size <= core.io.sb_axi.aw.bits.size @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.len <= core.io.sb_axi.aw.bits.len @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.region <= core.io.sb_axi.aw.bits.region @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.addr <= core.io.sb_axi.aw.bits.addr @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.bits.id <= core.io.sb_axi.aw.bits.id @[quasar_wrapper.scala 106:21] + io.sb_brg.aw.valid <= core.io.sb_axi.aw.valid @[quasar_wrapper.scala 106:21] + core.io.sb_axi.aw.ready <= io.sb_brg.aw.ready @[quasar_wrapper.scala 106:21] + io.dma_brg.r.bits.last <= core.io.dma_axi.r.bits.last @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.resp <= core.io.dma_axi.r.bits.resp @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.data <= core.io.dma_axi.r.bits.data @[quasar_wrapper.scala 107:21] + io.dma_brg.r.bits.id <= core.io.dma_axi.r.bits.id @[quasar_wrapper.scala 107:21] + io.dma_brg.r.valid <= core.io.dma_axi.r.valid @[quasar_wrapper.scala 107:21] + core.io.dma_axi.r.ready <= io.dma_brg.r.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.qos <= io.dma_brg.ar.bits.qos @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.prot <= io.dma_brg.ar.bits.prot @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.cache <= io.dma_brg.ar.bits.cache @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.lock <= io.dma_brg.ar.bits.lock @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.burst <= io.dma_brg.ar.bits.burst @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.size <= io.dma_brg.ar.bits.size @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.len <= io.dma_brg.ar.bits.len @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.region <= io.dma_brg.ar.bits.region @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.addr <= io.dma_brg.ar.bits.addr @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.bits.id <= io.dma_brg.ar.bits.id @[quasar_wrapper.scala 107:21] + core.io.dma_axi.ar.valid <= io.dma_brg.ar.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.ar.ready <= core.io.dma_axi.ar.ready @[quasar_wrapper.scala 107:21] + io.dma_brg.b.bits.id <= core.io.dma_axi.b.bits.id @[quasar_wrapper.scala 107:21] + io.dma_brg.b.bits.resp <= core.io.dma_axi.b.bits.resp @[quasar_wrapper.scala 107:21] + io.dma_brg.b.valid <= core.io.dma_axi.b.valid @[quasar_wrapper.scala 107:21] + core.io.dma_axi.b.ready <= io.dma_brg.b.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.last <= io.dma_brg.w.bits.last @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.strb <= io.dma_brg.w.bits.strb @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.bits.data <= io.dma_brg.w.bits.data @[quasar_wrapper.scala 107:21] + core.io.dma_axi.w.valid <= io.dma_brg.w.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.w.ready <= core.io.dma_axi.w.ready @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.qos <= io.dma_brg.aw.bits.qos @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.prot <= io.dma_brg.aw.bits.prot @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.cache <= io.dma_brg.aw.bits.cache @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.lock <= io.dma_brg.aw.bits.lock @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.burst <= io.dma_brg.aw.bits.burst @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.size <= io.dma_brg.aw.bits.size @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.len <= io.dma_brg.aw.bits.len @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.region <= io.dma_brg.aw.bits.region @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.addr <= io.dma_brg.aw.bits.addr @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.bits.id <= io.dma_brg.aw.bits.id @[quasar_wrapper.scala 107:21] + core.io.dma_axi.aw.valid <= io.dma_brg.aw.valid @[quasar_wrapper.scala 107:21] + io.dma_brg.aw.ready <= core.io.dma_axi.aw.ready @[quasar_wrapper.scala 107:21] + core.io.dbg_rst_l <= io.dbg_rst_l @[quasar_wrapper.scala 121:21] + core.io.rst_vec <= io.rst_vec @[quasar_wrapper.scala 122:19] + core.io.nmi_int <= io.nmi_int @[quasar_wrapper.scala 123:19] + core.io.nmi_vec <= io.nmi_vec @[quasar_wrapper.scala 124:19] + core.io.i_cpu_halt_req <= io.i_cpu_halt_req @[quasar_wrapper.scala 127:26] + core.io.i_cpu_run_req <= io.i_cpu_run_req @[quasar_wrapper.scala 128:25] + core.io.core_id <= io.core_id @[quasar_wrapper.scala 129:19] + core.io.mpc_debug_halt_req <= io.mpc_debug_halt_req @[quasar_wrapper.scala 132:30] + core.io.mpc_debug_run_req <= io.mpc_debug_run_req @[quasar_wrapper.scala 133:29] + core.io.mpc_reset_run_req <= io.mpc_reset_run_req @[quasar_wrapper.scala 134:29] + core.io.lsu_bus_clk_en <= io.lsu_bus_clk_en @[quasar_wrapper.scala 136:26] + core.io.ifu_bus_clk_en <= io.ifu_bus_clk_en @[quasar_wrapper.scala 137:26] + core.io.dbg_bus_clk_en <= io.dbg_bus_clk_en @[quasar_wrapper.scala 138:26] + core.io.dma_bus_clk_en <= io.dma_bus_clk_en @[quasar_wrapper.scala 139:26] + core.io.timer_int <= io.timer_int @[quasar_wrapper.scala 141:21] + core.io.soft_int <= io.soft_int @[quasar_wrapper.scala 142:20] + core.io.extintsrc_req <= io.extintsrc_req @[quasar_wrapper.scala 143:25] + io.rv_trace_pkt.rv_i_tval_ip <= core.io.rv_trace_pkt.rv_i_tval_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_interrupt_ip <= core.io.rv_trace_pkt.rv_i_interrupt_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_ecause_ip <= core.io.rv_trace_pkt.rv_i_ecause_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_exception_ip <= core.io.rv_trace_pkt.rv_i_exception_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_address_ip <= core.io.rv_trace_pkt.rv_i_address_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_insn_ip <= core.io.rv_trace_pkt.rv_i_insn_ip @[quasar_wrapper.scala 147:19] + io.rv_trace_pkt.rv_i_valid_ip <= core.io.rv_trace_pkt.rv_i_valid_ip @[quasar_wrapper.scala 147:19] + io.o_cpu_halt_ack <= core.io.o_cpu_halt_ack @[quasar_wrapper.scala 150:21] + io.o_cpu_halt_status <= core.io.o_cpu_halt_status @[quasar_wrapper.scala 151:24] + io.o_cpu_run_ack <= core.io.o_cpu_run_ack @[quasar_wrapper.scala 152:20] + io.o_debug_mode_status <= core.io.o_debug_mode_status @[quasar_wrapper.scala 153:26] + io.mpc_debug_halt_ack <= core.io.mpc_debug_halt_ack @[quasar_wrapper.scala 155:25] + io.mpc_debug_run_ack <= core.io.mpc_debug_run_ack @[quasar_wrapper.scala 156:24] + io.debug_brkpt_status <= core.io.debug_brkpt_status @[quasar_wrapper.scala 157:25] + io.dec_tlu_perfcnt0 <= core.io.dec_tlu_perfcnt0 @[quasar_wrapper.scala 159:23] + io.dec_tlu_perfcnt1 <= core.io.dec_tlu_perfcnt1 @[quasar_wrapper.scala 160:23] + io.dec_tlu_perfcnt2 <= core.io.dec_tlu_perfcnt2 @[quasar_wrapper.scala 161:23] + io.dec_tlu_perfcnt3 <= core.io.dec_tlu_perfcnt3 @[quasar_wrapper.scala 162:23] diff --git a/design/quasar_wrapper.v b/quasar_wrapper.v similarity index 98% rename from design/quasar_wrapper.v rename to quasar_wrapper.v index b0b92a9e..83b0c187 100644 --- a/design/quasar_wrapper.v +++ b/quasar_wrapper.v @@ -50524,6 +50524,7 @@ module csr_tlu( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -52650,6 +52651,7 @@ module csr_tlu( assign io_dec_tlu_misc_clk_override = mcgc[8]; // @[dec_tlu_ctl.scala 1718:31] assign io_dec_tlu_dec_clk_override = mcgc[7]; // @[dec_tlu_ctl.scala 1719:31] assign io_dec_tlu_lsu_clk_override = mcgc[4]; // @[dec_tlu_ctl.scala 1721:31] + assign io_dec_tlu_bus_clk_override = mcgc[3]; // @[dec_tlu_ctl.scala 1722:31] assign io_dec_tlu_pic_clk_override = mcgc[2]; // @[dec_tlu_ctl.scala 1723:31] assign io_dec_tlu_dccm_clk_override = mcgc[1]; // @[dec_tlu_ctl.scala 1724:31] assign io_dec_tlu_icm_clk_override = mcgc[0]; // @[dec_tlu_ctl.scala 1725:31] @@ -54378,6 +54380,7 @@ module dec_tlu_ctl( output io_dec_tlu_misc_clk_override, output io_dec_tlu_dec_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -54630,6 +54633,7 @@ module dec_tlu_ctl( wire csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 818:15] + wire csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 818:15] wire csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 818:15] @@ -55718,6 +55722,7 @@ module dec_tlu_ctl( .io_dec_tlu_misc_clk_override(csr_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(csr_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(csr_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(csr_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(csr_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(csr_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(csr_io_dec_tlu_icm_clk_override), @@ -56042,6 +56047,7 @@ module dec_tlu_ctl( assign io_dec_tlu_misc_clk_override = csr_io_dec_tlu_misc_clk_override; // @[dec_tlu_ctl.scala 890:40] assign io_dec_tlu_dec_clk_override = csr_io_dec_tlu_dec_clk_override; // @[dec_tlu_ctl.scala 891:40] assign io_dec_tlu_lsu_clk_override = csr_io_dec_tlu_lsu_clk_override; // @[dec_tlu_ctl.scala 893:40] + assign io_dec_tlu_bus_clk_override = csr_io_dec_tlu_bus_clk_override; // @[dec_tlu_ctl.scala 894:40] assign io_dec_tlu_pic_clk_override = csr_io_dec_tlu_pic_clk_override; // @[dec_tlu_ctl.scala 895:40] assign io_dec_tlu_dccm_clk_override = csr_io_dec_tlu_dccm_clk_override; // @[dec_tlu_ctl.scala 896:40] assign io_dec_tlu_icm_clk_override = csr_io_dec_tlu_icm_clk_override; // @[dec_tlu_ctl.scala 897:40] @@ -57940,6 +57946,7 @@ module dec( output [31:0] io_rv_trace_pkt_rv_i_tval_ip, output io_dec_tlu_misc_clk_override, output io_dec_tlu_lsu_clk_override, + output io_dec_tlu_bus_clk_override, output io_dec_tlu_pic_clk_override, output io_dec_tlu_dccm_clk_override, output io_dec_tlu_icm_clk_override, @@ -58485,6 +58492,7 @@ module dec( wire tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dec_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 120:19] + wire tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 120:19] wire tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 120:19] @@ -58941,6 +58949,7 @@ module dec( .io_dec_tlu_misc_clk_override(tlu_io_dec_tlu_misc_clk_override), .io_dec_tlu_dec_clk_override(tlu_io_dec_tlu_dec_clk_override), .io_dec_tlu_lsu_clk_override(tlu_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(tlu_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(tlu_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(tlu_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(tlu_io_dec_tlu_icm_clk_override), @@ -59080,6 +59089,7 @@ module dec( assign io_rv_trace_pkt_rv_i_tval_ip = tlu_io_dec_tlu_mtval_wb1; // @[dec.scala 300:32] assign io_dec_tlu_misc_clk_override = tlu_io_dec_tlu_misc_clk_override; // @[dec.scala 284:35] assign io_dec_tlu_lsu_clk_override = tlu_io_dec_tlu_lsu_clk_override; // @[dec.scala 286:36] + assign io_dec_tlu_bus_clk_override = tlu_io_dec_tlu_bus_clk_override; // @[dec.scala 287:36] assign io_dec_tlu_pic_clk_override = tlu_io_dec_tlu_pic_clk_override; // @[dec.scala 288:36] assign io_dec_tlu_dccm_clk_override = tlu_io_dec_tlu_dccm_clk_override; // @[dec.scala 289:36] assign io_dec_tlu_icm_clk_override = tlu_io_dec_tlu_icm_clk_override; // @[dec.scala 290:36] @@ -80509,6 +80519,625 @@ end // initial end end endmodule +module axi4_to_ahb( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_clk_override, + output io_axi_aw_ready, + input io_axi_aw_valid, + output io_axi_w_ready, + input io_axi_w_valid, + input io_axi_b_ready, + input io_axi_ar_valid +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_2_io_en; // @[lib.scala 368:23] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_5_io_en; // @[lib.scala 368:23] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_6_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_6_io_en; // @[lib.scala 343:22] + wire rvclkhdr_6_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_7_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_7_io_en; // @[lib.scala 343:22] + wire rvclkhdr_7_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_8_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_8_io_en; // @[lib.scala 343:22] + wire rvclkhdr_8_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_9_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_9_io_en; // @[lib.scala 343:22] + wire rvclkhdr_9_io_scan_mode; // @[lib.scala 343:22] + wire ahbm_clk = rvclkhdr_7_io_l1clk; // @[axi4_to_ahb.scala 31:22 axi4_to_ahb.scala 340:12] + reg [2:0] buf_state; // @[axi4_to_ahb.scala 37:45] + wire _T_49 = 3'h0 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_io_l1clk; // @[axi4_to_ahb.scala 57:21 axi4_to_ahb.scala 169:11] + reg wrbuf_vld; // @[axi4_to_ahb.scala 308:51] + reg wrbuf_data_vld; // @[axi4_to_ahb.scala 309:51] + wire wr_cmd_vld = wrbuf_vld & wrbuf_data_vld; // @[axi4_to_ahb.scala 146:27] + wire master_valid = wr_cmd_vld | io_axi_ar_valid; // @[axi4_to_ahb.scala 147:30] + wire _T_101 = 3'h1 == buf_state; // @[Conditional.scala 37:30] + wire _T_136 = 3'h6 == buf_state; // @[Conditional.scala 37:30] + wire _T_175 = 3'h7 == buf_state; // @[Conditional.scala 37:30] + wire _T_186 = 3'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_188 = 3'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_281 = 3'h4 == buf_state; // @[Conditional.scala 37:30] + wire _T_440 = 3'h5 == buf_state; // @[Conditional.scala 37:30] + wire _GEN_1 = _T_440 & io_axi_b_ready; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_281 ? 1'h0 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_20 = _T_188 ? 1'h0 : _GEN_3; // @[Conditional.scala 39:67] + wire _GEN_35 = _T_186 ? 1'h0 : _GEN_20; // @[Conditional.scala 39:67] + wire _GEN_51 = _T_175 ? 1'h0 : _GEN_35; // @[Conditional.scala 39:67] + wire _GEN_69 = _T_136 ? 1'h0 : _GEN_51; // @[Conditional.scala 39:67] + wire _GEN_83 = _T_101 ? 1'h0 : _GEN_69; // @[Conditional.scala 39:67] + wire buf_state_en = _T_49 ? master_valid : _GEN_83; // @[Conditional.scala 40:58] + wire [1:0] _T_14 = wr_cmd_vld ? 2'h3 : 2'h0; // @[axi4_to_ahb.scala 149:20] + wire [2:0] master_opc = {{1'd0}, _T_14}; // @[axi4_to_ahb.scala 149:14] + wire _T_51 = master_opc[2:1] == 2'h1; // @[axi4_to_ahb.scala 175:41] + wire _GEN_8 = _T_281 & _T_51; // @[Conditional.scala 39:67] + wire _GEN_29 = _T_188 ? 1'h0 : _GEN_8; // @[Conditional.scala 39:67] + wire _GEN_46 = _T_186 ? 1'h0 : _GEN_29; // @[Conditional.scala 39:67] + wire _GEN_63 = _T_175 ? 1'h0 : _GEN_46; // @[Conditional.scala 39:67] + wire _GEN_81 = _T_136 ? 1'h0 : _GEN_63; // @[Conditional.scala 39:67] + wire _GEN_97 = _T_101 ? 1'h0 : _GEN_81; // @[Conditional.scala 39:67] + wire buf_write_in = _T_49 ? _T_51 : _GEN_97; // @[Conditional.scala 40:58] + wire [2:0] _T_53 = buf_write_in ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 176:26] + wire _T_103 = master_opc == 3'h0; // @[axi4_to_ahb.scala 189:61] + wire _T_104 = master_valid & _T_103; // @[axi4_to_ahb.scala 189:41] + wire [2:0] _T_106 = _T_104 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 189:26] + wire _T_286 = buf_state_en & io_axi_b_ready; // @[axi4_to_ahb.scala 247:51] + wire _GEN_4 = _T_281 & _T_286; // @[Conditional.scala 39:67] + wire _GEN_26 = _T_188 ? 1'h0 : _GEN_4; // @[Conditional.scala 39:67] + wire _GEN_45 = _T_186 ? 1'h0 : _GEN_26; // @[Conditional.scala 39:67] + wire _GEN_62 = _T_175 ? 1'h0 : _GEN_45; // @[Conditional.scala 39:67] + wire _GEN_66 = _T_136 ? 1'h0 : _GEN_62; // @[Conditional.scala 39:67] + wire _GEN_86 = _T_101 ? 1'h0 : _GEN_66; // @[Conditional.scala 39:67] + wire master_ready = _T_49 | _GEN_86; // @[Conditional.scala 40:58] + wire _T_149 = master_valid & master_ready; // @[axi4_to_ahb.scala 203:82] + wire _T_152 = _T_149 & _T_103; // @[axi4_to_ahb.scala 203:97] + wire [2:0] _T_154 = _T_152 ? 3'h6 : 3'h3; // @[axi4_to_ahb.scala 203:67] + wire _T_287 = ~io_axi_b_ready; // @[axi4_to_ahb.scala 248:42] + wire [2:0] _T_293 = _T_51 ? 3'h2 : 3'h1; // @[axi4_to_ahb.scala 248:99] + wire [2:0] _T_294 = master_valid ? _T_293 : 3'h0; // @[axi4_to_ahb.scala 248:65] + wire [2:0] _T_295 = _T_287 ? 3'h5 : _T_294; // @[axi4_to_ahb.scala 248:26] + wire [2:0] _GEN_5 = _T_281 ? _T_295 : 3'h0; // @[Conditional.scala 39:67] + wire [2:0] _GEN_18 = _T_188 ? 3'h4 : _GEN_5; // @[Conditional.scala 39:67] + wire [2:0] _GEN_34 = _T_186 ? 3'h5 : _GEN_18; // @[Conditional.scala 39:67] + wire [2:0] _GEN_50 = _T_175 ? 3'h3 : _GEN_34; // @[Conditional.scala 39:67] + wire [2:0] _GEN_68 = _T_136 ? _T_154 : _GEN_50; // @[Conditional.scala 39:67] + wire [2:0] _GEN_82 = _T_101 ? _T_106 : _GEN_68; // @[Conditional.scala 39:67] + wire [2:0] buf_nxtstate = _T_49 ? _T_53 : _GEN_82; // @[Conditional.scala 40:58] + wire _T_44 = io_axi_aw_valid & io_axi_aw_ready; // @[axi4_to_ahb.scala 167:57] + wire _T_45 = io_axi_w_valid & io_axi_w_ready; // @[axi4_to_ahb.scala 167:94] + wire _T_46 = _T_44 | _T_45; // @[axi4_to_ahb.scala 167:76] + wire _T_55 = buf_nxtstate == 3'h2; // @[axi4_to_ahb.scala 179:54] + wire _T_56 = buf_state_en & _T_55; // @[axi4_to_ahb.scala 179:38] + wire _T_96 = buf_nxtstate == 3'h1; // @[axi4_to_ahb.scala 184:51] + wire _T_300 = _T_55 | _T_96; // @[axi4_to_ahb.scala 252:62] + wire _T_301 = buf_state_en & _T_300; // @[axi4_to_ahb.scala 252:33] + wire _GEN_9 = _T_281 & _T_301; // @[Conditional.scala 39:67] + wire _GEN_30 = _T_188 ? 1'h0 : _GEN_9; // @[Conditional.scala 39:67] + wire _GEN_47 = _T_186 ? 1'h0 : _GEN_30; // @[Conditional.scala 39:67] + wire _GEN_64 = _T_175 ? 1'h0 : _GEN_47; // @[Conditional.scala 39:67] + wire _GEN_67 = _T_136 ? _T_152 : _GEN_64; // @[Conditional.scala 39:67] + wire _GEN_87 = _T_101 ? master_ready : _GEN_67; // @[Conditional.scala 39:67] + wire buf_wr_en = _T_49 ? buf_state_en : _GEN_87; // @[Conditional.scala 40:58] + wire _GEN_10 = _T_281 & buf_wr_en; // @[Conditional.scala 39:67] + wire _GEN_22 = _T_188 & buf_state_en; // @[Conditional.scala 39:67] + wire _GEN_31 = _T_188 ? 1'h0 : _GEN_10; // @[Conditional.scala 39:67] + wire _GEN_36 = _T_186 ? buf_state_en : _GEN_31; // @[Conditional.scala 39:67] + wire _GEN_39 = _T_186 ? buf_state_en : _GEN_22; // @[Conditional.scala 39:67] + wire _GEN_53 = _T_175 ? buf_state_en : _GEN_39; // @[Conditional.scala 39:67] + wire _GEN_56 = _T_175 ? 1'h0 : _GEN_36; // @[Conditional.scala 39:67] + wire _GEN_70 = _T_136 ? buf_state_en : _GEN_56; // @[Conditional.scala 39:67] + wire _GEN_78 = _T_136 ? buf_wr_en : _GEN_53; // @[Conditional.scala 39:67] + wire _GEN_85 = _T_101 ? buf_state_en : _GEN_78; // @[Conditional.scala 39:67] + wire _GEN_91 = _T_101 ? 1'h0 : _GEN_70; // @[Conditional.scala 39:67] + wire buf_data_wr_en = _T_49 ? _T_56 : _GEN_91; // @[Conditional.scala 40:58] + wire slvbuf_wr_en = _T_49 ? 1'h0 : _GEN_85; // @[Conditional.scala 40:58] + wire wrbuf_en = _T_44 & master_ready; // @[axi4_to_ahb.scala 298:49] + wire wrbuf_data_en = _T_45 & master_ready; // @[axi4_to_ahb.scala 299:52] + wire wrbuf_cmd_sent = _T_149 & _T_51; // @[axi4_to_ahb.scala 300:49] + wire _T_622 = ~wrbuf_en; // @[axi4_to_ahb.scala 301:33] + wire wrbuf_rst = wrbuf_cmd_sent & _T_622; // @[axi4_to_ahb.scala 301:31] + wire _T_624 = ~wrbuf_cmd_sent; // @[axi4_to_ahb.scala 303:36] + wire _T_625 = wrbuf_vld & _T_624; // @[axi4_to_ahb.scala 303:34] + wire _T_626 = ~_T_625; // @[axi4_to_ahb.scala 303:22] + wire _T_629 = wrbuf_data_vld & _T_624; // @[axi4_to_ahb.scala 304:38] + wire _T_630 = ~_T_629; // @[axi4_to_ahb.scala 304:21] + wire _T_636 = wrbuf_en | wrbuf_vld; // @[axi4_to_ahb.scala 308:55] + wire _T_637 = ~wrbuf_rst; // @[axi4_to_ahb.scala 308:91] + wire _T_641 = wrbuf_data_en | wrbuf_data_vld; // @[axi4_to_ahb.scala 309:55] + wire _T_704 = buf_wr_en | slvbuf_wr_en; // @[axi4_to_ahb.scala 334:43] + wire _T_705 = _T_704 | io_clk_override; // @[axi4_to_ahb.scala 334:58] + wire _T_711 = buf_state != 3'h0; // @[axi4_to_ahb.scala 336:50] + wire _T_712 = _T_711 | io_clk_override; // @[axi4_to_ahb.scala 336:60] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + rvclkhdr rvclkhdr_6 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_6_io_l1clk), + .io_clk(rvclkhdr_6_io_clk), + .io_en(rvclkhdr_6_io_en), + .io_scan_mode(rvclkhdr_6_io_scan_mode) + ); + rvclkhdr rvclkhdr_7 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_7_io_l1clk), + .io_clk(rvclkhdr_7_io_clk), + .io_en(rvclkhdr_7_io_en), + .io_scan_mode(rvclkhdr_7_io_scan_mode) + ); + rvclkhdr rvclkhdr_8 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_8_io_l1clk), + .io_clk(rvclkhdr_8_io_clk), + .io_en(rvclkhdr_8_io_en), + .io_scan_mode(rvclkhdr_8_io_scan_mode) + ); + rvclkhdr rvclkhdr_9 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_9_io_l1clk), + .io_clk(rvclkhdr_9_io_clk), + .io_en(rvclkhdr_9_io_en), + .io_scan_mode(rvclkhdr_9_io_scan_mode) + ); + assign io_axi_aw_ready = _T_626 & master_ready; // @[axi4_to_ahb.scala 303:19] + assign io_axi_w_ready = _T_630 & master_ready; // @[axi4_to_ahb.scala 304:18] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = io_bus_clk_en & _T_46; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_2_io_en = _T_44 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_3_io_clk = rvclkhdr_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_45 & master_ready; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = buf_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 370:18] + assign rvclkhdr_5_io_en = buf_data_wr_en & io_bus_clk_en; // @[lib.scala 371:17] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_6_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_6_io_en = io_bus_clk_en & _T_705; // @[lib.scala 345:16] + assign rvclkhdr_6_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_7_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_7_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_7_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_8_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_8_io_en = io_bus_clk_en & io_clk_override; // @[lib.scala 345:16] + assign rvclkhdr_8_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_9_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_9_io_en = io_bus_clk_en & _T_712; // @[lib.scala 345:16] + assign rvclkhdr_9_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[2:0]; + _RAND_1 = {1{`RANDOM}}; + wrbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + wrbuf_data_vld = _RAND_2[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 3'h0; + end + if (reset) begin + wrbuf_vld = 1'h0; + end + if (reset) begin + wrbuf_data_vld = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahbm_clk or posedge reset) begin + if (reset) begin + buf_state <= 3'h0; + end else if (buf_state_en) begin + if (_T_49) begin + if (buf_write_in) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else if (_T_101) begin + if (_T_104) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_136) begin + if (_T_152) begin + buf_state <= 3'h6; + end else begin + buf_state <= 3'h3; + end + end else if (_T_175) begin + buf_state <= 3'h3; + end else if (_T_186) begin + buf_state <= 3'h5; + end else if (_T_188) begin + buf_state <= 3'h4; + end else if (_T_281) begin + if (_T_287) begin + buf_state <= 3'h5; + end else if (master_valid) begin + if (_T_51) begin + buf_state <= 3'h2; + end else begin + buf_state <= 3'h1; + end + end else begin + buf_state <= 3'h0; + end + end else begin + buf_state <= 3'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_vld <= 1'h0; + end else begin + wrbuf_vld <= _T_636 & _T_637; + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + wrbuf_data_vld <= 1'h0; + end else begin + wrbuf_data_vld <= _T_641 & _T_637; + end + end +endmodule +module ahb_to_axi4( + input clock, + input reset, + input io_scan_mode, + input io_bus_clk_en, + input io_axi_aw_ready, + output io_axi_aw_valid, + input io_axi_ar_ready, + output io_axi_ar_valid, + input io_axi_r_valid, + input [1:0] io_axi_r_bits_resp, + output io_ahb_sig_in_hresp +); +`ifdef RANDOMIZE_REG_INIT + reg [31:0] _RAND_0; + reg [31:0] _RAND_1; + reg [31:0] _RAND_2; + reg [31:0] _RAND_3; +`endif // RANDOMIZE_REG_INIT + wire rvclkhdr_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_io_en; // @[lib.scala 343:22] + wire rvclkhdr_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_1_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_1_io_en; // @[lib.scala 343:22] + wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_2_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_2_io_en; // @[lib.scala 343:22] + wire rvclkhdr_2_io_scan_mode; // @[lib.scala 343:22] + wire rvclkhdr_3_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_3_io_en; // @[lib.scala 368:23] + wire rvclkhdr_3_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_4_io_l1clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_clk; // @[lib.scala 368:23] + wire rvclkhdr_4_io_en; // @[lib.scala 368:23] + wire rvclkhdr_4_io_scan_mode; // @[lib.scala 368:23] + wire rvclkhdr_5_io_l1clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_clk; // @[lib.scala 343:22] + wire rvclkhdr_5_io_en; // @[lib.scala 343:22] + wire rvclkhdr_5_io_scan_mode; // @[lib.scala 343:22] + wire ahb_clk = rvclkhdr_io_l1clk; // @[ahb_to_axi4.scala 44:33 ahb_to_axi4.scala 133:31] + reg [1:0] buf_state; // @[Reg.scala 27:20] + wire _T_7 = 2'h0 == buf_state; // @[Conditional.scala 37:30] + wire _T_12 = 2'h1 == buf_state; // @[Conditional.scala 37:30] + wire bus_clk = rvclkhdr_5_io_l1clk; // @[ahb_to_axi4.scala 58:33 ahb_to_axi4.scala 181:27] + reg cmdbuf_vld; // @[ahb_to_axi4.scala 140:61] + wire _T_151 = io_axi_aw_valid & io_axi_aw_ready; // @[ahb_to_axi4.scala 138:67] + wire _T_152 = io_axi_ar_valid & io_axi_ar_ready; // @[ahb_to_axi4.scala 138:105] + wire _T_153 = _T_151 | _T_152; // @[ahb_to_axi4.scala 138:86] + wire _T_154 = ~_T_153; // @[ahb_to_axi4.scala 138:48] + wire cmdbuf_full = cmdbuf_vld & _T_154; // @[ahb_to_axi4.scala 138:46] + wire _T_21 = ~cmdbuf_full; // @[ahb_to_axi4.scala 81:24] + wire _T_22 = _T_21 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 81:37] + wire _T_28 = ~io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 82:38] + wire _T_29 = _T_21 & _T_28; // @[ahb_to_axi4.scala 82:36] + wire _T_30 = 2'h2 == buf_state; // @[Conditional.scala 37:30] + wire _T_36 = _T_28 & _T_21; // @[ahb_to_axi4.scala 87:44] + wire _T_37 = 2'h3 == buf_state; // @[Conditional.scala 37:30] + wire _T_41 = |io_axi_r_bits_resp; // @[ahb_to_axi4.scala 93:68] + wire _GEN_1 = _T_37 & io_axi_r_valid; // @[Conditional.scala 39:67] + wire _GEN_5 = _T_30 ? _T_22 : _GEN_1; // @[Conditional.scala 39:67] + wire _GEN_10 = _T_12 ? _T_22 : _GEN_5; // @[Conditional.scala 39:67] + wire buf_state_en = _T_7 ? 1'h0 : _GEN_10; // @[Conditional.scala 40:58] + wire _T_42 = buf_state_en & _T_41; // @[ahb_to_axi4.scala 93:41] + wire _GEN_2 = _T_37 & buf_state_en; // @[Conditional.scala 39:67] + wire _GEN_3 = _T_37 & _T_42; // @[Conditional.scala 39:67] + wire _GEN_6 = _T_30 & _T_36; // @[Conditional.scala 39:67] + wire _GEN_7 = _T_30 ? 1'h0 : _GEN_2; // @[Conditional.scala 39:67] + wire _GEN_11 = _T_12 ? _T_29 : _GEN_6; // @[Conditional.scala 39:67] + wire _GEN_12 = _T_12 ? 1'h0 : _GEN_7; // @[Conditional.scala 39:67] + wire cmdbuf_wr_en = _T_7 ? 1'h0 : _GEN_11; // @[Conditional.scala 40:58] + wire buf_rdata_en = _T_7 ? 1'h0 : _GEN_12; // @[Conditional.scala 40:58] + reg ahb_hresp_q; // @[ahb_to_axi4.scala 122:60] + reg buf_read_error; // @[ahb_to_axi4.scala 119:60] + wire _T_146 = ~cmdbuf_wr_en; // @[ahb_to_axi4.scala 137:113] + wire _T_147 = _T_153 & _T_146; // @[ahb_to_axi4.scala 137:111] + wire cmdbuf_rst = _T_147 | io_ahb_sig_in_hresp; // @[ahb_to_axi4.scala 137:128] + wire _T_157 = cmdbuf_wr_en | cmdbuf_vld; // @[ahb_to_axi4.scala 140:66] + wire _T_158 = ~cmdbuf_rst; // @[ahb_to_axi4.scala 140:110] + rvclkhdr rvclkhdr ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_io_l1clk), + .io_clk(rvclkhdr_io_clk), + .io_en(rvclkhdr_io_en), + .io_scan_mode(rvclkhdr_io_scan_mode) + ); + rvclkhdr rvclkhdr_1 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_1_io_l1clk), + .io_clk(rvclkhdr_1_io_clk), + .io_en(rvclkhdr_1_io_en), + .io_scan_mode(rvclkhdr_1_io_scan_mode) + ); + rvclkhdr rvclkhdr_2 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_2_io_l1clk), + .io_clk(rvclkhdr_2_io_clk), + .io_en(rvclkhdr_2_io_en), + .io_scan_mode(rvclkhdr_2_io_scan_mode) + ); + rvclkhdr rvclkhdr_3 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_3_io_l1clk), + .io_clk(rvclkhdr_3_io_clk), + .io_en(rvclkhdr_3_io_en), + .io_scan_mode(rvclkhdr_3_io_scan_mode) + ); + rvclkhdr rvclkhdr_4 ( // @[lib.scala 368:23] + .io_l1clk(rvclkhdr_4_io_l1clk), + .io_clk(rvclkhdr_4_io_clk), + .io_en(rvclkhdr_4_io_en), + .io_scan_mode(rvclkhdr_4_io_scan_mode) + ); + rvclkhdr rvclkhdr_5 ( // @[lib.scala 343:22] + .io_l1clk(rvclkhdr_5_io_l1clk), + .io_clk(rvclkhdr_5_io_clk), + .io_en(rvclkhdr_5_io_en), + .io_scan_mode(rvclkhdr_5_io_scan_mode) + ); + assign io_axi_aw_valid = 1'h0; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 157:28] + assign io_axi_ar_valid = cmdbuf_vld; // @[ahb_to_axi4.scala 20:10 ahb_to_axi4.scala 172:28] + assign io_ahb_sig_in_hresp = buf_read_error | ahb_hresp_q; // @[ahb_to_axi4.scala 108:38] + assign rvclkhdr_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_1_io_en = 1'h0; // @[lib.scala 345:16] + assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_2_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_2_io_en = io_bus_clk_en & buf_rdata_en; // @[lib.scala 345:16] + assign rvclkhdr_2_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign rvclkhdr_3_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_3_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_3_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_4_io_clk = rvclkhdr_5_io_l1clk; // @[lib.scala 370:18] + assign rvclkhdr_4_io_en = _T_7 ? 1'h0 : _GEN_11; // @[lib.scala 371:17] + assign rvclkhdr_4_io_scan_mode = io_scan_mode; // @[lib.scala 372:24] + assign rvclkhdr_5_io_clk = clock; // @[lib.scala 344:17] + assign rvclkhdr_5_io_en = io_bus_clk_en; // @[lib.scala 345:16] + assign rvclkhdr_5_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] +`ifdef RANDOMIZE_GARBAGE_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_INVALID_ASSIGN +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_REG_INIT +`define RANDOMIZE +`endif +`ifdef RANDOMIZE_MEM_INIT +`define RANDOMIZE +`endif +`ifndef RANDOM +`define RANDOM $random +`endif +`ifdef RANDOMIZE_MEM_INIT + integer initvar; +`endif +`ifndef SYNTHESIS +`ifdef FIRRTL_BEFORE_INITIAL +`FIRRTL_BEFORE_INITIAL +`endif +initial begin + `ifdef RANDOMIZE + `ifdef INIT_RANDOM + `INIT_RANDOM + `endif + `ifndef VERILATOR + `ifdef RANDOMIZE_DELAY + #`RANDOMIZE_DELAY begin end + `else + #0.002 begin end + `endif + `endif +`ifdef RANDOMIZE_REG_INIT + _RAND_0 = {1{`RANDOM}}; + buf_state = _RAND_0[1:0]; + _RAND_1 = {1{`RANDOM}}; + cmdbuf_vld = _RAND_1[0:0]; + _RAND_2 = {1{`RANDOM}}; + ahb_hresp_q = _RAND_2[0:0]; + _RAND_3 = {1{`RANDOM}}; + buf_read_error = _RAND_3[0:0]; +`endif // RANDOMIZE_REG_INIT + if (reset) begin + buf_state = 2'h0; + end + if (reset) begin + cmdbuf_vld = 1'h0; + end + if (reset) begin + ahb_hresp_q = 1'h0; + end + if (reset) begin + buf_read_error = 1'h0; + end + `endif // RANDOMIZE +end // initial +`ifdef FIRRTL_AFTER_INITIAL +`FIRRTL_AFTER_INITIAL +`endif +`endif // SYNTHESIS + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_state <= 2'h0; + end else if (buf_state_en) begin + if (_T_7) begin + buf_state <= 2'h2; + end else if (_T_12) begin + buf_state <= 2'h0; + end else if (_T_30) begin + if (io_ahb_sig_in_hresp) begin + buf_state <= 2'h0; + end else begin + buf_state <= 2'h3; + end + end else begin + buf_state <= 2'h0; + end + end + end + always @(posedge bus_clk or posedge reset) begin + if (reset) begin + cmdbuf_vld <= 1'h0; + end else begin + cmdbuf_vld <= _T_157 & _T_158; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + ahb_hresp_q <= 1'h0; + end else begin + ahb_hresp_q <= io_ahb_sig_in_hresp; + end + end + always @(posedge ahb_clk or posedge reset) begin + if (reset) begin + buf_read_error <= 1'h0; + end else if (_T_7) begin + buf_read_error <= 1'h0; + end else if (_T_12) begin + buf_read_error <= 1'h0; + end else if (_T_30) begin + buf_read_error <= 1'h0; + end else begin + buf_read_error <= _GEN_3; + end + end +endmodule module quasar( input clock, input reset, @@ -80900,6 +81529,7 @@ module quasar( wire [31:0] dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 73:19] wire dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 73:19] wire dec_io_dec_tlu_lsu_clk_override; // @[quasar.scala 73:19] + wire dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 73:19] wire dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 73:19] wire dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 73:19] wire dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 73:19] @@ -81466,6 +82096,50 @@ module quasar( wire rvclkhdr_1_io_clk; // @[lib.scala 343:22] wire rvclkhdr_1_io_en; // @[lib.scala 343:22] wire rvclkhdr_1_io_scan_mode; // @[lib.scala 343:22] + wire axi4_to_ahb_clock; // @[quasar.scala 242:32] + wire axi4_to_ahb_reset; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_scan_mode; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_bus_clk_en; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_clk_override; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_aw_ready; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_aw_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_w_ready; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_w_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_b_ready; // @[quasar.scala 242:32] + wire axi4_to_ahb_io_axi_ar_valid; // @[quasar.scala 242:32] + wire axi4_to_ahb_1_clock; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_reset; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_scan_mode; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_bus_clk_en; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_clk_override; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_aw_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_aw_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_w_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_w_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_b_ready; // @[quasar.scala 243:33] + wire axi4_to_ahb_1_io_axi_ar_valid; // @[quasar.scala 243:33] + wire axi4_to_ahb_2_clock; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_reset; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_scan_mode; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_bus_clk_en; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_clk_override; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_aw_ready; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_aw_valid; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_w_ready; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_w_valid; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_b_ready; // @[quasar.scala 244:33] + wire axi4_to_ahb_2_io_axi_ar_valid; // @[quasar.scala 244:33] + wire ahb_to_axi4_clock; // @[quasar.scala 245:33] + wire ahb_to_axi4_reset; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_scan_mode; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_bus_clk_en; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_axi_aw_ready; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_axi_aw_valid; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_axi_ar_ready; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_axi_ar_valid; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_axi_r_valid; // @[quasar.scala 245:33] + wire [1:0] ahb_to_axi4_io_axi_r_bits_resp; // @[quasar.scala 245:33] + wire ahb_to_axi4_io_ahb_sig_in_hresp; // @[quasar.scala 245:33] wire _T_1 = dbg_io_dbg_core_rst_l; // @[quasar.scala 80:67] wire _T_2 = _T_1 | io_scan_mode; // @[quasar.scala 80:70] wire _T_5 = ~dec_io_dec_pause_state_cg; // @[quasar.scala 81:23] @@ -81701,6 +82375,7 @@ module quasar( .io_rv_trace_pkt_rv_i_tval_ip(dec_io_rv_trace_pkt_rv_i_tval_ip), .io_dec_tlu_misc_clk_override(dec_io_dec_tlu_misc_clk_override), .io_dec_tlu_lsu_clk_override(dec_io_dec_tlu_lsu_clk_override), + .io_dec_tlu_bus_clk_override(dec_io_dec_tlu_bus_clk_override), .io_dec_tlu_pic_clk_override(dec_io_dec_tlu_pic_clk_override), .io_dec_tlu_dccm_clk_override(dec_io_dec_tlu_dccm_clk_override), .io_dec_tlu_icm_clk_override(dec_io_dec_tlu_icm_clk_override), @@ -82282,76 +82957,128 @@ module quasar( .io_en(rvclkhdr_1_io_en), .io_scan_mode(rvclkhdr_1_io_scan_mode) ); - assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 242:14] - assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 242:14] - assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 242:14] - assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 242:14] - assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 242:14] - assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 242:14] - assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 242:14] - assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 242:14] - assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 242:14] - assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 242:14] - assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 245:14] - assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 245:14] - assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 245:14] - assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 245:14] - assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 189:17] - assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 189:17] - assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 189:17] - assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 189:17] - assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 189:17] - assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 189:17] - assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 189:17] - assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 189:17] - assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 189:17] - assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 189:17] - assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 189:17] - assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 246:14] - assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 246:14] - assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 246:14] - assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 246:14] - assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 246:14] - assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 246:14] - assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 246:14] - assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 246:14] - assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 246:14] - assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 246:14] + axi4_to_ahb axi4_to_ahb ( // @[quasar.scala 242:32] + .clock(axi4_to_ahb_clock), + .reset(axi4_to_ahb_reset), + .io_scan_mode(axi4_to_ahb_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_io_axi_aw_valid), + .io_axi_w_ready(axi4_to_ahb_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_io_axi_w_valid), + .io_axi_b_ready(axi4_to_ahb_io_axi_b_ready), + .io_axi_ar_valid(axi4_to_ahb_io_axi_ar_valid) + ); + axi4_to_ahb axi4_to_ahb_1 ( // @[quasar.scala 243:33] + .clock(axi4_to_ahb_1_clock), + .reset(axi4_to_ahb_1_reset), + .io_scan_mode(axi4_to_ahb_1_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_1_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_1_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_1_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_1_io_axi_aw_valid), + .io_axi_w_ready(axi4_to_ahb_1_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_1_io_axi_w_valid), + .io_axi_b_ready(axi4_to_ahb_1_io_axi_b_ready), + .io_axi_ar_valid(axi4_to_ahb_1_io_axi_ar_valid) + ); + axi4_to_ahb axi4_to_ahb_2 ( // @[quasar.scala 244:33] + .clock(axi4_to_ahb_2_clock), + .reset(axi4_to_ahb_2_reset), + .io_scan_mode(axi4_to_ahb_2_io_scan_mode), + .io_bus_clk_en(axi4_to_ahb_2_io_bus_clk_en), + .io_clk_override(axi4_to_ahb_2_io_clk_override), + .io_axi_aw_ready(axi4_to_ahb_2_io_axi_aw_ready), + .io_axi_aw_valid(axi4_to_ahb_2_io_axi_aw_valid), + .io_axi_w_ready(axi4_to_ahb_2_io_axi_w_ready), + .io_axi_w_valid(axi4_to_ahb_2_io_axi_w_valid), + .io_axi_b_ready(axi4_to_ahb_2_io_axi_b_ready), + .io_axi_ar_valid(axi4_to_ahb_2_io_axi_ar_valid) + ); + ahb_to_axi4 ahb_to_axi4 ( // @[quasar.scala 245:33] + .clock(ahb_to_axi4_clock), + .reset(ahb_to_axi4_reset), + .io_scan_mode(ahb_to_axi4_io_scan_mode), + .io_bus_clk_en(ahb_to_axi4_io_bus_clk_en), + .io_axi_aw_ready(ahb_to_axi4_io_axi_aw_ready), + .io_axi_aw_valid(ahb_to_axi4_io_axi_aw_valid), + .io_axi_ar_ready(ahb_to_axi4_io_axi_ar_ready), + .io_axi_ar_valid(ahb_to_axi4_io_axi_ar_valid), + .io_axi_r_valid(ahb_to_axi4_io_axi_r_valid), + .io_axi_r_bits_resp(ahb_to_axi4_io_axi_r_bits_resp), + .io_ahb_sig_in_hresp(ahb_to_axi4_io_ahb_sig_in_hresp) + ); + assign io_lsu_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_aw_bits_id = lsu_io_axi_aw_bits_id; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_aw_bits_addr = lsu_io_axi_aw_bits_addr; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_aw_bits_region = lsu_io_axi_aw_bits_region; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_aw_bits_size = lsu_io_axi_aw_bits_size; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_aw_bits_cache = lsu_io_axi_aw_bits_cache; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_w_bits_data = lsu_io_axi_w_bits_data; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_w_bits_strb = lsu_io_axi_w_bits_strb; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_bits_id = lsu_io_axi_ar_bits_id; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_bits_addr = lsu_io_axi_ar_bits_addr; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_bits_region = lsu_io_axi_ar_bits_region; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_bits_size = lsu_io_axi_ar_bits_size; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_lsu_axi_ar_bits_cache = lsu_io_axi_ar_bits_cache; // @[quasar.scala 275:25 quasar.scala 285:27] + assign io_ifu_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 274:25 quasar.scala 284:27] + assign io_ifu_axi_ar_bits_id = ifu_io_ifu_ar_bits_id; // @[quasar.scala 274:25 quasar.scala 284:27] + assign io_ifu_axi_ar_bits_addr = ifu_io_ifu_ar_bits_addr; // @[quasar.scala 274:25 quasar.scala 284:27] + assign io_ifu_axi_ar_bits_region = ifu_io_ifu_ar_bits_region; // @[quasar.scala 274:25 quasar.scala 284:27] + assign io_sb_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_aw_bits_addr = dbg_io_sb_axi_aw_bits_addr; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_aw_bits_region = dbg_io_sb_axi_aw_bits_region; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_aw_bits_size = dbg_io_sb_axi_aw_bits_size; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_w_bits_data = dbg_io_sb_axi_w_bits_data; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_w_bits_strb = dbg_io_sb_axi_w_bits_strb; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_ar_bits_addr = dbg_io_sb_axi_ar_bits_addr; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_ar_bits_region = dbg_io_sb_axi_ar_bits_region; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_sb_axi_ar_bits_size = dbg_io_sb_axi_ar_bits_size; // @[quasar.scala 273:21 quasar.scala 283:27] + assign io_dma_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_w_ready = dma_ctrl_io_dma_axi_w_ready; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_b_valid = dma_ctrl_io_dma_axi_b_valid; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_b_bits_resp = dma_ctrl_io_dma_axi_b_bits_resp; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_b_bits_id = dma_ctrl_io_dma_axi_b_bits_id; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_r_bits_id = dma_ctrl_io_dma_axi_r_bits_id; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_r_bits_data = dma_ctrl_io_dma_axi_r_bits_data; // @[quasar.scala 272:16 quasar.scala 282:27] + assign io_dma_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 272:16 quasar.scala 282:27] assign io_core_rst_l = reset & _T_2; // @[quasar.scala 80:17] - assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 221:19] - assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 221:19] - assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 224:24] - assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 225:23] - assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 226:31] - assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 227:21] - assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 228:24] - assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 229:20] - assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 230:26] - assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 231:25] - assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 232:24] - assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 233:25] - assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 234:23] - assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 235:23] - assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 236:23] - assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 237:23] - assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 239:11] - assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 239:11] - assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 239:11] - assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 239:11] - assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 239:11] - assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 239:11] - assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 239:11] - assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 239:11] + assign io_rv_trace_pkt_rv_i_valid_ip = dec_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_insn_ip = dec_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_address_ip = dec_io_rv_trace_pkt_rv_i_address_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_exception_ip = dec_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = dec_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = dec_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar.scala 220:19] + assign io_rv_trace_pkt_rv_i_tval_ip = dec_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar.scala 220:19] + assign io_dccm_clk_override = dec_io_dec_tlu_dccm_clk_override; // @[quasar.scala 223:24] + assign io_icm_clk_override = dec_io_dec_tlu_icm_clk_override; // @[quasar.scala 224:23] + assign io_dec_tlu_core_ecc_disable = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_core_ecc_disable; // @[quasar.scala 225:31] + assign io_o_cpu_halt_ack = dec_io_o_cpu_halt_ack; // @[quasar.scala 226:21] + assign io_o_cpu_halt_status = dec_io_o_cpu_halt_status; // @[quasar.scala 227:24] + assign io_o_cpu_run_ack = dec_io_o_cpu_run_ack; // @[quasar.scala 228:20] + assign io_o_debug_mode_status = dec_io_o_debug_mode_status; // @[quasar.scala 229:26] + assign io_mpc_debug_halt_ack = dec_io_mpc_debug_halt_ack; // @[quasar.scala 230:25] + assign io_mpc_debug_run_ack = dec_io_mpc_debug_run_ack; // @[quasar.scala 231:24] + assign io_debug_brkpt_status = dec_io_debug_brkpt_status; // @[quasar.scala 232:25] + assign io_dec_tlu_perfcnt0 = dec_io_dec_tlu_perfcnt0; // @[quasar.scala 233:23] + assign io_dec_tlu_perfcnt1 = dec_io_dec_tlu_perfcnt1; // @[quasar.scala 234:23] + assign io_dec_tlu_perfcnt2 = dec_io_dec_tlu_perfcnt2; // @[quasar.scala 235:23] + assign io_dec_tlu_perfcnt3 = dec_io_dec_tlu_perfcnt3; // @[quasar.scala 236:23] + assign io_dccm_wren = lsu_io_dccm_wren; // @[quasar.scala 238:11] + assign io_dccm_rden = lsu_io_dccm_rden; // @[quasar.scala 238:11] + assign io_dccm_wr_addr_lo = lsu_io_dccm_wr_addr_lo; // @[quasar.scala 238:11] + assign io_dccm_wr_addr_hi = lsu_io_dccm_wr_addr_hi; // @[quasar.scala 238:11] + assign io_dccm_rd_addr_lo = lsu_io_dccm_rd_addr_lo; // @[quasar.scala 238:11] + assign io_dccm_rd_addr_hi = lsu_io_dccm_rd_addr_hi; // @[quasar.scala 238:11] + assign io_dccm_wr_data_lo = lsu_io_dccm_wr_data_lo; // @[quasar.scala 238:11] + assign io_dccm_wr_data_hi = lsu_io_dccm_wr_data_hi; // @[quasar.scala 238:11] assign io_ic_rw_addr = ifu_io_ic_rw_addr; // @[quasar.scala 101:13] assign io_ic_tag_valid = ifu_io_ic_tag_valid; // @[quasar.scala 101:13] assign io_ic_wr_en = ifu_io_ic_wr_en; // @[quasar.scala 101:13] @@ -82423,11 +83150,11 @@ module quasar( assign ifu_io_ic_eccerr = io_ic_eccerr; // @[quasar.scala 101:13] assign ifu_io_ic_rd_hit = io_ic_rd_hit; // @[quasar.scala 101:13] assign ifu_io_ic_tag_perr = io_ic_tag_perr; // @[quasar.scala 101:13] - assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 245:14] - assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 245:14] - assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 245:14] - assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 245:14] - assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 245:14] + assign ifu_io_ifu_ar_ready = io_ifu_axi_ar_ready; // @[quasar.scala 257:28 quasar.scala 284:27] + assign ifu_io_ifu_r_valid = io_ifu_axi_r_valid; // @[quasar.scala 257:28 quasar.scala 284:27] + assign ifu_io_ifu_r_bits_id = io_ifu_axi_r_bits_id; // @[quasar.scala 257:28 quasar.scala 284:27] + assign ifu_io_ifu_r_bits_data = io_ifu_axi_r_bits_data; // @[quasar.scala 257:28 quasar.scala 284:27] + assign ifu_io_ifu_r_bits_resp = io_ifu_axi_r_bits_resp; // @[quasar.scala 257:28 quasar.scala 284:27] assign ifu_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 99:25] assign ifu_io_ifu_dma_dma_ifc_dma_iccm_stall_any = dma_ctrl_io_ifu_dma_dma_ifc_dma_iccm_stall_any; // @[quasar.scala 100:18] assign ifu_io_ifu_dma_dma_mem_ctl_dma_iccm_req = dma_ctrl_io_ifu_dma_dma_mem_ctl_dma_iccm_req; // @[quasar.scala 100:18] @@ -82552,10 +83279,10 @@ module quasar( assign dec_io_dec_dma_tlu_dma_dma_pmu_any_write = dma_ctrl_io_dec_dma_tlu_dma_dma_pmu_any_write; // @[quasar.scala 126:18] assign dec_io_dec_dma_tlu_dma_dma_dccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_dccm_stall_any; // @[quasar.scala 126:18] assign dec_io_dec_dma_tlu_dma_dma_iccm_stall_any = dma_ctrl_io_dec_dma_tlu_dma_dma_iccm_stall_any; // @[quasar.scala 126:18] - assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 219:28] - assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 219:28] - assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 219:28] - assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 219:28] + assign dec_io_dec_pic_pic_claimid = pic_ctrl_inst_io_dec_pic_pic_claimid; // @[quasar.scala 218:28] + assign dec_io_dec_pic_pic_pl = pic_ctrl_inst_io_dec_pic_pic_pl; // @[quasar.scala 218:28] + assign dec_io_dec_pic_mhwakeup = pic_ctrl_inst_io_dec_pic_mhwakeup; // @[quasar.scala 218:28] + assign dec_io_dec_pic_mexintpend = pic_ctrl_inst_io_dec_pic_mexintpend; // @[quasar.scala 218:28] assign dbg_clock = clock; assign dbg_reset = io_core_rst_l; // @[quasar.scala 177:13] assign dbg_io_core_dbg_rddata = dma_ctrl_io_dma_dbg_cmd_done ? dma_ctrl_io_dma_dbg_rddata : dec_io_dec_dbg_rddata; // @[quasar.scala 178:26] @@ -82569,19 +83296,19 @@ module quasar( assign dbg_io_dmi_reg_addr = io_dmi_reg_addr; // @[quasar.scala 186:23] assign dbg_io_dmi_reg_wr_en = io_dmi_reg_wr_en; // @[quasar.scala 187:24] assign dbg_io_dmi_reg_wdata = io_dmi_reg_wdata; // @[quasar.scala 188:24] - assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 189:17] - assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 189:17] - assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 203:26] - assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 190:25] - assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 191:20] - assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 192:23] - assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 193:20] + assign dbg_io_sb_axi_aw_ready = io_sb_axi_aw_ready; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_w_ready = io_sb_axi_w_ready; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_b_valid = io_sb_axi_b_valid; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_b_bits_resp = io_sb_axi_b_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_ar_ready = io_sb_axi_ar_ready; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_r_valid = io_sb_axi_r_valid; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_r_bits_data = io_sb_axi_r_bits_data; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_sb_axi_r_bits_resp = io_sb_axi_r_bits_resp; // @[quasar.scala 263:27 quasar.scala 283:27] + assign dbg_io_dbg_dma_io_dma_dbg_ready = dma_ctrl_io_dbg_dma_io_dma_dbg_ready; // @[quasar.scala 202:26] + assign dbg_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 189:25] + assign dbg_io_dbg_rst_l = io_dbg_rst_l; // @[quasar.scala 190:20] + assign dbg_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 191:23] + assign dbg_io_scan_mode = io_scan_mode; // @[quasar.scala 192:20] assign exu_clock = clock; assign exu_reset = io_core_rst_l; // @[quasar.scala 153:13] assign exu_io_scan_mode = io_scan_mode; // @[quasar.scala 154:20] @@ -82660,24 +83387,24 @@ module quasar( assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_addr = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_addr; // @[quasar.scala 172:18] assign lsu_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata = dma_ctrl_io_lsu_dma_dma_dccm_ctl_dma_mem_wdata; // @[quasar.scala 172:18] assign lsu_io_lsu_dma_dma_mem_tag = dma_ctrl_io_lsu_dma_dma_mem_tag; // @[quasar.scala 172:18] - assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 218:28] + assign lsu_io_lsu_pic_picm_rd_data = pic_ctrl_inst_io_lsu_pic_picm_rd_data; // @[quasar.scala 217:28] assign lsu_io_lsu_exu_exu_lsu_rs1_d = exu_io_lsu_exu_exu_lsu_rs1_d; // @[quasar.scala 164:18] assign lsu_io_lsu_exu_exu_lsu_rs2_d = exu_io_lsu_exu_exu_lsu_rs2_d; // @[quasar.scala 164:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_external_ldfwd_disable; // @[quasar.scala 123:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_wb_coalescing_disable; // @[quasar.scala 123:18] assign lsu_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable = dec_io_lsu_dec_tlu_busbuff_dec_tlu_sideeffect_posted_disable; // @[quasar.scala 123:18] - assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 239:11] - assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 239:11] - assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 242:14] - assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 242:14] - assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 242:14] - assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 242:14] - assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 242:14] - assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 242:14] - assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 242:14] - assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 242:14] - assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 242:14] - assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 242:14] + assign lsu_io_dccm_rd_data_lo = io_dccm_rd_data_lo; // @[quasar.scala 238:11] + assign lsu_io_dccm_rd_data_hi = io_dccm_rd_data_hi; // @[quasar.scala 238:11] + assign lsu_io_axi_aw_ready = io_lsu_axi_aw_ready; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_w_ready = io_lsu_axi_w_ready; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_b_valid = io_lsu_axi_b_valid; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_b_bits_resp = io_lsu_axi_b_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_b_bits_id = io_lsu_axi_b_bits_id; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_ar_ready = io_lsu_axi_ar_ready; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_r_valid = io_lsu_axi_r_valid; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_r_bits_id = io_lsu_axi_r_bits_id; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_r_bits_data = io_lsu_axi_r_bits_data; // @[quasar.scala 250:28 quasar.scala 285:27] + assign lsu_io_axi_r_bits_resp = io_lsu_axi_r_bits_resp; // @[quasar.scala 250:28 quasar.scala 285:27] assign lsu_io_dec_tlu_flush_lower_r = dec_io_dec_exu_tlu_exu_dec_tlu_flush_lower_r; // @[quasar.scala 160:32] assign lsu_io_dec_tlu_i0_kill_writeb_r = dec_io_dec_tlu_i0_kill_writeb_r; // @[quasar.scala 161:35] assign lsu_io_dec_tlu_force_halt = dec_io_ifu_dec_dec_mem_ctrl_dec_tlu_force_halt; // @[quasar.scala 162:29] @@ -82719,52 +83446,52 @@ module quasar( assign lsu_io_scan_mode = io_scan_mode; // @[quasar.scala 173:20] assign lsu_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 174:19] assign pic_ctrl_inst_clock = clock; - assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 213:23] - assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 212:30] - assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 214:29] - assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 215:31] - assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 216:33] - assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 217:34] - assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 218:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 219:28] - assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 219:28] + assign pic_ctrl_inst_reset = io_core_rst_l; // @[quasar.scala 212:23] + assign pic_ctrl_inst_io_scan_mode = io_scan_mode; // @[quasar.scala 211:30] + assign pic_ctrl_inst_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 213:29] + assign pic_ctrl_inst_io_active_clk = rvclkhdr_1_io_l1clk; // @[quasar.scala 214:31] + assign pic_ctrl_inst_io_clk_override = dec_io_dec_tlu_pic_clk_override; // @[quasar.scala 215:33] + assign pic_ctrl_inst_io_extintsrc_req = {{1'd0}, io_extintsrc_req}; // @[quasar.scala 216:34] + assign pic_ctrl_inst_io_lsu_pic_picm_wren = lsu_io_lsu_pic_picm_wren; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rden = lsu_io_lsu_pic_picm_rden; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_lsu_pic_picm_mken = lsu_io_lsu_pic_picm_mken; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_lsu_pic_picm_rdaddr = lsu_io_lsu_pic_picm_rdaddr; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wraddr = lsu_io_lsu_pic_picm_wraddr; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_lsu_pic_picm_wr_data = lsu_io_lsu_pic_picm_wr_data; // @[quasar.scala 217:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meicurpl = dec_io_dec_pic_dec_tlu_meicurpl; // @[quasar.scala 218:28] + assign pic_ctrl_inst_io_dec_pic_dec_tlu_meipt = dec_io_dec_pic_dec_tlu_meipt; // @[quasar.scala 218:28] assign dma_ctrl_clock = clock; - assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 197:18] - assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 198:24] - assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 199:30] - assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 200:28] - assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 201:25] - assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 204:28] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 202:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 202:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 202:23] - assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 202:23] - assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 202:23] - assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 203:26] + assign dma_ctrl_reset = io_core_rst_l; // @[quasar.scala 196:18] + assign dma_ctrl_io_free_clk = rvclkhdr_io_l1clk; // @[quasar.scala 197:24] + assign dma_ctrl_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 198:30] + assign dma_ctrl_io_clk_override = dec_io_dec_tlu_misc_clk_override; // @[quasar.scala 199:28] + assign dma_ctrl_io_scan_mode = io_scan_mode; // @[quasar.scala 200:25] + assign dma_ctrl_io_dbg_cmd_size = dbg_io_dbg_cmd_size; // @[quasar.scala 203:28] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_valid = dbg_io_dbg_dma_dbg_ib_dbg_cmd_valid; // @[quasar.scala 201:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_write = dbg_io_dbg_dma_dbg_ib_dbg_cmd_write; // @[quasar.scala 201:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_type = dbg_io_dbg_dma_dbg_ib_dbg_cmd_type; // @[quasar.scala 201:23] + assign dma_ctrl_io_dbg_dma_dbg_ib_dbg_cmd_addr = dbg_io_dbg_dma_dbg_ib_dbg_cmd_addr; // @[quasar.scala 201:23] + assign dma_ctrl_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata = dbg_io_dbg_dma_dbg_dctl_dbg_cmd_wrdata; // @[quasar.scala 201:23] + assign dma_ctrl_io_dbg_dma_io_dbg_dma_bubble = dbg_io_dbg_dma_io_dbg_dma_bubble; // @[quasar.scala 202:26] assign dma_ctrl_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty = dec_io_dec_dma_tlu_dma_dec_tlu_dma_qos_prty; // @[quasar.scala 126:18] - assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 205:31] - assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 209:34] - assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 206:29] - assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 207:30] - assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 208:26] - assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 246:14] - assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 246:14] + assign dma_ctrl_io_iccm_dma_rvalid = ifu_io_iccm_dma_rvalid; // @[quasar.scala 204:31] + assign dma_ctrl_io_iccm_dma_ecc_error = ifu_io_iccm_dma_ecc_error; // @[quasar.scala 208:34] + assign dma_ctrl_io_iccm_dma_rtag = ifu_io_iccm_dma_rtag; // @[quasar.scala 205:29] + assign dma_ctrl_io_iccm_dma_rdata = ifu_io_iccm_dma_rdata; // @[quasar.scala 206:30] + assign dma_ctrl_io_iccm_ready = ifu_io_iccm_ready; // @[quasar.scala 207:26] + assign dma_ctrl_io_dma_axi_aw_valid = io_dma_axi_aw_valid; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_id = io_dma_axi_aw_bits_id; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_addr = io_dma_axi_aw_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_aw_bits_size = io_dma_axi_aw_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_valid = io_dma_axi_w_valid; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_bits_data = io_dma_axi_w_bits_data; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_w_bits_strb = io_dma_axi_w_bits_strb; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_b_ready = io_dma_axi_b_ready; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_valid = io_dma_axi_ar_valid; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_id = io_dma_axi_ar_bits_id; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_addr = io_dma_axi_ar_bits_addr; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_ar_bits_size = io_dma_axi_ar_bits_size; // @[quasar.scala 269:28 quasar.scala 282:27] + assign dma_ctrl_io_dma_axi_r_ready = io_dma_axi_r_ready; // @[quasar.scala 269:28 quasar.scala 282:27] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rvalid; // @[quasar.scala 172:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_ecc_error; // @[quasar.scala 172:18] assign dma_ctrl_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag = lsu_io_lsu_dma_dma_dccm_ctl_dccm_dma_rtag; // @[quasar.scala 172:18] @@ -82776,6 +83503,41 @@ module quasar( assign rvclkhdr_1_io_clk = clock; // @[lib.scala 344:17] assign rvclkhdr_1_io_en = _T_6 | dec_io_dec_tlu_misc_clk_override; // @[lib.scala 345:16] assign rvclkhdr_1_io_scan_mode = io_scan_mode; // @[lib.scala 346:23] + assign axi4_to_ahb_clock = clock; + assign axi4_to_ahb_reset = reset; + assign axi4_to_ahb_io_scan_mode = io_scan_mode; // @[quasar.scala 260:33] + assign axi4_to_ahb_io_bus_clk_en = io_dbg_bus_clk_en; // @[quasar.scala 261:34] + assign axi4_to_ahb_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 262:36] + assign axi4_to_ahb_io_axi_aw_valid = dbg_io_sb_axi_aw_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_w_valid = dbg_io_sb_axi_w_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_b_ready = 1'h1; // @[quasar.scala 263:27] + assign axi4_to_ahb_io_axi_ar_valid = dbg_io_sb_axi_ar_valid; // @[quasar.scala 263:27] + assign axi4_to_ahb_1_clock = clock; + assign axi4_to_ahb_1_reset = reset; + assign axi4_to_ahb_1_io_scan_mode = io_scan_mode; // @[quasar.scala 254:34] + assign axi4_to_ahb_1_io_bus_clk_en = io_ifu_bus_clk_en; // @[quasar.scala 255:35] + assign axi4_to_ahb_1_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 256:37] + assign axi4_to_ahb_1_io_axi_aw_valid = 1'h0; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_w_valid = 1'h0; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_b_ready = 1'h0; // @[quasar.scala 257:28] + assign axi4_to_ahb_1_io_axi_ar_valid = ifu_io_ifu_ar_valid; // @[quasar.scala 257:28] + assign axi4_to_ahb_2_clock = clock; + assign axi4_to_ahb_2_reset = reset; + assign axi4_to_ahb_2_io_scan_mode = io_scan_mode; // @[quasar.scala 247:34] + assign axi4_to_ahb_2_io_bus_clk_en = io_lsu_bus_clk_en; // @[quasar.scala 248:35] + assign axi4_to_ahb_2_io_clk_override = dec_io_dec_tlu_bus_clk_override; // @[quasar.scala 249:37] + assign axi4_to_ahb_2_io_axi_aw_valid = lsu_io_axi_aw_valid; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_w_valid = lsu_io_axi_w_valid; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_b_ready = 1'h1; // @[quasar.scala 250:28] + assign axi4_to_ahb_2_io_axi_ar_valid = lsu_io_axi_ar_valid; // @[quasar.scala 250:28] + assign ahb_to_axi4_clock = clock; + assign ahb_to_axi4_reset = reset; + assign ahb_to_axi4_io_scan_mode = io_scan_mode; // @[quasar.scala 266:34] + assign ahb_to_axi4_io_bus_clk_en = io_dma_bus_clk_en; // @[quasar.scala 267:35] + assign ahb_to_axi4_io_axi_aw_ready = dma_ctrl_io_dma_axi_aw_ready; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_axi_ar_ready = dma_ctrl_io_dma_axi_ar_ready; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_axi_r_valid = dma_ctrl_io_dma_axi_r_valid; // @[quasar.scala 269:28] + assign ahb_to_axi4_io_axi_r_bits_resp = dma_ctrl_io_dma_axi_r_bits_resp; // @[quasar.scala 269:28] endmodule module quasar_wrapper( input clock, @@ -83430,120 +84192,120 @@ module quasar_wrapper( .io_soft_int(core_io_soft_int), .io_scan_mode(core_io_scan_mode) ); - assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 103:19] - assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 103:19] - assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:19] - assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:19] - assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:18] - assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:18] - assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 106:19] - assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 106:19] - assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 161:23] - assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 162:23] - assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 163:23] - assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 164:23] + assign io_lsu_brg_aw_valid = core_io_lsu_axi_aw_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_id = core_io_lsu_axi_aw_bits_id; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_addr = core_io_lsu_axi_aw_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_region = core_io_lsu_axi_aw_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_size = core_io_lsu_axi_aw_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_cache = core_io_lsu_axi_aw_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_valid = core_io_lsu_axi_w_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_data = core_io_lsu_axi_w_bits_data; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_strb = core_io_lsu_axi_w_bits_strb; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_valid = core_io_lsu_axi_ar_valid; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_id = core_io_lsu_axi_ar_bits_id; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_addr = core_io_lsu_axi_ar_bits_addr; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_region = core_io_lsu_axi_ar_bits_region; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_size = core_io_lsu_axi_ar_bits_size; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_cache = core_io_lsu_axi_ar_bits_cache; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 104:21] + assign io_lsu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 104:21] + assign io_ifu_brg_aw_valid = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_id = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_addr = 32'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_region = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_size = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_burst = 2'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_cache = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_valid = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_data = 64'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_strb = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_w_bits_last = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_b_ready = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_valid = core_io_ifu_axi_ar_valid; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_id = core_io_ifu_axi_ar_bits_id; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_addr = core_io_ifu_axi_ar_bits_addr; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_region = core_io_ifu_axi_ar_bits_region; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_size = 3'h3; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_cache = 4'hf; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 105:21] + assign io_ifu_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 105:21] + assign io_sb_brg_aw_valid = core_io_sb_axi_aw_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_addr = core_io_sb_axi_aw_bits_addr; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_region = core_io_sb_axi_aw_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_size = core_io_sb_axi_aw_bits_size; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_cache = 4'hf; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_aw_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_valid = core_io_sb_axi_w_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_data = core_io_sb_axi_w_bits_data; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_strb = core_io_sb_axi_w_bits_strb; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_w_bits_last = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_b_ready = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_valid = core_io_sb_axi_ar_valid; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_id = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_addr = core_io_sb_axi_ar_bits_addr; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_region = core_io_sb_axi_ar_bits_region; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_len = 8'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_size = core_io_sb_axi_ar_bits_size; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_burst = 2'h1; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_lock = 1'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_cache = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_prot = 3'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_ar_bits_qos = 4'h0; // @[quasar_wrapper.scala 106:21] + assign io_sb_brg_r_ready = 1'h1; // @[quasar_wrapper.scala 106:21] + assign io_dma_brg_aw_ready = core_io_dma_axi_aw_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_w_ready = core_io_dma_axi_w_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_valid = core_io_dma_axi_b_valid; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_resp = core_io_dma_axi_b_bits_resp; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_b_bits_id = core_io_dma_axi_b_bits_id; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_ar_ready = core_io_dma_axi_ar_ready; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_valid = core_io_dma_axi_r_valid; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_id = core_io_dma_axi_r_bits_id; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_data = core_io_dma_axi_r_bits_data; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_resp = core_io_dma_axi_r_bits_resp; // @[quasar_wrapper.scala 107:21] + assign io_dma_brg_r_bits_last = 1'h1; // @[quasar_wrapper.scala 107:21] + assign io_dec_tlu_perfcnt0 = core_io_dec_tlu_perfcnt0; // @[quasar_wrapper.scala 159:23] + assign io_dec_tlu_perfcnt1 = core_io_dec_tlu_perfcnt1; // @[quasar_wrapper.scala 160:23] + assign io_dec_tlu_perfcnt2 = core_io_dec_tlu_perfcnt2; // @[quasar_wrapper.scala 161:23] + assign io_dec_tlu_perfcnt3 = core_io_dec_tlu_perfcnt3; // @[quasar_wrapper.scala 162:23] assign io_jtag_tdo = dmi_wrapper_tdo; // @[quasar_wrapper.scala 82:15] - assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 157:25] - assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 158:24] - assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 159:25] - assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 152:21] - assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 153:24] - assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 155:26] - assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 154:20] - assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 149:19] - assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 149:19] + assign io_mpc_debug_halt_ack = core_io_mpc_debug_halt_ack; // @[quasar_wrapper.scala 155:25] + assign io_mpc_debug_run_ack = core_io_mpc_debug_run_ack; // @[quasar_wrapper.scala 156:24] + assign io_debug_brkpt_status = core_io_debug_brkpt_status; // @[quasar_wrapper.scala 157:25] + assign io_o_cpu_halt_ack = core_io_o_cpu_halt_ack; // @[quasar_wrapper.scala 150:21] + assign io_o_cpu_halt_status = core_io_o_cpu_halt_status; // @[quasar_wrapper.scala 151:24] + assign io_o_debug_mode_status = core_io_o_debug_mode_status; // @[quasar_wrapper.scala 153:26] + assign io_o_cpu_run_ack = core_io_o_cpu_run_ack; // @[quasar_wrapper.scala 152:20] + assign io_rv_trace_pkt_rv_i_valid_ip = core_io_rv_trace_pkt_rv_i_valid_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_insn_ip = core_io_rv_trace_pkt_rv_i_insn_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_address_ip = core_io_rv_trace_pkt_rv_i_address_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_exception_ip = core_io_rv_trace_pkt_rv_i_exception_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_ecause_ip = core_io_rv_trace_pkt_rv_i_ecause_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_interrupt_ip = core_io_rv_trace_pkt_rv_i_interrupt_ip; // @[quasar_wrapper.scala 147:19] + assign io_rv_trace_pkt_rv_i_tval_ip = core_io_rv_trace_pkt_rv_i_tval_ip; // @[quasar_wrapper.scala 147:19] assign mem_clk = clock; // @[quasar_wrapper.scala 90:14] assign mem_rst_l = reset; // @[quasar_wrapper.scala 89:16] assign mem_dccm_clk_override = core_io_dccm_clk_override; // @[quasar_wrapper.scala 85:28] @@ -83589,52 +84351,52 @@ module quasar_wrapper( assign dmi_wrapper_rd_data = 32'h0; // @[quasar_wrapper.scala 73:26] assign core_clock = clock; assign core_reset = reset; - assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 103:19] - assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 103:19] - assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 104:19] - assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 104:19] - assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 104:19] - assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 104:19] - assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 104:19] - assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 105:18] - assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 105:18] - assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 106:19] - assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 106:19] - assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 123:21] - assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 124:19] - assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 125:19] - assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 126:19] - assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 129:26] - assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 130:25] - assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 131:19] - assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 134:30] - assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 135:29] - assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 136:29] + assign core_io_lsu_axi_aw_ready = io_lsu_brg_aw_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_w_ready = io_lsu_brg_w_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_b_valid = io_lsu_brg_b_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_b_bits_resp = io_lsu_brg_b_bits_resp; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_b_bits_id = io_lsu_brg_b_bits_id; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_ar_ready = io_lsu_brg_ar_ready; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_valid = io_lsu_brg_r_valid; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_id = io_lsu_brg_r_bits_id; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_data = io_lsu_brg_r_bits_data; // @[quasar_wrapper.scala 104:21] + assign core_io_lsu_axi_r_bits_resp = io_lsu_brg_r_bits_resp; // @[quasar_wrapper.scala 104:21] + assign core_io_ifu_axi_ar_ready = io_ifu_brg_ar_ready; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_valid = io_ifu_brg_r_valid; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_id = io_ifu_brg_r_bits_id; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_data = io_ifu_brg_r_bits_data; // @[quasar_wrapper.scala 105:21] + assign core_io_ifu_axi_r_bits_resp = io_ifu_brg_r_bits_resp; // @[quasar_wrapper.scala 105:21] + assign core_io_sb_axi_aw_ready = io_sb_brg_aw_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_w_ready = io_sb_brg_w_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_b_valid = io_sb_brg_b_valid; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_b_bits_resp = io_sb_brg_b_bits_resp; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_ar_ready = io_sb_brg_ar_ready; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_valid = io_sb_brg_r_valid; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_bits_data = io_sb_brg_r_bits_data; // @[quasar_wrapper.scala 106:21] + assign core_io_sb_axi_r_bits_resp = io_sb_brg_r_bits_resp; // @[quasar_wrapper.scala 106:21] + assign core_io_dma_axi_aw_valid = io_dma_brg_aw_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_id = io_dma_brg_aw_bits_id; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_addr = io_dma_brg_aw_bits_addr; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_aw_bits_size = io_dma_brg_aw_bits_size; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_valid = io_dma_brg_w_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_bits_data = io_dma_brg_w_bits_data; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_w_bits_strb = io_dma_brg_w_bits_strb; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_b_ready = io_dma_brg_b_ready; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_valid = io_dma_brg_ar_valid; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_id = io_dma_brg_ar_bits_id; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_addr = io_dma_brg_ar_bits_addr; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_ar_bits_size = io_dma_brg_ar_bits_size; // @[quasar_wrapper.scala 107:21] + assign core_io_dma_axi_r_ready = io_dma_brg_r_ready; // @[quasar_wrapper.scala 107:21] + assign core_io_dbg_rst_l = io_dbg_rst_l; // @[quasar_wrapper.scala 93:21 quasar_wrapper.scala 121:21] + assign core_io_rst_vec = io_rst_vec; // @[quasar_wrapper.scala 122:19] + assign core_io_nmi_int = io_nmi_int; // @[quasar_wrapper.scala 123:19] + assign core_io_nmi_vec = io_nmi_vec; // @[quasar_wrapper.scala 124:19] + assign core_io_i_cpu_halt_req = io_i_cpu_halt_req; // @[quasar_wrapper.scala 127:26] + assign core_io_i_cpu_run_req = io_i_cpu_run_req; // @[quasar_wrapper.scala 128:25] + assign core_io_core_id = io_core_id; // @[quasar_wrapper.scala 129:19] + assign core_io_mpc_debug_halt_req = io_mpc_debug_halt_req; // @[quasar_wrapper.scala 132:30] + assign core_io_mpc_debug_run_req = io_mpc_debug_run_req; // @[quasar_wrapper.scala 133:29] + assign core_io_mpc_reset_run_req = io_mpc_reset_run_req; // @[quasar_wrapper.scala 134:29] assign core_io_dccm_rd_data_lo = mem_dccm_rd_data_lo; // @[quasar_wrapper.scala 88:15] assign core_io_dccm_rd_data_hi = mem_dccm_rd_data_hi; // @[quasar_wrapper.scala 88:15] assign core_io_ic_rd_data = mem_ic_rd_data; // @[quasar_wrapper.scala 94:14] @@ -83645,16 +84407,16 @@ module quasar_wrapper( assign core_io_ic_tag_perr = mem_ic_tag_perr; // @[quasar_wrapper.scala 94:14] assign core_io_iccm_rd_data = mem_iccm_rd_data; // @[quasar_wrapper.scala 95:16] assign core_io_iccm_rd_data_ecc = mem_iccm_rd_data_ecc; // @[quasar_wrapper.scala 95:16] - assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 138:26] - assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 139:26] - assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 140:26] - assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 141:26] + assign core_io_lsu_bus_clk_en = io_lsu_bus_clk_en; // @[quasar_wrapper.scala 136:26] + assign core_io_ifu_bus_clk_en = io_ifu_bus_clk_en; // @[quasar_wrapper.scala 137:26] + assign core_io_dbg_bus_clk_en = io_dbg_bus_clk_en; // @[quasar_wrapper.scala 138:26] + assign core_io_dma_bus_clk_en = io_dma_bus_clk_en; // @[quasar_wrapper.scala 139:26] assign core_io_dmi_reg_en = dmi_wrapper_reg_en; // @[quasar_wrapper.scala 79:22] assign core_io_dmi_reg_addr = dmi_wrapper_reg_wr_addr; // @[quasar_wrapper.scala 78:24] assign core_io_dmi_reg_wr_en = dmi_wrapper_reg_wr_en; // @[quasar_wrapper.scala 80:25] assign core_io_dmi_reg_wdata = dmi_wrapper_reg_wr_data; // @[quasar_wrapper.scala 77:25] - assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 145:25] - assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 143:21] - assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 144:20] + assign core_io_extintsrc_req = io_extintsrc_req; // @[quasar_wrapper.scala 143:25] + assign core_io_timer_int = io_timer_int; // @[quasar_wrapper.scala 141:21] + assign core_io_soft_int = io_soft_int; // @[quasar_wrapper.scala 142:20] assign core_io_scan_mode = io_scan_mode; // @[quasar_wrapper.scala 66:21] endmodule diff --git a/design/src/main/resources/vsrc/beh_lib.sv b/src/main/resources/vsrc/beh_lib.sv similarity index 100% rename from design/src/main/resources/vsrc/beh_lib.sv rename to src/main/resources/vsrc/beh_lib.sv diff --git a/design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv b/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv similarity index 100% rename from design/src/main/resources/vsrc/dmi_jtag_to_core_sync.sv rename to src/main/resources/vsrc/dmi_jtag_to_core_sync.sv diff --git a/design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv b/src/main/resources/vsrc/dmi_wrapper.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/dmi_wrapper.sv rename to src/main/resources/vsrc/dmi_wrapper.sv diff --git a/design/src/main/resources/vsrc/gated_latch.sv b/src/main/resources/vsrc/gated_latch.sv similarity index 100% rename from design/src/main/resources/vsrc/gated_latch.sv rename to src/main/resources/vsrc/gated_latch.sv diff --git a/design/target/scala-2.12/classes/vsrc/gated_latch.v b/src/main/resources/vsrc/gated_latch.v similarity index 100% rename from design/target/scala-2.12/classes/vsrc/gated_latch.v rename to src/main/resources/vsrc/gated_latch.v diff --git a/design/src/main/resources/vsrc/ifu_ic_mem.sv b/src/main/resources/vsrc/ifu_ic_mem.sv similarity index 100% rename from design/src/main/resources/vsrc/ifu_ic_mem.sv rename to src/main/resources/vsrc/ifu_ic_mem.sv diff --git a/design/src/main/resources/vsrc/ifu_iccm_mem.sv b/src/main/resources/vsrc/ifu_iccm_mem.sv similarity index 100% rename from design/src/main/resources/vsrc/ifu_iccm_mem.sv rename to src/main/resources/vsrc/ifu_iccm_mem.sv diff --git a/design/src/main/resources/vsrc/lsu_dccm_mem.sv b/src/main/resources/vsrc/lsu_dccm_mem.sv similarity index 100% rename from design/src/main/resources/vsrc/lsu_dccm_mem.sv rename to src/main/resources/vsrc/lsu_dccm_mem.sv diff --git a/design/target/scala-2.12/classes/vsrc/mem.sv b/src/main/resources/vsrc/mem.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/mem.sv rename to src/main/resources/vsrc/mem.sv diff --git a/design/src/main/resources/vsrc/mem_lib.sv b/src/main/resources/vsrc/mem_lib.sv similarity index 100% rename from design/src/main/resources/vsrc/mem_lib.sv rename to src/main/resources/vsrc/mem_lib.sv diff --git a/design/src/main/resources/vsrc/mem_mod.sv b/src/main/resources/vsrc/mem_mod.sv similarity index 100% rename from design/src/main/resources/vsrc/mem_mod.sv rename to src/main/resources/vsrc/mem_mod.sv diff --git a/design/src/main/resources/vsrc/rvjtag_tap.sv b/src/main/resources/vsrc/rvjtag_tap.sv similarity index 100% rename from design/src/main/resources/vsrc/rvjtag_tap.sv rename to src/main/resources/vsrc/rvjtag_tap.sv diff --git a/design/src/main/resources/vsrc/rvtaj_tap.sv b/src/main/resources/vsrc/rvtaj_tap.sv similarity index 100% rename from design/src/main/resources/vsrc/rvtaj_tap.sv rename to src/main/resources/vsrc/rvtaj_tap.sv diff --git a/design/src/main/scala/.vscode/settings.json b/src/main/scala/.vscode/settings.json similarity index 100% rename from design/src/main/scala/.vscode/settings.json rename to src/main/scala/.vscode/settings.json diff --git a/design/src/main/scala/dbg/dbg.scala b/src/main/scala/dbg/dbg.scala similarity index 100% rename from design/src/main/scala/dbg/dbg.scala rename to src/main/scala/dbg/dbg.scala diff --git a/design/src/main/scala/dec/dec.scala b/src/main/scala/dec/dec.scala similarity index 100% rename from design/src/main/scala/dec/dec.scala rename to src/main/scala/dec/dec.scala diff --git a/design/src/main/scala/dec/dec_dec_ctl.scala b/src/main/scala/dec/dec_dec_ctl.scala similarity index 100% rename from design/src/main/scala/dec/dec_dec_ctl.scala rename to src/main/scala/dec/dec_dec_ctl.scala diff --git a/design/src/main/scala/dec/dec_decode_ctl.scala b/src/main/scala/dec/dec_decode_ctl.scala similarity index 100% rename from design/src/main/scala/dec/dec_decode_ctl.scala rename to src/main/scala/dec/dec_decode_ctl.scala diff --git a/design/src/main/scala/dec/dec_gpr_ctl.scala b/src/main/scala/dec/dec_gpr_ctl.scala similarity index 100% rename from design/src/main/scala/dec/dec_gpr_ctl.scala rename to src/main/scala/dec/dec_gpr_ctl.scala diff --git a/design/src/main/scala/dec/dec_ib_ctl.scala b/src/main/scala/dec/dec_ib_ctl.scala similarity index 100% rename from design/src/main/scala/dec/dec_ib_ctl.scala rename to src/main/scala/dec/dec_ib_ctl.scala diff --git a/design/src/main/scala/dec/dec_tlu_ctl.scala b/src/main/scala/dec/dec_tlu_ctl.scala similarity index 100% rename from design/src/main/scala/dec/dec_tlu_ctl.scala rename to src/main/scala/dec/dec_tlu_ctl.scala diff --git a/design/src/main/scala/dec/dec_trigger.scala b/src/main/scala/dec/dec_trigger.scala similarity index 100% rename from design/src/main/scala/dec/dec_trigger.scala rename to src/main/scala/dec/dec_trigger.scala diff --git a/design/src/main/scala/dma_ctrl.scala b/src/main/scala/dma_ctrl.scala similarity index 98% rename from design/src/main/scala/dma_ctrl.scala rename to src/main/scala/dma_ctrl.scala index 009aa782..34c1c005 100644 --- a/design/src/main/scala/dma_ctrl.scala +++ b/src/main/scala/dma_ctrl.scala @@ -16,18 +16,18 @@ class dma_ctrl extends Module with lib with RequireAsyncReset { val dma_dbg_rddata = Output(UInt(32.W)) val dma_dbg_cmd_done = Output(Bool()) val dma_dbg_cmd_fail = Output(Bool()) - val dbg_dma = new dec_dbg() - val dbg_dma_io = new dbg_dma() - val dec_dma = Flipped(new dec_dma()) + val dbg_dma = new dec_dbg() + val dbg_dma_io = new dbg_dma() + val dec_dma = Flipped(new dec_dma()) val iccm_dma_rvalid = Input(Bool()) // iccm data valid for DMA read val iccm_dma_ecc_error = Input(Bool()) // ECC error on DMA read val iccm_dma_rtag = Input(UInt(3.W)) // Tag of the DMA req val iccm_dma_rdata = Input(UInt(64.W)) // iccm data for DMA read val iccm_ready = Input(Bool()) // iccm ready to accept DMA request // AXI Write Channels - val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) - val lsu_dma = Flipped(new lsu_dma) - val ifu_dma = Flipped(new ifu_dma) + val dma_axi = Flipped(new axi_channels(DMA_BUS_TAG)) + val lsu_dma = Flipped(new lsu_dma) + val ifu_dma = Flipped(new ifu_dma) }) diff --git a/design/src/main/scala/dmi/dmi_wrapper.scala b/src/main/scala/dmi/dmi_wrapper.scala similarity index 100% rename from design/src/main/scala/dmi/dmi_wrapper.scala rename to src/main/scala/dmi/dmi_wrapper.scala diff --git a/design/src/main/scala/exu/exu.scala b/src/main/scala/exu/exu.scala similarity index 100% rename from design/src/main/scala/exu/exu.scala rename to src/main/scala/exu/exu.scala diff --git a/design/src/main/scala/exu/exu_alu_ctl.scala b/src/main/scala/exu/exu_alu_ctl.scala similarity index 100% rename from design/src/main/scala/exu/exu_alu_ctl.scala rename to src/main/scala/exu/exu_alu_ctl.scala diff --git a/design/src/main/scala/exu/exu_div_ctl.scala b/src/main/scala/exu/exu_div_ctl.scala similarity index 100% rename from design/src/main/scala/exu/exu_div_ctl.scala rename to src/main/scala/exu/exu_div_ctl.scala diff --git a/design/src/main/scala/exu/exu_mul_ctl.scala b/src/main/scala/exu/exu_mul_ctl.scala similarity index 100% rename from design/src/main/scala/exu/exu_mul_ctl.scala rename to src/main/scala/exu/exu_mul_ctl.scala diff --git a/design/src/main/scala/ifu/ifu.scala b/src/main/scala/ifu/ifu.scala similarity index 90% rename from design/src/main/scala/ifu/ifu.scala rename to src/main/scala/ifu/ifu.scala index 3da88b43..50e381a2 100644 --- a/design/src/main/scala/ifu/ifu.scala +++ b/src/main/scala/ifu/ifu.scala @@ -9,14 +9,14 @@ import include._ @chiselName class ifu extends Module with lib with RequireAsyncReset { val io = IO(new Bundle{ - val exu_flush_final = Input(Bool()) - val exu_flush_path_final = Input(UInt(31.W)) - val free_clk = Input(Clock()) - val active_clk = Input(Clock()) - val ifu_dec = new ifu_dec() // IFU and DEC interconnects - val exu_ifu = new exu_ifu() // IFU and EXU interconnects - val iccm = new iccm_mem() // ICCM memory signals - val ic = new ic_mem() // I$ memory signals + val exu_flush_final = Input(Bool()) + val exu_flush_path_final = Input(UInt(31.W)) + val free_clk = Input(Clock()) + val active_clk = Input(Clock()) + val ifu_dec = new ifu_dec() // IFU and DEC interconnects + val exu_ifu = new exu_ifu() // IFU and EXU interconnects + val iccm = new iccm_mem() // ICCM memory signals + val ic = new ic_mem() // I$ memory signals val ifu = new axi_channels(IFU_BUS_TAG) // AXI Write Channel val ifu_bus_clk_en = Input(Bool()) val ifu_dma = new ifu_dma() // DMA signals diff --git a/design/src/main/scala/ifu/ifu_aln_ctl.scala b/src/main/scala/ifu/ifu_aln_ctl.scala similarity index 100% rename from design/src/main/scala/ifu/ifu_aln_ctl.scala rename to src/main/scala/ifu/ifu_aln_ctl.scala diff --git a/design/src/main/scala/ifu/ifu_bp_ctl.scala b/src/main/scala/ifu/ifu_bp_ctl.scala similarity index 100% rename from design/src/main/scala/ifu/ifu_bp_ctl.scala rename to src/main/scala/ifu/ifu_bp_ctl.scala diff --git a/design/src/main/scala/ifu/ifu_compress_ctl.scala b/src/main/scala/ifu/ifu_compress_ctl.scala similarity index 100% rename from design/src/main/scala/ifu/ifu_compress_ctl.scala rename to src/main/scala/ifu/ifu_compress_ctl.scala diff --git a/design/src/main/scala/ifu/ifu_ifc_ctl.scala b/src/main/scala/ifu/ifu_ifc_ctl.scala similarity index 100% rename from design/src/main/scala/ifu/ifu_ifc_ctl.scala rename to src/main/scala/ifu/ifu_ifc_ctl.scala diff --git a/design/src/main/scala/ifu/ifu_mem_ctl.scala b/src/main/scala/ifu/ifu_mem_ctl.scala similarity index 100% rename from design/src/main/scala/ifu/ifu_mem_ctl.scala rename to src/main/scala/ifu/ifu_mem_ctl.scala diff --git a/design/src/main/scala/include/bundle.scala b/src/main/scala/include/bundle.scala similarity index 98% rename from design/src/main/scala/include/bundle.scala rename to src/main/scala/include/bundle.scala index 5dadfbe2..9263291d 100644 --- a/design/src/main/scala/include/bundle.scala +++ b/src/main/scala/include/bundle.scala @@ -74,14 +74,14 @@ class ahb_channel extends Bundle{ val in = new ahb_in val out = new ahb_out } -class axi_channels(val BUS_TAG :Int=3) extends Bundle with lib{ +class axi_channels(val BUS_TAG :Int=1) extends Bundle with lib{ val aw = Decoupled(new write_addr(BUS_TAG)) val w = Decoupled(new write_data()) val b = Flipped(Decoupled(new write_resp(BUS_TAG))) val ar = Decoupled(new read_addr(BUS_TAG)) val r = Flipped(Decoupled(new read_data(BUS_TAG))) } -class read_addr(val TAG : Int=3) extends Bundle with lib { // read_address +class read_addr(val TAG : Int) extends Bundle with lib { // read_address val id = UInt(TAG.W) val addr = UInt(32.W) val region = UInt(4.W) @@ -93,13 +93,13 @@ class read_addr(val TAG : Int=3) extends Bundle with lib { // read_address val prot = UInt(3.W) val qos = UInt(4.W) } -class read_data(val TAG : Int=3) extends Bundle with lib { // read_data +class read_data(val TAG : Int) extends Bundle with lib { // read_data val id = UInt(TAG.W) val data = UInt(64.W) val resp = UInt(2.W) val last = Bool() } -class write_addr(val TAG : Int=3) extends Bundle with lib { // write_address +class write_addr(val TAG : Int) extends Bundle with lib { // write_address val id = UInt(TAG.W) val addr = UInt(32.W) val region = UInt(4.W) @@ -116,13 +116,12 @@ class write_data extends Bundle with lib{ // write_data val strb = UInt(8.W) val last = Bool() } -class write_resp(val TAG : Int=3) extends Bundle with lib{ // write_response +class write_resp(val TAG : Int) extends Bundle with lib{ // write_response val resp = UInt(2.W) val id = UInt(TAG.W) } class dec_mem_ctrl extends Bundle with lib{ - // val dec_tlu_flush_lower_wb = Input(Bool()) val dec_tlu_flush_err_wb = Input(Bool()) val dec_tlu_i0_commit_cmt = Input(Bool()) val dec_tlu_force_halt = Input(Bool()) diff --git a/design/src/main/scala/lib/ahb_to_axi4.scala b/src/main/scala/lib/ahb_to_axi4.scala similarity index 69% rename from design/src/main/scala/lib/ahb_to_axi4.scala rename to src/main/scala/lib/ahb_to_axi4.scala index aeb918f8..60bf09d4 100644 --- a/design/src/main/scala/lib/ahb_to_axi4.scala +++ b/src/main/scala/lib/ahb_to_axi4.scala @@ -10,55 +10,14 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool()) val clk_override = Input(Bool()) - val axi_awready = Input(Bool()) - val axi_wready = Input(Bool()) - val axi_bvalid = Input(Bool()) - val axi_bresp = Input(UInt(2.W)) - val axi_bid = Input(UInt(TAG.W)) - val axi_arready = Input(Bool()) - val axi_rvalid = Input(Bool()) - val axi_rid = Input(UInt(TAG.W)) - val axi_rdata = Input(UInt(64.W)) - val axi_rresp = Input(UInt(2.W)) - // val ahb_haddr = Input(UInt(32.W)) // ahb bus address - // val ahb_hburst = Input(UInt(3.W)) // tied to 0 - // val ahb_hmastlock = Input(Bool()) // tied to 0 - // val ahb_hprot = Input(UInt(4.W)) // tied to 4'b0011 - // val ahb_hsize = Input(UInt(3.W)) // size of bus transaction (possible values 0 =1 =2 =3) - // val ahb_htrans = Input(UInt(2.W)) // Transaction type (possible values 0 =2 only right now) - // val ahb_hwrite = Input(Bool()) // ahb bus write - // val ahb_hwdata = Input(UInt(64.W)) // ahb bus write data -// val ahb_hsel = Input(Bool()) // this slave was selected -// val ahb_hreadyin = Input(Bool()) // previous hready was accepted or not - // outputs - val axi_awvalid = Output(Bool()) - val axi_awid = Output(UInt(TAG.W)) - val axi_awaddr = Output(UInt(32.W)) - val axi_awsize = Output(UInt(3.W)) - val axi_awprot = Output(UInt(3.W)) - val axi_awlen = Output(UInt(8.W)) - val axi_awburst = Output(UInt(2.W)) - val axi_wvalid = Output(Bool()) - val axi_wdata = Output(UInt(64.W)) - val axi_wstrb = Output(UInt(8.W)) - val axi_wlast = Output(Bool()) - val axi_bready = Output(Bool()) - val axi_arvalid = Output(Bool()) - val axi_arid = Output(UInt(TAG.W)) - val axi_araddr = Output(UInt(32.W)) - val axi_arsize = Output(UInt(3.W)) - val axi_arprot = Output(UInt(3.W)) - val axi_arlen = Output(UInt(8.W)) - val axi_arburst = Output(UInt(2.W)) - val axi_rready = Output(Bool()) + + val axi = new axi_channels(1) val ahb = new Bundle{ val sig = Flipped(new ahb_channel()) val hsel = Input(Bool()) val hreadyin = Input(Bool())} - // val ahb_hrdata = Output(UInt(64.W)) // ahb bus read data - // val ahb_hreadyout = Output(Bool()) // slave ready to accept transaction - // val ahb_hresp = Output(Bool()) // slave response (high indicates erro) - }) + }) + io.axi <> 0.U.asTypeOf(io.axi) val idle:: wr :: rd :: pend :: Nil = Enum(4) val TAG= 1 val master_wstrb = WireInit(0.U(8.W)) @@ -78,10 +37,6 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { val ahb_hwdata_q = WireInit(0.U(64.W)) val ahb_hresp_q = WireInit(Bool(), false.B) - //Miscellaneous signals - // val ahb_addr_in_iccm = WireInit(Bool(), false.B) - // val ahb_addr_in_iccm_region_nc = WireInit(Bool(), false.B) - // signals needed for the read data coming back from the core and to block any further commands as AHB is a blocking bus val buf_rdata_en = WireInit(Bool(), false.B) val ahb_bus_addr_clk_en = WireInit(Bool(), false.B) @@ -133,9 +88,9 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { } is(pend) { // Read Command has been sent. Waiting on Data. buf_nxtstate := idle // go back for next command and present data next cycle - buf_state_en := io.axi_rvalid & !cmdbuf_write // read data is back + buf_state_en := io.axi.r.valid & !cmdbuf_write // read data is back buf_rdata_en := buf_state_en // buffer the read data coming back from core - buf_read_error_in := buf_state_en & io.axi_rresp(1, 0).orR // buffer error flag if return has Error ( ECC ) + buf_read_error_in := buf_state_en & io.axi.r.bits.resp(1, 0).orR // buffer error flag if return has Error ( ECC ) } } buf_state := withClock(ahb_clk){RegEnable(buf_nxtstate,0.U,buf_state_en.asBool())} @@ -160,7 +115,7 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { (ahb_hresp_q & !ahb_hready_q) // Buffer signals - needed for the read data and ECC error response - buf_rdata := withClock(buf_rdata_clk){RegNext(io.axi_rdata,0.U)} + buf_rdata := withClock(buf_rdata_clk){RegNext(io.axi.r.bits.data,0.U)} buf_read_error := withClock(ahb_clk){RegNext(buf_read_error_in,0.U)} // All the Master signals are captured before presenting it to the command buffer. We check for Hresp before sending it to the cmd buffer. @@ -179,8 +134,8 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { ahb_addr_clk := rvclkhdr(clock, ahb_bus_addr_clk_en, io.scan_mode) buf_rdata_clk := rvclkhdr(clock, buf_rdata_clk_en, io.scan_mode) - cmdbuf_rst := (((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write) - cmdbuf_full := (cmdbuf_vld & !((io.axi_awvalid & io.axi_awready) | (io.axi_arvalid & io.axi_arready))) + cmdbuf_rst := (((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready)) & !cmdbuf_wr_en) | (io.ahb.sig.in.hresp & !cmdbuf_write) + cmdbuf_full := (cmdbuf_vld & !((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.ar.valid & io.axi.ar.ready))) //rvdffsc cmdbuf_vld := withClock(bus_clk) {RegNext((Mux(cmdbuf_wr_en.asBool(),"b1".U,cmdbuf_vld) & !cmdbuf_rst), 0.U)} @@ -199,31 +154,29 @@ class ahb_to_axi4 extends Module with lib with RequireAsyncReset { cmdbuf_wdata := rvdffe(io.ahb.sig.out.hwdata, cmdbuf_wr_en.asBool(),bus_clk,io.scan_mode) // AXI Write Command Channel - io.axi_awvalid := cmdbuf_vld & cmdbuf_write - io.axi_awid := Fill(TAG, 0.U) - io.axi_awaddr := cmdbuf_addr - io.axi_awsize := Cat("b0".U, cmdbuf_size(1, 0)) - io.axi_awprot := Fill(3, 0.U) - io.axi_awlen := Fill(8, 0.U) - io.axi_awburst := "b01".U + io.axi.aw.valid := cmdbuf_vld & cmdbuf_write + io.axi.aw.bits.id := Fill(TAG, 0.U) + io.axi.aw.bits.addr := cmdbuf_addr + io.axi.aw.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) + io.axi.aw.bits.prot := Fill(3, 0.U) + io.axi.aw.bits.len := Fill(8, 0.U) + io.axi.aw.bits.burst := "b01".U // AXI Write Data Channel - This is tied to the command channel as we only write the command buffer once we have the data. - io.axi_wvalid := cmdbuf_vld & cmdbuf_write - io.axi_wdata := cmdbuf_wdata - io.axi_wstrb := cmdbuf_wstrb - io.axi_wlast := "b1".U + io.axi.w.valid := cmdbuf_vld & cmdbuf_write + io.axi.w.bits.data := cmdbuf_wdata + io.axi.w.bits.strb := cmdbuf_wstrb + io.axi.w.bits.last := "b1".U // AXI Write Response - Always ready. AHB does not require a write response. - io.axi_bready := "b1".U + io.axi.b.ready := "b1".U // AXI Read Channels - io.axi_arvalid := cmdbuf_vld & !cmdbuf_write - io.axi_arid := Fill(TAG, 0.U) - io.axi_araddr := cmdbuf_addr - io.axi_arsize := Cat("b0".U, cmdbuf_size(1, 0)) - io.axi_arprot := Fill(3, 0.U) - io.axi_arlen := Fill(8, 0.U) - io.axi_arburst := "b01".U + io.axi.ar.valid := cmdbuf_vld & !cmdbuf_write + io.axi.ar.bits.id := Fill(TAG, 0.U) + io.axi.ar.bits.addr := cmdbuf_addr + io.axi.ar.bits.size := Cat("b0".U, cmdbuf_size(1, 0)) + io.axi.ar.bits.prot := Fill(3, 0.U) + io.axi.ar.bits.len := Fill(8, 0.U) + io.axi.ar.bits.burst := "b01".U // AXI Read Response Channel - Always ready as AHB reads are blocking and the the buffer is available for the read coming back always. - io.axi_rready := true.B - - + io.axi.r.ready := true.B bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) } diff --git a/design/src/main/scala/lib/axi4_to_ahb.scala b/src/main/scala/lib/axi4_to_ahb.scala similarity index 77% rename from design/src/main/scala/lib/axi4_to_ahb.scala rename to src/main/scala/lib/axi4_to_ahb.scala index 0baaf047..3422f2b1 100644 --- a/design/src/main/scala/lib/axi4_to_ahb.scala +++ b/src/main/scala/lib/axi4_to_ahb.scala @@ -13,37 +13,10 @@ class axi4_to_ahb_IO extends Bundle with Config { val scan_mode = Input(Bool()) val bus_clk_en = Input(Bool()) val clk_override = Input(Bool()) - val axi_awvalid = Input(Bool()) - val axi_awid = Input(UInt(TAG.W)) // [TAG-1:0] - val axi_awaddr = Input(UInt(32.W)) // [31:0] - val axi_awsize = Input(UInt(3.W)) // [2:0] - val axi_awprot = Input(UInt(3.W)) // [2:0] - val axi_wvalid = Input(Bool()) - val axi_wdata = Input(UInt(64.W)) // [63:0] - val axi_wstrb = Input(UInt(8.W)) // [7:0] - val axi_wlast = Input(Bool()) - val axi_bready = Input(Bool()) - val axi_arvalid = Input(Bool()) - val axi_arid = Input(UInt(TAG.W)) // [TAG-1:0] - val axi_araddr = Input(UInt(32.W)) // [31:0] - val axi_arsize = Input(UInt(3.W)) // [2:0] - val axi_arprot = Input(UInt(3.W)) // [2:0] - val axi_rready = Input(Bool()) - //----------------------------outputs--------------------------- - val axi_awready = Output(Bool()) - val axi_wready = Output(Bool()) - val axi_bvalid = Output(Bool()) - val axi_bresp = Output(UInt(2.W)) // [1:0]] - val axi_bid = Output(UInt(TAG.W)) // [TAG-1:0] - // AXI Read Channels - val axi_arready = Output(Bool()) - val axi_rvalid = Output(Bool()) - val axi_rid = Output(UInt(TAG.W)) // [TAG-1:0] - val axi_rdata = Output(UInt(64.W)) // [63:0] - val axi_rresp = Output(UInt(2.W)) // 1:0] - val axi_rlast = Output(Bool()) + // AXI-4 signals + val axi = Flipped(new axi_channels(1)) // AHB-Lite signals - val ahb = new ahb_channel + val ahb = new ahb_channel() } @@ -53,6 +26,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { val io = IO(new axi4_to_ahb_IO) val buf_rst = WireInit(0.U(1.W)) buf_rst :=0.U + io.ahb.out.htrans := 0.U val buf_state_en = WireInit(Bool(), init = false.B) val ahbm_clk = Wire(Clock()) val ahbm_addr_clk = Wire(Clock()) @@ -170,50 +144,31 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { MuxCase(7.U, temp) } wr_cmd_vld := wrbuf_vld & wrbuf_data_vld - master_valid := wr_cmd_vld | io.axi_arvalid - master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi_arid(TAG - 1, 0)) + master_valid := wr_cmd_vld | io.axi.ar.valid + master_tag := Mux(wr_cmd_vld.asBool(), wrbuf_tag(TAG - 1, 0), io.axi.ar.bits.id(TAG - 1, 0)) master_opc := Mux(wr_cmd_vld.asBool(), "b011".U, "b0".U) - master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi_araddr(31, 0)) - master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi_arsize(2, 0)) + master_addr := Mux(wr_cmd_vld.asBool(), wrbuf_addr(31, 0), io.axi.ar.bits.addr(31, 0)) + master_size := Mux(wr_cmd_vld.asBool(), wrbuf_size(2, 0), io.axi.ar.bits.size(2, 0)) master_byteen := wrbuf_byteen(7, 0) master_wdata := wrbuf_data(63, 0) // AXI response channel signals - io.axi_bvalid := slave_valid & slave_ready & slave_opc(3) - io.axi_bresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) - io.axi_bid := slave_tag(TAG - 1, 0) + io.axi.b.valid := slave_valid & slave_ready & slave_opc(3) + io.axi.b.bits.resp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) + io.axi.b.bits.id := slave_tag(TAG - 1, 0) - io.axi_rvalid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U) - io.axi_rresp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) - io.axi_rid := slave_tag(TAG - 1, 0) - io.axi_rdata := slave_rdata(63, 0) - slave_ready := io.axi_bready & io.axi_rready + io.axi.r.valid := slave_valid & slave_ready & (slave_opc(3, 2) === "b0".U) + io.axi.r.bits.resp := Mux(slave_opc(0), "b10".U, Mux(slave_opc(1), "b11".U, "b0".U)) + io.axi.r.bits.id := slave_tag(TAG - 1, 0) + io.axi.r.bits.data := slave_rdata(63, 0) + slave_ready := io.axi.b.ready & io.axi.r.ready // Clock header logic - bus_write_clk_en := io.bus_clk_en & ((io.axi_awvalid & io.axi_awready) | (io.axi_wvalid & io.axi_wready)) + bus_write_clk_en := io.bus_clk_en & ((io.axi.aw.valid & io.axi.aw.ready) | (io.axi.w.valid & io.axi.w.ready)) bus_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) bus_write_clk := rvclkhdr(clock, bus_write_clk_en.asBool(), io.scan_mode) - //State machine - io.ahb.out.htrans := 0.U - master_ready := 0.U - buf_state_en := false.B - buf_nxtstate := idle - //buf_wr_en := 0.U - buf_data_wr_en := 0.U - slvbuf_error_in := 0.U - slvbuf_error_en := 0.U - buf_write_in := 0.U - cmd_done := 0.U - trxn_done := 0.U - buf_cmd_byte_ptr_en := 0.U - buf_cmd_byte_ptr := 0.U - slave_valid_pre := 0.U - slvbuf_wr_en := 0.U - bypass_en := 0.U - rd_bypass_idle := 0.U - switch(buf_state) { is(idle) { master_ready := 1.U @@ -304,25 +259,6 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1,0) =/= 0.U) buf_cmd_byte_ptr_en := trxn_done | bypass_en buf_cmd_byte_ptr := Mux(bypass_en,get_nxtbyte_ptr(0.U(3.W),buf_byteen_in(7,0),false.B),Mux(trxn_done,get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2,0),buf_byteen(7,0),true.B),buf_cmd_byte_ptrQ)) - - - // - // buf_state_en := (cmd_doneQ & ahb_hready_q) | ahb_hresp_q - // master_ready := ((cmd_doneQ & ahb_hready_q) | ahb_hresp_q) & !ahb_hresp_q & slave_ready - // buf_nxtstate := Mux((ahb_hresp_q | !slave_ready).asBool(), done, Mux((master_valid & master_ready).asBool(), Mux((master_opc(2, 1) === "b01".U(2.W)), cmd_wr, cmd_rd), idle)) - // slvbuf_error_in := ahb_hresp_q - // slvbuf_error_en := buf_state_en - // buf_write_in := (master_opc(2, 1) === "b01".U) - // buf_wr_en := buf_state_en & ((buf_nxtstate === cmd_wr) | (buf_nxtstate === cmd_rd)) - // buf_data_wr_en := buf_wr_en - // cmd_done := (ahb_hresp_q | (ahb_hready_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) & ((buf_cmd_byte_ptrQ === "b111".U) | (buf_byteen(get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B)) === "b0".U)))) - // bypass_en := buf_state_en & buf_write_in & (buf_nxtstate === cmd_wr) // Only bypass for writes for the time being - // io.ahb_htrans := Fill(2, (!(cmd_done | cmd_doneQ) | bypass_en)) & "b10".U - // slave_valid_pre := buf_state_en & (buf_nxtstate =/= done) - // trxn_done := ahb_hready_q & ahb_hwrite_q & (ahb_htrans_q(1, 0) =/= "b0".U(2.W)) - // buf_cmd_byte_ptr_en := trxn_done | bypass_en - // buf_cmd_byte_ptr := Mux(bypass_en, get_nxtbyte_ptr(0.U(3.W), buf_byteen_in(7, 0), false.B), Mux(trxn_done, get_nxtbyte_ptr(buf_cmd_byte_ptrQ(2, 0), buf_byteen(7, 0), true.B), buf_cmd_byte_ptrQ)) - } is(done) { buf_nxtstate := idle @@ -348,7 +284,7 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { io.ahb.out.hburst := "b0".U io.ahb.out.hmastlock := "b0".U - io.ahb.out.hprot := Cat("b001".U, ~io.axi_arprot(2)) + io.ahb.out.hprot := Cat("b001".U, !io.axi.ar.bits.prot(2)) io.ahb.out.hwrite := Mux(bypass_en.asBool(), (master_opc(2, 1) === "b01".U), buf_write) io.ahb.out.hwdata := buf_data(63, 0) @@ -359,23 +295,23 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { last_addr_en := (io.ahb.out.htrans(1, 0) =/= "b0".U) & io.ahb.in.hready & io.ahb.out.hwrite // Write buffer - wrbuf_en := io.axi_awvalid & io.axi_awready & master_ready - wrbuf_data_en := io.axi_wvalid & io.axi_wready & master_ready + wrbuf_en := io.axi.aw.valid & io.axi.aw.ready & master_ready + wrbuf_data_en := io.axi.w.valid & io.axi.w.ready & master_ready wrbuf_cmd_sent := master_valid & master_ready & (master_opc(2, 1) === "b01".U) wrbuf_rst := wrbuf_cmd_sent & !wrbuf_en - io.axi_awready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready - io.axi_wready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready - io.axi_arready := !(wrbuf_vld & wrbuf_data_vld) & master_ready - io.axi_rlast := true.B + io.axi.aw.ready := !(wrbuf_vld & !wrbuf_cmd_sent) & master_ready + io.axi.w.ready := !(wrbuf_data_vld & !wrbuf_cmd_sent) & master_ready + io.axi.ar.ready := !(wrbuf_vld & wrbuf_data_vld) & master_ready + io.axi.r.bits.last := true.B wrbuf_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_en.asBool(),1.U,wrbuf_vld) & !wrbuf_rst, 0.U)} wrbuf_data_vld := withClock(bus_clk) {RegNext(Mux(wrbuf_data_en.asBool(),1.U, wrbuf_data_vld) & !wrbuf_rst, 0.U)} - wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi_awid(TAG - 1, 0), 0.U, wrbuf_en.asBool())} - wrbuf_size := withClock(bus_clk) {RegEnable(io.axi_awsize(2, 0), 0.U, wrbuf_en.asBool())} - wrbuf_addr := rvdffe(io.axi_awaddr, wrbuf_en.asBool,bus_clk,io.scan_mode) - wrbuf_data := rvdffe(io.axi_wdata, wrbuf_data_en.asBool,bus_clk,io.scan_mode) - wrbuf_byteen := withClock(bus_clk) {RegEnable(io.axi_wstrb(7, 0), 0.U, wrbuf_data_en.asBool())} + wrbuf_tag := withClock(bus_clk) {RegEnable(io.axi.aw.bits.id(TAG - 1, 0), 0.U, wrbuf_en.asBool())} + wrbuf_size := withClock(bus_clk) {RegEnable(io.axi.aw.bits.size(2, 0), 0.U, wrbuf_en.asBool())} + wrbuf_addr := rvdffe(io.axi.aw.bits.addr, wrbuf_en.asBool,bus_clk,io.scan_mode) + wrbuf_data := rvdffe(io.axi.w.bits.data, wrbuf_data_en.asBool,bus_clk,io.scan_mode) + wrbuf_byteen := withClock(bus_clk) {RegEnable(io.axi.w.bits.strb(7, 0), 0.U, wrbuf_data_en.asBool())} last_bus_addr := withClock(ahbm_clk) {RegEnable(io.ahb.out.haddr(31, 0), 0.U, last_addr_en.asBool())} buf_write := withClock(buf_clk) {RegEnable(buf_write_in, 0.U, buf_wr_en.asBool())} buf_tag := withClock(buf_clk) {RegEnable(buf_tag_in(TAG - 1, 0), 0.U, buf_wr_en.asBool())} @@ -404,4 +340,4 @@ class axi4_to_ahb extends Module with lib with RequireAsyncReset with Config { ahbm_clk := rvclkhdr(clock, io.bus_clk_en, io.scan_mode) ahbm_addr_clk := rvclkhdr(clock, ahbm_addr_clken, io.scan_mode) ahbm_data_clk := rvclkhdr(clock, ahbm_data_clken, io.scan_mode) -} +} \ No newline at end of file diff --git a/design/src/main/scala/lib/lib.scala b/src/main/scala/lib/lib.scala similarity index 100% rename from design/src/main/scala/lib/lib.scala rename to src/main/scala/lib/lib.scala diff --git a/design/src/main/scala/lib/param.scala b/src/main/scala/lib/param.scala similarity index 100% rename from design/src/main/scala/lib/param.scala rename to src/main/scala/lib/param.scala diff --git a/design/src/main/scala/lsu/lsu.scala b/src/main/scala/lsu/lsu.scala similarity index 100% rename from design/src/main/scala/lsu/lsu.scala rename to src/main/scala/lsu/lsu.scala diff --git a/design/src/main/scala/lsu/lsu_addrcheck.scala b/src/main/scala/lsu/lsu_addrcheck.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_addrcheck.scala rename to src/main/scala/lsu/lsu_addrcheck.scala diff --git a/design/src/main/scala/lsu/lsu_bus_buffer.scala b/src/main/scala/lsu/lsu_bus_buffer.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_bus_buffer.scala rename to src/main/scala/lsu/lsu_bus_buffer.scala diff --git a/design/src/main/scala/lsu/lsu_bus_intf.scala b/src/main/scala/lsu/lsu_bus_intf.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_bus_intf.scala rename to src/main/scala/lsu/lsu_bus_intf.scala diff --git a/design/src/main/scala/lsu/lsu_clkdomain.scala b/src/main/scala/lsu/lsu_clkdomain.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_clkdomain.scala rename to src/main/scala/lsu/lsu_clkdomain.scala diff --git a/design/src/main/scala/lsu/lsu_dccm_ctl.scala b/src/main/scala/lsu/lsu_dccm_ctl.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_dccm_ctl.scala rename to src/main/scala/lsu/lsu_dccm_ctl.scala diff --git a/design/src/main/scala/lsu/lsu_ecc.scala b/src/main/scala/lsu/lsu_ecc.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_ecc.scala rename to src/main/scala/lsu/lsu_ecc.scala diff --git a/design/src/main/scala/lsu/lsu_lsc_ctl.scala b/src/main/scala/lsu/lsu_lsc_ctl.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_lsc_ctl.scala rename to src/main/scala/lsu/lsu_lsc_ctl.scala diff --git a/design/src/main/scala/lsu/lsu_stbuf.scala b/src/main/scala/lsu/lsu_stbuf.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_stbuf.scala rename to src/main/scala/lsu/lsu_stbuf.scala diff --git a/design/src/main/scala/lsu/lsu_trigger.scala b/src/main/scala/lsu/lsu_trigger.scala similarity index 100% rename from design/src/main/scala/lsu/lsu_trigger.scala rename to src/main/scala/lsu/lsu_trigger.scala diff --git a/design/src/main/scala/mem.scala b/src/main/scala/mem.scala similarity index 100% rename from design/src/main/scala/mem.scala rename to src/main/scala/mem.scala diff --git a/design/src/main/scala/pic_ctrl.scala b/src/main/scala/pic_ctrl.scala similarity index 100% rename from design/src/main/scala/pic_ctrl.scala rename to src/main/scala/pic_ctrl.scala diff --git a/design/src/main/scala/quasar.scala b/src/main/scala/quasar.scala similarity index 52% rename from design/src/main/scala/quasar.scala rename to src/main/scala/quasar.scala index 7079c3f8..407cf6d9 100644 --- a/design/src/main/scala/quasar.scala +++ b/src/main/scala/quasar.scala @@ -18,7 +18,7 @@ class quasar_bundle extends Bundle with lib{ val ifu_ahb = new ahb_channel val sb_ahb = new ahb_channel val dma_ahb = new Bundle{ - val ahb= Flipped(new ahb_channel()) + val sig = Flipped(new ahb_channel()) val hsel = Input(Bool()) val hreadyin = Input(Bool())} @@ -186,7 +186,6 @@ class quasar extends Module with RequireAsyncReset with lib { dbg.io.dmi_reg_addr := io.dmi_reg_addr dbg.io.dmi_reg_wr_en := io.dmi_reg_wr_en dbg.io.dmi_reg_wdata := io.dmi_reg_wdata - dbg.io.sb_axi <> io.sb_axi dbg.io.dbg_bus_clk_en := io.dbg_bus_clk_en dbg.io.dbg_rst_l := io.dbg_rst_l.asBool() dbg.io.clk_override := dec.io.dec_tlu_misc_clk_override @@ -238,193 +237,53 @@ class quasar extends Module with RequireAsyncReset with lib { // LSU Outputs io.dccm <> lsu.io.dccm - // AXI LSU SIDE - io.lsu_axi <> lsu.io.axi - // AXI IFU - io.ifu_axi <> ifu.io.ifu - io.dma_axi <> dma_ctrl.io.dma_axi - - - - -/* when(BUILD_AHB_LITE.B) { + val sb_axi4_to_ahb = Module(new axi4_to_ahb()) + val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) val lsu_axi4_to_ahb = Module(new axi4_to_ahb()) - lsu_axi4_to_ahb.io.axi_awvalid := io.lsu_axi.aw.valid + val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) + lsu_axi4_to_ahb.io.scan_mode := io.scan_mode lsu_axi4_to_ahb.io.bus_clk_en := io.lsu_bus_clk_en lsu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override - lsu_axi4_to_ahb.io.axi_awid := io.lsu_axi.aw.bits.id - lsu_axi4_to_ahb.io.axi_awaddr := io.lsu_axi.aw.bits.addr - lsu_axi4_to_ahb.io.axi_awsize := io.lsu_axi.aw.bits.size - lsu_axi4_to_ahb.io.axi_awprot := io.lsu_axi.aw.bits.prot + lsu_axi4_to_ahb.io.axi <> lsu.io.axi + lsu_axi4_to_ahb.io.ahb <> io.lsu_ahb - lsu_axi4_to_ahb.io.axi_wvalid := io.lsu_axi.w.valid - lsu_axi4_to_ahb.io.axi_wdata := io.lsu_axi.w.bits.data - lsu_axi4_to_ahb.io.axi_wstrb := io.lsu_axi.w.bits.strb - lsu_axi4_to_ahb.io.axi_wlast := io.lsu_axi.w.bits.last - lsu_axi4_to_ahb.io.axi_bready := io.lsu_axi.b.ready - lsu_axi4_to_ahb.io.axi_arvalid := io.lsu_axi.ar.valid - lsu_axi4_to_ahb.io.axi_arid := io.lsu_axi.ar.bits.id - lsu_axi4_to_ahb.io.axi_araddr := io.lsu_axi.ar.bits.addr - lsu_axi4_to_ahb.io.axi_arsize := io.lsu_axi.ar.bits.size - lsu_axi4_to_ahb.io.axi_arprot := io.lsu_axi.ar.bits.prot - - lsu_axi4_to_ahb.io.axi_rready := io.lsu_axi.r.ready - - val ifu_axi4_to_ahb = Module(new axi4_to_ahb()) - ifu_axi4_to_ahb.io.axi_awvalid := io.ifu_axi.aw.valid ifu_axi4_to_ahb.io.scan_mode := io.scan_mode ifu_axi4_to_ahb.io.bus_clk_en := io.ifu_bus_clk_en ifu_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override - ifu_axi4_to_ahb.io.axi_awid := io.ifu_axi.aw.bits.id - ifu_axi4_to_ahb.io.axi_awaddr := io.ifu_axi.aw.bits.addr - ifu_axi4_to_ahb.io.axi_awsize := io.ifu_axi.aw.bits.size - ifu_axi4_to_ahb.io.axi_awprot := io.ifu_axi.aw.bits.prot + ifu_axi4_to_ahb.io.axi <> ifu.io.ifu + ifu_axi4_to_ahb.io.ahb <> io.ifu_ahb - ifu_axi4_to_ahb.io.axi_wvalid := io.ifu_axi.w.valid - ifu_axi4_to_ahb.io.axi_wdata := io.ifu_axi.w.bits.data - ifu_axi4_to_ahb.io.axi_wstrb := io.ifu_axi.w.bits.strb - ifu_axi4_to_ahb.io.axi_wlast := io.ifu_axi.w.bits.last - ifu_axi4_to_ahb.io.axi_bready := io.ifu_axi.b.ready - - ifu_axi4_to_ahb.io.axi_arvalid := io.ifu_axi.ar.valid - ifu_axi4_to_ahb.io.axi_arid := io.ifu_axi.ar.bits.id - ifu_axi4_to_ahb.io.axi_araddr := io.ifu_axi.ar.bits.addr - ifu_axi4_to_ahb.io.axi_arsize := io.ifu_axi.ar.bits.size - ifu_axi4_to_ahb.io.axi_arprot := io.ifu_axi.ar.bits.prot - - ifu_axi4_to_ahb.io.axi_rready := io.ifu_axi.r.ready - - // ifu_axi4_to_ahb.io.ahb_hrdata := io.hrdata - // ifu_axi4_to_ahb.io.ahb_hready := io.hready - // ifu_axi4_to_ahb.io.ahb_hresp := io.hresp - - val sb_axi4_to_ahb = Module(new axi4_to_ahb()) - sb_axi4_to_ahb.io.axi_awvalid := io.sb_axi.aw.valid sb_axi4_to_ahb.io.scan_mode := io.scan_mode sb_axi4_to_ahb.io.bus_clk_en := io.dbg_bus_clk_en sb_axi4_to_ahb.io.clk_override := dec.io.dec_tlu_bus_clk_override - sb_axi4_to_ahb.io.axi_awid := io.sb_axi.aw.bits.id - sb_axi4_to_ahb.io.axi_awaddr := io.sb_axi.aw.bits.addr - sb_axi4_to_ahb.io.axi_awsize := io.sb_axi.aw.bits.size - sb_axi4_to_ahb.io.axi_awprot := io.sb_axi.aw.bits.prot + sb_axi4_to_ahb.io.axi <> dbg.io.sb_axi + sb_axi4_to_ahb.io.ahb <> io.sb_ahb - sb_axi4_to_ahb.io.axi_wvalid := io.sb_axi.w.valid - sb_axi4_to_ahb.io.axi_wdata := io.sb_axi.w.bits.data - sb_axi4_to_ahb.io.axi_wstrb := io.sb_axi.w.bits.strb - sb_axi4_to_ahb.io.axi_wlast := io.sb_axi.w.bits.last - sb_axi4_to_ahb.io.axi_bready := io.sb_axi.b.ready - - sb_axi4_to_ahb.io.axi_arvalid := io.sb_axi.ar.valid - sb_axi4_to_ahb.io.axi_arid := io.sb_axi.ar.bits.id - sb_axi4_to_ahb.io.axi_araddr := io.sb_axi.ar.bits.addr - sb_axi4_to_ahb.io.axi_arsize := io.sb_axi.ar.bits.size - sb_axi4_to_ahb.io.axi_arprot := io.sb_axi.ar.bits.prot - - sb_axi4_to_ahb.io.axi_rready := io.sb_axi.r.ready - // sb_axi4_to_ahb.io.ahb_hrdata := io.sb_hrdata - // sb_axi4_to_ahb.io.ahb_hready := io.sb_hready - // sb_axi4_to_ahb.io.ahb_hresp := io.sb_hresp - - val dma_ahb_to_axi4 = Module(new ahb_to_axi4()) dma_ahb_to_axi4.io.scan_mode := io.scan_mode dma_ahb_to_axi4.io.bus_clk_en := io.dma_bus_clk_en dma_ahb_to_axi4.io.clk_override := dec.io.dec_tlu_bus_clk_override - dma_ahb_to_axi4.io.axi_awready := io.dma_axi.aw.ready - dma_ahb_to_axi4.io.axi_wready := io.dma_axi.w.ready - dma_ahb_to_axi4.io.axi_bvalid := io.dma_axi.b.valid - dma_ahb_to_axi4.io.axi_bresp := io.dma_axi.b.bits.resp - dma_ahb_to_axi4.io.axi_bid := io.dma_axi.b.bits.id + dma_ahb_to_axi4.io.axi <> dma_ctrl.io.dma_axi + dma_ahb_to_axi4.io.ahb <> io.dma_ahb - // AXI Read Channels - dma_ahb_to_axi4.io.axi_arready := io.dma_axi.ar.ready - dma_ahb_to_axi4.io.axi_rvalid := io.dma_axi.ar.valid - dma_ahb_to_axi4.io.axi_rid := io.dma_axi.r.bits.id - dma_ahb_to_axi4.io.axi_rdata := io.dma_axi.r.bits.data - dma_ahb_to_axi4.io.axi_rresp := io.dma_axi.r.bits.resp - - // AHB-Lite signals - // dma_ahb_to_axi4.io.ahb_haddr := io.dma_haddr - // dma_ahb_to_axi4.io.ahb_hburst := io.dma_hburst - // dma_ahb_to_axi4.io.ahb_hmastlock := io.dma_hmastlock - // dma_ahb_to_axi4.io.ahb_hprot := io.dma_hprot - // dma_ahb_to_axi4.io.ahb_hsize := io.dma_hsize - // dma_ahb_to_axi4.io.ahb_htrans := io.dma_htrans - // dma_ahb_to_axi4.io.ahb_hwrite := io.dma_hwrite - // dma_ahb_to_axi4.io.ahb_hwdata := io.dma_hwdata - dma_ahb_to_axi4.io.ahb.hsel := io.dma.hsel - dma_ahb_to_axi4.io.ahb.hreadyin := io.dma.hreadyin - lsu.io.axi.aw.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_awready, io.lsu_axi.aw.ready) - lsu.io.axi.w.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_wready, io.lsu_axi.w.ready) - lsu.io.axi.b.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bvalid, io.lsu_axi.b.valid) - lsu.io.axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bresp, io.lsu_axi.b.bits.resp) - lsu.io.axi.b.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_bid, io.lsu_axi.b.bits.id) - lsu.io.axi.ar.ready := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_arready, io.lsu_axi.ar.ready) - lsu.io.axi.r.valid := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rvalid, io.lsu_axi.r.valid) - lsu.io.axi.r.bits.id := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rid, io.lsu_axi.r.bits.id) - lsu.io.axi.r.bits.data := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rdata, io.lsu_axi.r.bits.data) - lsu.io.axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rresp, io.lsu_axi.r.bits.resp) - lsu.io.axi.r.bits.last := Mux(BUILD_AHB_LITE.B, lsu_axi4_to_ahb.io.axi_rlast, io.lsu_axi.r.bits.last) - - ifu.io.ifu.aw.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_awready, io.ifu_axi.aw.ready) - ifu.io.ifu.w.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_wready, io.ifu_axi.w.ready) - ifu.io.ifu.ar.ready := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_arready, io.ifu_axi.ar.ready) - ifu.io.ifu.r.valid := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rvalid, io.ifu_axi.r.valid) - ifu.io.ifu.r.bits.id := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rid, io.ifu_axi.r.bits.id) - ifu.io.ifu.r.bits.data := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rdata, io.ifu_axi.r.bits.data) - ifu.io.ifu.r.bits.resp := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rresp, io.ifu_axi.r.bits.resp) - ifu.io.ifu.r.bits.last := Mux(BUILD_AHB_LITE.B, ifu_axi4_to_ahb.io.axi_rlast, io.ifu_axi.r.bits.last) - - dbg.io.sb_axi.aw.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_awready, io.sb_axi.aw.ready) - dbg.io.sb_axi.w.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_wready, io.sb_axi.w.ready) - dbg.io.sb_axi.b.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bvalid, io.sb_axi.b.valid) - dbg.io.sb_axi.b.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_bresp, io.sb_axi.b.bits.resp) - dbg.io.sb_axi.ar.ready := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_arready, io.sb_axi.ar.ready) - dbg.io.sb_axi.r.valid := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rvalid, io.sb_axi.r.valid) - dbg.io.sb_axi.r.bits.id := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rid, io.sb_axi.r.bits.id) - dbg.io.sb_axi.r.bits.data := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rdata, io.sb_axi.r.bits.data) - dbg.io.sb_axi.r.bits.resp := Mux(BUILD_AHB_LITE.B, sb_axi4_to_ahb.io.axi_rresp, io.sb_axi.r.bits.resp) - - dma_ctrl.io.dma_axi.aw.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awvalid, io.dma_axi.aw.valid) - dma_ctrl.io.dma_axi.aw.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awid, io.dma_axi.aw.bits.id) - dma_ctrl.io.dma_axi.aw.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awaddr, io.dma_axi.aw.bits.addr) - dma_ctrl.io.dma_axi.aw.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_awsize, io.dma_axi.aw.bits.size) - dma_ctrl.io.dma_axi.w.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wvalid, io.dma_axi.w.valid) - dma_ctrl.io.dma_axi.w.bits.data := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wdata, io.dma_axi.w.bits.data) - dma_ctrl.io.dma_axi.w.bits.strb := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_wstrb, io.dma_axi.w.bits.strb) - dma_ctrl.io.dma_axi.b.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_bready, io.dma_axi.b.ready) - dma_ctrl.io.dma_axi.ar.valid := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arvalid, io.dma_axi.ar.valid) - dma_ctrl.io.dma_axi.ar.bits.id := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arid, io.dma_axi.ar.bits.id) - dma_ctrl.io.dma_axi.ar.bits.addr := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_araddr, io.dma_axi.aw.bits.addr) - dma_ctrl.io.dma_axi.ar.bits.size := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_arsize, io.dma_axi.aw.bits.size) - dma_ctrl.io.dma_axi.r.ready := Mux(BUILD_AHB_LITE.B, dma_ahb_to_axi4.io.axi_rready, io.dma_axi.r.ready) - // AHB Signals - io.ahb <> ifu_axi4_to_ahb.io.ahb - - io.lsu_ahb <> lsu_axi4_to_ahb.io.ahb - - io.sb_ahb <> sb_axi4_to_ahb.io.ahb - - io.dma.ahb <> dma_ahb_to_axi4.io.ahb.sig + io.dma_axi <> 0.U.asTypeOf(io.dma_axi) + io.sb_axi <> 0.U.asTypeOf(io.dma_axi) + io.ifu_axi <> 0.U.asTypeOf(io.dma_axi) + io.lsu_axi <> 0.U.asTypeOf(io.dma_axi) } .otherwise{ - // AHB Signals - io.ahb.out <> 0.U.asTypeOf(io.ahb.out) - - io.lsu_ahb.out <> 0.U.asTypeOf(io.lsu_ahb.out) - - io.sb_ahb.out <> 0.U.asTypeOf(io.sb_ahb.out) - - io.dma.ahb.in <> 0.U.asTypeOf(io.dma.ahb.in) + io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb) + io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb) + io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb) + io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb) + dma_ctrl.io.dma_axi <> io.dma_axi + dbg.io.sb_axi <> io.sb_axi + ifu.io.ifu <> io.ifu_axi + lsu.io.axi <> io.lsu_axi } - */ - io.lsu_ahb <> 0.U.asTypeOf(io.lsu_ahb) - io.ifu_ahb <> 0.U.asTypeOf(io.ifu_ahb) - io.sb_ahb <> 0.U.asTypeOf(io.sb_ahb) - io.dma_ahb <> 0.U.asTypeOf(io.dma_ahb) io.dmi_reg_rdata := 0.U } diff --git a/design/src/main/scala/quasar_wrapper.scala b/src/main/scala/quasar_wrapper.scala similarity index 95% rename from design/src/main/scala/quasar_wrapper.scala rename to src/main/scala/quasar_wrapper.scala index 51e49cb3..33820529 100644 --- a/design/src/main/scala/quasar_wrapper.scala +++ b/src/main/scala/quasar_wrapper.scala @@ -93,12 +93,12 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { core.io.dbg_rst_l := io.dbg_rst_l core.io.ic <> mem.io.ic core.io.iccm <> mem.io.iccm - + if(BUILD_AXI4) { - core.io.ifu_ahb <> 0.U.asTypeOf(core.io.lsu_axi) - core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_axi) - core.io.sb_ahb <> 0.U.asTypeOf(core.io.lsu_axi) + core.io.ifu_ahb <> 0.U.asTypeOf(core.io.ifu_ahb) + core.io.lsu_ahb <> 0.U.asTypeOf(core.io.lsu_ahb) + core.io.sb_ahb <> 0.U.asTypeOf(core.io.sb_ahb) core.io.dma_ahb <> 0.U.asTypeOf(core.io.dma_ahb) core.io.lsu_axi <> io.lsu_brg @@ -163,5 +163,5 @@ class quasar_wrapper extends Module with lib with RequireAsyncReset { } object QUASAR_Wrp extends App { - (new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper()) + println((new chisel3.stage.ChiselStage).emitVerilog(new quasar_wrapper())) } \ No newline at end of file diff --git a/design/src/test/scala/lib/Tester.scala b/src/test/scala/lib/Tester.scala similarity index 100% rename from design/src/test/scala/lib/Tester.scala rename to src/test/scala/lib/Tester.scala diff --git a/design/target/.history b/target/.history similarity index 100% rename from design/target/.history rename to target/.history diff --git a/design/target/global-logging/sbt-global-log13192661858450530136.log b/target/global-logging/sbt-global-log13192661858450530136.log similarity index 100% rename from design/target/global-logging/sbt-global-log13192661858450530136.log rename to target/global-logging/sbt-global-log13192661858450530136.log diff --git a/design/target/global-logging/sbt-global-log15583694003838645557.log b/target/global-logging/sbt-global-log15583694003838645557.log similarity index 100% rename from design/target/global-logging/sbt-global-log15583694003838645557.log rename to target/global-logging/sbt-global-log15583694003838645557.log diff --git a/design/target/global-logging/sbt-global-log3143817455308956308.log b/target/global-logging/sbt-global-log3143817455308956308.log similarity index 100% rename from design/target/global-logging/sbt-global-log3143817455308956308.log rename to target/global-logging/sbt-global-log3143817455308956308.log diff --git a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar similarity index 100% rename from design/target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar rename to target/scala-2.12/chisel-module-template_2.12-3.3.0-tests.jar diff --git a/design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar similarity index 100% rename from design/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar rename to target/scala-2.12/chisel-module-template_2.12-3.3.0.jar diff --git a/design/target/scala-2.12/classes/.vscode/settings.json b/target/scala-2.12/classes/.vscode/settings.json similarity index 100% rename from design/target/scala-2.12/classes/.vscode/settings.json rename to target/scala-2.12/classes/.vscode/settings.json diff --git a/target/scala-2.12/classes/QUASAR_Wrp$.class b/target/scala-2.12/classes/QUASAR_Wrp$.class new file mode 100644 index 0000000000000000000000000000000000000000..4d6926f6f0533f9814d005ba4531d12bb3e4a290 GIT binary patch literal 3859 zcmbtX`BxKH7`=}z5+Wc7iqg8p8iE=XE!I#gi&kuK3t+8n>5x2dbeM^giGppd-L(5= z_vOd>ThHmD=+Sff2lS8X>3uU3GDu2uPT?@gy!qa@+;_kG4S)Up;7ca z|LKV{b}kx%5NN)jUDgtYW=PrPJuh|nTLg4Y`O+yF^)Oq#-p^+0qW2wVY zft9I1zDa>bIV&>-N4LzhquGvtIK~p(bfQc)8lBMW>AXPexl}1&+Oc(Wn!8&AhPtUc zgH~3uij-Gu#xe}nPv41|f}>3uGLh2r&Ol*mO4{6=uEeg-H#$-cLtW6Tdu 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design/target/scala-2.12/classes/include/dec_mem_ctrl.class rename to target/scala-2.12/classes/include/dec_mem_ctrl.class index 50272f4c5df1297dec3fa00e32199eaad37be588..2f6f8250ab99c2a66256b682778f239fc6875769 100644 GIT binary patch delta 207 zcmWN?I}1T^90uU`Pcd1<*)2|zvdJI=yVb%6Fw5k6T#nnIevy({hQraZO4)n>rA*2! zgF!NQpXFJ8T+5HkHY`<>dp;<0OBch^hj_l9@}ct zfF>$vVFCkdv~fZQH+1nv ZPx)Y~F#0Nufy!g3su-y$#?EYSdjDj9RQ&(| delta 207 zcmWN?I}1T^90uU`Pcd0s&Tes%luZU1*sT^mfLSKF-!G+pk&;=4!#N$Rl+6cF%A|}2 zgF!NQpXFJ79IKDRY#MSjG+7wB{P=|@wwidix|DgA+kDJl{LG^}O%)E+67w_#0jx^tLeQtcN%9>wJKJ;Lo`W`Js@rwve|PKFCk;SNt(AaNcHkJx@Ak z7kD3k#_#i4{*70My)6$r>*ojfLw<|@;!`{k@fM9ZJHk8oJ#KuOzvWA#-WElj_3|vg z!Snnhf5F40-n7(Nj@R-l{4{^f$N7Sow?Djrr((`7@?$YKIuTofvvDavLV~D}G9+aM zQj)?dNn^FtVU4t)Qo68K4q~13VZHRDO3tBLE+H*fQ6sleE5q0zW5~!8Y?PPSB=4|U zrm#h(u~mMcPX3}^=b=FtqfsNsYB{#)N^I9kG-;+8&6>py&7noRu~QGBRga@h&mgA* uXxBk>=rwfe9qiHv*sbH}(h2O*N$l14*r%V-t>4k3Gw9V>#79TUI`u!B5v{oZ delta 621 zcmWN^J8TSa90%~gm`1HDJj$Gqk(5eSWp#}?vrT#8UBK_sLcNm+^& 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6a0eb50b1fb5beaeb3f03e0df3dfa7ea2b7fb7a9..aa946fae8c95caa345726dac28539ae85d995a80 100644 GIT binary patch delta 43 zcmX@gbChR;A}eF{yx;lNDLTCYP{=@>Vi%F;z3jG1V{_F;z~!#+nZR1x5>6 delta 39 vcmX@gbChR;BJ1QhR q;e02%l7Wk16@wnbYK9<&H4NDdYZ+P?)-fz+SkG{pVddm@u5JJY+8iJN diff --git a/design/target/scala-2.12/classes/include/dma_ifc.class b/target/scala-2.12/classes/include/dma_ifc.class similarity index 90% rename from design/target/scala-2.12/classes/include/dma_ifc.class rename to target/scala-2.12/classes/include/dma_ifc.class index 44fcfbbde24d2debdac7ba8520955c1dc551875b..b4cdafa85abce4593c4915d9b65727131d621a80 100644 GIT binary patch delta 27 jcmcb~b(3quBo;>H$&*>4Ih7c=7?l~68I>k~XGsD8a#;sO delta 27 jcmcb~b(3quBo;=M$&*>4Ih7f>7*!aQ8I>o0XGsD8a)$>= diff --git a/design/target/scala-2.12/classes/include/dma_lsc_ctl.class b/target/scala-2.12/classes/include/dma_lsc_ctl.class similarity index 81% rename from design/target/scala-2.12/classes/include/dma_lsc_ctl.class rename to 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design/target/scala-2.12/classes/include/inst_pkt_t.class rename to target/scala-2.12/classes/include/inst_pkt_t.class diff --git a/design/target/scala-2.12/classes/include/load_cam_pkt_t.class b/target/scala-2.12/classes/include/load_cam_pkt_t.class similarity index 84% rename from design/target/scala-2.12/classes/include/load_cam_pkt_t.class rename to target/scala-2.12/classes/include/load_cam_pkt_t.class index 55e11587c2497f1056da6883eafe0783e229f91a..120fd433ee1d602ca6282de8c1997e9781be32b2 100644 GIT binary patch delta 51 zcmcb{dyRKP1S{jR$&su!lOtHgCa-2ypF9;vzhKQ2T*AP`xQs!LaXEt#;|c~h#wC-J G*h&Dl2M?tH delta 51 zcmcb{dyRKP1ncCftYVY%Sk)(A0@ABl)frb#zRX%DxRim5aXEt=;|c~N#+3|ij7ujc Hv6TP-$43w+ diff --git a/design/target/scala-2.12/classes/include/lsu_dec.class b/target/scala-2.12/classes/include/lsu_dec.class similarity index 85% rename from design/target/scala-2.12/classes/include/lsu_dec.class rename to target/scala-2.12/classes/include/lsu_dec.class index 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design/target/scala-2.12/classes/include/lsu_error_pkt_t.class rename to target/scala-2.12/classes/include/lsu_error_pkt_t.class index c8e989872e7415908fd1e40463dba20e8bb9056f..bc57f17865014108a91dd9c22c5418eedf6e4a95 100644 GIT binary patch delta 79 zcmaDN@I+vPAseImK$?k0GlMUI#Cbt0TJRp4#NUsLc|A6!hAZ^V)Nm7-8i%Fe9 bj!A>Th)I*djY*3kibZ0eI&1L+nZ{Q^iI1k$SPVw3-|sWa+K&Sw*yY|TDNQjLL& eNrOR-Nt3~dNsGaaNt+>xNrxeyNp12o_BsHudK8!d diff --git a/design/target/scala-2.12/classes/include/lsu_exu.class b/target/scala-2.12/classes/include/lsu_exu.class similarity index 88% rename from design/target/scala-2.12/classes/include/lsu_exu.class rename to target/scala-2.12/classes/include/lsu_exu.class index 0fd02d56925f1005df9a3bd68ffdc0fd3f709f89..401e908efc2f53158ab2c6e16f88745116638ddf 100644 GIT binary patch delta 39 xcmV+?0NDSX4xJ9L*#!ZyliCG5li39plPm^x4X^+T0I>ir0I~p50I-v;25%Rh4Hf_Z delta 39 xcmV+?0NDSX4xJ9L*#(mp1{Ra=1t$TslNSbx4Y2?U0I~os0J8v60I`#<25$hj3|asH diff --git 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rename from design/target/scala-2.12/classes/lib/lib$$anon$1.class rename to target/scala-2.12/classes/lib/lib$$anon$1.class diff --git a/design/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class b/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class rename to target/scala-2.12/classes/lib/lib$gated_latch$$anon$4.class diff --git a/design/target/scala-2.12/classes/lib/lib$gated_latch.class b/target/scala-2.12/classes/lib/lib$gated_latch.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$gated_latch.class rename to target/scala-2.12/classes/lib/lib$gated_latch.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class b/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class rename to target/scala-2.12/classes/lib/lib$rvclkhdr$$anon$5.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvclkhdr$.class b/target/scala-2.12/classes/lib/lib$rvclkhdr$.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvclkhdr$.class rename to target/scala-2.12/classes/lib/lib$rvclkhdr$.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvclkhdr.class b/target/scala-2.12/classes/lib/lib$rvclkhdr.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvclkhdr.class rename to target/scala-2.12/classes/lib/lib$rvclkhdr.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvdffe$.class b/target/scala-2.12/classes/lib/lib$rvdffe$.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvdffe$.class rename to target/scala-2.12/classes/lib/lib$rvdffe$.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class b/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class rename to target/scala-2.12/classes/lib/lib$rvecc_encode$$anon$2.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvecc_encode.class b/target/scala-2.12/classes/lib/lib$rvecc_encode.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvecc_encode.class rename to target/scala-2.12/classes/lib/lib$rvecc_encode.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class b/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class rename to target/scala-2.12/classes/lib/lib$rvecc_encode_64$$anon$3.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class b/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvecc_encode_64.class rename to target/scala-2.12/classes/lib/lib$rvecc_encode_64.class diff --git a/design/target/scala-2.12/classes/lib/lib$rvsyncss$.class b/target/scala-2.12/classes/lib/lib$rvsyncss$.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib$rvsyncss$.class rename to target/scala-2.12/classes/lib/lib$rvsyncss$.class diff --git a/design/target/scala-2.12/classes/lib/lib.class b/target/scala-2.12/classes/lib/lib.class similarity index 100% rename from design/target/scala-2.12/classes/lib/lib.class rename to target/scala-2.12/classes/lib/lib.class diff --git a/design/target/scala-2.12/classes/lib/param.class b/target/scala-2.12/classes/lib/param.class similarity index 100% rename from design/target/scala-2.12/classes/lib/param.class rename to target/scala-2.12/classes/lib/param.class diff --git a/design/target/scala-2.12/classes/lsu/lsu$$anon$1.class b/target/scala-2.12/classes/lsu/lsu$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu.class b/target/scala-2.12/classes/lsu/lsu.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu.class rename to target/scala-2.12/classes/lsu/lsu.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_addrcheck$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_addrcheck.class b/target/scala-2.12/classes/lsu/lsu_addrcheck.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_addrcheck.class rename to target/scala-2.12/classes/lsu/lsu_addrcheck.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_bus_buffer$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_bus_buffer.class b/target/scala-2.12/classes/lsu/lsu_bus_buffer.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_bus_buffer.class rename to target/scala-2.12/classes/lsu/lsu_bus_buffer.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_bus_intf$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_bus_intf.class b/target/scala-2.12/classes/lsu/lsu_bus_intf.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_bus_intf.class rename to target/scala-2.12/classes/lsu/lsu_bus_intf.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_clkdomain$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_clkdomain.class b/target/scala-2.12/classes/lsu/lsu_clkdomain.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_clkdomain.class rename to target/scala-2.12/classes/lsu/lsu_clkdomain.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_dccm_ctl$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class b/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_dccm_ctl.class rename to target/scala-2.12/classes/lsu/lsu_dccm_ctl.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class b/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class rename to target/scala-2.12/classes/lsu/lsu_ecc$$anon$1.class diff --git a/design/target/scala-2.12/classes/lsu/lsu_ecc.class b/target/scala-2.12/classes/lsu/lsu_ecc.class similarity index 100% rename from design/target/scala-2.12/classes/lsu/lsu_ecc.class rename to target/scala-2.12/classes/lsu/lsu_ecc.class diff --git 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Qpt%feHm(ouWZ+xwA0^ejhX4Qo delta 676 zcmZ{g%WD%+6vpSv%sn%?N$NBY)3lj}8UjPWmTEVO7Ppp4b>ovFlZnORn;?;D{|8|f zXXmmjDbm1paN>N&hCzOGf55Cp&x=DwE`Nl|dSW;GOK{Ic+9$xouHqw+A+i|P_jarQ^ zDt6I`vNi8`T{ddGi)~|4*kUV<745Us5;QJJJ(X{HNtJuFoTdq~f?>Z5E12{hSe9*Vh8oC~S6 zL7EIg6uC$^ZN!`}6BfI-SA-cg!XE^8 z2SlSL+J&TTimQLMGujMasKV!`IavJRsM<0P?!o3&2S3$ue;mJIN4F}thGcd(b1KfX m_-#$u=O)nZ3A3@#=Jl)+&K|*Ib2q^YRjlrmkIq-|ed-_fbguOP diff --git a/design/target/scala-2.12/classes/vsrc/beh_lib.sv b/target/scala-2.12/classes/vsrc/beh_lib.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/beh_lib.sv rename to target/scala-2.12/classes/vsrc/beh_lib.sv diff --git a/design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv b/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv rename to target/scala-2.12/classes/vsrc/dmi_jtag_to_core_sync.sv diff --git a/target/scala-2.12/classes/vsrc/dmi_wrapper.sv b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv new file mode 100644 index 00000000..d9fd7410 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/dmi_wrapper.sv @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: Apache-2.0 +// Copyright 2018 Western Digital Corporation or it's affiliates. +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +//------------------------------------------------------------------------------------ +// +// Copyright Western Digital, 2018 +// Owner : Anusha Narayanamoorthy +// Description: +// Wrapper module for JTAG_TAP and DMI synchronizer +// +//------------------------------------------------------------------------------------- + +module dmi_wrapper( + + // JTAG signals + input trst_n, // JTAG reset + input tck, // JTAG clock + input tms, // Test mode select + input tdi, // Test Data Input + output tdo, // Test Data Output + output tdoEnable, // Test Data Output enable + + // Processor Signals + input core_rst_n, // Core reset + input core_clk, // Core clock + input [31:1] jtag_id, // JTAG ID + input [31:0] rd_data, // 32 bit Read data from Processor + output [31:0] reg_wr_data, // 32 bit Write data to Processor + output [6:0] reg_wr_addr, // 7 bit reg address to Processor + output reg_en, // 1 bit Read enable to Processor + output reg_wr_en, // 1 bit Write enable to Processor + output dmi_hard_reset +); + + + + + + //Wire Declaration + wire rd_en; + wire wr_en; + wire dmireset; + + + //jtag_tap instantiation + rvjtag_tap i_jtag_tap( + .trst(trst_n), // dedicated JTAG TRST (active low) pad signal or asynchronous active low power on reset + .tck(tck), // dedicated JTAG TCK pad signal + .tms(tms), // dedicated JTAG TMS pad signal + .tdi(tdi), // dedicated JTAG TDI pad signal + .tdo(tdo), // dedicated JTAG TDO pad signal + .tdoEnable(tdoEnable), // enable for TDO pad + .wr_data(reg_wr_data), // 32 bit Write data + .wr_addr(reg_wr_addr), // 7 bit Write address + .rd_en(rd_en), // 1 bit read enable + .wr_en(wr_en), // 1 bit Write enable + .rd_data(rd_data), // 32 bit Read data + .rd_status(2'b0), + .idle(3'h0), // no need to wait to sample data + .dmi_stat(2'b0), // no need to wait or error possible + .version(4'h1), // debug spec 0.13 compliant + .jtag_id(jtag_id), + .dmi_hard_reset(dmi_hard_reset), + .dmi_reset(dmireset) +); + + + // dmi_jtag_to_core_sync instantiation + dmi_jtag_to_core_sync i_dmi_jtag_to_core_sync( + .wr_en(wr_en), // 1 bit Write enable + .rd_en(rd_en), // 1 bit Read enable + + .rst_n(core_rst_n), + .clk(core_clk), + .reg_en(reg_en), // 1 bit Write interface bit + .reg_wr_en(reg_wr_en) // 1 bit Write enable + ); + +endmodule diff --git a/design/target/scala-2.12/classes/vsrc/gated_latch.sv b/target/scala-2.12/classes/vsrc/gated_latch.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/gated_latch.sv rename to target/scala-2.12/classes/vsrc/gated_latch.sv diff --git a/target/scala-2.12/classes/vsrc/gated_latch.v b/target/scala-2.12/classes/vsrc/gated_latch.v new file mode 100644 index 00000000..36570337 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/gated_latch.v @@ -0,0 +1,14 @@ +module gated_latch + ( + input wire SE, EN, CK, + output Q + ); + reg en_ff; + wire enable; + assign enable = EN | SE; + always @(CK, enable) begin + if(!CK) + en_ff = enable; + end + assign Q = CK & en_ff; +endmodule diff --git a/design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv b/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/ifu_ic_mem.sv rename to target/scala-2.12/classes/vsrc/ifu_ic_mem.sv diff --git a/design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv b/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv rename to target/scala-2.12/classes/vsrc/ifu_iccm_mem.sv diff --git a/design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv b/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv rename to target/scala-2.12/classes/vsrc/lsu_dccm_mem.sv diff --git a/target/scala-2.12/classes/vsrc/mem.sv b/target/scala-2.12/classes/vsrc/mem.sv new file mode 100644 index 00000000..0aee1897 --- /dev/null +++ b/target/scala-2.12/classes/vsrc/mem.sv @@ -0,0 +1,173 @@ + +module mem #( + parameter ICACHE_BEAT_BITS, + parameter ICCM_BITS, + parameter ICACHE_NUM_WAYS, + parameter DCCM_BYTE_WIDTH, + parameter ICCM_BANK_INDEX_LO, + parameter ICACHE_BANK_BITS, + parameter DCCM_BITS, + parameter ICACHE_BEAT_ADDR_HI, + parameter ICCM_INDEX_BITS, + parameter ICCM_BANK_HI, + parameter ICACHE_BANKS_WAY, + parameter ICACHE_INDEX_HI, + parameter DCCM_NUM_BANKS, + parameter ICACHE_BANK_HI, + parameter ICACHE_BANK_LO, + parameter DCCM_ENABLE= 'b1, + parameter ICACHE_TAG_LO, + parameter ICACHE_DATA_INDEX_LO, + parameter ICCM_NUM_BANKS, + parameter ICACHE_ECC, + parameter ICACHE_ENABLE= 'b1, + parameter DCCM_BANK_BITS, + parameter ICCM_ENABLE= 'b1, + parameter ICCM_BANK_BITS, + parameter ICACHE_TAG_DEPTH, + parameter ICACHE_WAYPACK, + parameter DCCM_SIZE, + parameter DCCM_FDATA_WIDTH, + parameter ICACHE_TAG_INDEX_LO, + parameter ICACHE_DATA_DEPTH) +( + input logic clk, + input logic rst_l, + input logic dccm_clk_override, + input logic icm_clk_override, + input logic dec_tlu_core_ecc_disable, + + //DCCM ports + input logic dccm_wren, + input logic dccm_rden, + input logic [DCCM_BITS-1:0] dccm_wr_addr_lo, + input logic [DCCM_BITS-1:0] dccm_wr_addr_hi, + input logic [DCCM_BITS-1:0] dccm_rd_addr_lo, + input logic [DCCM_BITS-1:0] dccm_rd_addr_hi, + input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_lo, + input logic [DCCM_FDATA_WIDTH-1:0] dccm_wr_data_hi, + + + output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_lo, + output logic [DCCM_FDATA_WIDTH-1:0] dccm_rd_data_hi, + +//`ifdef DCCM_ENABLE + +//`endif + + //ICCM ports + + input logic [ICCM_BITS-1:1] iccm_rw_addr, + input logic iccm_buf_correct_ecc, // ICCM is doing a single bit error correct cycle + input logic iccm_correction_state, // ICCM is doing a single bit error correct cycle + input logic iccm_wren, + input logic iccm_rden, + input logic [2:0] iccm_wr_size, + input logic [77:0] iccm_wr_data, + + output logic [63:0] iccm_rd_data, + output logic [77:0] iccm_rd_data_ecc, + + // Icache and Itag Ports + + input logic [31:1] ic_rw_addr, + input logic [ICACHE_NUM_WAYS-1:0] ic_tag_valid, + input logic [ICACHE_NUM_WAYS-1:0] ic_wr_en, + input logic ic_rd_en, + input logic [63:0] ic_premux_data, // Premux data to be muxed with each way of the Icache. + input logic ic_sel_premux_data, // Premux data sel + + input logic [70:0] ic_wr_data_0, // Data to fill to the Icache. With ECC + input logic [70:0] ic_wr_data_1, + input logic [70:0] ic_debug_wr_data, // Debug wr cache. + output logic [70:0] ic_debug_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC + input logic [ICACHE_INDEX_HI:3] ic_debug_addr, // Read/Write addresss to the Icache. + input logic ic_debug_rd_en, // Icache debug rd + input logic ic_debug_wr_en, // Icache debug wr + input logic ic_debug_tag_array, // Debug tag array + input logic [ICACHE_NUM_WAYS-1:0] ic_debug_way, // Debug way. Rd or Wr. + + output logic [63:0] ic_rd_data , // Data read from Icache. 2x64bits + parity bits. F2 stage. With ECC + output logic [25:0] ic_tag_debug_rd_data,// Debug icache tag. + + + output logic [ICACHE_BANKS_WAY-1:0] ic_eccerr, // ecc error per bank + output logic [ICACHE_BANKS_WAY-1:0] ic_parerr, // parity error per bank + output logic [ICACHE_NUM_WAYS-1:0] ic_rd_hit, + output logic ic_tag_perr, // Icache Tag parity error + + + input logic scan_mode + +); + + logic [ICACHE_BANKS_WAY-1:0][70:0] ic_wr_data; +assign ic_wr_data [0] = ic_wr_data_0; +assign ic_wr_data [1] = ic_wr_data_1; + // DCCM Instantiation + if (DCCM_ENABLE == 1) begin: Gen_dccm_enable + lsu_dccm_mem #( + .DCCM_BYTE_WIDTH(DCCM_BYTE_WIDTH), + .DCCM_BITS(DCCM_BITS), + .DCCM_NUM_BANKS(DCCM_NUM_BANKS), + .DCCM_BANK_BITS(DCCM_BANK_BITS), + .DCCM_SIZE(DCCM_SIZE), + .DCCM_FDATA_WIDTH(DCCM_FDATA_WIDTH)) dccm ( + .clk_override(dccm_clk_override), + .* + ); + end else begin: Gen_dccm_disable + assign dccm_rd_data_lo = '0; + assign dccm_rd_data_hi = '0; + end + +if ( ICACHE_ENABLE ) begin: icache + ifu_ic_mem #( + .ICACHE_BEAT_BITS(ICACHE_BEAT_BITS), + .ICACHE_NUM_WAYS(ICACHE_NUM_WAYS), + .ICACHE_BANK_BITS(ICACHE_BANK_BITS), + .ICACHE_BEAT_ADDR_HI(ICACHE_BEAT_ADDR_HI), + .ICACHE_BANKS_WAY(ICACHE_BANKS_WAY), + .ICACHE_INDEX_HI(ICACHE_INDEX_HI), + .ICACHE_BANK_HI(ICACHE_BANK_HI), + .ICACHE_BANK_LO(ICACHE_BANK_LO), + .ICACHE_TAG_LO(ICACHE_TAG_LO), + .ICACHE_DATA_INDEX_LO(ICACHE_DATA_INDEX_LO), + .ICACHE_ECC(ICACHE_ECC), + .ICACHE_TAG_DEPTH(ICACHE_TAG_DEPTH), + .ICACHE_WAYPACK(ICACHE_WAYPACK), + .ICACHE_TAG_INDEX_LO(ICACHE_TAG_INDEX_LO), + .ICACHE_DATA_DEPTH(ICACHE_DATA_DEPTH)) icm ( + .clk_override(icm_clk_override), + .* + ); +end +else begin + assign ic_rd_hit[ICACHE_NUM_WAYS-1:0] = '0; + assign ic_tag_perr = '0 ; + assign ic_rd_data = '0 ; + assign ic_tag_debug_rd_data = '0 ; +end // else: !if( ICACHE_ENABLE ) + + + +if (ICCM_ENABLE) begin : iccm + ifu_iccm_mem #( + .ICCM_BITS(ICCM_BITS), + .ICCM_BANK_INDEX_LO(ICCM_BANK_INDEX_LO), + .ICCM_INDEX_BITS(ICCM_INDEX_BITS), + .ICCM_BANK_HI(ICCM_BANK_HI), + .ICCM_NUM_BANKS(ICCM_NUM_BANKS), + .ICCM_BANK_BITS(ICCM_BANK_BITS)) iccm (.*, + .clk_override(icm_clk_override), + .iccm_rw_addr(iccm_rw_addr[ICCM_BITS-1:1]), + .iccm_rd_data(iccm_rd_data[63:0]) + ); +end +else begin + assign iccm_rd_data = '0 ; + assign iccm_rd_data_ecc = '0 ; +end + + +endmodule diff --git a/design/target/scala-2.12/classes/vsrc/mem_lib.sv b/target/scala-2.12/classes/vsrc/mem_lib.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/mem_lib.sv rename to target/scala-2.12/classes/vsrc/mem_lib.sv diff --git a/design/target/scala-2.12/classes/vsrc/mem_mod.sv b/target/scala-2.12/classes/vsrc/mem_mod.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/mem_mod.sv rename to target/scala-2.12/classes/vsrc/mem_mod.sv diff --git a/design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv b/target/scala-2.12/classes/vsrc/rvjtag_tap.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/rvjtag_tap.sv rename to target/scala-2.12/classes/vsrc/rvjtag_tap.sv diff --git a/design/target/scala-2.12/classes/vsrc/rvtaj_tap.sv b/target/scala-2.12/classes/vsrc/rvtaj_tap.sv similarity index 100% rename from design/target/scala-2.12/classes/vsrc/rvtaj_tap.sv rename to target/scala-2.12/classes/vsrc/rvtaj_tap.sv diff --git a/design/target/scala-2.12/update/update_cache_2.12/inputs b/target/scala-2.12/update/update_cache_2.12/inputs similarity index 100% rename from design/target/scala-2.12/update/update_cache_2.12/inputs rename to target/scala-2.12/update/update_cache_2.12/inputs diff --git a/design/target/scala-2.12/update/update_cache_2.12/output b/target/scala-2.12/update/update_cache_2.12/output similarity index 100% rename from design/target/scala-2.12/update/update_cache_2.12/output rename to target/scala-2.12/update/update_cache_2.12/output diff --git a/design/target/streams/_global/_global/_global/streams/out b/target/streams/_global/_global/_global/streams/out similarity index 100% rename from design/target/streams/_global/_global/_global/streams/out rename to target/streams/_global/_global/_global/streams/out diff --git a/design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous b/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous similarity index 100% rename from design/target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous rename to target/streams/_global/_global/checkBuildSources/_global/inputFileStamps/previous diff --git a/design/target/streams/_global/_global/checkBuildSources/_global/streams/out b/target/streams/_global/_global/checkBuildSources/_global/streams/out similarity index 100% rename from design/target/streams/_global/_global/checkBuildSources/_global/streams/out rename to target/streams/_global/_global/checkBuildSources/_global/streams/out diff --git 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target/streams/test/dependencyClasspath/_global/streams/export diff --git a/design/target/streams/test/dependencyClasspathAsJars/_global/streams/export b/target/streams/test/dependencyClasspathAsJars/_global/streams/export similarity index 100% rename from design/target/streams/test/dependencyClasspathAsJars/_global/streams/export rename to target/streams/test/dependencyClasspathAsJars/_global/streams/export diff --git a/design/target/streams/test/exportedProductJars/_global/streams/export b/target/streams/test/exportedProductJars/_global/streams/export similarity index 100% rename from design/target/streams/test/exportedProductJars/_global/streams/export rename to target/streams/test/exportedProductJars/_global/streams/export diff --git a/design/target/streams/test/exportedProducts/_global/streams/export b/target/streams/test/exportedProducts/_global/streams/export similarity index 100% rename from design/target/streams/test/exportedProducts/_global/streams/export rename to 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