diff --git a/el2_dec_dec_ctl.fir b/el2_dec_dec_ctl.fir index 85decf02..6d1c1f89 100644 --- a/el2_dec_dec_ctl.fir +++ b/el2_dec_dec_ctl.fir @@ -2026,15 +2026,16 @@ circuit el2_dec_dec_ctl : node _T_1969 = bits(io.ins, 4, 4) @[el2_dec_dec_ctl.scala 67:33] node _T_1970 = bits(io.ins, 3, 3) @[el2_dec_dec_ctl.scala 67:52] node _T_1971 = eq(_T_1970, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:33] - node _T_1973 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] - node _T_1974 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] - node _T_1975 = eq(_T_1974, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] - node _T_1976 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:42] - node _T_1977 = and(_T_1976, _T_1971) @[el2_dec_dec_ctl.scala 168:42] - node _T_1978 = and(_T_1977, _T_1972) @[el2_dec_dec_ctl.scala 168:42] - node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:42] - node _T_1980 = and(_T_1979, _T_1975) @[el2_dec_dec_ctl.scala 168:42] - node _T_1981 = or(_T_1966, _T_1980) @[el2_dec_dec_ctl.scala 167:103] - io.out.legal <= _T_1981 @[el2_dec_dec_ctl.scala 153:16] + node _T_1972 = bits(io.ins, 2, 2) @[el2_dec_dec_ctl.scala 67:52] + node _T_1973 = eq(_T_1972, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1974 = bits(io.ins, 1, 1) @[el2_dec_dec_ctl.scala 67:33] + node _T_1975 = bits(io.ins, 0, 0) @[el2_dec_dec_ctl.scala 67:52] + node _T_1976 = eq(_T_1975, UInt<1>("h00")) @[el2_dec_dec_ctl.scala 67:45] + node _T_1977 = and(_T_1968, _T_1969) @[el2_dec_dec_ctl.scala 168:43] + node _T_1978 = and(_T_1977, _T_1971) @[el2_dec_dec_ctl.scala 168:43] + node _T_1979 = and(_T_1978, _T_1973) @[el2_dec_dec_ctl.scala 168:43] + node _T_1980 = and(_T_1979, _T_1974) @[el2_dec_dec_ctl.scala 168:43] + node _T_1981 = and(_T_1980, _T_1976) @[el2_dec_dec_ctl.scala 168:43] + node _T_1982 = or(_T_1966, _T_1981) @[el2_dec_dec_ctl.scala 167:103] + io.out.legal <= _T_1982 @[el2_dec_dec_ctl.scala 153:16] diff --git a/el2_dec_dec_ctl.v b/el2_dec_dec_ctl.v index 715641b1..27f11f04 100644 --- a/el2_dec_dec_ctl.v +++ b/el2_dec_dec_ctl.v @@ -646,11 +646,11 @@ module el2_dec_dec_ctl( wire _T_1964 = _T_1963 & io_ins[1]; // @[el2_dec_dec_ctl.scala 167:99] wire _T_1965 = _T_1964 & _T_1281; // @[el2_dec_dec_ctl.scala 167:99] wire _T_1966 = _T_1943 | _T_1965; // @[el2_dec_dec_ctl.scala 167:50] - wire _T_1976 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:42] - wire _T_1977 = _T_1976 & _T_100; // @[el2_dec_dec_ctl.scala 168:42] - wire _T_1978 = _T_1977 & io_ins[2]; // @[el2_dec_dec_ctl.scala 168:42] - wire _T_1979 = _T_1978 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:42] - wire _T_1980 = _T_1979 & _T_1281; // @[el2_dec_dec_ctl.scala 168:42] + wire _T_1977 = _T_104 & io_ins[4]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1978 = _T_1977 & _T_100; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1979 = _T_1978 & _T_18; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1980 = _T_1979 & io_ins[1]; // @[el2_dec_dec_ctl.scala 168:43] + wire _T_1981 = _T_1980 & _T_1281; // @[el2_dec_dec_ctl.scala 168:43] assign io_out_alu = _T_7 | _T_11; // @[el2_dec_dec_ctl.scala 72:14] assign io_out_rs1 = _T_102 | _T_107; // @[el2_dec_dec_ctl.scala 73:14] assign io_out_rs2 = _T_115 | _T_122; // @[el2_dec_dec_ctl.scala 79:14] @@ -700,5 +700,5 @@ module el2_dec_dec_ctl( assign io_out_fence = _T_9 & io_ins[3]; // @[el2_dec_dec_ctl.scala 137:16] assign io_out_fence_i = _T_997 & io_ins[3]; // @[el2_dec_dec_ctl.scala 138:18] assign io_out_pm_alu = _T_1021 | _T_11; // @[el2_dec_dec_ctl.scala 139:17] - assign io_out_legal = _T_1966 | _T_1980; // @[el2_dec_dec_ctl.scala 153:16] + assign io_out_legal = _T_1966 | _T_1981; // @[el2_dec_dec_ctl.scala 153:16] endmodule diff --git a/src/main/scala/dec/el2_dec_dec_ctl.scala b/src/main/scala/dec/el2_dec_dec_ctl.scala index 5188f92a..3407d605 100644 --- a/src/main/scala/dec/el2_dec_dec_ctl.scala +++ b/src/main/scala/dec/el2_dec_dec_ctl.scala @@ -169,6 +169,5 @@ class el2_dec_dec_ctl extends Module{ } object dec extends App { - chisel3.Driver.execute(args, () => new el2_dec_dec_ctl()) - println(Driver.emitVerilog(new el2_dec_dec_ctl())) + println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl())) } diff --git a/src/main/scala/snapshot/el2_param.scala b/src/main/scala/snapshot/el2_param.scala index ceffa982..40978129 100644 --- a/src/main/scala/snapshot/el2_param.scala +++ b/src/main/scala/snapshot/el2_param.scala @@ -1,5 +1,158 @@ package snapshot +import chisel3._ -class el2_param { - +object pt{ + val BHT_ADDR_HI = "h9".U(4.W) + val BHT_ADDR_LO = "h2".U(2.W) + val BHT_ARRAY_DEPTH = "h100".U(11.W) + val BHT_GHR_HASH_1 = "h0".U(1.W) + val BHT_GHR_SIZE = "8h".U(4.W) + val BHT_SIZE = "h200".U(12.W) + val BTB_ADDR_HI = "h09".U(5.W) + val BTB_ADDR_LO = "h2".U(2.W) + val BTB_ARRAY_DEPTH = "h100".U(9.W) + val BTB_BTAG_FOLD = "h0".U(1.W) + val BTB_BTAG_SIZE = "h5".U(4.W) + val BTB_FOLD2_INDEX_HASH = "h0".U(1.W) + val BTB_INDEX1_HI = "h09".U(5.W) + val BTB_INDEX1_LO = "h02".U(5.W) + val BTB_INDEX2_HI = "h11".U(5.W) + val BTB_INDEX2_LO = "h0A".U(5.W) + val BTB_INDEX3_HI = "h19".U(5.W) + val BTB_INDEX3_LO = "h12".U(5.W) + val BTB_SIZE = "h200".U(10.W) + val BUILD_AHB_LITE = "h0".U(1.W) + val BUILD_AXI4 = "h1".U(1.W) + val BUILD_AXI_NATIVE = "h1".U(1.W) + val BUS_PRTY_DEFAULT = "h3".U(2.W) + val DATA_ACCESS_ADDR0 = "h00000000".U(32.W) + val DATA_ACCESS_ADDR1 = "hC0000000".U(32.W) + val DATA_ACCESS_ADDR2 = "hA0000000".U(32.W) + val DATA_ACCESS_ADDR3 = "h80000000".U(32.W) + val DATA_ACCESS_ADDR4 = "h00000000".U(32.W) + val DATA_ACCESS_ADDR5 = "h00000000".U(32.W) + val DATA_ACCESS_ADDR6 = "h00000000".U(32.W) + val DATA_ACCESS_ADDR7 = "h00000000".U(32.W) + val DATA_ACCESS_ENABLE0 = "h1".U(1.W) + val DATA_ACCESS_ENABLE1 = "h1".U(1.W) + val DATA_ACCESS_ENABLE2 = "h1".U(1.W) + val DATA_ACCESS_ENABLE3 = "h1".U(1.W) + val DATA_ACCESS_ENABLE4 = "h0".U(1.W) + val DATA_ACCESS_ENABLE5 = "h0".U(1.W) + val DATA_ACCESS_ENABLE6 = "h0".U(1.W) + val DATA_ACCESS_ENABLE7 = "h0".U(1.W) + val DATA_ACCESS_MASK0 = "h7FFFFFFF".U(32.W) + val DATA_ACCESS_MASK1 = "h3FFFFFFF".U(32.W) + val DATA_ACCESS_MASK2 = "h1FFFFFFF".U(32.W) + val DATA_ACCESS_MASK3 = "h0FFFFFFF".U(32.W) + val DATA_ACCESS_MASK4 = "hFFFFFFFF".U(32.W) + val DATA_ACCESS_MASK5 = "hFFFFFFFF".U(32.W) + val DATA_ACCESS_MASK6 = "hFFFFFFFF".U(32.W) + val DATA_ACCESS_MASK7 = "hFFFFFFFF".U(32.W) + val DCCM_BANK_BITS = "h2".U(3.W) + val DCCM_BITS = "h10".U(5.W) + val DCCM_BYTE_WIDTH = "h4".U(3.W) + val DCCM_DATA_WIDTH = "h20".U(6.W) + val DCCM_ECC_WIDTH = "h7".U(3.W) + val DCCM_ENABLE = "h1".U(1.W) + val DCCM_FDATA_WIDTH = "h27".U(6.W) + val DCCM_INDEX_BITS = "hC".U(4.W) + val DCCM_NUM_BANKS = "h04".U(5.W) + val DCCM_REGION = "hF".U(4.W) + val DCCM_SADR = "hF0040000".U(32.W) + val DCCM_SIZE = "h040".U(10.W) + val DCCM_WIDTH_BITS = "h2".U(2.W) + val DMA_BUF_DEPTH = "h5".U(3.W) + val DMA_BUS_ID = "h1".U(1.W) + val DMA_BUS_PRTY = "h2".U(2.W) + val DMA_BUS_TAG = "h1".U(4.W) + val FAST_INTERRUPT_REDIRECT= "h1".U(1.W) + val ICACHE_2BANKS = "h1".U(1.W) + val ICACHE_BANK_BITS = "h1".U(3.W) + val ICACHE_BANK_HI = "h3".U(3.W) + val ICACHE_BANK_LO = "h3".U(2.W) + val ICACHE_BANK_WIDTH = "h8".U(4.W) + val ICACHE_BANKS_WAY = "h2".U(3.W) + val ICACHE_BEAT_ADDR_HI = "h5".U(4.W) + val ICACHE_BEAT_BITS = "h3".U(4.W) + val ICACHE_DATA_DEPTH = "h0200".U(14.W) + val ICACHE_DATA_INDEX_LO = "h4".U(3.W) + val ICACHE_DATA_WIDTH = "h40".U(7.W) + val ICACHE_ECC = "h1".U(1.W) + val ICACHE_ENABLE = "h1".U(1.W) + val ICACHE_FDATA_WIDTH = "h47".U(7.W) + val ICACHE_INDEX_HI = "h0C".U(5.W) + val ICACHE_LN_SZ = "h40".U(7.W) + val ICACHE_NUM_BEATS = "h8".U(4.W) + val ICACHE_NUM_WAYS = "h2".U(3.W) + val ICACHE_ONLY = "h0".U(1.W) + val ICACHE_SCND_LAST = "h6".U(4.W) + val ICACHE_SIZE = "h010".U(9.W) + val ICACHE_STATUS_BITS = "h1".U(3.W) + val ICACHE_TAG_DEPTH = "h0080".U(13.W) + val ICACHE_TAG_INDEX_LO = "h6".U(3.W) + val ICACHE_TAG_LO = "h0D".U(5.W) + val ICACHE_WAYPACK = "h0".U(1.W) + val ICCM_BANK_BITS = "h2".U(3.W) + val ICCM_BANK_HI = "h03".U(5.W) + val ICCM_BANK_INDEX_LO = "h04".U(5.W) + val ICCM_BITS = "h10".U(5.W) + val ICCM_ENABLE = "h1".U(1.W) + val ICCM_ICACHE = "h1".U(1.W) + val ICCM_INDEX_BITS = "hC".U(4.W) + val ICCM_NUM_BANKS = "h04".U(5.W) + val ICCM_ONLY = "h0".U(1.W) + val ICCM_REGION = "hE".U(4.W) + val ICCM_SADR = "hEE000000".U(32.W) + val ICCM_SIZE = "h040".U(10.W) + val IFU_BUS_ID = "h1".U(1.W) + val IFU_BUS_PRTY = "h2".U(2.W) + val IFU_BUS_TAG = "h3".U(4.W) + val INST_ACCESS_ADDR0 = "h00000000".U(32.W) + val INST_ACCESS_ADDR1 = "hC0000000".U(32.W) + val INST_ACCESS_ADDR2 = "hA0000000".U(32.W) + val INST_ACCESS_ADDR3 = "h80000000".U(32.W) + val INST_ACCESS_ADDR4 = "h00000000".U(32.W) + val INST_ACCESS_ADDR5 = "h00000000".U(32.W) + val INST_ACCESS_ADDR6 = "h00000000".U(32.W) + val INST_ACCESS_ADDR7 = "h00000000".U(32.W) + val INST_ACCESS_ENABLE0 = "h1".U(1.W) + val INST_ACCESS_ENABLE1 = "h1".U(1.W) + val INST_ACCESS_ENABLE2 = "h1".U(1.W) + val INST_ACCESS_ENABLE3 = "h1".U(1.W) + val INST_ACCESS_ENABLE4 = "h0".U(1.W) + val INST_ACCESS_ENABLE5 = "h0".U(1.W) + val INST_ACCESS_ENABLE6 = "h0".U(1.W) + val INST_ACCESS_ENABLE7 = "h0".U(1.W) + val INST_ACCESS_MASK0 = "h7FFFFFFF".U(32.W) + val INST_ACCESS_MASK1 = "h3FFFFFFF".U(32.W) + val INST_ACCESS_MASK2 = "h1FFFFFFF".U(32.W) + val INST_ACCESS_MASK3 = "h0FFFFFFF".U(32.W) + val INST_ACCESS_MASK4 = "hFFFFFFFF".U(32.W) + val INST_ACCESS_MASK5 = "hFFFFFFFF".U(32.W) + val INST_ACCESS_MASK6 = "hFFFFFFFF".U(32.W) + val INST_ACCESS_MASK7 = "hFFFFFFFF".U(32.W) + val LOAD_TO_USE_PLUS1 = "h0".U(1.W) + val LSU2DMA = "h0".U(1.W) + val LSU_BUS_ID = "h1".U(1.W) + val LSU_BUS_PRTY = "h2".U(2.W) + val LSU_BUS_TAG = "h3".U(4.W) + val LSU_NUM_NBLOAD = "h04".U(5.W) + val LSU_NUM_NBLOAD_WIDTH = "h2".U(3.W) + val LSU_SB_BITS = "h10".U(5.W) + val LSU_STBUF_DEPTH = "h4".U(4.W) + val NO_ICCM_NO_ICACHE = "h0".U(1.W) + val PIC_2CYCLE = "h0".U(1.W) + val PIC_BASE_ADDR = "hF00C0000".U(32.W) + val PIC_BITS = "h0F".U(5.W) + val PIC_INT_WORDS = "h1".U(4.W) + val PIC_REGION = "hF".U(4.W) + val PIC_SIZE = "h020".U(9.W) + val PIC_TOTAL_INT = "h1F".U(8.W) + val PIC_TOTAL_INT_PLUS1 = "h020".U(9.W) + val RET_STACK_SIZE = "h8".U(4.W) + val SB_BUS_ID = "h1".U(1.W) + val SB_BUS_PRTY = "h2".U(2.W) + val SB_BUS_TAG = "h1".U(4.W) + val TIMER_LEGAL_EN = "h1".U(1.W) } diff --git a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar index 3a26a8a4..1b3c0211 100644 Binary files a/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar and b/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar differ diff --git a/target/scala-2.12/classes/dbg/el2_dbg.class b/target/scala-2.12/classes/dbg/el2_dbg.class new file mode 100644 index 00000000..cef85577 Binary files /dev/null and b/target/scala-2.12/classes/dbg/el2_dbg.class differ diff --git a/target/scala-2.12/classes/dec/dec$.class b/target/scala-2.12/classes/dec/dec$.class index 3634e2ed..36513d4d 100644 Binary files a/target/scala-2.12/classes/dec/dec$.class and b/target/scala-2.12/classes/dec/dec$.class differ diff --git a/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class b/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class index afc6d858..9b3c30e8 100644 Binary files a/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class and b/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class differ diff --git a/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class b/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class new file mode 100644 index 00000000..56370fa1 Binary files /dev/null and b/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class differ diff --git a/target/scala-2.12/classes/dmi/dmi_wrapper.class b/target/scala-2.12/classes/dmi/dmi_wrapper.class new file mode 100644 index 00000000..8de59608 Binary files /dev/null and b/target/scala-2.12/classes/dmi/dmi_wrapper.class differ diff --git a/target/scala-2.12/classes/dmi/rvjtag_tap.class b/target/scala-2.12/classes/dmi/rvjtag_tap.class new file mode 100644 index 00000000..0c060405 Binary files /dev/null and b/target/scala-2.12/classes/dmi/rvjtag_tap.class differ diff --git a/target/scala-2.12/classes/exu/el2_exu.class b/target/scala-2.12/classes/exu/el2_exu.class new file mode 100644 index 00000000..783b5e0a Binary files /dev/null and b/target/scala-2.12/classes/exu/el2_exu.class differ diff --git a/target/scala-2.12/classes/ifu/el2_ifu.class b/target/scala-2.12/classes/ifu/el2_ifu.class new file mode 100644 index 00000000..8724b649 Binary files /dev/null and b/target/scala-2.12/classes/ifu/el2_ifu.class differ diff --git a/target/scala-2.12/classes/include/el2_bundle.class b/target/scala-2.12/classes/include/el2_bundle.class new file mode 100644 index 00000000..8eb882cf Binary files /dev/null and b/target/scala-2.12/classes/include/el2_bundle.class differ diff --git a/target/scala-2.12/classes/lsu/el2_lsu.class b/target/scala-2.12/classes/lsu/el2_lsu.class new file mode 100644 index 00000000..936e7d04 Binary files /dev/null and b/target/scala-2.12/classes/lsu/el2_lsu.class differ diff --git a/target/scala-2.12/classes/snapshot/pt$.class b/target/scala-2.12/classes/snapshot/pt$.class new file mode 100644 index 00000000..42c5a973 Binary files /dev/null and b/target/scala-2.12/classes/snapshot/pt$.class differ diff --git a/target/scala-2.12/classes/snapshot/pt.class b/target/scala-2.12/classes/snapshot/pt.class new file mode 100644 index 00000000..17217ac1 Binary files /dev/null and b/target/scala-2.12/classes/snapshot/pt.class differ diff --git a/target/streams/compile/_global/_global/compileOutputs/previous b/target/streams/compile/_global/_global/compileOutputs/previous index 89c057c2..ef0d2540 100644 --- a/target/streams/compile/_global/_global/compileOutputs/previous +++ b/target/streams/compile/_global/_global/compileOutputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file +["sbt.Task[scala.collection.Seq[java.nio.file.Path]]",["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dbg/el2_dbg.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_wrapper.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt$.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/exu/el2_exu.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/rvjtag_tap.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lsu/el2_lsu.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/include/el2_bundle.class","/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/streams/compile/compileOutputs/_global/streams/inc_compile_2.12.zip"]] \ No newline at end of file diff --git a/target/streams/compile/_global/_global/compileSourceFileInputs/previous b/target/streams/compile/_global/_global/compileSourceFileInputs/previous index 02241a42..7d7fd69c 100644 --- a/target/streams/compile/_global/_global/compileSourceFileInputs/previous +++ b/target/streams/compile/_global/_global/compileSourceFileInputs/previous @@ -1 +1 @@ -["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala","bf772bd5f03f6938a3504872c23458ba6e032de2"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala","21b7b4ecacf689e7624e3b296d935d5e5a464bc3"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala","5f6161a41c08923a7d412d6c72024b0e498bb8a9"]],"lastModifiedTimes":[]}}] \ No newline at end of file +["sbt.Task[scala.collection.immutable.Map[java.lang.String, scala.collection.Seq[scala.Tuple2[java.nio.file.Path, sbt.nio.FileStamp]]]]",{"2.12.10":{"hashes":[["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/ifu/el2_ifu.scala","90ccc65ac7488b8494521c865b772c52b8366feb"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/snapshot/el2_param.scala","9d4cedee7eee5415275809ba6f02d693324110fd"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lsu/el2_lsu.scala","1ef8375e06a926acc2800ce9f66b230a1a778a47"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/exu/el2_exu.scala","3f9225ed252ed66244ffaadc30181214d49eae29"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dbg/el2_dbg.scala","a9288ad33e4be923745906ebdbedfc6940f5938b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala","bf772bd5f03f6938a3504872c23458ba6e032de2"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala","21b7b4ecacf689e7624e3b296d935d5e5a464bc3"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/rvjtag_tap.scala","725d115902c1948b83040e3ae82f26ae3d44ee4b"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_jtag_to_core_sync.scala","973d8d71d39c2efb8a9869b538f76cb3f12fbd98"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dmi/dmi_wrapper.scala","e57d82ef2ee034749d59900097403d64f5d99c7f"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/include/el2_bundle.scala","7305502ad88955c24e9f36a285410245bbd70b91"],["/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala","84211b988157662baf5d608862039be53d036cb8"]],"lastModifiedTimes":[]}}] \ No newline at end of file diff --git a/target/streams/compile/compile/_global/streams/out b/target/streams/compile/compile/_global/streams/out index 95f4a31a..4f942e88 100644 --- a/target/streams/compile/compile/_global/streams/out +++ b/target/streams/compile/compile/_global/streams/out @@ -1,6 +1,5 @@ -[error] /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala:173:12: type mismatch; -[error]  found : Unit -[error]  required: dec.el2_dec_dec_ctl => chisel3.iotesters.PeekPokeTester[dec.el2_dec_dec_ctl] -[error]  println(chisel3.Driver.emitVerilog(new el2_dec_dec_ctl())) -[error]  ^ -[error] one error found +[warn] there was one deprecation warning (since 3.2.2) +[warn] there was one deprecation warning (since 3.2.4) +[warn] there were two deprecation warnings in total; re-run with -deprecation for details +[warn] there were 72 feature warnings; re-run with -feature for details +[warn] four warnings found diff --git a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip index 516ae9f6..39de65e9 100644 Binary files a/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip and b/target/streams/compile/compileIncSetup/_global/streams/inc_compile_2.12.zip differ diff --git a/target/streams/compile/compileIncremental/_global/streams/export b/target/streams/compile/compileIncremental/_global/streams/export index d28b6970..994c5191 100644 --- a/target/streams/compile/compileIncremental/_global/streams/export +++ b/target/streams/compile/compileIncremental/_global/streams/export @@ -1 +1 @@ -scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala +scalac -bootclasspath /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar -classpath /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar -Xsource:2.11.0 /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala diff --git a/target/streams/compile/compileIncremental/_global/streams/out b/target/streams/compile/compileIncremental/_global/streams/out index 5ba02d9c..ba75e332 100644 --- a/target/streams/compile/compileIncremental/_global/streams/out +++ b/target/streams/compile/compileIncremental/_global/streams/out @@ -3,22 +3,22 @@ [debug]  removed:Set() [debug]  added: Set() [debug]  modified: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala) -[debug] Invalidated products: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller$$anon$2.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp$$anon$9.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCExpander.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1$$anon$3.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy$$anon$8.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_pkt_t.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top$$anon$4.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/caller.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$$anon$7.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/top.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/dec$delayedInit$body.class, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec/el2_dec_dec_ctl$$anon$1.class) +[debug] Invalidated products: Set() [debug] External API changes: API Changes: Set() [debug] Modified binary dependencies: Set() [debug] Initial directly invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t) [debug]  [debug] Sources indirectly invalidated by: -[debug]  product: Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/RVC.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala, /home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/lib/GCD.scala) +[debug]  product: Set() [debug]  binary dep: Set() [debug]  external source: Set() -[debug] All sources are invalidated. +[debug] All initially invalidated classes: Set(dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t) +[debug] All initially invalidated sources:Set(/home/waleedbinehsan/Desktop/SweRV-Chislified-master/src/main/scala/dec/el2_dec_dec_ctl.scala) [debug] Initial set of included nodes: dec.dec, dec.el2_dec_dec_ctl, dec.el2_dec_pkt_t -[debug] Recompiling all sources: number of invalidated sources > 50.0% of all sources -[info] Compiling 3 Scala sources to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ... +[info] Compiling 1 Scala source to /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes ... [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 [debug] Getting org.scala-sbt:compiler-bridge_2.12:1.3.5:compile for Scala 2.12.10 -[debug] [zinc] Running cached compiler 3e6bed8c for Scala compiler version 2.12.10 +[debug] [zinc] Running cached compiler 3bb278c6 for Scala compiler version 2.12.10 [debug] [zinc] The Scala compiler is invoked with: [debug]  -Xsource:2.11 [debug]  -Xplugin:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalamacros/paradise_2.12.10/2.1.0/paradise_2.12.10-2.1.0.jar @@ -26,5 +26,11 @@ [debug]  /home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-library.jar [debug]  -classpath [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel-iotesters_2.12/1.4.1/chisel-iotesters_2.12-1.4.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chiseltest_2.12/0.2.1/chiseltest_2.12-0.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3_2.12/3.3.1/chisel3_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl_2.12/1.3.1/firrtl_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/firrtl-interpreter_2.12/1.3.1/firrtl-interpreter_2.12-1.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/treadle_2.12/1.2.1/treadle_2.12-1.2.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/junit/junit/4.13/junit-4.13.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalatest/scalatest_2.12/3.0.8/scalatest_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalacheck/scalacheck_2.12/1.14.3/scalacheck_2.12-1.14.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/scopt/scopt_2.12/3.7.1/scopt_2.12-3.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/lihaoyi/utest_2.12/0.6.6/utest_2.12-0.6.6.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-macros_2.12/3.3.1/chisel3-macros_2.12-3.3.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/edu/berkeley/cs/chisel3-core_2.12/3.3.1/chisel3-core_2.12-3.3.1.jar:/home/waleedbinehsan/.sbt/boot/scala-2.12.10/lib/scala-reflect.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/antlr/antlr4-runtime/4.7.1/antlr4-runtime-4.7.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/google/protobuf/protobuf-java/3.9.0/protobuf-java-3.9.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/net/jcazevedo/moultingyaml_2.12/0.4.2/moultingyaml_2.12-0.4.2.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-native_2.12/3.6.8/json4s-native_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-text/1.8/commons-text-1.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-jline/2.12.1/scala-jline-2.12.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/hamcrest/hamcrest-core/1.3/hamcrest-core-1.3.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scalactic/scalactic_2.12/3.0.8/scalactic_2.12-3.0.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-lang/modules/scala-xml_2.12/1.2.0/scala-xml_2.12-1.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/scala-sbt/test-interface/1.0/test-interface-1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/portable-scala/portable-scala-reflect_2.12/0.1.0/portable-scala-reflect_2.12-0.1.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/github/nscala-time/nscala-time_2.12/2.22.0/nscala-time_2.12-2.22.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/yaml/snakeyaml/1.26/snakeyaml-1.26.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-core_2.12/3.6.8/json4s-core_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/apache/commons/commons-lang3/3.9/commons-lang3-3.9.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/fusesource/jansi/jansi/1.11/jansi-1.11.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/joda-time/joda-time/2.10.1/joda-time-2.10.1.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/joda/joda-convert/2.2.0/joda-convert-2.2.0.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-ast_2.12/3.6.8/json4s-ast_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/org/json4s/json4s-scalap_2.12/3.6.8/json4s-scalap_2.12-3.6.8.jar:/home/waleedbinehsan/.cache/coursier/v1/https/repo1.maven.org/maven2/com/thoughtworks/paranamer/paranamer/2.8/paranamer-2.8.jar -[debug] Compilation failed (CompilerInterface) -[error] (Compile / compileIncremental) Compilation failed +[debug] Scala compilation took 9.899922123 s +[debug] Done compiling. +[debug] New invalidations: +[debug]  Set() +[debug] Initial set of included nodes:  +[debug] Previously invalidated, but (transitively) depend on new invalidations: +[debug]  Set() +[debug] No classes were invalidated. diff --git a/target/streams/compile/packageBin/_global/streams/inputs b/target/streams/compile/packageBin/_global/streams/inputs index 89751ac1..70dfd041 100644 --- a/target/streams/compile/packageBin/_global/streams/inputs +++ b/target/streams/compile/packageBin/_global/streams/inputs @@ -1 +1 @@ -1741114334 \ No newline at end of file +1668409227 \ No newline at end of file diff --git a/target/streams/compile/packageBin/_global/streams/out b/target/streams/compile/packageBin/_global/streams/out index 32b1c817..7f4f13e1 100644 --- a/target/streams/compile/packageBin/_global/streams/out +++ b/target/streams/compile/packageBin/_global/streams/out @@ -1,19 +1,39 @@ [debug] Packaging /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/chisel-module-template_2.12-3.3.0.jar ... [debug] Input file mappings: +[debug]  ifu +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu +[debug]  ifu/el2_ifu.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/ifu/el2_ifu.class +[debug]  snapshot +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot +[debug]  snapshot/pt$.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt$.class +[debug]  snapshot/pt.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/snapshot/pt.class +[debug]  lsu +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lsu +[debug]  lsu/el2_lsu.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lsu/el2_lsu.class +[debug]  exu +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/exu +[debug]  exu/el2_exu.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/exu/el2_exu.class +[debug]  dbg +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dbg +[debug]  dbg/el2_dbg.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dbg/el2_dbg.class [debug]  lib [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib [debug]  lib/encoder_generator$$anon$6.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$$anon$6.class -[debug]  lib/ifu_compress$$anon$1.class -[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress$$anon$1.class [debug]  lib/rvrangecheck.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck.class [debug]  lib/reg1.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/reg1.class -[debug]  lib/RVCDriver$.class -[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$.class [debug]  lib/rvrangecheck$.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvrangecheck$.class +[debug]  lib/exp.sc +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.sc [debug]  lib/exp.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/exp.class [debug]  lib/top.class @@ -40,10 +60,6 @@ [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvbradder$$anon$5.class [debug]  lib/rvdff$$anon$1.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff$$anon$1.class -[debug]  lib/RVCDriver.class -[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver.class -[debug]  lib/RVCDriver$delayedInit$body.class -[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDriver$delayedInit$body.class [debug]  lib/RVCDecoder.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/RVCDecoder.class [debug]  lib/rvdff$.class @@ -52,8 +68,6 @@ [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/tocopy.class [debug]  lib/encoder_generator.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator.class -[debug]  lib/ifu_compress.class -[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ifu_compress.class [debug]  lib/encoder_generator$.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/encoder_generator$.class [debug]  lib/caller.class @@ -62,6 +76,18 @@ [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/rvdff.class [debug]  lib/ExpandedInstruction.class [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/lib/ExpandedInstruction.class +[debug]  dmi +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi +[debug]  dmi/rvjtag_tap.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/rvjtag_tap.class +[debug]  dmi/dmi_wrapper.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_wrapper.class +[debug]  dmi/dmi_jtag_to_core_sync.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dmi/dmi_jtag_to_core_sync.class +[debug]  include +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/include +[debug]  include/el2_bundle.class +[debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/include/el2_bundle.class [debug]  dec [debug]  /home/waleedbinehsan/Desktop/SweRV-Chislified-master/target/scala-2.12/classes/dec [debug]  dec/el2_dec_dec_ctl$$anon$1.class