From 39f6a6ee8819c532755aac9248c2b7ead758dfe3 Mon Sep 17 00:00:00 2001 From: waleed-lm Date: Thu, 8 Oct 2020 18:57:43 +0500 Subject: [PATCH] RegEnable added --- el2_ifu_iccm_mem.fir | 2 +- el2_ifu_iccm_mem.v | 2 +- src/main/scala/ifu/el2_ifu_iccm_mem.scala | 2 +- .../classes/ifu/el2_ifu_iccm_mem.class | Bin 92974 -> 92976 bytes 4 files changed, 3 insertions(+), 3 deletions(-) diff --git a/el2_ifu_iccm_mem.fir b/el2_ifu_iccm_mem.fir index 677a07ae..1768a319 100644 --- a/el2_ifu_iccm_mem.fir +++ b/el2_ifu_iccm_mem.fir @@ -501,7 +501,7 @@ circuit el2_ifu_iccm_mem : _T_371 <= redundant_data1_in @[Reg.scala 28:23] skip @[Reg.scala 28:19] redundant_data[1] <= _T_371 @[el2_ifu_iccm_mem.scala 100:21] - node _T_372 = bits(io.iccm_rw_addr, 3, 1) @[el2_ifu_iccm_mem.scala 102:50] + node _T_372 = bits(io.iccm_rw_addr, 2, 0) @[el2_ifu_iccm_mem.scala 102:50] reg iccm_rd_addr_lo_q : UInt, clock with : (reset => (reset, UInt<1>("h00"))) @[el2_ifu_iccm_mem.scala 102:34] iccm_rd_addr_lo_q <= _T_372 @[el2_ifu_iccm_mem.scala 102:34] node _T_373 = bits(addr_bank_inc, 2, 1) @[el2_ifu_iccm_mem.scala 103:48] diff --git a/el2_ifu_iccm_mem.v b/el2_ifu_iccm_mem.v index f8b91748..ec8556c3 100644 --- a/el2_ifu_iccm_mem.v +++ b/el2_ifu_iccm_mem.v @@ -516,7 +516,7 @@ end // initial if (reset) begin iccm_rd_addr_lo_q <= 3'h0; end else begin - iccm_rd_addr_lo_q <= io_iccm_rw_addr[3:1]; + iccm_rd_addr_lo_q <= io_iccm_rw_addr[2:0]; end if (reset) begin iccm_rd_addr_hi_q <= 2'h0; diff --git a/src/main/scala/ifu/el2_ifu_iccm_mem.scala b/src/main/scala/ifu/el2_ifu_iccm_mem.scala index ef709595..24199a5a 100644 --- a/src/main/scala/ifu/el2_ifu_iccm_mem.scala +++ b/src/main/scala/ifu/el2_ifu_iccm_mem.scala @@ -99,7 +99,7 @@ class el2_ifu_iccm_mem extends Module with el2_lib { io.iccm_wr_data(77,39), io.iccm_wr_data(38,0)) redundant_data(1) := RegEnable(redundant_data1_in, 0.U, redundant_data1_en.asBool) - val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI,1), 0.U) + val iccm_rd_addr_lo_q = RegNext(io.iccm_rw_addr(ICCM_BANK_HI-1,0), 0.U) val iccm_rd_addr_hi_q = RegNext(addr_bank_inc(ICCM_BANK_HI-1,1), 0.U) val iccm_rd_data_pre = Cat(Mux1H((0 until ICCM_NUM_BANKS).map(i=>(iccm_rd_addr_hi_q===i.U)->iccm_bank_dout_fn(i)(31,0))), diff --git a/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class b/target/scala-2.12/classes/ifu/el2_ifu_iccm_mem.class index 4db49e3e8112e874e705dd7c45f902e63ed99139..f10d07d73ec53ab293ec604e38597238adcc0cf3 100644 GIT binary patch delta 190 zcmZ2?jdjB{)`l&N`YN1-3_=Xf3=Fcm+bvWWt)v7}m^ZP^+|4pOQkZ3qK$?KjbVG4Q z+3j=f7!NY@CQFw{m$Q`1w8~7AnYlgNiBU(G*`2{*x}qOr^7H_AMuq7H&WtSE6~h>} zGAi~kq)WYK$dp!L$dZl%(y*fG9g=1r6?k}hQ_muZ%nA~St^ zt`nnX=B}1mP5<`}B1dxtq$dRdK z$d$RvkS8n5kSnXT{bx91Ig@rN0|)yQmVFEk((w$6>{A&`80=-H1I4BR#hhdsfnw8v OVvb