LSU with Bundling
This commit is contained in:
Laraib Khan
parent
fd0b01190e
commit
3a1fa4fbd7
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[
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_valid",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_lo",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_fwddata_buf_hi",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_hi",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_end_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_busy",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_tag_m",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_ld_byte_hit_buf_lo",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_byteen_ext_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_addr_m"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_buffer_full_any",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_d",
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"~lsu_bus_buffer|lsu_bus_buffer>io_dec_lsu_valid_raw_d",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_valid_m",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_ld_full_hit_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_bits_load",
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"~lsu_bus_buffer|lsu_bus_buffer>io_flush_m_up",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_m",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_pkt_m_valid"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
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"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_misaligned",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_busreq_r",
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"~lsu_bus_buffer|lsu_bus_buffer>io_ldst_dual_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_trxn",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_ar_ready",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_aw_ready",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_valid",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_axi_w_ready"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_addr_any",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_inv_r",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_commit_r"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_pmu_bus_error",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_load_any",
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"~lsu_bus_buffer|lsu_bus_buffer>io_tlu_busbuff_lsu_imprecise_error_store_any",
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_error",
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"~lsu_bus_buffer|lsu_bus_buffer>io_lsu_bus_clk_en_q"
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]
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},
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{
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"class":"firrtl.transforms.CombinationalPath",
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"sink":"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data",
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"sources":[
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"~lsu_bus_buffer|lsu_bus_buffer>io_dctl_busbuff_lsu_nonblock_load_data_tag"
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]
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},
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{
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"class":"firrtl.EmitCircuitAnnotation",
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"emitter":"firrtl.VerilogEmitter"
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},
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{
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"class":"firrtl.transforms.BlackBoxResourceAnno",
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"target":"lsu_bus_buffer.gated_latch",
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"resourceId":"/vsrc/gated_latch.v"
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},
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{
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"class":"firrtl.options.TargetDirAnnotation",
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"directory":"."
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},
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{
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"class":"firrtl.options.OutputAnnotationFileAnnotation",
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"file":"lsu_bus_buffer"
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},
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{
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"class":"firrtl.transforms.BlackBoxTargetDirAnno",
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"targetDir":"."
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}
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]
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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@ -617,4 +617,6 @@ class lsu_bus_buffer extends Module with RequireAsyncReset with lib {
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io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
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io.lsu_busreq_r := withClock(io.lsu_c2_r_clk){RegNext(io.lsu_busreq_m & !io.flush_r & !io.ld_full_hit_m, false.B)}
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lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
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lsu_nonblock_load_valid_r := withClock(io.lsu_c2_r_clk){RegNext(io.dctl_busbuff.lsu_nonblock_load_valid_m, false.B)}
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}
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}
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object busbuff extends App {
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println((new chisel3.stage.ChiselStage).emitVerilog(new lsu_bus_buffer()))
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}
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